Silicon Devices: Structures and Processing

Silicon Devices Structures and Processing Edited by Kenneth A. Jackson

@ WILEY-VCH

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Compound Semiconductor Devices Structures and Processing ISBN 3-527-29596-8

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Processing of Semiconductors Volume 16 of Materials Science and Technology ISBN 3-527-26829-4

W Schroter (Ed.)

Electronic Structure and Properties of Semiconductors Volume 4 of Materials Science and Technology ISBN 3-527-26817-0

Silicon Devices Structures and Processing Edited by Kenneth A. Jackson

@ WILEY-VCH Weinheim . New York * Chichester . Brisbane . Singapore . Toronto

Editor: Prof. K. A . Jackson The University of Arizona Arizona Materials Laboratory 4715 E. Fort Lowell Road Tucson, A 2 85712, USA

This book was carefully produced. Nevertheless, authors, editor and publisher do not warrant the information contained therein to be free of errors. Readers are advised to keep in mind that statements, data, illustrations, procedural details or other items may inadvertently be inaccurate.

Library of Congress Card No.: applied for British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library Die Deutsche Bibliothek - CIP-Einheitsaufnahme Silicon devices : structures and processing / ed. by Kenneth A. Jackson. - Weinheim ; New York ; Chichester ; Brisbane ; Singapore ; Toronto : Wiley-VCH, 1998 ISBN 3-527-29595-X 0 WILEY-VCH Verlag GmbH, D-69469 Weinheim (Federal Republic of Germany), 1998

Printed on acid-free and chlorine-free (TCF) paper All rights reserved (including those of translation into other languages). No part of this book may be reproduced in any form - by photoprinting, microfilm, or any other means - nor transmitted or translated into a machine language without written permission from the publishers. Registered names, trademarks, etc. used in this book, even when not specifically marked as such, are not to be considered unprotected by law. Composition, Printing and Bookbinding: Konrad Triltsch. Druck- und Verlagsanstalt GmbH, D-97016 Wurzburg Indexing: Borkowski & Borkowski, Schauernheim Printed in the Federal Republic of Germany

Preface

This volume covers the basic processes involved in the manufacture of silicon devices, starting with purification and crystal growth, includes a description of various device structures, and concludes with a description of the processes involved in device fabrication. The chapters are drawn from the book “Semiconductor Processing” which is Volume 16 of the VCH series on Materials Science and Technology. It may be surprising to some how little the descriptions of the processing depends on the fundamental physics of semiconductors. The properties of the silicon determine what is to be done in the manufacturing process, but not how it is to be done. The processing depends critically on the properties of the wide variety of materials which are used, and the processing in a semiconductor fabrication facility, a “fab”, is a complex multi-stage sequence. The cost of a new fab, which is now at the incredible level of about one billion US dollars, is a measure complexity of the processing and of the sophistication of the equipment used. Semiconductor processing often makes use of materials at a limit of their capability. The silicon crystals used as starting material are as pure and as perfect as single crystals can be made, deposited layers are uniform and defect free, conductor cross-sections are limited by current densities, insulating layers must be uniform in thickness and free of pinholes. Ultra-purity is required not only of the silicon, but also of all the processing chemicals such as dopants, etchants, and cleaning materials, including the water. Even the air in a semiconductor fab is special: a whole technology exists to build clean rooms which are designed to limit the number and size of airborne particulates. All of the processing materials and processes have been and are continually scrutinized in minute detail to improve their efficiency and performance, and to reduce costs. This volume does not deal with the semiconductor design process, although design is clearly the essential first step in the production of a device. The design of new processors, memory chips and ASICs (Application Specific Integrated Circuits) is now implemented with extensive use of computer aided design. The electrical circuits are designed using computers and the designs are tested by computer simulation. The layout of the circuit components based on the circuit design is done by a computer which prepares the input for an electron beam writer which writes a mask set. The mask set is delivered to the fab where the masks are used successively to pattern the distribution of various dopants in the semiconductor, to pattern the dielectric layers and the conductor metallizations. Many circuit designers have never been in a fab, and the people who work in fabs need to know little about the design process. The other major aspect of semiconductor manufacture which is not dealt with in this volume is testing. Simple circuits are sample tested, but expensive chips such as microprocessors are subject to extensive electrical and performance testing. Testing all of the transistors on a chip which has ten million transistors and only a few hundred input/output pins requires a complex test procedure. The test stations are expensive and the tests are time consuming, so that testing is a major cost factor in semiconductor production.

This volume deals with the basic manufacturing processes for silicon. The fabrication process starts with the purification of the silicon followed by the growth of single crystals. The crystals are sliced into wafers which are then polished, so that silicon arrives at the fab as polished wafers. Each wafer diameter requires its own suite of processing equipment, and at the present time wafers up to twelve inches in diameter are being processed. Crystal growth and wafering processes for silicon are discussed by J. G. Wilkes in first chapter. Device structures including potential-effect devices, field-effect devices, quantum-effect devices, microwave devices and photodetectors are described in the second chapter by C.-Y Chang and S. M. Sze. In the concluding chapter, D.-L. Kwong discusses device processing, including gettering, device isolation, dielectrics, junction formation, metallization, and cluster tool technology. The processing of a wafer typically involves hundreds of separate steps, but several hundred chips can be made from a single wafer. There is a continuing trend to use larger wafers and finer features on the wafers in order to get more chips from each wafer. There are several important aspects of the fabrication of semiconductors which are beyond the scope of this volume. These include photolithography, which is used for the patterning of the dopants to make the devices, as well as the dielectrics and metallization. The feature size on wafers is now at the limit of optical resolution. The very sophisticated chemistry is needed to design the photosensitive materials which are used is beyond the scope of this volume. Similarly, the ion implantation process which is used for the selective introduction of dopants into the semiconductor is not discussed in detail, nor is the packaging technology used to protect the chips and to connect them to the outside world. Silicon processing technology is very advanced in scale of integration and so, if a semiconductor device can be made with silicon, it will be. Silicon is used almost exclusively for logic and memory devices, and although it is used for photodetectors and solar cells, it cannot be used to make devices which emit light, such as light emitting diodes (LED’S)or semiconductor lasers. Semiconductor light source devices are the domain of compound semiconductors, such as GaAs, which are discussed in a companion volume. Although there are many aspects of the processing which are common to both silicon and compound semiconductors, many of the devices are different, and the basic chemistry of the materials introduces significant differences in processing. I would like to thank the authors who have taken time from their very busy schedules to prepare their chapters. They are experts in processing technology because they are involved with it on a daily basis, and it has been difficult for many of them to find the time to write. But the result is a valuable and timely description of the state-of-the art for silicon processing. Kenneth A. Jackson Tucson, A Z August, 1998

List of Contributors

Prof. Chun-Yen Chang National Chaio Tung University National Nano Device Laboratory 1001-1Ta Hsueh Road Hsinchu, Taiwan 30050 R.O.C.

Prof. Simon M. Sze National Chiao Tung University Microelectronics and Information Systems Research Center 1001Ta Hsueh Road Hsinchu, Taiwan 30050 R.O.C.

Prof. Kenneth A. Jackson University of Arizona Arizona Materials Laboratory 4715 East Lowell Road Tucson, AZ 85712 U.S.A.

Prof. John G. Wilkes t Formerly with Mullard Ltd., Southampton U. K.

Dr. Dim-Lee Kwong The University of Texas at Austin Microelectronics Research Center Department of Electrical and Computer Engineering Austin, TX 78712 U.S.A.

Contents

1 Silicon Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J. G. Wilkes t

1

2 Silicon Device Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.-E: Chang. S . M . Sze

63

3 Silicon Device Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D..L . Kwong

113

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

195

1 Silicon Processing

.

John G Wilkes t Formerly with Philips Components Ltd., Southampton. U.K.

List of 1.1 1.2 1.3 1.3.1 1.3.2 1.3.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.6 1.6.1 1.6.2 1.7 1.7.1 1.7.2 1.7.3 1.8 1.8.1 1.8.2 1.9 1.10

Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metallurgical-Grade Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Semiconductor Grade Polycrystal Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Chlorosilane Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Silane Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Polycrystal Silicon Market ..................................... Single Crystal Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Float-Zoned Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Neutron Transmutation Doped Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Carbon and Nitrogen in Float-Zoned Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . Periodic Crystal Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Czochralski Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dislocation-Free Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Constitutional Supercooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Incorporation of Carbon and Oxygen . . . . . . . . . . . . . . . . . . . . . . . . . . . . Magnetic Czochralski Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Commercial Scaling of Czochralski Silicon . . . . . . . . . . . . . . . . . . . . . . . . Slice Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Damage in Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Polishing and Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxygen in Czochralski Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Behavior of Oxygen in Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Precipitation of Oxygen in Silicon ............................... Thermal Donors and Enhanced Diffusion ............................. Crystal Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extrinsic Gettering in Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intrinsic Gettering in Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 5 7 11 11 14 16 17 17 19 20 22 25 26 28 30 33 34 36 36 43 44 44 45 49 51 51 53 59 60

2

1 Silicon Processing

List of Symbols and Abbreviations Fourier series coefficient lattice constant (for Si, a, = 5.42 A) constant slice bow depth concentration crystal habit concentration in liquid concentration (of oxygen in oxide) in particle concentration in solid equilibrium solid solubility concentration initial concentration diameter diffusion coefficient activation energy for the formation of a particle of critical radius cut-off frequency mean value o f f , volume free energy change of a precipitate magnitudes of the forces generated at the edge during sawing fraction of melt solidified height enthalpy of reaction detector signal interstitial collector-base current Boltzmann constant effective distribution coefficient equilibrium distribution coefficient number of particles number of particles of critical radius fast neutron, thermal neutron number of oxygen atoms in axial bonds number of oxygen atoms in other bonds bound interstitial oxygen concentration Prandtl number radius radius of the total volume from which oxygen condenses into a precipitate critical radius radius of a final precipitate particle, small compared with R time absolute temperature melting point (Si: 1412 "C) half life of radioactive species thickness of a silicon slice

List of Symbols and Abbreviations

3

temperature difference velocity vacancy velocity of growth intrinsic X-ray signal half width measured X-ray signal half width rocking curve broadening

Y 6 E

0 QR

AC ACR ASTM BP CMOS CVD

cz

DC DCS DI DRAM EBE EG FZ HF HI-LO LPCVD MG-Si MOS

alpha particle absorption coefficient for polarized infrared light parallel to the stress axis absorption coefficient for polarized infrared light perpendicular to the stress axis gamma particle boundary layer thickness strain test sample angle Bragg angle, X-ray reflection Fourier coefficient (with dimensions of inverse length) constant kinematic viscosity surface free energy relaxation time relaxation time constants angular velocity alternating current advanced carbothermic reduction American Society for Testing Materials boiling point complementary, using both n- and p-type, metal-oxide-silicon device chemical vapor deposition Czochralski material direct current dichlorosilane deionized dynamic random access memory extended bulk epitaxy enhanced gettering float zoned (material) high frequency high temperature-low temperature (heat treatment) low pressure chemical vapor deposition metallurgical-grade silicon metal-oxide-silicon (device) (n-MOS, p-MOS refer to the dopant type structure employed)

4

NFZ NTD NTP PPba PPma PPt psi RF r Pm SANS SIMS SRAM TCS TD TIR UHF ULSI

uv

VLSI WCA

1 Silicon Processing

nitrogen-doped float zone (material) neutron transmutation doping normal temperature and pressure atomic parts per billion (lo9) atomic parts per million parts per trillion (10'') pounds per square inch radio frequency rotations per minute small angle neutron scattering secondary ion mass spectrometry static random access memory trichlorosilane thermal donor total integrated reading (of bow or warp) ultrahigh frequency ultra large scale integration ultraviolet very large scale integration water classified alumina

1.1 Introduction

1.1 Introduction Silicon today is a commodity, its price subject to all the forces of supply and demand in an intensely competitive market, and this has driven the development of high yield processes for the tight tolerance materials demanded. While discrete and power device manufacture calls for some float zoned, and neutron transmutation doped (NTD) silicon; the worldwide compass of integrated circuit manufacture consumes more than 75% of all the semiconductor silicon produced. The development of the product market distribution is shown in Fig. 1-1. Supply of this material is dominated by Czochralski crystal growth, the operational scale of which has increased from charges weighing a few hundred grams, around 1962, to the current units of 60 kilogram and more. The evolution of the semiconductor industry as we now know it began in the 1950s, when many of the then large electrical companies became involved in the chemistry and metallurgy of Germanium. Their starting point was GeO,, the dioxide, which had to be reduced to metal powder, melted, zone refined, and crystals grown, before the machining operations which led to discrete devices. Germanium being an expensive rare element, the ma60 New techn 0.

40n

/

Discrete anq p o r e r O

80

.

'

I

82

'

f

'

84

86

88

,

, 1990

Year

Figure 1-1. Development of the semiconductor product market.

5

chining itself generated valuable byproduct sludges which had to be recovered. The extreme purity necessary led into problems in chemical and physical analysis, materials of containment, and in general chemical engineering. In retrospect, very few of these electrical companies possessed either the resources or the experience needed for such work; so when, only shortly afterwards, silicon was introduced, almost all of them took the opportunity to withdraw from the chemical end of the business. Silicon is one of the most abundant elements, and so the sludges are of no economic importance. Henceforth their starting point became the ultrapure polycrystalline silicon from which they made their own single crystal. With time, the number of companies doing even this has steadily declined, until today few of the electronics manufacturers have any involvement in bulk material processing. Indeed most purchase polished slices, cleaned and packaged, furnace ready, for fabrication lines. A number of the device makers still carry out epitaxy and, to that extent alone, retain a residual materials activity. In modern very large scale integration (VLSI) circuits, lithographic feature sizes have been reduced to 1 pn or less, and use multilevel interconnects to enable the production of high complexity devices of steadily rising chip area. Consequently, as the number of chips per wafer decreases, so there has been an accompanying call for ever larger wafer diameter - to reduce perimeter wastage, and to improve fabrication line yield and throughput, as shown in Fig. 1-2 - hence the continuous need to scale up crystal size, this demanding extremely heavy investment. This scaling has not been at the expense of quality - in fact quite the reverse. As more has been learnt about the relation-

6

1 Silicon Processing

200 175 150

- 125 $100

E

.E 0

15

50 25

0

1960

1970

1980

1990

Year

Figure 1-2. The year of introduction of the largest silicon wafers in production. (Note: This trend continues. A very small number of companies, mainly Far East, are now looking at 250 mm diameter possibilitics.)

ship between materials properties and the device parameters, so the demand for better performance from the silicon has grown. If one compares a typical purchasing specification of even the mid 1970s, with that in force today for a similar application endproduct, the increase in the number of parameters specified, and the narrowing of virtually all tolerances, is marked. Contributory factors leading to this position include: Fine geometry lithography, needing slices of a flatness not even contemplated ten years ago; cassette, and now robotic, handling techniques, which call for close machining tolerances, and edge rounded slices, to prevent chipping and particles accumulating in ultraclean fabrication equipment. Research into the behavior of oxygen and carbon precipitation in bulk silicon under device furnacing conditions has led to the introduction of new specification parameters, new crystal processing methods, and to the concept of “crystal engineering”. Controlled oxide precipitation in slices is carried out, prior

to their use in fabrication lines, to provide sites for the intrinsic gettering of unwanted fast diffusing electrically deleterious impurities, away from the surface layer where the MOS devices are made. Residual mechanical damage sites after the crystal machining provide similar extrinsic gettering sites. For many applications in “crystal engineering” today, combinations of controlled mechanical and oxide precipitate gettering are used together to achieve optimum performance from the silicon, to match the particular device requirements in MOS, CMOS, and bipolar configurations. To achieve this matching it is necessary to examine the total thermal inventory of the multistage fabrication process, in order to select the most appropriate structure. While the early 1990s have seen a general slowdown in world economies, the surge in the personal computer market, linked to the major developments in microprocessor chips, has meant that device production revenues have continued to grow, by 1993, to $60-70 billion (lo9),and are projected to be in the range $150-200 billion by the year 2000. These microprocessor chips are of ever increasing size and complexity; for example the Intel Pentium with around 3 million transistors, running at a speed of 100 million instructions per second, is about 0.5 sq. in. (-3 cm’) in area. In memory chips the 16 Mbit DRAM is being followed by the 256 Mbit version, and since each DRAM cell needs one transistor, even with shrinking all dimensions the chip size is increasing. Charge coupled devices for displays also require large-area chips. Such ultra large scale integration (ULSI) applications today are leading the demand for Czochralski silicon wafers with diameters of 200 mm (S”), and inevitably still bigger will follow. For these diameters, the current pullers have to be scaled up

1.2 Metallurgical-Grade Silicon

further towards 100- 150 kg machines. The larger thermal masses will impose difficulties in the control and uniformity of the dopant, oxygen, and crystal defect concentrations. Finer dimension lithography needs ultra flat wafers, and particulate contamination levels of less than 10 particles greater than 0.1 pm per wafer are expected. Leakage control in large DRAMS requires metallic surface contamination to below lo9 atoms/cm. These are severe challenges at the final wafer cleaning and packaging stages. Overall, larger slices, made to extremely close tolerances by rigidly defined processing, from silicon that conforms to tightly specified criteria with respect to uniformity, dopants, impurities, point defect precipitates, clean surface characteristics, and metrology, are required of the materials vendors. Yet as the market competition is fierce, all of this is wanted at the minimum possible price - a constraint that reflects back through every step in silicon material manufacture. Thus right back in the raw material sector, over the past twenty years the supply of silicon has steadily become concentrated into fewer large specialist merchant vendors, and usually these operate as a division within some much bigger general chemical corporation. Many of the same companies are now involved in the present ruthless shakeout of the parallel gallium arsenide material market, as this sector, in the 1990s, is becoming commercially more significant. Thus the highly competitive commodity environment, which can never be ignored, is the constant background influence against which this chapter is set.

1.2 Metallurgical-Grade Silicon The source of the raw silicon used for semiconductor purposes is metallurgical-

7

grade silicon, manufactured by the carbothermic reduction of silica in an electric arc furnace. Silica, occurring naturally as quartzite, in vein quartz, and in sandstone, and as unconsolidated sands and gravels, is a common mineral with worldwide distribution. Silicon, after oxygen, is the second most abundant element, but does not occur naturally in its elemental form. Silica, either free as in quartz or in the many forms of silicate igneous rocks, constitutes about a quarter of the earth’s crust. However, the silicon metal producers demand an ore purity of better than 99% SiO,, and also place tight restrictions on the allowable concentrations of various impurities present - in particular arsenic, phosphorus, and sulfur - so that often only a small fraction of an ore deposit meets their purity specification. Geologically washed out gravel from river bed deposits, and similarly leached out quartz sands, are a source of very high purity silica. Vast new deposits, yielding quartzite ore of the highest purity available today, have been discovered in Arkansas, U.S.A., from which monocrystals weighing several tons apiece have been displayed in exhibitions worldwide. In the traditional electric arc furnace process, which has been used for most of this century, chunky quartzite is reacted with carbon, as the reductant, in the forms of coal, coke, or charcoal, which can be a source of at least an order of magnitude greater impurity levels than present in the silica. The overall reaction appears simple:

SiO,

+ 2C

+

Si + 2CO

(11

However, as discussed by Healy (1970),the actual reaction sequence in the different temperature zones of the furnace is far more complex than this, as set out in the schematic diagram of Fig. 1-3.

8

1 Silicon Processing

Figure 1-3. Schematic diagram of the submerged-electrode electric arc furnace for the production of metallurgical grade silicon.

Towards the bottom of the furnace, in the region of the arc between the electrodes where the temperature can exceed 2000 "C, silicon is produced by the reaction S i c + SiO,

+

Si + SiO + CO

(2)

Above this, at a somewhat lower temperature, around 1700- 1500 "C, the rising byproduct gases react to form the intermediate product silicon carbide by SiO + 2 C

--f

S i c + CO

(3)

Nearer to the top, where the temperature falls below 1500"C, as is expected thermodynamically, the reverse reaction predominates: SiO

+ CO

--f

SiO,

+C

(4)

The input materials are fed into the top of the furnace, while liquid silicon is periodically tapped from the bottom and cast into ingots. If this casting is carried out directionally, under the conditions referred to

as normal freezing, impurity redistribution can be used to effect some purification, following the well equation by Pfann (1952, 1958):

c, = kerf C,(1 - g p f f - 1 ) For the arc process to run properly, it is essential to maintain porosity throughout the charge to allow uniform SiO and C O gas flow, and to permit the escape of CO, some SiO, and H,O from the top. To assist this wood chips may be included in the feedstock, and the silica must be of a form which does not readily crumble during initial heating in the upper part of the furnace, which could lead to premature fusion and crusting over, with the risk of a dangerous pressure buildup within the charge. Clearly the carbothermic reduction of silica is not a trivial process. Crossman and Baker (1977) have given a very interesting comparison of the impurities present in typical quartzite and the carbon used, related to the spectrographic analysis of more than 2000 tons of the met-

1.2 Metallurgical-Grade Silicon

allurgical-grade silicon produced. Their data, collected into Table 1-1, indicated total impurity levels in the quartzite of around 750ppma; in the carbon 8000ppma, and in the resulting metallurgical-grade silicon (MG-Si) 4000-4500 ppma. Within this analysis the two predominant impurities are seen to be aluminum and iron, largely originating from the carbon, and taken together accounting for over 80% of that in the silicon product. Since these results referred to MG-Si to be used for the production of semiconductor grade polycrystal silicon, the importance of the purity of the carbon source is underlined. Recent developments have focused on improved and cleaner processes, better quality carbon, and efforts to develop quartz sands as an alternative low cost and high purity source. Maintaining charge porosity constitutes the most serious restriction in the operation of the submerged arc furnace, and much attention has been focused on how to meet, or circumvent this problem. In work aimed to reduce drastically the impurities in arc furnace silicon, Dosaj et al. (1978) working at Hemlock

Table 1-1. Impurities in silica, carbon, and metallurgical-grade silicon. Impurity

A1 B Cr Fe P Others Mn Ni Ti V

‘ Weighted;

Quartzite (PPW

Carbon” (PPma)

MG-silicon (PPma)

620

5500

14 5 15 10 10

40 14 1700 140 600

1570f580 44f 13 137f 75 2070 510 28+ 6 -

70+ 47f 163f loo*

20 28 34 47

avcrage value f standard deviation.

9

Semiconductor Corp. U.S.A. reported using a high purity silica source together with carbon black powder, pelletized with pure sucrose binder, to obtain MG-Si at 99.99% purity. Although the boron content of the material was relatively low, this particular element tends to be more persistent through the later stages of semiconductor silicon manufacture, and therefore recently there has been interest in exploiting the lower boron content of carbon obtained from petrocoke. The pelletization of upgraded quartz sands can provide very pure silica in a suitable form. This material then has to be agglomerated to lumps, either separately or mixed with carbon powder. This approach has been studied by several groups, including Elkem A/S, Norway, the largest European silicon metal producer, but until now it has only been taken to a development stage. The Siemens advanced carbothermic reduction (ACR) process has recently been described by Aulich et al. (1985), in which high purity pelletized quartz sand is reduced by carbon granules, prepared from carbon black briquettes, which had been leached with hot HC1 to a purity comparable to that of the silica. Since in an arc furnace about 10% of the carbon comes from the electrode, the effective carbon impurity level was somewhat higher. Nevertheless a substantial overall impurity reduction was achieved. A more radical approach to overcoming the porosity problem has been the application of DC plasma-arc techniques to the production of ferrosilicon alloys and silicon metal. The most important feature of the plasma-arc furnace here is that it can process ore fines directly, without prior briquetting or pelletization. The potential of this route is supported by the extremely efficient plasma purification of normal MG-Si, by factors of up to 100000, re-

10

1 Silicon Processing

ported by Armouroux et al. (1986). Developed up to the stage of full scale production of ferrochromium ore, in South Africa, the plasma-arc technology is now being assessed in other countries. The great evolution of heat from the oxidation of aluminum forms the basis of the Thermit process for the reduction of refractory oxides, such as Cr,O,, and MnO,. By the application of this technique to silicon, an entirely new manufacturing route has resulted from the extensive work by Dietl and Holm [see, e.g., Dietl et al. (1981) and Dietl and Holm (1986)l at Wacker Heliotronic, Germany, on the aluminothermic reduction of quartz sand in a liquid flux system (CaO-SiO,) at a temperature of 1600- 1700"C: 3Si0,

+ 4A1 + 3Si + 2A1,0,

(5)

The flux serves simultaneously as a solvent for the byproduct aluminum oxide, and as a liquid-liquid extraction medium. As the silicon is released it is immiscible in the flux and so separates. Since the silicon is of lower density, if floats as the upper layer and at intervals can be poured off into a mold, where controlled normal freezing further separates low segregation coefficient impurities. The silicon made by this novel semicontinuous process is of relatively high purity compared with normal MG-Si. It is characterized by low boron and carbon levels, and after subsequent grinding, acid leaching, and liquid-gas extraction, provides a material that is suitable for solar-cell applications. During the past decade, the most important economic trend in silicon metal production has been abandonment of the earlier small scale multi-unit plants, having limited productivity, for the use of very much larger electric arc furnaces, commonly dedicated to a particular product, which operate with lower unit costs. A

modern commercial submerged-electrode arc furnace built in a three phase, three electrode configuration, each of these t .25 m in diameter, and driven from a 24 M W power source, can produce 8000-10000 t/a metallurgical-grade Si at an energy consumption of 12-14 kWh/kg. The demand for metallurgical-grade silicon is dominated by the iron-steel and aluminum alloy industries, which require 98% purity metal. A somewhat higher quality, of 99% + purity, is required for conversion into chlorosilanes, the key intermediates in the synthesis of organo-silicon compounds for the silicone industry, leading to products such as oils, resins, lubricants, and water repellants. Although the semiconductor industry wants the highest purity it can obtain, the amount needed still represents only a very small fraction of the world's output. For example the global production of MG-Si in 1986 was just under 600000 t, from which the organo-silicones consumed about 20%. By contrast, in that same year the production of semiconductor-grade, ultrahigh purity, polysilicon reached about 6000 t - representing a consumption of less than 2% of total MG-Si output, and, significantly, only a fraction of the capability of a single-arc furnace. Western Europe accounts for over half the world capacity, led by Elkem, Norway, and Pechiney, France at 100000, and 75000 tons per annum, respectively. Thus, in summary, while the manufacturers of semiconductor silicon can have only limited influence over the quality of metallurgical silicon, there have been improvements in this product. While these have probably been driven more by the much larger organo-silicon purity needs, some of the companies in the MG-Si industry have established strong links in the semiconductor market, and their contributions are of greater significance when set

11

1.3 Semiconductor Grade Polycrystal Silicon

1.3.1 The Chlorosilane Route

against the global background of silicon metal production.

This process, developed at Siemens (Bischoff, 1954), rapidly superceded the earlier SiCl,/Zn method, which had been the principal silicon source until that time. There are three basic key steps in the process:

1.3 Semiconductor Grade Polycrystal Silicon As shown in Table 1-1, metallurgicalgrade silicon of 99%+ purity contains, in addition to carbon, the major impurities iron and aluminum at more than 1000 ppma, various transition and other metals - titanium, chromium, etc. - at around 100 ppma, and lesser impurities, including boron and phosphorus, at lower levels of lo’s ppma. Semiconductor polysilicon specifications require that all of these be reduced to parts per billion (ppba: 1 in lo9) levels. For the producers this extremely demanding task has to be achieved economically, to meet the very competitive market pricing pressures which dominate the industry. Early polysilicon plants were built with a capacity of around 100 t/a, but today, to meet price targets, the latest plants are built with capacities around 1000 tons, or more. Two main routes are available for the production of semiconductor-grade silicon from MG-Si; either via chlorosilanes (principally trichlorosilane, SiHCl,), or via silane (SiH,). The former has been predominant since the late 1950s, but is now being challenged.

MG-Si

grit

1 Pure anhydrous HCl

The fundamental, reversible, reaction is Si,,, + 3

w,,-.

fluidircd bed

C”D

SiHCl,,,,

+ H2fg)

(6)

The layout of a fluidized bed unit is shown in Fig. 1-4. However, again the actual reactions are more complex, and between this and the later stages of the process there is considerable recycling. The overall flow design of the plant, the efficient use of heat exchangers, and precise control of the recycling of intermediates are crucial factors in the operating costs.

H,,

T Vaporizer Heater

(a) Reaction between powdered MG-Si and hydrogen chloride gas in a fluidized bed reactor to form trichlorosilane (TCS). (b) Fractional distillation of the TCS to provide it in an ultrapure, ppba, form. (c) Reduction of the ultrapure TCS by hydrogen in a chemical vapor deposition (CVD) reaction to yield the desired product - semiconductor-grade polycrystalline silicon.

HCI

-!ICondenser

300-400°C

I

I

Heating

Cooling

Figure 1-4. Layout of a fluidized bcd rcactor. The high degree of recycling in a chlorosilane plant is similar to that in a silane plant see also Fig. 1-5. ~

Si H CI,,

Si Cl,

12

1 Silicon Processing

The reaction between powdered silicon and anhydrous hydrogen chloride gas in the fluidized bed, held at 300 to 400°C is highly exothermic, producing a mixed output which contains about 90% of the wanted SiHCI, [Boiling point (BP): 31.8"C], about 10% SiCl, (BP: 57.6"C), and also a little dichlorosilane, SiH,Cl, (BP: 8.5 "C); together with hydrogen, unreacted HCl, and some volatile impurity metal chlorides. For this conversion high purity anhydrous HC1 gas is essential, and a complex purification plant is needed to guarantee the < 1 ppma level specified for this stage. Phosphorus trichloride (BP: 76 "C), and boron trichloride, which is a gas at room temperature, are the two principal electrically active impurities carried over from the MG-Si; arsenic, as AsCl, (BP: 130°C) is also present to a lesser degree, together with small amounts other volatile metal chlorides, such as AlCl,; but the fluidized bed stage does reduce the incoming impurity levels quite substantially. At the next stage conventional high performance multiplate fractional distillation is employed to refine the TCS, separating it from other chlorosilanes and Si-H-C-C1 species present, and reducing the undesirable metals to ppba levels. The fractional distillation is backed up by the use of selective adsorption techniques to reach the very highest purity possible. This stage is pure chemical engineering, akin to that to be seen at any petrochemical refinery. Provided that they are kept completely dry, chlorosilanes, and also anhydrous hydrogen chloride, are chemically inactive in both liquid and gaseous form, and therefore can be moved and transported in conventional carbon-steel pipelines and tanks, but special valves and pumps are needed to maintain a totally leak-free environment. Thus the final ultrapure TCS is relatively easy to handle onwards to the next, silicon deposition, stage.

The quality of the semiconductor-grade TCS obtained at this stage is seen in Table 1-2, which shows the low levels of all impurities typically achieved. There has had to be much development of new analytical techniques in order to be able to quantify these impurities. Even using the highly sensitive method of ultraviolet spectroscopy, all metals are normally at a level below their respective detection limits. Special grades of even higher purity are available, for example, for epitaxial deposition. At this level often the only way to discriminate between two source materials is by their comparative performance under rigorously controlled conditions. When the data in Table 1-2 are compared with earlier published results, as for example those

Table 1-2. Impurities in semiconductor-grade trichlorosilane and polycrystalline silicon '. Impurity

SiHCI, SiH,CI, SiCI, Resistivity Carbon Oxygen Donors Acceptors Metals

Trichlorosilane

99.9% min <0.2% max 0.01% max -

< 0.5 ppma a not quoted < 0.02 ppba < 0.03 ppba

Polycrystalline silicon

~

>1000Qcm < 0.5 ppma' not quoted <0.10 ppba" <0.05 ppba

below detection by neutron activalimits for UV tion analysis: spcctroscopy, e.g.: Fe <5ppba Fe <0.4 ppba Cr <0.05 ppba Ca < I ppba Al < I ppba Zr <0.2 ppba Mg <0.02 ppba other metals individually < 0.02 ppba

'

Hydrocarbons by chemical techniques; by IR absorption; by electronic measurements on the deposited polycrystal silicon. Compiled from standard trichlorosilanc and polysilicon specifications available from major suppliers, 1989.

'

1.3 Semiconductor Grade Polycrystal Silicon

given by Crossman and Baker (1977) (their studies of MG-Si have already been mentioned), the improvements of the last decade stand out, particularly with respect to the reductions in carbon, and residual donor levels. The third stage of the process is silicon deposition, where the Siemens chemical vapor deposition technique is used worldwide by all the major producers. Again today’s reactors are much larger, but the configuration is still essentially that first proposed in the mid 1950s. Two thin rods of ultrapure silicon, about 5 mm in diameter, and, today, up to 2 3 m in length are attached to heavy electrodes at their lower ends, while at their upper ends they are joined together with a shorter bridging piece of silicon thin rod - in an inverted “U” configuration. By passing an electric current through the silicon, the rods are heated to a temperature of about 1100 “C in a trichlorosilane -hydrogen mixture, when reaction at the hot surface deposits ultrapure silicon. The process is continued for some 200-300 h until the rods reach a diameter of 150-200 mm. The preferred input material is TCS, rather than SiCl,, which was used in the 1960s by some companies trying to evade the Siemens patent, because the reaction using TCS proceeds at a lower temperature and a faster rate. Again more complex than given by Reaction (6), the intermediate high temperature compound silicon dichloride, SiCl, , plays an important role, both in the adsorptiondeposition step at the surface and in the formation of byproduct SiCl,. Since chlorosilane epitaxy uses the same process to deposit thin single crystal silicon layers, this reaction has been studied extensively, the work of Bloem, Gilling, and their coworkers over a number of years being notable (Bloem and Gilling, 1978; Bloem and Classen, 1980, 1983/1984).

13

In such a deposition process, any homogeneous nucleation, followed by particle growth in the gas phase, would lead to powder deposits downstream all over the system, which would be disastrous. The TCS process operating parameters are chosen to ensure a heterogeneous surface controlled reaction. Under these conditions the rate of deposition with time (kg/h) is directly proportional to the surface area, rising as the rod diameter increases. Clearly it is desirable to grow the rod to as large a diameter as possible, and hence the scaling up of these reactors has contributed very markedly to reducing process costs, as does recycling. Only a fraction of the TCS fed through the reactor cells is converted to silicon. The outgoing gas contains unreacted SiHCl,, SiCl,, HCl, H,, and other lesser constituents, all of which are separated, repurified as necessary, and fed back to the appropriate earlier stage, the HC1, for example, being returned right back to the first fluidized bed stage. Some of the SiC1, byproduct from the overall operation is not recycled but finds a market, having various uses, in epitaxy, for some silicon and silicone products, and more recently in the manufacture of optical fibers. In summary, while there are operating complications, the Siemens process, in the three basic steps of dissolution, highly efficient distillation, and redeposition, converts MG-Si of ppma purity to ultrapure ppba semiconductor silicon, in a very costeffective manner, and far superior to the earlier SiCl,/Zn Dupont process (Lyon et al., 1949) that it displaced completely. By 1959 the laboratory growth of undoped float zone silicon crystals was being reported which had near intrinsic resistivity values, in excess of 100000 R cm (Hoffman et al., 1959). Today’s analytical data for typical electronic grade polysilicon, col-

14

1 Silicon Processing

lated from latest vendor specifications, as shown in Table 1-2, reflect the steadily continuing quality improvements, linked to those of its precursor trichlorosilane - the material which has underpinned the advances in the device field for over two decades. 1.3.2 The Silane Route

Although research into the potential semiconductor uses of silane, SiH,, started early, silane became commercially important only in the later 1960s when its planar fabrication applications emerged, used in the chemical vapor deposition of silicon dioxide and silicon nitride dielectrics, and for polysilicon interconnect layers in devices. Much of this silane has been made using the lithium hydride, high temperature flux LiC1(45%)/KC1(55%)electrolytic cell system (Sundermeyer, 1957), in which the key reaction at 390-430°C is SiCl,

+ 4 LiH -+ SiH, + 4 LiCl

(7)

The merchant market demand for silane for these purposes reached about 110 tons in 1986 and, following the continuing rapid silicon integrated circuit device expansion, has since more than doubled. However, here we are concerned with the use of silane as a route to bulk polysilicon. For many years Komatsu Ltd., Japan, has operated a silane plant (Yusa et al., 1975; Taylor, 1987) which uses a process based on the reactions 2Mg + Si Mg,Si SiH,

+

Mg,Si

+ 4NH,ClSiH, + + 2MgC1, + 4NH3

+

Si + 2H,

(8) (9) (10)

Powdered magnesium and silicon are melted together to form the silicide, which is then reacted with ammonium chloride

in a liquid ammonia solvent at a temperature of 0°C. Since boron forms a stable BH3:NH, addition compound, it is reduced to extremely low levels, 0.01-0.02 ppba, at this stage. Phosphorus, as phosphine, PH,, is a much more difficult impurity to remove from the output silane gas. Therefore the next step is multiplate fractional distillation, under reduced pressure at very low temperature, below the boiling point of silane, - 112 "C. Since silane forms a spontaneously explosive mixture with air, the equipment is complicated and expensive, and the product could still contain too much phosphorus. Further purification by selective adsorption onto modified A-type zeolites, at a temperature of - 20 to -30°C, removes PH, to extremely low levels, well below 0.01 ppba (Yusa et al., 1975). Work on improved modified zeolite adsorbants has continued, for example, Showa Denko KK (1984). The final stage of deposition, carried out in equipment as described above for the Siemens process, but operated at a somewhat lower temperature, around 900"C, in order to avoid unwanted homogeneous reaction, is a simple thermal pyrolysis, requiring no other reactant, unused silane and hydrogen being the only byproducts for recovery. The polysilicon produced is of a very high quality, but it is more expensive than that made by the trichlorosilane route. The capacity of the Komatsu plant is quite small (150 tons in 1986), and the premium grade silicon product finds its use in the market for high-resistivity float-zoned, and neutron transmutation doped single crystals (see Sec. 1.4.2). Within the U.S. Department of Energy funded solar energy program of the mid 1970s, various potential routes to silicon were explored or re-examined. Examples include the reduction of SiCI, by Na or Zn, and routes involving SiF,. These have

15

1.3 Semiconductor Grade Polycrystal Silicon

been well reviewed by Diet1 et al. (1981). Out of this program one process has reached full maturity, in a plant that added significantly to the world's semiconductor silicon capacity. The Union Carbide, Moses Lake, Washington, plant produces silane as the precursor to deposition, but combines the merits of both TCS and silane in the intermediate stages (Taylor, 1987).Manufacture again starts from MGSi fed into a fluidized bed reactor, but operated quite differently from that described in the Siemens process, in that the silicon is mixed with large amounts of recycled SiCl,, and hydrogen in the reaction 3 SiCl,

+ Si + 2 H,

+

4 SiHCl,

(1 1)

Operated at a high pressure of 500 psi (z35 bar) and at a temperature of 500 "C, this process is nearly thermoneutral, and yields a single-pass efficiency of 30-35%. It is quite unlike the highly exothermic Reaction (6) of the Siemens system. This stage is followed immediately by distillation to separate out and recycle the excess SiCl,.

The next two stages, leading to silane, are successive catalytic disproportionation steps: 2SiHC1,

--f

+ SiH,Cl,

SiCl,

(12)

to dichlorosilane (DCS) and then 2SiH,Cl,

+

SiC1,

+ SiH,

(1 3 )

both are carried out at a pressure around 50 psi ( ~ 3 . bar) 5 and at a temperature in the range of 6O-8O0C, using a tertiary amine ion-exchange resin catalyst; and each achieves a single-pass efficiency of around 10-12%. Again, as shown, the components are separated by distillation between the stages, the silane being finally purified by cryogenic fractionation. As revealed by the stage single-pass efficiency factors, there is a high degree of recycling throughout the process. The schematic flow diagram of the Union Carbide process set out in Fig. 1-5 shows the high level of feedback between stages. The development of the purification methods required to achieve the highest purity silane has demanded improved and

H, recycle

r

I

I

SiHCI, recycle SiH,CI,

II

1'

2

Metallurgical-grade silicon

Disproportionation SiH,CI,

i

i

I1

t

--

--I

. 1

L

Fluidized bed

recycle

I

Disproportionation and cryogenic distillation

3 t

Pyrolysis deposition reactor

I1

16

1 Silicon Processing

new analytical techniques, such as deep level transient spectroscopy and photoluminescent spectroscopy, where sensitivities down to the parts per trillion (ppt) level are now routinely reported (Taylor, 1988). The final pyrolysis at 900°C is as described above, with the byproduct hydrogen, and unused SiH, (not shown) being recycled. The quality of the polycrystal silicon material available now from the latest silane technology is of somewhat higher purity than that from the established chlorosilane route, particularly with respect to ultralow levels of boron. The differences, however, are fairly marginal, and, even in the new, very large installations, present indications are that production costs are still a little higher than those associated with chlorosilane material. 1.3.3 The Polycrystal Silicon Market While this chapter is concerned with technology, this is impacted by the market, and a few comments are appropriate. In order to compete, polysilicon plants have to be large. The initial installed capacity at Moses Lake in 1984 was 1200 t/a, which could be enlarged further to 3000 t/a. Another silane technology plant built in the U S A . by the Ethyl Corp., onstream in 1986 at 1000 t/a, was planned for 2000 t/a. The older Wacker, Germany, chlorosilane plant has been steadily modernized, and expanded to over 3000, and could reach 5000 t/a, while Tokuyama, in Japan is on a similar scale with room for expansion. The present western world installed capacity is dificult to state precisely but is in the range of 12000 t/a, while the eastern bloc nations (around 2200 t/a in 1987) are now passing 3000 t/a. It is important to recognize that this is the installed capacity, which makes no

allowance for maintenance downtime, breakdowns, and yields falling below design criteria; historically actual production output has been 70-80% of capacity. The cyclic and volatile nature of the component business has added to the competitive problems, as companies strive to hold, or increase their share; also Far East penetration into the silicon materials field increased substantially during the 1980s. Therefore it is not surprising that, notwithstanding increased energy costs and inflation, the pressure has meant that prices have stayed almost constant throughout this decade. Figure 1-6 shows the price/ time changes for polysilicon, and their link to monosilicon prices, discussed later. As a result of the introduction of the new plants, the fraction of this silicon made from silane rather than chlorosilane has increased markedly. Moving on, at the end of 1990 the Union Carbide, Moses Lake, plant was sold to

3000

-

2000

-

\\

Y m

\

#

._

600 -Monocrystalline

aJ

" .L a

?*.\.

0

200 100

-

!

-

Polycrystalline

40 -

201

'

50

55

'

60

'

65

I

70 75 Year

'

80

1

85 1990

Figure 1-6. Prices of polycrystal and monocrystal silicon, 1956-1990.

1.4 Single Crystal Silicon

Komatsu, Japan, a company with long experience of silane technology, as detailed above, which had the effect of further shifting market share towards the Far East. This operation has been renamed A. Si. M.: Advanced Silicon Materials. Following from the present and forecast device market trends, analysts are once again expressing some concern that there could be a silicon shortfall by the year 2000. Whether this develops or not, what is certain is that there will have to be further major capital investment in this sector, and it takes a considerable time to build a 1000 ton polysilicon plant. It remains to be seen who will lead, and where.

1.4 Single Crystal Silicon The manufacture of monocrystalline silicon from the ultrapure polycrystal material is practiced on a much wider base than polycrystal production, where some of the metal refiners take their process no further, and do not enter the semiconductor part of the operation. It involves major vendors that only partially resource, or have no in-house polysilicon capacity, and also includes a few of the largest device companies, whose single crystal production is augmented by the purchase of either ingot, or later stage, for example, polished slice, products. Those who retain materials activities, are generally those who have been involved historically, and consume in excess of, say, 200-300 t/a; even so they always second-source from the large merchant vendors. Thus, over the years, crystal growth and slice fabrication have moved out from the device companies into the vendors with their specialized materials science and chemical engineering expertise. Two techniques are used to manufacture monocrystalline silicon - free float zoning,

17

and Czochralski crystal pulling from a silica crucible. The material produced has different properties, and very different device applications. Today float zoning addresses a much smaller part of the market, and is discussed first. 1.4.1 Float-Zoned Silicon

Floating zone refining was introduced independently by several groups of workers in the early 1950s (Keck and Golay, 1953; Theurer, 1952,1956),and very quickly became a widely used crystal growth technique. In float zoning a cylindrical rod is held vertically and heated in argon by a radio frequency induction coil, to establish a molten droplet between the lower end of the rod and a single crystal seed rod mounted coaxially beneath, the two rods being rotated in opposing directions. The molten zone, retained in place between the polycrystal and seed rods only by surface tension, is then moved gradually upwards through the length of the polycrystal, converting it to monocrystal form. The input material is a 2-3 m long cylindrical rod, obtained by limiting the final diameter at the deposition stage. The surface of an as-deposited rod has a coarse granular structure on a millimeter scale, which is removed by rotary diamond grinding to a tight diameter tolerance. The rod is then deep etched to a bright smooth finish, to ensure that all the damage and impurities introduced into the surface by the machining are removed, and also to reach the diameter required for the zoner. Finally the rod is washed in very high purity deionized water before zoning. As already stated, the silicon deposition rate in the polycrystal reactor is proportional to diameter, and so limiting the process to making smaller diameter material

18

1 Silicon Processing

increases costs and reduces the reactor plant capacity. Only true straight rod sections can be used for zoning, and so, when the additional machining and preparation are taken into account, the input material is considerably more expensive than the simple broken poly lump suitable for melting in a crucible. Float zoning is an inherently difficult technique because of the problems in controlling such a free molten zone. Compared to Czochralski pulling, where melt convection can be influenced by the heater shape and its position with respect to the melt, and by baffle design, and the crucible and crystal rotations can be chosen at will, in the zoner there are far fewer degrees of freedom to chose from to adjust its performance. A great deal of work has centered on induction coil design, and the use of auxiliary coils, to set the desired temperature gradients. Hence developments to reach larger diameters lagged years behind the availability of equivalent Czochralski material. It was found almost impossible to maintain a large diameter molten zone whose volume was such that surface tension alone could hold it in place without the liquid falling out. The problem was eventually solved by

‘t

a new approach, known as the “needleeye” technique (Keller, 1959), see Fig. 1-7. During the rod preparation machining stage, described above, a modification was introduced whereby, after the rod had been ground to a parallel cylinder, its bottom end was further ground to a tapered cone, as matching section to the seed. The R F induction coil was made at a smaller diameter than the machined rod, so that as the zone was established and passed up through the polysilicon rod, with the coil now just inside the rod diameter, the smaller molten zone volume involved could then be successfully moved through the length of the rod without prematurely falling out. Establishing this as a reliable production procedure took much effort, and the design of highly specialized zoners. By this crucible-free technique standard crystal product, zero dislocation density silicon up to 150 mm diameter, is made at a purity close to that of the input polysilicon. Resistivities are available up to 5000Qcm, and in limited amounts even higher, well beyond that attainable by Czochralski growth. The control of doping to specific resistivity bands in float zoned (FZ) silicon is approached in three ways. Firstly, by gas

+ 0

Polycrystal feed r o d

+

;I

RF h e a t e r coil

olten zone

..-

u

El

N

(a 1

Single crystal--

,-

Figure 1-7. Floating zone growth configurations. (a) Keck, small diameter; (b) Needle-eye, large diameter.

1.4 Single Crystal Silicon

phase doping during crystal growth, adding diluted phosphine, PH,, or diborane, B2H,, to the argon gas flow through the zoner, a wide range of both n- and p-type specifications can be made. The higher resistivities are more difficult to meet, and the tolerances quoted get wider. The equilibrium segregation coefficients for boron and phosphorus in silicon are 0.8 and 0.35, respectively, and so doping uniformity, both axially and radially, is somewhat easier to achieve with boron. The second doping method used is only available to the polysilicon producers. The thin rods used to construct the inverted " U ' structures, for the reactors in which the silicon deposition occurs, are made by fast pulling from a pure silicon melt. By adding phosphorus or boron to the melt, doped thin rods can be made to various specifications and stocked, to be used later when the deposition rods are planned for float zoning. Then as the molten zone is passed through the polysilicon rod the dopant in the core is released. Very precise resistivity control can be achieved by this method, with high run-to-run reproducibility. The third method, only possible for phosphorus, n-type, material, is neutron transmutation doping (NTD) which has become very important for power applications. 1.4.2 Neutron Transmutation Doped Silicon By float zoning undoped material under very clean conditions crystal can be produced in which the resistivity is of the order of 5000 Q cm or greater, and with a very low residual phosphorus and boron. If this ingot is placed into a nuclear reactor, transmutation doping generates phosphorus in an extremely uniform distribution, avoiding the growth striation phenomena common to both the float zone and

19

Czochralski growth methods, to be discussed later. This method is particularly suitable for making the high resistivity silicon required for power device applications, where the other doping techniques cannot match NTD material in its ability to meet very close tolerances. Normal elemental silicon consists of three stable isotopes with abundancies as: "Si "Si ,OSi

92.2 1yo 4.70% 3.09%

The possibility of doping silicon by transmuting the 30Si isotope into 31Pwas first recognized by Lark-Horowitz (1951). Later, Tanenbaum and Mills (1961) made detailed experiments to verify that the scheme was potentially useful, but this work lay on one side and only re-emerged when Herrmann and Mucke (1973) published their power device study. Since then the major developments have taken place, leading to a series of international conferences and many papers on this sole topic. The principal nuclear reaction upon which the whole process depends is 30Si(n1,y)+ 31Si t1/2 =

2.62 h

'

31P+ e -

(14)

The stable 30Si isotope captures a thermal neutron to form 31Si with the emission of y-rays. For this isotope of natural abundance 3.09%, the capture cross-section for cm2, or a thermal neutron is 0.11 x 0.11 barn. In its turn 31Si is unstable and decays with a half life of 2.62 h to the stable phosphorus isotope ,'P with the emission of an electron of energy 1.47 MeV. During neutron irradiation other nuclear reactions occur, some of which must be taken into account: '*Si (nl, y)

+

29Si

(15 )

20

1 Silicon Processing

and 29Si(q,y)

+

30Si

(16 )

The thermal neutron capture cross-sections for these are 0.08 and 0.28 barn, respectively, and the only real effect on the process arises from ingot heating by the emitted y-rays. However, two other reactions occur, which are much more important: "B(n,, a) + 'Li

(1 7)

In this reaction a total energy release of 2.5 MeV is associated with the a and lithium particles, which leads to considerable short range lattice damage. Boron has a very high thermal neutron capture crosssection of >755 barn, but, provided the boron concentration in the silicon is kept low, the effect is small. The most serious side reaction in the process is (18) Since the capture cross-section here is only 0.2 barn the amount of sulfur produced is minute in doping terms, but the long half life for the decay of 32Pcan impose restrictions on the handling of low resistivity NTD silicon. All the reactions so far have referred to thermal neutrons, that is, neutrons which have already been scattered by sufficient collisions within the pile that their energy has reached thermal equilibrium with the medium before intersecting the silicon. Such neutrons, at room temperature, have an average energy of only 0.025 eV and a velocity of 2200 m/s. However, fast neutrons in the pile, with energies in excess of 1 MeV, also reach the silicon. These give rise to much of the lattice damage generated during transmutation doping, and are also responsible for reactions of the type '%i(n,,a)

+

"Mg

(19)

producing a high energy a-particle. Even without reaction, the head-on collision of a 1 MeV neutron with a silicon atom will knock out about 200 silicon atoms from their lattice sites. Thus the slow-to-fast neutron ratio in the nuclear reactor is critical, and it is for this reason that heavy water reactors, with slow-to-fast ratios around 1000: 1 (a much higher ratio than available in light water and other reactors), have proved so successful for NTD processing. The subject of neutron irradiation damage has proved to be a matter of great complexity, beyond the scope of this chapter. Much lattice disarray is introduced, immediately after irradiation high resistivity values are found, and at this point most of the phosphorus formed is interstitial. Therefore the post-irradiation annealing process is crucial and has been studied in depth. The resistivity values, expected from the total reactor neutron flux, are fully realized after about 1 h at 600°C; however, defect studies indicate the need for a higher temperature, and poor minority carrier lifetime has been a problem (Meese, 1978). The producer's postanneal processes, which at the introduction of NTD products were at moderate temperature, sometimes relying on the high temperature semiconductor fabrication to complete the anneal, subsequently moved to higher temperatures and more complex time-temperature schedules. The exact details of vendor anneal schedules are generally sensitive proprietary information.

1.4.3 Carbon and Nitrogen in Float-Zoned Silicon For many years it was thought that any residual carbon in silicon was of little importance; it is an isoelectronic group 4 element, it occupies substitutional sites in the

1.4 Single Crystal Silicon

lattice, and silicon carbide is an insulator. The first indication of device linked effects came when Akiyama et al. (1973) reported a correlation between high carbon concentrations, reduced breakdown voltage, and increased reverse current leakage in rectifier diodes. Because this work used silicon with a very high carbon level (between 1 and 2 x lo1’ atoms/cm3) close to the solid solubility limit, and only appeared as a short communication, its significance was generally overlooked at the time. Carbon was not listed in most purchasing specifications. The common requirement of trichlorosilane for organosilicon and semiconductor use has already been noted in Sec. 1.2, and many of the world’s polysilicon plants are cosited with, or close to a silicones plant. Thus, when in mid 1975, accidentally and undetected, a quantity of high-carbon float zone silicon reached device lines, serious yield problems were met in rectifier, thyristor, and power transistor manufacture. Subsequent research showed that, while not affecting the breakdown voltage, lower levels of carbon still degrade the reverse leakage, as is shown in the plot of Fig. 1-8. Recognizing a severe problem, polysilicon producers made major plant overhauls to remove carbonaceous sources from pumps, valves, glands, etc., set new low carbon operating standards, and instituted strict test procedures - in single crystal the substitutional carbon has an infrared absorption at 16.6 pm (605 cm- I ) measured by differential (double-beam) spectrophotometry, ASTM Standard F123. Today carbon levels are rigorously controlled by all silane, TCS, and polysilicon producers, to ensure final silicon levels below around 2 x 1OI6 atoms/cm3. The role of nitrogen in silicon is quite different. Unlike other group 5 elements, such as P, or As, nitrogen does not behave

21 I

300 2

- 100

P (u

U

m

1

+ m 200 P

I

c

10

t

c (u

2

L

2 (u

D Y

m (u

1.0

100 2

cn

rn Y m ( u

VI aJ L

0.1

01

QJ w

i 1015

I

10l6

id7 C, I

o m

Carbon concentration (atorns/crn31

Figure 1-8. Rectifier diode failure as a function of carbon concentration: o breakdown voltage; x reverse leakage current. Note that, even when the breakdown voltage has been restored, leakage effects persist to much lower carbon levels. The dashed vertical line marks C,, , the carbon solid solubility saturation value.

as a donor impurity. An electronic center deep in the band gap has been reported by Tokumaru et al. (1982), but in general nitrogen does not appear to be electrically active in melt doped silicon. Another distinguishing feature is its low solid solubility: 3 x IOl5 atoms/cm3 at the melting point of silicon (Yatsurugi et al., 1973).This is much lower than for other light elements, ~ , such as carbon, N = 3.5 x lo1’ ~ m - or oxygen, 1.7 x lo1* atoms/cm3. In float zoned silicon the equilibrium solid solubility is often exceeded, the excess concentration being proportional to the zone velocity, where typically the values met may be up to 5 x lo1’ atoms/cm3 (Yatsurugi et al., 2973). The low electrical activity of nitrogen in silicon is useful because it has a major attribute, in that nitrogen doping at low concentrations, limited by its solid solubility, effectively inhibits dislocation generation and propagation, as first reported by Abe et al. (1981). Second-phase hardening is a well known metallurgical phenomenon,

22

1 Silicon Processing

amount of crystallographic slip caused by the controlled thermal stress. The results in Fig. 1-9 show clearly the advantages of NFZ doping. The material has been used successfully in both, bipolar and MOS, fabrication, but has not yet achieved major market penetration.

but usually occurs at higher concentrations. Low levels of nitrogen in silicon, in the 1015atoms/cm3 range, impart resistance to the thermally induced warp of wafers met during device fabrication. Slices of Czochralski silicon, grown from a silica crucible, with around 8 x l O I 7 atoms/cm3 oxygen content, are warp resistant, unless some of the oxygen is precipitated, when the material becomes less resistant, and here the oxygen levels are three orders greater. Normal float zoned silicon slices, with an oxygen content less then 1 x 10l6 atoms/cm3, and also low in carbon, distort readily under thermal stress, but with nitrogen doping outperform high oxygen Czochralski material. A simple demonstration to compare the normal FZ and CZ material is as follows. Standard, polished, (100) orientation single crystal slices, 76 mm diameter, 380 pm thick, mounted on a three support point silica jig span 63 mm, and loaded by a 50 g weight are heated at 1150 "C for 1 h, ramping the temperature up and down from 850°C in 30min measuring the change in warp, and, by Secco etching, the Slices a l l 380pm thick

140

1.4.4 Periodic Crystal Growth

Temperature oscillations during crystal growth have been recognized for a long time, and their effects described (Carruthers, 1967; Hurle, 1967; Chedzey and Hurle, 1966). At first sight this may appear an odd concept, but the underlying principle is simple and can easily be demonstrated (Hurle et al., 1974). A small channel containing gallium (a metal which, conveniently, is molten at temperatures above 30°C) with a number of thermocouples inserted equispaced along its length is well wrapped in thermal insulation to prevent heat loss. One end of the channel is clamped to a flowing water cooler, and so held at around 35-40°C. The other end is attached to a heater, whose temperature is

{loo! orientation

- LH

Load 5 0 9 Span 6 3 m m

___

120

-3 0 0

Change in TIR (warp) axis Extent o f slip RH axis

80

.-c & 60 c

m

5

I I I I

40 20

0

I

L Float zone N-doped

-

Float zone standard

Czochralski 0-doped

Figure 1-9. A comparison of warp and slip after loading slices (1 h at 11 50°C) (LH: left hand, RH: right hand). [Note that curvature in a silicon slice is hardly cvcr a simple saucer shape; it is more like a potato chip (potato crisp). Modern metrology equipment scans the whole surfacc to arrive at a single value, the total integrated reading (TIR), and also provides plots of the surfaces.]

1.4 Single Crystal Silicon

gradually increased. At first, simple heat flow along the channel creates a thermal gradient, recorded by the thermocouples. However, as this temperature gradient is increased, a point is reached when the thermocouple signals suddenly change into regular sinusoidal oscillation. The system behaves analogously to an electrical AC driven oscillator, whose frequency is determined by the inductance-capacitance product. Here the thermal diffusivity, kinematic viscosity, and channel dimensions, replace their electrical counterparts in an equivalent thermal -mechanical resonator. Thermal oscillations have been seen widely in many crystal growth systems, not only in semiconductors - Si, Ge, GaAs, InSb, etc. but also in LiNbO,, garnets, and most oxides and fluorides (Cockayne and Gates, 1967). Superposition of oscillations on the temperature near the solidliquid interface between a crystal and its melt causes large regular fluctuations in the growth conditions. The driving force, which determines the overall rate of growth, is provided by supercooling setting the melt temperature close to the interface a little below the melting point. Since most crystal growth rates are relatively slow, this value is normally smaller than the magnitude of the thermal oscillations, and so the growth becomes highly dynamic, and even, at the peak of each cycle, includes momentary meltback. This periodic nature of crystal growth controls the incorporation of dopants and impurities into the crystal, whose concentrations may vary markedly, the changes exactly replicating the periodicity. The regularity of these growth striations can be seen by etching, and by spreading resistance (microresistivity) measurements, made on a cut vertical section of a crystal, as shown in Fig. 1-10. Since the crystal growth interface across a diameter is always curved, cut

23

-

-

Figure 1-10. Periodic crystal growth (1). Spreading resistance plot (above), with points taken at 10pm intcrvals along the growth axis. Etched surfacc micrograph (below), showing the structure variations within a single striation.

slices intersect several striae, and subsequent delineation reveals a spiral radial impurity distribution pattern in the slice, as shown in the X-ray topograph of the carbon distribution in a float-zoned slice in Fig. 1-11. (Note: the X-ray topography technique is covered in Sec. 1.6.1.) If growth periodicity did not include a meltback within the cycle its effect on impurity distribution would be far less severe. This has been demonstrated by the float zone growth of small diameter rods, when the latent heat of solidification generated at the interface can escape more easily than at larger diameters, permitting higher growth rates. As the rate is increased, a

24

1 Silicon Processing

such crystals reveal an extremely wide scatter of values. Such material is immediately rejected. The effects of normal striated silicon in device manufacture are quite variable. In some cases it does not seem to matter, but in other cases striae can cause serious losses. Again because of the greater difficulties in zoner operation, float zone silicon tends to have more problems. For example, in the manufacture of UHF transistors, for applications at around 500 MHz, the cut-off frequency, f,, is a function of the collector base current, I,, , which is very susceptible to small, local, microresistivity variations. In a direct comparative trial, the percentage standard deviations about the mean of f,, J;, at the operating I,, current, has been measured using three materials sources (see Table 1-3). In the third material an epitaxial layer of the same type, and resistivity as the underlying substrate, deposited from the vapor phase, and so free of the melt-growth striae, provides an extended bulk material within which the transistors are fabricated. As the table shows neither CZ nor F Z can match extended bulk epitaxy, EBE, while the FZ material is the worst in this application. EBE material is used in large scale production of these devices, its additional cost far outweighed by the yield improvement. ~

Figure 1-11. Periodic crystal growth (2). X-ray topograph of the carbon distribution across a cut slice. C, = 4 x loi6atoms/cm3.

point is reached when the supercooling gradient overcomes the thermal oscillations, and at a growth rate above 3 mm/ min the striae dissappear. This research, while interesting, is not a production option. In the case of Czochralski growth, where, as will be discussed later, the melt is normally positioned in the heat field to keep thermal convection low, the axial pitch of striations is closely linked to the growth parameters. The etched vertical section shown in Fig. 1-10 was taken from an 80 mm diameter, (100) orientation, crystal pulled at 1.5 mm/min, with a rotation rate of 15 rpm hence the thickness of the silicon layer grown per revolution was 100 pm, which, as the measurements show, is also the striation pitch. On the other hand if the crystal is grown under high thermal convection, that is, forced convection, conditions, then the striae are closely spaced, discontinuous, and aperiodic (Carruthers et al., 1977). Spreading resistance measurements taken on the slices cut from

Table 1-3. The effect of resistivity striations on device mean value of performance. c:standard deviation, the cut-off frequency.

x:

Type of material Float zone Czochralski Epitaxially extended bulk

c(1)in % 24 10

3

1.5 Czochralski Silicon

Epitaxy therefore is one way to overcome the bulk striation problem. Another is the neutron transmutation doping method already described, and whose importance in the high voltage and power fields will now be more fully appreciated. Again the costs are obviously somewhat higher than for the conventionally doped materials, but the fabrication and device performance are far superior. Herzer (1977, 1980) and Herrmann and Herzer (1975) have examined the interaction of striations in NTD doping. Using material with a starting resistivity of 10 times the final value shows no background striations, at 5 times slight striations are seen, while an initial resistivity 2 times final, gave f 10% variations. A third, and the most widely used way to overcome striation effects, which introduces no added costs, is that employed in MOS integrated circuit fabrication. Taking n-MOS as the example, the substrate is p-type, boron doped at around 20-30 SZ cm resistivity. The MOS devices are made entirely by ion implantation, with n + source and drain channels, and an n- gate implant equivalent to a resistivity of somewhere around 1 - 5 i2 cm. These implant concentrations are at least 10 times higher than the substrate boron level, and striation effects are reduced to insignificance; that is, similar to the NTD situation. Today integrated circuit manufacture consumes more than 75% of the world's semiconductor silicon as Czochralski crystal, our next topic.

1.5 Czochralski Silicon The increasing size of crystals pulled by the Czochralski (1917) technique, and the technological developments associated with the growth of dislocation-free material, in which there is close control over not only

25

the dopants, but all impurities, represents one of the outstanding achievements in semiconductor processing. The silicon pullers used initially were quite simple (Teal and Buehler, 1952). The charge, consisting of small lumps of broken polysilicon, was melted together with a small precise amount of dopant, from a silicon alloy made with P, As, or Sb (n-type), or B (ptype), at just above the melting point, 1412 "C, in a pure silica crucible, retained in a graphite holder to prevent it sagging, held under an argon atmosphere; either resistance or R F induction heating was used. A thin, single crystal, seed rod mounted in a rotating shaft was lowered into contact with the melt surface, and a little melted off in order to establish a clean solid-liquid interface. Then, as the temperature was lowered, silicon started to solidify on the seed, which was withdrawn at a controlled rate to pull a crystal of the desired resistivity, ultimately almost emptying the crucible. This apparently simple description is deceptive, there were many hidden subtleties needing to be understood. It was soon realized that, to be able to pull a crystal at all, without spurious growth at the crucible wall, it was essential to have a centrosymmetric heat field - the introduction of crucible rotation followed, which also eliminated random convection in the melt. As charge sizes increased, R F heating was abandoned, and the tapering of graphite resistance heaters was used to shape the best vertical heat field profile. However, having established this in the melt -crystal interface region, it could only be maintained as melt was used by introducing a crucible lift mechanism. The furnace configuration which resulted, as shown in Fig. 1-12a, is that still in use in even the largest pullers.

26

1 Silicon Processing

1:’

Crystal rotation and lift

Seed

Solid conduction /

Surface radiation

Thermal baffles SiO evaporation Interface generation of latent heat

Crucible holder

Oxygen dissolution

Crucible

1,

Heater

Heater

‘I

ll

M

q€===== II

Vacuum pump I

-1

Crucible rotation and lift

la)

-t

Ib)

Figure 1-12. The Czochralski silicon crystal puller. (a) Principal components of the hot zone. (b) Heat flow (t) and oxygen transport (0)during crystal growth.

1.5.1 Dislocation-Free Silicon The first dislocation-free material (Dash, 1958, 1959, 1960), was made by slowly growing small finely tapered crystals, but Zeigler (1961) used a rapid pull rate after seeding, to establish a thin neck, in which the few dislocations present grew out to the side surfaces, onto which a large dislocation-free crystal could then be grown. This was possible since, once a crystal is free of dislocations, it is better able to withstand the thermal stresses met during crystal growth. Prior to the introduction of dislocation-free growth, the germanium and early silicon crystals contained lo5-lo6 cm-’ dislocations. As a result of the thermal gradients in the system, these formed up into arrays, and lineage, deteriorating towards the bottom of the crystal; twinning was a serious problem leading to yield losses (Wilkes, 1959). The ability to grow

dislocation-free crystals depends critically on control of the shape of the solid-liquid interface in the meniscus region. Why any crystal takes the shape it does is closely linked to this problem, and is examined first. The external shape of a crystal is related to two basic parameters, each a generic term covering several associated attributes: (a) Temperature, T, which includes all aspects of heat flow conduction, convection, etc. - and generation - from the main heater, or from latent heat at the interface. (b) Crystal habit, C,, which includes all aspects of morphology - nucleation, crystal growth along basal planes, dislocation formation, twinning, etc. ~

The totally facetted alum crystal from a near isothermal solution growth is crystal habit dominated, while the near shapeless

1.5 Czochralski Silicon

mass from a crude unbaffled melt system with high temperature gradients is temperature dominated. Normal Czochralski growth from a well designed system produces crystals whose macroscopic features show the balance that exists between the “temperature”, and “crystal habit”, contributions. In such a machine a very slowly rotated, (1 11) orientation silicon crystal can be pulled, at low or high growth rates, and will not exhibit any marked “flats” along its sides. There are high-temperature gradients across the melt surface in the vicinity of the growing crystal. On the other hand, under fast rotation conditions, while the interface shape becomes fluid flow dominated, the crystal grows out of a near isothermal surface; and such crystals, irrespective of growth rate, always exhibit extremely pronounced “flats”. Under normal growth using moderate rotation rates a crystal may exhibit narrow side facets near to its top which increase in width towards the bottom, when the near empty crucible behaves as a “black box”, near isothermal, cavity. For this reason the crucible and remaining charge is lifted faster than needed to keep the melt surface stationary, but lifting it out of this too isothermal region, so avoiding excessive facetting. The T $ C, balance applies everywhere, including at the solid- liquid growth interface, on which we now focus. While the main heater, and baffles, determines the overall thermal profile of the puller, it is actually quite ineffective in influencing the interface shape of the growing crystal, whose thermal conduction provides a good heat sink during growth. However, the latent heat of solidification (12.1 kcal mol-l or 50 J mol-I), released at the interface, is a significant heat source. As the pull rate increases the interface curvature changes from convex (into the melt),

27

to concave (back into the crystal). Silicon crystallizes in the diamond-cubic lattice, with the (111) planes being the most densely packed, while the bonding between adjacent ( I l l ) planes is relatively weak compared to other directions. Growth is fast along the (111) planes, so leading to the appearance of { 111) facets on crystals, but slow perpendicular, while cleavage, twinning, and dislocation generation and propagation all occur along this dominant basal plane (Ellis and Treuting, 1951; Townley, 1973). Since in the T =+C , interactive model, facets are only expected in near isothermal regions, their position and size can be predicted, as the interface shape changes from convex to concave during the growth of a (1 11) orientation silicon crystal, shown in Fig. 1-13, and matched by a series of actual interfaces of crystals snatched from the melt grown at increasing pull rates: from convex, to inversion, to ring facet, finally concave (Wilkes and Perkins, 1971-72). Dislocations form on the very small peripheral (111) facets at the edge of convex interfaces, and once formed continue downwards into the crystal as it grows further. This cannot happen where the (111) crystal is bounded by a ring facet, or, in the case of a (100) crystal, when the interface is concave. These are the conditions for the zero dislocation growth of silicon, and are established immediately after seed-on in a narrow neck, before proceeding on to enlarging the diameter to full size. As stated earlier, when a crystal is grown in the dislocation-free mode from its start, it is better able to resist the temperature gradient hoop stresses met later as the solid crystal cools, when it is withdrawn from the hot zone in the puller. To avoid thermal shock at the end of the pulling process, when the crystal is withdrawn from the residual melt, which can

28

1 Silicon Processing

Figure 1-13. The changes in interface shape of a (1 11) orientation silicon crystal as the growth rate is increased. As the growth rate increases latent heat of solidification at the interface plays the most significant role in

determining its shape (LHT, latent heat temperature profile; MHT, main heater temperature profile; hatching indicates the solid crystal). (1, A) Low speed, small central facet, convex. (2, B) Somewhat faster pull, larger central facet, still convcx. (3, C ) Even faster pull, latent heat generation now compensates for heat losses across the whole interface, which becomes a {I 1 1 ) mirror surface; the point of inversion. (4, D) Speed of growth greater than for inversion, producing a wide ring facet and a small relatively shallow central concavity. (4, E) Speed faster still. The central cavity is deeper and wider so there is a narrower ring. (5, F) The pull rate is now very fast and any MHT/LHT compensation is outside the pheriphery of the crystal. Very deep concavity, no ring facet.

lead to stress-generated dislocations running back up into the solid, so causing yield losses, the final part of the crystal is grown tapered in a cone to a point. Mastery of the zero dislocation growth mode, for both CZ and FZ techniques, at the end of the 1960s, preceded the later machine developments which have led to the crystals weighing more than > 60 kg, with diameters of up to 150 mm or more, in cur-

rent production many thousands of tons of dislocation-free silicon per year. ~

1.5.2 Constitutional Supercooling For epitaxial substrates, large amounts of very highly doped, n + and p + , zero dislocation crystal are needed, which involves the particular problem of constitutional supercooling, as described for metals by

1.5 Czochralski Silicon

29

Rutter and Chalmers (1953). At the crystal-melt, solid-liquid interface of a growing crystal impurity segregation occurs, its coefficient, different for each dopant, defined by concentration in solid keff = concentration in bulk liquid

I

-~ - cs

(1-2)

c,

For a rejected impurity keff is less than 1.0, but as a result of the rejection, a boundary layer builds up in the liquid at the interface, at a higher concentration than in the bulk, from which the crystal grows. Therefore the effective k e f ffor a finite growth rate is higher than the equilibrium value, k , , and rises with increasing growth rate. The thickness of the boundary layer, 6, within which fluid motion is laminar, relatively slow, and hence nonmixing, so that diffusion is the predominant transport mechanism, is determined by the crystal rotation stirring, and as the rotation rate increases the boundary layer gets thinner. This relationship is given by the Burton, Prim, and Schlichter (Burton et al., 1953) equation

keff =

k0

ko

+ (1 - k,) exp (

-

vg 6/D)

(1-3)

where ug is the growth velocity, and D the impurity diffusion coefficient in the liquid, cm s. This formula of the order of 5 x shows that k e f f varies continuously from k , , at very low growth rates, to 1.O, at very high rates. The higher impurity level in the boundary layer results in a silicon-dopant composition of lower freezing point, as seen in Fig. 1-14. The temperature gradient from the solid into the melt, necessary to allow growth at the chosen rate, is also shown in Fig. 1-14. At the higher rates needed to obtain the desired interface

Temperature gradient i n t o melt L al

a

+ m 01 L

n

5

+

Tr,

Position o f maximum supercooling due t o local composition Distance i n t o melt

Figure 1-14. Constitutional supercooling during k , = C,/C,, k,,, = CJC,, crystal growth. 6 2 1.6D"3 V ' ' ~ W ~ ' 'TcG: ~ , crystal growth temperature. As u, and 6 + 0, k,,, -+ k,; and as ug and 6 become large, k,,, + t .O.

shape for dislocation free growth, and when the dopant levels are also high, a region is formed in the liquid, ahead of the crystal, which is supercooled by virtue of its local constitution, and in which nucleation and random crystallization can happen. As the advancing interface approaches this point, the single crystal rapidly becomes polycrystalline. The greatest risk of this occurring is in the later stages of n', or pf crystal growth, when segregation by normal freezing, as defined by Eq. (1-I), further increases the already high initial dopant concentration. Studies of the onset of constitutional supercooling in these crystals (Wilkes and Perkins, 1971-72), using striation etching to reveal the details, has shown that the initial perturbations, and formation of cellular structure, in (1 11) orientation silicon, originate on the inner edge of the ring facet, as

30

1 Silicon Processing

Figure 1-15. The onset of constitutional supercooling at the inner edge of the ring facet during the growth of dislocation free, (1 11) orientation, n + Sb doped, silicon. Note: In the enlargements the arrow points outwards radially. At a later stage of growth, the whole interface breaks up into a hexagonal cellular structure, prior to the transition from single crystal to polycrystal.

shown in Fig. 1-15. Acheiving high production yield and reproducibility for this material demands precise control of the pulling parameters.

1.5.3 The Incorporation of Carbon and Oxygen Most of the components in the hot zone of a puller are made of some form of carbon - graphite heaters and crucible holder, and carbon felts in the baffle assembly but careful housekeeping can virtually eliminate these as a source of contamination. Maintaining the pullers leak-tight, using ultrapure argon as the purge gas, and employing rigorous purging schedules after ioading the charge, remove air or rnois~

ture, which could otherwise react with the carbon parts to form CO, to dissolve into molten silicon; and as we have seen, polysilicon itself is very low in carbon yet carbon can be a problem. During the first step of meltdown of the polysilicon into the pure silica-glass crucible the system is at its hottest, up to around 150O-155O0C, to achieve meltdown in a short time. Under these conditions reaction between the graphite crucible holder and the outer surface of the silica crucible releases carbon monoxide [see Reaction (1-l)]. This is the prime source of the carbon impurity. After the meltdown is complete and the temperature is lowered, to around 1420-1430°C for the start of pulling, the reaction only continues at a ~

1.5 Czochralski Silicon

much lower rate (Barraclough and Wilkes, 1986). In an atmospheric pressure puller, where the argon purge rate is commonly around 60 L/min, the initial carbon content in the crystal is around 2 x 10l6 atoms/cm3; but, if the start is deliberately delayed, this steadily rises as more carbon is slowly dissolved. Operating the puller at a reduced pressure, of about 20 torr ( z2600 Pa), with an argon input of 10 L/min at normal temperature and pressure, the effective gas displacement rate sweeping out the chamber is increased six-fold, and the silicon crystal produced contains far less carbon by at least an order of magnitude. Under carefully regulated conditions, a large proportion of the crystal can be grown with carbon below its infrared absorption detection limit of 5 x l o L 5atoms/cm3. In this case when meltdown is complete, and during crystal growth, further carbon transfer is insignificant. Today all large silicon Czochralski production pullers are operated at reduced pressure. While risk of carbon incorporation is essentially limited to the meltdown period, another reaction continues throughout the whole process - that between the silicon and the inner surface of the crucible, dissolving oxygen into the melt: Si + SiO,

-+

2SiO

which, at the same time, allows any other electrically active impurities present in the silica into the melt. Crucible quality is clearly important, and has steadily improved as natural sources of silica have widely been superceded by the use of fused synthetic SiO, made from semiconductor grade materials. As a result, the resistivity reached by pulling undoped silicon is now routinely greater than 200 Q cm, and with low compensation. This has permitted the producers to offer CZ crystal specifications

31

of up to around 50 R cm resistivity, n- or P-tYPe. Returning to the oxygen dissolution, as can be seen in Fig. 1-12b, this occurs primarily along the hotter inner wall of the crucible, and only to a lesser degree across its base; and, while thermal convection transports the SiO up to the free melt surface where it can evaporate, much oxygen becomes incorporated into the growing crystal. This is a highly dynamic equilibrium, altering continuously as silicon is withdrawn from the crucible, and the ratio of melt volume to crucible surface contact area changes. The oxygen concentration decreases down the length of the crystal typically from near loi8 atoms/cm3 at the top to around 5 x lo1' atoms/cm3 towards the base end; that is, from 20 to 10 ppma. In the Czochralski system, melt fluid dynamics clearly play a vital role in the growth, and in the incorporation of all impurities, into the crystal; the prime contributors being the thermal convection and the mechanical drive provided by the crystal and crucible rotations - usually in opposite sense. The convective drive is influenced by several factors. In fluid flow adjacent to a hot vertical wall, the velocity is a function of the temperature gradient, height up the wall, h, and Prandtl number, Pr (Schlichting, 1968):

(1-4) where the dimensionless Prandtl number, the ratio of the kinematic viscosity to the thermal diffusivity, is a measure of the relative ease of movement and heat transport in a fluid element. The value of Pr (Si, liq.) is 0.015, a lower value than that of mercury, 0.023. [In comparison Pr (H,O, room temperature) is 7, and Pr of glycerol is 300.1 Because liquid silicon has such a low Pr value, as heat flows through the wall into silicon it read-

32

1 Silicon Processing

ily convects. (A stability analysis for convection links this low Pr to the rotationally coupled thermal oscillations, described in Sec. 1.4.4 above.) Therefore thermal convection is less in a relatively wide flat melt, as is normal in CZ silicon, and decreases as the liquid diminishes. (Note: in the CZ growth of oxides, with Pr around 30, taller narrower crucibles are common.) Positioning the crucible lower in the heat field, with a greater power transfer into the upper part of the melt, also promotes a reduction in the convective drive. Again, the baffle configuration surrounding the heater crucible assembly reduces the temperature gradients in the system, and can be arranged to keep the crucible wall cooler, so reducing its dissolution rate (Moody, 1986). The functions of the mechanical rotation drives are quite different. Rotation of the crystal only couples it to the melt over the small area of its base, and this is withdrawn above the surrounding free surface by the height of the meniscus cell - about 4 mm. Thus, while crystal rotation directly affects the dopants incorporation, and their uniformity across the crystal, it has only minor influence on the bulk fluid motion. A realistic analogy is that of a skater on ice. On the other hand, the crucible rotation couples to the whole body of the melt, and, particularly in large systems, provides an important centripetal force, to modify the thermal convection. Heat flow, and the theory of rotating fluids, are mathematically complex, and generally involve significant approximations, even when using computer iteration procedures. However, because of its importance, there has been much work on silicon - CZ flow patterns (Robertson, 1966),nonmixing cells (Carruthers and Nassau, 1968), computational analysis of interface

shape and flow in a crucible (Kobayashi and Arizumi, 1970; Kobayashi, 1978; Kobayashi and Wilcox, 1982), digital flow simulation (Langlois and Shir, 1977; Langlois, 1984, 1985), and heat transfer in CZ systems (Dupret et al., 1986) - which taken overall indicate that the main mode of convection is natural, rather than forced. Under the conditions of a well designed thermal geometry, with more gentle convection, it is easy for the crucible rotation centripetal force to play a greater part in shaping a stable thermohydrodynamic melt. The simple model of melt convection in a very slowly rotating crucible is that of a single Benard cell - liquid rising near the wall, then flowing inwards radially, near to the melt surface, towards the growing crystal. As the crucible rotation rate is increased, the centripetal forces act in opposition to the convection, slowing the fluid motion, until at some higher rotation rate the melt behaves almost as a solid body. Such solid body rotation is seen in water dye tracer simulations of CZ systems, and a practical application is found in the control of the oxygen content of silicon crystals. Since the fluid convection transports not only dopants but also heat to the vicinity of the crystal, increasing the crucible rotation reduces this heat flow, and it is necessary to increase the crucible wall temperature to compensate and maintain constant diameter growth. Optical pyrometer measurements of the wall temperature have recorded rises of 30-40°C at high rotations. As a result the silica dissolution rate rises markedly, providing a higher oxygen flux to the crystal. This is seen for a series of crystals, grown at increasing crucible rotation rates, in Fig. 1-16, which also shows how accelerating the rotation as growth proceeds can produce silicon to specified limits in oxygen content (Barraclough, 1982; Murgai et al., 1982).

1.5 Czochralski Silicon

c 0

m

Fraction solidified (gl

Figure 1-16. The effect of crucible rotation rate on the incorporation of oxygen into Czochralski silicon.

This process works well for the production of medium to high oxygen content material but good yields at lower oxygen concentration are difficult to achieve. This problem is now addressed in the next section.

1.5.4 Magnetic Czochralski Silicon Electromagnetic stirring and other effects in molten metals have been recognized for many years, and, in the intense radio-frequency fields within the heater coil of a float zoner, magnetic levitation in part supports the molten silicon. Some large Czochralski pullers have used a three-legged graphite picket heater, driven from a three-phase AC mains supply at 50- 60 Hz, the heavy heater current inducing rotational forces in the melt, where flow rates as high as 20rpm have been observed. The latest puller designs have returned to using two-legged picket heaters and DC drive to avoid this effect. Today it is the application of static magnetic fields to dampen out the convection flows in Czochralski systems that is important.

33

The early work by Chedzey and Hurle (1 966) was initially directed towards the suppression of growth-striae in FZ, and then in CZ crystals (Hurle, 1967). Czochralski growth in a transverse magnetic field was reported by Witt et al. (1970), but it is the recent revival, initiated by Hoshi et al. (1980), who applied very large electromagnets to commercial silicon pullers, that has stimulated worldwide interest, and major developments. The Sony Co. results show that products with a wide range of oxygen content can be made by Czochralski growth in a strong magnetic field; the technique offers the control of resistivity up to 5000 Q cm, and also higher than normal growth rates. Both electromagnets and superconducting cryomagnets have been used to provide fields in the general range of 1000- 5000 G (0.1 -0.5 T). Hoshi et al. (1980) and Suzuki et at. (1981)first used a transverse magnetic field, with the lines of force parallel to the melt surface; axial fields have also been applied (Hoshikawa, 1982; Hoshikawa et al., 1984; Cartwright et at., 1985). As the strength of the magnetic field is increased, fluid motion perpendicular to the lines of force is progressively dampened out until, in a high field, it is suppressed altogether. Thus in an axial, vertical, field the radial fluid flow across the surface is reduced; whereas in a transverse, horizontal, field it is the axial (upwards at the crucible wall, and downwards beneath the crystal) and azimuthal motions (rotational shear around the crucible wall) which are reduced but then not the radial flow. Clearly, in either mode there is a strong effect on thermal convection. Hoshi and Suzuki showed that a horizontal field of 0.15 T was sufficient to suppress the convection in a melt contained in a 25 cm diameter crucible. Again, the balance between field strength and the crucible and

34

1 Silicon Processing

crystal rotations, both in their rates and relative senses, is apparent in the effects on impurity distribution. In a vertical field a wide range of oxygen concentrations is possible, but, because the radial flow is reduced, it is dificult to achieve acceptable radial uniformity, compared with the results possible in the absence of a field, whereas very good radial impurity distribution is possible using a transverse horizontal field. The two magnetic field modes are distinguished principally by the large differences in their temperature distributions, and gradients, which to a considerable degree determine the alternative product properties. Using the vertical-field conditions the increased radial temperature gradients are larger than if no field were present, whereas in the same puller under horizontal field conditions the temperature gradients are reduced, and can be much smaller than with no field. As we have previously seen, the oxygen dissolution rate is set by the wall temperature, and experience now suggests that horizontal-mode growth is more suitable for the production of controlled low-oxygen silicon. While both modes sharply reduce the growth striae, produced by thermal fluctuations in the melt close to the interface, which are a feature common to all zero field growth, again it is the lowtemperature gradient beneath the crystal, available under transverse fields of around 0.25-0.3 T which permits growth rates some 50% higher than with no field, yet maintaining the correct interface shape required for dislocation-free growth. While the balance of these trends, when set against the device maker’s needs, appears to be moving towards transverse-mode material, very recent research has explored the development of shaped, compound magnetic fields, with horizontal, vertical, and low-field components, designed into

different sectors of the melt, obtained from the interaction of two vertical coaxial magnets placed one above the other (Barraclough and Series, 1988). The makers of commercial production Czochralski pullers now offer machines with either magnetic mode and 60- 150 kg silicon capacity (e.g., from Hamco or Ferrofluidics). In summary, Czochralski silicon technology is indeed very complex. A large number of highly interactive, adjustable parameters are available in the thermal design of the core furnace, its heater and baffles, and in the aspect ratio of the melt; in the mechanical movements to position, lift and rotate the crucible and crystal; and now in the magnetic conditions, in mode choice, and field strength and position. It is, however, precisely this flexibility in design variables and growth control, not available to the same degree in float zoning, that gives the Czochralski technique its power to address the product requirements. 1.5.5 The Commercial Scaling of Czochralski Silicon

The constant competitive pressures in the market, and the demand for ever larger slice diameter, doubling about every seven years (seen in Fig. 1-2), together with increasingly stringent quality specifications, have placed emphasis not only on the technologies discussed so far, but also on process scaling. During crystal pulling from a crucible, unavoidable yield losses occur from the silicon used in the top and base cones, and in the residual silicon left in the crucible at the end. Further fixed losses are entailed in grinding the ingot from the growth diameter to exact cylindrical dimensions before slicing to parameter limits (e.g., resistivity, oxygen content). As the diameters have risen it has been essential to

1.5 Czochralski Silicon

scale up capacity in order to maintain the output-input ratio. The plots given in Fig. 1-17 show clearly why pullers used for the production of 150 mm diameter slices need to be in the 30- 60 kg range; and the introduction of 200mm slices pushes this further. Modern pullers with the features described above, > 60 kg capacity, with fully automatic, computerized growth control, with a 2 m (or more) pullstroke, and designed for 150- 200 mm diameter slice production, cost up to $ 1 M. each; a price which continues to increase as the new magnetic techniques have been introduced and even larger machines are built. However, automation leads to high product reproducibility, and, when worked continuously, these machines have a high silicon throughput. The economic gains of operating a block of such pullers, linked to the expertise needed, goes far to explain why the device houses have largely withdrawn from materials. The developments described have been essential to keep production costs down during the past inflationary, and competitive, decade; this is demonstrated in Fig. 1-6, where the single crystal plot is for standard base-line specification material. To place the whole operation into a framework, Table 1-4 gives an added value comparison for silicon material at key points in its manufacture, from metallurgical silicon to an epitaxial slice,

/ I /Id (u

-$I2 Jz U

a 4

0 10 20 30 40 50 60 70 80 90 Yield (%I Figure 1-17. Czochralski silicon growth. The influence of the crystal diameter on the initial charge weight and maximum yield possible.

taking as reference polycrystal silicon at a value of “100”. Today the ongoing increase in the size of ULSI chips described in the introduction is forcing further scaling-up to 200mm diameter wafers; some 250 mm material is already being made, and research towards 300mm is active. As the melt volume increases it becomes ever more difficult to control the fluid motion. As shown in Figs. 1 12 b, heat enters through the near vertical side wall of the crucible, and the principal heat losses are axial - downwards through the base, and upwards by conduction through the crystal and by radiation from the melt surface. However, even in a 30-40 kg melt the fluid motion is complex. Although the heat transfer mechanism still leads to the molten silicon rising around the crucible periphery and falling in the central region, the form is no longer a simple Benard cell. It is much more complex, -

Table 1-4. Addcd valuc comparison in silicon materials. Material stage Metallurgical grade Si Ultrapure polysilicon Monosilicon rod Polished Si slice Epitaxial slice“ a

Product price per kg 20 100 500 -900 2000 4000 5500- 14 000

(Ref.)

Epitaxy is the subject of Chap. 3 of this Volume.

35

36

1 Silicon Processing

with rotating eddies swirling in the mid-radial area superimposed upon the overall flow pattern. Crystal growth interfaces snatched from the melt reveal the greater thermal complexity, which causes the most problems during the initiation of growth, from seed on and through the phase until the crystal reaches a sufficient diameter that its rotation is able to stabilize the fluid flow geometry axially. As charge weights increase towards 100-1.50 kg these problems can only become more severe. Attaining high yields of close-tolerance material, both radially and along the crystal length, with respect to dopant and oxygen concentration will need fully computerized programmed control of all motions (translation and rotation), melt position in the heat field, and argon gas flow and pressure. During growth all these parameters may be varied continuously. For some years it has been recognized that the use of epitaxial material could offer advantages in MOS manufacture, in particular improved parasitic capacitance, leakage, and threshold voltage control, but the cost of an epitaxial slice has been a deterrant. Now, for large DRAM, SRAM, and some other applications, the use of pp’ and nn’ silicon is rising. However, the importance of gettering during fabrication means that the heavily doped substrate wafers needed for epitaxy also have precise oxygen-content requirements. This combination of very heavy doping and oxygen control in large diameter crystals poses further technological problems.

1.6 Slice Fabrication Stated simply, the polished slice fed into a device line must be flat, clean, and damage free; but often in the past, companies, after achieving good bulk crystal, have

failed to produce acceptable slice products. The steps used in wafer processing hide many pitfalls. In the slicing and grinding stages much damage is caused to the surface of the material, whether or not the shape be correct, and both have to be controlled. The subsequent etching and polishing stages have to remove the damage and produce the final surface in which devices are made. However, low level mechanical damage sites, at the back surface, have the useful property of acting as collection sinks for unwanted fast diffusing, electrically active, heavy metal contaminants, well away from the front polished surface and the devices. This is known as “extrinsic gettering”. On the other hand the precipitation of oxygen within the bulk of the slice, but away from the surface, provides internal, “intrinsic gettering” sites which perform a similar role. How these various features are handled is the subject of this section.

1.6.1 Mechanical Damage in Silicon The subsurface damage in silicon which results from the processes of diamond grinding, sawing, or lapping, can be assessed by various means. An early method was based on the fact that damaged silicon is etched faster than undamaged material, so that plotting etch rate versus depth gave some indication of the extent of damage associated with a particular process. Minority carrier surface recombination is very high in damaged material, but falls rapidly as the damage is removed by etching, providing another route to depth assessment (Buck and McKim, 1956). The decoration of dislocations and damage centers by copper, followed by infrared transmission microscopy, permitted the direct visualization of defects in silicon (Thomas, 1963), but the effects of decora-

37

1.6 Slice Fabrication

tion at 900°C and quenching were questionable. An unambiguous measurement technique uses the X-ray double crystal diffractometer to study strain and defects in crystals. First introduced by Bond and Andrus (1952), applied to silicon, it has become a major tool in the study of machining. The X-ray system is shown in Fig. 1-18 a, where the double crystal configuration results in monochromatic radiation reaching the sample crystal. The signal to the detector, I(@, changes as the sample is turned through a small angle about the Bragg reflection, producing the rocking curve of Fig. 1-18b. Provided that the reference crystal quality is good enough (Tanner, 1977), the angular width of the rocking curve is a measure of the defects and strain present in the test crystal. The width of the rocking curve at half peak height -the half width - can be calculated from first principles using structure factors, and the angular beam spreads (Deslattes and Paretzkin, 1968; Batterman and Hildebrandt, 1968), where useful intrinsic half-width values, W,, for silicon are:

(b) (422) reflection from (100) silicon: = 15.4”.

w,

Observed half-widths greater than these intrinsic values measure the strain in the lattice, which may be quantified using the expression

A%

-= - A W

cot0,

(1-5)

‘1 0

where AW = (W, - Wc),that is, the difference between the measured and intrinsic half widths. In addition to the rocking curve, this X-ray method leads to topography. If the sample is rotated into a position where the signal is at a half-height value, and then the detector is replaced by a photographic plate, contrast across the image originates from the variations in signal intensity caused by localized strains around defects in the surface of the sample. Carbon is a smaller atom than silicon and its substitution in the crystal leads to local strain, which, developed in the whole slice topograph (Fig. 1-1I), shows its radial distribution. In both rocking curve and topography applications, the X-ray penetration depth is limited to no more than about 30 pm,

(a) (115) reflection from (111) silicon: W, = 6.3”, X-ray source

I1

Rockino curve h d t h

/<-test-

Half height

. 1 1

I

(a)

‘

T e s t sample angle ( 8 )

Detector or f i l m plate

(b)

Figure 1-18. The measurement of strain and defects in crystals. (a) The double crystal goniometer. (b) The rocking curve measurement.

38

1 Silicon Processing

14

a y1

11 2 J=

+ u W

.-c V

> 01

0 : L

r

'a 5

and therefore the method is usually coupled with etch removal of known depths, to build up a total picture of the damage. Applied to slicing, Fig. 1-19 shows the X-ray topograph of a step-etched sawn slice, and the associated step site density versus depth plot. In this case most of the sawing damage is confined within about 20pm depth beneath the surface. This is confirmed by the rocking curve plot shown in Fig. 1-20. Some low level of point damage sites persists beyond 20 pm, not readily

Initial, a s sawn, values 80 - 120s

I

0

5

I

I

I

I

10 15 20 25 Depth o f etch per side Iprn)

Figure 1-20. The depth of damage beneath a sawn surface measured by the etch/)(-ray rocking curve technique (A" = W, - WJ.

d

Figure 1-19. X-ray topography of a sawn and step-etched slice. Reflection: {220}, Mo KELradiation.

seen in the topograph, but detected by the signal integration inherent in this measurement. When both sides of a slice are examined it is usually found that the damage levels are different, and that the slice is bowed. It is important to distinguish between transient and permanent bow. The surface damage in a silicon slice can be pictured as an abrasion by surface cracking along the weaker bonded (111) planes, with the stress caused by the wedging open of microcracks by abraded debris. The annealing of an abrasion scratch at 1100"C for 30 min, examined by interference contrast microscopy in Fig. 1-21 a, reveals the (111) slip lines, while the topograph in Fig. 1-21 b shows the stress relief by plastic flow, creating an array of long dislocation loops on slip planes on either side of the scratch. Thus, in the presence of differential damage between two surfaces a slice bows - hollow on the least damaged side. If the bow, B, measured as the maximum depth of the hollowed side of the slice, diameter d, is taken to have a uniform radius of curvature, r = d2/(8B), then the relation between bow and strain (Tamura and Sunami, 1972), is given by c=--

16tSiB 3 d2

1.6 Slice Fabrication

Figure 1-21. Surface damage in silicon. Annealing of an abrasion scratch in a { 11 I } orientation polished slice (1100°C for 30 min). (a) Interference contrast microscopy revealing slip relief along { 111) planes. (b)X-ray topograph showing the stress relief by plastic flow, creating a network of long dislocation loops on j l l l } slip planes on either side of the original scratch.

39

At temperatures below around 500 "C elastic deformation leads to brittle fracture as E > 5 x lo3, at a stress in the silicon > lo9N m-'. At higher temperatures, the elastic bending gives way to plastic deformation as the stress is applied, shown in the plot of Fig. 1-22. Since both silicon and germanium are hard brittle elements of the diamond cubic lattice structure, from the outset of the semiconductor industry diamond sawing has remained the prime route to slicing ingot material. Initially the sawblades were steel discs, slotted around the periphery, into which diamond grit particles were pressed. Such saw discs when rotated at high speed around 1500-2000 rpm, with water as a coolant, cut both germanium and silicon well. However, to cut thin slices accurately such blades have to be thicker than the wanted slices, and this is obviously very wasteful of the crystal material. As a result, these peripheral blades were rapidly superseded by internal diameter blades. Thin high tensile rolled steel sheet is punched out into large discs with a central hole around which a band of diamond of closely controlled particle size is electroplated. This blade is clamped into a mounting frame which is stretched over an outer ring in high tension, sufficient to enlarge the central diamond saw hole to-

1500

+ rn L W

a

Elastic d e f o r m a t i o n

01

I

lo7

I

1

1

1

1

I

I

I

I

I

1o8 Yield s t r e s s

(Nm-*)

OhP

d

Figure 1-22. Deformation and fracture of silicon resulting from mechanical stress. Note: For silicon Y/(1 - P ) = 1.8 x 10" (N rn-'). and so, approximately, thc stress/strain ratio is 2 x 10" ( Y :Young's modulus, P: Poisson's ratio). Hencc for cxample at a stress of lo8 N m-' the corresponding strain is 5 x

40

1 Silicon Processing

wards its elastic limit, so providing a thin but extremely rigid blade, capable of very precise slicing with minimum kerf loss of material. Very considerable effort has gone into the development of the internal diameter sawing machines and blades to meet the continuing scaling up of slice diameters. When an internal diameter diamond blade, stretched in tension over an outer ring and rotating at high speed, is driven forward into silicon to saw a slice, the tension is slightly relaxed and the blade vibrates (wobbles) slightly. The ingot on one side of the kerf slot is rigid, whereas the partially cut slice on the other side of the sawblade can relax a little. As the blade edge vibrates, the diamond on its sides impacts against the ingot and slice, causing differential damage, where, on the next cut, the newly exposed ingot surface becomes the other side of the next slice. Such slices may be cut perfectly uniform in thickness but bowed, until they are etched to remove the damage before polishing, when they relax to a very low bow value. On the other hand, if a blade is mounted and run incorrectly, so that it deflects during slicing, no amount of subsequent etching can correct the ensuing permanent bow. The forces which are generated at the blade edge during sawing can be followed by mounting the ingot on a dynamometer attached to an x --y - z - t chart recorder. The forces F,, Fy,and F,, measured simultaneously as the blade traverses the full diameter of the ingot, are related to the operating conditions. Typical results, looking at variable cutting rates, are shown in Fig. 1-23. Here F, is the direct loading force between the advancing ingot and blade, Fy is the tangential, dragging, force along the blade periphery, and F, is the smaller, but very important, vibrational force perpendicular to the blade. At a low feed rate the

saw is only in gentle contact with the silicon and free to vibrate; then, as the feed rate is increased towards its optimum, the blade is held more firmly and vibration decreases. . . and on the slices sawn so does the bow. Finally, as the feed rate is set too high, the pressure between the ingot and the blade begins to relax the blade tension, F, starts to rise again and the bow becomes severe. Taken further, beyond its stress limit, the blade ruptures. The role of the cutting fluid, “lubricant”, can also be studied. As an example: at such high rotation rates, around 2000 rpm, centripetal forces rapidly remove the cutting fluid from the blade edge, and the liquid film whose thickness should provide a cushion against F, is very thin. The long chain molecule polyethylene glycol both improves the streamline flow of high speed liquids and increases their viscosity, so maintaining a thicker film. Applied to silicon slicing under otherwise optimum feed conditions, the F, is halved, and the bow reduced even more. Today it is recognized that the slicing quality, which is hardly ever seen by device customers, is the key to performance, yield, and rework, in all the following polished slice manufacturing steps, and has a major impact on the overall production costs. Vendors internal sawn slice specifications always have tight tolerances on flatness, bow, and mean thickness distribution. Grinding is used at three stages in the progress of a slice into devices. Near the end of fabrication, prior to assembly, slices are back-ground substantially to reduce their thickness. In the process the slices move sideways under a spinning diamond loaded cup grinder, where the loading conditions are somewhat akin to sawing, in that material is removed parallel to the surface, and the perpendicular damaging forces into the slice are kept low. In fact,

1.6 Slice Fabrication

41

-

5-

I

m

.c_

31 2

. I =

+ u

; 1 W

L c

m

O

3-

8-1 c W ._ - -2 L

c W

5u - 3

-;"-&I W

t 01

1

1

n I

1

1

Jo

vr

-5-

-3

3 4 5 Saw feed r a t e (cm min-') 2

(a)

-2

-1

0

1

2

3

Saw blade deflection (pml

(b)

Figure 1-23. Damage during silicon slicing. In (a) the force measurements and bow were recorded using distilled water as the cutting fluid ( 0 Fx, x F,,, + F,. o bow). The effect of replacing this by a 1YOsolution of polyethylene glycol (6000 mol wt.) is seen in a force F, (A) of 0.04 N, and a bow ( 0 ) of under 10 pm. Subsequently in (bf it is necessary t o etch the sawn slices to reveal the true distortion associated with blade deflection. + marks the zero bow, zero saw blade deflection intersection of the two axes.

the output surfaces, which will meet no further high temperature processing, have a semiglazed finish. Moving back into wafer manufacture, after sawing, the slices are edge-rounded to avoid the chipping which in automatic handlers leads to particle problems in clean lines. For this a spinning diamond loaded wheel is used, shaped to the desired edge profile, against which the silicon slice is itself slowly rotated. Before this, the first grinding stage the silicon meets is that of grinding the as-grown crystal into a cylindrical rod, prior to slicing. Again, the spinning diamond wheel traverses along the ingot, minimizing the forces into the silicon. Both of these stages introduce damage around the periphery, which has to be removed by etching. During later device processing the slice meets several high-temperature stages in which, if residual peripheral damage is still present, the heating and cooling gradients will lead to slip, and yield losses. This is

shown in Fig. 1-24. Here the transistor printout marking of rejects on-slice at Test1 , matches the slip, revealed by etching the back of a slice, which had been inadequately etched after grinding. After ingot

l a)

lbi

Figure 1-24. Device failures from slice fabrication. The Test-1 printout on-slice of UHF transistor rejects in (a) is linked directly to the process induced crystallographic defects revealed by selectively etching the reverse back face, seen in (b). Note the high incidence of failures initiated from the periphery, particularly near to the reference flat, contributed to by insuffcient ingot etching after grinding.

42

1 Silicon Processing

grinding, slicing, and edge-rounding, it is normal to etch off around 40 pm from the surface (80 pm thickness; 80 pm diameter), before going on to the polishing stage. For the back surface of the slice this etching defines the final finish, normally specified damage-free, unless some extrinsic gettering is required (see later). Its texture may be defined as “polished”, or “semi-matt” to customer choice. Various etches are used for this purpose. Lapping is a very different issue. While it is used after slicing to provide slices of the close thickness uniformity necessary to proceed on to etching and polishing, to remove any saw marks, and to improve the planarity and parallelism, fundamentally it is a retrograde process. The abrasive pressure is directed directly into the silicon surface. Under very low load, in hand lapping, the depth of damage generated is proportional to, but somewhat greater than the abrasive particle size (Buck and McKim, 1956).When the pressure is increased, as is necessary to achieve useful stock removal rates from commercial lapping machines, both the depth of damage, and the site density, rise steeply - under normal operating conditions to at least 3-4 times particle size. For example using a 20 pm, close particle size distribution, water classified alumina, WCA, at a load of 30g/cm2, the damage extends to a depth of around 90 pm - worse than in the original sawn slice. Where lapping is part of the slice machining, deep etching is needed subsequently to remove the subsurface structural damage it has caused. The issue of residual mechanical damage and flatness requirements in the large slices, of diameter 200 mm and above, required for the latest ULSI microprocessor and memory chip applications has focused attention on the lapping process and possible alternatives. The new standards of flat-

ness in the final polished wafers are now measured in nanometers (1 nm = m = 10A). This is needed because, in the fabrication of ULST circuits, the lithography uses submicrometer dimensions, with minimum feature sizes currently around 0.5 pm but decreasing and expected to be down to 0.15-0.2 pm before the century’s end. Associated with these dimensions, the thickness of gate oxides is now already down in the region of 200-100A, with close tolerances of k a few angstroms, and is also decreasing. Thus the underlying substrate surface has to be polished to commensurate values, with overall flatness within some tens of nanometers. Again, in processing these large diameter slices through the furnacing stages, thermal stress is a serious issue, pointing to the need for even greater attention to the effects of residual mechanical-damage-related defects (Wanatabe, 1991). This reference includes tables of current, and prognosed, specifications for ULSI wafers, and a useful glossary defining measurement terms, such as TTR. The back grinding of fabricated slices under a spinning diamond loaded cup grinder described above produces very flat surfaces, and as explained, since it removes material by a sideways motion there is very little damage driven into the wafer, compared to that generated by lapping. As an alternative to lapping, this process looks increasingly attractive, and new nanogrinders have been developed. These are built very rigidly to minimize vibration and maintain very low surface roughness and damage, while the feed mechanism can index in nanometer steps, starting off coarser but ending with very small increments. Sawn slices when nanoground on both sides exhibit a very high degree of parallelism and flatness. The subsurface

1.6 Slice Fabrication

crystal structural damage is also shallow in depth, facilitating the subsequent etching and polishing stages. In order to assess the final surfaces of ULSI wafers, matching advances in the metrology apparatus now permit measurements at nanometer levels for production control, and these show that the nanoground material, with a near mirrorlike finish, can be flat overall across a 200 mm diameter to TIR values well under 100 nm. Comparing this to earlier previous standards, e.g. for 100 mm diameter wafers TIR values in the 1-3 pm range were common, the high standards now required can be appreciated. In reply to this challenge there have also been some advances in lapping techniques, with more attention being paid to abrasive quality in the particle shape and size distribution, operating process pressure and procedures, and in the construction of lapping machinery aimed to give flatter output. The economic cost differences between these contrasting processes have also to be taken into account in this highly competitive field. However, as tolerances continue to get tighter with respect to both metrology and damage levels, and as diameters further increase, nanogrinding is seen as a significant advance. Finally is should be noted that in research another new technique, atomic force microscopy, is being applied to the study of silicon surfaces at the nanometer level. Overall, mechanical damage in silicon is a serious issue, and closely linked to the material performance during device manufacture.

1.6.2 Polishing and Cleaning These will only be covered in outline since, although very important, much is concerned with practice and choice of materials, rather than underlying semicon-

43

ductor science. Silicon is a very hard, diamond type, element, but extremely chemically reactive, and is always covered by a native oxide, normally around 2 0 A in thickness. The materials used to polish it are all much softer, and the process employed is chemical-mechanical in nature, operating across the native oxide (Walsh and Hertzog, 1963), the Monsanto Syton patent. In principle therefore, while silicon is removed, there is little or no lattice damage generated. A three stage process is common. In the first stage an alkaline colloidal silica slurry is used with a fairly hard but porous bed pad. The silicon slices are mounted in groups on rigid very flat discs, generally by wax-mounting, but sometimes by a waxless process (against backing pads whose micropores act as vacuum suction points). These discs, which are driven in rotation themselves, are pressed into contact with the rotating bed pad, fed with the slurry, where fast stock removal occurs, around 1.O pm/min at SO- 60 “C. The temperature, monitored on the bed plate surface, is controlled to stay within close limits, initially by heating, but then later, as the process itself generates heat, by applying cooling to the bed and slice mounting plates. The pressure removes oxide from higher points on the slices, while the hot alkaline slurry dissolves the freshly formed, and chemically reactive, oxide- hydrated silicate film, generated by the reaction between the silicon and the high-pH slurry solution. About 20-25 pm may be removed at this stage, resulting in a surface having a highly polished appearance, free of all residual “orange peel” from the etched surface, haziness, and scratches. After being rinsed in deionized water, the mounted slices are transferred to a second similar polishing machine, which has a

44

1 Silicon Processing

softer bed pad, uses a gentler slurry of near neutral pH, and operates at lower pressure and around room temperature. After a somewhat shorter second polishing period, around 10 min, only a small extra amount of silicon is removed (1 -2 pm), but this delivers the final defect-free surface. In the third stage on the same machine, pressure is relieved so that the slices are almost free floating and the second stage slurry is replaced by a “haze supressant”, a complex organo-silicate, diluted in a glycol-water medium, which contributes to hydrophobicity, and clean liquid drainage from the slice surfaces, leaving no marks as they are removed at the end of the process. The fine tuning of the polishing process, to reach the very high standards demanded, involves considerably more variables and detail than given in this outline. This chemical-mechanical polishing combines both the mechanical process necessary to achieve flatness to micrometer tolerances, and a chemical process to ensure a final crystallographic perfection with undisrupted atomic structure free of all damage. The final cleaning and packaging are similar to polishing in their emphasis on the materials used and the practice. Again in outline, the first step after polishing is to remove any traces of polishing slurries, waxes, and organics by means of degreasants, and/or organic destruct routes, using, for example, hot nitric acid, followed by washing in deionized (DI) water. The emphasis in the final clean is on the removal of every trace of surface contaminants, metals, etc., and particles of whatever form. Kern and Puotinen (1970) first described the, subsequently widely used, RCA cleaning process. All the chemicals employed have to be of electronic grade, and membrane filtered to very low submicrometer particle counts, as is the DI water. Much

depends on the performance of soft-pad slice scrubbers, and single slice spinners, operating in a cassette-to-cassette mode, while robotics are finding increasing use, in Class 10, and lower, clean surroundings. In routes where hydrophobic slices are required, an HF dip is inserted, but where the, more normal, hydrophilic surface is wanted, the ammonia-peroxide treatment has become common, before the final DI water scrub-rinse-spin-dry schedule. Cassette packaging in multicomponent ultraclean boxes completes the wafer processing. The impact of ULSI requirements on these stages has been as demanding as elsewhere. At the polishing stage much attention has been paid to the machine bed construction to ensure that slices do not have their flatness degraded during the process. Then the process itself has been modified, essentially with the aim of reducing the temperatures and pressures used at all stages to achieve gentler processing. Pads and slurries have been improved; now instead of feeding slurry onto the machine in small quantities, flooding from a recirculating tank is used to ensure that adequate compound reaches the central area of large diameter slices. The comments on cleanliness given above are reinforced, and even more attention has been given to assay methods to test for impurities in chemicals to ultralow levels of detection in order to meet the very low surface metal ULSI targets of below lo9 atoms/cm2.

1.7 Oxygen in Czochralski Silicon 1.7.1 The Behavior of Oxygen in Silicon The dissolution, evaporation, and fluid flow, dynamic balance, controlling the incorporation of oxygen into silicon described in Secs. 1.5.3 and 1.5.4, above ig-

1.7 O x y g e n in Czochralski Silicon

nored its distribution coefficient. Under such growth conditions this is not easy to determine, and past estimates have varied widely, from ko = 0.5 to 1.4. Current views that it is less than 1.0 are supported by a recent study (Jackson, 1990),which arrived at 0.7. While carbon enters the lattice as a substitutional impurity occupying a silicon site, oxygen does not, but instead enters as a bound interstitial impurity, bonding between two adjacent silicon atoms, in a structure which permits more complex vibrational modes (Newman, 1973). The broad 9 pm infrared absorption band, seen at room temperature, arises from a number of vibrational modes of similar energies. The concentration of bound-interstitial oxygen in silicon is measured by the 9 pm

45

absorption (ASTM Standard F-121), and if any oxygen is precipitated within the crystal, by heating in the range 1050-600°C, the absorption decreases. Reheating at a high temperature, > 1100"C, disperses the precipitates and restores the absorption. However, if the temperature is held at around 450 "C, any unprecipitated interstitial oxygen present forms "thermal donors", which cause major resistivity changes in the crystal. This thermal behavior pattern was first established by Kaiser et al. (1956) and then expanded (Kaiser, 1957; Kaiser et al., 1958). Long Czochralski crystals, which are grown over a period of many hours, slowly withdrawing into a cooler chamber, experience a different thermal history between the seed and tail ends, depicted in Fig. 1-25. Heat losses:

Conduction along c r y s t a l and convective t r a n s f e r from surface t o gas

.,oooc

fi

-

Heterogeneous and homogeneous nucleation

Precipitate g r o w t h

Carbon via

900°C/ Oxide precipitation 1000oc

on nuclei-C, or condensing i n t e r s t i t i a l s

/ /

High temperature radiation

f a u l t defects high Si i n t e r s t i t i a l concentration

and convection Oxygen dissolution into melt a t wall

Figure 1-25. The variable thermal history of an as-grown Czochralski silicon crystal.

46

1 Silicon Processing

This has direct device effects; for example, a difference in leakage current yield losses of 16 k DRAM chips has been linked to the slice cutting location, reported by Steinbeck (1980 a, b). Other studies have shown device failures associated with crystal defects, either present at the start of the fabrication process or formed during it, and also linked to the oxygen status. From defect etching studies, many observers noted that where a high density of surface defect features (e.g., oxidation induced stacking faults, seen after the first furnace step) was found on one side of a slice, the opposite face had a very low density. In one direction, this was soon linked to residual damage remaining after slice polishing. Similar work demonstrated the relation between oxidation-induced stacking faults, the slice heat treatment temperature, and oxygen precipitation (Matsushita, 1982). Much device engineering research has explored the generation and supression of oxidation-induced stacking faults during fabrication (Stimmel, 1986), but to work bulk silicon it is necessary to understand the basic precipitation mechanism.

1.7.2 The Precipitation of Oxygen in Silicon The maximum amount of oxygen grown into a crystal at its top (seed) end, is such that, as it cools below about 12OO0C,the concentration exceeds the solid solubility limit (Carlberg, 1986), and precipitation of a second, silicon oxide, phase may be expected at any lower temperature. Solid state reactions proceed at far slower rates than in liquids or gases, so as the crystal cools, over many hours, the amount of the supersaturated oxygen which actually precipitates is so small as to be almost indetectable. It is only on heating slices cut

from the crystal, for many hours at elevated temperatures, that substantial precipitation occurs, growing from tiny initial nuclei. Research into bulk crystallization from liquids, to produce, for example, fertilizers and salts, has contributed much to nucleation concepts, and in particular the particle of critical radius r , . In a supersaturated liquid, or solid, at the outset tiny atomic clusters form and redisperse in a highly dynamic situation, but some merge and grow, until, reaching a certain critical radius, they become stable, and from then on will not redissolve. In such a process there is an initial induction period during which sufficient nuclei reach r,, then faster precipitation, which dies away as the equilibrium solubility is approached. Many systems exhibit this behavior, including the solid state precipitation of oxygen in silicon, where at 750 "C, the process has still not reached equilibrium after over 1000 h - solid state reactions are very slow. In this approach it should be expected that the nuclei formed by other impurities present will affect the initial nucleation induction step. Thus in the silicon case, the distribution of oxide precipitates across a slice after heat treatment closely maps the grown in carbon distribution shown in Fig. 1-11 (Wilkes, 1983), and also influences the actual precipitation kinetics (Kishino et al., 1979; Craven, 1981; Shimura et al., 1985; Barraclough and Wilkes, 1986). After nucleation, the main precipitation process reduces the bound interstitial oxygen concentration, developing different numbers and sizes of particles according to the temperature employed. A simple model can be used to predict the qualitative behavior correctly, and provides a basis for understanding the theoretical approach. Suppose two similar, adjacent, samples of the same impurity content, and with the

47

1.7 Oxygen in Czochralski Silicon

same high background nucleation site density, are annealed for a long time, but at different temperatures in the supersaturation range. (1) In the sample heated at the high temperature the supersaturation driving force for precipitation is low, whereas the diffusion rate of oxygen through the silicon is high. Once a few particles exceed the critical radius, rapid precipitation reduces the oxygen concentration, leading to the formation of a low density of large particles, making use of only a few of the available nucleation sites. (2) Conversely, in the sample heated at a low temperature, by the same reasoning, the supersaturation is high, but now the diffusion is low. The second phase must precipitate, but, since the oxygen only moves slowly and through a short range, a high density of small particles is predicted, making use of many of the available sites.

This is exactly what happens in practice, and if the substitional carbon signal is followed (linked to the nucleation), in the high temperature case it stays unchanged, but in the low temperature case disappears rapidly. There is an important further consequence: (3) Since the native oxide film on the surface of the silicon sample is effectively a particle of infinite radius, present at time zero, and needing no induction period, the supersaturation-diffusion model provides a simple and obvious explanation for the existance, close to the surface, of denuded zones, free of any precipitation. From the start of the heating process, oxygen close to the surface can diffuse out into the native oxide layer, so reducing its concentra-

tion and inhibiting precipitate formation in this region. The depth of this denuded zone is expected to be of a similar magnitude to the distance between particles in the bulk - deeper when formed at a higher temperature, but very shallow from a low temperature anneal. Again this is as observed in practice. In a quantitative approach, the mathematics of diffusion-limited precipitation (Ham, 1958) have been applied to the case of oxygen in silicon. The starting concentration of bound interstitial oxygen, C,, is assumed to be uniform. After a short induction period small precipitates are formed, whose density, N , remains constant throughout the remainder of the process. The particles are assumed to grow by diffusion with a spherical shape, and a common radius, ro ( t ) , small compared to the interparticle distance, and taken to be a constant corresponding to the final value r o , at t +a.The particle are a form of silica containing oxygen at a concentration C,, while that in the matrix close to the particle is C,, , the equilibrium solid solubility at the termperature chosen. The Wigner - Seitz approximation replaces the cubic cells around each particle, accounting for the total volume, by equivalent spheres of radius R , defined by (4/3)7t R 3 N = 1. The oxygen concentration profile as a function of position, and time, C (r, t ) can be represented by a Fourier series: C ( r , t )= c,, +

. exp

c 4 sin [An(r r

(- :.>

-

ro)]

n=O

(1-7)

satisfying the boundary conditions C = C,, at r = r o , and where z, is the relaxation time constant.

48

1 Silicon Processing

Fick's diffusion equation in spherical coordinates may be written

a2c(r,t ) +-2 ac (r, t ) ] -aC (r, t ) ar2

r

ar

at

(1-8)

while the requirement that there be no net o x y d flux across the outer sphere boundary is defined by

The oxygen distribution so described is essentially uniform, with a value slightly less than C,, throughout the diffusion volume, except in a small region of radius about 5 r,, around the particle, in what may be described as a random-walk-well model, as shown in Fig. 1-26. Further manipulation of the equations leads to two important expressions: 113

(1-14) Differentiating Eq. (1-7) with respect to r and t and substituting into Eq. (1-8) leads to the core expression given by Ham: tan [An(r-ro)] = A, r , r

=R

(1-10)

In this result A, has the dimensions of inverse length, and can take an infinite number of discrete positive values, which are the required solutions. Expanding this in a power series for small values of the argument gives 1

(1-11)

7, = __

A,zD

and 7, =

R3 3Dr,

(1-12)

~

If a particle does not nucleate, ro = 0; there is no oxygen diffusion, and the supersaturation is maintained indefinitely. Normally, after an initial transient, the first term of the Fourier series in Eq. (1-7) dominates when C(r,t) - C,, z A , A,

. exp

(-);

( - 3. 1

-

(1-13)

The constant A , 1, has the dimensions of concentration and a value somewhat less than C, - C,, .

and

If it is reasonably assumed that the oxide is close to SiO, in its composition, then a value can be assigned to C,. The values of C,, C,, , and the relaxation time constant, zo, are obtained from the infrared absorption measurements used to follow the precipitation process (Binns et al., 1983; Newman et al., 1983a; Wilkes, 1983). Hence, values for the particle density, N , and its radius, r, can be obtained at various annealing temperatures, based soZeZy on kinetic data. This can then be compared with direct measurements obtained from integrational etch pit counts, and scattering. By near infrared transmission the optical scattering from the large particles formed by high temperature anneals can be used to calculate N and r. Similarly, the very small particles, with radii less than 100 I$, can be measured by small angle neutron scattering (SANS) to validate the theoretical model (Livingston et al., 1984), as shown in Fig. 1-27. The analysis of SANS results also provides information about the shape of the particles, which has recently been allied to high resolution transmission electron microscopy, to reveal platelet precipitates, shown in Fig. 1-28 (Bergholtz et al., 1989).

49

1.7 Oxygen in Czochralski Silicon

Temperature 1100 1000 900

lo' 7.0

8.0

800

9.0

700

10.0

11.0

10L/T I K - ' )

Figure 1-26. The random-walk-well model of diffusion limited precipitation.

Only within a region of about 5 x the particle radius does a diffusing oxygen atom become trapped to a particular site and the number of particles formed is strictly defined.

Figure 1-27. Oxygen precipitation in silicon. The particle radii, and their corresponding number densities, based on the four methods shown, all assume spherical geometry. However, in the random walkwell theory the particle shape does not significantly affect the overall data given. The symbols are: o radius derived from kinetics, n radius from etch pit measurements, x radius from neutron scattering, + radius from optical scattering.

The total assembly of particle radii from these various techniques, plotted against reciprocal temperature in Fig. 1-27, shows a remarkable coherence of results, in spite of the different nature of the experimental methods and approximations involved, and the diffusion-limited precipitation theory underpins the qualitative model set out earlier.

1.7.3 Thermal Donors and Enhanced Diffusion The problems surrounding the understanding of thermal donors, their formation, and behavior, are aggravated by the lower temperatures involved, 350- 500 "C, in any kinetic study, and by the complexity

Figure 1-28. Direct lattice image of a platelike oxide precipitate in silicon. Finlike features extend above, and probably below, the main (100) habit plane. Sample annealed at 750°C for 431 h.

50

1 Silicon Processing

of their structure, where work suggests that four interstitial oxygen atoms are involved in a TD center (Newman and Claybourn, 1988). Following the oxygen precipitation kinetics at low temperatures requires a more sensitive method than infrared absorption; this is provided by the technique of the relaxation of stress induced dichroism (Corbett and Watkins, 1961), which has been applied to the silicon-oxygen system (Benton et al., 1983; Newman et al., 1983b). In this procedure, a small silicon rod sample, cut with a [ l l 11 axis, is heated at a temperature of 450- 500 "C, under a high pressure applied along the axis; subsequently the sample is cooled while still under stress. As a result of diffusion while stressed, the number of bound interstitial oxygen atoms, n , , linking matrix silicon sites in the [ l l l ] axial bonds becomes less than the number, n 2 , in each of the bonds in the [TIT], [Till, and [lTT], directions. If now linearly polarized 9 pm infrared light is used to measure the oxygen absorption coefficient, in directions parallel and perpendicular to the stressed [ l l l ] axis in the samples, the following relations apply:

from which (a, - c l , , ) = const . (nz- n,)

(1- 7)

When such a prepared test sample is then annealed at some chosen temperature but under no load, further diffusion allows the oxygen to return towards a random distribution, relaxing the induced stress dichroism, by a first order kinetic process, with a relaxation time constant L. Using a normalized dimensionless parameter (aI- all)/ai the constant tt is given by the slope d [log (a, - all)/a,]/dt, and is equal to t/8 where l/t is the fundamental fre-

quency of a single diffusion jump at the temperature concerned. The diffusion coefficient then follows from the simple relationship that D = a;/@ z), where a, = 5.42& the lattice constant of silicon. An early problem in the understanding of thermal donors arose from their speed of formation, requiring only a short heating time to reach an equilibrium resistivity. The role of lattice defects in this process is now recognized to be a major contributor. In their stress dichroism study, Benton et al. (1983) observed that, if the silicon was given a 900"C/2 h heat treatment followed by quick cooling to eliminate donors (but thereby freezing in excess silicon self-interstitials) before going into the stress dichroism procedure as described above, the value of the diffusion coefficient, D, was enhanced by nearly two orders of magnitude. Another way to alter the intrinsic defect balance in silicon is by irradiation. Newman et al. (1983 b) used 2 MeV electrons onto a stressed silicon sample target held on a water-cooled block at well below 60°C. After irradiation the 9 pm signal was lowered, while the generation of oxygenvacancy (0-V) A-centers was measured by their infrared absorption at 830 cm-'. On subsequent relaxation, the induced dichroism now decayed exponentially - with D several orders higher. Oxygen can also trap mobile silicon self-interstitials, to form an (0-1) center, with absorption at 935 cm-l. Tin is an efficient trap for vacancies in silicon; as-grown Sn-doped crystals have similar (0-1) center concentrations to undoped silicon, but substantially lower (0- V) A-center levels, and in this material the relaxation of stress dichroism is retarded by a factor of approximately 6. Involvement of both vacancies and interstitials in this diffusion was proposed by Gosele and Tan (1983). A simplistic view of a single jump could be that either oxygen

1.8 Crystal Engineering

traps a vacancy to form an A-center, which then intersects a self-interstitial, or, alternatively, an (0-1) center is formed, which then traps a vacancy. The reality is more complex than this. Enhanced diffusion is seen after metallic contamination by copper or iron. Carbon enters into a number of low temperature centers with oxygen and silicon, and as nucleation sites for self-interstitials (Davies, 1989). Free electron effects have been used to provide an explanation for dopant concentration-dependent thermal donor kinetics (Wada, 1984; Wada and Inoue, 1986); while in the precipitation of oxygen in heavily doped, n f and p’, silicon, Bains et al. (1990) have observed both enhanced (p’) and retarded (n’) precipitation, which they also link to the free electron model. Finally the thermal donor formation in p-type, 0.3 0 cm, material at 450°C is accompanied by the simultaneous loss of substitutional boron (Newman and Claybourn, 1988). Overall, while the diffusionlimited precipitation model provides a sound basis for understanding the behavior of oxygen in dislocation-free silicon, which is applied in the “crystal engineering” discussed next, there is still much to be learned about the detailed mechanism of enhanced diffusion and thermal donors.

1.8 Crystal Engineering In the preceding sections of this chapter, reference has been made at various points to the ability of defects to act as gettering sites, sinks, for fast diffusing impurities. Also the serious deleterious effects of such defects, where they intersect device structures, has been emphasized. In addition the very slow nature of solid-state oxygen precipitation, seen above, has to be overcome if any use is to be made of such bulk precip-

51

itates. The controlled application of external surface mechanical damage (extrinsic gettering), and internal bulk oxide particles (intrinsic gettering) is now addressed.

1.8.1 Extrinsic Gettering in Silicon Mechanical damage in a silicon surface has to be quantified in both density and depth, where as seen in Figs. 1-19 and 1-20, only a few damage sites extend to any great depth. Since etch rates are a function of the intensity of damage, they fall rapidly during the initial stages of etching, so it is very difficult to leave a well-controlled residual damage level on the back side and achieve the required slice thickness tolerances by trying to limit the etching. This also leaves more to be polished off the front surface. What is required is to create intentionally a high density of relatively shallow lattice disorder, whose associated stress relaxes into stacking faults and dislocation loops early on in the device thermal processing, to provide a high gettering capacity. The lattice distortion around the dislocations sets up strained regions, the actual gettering sites, which, in accommodating the diffusing impurities, relax further into stable lower energy atomic configurations. There are several controlled backside damage options available from polished slice suppliers, aimed to match the individual device processes: MOS, bipolar, etc. The damage is reinserted starting from well-etched slices. One method, widely used, employs a high adjustable- pressure water jet system, commonly used at around 1000 psi ( z 70 bar), which contains fine ground silica of well-defined particle size (about 1 pm). The grades of damage generated by the impingement of this jet on slices traversed beneath are achieved by varying the pressure, number of jets, and the traverse speed. Afterwards the front surface is polished in the normal way.

52

1 Silicon Processing

Typical site densities obtained by this treatment range between 5 x lo3 cmP2and 5 x lo7 cmP2.An example of a higher damage level slice, before and after treatment, is shown in Fig. 1-29, while the rocking curve broadening from this process is low to moderate: A W = 10’ to 30’. (Note other values: deep-etched slice 0” to 4/8“, sawn slice 80” to loo’, lapped slice A W > 120”.) Lighter damage is most suitable for MOS device processes when, during the first oxidation at around 1000- 1100“C, stacking fault gettering sites are formed on the treated back surface at a density of around lo5 cmP2, which has a negligible effect on the subsequent mechanical behavior, warp, etc. However, as device feature sizes continue to shrink, there is strong emphasis on reducing both the maximum temperatures, and the total thermal inventory, used in fabrication. At temperatures below 1000°C the stacking fault generation is more complex and influenced by the oxidation ambient (Claeys et al., 1981).Again, if the damage is too light, instead of forming getter sites on heating, a large proportion may be an-

Figure 1-29. Extrinsic gettering by silica-high pressure water jet trcatmcnt. Note the well-etched surface to remove uncontrolled damage prior to treatment, and the uniformity of mechanical damage sites generated (SEM photograph).

nealed out. This is seen when first stage polished surfaces, with some submicrometer damage, are compared by etching to reveal defects before and after an 1100 “C thermal cycle, when most of the damage sites disappear, and too low a stacking fault density results. The gettering performance, extrinsic or intrinsic, is monitored by etching the front polished surface, in which the device structures are fabricated, to reveal point defect sites: S-pits - shallow saucer etch pits, or haze, which are known to be related to the presence of heavy metal impurities, to low carrier lifetimes, and to emitter-collector leakage, which are all detrimental to yields. Again where the device process involves a number of high temperature stages, the extrinsic gettering performance gradually falls, and a higher initial damage level is necessary to counter this. For bipolar applications the same rules stand, but now the process employs higher temperatures, up to 1200”C, where shallow damage sites are more easily annealed out, and gettering performance falls more rapidly through the successive high-temperature stages. While damage depths around 1- 1.5 pm may be adequate in an MOS process, bipolar conditions can demand 2-4 pm, and even then the efficiency may be lower. Alternative approaches for inserting the mechanical back-surface damage, also widely used, are brush damage, or abrasive polishing, of the deep-etched slice, an example of which is seen in Fig. 1-30. By choice of materials and operating conditions (soft or hard brush, abrasive size, pressure, etc.) well-controlled products result, suitable for both MOS and bipolar applications. Finally, in a further development of extrinsic gettering, it has been recognized that fine grain polycrystalline silicon is an excellent, high temperature

1.8 Crystal Engineering

53

resistant, gettering material. Using low pressure chemical vapor deposition (LPCVD) and a silane source, in a process closely similar to that employed during the fabrication of polysilicon interconnects, a thin, 1-2 pm, layer is deposited on the deep-etched slices, at a temperature of 600-650 "C, prior to the polishing stage, which becomes the extrinsic gettering backside of the slice. Known as enhanced gettering (EG) this additional step is obviously rather more expensive to manufacture than the other routes described for providing extrinsic gettering, but its performance, particularly in the multistage higher temperature applications, such as in bipolar circuits, is superior, maintaining very low S-pit densities, and high lifetimes, as shown in Fig. 1-31. Achieving the best results in this field involves very close liaison between the slice manufacturer and the consumer device engineer, in order to match the incoming material to the specific fabrication process.

Number of oxidation cycles

(b) Figure 1-30. Extrinsic gettering by abrasive (brush)

treatment: (a) and (b) show lower and higher damage, respectively. Note the well-etched underlying substrates.

Figure 1-31. Enhanced gettering by deposited polysilicon. Comparison between EG and mechanical backside damage (MBD) treatments. Material: Medium oxygen content, p-type, (100) orientation. Test: bipolar oxidation cycle - 1I O O T , steam, 2 h. Spits: x ; lifetime: 0 .

54

1 Silicon Processing

1.8.2 Intrinsic Gettering in Silicon The beneficial effects of oxygen precipitates in the bulk of a device structure, and also in the substrate of an epitaxial slice, were reported by Tan et al. (1977)and Yang et al. (1978). Now there are many papers on this topic, which, since it directly interfaces to device processing, has attracted much attention. The single stage heat treatments described in Sec. 1.7.2 are obviously far too slow to provide crystal-engineered slices tailored to meet device specifications. However, this is not the only constraint. Any useful process must make consistent intrinsically gettered slices using input silicon slices containing the varying amounts of oxygen typical of normal Czochralski growth. If insufficient of this oxygen is precipitated, there is a serious likelihood of further secondary precipitation in the vicinity of devices at some point during fabrication. Earlier work concentrated on two-step processes, with a first high temperature heat treatment, followed by a second at a lower temperature, the so-called HI - LO, treatment. Typical times and temperatures used are: 16 h a t 1150°C and 64 h a t 650°C (Yamamoto et al., 1980). While other variants of two-step treatments have been proposed, this HI -LO process shows the principles, using the models developed in Sec. 1.7.2 above. In the first step, the high temperature, 1150 "C, anneal is in a range where the supersaturation of bound interstitial oxygen is relatively low but diffusion high; any preexisting microprecipitates near the surface tend to dissolve. Oxygen readily diffuses to the surface oxide, so developing a concentration gradient near the surface, while deeper in the bulk, precipitates start to form.

In addition to conventional analysis methods, for example, by a SIMS profile on a cut section through the slice, the concentration gradient from the out-diffusion can also be measured by reheating the sample at 450"C, to generate thermal donors from the remaining interstitial oxygen, and then making a microresistivity scan on a beveled section, to calculate the gradient profile. The results from material with a bulk value [Oil around 8 x IOl7 cm-2 show the surface concentration falling to around 5 x 1017 after 6 h, with a precipitate denuded zone 20pm deep, while after 16 h the values are around 3-4x 1017 with a denuded zone up to 50 pm deep. While the interstitial oxygen content is lowered at step 1, in the following low temperature step 2 at 650°C the supersatura'tion is still high and precipitate growth continues at the sites formed at step 1 but there is little added fresh bulk nucleation. The desired intrinsic gettering structure, bulk precipitates and a surface denuded zone, is achieved - but there are problems. The amount of bound interstitial oxygen precipitated by this process, and whether or not a denuded zone is formed, are a direct function of the original oxygen content, as shown in Fig. 1-32. In addition, in this plot the wider scatter of results from material of lower initial oxygen content reflects the effects of other contributory factors. For example, in the influence of carbon on nucleation, where using material of normal high oxygen content but ultralow in carbon, < 3 x lo1' atoms/cm3, the precipitation is heavily retarded, and there is no denuded zone formation (Wilkes, 1983). The effects of not precipitating enough oxygen have been demonstrated by de Kock (1982),who found that, during an n+ phosphorus diffusion into an epitaxial layer, under the diffused region the denuded zone

1.8 Crystal Engineering

-E

No denuded !

Denuded zone

A

I 0 %

I

+

I

'

I

I

I

I

I

7.0 10.0 8.0 9.0 Initial oxygen concentration [O,I(1017*)

cm3

Figure 1-32. Two-stage oxygen precipitation in silicon. Thermal cycles: 1 1 5 0 T , 16 h; 650"C, 64 h. Other two-stage processes exhibit similar behavior, with no denuded zone formation below an initial oxygen concentration of around 8 x lo" atoms/cm3.

width shrank, in one case from 50 to 25 pm, in another from 25 pm to zero. His interpretation of the denuded zone shrinkage under the diffused islands is that the rapid formation of critical nuclei and secondary precipitation is due to the local injection of a large excess of silicon self-interstitials. This links to the diffusion jump mechanism and enhanced diffusion described in Sec. 1.7.3. Such secondary precipitation is quite general, and may build up throughout a multistage process, rather than at one particular step. Again, during lower fabrication temperature CMOS device processing, using substrates of medium to high oxygen content, difficulties are often encountered because of thermal donor formation, which make voltage threshold adjustment steps necessary. Reducing the residual oxygen concentration eliminates this problem. Thus, while many intrinsic gettering studies have concentrated on the aspects of denuded zone depths, and the precipitate sizes and number densities, the residual bound interstitial oxygen concentration present afterwards is

55

a crucial performance parameter. Some two-step gettering processes rely on the first oxidation in the MOS fabrication line, at a temperature of 1000-1100"C, to provide some further precipitation, but as the oxides required get thinner, and oxidation times shorter, this is insufficient. A much better intrinsic gettering process, which overcomes these problems and permits matching, to optimize the material characteristics to individual device lines, is provided by a three-step system which separates control of the desired parameters. The concepts are illustrated in Fig. 1-33, which shows the purpose of each step. The highest oxygen concentrations, normally met at the top of Czochralski crystals, are around 1 x 1018atoms/cm3 which corresponds to a maximum solid solubility temperature of approximately 1200 "C, lower for the remainder of the crystal which contains less oxygen. In step 1 the slices are heated at a temperature chosen in the range 1100- 1200"C, above the solid solubility values for most slices, while even in the "worst cases" the supersaturation is very low. There is no precipitation and any pre-existent grown-in nuclei (Fig. 1-25) are dispersed, to ensure that all the material is in a uniform state. Out-diffusion reduces the oxygen content substantially as described above, the time, commonly in the range of 5-10 h, defining the chosen depth of the denuded zone to follow, Fig. 1-33 a. Next, in step 2, the slices are given a low temperature heat treatment, for example, at 750°C for times between 5 to 30 h. In accord with the theory a large number of small nuclei form and begin to grow slowly, except in the reduced oxygen content layer close to the surface, where very few are formed, any that are being of very small size, Fig. 1-33b. The assemblage so produced has a statistical particle size distribution, increasing slowly as longer times

56

1 Silicon Processing

1011 2

-.v)

W

u c

m L

a .e 0

d z

Particle size

Distance from surface X

I ‘;lICCCl

(a)

(C)

I

Temperature

Distance from surface X

(d)

(b)

I

I 1 !

Oxygen diffuses t o growing

Denuded; zone !e

Figure 1-33. Three stage oxygen precipitation in silicon. Crystal engineering: (a) stage 1: outdiffusion of oxygen to surface at 1100°C; (b) stage 2: nucleation at 750°C (c) particle size distributions at stage 2; (d) critical radius, r,, for particle growth as a function of temperature: (e) stage 3: particle growth at 1000°C.

Distance from surface X

(el

are chosen, while, as required by the Ham theory and depicted in Fig. 1-33c, their total numbers remain near constant. The concept of the stability of particles of greater than some critical radius, rc , has been introduced above. The value of this radius depends on a number of factors: (a) The surface free energy of the particle matrix interface, CT, and the volume free energy change of the precipitate, AF, (Burke, 1965), where y

20 AF,

=-

(1-18)

(b) The degree of supercooling, AT, the difference between the chosen anneal temperature, T, and that higher temperature at which the solute oxygen concentration, C,, is at saturation equilibrium, and the activation energy, E,, for the formation of a nucleus of the critical radius, are related by

N , = c, exp

(- &)

(1-19)

where N , is the concentration of precipitate particles.

57

1.8 Crystal Engineering

(c) The volume free energy is related to the supercooling and the enthalpy of reaction, AH, by

AFv =

($)

AT

(1-20)

Finally the surface free energy for the precipitate-matrix interface is obtained from 3 E, (AFv)2‘ I 3 1671

.=[

]

(1-21)

Values for critical radii have been calculated for various temperatures and degrees of supersaturation (Freedland et al., 1977; Osaka et al., 1980).These are all very small, ranging from around 108, at a temperature of 1050”C, which corresponds to nuclei containing clusters of about 100 atoms, down to only 3-4 8, and clusters of 6-10 atoms at 650°C. While these numbers are very small, it should be remembered that the final precipitates grown at 650”C, while of platelet structure, have an “equivalent” spheroid radius of only around 30 8, (see Fig. 1-27).The form of the temperature dependence of the critical radius is shown in Fig. 1-33d. Further extension of this model to the rates of nucleation leads to predictions of induction times at the outset of single stage anneals, while stable nuclei are being formed, in accord with observations (Capper et al., 1977; Hu, 1981; Inoue et al., 1981). However, the important point to note is that the critical radius is temperature dependent, and at 7 5 0 T is much smaller than at 1000°C. Therefore, when in stage 3 the slices are heated for some hours at 1000°C most of the small particles generated at stage 2 redissolve, leaving only those at the upper end of the statistical distribution to continue to grow. A longer heating time at

stage 2 leaves more larger nuclei so this stage defines the number density of particles from the overall precipitation process. The final stage then determines how much of the oxygen initially present is to be precipitated, and so the particle size, see Fig. 1-33e (Wilkes, 1988). The matrix of Fig. 1-34, taken from the work of Huber and Reffle (1983), shows this three-stage process in operation. All the slices were given the same stage 1 out-diffusion of 10 h at 1100 “C then groups were nucleated at 750°C for increasing times, before the final precipitate growth at 1000°C again for 4 increasing times. The expected pattern is seen with all having about the same denuded zone depth, while the particle density increases with stage 2 time, down the figure, and the particle size with stage 3 time, from left to right across the figure, in a well-controlled manner. The ability of the three-stage process to handle a wide range of input oxygen concentrations is shown in Fig. 1-35 in comparison with two-stage results, where the high and consistent reduction in the initial oxygen level achieved ensures minimal further precipitation during subsequent device fabrication. In summary then, a three-stage intrinsic gettering process can overcome the earlier problems met in two-step methods. It accepts a wide input oxygen range, and the functions are separated, with stage 1 defining the denuded zone, stage 2 the particle density, and stage 3 the particle size and the total amount of supersaturated bound interstitial oxygen removed from solid solution. The three stages allow the parameters to be varied to meet individual customer requirements to match the material to the specific device fabrication process. Entering the ULSI era, it is becoming even clearer that close links between the silicon suppliers and the users are essential. -

58

1 Silicon Processing

Figure 1-34. A three-stage precipitation matrix. Note the clear separation of stage functions defining: (1) the denuded zone depth, (2) the number density, and (3) the precipitate size. Stage (1) was outdiausion at 1100°C for 10 h. The initial oxygen concentration was 8.15 x 10” atoms/ cm’. (By kind permission of Huber and Reffle, 1983.)

The crystal engineering of large diameter wafers has been noted previously in regard to the rising demands for the control of the oxygen level in p + and n + substrate materials, in addition to the attention already paid to this in normal p and n silicon. Full intrinsic gettering procedures as described

above are still not as widely adopted as might have been anticipated, although delivery of partially heat treated wafers in now common. On the other hand, forms of extrinsic gettering are quite widely used, and the market for enhanced gettered material appears to be growing steadily. After

1.9 Acknowledgements

59

Figure 1-35. The reduction in bound interstitial oxygen after two-stage (0)and three-stage annealing ( x). The markcd superiority of thc three-stage process is obvious. Initial oxygen concentration 1 1 0 ’ ~atoms/cm’)

many years of research and development fully crystal engineered wafers are now widely available incorporating both extrinsic and intrinsic gettering in combinations to achieve the highest possible performance. As in the other sectors examined in this chapter, in wafer manufacture the market pressures have been linked closely to the advances demanded in the technical attributes engineered into the material. Knowledge of the interaction between crystal microdefects and impurities, and device fabrication and performance has increased dramatically, and has impinged on the whole process, from crystal growth onwards, which has become more and more specialized, in the hands of the high capacity merchant producers. It is here, where the closest collaboration between the silicon material vendors and the device makers is most essential, that the combined economic and technical pressures from the Far East have been the most severe.

1.9 Acknowledgements The work described here represents over 30 years of continuing research and development. The author is indebted to his many colleagues in the Materials Departments at Philips/Mullard, Southampton for their years of valued, exciting, and enjoyable, support. Particularly I must record my thanks to Dave Perkins, Roland Kingsnorth, Dave Griffiths, and Ian Baldwin, and, for their encouragement, to Stan Bradshaw, and Dr. Max Smollett and Dr. Brian Avient. I also wish to recognize our long collaboration with the U.K. teams led by Prof. Ron Newman (Reading University), Dr. Keith Barraclough (RSRE, Malvern), and Prof. Ed Lightowlers (London University), in a wide range of joint projects. The contributions to my understanding of the silicon field from many friends in the major equipment and materials suppliers, and device houses around the world must be noted. In particular, Bob Lorenzini (Siltec), Remo Pellin and Gordon Martin (Monsanto), Ken Jackson (Bell Labs.), Ed Giess (LBM),and Don Jackson (Motorola),

60

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have shared and discussed new developments over a long period. The close links with Dr. Erhard Sirtl and Dr. Dieter Huber (Wacker Chemitronic) have contributed directly to the preparation of this chapter. Figure 1-34 (first published by Wilkes, 1983) came from the work of Huber and Reffle, and was reproduced with their permission, while Horst Fleischmann has been-a prime source for my awareness of the market pressures and industry trends.

1.10 References Abe, T.. Kikuchi, K., Shirai, S., Muraoka, S. (1981), in: Semiconductor Silicon 1981: Huff, H. R., Kriegler, R. J., Takeishi, Y. (Eds.). Pennington, NJ: Electrochem. SOC.,PV81-5, p. 54. Akiyama, N., Yatsurugi, Y., Endo, Y., Imayoshi, Z., Nozaki, T. (1973), Appl. Phys. Lett. 22, 630. Amouroux, J., Morvan, O., Apostolidou, H., Shootman, F. (1986), Electrochem. Soc. Extended Abstr. NO. 298, PV86-1, 441. Aulich, H. A,, Eisenrit, K. H., Schulze, F. W., Strake, B., Urbach, H. P. (1985), 6th E.C. Photovoltaic Energy Con$ London: Commun. Eur. Communities Rep. EUR 10025, p. 951. Bains, S. K., Barraclough, K. G., Griffiths, D. P., Series, R. W., Wilkes, J. G. (1990), J. Electrochem. Soc. 137, 647. Barraclough, K. G. (1982), in: Symp. Aggregation Phenomena of Point Defects in Silicon, ESSDERC, Munich: Sirtl, E., Goorissen, J., Wagner, P. (Eds.). Pennington, NJ: Electrochem. Soc., PV83-4, p. 176. Barraclough, K. G., Series, R. W. (1988), Patent GB 8 805 478. Barraclough, K . G., Wilkes, J. G. (1986), in: Semzconductor Silicon 1986: Huff, H. R., Kolbesen, B. O., Abe, T. (Eds.). Pennington, NJ: Electrochem. SOC., PV86-4, p. 889. Batterman, B. W., Hildebrandt, G. (1968), Acta Crystallogr. A24, 150. Benton, J. L., Kimmerling, L. C., Stavola, M. (1983), Physica B 116, 271. Bergholtz, W., Binns, M. J., Booker, G. R., Hutchinson, J. C., Kinder, S. H., Messoloras, S., Newman, R. C., Stewart, R. J., Wilkes, J. G. (1989), Phil. Mug. B 59, 499. Binns, M. J., Brown, W. P., Livingston, F. M., Messorolas, s., Newman, R. C., Stewart, R. J., Wilkes, J. G. (1983), Appl. Phys. Lett. 42, 525.

Bischoff, F. (1954), Patent DBP 1 134459. Bloem, J., Classen, W. A. P. (1980), J. Cryst. Growth 4Y. 435 (part I), and 807 (part 2). Bloem, J., Classen, W. A. P. (1983-84), Philips Tech. Rev. 41. 60. Bloem, J., Gilling, L. J. (1978), in: Current Topics in Materials Science, Vol. 1: Kaldis, E. (Ed.). Amsterdam: North-Holland, p. 147. Bond, W. L., Andrus, J. (1952), Am. Mineral. 37,622. Buck, T. M., McKim, F. S. (1956), J. Electrochem. Soc. 103. 593. Burke, J. (1965), The Kinetics of’ Phase Transformations in Metals. London: Pergamon, Chaps. 6 and 7. Burton, J. A,, Prim, R. C., Schlichter, W. P. (1953), J. Chem. Phys. 21, 1987. Capper, P., Jones, A. W., Wallhouse, A. J., Wilkes, J. G. (1977), J. Appl. Phys. 48, 1646. Carlberg, T. (1986), J. Electrochem. Soc. 133, 1940. Carruthers, J. R. (1967), J. Electrochem. Soc. 114, 1077. Carruthers, J. R., Nassau, K. (1968), J. Appl. Phys. 39, 5205. Carruthers, J. R., Wilt, A. F., Reusser, R. E. (1977), in: Semiconductor Silicon 1977: Huff, H. R., Sirtl, E. (Eds.). Pennington, NJ: Electrochem. SOC., PV77-2, p. 70. Cartwright, R. A., El-Kaddah, N., Szekely, J. (1985), I M A J. Appl. Math. 35, 175. Chedzey, H. A,, Hurle, D. T. J. (1986), Nature 210, 933. Claeys, C., Declerck, G., Van Overstraeten, R., Bender, H., Van Landuyt, J., Amelinckx, S. (1981), in: Semiconductor Silicon 1981: Huff, H. R., Kreigler, R. J., Takeishi, Y. (Eds.). Pennington, NJ: Electrochem. SOC.,PV8I-5. Cockayne, B., Gates, M. P. (1967), J. Mater. Sci. 2, 118. Corbett, J. W., Watkins, G. D. (1961), J. Phys. Chem. Solids 20, 319. Craven, R. A. (1981), in: Semiconductor Silicon 1981: Huff, H. R., Kreigler, R. J., Takeishi, Y. (Eds.). Pennington, NJ: Electrochem. SOC., PV81-5, p. 254. Crossman, L. D., Baker, J. A. (1977), in: Semiconductor Silicon 1977; Huff, H. R., Sirtl, E. (Eds.). Pennington, NJ: Electrochem. SOC.,PV77-2, p. 18. Czochralski, J. (1917), Z . Phys. Chem. 92, 219. Dash, W. C. (1958), J. Appl. Phys. 29, 739. Dash, W. C. (1959), J. Appl. Phys. 30, 459. Dash, W. C. (1960), J. Appl. Phys. 31, 736. Davics, G. (1989), in: Proc. 15th Znt. Conf. Defects in Semiconductors, Budapest, Aug. 1988. Mater. Sci. Forum 38-41 ( I ) . deKock, A. R. J. (1983), Proc. Symp. ESSDERC, Munich. Pennington, NJ: Electrochem. SOC., PV83-4, p. 58. Deslattes, R. D., Paretzkin, B. (1968), J. Appl. Crystallogr. 1. 176.

1.10 References

Dietl, J., Holm, C. (1986), Electrochem. Soc. Extended Abstract No. 299, PV86-1, 441. Dietl, J., Helmreich, D., Sirtl, E. (1981), Solar Silicon, in: Crystals: Growth, Properties, and Applications, Vol. 5: Grabmeier, J. (Ed.). Berlin: Springer, p. 43. Dosaj, V. D., Hunt, L. P., Schei, A. (1978), J. Met. 30, 8. Dupret, F., Ryckmans, Y.. Wouters, P., Crochet, M. J. (1986), J. Cryst. Growth 7Y,84. Ellis, W. C., Treuting, R. G. (1951), J. Met. 191, 53. Freedland, P. E., Jackson. K. A,, Lowe, C. W., Patel, J. R. (1977), Appl. Phys. Lett. 30, 31. Gosele, U., Tan, T. Y. (1983), Proc. Symp. ESSDERC, Munich. Pennington, NJ: Electrochem. SOC.,PV83-4, p. 17. Ham, E S. (1958), J. Phys. Chem. Solids 6 , 335. Healy, G. W. (1970), Earth Miner. Sci. 39, 46. Herrmann, H. A,, Herzer, 13. (1975), J. Electrochem. Soc. 122, 1568. Herrmann, H. A., Mucke, E. (1973), 2nd DFG Colloquium on Power Devices, Freiburg. Herzer, H. (1977), in: Semiconductor Silicon 1977: Huff, H. R., Sirtl, E. (Eds.). Pennington, NJ: Electrochem. Soc., PV77-2, p. 106. Herzer, H. (1980), Proc. 3rd Int. Conf: on NTD Silicon, Copenhagen. New York: Plenum. Hoffman, A., Reuschel, K., Rupprecht, J. (1959), J. Phys. Chem. Solids 11, 284. Hoshi, K., Suzuki, T., Okubo, Y., Isawa, N. (1980), Electrochem. Soc. Extended Abstr. N o . 324, PVH0/, 811. Hoshikawa, K. (1982), Jpn. J. Appl. Phys., Part 2,21, L545. Hoshikawa, K., Kohda, H., Hirata, H. (1984), Jpn. J. Appl. Phys. 23, L37. Hu, S. M. (1981), J. Appl. Phys. 52, 3974. Huber. D., Reffle, J. (1983), Solid State Technol. 26, 137. Hurle, D. J. T. (1967), in: Crystal Growth: Peiser, H. S. (Ed.). Supplement to: J. Phys. Chem. Solids. Oxford: Pergamon, p. 659. Hurle, D. T. J., Jakeman, E., Johnson, C. P. (1974), J. Fluid Mech. 64, 565. Inoue, N., Wdda, K., Osaka, J. (1981), in: Semiconductor Silicon 1981: Huff, H. R., Kreigler, R. J., Takeishi, Y. (Eds.). Pennington, NJ: Electrochem. SOC.,PV81-5, p. 282. Jackson, K. A. (1990), Recent results, private communication. Kaiser, W. (1957), Phys. Rev. /05, 1751. Kaiser, W., Keck, P. H., Lange, C. F. (1956), Phys. Rev. 101, 1264. Kaiser, W., Frisch, H. L., Reiss, 11. (1958), Phys. Rev. 112, 5. Keck, P. H., Golay, M. J. E. (1953), Phys. Rev. 8Y, 1297. Keller, W. (1959), Patent DBP 1 148 525. Kern, W., Puotinen, D. A. (1970), RCA Rev. 31, 187. Kishino, S., Matsushita, Y., Kanamori, M . (1979), Appl. Phys. Lett. 35, 213.

61

Kobayashi, N. (1978), J. Cryst. Growth 52, 425. Kobayashi, N., Arizumi, T. (1970), Jpn. J. Appl. Phys. 9, 361 and 1255. Kobayashi, N., Wilcox, W. R. (1982). J. Cryst. Growth 59, 616. Langlois, W. E. (1984), J. Cryst. Growth 70, 73. Langlois, W. E. (1985), Annu. Rev. Fluid Mech. 17, 191. Langlois, W. E., Shir, C. C. (1977), Comput. Methods Appl. Mech. Eng. 12, 145. Lark-Horowitz, K. (1951), Proc. Conf. Semiconducting Materials, Reading, U.K. London: Butterworth, p. 47. Livingston, F. M., Messoralas, S., Newman, R. C., Pike, R. J., Stewart, R. J., Binns, M. J., Brown, W. P., Wilkes, J. G. (1984), J. Phys. C: Solid Stare Phys. 17, 6253. Lyon, D. W., Olsen, C. M., Lewis, E. D. (1949), J. Electrochem. Soc. 96, 359. Matsushita, Y. (1982), J. Cryst. Growth 56, 516. Meese, J. M. (Ed.) (1978), 2nd Int. Conf. on N T D Silicon, Missouri, U.S.A. New York: Plenum (29 Refs.). Moody, J. W. (1986), Proc. Semiconductor Silicon 1986: Huff, H. R., Kolbesen, B. O., Abe, T. (Eds.). Pennington, NJ: Electrochem. Soc., PV86-4, 100. Murgai, A,, Patrick, W. J., Combronde, J., Felix, J. C. (1982), IBM J. Res. Dev. 26, 546. Newman, R. C. (1973), Infrared Studies qf Crystal Defects. London: Taylor and Francis. Newman, R. C. (1988), Muter. Res. Soc. Symp. Proc. 104, 25. Newman, R. C., Claybourn. M. (1988), Inst. Phys. Con6 Ser. 95, 211. Newman, R. C., Binns, M. J., Brown, W. P., Livingston, F. M., Messorolas, S., Stewart, R. J., Wilkes, J. G. (1983a), Physica B 116, 264. Newman. R. C., Tucker, J. H., Livingston, F. M. (1983b), J. Phys. C: Solid State Phys. 16, L 151. Osaka, J.. Inouc, N., Wada, K. (1980), Appl. Phys. Lett. 36, 288. Pfann, W. G. (1952), J. Met. 4 , 747. Pfmn, W. G. (1958), Zone Melting. New York: Wiley. Robertson, D. S. (1966), Br. J. Appl. Phys. 17, 1047. Rutter, J. W., Chalmers, B. (1953), Can. J. Phys. 31, 15. Schlichting, H. (1968), Boundary Luyer Theory. New York: McGraw-Hill, Chap. 12. Shimura, F., Hockett, R. S., Reed, D. A,, Wayne, D. H. (1985), Appl. Phys. Lett. 47, 794. Showa Denko K. K. (1984), Patent Japan 593071i. Steinbcck, H. H. (1980a), Electrochem. Soc. Extended Abstracts, PV80-2, 1325. Steinbeck, H. H. (1980 b), Proc. 1st Eur. Symp. Materials and Processing, Mountain View, CA, U.S.A. SEMI, p. 57. Stimmel, J., Strathman, M., Wittmer, M. (Eds.) (1 986), Materials Issues in Silicon IC Processing. Muter. Rex. Soc. Synip. Proc. 71. Sundermeyer (1957). Patent.

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Suzuki, T., Isawa, N., Okubo, Y., Hoshi, K. (1981), in: Semiconductor Silicon 1981, Huff, H. R., Kreigler, R. J., Takeishi, Y.(Eds.). Pcnnington, NJ: Electrochcm. SOC.,PV81-5, p. 90. Tamura, M., Sunami, H. (1972), Jpn. J. Appl. Phys. 11, 1097. Tan, T. Y, Gardner, E. E., Tice, W. K. (1977), Appl. Phys. Lett. 30, 175. Tanenbaum, M., Mills, A. D. (1961), J. Electrochem. SOC.108, 171. Tanner, B. K. (1977), X-Ray Diffraction Topography. Oxford: Pergamon, p. 50. Taylor, P. A. (1987), Solid State Technol. 30, No. 7, 53. Taylor, P. A. (1988), J. Cryst. Growth 89, 28. Teal, G. K., Buehler, E. (1952), Phys. Rev. 87, 190. Theurer, H. C. (1952), Patent USP 3060 123. Theurer, H. C. (1956), Trans. AIME 206, 1316. Thomas, D. J. D. (1963), Phys. Status Solidi 3, 2261. Tokumaru, Y., Ohushi, H., Masui, T., Abe, T. (1982), Jpn. J. Appl. Phys. 21, 443. Townley, D. 0. (1973), Solid State Technol. 16, 43. Wada, K. (1984), Phys. Rev. B 30, 5884. Wada, K., Inoue, N. (1986), in: Semiconductor Silicon 1986: Huff, H. R., Kolbesen, B. O., Abe, T. (Eds.). Pennington, NJ: Electrochem. SOC., PV86-4, p. 778. Walsh, R. J., Hertzog, A. H. (1963), Patent USP 3 170 273. Wanatabe, M. (1991), Solid State Technol. 34, 69, 133. Wilkes, J. G. (1959), Proc. IEE 106B. Supp. 17, 866. Wilkes, J. G. (1983), J. Cryst. Growth 65, 214. Wilkes, J. G. (1988), Trans.-Inst. Min. Metall. 97, C 72. Wilkes, J. G., Perkins, D. W. (1971 -72), DCVD Res. Rep. RP6-62. London: Ministry of Defence. Witt, A. F., Herman, C. J., Gatos, H. C. (1970), J. Mater. Sci. 5 , 822. Yamamoto. K., Kishino, S., Matsushi, Y. Iizuka, T. (1980), Appl. Plzys. Lett. 36, 195. Yang, K. H., Kappert, H. F., Schwuttke, G. H. (1978), Phys. Status Solidi A 50, 221. Yatsurugi, Y, Akiyama, T., Endo, Y., Nozaki, T. (1973), J. Electrochem. SOC.120, 985.

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General Reading Brice, J. C. (1973), The Growth of Crystalsfrom Liquids. Amsterdam: North-Holland. Einspruch, N. G., Huff, H. (1985), V L S IElectronics, Vol. 12: Silicon Materials. London: Academic. Gupta, D. C. (Ed.) (1983, 1984), Silicon Processing. Technical Publications 804 and 850. Philadelphia, PA: ASTM. Hurle, D. T. J. (1993), Crystal Pulling from the Melt. Heidelberg: Springer. Mikkelsen, J. C., Corbett, J. W., Pearton, S. J., Penneycook, s. J. (Eds.) (1986), Oxygen, Carbon, Hydrogen, and Nitrogen in Crystalline Silicon. Mater. Res. SOC.Symp. Proc., Vol. 59. Pittsburgh, PA: Materials Research Society. Ravi, K. V. (1981), Imperfections and Impurities in Semiconductor Silicon. New York: Wiley. Stavola, M., Pearton, S. J., Davies, G. (Eds.) (1988), Defects in Electronic Materials. Mater. Res. SOC. Symp. Proc., Vol. 104. Pittsburgh, PA: Materials Research Society. Sze, S. M. (Ed.) (1983), VLSI Technology. New York: McGraw-Hill. Wolf, S., Tauber, R. N. (1986), Silicon Processing for the V L S I Era, Vol. 1: Process Technology. Sunset Beach, CA: Lattice Press. Crystals: Growth, Properties, and Applications, Vols. 1-10. Vol. 5: Freyhard, H. C. (Ed.) (1981) for F Z Si. Vol. 7: Grabmaier, J. (Ed.) (1982) for CZ Si. Berlin: Springer. Semiconductor Silicon. This series of symposia organized by the Electrochemical Society reflects the whole development of silicon materials technology and provide a very important reference and reading resource: 1969 New York; 1973 Chicago; 1977 Philadelphia; 1981 Minneapolis; 1986 Boston; 1990 Montreal. The proceedings are published by the Electrochemical Society, Pennington, NJ.

2 Silicon Device Structures

.

Chun-Yen Chang and Simon M Sze National Chiao Tung University. Hsinchu. Taiwan. R.O.C.

List of Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Potential-Effect Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 2.2.1 n+-i-n+ Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Planar Doped Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 p-n Junction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4 Bipolar Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5 Heterojunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.6 Heterojunction Bipolar Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.7 Thyristors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.8 Hot Electron Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Field-Effect Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Metal-Silicon Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 Homogeneous Field-Effect Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 MOS Structure and Charge-Coupled Devices . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4 MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4.1 Submicrometer MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4.2 Silicon-on-Insulator Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4.3 Thin-Film Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4.4 Nonvolatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.5 MODFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.6 Microvacuum Field Emitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quantum-Effect Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 2.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 Quantum Wells, Wires, and Dots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.3 Resonant-Tunneling Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.4 Multiple Quantum Well Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.5 Resonant-Tunneling Hot-Electron Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Microwave and Photonic Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 IMPATT Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 BARITT Diode ................................................... 2.5.3 Photodetectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.4 Solar Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8

64 67 68 68 69 70 72 74 75 77 79 80 80 82 82 84 84 88 89 90 92 93 95 95 95 97 99 99 102 102 104 104 107 109 111 111

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2 Silicon Device Structures

List of Symbols and Abbreviations cross-sectional area doping region thickness capacitance thickness; dimensionality diffusion constant energy electric field bandgap difference between emitter and base valence band offset Fermi energy frequency maximum frequency of oscillation cutoff frequency transconductance Planck constant (ti = h/(2x)] current gain current generation current recombination current current density Boltzmann constant wave vector length z-component of the angular momentum effective mass concentration doping concentration momentum charge charge surface density junction depth resistance subthreshold slope depleted silicon film thickness absolute temperature; transmission coefficient voltage breakdown voltage volume in k-space surface depletion width W,,W,, Wsub depletion layer width of source, drain, supporting silicon substrate Z total number of states c1

Y

sum of current gain lifetime width of resonant state

List of Symbols and Abbreviations

infinitesimal thickness permittivity dielectric permittivities in silicon, metal emission efficiency wavelength; penetration depth cutoff wavelength electron mobility valley degeneracy charge density lifetime barrier lowering metal work function change in electrostatic potential heterojunction barrier barrier height for electrons in the metal; Schottky barrier electron affinity BARITT BICFET BICMOS CCD CMOS CTE CVD CW DBQW DBRTD 2 DEG 2 DHG DOS EEPROM EPROM FAMOS FIPOS HBT HET HIPOX IBT IGBT IMPATT JFET LDD LRP LT MBE

barrier injection transit time bipolar inversion-channel field-effect transistor bipolar complementary metal-oxide semiconductor charge-coupled device complementary metal-oxide semiconductor charge-transfer efficiency chemical vapor deposition continuous wave double-barrier quantum well double-barrier resonant-tunneling diode two-dimensional electron gas two-dimensional hole gas density of states electrically erasable programmable read-only memory erasable programmable read-only memory floating gate avalanche injection metal-oxide semiconductor full isolation by porous oxidized silicon heterojunction bipolar transistor hot-electron transistor high-pressure oxidation induced base transistor insulated-gate bipolar thyristor impact ionization avalanche transit time junction field-effect transistor lightly doped drain limited reaction process low temperature molecular-beam epitaxy

65

66

2 Silicon Device Structures

MESFET MIOS MOCVD MODFET MOS MOSFET MQW NDR PBT PDB PECVD QW RTA SIMOX

so1

TFT UHV ULSI VLSI ZMR

metal-semiconductor field-effect transistor metal-insulator-oxide-semiconductor metal-organic chemical vapor deposition modulation-doped field-effect transistor metal-oxide semiconductor metal-oxide semiconductor field-effect transistor multiple quantum well negative differential resistance permeable-base transistor planar-doped barrier plasma-enhanced chemical vapor deposition quantum well rapid thermal annealing separation by implanted oxygen silicon-on-insulator thin-film transistor ultra-high vacuum ultra-large-scale integration very-large-scale integration zone melting recrystallization

67

2.1 Introduction

2.1 Introduction Silicon is the most important semiconductor for the electronics industry. At present, silicon-based devices constitute over 95% of all semiconductor devices sold worldwide. Silicon’s dominance is the result of its bandgap, its superb natural oxide, its outstanding mechanical properties, and its abundance in nature. Silicon’s bandgap of 1.12 eV at room temperature is large enough to give relatively low leakage current from thermally generated carriers. Silicon is unique in that it possesses the most outstanding natural dielectric, silicon dioxide (SiO,), which has high breakdown strength (- 10 MV/cm) and low interface trap density ( - lo9 traps/cm2). Silicon is an extremely hard, unyielding semiconductor with a Knoop hardness of 1150 kg/mm2 (twice that of stainless steel) and a yield strength of 7 x lo1’ dyn/cm2 (a factor of 1.8 larger than tungsten). Silicon in the form of silica and silicates makes up 28% of the Earth’s crust, and silicon is second only to oxygen in abundance. Figure 2-1 shows the world production of polished single-crystal Si wafers and 111-V compound semiconductor wafers. It is apparent that silicon has much higher production volume due to its pre-eminent position in very-large-scale integrated (VLSI) circuits as well as numerous discrete-device applications. We anticipate that this production trend will continue. By the year 2000, silicon wafer area will reach 10 square kilometers (or about 200 million wafers with a 250 mm diameter) while the 111-V compound wafer area will be about two orders of magnitude lower (Pearce, 1988; Meindl, 1984). Semiconductor devices can be broadly divided into three groups: potential-effect

10‘1,

10’0

I

1

’ /

-

h

N

6

v

109-

W LT

Q

108

-

107 1960

1980 YEAR

2000

Figure 2-1. World production of single-crystal silicon and 111-V compound semiconductors (after Pearce, 1988; Meindl, 1984).

devices, field-effect devices, and quantumeffect devices. Potential-effect devices, considered in Sect. 2.2, are current controlled, with the control electrode resistively coupled to the active device region, and the charge carriers separated energetically by an energy barrier. Potential-effect devices include the classic bipolar transistor and the heterojunction bipolar transistor. Fieldeffect devices, considered in Sect. 2.3, are voltage controlled, with the control electrode capacitively coupled to the active region of the device and the charge carriers separated by an insulator or a depletion layer. Field-effect devices include the MOSFET, MESFET, and MODFET. Quantum-effect devices, presented in Sect. 2.4, use resonant tunneling to provide controlled transport. In such devices, the operational distance is comparable to the de Broglie wavelength (A = h/p, where h is Planck’s constant and p is the momentum), which is about 200 A at room temperature.

68

2 Silicon Device Structures

Quantum-effect devices can increase the operational speed above that achievable by the conventional potential-effect or fieldeffect devices. In addition, many quantumeffect devices are functional devices, i.e., they can perform a given electronic function with a minimum number of electronic components. Silicon microwave and photonic diodes are covered in Sect. 2.5. The operation of most of these devices is based on the potential-effect principle. Microwave diodes are two-terminal devices that can generate, amplify, or detect signals at microwave frequencies (1 to 1000 GHz). The silicon microwave diodes to be considered are the IMPATT diode and the BARITT diode. Silicon photonic devices include the photodetector, which can detect optical signals through electronic processes, and the solar cell, which can convert optical radiation into electrical energy. We expect that silicon-based devices will remain the dominant devices for electronic applications in the foreseeable future. An outlook for advanced silicon-device structures is presented in Sect. 2.6.

2.2 Potential-Effect Devices 2.2.1 n+-i-n+ Diode In Fig. 2-2a, the n+-i-n+ diode is a majority-carrier device (electron conduction in n+-n-nf and hole conduction in p+-i-p+) in which a semicircular potential is formed between these two heavily doped electrodes. The formation of the barrier is due to the electron concentration n

in the i-layer, which constitutes a charge density e in the Poisson equation.

.

.,

U

V

I

I

'

L

I

-

a

v=o

I

APPLIED B l A S f P V )

(b) Figure 2-2. Illustration of the n-i-n diode under applied bias. (a) Schematic profiles of the electric field and the electrostatic potential energy. The energy diagram also shows the quasi-Fermi level EF(x)(dashed line). (b) Calculated current-voltage characteristics (Luryi, 1990).

The I - V characteristic is shown in Fig. 2-2b, which can be expressed at high voltage as

69

2.2 Potential-Effect Devices

wherej is the current density, L the i-layer thickness, E , the permeability, zcc! p the electron mobility. Equation (2-2) is identical to the classical Mott-Gurney law (Luryi, 1990) for space-charge-limited current, and at low voltage the I - V characteristic becomes

(2-3) which represents a linear law. n(0) is the carrier concentration at x = 0. The n+-i-n+ or p+-i-p+ diode is one of the building blocks for various kinds of novel electron devices.

A

2.2.2 Planar Doped Barrier The planar-doped-barrier (PDB) rectifying structure was first demonstrated in GaAs molecular-beam-epitaxy (MBE) grown samples (Malik et al., 1980). It represents an extension (the limiting case) of the camel-diode structure. We begin by reviewing the theory of rectification and charge injection in this important structure (Kazarinov and Luryi, 1982). A PDB [n-i-6 (p+)-i-n] structure, as shown in Fig. 2-3 a, has a nearly intrinsic (i) layer of thickness L sandwiched between two n-type layers of low resistivity. In the process of epitaxial growth, a p+-doped layer of (infinitesimal) thickness 6 4 L with a doping of NA is built into the i region. Acceptors in the p+ layer are completely ionized, that is, Completely depleted of holes. A negative charge sheet of surface density Q = q NA6 gives rise to a triangular potential barrier with shoulders L , and L , and a height 4 given approximately by

(2-4) This expression corresponds to a “capacitor” model in which the fixed charge Q

o+-,

0.5 1 1.5 2 APPLIED VOLTAGE ( V )

(b) Figure 2-3. (a) Schematic illustration of the planardoped triangular barrier. (b) Calculated I V characteristics for a Si PDB diode with the following parameters: L , = 250 A, L , = 2000 A, N,, = IOl9 ~ r n - ~ , Q/q = 2 x 10” (after Luryi, 1990). ~

induces charges only in an infinitesimally thin layer of the doped contacts at the boundaries of the i layers. In equilibrium, the barrier height is the same on both sides if the doping in both contact layers is identical. Under an applied bias K the height of the emitter (“uphill”) barrier will decrease by the amount V L J L(without loss of generality, we can assume that the emitter barrier corresponds to the shoulder L giving

70

2 Silicon Device Structures

rise to an exponentially increasing current I ePvLIILz (2-5) where = q/(k T ) . The band diagram of the planar-doped diode is shown in Fig. 2-3 a under equilibrium (V = 0) and nonequilibrium conditions [V(F) for forward bias and V(R) for reverse bias]. As can be seen from the figure, the barrier at the left is lowered (forward bias) by V, while the barrier at the right is increased by V2 in a reverse-bias sense, which is similar to the emitter-base and the base-collector harriers in an npn transistor, respectively. Figure 2-3 b shows I - V characteristics of a Si PDB with different lengths for L , and L,, ( L 2 / L ,= 8), and indicates that the device acts as a rectifier. The planar-doped barrier is another name for the “trinangular barrier”. It can also be built by grading the bandgap to make a triangular shape in the conduction or valence band, by using graded compositions of Si/Ge, Si/SiC (Jwo and Chang, 1986), and GaAs/AlGaAs (Allyn et al., 1980), etc. The planar-doped barrier is akin to a Schottky diode, with the advantage that the barrier height can be modified by the composition, doping or by controlling L and L,.

,

2.2.3 p-n Junction The most important characteristic of p-n junctions is their ability to rectify, that is, they allow current to flow easily in only one direction. When we apply a “forward bias” to the junction, the current increases rapidly as the voltage increases. However, when we apply a “reverse bias”, virtually no current flows initially. As the reverse bias is increased, the current remains very small until a critical voltage is reached, at

which point the current suddenly increases. This sudden increase in current is referred to as the junction breakdown. The applied forward voltage is usually less than 1 V, but the reverse critical voltage, or breakdown voltage, can vary from just a few volts to many thousands of volts depending on the doping concentration and other device parameters. The p-n junction is the basic building block of the bipolar transistor and thyristor, as well as of JFETs and MOSFETs. Given proper biasing conditions or exposure to light, the p-n junction also functions as either a microwave or photonic device. Figure2-4a shows the p-n junction cross section, the minority-carrier concentration, and the current across the depletion layer. The depletion layer is developed in the vicinity of the metallurgical junction when a bias V is applied (forward bias on the left side of Fig. 2-4a and reverse bias on the right side). The band diagram is shown in Fig. 2-4b. The quasi-Fermi levels E,, and E,., are split by an amount equal to I/: Therefore, the nonequilibrium minoritycarrier density at the depletion-layer edges are in accordance with the position of E,, in the p layer, and of E,, in the n layer. As shown, for example, under forward bias, np (0) = npo exp [q V / ( kT ) ] , while pn(0)= pnoexp [q V/(kTI],where npoI pno are the minority carrier concentrations at equilibrium (V = 0). The slopes of these carrier profiles represent the respective diffusion current by the equation

where i = n or p, i.e., C, = It, C, = p , D ithe diffusion constant, Lithe diffusion length = and zi the carrier lifetime. The

6,

2.2 Potential-Effect Devices

FORWARD

71

REVERSE

Ln W Lp

M

m

JI

x‘

j

j

I

,

x

FP

EC

E Fn

Ev

Figure 2-4. (a) Injected minority carrier distribution and electron and hole diffusion currents of a pn junction under forward and reverse bias. (b) Band diagram and quasi-Fermi levels E,,, EFp.

total diffusion current becomes

while the generation current is

where A is the junction cross-sectional area. Another current comes from the recombination generation process in the depletion layer. Under forward bias the net rate is due to recombination, while under reverse bias it is due to generation (Sze, 1981, 1985). The recombination current is

where W is the depletion layer width. Figure 2-5 shows the I - V curves for a typical Si p-n junction under forward (a) and reverse (b) conditions, respectively. At low bias, the factor exp[q 1//(2k T ) ]is dominant while at high bias exp [q V / ( kT ) ]predominates. The increase of I, versus I/ is mainly due to an increase in the depletionlayer width W The breakdown voltage V, for a given background concentration can be ob-

72

2 Silicon Device Structures

-E

10-~

10 Y >

I

Y

10-6

ONE- SIDED ABRUPT JUNCTION

W E

n

-I

-a

w LL

z

za

; 10-8

Y

U

a

w (r m I-

10-10

U

T

: I-

10-12

0

0.2 0.4 0.6 0.8 1.0

(v) (a)

a W

VF

10-6

Z 1

I

0 I-

W

-I

a W

n

0.013 10'4

1 1017 1018 BACKGROUND DOPING NB ( ~ r n - ~ )

1015

10'6

Figure 2-6. Depletion-layer width ( Wm), maximum field at breakdown (&',,) and breakdown voltage (V,) for one-sided abrupt Si pn junctions (after Sze and Gibbons, 1966).

a CI

10-12 c 10-3

I

I

10-l

loo

plotted in Fig. 2-6 for a one-sided abrupt Si p-n junction at 300 K.

I

I

10'

lo2

2.2.4 Bipolar Transistor Figure 2-5. The current-voltage characteristics of a Si pn diode at various temperatures. (a) Forward bias. (b) Reverse bias.

tained from the maximum depletion-layer width W, and the maximum critical field &m, € , = q N , WJE,.The breakdown voltage VB is

(2-10) The breakdown voltage, the maximum ,, and the maximum depletion-layer field € width at breakdown W , versus NB are

The bipolar transistor is an active threeterminal device that combines an n-p junction and a p-n junction by means of a common middle p layer (base) which is very narrow. This is the npn bipolar transistor. Its complementary type is the pnp bipolar transistor. The band diagram of an npn bipolar transistor is shown in Fig. 2-7a. The solid lines are for the normal bias condition (i.e., emitter-base forward biased and the base-collector reverse biased) and the dotted lines for the equilibrium condition. Figure 2-7 b shows the minority carrier distribution profiles. Note that due

2.2 Potential-Effect Devices

c

_

-

EMITTER

BASE

I'

COLLECTOR

73

tion current I, in the E-B junction and a generation current f G in the C-B junction as shown in Fig. 2-7 b. In Fig. 2-7c, the electron current In, is emitted from the E-B junction and diffuses through the base with partial leakage to the base due to electron-hole recombination ZnB.The remainder I , , is collected by the collector electrode. Hole-diffusion current I,, and I, is injected from the base to the emitter. This current makes no contribution to the collector current. Therefore, to achieve a high current gain, the hole-diffusion current should be minimized. I , and I , are the leakage currents due to diffusion and generation, respectively, under a C-B reverse bias condition. The inverse of current gain hf,' can be expressed (Yang, 1988) as h;

1 =

'B b + In' - InC+ I,

(2-1 1) IC In, In, In, Applying the p-n junction current theory,

5v

0.6 V

(C) Figure 2-7. An npn transistor in equilibrium and in nonequilibrium. (a) Band diagram and quasi-Fermi levels under bias compared to a no-bias condition. (b) Minority-carrier concentrations under normal active bias. (c) Carrier flows in the respective regions.

to a reverse bias applied to the collectorbase (C-B) junction, nP(xB)% 0 while np(0) = npo exp [q V E J k T ) ]due to forward bias in the emitter-base (E-B) junction. It is easy to apply the same principle, discussed in the previous section (2.2.3), to derive the current flows in the respective regions. In addition, there is a recombina-

,N

+

NA xB XdE DnB 'i

- e V ~ / ( 2Tk)

(2-12)

'0

Subscripts E, B, C refer to the emitter, base, and collector respectively. From Eq. (2-12), h,, increases with decreasing base doping concentration N A B . This, in turn, decreases the high-frequency performance due to a large base spreading resistance R B B . The maximum unity-power-gain frequency J,,, is (Sze, 1990) (2-13 ) where f is the cutoff frequency at unity current iain due to total delay and transit time from E to C. A heterojunction bipolar

74

2 Silicon Device Structures

transistor can meet the requirements of both high gain and high-frequency response by having wider bandgap material in the emitter. This will be discussed in the following two sections. A modern high-frequency, doped polycrystalline emitter, bipolar transistor is shown in Fig. 2-8. The device was fabricated in a double-polysilicon self-aligned bipolar process (Chen et al., 1989). A schematic cross section is shown in Fig. 2-8 a. A p- substrate with an n+/n-epitaxial layer was used. Then, the device fabrication follows the polysilicon refilled-trench isolation process. An epitaxial p-type layer was grown on top of n-collector and isolation-

oxide layer. After p'-polysilicon delineation, oxidation, and n+-polydeposition at the emitter window, a thermal furnace and rapid thermal annealing were used to provide a shallow emitter-base junction. A representative device profile is shown in Fig. 2-8 b. The estimated base widths range from 63 to 95 nm with an emitterbase junction depth of about 25 nm. Such devices exhibit gains ranging from around 100 to 200, depending on the base implant dose and the resulting base Gummel number. The cutoff frequency f , reaches 51 GHz at a current density of more than 1.0 mA/pm2 while maintaining an emittercollector breakdown of 3 V. The total transit time is less than 3.0 ps.

2.2.5 Heterojunction

n

0.0

0.1

0.2 0.3 DEPTH ( f i m )

0.4

0.5

(b)

Figure 2-8. The self-aligned poly-Si emitter npn bipolar transistor. (a) Schematic device cross section. (b) Representative secondary ion mass spectrometry (SIMS) profile of a device obtained from a monitor wafer (after Chen et al., 1989).

In the early 1980s, a new unorthodox player emerged on the heterostructure scene, Ge,Si, - on Si (Kasper and Bean, 1989).The lattice constant of germanium is about 4% larger than that of silicon. For a strained, but not relaxed, overgrowth layer that obeys a rule of equilibrium, the overgrowth thickness should not exceed a critical thickness L, as is shown in Fig. 2-9 with different germanium fractions x. The bandgap versus x is also shown and decreases with increasing x values. The epitaxial growth techniques involve the molecular beam epitaxy (People, 1985), UHV/CVD (Meyerson, 1986), limited reaction process (Gibbons et al., 1985), etc. The band alignment of Ge,Si,-, on Si substrates for different x values is shown in Fig. 2-10. The bandgap discontinuity in the conduction band is always smaller than that in the valence band, e.g., AEc = 0.020 eV while AEv = 0.15 eV for x = 0.2, as shown in Fig. 2-10a. For x = 0.5, AEc = 0.15eV and AEv=0.30eV on an unstrained (001) Geo.25Sio,75buffer layer

75

2.2 Potential-Effect Devices

(not shown), as illustrated in Fig. 2-lob. Figure 2-1Oc shows the band alignment of the Ge,,,5Sio,5/Si heterostructure on a (001) Si substrate (People and Bean, 1986). The heterostructure is the building block for various kinds of novel GeSi/Si devices such as the heterojunction bipolar transistor, MODFET, and resonant-tunneling devices, which will be discussed in more detail in the following sections.

2.2.6 Heterojunction Bipolar Transistor The heterojunction bipolar transistor (HBT) offers numerous advantages over conventional homojunction bipolar transistors for high-frequency and high-speed applications. The advantage is due to the HBT's higher emitter injection efiiciency as a result of the bandgap of its emitter being larger than that of its base. Thus, higher base doping and lower emitter doping can be used to reduce the emitter-base delay time. The use of a graded base can further reduce the base transit time.

STRAl NED Eg (Geo.zSi0.e I = 1.OeV

CUBIC Eg (Si)=1.17eV

AEc Ec

0.150eV

__

t

I

STRAINED Eg (Geo.sSi0.5 ) = 089eV

STRAINED Eg ( S i 1 = 1.04eV

1 AEv = 0.30eV

- (bl

Ev

CUBIC

I

' STRAINED E g (Geo.sSi0.51= 0.78eV 4

E g ( S i ) = 1.17eV Ev

1

AEv

-__-

2

0.37eV

(C)

>

Figure 2-10. Band alignments for (a) Ge,,,Si,,,/Si heterostructures on (001) Si substrates, (b) Ge,,,Si,,,/Si heterostructures on an unstrained (001) Ge,,,,Si,,,5 buffcr layer, and (c)Ge,,,Si,,,/Si heterostructures on (001 )Si substrates (after People and Bean, 1986). 1.2

a,

v

a

1.1

Figure 2-1 1 a shows the band diagram of an HBT. Following the analysis of Eq. (2-12), the current gain, limited by emitter injection efficiency, is

1.0 >

2

0.9

w Z

w 0.8 h f e = NAE xEDnB

0.7

1-6.0

NAB x13 DpE

0 Si

0.2

0.4 0.6

Ge FRACTION , x

0.8

1.0

Ge

Figure 2-9. The critical thickness and bandgap energy versus Ge fraction of strained GeSi on a Si substrate (Bean, 1978).

exp

(2)

(2-14)

where AE, is the bandgap difference of the emitter and the base. Representative doping concentrations in state-of-the-art HBTs fabricated in the Si/GeSi system are shown in Fig. 2-11 b,

76

2 Silicon Device Structures

7SiGe

P

z

(550 "C) epitaxial silicon deposition process known as ultra-high vacuum chemical-vapor deposition (UHV/CVD). Demonstrated in this work are the excellent quality of Si/GeSi junctions formed using this method, the advantages of GeSi for bipolar device design, and the integration of this technology into a polyemitter bipolar process. Figure 2-12a shows the polyemitter bipolar structure with emitter dimensions of only 1.2 x 2.4 pm2, that was used in this work. An example of the final doping profile of a GeSi-base device is shown in Fig. 2-12b. In the GeSi-base transistors, the Ge content was graded from 0 to 14% across the base (roughly 6 to 13% across

- N * Pniv

,NITRIDE

w

0

0 N

+

SUBCOLLECTOR

P - SUBSTRATE

DEPTH (urn) (b) Figure 2-11. (a) Representative band diagram and (b) doping profile of an HBT.

which should be compared with those of Fig. 2-8 b for the homojunction transistor. In HBTs, doping levels of lozocmP3have been used in the base. As a result, base sheet resistance can be greatly decreased, even with ultra-narrow base regions, and transistor f,,, can be greatly increased, (Eq. (2-12)). In recent work (Meyerson et al., 1990),Si and graded-GeSi-base bipolar transistors were fabricated in a standard polyemitter bipolar process using the low-temperature

DEPTH ( n m l

(b) Figure 2-12. (a) Schematic cross section of the nonself-aligned bipolar structure with a base formed by UHV/CVD low-temperature epitaxy. (b) SIMS impurity profile of a 75 GHz (GeSi-base transistor (poly-Si emitter contact not shown) (after Meyerson et al., 1990).

77

2.2 Potential-Effect Devices

the neutral base region), with the highest Ge percentage (largest bandgap reduction) occurring at the base-collector junction. The smaller bandgap in the base reduces the barrier for electron injection into that region, while the bandgap grading introduces a drift field (over 15 kV/cm) to aid the transport of electrons across the neutral base. The maximum cutoff frequency of the GeSi transistor increases from 75GHz at 298 K to 94 GHz at 85 K at a collector current of 28 mA. Equally significant, the peak cutoff frequency of the homojunction Si device increases from 52 to 57 GHz for a doubling of collector current, as illustrated in Fig. 2-13. The larger relative improvement for the graded-GeSi base transistor results from the quasi-field created by the bandgap grading in the base. This field is more effective at low temperatures, and it compensates the degradation in diffusivity of the base (Grabbe et al., 1990). A combination of the high density of ULSI and the high speed capability of GeSi-based HBT technology will have dramatic impact on future electronics system applications.

2.2.7 Thyristors The thyristor is a four-layer device that has an npnp or a pnpn structure. It can be treated as two transistors, one an npn and the other a pnp, connected in series. A schematic diagram of a thyristor is shown in Fig. 2-14a. Under forward conducting conditions, both pl -pl and n2-p2 are reverse biased while nl -p2 is forward biased. When the sum of current gains a,, a2 of the two transistors becomes unity, the device is turned on to a high-conduction state. The doping profile and the currentvoltage characteristics are shown in Fig. 2-14b and c, respectively (Yang, 1988). The

z t-

z

W

100

a a

3 V

I

-

-

-

-

-

50 -

Si

3

z

X

- C L - - 4 - 4 - 4 - 4 - 4 - 4 - - *

Q

=

-

1

I

I

300 A ~ 2 1 . 0 ~ 4 wrn* .6 200 - b = O V

20

-

I

I

I

I

I

L

I

I

I

80

-

C

-

I

60 -

l3

. 2 !

40 -

20 -

Figure 2-13. Collector current dependence of f , at 298 K and 85 K for Si and SiGe devices. In both cases, the peak fT and the associated collector current increase at lower temperature (after Grabbe et al., 1990).

basis current-voltage characteristic of a p-n-p-n diode exhibits five distinct regions: 0 + 1: The device is in the forward-blocking or off state and has a very high impedance. Forward breakover (or switching) occurs where dVdZ = 0; at point 1 we define a forwardbreakover voltage V,and a switching current I,.

78

2 Silicon Device Structures

dt

.,

K

(C)

Figure 2-14. (a) Planar three-terminal thyristor. (b) Doping profile. (c) i / V characteristics with I, (gate bias current) trigger.

2: The device is in a negative-resistance region, that is, the current increases as the voltage decreases sharply. 2 + 3: The device is in the forward-conducting or on state and has a low impedance. At point 2, where dV/dl = 0, we define the holding current I , and holding voltage V,. 0 -+ 4: The device is in the reverse-blocking state. 4 -+ 5: The device is in the reverse-breakdown region. Thus, a p-n-p-n diode operated in the forward region is a bistable device that can 1

-+

switch from a high-impedance, low-current off state to a low-impedance, high-current on state, or vice versa. The device can be operated in a threeterminal mode. The turn-on behavior can be modified by increasing the gate bias current I , turning on the device at a lower breakover voltage. Another type of thyristor, called the insulated-gate bipolar thyristor (IGBT), can handle power up to 1 MW and can be turned on and off quickly. Figure2-15 shows the structure of the IGBT. The IGBT is composed of an npnp thyristor and a MOSFET that acts as a gate to control the device’s on/off mode. When a positive bias is applied to th gate, the p base is inverted into the n channel along the Si0,-Si interface, which turns the device on immediately. The device can sustain a voltage of 2000 V and can be turned on in microseconds. Turning off is faster and happens within 0.2 ps. The devices were processed on 90 cm bulk silicon material with a thickness of 350 pm. The back side emitter was formed by a shallow backside boron implantation. No lifetime-killing steps were used. The result is a 2000 V IGBT on an area of 6.5 x 6.5 mm2 with an on-state voltage of 4.5 V at 15 A. To get the high blocking voltage, two factors have to G

I

E

-T I

n-

Figure 2-15. 2000 V insulated-gate bipolar thyristor (IGBT). The gate (G) inverts p- into n-channel and switches the device to a high conduction state (Laska and Miller, 1990).

79

2.2 Potential-Effect Devices

be considered: a suitable junction termination using a poly-Si/Al field plate and a substrate with a width of 550 pm, which can sustain 2000 V. The device exhibited a turn-off time of 20011s. It can switch a shorted load up to 1800 V with a gate voltage of 20 V. The current is limited to 160 A (570 A/cm2) by the device itself (Laska and Miller, 1990).

I

L-

2.2.8 Hot Electron Transistor Basically, a hot electron transistor consists of an emitter that ejects electrons by a thermionic process, a base that controls the ejected current, and a collector that collects the current ejected ballistically from the base. In this section, two types of hot electron transistors are presented, namely the bipolar inversion-channel field effect transistor (BICFET) and the induced base transistor (IBT). Both of them can be built on a Si substrate with epitaxially grown SiGe/Si layers. The Ge,Si, -,/Si system is ideally suited for a silicon-based implementation of the p-channel BICFET because of the band lineup between unstrained silicon and commensurately strained Ge,Si, - x . Almost all of the band offset lies in the valence band, leading to a AEv = 0.37 eV for x = 0.5. Figures 2-16a and b show the charge distribution and the vertical cross section of the silicon-based BICFET band structure, respectively (Taft et al., 1989). The transistor is doped n-type, except for a very narrow region that is doped p-type. This p-type region is so narrow that there is insufficient band bending to produce a charge-neutral region of holes. However, the negative-acceptor charge sheet sets up a thermionic barrier that prevents electron flow even when a positive bias is applied to

0.0

0.5

1.0

1.5

2.0

APPLIED COLLECTOR VOLTAGE ( V 1 ( C )

Figure 2-1 6. Bipolar inversion-channel field effect transistor (BICFET). (a) Charge distribution. (b) Band diagram under bias. (c) I/V characteristics. The common-emitter characteristics are for a single-basecontact, 4 pmm BICFET (Taft et al., 1989).

the collector. The collector current is controlled by the hole quasi-Fermi level of the base region, or equivalently, the concentration of holes in the inversion channel, which can act directly to lower the barrier. The doping profile and the composition profile are also indicated in Fig. 2-16b. Before forming a two-dimensional hole gas (2DHG) in the narrow (50 A-100 A) GeSi layer, the nf-i-6p-i-n+ structure forms a triangular barrier shown in Fig.

80

2 Silicon Device Structures

2-16a. When a positive bias is applied to the collector with respect to the emitter, a 2 DHG is formed that reduces the effect of Ap (depleted negative delta charges). The reduced effect of Ap causes a barrier lowering A 4 which, in turn, increases the electron emission from the emitter. The amount of barrier lowering is

Si

(2-15 ) where Ap is the 2DHG concentration induced by VEB.The current

lOc A * T ~ ~ - ~ J o / ( ~ T ) ~ A $ / ~ T(2-16) ) The current-voltage characteristics are shown in Fig. 2-16c. The effect of VBE which induces A 4 is obvious. Because of the high conductance of the 2 DHG in the base, the device can operate at high speed and has high current handling capability. The implementation of an inducedbased transistor (IBT) ion a Ge/Si heterosystem is desirable (provided, of course, that one can achieve a high-quality interface of these lattice-mismatched materials). It makes sense to use the injection of hot holes because, unlike the conduction-band minima, the valence-band maxima are located at the same k = 0 point in both semiconductors. For a discussion of other exotic possibilities related to the IBT concept, see Luryi (1990) and Chang et al. (1986). The proposed induced-base transistor layer structure and band diagram is shown in Fig. 2-17. Layers 1-4 are GeSi, and layer 5 is undoped Si. In GeSi, the pf -i - 6n+-i2DHG forms a triangular barrier. At the GeSi-Si interface, there is a band discontinuity AE,. Holes are injected from emitter to base and traverse ballistically to the collector. The 2 DHG produces a barrier lowering, which enhances the hole emission.

6N i

E

C

A

-1

SiGe

I-Si

4

SI

2 (a)

.-

DEPLETED CHARGE SHEETS I'siZDHOLE GAS

'

G e l S i ALLOY I

I

3

5-

- 5 VLLECTOR

UNDOPED

AEv I

2h' (b)

Figure 2-17. Proposed induced-base transistor (IBT). (a) Charge distribution. (b) Band diagram (after Luryi, 1990).

2.3 Field-Effect Devices 2.3.1 Metal-Silicon Contact The first systematically studied semiconductor device was the metal-semiconductor contact (by Braun in 1874), which also happened to be the first practical semiconductor device (in the form of a point contact rectifier in 1904). In 1938, Schottky suggested that the rectifying behavior could arise from a potential barrier as a result of a stable space charge in the semiconductor. The model arising from his consideration is known as the Schottky barrier. Metal-semiconductor contacts For a collection of pioneering papers in metal-semiconductor contacts and other semiconductor devices see Sze (1991).

2.3 Field-Effect Devices

can also be nonrectifying; that is, the contact has a negligible resistance regardless of the polarity of the applied voltage. Such a contact is called an ohmic contact. All semiconductor devices as well as integrated circuits need ohmic contacts to make connections to other devices in an electronic system. The metal-silicon contact is the most extensively studied among all metal-semiconductor systems because of its importance in silicon-based devices and VLSI (very-large-scale integration) circuits. For high-barrier contacts operated at room temperature, the current transport is due mainly to thermoionic emission of majority carriers (e.g., electrons in an n-type Si) across the Schottky barrier. For lower temperatures or high doping concentrations ( > lo1* impurity atoms/cm3), field emission becomes dominant. For the classical metal-silicon contacts (e.g., Al), metals are deposited physically (e.g., by evaporation) or chemically (e.g., by chemical vapor deposition) onto a silicon surface. One potential problem is the possible contamination of the interface between the metal layer and the silicon surface. Recently, there has been a significant emphasis on the use of silicide-silicon contacts instead of the classical metal-silicon contacts. The new contacts are of interest because (1) many silicides have relatively low resistivities and, (2) silicide is formed underneath the original silicon surface and the silicide-silicon interface is generally free of oxides, impurities, or defects. Therefore, the silicide-silicon contacts are more reproducible and highly reliable. A new model for the silicide-silicon intimate contacts has been proposed based on microphysical investigations that show the existence of an interphase layer between the silicide and the silicon surface. This transition layer is responsible for the grad-

81

ual shift from silicon to metal silicide. The equilibrium band diagram of the silicide/ transition layer/silicon is shown in Fig. 2-1 8. The barrier height for the electrons in the metal, g5,,, is the Schottky barrier. From Fig. 7-18, we obtain

where +M is the metal work function, is the electron affinity, (A+)Mis the change in electrostatic potential at the metal surface, and fl is given by (2-18) where d is the transition-layer thickness (about 30 8, for a CrSi,/n-Si contact), 1 is the penetration depth in silicide (0.5 8, for CrSi,), and E, and E , are the dielectric permittivities in silicon and metal, respectively. The new model can explain the bias and temperature dependence of the current-voltage characteristics using a fielddependent barrier height as given by Eq. (2-17) (Sze, 1991).

x:O

\SILICIDE

x:d

\:RA;~ION

\

n-Si

Figure 2-18. Thermal equilibrium energy diagram for the silicide/transition layer/n-Si system (after Sze, 1991).

82

2 Silicon Device Structures

2.3.2 Homogeneous Field-Effect Transistors Homogeneous field-effect transistors include the JFET Cjunction FET), the MESFET (metal-semiconductor FET), and the PBT (permeable-basetransistor). They employ homogeneous semiconductor materials instead of heterojunctions to offer greater simplicity and ease of fabrication, because they do not depend critically on the precise control of layer thicknesses and sharp interfaces. The JFET consists of a conductive channel for current flow and two ohmic contacts. It uses the depletion region of a reverse-biased p-n junction as the gate electrode to modulate the crosssectional area of the conductive channel. The operation of a MESFET is identical to that of a JFET. The MESFET, however, has a metal-semiconductor rectifying contact instead of a p-n junction for the gate electrode. Silicon JFETs have been used extensively in many discrete and IC applications. Si MESFETs are more difficult to make than Si MOSFETs due to the great care needed to prevent native oxide formation at the metal-silicon interface. Furthermore, Si MESFETs are relatively unpopular, because they are outperformed by Si MOSFET and bipolar transistors. The Si permeable-base transistor (PBT) is a high-speed device that can be used in analog applications at microwave frequencies. In contrast to the planar homogeneous FETs such as JFET and MESFET, the PBT is a vertical device in which the current flow is normal to the Si waver surface rather than parallel to the surface. Because of lower effective electron velocity in Si, the frequency capabilities of the Si PBT are below that of its GaAs counterpart. However, the Si PBT provides a practical, high-performance microwave device that

EMITTER CONTACT

CONTACT

/

COLLECTOR CONTACT

si3 NL

Figure2-19. Cutaway diagram of a Si permeablebase transistor (after Rathman and Niblack, 1988).

has advanced fabrication technology and superior thermal conductivity. A schematic diagram of a Si PBT is shown in Fig. 2-19. Grooves are etched into an n-type Si layer, a metal (e.g., Pt) is deposited on top of the ridges and in the bottom of the grooves and then sintered to form silicide (e.g., PtSi) emitter and base contacts. Selective ion implantation is used to dope the active region and to obtain device isolation. Si PBTs with a grating periodicity of 0.32 pm have demonstrated a maximum frequency of oscillation (fmax) of 30GHz and a cutoff frequency (f,) of 22 GHz. Si PBT has very low llfnoise and excellent performance in low-noise oscillators (Rathman and Niblack, 1988). 2.3.3 MOS Structure and Charge-Coupled Devices The MOS diode is the heart of the most important device for very-large-scale integration - the MOSFET. It is also of paramount importance in semiconductor device physics. In recent years, MOS structures have been adopted for even wider applications. One example is the tactile imager for use in precision robotics applications where high packaging density and high resolution are required.

2.3 Field-Effect Devices

THIN SILICON SUPPORT BEAM

a3

DEEP BORON DIFFUSION

..... SILICUN-KIA1

1;1 A55

Figure 2-20. Fabrication of an MOS tactile imaging cell: (a) device cross section, (b) K O H etch, (c) deep boron diffusion, (d) shallow boron diffusion and dielectric deposition, (e) electrostatic bonding and final wafer etching (after Suzuki et al., 1990).

(el Figure 2-20 shows the MOS structure of the imaging cell. The force-sensitive capacitor is formed between the lower metallic plate on the glass substrate and a thick Si center plate that is supported by two thinner Si beams. When a force is applied to the top surface of the center plate, it deflects the thin beams to change the capacitive gap and hence the cell capacitance. The dielectric film over the center plate prevents electric shorts and provides buildin over-range protection when excessive force causes the plates to touch. The fabrication sequence of the tactile imager is shown in Figs. 2-20b-e. The process starts with a p-type (100) Si wafer. The wafer is oxidized and oxide mask patterns aligned to (110) are formed by HF etching. The Si islands are then created by

anisotropic etching in KOH, Fig. 2-20 b. Next, a thick oxide is thermally grown and patterned, followed by a deep boron diffusion, which defines the thickness of the center plate and the bonding islands, Fig. 2-2Oc. All oxide is removed and a third oxide is grown and patterned, followed by a shallow boron diffusion to define the supporting beams. Finally, a thin oxide and a thin nitride layer are deposited and patterned to form the protective dielectric, Fig. 2-20d. A glass substrate is metallized and patterned. The Si structure is fused to the glass substrate by electrostatic bonding. The device is placed in an EDP (ethylene diamine-pyrocatechol-water) etchant, which etches the lightly doped silicon wafer and stops at the boron p + layer, Fig. 2-20e.

84

2 Silicon Device Structures

This MOS structure is rugged and has a high damage threshold against excessive force. It operates over a wide temperature range and has a low temperature sensitivity (<30 ppmpC). A 32 x 32-element, capacitive Si tactile imager has been made; it can be read at a rate of 15 &element offering an effectiveframe rate of 5.1 ms (Suzuki et al., 1990). A charge-coupled device (CCD) is basically an array of closely spaced MOS diodes. Under the application of a proper sequence of clock-voltage pulses, the MOS diode array is biased into the deep surface depletion. By changing the potential across the array, the charge packet (representing the information) can be stored and transferred in a controlled manner across the Si substrate. To increase the clock rate and to reduce the clock voltage, an ultrafast, buriedchannel CCD with built-in drift field has been designed and fabricated. A schematic diagram of the CCD and the calculated

2.5

t t

12.5 15.0 0

10 20 DISTANCE ( pm 1

30

Figure 2-21. Step-doped, charge-coupled device with the calculated potential distribution. The barrier gate is 4 pm and the storage gate is 7 pm (after Lattes et al., 1991).

potential profile are shown in Fig. 2-21. It has 4 ym barrier gates and 7 ym storage gates. The potential gradient is permanently built into the storage gate by a step implant to improve the charge-transfer efficiency (CTE) at high clock rates. The buried channel is defined by a uniform phosphorus implant, a second phosphorus implant is added to create the storage wells. The delay lines are operated with 5 V two-phase clocks. The CCD has been tested up to 325 MHz with no degradation in CTE (> 0.99996). The equivalent CCD with uniformly doped storage wells degrades rapidly above 240 MHz (Lattes et al., 1991).

2.3.4 MOSFET 2.3.4.1 Submicrometer MOSFET The metal-oxide semiconductor fieldeffect transistor (MOSFET) is the most important device for very-large-scale integrated circuits (> lo5 components/cm2) and ultra-large-scale integrated circuits (> 107 components/cm2). It is a four-terminal device as shown in Fig. 2-22a, consisting of a p-type Si substrate into which two n f regions, the source and drain, are formed. (This is called an n-channel device. One may consider a p-channel device by exchanging p for n.) The top metal contact is called the gate. Heavily-doped polysilicon or a combination of silicide and polysilicon can also be used as the gate electrode. Because the gate electrode is used as a mask to implant the source/drain regions, it self-aligns the source/drain with respect to the gate to minimize parasitic capacitance. The sidewall oxide spacer is used to bring the source/drain ohmic contacts as close as possible to the channel without shorting the source/drain to the gate electrode.

2.3 Field-Effect Devices GATE

P

SIDEWALL OXIDE /

p-Si

b SUBSTRATE (a1 SIDEWALL OXIDE

SHALLOW n

p- si

I

(b) Figure 2-22. (a) MOSFET with sidewall spacer. (b) MOSFET with sidewall spacer and lightly doped drain structure.

The basic device parameters are the channel length L , the oxide thickness d, the p-n junction depth rj, and the substrate doping N . To reduce the channel length to the submircometer ( < 1 pm) region, various approaches have been proposed. An empirical formula has been obtained to serve as a guide for MOSFET miniaturization:

+

Lmin= 0.4 [rj d (W, Wd)2]”3(pm) (2-19)

where Lminis the minimum channel length to maintain proper device behavior, W, and Wd are the depletion widths of source and drain, with rj, W,, W, in micrometers and d in angstroms. It is apparent that in order to reduce channel length, one must reduce rj, d, and the depletion widths (Sze, 1981). As the channel length moves into the submicrometer region, one key concern is

85

the hot-electron effect, i.e., the high-energy electrons near the drain can cause threshold-voltage shift and degradation of transconductance. To minimize the hot-electron effect, “drain engineering” has been proposed. One approach is the lightly doped drain (LDD) as shown in Fig. 2-22b. The drain consists of a shallow lightly doped n region followed by a deeper nf region. By proper design of the doping and the extension of the shallow n region, one can substantially reduce the peak field near the drain, thus reducing the generation of hot carriers there (Brews, 1990). To place millions of devices in an IC package, we must reduce power dissipation. Because of its low power dissipation, CMOS (complementary MOS) technology becomes the dominant technology in which both n-channel and p-channel devices are constructed simultaneously on the same substrate. Two examples of submicrometer CMOS devices are shown in Fig. 2-23. The device shown in Fig. 2-23 a has twin wells on a p- substrate. Each well is 2 pm deep and of retrograde type formed by high-energy ion implantation. The 2.2 pm deep trenches isolate the wells. The wells are 1 pm wide and are filled with chemicalvapor-deposited SiO, on top of a 2008, thick thermal oxidation layer of the trench surface. The active regions of each device are delineated with the LOCOS (local oxidation of silicon) process. The gate-oxide thickness is 35 8,. Surface-channel nMOS and buried-channel PMOS are employed so that a phosphorus-doped n + single-gate process can be used. The use of retrograde wells and trench isolation gives the devices a high latch-up immunity. The transconductance of the 0.22 pm gate-length n- and p-MOSFETs are 450 and 330 mS/mm, and unloaded ring-oscillator delays are 36 ps at 2 V (Okazaki et al., 1990).

86

2 Silicon Device Structures P DOPED POLY-Si

(a)

PMOS

nMOS

LOW-IMPURITY-CHANNEL

EPITAXIALLY GROWN FILM

I

S i0,

n

P,

\

/

J

HIGHLY DOPED WELL

(b) Figure 2-23. (a) Cross section of sub-0.25 pm CMOS device (after Okazaki et al., 1990).(b) 0.1 pm CMOS device using low-impurity-channel transistors (after Aoki et al., 1990).

Figure 2-23b shows a 0.1 pm CMOS using low-impurity channel transistors. The impurity concentrations in the low-impurity channels are 10'6-1017cmP3, which are about two orders of magnitude lower than those of the highly doped wells. The gate-oxide thickness is 50 8,. Ultra-shallow junctions are formed at 900 "C with rapid thermal annealing to give junctions of 500A for nMOS and 10008, for PMOS. By proper choice of the thickness of the low-impurity layer, we obtain low threshold voltage (due to low-impurity concentration in the channels) and high punchthrough voltage (due to the highly doped wells). The device shows a subthreshold swing of 40 mV at 77 K (Aoki et al., 1990). The performance of CMOS circuits is limited by the low transconductance of pMOSFET. This transconductance can be

improved by increasing the hole mobility. One novel approach is to place a buried Ge,Si, - x layer under the gate of a pMOSFET as shown in Fig. 2-24a where a 100 8, Ge,Si, -, layer is grown on a Si substrate, followed by the growth of a Si spacer layer of 30-90 A, both by chemical vapor deposition. Figure 2-24 b shows the band diagram at the flatband condition for a structure with a 75 A Si spacer and a 100 8, Ge,.,Si,,, well. The quantum well for holes is created because the bandgap discontinuity between Si and Ge,Si, -,occurs predominantly in the valence band. When a negative gate voltage is applied, an inversion layer is formed in the Ge,Si, --x well as shown in Fig. 2-24c. Numerical simulations have indicated that it is desirable to employ a minium Si spacer thickness and a maximum Ge fraction to maximize the number of holes confined in the Ge,Si, -, well. Since the hole mobility in Ge,Si, --x is higher than that in Si, this MOS-gated Ge,Si, -x.Si heterostructure is expected to have higher transconductance, improving CMOS performance (Garone et al., 1990). A novel combination of CMOS and bipolar technology has recently been considered. This BiCMOS approach can combine the advantages of both technologies the speed and power-handling capability of bipolar devices with the ease of fabrication and high density of MOS devices. Figure 2-25 shows the cross section of a nonoverlapping, super self-aligned BiCMOS structure. The active areas of the bipolar transistor and MOSFETs are virtually identical. The structure allows complete silicidation of active polysilicon electrodes, reducing the parasitic resistances of the source, drain, and extrinsic base. The gate and emitter regions are protected from exposure and damage from reactive ion etching. All shallow p-n junctions are con-

2.3 Field-Effect Devices

87

ALUMINUM GATE \

30 TO 90 A 5i BUFFER LAYER tooQQQ(

n - S i SUBSTRATE

EC EF Gex Sii-, W E L L Si BUFFER

I

BULK Si

GexSii-x W E L L SI BUFFER

BULK S i

(C)

Figure2-24. (a) Cross section of an MOS-gated Ge,Si, ~x device. (b) Thermal equilibrium band diagram of the device with a 75 8, Si buffer and a 100 A Ge, 4Sio.6well. (c) Band diagram of the device when the Ge,,Si,,, well is inverted (after Garone et al., 1990).

GATE

NMOS

DSi02 POLY

S/D

tacted by polysilicon electrodes that minimize silicide-induced leakage. An arsenic buried-collector layer minimizes collector resistance. Fully recessed oxide with a polysilicon buffer layer is used to achieve low defect-density isolation. CMOS with a channel length of 1.1 pm and a width of 10 pm exhibits ring oscillator delays of 128 pslstage. The corresponding n-p-n transistor has a cutoff frequency of 14 GHz and a ring oscillator delay of 87 ps/stage. This BiCMOS structure is suitable for gigabits per second, digital VLST applications. By scaling down the device dimensions, even higher speed operation is anticipated (Chiu et al., 1991). Another novel combination is the integration of Si devices with compound-semiconductor devices using heteroepitaxial technology. However, there are many difficulties in Si heteroepitaxy. These include lattice mismatch (the lattice of GaAs is 4% larger than that of Si), mismatch in thermal

GATE BASE EMITTER COLLECTOR

-

PMOS

ALUMINUM SlLlClDE

BIPOLAR

N C - REGtON P * - REGION

Figure 2-25. Cross-sectional view of a nonoverlapping, super self-aligned BiCMOS structure (after Chiu et al., 1991).

88

2 Silicon Device Structures

expansion coefficient (2.6 times larger for GaAs), and antiphase disorder due to single atomic layer steps on a Si surface. Various approaches have been investigated to grow compound semiconductors heteroepitaxially on a Si substrate, and the viability of GaAs-based millimeter-wave integrated circuits on Si substrates has been established. Figure 2-26 depicts a cross section of a Si wafer showing GaAs MESFETs integrated with Si CMOS devices. The Si devices are fabricated first because they require higher temperatures for their formation than do the GaAs devices (Shichijo et al., 1988). It is conceivable that a monolithic integration of digital and analog devices, Si and non-Si devices, and electronic and photonic devices can be built on a Si substrate using heteroepitaxial technology. This technology will create novel system architectures and enhance overall system performance.

2.3.4.2 Silicon-on-Insulator Devices When devices are scaled down to submicron dimensions, they are also pushed closer together to increase the packing density. But close packing of devices places severe demands on isolation between devices. One solution to the isolation requirement is to build the circuit on an insulating substrate. A silicon-on-insulator (SOI) MOSFET is shown in Fig. 2-27 where a MOSFET is built on a silicon dioxide layer, so substrate isolation does not require buried n + regions as shown previously in Fig. 2-25. There are additional advantages of SO1 devices. Since there are no parasitic p-n-p-n’s in SO1 devices, there is no latch-up in CMOS circuits. The volume of the p region under the gate is much smaller than that of the conventional device, there-

TiW/Au PLASMA LPCVD OXIDE NITRIDE

\ -

I

BORON ISOLATION POLYSILICON 1

SCHOTTKY GATE

p-Si, 3’ OFF

Figure 2-26. Cross section of a Si wafer showing a GaAs MESFET integrated with Si CMOS devices (after Shichijo et al., 1988).

fore, only a limited number of electronhole pairs will be generated under radiation by high-energy particles. The SO1 devices can thus stand a much higher dose of radiation than a conventional MOSFET. When the silicon film (p region) is fully depleted, the device behavior will depend on both the top and bottom Si-SiO, interfaces. this two-sided behavior lowers the fields inside the device and tends to reduce hot-electron effects and short-channel effects. Furthermore, the subthreshold slope S can be improved in a fully depleted device. The slope S is proportioned to (1 + C,/Cox),where C, is the capacitance between the silicon surface and ground and Coxis the gate-oxide capacitance, both per unit area. For a bulk or non-fully depleted MOSFET

c, = E,/W

(2-20)

f

f

GATE

f ts1-02wn

p-

SUBSTRATE

db’0.6)~m

Figure 2-27. A MOSFET built on an insulating substrate (after Brews, 1990).

a9

2.3 Field-Effect Devices

where E , is the permittivity of Si and Wis the surface depletion width. For a fully depleted device, the capacitance C , is a series combination of the capacitances of three layers:

c,= - + - + -

(

tsi E,

db

cox

Y1

-

SILICON

-

OXIDE

S lLlC0 N

(2-21)

ES

where tSi and d, are the depleted Si film thickness and the lower oxide-layer thickness, respectively (shown in Fig. 2-27), and is the depletion width in the supporting silicon substrate. If C, from Eq. (2-21)is less than C, from Eq. (2-20), the SOT device has a lower S than the bulk device for the same C,, (Brews, 1990). The major problem in SO1 technology is the relatively poor quality of the material, since it is difficult to produce a high-quality Si film on an insulating substrate. SO1 technologies include ZMR (zone-melting recrystallization of polysilicon by using a laser beam or a strip heater), FIPOS (full isolation by porous oxidized silicon), and SIMOX (separation by implanted oxygen, i.e., implantation of oxygen ions into Si followed by high-temperature annealing to form buried SiO,). These technologies are still evolving and their success depends on further improvements in the quality of Si film. A new SO1 method has been introduced to yield ultra-thin, defect-free silicon on silicon dioxide. This technique uses epitaxial overgrowth of Si and chemical-mechanical polishing. Figure 2-28 shows the fabrication sequence. A thermal oxide (0.3 pm) is grown and a polish-stop film is formed (Fig. 2-28a). Narrow lines are opened in the exposed oxide to act as a seed area for selective epitaxial silicon growth (Fig. 2-28 b). These lines are along (100) so that a defect-free film can be obtained by an epitaxial lateral overgrowth process, i.e., the growth initiates in the seed area and

I

SILICON

I

p e wOXIDE

1

SILICON

1

Figure 2-28. Fabrication sequence for producing Sion-insulator (SOI) structures using epitaxial lateral overgrowth and chemical-mechanical polishing (after Shahidi et al., 1990).

grows vertically and laterally over the oxide, as shown in Fig. 2-28 c. Chemical-mechanical polishing is used to thin the film. The polishing process is stopped when the polish pad reaches the polish-stop film. This process produces a SO1 film thickness that is determined by the polish-stop film thickness (Fig. 2-28 d). The quality of the SO1 film is equivalent to bulk silicon, and the basic device characteristics are comparable to those resulting from fabrication on bulk. However, because SO1 devices have better isolation and lower parasitic capacitance, ring oscillator measurements on the SO1 film have shown significant speed improvement over the bulk devices (e.g., 30ps versus 120ps for 0.5 pm channel length devices operated at 2 V) (Shahidi et al., 1990).

2.3.4.3 Thin-Film Transistors Thin-film transistors (TFTs) are MOSFETs fabricated by depositing amorphous or polycrystalline semiconductors on largearea glass or other insulating substrates. Because of their lower costs, TFTs are potentially very useful for active-matrix liq-

90

2 Silicon Device Structures

uid-crystal displays, printer heads, and image sensors. Figure 2-29a shows a cross section of a polysilicon TFT. The polysilicon films are deposited on an insulating substrate using standard low-pressure chemical vapor deposition techniques. Typically, they have a fine-grain structure of the order of 0.05 pm in diameter. To increase the grain size, lowtemperature seed selection is used by means of an ion-channeling technique. A Si ion implantation can make the deposited polysilicon film amorphous but a few (1 10) oriented grains survive the implant due to the ion channeling effect. When annealed at about 625 "C, the amorphized polysilicon film recrystallizes from the surviving grains via a solid-phase epitaxy process. Much larger grains, in excess of 1 pm, can be obtained. When the channel dimensions are reduced to the same size as the grain size, the TFT characteristics improve dramatically. A comparison of the mobilities for small and large grain sizes is shown in Fig. 2-29 b. Note the substantial increase in mobility for devices with large grains, especially with very small channel dimensions. Mobilities as high as 70 cm2 V - ' s-' and ON/OFF ratios larger than lo8 have been obtained in 2 pm devices (Yamauchi et al., 1991).

2.3.4.4 Nonvolatile Memory Nonvolatile memories are MOSFETs with modified gate electrodes to enable semipermanent charge storage inside the gate. At present, nonvolatile memories such as the EPROM (erasable programmable read-only memory) and the EEPROM (electrically erasable programmable read-only memory) constitute about 10% of all MOS IC scales. The first nonvolatile memory had a floating gate (not connected to external

Al-Si

n' POLY-Si

/

Al-Si

SPUTTERED 302

LPCVD POLY-Si

VD = 0.5V 150

SMALL GRAIN

LL LL W

n

_I

F

o-t0 o

-

-1r-70

CHANNEL DIMENSION W = L

2-5

(lm)

(b) Figure 2-29. (a) Cross section of a polysilicon thinfilm transistor. (b) Field-effect mobility in large and small grain polysilicon film as a function of channel dimensions (channel length = channel width) (after Yamauchi et al., 1991).

voltage) sandwiched between two insulating layers, Fig. 2-30a. When an appropriately high field is applied through the outer control gate, charge carriers transport through insulator 1 and charge the floating gate, giving rise to a threshold voltage shift. Such a device can function as a bistable, nonvolatile memory, because the charges are stored even after the charging field is removed due to a much lower probability of back-transport. If avalanche injection of electrons (near the drain) is used to charge the floating gate, we have a FAMOS (floating-gate

2.3 Field-Effect Devices INSULATOR 2

91

CONTROL GATE

(a) PA' V C l l c

' sio2

22

c avalanche injection MOS) nonvolatile memory (Fig. 2-30b). Since there is no outer gate electrode, the initial equilibrium condition can be restored by illuminating the device with ultraviolet light or exposing it to X-ray radiation. A MIOS (metal-insulator-oxide-semiconductor) memory device, shown in Fig. 2-30c, has a double-dielectric (AI-Si,N,Si0,-Si) structure. The charge carriers can tunnel through SiO, and are stored at the Si,N,-SiO, interface. Nonvolatile memories are now moving towards higher densities, faster access times, scaled-down cell sizes, lower power consumption, and lower voltage operation (e.g., 5 V for microcomputer systems). A triple-dielectric structure (Fig. 2-30d) has been proposed. Charge transport and storage can be modeled by using two-carrier (electrons and holes) injection simultaneously at both the Si-bulk and gate-electrode boundaries via Fowler-Nordheim or direct tunneling. In the case of low-voltage operations ( f 5 V), a projected 10 year lifespan and lo6 cycles are obtained for a device with dimensions of 20 8, for the tunnel oxide, 50 8, for the nitride, and 35 8, for the blocking oxide (Libsch and White, 1990).

Figure 2-30. Nonvolatile memory devices. (a) Floating gate. (b) FAMOS. (c) MIOS. (d) Triple-dielectric structure (after Libsch and White. 1990).

A novel nonvolatile memory cell has been made based on microelectromechanics. A schematic diagram of the memory cell is shown in Fig. 2-31. The memory cell has a micromachined, conductive membrane in the form of a bridge. The bridge is longitudinally stressed so that it can buckle upward or downward and is therefore mechanically bistable. The cell is fabricated using a modified MOS process. Silicon substrate is covered with a thin, insulating thermal oxide and a spacer layer of 1.5 pm polysilicon. The polysilicon is selectively masked and the unmasked areas are implanted heavily with boron; the implanted

L

,METAL

Figure 2-31. Schematic drawing of a microelectromechanical, nonvolatile memory cell based on a bistable bridge (B), a spacer (S), and the substrate (SUB) with lateral electrodes (L) fafter Holg, 1990).

92

2 Silicon Device Structures

areas are the etch-stop areas. The bridge material is a thermally grown SiO, layer covered by a 20 8, Cr layer, and the bridge is defined by photolithography and etching. The bridge is released by partly etching away the polysilicon spacer with EDP (ethylene diamine pyrocatechol solution). The etched channels are defined by the boron etch-stop mentioned above. The bistable bridge performs the memory function. The two logic levels are defined by the two stable states: the bridge bending upward or downward. The write function corresponds to the switching of the bridge between the two states. Switching to either state is done electrostatically by applying a voltage between the bridge and the substrate or the lateral electrodes. The read function is done by sensing the capacitance between bridge and substrate. Thus, the memory cell is nonvolatile and fully immune to an electromagnetic field, and the stored data can be retained permanently. Switching voltages around 30 V have been achieved; lower voltages are expected. Since the fabrication technology for the bridge is close to a standard MOS process, we expect that the microelectromechanical memory cells can be integrated monolithically with microelectronic read/ write circuits to form a full memory device (Holg, 1990).

We have used a Ge,Si, - x strained layer to fabricate the Si-based MODFET (modulation-doped FET) in which a two-dimensional electron gas is formed at the GeSi-Si heterojunction interface. The layers are grown at an epitaxy temperature of 600 "C on a (100) Si substrate using the Si MBE system. A schematic cross section of the layered structure is shown in Fig. 2-32a. A Geo,25Sio.,5buffer layer is deposited on a high resistivity (lo4Q cm) p-type Si substrate. The subsequent layers consist of an undoped Ge,Si,-, graded layer with x varying from 0.5 to 0 within the 1008, width, and, finally, an undoped Si top layer of 100 8,. Source and drain ohmic contacts

SOURCE

GATE

DRAIN

Ge0.25Si0.75 0.2 m

T

BUFFER LAYER

S i - SUBSTRATE

Sb DOPING SPIKE

2.3.5 MODFET Ev

In Sect. 2.2 we have considered the Ge,Si, -,/Si system. A Ge,Si, -, layer can be grown epitaxially on a Si substrate as a strained layer without interfacial misfit dislocations as long as the thickness of the Ge,Si, -,layer is less than the critical thickness (e.g., for x = 0.2, the critical thickness L , is 1600 A, and for x = 0.5, L , is 140 A).

p 0 0 . i +1ooA

+1ooA+2ooA

1 - 5 1 Ge,Sil-, GeaQias GRADED LAYER

+2000AI-SI

Gea2sSio.n BUFFER LAYER

(b) Figure 2-32. (a)Cross section of a GeSi/Si MODFET structure. (b) Band diagram of the n-channel MODFET at thermal equilibrium (after Daembkes et al., 1986).

2.3 Field-Effect Devices

are formed by thermal evaporation of AuSb. The gate is formed by electron-gun evaporation of a Pt/Ti/Au sandwich of 1000 A/IOOO A/1500 A thickness. The gate length and width are 1.6 and 160 pm, respectively, and the drain-to-source spacing is 5 pm. A schematic band diagram of the nchannel MODFET is shown in Fig. 2-32 b. A 2 DEG is formed in the undoped Si layer adjacent to the Geo,,Sio., layer. Because of the Ge,Si, -,graded layer we avoid the formation of a second quantum well near the surface. The device shows good FET characteristics with a transconductance of 70 mS/mm. The mobility is 1550 cm2 V - ' S - ' near the heterojunction interface. The cutoff frequency is 2.2 GHz. These values are all higher than those of a comparable Si MESFET, indicating the improved transport properties of electrons in the MODFET. Various device optimizations can be made so that the device can have substantially higher transconductance and higher cutoff frequencies. The Si n-channel MODFET can be combined with Si p-channel MODFET to form highperformance Si complementary-logic circuits (Daembkes et al., 1986). A MODFET consisting of p-Geo,,Sio,,/ Ge/Geo,,,Sio,,, with a strain-controlled Ge channel can be fabricated by MBE. A cross section of such a device is shown in Fig. 2-33. A 0.5 pm Geo,75Sio,,5buffer layer is grown on a (100) Ge substrate by MBE. A thin Ge film (200A) and a thin Ge,.,Si,,, film (150 A) are commensurably grown on the buffer layer. For the doping, Ge atoms are adsorbed on the Geo,,Sio,, surface. Finally, a Geo,,Sio~,film (150 A) is deposited. The strain at the heterointerface between p-Geo,,Sio., and Ge is controlled by the Ge,Si,-, buffer layer. By proper choice of x one can maximize the valence-band discontinuity at the heteroin-

si02

93

(5008) \

1- f

2D-HOLE GAS

Al

AuGo

\\\\\\\\\

----- Geo.sSio.s- - - -- GeXSii-, BUFFER LAYER

l50A 1508 2ooA

0.5 I r n

MISFIT SUBSTRATE

Figure 2-33. Cross section of a strain-controlled Gechannel MODFET (after Murakami, 1991).

terface and enable sufficient confinement of the two-dimensional hole gas. The x value is chosen to be 0.75 to give maximum hole mobility. The p-channel MODFET has a ultra-high hole mobility of 9000cm2 V - ' S - ' at 77 K (Murakami, 1991).

2.3.6 Microvacuum Field Emitter One of the major limitations of highspeed semiconductor devices is the carrier velocity saturation due to scattering effects. The carrier velocity in a vacuum, on the other hand, can be substantially higher and is only limited by relativistic effects. Therefore, a microvacuum devices become an important area of study. Figure 2-34a shows a microvacuum triode with molybdenum field-emission cathodes, and a close-spaced Si anode that is made by microfabrication technology. The anodes are fabricated from a (100) p + silicon wafer. A thermal oxide, 2 pm thick, is grown on the wafer. The oxide is then lithographically patterned with 1.25 mm wide lines on 2.5 mm centers parallel to the (1 11) plane. This pattern is transferred by anisotropic etching of Si using KOH to the depth required for emitter-to-anode spacing (up to 20 pm).After dicing, the silicon anode chip is positioned so that the SiO, straddles the emitting area. The anode is

94

2 Silicon Device Structures

-------_-- v,

0

= 120

_i 200

100

Va (VOLTS1

(b) Figure 2-34. (a) Microvacuum triode with closespaced Si anode. (b) Current-voltage characteristics of the microvacuum triode (after Holland et al., 1990).

supported by a layer of SiO, resting on the gate electrode. Electrical contact is made to the back of the Si anode chip, which is coated with TiW. BUILT-ON-ANO\DE

’’

/

I 1 ‘ c -

--

Figure 2-34b shows a set of currentvoltage characteristics for a triode that has an emitter-to-anode spacing of 8 pm. The measured transconductance is 1 pS for a cathode with 2500 emitters. The average tip current is 4 nA per emitter. The transit time is 4 x 1 0 - l ’ ~at 60 V. The advantage of the Si anode is that much lower anode voltage is required due to the small anodeto-emitter spacing. However, additional studies are needed to improve the transconductance and the emitter current (Holland et al., 1990). Figure 2-35 shows the cross section of a Si avalanche cold cathode. The device is fabricated on a (100) p-type Si epitaxial wafer ( 4 n c m ) grown on a p + substrate. The emission current is measured with a stainless steel anode at a distance of 1 mm from the cathode. Standard IC processing, including implantation of B, As, and P, is used to fabricate the cold cathode. The As peak is located at a depth of 120 A, and the junction depth is 300 A. When the device is reverse-biased to avalanche breakdown, the reverse current I increases linearly. The emission current I D also increases approximately linearly with increasing I,. The emission efficiency q is defined as I E / ( I D I,). For a single cathode with a 40 pm diameter, a reverse bias of 6.2 V, and an anode voltage of

+

..

p EPILAYER

p’ SUBSTRATE

=

METAL

~i02

nsi

Figure 2-35. Cross section of a Si avalanche cold cathode device (after Ea, 1990).

95

2.4 Quantum-Effect Devices

500 V, q is 2 x lo-’. The anode voltage can be lowered to 1 V and the emitter efficiency can be increased when the anode is replaced by cantilevered polysilicon beam to be constructed at a distance of 1-2 p from the emitting cathode as shown by the dashed line in Fig.2-35. Because of the small area (2x20pm2) of the proposed cantilevered polysilicon beam anode, the expected capacitance is a fraction of a picofarad, thus subpicosecond transit-time operation is posible (Ea, 1990).

2.4 Quantum-Effect Devices

well, quantum wire and even quantum dot. For example, a resonant tunneling device was fabricated (Takeda et al., 1990), and the multiple quantum-well structure revealed a n excellent infrared detection capability (Kesan et al., 1990). A resonant hotelectron transistor has also been fabricated (Rhee et al, 1989). All these devices will be presented in the following sections.

2.4.2 Quantum Wells, Wires, and Dots In the three-dimensional case, the energy E versus wave vectors k I,k i l can be expressed as

2.4.1 Introduction The quantization effect in field-effect transistors was first observed in a MOSFET in 1966 (Fowler et al., 1966). A twodimensional electron gas (2DEG) in nMOSFET and a two-dimensional hole gas (2DHG) in p-MOSFET are present in the triangular potential well right next to the SiO, -Si interface. Modern lithographic technology can fabricate a MOSFET with a channel length and width of 0.1 pm. For such a small channel, we can find only “one” interface state in the channel, if the interface state density is 10” states/cm2. Recently, single-electron trapping was observed. Employing the quantum wire as the channel of a MOSFET, e.g., a MOSFET with a channel length of 1 pm and a channel width of 10 nm, revealed many interesting physical insights (Pepper, 1990). In addition, using resonant tunneling phenomena, different kinds of structures can be made such as the effective-mass filter (Gennser et al., 1990), energy filter (Gennser et al., 1990), and the wave function filter (Rajakarunanayak, 1989), etc. Recent developments in GeSi technology can be employed to fabricate quantum

(2-22) where k I is the wavevector perpendicular to k l l and m , and m l l are the effective masses in the corresponding directions. However, in a quantum well a standing electron wavefunction is formed. This implies a quantized energy in this direction ( z in real space and k l l in reciprocal space). The wavevector k l Iis

In: k l l = - 1=1,2,3 ) . . . (2-23) Lz The E - k relation in a band (conduction or valence band) is given by hZk t hZ E ( k ,, 1) = -+ 122m, mllL2,

(2-24)

The low dimensionality can be further reduced to one dimension and to zero dimensions, in which the transverse wavevector k I is further quantized. Generally, the density of states (DOS) in d dimensions can be found. The number of states per unit volume in k-space is (2 x ) ~ , where d = dimensionality. The total number of states 2 in volume &(d) in k-space is (2-25)

96

2 Silicon Device Structures

In a multivalley semiconductor, using iJv for the valley degeneracy,

The energy-k relation is given by

for isotropic effective mass m. Therefore, the DOS per energy E to E+dEis

= 1.587 x

10"(~)(~)/(cm2meY)

for (100) Si e(E)=-=dE

-

dk dk states/( V d')energy) (2-26)

= 2.8 x 10'O/(cm2 meV) for GaAs In a one-dimensional system

For example, in a three-dimensional (3D) system, a free-electron-like gas has spin

dZ 8xk2 dk ( ~ I T dE h2k -=dk. m -=-

k

=

d Z- - 4 dk -27c

) ~

(2-29)

(2 m E)12 h 212 m 3 2 E12

Q3D(E)

=

7c2h3

(2-27)

In 3D, the DOS is proportional to the square root of energy. In a two-dimensional (2 D) system,

- -

-~ mll

h2kil nh2 The DOS is independent of energy.

(2-28)

In a zero-dimensional (OD) system, the DOS becomes a delta function located at each quantized state. The DOSs of 3D, 2D, 1D, and OD systems are shown in Fig. 2-36. Realizations of a 2 DEG or 2 DHG in a Si system have been shown previously. However, a quantum-wire-channel MOSFET, shown in Fig. 2-37a, has also been fabricated (Takeda et al., 1990). There are two gates, the first and the second, fabricated by electron-beam lithography. Their widths were both varied from 0.1 pm to 1.0 pm. The channel length from source to drain is approximately 2 pm. The second gate, which has a 10 nm gate oxide, creates the narrow conducting channel. In Fig. 2-37 b, the transconductance g,( = aI,,/a VFG) is found to show oscillatory behavior and negative differential resistance, which implies a resonant transport.

97

2.4 Quantum-Effect Devices FIRST GATE

B"'v I

I

..

\ ,';

-4 -VS 5 vVG

i

I 0.1 ps

i.

E

lu poDu 2

i = l

+.-I

0

3

(C 1

QUANTUM DOT

i =

1

3 4 5

(d

-

E,Ei

1

I

4.2 K I

I

2

1

,v,

I

(V 1

(b)

Figure 2-36. Density of states in (a) 3 D, (b) 2 D, (c) 1 I),and (d) 0 D systems.

Figure 2-37. Quantum wire channel MOSFET: (a) device structure; (b) transconductance oscillation in narrow Si inversion layers.

The quantum-dot structure can be fabricated by the following process steps. As shown in Fig. 2-38, thin layers of Si and GeSi are deposited on a Si substrate by MBE or a UHV/CVD process. After a mesa etching, an SiO, layer can be formed by a low-temperature oxidation step such as high-pressure oxidation (HIPOX) or plasma-enhanced chemical vapor deposition (PEVCD). Finally, a narrow metal gate strip is formed on the top oxide. If the dimensions L,, L,, L , are smaller than the

de Broglie wavelength (about 200 A at 300 K), a quantum dot is formed.

2.4.3 Resonant-Tunneling Diode The quantized states in a double-barrier quantum well (DBQW) are shown at the left in Fig. 2-39. The resonant phenomenon is analogous to the resonant transmission of light through a Fabry-Perot etalon. In DBQW, an electron wave behaves like a light wave.

98

2 Silicon Device Structures ,GATE

W

INVERSION LAYERS (QUANTUM WIRES 1

METAL

Figure 2-38. Structure of a quantum dot.

LY

Consider an electron at energy E incident on the one-dimensional DBQW structure. When E matches one of the energy levels Ei in the QW, the amplitude of the electron de Broglie waves in the QW increases due to multiple scattering, and the waves leaking in both directions cancel the reflected waves and enhance the transmitted ones. Near resonance one has (Luryi, 1990)

where Tl and T, are the transmission coefficients of the two barriers at the energy E = Ei and y = h/z is the lifetime width of the resonant state [quasi-classically,y z Ei

(Tl = T,)]. In the absence of scattering, a system of two identical barriers (TI = T2)is completely transparent to electrons entering at resonant energies and the transmission coefficients, plotted against the incident energy, have a number of sharp peaks, as shown at the right in Fig. 2-39b. A GeSi/Si double-barrier resonant-tunneling diode (DBRTD) was fabricated (Rhee et al., 1988). Figure 2-40a shows the energy barrier diagram in the valence band. Figure 2-40 b is the current-voltage characteristic ( I - V ) in which a resonant tunneling peak can be clearly observed around 300 meV at both 4.2 K and 77 K. The peak is due to the transmission through the light-hole ground state Elht (higher energy not shown).

B

0.8

Y

0.6

a

w

z w

0.4

.---

u

L

id

zY

c z w

i -- 1 uo 9 V

10-4

10oA

Si

GexSii-x

Figure 2-39. Double-barrie1 resonant-tunneling diode (DBRID): (a) quantized states in the well; (b) transmission coefficient vs. energy E (after Luryi, 1990).

Si

I 0-8

TRANSMISSION COEFFICIENT

5

2.4 Quantum-Effect Devices

index confinement region that permits effective waveguiding in the silicon overlayer. A silicon ridge was used as the waveguide. A multiple quantum well (MQW) layer was imbedded in a p-i-n structure as shown in Fig. 2-41 a. The 40 8, Si,,,Ge,,6/210 A Si, 28-period layer is equivalent to an average Ge composition of 10%. The response of the detector as a function of wavelength at 10 V reverse bias and at room temperature is shown in Fig. 2-41 b. A 50% internal quantum efficiency was obtained at 1.1 pm wavelength with an impulse response time of 100 ps (Kesan et al., 1990).

I

84-

c

99

2-

z w

2.4.5 Resonant-Tunneling Hot-Electron Transistor

a [L

3 0

u 0

8 -.

I

I

I

-800 -400 -200

I

I

200 400 DC VOLTAGE (mV)

0

800

(b) Figure 2-40. (a) Schematic band diagram of the double-barrier diode. For the structure used in this experiment, W, = W, = 50 A, W, = 40 A, and x = 0.4. (b) Observed current-voltage characteristics for the structure at three different temperatures (after Rhee et al., 1988).

The heavy-hole ground state Ehhl can only be seen by dI/dV or d2i/dV2 measurement because of the large tunneling effective mass. At higher bias a second peak occurred at 900 meV in the dl/dV measurement due to the first excited heavyhole state EhhZ(Rhee et al., 1988).

2.4.4 Multiple Quantum Well Detector The Si-Ge heterostructure makes the realization of a Si-based 1.3 pm long wavelength optoelectronic detector possible. Silicon-on-insulator (SOI) structures are used. The buried-oxide layer forms a low-

When a double-barrier resonant-tunneling diode (DBRTD) is imbedded in a structure, as in p + (Ge,,,Si,,,)-DBRTDP+ (Geo.5Sio.5) base-i (Ge,, 2Si,, &p (Ge,,,Si, ,6), a hot-electron transistor (HET) is formed. The HET exhibits negative differential resistance (NDR) in its current-voltage (I- V ) characteristics (Rhee et al., 1989). Because of its high-speed tunneling capability and negative differential resistance, integration of such a device into Si-based circuits could find applications in high-speed digital circuits, frequency multipliers, multistate logic circuits and tunable oscillator/ amplifiers. The HET samples were grown on highly doped p-type
100

2 Silicon Device Structures r

Si/SiGe MULTIPLE QUANTUM

WELL ABSORBING REGION

EMITTER

1-1

t

UNDOPED Ge,Sin lOOnm P'- Ge.4Si.s 1200 nm

1

p * - Si ( 100 1 SUB.

\ \

HH

'LH

DETECTOR RESPONSE ( LIGHT WAVEGUIDE 1 - l O V BIAS

h'

--

-a -

70

E 50

(C)

2 30

z -

(THOUSANDS) WAVELENGTH ( A 1

(b) Figure 2-41. (a) Schematic view of a photodetector consisting of an MQW absorber integrated into a rib waveguide-P-i-N structure showing both device geometry and epitaxial layer structure. (b) Internal quantum efficiency vs. well length for the structure in (a) (after Kesan et al., 1990).

10

0

400 800 1200 1400 VBC (mV1

Figure 2-42. The resonant-tunneling hot-electron transistor: (a) cross-sectional view of the GeSi resonant-tunneling hot-hole transistor. (b) Schematic band diagram of the transistor under bias when resonant tunneling occurs through the light-hole ground state in the quantum well. (c) I- V characteristics (after Rhee et al., 1989).

2.4 Quantum-Effect Devices

tor and the collector barrier consists of layer. A 10008, a IOOOA Ge,,,Si,,, Ge,,,Si,,, base is inserted between the double-barrier quantum-well emitter and the collector barrier. The doping concentration is about 1 x lo', cm-3 throughout the device except for the collector barrier and the double-barrier resonant-tunneling structure, which are undoped. Substrate temperature was held at about 530 "C during the growth. The emitter and base contacts were obtained using selective wet etching and standard photolithographic techniques. The valence-band offsets and boundstate energy of the light-hole ground state in the quantum well is shown schematically in Fig. 2-42b. For convenience, the hole energy was taken to be positive. All the values are given with reference to the valence-band edge of the unstrained Ge,,,Si,,, layers. The collector barrier and the resonant-tunneling double barriers in the emitter are subjected to an in-plane tensile strain that causes the heavy-hole band edge to be above the light-hole band edge. In the base, the heavy-hole band edge is below the light-hole band edge due to the compressive strain. In the unstrained Ge,,,Si,,, layers, the light-hole and heavyhole bands are degenerate. The light and heavy holes moving from the collector to the base have to overcome 106meV and 155 meV barriers, respectively. On the other hand, the light and heavy holes see barrier heights of 137 meV and 208 meV, respectively, from the base to the collector. Due to the degenerate light- and heavyhole bands in the collector, the majority of the current from the collector to the base is from light holes because of the lower lighthole barrier height. The effective barrier height from the collector to the base is 106 meV as seen by the light hole and 208 meV from the base to

101

the collector as seen by the heavy hole. An asymmetric I - I/ characteristic between the base and the collector is evident as a result of the unequal barrier heights. In the double-barrier quantum-well emitter, the barrier heights for the light and heavy holes are 211 meV and 315 meV, respectively. There are three bound states for the heavy hole and one bound state for the light hole in the quantum well. The negative differential resistance of the device is due to the light-hole tunneling through the light-hole ground state located 61 meV from the bottom of the well. Figure 2-42 b shows the band diagram under an external bias. When the emitter is biased positively with respect to the base, holes are injected into the base through the double-barrier resonant-tunneling emitter with an excess hole energy relative to the valence-band maximum of the Ge,,,Si,,, base. The holes injected into the base are then transported near-ballistically to the collector. The 1000 8, Ge,,,Si,,, collector barrier prevents injection of the holes initiated from the valence band of the base to the collector when V,, is applied, but allows transport of the injected hot holes from the emitter to the collector if the hot holes have higher energies than the collector barrier height. In Fig. 2-42c, a set of collector currents (I,) is shown as a function of the base-collector voltage (VBc) at 77 K, with VEB as a parameter. The rightmost curve corresponds to VEB = 0 and the others are obtained for an incremental step of 0.2 V. At V,, = 0, no negative differential resistance (NDR) is observed because a large portion of the collector current comes from the base. As the emitter bias is increased, the injection current from the emitter becomes the dominant source of the collector current and he NDR increases with VEB.

102

2 Silicon Device Structures

2.5 Microwave and Photonic Diodes

ity of Si-based optical sources (Luryi and Sze, 1987). 2.5.1 IMPATT Diode

The most important Si microwave diodes are the IMPATT diode and the BARITT diode. They provide high-power7hight-efficiency, or low-noise operations from I GHz to the millimeter-wave band. Although Si tunnel diodes have been made, the device performance is inferior to that of GaAs tunnel diodes due to Si's relatively large effective mass for tunneling. There is no Si transferred-electron diode, because the satellite valley in the Si conduction band is located 1.1 eV above the bottom of the conduction band, too high for intervalley transfer of electrons. Si photonic devices include the Si photodetectors, which detect optical signals through electronic processes, and Si solar cells, which furnish the power for satellites and space vehicles as well as for terrestrial applications. No Si optical sources have been developed yet, because Si has an indirect bandgap. It is conceivable, however, that certain Si-based materials may have direct bandgaps, thus opening the possibil-

N

The IMPATT (impact ionization avalanche transit time) diode is one of the most powerful solid state sources of microwave power. It can generate the highest CW (continuous wave) power at millimeter-wave frequencies, and is used most extensively in that frequency range (30 to 300 GHz). Si IMPATT diodes are superior to GaAs IMPATT diodes in the millimeterwave frequency range because Si has a smaller energy relaxation time, which results in faster response to impact ionization when an electric field is applied. In addition, Si has a higher thermal conductivity for better heat dissipation. The basic members of the IMPATT diode family are the single-drift devices and the double-drift devices. Figure 2-43 shows the single-drift IMPATT diodes in which only one type of charge carriers (i.e., electrons) traverses the drift region. Figure 2-43a shows the doping profile and electric field distribution at the avalanche

N

W - X

A b

€

-x 0 XA

w

(a)

Em\r:;;:: ~x

0 XA

w

(b)

Em\

BE,,,, -5.

0 XA

w

(C)

-X

Figure 2-43. Doping profiles and electric-field distributions at the avalanche breakdown condition of three singledrift IMPATT diodes: (a) one-sided abrupt p-n junction, (b) hi-lo structure, and (c) lo-hi-lo structure (after Sze, 1990).

2.5 Microwave and Photonic Diodes

NL

103

N. E

E

t

n+ ,

N. E

N. E

I W

0 (C)

X

Figure 2-44. Doping profiles and electricfield distribution of four double-drift IMPATT diodes: (a) flat profile, (b) hi-lo structure, (c) lo-hi-lo structure, and (d) hybrid structure (after Sze, 1990).

(d1

breakdown condition of a one-sided abrupt p-n junction. The avalanche multiplication process occurs in a narrow region near the highest field between 0 and x. Figure 2-43 b shows a hi-lo structure in which a high doping N , region is followed by a lower doping N , region. With proper choice of the doping Nl and its thickness b, the avalanche region can be confined within the N , region. Figure 2-43c is the lo-hi-lo structure, in which a “clump” of donor atoms is located at x = b . Since a nearly uniform high-field region exists from x = 0 to x = b, the avalanche region is equal to b, and the maximum field can be much lower than that for the hi-lo structure. Figure 2-44 shows double-drift devices in which both electrons and holes participate in device operation over two separate drift regions. The double-drift devices have higher efficiency and higher output power than single-drift devices. Figure 2-44 a illustrates the doping profile and electricfield distribution of a two-sided abrupt p-n junction. The avalanche region is located near the center of the depletion layer. Fig-

ure 2-44b shows a double-drift hi-lo structure that consists of a lo-hi structure on the p-side and a hi-lo structure on the n-side. Figure 2-44c shows a double-drift lo-hi-lo structure, the avalanche region is given by the distance between the p + clump and the n’ clump. Figure2-44d shows the double-drift hybrid structure in which the p side has a flat doping profile but the n side has a hi-lo profile. The selection of a particular device structure depends on many factors, such as the operating frequency, the CD-to-AC conversion efficiency, power output, and ease of fabrication. The double-drift lo-hilo structure (Fig. 2-44c) is expected to have the highest efficiency, but it is also the most difficult to fabricate. The double-drift hybrid structure (Fig. 2-44d) is a good compromise, since it has good efficiency and is relatively easy to make. Of course, the simplest structure is the single-drift p-n junction (Fig. 2-43 a). For lower-frequency operation, Si IMPATT diodes are fabricated using diffusion, chemical vapor deposition, or ion implantation processes to form the n-type

104

2 Silicon Device Structures

and p-type layers. At higher frequencies, especially in the millimeter-wave region, the layer thickness becomes very small. At these frequencies, we must use molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD) to control the doping and layer thickness precisely. State-of-the-art Si IMPATT diodes have CW power output of about 10 W at 10 GHz, 1 W at 100 GHz, and about 0.1 W at 200 GHz. The conversion efficiency is a constant value of 15% up to IOOGHz, then it decreases to 1% at 200 GHz (Sze, 1990).

2.5.2 BARITT Diode The BARITT (barrier injection transit time) diode is also capable of operating in the millimeter-wave frequency region with substantially lower noise, but also with lower power output than the IMPATT diode. BARITT diodes are particularly useful for applications in self-mixing oscillators where the minimum detectable signal power level can be 30 dB below that of IMPATT diodes. The BARITT diode is basically a backto-back pair of p-n junctions or metalsemiconductor diodes biased into a reachthrough condition. Figure 2-45 a shows a Si pf-n-pf structure. When a voltage is applied to the device, one junction is forward biased and the other is reverse biased. When the voltage is above the reachthrough condition, the BARITT diode has the electric field profile shown in Fig. 2-45 b. The point xRcorresponds to the potential maximum for minority-carrier (holes in this case) injection; the point x, separates the low-field drift region from the saturation-velocity drift region as shown in Fig. 2-45 c.

+

-

n W

0

ELECTRIC FIELD

I

INJECTION REGION

DRIFT REGION

(b) DRIFT VELOCITY

t

"I-/, 0 LOW-FIELD REGION

W SATURATED +VELOCITY i REGION

X

X R XS

4

Figure 2-45. Device cross section, field distribution, and carrier drift velocity of a BARITT diode (after Sze, 1990).

State-of-the-art Si BARITT diodes have CW power output of 100 mW at 10 GHz, and about 1 mW at 60GHz. Typical efficiencies are in the range of 0.5 to 2% (Sze, 1990).

2.5.3 Photodetectors Si photodetectors include the p-i-n photodiode and the avalanche photodiode (e.g., hi-lo or lo-hi-lo structures similar to those shown in Fig. 2-43 b and c). The conventional Si photodetectors are useful in the wavelength range from 0.6 to 0.9 ym, where nearly 100% quantum efficiency (i.e., number of electron-hole pairs generated per incident photon) has been ob-

2.5 Microwave and Photonic Diodes

tained from devices with antireflection coatings (Sze, 1981).Recently, many novel Si photodetectors have been designed exhibiting excellent photoresponse from the near-ultraviolet to the far-infrared region In addition, heteroepitaxial technology has been used to form Si-based, monolithic optoelectronic integrated circuits that combine 111-V compound photodetectors and MESFET with Si integrated circuits on a Si substrate. Figure 2-46 a shows a cross-sectional view of a single pixel of a 160 x 244-element focal plane array in which a frontilluminated PtSi Schottky-barrier photodetector is connected with a charge-coupled device (CCD). The photodetector is fabricated on a p-type (100) Si wafer using electron-beam evaporation to deposit a

105

10 8, thick Pt film in an ultrahigh vacuum system and subsequent annealing in situ at 400°C to form a 20 %, PtSi (the barrier height of PtSi/p-Si is 0.18 eV). An n-type guard ring surrounding the periphery of the silicide is utilized to suppress edge leakage. Electrons generated by illumination are accumulated on the PtSi electrode and are subsequently transferred to the CCD channel. The quantum efficiency, as a function of wavelength, of a photodetector reversebiased to 5 0 V and at 50K is shown in Fig. 2-46 b. For wavelengths 2 1 pm, corresponding to photon energies below the bandgap of Si, the photodetector response is produced by carriers generated by absorption of light in the PtSi film. The quantum efficiency is 3% at 1.5 pm and de-

uv VIS'BLE .-

CCD TRANSFER GATE

BURIED C C D CHANNEL

GUARD RING

(a) 100.

< t

I

I

I

1

I

1

10-

P V

z

w

G

1-

LL

LL W

I 3 L I2

5

Q 3

0.1 0.01

-

d

0.001 I 0

I

1

I

I

I

I

2 3 4 5 WAVELENGTH I urn

(b)

I

6

J

7

Figure 2-46. (a) Schematic diagram of a single pixel of a 160 x 244-element PtSi focal-plane array operated in the frontillumination mode. (b) Quantum efficiency as a function of wavelength (after Tsaur et al., 1990).

106

2 Silicon Device Structures

creases to 0.01% at 6.3 pm. For shorter GeS i '?' i02 wavelengths, the quantum efficiency increases drastically, because the radiation can transmit through the 20A PtSi film and is absorbed by the Si substrate to generate carriers that contribute to the photoresponse. The quantum efficiency is 60% at 0.8 pm, remains essentially constant down to 0.4 pm, and then decreases to 35% at 0.3 pm. Using this photodetector and CCD readout circuitry, very large, highly uniform focal-plane arrays have been demonstrated. Such an array is useful for remote sensing and imaging applications (Tsaur et al., 1990). A Ge,Si, -,./Si heterojunction internal photoemission detector has been investigated. This Si-based far-infrared photodetector has a quantum efficiency of 3-5% in :: 4006 I the 8-12 pm region. Figure 2-47a shows '10' t. +40008 2 V the structure of a p+-GeSi/p-Si detector. The device is fabricated on a p-type (100) Si substrate. The pf-GeSi layer is grown in a MBE system with a base pressure of 3 x 10-l' Torr. The substrate is heated to 500-600°C and Ge and Si are coevaporated from two electron-gun sources. The GeSi layer thickness ranges from 100 to 4000 A, the Ge composition ranges from 0.2 to 0.4, and the boron doping concentration ranges from loi9 to 4 x lo2' ~ m - ~ . Figure 2-47. Device structure of a p+-GeSi/p-Si photodetector. (b) Energy band diagram of the The energy band diagram is shown in photodetector. (c) Quantum efficiency of two GeSi/Si Fig. 2-47 b. Infrared radiation is absorbed photodetectors as a function of wavelength (after Lin in the p+-GeSi layer, the photoexcited and Maseyian, 1990). holes are emitted over the GeSi/Si heterojunction barrier into the Si by internal photoemission. Strong infrared absorption in turn, reduces the heterojunction barrier is achieved in the p'GeSi layer due to free q 4 B given by carrier absorption and intra-valence-band (2-31) q & = AE, - ( E , - E ) (in eV) transitions. The heterojunction band alignThe cutoff wavelength I , [1.24/(q &)I will ment for the GeSi/Si system is essentially of type 111, that is, most of the band-edge diftherefore increase. ference appears at the valence band. By Figure 2-47c shows the quantum effidecreasing the Ge composition, we can reciencies of two GeSi/Si photodetectors as a duce the valence band offsets A E v , which, function of wavelength. For both detec-

-

-

2.5 Microwave and Photonic Diodes

tors, the GeSi layers have the same Ge content of 0.3 and the same total quantity of boron, but for detector A, the layer thickness is 400 A, and for detector B, the layer is 10 times thicker. The thinner layer of detector A allows more photoexcited holes to reach the interface before undergoing inelastic scattering, resulting in higher quantum efficiency. In addition, the higher doping concentration of detector A reduces the effective potential barrier because its Fermi level moves further below the valence band, and thus extends the photoresponse to 10 pm. By optimizing the thickness, composition, and doping concentration of the GeSi layer, significantly improved quantum efficiencies are expected (Lin and Maseyian, 1990). Another Si-based photodetector is the InGaAs/InP detector for the 0.9-1.7 pm wavelength. The detector is fabricated on a Si substrate by a heteroepitaxial process. This approach allows monolithic integration of photonic and electronic devices on a single Si substrate. Figure 2-48 shows the cross section of the photodetector. A Si wafer (4” off (100) orientation) with a GaAs layer grown by the MOCVD process serves as the starting material. The hydride vapor-phase epitaxial technique is used to deposit seven 1 pmthick Tn,Ga,p,As layers with x ranging from 0.07 to 0.49 in equal steps to accommodate the 3.8% mismatch with GaAs. A final 5 pm thick Ino,53Gao,4,As layer is

107

deposited to serve as the optical absorption layer, followed by a 1 pm thick InP layer, which serves as the high-bandgap passivation “window” layer. Planar p-i-n photodetectors with 75 pm diameter are then fabricated by conventional processes using Zn diffusion. For a reverse bias of 5 V, the quantum efficiency at 1.3 pm is 85% and the capacitance is 1.1 pF. The detectors have been life-tested at 125 “C and - 5 V. No increase in room temperature dark current has been observed after 2000 h, indicating that the detectors are quite reliable (Olsen, 1990). 2.5.4 Solar Cells

There have been dramatic increases in the Si solar cells’ conversion efficiency in the past few years. Most of these increases have originated from improved cell structures and processing techniques, rather than improved Si quality. Figure 2-49 a shows a schematic diagram of a passivated emitter and rear cell, which shows a high efficiency of 23.1 ‘YOunder AM 1.5 spectrum (i.e., an air mass 1.5 condition with the sun at 45” above the horizon; these conditions are an energy-weighted average for terrestrial applications). We note that the cell structure is quite different from that of the conventional solar cell. The front side has an invertedpyramid surface texture to trap the incident light. A heavy n f diffusion under-

Figure 2-48. In,,,Ga,,,,As/ InP compositionally graded photodetector on a Si substrate (after Olsen, 1990).

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2 Silicon Device Structures

Figure 2-49. (a) Schematic diagram of a passivated emitter and rear cell (after Green, 1990).(b) Schematic diagram of a solar cell with 26% efficiency at the 90 sun, AM 1.5 condition (after Cuevas et al., 1990).

neath the top metal contact helps to minimize series resistance and increase opencircuit voltage. The top surface oxide is 250 8, thick, and a MgF,/ZnS double-layer antireflection coating (not shown) is applied. On the bottom surface, a thermally grown oxide passivates most of the surface. Nonalloyed ohmic contact is made at isolated contact holes through the passivating oxide. In order to have a low contact resistance, relatively low-resistivity Si should be used (e.g., e = 0.2 f2 cm). The cell thus incorporates a highly reflective planar rear surface. The calculated reflectance of this layer is above 97% (Green, 1990). Figure 2-49 b shows a similar cell with efficiency of 21.7% at 1 sun (AM 1.5 condi-

tion) and 26% at 90 suns concentrated light, 25"C, AM 1.5 condition. The cell consists of an undoped (or moderately doped n-type) substrate with imbedded point p + and n + islands. The SiO, used to mask the boron and phosphorus diffusions passivates the undoped surface and also acts as an antireflection coating. The percentage of silicon area that is contacted is 1% for the p + and 2% for the n f materials. The metal grid is arranged in a chevron pattern that aligns on the triangular ridges (Cuevas et al., 1990). Progress has also been made on a polycrystalline Si solar cell. Efficiency as high as 17.8% has been obtained under a 1 sun AM 1.5 condition. A passivated-emitter solar cell is shown in Fig. 2-50. The cell incorporates two novel treatments. The first is the phosphorus pretreatment in which phosphorus is diffused into the polycrystalline silicon. The enhanced diffusion of phosphorus along the crystallographically poor regions (grain boundaries) converts areas which would otherwise be minority carrier sinks into useful collection regions. The second is the rear aluminum treatment. Aluminum, like phosphorus, is also found to exhibit enhanced diffusion

Figure 2-50. A passivated-emitter polysilicon solar cell with anti-reflection (AR) Zoating (after Narayanan et al., 1990)

109

2.6 Outlook

along grain boundaries. The aluminum treatment can increase both the open-circuit voltage and short-circuit current. These treatments in gettering the substrate and nullifying the deleterious effects of grain boundaries have improved the performance of the less expensive polysilicon solar cell to nearly match that of singlecrystal devices. Using a surface-texturing approach similar to that shown in Fig. 2-49 may further increase the eficiency (Narayanan et al., 1990).

2.6 Outlook As the technology of microelectronics advances, the feature size becomes smaller. Figure2-51 shows that, in the year 2000, the MOSFET’s gate length may be reduced to 0.2 pm, gate-oxide thickness to 4nm, and junction depth to 0.04pm. Simultaneously, bipolar transistors that have a base width of 50 nm in 1990 may be reduced to 30 nm in the year 2000 by using a heterojunction GeSi approach. Consequently, cost and performance improvement will be tremendous. In 2000,256 Mbit (- 3 x lo8 components/chip) DRAM will be available with a gate delay of only 30 ps,

Table 2-1. Performance projection. Year

Minimum feature length

1960

1991

2000

25

0.7

0.2

(PI Component density (devices/cm*) Gate delay (ns) Power-delay product (pJ) Wafer size (mm)

8 x i06 0.03

1

500 10000

25

0.1 0.03 0.01 0.0003 200 250

compared to 500 ns in 1960. Power-delay products will also profoundly improve from 10000 pJ in 1960 to 0.0003 pJ by the year 2000. These projections are summarized in Table 2- 1. Figure 2-52 shows the evolution of circuit complexity versus year. MOSFET has the highest complexity. Bipolar still maintains its momentum but levels off after 1990. MESFETs and MODFETs are still in their development stage, however, their momenta are extremely high high enough to challenge MOSFETs in the future. A combination of the high complexity of Si-based devices with the high-speed capability of GaAs devices will create new system applications for the future computer, ~

30 10

1

0.1

1o o o i

0.01

loo8

0.004 1960

408 1970

1980

YEAR

1990

2000

Figure 2-51. Dimension scaling of MOSFETs and bipolar junction transistors vs. time.

110

2 Silicon Device Structures

LT

w

BIPOLAR

a cn

....TRANSISTOR

+ z

MESFET

W

z

0

a H

103

i MODFET

0 0

1960

1 1970

I 1980

t 1990

I 2000

2010

YEAR Figure 2-52. Evolution of VLSI circuit complexity.

communication, and high-quality entertainment equipment such as high-definition television (HDTV), which may use heteroepitaxy of GaAs on Si technology. On the other hand, work on GeSi strained layers on Si is attracting a lot of attention. Using narrower bandgap GeSi material for the base of bipolar transistors makes the device speed competitive with that of heteroepitaxy of GaAs on Si. A commensurate GeSi layer on Si is much more suitable to realize the heterojunction bipolar transistor, which will have an extraordinary impact on both Si and GaAs technologies. In order to mass produce these devices beyond the year 2000, low-temperature process technologies are required. Otherwise, the diffusion of the constituent materials will seriously affect device performance, especially when the channel length of MOSFETs is reduced to 0.1 pm and the base width of bipolar transistors is reduced to 30nm. The growth of Si or GeSi epitaxially at a temperature lower than 550 "C has already been achieved (Meyerson, 1986). Deposition temperatures for poly-Si or poly-SiGe,

oxide, nitride, and even the annealing temperature should be lowered accordingly, preferrably to below 800°C. Table 2-2 presents the possible low-temperature processes for future ultra-large-scale integration (ULSI). Therefore, there are callenges to many professionals including the physicist, chemist, materials scientist, and electronics and device engineer to work together towards solutions. Advances in Si technology such as Si micromachining have created many new applications, which include microvacuum and micro-electromechanical systems (Fan et al., 1989). New sensors, transducers, actuators, and even new kinds of field-emission devices such as field-emission displays (Spindt, 1989) and high-power distributed microwave vacuum triode arrays using field-emission types have been developed (Kosmahl, 1989). We anticipate that Sibased devices will remain the dominant semiconductor devices in the foreseeable future.

Table 2-2. PossibIe low temperature technologies for future ULSI circuits. Feature

Technologya

Epitaxial or poly Si, UHVjCVD, MBE, LRP, SiGe LPCVD Oxides and interfaces Plasma treatment, UV ozone, Hipox Nitrides CVD-PECVD, photo-CVD, LPCVD, Metals (and silicates) Sputtering CVD Contacts Non-alloy, LT-EPI, with RTA Junctions TRP, RTA, LT-EPI a Abbreviations: UHV, ultra-high vacuum; CVD, chemical vapor deposition; MBE, molecular beam epitaxy; LPR, limited reaction process; LPCVD, low pressure chemical vapor deposition; UV, ultraviolet; HI POX, high-pressure oxidation; PECVD, pfasma-enhanced chemical vapor deposition; LT, low temperature; EPI, epitaxy; RTA, rapid thermal annealing; RTP, rapid thermal processing.

2.8 References

2.7 Acknowledgements This Chapter is dedicated to the memory of Mrs. Cheng-Hwei Wu Chang, C. Y. Chang's wife, who passed away during our writing of the manuscript. We wish to thank Mr. N. Erdos who did the technical editing of the Chapter, Ms. B. L. Huang who typed the initial draft and the final manuscript, and Mr. T. Z . Jung who furnished the technical illustrations.

2.8 References Allyn, C. L., Gossard, A. C., Bethea, C. G., Levine, B. F. (1980), Appl. Phys. Lett. 36, 373. Aoki, M., Ishii, T., Yashimura, T. (l990), IEEE Int. Electron Device Mtg. Tech. Digest, pp. 939-941. Bean, J. C. (19781, Appl. Phys. Lett. 33, 654. Brews, J. R. (1990), in: High Speed Semiconductor Devices: Sze, S. M. (Ed.). New York: Wiley, pp. 139-210. Chang, C. Y., Luryi, S., Sze, S. M. (1986), IEEE Electron Device Lett. 7, 497. Chen, T. C., Toh, K . Y., Cressler, J. D. (1989), IEEE Electron Device Lett. 10, 344. Chiu, T. Y., Chin, G. M., Lan, M. Y (1991), IEEE Trans. Electron Devices 38, 141. Cuevas, A., Sinton, R. A,, Midkiff, N. E. (1990), IEEE Electron Device Lett. 11, 6. Daembkes, H., Herzog, H. J., Jorke, H. (1986), IEEE Trans. Electron Devices 33, 633. Ea, J. Y (1990), IEEE Electron Device Lett. 11, 403. Fan, L. S., Tai, Y. C . , Muller, R. S. (1989), IEEE Trans. Electron Devices 35, 724. Fowler, A. B., Fang, F. F., Howard, W. E., Stiles, P. J. (1966), Phys. Rev. Lett. 16, 901. Garone, P. M., Venkataraman, V., Sturni, J. C. (1990), IEEE Int. Electron Device Mtg Tech. Digest, p ~ 383-386, . 5877590. Gennser, U., Kesan, V. P., Iyer, S. S., Bucelot. T. J., I Vac. Sci. Tech. B 8 , 210. Yang, E. S. (1990), . Gibbons, J. F., Gronet, C. M., Williams, K. E. (1985), Appl. Phys. Lett. 47, 721. Grabbe, E. F., Patton, G. L., Stork, J. (1990), IEDM 17. Green, M. A . (1990), IEEE Trans. Electron Devices 37, 331. Grinberg, A. A,, Luryi, S. (1981), Appl. Phys. Lett. 38, 810.

111

Holg, B. (1990), IEEE Trans. Electron Devices 37, 2230. Holland, C. E., Rosengreen, A., Spindt, C. A. (1990), IEEE Int. Electron Device Mtg. Tech. Digest, pp. 977-982. Jwo, S. C., Chang, C. Y. (1986), IEEEElectron Device Lett. 7 , 689. Kasper, E. C., Bean, J. C. (1989). Silicon Molecular Beam Eppituxy. Bocd Raton, FL: CRC Press, Chaps. 2, 4. Kazarinov, R. F., Luryi, S. (1982), Appl. Phys. A 38, 15. Kesan, V. P., May, P. G., Bassous, E., Iyer, S. S. (1990), IEDM. Kosmahl, H. G. (1989), IEEE Trans. Electron Devices 36, 2728. Laska, T., Miller, G. (1990), IEDM, 807. Lattes, A. L., Munroe, S. C., Seaver, M. M. (1991), IEEE Electron Device Lett. I2, 104. Libsch, F. R., White M. H. (1990), Solid-State Electron 33, 105. Lin, T. L., Maseyian, J. (1990), Appl. Phys. Lett. 57, 1422. Liu, H. C., Landhear, M., Buchanan, M., Hougton, D. C. (1988), Appl. Phys. Lett. 52, 1809. Luryi, S. (1985), Physica 134B, 466. Luryi, S., (1990), in: High Speed Semiconductor Devices: Sze, S. M. (Ed.). New York: Wiley. Luryi, S., Szc, S. M. (1987), in: Silicon Mokculur Beam Epitaxy: Kasper, E., Bean, J. C. (Eds.). CRC Uniscience, pp. 251 -288. Malik, R. J., Aucoin, T. R., Board, K., Wood, C. E. C., Eastman, L. F. (1980), Electron. Lett. 10, 836. Meindl, J. D. (1984), IEEE Trans. Electron Devices 31. 1555. Meyerson, B. S. (1986), Appl. Phys. Lett. 48, 797. Meyerson, B. S., et al. (1990), IEEE Int. Electron. Device Mtg. Tech. Digest, p. 21. Murakami, E. (1991), IEEE Electron Device Lett. 12, 71. Narayanan, S., Wenham, S. R., Green, M. A. (1990), IEEE Trans. Electron Devices 37, 382. Okazaki, Y., Kobayashi, T., Miyake, M . (1990), IEEE Electron Device Lett. 11 ( 4 ) , 134. Olsen. G. H. (1990), IEEE I n t . Electron. Device Mtg. Tech. Digest, pp. 145-147. Pearce, C. W. (1988), in: Y L S ITechnology: Sze, S. M. (Ed.). New York: McGraw-Hill, pp. 9-45. People, R (1985), Appl. Phys. Lett. 47, 322. People, R., Bean, J. C. (1986), Appl. Phys. Lett. 48, 538. Pepper, M. (1990), in: Proc. Int. Electron Devices Symp., EDMS '90. Hsinchu, Taiwan, R.O.C.: NCTU, p. 465. Rajakarunanayak, Y. (1989). Appl. Phys. Lett. 55, 1537. Rathman, D. D., Niblack, W. K. (1988), IEEE M T T S Intl. Microwave Symp. Digest, Vol. 1. Piscataway, NJ: IEEE, pp. 537-540.

112

2 Silicon Device Structures

Rhee, S. S., Park, J. S., Karunasiri, R. P. G., Ye, Q., Wang, K. L. (1988), Appl. Phys. Lett. 53, 204. Rhee, S. S., Chang, G. K., Carns, T. K., Wang, K. L. (1989), Int. Electron Device Mtg., p. 651. Rhee, S. S., Chang, G. K., Carns. T. K., Wang, K. L. (1990), Appl. Phys. Lett. 56, 1061. Shahidi, G., Davari, B., Taur, Y., Warnock, J. (1990). in: Proc. IEEE Int. Electron. Device Mtg. Shichijo, H., Matyi, R. J., Taddiken, A. H. (1988), IEEE Intl. Electron Device Mtg. Tech. Digest, pp. 778 -781. Smith, C. G., Pepper, M. (1989), J Phys. Condens. Matter 1. 9035. Spindt, C. A. (1989), ZEEE Trans. Electron Devices 36, 225. Suzuki, K., Najafi, K., Wise, K. D. (1990), ZEEE Trans. Electron. Devices 37, 1852. Sze, S. M. (1981), Physics of Semiconductor Devices, 2nd ed., New York: Wiley. Sze, S. M. (1985), Semiconductor Devices: Physics and Technology. New York: Wiley. Sze, S. M. (Ed.) (1990), High Speed Semiconductor Devices. New York: Wiley, p. 425, pp. 521 -585. Sze, S. M. (Ed.) (1991), Semiconductor Devices: Pioneering Papers. Singapore: World Scientific. Sze, S. M., Gibbons, G. (1966), Solid-state Electron, 9, 831. '

Taft, R. E., Plumer, J. D., Iyer, S. S. (1989), Int. Electron Device Mtg., p, 55. Takeda, E. (1990), IEEE Int. Electron. Device Mtg. Tech. Digest, p. 389. Tsaur, 3 . Y., Chen, C. K., Mattia, J. P. (1990), IEEE Electron Device Lett. 11, 162. Turner, G. W. (1988), Proc. Mat. Res. SOC.Symp. 116, 179. Yamauchi, N., Hajjar, J. J., Reif, R. (1991), IEEE Trans. Electron Devices 38, 55. Yang, E. S. (1988), in: Microelectronic Devices. New York: McGraw-Hill.

General Reading Sze, S. M. (1981), Physics of Semiconductor Devices, 2nd ed. New York: Wiley Sze, S. M. (1985), Semiconductor Devices: Physics and Technology. New York: Wiley. Sze, S. M. (Ed.) (2990), High Speed Semiconductor Devices. New York: Wiley, p. 425, pp. 521 -585. Sze, S. M. (Ed.) (1991), Semiconductor Devices: Pioneering Papers. Singapore: World Scientific. Yang, E. S. (1988), Microelectronic Devices. New York: McGraw-Hill.

3 Silicon Device Processing Dim-Lee Kwong Microelectronics Research Center. Department of Electrical and Computer Engineering. The University of Texas at Austin. Austin. TX. U.S.A.

List of 3.1 3.2 3.2.1 3.2.2 3.3 3.3.1 3.3.2 3.3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.5 3.5.1 3.5.2 3.5.2.1 3.5.2.2 3.5.2.3 3.5.2.4 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.7 3.7.1 3.7.2 3.7.2.1 3.7.2.2 3.7.2.3 3.7.2.4 3.7.2.5

Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Gettering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Intrinsic Gettering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 122 Gettering by Hydrogen Annealing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 LOCOS-Based Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 126 Advanced Isolation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Silicon-on-Insulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate Dielectrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 136 Preoxidation Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Process Dependence of Gate Oxide Quality . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Chemically Modified Gate Oxides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 CVD and Stacked Oxides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shallow Junction Formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 146 Ion Implantation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Techniques for p+-n Junction Formation . . . . . . . . . . . . . . . . . . . 148 149 Diffusion from Doped Deposited Layers ............................ 153 Gas Immersion Laser Doping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Gas Phase Diffusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Plasma Immersion Ion Implantation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metallization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 155 Gate Electrodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Planarization for Multilevel Interconnections . . . . . . . . . . . . . . . . . . . . . . . . . 169 Cluster Tool Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Rapid Thermal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 In Situ Dry Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 180 Interface Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate Stack of Nitride and Oxynitride . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 181 Deposition of DRAM Storage Dielectrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Selective Deposition Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

114

3.7.2.6 3.7.2.7 3.7.2.8 3.7.3 3.8

3 Silicon Device Processing

Ultra-Shallow Junction Formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Integrated CMOS Processing Based on RTP . . . . . . . . . . . . . . . . . . . . . . . . . Ge,Si, -, /Si Heteroepitaxy by RT-CVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Wafer Integrated Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

182 183 183 185 186

List of Symbols and Abbreviations

List of Symbols and Abbreviations

xj

capacitance interface density of states diffusivity x time breakdown electric field effective electric field Preston coefficient effective length surface doping concentration pressure charge-to-breakdown resistance removal rate relative velocity temperature time time-to-breakdown effective oxide thickness threshold voltage flatband voltage shift junction depth

Peff

effective electron mobility

ajc AHF APCVD ASIC BESOI Bi-CMOS BOX BPBL BPSG BSG CMOS CMP CVD cz DCS DI DMAH DOF DZ ECR

amorphous/crystalline anhydrous H F atmospheric pressure chemical vapor deposition application specific integrated circuit bond and etch-back silicon-on-insulator bipolar complementary metal oxide semiconductor buried oxide bird’s beak controlled poly-buffered local oxidation of silicon boropolysilicate glass borosilicate glass complementary metal oxide semiconductor chemical-mechanical polishing chemical vapor deposition Czochralski (wafers) dichlorosilane distilled dimethylaluminum hydride depth of focus denuded zone electron cyclotron resonance

c

Dit Dt Ebd Eeff

K L f f Nsurf

P Qbd

R drldt dsldt T t lbd

‘ox, eff

VT

A Vfb

116

3 Silicon Device Processing

EG fab FET FIPOS GIDL GILD GO1 HBT HTO IG IPA LICT LOCOS LPCVD LTO MCZ MOS MOSFET MQW NCL OISF ON ON0 PBL PBR PELOX PI11 PMOS POlY PSG RAM RCA RESSFOX RIE RLS-PBL RTA RTCVD RTMP RTN RTO RTP SACVD SADS SALICIDE SCVDW

extrinsic gettering fabrication facility field effect transistor full isolation by porous oxidized silicon gate induced drain leakage gas immersion laser doping gate oxide integrity heterojunction bipolar transistor high temperature oxides intrinsic gettering isopropyl alcohol low-impurity-channel transistor local oxidation of silicon low pressure chemical vapor deposition low temperature oxides magnetic Cz metal oxide semiconductor metal oxide semiconductor field effect transistor multiple quantum well nitride-clad local oxidation of silicon oxidation induced stacking faults oxide/nitride oxide/nitride/oxide poly-buffer local oxidation of silicon poly-buffer recessed polysilicon encapsulated local oxidation plasma immersion ion implantation p-channel MOS polysilicon polysilicate glass random access memory Radio Corporation of America recessed sealed sidewall field oxidation reactive ion etching reverse L-shaped sealed poly-buffer localoxidation of silicon rapid thermal annealing rapid thermal chemical vapor deposition rapid thermal multiprocessing rapid thermal nitridation rapid thermal oxidation rapid thermal processing subatmospheric pressure CVD silicon as diffusion source self-aligned silicide selective CVD tungsten

List of Symbols and Abbreviations

SEG SILO SIMOX SIMS SMD SOG

so1

SRAM SRO SST STI SWAMI TDDB TEOS TIBA ttv UHVCVD ULSI VLSI

selective epitaxial growth sealed interface local oxidation separation by implantation of oxygen separation by implantation of silicon surface micro-defects spin-on glass silicon-on-insulator static RAM stress relief oxide sealed sidewall trench shallow trench isolation sidewall mask isolation time-dependent dielectric breakdown tetraethyl orthosilicate triisobutyl aluminum total thickness variation ultra-high vacuum chemical vapor deposition ultra-large scale integration very-large scale integration

117

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3 Silicon Device Processing

3.1 Introduction Demand for low cost, high speed integrated circuits with large on-chip functionality has necessitated the scaling down of device dimensions in MOS ICs. Reduction in channel length of a MOSFET increases its drive current capability, which is necessary for faster switching of capacitive loads. Moreover, scaling down of device dimensions is desirable in order to obtain higher levels of integration on a chip. Such high levels of integration can lead to a higher on-chip functionality in logic applications and a higher storage capacity in memory applications. Over the last ten years, silicon devices have progressed from micron into deep-submicrometer dimensions. As we begin the era of sub-0.5 pm fabrication, conventional device structures and fabrication techniques are reaching their physical limitations. Therefore, device and process designs, together with new materials must be developed to maximize the gain in performance, yet at the same time meet the increasingly stringent reliability requirements. This chapter covers semiconductor process technology for CMOS devices. It provides a comprehensive survey of some of the key process technologies involved in manufacturing state-of-the-art CMOS devices. These include device isolation, gate dielectrics, shallow junctions, and metallization. Emerging technologies in these areas that have received considerable attention in recent years from the research and development community are also included. Areas that will need significant improvement and changes for the future to comply with the device downscaling while maintaining reliability goals will be discussed. In addition, since dry etching and trench structures are increasingly being used in device fabrication, gettering tech-

niques which supply gettering sinks closer to the active device region are required to control and eliminate serious contamination problems. Furthermore, the use of larger size wafers and the more stringent requirements for process performance, reliability and cost have driven the move from batch processing to single wafer, integrated processing where large size single wafers are processed and sequential process steps can be “clustered” into multichambered in situ processing modules or into linked cells of independent modules. Finally, as we continue to reduce the thermal cycle, rapid thermal processing becomes an attractive direction in sub-0.5 pm processing.

3.2 Gettering Because of intense competition in manufacturing quality and cost, together with increasingly complex fabrication processes, ULSI manufacturing will require profound effort to cut down defect generation due to unintended contamination. By the year 2000, the number of discrete process steps in the manufacturing of advanced DRAM chips is expected to exceed 700. Significant efforts are required towards defect reduction of any given processes and equipment. Highly mobile transition metals have been identified as one of the main contaminations that degrade device yield and reliability. These fast-diffusing transition metals can nucleate or decorate extended crystalline defects (dislocations, stacking faults, precipitates, etc.) and form deep level defects, which generate leakage currents and lifetimekilling recombination, or silicide precipitates which cause junction shorts and oxide breakdown. The effects of Fe, Cu, Ni, and Cr impurities on junction leakage,

3.2 Gettering

SiO, film breakdown, and MOS C-t characteristics have been studied extensively (Ohsawa et a]., 1990). In general, Fe increases the junction leakage current at the periphery isolated by LOCOS and causes the gate SiO, breakdown by lowering the potential barrier height at electrode-SiO, interfaces. Cu, Ni, and bulk Fe generate weak spots in the oxide in the form of crystal defects, causing gate oxides breakdown. In addition, these defects also degrade MOS C-t characteristics. Fe decreases the generation lifetime and increases the surface generation velocity at concentrations above 5 x 10l1 cm-’, while Ni reduces generation lifetime even at concentrations as low as lolo cm-’. Transition metal atoms in silicon generally occupy interstitial and substitutional lattice sites, and diffuse via predominantly interstitial diffusion through the open diamond lattice (Weber, 1988). This interstitial diffusion is very fast, as it does not depend on the presence of native lattice defects, and has typical activation energies of the order of 0.4-1.8 eV, as shown in Table 3-1 (Weber, 1990). Although precautions, such as wafer surface cleaning procedures, clean room conditions, and the purity of water and other chemicals, can reduce the level of contamination, they cannot exclude accidental metal contamination. Gettering is a technique which effectively removes heavy metals from the Table3-1. Diffusion coefficients of 3d metals in intrinsic silicon.

Ti Cr Fe co Ni

cu

Do (cm2/s)

AH,,, (eV)

T range (“C)

1.45 x lo-’ 1.0 xlO-z 1.3 10-3 9.0 X I O - ~ 2.0 x 4.7 10-3

1.79 1 .0 0.68 0.37 0.47 0.43

950 1200 900-1250 30-1250 900- 1100 800-1300 400- 700 -

119

active device regions. It is a necessary insurance policy for high device yields, because it allows to considerably increase the level of accidental contamination which can be tolerated. Extrinsic gettering (EG) employs external treatments to create either extrinsic or intrinsic defects to getter metallic impurities. These include: phosphorus diffusion (Seidel, 1975), ion implantation (Seidel, 1979, mechanical damage (Mets, 1965), and polysilicon deposition (Chen, 1982). Both substitutional and interstitial impurities can be collected near the backside of the wafer and gettering occurs during high temperature annealing. In the case of intrinsic gettering (IG), extrinsic or intrinsic defects are already present in as-grown materials or are produced or activated by annealing. Because extrinsic gettering techniques have several limitations, such as lack of stability and gettering process induced side effects, more focus has been on intrinsic gettering.

3.2.1 Intrinsic Gettering The gettering process removes metal impurities from active device regions by (1) release of the impurities to be gettered; (2) diffusion of the impurities to the region where they are gettered; and (3) capture of the impurities by extended defects (stacking faults, dislocations or precipitates). The intrinsic material properties of Czochralski (Cz) grown wafers (e.g., interstitial oxygen, substitutional carbon, Si vacancies, Si interstitials, dopant point defects, as grown precipitates and stacking faults, etc.) are used to induce bulk oxygen precipitation by the formation of SiO, (xx 2) complexes. Due to the lower density of Si in SiO, as compared to bulk silicon, these SiO, precipitates generate silicon lattice disorder and dislocations that act as gettering sites (traps) for unwanted impu-

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3 Silicon Device Processing

rities (Tan, 1977). Also associated with the formation of SiO, precipitates is the ejection of silicon interstitials (Si,), which can enhance the migration/diffusion of the impurities to the gettering sites. For effective IG, both a denuded zone (defect-free area) in the device active region and gettering sites in the bulk of the wafer away from the active region must be formed. Intrinsic gettering of interstitial transition metals in silicon can be achieved using following sequence of heat treatments (Gupta and Swarroap, 1984): Step 1 : Denudation: Annealing at a high temperature (above 1100°C) to form the denuded zone by out-diffusion of oxygen from the region near the wafer surface; Step 2: Nucleation: Annealing at a low temperature (below 700 "C) to homogeneously nucleate oxygen precipitates; Step 3 : Growth: Annealing at a high temperature (above 1000"C) to accelerate the growth of oxygen precipitates. The first high temperature annealing step causes interstitial oxygen to out-diffuse from the wafer surface. This reduces the oxygen concentration in a several tens of micrometers thick layer below the surface towards the solubility at this out-diffusion temperature. Heat treatments for a few hours at temperatures above 1100"C in inert or oxidizing ambients are very effective for denuding. A surface oxide cap is recommended at this step to protect the wafer surface from possible contamination and pitting. However, a pure oxidizing ambient is not recommended because, during high temperature oxidation, excess Si, is ejected at the oxidizing front, resulting in a supersaturation of Si, in the bulk. This makes the free energy of formation for

SiO, precipitates thermodynamically unfavorable, leading to oxidation induced stacking faults (OISF) and retardation of bulk SiOx precipitation (Hu, 1980). In the subsequent nucleation step the supersaturation of oxygen in this subsurface layer is no longer sufficient to form stable nuclei. However, nuclei will be formed in the interior of the crystal. These oxygen clusters, after reaching a critical size, will grow during the third annealing step. Gilles et al. (1990) have studied the lowtemperature Fe precipitation kinetics in Cz-Si. They proposed a mechanism for intrinsic gettering based on impurity saturation and precipitation during the gettering process. The model shows that the gettering efficiency depends on the difference between the precipitation kinetics of the impurity species in the denuded zone and in the bulk. This model allows optimization of the gettering temperature for a given impurity and contamination level. If there is a sufficient density of heterogeneous nucleation sites for impurity precipitation, the gettering process is uniquely determined by the diffusion coefficient of the interstitial impurity, the width of the denuded zone, and the cooling rate or temperature which is used for the gettering process. The relevance of oxygen to integrated circuit fabrication is primarily due to the ability of oxygen to form oxide precipitates and to generate lattice defects in a controlled manner for impurity gettering during device processing. In addition, the presence of interstitial oxygen in silicon gives an added strengthening effect to the silicon lattice, which can prevent plastic deformation and slip during wafer thermal processing. In precipitation gettering, care must be taken to avoid over-precipitation, which would "drain" interstitial oxygen from the silicon lattice. The reduction of

3.2 Gettering

interstitial oxygen lowers wafer’s yield strength and would make it more susceptible to plastic deformation when subjected to thermal gradients. The net results are wafer warpage, and generation of slip dislocations into active device regions. A wide range of oxygen concentrations have been applied in IC device processing (ASTM, 1988), depending on the nature of thermal processing and sensitivity of the device to gettering/defect generation. In general, for device processing technologies in which gettering by precipitates is essential, high or medium oxygen concentrations are needed. When the device performance is more sensitive to lattice defects, the oxygen related defect formation is intentionally avoided by using Si wafers such as magnetic CZ (MCZ) wafers with low oxygen and low microdefect density. In ULSI device manufacturing, it is essential to “engineer” oxygen precipitation to occur at the right locations and at the right time through tight control of wafer oxygen concentration and/or tailoring of thermal process strategically. Depending on oxygen level and thermal cycle sequence, the precipitate distribution in the wafer cross-section can be classified into four categories, as shown in Fig. 3-1 (Lin, 1990). Figure 3 - l a is an ideal configuration where a denuded zone in the device active region and gettering sites in the bulk of the wafer away from the active region are formed. Figure 3-1 b is a non-perfect denuded zone formation due to local precipitation enhancement. This effect is caused by grown-in microdefects or local oxygen concentration fluctuations. The configuration shown in Fig. 3-1 c corresponds to uniform oxygen precipitation with no oxygen out-diffusion during gettering, resulting in no denuded zone formation. This may be caused by using a mismatched thermal cycle. The precipi-

121

Denuded zone Precipitate

zone

Figure 3-1. Schematic wafer cross-sections showing various denuded zone and precipitate zone distributions during IC processing.

tates and bulk stacking faults can intersect the device active surfaces and cause gate oxide integrity (GOI) degradation. Figure 3-1 d corresponds to situations where the oxygen precipitation is intentionally avoided by using wafers with oxygen concentration below the threshold of oxygen precipitation for the thermal cycle used. Therefore, when integrating I G into CMOS device process flow, it is important to understand how I G is to be activated in order to optimize and maintain I G effectiveness and durability through the numerous high temperature thermal cycles. In most CMOS device processing lines, process induced IG occurs naturally in the wafer because the processing thermal sequence is similar to the three-step thermal IG cycle. The high temperature ( > 1100“C) N-well/P-well drive-in process also acts as an effective denudation step, causing oxygen out-diffusion. Following the well drive-in process is usually the field oxide isolation process at intermediate temperatures between 900 “C and 1000“C.This will also induce oxygen precipitation and growth in the bulk of the wafer, thereby

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3 Silicon Device Processing

activating the I G process. For some other CMOS device processing lines, process induced IG may not be sufficient, so enhanced process induced IG is required. By adding a 700°C SiO, nucleation anneal step after the well drive-in step prior to the field oxide isolation step, one can increase the precipitate density and SiO, precipitation rate during the field oxidation step. In this way, the IG effectiveness is improved, especially for the critical gate oxidation step.

3.2.2 Gettering by Hydrogen Annealing As the design rules of MOS ULSI shrink to the quarter micron range, high quality and high reliable ultra-thin silicon oxides are required for gate oxide and tunnel oxide. In general, the failure of a thin oxide can be categorized by three modes (Yamabe, 1990): Mode A, Mode B, and Mode C. Mode C failures represent intrinsic oxide breakdown while mode A failures are related to surface foreign material such as unintentional contaminants, impurities and particles. Mode B failures on the other hand are related to silicon material crystallographic defects such as as-grown stacking faults and SiO, precipitates and process induced crystallographic defects. It has been shown that the crystal quality of the silicon wafer surface plays an important role for gate oxide integrity (GOI) (Yamabe et al., 1983; Ryuta et al., 1990; Yamagishi et al., 1992; Miyashita et al., 1991; Miyashita and Matsushita, 1993): crystal defects in the wafer surface region reduce the dielectric breakdown strength and long-term reliability of thin oxides (Miyashita and Matsushita, 1993). Silicon wafers typically used for ULSI fabrication are made of CZ grown crystal and have several types of as-grown defects, such as

oxygen precipitates and surface micro defects (SMD) (Yamabe, 1990; Yamabe et al., 1983; Ryuta et al., 1990; Yamagishi et al., 1992; Miyashita et al., 1991; Miyashita and Matsushita, 1993). To reduce these micro-defects near the silicon wafer surface extensive research has been done. One approach is to form a denuded zone (DZ) by annealing the silicon wafers at high temperatures in an oxygen-containing environment (Tsuya, 1991). Having a region free of defects and interstitial oxygen will result in the elimination of mode B failures. The use of an epitaxial layer as a DZ also significantly improves GOI. Another possibility to decrease the as-grown defects is to slowly grow the silicon crystal and control the thermal history of the crystal (Hizuki et al., 1990). These approaches have proved to be effective in reducing the as-grown defects to some extent, but insufficient for the improvement of time-dependent dielectric breakdown (TBBD) of oxides thinner than 10nm (Miyashita and Matsushita, 1993). Annealing of silicon wafers in a hydrogen environment at high temperatures to cause outward oxygen diffusion has been shown to be a very effective method to reduce the oxygen precipitates in the surface region. Improved GO1 has been reported in hydrogen annealed wafers (Matsushita et a]., 1988; Adachi et a]., 1992; Samato et al., 1993). A comparison of oxygen concentration and defect density for hydrogen-annealed CZ wafers, conventional CZ wafers, defect-free CZ wafers, and epitaxial wafers is shown in Fig. 3-2 (Nikkei, 1993). It is clearly seen that the hydrogen-annealed wafers are comparable to the more expensive epi wafers, but are superior to other wafers. On the other hand, however, Omar et al. (1 992) observed a high density of micropits on the surface after annealing in H, at 1150 "C. Xu et al. (1993) also observed sur-

3.2 Gettering

123

Figure 3-2. Comparison of oxygen concentration and oxygen-extraction defects for hydrogen-annealed Cz wafers, conventional Cz wafers, defect-free Cz wafers and epi wafers.

face roughening during pre-annealing at 1050°C in H, which resulted in degraded dielectric breakdown. More fundamental understanding of the hydrogen annealing mechanism and process optimization is

needed before this technology can be incorporated in ULSI manufacturing. Deep submicrometer CMOS technology is switching from high-temperature diffused well to low-temperature MeV im-

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3 Silicon Device Processing

plantation technology (Lee et al., 1993). A process sequence based on MeV implantation can eliminate two to three masking steps, eliminate up to 30 processing steps, improve surface topography, and reduce manufacturing cost by 5 to 15 YO,depending on the application. For MeV processing a denudation step must be added or incorporated into the process flow. An inert denuding environment is superior to an oxidizing environment and hydrogen has been reported to be the best (Borland and Koelsch, 1993; Borland, 1989). Recently a significant breakthrough in bulk Cz wafer quality was reported by using hydrogen annealingldenudation, resulting in the realization of surface properties similar to those on epi wafers without additional cost (Nikkei Microdevices, 1993). Under inert conditions such as hydrogen annealing at temperatures as high as 1200°C for 1 h, elimination of mode B failures has been reported (Samato et al., 1993). Gardner et al. (1 994) reported significantly improved CMOS bulk Cz wafer quality on the use of hydrogen denudation processing (annealing). Superior device performance, thin tunnel/gate oxide quality and Cz wafer surface properties have been measured demonstrating the potential for epitaxial elimination. This is achieved by subjecting the wafers to a short hydrogen denudation pre-process between 1050°C and 1200°C for 15-30 min. For thin oxides down to 8.2 nm up to 29% improvement was observed on two different QBD structures. Hydrogen denuding was also very effective in eliminating mode B oxide breakdown failures on bulk non-epitaxial Cz wafers. Additionally, an order of magnitude decrease in junction leakage was observed for the H, annealed wafers relative to the bulk non-epitaxial Cz wafers, resulting in bulk Cz wafers with surface properties similar to epi wafers without the added cost. These

results have immense potential cost savings for all CMOS fabrication areas today currently using epitaxial substrates, especially when applying MeV technology.

3.3 Device Isolation The electrical isolation of active devices in integrated circuit technology includes both general oxide isolation in the “field” regions between devices and special application structures. The most common isolation is the field region, which is typically implemented by partially or fully recessed thick oxide regions between active device regions. Complete oxide isolation with no parasitic leakage paths is possible only in silicon-on-insulator (SOI) technologies. Special isolation structures, such as deep trenches, have been developed to separate the n- and p-well regions of complementary MOS (CMOS). The basic desired properties for any isolation technology are: A small pattern transfer difference between mask layout dimensions and final device geometries. No downscaling of the field oxide thickness as other device geometries are scaled down. A planar surface topology. A defect-free process.

3.3.1 LOCOS-Based Isolation Almost all modern integrated circuits use LOCOS (local oxidation of silicon) for device isolation (Appels et al., 1970). A nitride/oxide stack is formed on the silicon substrate and is patterned and etched to remove the nitride layer in the field regions. Before the resist is stripped off, boron impurities are implanted into the field

3.3 Device isolation

regions. The oxidation is then followed and the silicon is oxidized only locally in the field regions without nitride coverage. The thickness of the field oxide typically is between 700 and 1000 nm. A major drawback of LOCOS is the so-called “bird’s beak” transition between the field region and active device area (Bassous et al., 1976), caused by lateral diffusion of oxidizing species beneath the nitride oxidation mask. The transition length varies depending on the oxidation condition. This transition reduces the device packing density and, as the isolation area is scaled down for VLSI application, the problem becomes more serious. Scaling down the field oxide thickness can reduce the encroachment, but requires a heavier channel-stop implantation to maintain adequate isolation between the devices. The lateral diffusion of the channel-stop impurities during the oxidation and the subsequent high temperature processes can degrade junction capacitance, increase the junction leakage and reduce the “effective” electrical channel width associated with MOS current gain. An option in scaling LOCOS is a channel-stop implant done after the oxidation. This reduces the depletion of boron into the field oxide during the field oxidation, thus retains more boron impurities near the oxide/silicon interface in silicon. As a result, thinner oxide can be used to achieve appropriate isolation. However, the field oxide threshold voltage is very sensitive to the oxide thickness with through-field implant due to the variation of the field oxide thickness. Another problem associated with through-field implant is the increased junction capacitance and reduced junction breakdown voltage for N + / P junctions due to the increased substrate concentration under the junctions from the high energy, unmasked through-field implant.

125

Modifications of the LOCOS process have been investigated. SWAMI (sidewall mask isolation) is one of the best known LOCOS-based isolation techniques (Chiu et al., 1982) and was developed with the objective of retaining the advantages of LOCOS while drastically reducing the bird’s beak. Since the bird’s beak is due to oxygen lateral diffusion through thin oxide from the active area edges, an obvious solution is to block it with a nitride barrier (Teng et al., 1985). SILO’S (sealed-interface local oxidation) approach to bird’s beak reduction consists of reducing the thickness of the LOCOS pad oxide to zero in order to seal the silicon interface under the LOCOS stack (Hui et al., 1982). This eliminates the need for a perimeter nitride seal, as used in SWAMI, and allows for a simpler process. SILO uses an active area stack with two different nitride layers, one very thin ( z130 8, for interfacial seal) in direct contact to silicon and one much thicker ( z1000 8, for oxidation mask) on top of the stack. Between them, the usual pad oxide is retained for stress relief purposes. The key to prevention of Si defects is the extremely small thickness of the sealing nitride, which limits the compressive stress induced in Si to values below the plastic deformation threshold (DerouxDauhphin et al., 1985). Another approach uses a stress relief poly-buffer layer between the nitride and the initial pad oxide (poly-buffer LOCOS, PBL), which absorbs stress produced during field oxidation (Nishihara et al., 1988; Havemann and Pollack). Although low bird’s beak was demonstrated, the resulting field oxide protrudes significantly above the original silicon surface, producing severe topography. Using the principle of a stress relief polysilicon layer and a reverse L-shaped sealed nitride spacer, the bird’s beak can be further reduced com-

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3 Silicon Device Processing

pared to conventional PBL (Sung et al., 1990). The process flow for this reverse L-shape sealed poly-buffer LOCOS (RLSPBL) is shown in Fig. 3-3 (Sung et al., 1990). The pad oxide is selectively removed using the silicon nitride/polysilicon stack as a mask to form undercut portions. A new stress-buffer oxide film is then grown to cover the entire silicon surface. After LPCVD nitride deposition and RIE, a reverse L-shape sealed silicon nitride spacer is formed. Shimizu et al. (1992) developed a poly-buffer recessed LOCOS (PBR LOCOS) isolation for 256 Mbit DRAM cells. In this process, the low bird’s beak and defect-free isolation are achieved by using shallow silicon recess etch (25-200 nm), buffer polysilicon, and nitride sidewall sealing. The process flow of PBR LOCOS is shown in Fig. 3-4.

si

\PAD

OXIDE

(a)

E

(C)

Figure 3-3. Reverse L-shape sealed PBL process flow: (a) formation of side etched portions of pad oxide; (b) sealed nitride film deposition; and (c) RIE nitride etching. The pad oxide (100 A), polysilicon film (500 A), nitride cap (2000 A), and regrown oxide (60 A) are not drawn to scale.

3.3.2 Advanced Isolation Techniques The scalability of LOCOS to deep submicrometer dimensions has been difficult due to the conflicting requirements for a small bird’s beak profile, defect-free substrate and adequate field oxide thickness to ensure good electrical isolation. Several isolation techniques have been investigated as replacements for standard LOCOS. Non-planar techniques are not favored because of the patterning difficulties associated with subsequent levels such as interconnect. Those that are sufficiently planar can be divided into the following categories : Modified LOCOS that use improved nitridation masking Shallow Trench Isolation (STI) Selective Epitaxial Growth (SEG) Trench isolation Silicon on insulator (SOI)

Figure 3-4. PBR LOCOS process sequence: (a) after recess etching; (b) after nitride sidewall formation; and (c) field oxidation.

3.3 Device Isolation

Recessed sealed sidewall field oxidation (RESSFOX) (Lee et al., 1990) employs a consumable sidewall nitride to reduce bird’s beak. A thin consumable nitride film of about 200 8, thickness is deposited over a shallow trench (1 50 nm) in the Si substrate after the field implant. RIE is used to form the consumable nitride on the sidewall of the shallow trench prior to field oxide growth. This thin nitride must be thick enough to block the oxygen lateral diffusion, and thin enough not to add additional stress and to be consumed during field oxidation. This is the main difference between RESSFOX and SWAMI. The use of a self-aligned nitride-filled or polysilicon-filled cavity followed by nitride spacer formation to offset the bird’s beak from the nitride-I edge has received much attention for 0.25 pm CMOS technology. Polysilicon encapsulated local oxidation (PELOX) controls the bird’s beak through the use of a polysilicon-filled cavity, selfaligned to the nitride edge (Roth et al., 1991). The process only involves simple modification of a standard LOCOS process flow. These modifications include an H F dip after nitride pattering to form a cavity self-aligned to the nitride edge, reoxidation of exposed silicon, and polysilicon deposition to fill the cavity, as shown in Fig. 3-5. Using nitride-filled cavity instead of polysilicon-filled cavity, Pfiester et al. (1993) have developed a nitride-clad LOCOS (NCL) isolation which exhibits 600 A per side bird’s beak encroachment profiles with adequate field oxide thickness in narrow field regions. The process flow is shown in Fig. 3-6. A bird’s beak controlled poly-buffered LOCOS (BPBL) was developed by Huang et al. (1993). A schematic process sequence of BPBL isolation is shown in Fig. 3-7. The pad oxide was grown, followed by LPCVD polysilicon and nitride deposi-

127

tions. After nitride etching by RIE, isotropic plasma etching was used to partially remove the exposed polysilicon to form rounded thin polysilicon regions under the nitride layer. After nitride spacer formation, the remaining polysilicon is removed to increase the recess depth of a 4000 8, field oxide. The corner between the first nitride and polysilicon is rounded to diffuse stress impinging from the nitride spacer to the Si substrate during field oxide growth. The polysilicon is thinned to minimize the bird’s beak penetration. Results show that the surface morphology is quite planar, i.e., the recessed portion of field oxide profile reaches almost 70% of total thickness. Isolation space up to 0.35 pm has been achieved with excellent junction characteristics and gate oxide integrity. For buried oxide (BOX) isolation (Kurosawa et al., 1981; Shibata et al., 1983) or shallow trench isolation (STI) (Fuse et al., 1987; Davari et al., 1988; Pierce et al., 1991; Yu et al., 1992; Shibahara et al., 1992; Fazan et al., 1993) shallow trench and advanced planarization techniques are used. For feature size of 0.25 pm or below, neither LOCOS nor its advanced modifications are expected to provide the required surface planarity, field-oxide thickness, edge contour, and channel-stop characteristics. On the other hand, BOX and STI isolations have the potential to fulfill these needs. Unlike the local oxidation process, in BOX a deposited oxide is used. Thermal oxidation depletes the channel stop boron impurities near the interface which degrade the isolation. Using deposited oxide can retain more boron under the field and can achieve sharper corners with more potential barrier enhancement. However, BOX isolation suffers from process control problems, such as field isolation uniformity at mesa corners, double-resist processing, and

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3 Silicon Device Processing

Figure 3-5. PELOX process flow: (a) RIE nitride; (b) HF dip to undercut nitride and form cavity; (c) growth reoxidation; and (d) deposit polysilicon encapsulation layer.

Figure 3-6. NCL process flow: (a) HF etching of the first stress relief oxide (SRO-1) to form a 750 8, selfaligned cavity under Nitride-1; (b) a 5 5 8, thermal reoxidation (SRO-2) followed by a 100 8, Nitride-2 deposition; and (c) field oxidation.

Figure3-7. Process flow of BPBL isolation.

3.3 Device Isolation

I

I

129

oxide

Figure 3-8. STI process flow summary: (a) mask and trench definition, (b) trench oxidation and B doping, (c) CVD oxide and CMP planarization, (d) oxide spacer formation, (e) pad oxide wet etching, (0 gate oxide growth and gate deposition.

registration of the first-resist pattern. Moreover, the adoption of sloped sidewalls contrasts with the trend toward higher resolution. STI provides a planar surface and a fully recessed field oxide; it does not suffer from field oxide thinning and can easily be scaled down. Fazan and co-workers (1993) proposed a simple STI process suitable for 256Mb to 4Gb DRAMS. The process flow is summarized in Fig. 3-8. The features of this STI process are tapered trench sidewalls, a slight trench reoxidation, a vertical boron field implant, a CMP-only planarization, and disposable oxide spacers to smooth the trench corners. In addition to device isolation, STI has been employed to fabricate 0.25 pm CMOS devices with buried trench gate structures, as shown in Fig. 3-9 (Wen et al., 1991). The entire poly gate is buried in both active and isolation areas and a fully planarized structure is achieved- The electrical junction depth with respect to the channel surface is

Figure 3-9. Process sequence of the fully planarized CMOS technology.

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3 Silicon Device Processing

about 50nm, which is much shallower than the conventional junction due to the recessed poly gate. Excellent short channel effects and device characteristics are achieved using this fully planarized CMOS technology. The highly planar topography of this technology also forms an excellent base for future planarized multilevel interconnect structures. SEG is conceptually the simplest method for achieving fully recessed oxide isolation. Active silicon layers are grown epitaxiaily between columns of oxide that serve as device isolation. At the leading edge of this technology, SEG demonstrated an incredibly short active area spacing across the well of only 1/4 pm (Kasai et al., 1987; Kamins et al., 1985). The rapid progress experienced by SEG has resulted in a growing number of publications and improvements in SEG fabrication equipment, indicating that this technique will play a major role in CMOS submicrometer isolation at 0.25 pm and below. The other 1. Oxide

2. Etch N-well windows

5. Etch P-well windows

advantage of SEG is that the n-well and p-well can be formed independently, as shown in Fig. 3-10 (Borland, 1987). Independent n-well and p-well CMOS structures with retrograde wells can be realized through graded epitaxial growth without the use of ion implantation and high temperature annealing. This advantage can also be found in bipolar and BiCMOS structures. The selective doping is also very attractive for other applications such as shallow junction formation and contact refill as well as planarization for interconnect. Remaining issues to be resolved in SEG include the faceting and the defect generation in epi near the epi/oxide interface. Although defect-free structures have been reported for patterns oriented parallel to the (100) direction, they have yet to be determined for other orientations. The major objective of trenches is to achieve high density without suffering an increase of isolation leakage or having to reduce the supply voltage. This is achieved

3. N-Type SEG epi for N-well formation

6. P-type SEG epi for P-well formation

4. Thin thermal oxide

7. Strip thin oxide

'Retrograde wells are possible by buried layer epitaxy or graded epitaxy techniques

Figure 3-10. Independent n-well and p-well formation by SEG.

3.3 Device Isolation

by folding the silicon surface across the isolation to form a deep, narrow barrier, which increases the current path many times with respect to the spacing. Moreover, by digging the trench so deep that its bottom lies in heavily doped silicon, such as the substrate of an epitaxial wafer, the isolation leakage suppression is virtually complete. Particularly for trench capacitors, the trench oxidation properties are important to ensure high dielectric strength, high breakdown voltage, and low leakage current of the capacitor dielectric. Fortunately, these properties were found to be only slightly inferior to those of planar surfaces (Baglee et al., 1985), with the weakest spot being at the corners, where the oxidation rate is smaller (Marcus and Sheng, 1982). However, using a sacrificial oxidation, these corners can be rounded off erasing any difference between the trench and the planar oxide properties (Yamabe and Imai, 1981). Conventional trench isolation results in stress induced defect generation. The problem can be overcome by a sealed sidewall trench (SST) process (Teng et al., 1984) containing an additional nitride layer in the trench, although this introduces process complexity. With the conventional trench process (either refilled with poly or deposited oxide), the leakage is about 2 to 3 orders of magnitude higher than without a trench (Teng et al., 1984). However, with SST the leakage is comparable. Although trench isolation can produce excellent lateral isolation, it does not address vertical isolation. The ideal situation for future isolation would be to suspend both device types in a dielectric layer (e.g., SO,). This would effectively eliminate latch-up and radiation induced error phenomena, as well as reduce performance limiting effects such as parasitic capacitances. Furthermore, such a structure

131

would require less layout area for the same design rules than conventional, junctionisolated CMOS, because the deep p- and n-wells are eliminated and the area required to accommodate p-n junctions is significantly reduced.

3.3.3 Silicon-on-Insulator Silicon-on-insulator (SOI) technology is a major contender to provide the high performance, low voltage, low power capabilities required for future generations of integrated circuits. The performance advantages of this technology, as well as the potential yield advantages offered by the unique “all around” isolation in SO1 devices, have been discussed in several publications. During the past several years, unique problems in device performance in this technology have been identified and solved, but the long standing issues of quality, availability, and cost of SO1 substrates have prevented this technology from being commercial IC applications. FIPOS (full isolation by porous oxidized silicon) employs lateral anodic oxidation to form isolated silicon islands over a silicon substrate (Zorinsky et al., 1986; Kubota et al., 1986; Imai et al., 1984). In early developments, lateral oxidation could only be extended to a few micrometers without forming excessively thick porous oxide films, which would cause warpage and later interfere with the rest of the process. An improved FIPOS approach was developed. It is known as the ISLANDS method (Zorinsky et al., 1986) and its process sequence is illustrated in Fig. 3-11. A heavily doped n + layer is formed by epitaxy followed by a second n-epitaxial layer with the desired resistivity. Then, Si,N, and SiO, are deposited to form the masking stack. Trenches with a

132

(A)

3 Silicon Device Processing

I

EPI LAVER

T

SUBSTRATE

{

OXIDIZED POROUS SILICON LAVER

THERMAL OXIDE

(C)

ANODIZIBLE LAVER

FORM N+ ANODIZABLE LAYER GROW EPiTAXIAL “ T U B LAYER

FORM (POROUS) ANODIZED LAYER (P = FI [HF],J, Nd.. ))

ANODIZABLE LAVER

GROW ISOLATION OXIDE

\

..

PLANAAIZED DEPOSITED OXIDE

DEPOSIT ANODIZATION MASK/TAENCH HARD MASK LAYERS PATTERN TRENCH MASWETCH STACK, ETCH TRENCH

-

REFILL TRENCH DEPOSITED OXIDE PLANARIZE RESIST EROSION DENSIFY TRENCH OXIDE

few micrometers are formed along the active area edges. The porous oxide is formed preferentially along the n + epitaxial layer, electrically isolating the top n-silicon layer from the substrate. Finally, the trenches are refilled with oxide and planarized. The maximum size of an isolated feature is 42 pm in width and unlimited in length. The minimum pitch is 2.8 pm and consists of a 1-pm line and a 1.8-pm gap. The porous oxide thickness is uniformly controlled to 4900 ? 300 A. Measured electron mobilities are equivalent to those of BULK. The subthreshold leakage current is low ( x0.1 pA/pm width at 5 V), demonstrating complete elimination of the back channel. Several significant contributions have been made recently to the two primary SO1 technologies being considered for volume VLSI device applications : separation by implantation of oxygen (SIMOX) and wafer bonding (as used here, “wafer bonding” includes all of the thinning techniques for producing SO1 which use bonded wafers as a basis). The SIMOX process is illustrated in Fig. 3-12. This process uses a high dose oxygen implantation (10” oxygen atoms/cm2) into a silicon substrate, followed by high tem-

-

Figure3-11. The ISLANDS process flow.

perature annealing to form a buried oxide. The structure after the implantation is composed of the silicon substrate, a buried oxide, and a single-crystal silicon film. If necessary, the single-crystal silicon thickness can be increased by conventional epitaxy. During oxygen implantation, the wafer is kept at an elevated temperature (> 400 “C) in order to minimize the damage to the surface layer. The growth characteristics and physical structure of the buried oxide and the single-crystal silicon produced by the SIMOX process has been studied extensively over the past several years, During the implantation, the oxygen concentration first forms a skewed Gaussian profile, but once the oxygen dose is sufficiently high the distribution becomes flat-topped, with a peak oxygen concentration corresponding to stoichiometric S O , . It has been found that al~rlTlalt

,

After Annealing

Figure 3-12. Scheme of SIMOX process.

3.3 Device Isolation

though the SIMOX buried oxide is in many ways similar to thermal oxides, it differs significantly in both conduction characteristics and radiation response. High temperature annealing ( > 1300“C) is performed following the implantation to eliminate crystallographic damage in the surface silicon layer, and to allow oxygen from the tails of the implanted distribution to diffuse to and be incorporated in the SiO, layer. After annealing, the dislocation and stacking fault density in the top silicon layer was quite high, i.e., approximately l o 4 to lo6 per cm’. Such high density of dislocations and stacking faults remaining in SIMOX wafers after annealing can cause emitter-collector shorts in bipolar devices, similar to the effects of these crystallographic defects on devices built in bulk material. As a result, SIMOX wafers cannot be used for ULSI bipolar applications. On the other hand, the effects of crystallographic defects in SIMOX material on CMOS devices can be minimized. The majority of applications of SIMOX SO1 technology are found in CMOS devices designed for operation in harsh environments. The typical SO1 materials needed for these applications have buried oxides with thicknesses in the range of 0.4 pm, and silicon layers with thicknesses of 0.3-0.5 pm. The SIMOX process is ideally suited to producing material with these layer thicknesses. Even with the device demonstrations, the major stumbling block for the use of SO1 technology in any large scale applications has been the credibility of supply of high quality SO1 at reasonable costs. A fundamental problem of buried oxide “pipes” are plagued SIMOX wafers. These buried oxide “pipes” are observed as conductive threads of silicon through the oxide. Measurements also showed that there are “partial pipes”, that is, areas which appear as thin oxide regions

133

in the SIMOX materials. The buried oxide pinhole problem has been correlated with particles on the wafers during the implantation step. The “pipes” are a result of the shadowing of specific areas from the oxygen implant by the particles. Eliminating these defects has not been a trivial task since particles can be generated in the clean-up before wafers are implanted as well as in the implanter itself. The wafer bonding process is illustrated in Fig. 3-13. In this process, two silicon wafers which have a very high degree of flatness are used. One, or both, of the wafers are oxidized. The surfaces are then mated, and the composite is annealed to form a single structure. One of the wafers is then used as a handle, and the other wafer is thinned from the back side until only a thin superficial silicon film is left. Several techniques for the thinning process have been used, including both physical and chemical techniques. In some methods, an etch stop is either implanted or diffused into the wafer to be thinned before the bonding process; initial thinning is accomplished by a mechanical process to produce a film in the range of several micrometers thickness. The final thinning is then accomplished by a chemical etch Two Flat Si Wafers Wafer 1 Wafer 2

1

I Oxidize, Bond, Anneal

Wafer 1

-

Oxide

Grind, Polish or Preferential Etch

r Wafer 2

Figure 3-13. Scheme of wafer bonding process.

134

3 Silicon Device Processing

back using a preferential etchant and an etch-stop layer. The structure of the superficial silicon films on bonded wafers are expected to be very similar to those of the bulk wafers used in the SO1 fabrication. This is generally found to be the case, at least for superficial silicon layers down to a thickness of a few micrometers. Typical crystal defect densities in bulk silicon are < 1o2/cm2. With the usual wafer grinding and polishing techniques used for silicon IC substrates, it is difficult to produce uniformities superior to & 0.5 pm. Although thinner superficial silicon layers can be produced with chemical etch stop techniques, this is at the expense of added process complexity and the possible introduction of defects due to the etch stop layer itself. Because it is relatively difficult to control the thickness of bonded wafers within very small ranges, these materials have been primarily applied to bipolar devices. In bipolar circuits, the superficial silicon layer must be essentially free of crystallographic defects, and is typically used to form a deep collector. This requires a thickness in the range of 2-4pm, with tolerances of f 0 . 5 pm. The wafer bonding approach is ideally suited for this application. Ultrathin bond and etch-back silicon on insulator (BESOI) in the thickness range of 75 to 100 nm offers the potential for performance enhancement in both CMOS and BiCMOS technology (Omura and Izumi, 1990; Shahidi et al., 1991). To be useful however, a very low total thickness variation (ttv) is desirable, typically below 10 nm. With the conventional grinding technology ttvs around 300 nm can be obtained, with ultra-precision grinders even better ttvs are possible (Abe et a]., 1992). Nevertheless, conventional grinding technology may be incapable of achieving the ultra-low ttvs which are required by these

new applications. Recently, several polishing techniques have been reported that utilize polish stops to achieve high ttvs with selected patterns. While these techniques are useful, they are expensive and do not yield a generic wafer. A unique plasma thinning technology has been demonstrated to be able to thin the superficial silicon on bonded wafers to thicknesses of 0.3 pm or less, with thickness tolerances of less than f 0.01 pm (Mumola et al., 1992). This may allow bonded wafers to be used for both CMOS and bipolar devices. Bonding of an oxidized wafer to another wafer was proposed by Lasky and coworkers (1985). They developed an ion implanted etch stop technology to thin the device wafers. Mazara (1991) and Hunt et al. (1991) extended this technique to include a double etch stop. A potential high throughput BESOI process that is capable of achieving both intrinsic high quality (both silicon and oxide) and versatility as well as high uniformity was developed by Iyer et al. (1993) using a well-defined and highly uniform etch stop system. The Si-Ge etch stop layers are deposited by low temperature UHVCVD epitaxial techniques (Iyer et al., 1989). After a low temperature joining and bonding process, the device wafer is thinned by moderate ttv grinding, followed by a damage removal step. The device wafer is then selectively etched in high selectivity silicon etch with the etching stopping well within the etch stop system. The etch stop layers are then separately removed in another selective etch. After taking into consideration the uniformity of the epitaxial processes, grinding and etching processes, a ttv that is typically well below 10 nm is routinely achieved with minimal edge loss. Electrical characterization of SO1 films showed superior carrier lifetimes and FET devices characteristics.

135

3.4 Gate Dielectrics

CMOS TECHNOLOGY TREND

The bonding interfaces must be free of bubbles. Bubbles are mainly caused by particles and adsorbed gases on silicon surfaces such as hydrocarbons. These particle-related bubbles can be eliminated by mating two wafers in an ultra-cleanroom (class 1 or better) or by using a micro-cleanroom set up (Mitani et al., 1991). Bubble generation caused by adsorbed gases can be prevented by degassing before wafer bonding (Mitani et al., 1991). Bonding strength is monotonically increased with increasing the annealing temperature due to atomic phase change at the bonding interface and the thermal flow of oxide at high temperature.

l

0

1000

-

-

Low defect density Good barrier properties against impurity diffusion High quality Si/SiO, interface with low interface state density and fixed charge

-

“Q v)

W

z Y

uI t-

W

E I

100

0 *

s W

3.4 Gate Dielectrics As device dimensions continue to shrink, a commensurate reduction in the gate oxide thickness is required, as shown in Fig. 3-14 (Taur et al., 1993), primarily to prevent the short-channel effects. For example, an excessive reduction in channel length without an adequate thickness scaling can result in threshold voltage instabilities due to charge sharing effect as well as excessive subthreshold and off-state currents due to drain-induced barrier lowering and punchthrough. Thus, in order to minimize the undesirable short channel effects while ensuring high performance of the device, gate oxide thickness scaling is a very efficient approach. In other words, by scaling the oxide thickness, the behavior of a MOSFET can be made more long-channel-like. Thin gate oxides ( < l o 0 A) in ULSI MOS applications should meet the following crucial requirements :

7

..

I

110

0.I

1.0 MOSFET CHANNEL LENGTH (pm) Figure 3-14. CMOS technology trend

-

-

Stability under hot carrier stress and irradiation Low thermal budget processing

Low defect density in the oxide ensures that the number of catastrophic oxide failures at low electric fields is minimum. One method to characterize oxide integrity is breakdown histograms. This well-established method categorizes failure modes as either mode A, B, or C (Sanchez et al., 1989). Mode C failures represent intrinsic oxide breakdown while mode A failures are related to surface foreign material such as unintentional contaminants, impurities and particles. Mode B failures on the other hand are largely related to silicon material crystallographic defects such as as-grown stacking faults and SiO, precipitates and process induced crystallographic defects. Other causes for Mode B failures are listed in Table 3-2.

136

3 Silicon Device Processing

Table 3-2. Causes for B-mode failures in oxide. 1 . Local electric field intensification a. Local oxide thinning b. Residual nitrogen at surface (Kooi effect)

2 . Charge trapping of oxide a. Electron trapping water related traps non-bridging oxygen defects dopant impurities b. Hole trapping oxygen vacancy

3. Crystal quality a. Metallic contamination b. Surface roughness c. Oxygen precipitates 4. Process-induced damage

a. Reactive ion-etching b. Photoresist ashing

Improved barrier properties are particularly important for p+-polysilicon gated p-MOSFETs. Low interface state density ensures a sharp switching characteristic in MOSFETs. High lateral electric fields in the channel in the downscaled MOSFETs lead to significant heating of channel carriers, resulting in hot carrier effects such as oxide charge trapping and interface state generation. The use of a gate dielectric which suffers minimum damage under hot carrier stress is a promising option in aggressively scaled MOSFETs. Processing techniques such as reactive ion etching (RIE) and some of the future tools such as X-ray lithography can expose gate oxides

to high energy plasma and radiation, which are known to reduce the quality of gate oxides. This imposes the requirement of the radiation “hardness” on thin gate oxides. Finally, low thermal budget is necessary in ULSI in order to minimize the redistribution of dopants by diffusion. The main thrust in the gate dielectric research in recent years has been addressed to the above mentioned issues. Numerous techniques have been suggested to solve one or more of these problems. These techniques can be broadly divided into four categories. The first approach involves variations of pre-oxidation cleaning procedures. The second approach involves process variations of the oxidation process. The third approach, which has received considerable attention over the past decade, is to chemically modify the properties of gate oxides. The final approach is deposition of oxides or formation of stacked layers as gate dielectrics. 3.4.1 Preoxidation Cleaning

The fundamental role of a silicon cleaning procedure is to remove from the surface (a) organics, (b) transition metal and alkali ions and (c) particulates. These contaminants, if not removed from the wafers prior to oxidation, can affect the quality of the gate oxide. Common wet cleans and their application are listed below:

0

HF/H,O

etching native SiO, layers

0

H2S04/H20,( 5 : l ) NH40H/H 2 0 2 / H 2 0(1 : 1 : 5 ) (SC-1)

removing heavy organics

HCl/H20,/H20 (1 : 1:5) (SC-2) Effects of NH,OH/H,O, ratio:

removing metallic species

0

0

0

removing light organic residue and particles

High: good for particle removal Low: less surface roughening

137

3.4 Gate Dielectrics

The RCA cleaning procedure, proposed by Kern and Puotinen (1970), is still used widely in its original form or with minor modifications. The cleaning procedure consists of two steps. The first step involves cleaning in a hot, high pH H,O, SC1 solution (H,O/H,O,/NH,OH = 5 : 1 : 1) in order to remove organic contaminants from the silicon surface by oxidation. The second step involves treatment of the silicon surface with a hot, low pH H,O, SC2 solution (H,O/H,O,/HCl= 5 : 1:1) to remove the metal contaminants via metal complex formation. An additional intermediate step of dilute H F dip is often used to remove the oxide grown during the first cleaning step. A detailed review of the chronological development of the cleaning processes has been published by Kern (1990). As the oxide thickness is scaled down to below 100 A, the requirements on the cleaning processes have become more stringent. Although RCA or modified RCA clean are adequate in effectively removing the surface contaminants, these cleaning treatments can also lead to surface microroughness due to the presence of alkaline NH,OH solution used. Ohmi et al. (1992) investigated this phenomenon in detail and reported that microroughness causes lowering of breakdown electric field and charge-to-breakdown in gate oxides grown on these surfaces. They suggested the use of a 5 : 1:0.25 H,O/H,O,/NH,OH solution, rather than the traditional 5 : 1 :1 mixture in order to prevent the surface microroughness. Optimization of the NH,OH/H,O,/H,O ratio in the SCIcleaning has been studied by Meuris et al. (1992). It was found that both metal contamination and particle densities were equal after the complete RCA cleaning for wafers processed using SC1 with different mixtures (NH,OH/H,O,/H,O =0.1- 1 : 1 :5).

From this, one would normally expect similar breakdown properties of subsequently grown gate oxides. However, large differences were found in yield. The 0.25:1:5 SC1 mixture results in much higher gate oxide integrity than the 1:1:5 mixture due to the Si-surface roughness caused by SC1 solutions. A qualitative model for the action of the SC1-cleaning helps to understand the observations (Meuris et al., 1992). When silicon is exposed to the SC1mixture, the peroxide will oxidize the silicon surface while the ammonia will disperse this chemical oxide; i.e. a chemical oxide layer will continually form and dissolve as a result of the compensating effect of the two chemical components. This process slowly etches the silicon. A high etching rate will increase the particle removal efficiency by undercutting the particles, but will cause a larger surface roughening during 10 min of cleaning. Consequently, it is important to find an optimum between particle removal efficiency and silicon surface roughening. An etching rate of 0.2 nm/ min was found to be the best. New cleaning solutions such as choline are also being used (Kao et al., 1989) with a reduction in defect density in oxides. The metallic contamination on Si wafers after various cleaning treatments is shown in Table 3-3 (Verhaverbeke et al., 1991). In general, a final cleaning step in H F results in lower metallic contamination compared with standard RCA cleaning. Surface metal Table 3-3. Typical metallic contamination after various final cleaning steps followed by DI water rinsing (10" at/cm2) (Verhaverbeke et al., 1992).

K

Ca

Cr

Fe

Ni

Cu

Zn

0.3 0.06 0.09 3.7

0.4 0.1 1.2 0.7

~

RCA HF HF/H,O, BHF

0.3 0.1 0.6 0.2

8.6 3.8 1.6 1.4

0.2 5.1 3.3 0.05 0.3 0.1 0.3 2.2 0.2 0.4 2.6 0.3

138

3 Silicon Device Processing

contamination resulting from SC-1 solutions include the following: -

Fe will form non-soluble iron hydroxide under SC-1 conditions; Iron hydroxide can be removed during SC-2 cleaning; Electrochemical plating of noble metals (e.g., Cu) from HF.

The hydrogenated surface resulting from H F etching allows electrochemical reactions with noble metals to occur. The reaction product is mostly a silicide, a chemical substance very difficult to remove in a subsequent set of chemical cleaning steps. Cu is present in an acid HF-solution with a higher half-cell potential than hydrogen and, therefore, can be deposited on the Sisurface from an HF-solution (Kern et al., 1991). This can be avoided by using highly purified chemicals or by adding small amounts of H 2 0 2 to the HF-solution (Ohmi et al., 1991). Contaminants in the chemicals used in wet etching and DI water distribution system have been major sources of metallic impurities which reduce the gate oxide integrity. In a recent work (Verhaverbeke et al., 1991), roles of various metallic contaminants on the gate oxide breakdown properties were studied. Ca was found to interact strongly with the Si substrate, resulting in interface roughness and deterioration of breakdown properties. Whereas Fe was observed to degrade the oxide integrity by forming defect spots during oxidation, A1 was shown to cause damage under the polysilicon gate/SiO, interface. Unlike Fe and A1 contamination, Ca contamination is largely unaffected by the gettering cycle. This is consistent with the fact that Ca is mainly located in the thermal oxide. From these results it can be concluded that for gate oxide integrity, Ca is the most important contaminant. The Ca

contamination can be avoided by using ultra-pure chemicals, ultra-pure distilled (DI) water, a carefully designed DI-water distribution system and by final cleaning with H F (Verhaverbeke et al., 1992). After the last cleaning step with HF, the metallic contamination on the Si-surface is lower on the average than after an RCA-cleaning for the typical metals found after a stateof-the-art cleaning. Owing to their low metallic contamination, HF-dipped surfaces are well-suited for the growth of highlyreliable thin gate oxides. However, hydrophobic surfaces are well-known to be susceptible to particle deposition, particularly during subsequent DI-water rinsing (Table 3-4). These particles can be reduced significantly after oxidation. Table3-4. Particles on a 5 inch wafer after HF-dip and rinse-dry (Verhaverbeke et al., 1992). N, Spin Spin manual dryer rinseblow dryer ~

HF-dip/no rinse HF-dip/overflow rinse HG-dip/quick dump rinse

7 400 3100

_

_

_

250 6900 500 6100 1200 7600

By adding minute amounts of isopropyl alcohol (IPA) to the HF-solution (Verhaverbeke et al., 1992), the deposition of particles on the Si surface can be prevented during HF-dipping and subsequent rinsing and results in highly reliable oxide layers. By adding 200 ppm or more IPA to the 0.5 YOH F solution, the particle deposition is dramatically reduced. The IPA does not chemically react with the Si surface; it is only physically adsorbed and desorbs readily at moderate temperatures. As the devices become smaller and smaller, there are several serious concerns for wet chemical cleaning. These include :

_

3.4 Gate Dielectrics -

-

-

Particulates generated after cleaning; Drying difficulties (watermarks) ; Large amount of hazardous waste chemicals produced; Inability to clean small contact holes with large aspect ratio; Incompatibility with certain existing processes ; Incompatibility with integrated processing.

For these reasons, dry cleaning processes have attracted significant attention (Moslehi et al., 1992; Ruzyllo et al., 1989) over the past several years. Advantages of dry cleaning include : -

~

-

-

A “cleaner” process; Gas reactive species have easier access to the wafer surface, capable of penetrating minute, high aspect ratio trenches ; Significant reduction in chemical waste disposal ; Can be incorporated in situ for integrated single wafer processing; Removal of metal and organics can be achieved by using UV-enhanced or plasma dry cleaning.

Ruzyllo et al. (1989) reported that the use of UV treatment on wafers in an 0, ambience to remove organic contaminants had no detrimental effect on mean time-tobreakdown ( t b d ) as well as t,, distribution. Kao et al. (1991) used a vapor phase HF/ HCl cleaning procedure and observed a ten-fold increase in t,, for the subsequently grown gate oxides compared to the oxides on RCA cleaned wafers. Kasi and Liehr (1 992) concluded that a pre-oxidation high temperature UV/O, treatment can effectively remove the hydrocarbon contamination. Fukuda et al. (1992) adopted a rapid thermal cleaning approach in which the wafers, initially subjected to H,SO,-H202 cleaning and 1 % HF dip were treated in

139

either H, or HCl/Ar ambience for various temperatures and durations. It was concluded that the HCl/Ar cleaning removes metallic impurities as well as the native oxide, whereas the H, cleaning is unable to remove the metallic impurities.

3.4.2 Process Dependence of Gate Oxide Quality The impact of gate oxide temperature on the quality of the gate oxides has been investigated by several researchers. For example, in an earlier work, Deal et al. (1967) reported that the fixed positive charge in the oxide decreased nearly linearly with increasing oxidation temperature. Hahn and Henzler (1984) studied the structural and electrical properties of the Si/SiO, interface as a function of oxidation temperature. They reported a strong correlation between the atomic steps at the interface, which were taken as a measure of roughness, and the electrical properties and concluded that high temperature oxidation results in a smoother interface with less interface states and less fixed charge. Fukuda et al. (1992) also indicated that high temperature (1200 “C) RTP oxidation results in a superior gate oxide with lower interface state density, longer t,d and tighter t,, distribution, as compared to low temperature (800 “C) furnace grown oxide. Walters and Reisman (1990) reported that the density of electron traps in the gate oxide decreased with an increase in oxidation temperature from 800°C to 1000°C. Joshi and Kwong (1992) reported that MOSFETs with gate oxides grown at high temperature show improved electron and hole mobility as well as suppressed degradation under radiation and hot-carrier stress, as shown in Fig. 3-15. The improved mobility was attributed to the formation of a smoother interface at elevated

140

3 Silicon Device Processing

560 m

. j

N

5

v

0 E,ff = 0.2 MVlcm . o Eeff = 0.8 MVlcm

550 -

9 z B 540

-

- 320

"*.,

,''

I'

-310

/

?

1;

J2 .2

M

Q-----&'

i L

+ -5s

/

,, /

/

- 330;

p--,P

/'

-

0

5

340

- 300

L 0

530

xO0

"

'

900

I

'

1000

"

'

1100

'

290

0 12Uu

TEMPERATURE ("C)

Figure 3-15. (a) Effective electron mobility (p,,) for two values of effective electric field (Eeff)in MOSFETs with gate oxides grown at different temperatures. (b) Increase in off-state leakage current (Aid,) and transconductance degradation as a function of gate oxide growth temperature.

temperatures, while the improved reliability was attributed to interfacial strain relaxation by viscous oxide flow at temperatures above 960°C (EerNisse, 1977). These studies suggest that high temperature oxidation is preferred in order to achieve good performance and reliability in gate oxides. Consequently, rapid thermal oxidation at high temperature appears to be a suitable approach for gate oxide growth in ULSI MOS devices. Apart from the higher growth rate, suppressed number of early breakdown as compared to dry oxides is an attractive feature of wet oxides (Irene, 1978). Wu et al. (1989) observed that wet oxides

-

show very sharp t,, distributions with 15 x larger t,, values as compared to dry oxides. Li and Chang (1988) used a two step approach to grow gate oxides, with a combination of dry-dry, wet-dry and wetwet processes. The wet-wet process resulted in the minimum defect density. A systematic decrease in the number of low field breakdowns was observed with an increase in wet oxygen partial pressure during oxidation. Recently, wet oxides have been implemented in a 0.8 pm technology and some attractive features have been reported (Wei et al., 1992). The comparison was made between 850°C wet oxide MOSFETs and 900°C dry oxide MOSFETs. The breakdown histograms were comparable in both the cases, unlike the significant improvement for wet oxides reported in earlier studies. A 10% increase in linear transconductance was observed in n-channel MOSFETs with wet gate oxides. However, in p-channel MOSFETs, where electron trapping during hot carrier stress is the dominant degradation mechanism (Koyanagi et al., 1984), wet oxide devices are somewhat worse than dry oxide devices. The use of high pressure oxidation was suggested for growing thick field oxides, e.g., in a LOCOS isolation (Baglee et al., 1984). The major advantage of high pressure oxidation is an enhanced growth rate as compared to atmospheric pressure oxidation. If atmospheric pressure oxidation is used to grow thick field oxide necessary to provide isolation between adjacent MOSFETs, high temperature/long duration processing is necessary. For example, a 3000 A field oxide can be grown by wet oxidation at 1000°C in about 2 h. Such a high thermal budget is not desirable in ULSI processing due to redistribution of dopants by diffusion. For example, channel width narrowing due to the encroach-

3.4 Gate Dielectrics

ment of channel stop implants into the active regions has been reported by Baglee et al. (1984). Due to the enhanced oxide growth rate, high pressure oxidation can be performed within a considerably smaller thermal budget either by lowering the oxidation temperature or by reducing the growth time. Since thermal budget reduction is crucial in ULSI processing, Tay et al. (1987) applied high pressure oxidation to grow gate oxides. At a pressure of 10 atm, an 120 8, thick gate oxide was grown at as low a temperature as 700°C. The pressure ramp-up was performed in N, ambience in order to avoid nonuniform oxide growth on wafers due to temperature instabilities. These oxides shows low interface state densities in the 1010 eV-' cm-, range. In a more recent work (Tay et al., 1990), the same research group demonstrated that high pressure oxidation at 700°C followed by nitrogen annealing at 900°C results in gate oxide films (80 A) with up to 15 MV/cm breakdown field and high quality Si/SiO, interface. In an earlier work, it has been indicated that high pressure oxides and conventional oxides grown at atmospheric pressure show similar radiation response (Gupta et al., 1980). Although the high pressure gate oxidation technique appears to be attractive due to its low thermal budget, a more detailed investigation is required to judge its applicability to ULSI MOS processing, especially regarding the MOSFET reliability. N

3.4.3 Chemically Modified Gate Oxides Over the past decade, a considerable amount of work has been reported on chemically modified gate oxides for MOS applications. The main goal of chemical modification is to introduce controlled quantities of impurities such as nitrogen or fluorine primarily at the Si/SiO, interface

141

to improve the interfacial properties that are critical to the performance and reliability of SiO, . The Si/SiO, interfacial region consists of a non-stoichiometric monolayer followed by a 10-40 8, thick strained SiO, (Grunthaner and Maserjian, 1978). The non-stoichiometric monolayer results from incomplete oxidation and the strained region is due to lattice mismatch between Si and SiO,, which causes a compressive strain in the interfacial SiO, . Relaxation of intrinsic strain at the Si/SiO, interface is an important technique to improve the reliability of MOS devices under electrical or radiation stresses. It is known that tensile strain exists in Si,N, in the Si,N,/Si system. This led to an approach which involves incorporation of a small amount of nitrogen in the interfacial region so as to oppose the compressive strain (Vasquez and Madhukar, 1985). Strain relaxation in such nitrided oxides is probably due to the formation of Si,N,O (Vasquez and Madhukar, 1986). Triangular planer bonding in Si,N,O allows a smoother transition from the tetrahedral bonding in silicon to amorphous SO,. In addition, since the Si-N bond strength is significantly higher than that of Si-H bonds, defect generation by hot carriers and ionizing radiation is suppressed. The other important advantage of introducing nitrogen into SiO, is the improved diffusion barrier properties to boron penetration, an extremely important requirement for p -polysilicon-gated surface-channel p-MOSFETs (Lo and Kwong, 1991). Incorporation of fluorine at the Si/ SiO, interface is another approach to modify the properties of MOS system. Fluorine has been suggested to satisfy some of the dangling bonds at the Si/SiO, interface (Wright and Saraswat, 1989). In a conventional process, the dangling bonds are satisfied by hydrogen during the sintering step. Since the bond strength of Si-F +

142

3 Silicon Device Processing

bonds (5.73 eV) is significantly higher than that of Si-H bonds (3.17 eV), defect generation by hot carriers and ionizing radiation is suppressed. Moreover, fluorine incorporation leads to strain relaxation at the interface (da Silva et al., 1987). Both these approaches to chemically modify thin oxides have been extensively studied. Annealing of gate oxides in NH, (Ito et al., 1982a; Lai et al., 1983) has been reported to achieve such desirable properties as good resistance against impurity diffusion (Ito et al., 1982a) and endurance against hot electron stress (Lai et al., 1983). Rapid thermal nitridation (RTN) is an attractive approach due to its low thermal budget requirement and good control over the resulting nitrogen profile (Moslehi and Saraswat, 1985). Reoxidation (Hori et al., 1989; Yang et al., 1988; Dunn and Scott, 1990; Joshi et al., 1992) or inert gas annealing (Wright et al., 1990) was proposed to reduce electron trap and fixed charge density in the nitrided oxides while still retaining the nitrogen-rich layer at the Si/SiO, interface. However, the electron traps induced by residual nitridation cannot be eliminated completely by reoxida-

tion or annealing, resulting in worse reliability in p-channel MOSFETs (Momose et al., 1991). The reoxidized nitrided oxides used in this case were prepared by rapid thermal processing after the conventional oxide growth. It turned out that reoxidized nitrided gate oxides are superior to pure oxides in numerous aspects. However, the presence of residual nitridation induced electron traps is a shortcoming in these dielectrics and, as a result, pMOSFET reliability is worse than that of the conventional gate oxide MOSFETs. The disadvantage can be avoided by using light NH,-nitridation, but such light nitridation may not be sufficient to prevent boron penetration into the channel region. This trade-off is depicted in Fig. 3-16 (Momose et al., 1991). Compared to NH,-based processes, the N,O-based processes have an important advantage in addition to the process simplicity, i.e., the elimination of any hydrogen-containing species during processing. Therefore, the hydrogen-related disadvantages can be avoided. Depending on process design, thermal budget limitation, and device applications, several processes have

Figure 3-16. Performance and reliability of RTN/ RTO SO, as a function of nitrogen concentration.

3.4 Gate Dielectrics

143

been developed to use the significant advantages offered by N,O process. These include Oxidation of Si in pure N,O (Lo et al., 1991); Nitridation of thermally grown SiO, in N,O (Ahn et al., 199221); Densification and Nitridation of CVD SiO, in N,O (Ahn et al., 1992b); Nitridation of N,O oxides in NH, for p+-poly-Si gated P-MOSFETs (Yoon et al., 1993).

Figure3-17. Comparison of the growth kinetics between N,O and 0, oxidation of Si.

The oxidation process is self-limiting compared with 0, oxidation, as shown in Fig. 3-17, allowing growth of ultrathin oxides with excellent thickness controllability. The process is simple, hydrogen-free and easy to integrate into modern ULSI processes. Because of nitrogen incorporation at the Si/SiO, interfizce during N,O oxidation, the resulting oxynitrides show lower hole trap density, reduced electron trap generation under high-field stressing, and reduced interface state and neutral trap generation under both hot-carrier stressing and X-ray irradiation in comparison to the control oxide. NH, nitridation of N,O-oxides does not reduce electrical and reliability properties of N,O-oxides, with the additional advantage of significantly improved resistance to boron penetration. Finally, study of hot-carrier related reliability in both n- and p-MOSFETs with N,O-based gate oxides under application specific stress conditions such as for SRAM-type pass transistors, CMOS logiccircuit transmission gates and CMOS analog devices shows that all the hot-carrier induced damages (i.e., interface states, electron/hole trapping, and neutral electron traps) are greatly suppressed in N,Obased gate oxides compared with control oxide devices (Yoon et al., 1993). These results suggest that N,O-based gate oxides

are promising for numerous MOS ULSI applications. Fluorine incorporation in the gate oxide has been performed by different techniques, such as immersion of Si wafers in HF prior to gate oxidation (Nishioka et al., 1988), F ion implantation (Lo and Kwong, 1991; Nishioka et a]., 1989) and NF, purge during or before gate oxidation (Lo et al., 1992). Different techniques produce different distributions of fluorine in the gate oxide, resulting in a wide variation of electrical properties. Since excessive fluorine incorporation in the oxide can lead to worse dielectric properties (Lo and Kwong, 1991; Nishioka et al., 1989), excellent control over the amount of incorporated fluorine is necessary which can be achieved by rapid thermal processing (RTP). Fluorination has been reported to increase fixed positive charge but suppress interface state density (Nishioka et al., 1989; Lo et a]., 1992). Wright and Saraswat (1989), on the other hand, reported a negative charge in the fluorinated oxides. The reduction in interface state density has been attributed to passivation of dangling bonds at the Si/SiO, interface by fluorine (Wright and Saraswat, 1989; Nishioka

~

-

-

z

C:

ion 0

0

~ ~ ~ " ~ ~ ~ ~

20

40

60

80

100 120 140 160

Oxidation Time (min)

144

3 Silicon Device Processing

et al., 1989; Lo et al., 1992), whereas the increase in positive charge is due to the formation of nonbridging oxygen defects by incorporation of fluorine in the oxide. Wright and Saraswat (1989) reported that the hot electron induced degradation in MOSFETs is considerably suppressed with an increase in the amount of fluorine incorporated in the gate dielectric. Lo et al. (1992), on the other hand, reported that both the amount and distribution of fluorine in the gate dielectric affect the hot carrier reliability of fluorinated oxides. Only a small process window was observed to result in improved hot carrier reliability as well as radiation hardness as compared to pure oxides. Moreover, the presence of fluorine at the Si/SiO, interface was found to be essential in order to realize a gate dielectric with superior reliability. The improvement in radiation and hot carrier immunity in fluorinated oxides has been mainly due to suppressed interface state generation. Interfacial fluorine incorporation has generally been accepted as a cause for the improvement (Ma and Dressendorfer, 1989). 3.4.4 CVD and Stacked Oxides

Deposition of gate oxide, rather than its growth from the substrate, is an attractive technique to suppress the density of defectrelated breakdowns in oxide films because the deposited oxides are less likely to be affected by the defects from the Si substrate. Another advantage of this technique is the feasibility of low temperature processing, which is an attractive feature from the viewpoint of stringent thermal budget requirements in ULSI MOS processing. Various CVD oxides such as TEOS, HTO, and LTO have been studied (Tseng et al., 1993). Ahn et al. (1992b) investigated hot-carrier reliability of MOSFETs with

z 65 LPCVD gate oxides (silane and oxygen reaction) annealed in presence of N, . The compressive stress in the films after post-deposition annealing was observed to be smaller than conventional thermal oxides, and was suggested to be the cause of improved current drive capability as well as hot-carrier reliability. In a recent report (Ahn and Kwong, 1992), N,O post-deposition is used instead of the conventional N, annealing in order to incorporate a small amount of nitrogen at the Si/SiO, interface. The resulting films show superior hot carrier reliability due to nitrogen at the Si/SiO, interface as well as low defect density due to the deposition of oxides, rather than growth from substrate. Roy et al. (1988) studied oxide films containing a stack of a “pad” oxide and a CVD oxide on top of it. The dramatic reduction in defect density observed in this stack layer was mainly attributed to misalignment of defects in individual components of the stack. Moreover, the stress at the Si/SiO, interface is close to zero due to the stress compensation between component layers. Kawamoto et al. (1987) demonstrated stacked layers with performance comparable to thermal oxide films. Tseng et al. (1991) used =I40 A stacked CVD oxides (40 8, thermal oxide and 100 8, LPCVD/TEOS) for 0.5 pm CMOS process and demonstrated several advantages. Firstly, the number of low field breakdowns was significantly smaller than for the conventional thermal oxides. In addition, due to the smaller levels of stress at the Si/SiO, interface, a large reduction in process induced damage was observed. An optimum ratio of bottom thermal oxide thickness to the top CVD oxide thickness was reported to achieve longer time-tobreakdown and lower defect density. The optimum ratio is a consequence of the compensation between the intrinsic defect

145

3.5 Shallow Junction Formation

3.5 Shallow Junction Formation

densities of the two layers and the mismatch mechanism. The use of oxide and Si,N, in a gate dielectric stack (ON (oxide/nitride) or O N 0 (oxide/nitride/oxide)) can yield two advantages. Firstly, as in the case of stacked CVD and thermal oxide, the misalignment of micropores in the individual components acts as an effective “seal” to prevent the early gate dielectric failures (Roy et al., 1988). Secondly, the use of Si,N, increases the effective dielectric constant of the film and serves as effective barrier against boron penetration. Iwai et al. (1990) studied the hot carrier irnmunity of MOSFETs with stacked ON gate dielectrics. It was observed that by reducing the top nitride thickness to about 30 A, the charge trapping in stacked layers can be significantly reduced and can be comparable to a conventional thermal oxide film. Dori et al. (1987) used ON dielectrics for a dual gate process and demonstrated that the top nitride layer is an effective barrier against boron penetration, which facilitates the fabrication of p +-polysilicon gated p-MOSFETs. In addition, these dielectrics showed a tighter E,, distribution than the conventional thermal oxides. Reduction in electron trapping by reducing the top nitride layer thickness was reported, as also stated by Iwai et al. (1987).

A significant requirement in high-performance semiconductor technologies is CMOS source/drain junction depth reduction to suppress MOS punchthrough leakage and to minimize device short channel effects such as drain-induced barrier lowering (DIBL) in CMOS devices. Device junctions with relatively high surface dopant concentrations, ultra-shallow depths, low contact and sheet resistances, and low junction leakage currents will be critical for advanced CMOS technologies. It has been projected that ultra-shallow junctions with junction depth <60 nm will be required in the source/drain regions of MOSFETs for L,,,=O.25 pm devices. By 2010, Leffis expected to reduce to 0.1 pm geometries, with a concomitant reduction of junction depth, Xj, to 10 nm and junction leakage current to 0.1 nA/cm2 (Table 3-5). In concert with the reduction of junction depths, the surface doping concentration (N,,J in the source/drain junctions immediately next to the channel is expected to reduce from loi8 cm-3 to (5-10 x 10’’ cm-,. The reduction of Xj is dictated by short-channel effects while the reduction of Nsurf is mandated by the high fields near the pinch-off region which cause adverse hot carrier effects. The

Table 3-5. Evolution of MOS S/D junction technology requirements. L,ff (wm)

0.5

0.35

0.25

0.18

0.12

0.10

V”D(V) (nm) Nsurr(cm - 3, Nchanne, (cm-3) Junction leakage (nA/cm2)

5 120

3.3 100

2.2 60

2.2

1018

6 x IOl7 0.2

(7-l0)x 1017 8 x lo1? 0.1

1.5 10 l o x 1017

mid l O I 7 0.8

1.5 25 (5-iolX 1017 1018 0.1

xj

10’8

mid l o i 7 1

40

10’8

0.1

146

3 Silicon Device Processing

simultaneous reduction of Xj and Nsurf results in an excessive increase in the sheet and spreading resistance and, therefore, the sourceidrain series resistance.

3.5.1 Ion Implantation Ion implantation has been the technique of choice for forming shallow junctions. The junction depth is controlled by the implantation energy and subsequent diffusion steps. A lower limit on implantation energy is imposed by reduced beam current, and the lower limit on the diffusion temperature is set by the necessity to anneal implantation damage, activate dopants, and avoid transient enhanced diffusion of dopants during annealing (Fair, 1988; Morehead and Lever, 1986; Sedgwick et al., 1988; Kim et al., 1991). Current generation commercial implanters do not routinely go down to energies much below 10 keV. At extremely low energies (1-10 keV) (Davies, 1985; Hong et al., 1988; Bousetta et al., 1991), there are problems of beam stability and low beam currents (which cause throughput problems). The projected range of commonly used species, such as B for p-type doping, are too deep for formation of ultra-shallow junctions using current generation implanters. Although the problems are somewhat alleviated by using BF, instead of B for p-type, the projected ranges at the lowest currently available energies (x10 keV) are still too large. Also, there are problems associated with the straggle, lateral straggle and channeling in tightly controlling the as-implanted profile to achieve junction depths below 60 nm. Finally, since there is damage associated with the ion implant, it is necessary to anneal it out using the lowest possible thermal budget. There are tradeoffs in terms of the mini-

mum acceptable dopant diffusion (which increases with thermal budget) and junction leakage (which decreases with increasing thermal budget). Residual defects not only increase junction leakage via SRH generation-recombination sites, but can also cause enhanced gate induced drain leakage (GIDL) in MOSFETs. It can be enhanced by residual trap sites which cause defect-assisted tunneling. Driven by a need for lower thermal budgets, there has been a shift from furnace annealing to rapid thermal annealing (RTA). However, the thermal dissolution of these defect clusters produce excess point defects (vacancies and silicon interstitials), which give rise to the phenomena of transient enhanced diffusion of dopants (Fair, 1988; Morehead and Lever, 1986; Sedgwick et al., 1988; Kim et al., 1991) observed in the initial stages of the annealing process. In other words, as the Dt product of the RTA is decreased by reducing the temperature ( T )or time (t), the broadening of the implanted profile cannot be reduced below a certain value which is governed by thermal, defect-assisted diffusion. An alternative solution has been proposed and demonstrated for p+-n shallow junction formation. By implanting an electrically inactive species, such as Si or Ge, to form a fully amorphous surface layer, the channeling effect can be removed (Bousetta et al., 1991; Ruggles et al., 1989). In addition, the fully amorphous layer would result in a better quality crystal after annealing compared to heavily damaged implant layers. The leakage current and final junction depth of the pre-amorphized junctions is very sensitive to the amount of post-annealing residual damage and its location relative to the junction. Although the epitaxially regrown region is free of extended defects, a high density of dislocation loops form on the crystalline side of

3.5 Shallow Junction Formation

the original amorphous/crystalline (a/c) interface. The position of this interface relative to the junction region will determine the amount of leakage current and enhanced diffusion observed (Sedgwick et al., 1988; Brotherton et al., 1989). If the defect region is in the vicinity of the junction, then both leakage current and dopant diffusion increase. Therefore, the tail of the impurity profile must be carefully controlled in order to avoid the damage region near the a/c interface. The question of whether a particular amorphizing species (Si+, Ge', Sb', In', Sn', F') has a different effect on defect formation over another species has been investigated by many research groups. A systematic study by Brotherton et al. (1989) and Ruggles et al. (1989) revealed no difference in boron diffusion in Si+, G e+, and Sn' preamorphized substrates, but Tanaka et al. (1991) and Ajmerd et al. (1986) found that Ge+ preamorphization produced fewer end-of-range defects and had lower leakage current than Si+ preamorphized samples. Sb, although of the opposite conductivity type to boron, can also be used for pre-amorphization. Sb is much heavier than both Si and Ge, and

147

therefore produces a sharper crystalline/ amorphous interface so that the defects can be controlled with minimal thermal budget. The estimated concentration required for amorphorization with Sb is about one order of magnitude less than Ge (Davari et al., 1989). In addition to forming an amorphous region, n-type Sb compensates the boron in the tail region, resulting in a sharp junction. The end of range dislocation loops are annealed out for heat cycles as low as 950 "C and 10 s for an Sb dose and energy of 1 x 1014/cm2, 40keV, which produces a 60 nm amorphous layer. Davari et al. (1989) fabricated p +/ n junctions by implanting boron into Sb-pre-amorphized layers, followed by annealing. The experimental conditions and junction characteristics are shown in Table 3-6. Shallow junctions with lower leakage current and fewer end-of-range defects than Si pre-amorphization were achieved. A 600 8, deep p'/n junction has been fabricated by Sb pre-amorphization and low energy BF, implantation [13]. Although the exact mechanism which causes the difference in defect structure in not known, it is certain that the density and position of the end-of-range defect +

Table 3-6. Experimental conditions and junction characteristics of p+-n junctions fabricated by antimony pre-amorphization. No.

Ion/energy/dosc (keV, atoms/cm2)

Boron dose (atoms/cm2)

x,

R

Annealing ("C, s)

(nm)

(aim)

800/300 900/ 10 950/lO 950110 950jlO lOOO/l 0 800/l800 800/900 0 0

85 90 95 105 50 110 110 115 75 75

123 192 197 170 156 160 399 230 120 90

I@(-5.0V) (nA/cm2)

~~

1 2 3 4 5 6 7 8 9 10

Sb/40/1 x 1014 Sb/40/1 x lOI4 sb/40/1 x l o L 4 Sb/40/1 x l O I 4 sb/60/3 1014 s b p o / i x loi4 sbj40/1 x 1014 Sb/40/1 x l o i 4 Sb/40/1 x lOI4 Si/30/1 x IOl5

265.0 8.0 7.5 4.7 1.3~10~ 2.7 100.0 3.6 2.0x 106 4.1 x lo8

148

3 Silicon Device Processing

with respect to the dopant profile play key roles in determining the amount of enhanced diffusion observed. If the defect region is in the vicinity of the junction, leakage current and enhanced diffusion due to Si interstitials increase, and a higher density of dislocation loops at the a/c interface allow fewer interstitials to pass through into the regrowth region from the crystalline side. Therefore, careful defect engineering is required. Fluorine is known to segregate near defect sites and therefore acts as a marker for defects, such as in BF, implantation (Tsai et al., 1978). Ohyu et al. (1990) and Ando et al. (1990) performed F/B dual-implantation and observed a reduction in boron diffusion. They explained that the fluorine immobilized the Si interstitials which cause the enhanced diffusion of boron. Fluorine post-implantation has been shown to reduce phosphorus and arsenic diffusion (Kato, 1990), reduce leakage current, and decrease the hot-electron induced interface trap density in MOS capacitors as well (Ohyu et al., 1990; Nishioka et al., 1988). The improvement in electrical properties was believed to arise from the termination of dangling bonds by the fluorine, thereby reducing the trap density, or the stress state of the Si/SiO, interface was affected by the presence of fluorine. By combining fluorine pre-amorphization with low energy (10 keV) BF, implantation, the advantages of implant channeling elimination and diffusion retardation in the tail region were realized by Ando et al. (1990). Shallow n+-pjunctions have been fabricated by using As, As,, and Sb implantation followed by RTA or low temperature furnace annealing. Shibata et al. (1990) was able to fabricate a 60 nm, low reverse current junction by simply implanting 2 x 10'' cm-' dose As at 25 keV and annealing at 450°C for 5 h. Instead of using

As, Sb was implanted at 35 keV (10 keV), 4 x 1014 cm-, dose by Sai-Halasz and Harrison (1986) to fabricate a 80 nm (65 nm) n'/p junction after 16 min annealing at 950 "C. Their electrical characteristics showed very low leakage and low sheet resistivity. In comparison with As, Sb has smaller diffusion coefficient and its concentration enhancement is also less pronounced. For a given mean ion implant depth, Sb has less straggling. The lateral straggle at mask edges is even more significantly diminished. This is critical to deep sub-micrometer MOSFET structures where the source/drain junction edges must be as abrupt as possible. Dual-implant techniques can be applied towards n+-p junction formation. Phosphorus was implanted into Sb-preamorphized Si by Harame et al. (1991). Using As, ion implantation instead of As' ions and rapid thermal annealing, 40 nm n+-p junctions with very low leakage current (< 0.5 nA/ cm2) up to 2 V reverse bias have been realized by Park et al. (1982).

3.5.2 Advanced Techniques for p+-n Junction Formation The main disadvantage associated with ion-implantation is the residual defects remaining near the critical junction area and the need for high temperatures to eliminate them. Various techniques have been attempted in order to overcome the difficulties associated with the fabrication of shallow p f - n junctions using ion implantation. These include: Diffusion from doped deposited layers Epitaxial Si, Ge, and Si, -xGex Polycrystalline Si and Si - xGex Silicide Borosilicate glass (BSG) Spin-on oxide Gas-immersion laser doping

3.5 Shallow Junction Formation

-

Gas phase diffusion Plasma immersion ion implantation

3.5.2.1 Diffusion from Doped Deposited Layers The advantage of using doped layers above the contact region as a diffusion source is that the diffusion profile in the substrate has a high surface concentration and is very steep without the characteristic channeling tail observed in ion-implantation. When using a constant diffusion source, the surface layer is highly doped so that the dopant concentration at the source/substrate interface is above the solid solubility for that particular annealing temperature. Various materials have been used as a diffusion source for shallow junction formation: epitaxial and polycrystalline Si, crystalline and polycrystalline Si, -,Ge,, spin-on oxide, borosilicate glass (BSG), and silicide. Due to the presence of high diffusivity paths along the grain boundaries of polysilicon, dopant diffusion within the poly-Si is fast compared to that in the single crystal silicon, and therefore, dopant distribution is uniform within the poly-Si. Since only mobile dopants can diffuse into the Si substrate, the surface concentration is fixed at the solubility limit for the annealing temperature. Another factor in poly-Si source diffusion is that the transport of dopant from the poly-Si into the single crystal silicon can be greatly affected by the nature of the poly-Si/Si interface. For example, an interfacial oxide will create a barrier for dopant diffusion into the substrate (Raicu et al., 1990). In situ arsenic doping of poly-Si for shallow (40-50 nm) n+-p junction formation has been demonstrated by Hsieh et al. (1990) using rapid thermal CVD (RTCVD). Georgiou et al. (1990) investi-

149

gated the p f -n junction formation through BF, implantation into LPCVD deposited poly-Si. Poly-Si has also been applied in the fabrication of shallow emitters in bipolar transistors (Nouri and Scharf, 1992); Hamel et al., 1992). Si, -xGex can be used as an alternative diffusion source, with the added advantage of increased selectivity of Si, -xGex deposition between Si and SiO, compared with poly-Si deposition (Grider et al., 1991; Sanganeria et al., 1991). The process sequence and diffusion behavior is similar to that of the poly-Si diffusion source. Grider et al. (1990) selectively deposited Si, -xGex ( x = O . 3 ) by RTCVD followed by 10 keV boron implantation to form a 40 nm p +-n junction. When device dimensions are downscaled to 0.25 pm or less, it becomes increasingly necessary to use metal silicides, self-aligned (SALICIDEs) to the diffusion areas to reduce contact and interconnect resistance which become comparable with the channel resistance (Osburn, 1990). Since silicon consumption during silicide formation is a part of the junction depth, both the silicide thickness and the diffusion of dopant beyond the silicide should be minimized. Compared to the conventional SALICIDE process in which junctions are formed before silicide formation, dopant diffusion from titanium and cobalt silicide layers into silicon substrate, the silicide-as-diffusion-source (SADS), has received much attention. In this process, the silicide is formed before the junction. Dopants are then implanted into the silicide, followed by RTA drive-in to diffuse the dopants into the substrate. This process has the potential of minimizing the diffusion length beyond the silicide and produces a junction that follows the contours of the rough silicide/Si interface so that the junction is not locally penetrated and shorted.

150

3 Silicon Device Processing

A novel SALICIDE technology uses rapid thermal annealing and ion-beam induced interface mixing for self-aligned Ti silicide formation, and a doped silicide as diffusion source for shallow junction formation (Ku et al., 1990). The ion-beam mixing can break up the native oxide at the TijSi interface and achieve interface mixing that enhances the Ti-Si reaction rate and results in a smooth silicide surface. The detailed structure and process steps of this technology are shown in Fig. 3-18. After polysilicon gate patterning and oxide spacer formation, a layer of titanium was sputter deposited on the wafers. These wafers were then implanted with 28Sif ions to achieve interface mixing. The wafers were then first annealed at a relatively low temperature in the presence of

Gate oxide n-

r’

p-Si 750A titanium deposition

Si ion-implantation

I

si+ l

l

Ti \

Low temperature RTA (SSO’C, 30s in N2) Selective etching High temperature RTA in N2

As ion-implantation CVD oxide deposition BPSG anneal & impurity drive-in

C/VD oxide

Figure 3-18. Process sequence of SALICIDE technique using ion-beam mixing, doped silicide and RTA.

nitrogen using RTA. The titanium nitride and unreacted Ti were then selectively removed followed by a high temperature RTA in an NH, ambience for contact barrier formation. Suitable impurity ions are then implanted into silicide layers for shallow silicided junction formation. After BPSG deposition, high temperature RTA is used to drive-in the implanted ions from the silicide layers into the Si substrate as well as to anneal the BPSG layer, followed by contact opening, A1 sputtering and sintering. In general, this technology has several significant advantages over other techniques including enhanced Ti-Si reaction rate, improved surface morphology, and smoother silicide/Si interfaces due to the suppression of the native oxide effects at the Ti/Si interface, and the formation of the same silicide thicknesses on both nand p-channel devices. By controlling the subsequent drive-in conditions (RTA time/ temperature), silicided shallow junctions with sufficiently high carrier concentration at the silicide/Si interface were achieved (Ku et al., 1989). The p’/n diodes and LDD p-channel MOSFETs with Ti SALICIDE structures fabricated using the doped silicide technique showed excellent electrical characteristics (Ku et al., 1988). There are several critical issues associated with SADS processes, however. The implantation of dopants into very thin silicide films is limited by the channeling of boron through the polycrystalline silicide. In addition, the dopant concentration at the silicide/Si interface varies with the dopant redistribution in the silicide/silicon system which is determined by the complicated interactions of diffusion within the silicide, surface segregation, and the extensive loss of dopant via evaporation. In Fig. 3-19, SIMS profiles are shown for diffusion of boron and arsenic from various

3.5 Shallow Junction Formation

151

C

.-0 e (P

* L C P,

z

0

0

implanted silicides into Si (Maex et al., 1991). The depth scale of the SIMS profiles starts at the silicide/Si interface. As can be seen, out-diffusion of dopants from CoSi, and MoSi, is much easier than in the case of TiSi, and TaSi,. In the case of TiSi,, formation of metal dopant compound precipitates (TiAs and TiB,) has been observed during annealing in the implanted TiSi, layer and at the TiSi,/Si interface (Probst et al., 1988). The defect clusters in the implantation-damaged zone may act as nuclei for the formation of metal dopant compounds during drive-in annealing. This compound formation results in dopant immobilization and thus low carrier concentration at the TiSi,/Si interface. As a consequence, the contact resistance between p-n junctions and TiSi, is unacceptably high, especially for boron. Finally, material characterization and dopant profiling are becoming increasingly difficult when both the silicide thickness and the junction depth are only tens of nanometers.

Figure 3-19. SIMS profiles in Si after diffusion of (a) B and (b) As from various diffusion sources upon furnace treatment. The origin of the depth axis is the silicideiSi interface.

Takemura et al. (1987) demonstrated the use of borosilicate glass (BSG) to fabricate shallow emitters. BSG and doped poly-Si emitter technologies are combined to fabricate the base and emitter regions, respectively. After the window has been etched over the emitter region, BSG film is deposited by CVD over the entire wafer. Boron drive-in is done by RTA to form the intrinsic p- base region. The BSG film is removed by reactive ion etching, leaving behind boron doped sidewall spacers around the emitter window. Then, n f poly-Si is deposited and annealed to form a shallow emitter junction. The BSG spacers allow the formation of p + regions, which naturally link the intrinsic and extrinsic base regions. The resulting boron profile is very steep, and the base resistance can be controlled by adjusting the boron concentration in the BSG film. M. Saito et al. (1992) applied solid state diffusion process and RTA to fabricate 0.1 pm PMOS with ultra-shallow junctions. The schematic diagram of the solid-

152

3 Silicon Device Processing

(4

[ LDDJ

[ SPDD J Solid Phase Diffused Drain

Lightly Doped Drain

(b) 1 / 1 (BF2) 0

15 keV 4x ~ ~ ~ ~ c r n - ~ 1000°C 15sec 1000°C 3sec 950°C 15sec

0

0

(

]

SPD ( BSG )

]

4 x10~~crn”

100nm 0

1000°C15sec

phase diffused drain PMOS structure is shown in Fig. 3-20. The highly doped BSG sidewall is used as the diffusion source for the ultra-shallow junction formation. The junction is extremely shallow compared with those formed by BF, implantation, as shown by the SIMS profiles. Unlike other solid source diffusion materials, the deposition of spin-on films can be done at room temperature, which therefore eliminates one thermal cycle. Usami et al. (1992) used spin-on phosphorus doped oxides and polymeric-boron doped films to obtain very shallow junctions. By controlling the RTA parameters and the amount of B and P in the doped film, ultra-

Figure3-20. (a) Solid phase diffused drain structure. (b) Boron SIMS profiles.

shallow junctions 50 nm deep and less were fabricated. The junction depth was found to increase with temperature, heating rate, and surface concentration. The effect of heating rate on the enhanced diffusion of B and P was attributed to the formation of point defects at the film/substrate interface due to the difference in thermal expansion coefficients. These ultra-shallow junctions, however, exhibited very large leakage and required a second annealing process (SOOOC, 60 s) to remove defects. Although this reduced the leakage current, the junction depth nearly doubled to 100 nm after the second annealing process.

3.5 Shallow Junction Formation

3.5.2.2 Gas lmmersion Laser Doping Gas immersion laser doping (GILD) incorporates the dopant into very shallow layers using a melt/regrowth step to drive in a gas phase surface adsorbed impurity (Carey et al., 1985; Kato et al., 1987; Sameshima et al., 1987). Usually a doping gas is enclosed in the chamber during the laser irradiation. The incident laser fluences cause the the silicon to melt and simultaneously create dopant atoms by photolysis or pyrolysis of the doping gas molecules. Then dopant atoms are incorporated into a shallow molten region by the liquid-phase diffusion. Finally, the molten region is recrystallized in the way of liquid-phase epitaxy, and the doping process is completed. Pulsed excimer lasers such as XeCl operated in the ultraviolet wavelength region are often used for laser doping. Since single-crystal silicon has a large absorption coefficient at the ultraviolet region (Jellison and Modine, 1982), the incident laser fluences are absorbed extremely close to the surface of the silicon substrate ( z 20 nm). It is only able to melt a shallow region, resulting in very shallow junctions. Dopant atoms are known to be supplied mainly from the adsorbed layers formed either prior to the laser irradiation or during the irradiation (Bentini et al., 1988; Matsumoto et al., 1990; Landi et al., 1988). The formation of the adsorbed layers is sensitive to the surface state of the sample and the pressure of the doping gas (Matsumoto et al., 1990; Foulon et al., 1989); this is the reason for the rather poor control of sheet resistances and junction depths as compared with the ion-implantation technique. In order to control the sheet resistance, a two-step doping process consisting of the deposition of a doping source and the incorporation of dopant

153

atoms in silicon in a successive process was developed (Inui et al., 1991). 3.5.2.3 Gas Phase Diffusion Recently, a novel approach based on surface chemical adsorption and solid state diffusion has been developed (Nishizawa et al., 1990a, b; Kiyota et al., 1991, 1992; Inada et al., 1991) for very shallow, high quality p+-n junction formation. This process consists of three steps: (1) removal of native oxides from the Si surface by thermal annealing in H,, (2) formation of an adsorbed boron layer on the Si surface by supplying 5 % B,H, diluted in nitrogen, and (3) solid phase diffusion of boron atoms from the adsorbed boron layer into the Si substrate in a hydrogen environment. Boron atoms are incorporated into Si by diffusion in an oxygen-free atmosphere at a relatively low temperature. This process differs from the conventional diffusion process in which boron diffusion is performed in an oxygen-rich ambience. Results show that the boron concentration in the adsorbed boron layer on the Si surface exceeds the solid solubility of boron in Si. In addition, ultra-shallow p f - n junctions (junction depth z 700 A) with excellent electrical characteristics (leakage current < 2 x A/pm2 at 5 V) have been achieved (Kiyota et al., 1991). Ultra-thin base (base width < 25 nm) bipolar transistor with excellent performance has also been demonstrated (Inada et al., 1991). The formation of an adsorbed boron layer on SiO, was also examined and results showed that the total amount of boron adsorbed onto the SiO, surface was less than 1 YOof that adsorbed onto the silicon surface, indicating selective doping.

154

3 Silicon Device Processing

3.5.2.4 Plasma Immersion Ion Implantation In plasma immersion ion implantation (PIII) (Chueng, 1991), a wafer holder of 10 inches diameter is immersed in a high-density plasma created by an electron cyclotron resonance (ECR) source. When microsecond pulses of negative bias are applied to the wafer holder, electrons are repelled from the wafer surface, creating a sheath region. Positively charged ions are accelerated across this sheath and implanted into the wafer. The charge per pulse is measured by an integrator attached to a Rogowski loop on the wafer holder, and implant time is chosen to set the implant dose. One major concern with the PI11 doping process is the contamination level involved from the multi-species gaseous plasma, the sputtering of the wafer holder and the chamber wall. Because there is no mass selection or ion focusing in this system, the result is largearea implantation of all the ion species created in the plasma source. Since both the processing chamber and ECR source chamber are fabricated from aluminum parts, detrimental contamination due to PI11 needs to be carefully studied. Fabrication of a sub-100-nm p + junction requires a two-step implant: first, ions from an SiF, plasma are implanted to create a surface layer of amorphous Si (a-Si), and B is then implanted into the a-Si layer using a BF, plasma (Pic0 et al., 1991; Qian et al., 1991). The thin amorphous layer reduces B channeling into the substrate (Wu et al., 1989). Enhanced diffusion of B in the a-Si, as reported by Hong et al. (1991), is also observed. Additionally, the presence of F may further reduce the diffusion of B in a-Si during annealing (Jones and Cheung, 1993). With PIII, the two implantation steps can be performed without breaking

vacuum at extremely low energies (1 - 6 kV), and with high ion dose rates. Low-resistivity, ultra-shallow p'/n junctions have been demonstrated using the PIII technique (Qian et al., 1991; Minondo et al., 1993). Other advantages of PI11 are continuous bias waveform adjustment, high throughput and no destructive field oxide charging during the short implant times required for shallow junctions (En and Cheung, 1993).

3.6 Metallization In order to meet the quality required for high performance ICs, more and more functions are integrated into each device. For system-on-chip or high speed design, multilayer metallization is indispensable. Today, 4 to 6 metal layers are not uncommon for bipolar and CMOS ASICs (application specific integrated circuits). To save space and increase packing density, planarized dielectrics, vertical-walled, filled vias and tight-pitched metal lines are increasingly being used, as shown in Fig. 3-21. There are several critical issues in the development of multilevel metallization technology : -

Refilling via-holes and contact-holes with high aspect ratios. Planarizing structures with both narrow and wide lines/spaces. Developing new conductor materials.

The desirable characteristics required for interconnecting materials are (1) low resistivity, (2) ability to withstand subsequent elevated processing temperatures, (3) chemical compatibility with intermetal dielectrics and their formation methods, (4) chemical compatibility with other metals, ( 5 ) good resistance to electromigration as well as (6) stress migration. In

3.6 Metallization

Figure 3-21. Schematic cross-section of a two-layer multilevel interconnect system.

addition, they must be deposited uniformly on the underlying topography and etched easily by RIE. This chapter will cover several metallization topics : gate electrodes, contacts, and multilevel interconnections. Advanced interconnection concepts and technologies that will be useful for deep submicrometer CMOS circuits will also be discussed. 3.6.1 Gate Electrodes Gate electrode materials have traditionally been the realm of heavily doped n-type (n +) polysilicon. Typically, the p-channel MOSFET using an n + polysilicon gate will have a threshold that is too negative, and a boron implant is required to increase it. This counterdoping produces a buried channel type device that has poor turnoff or subthreshold characteristics. A larger work function allows the device designer to reduce the boron implant dose, thus improving the subthreshold characteristics. Conversely, the threshold of an n + polysilicon gate NMOS device is too low because a moderately doped p-type silicon surface is depleted by the low work function of the n + polysilicon gate. The acceptor doping concentration must, therefore, be increased to raise the threshold. Other methods to minimize short channel effects include the use of surface chan-

155

nel devices: i.e. n + poly for NMOS and p + poly for PMOS. With proper choices of polysilicon thickness, implant dose and annealing conditions, flat-band voltages corresponding to the degenerately doped polysilicon/SiO, interface can be obtained (Wong et al., 1988). However, even when the proper gate work function is achieved, a slight polysilicon depletion which causes device current degradation could still take place at reverse biases. There is evidence that rapid thermal annealing (RTA) after the polysilicon implant helps reduce the depletion significantly through increased dopant activation. This depletion in polysilicon will become more severe as the gate oxide thickness is downscaled. As the gate oxide thickness is decreased, increased carrier density is required to limit the current loss due to polysilicon depletion effects. Taking into account grain-boundary and interfacial segregation where the dopants are generally considered to be electrically inactive, chemical concentrations of the dopants, as measured by SIMS, should be even higher than the indicated carrier density. A major concern with p + polysilicon is the penetration of boron from the degenerate p f polysilicon through thin gate oxide into the channel region (Sun et al., 1989). Boron penetration introduces V, shift and degrades VT control. The thermal cycle, polysilicon gate thickness, and boron dose should be optimized to meet the requirement of p+-poly work function without causing boron penetration. Boron penetration through thin gate oxide is most easily studied by fabricating p+-poly gate MOS capacitors on n-Si substrates and monitoring the C-V shift. Since the diffusivity of boron is also greatly increased in a hydrogen environment, care must be taken to minimize hydrogen or moisture in the annealing ambience after boron is implanted

156

3 Silicon Device Processing

Table 3-7. Effects of oxidation and passivation/reflow on boron penetration after the p+-poly gate is doped to 1 x 10,' boron/cm3 (Sun et al., 1989). to,

7 I I 7 13 13 13 13 13

(nm)

Process conditions

Process temperature

dry oxidation (10 nm) wet oxidation (20 nm) LTO cap + N, annealing 30 rnin LTO cap + steam annealing 60 min BPSG cap + N, annealing 15 min BPSG cap + steam annealing 15 min LPCVD nitride cap (100 nm) LPCVD nitride cap + 30 rnin N, TEOS cap + N, annealing 60 rnin

into the polysilicon gate. RTA allows the highest temperature for p -poly processing without boron penetration. Effects of conventional passivation/steam reflow processes on boron penetration in p+-poly-Sigated MOS devices have been extensively studied by Sun, et al. (1989) and are summarized in Table 3-7. It was also reported (Baker et al., 1989; Sung et al., 1989; Wong and Lai, 1986) that fluorine (from BF, implant) enhances boron penetration into and through the gate oxides of p-channel MOSFETs using pf polysilicon gates. Inclusion of a phosphorus co-implant or TiSi, salicide was shown to minimize this effect. The boron penetration phenomenon can be modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the SiOJSi interface. Elemental boron is therefore considered to be superior to BF, as an implant species for surface channel submicrometer PMOS devices. Another disadvantage of polysilicon gates is found in their low conductivity. A good alternative to doped poly-Si is a gate interconnection involving a polycide. The polycide structure uses a silicide shunt on a doped poly-Si pad to reduce the overall sheet resistance to as low as 1 n/u.This technique combines the advantages of the +

800 "C

850°C

900 "C

OK OK OK AV,.=O.l V OK OK AVT=0.2 V

OK OK

OK AVT=0.3 V OK

-

-

OK OK

AVT=0.2 V

-

-

-

-

-

AVT=0.2 V

AK=1 V

OK

-

-

well characterized Si0,-poly-Si interface with the advantages of the silicide, which include low resistivity and thermal and process stability. Various silicides and their material properties are listed in Table 3-8 (Murarka, 1983; Chow et al., 1986; Kato et al., 1986). However, the lateral diffusion of dopants in various silicides is extremely high (Chu et al., 1990), causing gate workfunction shift as well as the formation of a depletion capacitor at the polysilicon/SiO, interface. When polycide interconnections are used to connect p + contacts, considerably high contact resistance is observed

Table 3-8. Silicide resistivity at room temperature. Material CoSi, HfSi, MoSi, NbSi, Nisi, PdSi, PtSi TaSi, TiSi, WSi, ZrSi,

Co-Sputter (pa cm)

Metal-Polysilicon Reaction (pa cm)

25

17-20 45-50

100 70 50-60

50-55 35 40-70

50 30-35 28-35 35-45 13-16 35-40

3.6 Metallization

due to boron segregation at the SiO,/WSi, interface and the lateral diffusion of both As and B through WSi, during high temperature treatment, as shown in Fig. 3-22 (Fuji, 1992). To reduce the degradation of dual-polycide-gate n'/p CMOS polycide transistors as well as dual polycide interconnections, the thermal budget should be kept as low as possible. More recently, chemical vapor deposition (CVD) has been used to produce polycide films, particularly WSi, because the films have lower resistivity, less contamination of oxygen, and better step coverage. The first process to be successfully integrated into production was that based on the reduction of tungsten hexafluoride (WF,) by silane (SiH,) (Saraswat et al., 1983; Shioya and Maeda, 1986). However, WSi, films produced by this process contain fluorine in high amounts (> 10,' atom/cm3), which, upon annealing, diffuses into the underlying gate oxide and leads to performance degradation of metal oxide semiconductor (MOS) devices (Shioya et al., 1987a; Wright and Saraswat, 1988). In addition, the silane-produced films suffer from poor step coverage and adhesion problems, and tend to crack and peel off, especially over extreme topography (Ellwanger et al., 1991). These problems can be avoided by changing the reducing agent to SiH,Cl, (dichlorosilane - DCS). The fabrication of DCS-WSi, films in a batch reactor (Shioya et al., 1987b; Selbrede, 1988; Hara et al., 1990) as well as in a plasma-enhanced single-wafer system (Wu et al., 1988) with lower F content, improved step coverage and adhesion, have recently been published. A specific problem with DCS-WSi, is related to in-depth compositional nonuniformity. DCS-WSi, films, especially those grown on poly-Si, show a reduction in x at the initial stages of the deposition

157

+

Figure3-22. Diffusion path of the dopants in the conventional dual polycide structure.

that is below the optimal regime of 2.2 to 2.6. Values smaller than 2, the stoichiometry of the stable tungsten silicide, have been observed (Hara et al., 1990). This is extremely unfavorable since the formation of a W-rich region at the WSi,/poly-Si interface can cause excessive interdiffusion of Si, localized stress, and adhesion problems following a high-temperature oxidation process. Sheet resistance nonuniformity across the wafer has also been a problem in DCS-WSi, in contrast to silane-based WSi, . Using single wafer reactor, highly uniform in composition (in depth and in lateral position) CVD WSi, films have been deposited on 200 mm Si wafers using SiH2Cl,/WF6 on Si0, or poly-Si (Telford et al., 1993). Annealing at 900°C in N, of such films deposited on P-doped poly-Si resulted in a uniform reduction of x to a value of 2.1 to 2.2 and resistivity values in the range of 80 to 100 psZ cm. The as-deposited films were predominantly in the hexagonal structure of WSi,, which transformed to the tetragonal structure upon annealing at temperatures above 600 "C. The films had a very good step coverage even at high aspect ratios and did not crack or peel off upon annealing. The films contained relatively little F: ~6 x lo1, to 2 x 10" atoms/cm3.

158

3 Silicon Device Processing

For future scaled CMOS devices using thinner gate oxides, it is advantageous to work with a gate electrode material with a larger work function to obtain the desired threshold voltage. The larger work functions of Mo (4.7 V), W, or refractory silicides produce low and nearly symmetrical thresholds for p- and n-channel devices on moderately doped substrates (Kim et al., 1983). In addition, MOSFETs with refractory metal gates require much less channel doping than n polysilicon gate devices (Takeda et al., 1985) and reduced subthreshold leakage. However, they are rarely used directly on gate oxides as gate electrode materials due to incompatibilities with the underlying gate oxide, inability to form stable dielectrics, and poor contamination barrier characteristics. +

3.6.2 Contacts After aluminum deposition, most processes need an annealing step at 400 “C anneal. This reduces defects and lowers contact resistance by dissolving any “native” silicon oxides between the aluminum and silicon. During this annealing - and other high-temperature processing steps - silicon tends to diffuse into the aluminum forming silicon pits and aluminum spikes. The silicon-into-aluminum diffusion can be suppressed by adding 0.5 -2% silicon to a deposition source. When this alloy cools, however, the solubility of silicon in aluminum decreases, i.e., the aluminum becomes saturated with silicon and any excess silicon precipitates. The precipitated silicon causes an increase in contact resistance. The use a barrier layer between A1 and Si can reduce the diffusion of silicon into the aluminum during sintering and, at the same time, act as “etch-stops” to avoid aggressive etching of Si in the contact area due to a misalignment error.

The diffusion barrier can be chemically inert to the materials it separates, or it can be stuffed with small amounts of impurities to inhibit diffusion along fast diffusion paths such as grain boundaries or microcracks that the impurities seal. Diffusion barriers must satisfy a number of criteria. For example, they must be chemically and thermally stable, and they must adhere to both the silicon substrate and the metal film. In addition, they must have minimum intrinsic stress to avoid stress-induced-microcrack failures (Kohlhase et al., 1989). Titanium-tungsten (Ti-W) and titanium nitrides (TIN) are first choices for barrier layers for several reasons. They have very high thermodynamic stabilities and are relatively easy to process. Tungsten is the principal component of Ti-W; it contains 3-28 % titanium to improve adhesion, contact resistance, corrosion behavior and ease of etching. Although Ti-W alloys have shown excellent barrier properties, they have very high compressive film stress, resulting in film delamination from the sputtering chamber walls and the subsequent increase in particles. In addition, while TiW can be an excellent etch-stop with chlorine-based dry-etch compositions, it is also very prone to post-etch corrosion and undercut. Titanium nitride (TiN) is an excellent choice because of the following advantages : -

-

-

Extremely high thermal stability - TiN resists silicon interdiffusion at temperatures up to 600 “C for 20 h (Wittmer and Melchior, 1982); Low and stable contact resistance when used with a titanium silicide layer - contact resistivity for a Si/TiSi,/TiN/Al scheme remains stable when exposed to 550°C for 20 min (Wittmer, 1985); Low sheet resistance - can be used as a

3.6 Metallization

-

local interconnection in CMOS technology (Jeng et al., 1993); Low stress (zlo9 dyne cm-’) (Kohlhase et al., 1989); Excellent etch-stop capability (Brat et al., 1987).

Several methods have been proposed for TiN deposition, including sputtering, reactive evaporation, thermal nitridation of pure titanium and CVD. Recent results have shown that high quality TiN/TiSi, bilayer can be formed using Ti-rich TIN films deposited from a single TIN,., alloy target followed by rapid thermal nitridation. Excellent contact resistance and junction thermal stability as well as tight control over the stoichiometry of the sputtered films have been demonstrated, as shown in Fig. 3-23 (Nakamura, 1993). Reactive sputtering of Ti in the presence of N, results in films with low stress and high adhesion (Circelli and Hems, 1988; Stimmell, 1986). The metallization scheme typically included a 10 to 30 nm thick layer of pure titanium, 80 nm and 120 nm thick layers of TIN and 800 nm of aluminum-I % silicon. TIN can also be formed by thermal nitridation of titanium in the presence of NH3

159

with furnace annealing or rapid thermal processing. The latter, in particular, forms a TiN/TiSi, structure during a two-step, self-aligned salicide process (Ku et al., 1987). However, there are limits to the quality of the resultant titanium nitride and its thickness. For high aspect ratio contact or via holes (>2: l), film conformality is a critical issue. Collimated sputtering technology has been developed to deposit low resistance Ti and TIN films to improve the contact coverage. A collimator, whose aspect ratio is 1.O, is placed between the sputter target and the wafer so that the wafer can collect the fraction of Ti clusters with normal incidence angle to the surface of the wafer. The problems with collimated sputtering have been shown to consist of no deposition on the side of the contacts, low deposition rate, and particles generation from the collimator. CVD TIN becomes a viable alternative, since these films can be almost 100% conformal. It is also possible to completely fill sub-micrometer contact holes. Traditional CVD TIN processes involve the reaction TiC1, + N, + H, at 1000°C or TiCl,+NH, (6 TiCl,+ 8 NH, + 6 TiN+24 HCl+N,) at lower

Figure 3-23. Breakdown voltage distributions of pure Ti and Ti(N,,,J samples after (a) 4 5 0 ° C (b) 525°C annealing. Breakdown Voltage [ V ] ( Vb: > l O b A )

Breakdown Voltage [ V ] (Vb: >lObA)

160

3 Silicon Device Processing

temperatures (Price et al., 1986; Kurtz and Gordon, 1986). Since TiCl, and NH, react at room temperature to form a solid product, it is difficult to mix the gases and introduce them to the reactor without gas phase nucleation. It has been found (Price et al., 1986; Kurtz and Gordon, 1986) that these two gases neither react in the gas phase nor deposit any TiN film on surfaces in the temperature range of ~ 2 5 0 -3 5 0 " C . Based on this fact, both a low-pressure, hot-tube system at 700°C and an atmospheric pressure, cold-wall tube reactor and deposited films at 500-650°C were developed. More recently, a number of studies have demonstrated that the TiCl, + NH, reaction could be carried out in a low-pressure, cold-wall, single-wafer reactor at similar temperatures and high deposition rates (500-1000~/min)(Yokoyama et al., 1989; Sherman, 1990; Smith, 1989; Buitinget al., 1991). One group used a reactor with warm (rather than cold) walls ( ~ 2 5 0 - 3 5 0 ° C )to prevent deposition on the walls (Smith, 1989). Although resistivity of these films is considerably higher than bulk TiN, it can be kept quite low when depositions are done at higher temperatures. Values from 100 to 300 p!2 cm are typical, with the lowest values observed at the highest temperatures. Excellent diffusion barrier properties have been demonstrated (Sherman, 1990; Reid et al., 1991; Travid et al., 1990) between silicon and aluminum. Contact resistance of = l o p 60 cm were obtained for TiN deposited onto titanium silicide (salicide) contacts and pf-Si (Sherman, 1990; Travid et al., 1990) with excellent leakage current. A number of studies have shown that conformality for TIN can be outstanding, even for sub-micrometer trenches (Yokoyama et al., 1989; Sherman, 1990; Smith, 1989; Buiting et al., 1991). Rather than using TiCl, as the Ti precursor in

CVD TIN, one could use an organometallic molecule, thereby avoiding chlorine contamination. Two choices are available. One possibility would be the use of tetrakis (dimethylamido) titanium, Ti(N[CH,],), and pyrolize it to yield TiN, since the molecule already contains nitrogen. It has been shown that a more successful approach involves reduction with NH, (Fix et al., 1989). In this case, deposition in an atmospheric-pressure, cold-wall tube reactor at 200-400 "C yielded reasonably pure stoichiometric films. Another approach would be to use biscyclopentadienyl titanium, (C,H,),Ti, again with NH, (Yokoyama et a]., 1990). Here, reasonably pure films are reported at deposition temperatures of 450 'C in a low-pressure, coldwall reactor. If either film, when deposited at temperatures 400"C, can be shown to have properties similar to the higher temperature films deposited from TiC1, , they will be better choices than aluminum or silicon. Finally, the deposition temperature can be lowered using a glow discharge. Although a number of studies have shown that this is possible for TiCl,+ + N, + H, or TiCl, + NH, , they all result in a large amount of chlorine incorporation. One exception has been reported where a TiCl,+NH, mixture was excited at 13.45 MHz, and the chlorine content of the film was found to be quite low at 400°C (Hilton et al., 1986). The performance of MOS ICs depends on several parameters, of which the RC time constant is probably the most important. As the size of MOSFET devices decreases, the RC time delay due to the wiring (metal and polysilicon layers) that is used to contact the device gate, source, and drain, does not scale with the shrinking of the physical dimensions of the device. Therefore, for downscaled MOSFETs, the RC speed enhancement can be leveled by

161

3.6 Metallization

the time delay due to the wiring. Selfaligned silicides (SALICIDEs) including PtSi, TiSi,, CoSi,, MoSi,, and WSi,, have been reported to simultaneously form silicide on source/drain and diffused interconnections with the gate. The conventional SALICIDE process flow for n-channel MOSFETs fabrication consists of the following steps. The sidewall oxide spacers are formed after polysilicon gate patterning, lightly-doped source/drain ion implantation, and activation. A thin metal film chosen to form metal silicide is then deposited to cover the entire surface area. Metal silicide is thermally formed at both polysilicon gate regions and source/drain diffusion regions. A selective etching process removes the unreacted metal from the silicon dioxide surfaces but does not attack the metal silicide. A layer of doped glass (BPSG or PSG) is then deposited, followed by flow, contact window opening, reflow, and A1 metallization. For noble and near noble metal silicides, the metal is the dominant moving species during the reaction. This reduces the probability of bridging between gate and source/drain because of less lateral silicide formation. One major disadvantage of no-

bie and near noble metal silicides is the high temperature limitation. This temperature limitation can be relaxed by the use of refractory metal silicides, due to their high temperature stability. The use of TiSi, and CoSi, in SALICIDE technology has received considerably more attention than other metal silicides because of low resistivity, good adhesion, and high temperature stability. A comparison between CoSi, and TiSi, is shown in Table 3-9. Using the conventional TiSi, SALICIDE process for CMOS applications causes several problems, including the formation of native oxide at the metal/Si interface which slows down the reaction and results in a rough silicide surface, critical ambient control, lateral silicide growth, different amounts of Si consumption in p-channel and n-channel devices, and non-ohmic contacts due to significant dopant redistribution during silicide formation. The native oxides at the TijSi interface cause the reaction to proceed in a non-uniform fashion, resulting in a rough silicide surface. In addition, a high concentration of As at the TijSi interface retards titanium silicide formation. Therefore, the growth rates of titanium silicides formed on n + (As doped)

Table 3-9. Comparison of the properties of CoSi, and TiSi, Properties _____

~~

CoSi,

TiSi,

10-15

13-16 Yes good poor (2-2.25) x 10" 700 "C Si poor poor good poor poor

~~________

Resistivity (pR/cm) Metal-dopant compound formation Thermal stability on single crystal Si Thermal stability on polysilicon (undoped) Mechanical stress (dyne/cm') Reaction temperature with SiO, ("C) Dominant diffusion species during silicide formation Sheet resistance control Resistivity to dry/wet etching Native oxide consumption Thermal stability in the Al/silicide/Si system Lattice match with Si

no good poor

(8-10)~109 > 1000"C co good good poor poor good

162

3 Silicon Device Processing

and p + (B doped) regions are different, resulting in different amounts of silicon consumption in the diffusion regions of pand n-channel MOS devices. Furthermore, significant amounts of dopant redistribution in source and drain areas occurred during SALICIDE formation, which makes the ohmic contact resistance very difficult. The above mentioned problem is avoided in the source-drain extension structure (Taur et al., 1993), in which shallow p f (or n') source-drain extensions are used in conjunction with deeper p f (or n') source/drain regions implanted after thick oxide spacer formation, as shown in Fig. 3-24. The shallow extension depth is decoupled from the deep junctions required for the SALICIDE process. A 600 A deep p + source-drain extension has been fabricated by Sb pre-amorphization and low energy BF, implantation (Taur et al., 1993). Another approach is to use selective silicon deposition to form raised sourcedrain structures (Mazure et al., 1992; Kotaki et al., 1993). Issues with SEG elevated S/D structures and technologies are: capacitance increase, effects of faceting.

3.6.3 Interconnections The reduction in interconnection feature sizes has lead to reliability degradations

caused by electromigration and stress-induced migration. The increase in wiring resistance as a result of the increase in chip size has been solved by increasing the number of interconnection levels. To meet this requirement, the thicknesses of both conductors and inter-layer dielectrics have been kept constant to reduce parasitic resistances and capacitances, making contact- and via-hole aspect ratios greater than one. Therefore, new contact- and viahole filling technologies as well as highly reliable multilevel interconnection conductor systems will be required. An example of interconnection materials and technologies for 256 M DRAM is shown in Table 3-10 (Kikkawa, 1992). As traditional interconnection materials A1 as well as various alloys of A1 have been used. Aluminum has a number of ideal properties: (1) low resistivity = =2.8 psZ cm); (2) excellent adhesion to SiO,; and (3) excellent wire bonding properties. However, because of its very low melting point (660 "C), electromigration occurs at relatively low temperatures and low current densities. Electromigration of A1 atoms takes place at the grain boundaries within the metallization line. The electron stream creates a flow of these atoms because they are less tightly bound than those within grains where the atoms are bound in lattice positions. Because the atom flow

p -TYPE SUBSTRATE

Figure 3-24. Schematic cross-section of 0.1 pm CMOS devices with source/drain extension structure for silicided junctions.

163

3.6 Metallization

Table 3-10. Interconnection materials and technologies for 256M DRAM (Kikkawa, 1992). Interconnection Word line Bit line Bit contact Capacitor contact Peripheral contact

Material

Process

Design rule

Aspect ratio

WSi,,poly-Si WSi, N + poly-Si N + poly-Si W/TiN/Ti

sputtering/LP-CVD sputtering doped LP-CVD doped LP-CVD blanket W-CVD collimated sputtering reflow sputtering (L. T.) collimated sputtering reflow sputtering (H. T.) collimated sputtering sputtering

0.25 0.25 0.25 0.25 0.3

1-1.4 0.5-1.0 2-4 3-6 3-4

0.3

3-4

0.3 0.25

3 -4 1-2

0.25 0.6

1-2 1-1.5

0.6

1-1.5

Al-Ge/TiN/Ti

Metal line

Via-hole

Al-Si-Cu/ TiN/Ti TiN/Al-Si-Cu/ TiN/Al-Si-Cu/TiN cu W/TiN/Ti Al-Ge/TiN/Ti

sputtering blanket W-CVD reactive sputtering reflow sputtering (L. T.) reactive sputtering

occurs along the grain boundary in the direction of electron flow, a grain boundary that extends completely across the metallization pattern (“bamboo” structure) should have greater electromigration resistance. However, this type of structure is not manufacturable. The practical method of reducing grain electromigration is to introduce impurities, such as Si and Cu, that passivate the grain boundaries. The additions of high percentages of Cu make alloys difficult to etch and prone to corrosion problems; therefore, large numbers of circuits are still being made with A1 (1 YOSi) or A1 (1 OO/ Si) with a small percentage of Cu ( 1 0 . 5 YO).The addition of Si causes Si “nodule” formation due to Si precipitation within the line that can occur during cooling or during the operation of the device (Shen et al., 1985). As the nodule grows in size, the current density in the A1 around the nodule increases and the line can eventually crack because of the stress around the growing nodule. Nodule growth can also cause interlevel metal

shorts or time-dependent breakdowns. Another traditional problem with A1 metallization has been hillock formation. Hillocks are formed by solid-state diffusion of A1 to relieve the film stress during thermal cycling at temperatures below those where plastic flow can occur. Hillocks are also formed by electromigration. Ti (0.2-3 wt. YO)has been substituted for Cu to add to an A1 (1 YO Si) alloy to reduce electromigration. These additions of Ti increase the resistivity. Thin multilayers of Ti and A1 (1 % Si) have been proposed and demonstrated with a 10 to 100 times improvement in the mean time to failure compared to A1 (1 YOSi) films (Shen et a1.,1985; Jones et al., 1985; Gardner et al., 1985). It must be noted that it is especially important to create a good barrier between the contact to silicon if an Al-Si-Ti metallization is used because the solubility of Si in the A1,Ti intermetallic compound can be as high as 15% (Shen et al., 1985). A new interconnection structure using TiN/Al-l %Si-0.5 %Cu/TiN/Al-

164

3 Silicon Device Processing

1 %Si-0.5 %Cu/TiN/Ti layered films has been developed for both electro- and stress-migration-resistant interconnections (Kikkawa et al., 1991). The multilayer interconnection shows larger Vickers hardness value, less tensile stress relaxation and longer electromigration lifetime in comparison with Al-Si-Cu single layer. These improvements are due to the rigid intermetallic compounds, Ti,Al, at the interface between TIN and Al-Si-Cu (Kikkawa et al., 1991). Contact holes with minimum geometries in the order of 0.25 pm and aspect ratio greater than one must be plugged with an interconnection material having good coverage, low resistivity, stability during thermal processing, and compatibility with existing processes. Aluminum alloy reflow sputtering is a promising low-cost technology for contact-hole filling. Aluminumgermanium (AI-Ge) alloy (Kikuta et al., 1991) can flow and fill in quarter-micrometer contact holes at 300 "C due to its lower eutectic temperature (424 "C) than other Al-alloys. A highly reliable sub-half-micrometer via and interconnection technology using high temperature sputter filling of Al-Si-Cu alloys has been developed by Nishimura et al. (1992). A thin Ti underlayer was employed to prevent Si from precipitating. The substrate temperature during the sputtering for a filled via was 500°C. Complete filling of a 0.15 pm diameter via with aspect ratio of 4.5 has been realized with four orders of magnitude improvement in electromigration resistance compared with conventional via formation sputtering. Silver is a potential candidate for ULSI interconnection because of its lowest resistivity compared with other interconnect materials. However, silver has numerous processing difficulties, which limited its wide use in the past (Table 3-1 1). The ma-

Table 3-11. Properties of Al, Cu, Ag and Au. A1 Resistivity (pa cm) 2.8 Melting point ("C) 660 EM endurance 1 (normalized to Al) Heat of formation -400 of oxide (kcal/mol) Diffusion into SiO, no Agglomeration no RIE easy

Cu

Ag

Au

1.7 1083 20

1.6 961 10

2.2 1063 20

-40

- 1.3 -0.8

yes small difficult

no Yes severe no diffi- diffcult cult

jor problems are the lack of reliable dry etching and the requirement of high temperature annealing needed to obtain low resistivity. A novel planarized silver interconnect technology with TiO, passivation has been developed by Ushiku et al. (1993). The process sequence is shown in Fig. 3-25. The first annealing at 400°C results in Ag planarization due to significant surface diffusion of Ag. After etching back or CMP process, the sample is then annealed at 600 "C. During annealing, Ti diffuses upwards through the Ag films to the surface and forms a TiO, layer. The TiO, layer protects the agglomeration in Ag films during annealing. Recently, a novel contact filling technique has been developed based on polysilicon plug and Ni silicidation with a TIN barrier layer (Iijima et al., 1992). The process details are shown in Fig. 3-26. This

(a)

(b)

(d

(d)

Figure 3-25. Process sequence of Ag interconnection technique: (a) Ag deposition; (b) annealing at 400°C; (c) etch-back or polishing; and (d) annealing at 600 "C.

3.6 Metallization Poly-Si Plug Poly-Si

Ni

TiNlTi a) NI Sputtering Si-Substrate Ni,Si Ni b) Ni silicidation

-

1

Silicidation stop

c) Selective metal etch Si-Substrate Figure 3-26. Schematic process sequence of the Ni,Si contact plug technology: (a) Ni sputtering; (b) Ni silicidation ; and (c) selective metal etching.

process is self-aligned, selective, and is capable of filling both shallow and deep contacts simultaneously with the help of a TIN silicidation stop layer. During Ni silicidation, Ni diffuses into polysilicon plug, resulting in a flat plug surface. Excellent junction leakage and transistor characteristics have been obtained with these selective Ni,Si contact plug techniques. In order to achieve lower contact resistances in high aspect ratio contact-holes, metal plugging is necessary. CVD of metals, particularly selective deposition of interconnections, represents a fundamentally different capability for integrated circuit manufacture than has been available in the past. With its advent vertical wiring capabilities arise that will enhance the pace at which industry can implement multilevel metallization for three or more levels of interconnections. Especially in the deep submicrometer range, CVD metallization will reduce processing problems by provid-

165

ing an effective technique to achieve planarized wiring and by increasing reliability. For the past few years, A1 CVD has been investigated for its capability of achieving conformal step coverage (It0 et al., 1982 b; Cooke et al., 1982; Lvey et al., 1984), selective growth onto the Si surface (Amazawa and Arita, 1991a; Amazawa et al., 1988; Sasaoka et al., 1989; Masu et al., 1990; Shinzawa et al., 1989) and single crystal growth on Si wafer (Kobayashi et al., 1988). To provide full control over selective and nonselective deposition of high quality Al, Tsubouchi et al. (1992), have developed a plasma excitation technique for A1 CVD deposition. Dimethylaluminum hydride [DMAH; (CH,),AlH] was chosen as the precursor due to its high vapor pressure (z2 Torr at 20 "C, ten times higher than that of triisobutyl aluminum). A1 is produced from DMAH and H, via the following reaction :

.A l - H + i H,

+

A1 4

+ 2CH,

CH,' Using this process, single crystal (100) and (111) Al are selectively deposited on (111) Si and (100) Si, respectively with resistivity close to the bulk resistivity. The selective growth mechanism is explained sequentially as follows : (1) the Si surface is hydrogen (H) terminated after cleaning by dilute HF, followed by a pure water rinse; (2) the terminated H atom (the terminator) reacts selectively with the CH, radical (the selective reacting radical) of adsorbed DMAH; and ( 3 ) after A1 deposition, the H atom of the DMAH molecule remains on the deposited surface as the new terminator. In the case of the nonselective deposition, the plasma supplies both electrons and H atoms to the SiO, surface. As a result, the reaction of C H , + H + CH,

166

3 Silicon Device Processing

occurs on the SiO, surface, producing a thin A1 layer on SiO,. A 0.25 pm via plug process based on selective CVD aluminum for multilevel interconnect has been developed by Amazawa and Arita (1991 b) using triisobutyl aluminum (TIBA), as shown in Fig. 3-27. Surface native oxides on Al, Ti, or W have prevented A1 growth. In situ RF cleaning was used in this study to remove native oxides prior to A1 deposition. In order to avoid A1 nucleation on dielectrics treated by R F etching, amorphous Si was deposited on dielectrics. 0.25 pm via holes with very low contact resistivity and excellent electromigration reliability have been demonstrated. In recent years CVD tungsten has received the most attention among CVD metals and is likely to replace aluminum alloys in the lower metallization levels because of better deposition uniformity than aluminum and excellent electromigration resistance. The higher resistivity of W relative to A1 can be tolerated because line lengths in the lower levels are relatively short. Tungsten originally attracted attention because of its potential for selective

deposition. Tungsten deposition only occurs in the oxide or nitride windows that have been opened to the surface of the Si and not on the oxide and nitride surfaces. In applications such as via filling, barrier metal, and source/drain/gate shunts, selective deposition is attractive since it would allow the elimination of mask and etch steps, thereby reducing the complexity of the production process. Moreover, because deposition occurs only at the base of the feature, void-free feature filling is automatic and step coverage is not an issue. However, tungsten has poor adhesion to the underlying silicon (in the case of vias). The adhesion can be improved by performing a precleaning step to remove any residue or native oxide that may be present, followed by the deposition of an adhesion layer such as TiN. A novel doubleself-aligned TiSiJTiN contact with selective CVD tungsten plug for submicrometer device and interconnection applications has been developed by Wang et al. (1991). As shown in Fig. 3-28, the reactively sputtered TiN layer on dielectric-I layer provides a stable surface which prevents any tungsten nucleation during selective CVD

Figure 3-27. Selective CVD aluminum via plug process.

3.6 Metallization

167

After Low temperature anneal, selective wet etch, and N

N-Well

I

After dielectric 1 (Dl) deposition, TIN deposition, and contact patterning Ti

After: Plasma CHF3- 0 contact dry et 900°C NH 3 rapid thermal aneal to densify D1, and convert

After selective CVD W deposition

,w Figure 3-28. Schematic process flow of SCVDW (selective CVD tungsten) plug process.

tungsten process. However, tungsten will nucleate on the TiN/TiSi, layer formed by RTA of TiSi, in presence of NH, , The selective nature of the tungsten deposition is initiated by the highly exothermic, rapid reaction of WF, with silicon to produce solid tungsten and gaseous silicon fluorides (2 WF, + 3 Si -, 2 W + 3 SiF,). Since the reaction involves Si consumption, the deposition is selective. The reaction is characterized by a fast growth rate, but the W thickness is self-limiting. After a thin layer of W is deposited, a barrier is created. This barrier prevents the WF, molecule from diffusing through the W film and reacting with the Si surface, or the Si is prevented from reaching the surface and reacting with WF,. The final W film thickness is dependent on substrate, deposition temperature, WF, partial pressure and

total pressure. Thicker W films can be deposited by adding a reducing agent such as H, to the reactor. Hydrogen dissociatively adsorbs on the growing tungsten film and reduces co-adsorbed WF, producing W and volatile H F (WF,+3 H, W + 6 HF). Hydrogen does not readily adsorb dissociatively on silicon dioxide or nitride. It is this difference in adsorption behavior which, at least in principle should allow deposition to continue in a selective manner. Silicon reduction reaction which initiates selective deposition removes Si from under the edge of the oxide at the base of the contact hole and deposits W under the oxide. The haloing effect (encroachment of W at the Si/SiO, interface) as well as the wormholes (tunnel formation in the Si) (Broadbent and Stacy, 1985) can be mini--f

168

3 Silicon Device Processing

mized by adding silane in the gas phase to reduce Si consumption at the W/Si interface (3 SiH, + WF, + 2W + 3 SiF, + 6 H2). Silane reduction provided faster deposition rates, a lower deposition temperature and was a much cleaner process. However, the resulting W films contain Si and have larger resistivities than films deposited by hydrogen reduction (Kusumoto et al., 1988; Yu et al., 1989). Because of these interfacial problems, barrier layers such as TIN have been deposited between Si and W. Conformal composite layer metallization, such as tungsten selectively deposited onto patterned aluminum interconnection, has been demonstrated (Hey et al., 1986). Open circuit failures have been reduced dramatically because of improved step coverage and greater electromigration resistance from the uniform tungsten cladding layer that can be made to encapsulate the aluminum lines. Selectivity loss is the most serious concern with selective tungsten deposition. The selectivity loss on patterned silicon wafers has been related to the reaction intermediates or by-products such as silicon subfluorides and silicon oxyfluorides formed by etching of SiO, by WF, or H F ablation of SiO, (Foster et al., 1988; Hirase et al., 1988; Kwakman et al., 1988). Experimental results suggested that volatile tungsten subfluorides produced on tungsten surfaces adsorb on surrounding SiO,, producing tungsten nuclei (Creighton, 1987). Process parameters which influence selectivity loss include the partial pressures of WF, and H, , total pressure, deposition temperature and time, and reactor configuration. In addition, dielectric surface properties also affect selectivity loss. For example, sputter-deposited SiO, exhibits a greater tendency towards selectivity loss than thermally grown SiO, (Sumiya et al., 1987). Because of these difficulties in selec-

tive tungsten CVD, blanket deposition with etch-back has been adopted in multilevel metallization schemes to achieve via fills. Copper is a potential candidate for interconnection because of its high conductivity and high reliability. Theoretically, copper exhibits significant advantages over aluminum as a high density interconnection material. The electrical resistivity of copper is 30-50% lower than that of aluminum alloys. Also, the electromigration performance of copper interconnections is expected to be more than two orders of magnitude better than for systems based on aluminum alloy due to copper’s considerably higher melting temperature. Thus, copper interconnections deposited with the same design rules as A1 alloys could increase the operating frequency of devices as well as allow higher current densities. Despite these advantages, however, there are several concerns with copper interconnection technology : (1) the lack of a suitable Cu dry-etch process; (2) copper is incompatible with silicon and acts as a “poison” to the active device area by forming deep acceptor level traps in the forbidden gap, reducing the minority carrier lifetime; (3) the lower heat of formation of copper oxide compared to Si/SiO, results in low thermal stability during annealing, planarization and etch-back processes; and (4) the high diffusion coefficient of copper in silicon dioxide. The fast diffusion of Cu through oxide and then into the Si substrate can be prevented by completely encapsulating Cu, as shown in Fig. 3-29 (Cho et al., 1991). Figure 9-29A involves the use of selective tungsten for encapsulation. Figure 9-29 B starts with the deposition of a seed layer (TiW) for tungsten into LTO trenches. The diffusion of Cu into the sides of trenches is protected by the use of nitride spacers.

3.6 Metallization

169

Figure3-29. Process sequence for (A) non-planar and (B) planar Cu interconnection with W cladding.

Selective CVD for metal surfaces has been the subject of a number of contradictory reports in recent literature, most probably because of the differences in surface pre-treatments, reactor systems and deposition conditions used by various groups (Jain et al., 1992a; Reynold et al., 1991;Norman et al., 1991; Baum and Larson, 1992). A number of groups have proposed that the interaction of organometallic precursors with the SiO, surface is a crucial aspect of the selective deposition of metals such as W and Cu in the presence of SiO, (Cheek et al., 1992; Creighton, 1991). The surface of SiO, consists partially of hydroxyl groups (Si-OH) and oxo-groups (Si-0-Si) which are most likely to be the active sites available for absorption of the precursor molecule. Differences in selectivity have been attributed to the differences in the interaction of (hfac)CuL molecules with the hydroxyl groups in a series of model experiments on SiO, (Cab-O-Sil) surfaces (Hardcastle et al., 1991). Chemi-

cally passivating or removing the surface hydroxyl groups resulted in modified selectivity (Jain et al., 1992b; Dubois and Zegarski, 1992). Copper CVD following the intentional modification of the SiO, surface hydroxyl groups on the silica surface using functionalized silanes with a variety of copper(1) precursors resulted in controlled selective deposition of copper on SiO, versus other metal surfaces. 3.6.4 Planarization for Multilevel Interconnections

The trend toward modular VLSI design with computer aided routing of interconnections is pushing the technology toward multilevel metallization structures. Besides easing the routing problem, thus enhancing circuit performance, this results in smaller chip size connected with cost reduction because of the larger number of chips per wafer. Unfortunately, the topography created by the first-level metallization of-

170

3 Silicon Device Processing

ten makes continuous metal lines difficult in upper metal levels, seriously affecting die yield. To compensate for this topography, various planarizing and smoothening processes have been developed. In order to planarize the deposited dielectric layer over severe topography, the deposited dielectric layer must be thicker than the required final film thickness since a significant portion will be removed by the planarizing process. Furthermore, the thick deposited dielectric layer must be free from defects. The key film characteristics desirable for interlevel dielectrics are : -

-

-

-

-

Good step coverage on metal and dielectrics; Good gap filling for planarization; Low as-deposited stress and small hysteresis on heat treatment; No stress-voiding in metal lines either on heat treatment or long term storage; High dielectric breakdown strength; Stability with respect to ion migration; Low density of defects/particles.

A common problem is the formation of voids or key holes in gaps with high aspect ratio. The CVD technology used to deposit a gap filling dielectric layer was originally based on the oxidation of silane. Silane oxide, however, does not give a very uniform coating over topography with aspect ratios of 0.5 or larger. The use of the CVD TEOS/oxygen process greatly improves the conformality of the deposited oxide. As a result, TEOS oxide has become the most popular film type for interlayer insulation in sub-pm devices. Reflow oxide films under A1 metallization are generally made with TEOS oxide films using normal pressure CVD. One technology attracting attention is the combination of TEOS and 0, normal pressure CVD. The step coverage is improved from TEOS+O, and voids in concave sections are eliminated.

The dielectric films deposited by thermal TEOS/ozone process tend to be rather porous and may absorb a significant amount of moisture (Nguyen et al., 1990). Therefore, it is common to use it in the dep/etch process so that the bulk thermal TEOS/ ozone film is etched away leaving only this film in the gap filling area (Pennington et al., 1989). The step coverage capability and the dielectric quality of the TEOS/ozone films can be improved by increasing the deposition pressure. The deposited TEOS/ozone films at atmospheric pressure (APCVD) or sub-atmospheric pressure (SACVD) using high ozone concentration tend to be thicker at the inside corners of a gap, thus giving a rounded or “reflowed” profile over a step (Nishimoto et al., 1989; Fujino et al., 1991; Kotani et al., 1989; Lee et al., 1990). This is opposite to the cusp formation over a step in standard CVD dielectric films. Furthermore, these AP-TEOS/ozone or SA-TEOS/ozone films tend to be denser and absorb less moisture than TEOS/ ozone films deposited at low pressure (Kotani et al., 1989; Lee et al., 1990). However, AP-TEOS/ozone film deposited with high ozone/TEOS ratio tend to be surface sensitive and pattern density sensitive. This would make the step coverage vary with different surfaces and pattern densities. Adding Ge to AP-TEOS/ozone films can significantly alter the mechanical properties of the film, dramatically reducing the reflow temperature and improving film stability (Baret et al., 1991). The capability of the AP-CVD TEOS/ozone deposition process to fill submicrometer high aspect ratio gaps or re-entrant profiles could provide significant simplifications to the planarization processes for future ULSI structures. The resist spin-on and etch-back procedures were developed to provide the low

3.6 Metallization

temperature planarization process (Adams and Capio, 1981). This process is based on the planarization capability of a photoresist which is coated in liquid form over the topography surface in question by spinning the wafer at high speed. This technique starts with the deposition of a 1-1.5 pm thick layer of CVD silicon dioxide. The exact thickness is determined by such parameters as polysilicon thickness, first metal layer thickness, and geometry pitch. After oxide deposition, the photoresist is spun onto the wafers and baked above the glass transition temperature to flow the resist and create a planar surface. Next, the nearly planar surface of the photoresist is transferred to the underlying dielectric film by using a dry-etching process that etches the photoresist and the dielectric layer at nearly equal rates (1 :1 selectivity). The etching process is continued until all the photoresist is removed so that the smooth photoresist surface contour is transferred into the dielectric film. Finally, a second deposition of silicon dioxide brings the interlayer metal dielectric to the desired thickness for the second level of metallization. This process has been widely used to planarize dielectric layers over A1 metallization. However, the degree of planarization depends not only on the resist coating thickness, but also on underlying geometries. Good planarity is obtained only for small closely spaced patterns. The planarity degrades rapidly when the pattern width or gap width exceeds several micrometers. Although this problem can be reduced by using an additional photolithography step (Sheldon et al., 1988), it in- creases the process complexity. The surface planarity of the spin-on layer can be greatly improved if thermally flowing polymer is used for the spin-on layer. Sufficient planarization can be achieved over geometries as large as several hundred micrometers (Ting et al., 1989).

171

While a very planar surface can be obtained by the photoresist etch-back technique, the planar surface results in oxides of varying thicknesses in areas where vias are to be cut to the first metal layer over diffusion areas, field areas, or polysilicon. Oxide thicknesses can vary by nearly 100 % from area to area. For example, oxide thickness of nearly 1.8 pm can exist in areas where vias are over diffusions and are as thin as 0.9 pm of oxide over polysilicon. If a via fill or tungsten plug process is not available, a tapered via etching process produced by photoresist erosion etching is necessary to ensure adequate metal step coverage into the via. Tapering the developed vial profile in the thick resist layer has required post-exposure baking or carefully controlled post-develop baking of the thick resist. These processes are very temperature sensitive and often result in incomplete developing of the polysilicon vias. In addition, since the photoresist is lost during the via etch, it should be at least as thick as the thickest oxide. The via etching time must be long enough to etch the thickest oxides - those over diffusion areas. Consequently, the thinner oxides over polysilicon get nearly 100 YOover etching. This results in vias that are oversized with no taper. The resist spin-on etch-back process can be simplified if the spin-on material can be used either as a stand-alone dielectric layer or in conjunction with CVD dielectric films. Spin-on glass (SOG) films have received much attention for this application. There are many different types of SOG materials such as silicates, doped silicates and a variety of polysiloxanes. They can be coated from liquid to give a spin-on film with good surface planarity. SOG films can be cured at relatively low temperature to give a silicon dioxide-like film. However, the film properties depend on the

172

3 Silicon Device Processing

starting material and the curing conditions as well as subsequent processing conditions (Pai et al., 1987). In general, the density of SOG layer is lower than the thermal oxide and it cracks easily for thick layers. Therefore, it is usually used in conjunction with other CVD dielectric layers to form a CVD-SOG-CVD sandwich structure (Nguyen et al., 1990). A partial etch-back process is generally used to remove SOG from the via opening areas to avoid excessive moisture absorption in the SOG films. The silicate SOG film cured at low temperature is rather porous and can absorb a large amount of moisture. The porosity of the film can be reduced if the SOG is densified at high temperatures (i.e., 9OO0C), which is not acceptable for aluminum. Another way to reduce the porosity is by using siloxane materials, which have organic groups such as methyl or phenyl groups at the end of silicon-oxygen chain to relieve film stress and to reduce moisture absorption. With proper material choice, the moisture absorption of a siloxane film can be reduced to a negligible amount. In general, the wafers are soft baked after coating at 150-350°C to remove the solvent base. Then they are cured at 425 “C for 60 min. The resulting film is nearly 100% silicon dioxide with some organic substituents. This smoothing process fills in any voids created by the initial oxide deposition process. After curing, the process continues with a “blanket” etch-back. Then, the resulting substrate is capped with additional CVD oxide forming a CVD-SOG-CVD sandwich structure. Thick single coatings of SOG tent to crack. Topographies on the wafer can produce SOG as thin as a few hundred angstroms over high spots to as thick as 8000 8, between minimum spaced line pairs. To minimize the chance of cracking, the SOG is

spun on in two applications with soft baking after each coating application. The final cure plays an important role for the quality of the finished film. SOG cracks from thermal shock. If SOG remains in areas where vias are to be cut, out-gassing of retained or absorbed water can cause an “exploding” or “poisoning” of vias (Ting et al., 1987). This results in high contact resistance or open circuits. To prevent this, SOG should be etched back so there is none where vias were to be cut, leaving only fillets sandwiched between CVD oxide structures. The integrity of organic substituents containing siloxane films is destroyed by oxygen plasma, such as those commonly used for organic resist stripping. The siloxane film with organic groups partially removed by oxygen plasma is very porous, and it cracks easily and absorbs a large amount of water. Therefore, the oxygen plasma steps must be eliminated if the siloxane film is to remain on the wafer surface such as that used in the non-etch-back SOG planarization process. Otherwise, the siloxane film must be protected from the oxygen plasma by using a dense capping layer over the SOG film. A physical etching process has an incident-angle-dependent etching rate. It generally has a lower etching rate for flat surfaces than sloped surfaces. Therefore, physical etching processes can be used to remove sharp corners to give a smoother surface. Using repeated etching and deposition cycles, a planarized surface can be obtained over small dimensions. To reduce wafer handling for repeated depletch cycles, several equipment manufacturers have developed automated systems that combine etching and CVD deposition processes in a single system. By using different combinations of deposition and etching cycles one can obtain various degrees of

3.6 Metallization

planarization in the final dielectric layer surface. The well-known AMP-500 system uses plasma TEOS for the main dielectric layer. However, plasma TEOS does not have sufficient step coverage for tight geometries. Therefore, it is used in conjunction with thermal TEOS/O, to provide the needed step coverage. Unfortunately, thermal TEOS/O, has rather poor dielectric properties (i.e., a high water content as mentioned previously) so an etchback process is used to remove most of the film leaving only pockets of thermal TEOS/O, in the gaps to provide a planarized surface. Both SOG and resist etch-back planarize over a distance in the tens-of-micrometer range. For deep sub-half-micrometer devices, etch-back and SOG techniques are not sufficient for wafer planarization or topography smoothing. Chemical-mechanical polishing (CMP), which involves the use of mechanical padpolishing systems with fumed-silica as the slurry, offers one major advantage: global wafer planarity, as shown in Fig. 3-30. Planarity across the wafer is required for the following reasons: ~

-

-

Global planarity can compensate for shallow depth of focus (DOF) ( < 0.5 pm) with high numerical aperture lenses (i-line, 365 nm). This is essential for fine line lithography over a large stepper field size. With photoresist thickness variation over topography, CD control is very diffucult. Global planarity also improves metal step coverage and its associated reliability. Since metal is situated where the device topography is most severe, perfectly flat metals will improve device yield and reliability. Global planarity exerts an additive topography effect on the final metal layers.

173

Non-planarization

I

-

Smoothing

I

i

n n

Local planarization

I Global planarization Figure 3-30. Planarization capability.

Mechanistically, the removal rate, drldt, of a glass surface during polishing follows the Preston equation (Preston, 1927) drldt = K p (dsldt)

(3-1)

where p is the applied pressure, and ds/dt is the relative velocity between the glass surface and the pad. K , the proportionality constant, is termed the Preston coefficient. The units of K, area/force, relate it to the mechanical properties of the glass. At the fine polishing situations that are normally encountered in planarization, the Preston coefficient is related to the Young’s modulus and the hardness of the glass. It is only a weak function of the applied pressure and the relative velocity. During a brittle grinding situation, macroscopic chunks of material are removed from the glass surface, whereas polishing is characterized by near surface interactions and removal of molecular clusters of material. The key tooling elements of a CMP equipment are shown schematically in Fig. 3-31 (Thomas et al., 1991). Wafers are held by rotating wafer chucks or heads. The wafer surface is exposed to the opposing surface of a polishing pad which is also rotating. A controlled amount of pressure is applied during this process. A slurry fed

174

3 Silicon Device Processing

--KGz? Figure 3-31. Key tooling elements of CMP equipment.

at a controlled rate wets the polishing pad and the wafer surface. The process of polishing is thought to occur according to the following sequence: (a) Formation of hydrogen bonding between the solvated oxide surface and the solvent in the slurry. The solvated oxide surface pertains to both the surface of the wafer and the surface of the slurry particles. (b) Formation of hydrogen bonding between the solvated surfaces on the wafer and on the slurry particles. (c) Formation of molecular bonding between the surfaces. (d) Removal of the bonded wafer surface as the slurry particle moves away. Polishing occurs when the depolymerization reaction proceeds faster than the polymerization reaction. The cleavage of the Si-0-Si below the wafer oxide surface is controlled by the diffusion of water through the oxide. The role of the slurry particle is to impart a chemical “tooth” to the polishing process. The strength of the bond between the slurry particle surface and the wafer surface determines the effective kinetic coefficient of friction between the two surfaces during polishing. Thus the chemical nature of the oxide dispersed in

the slurry is crucial to the final oxide removal rate. Cerium oxide shows in the highest removal rate, followed by Zr and Ti oxides. However, for the planarization process, the choice of the slurry components must be made not only based on the removal rate, but also on the planarity obtained, and the ability to distribute the particles effectively in a stable colloidal distribution. To achieve planarity with the polishing process is relatively simple. However, obtaining simultaneously stable, high removal rates and uniformity across the wafer is more challenging. The removal rate falls off with the age of the pad, causing process control problems. This dropoff with pad life is due to plastic deformation of the pad surface and the resultant glazing. Pad glazing appears to result in two phenomena: (1) the net area of contact between the pad and the wafer increases and hence the effective polishing pressure drops, and (2) the channels available for slurry transport to the interior of the wafer are blocked. It is hypothesized that the latter has the stronger effect. It has also been observed that an isolated small elevated feature on an otherwise flat topography polishes must faster than a dense array of elevated features. Large high areas polish the slowest. Hence differing densities of features within a die can result in degraded planarity due to different removal rates (Daubenspeck et al., 1991). Such a pattern sensitivity in polishing degrades within-die uniformity and if uncontrolled, might expose underlying layers in one portion of the wafer while leaving large under-polished regions in other parts. CMP can also be applied to form the aluminum contact and wiring plugs with different polishing liquids (Hayashi et al., 1992; Kikuta, 1993). Multilevel pla-

3.7 Cluster Tool Technology

narized-trench-aluminum interconnection using aluminum reflow sputtering and CMP has been demonstrated. Laser planarization is a viable technique for the fabrication of VLSI and ULSI interconnection layers (Magee et al., 1988; Wang and Ong, 1990). As shown in Fig. 3-32, via hole filling with a thin film of Au, Al, or Cu can be effectively planarized by briefly melting it with a pulsed XeCl (308 nm) excimer laser in a process vacuum chamber with substrate heating. Planarization is rapid because of the high surface tension and low viscosity of clean liquid metals. Micrometer and submicrometer diameter contacts and vias have been filled with A1 under proper conditions (Magee et al., 1988; Wang and Ong, 1990; Liu et al., 1989; Pramanik and Chen, 1989). Due to the high thermal diffusivity of A1 (1 cm2/s), the time required for heat transfer through a 1 pm thick film is only about 10 ns. A pulse tens of nanoseconds long is sufficient to melt the metal overlayer while minimizing metallurgical and thermal reactions between the film and its underlying barrier or dielectric layer. Dielectric films such as SiO, with thermal diffusivities one hundredth that of

Metal Cap Formation

I

After Laser Pulsing

Figure 3-32. Laser planarization process.

175

molten A1 prevent heat transfer to the underlying substrate. The high surface tension, low viscosity, and excellent thermal diffusivity of A1 combined with the good thermal barrier of SiO, make it practical to planarize an A1 interconnection film without damaging underlying devices. The composite film stress changes from slightly compressive to slightly tensile after laser processing. Stress relief of the metal and out-diffusion of oxygen and other impurities occur during the laser process, similar to the zone-refining technique; this creates a high purity A1 alloy film which suppresses hillock growth. A general improvement in the distribution of contact resistance of the devices is observed on the laser planarized samples with no apparent shift in threshold or breakdown voltages. Pramanik et al. (1989) have shown a significant improvement in contact and via resistances of submicrometer contacts and vias with the laser planarization process with no observable junction degradation. The electromigration resistance of laser processed A1 wafers is significantly superior to the control devices (Boeck et al., 1990). Copper is also a good choice for the laser reflow process. Because Cu has lower reflectivity ( ~ 3 5 % )than A1 (x 9 0 %), a lower incident laser fluence is required to reflow Cu, even though Cu melts at much higher temperature (z1035"C) than A1 (~660OC).

3.7 Cluster Tool Technology Because of intense competition in manufacturing quality and cost, together with increasingly complex fabrication processes, future semiconductor manufacturing will require significant efforts toward defect reduction of any given process or tool. As shown in Fig. 3-33, for 4Mb DRAMS,

176

3 Silicon Device Processing

0

5

10 20 30 40 50 60 70 80 90 YIELD (%)

Figure 3-33. Relationship between defect density and yield for several DRAM generations.

1.6 defects/cm2 equals a 40% yield. That same defect density in the manufacturing of 16 Mb DRAMs will provide a yield of only 10 %, while the yield drops to zero for 64Mb DRAMs. By the year 2000, the number of discrete process steps in the manufacturing of advanced DRAM chips is expected to exceed 700, requiring an even more stringent control of both equipment and process induced defects. In addi-

tion, wafers with 300 mm in diameter should become available by the year 2000. The increase in wafer diameter significantly increases the process equipment cost, primarily due to the increased tool complexity to meet the uniformity requirements across the larger wafers. Today, about 60-70% of the cost for an 8 inch wafer fab is spent on equipment. As shown in Fig. 3-34, it will require $ 2 billion fabs to manufacture 1GB DRAMs with feature sizes of 0.18 pm on wafers of 300-400 nm and five to six levels of interconnection (Chatterjee and Larrabee, 1993). Meanwhile, the typical life cycle of leading-edge ICs has dropped from five years to two or three years. When wafer fabrication areas change to new IC designs, they often need to dispose of still viable process equipment, rapidly escalating the manufacturing cost. As a result, the following trends in Si semiconductor industry could be observed over the past few years: -

Device/circuit scaling; Larger wafers; More dry processes;

FACTORY CAPITAL COSTS 0.35 p m devlcw

Figure 3-34. Escalating costs of wafer fabrication factories (fabs).

3.7 Cluster Tool Technology

More single wafer processes; New cleaning philosophy : minimizing the generation of particles rather than focusing on the removal of the particles once they are on the wafer; Increased automation of real-time process and factory control; Differentiated products; Fast (cycle time), economical (cost) manufacturing of a variety of products (flexibility) with first pass success (quality).

3.7.1 Advantages These requirements provide a significant opportunity for a new class of equipment for future IC manufacturing where largesize single wafers are processed and sequential process steps can be “clustered” into multichambered in situ processing modules or into linked cells of independent modules (Doering, 1992). The single wafer cluster tool technology offers significant advantages in IC manufacturing. The inherent cleanliness of process chambers and wafer transfer environments provide substantial improvements in both film and interface quality due to reduction in particle contamination and reactive impurities (H,O, 0,, etc.). This, together with the reduction of the number of times that a wafer must be “handled” moving between operations, results in lower defect densities/higher yields. In addition, fast processing of new devices moves a company quickly up the learning curve, allowing early product introduction. This in turn can result in higher prices for the product on the wafers as well as increased market share. Reduction of cycle times also accelerates process development and yield/defect learning, an extremely important factor for cost-effective manufacturing. Furthermore, as the wafer size increases,

177

the value of each wafer becomes greater, particularly for ASIC circuits, and the risk of committing a large number of wafers to a batch process becomes significant. In an era of increased attention to process monitoring and real-time control for improved tool reliability, single wafer processing also offers improved diagnostic access, especially in comparison to batch processes. Finally, since new processes can be developed in a “production” module, their transfer from R & D to production may well be shortened. The main functional units of a cluster tool are shown in Fig. 3-35. Main units include the following: -

-

-

Central handling platform: contains the transport mechanisms to move wafers from module to module; Cassette stations; Single process modules: provide single wafer processing environments for cleaning, CVD, PVD, RIE, RTP, and other processes. Some of the process modules may involve proprietary design and some may be stand-alone standard process modules; Batch modules: increase throughput of some slow process steps with batch or minibatch modules.

Figure 3-35. Main functional units of a cluster tool.

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An important idea behind cluster tools is that a change in an IC fabrication process only requires a change in process modules. In this fashion, semiconductor manufacturers can accommodate a newly integrated process requiring a completely different set of process steps. They retain the cluster tool platform comprising the cluster controller and the transport and cassette modules with associated pumps, controls and power supplies. Only some of the peripheral process stations would then be needed to be upgraded, expanded, or replaced. The flexible, modular tools can be reconfigured to meet future process requirements developed on stand-alone R & D modules for rapid transfer to manufacturing, reducing retooling costs and extending the lifetime of installed equipment. Accordingly, capital expenditures are considerably reduced. One of the advantages of cluster tools is their capability to facilitate the performance of processes that would otherwise be very difficult or impossible. Most clustering activities are intended to reduce the costs of more sophisticated and advanced integrated processing tools by increasing performance and yield. In some cases, integrated clustering is intended to develop new materials, novel processes, and exotic structures.

3.7.2 Rapid Thermal Processing Rapid thermal processing (RTP) tools are strategically important for submicrometer manufacturing because of trends towards reduced thermal budget and tightened process control requirements on large diameter Si wafers. The desirable attributes of a RTP tool are rapid lamp heating, cold wall, the capability of rapidly changing the wafer temperature and processing environment for multiple in situ processing, and

single wafer processing. The capability of a rapid ramp rate allows short-time processing with enhanced temperature programmability and range. Since chemical reaction rates are thermally activated and thus usually increase significantly with temperature, much higher manufacturing throughput can be obtained in CVD processes using RTP. This overcomes the primary drawback to single wafer processing. The cold wall aspect is important for CVD applications where deposition takes place primarily on the wafer and not on the chamber wall. This minimizes contamination and particulate problems. The implementation of multiple in situ processing steps within the same equipment has the potential to reduce particulate contamination by improved control of the wafer environment, and increased throughput by reducing overall processing time. The single wafer processing feature is important for large wafer sizes to improve process control. In an era of increased attention to process monitoring and real-time control, single wafer processing also offers improved diagnostic access, especially in comparison to batch processing. Furthermore, each isolated single process module can be integrated or “clustered” to match processing needs in an “application specific” fashion. Various Si technology process modules are being developed in RTP for submicrometer device manufacturing. Formation of SALICIDE and TIN, junction formation, channel dopant profile control, thin gate dielectric formation, native oxide removal, glass reflow, and contact metallurgy sintering are some of these processes. By combining RTP with CVD (RT-CVD), the substrate temperature and the reactive gas flux are used as switches to turn a CVD reaction rapidly ON or OFF. The thermal exposure of the substrate is therefore minimized, allowing

3.7 Cluster Tool Technology

ultrathin film deposition. In addition, precise control of layer thickness, and its composition and structure can be obtained. Furthermore, RT-CVD is capable of in situ multilayer processing for high purity interfaces, an extremely important characteristic of fabricating ultrathin high quality stacked dielectrics. The extremely fine control of layer thickness and composition, and the capability of in situ cleaning and processing by RT-CVD, lead to the possibility of multicycle processing within a single chamber, and have led to exciting breakthroughs in ULSI technologies. Because of its unique characteristics, RT-CVD is becoming the most important process module for integrated processing. In the following, some of the important clusterable processes that employ RTP and RT-CVD are discussed.

3.7.2.1 In Situ Dry Cleaning The structural, chemical, and electrical properties of various interfaces between different layers (semiconductor/dielectric, semiconductor/semiconductor, and metal/ semiconductor) strongly influence the overall performance and reliability of the resulting devices. Approximately 40 YO of the processes used to fabricate today's ICs involve wafer cleaning steps. Wet cleaning processes for wafer surface cleaning are used exclusively to remove both particles and contaminants remaining on wafer surfaces after each process. As the devices become smaller and smaller, it will be more and more difficult for wet chemicals to clean abrupt contact holes and deep trenches. In addition, a much higher level of cleanliness is required for wafer surfaces of deep submicrometer devices. Furthermore, the large amount of chemical wastes generated by such processes are hazardous to the environment and their proper treat-

179

ment and disposal have become very expensive. Because of the equipment and process incompatibility, traditional wet cleaning processes have been prevented from being integrated into a cluster tool. For these reasons, significant advances must be made in cleaning technology. One promising possibility is to use vapor phase or gas phase dry cleaning technology, which requires only minute amounts of chemicals (Moslehi et al., 1992). Compared to liquid-based compositions, reactive gas species enjoy a greater access to the wafer surface because gas molecules don't have to diffuse through a thick water layer to reach the wafer. As a result, a gas phase system uses anhydrous H F from one 5 Ib (-2.3 kg) H F bottle to process 90 000 wafers, compared to 2000 lb (- 900 kg) of 10% H F for a wet bench system. The typical method used for in situ cleaning in RT-CVD is the H, pre-bake ( 2 1000"C, 2 1 min). Limits may be placed on the contribution of the in situ cleaning to the total process thermal exposure in order to reduce autodoping and broadening of any existing doping profiles. As long as the partial pressures of 0, and H,O are kept below the critical values for a given temperature, the fast oxide etching rates reported by Ghidini and Smith (1994) and Smith and Ghidini (1982) should allow the pre-bake time to be reduced to the order of seconds. Recently, conditions have been established (not due to hydrogen passivation by H F treatment) by which Si and Ge,Si, --x epitaxies were achieved with 500-800°C H, pre-baking for 15-30 s (Jung et al., 1991a). Recently, in situ anhydrous H F (AHF) cleaning with H, in the range of 325-750°C has been demonstrated (Apte et al., 1991). The AHF cleaning process is simple and manufacturable, and it is selective in a way that it removes surface native oxides, but leaves thermal

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oxides intact. The other potential low temperature gas phase RTP cleaning to remove native oxide layers and other surface contaminants is germane-assisted cleaning (Moslehi eta]., 1992). The cleaning process composition consists of a mixture of GeH, and H, . The germane-to-hydrogen flow ratio is kept very low to prevent deposition or surface nucleation of germanium during the thermal cleaning process. The GeH,/ H, processes clean the Si substrate surface by direct reaction of GeH, with the native oxide layer, producing volatile germanium oxide species (GeO). Although this process works well on native oxides and CVD oxides, it does not easily remove thermally grown oxides. These RTP-based gas phase dry etching techniques can be easily integrated into various RTP-based thin-film growth and deposition process modules in a cluster tool environment. 3.7.2.2 Interface Engineering Interface engineering is critical to high speed bipolar and Bi-CMOS processes. It consists of the steps of surface cleaning, controlled interfacial oxide or nitride growth, and polysilicon deposition (RTP cleaning, oxide/nitride growth by RTP, in situ doped poly-Si deposition by RTCVD). 3.7.2.3 Gate Stack of Oxide and Oxynitride The gate stack process is a good example of a process which may potentially benefit from RTP cluster tool processing. It consists of RTP cleaning, gate dielectrics growth by RTP, and in situ poly-Si deposition by RT-CVD. Critical interfaces are kept free of contamination in a cluster tool to achieve excellent device performance and reliability. An excellent example is the fabrication of a simple MOS capacitor. The MOS capacitor can be fabricated com-

pletely within the same RT-CVD chamber, utilizing the processes of rapid thermal oxidation (RTO) and in situ doped poly-Si deposition. Additional processing can easily transform the MOS capacitor into a MOSFET. High quality MOS capacitors and MOSFETs have been demonstrated (Sturm et al., 1986). For a 290 8, gate oxide and capacitor area of 4.5 x cm’, values of 5 x lo9 cm-2 eV-’ for the midgap interface state density, ~ 1 0 1 0cm-’ for the fixed charges, and 10 MV/cm for the breakdown field were achieved. Oxynitride gate dielectrics grown by RTP of Si in presence of N,O are superior to conventional SiO, grown ones in 0, (N,O oxides have significantly less charge trapping and interface state generation under constant current stress, a tenfold increase in both charge-to breakdown and time-to-breakdown values, and much better dopant diffusion barrier properties) (Hwang et al., 1990). The lifetime of MOSFETs with N,O gate oxides is almost one order of magnitude longer than that of the control devices under identical channel hot-carrier stress conditions (Hwang et al., 1991). Stacked nitride/oxide (NO) films have received considerable attention due to their low defect density, low leakage current, diffusion barrier property, and excellent long-term reliability (Watanabe et al., 1984; Young et al., 1988; Weinberg et al., 1990). Charge trapping in the nitride or at the nitride/oxide interface has limited the application of these films to memory elements. It has been demonstrated that the charge trapping in NO layers can be considerably reduced by in situ multi-layer processing for high purity interfaces in a RT-CVD reactor. In the experiments, the bottom oxide of the NO structure is prepared by RTO in 0, at 1050°C followed by in situ nitride RT-CVD deposition us-

3.7 Cluster Tool Technology

ing SiH, and NH, diluted in N, at 850 "C. The nominal bottom oxide thickness was 40 A and the nitride thickness was 30 A. The leakage current of the control oxide fabricated by RTO at 1050°C and NO devices are comparable at low fields. Capacitors with NO dielectrics exhibited V,, very close to that of the control oxide. Both control and NO devices exhibited Di, values of z 2 x 10'' cmP2eV-', indicating excellent interfacial integrity. NO devices showed dramatic improvements in breakdown field distribution over the control oxides, although the control oxide and the bottom oxide of the NO layers were grown in the same RT-CVD reactor with the same recipe and in consecutive order. The high quality top nitride covered up or sealed the defects of the bottom oxide, thus significantly reducing the frequency of low-field breakdown events (Roy et al., 1988). Another possibility is that the in situ nitride deposition effectively protects the oxide from contamination before poly-Si deposition. 3.7.2.4 Deposition of DRAM Storage Dielectrics The application of RT-CVD technology to the formation of ultra-high density DRAM storage dielectrics is becoming increasingly important. The process could consist of RTP cleaning/surface passivation, storage dielectric deposition by RTCVD, in situ post-deposition RTP annealing, deposition of in situ doped polysilicon top electrode by RT-CVD. For oxide/nitride/oxide (ONO) DRAM storage dielectrics, the bottom SiO, over the bottom polysilicon electrode plays an important role in the film integrity. The reason is that the thin bottom SiO,, usually a low-grade native SiO, , degrades the quality of O N 0 films. In addition, the bot-

181

tom SiO, prevents further scaling of the effective dielectric thickness and thus limits the maximum attainable capacitance. Therefore, it is extremely critical for advanced DRAM manufacturing to eliminate the native oxides completely prior to dielectric deposition. It has been demonstrated that by using rapid thermal nitridation (RTN) in pure NH of poly-Si surface prior to Si,N, deposition, (bottom native SiO, free) Si,N, dielectric (t,,, z 35 A) with enhanced reliability can be achieved (Lo et al., 1992). The defect-related dielectric breakdown caused by low-grade native SiO, is completely eliminated by the use of RTN. In addition, capacitors with RTN treatment have an improved lifetime (by factor z lo3)than the ones without RTN. The ultrathin stacked NO layer can also be fabricated by in situ multiprocessing (RTMP) (Ando et al., 1993). As shown in Fig. 3-36a, the multiprocessing steps include in situ surface cleaning, RTN, rapid thermal CVD of the Si,N, films, and rapid thermal CVD of poly-Si. All these steps are carried out in sequence without lifting the vacuum. Elimination of interfacial oxides at the Si,N,/Si interface leads to high quality nitride films with low leakage current density and extremely high reliability. As shown in Fig. 3-36 b, the TDDB characteristics of Si,N, films prepared by in situ RTMP are improved about lo4 times over conventional LPCVD Si,N, films. This result clearly demonstrated the capability of in situ multiprocessing for the fabrication of high quality ultrathin films for ULSI applications.

,

3.7.2.5 Selective Deposition Processes Process complexity and number of mask levels steadily increases with each generation of IC technology. Projections of present trends indicate as many as 700 process

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0

2

4

6

lime (rnln)

8

1

i

0

Stress t h e (sec)

Figure 3-36. (a) Schematic time- temperature profile of in situ RTMP processing for fabricating DRAM storage capacitors. (b) Comparison of TDDB characteristics of dielectrics fabricated by various techniques.

steps in IC technologies by the year 2000. The increased use of selective processes is one way to greatly reduce the number of process steps, since each selective process can eliminate many other process steps (usually mask levels, lithography and etching steps). Selective metal deposition (tungsten, copper, TIN) and selective silicide (TiSi,) processes are two of the better known and more mature of the various selective processes. Other possibilities include selective epitaxy processes for advanced CMOS isolation and for raised source/drain CMOS devices. Selective processes are emphasized here because they provide considerable leverage for cluster

tools. They eliminate the need for masking steps and facilitate more sequential processing steps within a single cluster tool before the wafer must be removed for lithography steps. Selective epitaxy growth has been applied to a novel transistor structure, the low-impurity-channel transistor (LICT), for advanced CMOS applications. By selectively growing a thin undoped Si epilayer on top of the heavily-doped wells, threshold voltages can be lowered and band bending made more gradual, thereby weakening the effective field for carriers and reducing surface-roughness scattering. In addition, carrier freeze-out is eliminated since no channel implantation is performed. The heavily-doped wells are for sharpening turn-offs and preventing punch-through. Fairly good transistor operation has been achieved for 0.1 pm CMOS devices implementing the LICT structure (Aoki et al., 1990). Critical to LICTs are steep impurity profiles which makes RT-CVD ideal for LICT fabrication since RT-CVD can provide minimal autodoping and out-diffusion of impurities (Gibbons et al., 1985; Lee at al., 1989; Jung et al., 1991 b).

3.7.2.6 Ultra-Shallow Junction Formation Recently, a novel approach based on surface chemical adsorption of dissolvements from induced dopant gas molecules has been developed by Nishizawa et al. (1990b) and Inada et al. (1992) for very shallow, high quality p+-n junction formation. In this process boron atoms are incorporated into Si by diffusion in an oxygen-free atmosphere at a relatively low temperature. This process differs from the conventional diffusion process in which boron diffusion is performed in an oxygenrich environment. Kiyota et al. (1994) have developed a rapid thermal vapor-phase

3.7 Cluster Tool Technology

doping technique to fabricate ultra-shallow boron-doped junctions with junction depth less than 30 nm and surface boron concentration of 5.8 x 1019crnp3.

3.7.2.7 Integrated CMOS Processing Based on RTP A 0.25 pm CMOS technology has been developed and demonstrated with all-RTP thermal processing (Moslehi et al., 1993a). These RTPs cover a processing temperature range of 450" to 1100°C. The process features are listed in Table 3-12. Excellent CMOS transistors with considerable process simplification have been established. Improved RTP control over furnace was also demonstrated. These results show the effective use of RTP for IC manufacturing.

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3.7.2.8 Ge,Si, -x/Si Heteroepitaxy by RT-CVD RT-CVD was the first non-UHV technique used to demonstrate high performance Ge,Si -,/Si heterojunction bipolar transistors (HBTs). Early work showed higher current gains of 400 compared to Si devices and high unity gain cut off frequencies of 28 GHz (Kamins et al., 1989). Improved HBT performance has been obtained by controlling base dopant out-diffusion and using graded base layers (Sturm and Prinz, 1991). More recently, a double base HBT has been demonstrated which could find application as a single-transistor NAND gate (Prinz et al., 1992). Si, _,Ge,/Si heterostructure FETs have a potential for higher performance due to higher carrier mobilities in strained Si and

Table 3-12. List of the lamp-heated RTP-based CMOS fabrication processes (Moslehi et al., 1993a) RTP-based processes

Applications

RTP parameter domain

Germane clean

split gate formation

Dry RTO

gate oxide, PBL oxide

Wet RTO Source/drain RTA and gate RTA

thick oxides ("0NED"-tank and sacrificial oxide) S/D activation, gate annealing

RTP tank formation

CMOS n & p well formation

LPCVD polysilicon

CMOS gate formation

LPCVD amorphous Si

CMOS gate formation

LPCVD tungsten

multilevel metal

TiN/TiSi, RTA reaction and annealing RTP sinter (FGA)

Salicide, silicided contacts forming gas annealing

LPCVD nitride

PBL nitride deposition

LPCVD oxide

oxide spacers, undoped oxide

65O-75O0C, low pressure (750°C/15 torr) GeH,/H, 1OOO-105OoC, high pressure (1OOO0C/65Otorr) 0, 950- 1000"C, high pressure (100OoC/650torr) H,O/O, 950- 1050 'C, high pressure (95OoC/650Torr) Ar or NH, 1050-1 100°C. high pressure (1100"C/650 torr) NH, 650-750"C, low pressure (650 'Cjl5 torr) SiH,/Ar 500- 590°C, low pressure (560°C/15 torr) SiH,/Ar 475-5OO0C, low pressure (475 "C/20 torr) SiH,/H,/WF,/Ar 65O-75O0C, low pressure (650"/750T / l torr) N,, Ar 450-475"C, high pressurc (475 "C/650 torr) HJN, 8O0-85OnC, low pressure (3 torr) SiH,/NH, 70O-75O0C, low pressure (74OoC/1tom) TEOS/O,

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Si, -xGex channels. Higher hole mobilities at room temperature have been achieved in GeSi/Si heterostructure FETs grown by RT-CVD with a buried SiGe channel compared to a silicon surface channel (Garone et al., 1992). Similarly, improvements in electron mobility have been reported in both surface and buried tensile strained Si channels on top of a relaxed Si,,71Geo.29 layer (Welser et al., 1992). Peak effective mobilities were 2.2 times larger than those in devices fabricated in bulk silicon at room temperature. Si, _,Ge, alloys could provide low cost alternatives to compound semiconductors in the fabrication of long wavelength receivers and other optoelectronic integrated circuits due to the well-established Si VLSI technology. By adjusting the Ge content in the SiGe layers the operating wavelength can be tuned in the technologically important 1.3 to 1.55 pm range. RT-CVD has much to offer in growing epitaxial GeSi layers required for such devices. Low loss waveguides and directional couplers have been fabricated (Mayer et al., 1991). SiGe/ Si superlattice waveguide pin photodetectors with high internal quantum efficiency and low dark currents that can operate at 1.5 Gbit/s at 1.3 pm have been demonstrated (Jalali et al., 1992). Evidence of the fine control with which superlattice layers can be grown by RT-CVD is seen in the growth of a 50 period superlattice containing a 24 8, SiGe layer and a 23 8, Si layer (Sturm et al., 1991). The ability to rapidly switch the gases and growth temperature enables the optimization of growth temperature of individual layers, resulting in the realization of multiple quantum well (MQW) structures with minimum interdiffusion and high throughput. The SiGe layers are grown at low temperatures (550"-650 "C) to avoid islanding growth and Si barrier layers are grown at some-

what higher temperatures (700" - 800 "C) in order to get adequate growth rates. The wide range of growth rates that RT-CVD can provide could be applied to the growth of thick waveguide layers and thin MQW layers to obtain integrated waveguidephotodetector structures. Further improvements in device performance can be expected utilizing the capability of RTCVD to grow selective epitaxial SiGe layers (Kamins et al., 1992) and SiGe on silicon-on-insulator (SOI) (Hsieh et al., 1991) structures. Commercial versions of RTP modules for CVD are not available with the uniformity and control required for the manufacturing environment. This is primarily due to the difficulties of measurement and control of wafer temperature and its uniformity across a large size wafer. The non-contact measurement and control of absolute temperature and of temperature uniformity across a wafer have proven to be major problems with single wafer RTP processing. Research is presently underway at many laboratories addressing these issues, and progress is being made (Moslehi et al., 1992; Peyton and Kwong, 1990). For example, the use of multi-zone heating techniques appear very promising for achieving process uniformity across a wafer. Several approaches are being explored for surface emissivity corrections to be used with non-contact temperature measurements in order to control the temperature magnitude as seen by a pyrometer looking at a wafer. All of these approaches appear promising but at present the single most important limitation is the lack of an RTP module design with acceptable process uniformity and control.

3.7 Cluster Tool Technology

3.7.3 Single-Wafer Integrated Processing One factor is now driving clustered integrated processing toward a broader spectrum of applications in which sequential processes with very different character (temperature, chemistry, pressure) are linked in clusters; that is the significant benefits from exploiting the advantages of integrated processing by the possibility it offers to mix and match whichever process combinations will result in the highest quality materials and structures. To tailormake films with matching physical, structural, dielectric, mechanical, chemical, crystallographic, and electrical properties, the existing and future processes must be combined together. Some of the important clusterable processes are : Cleaning, CVD, PVD, and etching processes must be integrated to cope with topographical problems in the upper levels of metallization, including multilayered metallization. Self-aligned silicide process (cleaning, PVD, RTP, etching). Multilevel film etching or multistep etching. This is necessary for complex structures. Since it may require different chemistries and etching technologies for individual steps, cross contamination and particulates become important issues (cleaning, etching). Interface engineering. This is critical to bipolar and Bi-CMOS processes. It consists of the steps of surface cleaning, controlled interfacial oxide or nitride growth, and polysilicon growth (cleaning, RTP, CVD). Selective deposition/growth processes rely on well-defined, properly prepared surfaces which are highly amenable to integrated processing (cleaning, passivation, CVD). The increased use of selective processes is one way to greatly re-

-

-

-

-

-

185

duce the number of process steps, since each selective process can eliminate many other process steps (usually mask levels, lithography and etching steps). Selective processes are emphasized here because they provide considerable leverage for cluster tools. Gate stack of oxide (or oxynitride) and in situ doped polysilicon (cleaning, RTP, CVD). The gate stack process is a good example of a process which may potentially benefit from cluster tool processing (Apte et al., 1992). It consists of pre-gate cleaning, gate dielectric growth, and polysilicon electrode deposition and annealing. Critical interfaces are kept contamination-free in a cluster tool to achieve excellent device performance and reliability. DRAM storage dielectrics deposition (cleaning, CVD, RTP). Ultra shallow junction formation based on surface chemical adsorption of dissolvements from induced dopant gas molecules (cleaning, RTP) (Nishizawa et al., 1990b; Inada et al., 1992; Kiyota et al., 1994). BPSG flow (cleaning, CVD, high pressure RTP). To reduce the thermal budget for reflow, a single-wafer high-pressure RTP system has been used to reflow BPSG in steam or nitrogen at temperatures as low as 720°C. Oxide spacer/collar formation (etching, CVD, etching) (Matuszak et al., 1989).

Throughput has been an issue for cluster tools. For a single wafer process, 60 wafers per hour has been considered a reasonable figure. A substantial number of single wafer processes used or being considered in cluster tools achieve this value, including cleaning, stripping, RTP, and many etching processes. However, other etch processes and many CVD processes take

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longer than 1 min. When these slower processes are integrated into the fabrication of cluster tools, typical throughputs are 10 to 25 wafers per hour. A cluster tool’s throughput is dictated by the slowest or “bottleneck” process and to a lesser extent by machine throughput (Lea,the speed of wafer handling including pumping and venting). Significant efforts are being made to reduce the process times for the potential bottleneck processes. For some of the longer-time processes, batch process modules may be required. However, one of the unique characteristics of single-wafer processing is the ability to manufacture small lots with a fast turnaround. This is extremely attractive for process development and for applications where short cycle times are significantly more valuable than the wafer cost. Simulation results have shown that for single wafer lots running through the cluster fabs, the theoretical cycle times can be as short as 5 days. This should be extremely valuable for small-volume ASIC runs. A performance comparison of conventional fabs and cluster-based fabs is made in (Wood et al., 1991), in which the cost per wafer is plotted against average cycle-time. As can be seen clearly, at high throughput, the wafer costs are comparable. However, for the low throughput time range, the wafer costs are much higher for conventional fabs. The total use of single-wafer processing for fast-cycle-time IC production has been demonstrated recently (Moslehi et al., 1993b). Complete 0.35 pm CMOS process integration and 3-day CMOS IC manufacturing cycle time have been established with all-RTP thermal processing. The future of cluster tools and the extent to which cluster tools will permeate and dominate IC manufacturing depends on the successful development of a broader

spectrum of single wafer processing technologies. In addition, to obtain fundamental mechanistic insight and to develop new levels of process control and material/ structure quality, the wafer surface and the process environment during the process must be studied in detail, using a variety of sophisticated techniques from surface science as well as mass and optical spectroscopy. If proposed benefits of improved process control, process configurability on a wafer-to-wafer basis and easy mixing of process technologies are to be realized, improved process sensors must be available and used in cluster tools. There is a great lack of adequate process sensors for key process variables including gas species and gas flows at the wafer, and thicknesses of films depositing or being etched on the wafer. Most sensors, if available, provide either indirect data or measure parameters at some point far off the wafer surface. It may be possible to use such remotely measured parameters with appropriate process and equipment models to infer values at the wafer. However, much research, development and process characterization work remains to be done.

3.8 References Note: IEDM stands for International Electron Device Meeting.

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General Reading Tungsten and Other Refractory Metals for V L S IApplications, Vols. I, 11,111, IV, V, VI: Pittsburgh, PA: Materials Research Society.

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Index

abrasion scratch, annealing 39 abundance, silicon 67 agglomeration, noble metals 164 alkali ions, preoxidation cleaning 136 alkaline colloidal silica slurry 43 aluminothermic reduction 10 aluminum diffusion barrier 160 physical properties 164 aluminum contamination, preoxidation cleaning 138 aluminum impurities 9 f amorphization, shallow junction formation 147 annealing - abrasion scratch 39 - growth 120 hydrogen 122 f shallow junction formation 146 antimony pre-amorphization, shallow junction formation 147 application specific integrated circuit (ASIC) 154 argon atmosphere 25 arsenic impurities 7 ASTM Standard F 123 2 1 ASTM Standard F124 45 atmospheric pression puller, Czochralski silicon 3 1 atmospheric pressure, metallization 170 avalanche breakdown, microvacuum field emitter 94 avalanche photodiode, quantum effect devices 104 ~

~

~

~

base-collector junction, bipolar transistor 77 batch modules, cluster tool technology 177 Benard cell, Czochralski silicon 32, 35 BF2 implantation, shallow junction formation 148 bias, silicon device structures 70, 72 bipolar application, ULSI 133 bipolar CMOS 86 bipolar inversion-channel field effect transistor 79 bipolar transistor 67, 72 f bird’s break transition, silicon device isolation 125 bit line, interconnections, metallization 163 bonding, wafer 133 boron diffusion - field-effect devices 83 - shallow junction formation 147 - solar cells 108 boron implantation device isolation 124 thyristors 79 boron impurities 9 f boron incorporation, shallow junction formation 153 boron segregation, single crystal silicon 19 boron SIMS profiles 152 borosilicate glass 148 Bragg reflection 37 breakdown properties, gate dielectrics 137 breakdown strength, silicon device structures 67 breakdown voltage contacts, metallization 159 silicon device structures 7 1 brittle fracture, silicon slice fabrication 39 bubbles, bonding interfaces 135 buried channel PMOS 85 buried oxide (BOX), isolation techniques 127 ~

~

~

~

baking, metallization 17 1 bamboo structure 163 band alignments, HBT 75 band diagram - MODFET 92 quantumeffect devices 101 silicide/transition layer/silicon 8 1 bandgap germanium 74 silicon 67 barrier height, quantum effect devices 101 barrier injection transit time (BARITT) diode 68, 104 f barrier layers, metallization 158 barriers - impurity diffusion 135 - silicon device structures 69 ~

~

~

~

calcium contamination, preoxidation cleaning 138 capacitor contact, metallization 163 capacitor model, silicon device structures 69 carbon float-zoned silicon 20 f - silicon fabrication 23, 30 f, 37 carbothermic reduction 7 f cassette station, cluster tool technology 177 catalytic disproportionation steps, silane route 15 channel width, silicon device isolation 125 channels, MOSFET 85 ~

196

Index

charge coupled devices (CCD) 82 f, 105 charge distribution, BICFET 79 charge sizes, Czochralski silicon 25 charge transfer efficiency, field-effect devices 84 charge weight, Czochralski silicon 35 chemical mechanical polishing - metallization 173 - silicon-on-insulator 89 chemical vapor deposition (CVD) - cluster tool technology 177 - gate dielectrics 144 - silicon processing 11 chemically modified gate oxides, dielectrics 141 f chip integration levels 118 chlorosilanes 10 f chromium impurities - gettering 118 f - silicon processing 9 cleaning - cluster tool technology 185 - silicon slice fabrication 43 f cleavage - Czochralski silicon 27 - Si-0-Si, metallization 174 cluster tool technology 175 ff CMOS fabrication, RTP-based 183 cobalt, impurities 119 collar formation, cluster tool technology 185 collector currents, quantum effect devices I01 collimated sputtering, metallization 163 complementary metal-oxide-silicon, (CMOS) 55 constitutional supercooling, Czochtalski silicon 28 f contact plug technology 165 contact resistance 158 contact holes 154, 164 contacts - metal-silicon 80f - metallization 158 f contaminations, preoxidation cleaning 137 convection, thermal 3 1 copper - damagecenters 36f - impurities, gettering 118 f - interconnections 168 - physical properties I64 CoSi,, physical properties 161 cracking, silicon slice fabrication 38 critical radius - oxygen in Czochralski silicon 46 - oxygen precipitation 56 critical thickness, heterojunction 74 f cross-sections, thermal neutron capture, silicon 20 crusting over 8 crystal diameter, Czochralski silicon 35 crystal engineering 6,5 1 ff crystal growth, periodic 22 f crystal habit, Czochralski silicon 26 crystalline defects, gettering 118 current controlled potential effect devices 67 current-voltage characteristics, p-n-p-n diode 77

cutoff frequency, silicon device structures 74 cutoffwavelength, photodetectors 106 CVD see: chemical vapor deposition 11 Czochralski crystal growth 5 Czochralski grown wafers 1 19,123 Czochralski pulling, single crystal silicon 17 f, 24 Czochralski silicon 25 ff Czochralski silicon wafers, ULSI 6 damage, silicon slice fabrication 36 f de Broglie waves - quantum effect devices 98 - silicon device structures 67 deep etching, silicon slice fabrication 42,52 deep level defects, gettering 1 I8 deep level transient spectroscopy 16 defect free area, gettering 120 defect free Cz wafers, gettering 123 defect free surface, silicon slice fabrication 44 defects - crystal engineering 5 1 - fluorine segregation 148 - silicon device processing 118 37 f - silicon slice fabrication degradation, gettering 121 deionized water cleaning, silicon slice fabrication 44 density of states, quantum effect devices 95 denudation, gettering 120 depletion layer width 71 device dimensions, silicon device processing 1I8 device isolation 124 ff device structures 63-1 12 diamond blade, silicon slice fabrication 40 diamond grinding 36 f diamond lattice 119 dichlorosilane, metallization 157 dielectric breakdown, gettering 122 diffusion doped deposited layers 149 oxygen in Czochralski silicon 47,49 f silicon device structures 70 solar cells 108 diffusion barrier properties, metallization 160 difision coefficients, 3d metals in intrinsic silicon 119 diasivity, thermal, single crystal silicon 23 diodes 102 ff - quantum effect devices - resonant-tunneling 97 silicon device structures 68 dislocations - Czochralski silicon 26 f - gettering 118 dissolution, oxygen in Czochralski silicon 3 1, 44 distribution coefficients, oxygen in Czochralski silicon 45 donor impurities, float-zoned silicon 2 1 donors, thermal 45,49 dopant diffusion, shallow junction formation 146 -

-

-

Index doped silicon, oxygen in Czochralski silicon 5 1 doping, shallowjunction formation 148 f dots, quantum effect devices 95 double barrier quantum well 97 double drift devices I02 double polysilicon self-aligned bipolar process 74 drain engineering, MOSFET 85 drain induced barrier lowering (DIBL) 145 . DRAM storage dielectrics deposition, cluster tool technology I8 I dry cleaning gate dielectrics 139 in situ, cluster tool technology 179 dry etching, metallization 17 1 Dupont process 13 dynamic random access memory 7 ~

~

fast difising transition metals, gettering 1 18 fast pulling, pure silicon melt 19 Fermilevel 68 Fick's diffusion laws 48 field effect devices 80 ff field effect silicon device structures 67 field modes, magnetic 34 float zoned silicon 17 f floating gate avalanche injection MOS 90 fluid motion, Czochralski silicon 35 fluidized bed reactor, chlorosilane plant I 1 fluorination, gate dielectrics 143 fluorine impurities, gate dielectrics 141 fluorine segregation, shallow junction formation forward bias 70 Fowler-Nordheim tunneling 91 fractional distillation, TCS 11 fracture, brittle 39 full isolation by porous oxidized silicon (FIPOS) 89, 131 functional units, cluster tool technology I77 furnaces 8 fusion, premate 8

197

148

efficiency, quantum effect devices 105 elastic deformation, silicon slice fabrication 39 clectrically erasable programmable read-only memory (EEPROM) 90 clectromigration, metallization I62 electron cyclotron resonance (ECR) 154 electron trapping, gate dielectrics 136 emitter characteristics, BICFET 79 emitter-base delay time, heterojunction bipolar transistor 75 energy band diagram, photodetectors 106 energy consumption, reduction 10 enhanced diffusion oxygen in Czochralski silicon 49 f phosphorus, solar cell I08 enhanced gettering, crystal engineering 53 epitaxial deposition I2 epitaxial layer, single crystal silicon 24 epitaxial wafers, gettering 122 f epitaxy, periodic crystal growth 25 erasable programmable read-only memory (EPROM) 90 etch back procedure, metallization 170 etch back silicon on insulator, BESOI 134 etch stop capability, metallization 159 etch stop layers, BESOI 134 etching metallization 165 silicon slice fabrication 42 single crystal growth 23 ethylene diamine-pyrocatechol-water etchant, FETs 83 evaporation, oxygen in Czochralski silicon 44 extrinsic gettering I19 - silicon crystal engineering 5I f - silicon slice fabrication 36 ff

GaAsMBE 69 GaAs MESFETs 88 gas immersion laser doping, GILD 153 gas phase diffusion, shallow junction formation 149, 153 gas phase doping, floated zone silicon 18 f gas-immersion laser doping 148 gate dielectrics 135 ff gate electrodes, metallization 155 gate induced drain leakage, GIDL 146 gate oxide integrity (GOI) 121 f gate oxides - breakdown properties 137 - quality 139 f gate stack, cluster tool technology 180, 185 germanium, heterojunction 74 germanium metallurgy 5 gettering - silicon crystal engineering 51 f - silicon device processing 118 ff - silicon slice fabrication 36 f gold, physical properties, metallization 164 goniometer, silicon slice fabrication 37 gravels, unconsolidated 7 grinding, silicon slice fabrication 36 f, 40 group 111-V compound semiconductors, wafers 67 growth, gettering I20 growth processes, cluster tool technology 185 Gummel number 74

fabrication sequences, field-effect devices 83 Fabry-Perot etalon, quantum effect devices 97 failure, rectifier diode 21 failure modes, gettering 122 f

haloing effect, metallization 167 Ham theory - oxygen in Czochralski silicon 48 f - silicon processing 55

~

~

~

~

~

198

index

hardness, silicon device structures 67 haze supressant, silicon slice fabrication 44 heat transfer mechanisms, Czochralski silicon 32,35 heavily doped silicon 5 1 heavy metals, gettering I 19 heteroepitaxy RT-CVD 183 - silicon 87 heterogeneous nucleation, oxygen in Czochralski silicon 46 heterojunction, silicon device structures 74 f heterojunction bipolar transistors 75 f, 124 f, 183 - silicon device structure 67 HF-dip and rinse-dry, gate dielectrics 138 HI-LO treatment, crystal engineering 54 high performance fractional destillation, TCS 12 high pressure oxidation (HIPOX), quantum effect devices 97 hole diffusion current, bipolar transistor 73 hole trapping, gate dielectrics 136 holes, metallization 154 homogeneous field-effect transistors 82 homogeneous nucleation, oxygen in Czochralski silicon 46 hot electron transistor - resonant-tunneling 99 - silicon device structures 79 hydrogen annealing, gettering 122 f hydrogen bonding, metallization 174 ~

imaging cell, field-effect devices 83 impact-ionization avalanche transit time (IMPATT) 102 IMPATT diode 68 impurities - gate dielectrics I4 1 - gettering 118 - oxygen in Czochralski silicon 45 f - semiconductor grade polycrystal silicodTCS I2 - silicon device isolation 124 - silicon processing 7f impurity diffusion, gate dielectrics 135 impurity segregation, supercooling, Czochralski silicon 29 in situ dry cleaning 179 incorporation, oxygen in Czochralski silicon 30 f, 44 induced base transistor 79 induction heating, Czochralski silicon 25 InGaAsiInP detector, quantum effect devices 107 inner surface, Czochralski silicon 30 InP, doping processes 202 f insulated-gate bipolar thyristors 78 integrated circuits, very large scale 5 integrated CMOS processing, RTP 183 integration levels, chipsg 118 interconnection techniques, silver 164 interconnections, metallization 162 f interface engineering 180,185 interface gap, silicon device structures 67

interstitial impurities, oxygen in Czochralski silicon 45 interstitial lattice sites, gettering 119 intervalley electron transfer 102 intrinsic gettering 119 f silicon crystal engineering 53 f - silicon slice fabrication 36 f ion channeling, thin film transistors 90 ion implantation - gettering 119 - shallow junction formation 146 f ion migration, metallization 170 iron, impurities - gettering 118 f - silicon processing 9 f iron contamination, preoxidation cleaning 138 iron hydroxide, preoxidation cleaning 138 irradiation, neutron 19 ISLANDS method, isolation techniques 131 isolation methods, advanced 126 f isopropyl alcohol, preoxidation cleaning 138 isotopes, silicon 19 isotropic plasma etching 127 ~

junction field effect transistor (JFET) 82 junction formation, ultra-shallow 182 junction leakage, gettering 118 junction shorts, gettering 1I8 kinematic viscosity, single crystal silicon 23 h o o p hardness 67 Komatsu silane plant 14 lamp-heated RTP-based CMOS fabrication 183 lapping, silicon slice fabrication 36 f, 42 laser planarization, metallization 175 lattice mismatch 87 lattice sites, gettering 119 lattice structure, silicon 39 leakage currents - bipolar transistor 73 - gettering 118 shallow junction formation 146 lifetime killing recombination, gettering 118 lightly doped drain (LDD), MOSFET 85 local oxidation of silicon (LOCOS) 119 ff, 124 f low defect density, gate dielectrics 135 low impurity channel transistors 86 - cluster tool technology 182 low pressure chemical vapor deposition (LPCVD) 53 low thermal budget processing, gate dielectrics 135 lubricants, silicon slice fabrication 40 ~

magnetic Czochralski silicon 33 f magnetic Czochralski wafers 121 manufacturing, single crystal silicon

17 f

Index mask definition, isolation techniques 129 materials, interconnection, metallization 162 MBE, IMPATT diodes 104 mechanical backside damage treatment 54 mechanical damage - gettering 119 silicon 36f mechanical stress, salicides 161 melt convection, Benard cell 32 melting points, noble metals 164 memory applications 118 MESFET 67 metal deposition, selective I82 metal-insulator-oxide-semiconductor (MIOS) 9 1 metal line, metallization 163 metal-organic CVD, IMPATT diodes 104 metal-oxide semiconductor structures 82 f metal-oxide-silicon (MOS) 5 1 f metal-semiconductor field effect transistor (MESFET) 82 metal-silicon contact, field-effect devices 80 f metallic contamination oxygen diffusion in silicon 5 1 preoxidation cleaning 137 metallic surface contamination 7 metallization 154 ff metallization structures I69 metallurgical-grade silicon 7 ff microcracks, silicon slice fabrication 38 microvacuum field emitter 93 microwave diodes quantum effect devices 102 ff silicon device structures 68 migration, metallization 162, 170 minority carrier concentrations bipolar transistors 73 silicon device structures 70 f MODFET 67 modulation-doped FET (MODFET) 92 monocrystalline silicon 17 f Monsato Syton patent 43 MOS (metal-oxide-silicon) 5 1 f MOS S/D junction technology 145 MOSFET 8 4 f - silicon device structures 67 Mott-Gurney law 69 multichambered in situ processing modules 118 multilevel interconnection plananzation I69 f multiple quantum well detector, SO1 99 -

-

-

-

199

nickel sputtering, metallization 165 nitridation, gate dielectrics 143 nitride etching 126 nitride-clad LOCOS (NCL) 127 nitrogen - float-zoned silicon 20 f - residual, gate dielectrics 136 nitrogen impurities, gate dielectrics 141 noble metal silicides, metallization 161 nonvolatile memory, MOSFET 90 nucleation - gettering 120 - oxygen in Czochralski silicon 45 f - silicon crystal engineering 54 ohmic contacts field-effect devices 8 I - nonalloyed, solar cells 108 orange peel, silicon slice fabrication 43 organics, preoxidation cleaning 136 oscillator, single crystal growth, silicon 23 outdiffusion temperature, gettering 120 outer surface, Czochralski silicon 30 oxidation effects, boron penetration I56 oxidation induced stacking faults (OISF) 120 oxidation process, gate dielectrics 143 oxide films I70 oxide gate stack, cluster tool technology 180 oxide spacericollar formation 185 oxidized wafers, bonding 134 oxygen, in Czochralski silicon 30 f, 44 ff, 49 oxygen precipitation 54 oxygen-vacancy centers 50 oxynitride gate stack, cluster tool technology 180 ozone concentration, metallization 170 -

-

n-i-n diode 68 f n-p-n bipolar transistor 72 n-well formation, isolation techniques 130 native oxide, silicon slice fabrication 43 native oxide films, oxygen in Czochralski silicon 47 needle eye technique, single crystal silicon 18 negative differential resistance (NDR) 99 neutron transmutation doped silicon (NTD) 5 , 19 f nickel impurities, gettering 1 18 f

p n junction 70 p n junction formation, advanced techniques 148 f p-well formation, isolation techniques 130 particulates, preoxidation cleaning 136 passivated emitter polysilicon solar cell 108 passivatiodreflow effects, boron penetration 156 pelletization, upgraded quartz sands 9 periodic crystal growth, single crystal silicon 22 f permeable-base transistor (PBT) 82 phosphorus, segregation coefficients 19 phosphorus diffusion - gettering 1 19 - solar cells 108 phosphorus impurities 7, 11 photodetectors 104 f photolurniniscent spectroscopy 16 photonic diodes 102 ff - quantum effect devices - silicon device structures 68 photoresist ashing, gate dielectrics 136 pin photodiode 104 planar doped barrier 69 f

200

Index

planarization metallization 173 multilevel interconnections 169 f Planck’s constant 67 plasma enhanced CVD, quantum effect devices 97 plasma etching, isotropic 127 plasma immersion ion implantation 149, 153 plastic deformation - gettering 121 - silicon slice fabrication 39 Poisson equation 68 f Poisson ratio, silicon 39 polishing - metallization 173 f - silicon slice fabrication 42 f poly-buffer layer, device isolation 125 polycrystal silicon 11 f - ultrapure 5 polyemitter bipolar process 76 polysilicon - metallization 155 - zone melting recrystalization 89 polysilicon deposition, gettering 119 polysilicon electrodes, BiCMOS 86 polysilicon encapsulated local oxidation (PELOX) 127 polysilicon thin film transistors 90 polysiloxanes, metallization 171 potential effect devices 332 ff Prandtl number 3 1 precipitation, oxygen in Czochralski silicon 45 f, 5 I precipitation kinetics, gettering 120 precipitation matrix 57 premate fusion 8 preoxidation cleaning, gate dielectrics 136 f Preston equation, metallization 173 process sequence - CMOS devices 118 ff - SALICIDES 150 production routes 11 pulling, Czochralski 18,26 purity, metallurgical-grade silicon I0 PVD, cluster tool technology 177

rapid thermal nitridation (RTN) cluster tool technology 181 - gate dielectrics 142 rapid thermal processing (RTP) 178 - cluster tool technology 177 - oxidation, gate dielectrics 139 RC time constants, metallization 160 RCA cleaning, gate dielectrics 137 recessed sealed sidewall field oxidation (RESSFOX) 127 recombination, lifetime killing, gettering 118 recombination-generation process 7 1 rectifier diode failures 21 reduction, carbothermic 7 f reflow sputtering, metallization 163 relaxation time constant, oxygen in Czochralski silicon 48 residual mechanical-damage-related defects, silicon 42 residual nitrogen, gate dielectrics 136 resist spin-on procedure, metallization 170 f resistance, negative differential 99 resistance heating, Czochralski silicon 25 resistivity - noblemetals 164 - salicides 161 resistivity striation, single crystal silicon 24 resonant-tunneling diode 97 resonant-tunneling hot-electron transistor 99 retarded precipitation, oxygen in Czochralski silicon 51 reverse bias 70 RF induction heating, Czochralski silicon 25 RIE, cluster tool technology 177 RIE nitride etching, isolation techniques 126 Rogowski loop 154 rotation, Czochralski silicon 32 -

~

~

sagging, Czochralski silicon 25 SALICIDES cluster tool technology 178 metallization 161 shallow junction formation 149 sandstone 7 sawing, silicon 36 f scaling, Czochralski silicon 34 f Schottky barriers, field-effect devices 80 SCI cleaning, gate dielectrics 137 scrub-rinse-spin-dry schedule, silicon slice fabrication 44 sealed interface local oxidation (SILO), device isolation 125 sealed sidewall trench (SST), isolation techniques I3 I Secco etching, float-zone silicon 22 segregation, fluorine 148 segregation coefficients, single crystal silicon 19 selective CVD tungsten plug process 167 selective deposition techniques 181,185 ~

~

~

quantization effect, quantum effect devices 95 quantum dot structure 97 f quantum effect devices 95 ff quantum effect silicon device structures 67 quantum wire channel MOSFET 97 quartzite 7 quasi-Fermi level 68 f radiation stability, gate dielectrics I35 random crystallization, Czochralski silicon 29 random-walk-well model, oxygen in Czochralski silicon 48 f rapid thermal annealing (RTA) 146 rapid thermal chemical deposition, (RTCVD) 149

Index selective doping, shallow junction formation 153 selective epitaxial growth (SEG) 126 isolation techniques 130 selective metal etching, metallization 165 selectivity loss, tungsten depositon 168 self-aligned salicides 149 self-interstitials, oxygen precipitation in silicon 50,55 semiconductor grade polycrystal silicon 1 1 ff semi-matt texture, silicon slice fabrication 42 separation by implantation of oxygen (SIMOX) 89, 132 shallow backside boron implantation, thyristors 78 shallow junction formation 145 ff shallow trench isolation (STI) 126 sheet resistance, metallization 158 Si-0-Si cleavage, metallization 174 sidewall mask isolation (SWAMI) 125 Siemens advanced carbothermic reduction 9, 13 f silane - copper precursors 169 - metallization 157 semiconductor grade polycrystal silicon 1 I ff silicidation, nickel 165 silicide precipitates, gettering 1 18 silicide resistivity, metallization 156 silicide-as-diffusion-source,SADS 149 silicide-silicon contact, field-effect devices 8 1 silicides, shallow junction formation 148 silicon - band gap 67 diffusion barrier, metallization 160 neutron transmutation doped 5 silicon avalanche cold cathode device 94 silicon device processing 113-193 silicon device structures 63-1 12 silicon processing 1-62 silicon-on-insulator (SOI) devices 88 f, 124, 13 1 f silicon-on-insulator structures, quantum effect devices 99 silver, physical properties 164 single crystal silicon 17 ff single drift, quantum effect devices 102 single wafer integrated processing 185 slice fabrication 36 ff slurries 43 small angle neutron scattering (SANS) 48 smoothing, metallization I70 ff Sol, isolation techniques 126 solar cells 107 f solid phase diffused drain structures 152 source-drain extension structure, SALICIDE process 162 spectrographic analysis 8, 16 spin on glass (SOG), metallization 171 spin on oxide, shallow junction formation 148 spinning diamond, silicon slice fabrication 4 1 sputtering, metallization 163 stable isotopes, silicon 19 stacked nitrideioxide films 180 stacked oxides, gate dielectrics 144 -

-

-

201

stacking faults gettering 11 8 - silicon crystal engineering 45, 52 step-etched slice, silicon 38 stirring, electromagnetic 33 storage capacity 118 strain-controlled Ge-channel MODFET 93 stress induced migration, metallization 162 stress voiding, metallization 170 stressistrain ratio, silicon 39 striation, single crystal silicon 23 striation etching 29 sub-atmospheric pressure, metallization I70 submerged-electrode arc furnace 8 submicrometer MOSFET 84 f substitutional lattice sites, gettering 119 subsurface damage, silicon 36 f sulfur, impurities 7 supercooling Czochralski silicon 28 f oxygen precipitation in silicon 56 - single crystal silicon 23 supersaturation, oxygen precipitation 47, 55 surface cracking, silicon slice fabrication 38 surface microdefects, gettering 122 surface-channel PMOS 85 surfaces, Czochralski silicon 30 -

-

-

TCS see: trichlorosilanes temperature, furnace 8 temperature dependence, Czochralski silicon 26,29 temperatures, stacking faults 52 TEOS oxide films, metallization 170 textures, silicon slice fabrication 42 thermal budget, gate dielectrics 135 thermal donors, oxygen in Czochralski silicon 45,49 thermal gradients, plastic deformation, gettering 12 1 thermal mechanical resonator 23 thermal neutron capture cross-sections, silicon 20 thermal oscillations, single crystal growth 23 thermal shock, Czochralski silicon 27 thermal stability - salicides, metallization 161 TiN, metallization I58 thin film transistors (TFTs) 89 three stage oxygen precipitation 56 thyristors 77 f time dependent breakdown (TBBD), gettering 122 TiN formation, cluster tool technology 178 TiSi,, physical properties 161 titanium impurities gettering 119 silicon processing I 1 titanium nitrides barrier layers 158 titanium silicide layer 158 titanium-tungsten barrier layers 158 topography, metallization 170 total integrated reading (TIR), silicon slice fabrication 42 -

-

202

Index

transconductance, MOSFET 86 transconductance oscillation 97 transistors - bipolar 72 f - cluster tool technology 183 - silicon device structures 67 transition metals - fast-diffusing, gettering 118 - preoxidation cleaning, gate dielectrics 136 trapping, gate dielectrics 136 trench isolation 126 triangular barrier 70 trichlorosilanes - float-zoned silicon 21 - semiconductor grade polycrystal silicon 11 f trichlorosilanes impurities 12 triisohutyl aluminum 166 triodes, microvacuum 94 triple-dielectric structure, MOSFET 9 1 tungsten deposition, metallization 166 f tunneling, direct, MOSFET 91 twinning, Czochralski silicon 27 two stage oxygen precipitation 54 ultra high vacuum CVD 76 ultra large scale integration (ULSI) 6 - bipolar application 133 - gettering 121 ultra shallow junction formation 182, I85 ultrapurity, polycrystalline silicon 5 unconsolidated sands 7 Union Carbide ultrahigh silane-silicon process 15 unity-power-gain frequency, bipolar transistor 73 uphill barrier 69

vacancies, oxygen in Czochralski silicon SO valence band offsets, quantum effect devices 10 1 veinquartz 7 very large scale integrated circuits, (VLSI) 5 - silicondevices 67 via-holes, metallization 163 via-holes refilling, metallization 154 via plug process, metallization 166 vias exploding 172 vias poisoning I72 voltage controlled field-effect devices 67 wafer, polished single-crystal silicon 67 wafer bonding process, SO1 133 wafer size, silicon device processing 1 18 water jet treatment, silicon crystal engineering wax-mounting, silicon slice fabrication 43 waxless process, silicon slice fabrication 43 well formation, isolation techniques 130 wells, quantum effect devices 95 wet etching, gate dielectrics 138 wet oxides, gate dielectrics 140 wires, quantum effect devices 95 wormholes, metallization 167 yields, Czochralski silicon 35 Young modulus, silicon 39 zero dislocation growth, silicon 27 zone melting recrystallization (ZMR) 89

52