Applications of silicon-germanium heterostructure devices

Applications of Silicon–Germanium Heterostructure Devices Series in Optics and Optoelectronics Series Editors: R G W B...

Author: C.K Maiti | G.A Armstrong

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Applications of Silicon–Germanium Heterostructure Devices

Series in Optics and Optoelectronics Series Editors: R G W Brown, University of Nottingham, UK E R Pike, Kings College, London, UK

Other titles in the series The Optical Transfer Function of Imaging Systems T L Williams Super-Radiance M G Benedict, A M Ermolaev, U A Malyshev, I V Sokolov and E D Trifonov Solar Cells and Optics for Photovoltaic Concentration A Luque

Forthcoming titles in the series Optical Fibre Devices J P Goure and I Verrier Diode Lasers D Sands High Aperture Focussing of Electromagnetic Waves and Applications in Optical Microscopy C J R Sheppard and P Torok Power and Energy Handling Capabilities of Optical Materials, Components and Systems R M Wood The Practical Application of the Moire Fringe Method C A Walker (ed) Transparent Conductive Coatings C I Bright XUV Optics: Fundamentals and Applications A V Vinogradov

Other titles of interest Thin-Film Optical Filters (Third Edition) H Angus Macleod

Series in Optics and Optoelectronics

Applications of Silicon–Germanium Heterostructure Devices C K Maiti and G A Armstrong Indian Institute of Technology, Kharagpur 721302, India and The Queen’s University of Belfast, Belfast, Northern Ireland, UK

Institute of Physics Publishing Bristol and Philadelphia

c IOP Publishing Ltd 2001 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior permission of the publisher. Multiple copying is permitted in accordance with the terms of licences issued by the Copyright Licensing Agency under the terms of its agreement with the Committee of ViceChancellors and Principals. British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library. ISBN 0 7503 0723 4 Library of Congress Cataloging-in-Publication Data are available

Consultant Editor: S C Jain Commissioning Editor: Tom Spicer Production Editor: Simon Laurenson Production Control: Sarah Plenty Cover Design: Victoria Le Billon Marketing Executive: Colin Fenton Published by Institute of Physics Publishing, wholly owned by The Institute of Physics, London Institute of Physics Publishing, Dirac House, Temple Back, Bristol BS1 6BE, UK US Oﬃce: Institute of Physics Publishing, The Public Ledger Building, Suite 1035, 150 South Independence Mall West, Philadelphia, PA 19106, USA Typeset in LATEX using the IOP Bookmaker Macros Printed in the UK by J W Arrowsmith Ltd, Bristol

In memory of Dr Suva Maiti

CONTENTS

PREFACE

xiii

1 INTRODUCTION 1.1 Evolution of bipolar technology 1.2 Heterojunction bipolar transistors 1.3 Development of SiGe/SiGeC HBT technology 1.4 Heterostructure ﬁeld-eﬀect transistors 1.5 Vertical heterostructure FETs 1.6 Optoelectronic devices 1.7 Applications of SiGe HBTs 1.8 Summary Bibliography

1 5 9 13 16 18 20 21 25 25

2 FILM GROWTH AND MATERIAL PARAMETERS 2.1 Strained layer epitaxy 2.2 Deposition techniques 2.2.1 Wafer cleaning 2.2.2 Molecular beam epitaxy 2.2.3 UHVCVD 2.2.4 LRPCVD and RTCVD 2.2.5 Very low pressure CVD 2.2.6 Remote plasma CVD 2.2.7 Atmospheric pressure CVD 2.2.8 Solid phase epitaxy 2.2.9 SiGeC ﬁlm growth 2.2.10 Strained-Si ﬁlm growth 2.3 Thermal stability of alloy layers 2.4 Bandgap and band discontinuity 2.4.1 Si/SiGe 2.4.2 Si/SiGeC 2.4.3 Strained-Si 2.5 Mobility 2.5.1 Si/SiGe 2.5.2 Si/SiGeC

32 33 42 43 44 46 47 48 48 48 49 49 50 51 52 54 56 58 59 59 59

viii

Contents 2.6

2.5.3 Strained-Si Summary Bibliography

63 64 65

3 PRINCIPLE OF SIGE HBTS 3.1 Energy band 3.2 Terminal currents in a SiGe HBT 3.3 Transit time 3.4 Early voltage 3.5 Heterojunction barrier eﬀects 3.5.1 Eﬀect of undoped spacer layers 3.6 High level injection 3.7 High-frequency ﬁgures-of-merit 3.7.1 Unity gain cut-oﬀ frequency, fT 3.7.2 Maximum oscillation frequency, fmax 3.8 Breakdown voltage, BVceo 3.9 Summary Bibliography

73 75 77 83 85 90 92 94 96 96 98 99 100 100

4 DESIGN OF SIGE HBTS 4.1 Device modelling 4.2 Numerical methods 4.3 Material parameters for simulation 4.3.1 SiGe: hole mobility 4.3.2 SiGe: electron mobility 4.3.3 SiGe: bandgap 4.3.4 Recombination and carrier lifetime 4.4 History of simulation of SiGe HBTs 4.5 Experimental SiGe HBTs 4.6 Device design issues 4.6.1 Base design 4.6.2 Emitter design 4.6.3 Collector design 4.7 Small-signal ac analysis 4.7.1 Small-signal equivalent circuit 4.7.2 Evaluation of transit time 4.7.3 ECL gate delay 4.8 Summary Bibliography

104 106 108 110 112 113 115 117 118 119 121 122 126 129 134 134 139 141 145 145

5 SIMULATION OF SIGE HBTS 5.1 Epitaxial-base SiGe HBT (1995) 5.2 Double polysilicon self-aligned SiGe HBT (1998) 5.3 Energy balance simulation 5.4 SiGe HBTs on SOI substrates

152 155 159 162 166

Contents 5.5 5.6 5.7 5.8 5.9

Low-temperature simulation 5.5.1 Low-temperature SiGe HBTs 5.5.2 Low-temperature simulation using ATLAS I2 L circuits using SiGe HBTs Noise performance Radiation eﬀects on SiGe HBTs 5.8.1 Low dose-rate eﬀects 5.8.2 Simulation of radiation hardness Summary Bibliography

ix 172 173 175 180 182 186 189 190 192 192

6 STRAINED-SI HETEROSTRUCTURE FETS 6.1 Mobility in strained-Si 6.1.1 Theoretical mobility 6.1.2 Experimental mobility 6.2 Band structure of strained-Si 6.3 Device applications 6.3.1 Strained-Si n-MOSFETs 6.3.2 Strained-Si p-MOSFETs 6.4 Simulation of strained-Si HFETs 6.5 MODFETs 6.6 Heterojunction Si/SiGe CMOS 6.7 Summary Bibliography

196 198 198 200 203 204 206 209 213 217 226 231 232

7 SIGE HETEROSTRUCTURE FETS 7.1 HFETs: structures and operation 7.1.1 Experimental HFETs 7.2 Design of SiGe p-HFETs 7.2.1 SiGe: MOS capacitor simulation 7.2.2 Si-cap/oxide thickness variation 7.2.3 Germanium mole fraction 7.2.4 Choice of gate material 7.2.5 Current–voltage characteristics 7.2.6 δ-doped p-HFETs 7.3 SiGe p-HFETs on SOI 7.4 SiGeC p-HFETs 7.5 Devices using poly-SiGe 7.5.1 Poly-SiGe gate MOSFETs 7.5.2 Poly-SiGe thin-ﬁlm transistors 7.6 Vertical FETs 7.6.1 Vertical SiGe HFETs 7.7 Noise in p-HFETs 7.8 Summary Bibliography

238 241 242 245 245 246 247 249 250 252 254 257 259 260 261 263 263 265 267 268

x

Contents

8 METALLIZATION AND HETEROSTRUCTURE SCHOTTKY DIODES 8.1 Deposition of metal ﬁlms 8.2 Fabrication of Schottky diodes 8.3 Silicidation of group IV alloy ﬁlms 8.4 Silicidation with titanium 8.4.1 Rutherford backscattering characterization 8.4.2 Auger electron spectroscopy characterization 8.4.3 Sheet resistivity 8.5 Silicidation using Pt and Pd 8.6 Heterostructure Schottky diodes 8.7 Schottky diodes on strained-Si1−x Gex 8.7.1 Barrier height and ideality factor 8.7.2 Interface state density distribution 8.8 Schottky diodes on strained-Si 8.9 Summary Bibliography

272 274 276 276 278 279 282 284 285 287 291 293 300 303 305 307

9 SIGE OPTOELECTRONIC DEVICES 9.1 Optoelectronic devices in silicon 9.1.1 p–n junction photodiode 9.1.2 Schottky barrier photodiode 9.1.3 p–i–n photodetectors 9.1.4 Metal–semiconductor–metal photodetectors 9.2 Optical properties of SiGe and SiGeC ﬁlms 9.3 Optical devices using SiGe alloys 9.4 Optical devices with SiGeC and GeC alloys 9.5 Simulation of optoelectronic devices 9.5.1 PtSi/SiGe Schottky photodetectors 9.5.2 SiGe p–i–n photodetectors 9.5.3 MSM photodetectors 9.5.4 SiGe/Si waveguide photodetectors 9.6 Summary Bibliography

310 315 316 317 318 318 321 325 334 336 338 341 345 350 352 353

10 RF APPLICATIONS OF SIGE HBTS 10.1 SiGe: perspective for wireless communication 10.2 Technology comparison 10.3 MOS versus bipolar 10.4 SiGe BiCMOS technology 10.5 RF circuits 10.5.1 Low-noise ampliﬁers 10.5.2 Power ampliﬁers 10.5.3 VCOs and frequency synthesizers 10.6 Passive components

359 363 367 369 375 378 378 381 384 386

Contents

xi

10.7 Commercially available products 10.7.1 TEMIC Semiconductors 10.7.2 IBM 10.8 Summary Bibliography

388 388 390 392 392

INDEX

397

PREFACE

Since the ﬁrst report of SiGe heterostructure bipolar transistors (HBTs) in 1987, there has been tremendous progress in SiGe research. The successful demonstrations of SiGe HBT technology, in both high-performance digital and analogue circuit applications, are the results of over 15 years of steady research progress from initial material preparations in 1984, through device demonstrations from 1987–1992 to large scale circuit fabrication in 1994 and commercial products in 1998. With the development of the ultrahigh vacuum chemical vapour deposition (UHVCVD) system, which produces highly uniform SiGe heterostructures more rapidly than other methods, such as molecular beam epitaxy (MBE) or low-pressure CVD, only minor modiﬁcations to the process ﬂow are required to incorporate the manufacture of SiGe HBTs into a conventional bipolar or complementary metal–oxide-semiconductor (BiCMOS) line. Indeed, SiGe HBTs integrated with CMOS (BiCMOS) circuits have been shown to be substantially cheaper than III–V technology. Qualiﬁed full-scale production devices (with cut-oﬀ frequencies in the 50–60 GHz range) and circuits using 200 mm wafers in a standard 0.5 µm CMOS line are now available. SiGe HBTs are superior to Si bipolar junction transistors (BJTs) and comparable to the best GaAs transistors, in that they are ideally suited for low-voltage, low-power wireless communication applications. Promising research results, combined with recent commercialization announcements, have generated considerable optimism. Silicon has been pushed to the 1–2 GHz frequency domain. However, many new RF applications, such as handheld and personal communication systems (PCS), direct broadcast TV, local multipoint distribution systems and wireless LANs, require circuit operation at frequencies up to 30 GHz. High-speed digital communications (up to 40 Gbps) such as synchronous optical network (SONET) applications also require highspeed devices—typically with a maximum oscillation frequency, fmax in excess of 100 GHz. It is now believed that, in many of these markets, SiGe will provide direct competition for GaAs on the grounds of cost and design ﬂexibility. Indeed, it is possible that SiGe technology may xiii

xiv

Preface

eventually be applicable in the frequency range above 30 GHz, where GaAs is currently well established, in projects requiring wireless technology for traﬃc management and control, such as global positioning systems (GPS), sensor collision avoidance systems, road speed monitors and side airbag triggers. The application of strained-SiGe to heterostructure ﬁeld-eﬀect transistors (FETs) is not as well developed as that of HBTs. In MOS technology, scaling the gate length is impeded by lithographic techniques and scaling device width is limited by the relatively low hole mobility of a silicon p-channel metal–oxide-semiconductor ﬁeld-eﬀect transistor (p-MOSFET). When used in a heterojunction FET, strained-SiGe enhances the mobility of holes but not of electrons. Thus, the current drive of the p-MOSFET is improved, but not that of the n-MOSFET. However, strained-Si grown on a relaxed-SiGe buﬀer layer improves the electron mobility and current drive of an n-MOSFET. Other important research topics include synthesis of SiGeC, a carbon-containing alloy of SiGe and Si, and quantum-conﬁned structures, which may ultimately oﬀer an alternative to lithographic techniques or serve as single-electron devices. Integrated optoelectronics is another promising research ﬁeld for SiGe devices, although development is hindered by the lack of a SiGe light emitter. Detectors and waveguides have been demonstrated, and integrated SiGe and Si devices are possible. Work is underway on a graded buﬀer layer—a virtual substrate—of SiGe that would permit III–V/SiGe/Si integration. Possible photonic devices are under development including: low-loss optical waveguides, photodetectors for 1.3–1.6 µm, light emitters, long-wave infrared detectors, optical switches and photonic integrated circuits. In this textbook, we discuss the relevance of SiGe technology to all the above application areas. The main focus of the book is on device applications, backed up by an extensive survey of the literature. Chapter 1 reviews the key developments in SiGe technology from the earliest research to the present day, leading to a brief summary of the current status of SiGe products in the marketplace. Chapter 2 describes key technology issues for the growth of stable strained-SiGe layers using diﬀerent types of reactors. The eﬀect of the Ge composition on strain and the consequent eﬀect on bandgap and mobility is described. Chapter 3 gives the background theory of the HBT. Chapter 4 describes issues relating to optimal design of SiGe HBTs and considers how device simulation can be used to determine key indicators of device performance. Chapter 5 extends the concepts of chapter 4 to give a number of examples of the use of device simulation to study a wide range of device structures involving application of SiGe. Chapter 6 describes how growth of a strained silicon (strained-Si) layer on a relaxed-SiGe buﬀer layer has led to higher values of electron mobility with the resultant enhancement in the high-frequency performance

Preface

xv

of heterojunction ﬁeld-eﬀect transistors (HFETs). Strategies for the enhancement of hole mobility using either MOSFET or modulation-doped ﬁeld-eﬀect transistor (MODFET) structures are given. The impact of both strained-Si MODFETs and MOSFETs as a basis for future deep submicron CMOS is considered. In chapter 7, an alternative approach to the formation of a p-HFET is described, involving growth of a strained-SiGe epitaxial layer on a silicon substrate. Once again, the overall objective is a higher mobility, in this case hole mobility, to improve both the transconductance and bandwidth associated with the p-channel MOSFET. Chapter 8 discusses design, characterization and application of Schottky diodes, while chapter 9 considers the design and application of optoelectronic devices. Finally, chapter 10 assesses how SiGe technology competes with other alternative technologies in the wireless telecommunications marketplace. It also focuses on how SiGe technology has rapidly matured, allowing its integration into a mixed signal BiCMOS process. In summary, this book ﬁlls a gap in the literature in a rapidly evolving ﬁeld, as it blends together wide ranging descriptions of SiGe technology, device physics and circuit applications. Where possible, the theoretical material is backed up by computer simulation. An extensive bibliography is provided for each chapter, which helps the reader identify the key stages in the development of SiGe from early research through to its integration in high-performance BiCMOS. We wish to extend special thanks to Professor S C Jain, Consultant Editor, Institute of Physics Publishing, for his keen interest and valuable comments. We are grateful to Tom Spicer, Commissioning Editor, for his personal support for this project. It was due to the skill and eﬀorts of his colleagues, Simon Laurenson, Production Editor, and Sarah Plenty, Production Controller, that the project could be completed in a relatively short time. They deserve our sincere thanks. The help of the Production Department in removing the deﬁciencies in several ﬁgures is gratefully acknowledged. Finally, we must thank sincerely our families for their support and help during the preparation of this book. C K Maiti G A Armstrong 26 October 2000

Chapter 1 INTRODUCTION

Silicon is by far the most widely used semiconductor material and is likely to remain so for the foreseeable future, although from the perspective of an integrated circuit (IC) designer silicon is hardly a perfect semiconductor. Compared with other semiconductors, it is relatively poor in terms of how fast the charge carriers can move through the crystal lattice, which limits the speed at which silicon devices can operate. ‘Why is silicon still dominant?’ The answer to this question is economics. Silicon is abundant in nature, non-toxic, strong and an excellent conductor of heat. It can be grown to a very high purity and very large diameter (with 12 inch now being contemplated) wafers, and it readily forms a stable insulating ﬁlm (SiO2 or Si3 N4 ) of high quality. Properties of this kind make silicon a natural choice for IC manufacturing and, in fact, over the past 40 years or so, the performance of silicon ICs and the density of devices per unit area have soared, while the cost per function has plunged (see ﬁgure 1.1). ICs are more diﬃcult and more expensive to fabricate from III–V compound semiconductors such as GaAs/AlGaAs or InP. High-quality oxides are scarce in the III–V semiconductors, impeding device integration. Highpurity, large diameter crystals are diﬃcult to grow and yield is poor because of more defect density. For decades, miniaturization has been the key to faster performance of ICs. As the size of a transistor, whether ﬁeld eﬀect or bipolar, inﬂuences its speed of operation, designers have focused on creating ever smaller transistors. The strategy for enhancing the function of an electronic device by reducing its critical dimensions is commonly referred to as scaling. Although scaling has led to improvement in the speed and ﬂexibility of silicon-based electronics, the trend cannot continue indeﬁnitely. Researchers are actively pursuing alternative approaches to boost the speed of electronic devices by introducing ‘bandgap engineering’. In silicon technology, two materials may be used in bandgap-engineered transistors: silicon carbide (SiC) and silicon–germanium (SiGe). Silicon 1

2

Introduction

Figure 1.1. Moore’s law: the gate length and cost of production lines as a function of time. Source: National Technology Roadmap for Semiconductors, Semiconductor Industry Association, San Jose, USA, 1997. (After Paul D J 1999 Adv. Mater. 11 191–204.)

carbide is a suitable emitter material, since it has a wider bandgap of 2.2 eV, while SiGe is a suitable base material with a lower bandgap which is dependent on the Ge content. The evolution of SiGe technology has been very rapid. It has gone from laboratory research in less than eight years to a commercial reality. As an example, a 12-bit digital-to-analogue converter (DAC) has been developed jointly by IBM and Analog Devices that processes data at 1.0 Gbit s−1 , which matches the speed of the best such circuits built using GaAs technology and it operates on a fraction of the power they require. At present, aggressively designed SiGe transistors have cut-oﬀ frequencies in excess of 130 GHz. In recent years, SiGe transistors, and other devices based on SiGe alloys, have been evident in an increasing number of products. SiGe heterojunction bipolar transistor (HBT) technology has the advantage of relatively simple integration with conventional complementary metal–oxide semiconductor (CMOS) silicon circuits to form a SiGe BiCMOS technology, in which the Si bipolar devices and SiGe HBTs can be integrated for critical high-speed analogue or digital functions. Silicon CMOS can serve for very high density memory or compact on-chip signal processing functions, which cannot be realized in other technologies. The two most important devices used in silicon technology are the bipolar and ﬁeld-eﬀect transistors, each having their strengths and

Introduction

3

Figure 1.2. Capacity of backbone network. (After Nakamura M 1998 IEEE ISSCC Tech. Dig. pp 16–21.)

weaknesses. Bipolar transistors with their high transconductance have predominantly been used in analogue applications, such as small-signal ampliﬁcation, and in high-speed digital circuits, such as emitter coupled logic (ECL). For digital circuit applications, CMOS technology dominates because of its low power dissipation and high density of integration. The variety of bipolar transistors can, in general, be grouped into those optimized to satisfy the requirements of two major industries: communications and computers. As all activities of modern society have become information oriented, the need for high-speed and large capacity telecommunications systems is rapidly increasing. The rapid growth in data transmission has also created an urgent demand for increasing transmission capacity in backbone networks. Today, 10 Gb s−1 systems are in commercial use. Figure 1.2 shows the predicted trend for optical ﬁbre transmission capacity. Two methods exist for achieving a higher transmission capacity: (i) time division multiplexing (TDM), and (ii) wavelength division multiplexing (WDM). Figure 1.3 shows the relationship between the bit rate and the required cut-oﬀ frequency (fT ) of devices from diﬀering technologies. A 10 Gb s−1 system with fT in the range 25–50 GHz can be satisﬁed using Si bipolar technology, while a 40 Gb s−1 system, with corresponding fT in the range 100–200 GHz, will require SiGe, GaAs or InP HBTs. In communication applications, the increased importance of transmitting, receiving and interpreting data transmissions at high speeds has generated a need for high-frequency precision analogue circuitry. With

4

Introduction

Figure 1.3. Electron devices for backbone network. (After Nakamura M 1998 IEEE ISSCC Tech. Dig. pp 16–21).

internet host counts doubling every ﬁve to seven months, there is a pressing need for high-speed interconnect circuits [1]. In these circuits, the high operating frequency, high transconductance, close matching of the device parameters and bandgap voltage referencing capabilities of bipolar transistors make them invaluable to the design of analogue circuits. In the computer industry, the high-frequency performance and high current drive capabilities of bipolar transistors enable the realization of digital circuits with very low gate delay and high fan-out compatibility. The switching delay of a bipolar circuit is made up of three major components. The importance of these two characteristics can be best illustrated by a graph of the ECL gate delay time versus the collector current of the bipolar transistors, as shown in ﬁgure 1.4. In the low collector current range, the gate delay is a function of the load resistance, RL , and the input capacitance of the gate, Cin , which is determined by the capacitance of the bipolar transistors as seen from the gate input. In the high collector current range, the gate delay decreases, approaching a minimum set by the total forward transit time of the transistor, τF . At higher currents, the product of the combination of extrinsic and intrinsic base resistance and the diﬀusion capacitance begins to dominate the propagation delay. As is evident from ﬁgure 1.4, the realization of low gate delays requires the use of increased collector currents. Thus, if the operating current per gate is a limiting factor, the design should be focused on the reduction of parasitic capacitances. The delay contributed by each part of the transistor is diﬀerent, depending on the type of circuit used.

Evolution of bipolar technology

5

Figure 1.4. Variation of delay components of a bipolar circuit versus collector current. At low currents, the gate delay is determined by the charging of the junction capacitances. At high currents, the minority carrier storage associated with high-level injection prevails.

However, power consumption and dissipation restrictions in digital bipolar circuits limit the collector current of the densely packed transistors. For high-speed digital applications, the challenges for designers of bipolar junction transistors (BJTs) include an increased level of integration, lower operating currents, reduction in base resistance and lower minimum gate delays. 1.1.

EVOLUTION OF BIPOLAR TECHNOLOGY

The design and study of a new semiconductor device structure hold promise at both the device level, where the transistor’s electrical behaviour may lead to novel eﬀects, and the circuit level, where the device characteristics may be exploited to enhance functional performance. Since the revolutionary invention of the point-contact transistor at Bell Laboratories in 1947, numerous new transistor structures have been proposed and demonstrated. Of the many transistors demonstrated in the last ﬁfty years, however, the IC market is dominated by just two devices: the BJT with a market share of about 20%, and the metal–oxide semiconductor ﬁeld-eﬀect transistor (MOSFET) with 75%. BJTs and MOSFETs are the dominant highperformance devices in silicon technology. In this section, we shall present an overview of the high-performance transistors in silicon.

6

Introduction

Figure 1.5. (a)–(g) The evolutionary continuum between bipolar and ﬁeld-eﬀect transistors. A conventional FET is shrunk in lateral dimension (a), then converting to a stacking conﬁguration (b). Rotating the structure by 90◦ produces (c). Reducing the vertical dimensions from (c) to (e) yields a permeable base transistor. Replacing the grid with a sheet of metal produces a metal-base transistor (f ). Finally, replacing the metal base with a p-doped layer results in the conventional bipolar transistor (g). (After Stoneham E B 1982 Microwaves 55–60.)

Evolution of bipolar technology

7

The FET represents a class of devices (including MOSFETs, metal– semiconductor ﬁeld-eﬀect transistors (MESFETs) and junction ﬁeld-eﬀect transistors (JFETs)) which operate on a principle substantially diﬀerent from that of the class of devices represented by the BJT. FETs represent lateral geometries and spatial charge control (via depletion regions), while BJTs represent vertical geometries and charge control. An ideal threeterminal device may be considered to move the charge within a ﬁnite time, when stimulated by some input voltage or current. Stoneham [2] has shown that most new devices lie somewhere between the extreme cases of BJTs and FETs. By manipulating the geometries and translating lateral and vertical properties, the evolution of one device into the other is possible as shown in ﬁgure 1.5. Although MOSFETs have constantly challenged the BJTs for performance superiority, bipolar devices have consistently kept their advantage by evolving new and/or improved process and design. The historical advantage of the bipolar device is the fact that its vertical dimensions are easier to control than the lateral MOS structure. Current gain in a homojunction npn bipolar transistor is mainly determined by the ratio of the density of electrons injected from the emitter into the base and the density of holes reinjected from the base into the emitter, and results in a ﬁnite dc current gain. Many attempts have been made to design improved emitter structures to minimize the disadvantages of the homojunction Si BJT with a heavily-doped emitter. Among these, polysilicon technology is by far the most advanced but problems with contact resistance still exist. Techniques to reduce contact resistance lead to reduced emitter eﬃciency [3, 4]. In a circuit environment, however, parasitics tend to dominate. The base–collector extrinsic junction and the base resistance prevent input signals from reaching the appropriate internal junctions until suﬃcient charge has ﬁlled the depletion regions (in the case of the base–collector capacitance), while the base resistance reduces the voltage seen by the internal emitter–base junction, lowering the eﬀective transconductance. The steady improvement in performance of the BJT is the result of technology maturing suﬃciently to build these scaled optimal structures. The evolution of new process technologies, such as silicon-on-insulator (SOI), trench isolation and epitaxial regrowth, provide techniques to drastically reduce the junction capacitances. These techniques have pushed the evolution of the transistor to its technical limits. As lateral geometries continue to shrink, devices require vertical design modiﬁcations in order to maintain higher performance. Several alternative structures have been proposed in the literature to extend the performance of silicon bipolar devices. The metal-base transistor at one time held the most promise of all hot electron devices [5]. The injection of electrons from the emitter occurs as in a BJT, but electrons

8

Introduction

entering the base from the emitter see a large band discontinuity. This accelerates them to a large momentum in the vertical direction. The base being very narrow, electrons remain hot throughout the base region, resulting in a reduction in the base transit time. In addition, the use of a metal for the base reduces the base resistance. In principle, the metal-base transistor should have a signiﬁcant performance advantage over the BJT. Unfortunately, no metal-base transistor has yet achieved even unity current gain. Nishizawa [6] proposed a high-speed switching device known as the bipolar static induction transistor (BSIT) which may be thought of as a bipolar transistor with the intrinsic base region missing. Control of collector current in this device is only possible because the extrinsic p+ base regions are physically close together and current is controlled by forward biasing the base–emitter junction. A high transconductance is obtained compared to FETs of comparable dimensions and also leads to faster switching times. Indeed, several types of circuits have been successfully fabricated with the BSIT device [6, 7]. However, due to its extreme sensitivity to process variations, the BSIT could hardly be useful for high levels of circuit integration. Another interesting structure, a tunnel transistor, which is identical to that of a p-channel MOSFET with a very thin (20 ˚ A) gate oxide layer has also been proposed [8]. The thin oxide layer allows substantial electron tunnelling currents in the vertical direction. The gate can thus act as an emitter, the substrate as a collector and the source/drain regions as extrinsic base regions. The intrinsic base is replaced with a mobile hole layer or ‘inversion channel’ whose charge density modulates the electric ﬁeld strength across the oxide, and thus controls the electron tunnelling currents in the vertical direction. This hole charge density is controlled by the extrinsic base potential. Using this concept, Simmons and Taylor [8] have theoretically and experimentally studied tunnel transistors built in the Alx Ga1−x As/GaAs material system. GaAs was used as the emitter and the collector semiconductors and AlAs was used as a wide bandgap semiconductor replacing the insulator. However, limited current density and transconductance resulted in a much slower device. Despite much research on alternative technologies, silicon integrated circuits dominate mainstream electronics. Impressive improvements in high-speed Si bipolar technology have been made in the last few years. Self-aligned bipolar transistors having polySi base electrodes have been eﬀective in reducing base resistance through their small resistance in the base electrode and short length between the emitter and the base. Si homojunction transistors with a maximum oscillation frequency, fmax above 80 GHz have been obtained using low base resistance selfaligned metal/IDP (SMI) technology. The base resistance is reduced to a half compared to conventional polySi technology and a 12.2 ps gate delay

Heterojunction bipolar transistors

9

Figure 1.6. Si and SiGe device performance over the past several years. In terms of device speed, SiGe has maintained about 50% advantage over Si devices.

time in an ECL ring oscillator at a voltage swing of 250 mV has been achieved [9]. In 1999, Bopp et al [10] reported a near production, standard implanted base silicon bipolar technology for mixed-signal applications. Applicability for mobile communications up to at least 6 GHz, and for high-speed data links in the range 10–40 Gbits s−1 , was demonstrated. Transistors exhibited an fmax of 65 GHz, a minimum noise ﬁgure of 1.3 dB at 6 GHz and a 12 ps ECL gate delay. Summarized in ﬁgure 1.6 are some of the reported results obtained with high-performance Si homojunction transistors. Although the data for Si are only plotted up to 1997, the trend line shows that SiGe oﬀers approximately 50% advantage in overall device performance. By way of comparison, back in 1991, AlGaAs/GaAs MODFETs achieved an fT of over 250 GHz [11] and exceeded the 400 GHz barrier for fmax . In an eﬀort to improve single chip functionality, it is not surprising that, despite increased process complexity, BiCMOS processes have been developed to combine the advantages of CMOS and bipolar devices [12]. 1.2.

HETEROJUNCTION BIPOLAR TRANSISTORS

The idea of varying the bandgap in a bipolar transistor structure to increase the emitter injection eﬃciency is almost as old as the bipolar junction transistor itself. Shockley described the idea in his application for a patent on the junction bipolar transistor [13]. The inherent performance advantages of HBTs over conventional bipolar junction transistors have been recognized and Kroemer [14] ﬁrst explained the underlying principle

10

Introduction

of the heterojunctions. The heterojunction oﬀers a larger set of device conﬁgurations and has become the basis for the so-called ﬁeld of bandgap engineering [15]. The principle of operation of an HBT is identical to that of the BJT, except that the bandgap of the emitter region exceeds that of the base region by ∆Eg , typically of the order of 0.1–0.2 eV. The resultant e∆Eg /kT exponential increase in current gain permits scaling of the base region to smaller thicknesses and higher doping levels. Conceptually, the simplest way to incorporate a heterojunction into a silicon bipolar transistor process is to replace the polySi emitter of a standard bipolar process with a wide bandgap material having a high-quality interface to the silicon base, thereby combining the minimized parasitic capacitances and resistances of the device structure with the increased emitter injection eﬃciency of the wide bandgap emitter HBT. Several wide bandgap materials have been investigated, such as GaP [16–18], semi-insulating polycrystalline silicon (SIPOS) [19–21], oxygen-doped silicon epitaxial ﬁlms [22], epitaxial β-SiC [23], polycrystalline β-SiC [24], amorphous silicon (α-Si) and microcrystalline (µc-Si) silicon [25–27]. Major problems encountered were antiphase domains and cross doping (GaP), high bulk or contact resistance (α-Si and poly-β-SiC), and high processing temperature (single crystalline β-SiC). Moreover, it seems diﬃcult to realize ideal, or at least reproducible, base currents with these materials [26, 28]. β-SiC can now be grown at 750 ◦ C, greatly improving its prospects for integration into Si HBTs with narrow and heavily-doped bases. A key point concerning wide bandgap emitter silicon HBTs is that the shape of the conduction band barrier in the base is identical to that of an Si homojunction transistor. It is therefore impossible to obtain improvements in transit time and output resistance associated with a bandgap grading between the emitter and collector sides of the base leading to a built-in drift ﬁeld for the minority carriers in the base. Some of these structures may prove useful for special applications. However, in general, these have not been accepted by the semiconductor industry due to the diﬃculties in process optimization and reproducibility. Although the performance advantages of HBTs over BJTs were well understood, no fabrication technologies were available to produce highquality heterojunctions until the 1970s. The emergence of two new growth techniques, namely molecular beam epitaxy (MBE) [29] and metal–organic chemical vapour deposition (MOCVD) [30], sparked a thrust in the research of high-speed HBTs. Most research has been on the AlGaAs/GaAs system and related compound semiconductors. The high performance demonstrated by HBTs is a result of not only the inherent advantages of heterojunctions, but also the use of semiconductor materials with higher mobilities and saturated drift velocities. For instance, implementation of an Alx Ga1−x As/GaAs HBT has yielded the lowest demonstrated gate delay of

Heterojunction bipolar transistors

11

1.9 ps, and an AlInAs/InGaAs HBT has given a unity current gain cut-oﬀ frequency exceeding 200 GHz. Despite the advances in HBT fabrication techniques, mostly using group III–V and II–VI materials, silicon devices continue to dominate due to the low cost and ease of manufacturability. Silicon readily forms a high-quality oxide which can be used to mask implants, diﬀusion and metallization. The isolation technique, chemical vapour deposition, diﬀusion, ion implantation, contact technology and etching methods are highly developed in Si technology. GaAs and the other III–V semiconductors lack this important property. It is well known that GaAs or InP technologies exhibit superior fT and fmax , compared to a SiGe device, for a speciﬁed geometry. An excellent comparison of the technologies has been presented by Konig and Gruhle [31]. Plots from [31] of both fT and fmax as a function of base width are shown in ﬁgures 1.7 and 1.8. A further performance comparison of a III–V material HBT with a SiGe HBT has been presented by Larson [32]. Clearly, if maximum bandwidth or speed is the only criterion, then

Figure 1.7. Comparison of cut-oﬀ frequency, fT , as a function of base width for SiGe HBTs and devices from III–V technologies. (After Konig U and Gruhle A 1997 Proc. IEEE Cornell Conf. on Advanced Concepts in High Speed Semiconductor Devices and Circuits pp 14–23.)

12

Introduction

Figure 1.8. Comparison of maximum frequency of oscillation as a function of base width for SiGe HBTs and devices from III–V technologies. (After Konig U and Gruhle A 1997 Proc. IEEE Cornell Conf. on Advanced Concepts in High Speed Semiconductor Devices and Circuits pp 14–23.)

III–V technology is a superior option. In overall radio frequency (RF) system performance, including antenna interfacing, low noise and low power ampliﬁer performance and relatively high levels of integration, SiGe HBT technology oﬀers signiﬁcant advantages, as summarized in table 1.1. Table 1.1. Technology comparison in the frequency range of 1–10 GHz. (After Temic Semiconductors, Germany.)

Low-frequency noise Low RF noise Low voltage High gain High power High eﬃciency Analogue capability Integration level Power supply

Si BJT

SiGe HBT

GaAs FET

+ O + − − − O + +

+ + + + + + + + +

− + O + + + + O −

Development of SiGe/SiGeC HBT technology 1.3.

13

DEVELOPMENT OF SIGE/SIGEC HBT TECHNOLOGY

As silicon BJTs reach their fundamental limits on speed because of the physical properties of the semiconductor material, advanced high-speed devices require heterojunction technology, as has been demonstrated in the previous section. Although Ge had made its mark as the point-contact electrode on the ﬁrst transistor, Si eventually became the semiconductor of choice for its material properties. In 1957, Kroemer patented the ﬁrst heterojunction Si bipolar transistor and eighteen years later, Erich Kasper at Daimler–Benz (now Daimler–Chrysler) made the ﬁrst SiGe strained layer [33]. With the advent of heteroepitaxy, the concept of strained layers has been extended to include other elemental semiconductors. These developments set the stage for IBM’s development of SiGe HBTs in 1987 using MBE. The use of the ultrahigh vacuum chemical vapour deposition (UHVCVD) tool for HBT and BiCMOS devices followed. SiGe HBTs are particularly exciting because of their ability to take immediate advantage of highly developed silicon processing techniques. Impressive improvements in high-speed SiGe bipolar technology have been made through the growth of device quality strained-Si1−x Gex layers. This strain, which occurs because of a ∼4% diﬀerence in the lattice constants of Si and Ge, is used to vary the bandgap energy, band discontinuities and other properties of the material. For any given Ge content, there is a critical thickness of SiGe, above which dislocations cause severe performance degradation, as discussed more fully in chapter 2. The thin base layer of Si1−x Gex , sandwiched between the Si collector and emitter, must be thin enough to prevent the formation of these dislocations. Of additional signiﬁcance is the enhanced mobility in a strained layer which oﬀers the possibility of improved performance in SiGe-based FET devices, as discussed in chapters 6 and 7, although much of this work is still in the research stage. Higher mobility in digital circuits permits a smaller voltage swing to switch between states, leading to both faster switching times and reduced power consumption. Although the introduction of Ge in the base increases process integration complexity, it oﬀers an additional degree of freedom which relaxes a series of trade-oﬀs aﬀecting device design. Several key advantages over conventional bipolar transistors include: • • • •

reduction in base transit time—resulting in higher frequency performance; increase in collector current density and hence current gain; lower intrinsic base resistance; and increase in Early voltage.

The design of a SiGe HBT, for a particular technology generation, is optimized by appropriate scaling of the emitter, base and collector regions

14

Introduction

and their associated doping proﬁles. A SiGe HBT oﬀers additional design ﬂexibility in that the bandgap of the base may be tailored by grading the Ge concentration. Reducing the width of the base region reduces the base transit time with associated improvement in cut-oﬀ frequency, but inevitably increases overall base resistance with possible reduction in fmax . For eﬀective design, it is thus essential to use an appropriate simulation tool. Many of the signiﬁcant issues have been published in a number of reports dealing with aspects of both numerical and analytical modelling of SiGe HBTs [34–41]. In chapters 4 and 5 of this book, we discuss the design considerations for SiGe HBTs in terms of the following: • • • •

optimization of base, emitter and collector doping proﬁles; eﬀect of Ge proﬁle on the transit times; prediction of cut-oﬀ frequencies, fT and fmax ; and design issues at low temperature.

Since the ﬁrst report of SiGe HBTs in 1987, there have been numerous demonstrations (see ﬁgure 1.6) of its impressive potential. For example, an early theoretical study [42] predicted a unity gain cut-oﬀ frequency in excess of 300 GHz. Since then there have been a number of signiﬁcant milestones in the measured performance of SiGe HBTs, including fT in excess of 130 GHz [43], fmax values of 160 GHz [44], ECL and current model logic (CML) gate delay of less than 10 ps [45–47]. Recently, an Si/Si0.65 Ge0.35 abrupt SiGe HBT with an fT of 213 GHz and fmax of 115 GHz at 77 K has been reported [48]. Summarized in table 1.2 are some of the reported results obtained with high-performance SiGe HBTs, which relate to state-of-the-art performance in commercially available devices. The addition of substitutional carbon to silicon–germanium thin ﬁlms

Table 1.2. Some of the commercially available (as of 1998) device results from various SiGe research groups. Group parameter

IBM (1996)

IBM (BiCMOS)

NEC

HP

Daimler–Benz

fT /fmax (GHz)

48/60

48/60

60/50

40/–

59/90 113/65

Rbi /Rb (Ohms/square)

7–9 k

7–9 k

–

40k

380–780

Wb (˚ A)

700–1000

700–1000

–

500–600

150 w/spacers

Ge Proﬁle

0–15% various shapes

0–15% various shapes

15% graded

16% graded

30% uniform

Development of SiGe/SiGeC HBT technology

15

leads to a new class of semiconducting materials (SiGeC) [49, 50]. This new material can remove some of the constraints (such as the critical layer thickness) on strained-Si1−x Gex and may help to open up new ﬁelds of device applications for heteroepitaxial Si-based systems. The incorporation of carbon [51] can be used: • • •

to enhance the SiGe layer properties; to obtain layers with new properties; and to control dopant diﬀusion.

A summary of possible applications of C-containing Si and SiGe ﬁlms are shown in table 1.3. The incorporation of a low concentration of carbon (<1020 cm−3 ) in the SiGe region of SiGe HBTs can suppress boron out-diﬀusion caused by subsequent processing steps [52]. This allows one to use higher boron doses within the SiGe base layer and/or narrower undoped SiGe spacers, leading to a signiﬁcantly improved transistor performance. For example, SiGeC HBTs have demonstrated excellent fT and fmax values [53] comparable to the performance of state-of-the-art SiGe HBTs, as shown in ﬁgure 1.9. The presence of carbon also relaxes technological process design constraints by reducing the sensitivity of dopant proﬁles to subsequent processing steps. When compared with SiGe technologies, the addition of carbon oﬀers a signiﬁcantly greater ﬂexibility in process design and a greater latitude in processing margins [54–56]. Basic growth techniques, the mechanical and electrical properties of Si1−x−y Gex Cy layers

Figure 1.9. Cut-oﬀ and maximum oscillation frequencies versus collector current for SiGeC HBTs. (After Osten H J et al 1999 IEEE BCTM Proc. pp 109–16.)

16

Introduction

Table 1.3. Possible applications of C-containing Si and SiGe ﬁlms. (After Osten H J et al 1998 Thin Solid Films 321 11–14.) Material advantages

Possible device applications

Increase performance and process margins for HBTs Suppress transient enhanced diﬀusion of boron Reduce undoped SiGe spacers

HBT

Increase thickness, stability, Ge content of Si1−x Gex

p-Channel FET, npn HBT

Use strained-Si1−y Cy on Si instead of Si on relaxed buﬀer

n-Channel FET, pnp HBT

Design new buﬀer concepts with Si1−x−y Gex Cy Use the reduction of dislocation propagation

Virtual substrates for hetero-FETs

Strain symmetrization on Si

Superlattices on Si(001) for optical applications

grown pseudomorphically onto Si(001) and their applications have been comprehensively reviewed by Osten [57]. 1.4.

HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS

The Semiconductor Industry Association (SIA) roadmap for CMOS technology predicts that the minimum feature size will approach 10 nm by 2024. For the most aggressively scaled DRAM, the scale of integration will reach 64 Gbits in 2010. The slowing of the scaling rate noted in the roadmap indicates several key technological hurdles that must be surmounted in order to attain the milestones of the roadmap. These challenges encompass almost all aspects of device science, processing and integration architectures including interconnections and patterning technology. The ﬁeld-eﬀect transistor (FET) is customarily a lateral structure, while the bipolar transistor discussed in the previous section is, in general, vertical. The ﬁrst insulated gate ﬁeld-eﬀect transistor (IGFET) was demonstrated in 1960, a metal–oxide semiconductor FET (MOSFET) which uses silicon as the semiconductor and silicon dioxide as the insulator. A primary reason for the success of this device is the passivating eﬀect that the silicon dioxide has on the underlying silicon interface. For this reason,

Heterostructure ﬁeld-eﬀect transistors

17

the most successful IGFETs are still silicon-based MOSFETs. MOSFETs using an n-channel (i.e., with electrons rather than holes as the charge carriers between n-type source and drain), are smaller than those of p-MOS due to the higher electron drift velocity. Because of the technical diﬃculty in passivating other semiconductor materials, other successful FET structures which avoid the need for passivation have also been proposed. In the metal–semiconductor FET (MESFET), the insulating layer is replaced with a Schottky contact. The need for passivation of column III–V semiconductors, such as GaAs, is circumvented at the expense of substantially larger gate leakage currents. The high-performance MESFETs are generally n-channel due to the higher electron drift velocity. In scaling down the classical planar MOS device towards deep submicron dimensions, the most important technological limit encountered is the deﬁnition of the channel length by lithographic techniques. From a physical point of view, the short channel eﬀect, which translates into drain-induced barrier lowering (DIBL) and as such into threshold voltage roll-oﬀ and oﬀ-state leakage current, is the most important limitation. Heterojunction FETs (HFETs) can be pictured as a hybrid between the MOSFET and MESFET and are the high performing junction FETs. Instead of a very wide bandgap oxide, a moderately wide bandgap semiconductor is used as the insulator. Often this layer is doped with impurities, but the resulting charge carriers are localized in the narrower bandgap and therefore lower potential, second semiconductor. Due to the separation of doping and charge carriers, the resulting FETs are frequently referred to as modulation-doped ﬁeld-eﬀect transistors (MODFETs). An alternative name, high electron mobility transistors (HEMTs) is derived from the much higher mobilities that result from modulation doping, since the physically segregated impurities are less eﬀective in scattering the charge carriers. However, for high-performance short-channel devices fabricated to date, the mobility plays only a small role, and it is the saturated drift velocity which determines the channel transit time of an FET. In the area of SiGe electronics, the bulk of the eﬀort has concentrated on HBTs. However, the inherent capabilities of an Si/SiGe heterostructure can also be applied to create SiGe-based modulation-doped FETs, as well as being inserted into MOS structures to create heterostructure complementary metal–oxide semiconductor (HCMOS) transistors, in which the Schottky gate, used in a MODFET, has been replaced with a MOSgate [58]. Typically, n-MODFETs use Si quantum wells (QW), while p-MODFETs use a SiGe or a Ge QW, with both structures requiring the growth of a thick SiGe buﬀer layer. Ismail [59] has reported on 0.4 µm gate length n-MODFETs with a measured peak transconductance

18

Introduction

of 420 mS mm−1 , which is about a factor of two higher than Si n-MOSFETs. This MODFET exhibited an fT and fmax of 33 and 40 GHz, respectively. Introduction of the graded SiGe buﬀers dramatically increases two-dimensional electron gas (2DEG) mobility values as high as 180 000 cm2 V−1 s−1 at low temperature for n-MODFETs. However, what is more important for device applications is room temperature mobility, which is found to range from 1000 to 3000 cm2 V−1 s−1 —a factor of four to six times greater than for Si-only MOSFETs. A 0.7 µm gate length SiGe p-MODFET has shown peak transconductance of 200 mS mm−1 , while similar transconductance values for Si-only p-MOSFETs can only be achieved with gate lengths reduced to 0.2 µm or below. The p-MODFETs exhibited an fT and fmax of 10 and 18 GHz, respectively, along with room temperature mobilities of 1400–1800 cm2 V−1 s−1 —a factor of six to nine times those above standard p-MOSFETs with comparable doping. Simulation studies on the performance of complementary MODFET structures predict, for a 0.1 µm gate length device, peak transconductance of 820 mS mm−1 for an n-MODFET, and 610 mS mm−1 for a p-MODFET, comparable to the performance achievable with III–V-based materials. The application of strained-SiGe layers to FETs is not as well developed as HBT applications. A fundamental limitation has been that strained-SiGe enhances the mobility of holes but not electrons. Thus, the current drive of p-FET devices is improved, but not that of n-FETs. However, strained-Si grown on a relaxed-SiGe layer improves electron mobility and n-FET device performance. Techniques for forming highquality relaxed-SiGe on Si substrates have demonstrated performance improvements for both n- and p-HFETs [60–62]. Hartmann et al [63] have proposed that SiGeC alloys may oﬀer an increased leverage in CMOS technology, just as SiGe has increased the performance of bipolar technology. It has been shown that both electron and hole conﬁnement appear possible without the need of relaxed buﬀer layers, making the SiGeC alloy a potential for CMOS technology. Recently, Quinones et al [64] have presented the evaluation of the strainstabilizing capabilities of C in the SiGe material system by fabricating SiGeC heterojunction p-MOSFETs over a range of Ge concentrations. Several excellent reviews on the possibilities and potential of the SiGechannel MOSFETs for a submicron CMOS technology have also appeared [65–67]. 1.5.

VERTICAL HETEROSTRUCTURE FETS

Vertical MOS structures are being explored for increasing the integration density and for incorporation of quantum eﬀects into MOS devices. Vertical MOS heterostructures are expected to solve the scaling issues of lithography, doping conﬁnement and DIBL. Vertical devices will have

Vertical heterostructure FETs

19

small contact areas and will facilitate interconnects and minimize the via contacts leading to a minimization of the area per function. Present projections, based on the operation of a 20 nm channel length vertical device at room temperature, result in an on-current of 20 000 µA µm−1 , an oﬀ-state current less than 1 pA µm−2 , a peak transconductance of more than 3500 mS mm−1 , a VT of less than 0.3 V at VDD of 1 V and an intrinsic carrier transit time of less than 1 ps. In establishing its potential advantages and assessing its performance with respect to conventional transistors, a technology which provides denser and faster structures, and uses the standard processing technology and production equipment, research has been initiated. In fact, the SiGe technology has been implemented in the Si process lines by several manufacturers and is expected to facilitate a low-cost transfer of the new vertical SiGe heterostructure MOS into production. In addition, a CMOS possibility also exists if the heterojunction is made by a SiGe/Si(p-MOS) or SiGe/Ge(n-MOS) combination. All these materials are compatible with Si technology and allow for an easy integration into production. A vertical heterostructure MOS (VHMOS) has the following advantages. •

•

The device is not a lateral but a vertical one; source/channel and drain regions are grown epitaxially. As such the device channel length is deﬁned by the channel layer epitaxial growth and thus fully decoupled from lithographic limitations. Therefore, much shorter channel lengths (down to 20 nm) become feasible. At the source side of the device, a heterojunction is used which keeps the barrier for conduction in the oﬀ-state constant and not aﬀected by the drain voltage. In order to have conduction in the on-state, the source side closest to the channel region is intrinsic. This allows for Fermi-level modulation by the action of the overlapping gate and thus conduction. The DIBL eﬀect no longer exists [68].

The experimental evidence of the enhancement of out-of-plane hole mobility in SiGe using a vertical p-MOSFET structure, fabricated by high-dose Ge implantation followed by solid phase recrystallization, has been reported [69]. The structure combines the merits of a very short channel device without a critical lithography process and a higher hole mobility in the channel region. Superior performance with respect to a homojunction structure has been demonstrated, especially for deep submicron dimensions. Although the p-MOS devices have been reported so far, similar work is being performed on n-MOS devices with strainedSi/SiGe in the source/channel and drain regions. However, in this case, a virtual substrate consisting of a relaxed-SiGe layer is needed [68, 70]. Up to this point, we have described the major application areas where SiGe technology has become established. However, there are a number of

20

Introduction

other application areas in which SiGe devices may have a role to play. Bipolar inversion channel ﬁeld-eﬀect transistors (BICFETs) have been studied extensively theoretically [71] as well as experimentally in SiGe materials [72–74]. Taft and Plummer [71] implemented the concept in the SiGe material system in order to take advantage of the established Si technology and showed that the SiGe BICFET could potentially fulﬁl both the ends: high performance (due to its intrinsic speed advantage) and manufacturability (due to the lower costs of silicon processing). Kasper and Reitemann [75] have explored the idea of a common device structure for diﬀerent functions by combining a SiGe HBT and a charge injection transistor (CHINT) on Si–SiGe–Si–SiGe [76]. It is a hot electron device; VDS accelerates the carriers, which cross the SiGe–Si barrier to be collected at the real space transfer output as stated. 1.6.

OPTOELECTRONIC DEVICES

The optoelectronics realm has traditionally been reserved to III–V and II–VI compound semiconductors, due to the availability of direct transitions and heterostructures. However, the introduction of SiGe allows heterostructures to be fabricated in traditional Si-only technologies, which expands the potential of Si optoelectronics. A conceptual integrated silicon chip of the future including CMOS, HBT/bipolar, SiGe quantum devices, SiGe detectors, SiGe waveguides and light emitter all on a chip is shown in ﬁgure 1.10. Integrated optoelectronics is another promising research

Figure 1.10. The integrated silicon chip of the future: CMOS, HBT/bipolar, SiGe quantum devices, SiGe detectors, SiGe waveguides and light emitter all on a chip. (After Paul D J 1998 Thin Solid Films 321 172–80.)

Applications of SiGe HBTs

21

ﬁeld for SiGe devices, although development is hindered by the lack of a SiGe light emitter. Detectors and waveguides have been demonstrated, and integrated SiGe and Si devices are possible. Si-based heterostructures, such as Si/SiGe, oﬀer the possibility of improving the standard Si device performances, particularly in highfrequency and low-noise applications, with the additional advantage of still being compatible with mainstream Si technology. Furthermore, SiGe microstructures can also enable the integration of optical devices (LEDs and photodiodes) with silicon-based integrated circuits. Research has been initiated on a graded buﬀer layer of SiGe—a virtual substrate—that would permit III–V/SiGe/Si integration and open the door for integrated optoelectronics [77]. The growth of device quality GaAs epitaxial layers on Si substrates is a long-range goal of electronic materials research. The epitaxial growth of GaAs on Si substrates through the use of a Ge/graded-Si1−x Gex /Si buﬀer layer would allow monolithic integration of GaAs-based optoelectronics with Si microelectronics [78]. 1.7.

APPLICATIONS OF SIGE HBTS

The revolution in wireless communications has been brought about by a combination of advances in digital integrated circuit technology, RF components, digital communications and networking techniques [79]. RF communication systems can be broadly categorized in two market sectors, namely, ‘low-end’ such as pagers, cordless phones etc, and ‘high-end’ such as personal communication service (PCS), GSM, IS-136 etc. SiGe HBTs are suitable for applications in the high-end applications where the best performance is essential, while CMOS technology will dominate the low-end applications. Several excellent reviews of research in wireless communications systems presently in use may be found in [32, 80, 81]. Figure 1.11 shows the present wireless system trends. The vertical axis is a measure of mobility, and the horizontal axis is the information rate. Analogue cellular systems are called ﬁrst generation systems, and the present digital cellular and digital cordless systems are called second generation systems. The third generation systems, however, only represent a midpoint in the planned development of mobile communication systems. Fourth generation systems will provide high bit rates of more than 2 Mbps under high mobility conditions. The sell-oﬀ of rights to the spectrum by the US Federal Communications Commission is creating a large market opportunity for SiGe in the USA, while the same trend is occurring elsewhere in the world. Components for PCS devices operating between 1.8–2.2 GHz are a fast growing market segment, along with pagers, beepers and wireless local area networks. The implementation of a complete RF integrated circuit on a single silicon chip is a complicated task, as wireless circuits have a very

22

Introduction

Figure 1.11. Wireless system trends. (After Muraguchi M 1999 Solid-State Electron. 43 1591–8.)

Figure 1.12. Selected high-frequency applications and allocated frequency bands between 1 and 100 GHz. The three market segments labelled communication, traﬃc and navigation will drastically expand in the next few years, mainly in the range up to about 10 GHz. (After Schaﬄer F 1998 Thin Solid Films 321 1–10.)

Applications of SiGe HBTs

23

broad range of requirements including noise ﬁgure, linearity, gain, phase noise and power dissipation. The advantages and disadvantages of each of the competing technologies Si CMOS, BJTs, Si/SiGe HBTs and GaAs MESFETs, HEMTs and HBTs have been examined by Larson in the light of these requirements [79]. Wireless communication systems require very high eﬃciency power ampliﬁers to extend battery life, simplify thermal design, and reduce the cost of handheld phones. In order to serve this new high volume market, faster and more powerful integrated circuit chips are required. For many of these applications, as shown in ﬁgure 1.12, all-silicon transistors have been pushed to the 1–2 GHz frequency domain. However, many new

Table 1.4. Summary of several circuits reported in the literature using SiGe HBT technology. Reference

Circuit type

Results

[10] [82]

Transceiver Limiting ampliﬁer

[83] [84]

Optical receiver Mixer

[85] [86]

Radio transceiver 6.25 GHz LNA

[87] [88] [88]

1.88 GHz power ampliﬁer ECL inverter chain 2.4 GHz downconverter (LNA + mixer)

[88]

Broadband amp

[89]

12 GHz VCO

[89]

12 GHz active mixer

[89] [90] [91] [92] [93]

12 GHz power amp 1/128 frequency divider RZ comparator Gilbert mixer 12-bit DAC

complete chip 60 dB Gain 55 dB dynamic range 10 Gb s−1 40 Gb s−1 analogue IC Conversion loss 6.5 dB, LO power 10 dBm 1/f noise corner frequency 3 kHz, 1 mA 900/1900 MHz, 2.7 V NF 2.2 dB, gain 20.4 dB Dissipation 9.4 mW, 2.5 V supply Power gain 16 dB, PAE 53% 16 ps/stage, 660 µA @ 3.3 V LNA: gain 10.5 dB NF 0.95 dB Mixer: +4 dBm input intercept 5 mA @ 1 V (total) Gain 8 dB Bandwidth 17 GHz 16.8 mA @ 2.5 V 19 dBm, 5% tuning range, −80 dBc Hz−1 phase noise >0 dB gain @ +3 dBm LO, 100 KHz IF BW, 30 dB isolation >6 dB gain, 19 dBm output 6.4–23 GHz, 1.5 W 5 GHz, 1.5 V, 89 mW Bandwidth 12 GHz GBW >22 GHz 1.2 Gsps, 750 mW

24

Introduction

RF applications require circuit operation at frequencies up to 30 GHz, a regime well out of the realm of devices based solely on Si. A number of circuit designs have been fabricated in SiGe technology in order to demonstrate its capability in the RF marketplace. Among the circuits that have been reported are: voltage controlled oscillators (VCOs), lownoise ampliﬁers (LNAs), power ampliﬁers (PAs), mixers and digital delay lines. Several reported circuit results are presented in table 1.4, and a more comprehensive survey is included in chapter 10. An exciting example of a communications application is the 10 Gbps data transmission system designed by Alcatel using advanced IBM SiGe technology [94]. In this system, SiGe technology has made a signiﬁcant contribution toward the implementation of a cost eﬀective transmission on a standard optical ﬁbre, oﬀering operators the advantage of upgrading their existing networks to terabit speed, without the time and cost of laying new cables. Table 1.5. List of devices available in the SiGe BiCMOS technology. The main characteristics are provided for each device which are available to the designers to make a full custom design. (After Brenner et al 1999 IBM MicroNews 5 1–4.) Device 1 npn 2 npn 3 n-FET 4 p-FET 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Gated lateral pnp Spiral inductor Varactor Schottky barrier diode Substrate contact Polysilicon resistor (RP) Polysilicon resistor (XN) Reach-through implant resistor (RN) n+ -subcollector resistor (RS) Ion implanted resistor (RI) Metal–insulator–metal capacitor Decoupling capacitor p–i–n diode ESD protective device

Parameter SiGe HBT fT = 47 GHz fmax = 65 GHz Higher breakdown SiGe HBT fT = 27 GHz, fmax = 55 GHz ID,sat = 485µA/µm Leﬀ min=0.39 µm ID,sat = 213µA/µm Leﬀ min=0.39 µm β = 107, VA = 67 V L = 10 nH, Q = 6 at 1 GHz 1.4 fF µm−2 Vf = 0.31 V @ 100 µA for 5 × 5 µm 330 Ωs (p+ subs.) for 2 × 10 µm 220 Ω/square 340 Ω/square 23.5 Ω/square 8 Ω/square 1750 Ω/square 0.7 fF µm−2 1.5 fF µm−2 6 Ω for a 2 × 10 µm 2000 V HBM

Summary

25

An excellent review of the application-driven origins of SiGe technology, how it has evolved and how the limitations of conventional silicon bipolar scaling have enhanced its adoption in the semiconductor industry, has been written by Meyerson [95]. This review demonstrates that SiGe HBTs are superior to Si BJTs and comparable to the best GaAs transistors and ideally suited for low-voltage and low-power wireless communication applications. In some aspects, such as low noise and low power consumption, SiGe HBTs have advantages over III–V HBTs, and approach the performance of some HEMTs, at least below 10 GHz. So far, Si BJT performance has been the main barrier for silicon to penetrate wireless RF front-ends. While SiGe HBTs have removed the barrier, RF isolation and system cost issues still remain. Since silicon substrates are conductive, it is not practical to build high-quality passive elements on-chip. However, much of the cost in current RF systems using discrete components comes from the passive elements. In addition to the SiGe HBT, recent progress in passive component design on silicon substrates, listed in table 1.5, now gives the RF designers a rich environment to realize applications for the wireless marketplace. 1.8.

SUMMARY

This introductory chapter has described the evolution of SiGe technology from early materials research to its current established position in the marketplace. The evolution of bipolar technology has led to the development and application of a SiGe transistor through utilization of strained layers. SiGe HBT technology has the potential to revolutionize high-frequency transceiver design in a way comparable to the revolution in digital integrated circuit technology brought about by CMOS. Its unique combination of outstanding high-frequency performance, low manufacturing cost and high yield will provide abundant opportunities for new architectures and new systems in the near future. Subsequent chapters in this book describe the basis of SiGe technology in much more detail. BIBLIOGRAPHY [1] Walker R C, Hsieh K-C, Knotts T A and Yen C-S 1998 A 10 Gb/s Si-bipolar TX/RX chipset for computer data transmission IEEE ISSCC Tech. Dig. pp 302–3 [2] Stoneham E B 1982 The search for the fastest three-terminal device Microwaves 55–60 [3] Ashburn P 1988 Design and Realization of Bipolar Transistors (Chichester: Wiley) [4] Patton G L, Bravman J C and Plummer J D 1986 Physics, technology

26

[5] [6] [7] [8]

[9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24]

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28

Introduction

[43] Oda K, Ohue E, Tanabe M, Shimamoto H, Onai T and Washio K 1997 130 GHz fT SiGe HBT technology IEEE IEDM Tech. Dig. pp 791–4 [44] Schuppen A, Erben U, Gruhle A, Kibbel H, Schumacher H and Konig U 1995 Enhanced SiGe heterojunction bipolar transistors with 160 GHz fmax IEEE IEDM Tech. Dig. pp 743–6 [45] Washio K, Kondo M, Ohue E, Oda K, Hayami R, Tanabe M, Shimamoto H and Harada T 1999 A 0.2 µm self-aligned SiGe HBT featuring 107 GHz fmax and 6.7 ps ECL IEEE IEDM Tech. Dig. pp 557–60 [46] Oda K, Ohue E, Tanabe M, Shimamoto H and Washio K 1999 DC and AC performances in selectively grown SiGe-base HBTs IEICE Trans. Electron. E82-C 2013–20 [47] Meister T F, Schafer H, Franosch M, Molzer W, Auﬁnger K, Scheler U, Walz C, Stolz M, Boguth S and Bock J 1995 SiGe-base bipolar technology with 74 GHz fmax and 11 ps gate delay IEEE IEDM Tech. Dig. pp 739–42 [48] Zerounian N, Aniel F, Adde R and Gruhle A 2000 SiGe heterojunction bipolar transistor with 213 GHz fT at 77 K Electron. Lett. 36 1076–8 [49] Lanzerotti L D, Sturm J C, Stach E, Hull R, Buyuklimanli T and Magee C 1997 Suppression of boron transient enhanced diﬀusion in SiGe heterojunction bipolar transistors by carbon incorporation Appl. Phys. Lett. 70 3125–7 [50] Osten H J, Heinemann B, Knoll D, Lippert G and Rucker H 1998 Eﬀects of carbon on boron diﬀusion in SiGe: principles and impact on bipolar devices J. Vac. Sci. Technol. B 16 1750–3 [51] Osten H J, Barth R, Fischer G, Heinemann B, Knoll D, Lippert G, R¨ ucker H, Schley P and R¨ opke W 1998 Carbon-containing group IV heterostructures on Si: properties and device applications Thin Solid Films 321 11–4 [52] Anteney I M, Lippert G, Ashburn P, Osten H J, Heinemann B, Parker G J and Knoll D 1998 Characterization of the eﬀectiveness of carbon incorporation in SiGe for the elimination of parasitic energy barriers in SiGe HBTs IEEE Electron Device Lett. 20 116–8 [53] Osten H J, Knoll D, Heinemann B, Rucker H and Tillack B 1999 Carbon-doped SiGe heterojunction bipolar transistors for high-frequency applications IEEE BCTM Tech. Dig. pp 109–16 [54] Lanzerotti L D, St Amour A, Liu C W, Sturm J C, Watanabe J K and Theodore N D 1996 Si/Si1−x−y Gex Cy /Si heterojunction bipolar transistors IEEE Electron Device Lett. 17 334–7 [55] Osten H J, Knoll D, Heinemann B and Tillack B 1998 Carbon doping of SiGe heterobipolar transistors Proc. Silicon Monolithic Integrated Circuits in RF Systems pp 19–23 [56] Osten H J, Knoll D, Heinemann B and Schley P 1999 Increasing process margin in SiGe heterojunction bipolar technology by adding carbon IEEE Trans. Electron Devices 46 1910–2 [57] Osten H J 1999 Carbon-Containing Layers on Silicon—Growth, Properties and Applications (Switzerland: Trans-Tech Publications) [58] Sadek A, Ismail K, Armstrong M A, Antoniadis D A and Stern F 1996 Design of Si/SiGe heterojunction complementary metal–oxide semiconductor transistors IEEE Trans. Electron Devices 43 1224–32 [59] Ismail K 1995 Si/SiGe high-speed ﬁeld-eﬀect transistors IEEE IEDM Tech.

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Dig. pp 509–12 [60] Welser J, Hoyt J L, Takagi S and Gibbons J F 1994 Strain dependence of the performance enhancement in strained-Si n-MOSFETs IEEE IEDM Tech. Dig. pp 373–6 [61] Nayak D K, Goto K, Yutani A, Murota J and Shiraki Y 1996 High-mobility strained-Si PMOSFETs IEEE Trans. Electron Devices 43 1709–15 [62] Maiti C K, Bera L K, Dey S S, Nayak D K and Chakrabarti N B 1997 Hole mobility enhancement in strained-Si p-MOSFETs under high vertical ﬁelds Solid-State Electron. 41 1863–9 [63] Hartmann R, Gennser U, Sigg H, Grutzmacher D and Dehlinger G 1999 Si/SiGeC heterostructures: a path towards high mobility channels Future Trends in Microelectronics—the Road Ahead (New York: Wiley Interscience) pp 133–42 [64] Quinones E J, John S, Ray S K and Banerjee S K 2000 Design, fabrication and analysis of SiGeC heterojunction PMOSFETs IEEE Trans. Electron Devices 47 1715–25 [65] Alieu J, Skotnicki T, Bouillon P, Regolini J L, Souﬁ A, Guillot G and Bremond G 1999 Potential of SiGe-channel MOSFETs for a submicron CMOS technology Future Trends in Microelectronics—the Road Ahead (New York: Wiley Interscience) pp 143–54 [66] Whall T E and Parker E H C 2000 SiGe heterostructures for CMOS technology Thin Solid Films 376 250–9 [67] Paul D J 1999 Silicon–germanium strained layer materials in microelectronics Adv. Mater. 11 191–204 [68] Collaert N and De Meyer K 1999 Modelling the short-channel threshold voltage of a novel vertical heterojunction pMOSFET IEEE Trans. Electron Devices 46 933–9 [69] Liu K C, Ray S K, Oswal S K and Banerjee S K 1998 A deep submicron Si1−x Gex /Si vertical PMOSFET fabricated by Ge ion implantation IEEE Electron Device Lett. 19 13–15 [70] De Meyer K, Caymax M, Collaert N, Loo R and Verheyen P 1998 The vertical heterojunction MOSFET Thin Solid Films 336 299–305 [71] Taft R C and Plummer J D 1992 Gex Si1−x /silicon inversion-base transistors: theory of operation IEEE Trans. Electron Devices 39 2108–18 [72] Taft R C, Plummer J D and Iyer S S 1989 Demonstration of a p-channel BICFET in the Gex Si1−x /Si system IEEE Electron Device Lett. 10 14–16 [73] Taft R C, Plummer J D and Iyer S S 1992 Gex Si1−x /silicon inversion-base transistors: experimental demonstration IEEE Trans. Electron Devices 39 2119–26 [74] Mierzwinski M E, Plummer J D, Croke E T, Iyer S S and Harrell M J 1992 AC characterization and modelling of the Gex Si1−x /Si BICFET IEEE IEDM Tech. Dig. pp 773–6 [75] Kasper E and Reitemann G 1999 Can silicon-based heterodevices compete with CMOS for system solutions? Future Trends in Microelectronics—the Road Ahead (New York: Wiley Interscience) pp 125–32 [76] Mastrapasqua M, King C A, Smith P R and Pinto M R 1996 Functional devices based on real space transfer in Si/SiGe structures IEEE Trans. Electron Devices 43 1671–7

30

Introduction

[77] Samavedam S B, Currie M T, Langdo T A and Fitzgerald E A 1998 Highquality germanium photodiodes integrated on silicon substrates using optimized relaxed graded buﬀers Appl. Phys. Lett. 73 2125–7 [78] Sieg R M, Ringel S A, Ting S M, Samavedam S B, Currie M, Langdo T and Fitzgerald E A 1998 Toward device-quality GaAs growth by molecular beam epitaxy on oﬀcut Ge/Si1−x Gex /Si substrates J. Vac. Sci. Technol. B 16 1471–4 [79] Larson L E 1998 Integrated circuit technology options for RFICs—present status and future directions IEEE J. Solid-State Circuits 33 387–99 [80] Abidi A A 1995 Direct-conversion radio transceivers for digital communications IEEE J. Solid-State Circuits 30 1399–410 [81] Rudell J C, Ou J-J, Cho T B, Chien G, Brianti F, Weldon J A and Gray P 1997 A 1.9 GHz wide-band IF double conversion CMOS receiver for cordless telephone applications IEEE J. Solid-State Circuits 32 2071–87 [82] Greshishchev Y M and Schvan P 1999 A 60 dB gain 55 dB dynamic range 10 Gb/s broadband SiGe HBT limiting ampliﬁer IEEE ISSCC Tech. Dig. pp 382–3 [83] Masuda T, Ohhata K, Oda K, Tanabe M, Shimamoto H, Onai T and Washio K 1998 40 Gb/s analog IC chipset for optical receiver using SiGe HBTs IEEE ISSCC Tech. Dig. pp 314–15 [84] Strohm K M, Luy J-F, Hackbarth T and Kosslowski S 1998 MOTT SiGe SIMMWICs IEEE MTT-S Dig. pp 1691–4 [85] Sevenhans J, Verstraeten B, Fletcher G, Dietrich H, Rabe W, Bacq J L, Varin J and Dulongpont J 1998 Silicon germanium and silicon bipolar RF circuits for 2.7 V single chip radio transceiver integration IEEE CICC Proc. pp 409–12 [86] Ainspan H, Soyuer M, Plouchart J-O and Burghartz J 1997 A 6.25 GHz low DC power low-noise ampliﬁer in SiGe IEEE CICC Proc. pp 177–80 [87] Henderson G N, O’Keefe M F, Boles T E, Noonan P, Sledziewski J M and Brown B M 1997 SiGe bipolar junction transistors for microwave power applications IEEE MTT-S Dig. pp 1299–1302 [88] Long J R, Copeland M A, Kovacic S J, Malhi D S and Harame D L 1996 RF analogue and digital circuits in SiGe technology IEEE ISSCC Tech. Dig. pp 82–3 [89] Larson L, Case M, Rosenbaum S, Rensch D, Macdonald P, Matloubian M, Chen M, Harame D, Malinowski J, Meyerson B, Gilbert M and Maas S 1996 Si/SiGe HBT technology for low-cost monolithic microwave integrated circuits IEEE ISSCC Tech. Dig. pp 80–1 [90] Case M, Knorr S, Larson L, Rensch D, Harame D, Meyerson B and Rosenbaum S 1995 A 23 GHz static 1/128 frequency divider implemented in a manufacturable Si/SiGe HBT process IEEE BCTM Proc. pp 121–4 [91] Gao W, Snelgrove W M, Varelas T, Kovacic S J and Harame D L 1995 A 5 GHz SiGe HBT return-to-zero comparator IEEE BCTM Proc. pp 166–9 [92] Glenn J, Case M, Harame D and Meyerson B 1995 12 GHz Gilbert mixers using a manufacturable Si/SiGe epitaxial-base bipolar technology IEEE BCTM Proc. pp 186–9 [93] Harame D L, Schonenberg K, Gilbert M, Nguyen-Ngoc D, Malinowski J, Jeng S-J, Meyerson B S, Cressler J D, Groves R, Berg G, Tallman K,

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Stein K, Hueckel G, Kermarrec C, Tice T, Fitzgibbons G, Walter K, Colavito D and Houghton D 1994 A 200 mm SiGe HBT technology for wireless and mixed-signal applications IEEE IEDM Tech. Dig. pp 437–40 [94] Brenner T, Wedding B and Coene B 1999 Alcatel’s revolutionary 10 Gbps transmission system enabled by IBM’s SiGe high-speed technology IBM MicroNews 5 1–4 [95] Meyerson B S 2000 Silicon:germanium-based mixed-signal technology for optimization of wired and wireless telecommunications IBM J. Res. Dev. 44 391–407

Chapter 2 FILM GROWTH AND MATERIAL PARAMETERS

Silicon-based heterostructures have come a long way from the use of strain as a parameter for bandgap engineering, to the present state of devices/circuits with enhanced performance compared to those obtained in bulk-Si and competing III–V compound semiconductors. Apart from the inherent performance enhancement, undoubtedly the main attraction of high mobility Si/SiGe, SiGe/strained-Si and Si/SiGeC heterostructures is their basic compatibility with standard Si processing. For any material, issues important to the device designer include bandgap diﬀerence, band alignments and mobility. The ﬁrst two properties determine the class of devices that can be fabricated. For example, quantum conﬁnement of electrons cannot occur without a conduction band discontinuity. It is the purpose of this chapter to consider the recent developments in growth techniques and the performance levels achieved to date in group IV alloy systems, to address the problems related with ﬁlm development and process integration and to discuss alternative routes that could circumvent the use of strain adjusting epilayers, which are presently the bottleneck for an introduction of these promising materials (such as strained-Si and SiGeC) into a production environment. We shall discuss various growth and doping techniques and strain-induced material properties of diﬀerent group IV alloy layers. The electronic properties of Si/SiGe, Si/SiGeC and strained-Si ﬁlms will be presented. Semiconductor heterostructure devices rely on the diﬀerences in the electronic bandstructure of the two semiconductors used to fabricate a device. In the beginning of heterostructure devices, the emphasis was on ﬁnding a pair of semiconductors with diﬀerent bandgaps but with nearly the same lattice constants. This was necessary so that a good epilayer of one semiconductor could be grown on the other. In lattice matched heterostructures, one can obtain an interface of high quality without 32

Strained layer epitaxy

33

defects, so that as a free carrier approaches a heterostructure boundary, it would be inﬂuenced only by the potential gradients and is not trapped or artiﬁcially scattered at the heterostructure boundary. Heterostructures based on column III–V and II–VI compound semiconductors, such as AlAs and GaAs, can be easily fabricated since there are direct structural and chemical matches among these semiconductors. On the other hand, for silicon-based heterostructures this is not the case as silicon has no natural semiconductor partner with respect to the conﬁguration of its atomic lattice and chemistry, although silicon and germanium are completely miscible over the entire compositional range and give rise to alloys with a diamond crystal structure. At room temperature, the lattice constants for silicon and germanium are 5.43 ˚ A and 5.65 ˚ A, respectively, leading to a 4.2% lattice mismatch. Clearly, the large mismatch between silicon and germanium precludes depositing epitaxial germanium directly on silicon. The miscibility of silicon and germanium, however, allows deposition of epitaxial Si1−x Gex , without adhering to stoichiometric ratios, on silicon. As a result, the lattice mismatch between silicon and Si1−x Gex is lessened. Because a signiﬁcant lattice mismatch still exists, Si1−x Gex on silicon can range from a fully strained to a fully relaxed state. Normal heterostructures of Si and Ge thus grow with high dislocation densities that were believed to be incompatible with most device applications. In the early 1980s, however, the situation changed when it was demonstrated that by utilizing strained layer epitaxy, defects could be eliminated in thin silicon-based heterostructures. In strained alloys of Si and Ge, Si1−x Gex , it was found that heterostructure eﬀects were much stronger than expected, making them very attractive for device applications. 2.1.

STRAINED LAYER EPITAXY

Before we discuss the deposition and properties of strained layers, we brieﬂy discuss the properties of the relevant bulk materials as given in table 2.1. Ge has been known to be produced with extremely poor impurity concentrations and large mobilities with both p- and n-type conductivity. Both the n- and p-type high-quality Ge samples exhibit mobilities of about 2 000 000 cm2 V−1 s−1 at about 4 K. On the other hand, high-purity Si exhibits electron mobilities slightly in excess of 500 000 cm2 V−1 s−1 at 4 K. As the atomic spacing of germanium is 4.2% larger than that of silicon, when the ﬁrst few atomic layers of Ge are deposited, it is energetically desirable that they maintain full bonding with the silicon by compressing together. In the fully strained case, the larger Si1−x Gex horizontal lattice compresses to match the silicon substrate and the Si1−x Gex vertical lattice constant expands to accommodate the horizontal compression as shown

34

Film growth and material parameters

Table 2.1. Room-temperature materials data of selected group IV elements. Element Lattice Lattice constant, ao (˚ A) Density, g cm−3 TCE, α (10−6 K−1 ) Bandgap, Eg (eV) Dielectric constant, Electron mobility, µe (cm2 V−1 s−1 ) Hole mobility, µh (cm2 V−1 s−1 ) Eﬀective mass m∗ Electron, m∗e (⊥) Electron, m∗e () Light-hole, m∗h (l) Heavy-hole, m∗h (h)

C Diamond 3.5668 3.515 1.0 5.48 5.7

Si Diamond 5.431 2.329 2.56 1.11 11.9

Ge Diamond 5.657 5.323 5.9 0.664 16.2

α–Sn Diamond 6.489 7.285 4.7 – 24

1800

1450

3900

1400

1600

450

1900

1200

– – 0.7 2.18

0.19 0.92 0.15 0.54

0.08 0.64 0.043 0.28–0.38

0.024 0.2–0.45 – –

Figure 2.1. A schematic diagram of strained-Si1−x Gex crystal lattices illustrating two types of strain. In both cases, the epitaxial ﬁlm is constrained by the substrate along two axes, as indicated by the arrows.

in ﬁgure 2.1. The higher energy state of strained-Si1−x Gex is sustained because the activation energy for the dislocation formation has not been reached. Since the Si substrate lattice is both much thicker and stiﬀer, it remains essentially undistorted. The growth of Si1−x Gex on silicon begins as a strained layer, but when the thickness or germanium concentration of the layer exceeds a critical value, the layer relaxes. Since the lattice

Strained layer epitaxy

35

Figure 2.2. Lattice constant for an Si1−x Gex alloy as a function of x. Vegard’s law is a linear interpolation between aSi and aGe .

constants of Si1−x Gex alloys are larger than that of Si, pseudomorphic Si1−x Gex layers grown on silicon have biaxial in-plane compression of the alloy and an extension normal to the interface. If layers are grown on a germanium substrate the reverse is the case. In both cases the layers suﬀer a tetragonal distortion. In fully relaxed Si1−x Gex on silicon, the lattice constant returns to the bulk value. The lattice constants of bulk-Si1−x Gex alloys have been measured and the results obey Vegard’s law to a very good approximation. Assuming Vegard’s law applies, the bulk-Si1−x Gex lattice constant (aSi1−x Gex ) is a function of the silicon and germanium lattice constants (aSi and aGe ) and the mole fraction of germanium, x in equation (2.1). The lattice constant of Si1−x Gex alloys varies linearly, as shown in ﬁgure 2.2 obeying Vegard’s rule: a(Si1−x Gex ) = aSi + x(aGe − aSi ).

(2.1)

Due to the relatively large lattice mismatch between SiGe and silicon, commensurate (defect-free) SiGe alloy ﬁlms cannot be grown on silicon substrates without introducing large amounts of strain. As the thickness of the SiGe layer increases, so does the integrated strain energy and at some point this conﬁguration will reach a thickness, which is known as the ‘critical layer thickness’, beyond which the total energy becomes larger and results in ‘misﬁt dislocations’ or periodic arrays of incompletely bonded atom rows. Misﬁt or threading dislocations appear at the interface in both the relaxed and partially relaxed cases. Threading dislocations aﬀect the heterojunction by acting as a pathway for enhanced

36

Film growth and material parameters

dopant diﬀusion. This leads to increased junction leakage current. Misﬁt dislocations located inside a heterojunction depletion region result in an increased space-charge layer recombination and generation current. For most device applications, dislocations are deleterious and should be avoided. Since the dangling bond can become a trap or leakage site, such dislocations must be avoided within the active volume of a heterostructure device. This implies that active device areas must not lie at the interface of the Si1−x Gex and Si layers. This is possible in certain devices but, unfortunately, there are also segments of dislocations that thread from the heterostructure interface up to the surface of the crystal. A number of strategies have been suggested to minimize the impact of such threading dislocations [1]. The ﬁrst possibility is extending the dislocation plane either to the edge of the wafer or at least to the boundary of a device die where threading dislocations would be irrelevant. Alternating thin layers can also be grown so that dislocations do not form and instead the atomic spacings of one or both materials shift to accommodate one another. This occurs naturally in very thin layers (e.g., 10–100 atoms thick) and can persist in much thicker layers (100–1000 layers) if a low-temperature growth technique is used, where dislocations do not have enough energy to form and grow. In some recent applications, however, the use of thick relaxed-Si1−x Gex layers as a starting substrate for strained silicon (strained-Si) deposition has been made. Relaxed-Si1−x Gex layers can be grown thick enough to cause threading dislocations to loop around. As a result, the surface is nearly defect-free. Alternating layers of silicon and Si1−x Gex may also be used to ﬁlter out threading dislocations. Contrary to the simplistic view given above, the transition from the strained to the relaxed case is not abrupt and is not clearly deﬁned. Varying degrees of strain relaxation can exist [2]. Figure 2.3 shows three regimes (stable, metastable and relaxed) in the plot of Si1−x Gex layer thickness on silicon versus germanium mole fraction. The germanium concentration is directly related to the lattice mismatch according to Vegard’s law. The term ‘critical thickness’ was initially deﬁned to denote the transition from a strained to a relaxed-Si1−x Gex layer. Van der Merwe [3, 4] calculated the critical thickness as a function of increased lattice mismatch, by minimizing the sum of the interfacial and strain energy. However, most of the published literature accepted the mechanical equilibrium theory of Matthews and Blakeslee [5, 6] as deﬁning the transition from the stable to metastable regimes. Mechanical equilibrium theory assumes the existence of a threading dislocation. The energy required to glide a threading dislocation into a misﬁt dislocation is balanced with the strain energy from the lattice mismatch to deﬁne the critical thickness as a function of lattice mismatch. When the strain energy exceeds the misﬁt dislocation forms to

Strained layer epitaxy

37

Figure 2.3. Critical layer thickness versus Ge content showing stable, metastable and relaxed ranges of Si1−x Gex layers on Si. (After Schuppen A et al 1995 J. Mater. Sci., Mater. Electron. 6 298–305.)

relieve the strain energy. A simpliﬁed Matthews–Blakeslee critical thickness calculation (hc ) where angular dependences have been ignored [7], is given by equation (2.2) b hc 1 ln +1 (2.2) hc f 4π(1 + ν) b where ν is Poisson’s ratio (0.3), b is the slip distance (0.4 nm), f is the mismatch between the ﬁlm and substrate and for Si1−x Gex on silicon, f is 0.042x. For a detailed derivation of the critical thickness, the reader may refer to an excellent review by Jain and Hayes [8]. Although the Matthews–Blakeslee equilibrium theory is widely cited, strained-Si1−x Gex layers have been deposited much thicker than the theory predicts. Bean et al [9] deposited strained layers by molecular beam epitaxy at 550 ◦ C with the thickness an order of magnitude or more above the Matthews–Blakeslee curve, as shown by the solid curve in ﬁgure 2.3. The dashed curve demarcates the metastable and dislocation regimes. Above the dashed curve, strained-Si1−x Gex layers were impossible to deposit. Between the solid mechanical equilibrium curve and the dashed curve, the layers are labelled metastable. Layers in the metastable regime are

38

Film growth and material parameters

strained, even though the layers are above the Matthews–Blakeslee critical thickness. However, metastable layers relax with subsequent annealing. People and Bean sought to reconcile these diﬀerences by including the kinetics of relaxation in their calculation [10]. Their critical thickness prediction ﬁts their data, but their theory has not been widely accepted by other researchers. Many other researchers have also contributed with critical thickness theories based on energy, mechanical equilibrium and kinetics of dislocations [11–13]. The critical thickness theories based on dislocation formation are disputed by some researchers because other factors, such as wafer preparation and particulate contamination, may play a much larger role in determining misﬁt dislocations [14]. Furthermore, methods for determining whether a layer is strained or relaxed may not have enough sensitivity to detect the onset of dislocation formation [15]. As a result, dislocation techniques with poor resolution overestimate the critical thickness. Determination of the critical thickness curve depends on the deposition methods and characterization methods used. Nonetheless, most researchers concur that the Matthews–Blakeslee equilibrium curve distinguishes the point where strained-Si1−x Gex layers cannot sustain extended thermal processing. When a thin ﬁlm with a larger lattice constant (e.g., Si1−x Gex ) is grown on a smaller lattice constant substrate (e.g., silicon), the ﬁlm maintains an in-plane lattice constant of the substrate and is under a biaxially compressive strain. Since layer sequences with well-deﬁned electrical and optical properties require coherence of the in-plane lattice constant, biaxial strain is always present in such heterostructures. This asymmetry of the strain with respect to the (001) growth direction leads to a splitting of the sixfold degenerate conduction band and also of the heavy-hole/light-hole valence band degeneracy. The band ordering in this heterosystem is therefore strongly strain dependent, and a type I band alignment is obtained where the entire band oﬀset occurs in the valence band (ﬁgure 2.4(a)) while the band oﬀset in the conduction band is very small. This type of structure is favourable for hole conﬁnement and has been exploited in several novel heterostructure devices, namely buried channel p-MOSFETs, p-MODFETs and HBTs (see for example, a review by Konig and Daembkes [16]). Similarly, a smaller lattice constant silicon epilayer (strained-Si) will be under biaxial tension when grown on a larger lattice constant relaxedSi1−x Gex substrate. In this case, type II band oﬀset occurs (ﬁgure 2.4(b)) and the structure has several advantages over the more common type I band alignment. A large band oﬀset is obtained in both the conduction and valence bands, relative to the relaxed-Si1−x Gex layer [7]. This allows both electron and hole conﬁnements in the strained-Si layer, making it useful for both n- and p-type devices for strained-Si/SiGe-based CMOS technology. The ability to achieve both n-MOS and p-MOS devices

Strained layer epitaxy

39

Figure 2.4. Band alignments for (a) Si0.8 Ge0.2 on (001)Si, (b) strained-Si on (100)Si0.8 Ge0.2 and (c) Si0.6 Ge0.4 /Si heterostructure on (001)Si0.8 Ge0.2 substrates.

using strained-Si provides a promising alternative for next generation high-performance SiGe CMOS technology (see for example, reviews by Maiti et al [17] and Schaﬄer [18] and references therein). Since strainedSi provides both larger conduction and valence band oﬀsets and does not suﬀer from alloy scattering, a signiﬁcant improvement in carrier mobility can be achieved. However, strained-Si is more diﬃcult to grow compared to strained-Si1−x Gex , as the growth of thick relaxed-Si1−x Gex is diﬃcult without forming a large concentration of defects due to dislocation, and a total thickness of several microns leads to non-planarity, high defect density and surface roughness.

40

Film growth and material parameters

To fully exploit strain as an additional parameter for bandgap engineering, it is necessary to have substrates available that provide the desired in-plane lattice constant for the subsequent pseudomorphic layers. For this purpose, strain-relaxed SiGe buﬀer layers on an Si substrate are used. In an eﬀort to extend the Si1−x Gex strained layer technology and to search for new materials, experimental work on Si1−x Cx and Si1−x−y Gex Cy alloys was started in the early 1990s and recently on Ge1−y Cy alloys. A diﬀerent concept for strain adjustment has been suggested by adding carbon into the Si/SiGe material system [19, 20] indicating that the addition of carbon is a promising way for new relaxed buﬀer concepts with low threading dislocation densities. As the lattice parameter of carbon (3.546 ˚ A) is much smaller than that of Si and Ge, C may be used as a substitutional impurity in the SiGe to decrease the lattice mismatch of the SiGe system. In the case of a ternary alloy such as Si1−x−y Gex Cy , assuming Vegard’s law and for a fully relaxed ﬁlm, the lattice parameter can be written as aSiGeC = aSi + x (aGe − aSi ) + y(aC − aSi )

(2.3)

where ai is the lattice parameter of the ith component. The third term being negative, it is possible to adjust composition of the alloy to cancel the second and third term leading to an alloy with exactly the Si lattice parameter (i.e., zero net strain). According to equation (2.3), for about 12% Ge in Si and 1% C in silicon, the mismatch is equal and opposite and a strain symmetrized structure with average zero strain may be obtained. Addition of substitutional carbon to the Si1−x Gex material system can provide an additional design parameter in band structure engineering on Si substrates. Since large bandgap variations from 5.5 eV (diamond) to 0.66 eV (Ge) exist, the Si1−x−y Gex Cy system may result in an increase in the bandgap to values greater than those of SiGe and Si, in addition to other interesting properties such as the highest known thermal conductivity (diamond), high hole mobility (Ge) and matured processing technology (Si). The incorporation of C, however, presents diﬃcult challenges due to the large lattice mismatch between C and Si, low solubility of carbon in Si and silicon carbide precipitation. Attempts have been made to form strained layers on Si or Ge substrates containing Sn as a constituent. Synthesis of dislocation-free Siy (Snx C1−x )1−y [21] and growth of quaternary Si1−x−y−z Gex Cy Snz alloy have also been announced [22]. For the last few years, experimental studies on strained-SiGe materials have resulted in a signiﬁcant progress in the understanding of strain relaxation kinetics and optimization of graded buﬀer layers with respect to relaxation and surface morphology [23–27]. These parameters are of crucial importance as they are interdependent and are aﬀected by growth temperature, grading rate and composition. It appears that the competition between dislocation nucleation and propagation determines

Strained layer epitaxy

41

Figure 2.5. Cross-sectional transmission electron micrograph and secondary ion mass spectrometry proﬁle of a graded SiGe buﬀer layer on an Si substrate. (After Schaﬄer F 1998 Thin Solid Films 321 1–10.)

the ﬁnal threading dislocation density in the ﬁlm. The compositional grading is believed to promote propagation while suppressing nucleation of dislocations and leading to reduced amounts of surface strain, thus allowing higher growth temperature [28,29]. Figure 2.5 shows the secondary ion mass spectrometry (SIMS) proﬁle together with a cross-sectional transmission electron micrograph (TEM) micrograph of a graded SiGe buﬀer layer grown at 750 ◦ C by MBE. It is interesting to note that, close to the substrate interface, the misﬁt dislocation segments appear quite irregular with respect to spacing and length, whereas long-stretched misﬁts can be observed in the upper part of B1. B2 remains free of misﬁt dislocations, as expected, because once B1 is fully relaxed, B2 becomes

42

Film growth and material parameters

strain-free. In fact, the use of a compositionally graded, relaxed, Si1−x Gex buﬀer layer has been advocated as ‘virtual substrate’ and allows the strain in the ﬁlm to be tailored at will. (For a detailed discussion on strain adjustment in SiGe buﬀer layers see, for example, excellent reviews by Schaﬄer [18, 30].) In the following sections, we discuss the technology of growth of SiGe, SiGeC and strained-Si ﬁlms. Only a brief review is given for wellestablished results, and readers are referred to the original publications for more detail. We shall examine the deposition of heteroepitaxial ﬁlms using various reactors in greater depth. As the reactor conﬁgurations diﬀer substantially, the advantages and disadvantages of each system are also compared. For a detailed discussion, the reader may refer to a review by Maiti et al [31]. 2.2.

DEPOSITION TECHNIQUES

Many methods exist for depositing low-temperature silicon and Si1−x Gex on silicon. These can be broadly categorized into physical deposition and chemical vapour deposition (CVD) methods. To cope with the diﬃculties of growing SiGe alloys, molecular beam epitaxy was used at ﬁrst to produce thin, device quality ﬁlms. MBE is a physical vapour deposition method and is mostly used for the deposition of III–V compound semiconductors because of the excellent control of layers. Pioneering studies in the mid1980s at AT&T Bell Laboratories, IBM Thomas J Watson Research Center and Daimler–Benz Research Laboratories, Germany, British Telecom, UK, Hitachi and NEC, Japan, among others, used molecular beam epitaxy to show that SiGe alloys could be bandgap-engineered controllably and successfully used to realize a host of novel electronic and photonic devices. MBE allows the fabrication of moderately defect-free heterojunctions. However, MBE not being a production tool, they are only used for demonstration devices. On the CVD side, Gibbons et al [32] at Stanford were one of the ﬁrst groups to demonstrate high-quality Si1−x Gex on silicon. Towards commercialization of SiGe technology, the development of UHVCVD by Meyerson et al [33] at IBM has been a key step forward which appeared at nearly the same time in the mid-1980s as limited reaction processing CVD (LRPCVD). The UHVCVD reactor combines a standard diﬀusion furnace with an ultrahigh vacuum and has made the most signiﬁcant impact in the fabrication of Si/Si1−x Gex HBTs. An excellent review of this technique, and of the devices fabricated using this method of growth, has been published [34]. Other CVD techniques have also been used to grow device quality SiGe layers [35]. Results of Si1−x Gex ﬁlm depositions at atmospheric pressure CVD by ASM, the only commercial entry in the late 1980s, have been published. These atmospheric CVD results may

Deposition techniques

43

be the most promising for widespread application of Si1−x Gex on silicon heterostructures in a production environment. In the following, we brieﬂy discuss several reactors, the wafer cleaning method, reactor kinetics such as Ge incorporation control, dopant control and selective deposition, and compare the performances of various reactors. Focus is placed on systems that have successfully demonstrated devices and the discussion of the reactors proceeds in order of increasing base pressure. 2.2.1.

Wafer cleaning

Perhaps the most important issue in silicon-based heteroepitaxy is wafer preparation and in situ cleaning prior to epitaxial growth. Poor surface cleaning results in defects at the epitaxial interface that are independent of the lattice mismatch between Si and Si1−x Gex . Conventional silicon homoepitaxial reactors use an in situ high-temperature hydrogen or hydrogen chloride (HCl) ambient to ensure that the surface is free of oxide prior to epitaxial growth. Several approaches to the cleaning problem have been made in the low-temperature deposition of Si1−x Gex on silicon: retaining the high-temperature step and using an ultrahigh vacuum to desorb oxide; using a lamp-heated system to rapidly change from the cleaning temperature to the deposition temperature; using ion bombardment to physically remove the oxide; or using the unique properties of silicon wafers after dipping in liquid hydroﬂuoric (HF) acid for an H2 -terminated surface. Carbon and oxygen contamination is a common problem in epitaxy. Having a very low base pressure reduces the oxygen and carbon contamination and prevents the formation of a native oxide. Using a load-lock during the wafer load and unload is an additional method of keeping the deposition chamber free of oxygen and carbon from the atmosphere. In silicon homoepitaxy, emphasis is placed on obtaining a high growth rate for high throughput and reducing the autodoping from deposition. In low-temperature silicon and Si1−x Gex epitaxy, autodoping is not a problem and desired layer thicknesses are of the order of 100 nm or less. Precise control of the germanium and dopant concentration proﬁles becomes more important than high growth rates. Certain device applications need bandgap grading, so Ge incorporation control down to 1–2% is desirable. High and moderate levels of dopants of both types are needed to form diﬀerent device structures. Quick transitions from high to low and low to high dopant and Ge concentrations are also desired for the formation of lightly-doped spacers for modulation-doped structures. Control of in situ doping proﬁles down to 50 nm and formation of dopant proﬁles with peaks below the surface are extremely important for precise vertical dopant proﬁles and lower junction capacitance. As ion implantation cannot produce these types of proﬁles, in situ doping is a necessity.

44

Film growth and material parameters

For CVD techniques, gas chemistry and gas purity are very important issues. Silane (SiH4 ) is more reactive than dichlorosilane (SiH2 Cl2 ), so a lower deposition temperature is possible. Even lower deposition temperatures can be achieved by using disilane (Si2 H6 ). 2.2.2.

Molecular beam epitaxy

Molecular beam epitaxy is the growth technique most widely used to grow pseudomorphic Si1−x Gex layers on Si. This is a growth technique where the thermally evaporated molecules of the desired species impinge on an atomically clean heated substrate to form a crystalline solid. The growth technique is intrinsically clean due to UHV growth environment (base pressure ∼10−11 Torr). Cryopumps provide an oil-free evacuation system. MBE is specially suited for the growth of heterostructures requiring precise control of alloy composition, layer thickness and doping. The main characteristics of the MBE growth technique are as follows: • • • • •

very low growth pressure (∼10−9 Torr) allowing atomic layer by layer growth on a atomically clean surface; low growth temperature (350–600 ◦ C) which minimizes solid state diﬀusion and autodoping; slow growth rate (0.1–5 ˚ A s−1 ) which permits atomically thin-layer growth and better uniformity; multilayer growth capability that allows growth of quantum well and superlattice structures; in situ surface analysis capability such as high-energy electron diﬀraction (RHEED), Auger electron spectroscopy (AES) and x-ray photoelectron spectroscopy (XPS).

Most MBE systems retain some type of high-temperature cleaning or anneal cycle. The resistively heated substrate can be lowered to the deposition temperature without worry of surface recontamination because of the very low partial pressures of oxygen and carbon in the process chamber. Argon sputter cleaning has been used to etch 10 nm from the surface of the wafer. The etch is followed by a 850 ◦ C anneal before lowering down to the deposition temperature, between 500–750 ◦ C. But sputter cleaning leads to degradation in the minority carrier lifetime by heavy metal contamination sputtered from the chamber onto the surface of the wafer [36]. Because of the UHV conditions, medium temperature (<850 ◦ C) bakeouts are suﬃcient to cause native oxide and other contaminants to desorb from the surface of the wafer [37]. The success of using HF dips as a cleaning method in UHVCVD has also spread to MBE, allowing silicon homoepitaxy at a temperature down to 370 ◦ C without any hightemperature anneals [38].

Deposition techniques

45

Molten pools of extremely pure elemental sources such as silicon and germanium at the base of the MBE apparatus provide a source of atoms, with beams of these atoms directed at the substrate to produce the desired ﬁlm. The atoms strike the silicon substrate and accumulate in a crystalline manner (epitaxial growth). The deposition kinetics are simple in MBE, since a chemical reaction does not take place. The heated substrate provides the surface mobility necessary to epitaxially align the impinging molecules. Deposition rate is controlled by the ﬂux of the evaporated molecules and the substrate temperature. Deposition rates of up to 600 nm min−1 for silicon are possible. However, typical Si1−x Gex deposition rates are in the 30 nm min−1 range for greater proﬁle control [39]. Also, extremely abrupt compositional proﬁle control is possible by the use of mechanical shutters. To minimize the strain that results from lattice mismatch, generally SiGe alloys layers containing less than 30% Ge are grown. Bean et al [39] found that the maximum germanium incorporation before the occurrence of non-planar growth depends on the deposition temperature, as shown in ﬁgure 2.6. At 750 ◦ C, the maximum germanium mole fraction is 10%, whereas at 550 ◦ C 100% germanium is possible [9,39].

Figure 2.6. Temperature dependence for planar Si1−x Gex growth as a function of Ge concentration. It is noted that for the Ge fraction more than 0.5, the growth temperature must be lower than 550◦ C.

46

Film growth and material parameters

A limited range of dopant incorporation by coevaporation is possible in MBE, speciﬁcally for n-type dopants, because of low sticking coeﬃcients of Sb and As and surface segregation. Low-energy implantation during deposition may solve these problems, but increases the complexity and the cost of MBE. Wafer uniformity is another limitation. Rotating the substrate partially circumvents the problem, but large wafers (>125 mm) may present an insurmountable problem from a uniformity stand point. The inability to in situ dope n-type dopants and to deposit selective layers has been surmounted by using gas source MBE (GSMBE) [37, 40–42]. In GSMBE, Si2 H6 , germane (GeH4 ), diborane (B2 H6 ) and phosphine (PH3 ) are introduced into the deposition chamber instead of evaporating elemental sources. The deposition is controlled by the chemical reaction of the gaseous radicals at the surface of a heated wafer. GSMBE may be described as a hybrid MBE/CVD system, but the deposition pressure is an order of magnitude or more below other CVD systems. At these deposition pressures, gas phase equilibrium may not be achieved, so standard CVD kinetics may not apply. 2.2.3.

UHVCVD

Chemical vapour deposition systems utilize precursor gases that incorporate the desired atoms to the substrate surface. This technique, which has been well known for decades, is in many ways simpler than MBE. CVD is the most advantageous process because it is a high throughput process and also it has in situ doping capabilities. An ultrahigh vacuum chemical vapour deposition reactor consists of a diﬀusion furnace under ultrahigh vacuum, as shown in ﬁgure 2.7. Since the base pressure is comparable to MBE at 10−9 Torr, the advantages of low contamination

Figure 2.7. A schematic cross section of a UHVCVD reactor.

Deposition techniques

47

and prevention of native oxide after loading are similar to MBE. UHVCVD does not use an in situ cleaning step, but relies on the passivation of the surface immediately after an HF dip [43]. A load-lock is also used to prevent exposing the deposition chamber to the atmosphere. The gases SiH4 , GeH4 , B2 H6 and PH3 provide the sources for CVD of p-type and n-type silicon and Si1−x Gex . The deposition pressure is about 1–2 mTorr, with deposition rates around 1–2 nm min−1 . The control of the wafer temperature in a diﬀusion furnace is extremely good. As a result, a surface rate-limited reaction results in a very uniform layer.

2.2.4.

LRPCVD and RTCVD

Limited reaction processing CVD for silicon homoepitaxy and Si1−x Gex heteroepitaxy was ﬁrst developed at Stanford University. The unique feature of this system is that the surface reaction is temperature driven, and the temperature of the substrate acts as a switch either to initiate a reaction, terminate a reaction or to change the reaction rate. This technique employs rapid isothermal processing, and the temperature of the substrate (hence the reaction rate) can be rapidly varied (as fast as 350 ◦ C s−1 ). In this system, the base pressure is about 1 mTorr and the gas ﬂows are established at low temperature. Typical gases used include SiH2 Cl2 , GeH4 , B2 H6 , AsH3 and PH3 as source gases. The lamps are turned on to raise the substrate temperature and initiate the deposition, hence the terminology limited reaction processing. As a result of the rapid temperature transitions, the high-temperature in situ cleaning step occurs with hydrogen or hydrogen chloride in a short time, thus reducing the total thermal budget compared to commercial epitaxial deposition systems. Many other research groups have used similar conﬁgurations and have adopted the name rapid thermal chemical vapour deposition (RTCVD) instead of LRPCVD because they use gas switching rather than lamp heating to control the reaction. However, rapid doping and compositional transitions are possible by using the lamps as a thermal switch to control the reaction. In situ doping and selective silicon and Si1−x Gex heteroepitaxy have been demonstrated. Si1−x Gex layers need to be deposited at a lower temperature to avoid relaxation and three-dimensional growth problems. The deposition temperature used for Si1−x Gex is about 625 ◦ C and is increased to 850 ◦ C for silicon cap layer deposition, if required. One of the major problems with reducing the temperature, however, is increased oxygen incorporation in the Si1−x Gex layers. The oxygen incorporation problem may be reduced with the use of a load-lock and point-of-use ﬁltration of SiH2 Cl2 .

48 2.2.5.

Film growth and material parameters Very low pressure CVD

The very low pressure CVD (VLPCVD) deposition tool follows the more conventional CVD method with some diﬀerences and was ﬁrst developed at MIT. The deposition chamber is a quartz tube evacuated by a turbopump to a base pressure of 10−8 Torr when cold. The susceptor and wafer are heated by a bank of quartz halogen infrared lamps up to a temperature of 800 ◦ C. The base pressure increases to about 10−7 Torr when the chamber is heated to 800 ◦ C. Process gases during deposition include silane (SiH4 ), germane (GeH4 ), diborane (B2 H6 ), arsine (AsH3 ) and phosphine (PH3 ) as the semiconductor and dopant gas sources. Unlike MBE or UHVCVD, the base pressure in VLPCVD is not low enough to prevent the formation of oxide in the reaction chamber. Therefore, in situ plasma cleaning techniques are needed to prepare the surface for epitaxial deposition. The VLPCVD reactor resembles the UHVCVD deposition kinetics because of the mTorr deposition pressure and SiH4 gas chemistry. Deposition of in situ doped n- and p-type layers of up to 1020 cm−3 dopant concentrations and the deposition of selective epitaxial layers using VLPCVD have been demonstrated [44–46]. 2.2.6.

Remote plasma CVD

Remote plasma enhanced CVD (RPCVD) has also been used for the Si and Si1−x Gex epitaxy [47]. It is a low-temperature process and has been successfully employed for silicon homoepitaxy and Si1−x Gex heteroepitaxy in the temperature range of 150–450 ◦ C. The epitaxial process employs an ex situ wet chemical clean, an in situ remote hydrogen plasma clean, followed by a remote argon plasma dissociation of silane and germane to generate the precursors for epitaxial growth. Boron doping concentration as high as 1021 cm−3 has been achieved in the low-temperature epitaxial ﬁlms by introducing B2 H6 /He during growth. The growth rate of epitaxial Si can be varied from 0.4–50 ˚ A min−1 by controlling the RF power. The wide range of controllable growth rates makes RPCVD an excellent tool for applications ranging from superlattice structures to more conventional Si epitaxy. Defect densities below the detection limits of TEM (∼105 cm−2 or less) have been reported. The RPCVD process also exploits the hydrogen passivation eﬀect at a temperature below 500 ◦ C to minimize the adsorption of C and O during growth. Low oxygen content ∼ 3 × 1018 cm−3 has been achieved by RPCVD. Silicon and Si/Si1−x Gex ﬁlms with boron concentrations ranging from 1017 to 1019 have been achieved. 2.2.7.

Atmospheric pressure CVD

Atmospheric pressure reactors hold the greatest promise for widespread commercial use of Si1−x Gex heteroepitaxy of silicon. CVD of epitaxial SiGe

Deposition techniques

49

ﬁlms from SiH4 –GeH4 –HCl–H2 gas mixtures in an atmospheric pressure CVD process has been reported [48]. IBM [49,50] and ASM [51–53] deposit silicon and Si1−x Gex at atmospheric pressure using SiH2 Cl2 and GeH4 . Layer depositions are carried out in a horizontally arranged, inductionheated and air-cooled conventional epitaxy reactor. RCA precleaned silicon wafers were treated in situ in hydrogen at 1070 ◦ C for 10 min and then HCl gas-etched for a further 10 min. Gas puriﬁers and load locks are essential in both cases to reduce the oxygen and carbon incorporation. The IBM system uses a silicon carbide susceptor, whereas the ASM system uses a quartz support plate. The deposition kinetics appear similar to the LRPCVD or RTCVD systems since SiH2 Cl2 and GeH4 are used. The IBM system deposited smooth Si1−x Gex layers with up to 44% germanium at 550 ◦ C; they speculate that the chlorine-based gas chemistry suppresses islanding at high germanium concentrations. Unfortunately, no in situ doping data or Si1−x Gex device results have been reported using atmospheric CVD. 2.2.8.

Solid phase epitaxy

From the viewpoint of the compatibility with conventional silicon processing, it may be diﬃcult and extremely costly to merge MBE techniques within a standard bipolar/BiCMOS process. An alternative approach to forming the SiGe layer, is to implant high-dose Ge ions on the silicon substrate using solid phase epitaxy (SPE) [54–56]. This produces an amorphous SiGe layer on the silicon substrate and subsequent thermal annealing is required to induce crystallization. Residual implantation defects due to high-dose germanium implantation may be removed by sequential RTA. This method is fully compatible with the conventional silicon IC manufacturing process and is relatively simple. SPE growth of a SiGe alloy using Ge ion implantation and prolonged furnace anneal has been reported [57–60]. Carbon has a very low bulk solubility in Si and Ge. It is known that the incorporation of elements into Si at concentrations far in excess of their bulk solubility limit is possible by SPE. Thus, SPE provides another possible synthesis route for forming metastable Si1−y Gey or Si1−x−y Gex Cy layers. 2.2.9.

SiGeC ﬁlm growth

SiGe grown on Si(001) is compressively strained due to the larger lattice constant of germanium compared to silicon. This causes limitations such as a critical thickness for planar pseudomorphic growth. Adding a small amount of carbon into the SiGe material system allows strain adjustment due to the small lattice constant of carbon. Exactly strain compensated SiGeC structures have been shown to exhibit a smaller bandgap than silicon with a considerable valence band oﬀset [61–64]. Si1−y Cy and

50

Film growth and material parameters

Si1−x−y Gex Cy alloys in which C is incorporated substitutionally oﬀer considerably greater ﬂexibility compared to that available in Si/Si1−x Gex heterostructures. In particular, the growth of Si1−x−y Gex Cy alloys with a Ge:C ratio of about 8:1 oﬀers the possibility of fabricating group IV heterostructure devices lattice matched to Si. Due to the smaller lattice constant of carbon, synthesis of carboncontaining alloys with high electronic quality is challenging in part because of the low equilibrium solubility of carbon on the Si lattice. A number of research groups have investigated the maximum amount of carbon that can be incorporated in Si1−x−y Gex Cy by MBE and CVD [62, 65, 66] and also studies have been carried out to determine the fraction of the total carbon concentration that is substitutional on the lattice. An MBE system, equipped with an electron beam evaporator for silicon, a pyrolytic graphite ﬁlament for carbon and eﬀusion cells for germanium and boron, has been used for the growth of Si1−x−y Gex Cy samples with Ge contents up to 6% and carbon concentrations up to 0.55% at 450 ◦ C on a thick Si buﬀer layer. High-quality Si/Si1−x−y Gex Cy heterojunctions have been grown [67] by RTCVD using dichlorosilane (Si2 H2 Cl2 ), germane (GeH4 ) and methylsilane (SiCH6 ) as the precursors of Si, Ge and C, respectively. Using a cold-wall, ultrahigh vacuum, stainless steel chamber with single-wafer-processing capability, epitaxial SiGeC ﬁlms have been grown at 550 ◦ C with 1–20 sccm of Si2 H6 , 0.1–2 sccm of GeH4 and 0.8– 1.6 sccm of CH3 SiH3 . Carbon incorporations of 2.6 atomic wt.% in Si and 1.4 atomic wt.% in SiGe were obtained [68]. Photoluminescence studies of Si1−x−y Gex Cy and electrical measurements on the Si1−x−y Gex Cy -based bipolar transistors [69] indicate that the incorporation of substitutional C increases the bandgap of Si1−x−y Gex Cy pseudomorphically grown on an Si(100) substrate, with the bandgap increasing by 21–25 meV when 1% C is added. 2.2.10.

Strained-Si ﬁlm growth

High-quality completely lattice-relaxed SiGe buﬀer layers have been grown on Si(001) using MBE in the temperature range of 750 and 900 ◦ C and compositional grading of the order of 10% µm−1 or less with ﬁnal Ge concentrations of about 30%. Xie et al [1] have grown compositionally graded relaxed-Si1−x Gex buﬀer layers on Si with various composition gradients and temperatures. The authors reported a threading dislocation density in fully relaxed-SiGe buﬀer layers grown using both MBE and RTCVD in the range of 105 –106 cm−2 [70]. GSMBE [71, 72] has also been successfully employed for the growth of high-quality completely latticerelaxed step-graded SiGe buﬀer layers on Si(001) in the temperature range of 750 and 800 ◦ C. A more abrupt compositional transience of the SiGe/Si interface is expected in GSMBE-grown QWs, owing to reduced Ge

Thermal stability of alloy layers

51

segregation at the heterointerface [73], than in those grown by solid source MBE where Ge segregation has been recognized as an important issue [74]. Another advantage of GSMBE is that uniform thickness and composition can be obtained without sample rotation. However, GSMBE is associated with autodoping of doping gas impurities, which would aﬀect the device characteristics. 2.3.

THERMAL STABILITY OF ALLOY LAYERS

Since most of the low-temperature grown strained layers are metastable in nature, at a high processing temperature these coherently strained layers can relax by forming misﬁt dislocations. Even for sub-critically strained (i.e., thermodynamically stable) epilayers, interdiﬀusion can be important at a high temperature. Since standard silicon processing steps, such as implantation annealing and thermal oxidation, typically exceed the strained layer deposition temperature, thermal stability of strained layers is of utmost importance. The Matthews–Blakeslee curve imposes severe limitations on stable strained-Si1−x Gex layer thickness and germanium concentration. Understanding the relaxation processes of metastable layers is imperative if thicknesses and germanium concentrations greater than the equilibrium curve are needed. Relaxation processes from thermal cycling can be categorized into three mechanisms: temperature dependence of the threading dislocation glide force [75]; dislocation multiplication [76]; and germanium diﬀusion [77]. In an advanced very large scale integration (VLSI) process, there are two high-temperature steps: (i) thermal oxidation to grow gate oxide and (ii) post implant anneal after ion implantation. For gate oxidation, a temperature between 850–950 ◦ C is typically used, whereas for rapid thermal implant anneal a temperature as high as 1050 ◦ C is used depending on the dopant and dose. These high-temperature process steps impose serious limitations on the thermal budget that can be used to fabricate a device based on these metastable ﬁlms. The characterization methods used vary due to the detection limits of each technique. Detection methods include plan-view TEM, in situ plan-view TEM, Raman spectroscopy, double crystal diﬀractometry (DCD) and defect etching. X-ray diﬀraction analysis is not very sensitive to study dislocation defect densities device grade materials. Capacitance–voltage (C–V ) measurements can be employed to study the carrier conﬁnement in the QW. The SiO2 /Si/SiGe/Si MOS low-frequency capacitance shows a plateau region in inversion. This property of the low-frequency capacitance can be used to qualitatively study the degradation of the material properties due to high-temperature process steps. The plateau in the C–V curve is sensitive to the band oﬀset in the valence band at the Si/SiGe interface [78]. This band oﬀset in the valence band is reduced if the quality of the

52

Film growth and material parameters

heterointerface is degraded either due to the creation of misﬁt dislocation defects or due to interdiﬀusion. A few general trends may be established from the published literature on thermal stability of the strained layers: • • • •

2.4.

layers below the Matthews–Blakeslee equilibrium curve appear stable; relaxation of uncapped layers ranges from 600–700 ◦ C; unstrained silicon cap layers improve the thermal stability by extending the point of relaxation to 800 ◦ C. A silicon cap suppresses dislocation nucleation and propagation; and interfacial contaminants play a major role in the number of asdeposited dislocations.

BANDGAP AND BAND DISCONTINUITY

Theoretical calculations based on the electronic structure of heterointerfaces, involving a variety of SiGe layers on Si and Ge substrates, have been employed to predict the band oﬀset [7, 79]. Computations are generally based on local density functional theory, [80], phenomenological deformation potential theory [81] and self-consistent ab initio pseudopotential [82]. Experimental determination of the valence band oﬀset between strained-Si1−x Gex and Si (type I band alignment) has been reported by several workers using diﬀerent techniques such as x-ray photoelectron spectroscopy (XPS) [83], admittance spectroscopy [84], deep-level transient spectroscopy (DLTS) [85], capacitance–voltage and temperature-dependent current–voltage (I–V ) characteristics [86–88]. In the case of a p-type Si/Si1−x Gex MOS capacitor, as the gate bias is swept negative, holes will accumulate ﬁrst in the buried Si1−x Gex potential well formed by the valence band oﬀset ∆Ev , rather than at the silicon/oxide interface. Carrier accumulation in the buried well produces a bias region over which there is little change in the capacitance as a function of gate bias. As the gate bias continues to be swept to negative voltage, holes will eventually begin accumulating at the silicon/oxide interface. The capacitance then rises towards the maximum value of Cox , as is usual for an Si MOS capacitor. Band oﬀsets can be extracted by ﬁtting the shape of simulated MOS capacitance–voltage curves in the plateau region to measurements at diﬀerent temperatures, typically ranging from 100– 300 K [87]. To extract band oﬀsets from C–V measurements of p-MOSFETs, threshold voltages at heterointerface (VTH ) and SiGe/SiO2 interface (VTS ) √ are measured both from the ID –VG characteristics and a plot of ID / gm versus VG curve of a MOS device [89]. The relationship between threshold

Bandgap and band discontinuity

53

voltages and valence band oﬀset (∆Ev ) is given by [90] VTH = VFB + φTH − qNB xdm and VTS = VFB + φTS −

tSi tox + Si ox

(2.4)

qNB xdm 1 + H(φH ) Cox

(2.5)

where ∆Ev q φTH − φH H(φH ) = ho exp kT /q φTH = 2φF +

(2.6) (2.7)

where 2

ho = 2Si NB kT / (qNB xdm )

(2.8)

where VFB is the ﬂatband voltage, φTH is the potential at threshold at the top Si/Si1−x Gex interface, φTS is the potential at Si/Si1−x Gex interface, φF is the Fermi potential, q is electronic charge, NB is the eﬀective doping concentration in the bulk of the semiconductor, xdm is the maximum depletion layer width in strong inversion, tSi is the Si cap layer thickness, tox is oxide thickness, ox is the oxide permittivity, k is the Boltzmann constant, T is temperature and ∆VT = VTH − VTS . By subtracting equation (2.5) from equation (2.4) and rearranging, a system of two nonlinear equations (2.9) and (2.10) with ∆Ev and φH as unknown is obtained: 2 tSi kT Cox (∆VT − ∆Ev ) −1 ln 1 + Cox ∆Ev = φH −2φF + + −1 (ho ) q Si qNB xdm (2.9) and φH is given by kT φH = φTH − ln q

Si (φH − 2φF ) qNB xdm tSi

2

−1

− 1 (ho )

.

(2.10)

For an Si/SiGe heterostructure, an experimental valence band oﬀset (∆Ev ) is obtained by iterating equations (2.9) and (2.10) using the values of doping concentration and threshold voltages obtained from the experimental high-frequency apparent doping versus gate voltage characteristics [89], as shown in ﬁgure 2.8.

54

Film growth and material parameters

Figure 2.8. Apparent doping versus distance from the Si/SiO2 interface. Data obtained from the high-frequency C–V measurements.

2.4.1.

Si/SiGe

The electronic properties of SiGe materials depend on the substrate material on which they are grown, the germanium mole fraction in the ﬁlm, and the quality of the ﬁlm and interface. Although SiGe can be grown on silicon, germanium or even SiGe substrates, the fabrication of SiGe HBTs requires SiGe growth on silicon substrates. When a thin ﬁlm with a larger lattice constant (e.g., Si1−x Gex ) is grown on a smaller lattice constant substrate (e.g., silicon), the ﬁlm maintains the in-plane lattice constant of the substrate and is under a biaxially compressive strain. Figure 2.4, described earlier, shows the band oﬀset between a strained-Si0.8 Ge0.2 ﬁlm grown on silicon and strained-Si on a relaxed-SiGe layer. A discussion of strain-induced splittings within the framework of deformation potential theory has been given by van de Walle and Martin for strained-SiGe [79]. Depending on the composition, the bandgap of Si1−x Gex alloy varies from 1.1–0.7 eV, corresponding to the wavelength range of about 1–1.5 µm. This is a very useful range for discrete optoelectronic devices and for integrated optoelectronics on silicon. Figure 2.9 shows the bandgap diﬀerence compared to bulk-Si of unstrained Si1−x Gex [91] and the calculated values of strained-Si1−x Gex [92] at room temperature. The strained-Si1−x Gex curve splits into two lines because of uncertainty in some of the parameters used in the calculations. The

Bandgap and band discontinuity

55

Figure 2.9. Germanium mole fraction and strain-dependent bandgap of Si1−x Gex . The bandgap reduction for compressive (strained-SiGe), tensile (strained-Si) and relaxed cases are shown. (After People R 1986 IEEE J. Quantum Electron. 22 1696–710.)

calculated strained value lies in between the two dotted curves. The calculations for the bandgap of strained-Si1−x Gex were conﬁrmed by Lang [93] using photocurrent spectroscopy. The bandgap depends on the germanium fraction in both cases, but strained-Si1−x Gex experiences a faster drop in bandgap than the unstrained case due to splitting of the valence band degeneracies. Figure 2.9 indicates that strained-Si1−x Gex layers need less germanium to achieve the desired bandgap diﬀerence. The bandgap alignment for strained-Si0.8 Ge0.2 on silicon appears in ﬁgure 2.9 based on pseudopotential and deformation potential calculations by van de Walle [82] and People [81]. Since the conduction band discontinuity is much smaller than the valence band discontinuity, researchers often ignore the conduction band discontinuity. Quantum conﬁnement of electrons at the Si–strained-Si1−x Gex heterointerface is diﬃcult because of the small conduction band discontinuity. However, the

56

Film growth and material parameters

state of the initial substrate plays a major role in determining the band oﬀsets, as shown in ﬁgure 2.9. In fact, calculations show virtually any bandgap alignment is possible [14]. 2.4.2.

Si/SiGeC

Present knowledge about the band structure of tensilely strained-SiGeC ternary alloys on Si001 is limited. Assuming an average band structure for Si1−x−y Gex Cy alloys, Soref [94] has suggested an empirical interpolation between Si, Ge and diamond (C) for the bandgap which increases in the fundamental gap of Si1−x−y Gex Cy layers with increasing y. This result has been contradicted by Demkov and Sankey [95] who have shown that the fundamental gap is reduced when a small percentage of carbon is added to the silicon lattice. This reduction in bangap is in agreement with the photoluminescence measurement data. To describe adequately the observed energy shifts for pseudomorphic carbon-containing layers, strain-induced eﬀects and eﬀects due to alloying should be considered [96]. An estimation for the band oﬀsets and the fundamental bandgap for Si1−x−y Gex Cy alloys (containing up to 3% carbon and 30% Ge concentration) tensile or compressive strained has been reported by Osten [97]. This estimation considers both the band alignment at the interface of two diﬀerent materials, as well as strain eﬀects. Figure 2.10 summarizes the results for the highest valence band for diﬀerent tensile and compressive strained-Si1−x−y Gex Cy layers on Si001. The plot shows ∆Ev as a function of the eﬀective Ge or C

Figure 2.10. Valence band oﬀsets for compressively strained Si1−x Gex and Si1−x−y Gex Cy (x = 10%, 20% and 30%, y varies between 0% and 3%) and tensile strained Si1−y Cy and Si1−x−y Gex Cy (y = 1%, 2% and 3%, x varies between 0% and 30%) plotted as a function of the eﬀective lattice mismatch—expressed in ‘eﬀective’ Ge or C concentrations, respectively. (After Osten H J 1998 J. Appl. Phys. 84 2716–21.)

Bandgap and band discontinuity

57

concentration for the compressive or tensile strained layers, respectively. The eﬀective concentration corresponds to the concentration needed for identically strained binary layers. The valence band oﬀset between compressive strained layers and Si is generally much larger than that at the tensile strained layer/Si interface. Photoluminescence studies of Si1−x−y Gex Cy sandwiched between Si layers [62, 63] and electrical measurements on the Si1−x−y Gex Cy -based bipolar transistors [69] indicate that the incorporation of substitutional C increases the bandgap of Si1−x−y Gex Cy pseudomorphically grown on an Si(100) substrate, with the bandgap increasing by 21–25 meV when 1% C is added. Analysis of n- and p-type MOS capacitors indicates that most of the band oﬀset is in the valence band for Si/Si1−x−y Gex Cy heterojunctions with carbon contents less than or equal to 0.8 at.%, i.e., no capacitance plateau region is observed for n-type Si/Si1−x−y Gex Cy /Si capacitors. Figure 2.11 summarizes the extracted valence band oﬀsets as a function of the mismatch to Si for Si/Si1−x−y Gex Cy capacitors with Ge contents of 20 and 30% and carbon contents up to roughly 1 at.%. From the data it is seen that the extracted valence band oﬀset decreases as carbon is added to Si1−x−y Gex Cy . This is consistent with the widening of the Si1−x−y Gex Cy bandgap with the increasing carbon content that has been

Figure 2.11. Summary of valence band oﬀsets extracted from MOS capacitance–voltage characteristics for p-type Si/Si1−x−y Gex Cy capacitors. The oﬀset is extracted by ﬁtting C–V simulations to the measured data. (After Hoyt J L et al 1998 Thin Solid Films 321 41–6.)

58

Film growth and material parameters

observed by photoluminescence measurements [63, 98]. It is also observed from ﬁgure 2.11 that, for a given mismatch to Si, the valence band oﬀsets appear to be slightly higher for Si/Si1−x−y Gex Cy than for Si/Si1−x Gex heterojunctions. XPS has been used to measure the conduction and valence band oﬀsets in thick, relaxed Ge-rich Si1−x−y Gex Cy alloys grown by solid source molecular beam epitaxy on (100) Si substrates [99]. It was shown that addition of C increased the valence band maximum of SiGeC by +48 meV %C−1 . The bandgap energies were obtained from optical absorption, and were combined with the valence band oﬀsets to yield the conduction band oﬀsets. For SiGeC/Si heterojunctions, the oﬀsets were typically 0.6 eV for the valence band and 0.38 eV for the conduction band, with a staggered type II alignment. These oﬀsets provide signiﬁcant electron and hole conﬁnement for device applications. Admittance spectroscopy has been used to measure valence band oﬀsets in Si/Si1−x Gex and Si/Si1−x−y Gex Cy heterostructures grown by MBE. The Si/Si1−x Gex and Si/Si1−x−y Gex Cy samples consisted of 250 ˚ A Si1−x Gex or Si0.796 Ge0.20 C0.004 alternating with 350 ˚ A Si for ten periods, and both layers were doped p-type with dopant concentrations of 7.4 × 1016 cm−3 and 1 × 1017 cm−3 , respectively. These heterostructures were grown on a 2000 ˚ A Si buﬀer on Si substrates and capped with 2000 ˚ A Si. Measurements of conductance and capacitance as functions of temperature at various frequencies were used to determine the activation energy for thermal excitation over the Si barriers in the p-type multiple quantum well (MQW) structures; band oﬀsets were then obtained from the measured activation energies. For Si/Si0.75 Ge0.25 and Si/Si0.80 Ge0.20 heterostructures coherently strained to Si, valence band oﬀsets of 198 ± 12 and 160 ± 20 meV, respectively, were obtained. For a Si0.796 Ge0.20 C0.004 heterostructure, the valence band oﬀset was 118 ± 10 meV. This value is slightly lower than the valence band oﬀset of approximately 135 meV expected in a Si/Si0.833 Ge0.167 heterojunction, for which the lattice mismatch is the same as in the Si/Si0.796 Ge0.20 C0.004 heterojunction. 2.4.3.

Strained-Si

The heterojunction band oﬀsets (∆Ec , ∆Ev ) in a strained-Si/SiGe heterostructure have been determined from the measurement of threshold voltages of surface channel strained-Si p-MOSFET structures [89, 100]. The extracted experimental valence band oﬀset ∆Ev was found to be 160 meV. Using the valence band oﬀset value, the conduction band oﬀset was obtained from the following equation ∆Ec = Eg (Si1−x Gex ) + ∆Ev (Si1−x Gex /Si) − Eg (strained-Si)

(2.11)

Mobility

59

where Eg (strained-Si) is given by [7, 101] Eg = 1.11 − 0.4x

(2.12)

where x is the Ge concentration in the top part of a completely relaxed SiGe buﬀer cap. The conduction band oﬀset ∆Ec was found to be 126 meV for a Ge concentration of 0.2 at the top of the relaxed-SiGe layer. 2.5.

MOBILITY

Strain not only modiﬁes the bandgap energy and band alignments but also lowers the eﬀective mass at the band edges and higher mobilities may be expected [102]. In the following, we discuss some experimental work used to determine mobility in strained layers. A more comprehensive discussion of the electron and hole mobility on strain level and the band structure will be given in chapter 4. 2.5.1.

Si/SiGe

Calculations have been made for strained and unstrained Si1−x Gex that have shown an increased electron mobility perpendicular to the growth interface and increased hole mobility parallel to the growth interface for strained layers with increasing Ge content. If an Si1−x Gex strained epilayer is grown on (100) Si, the splitting of the conduction band minimum due to strain reduces the eﬀective mass and improves the electron mobility in a direction perpendicular to the interface by about 50% [103, 104]. These results, however, have been contradicted by other simulations showing that the mobility peaked and then decreased with increasing Ge concentration [105, 106]. If the epilayer is grown on a thick relaxed-Si1−x Gex buﬀer layer with a higher Ge concentration than in the epilayer, the mobility perpendicular to the layer is reduced while the mobility parallel to the interface increases [107]. As the doping concentration in the semiconductor increases, the strict periodicity of the lattice is disturbed by the existence of the impurity atoms, and various heavy doping eﬀects occur. Besides the dependence of carrier mobilities on the doping concentration and electric ﬁeld, in alloy semiconductors, mobilities also depend on the composition. It is well known that heavy doping of a semiconductor can reduce the bandgap. In SiGe alloys and strained layers, the combined eﬀect of strain and heavy doping on the bandgap and bandgap narrowing have been reported [8, 108]. 2.5.2.

Si/SiGeC

Given the potential of Si/Si1−x−y Gex Cy , it is imperative to know its carrier transport properties and compare them with those in the Si/Si1−x Gex

60

Film growth and material parameters

system. Two-dimensional modulation-doped hole gases can in principle be fabricated since the band oﬀset at the Si/Si1−x−y Gex Cy interface is predominately in the valence band [109, 110]. To date, however, there are very few reports on the transport properties of holes in the Si/Si1−x−y Gex Cy interface and reports of transport properties are limited to the temperature range of 77–300 K. In the following, we discuss the transport properties of a two-dimensional hole gas in an Si/Si1−x−y Gex Cy modulation-doped structure. Using modulation-doped p-type Si1−x−y Gex Cy QWs, transport properties of boron-doped tensile strained, perfectly strain compensated and compressively strained-Si1−x−y Gex Cy alloy layers on Si(001) substrates have been studied by Duschl et al [111]. The layer sequence of the p-type modulation-doped Si0.85−y Ge0.5 Cy QWs is 200 nm undoped silicon, 20 nm Si0.85−y Ge0.5 Cy , 10 nm Si spacer, a 30 nm thick 2×1018 cm−3 boron-doped Si layer and a 30 nm Si cap. The mobility and charge carrier density were determined in a temperature range 40–300 K using the standard van der Pauw technique at a magnetic ﬁeld of 0.3 T. At room temperature, acoustic and optical phonon scattering is dominant. However, with the freeze-out of phonons at cryogenic temperatures, ionized impurity scattering becomes dominant in moderately doped semiconductors. In Si1−x−y Gex Cy layers, alloy scattering contributes as a further mechanism. The carrier mobility also depends on the amount of ionized impurities, the germanium and carbon contents. In the following, we discuss the eﬀect of the addition of carbon and germanium on the hole mobility of strained and exact strain compensated Si1−x−y Gex Cy layers. Figure 2.12 shows the room temperature mobility and hole density data. Besides a silicon reference layer (solid square), the ﬁrst (open squares) starts with the compressively strained Si0.94 Ge0.06 . By adding carbon, while leaving the germanium content constant, the strain is subsequently reduced until exact strain compensation is reached (C = 0.55%). Then the amount of Ge is reduced leading to tensile strained Si0.995−x Gex C0.0055 and ﬁnally to Si0.995 C0.0053 . The second sequence (open circles) starts with Si0.96 Ge0.04 and ends at Si0.996 C0.0037 . Considering the Hall mobility (ﬁgure 2.12(a)) it is quite evident that additional germanium and carbon reduces the mobility as compared to pure silicon. A general trend is that the room temperature mobility on the compressive strain side is nearly independent of the carbon content. On the other hand, the hole density (ﬁgure 2.12(b)) decreases from compressive to tensile strain. Figure 2.13 shows the temperature dependence of the Hall mobility. The reduced mobility of the Si1−x−y Gex Cy alloys compared to pure silicon at room temperature agrees well with the results published in the literature [18, 112, 113]. The reasons for the drop in mobility are the

Mobility

61

Figure 2.12. Room temperature mobility (a) and hole density (b) of pure Si (solid square) and two sample sequences. The ﬁrst sequence (open squares) starts with Si0.94 Ge0.06 . By adding carbon, while leaving the germanium content constant, the strain is subsequently reduced until strain relaxation is reached Si0.935 Ge0.06 C0.055 then the amount of germanium is reduced leading ﬁnally to Si0.995 C0.0053 . The second sequence starts with Si0.96 Ge0.04 and ends with Si0.996 C0.004 . (After Duschl R et al 1998 Thin Solid Films 336 336–9.)

alloy scattering and the enhancement of optical phonon scattering with increasing germanium incorporation due to the smaller optical phonon energy of germanium compared to silicon. But the theoretically predicted and experimentally observed small decrease of the eﬀective mass due to the germanium incorporation, which should lead to a higher mobility, cannot compensate these eﬀects. However, at a low temperature, the Si1−x−y Gex Cy layers show a higher mobility than the silicon due to the lower carrier concentration which leads to a lower eﬀective mass and minor role of the optical phonon scattering at a low temperature. It is seen that

62

Film growth and material parameters

Figure 2.13. Temperature dependence of the hole mobility for the compressively strained Si0.94 Ge0.06 , exact strain compensated Si0.935 Ge0.06 C0.055 and tensile strained Si0.995 C0.053 layers. (After Duschl R et al 1998 Thin Solid Films 336 336–9.)

the room temperature mobility decreases with C and Ge alloy concentration compared to pure Si from 180 to 120 cm2 V−1 s−1 , which is due to the increasing alloy scattering and enhanced scattering at optical phonons. At temperatures below 100 K, a higher mobility is measured for the samples containing C, due to the lower carrier concentration and because ionized impurity scattering becomes dominant. Figure 2.14 shows the mobility and carrier density of a two-dimensional hole gas in the Si1−x−y Gex Cy channel from room temperature to 10 K. The initial decreasing and eventual saturation of hole density indicate the freeze-out of parallel conduction paths and the gradual transfer of holes to the Si1−x−y Gex Cy channels as temperature is decreased. In contrast, the hole mobility increases with decreasing temperature. This is evidence of the formation of two-dimensional hole gas in the Si1−x−y Gex Cy channels. The hole mobility at a low temperature decreases as C is incorporated. For example, at 10 K the mobility with no C is 1800 cm2 V−1 s−1 compared to 1500 and 800 cm2 V−1 s−1 with C levels of 0.3% and 0.6%, respectively. It is not clear if the decrease in hole mobility is due to enhanced alloy scattering with the addition of C, or other factors, such as increased interface roughness or C-related defects. The carrier density saturates at ∼1012 cm−2 at a low temperature, suggesting a complete hole transfer, as intended, from the Si dopant layer to Si1−x−y Gex Cy channels. The variation in the carrier density may be due to imperfect doping control during growth and is not thought to result from a change in the valence band.

Mobility

63

Figure 2.14. Hole density and mobility as a function of temperature for Si/Si1−x−y Gex Cy modulation-doped heterostructures. (After Chang C L et al 1998 Thin Solid Films 321 51–4.)

2.5.3.

Strained-Si

Low-temperature Hall mobility measurements are commonly used to determine the overall quality of a heterostructure and are used to optimize the growth parameters. At low temperature, where the thermal eﬀects and scattering by phonons are dramatically reduced, the electron mobility becomes very sensitive to residual scattering mechanisms due to background charge impurities, roughness and dislocation. Experimental electron mobility data from strained-Si/SiGe modulation-doped structures may be divided into two categories: (i) data from devices with the uniform composition buﬀer and (ii) devices with the compositionally graded buﬀer. A detailed discussion on the mobility of electrons and holes in strained-Si may be found in [17]. At room temperature, strained-Si electron mobility values are between 2000 and 2800 cm2 V−1 s−1 for n-channels [118,119], which exceed those in bulk-Si MOSFETs by a factor of four to six. High hole mobilities in excess of 9300 cm2 V−1 s−1 at 4 K in p-type modulation-doped Si/Si0.87 Ge0.13 /Si heterostructures have been reported by Whall et al [120]. For p-MOSFETs, room temperature values between 1400 and 1800 cm2 V−1 s−1 have been reported [121], a factor of six to nine above those of conventional Si pMOSFETs. The dependence of low-ﬁeld electron and hole mobility on strain level is shown in table 2.2. A more comprehensive discussion of the dependence of low-ﬁeld electron and hole mobility on strain level and the band structure will be given in chapter 6.

64

Film growth and material parameters

Table 2.2. Experimental low-ﬁeld electron and hole mobility: dependence on strain level. Ge concentration in the buﬀer (%) Electron

Strain in Si (%)

Temperature (K)

Mobility enhancement factor

10 20 29 29

0.4 0.8 1.3 1.3

300

[114]

77

1.45 1.67 1.75 1.35

1.33 0.8 0.8 1.0

300 300 77 300

1.2 1.4 2.0 1.5

[115] [116]

Ref.

Hole 29 18 18 25

2.6.

[117]

SUMMARY

In this chapter we have given the background for growing diﬀerent strained layers using various types of reactors. Basic Si1−x Gex properties and deposition systems have been brieﬂy covered. A variety of methods exist to deposit high-quality alloy layers. In addition to depositing layers with germanium concentrations of at least 15%, control of the germanium proﬁle to within 1% is desirable for bandgap grading. The use of Si/Si1−x Gex heteroepitaxial structures for heterojunction devices is hindered by the lattice mismatch between the two materials. However, strained-Si1−x Gex layers can be deposited on silicon at or above the Matthews–Blakeslee critical thickness curve without interfacial dislocations. Typical bandgap engineering applications may require up to 150 meV bandgap diﬀerence. Therefore, the deposition technique must be able to deposit Si1−x Gex layers with germanium concentrations of at least 20%. Layers deposited above the Matthews–Blakeslee curve must contend with thermal relaxation during thermal processing. Unfortunately, the Matthews–Blakeslee critical thickness at 20% germanium is only about 20 nm, and is a limitation for applications requiring higher Ge mole fractions. Partially straincompensated or fully strain-compensated SiGeC ﬁlms may extend the application areas. Diﬀerences in the reactor design, base pressure, gas chemistry and deposition temperature do not appear to limit the ability to deposit device quality group IV alloy layers. MBE is commonly used as a research tool due to its low wafer throughput. UHVCVD appears to have the

Bibliography

65

most advantages in terms of material quality and throughput. Research using LRP/RTCVD reactors have demonstrated device quality material. Extension of the LRP/RTCVD reactor concept to commercial atmospheric CVD reactors holds promise, but additional work in characterizing atmospheric reactors is needed. Furthermore, the throughput of these single wafer atmospheric CVD reactors needs to be examined. The experimental determination of valence band and conduction band oﬀsets (∆Ev , ∆Ec ) in a heterostructure, from the measured threshold voltages (VTH and VTS ) of a p-MOSFET have been discussed. A review of experimental work to determine the variation of mobility in SiGe, SiGeC and strained-Si layers on strain, doping and temperature has also been described.

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Si1−x−y Gex Cy J. Appl. Phys. 70 2470–2 [95] Demkov A A and Sankey O F 1993 Theoretical investigation of random SiC alloys Phys. Rev. B 48 2207–14 [96] Zollner S 1995 Theory of optical interband transitions in strained Si1−y Cy grown pseudomorphically on Si(001) J. Appl. Phys. 78 5209–11 [97] Osten H J 1998 Band-gap changes and band oﬀsets for ternary Si1−x−y Gex Cy alloys J. Appl. Phys. 84 2716–21 [98] Boucaud P, Francis C, Julien F H, Lourtioz J M, Bouchier D, Bodnar D, Lambert B and Regolini J L 1994 Band-edge and deep level photoluminescence of pseudomorphic Si1−x−y Gex Cy alloys Appl. Phys. Lett. 64 875–7 [99] Kolodzey J, Chen F, Orner B A, Guerin D and Ismat Shah S 1997 Energy band oﬀsets of SiGeC heterojunctions Thin Solid Films 302 201–3 [100] Maiti C K, Bera L K, Dey S S, Nayak D K and Chakrabarti N B 1997 Hole mobility enhancement in strained-Si p-MOSFETs under high vertical ﬁelds Solid-State Electron. 41 1863–9 [101] Abstreiter G, Brugger H, Wolf T, Jorke H and Herzog H J 1985 Straininduced two-dimensional electron gas in selectively doped Si/Six Ge1−x superlattices Phys. Rev. 54 2441–4 [102] Manku T and Nathan A 1991 Eﬀective mass for strained p-type Si1−x Gex J. Appl. Phys. 69 8414–6 [103] Smith C and Welbourn A D 1987 Prospects for a heterostructure bipolar transistor using a silicon–germanium alloy IEEE BCTM Proc. pp 57–64 [104] Manku T and Nathan A 1991 Lattice mobility of holes in strained and unstrained Si1−x Gex alloys IEEE Electron Device Lett. 12 704–6 [105] Kay L E and Tang T-W 1991 Monte Carlo calculation of strained and unstrained electron mobilities in Si1−x Gex using an improved ionizedimpurity model J. Appl. Phys. 70 1483–8 [106] Pejcinovic B, Kay L E, Tang T-W and Navon D H 1989 Numerical simulation and comparison of Si BJTs and Si1−x Gex HBTs IEEE Trans. Electron Devices 36 2129–37 [107] Smith C and Jones M E 1988 The mobility of electrons in strained silicon Superlattices Microstruct. 4 391–4 [108] Poortmans J, Martens R P and Jain S C 1989 Bandgap narrowing due to heavy doping in Si1−x Gex layers Proc. ESSDERC’89 pp 807–10 [109] Chang C L, St Amour A and Sturm J C 1997 The eﬀect of carbon on the valence band oﬀset of compressively strained Si1−x−y Gex Cy /(100) Si heterostructures Appl. Phys. Lett. 70 1557–9 [110] Chang C L, Shukla S P, Pan W, Venkataraman V, Sturm J C and Shayegan M 1998 Eﬀective mass measurement in twodimensional hole gas in strained Si1−x−y Gex Cy /Si(100) modulationdoped heterostructures Thin Solid Films 321 51–4 [111] Duschl R, Seeberger H and Eberl K 1998 Hole mobilities in pseudomorphic Si1−x−y Gex Cy alloy layers Thin Solid Films 336 336–9 [112] Osten H J and Gaworzewski P 1997 Charge transport in strained Si1−y Cy and Si1−x−y Gex Cy alloys on Si(001) J. Appl. Phys. 82 4977–81 [113] Gaworzewski P, Tittelbach-Helmrich K, Penner U and Abrosimov N V 1998 Electrical properties of lightly-doped p-type silicon–germanium single

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Chapter 3 PRINCIPLE OF SIGE HBTS

In chapter 2, the technologies involved in SiGe layer growth and the electronic properties of strained-Si1−x Gex layers have been described with special emphasis on those properties which are related to their use as a narrow bandgap material in the base of a heterojunction bipolar transistor (HBT). In this chapter, we examine the underlying physics of the npn SiGe HBT, with particular emphasis on the fundamental diﬀerences between the operations of the SiGe HBT and the Si BJT. The concept of a bipolar transistor in which the emitter has a greater bandwidth than the base dates back to the time of Shockley’s original patent on the junction bipolar transistor [1]. A detailed theoretical analysis of the potential performance advantages of this type of device, commonly known as a heterojunction bipolar transistor, was presented by Kroemer in 1957 [2]. However, it was not until 1987 that a functional HBT employing a base layer was demonstrated. The introduction of Ge into the base of an npn Si BJT reduces the bandgap of the SiGe alloy in the p-doped base, relative to Si in the n-doped emitter and collector regions. This bandgap discontinuity creates the heterojunctions needed for the enhanced performance of a SiGe HBT. Before discussing heterojunction action in a bipolar transistor we start by recapping well-established Si BJT fundamentals [3]. If the eﬀect of carrier recombination is initially ignored, the electron and hole injection currents in a forward biased pn junction can be expressed as

qVbe qADnb In = −1 (3.1) np0 exp Lnb kT

qVbe qADpe Ip = −1 (3.2) pn0 exp Lpe kT where Vbe is the applied bias, A is the area of the junction, Dnb and Dpe are the minority carrier diﬀusion constants, Lnb and Lpe are minority carrier 73

74

Principle of SiGe HBTs

diﬀusion lengths, and np0 and pn0 are the equilibrium minority carrier concentrations in the neutral base and emitter, respectively. In conventional homojunction transistors, the doping concentration in the emitter is considerably higher than in the base, in order to obtain a high injection eﬃciency. For a typical gain of 100, the emitter must be doped 100 times more heavily than the base. As the doping concentration increases to more than 1018 cm−3 , bandgap narrowing due to heavy doping becomes signiﬁcant [4]. The following substitutions can be made in equations (3.1) and (3.2) np0 =

n2io Nb

(3.3)

pn0 =

n2ie Ne

(3.4)

∆Ebgn (3.5) kT where nio is the intrinsic carrier concentration and ∆Ebgn represents the bandgap reduction in the emitter due to heavy doping. When bandgap narrowing is included, the current gain β becomes Ne Lpe Dnb −∆Ebgn . (3.6) βSi = exp Nb Lnb Dpe kT n2ie = n2io exp

In an HBT with a narrow bandgap base, the bandgap of the emitter is larger than the base and therefore the injection eﬃciency can be made very high, even if the base is doped more heavily than the emitter [2, 5]. In a SiGe HBT, a narrow bandgap SiGe base is used and the bandgap diﬀerence between the emitter and base is ∆Eg (x) = Eg,Si − Eg,SiGe (x). Due to its smaller bandgap, the intrinsic carrier concentration in the SiGe base increases. The diﬀerence between the HBT and BJT is that the concentration of the injected electrons is much higher (several orders of magnitude) into the base due to lower conduction band barrier. The current gain for a SiGe HBT becomes ∆Eg (x) βSiGe = βSi exp . (3.7) kT This means that the collector current will be much higher than in a similarly doped BJT, by a factor of exp(∆Eg (x)/kT ), while the base current is not aﬀected. In a SiGe HBT, the bandgap diﬀerence ∆Eg (x) can be made much larger than kT . For example, a Ge fraction x = 0.2 in the base yields a bandgap diﬀerence of more than 170 meV. Therefore, the current gain of the HBT can be made large, irrespective of the doping ratio in the emitter and the base. However, the real advantage of the HBT

Energy band

75

is not to achieve a very high current gain, but to trade it against a high base doping, necessary to reduce the base resistance. High values of maximum oscillation frequency and low values of gate delay τd (for digital switching applications) can be obtained in HBTs [6,7]. Base resistance is an important parameter in determining fmax . In a welldesigned HBT, a value of 50 for β is usually suﬃcient, so emitter injection eﬃciency can be traded for increased doping in the base. Increased base doping gives rise to reduced base resistance which is also desirable in helping to avoid punch-through as the base–collector voltage is increased. High base doping may contribute to the onset of tunnelling current at the emitter–base junction. This can be avoided by deliberately reducing the doping concentration in the emitter. Indeed, in the HBT, it is in principle feasible to consider the possibility of interchanging collector and emitter, providing additional advantage in some digital circuits. Many of the speciﬁc issues involved in transistor design are more fully covered in chapter 4. For the remainder of this chapter, we focus in more detail on device physics, showing how the incorporation of germanium signiﬁcantly changes the physics of the base region and the emitter–base and base– collector junctions. 3.1.

ENERGY BAND

The ﬁrst step in understanding how a heterostructure device will operate is to consider the energy band diagram. For homostructures, the electron aﬃnity and bandgap are position independent, and there is no need to worry about the reference level. But for heterostructures, a reference level is essential, normally taken to be the ﬁeld-free vacuum level. To draw energy band diagrams for devices with a position-dependent alloy composition, it is essential to know how the bandgap varies with position and also the band line up at compositional junctions. Figure 3.1 shows the band diagram of an npn bipolar transistor. In forward active mode, the emitter–base junction is forward biased by the input voltage Vbe , and the base–collector junction is reverse biased by the output voltage Vbc . The collector current Ic consists of electrons which are injected from the n-emitter into the thin p-base, move through the base by drift and diﬀusion, and are collected in the n-collector layer (a drift ﬁeld in the base can be caused by either a doping or a bandgap gradient). The number of electrons injected into the emitter side of the base is determined by the height of the potential barrier, ∆Vn , in the conduction band between the emitter and the base, which can be controlled by the input voltage Vbe . The dominant component of the base current Ib consists of holes which are injected from the p-base into the n-emitter (no holes are injected into the n-collector in forward active mode because the base–collector junction is reverse biased). The number of holes injected into the emitter is determined

76

Principle of SiGe HBTs

Figure 3.1. Simulated band diagram of an npn bipolar transistor. (After Prinz E J 1992 Base transport and vertical proﬁle engineering in Si/Si1−x Gex /Si heterojunction bipolar transistors PhD Dissertation Princeton University.)

Figure 3.2. Simulated band diagram of a narrow bandgap base npn heterojunction bipolar transistor. (After Prinz E J 1992 Base transport and vertical proﬁle engineering in Si/Si1−x Gex /Si heterojunction bipolar transistors PhD Dissertation Princeton University.)

Terminal currents in a SiGe HBT

77

by the potential barrier ∆Vp in the valence band between base and emitter, which is also controlled by the input voltage Vbe . The key idea of an HBT is to lower the potential barrier seen by the carriers responsible for the output current (electrons in npn devices) compared with the one seen by the carriers constituting the input current (holes in npn devices), thereby increasing the ratio of output to input current, the common emitter current gain of the HBT [5]. This is done by fabricating the emitter and the base using materials having diﬀerent bandgaps. Depending on the layer in which the bandgap is changed compared to a homojunction device, two HBT conﬁgurations can be distinguished: (i)

in a narrow bandgap base HBT, the bandgap in the base is lowered thereby increasing the collector current, whereas (ii) in a wide bandgap emitter HBT, the bandgap in the emitter is increased compared to the base, resulting in a lower base current. In both cases, the common emitter current gain is increased by a factor proportional to exp(∆Eg /kT ) if spike and notch eﬀects at the heterojunctions are neglected. Note that in an HBT, where the emitter bandgap is larger than that in the base, the current gain β should increase when the temperature is lowered, making it possible to operate the transistors more eﬀectively at cryogenic temperature. 3.2.

TERMINAL CURRENTS IN A SIGE HBT

In this section we consider a comparison of a SiGe HBT with the equivalent Si BJT. For the purpose of comparison, it is assumed that both the silicon bipolar and the SiGe HBT are identical, other than the fact that germanium is present in the SiGe HBT. Figure 3.3 shows how the base bandgap changes are brought about by the incorporation of Ge into the base. In thermal equilibrium, the Fermi level, EF , is constant across the junction. Therefore, for an abrupt Si/SiGe interface, the diﬀerence in bandgap between the emitter and base causes discontinuities to exist at the conduction and valence bands, shown in ﬁgure 3.3 as ∆Ec and ∆Ev , respectively. Also, the total discontinuity, ∆Ec + ∆Ev , is equal to the base bandgap diﬀerence between the silicon emitter and SiGe base, ∆Egc−b . In SiGe, the valence band discontinuity, ∆Ev , tends to be considerably larger than the conduction band discontinuity, ∆Ec . Figure 3.4 shows the band diagram in forward active mode, where in this more general case, the germanium concentration is graded linearly across the base, increasing from emitter towards the collector. With the presence of germanium, the electron injection barrier from emitter to base, ψn , is reduced and there will be greater electron injection from emitter to base. This means an increase in the collector current. However, the hole

78

Principle of SiGe HBTs

Figure 3.3. Eﬀect of strained-SiGe layer on the bandgap of emitter–base junction for an abrupt Si/SiGe interface. (After Tang Y T 2000 Advanced characteristics and modelling of SiGe HBTs PhD Thesis University of Southampton.)

injection barrier from base to emitter, ψp , remains the same as in a silicon bipolar transistor. Therefore, the hole current from base to emitter, which is the main contributor to base current, remains the same. Hence, silicon bipolar transistors and SiGe HBTs tend to have approximately the same base current. The following derivations [8], used to show enhancements resulting from Ge incorporation in the base, closely follow derivations contained in [9]. We consider the most general case of germanium grading and show how constant grading may be treated as a particular case for which the theoretical treatment is still valid. The collector current of a graded SiGe HBT can be obtained by altering the collector current equation of a silicon bipolar transistor. Assuming uniform base doping for the device, the silicon bipolar collector current density, Jc,Si , for uniformly-doped base can be

Terminal currents in a SiGe HBT

79

Figure 3.4. Bandgap energy diagram across a graded SiGe HBT in forward active mode of operation. Of and Wf are the electrical boundaries of the neutral base region on the emitter and collector sides of the base, respectively. (After Tang Y T 2000 Advanced characteristics and modelling of SiGe HBTs PhD Thesis University of Southampton.)

written using the Moll–Ross relation [10] Jc,Si = q (exp (qVbe /kT ) − 1) =

Wf

Of

Nb (x)dx Dnb (x)n2ie (x)

−1

qDnb n2io app exp ∆Egb /kT [exp (qVbe /kT ) − 1] Wb Nb

(3.8) (3.9)

where q is the charge on an electron, Vbe is the forward biased emitter– base voltage, k is the Boltzmann constant, T is temperature, Of and Wf are the base electrical junction positions at the emitter and collector side of the neutral base, in forward active mode, Wb is the neutral base width, Nb (x) is the positional-dependent base doping concentration, Dnb (x) and nie (x) are the positional-dependent base electron diﬀusion coeﬃcient and eﬀective intrinsic carrier concentration, respectively, nio is the intrinsic

80

Principle of SiGe HBTs

carrier concentration in the absence of heavy doping eﬀects, Nb is the app base doping, and ∆Egb is the base apparent bandgap narrowing due to the heavy doping eﬀect. In equation (3.8), nie (x) accounts for the eﬀective intrinsic carrier concentration across the base and is a function of the bandgap. For a graded SiGe HBT, bandgap changes across the base, as depicted in ﬁgure 3.4, can be accounted for [9] app ∆Egb ∆Eg,SiGe (grade)(x/Wb ) ∆Eg,SiGe (Of ) 2 2 nie (x) = γnio exp + + kT kT kT (3.10) where [11] (Nc Nv )SiGe γ= ≈ 0.4 (3.11) (Nc Nv )Si and neutral base width, Wb = Wf −Of . The term Eg,SiGe (grade) represents the bandgap diﬀerence across the neutral base. The term ∆Eg,SiGe (Of ) represents the bandgap diﬀerence at the emitter side of the neutral base, Nc and Nv are the density of states in the conduction and valence bands, respectively. Putting equations (3.8) and (3.10) together and integrating, the most general form for the SiGe HBT collector current density, Jc,SiGe , incorporating both bandgap oﬀset and grading, can be written as [9] app 2 ∆Egb qV n qD nb be io + −1 exp Jc,SiGe = ζ¯γ¯ Wb Nb kT kT (3.12) exp ∆Eg,SiGe (Of )/kT ∆Eg,SiGe (grade) × kT 1 − exp − ∆Eg,SiGe (grade)/kT where ζ=

(Dnb )SiGe >1 (Dnb )Si

(3.13)

where the symbol ‘–’ refers to a position averaged quantity. The ratio of (Dnb )SiGe to (Dnb )Si accounts for the strain enhancement of the minority carrier electron mobility with increasing germanium content [12]. Taking the ratio of Jc,SiGe to Jc,Si , the collector current enhancement due to bandgap engineering can be estimated by, exp (∆Eg,SiGe (Of )/kT ) Jc,SiGe ∆Eg,SiGe (grade) ≈ ζ¯γ¯ kT 1 − exp (−∆Eg,SiGe (grade)/kT ) Jc,Si

(3.14)

where we can draw important conclusions by considering the magnitudes of the terms in the above equation in giving rise to collector current enhancement, i.e.,

Terminal currents in a SiGe HBT • • •

81

ζ¯ > 1 deﬁnes the eﬀect of the diﬀerence in diﬀusivity/mobility between SiGe and Si;

∆Eg,SiGe (Of ) > 1 deﬁnes the eﬀect of basic heterojunction action exp kT due to bandgap shrinkage in the base; and ∆Eg,SiGe (grade)/kT > 1 deﬁnes the eﬀect of bandgap grading 1−exp −∆Eg,SiGe (grade)/kT across the base.

It should be pointed out that equation (3.12) applies in the general case. In the limiting case, where there is no grading, the latter term tends to unity as ∆Eg,SiGe (grade) tends to zero, and the overall expression for collector current is still valid in a much simpliﬁed form. Even though γ¯ < 1 [11], exp(∆Eg,SiGe (Of )/kT ) increases the SiGe HBTs collector current exponentially for a ﬁnite germanium content. For a SiGe HBT having a germanium concentration varying from 4% at the emitter–base junction to 12% with a trapezoidal shape across the base (see ﬁgure 3.5), a collector current enhancement by a factor of 4.5 has been reported [9]. The base current in a bipolar transistor, consists of several components. In the emitter, holes can recombine with electrons at the

Figure 3.5. Uniform (ﬂat), triangle, and trapezoid Ge proﬁles in the base of a SiGe HBT. (After Harame D L et al 1995 IEEE Trans. Electron Devices 42 455–68.)

82

Principle of SiGe HBTs

emitter surface, in the neutral emitter, or in the wide bandgap part of the emitter–base space-charge region. In the narrow bandgap base, electrons can recombine with holes in the narrow bandgap part of the emitter– base space-charge region, or in the neutral base. An additional source of collector and base current consists of electron–hole pairs created by avalanche multiplication or thermal generation in the base–collector spacecharge region. The various base current components can be distinguished by their dependence on emitter–base voltage, base–collector voltage, and temperature. If both base and emitter material have a high minority carrier lifetime, which is usually the case in SiGe HBTs, the base current is dominated by emitter surface recombination current or the current in the neutral emitter. Since the boundary conditions for the injected minority carriers into the emitter remain the same as in the homojunction, the reverse injected hole current can be written as Jp =

qDpe n2ie,Si qVbe /kT e −1 . Nde We

(3.15)

Equation (3.15) assumes a short, uniformly-doped emitter. For emitters with a short minority carrier lifetime, We is replaced by the diﬀusion length Lpe = Dpe τp where Dpe and τp are the respective minority carrier diﬀusivity and lifetime in the emitter region, giving Jp =

qDpe n2ie qVbe /kT e Nde Lpe

(3.16)

where Nde and Lpe are the emitter doping density and hole diﬀusion length, respectively. Equation (3.16) implies that Jp has an ideality factor of unity. The potential barrier for hole injection into the emitter is the same for both the homojunction and the narrow bandgap heterojunction device, which implies that this component of the base current should be identical in the two devices, if they have similar emitters. This has indeed been observed in experimental SiGe HBTs and is evident from ﬁgure 3.6. Auger recombination deals with the heavy doping eﬀects. This bandto-band recombination mechanism occurs at dopant concentrations beyond 1019 cm−3 [13]. One of the main objectives in SiGe HBT design is to lower the base resistance by increasing the base doping concentration. The lower base resistance improves high-frequency performance. In the highly-doped emitter of a BJT, the net eﬀect of Auger recombination is a lower eﬀective lifetime in the emitter, leading to a shortened diﬀusion length and increased base current. In a device simulator this eﬀect is easily included as an extra term in the current continuity equations. Figure 3.6 shows the collector and base currents of a ﬂat-base SiGe HBT (x = 0.2) compared to the corresponding Si homojunction device.

Transit time

83

Figure 3.6. Room temperature Gummel plots of a ﬂat-base SiGe HBT and silicon control device with similar base sheet resistances, and emitter areas, showing the increased collector current due to the narrow bandgap base. (After Prinz E J 1992 Base transport and vertical proﬁle engineering in Si/Si1−x Gex /Si heterojunction bipolar transistors PhD Dissertation Princeton University.)

In the Gummel plot, the collector current of an ideal bipolar transistor should be proportional to eqVbe /kT , corresponding to an inverse slope of approximately 60 mV per decade of collector current at room temperature. The ∼50× increase in the collector current (and the current gain) of the HBT compared to the homojunction transistor is due to the narrower bandgap in the base, since both the devices have the same integrated base dopant concentration. Since the base current of silicon and SiGe HBTs are virtually identical, the current gain enhancement due to germanium incorporation is similar to the collector current enhancement. Therefore, the superior current gain potential of a SiGe HBT can be traded oﬀ for an increased fmax and reduced base resistance, leading to higher power gain, faster switching speed and a lower noise ﬁgure. 3.3.

TRANSIT TIME

Bandgap grading across the base creates a drift electric ﬁeld that accelerates the electron minority carriers through the base. The graded electric ﬁeld reduces the amount of base stored charge per unit collector current. This reduces the energy and time required to move charge in and out of the base during transients. As a result, the base transit time, τb , decreases.

84

Principle of SiGe HBTs

In any bipolar transistor, the base transit time for constant base doping can be written as [10] Wf 2 Wf nie (z) Nb (y)dy Qb τb = dz (3.17) = Ic Dnb (y)n2ie (y) Of Nb (z) z where Qb is the total base stored charge and Ic is the collector current. Putting equation (3.10) into (3.17) and integrating, τb,Si [13,14] and τb,SiGe [9] become: Wb2 τb,Si = (3.18) 2Dnb kT W2 τb,SiGe = ¯ b (3.19) ζDnb ∆Eg,SiGe (grade) −∆Eg,SiGe (grade) kT 1 − exp . × 1− ∆Eg,SiGe (grade) kT Taking the ratio of τb,SiGe /τb,Si gives: kT 2 τb,SiGe (3.20) = ¯ τb,Si ζ ∆Eg,SiGe (grade) −∆Eg,SiGe (grade) kT 1 − exp . × 1− ∆Eg,SiGe (grade) kT For a ﬁnite germanium grading of more than 1% at room temperature, τb,SiGe /τb,Si will be less than 1 and therefore the SiGe HBT base transit time will be shorter than the silicon bipolar. The cut-oﬀ frequency, fT of a bipolar device, as explained in section 3.7, is a function of base transit time, implying that bandgap grading will also increase the usable frequency of operation of the device. An additional beneﬁt of incorporating Ge into the base is a reduction in emitter transit time τe , compared to a silicon BJT. Since τe is inversely proportional to the collector current, for a given base doping proﬁle, the enhancement in τe , is obtained from the inverse of (3.14) as τe,SiGe Jc,Si 1 − e−∆Eg,SiGe (grade)/kT ≈ = . ∆E (grade) ∆Eg,SiGe (0)/kT τe,Si Jc,SiGe e ζ¯γ¯ g,SiGe kT

(3.21)

The emitter transit time can potentially be a limiting factor in HBTs which include a low-doped emitter region to avoid tunnelling current from base to emitter. Such structures are discussed in chapter 4. The eﬀect of base and emitter transit times on ac performance is more fully discussed in section 3.7.

Early voltage 3.4.

85

EARLY VOLTAGE

For analogue circuit applications, a high value of the product of current gain and Early voltage (βVA ) is desirable. There are several physical eﬀects which cause the collector current to increase with collector–emitter voltage for a constant base current. The most important of these is the increase of the collector current caused by a decrease of the width of the neutral base with base–collector reverse bias [15]. Output conductance is a measure of collector current variation with base–collector reverse bias. In ﬁgure 3.8, the base–collector depletion region widens and reduces the neutral base width as the reverse biased base–collector voltage increases, while keeping a ﬁxed emitter–base voltage. Reduction of the neutral base width leads to an increase in the gradient of the injected electron distribution in the p-type base. Since the electron diﬀusion current across the base is directly proportional to this gradient, the collector current will increase. A low output conductance is desirable to achieve invariant output current in low-frequency analogue applications. The Early voltage, VA , an indicator of the extent of base width modulation, can be obtained by extrapolation of the output characteristics. With reference to ﬁgure 3.7, the Early voltage (ignoring recombination in the base) is given by ∂Vce ∂Wb ∂Vce VA ≈ Jc . (3.22) = Jc ∂Jc ∂Wb ∂Jc The rate of change of the neutral base width Wb with respect to the

Figure 3.7. Deﬁnition of the Early voltage VA . The linear parts of the output characteristics of a bipolar transistor are extrapolated to zero collector current.

86

Principle of SiGe HBTs

Figure 3.8. Minority carrier distribution in an npn transistor for increasing base–collector reverse bias voltage in forward active mode. np (x) is the electron concentration in the p-type base. (After Tang Y T 2000 Advanced characteristics and modelling of SiGe HBTs PhD Thesis University of Southampton.)

base–collector voltage, for constant emitter–base voltage, is given by ∂Wb Cjc =− ∂Vbc qNb (Wb )

(3.23)

and the change of the collector current density with respect to the base width is Nb (Wb )/ n2ie (Wb )Dnb (Wb ) ∂Jc (3.24) = −Jc Wb . ∂Wb Nb (x)/ (n2 (x)Dnb (x)) dx 0

ie

For a constant base proﬁle, combining equations (3.23) and (3.24) one gets qn2 (Wb )Dnb (Wb ) Wb VA = ie Nb (x)/ n2ie (x)Dnb (x) dx (3.25) Cjc 0 where n2ie (Wb ) denotes the intrinsic carrier density at the end of the neutral base on the collector side. Combining equation (3.25) with the standard equation for bipolar current gain −1 Wb 2 q p(x)/ nie (x)Dn (x) dx (3.26) β= Jb0 0

Early voltage

87

and assuming p(x) = Nb (x) yields an important ﬁgure-of-merit for bipolar transistors, βVA , given by βVA =

q2 2 nie (Wb )Dn (Wb ) . Jb0 Cjc

(3.27)

The following three points are signiﬁcant: • • •

βVA is a strong function of Ge concentration at the end of the neutral base (base–collector junction); βVA is larger in SiGe than in silicon due to the larger n2io (Wb ) value in SiGe; and to maximize βVA , the base–collector junction capacitance should be as low as possible.

Harame et al [9] showed that Early voltage enhancement of a graded SiGe HBT can be expressed as 1 − exp (−∆Eg,SiGe (grade)/kT ) ∆Eg,SiGe (grade) VA,SiGe . ≈ exp VA,Si kT ∆Eg,SiGe (grade)/kT (3.28) Combining equations (3.28) and (3.14), the enhancement in βVA at constant emitter–base voltage can be shown as βVA,SiGe ≈ γζe∆Eg,SiGe (Of )/kT e∆Eg,SiGe (grade)/kT βVA,Si

(3.29)

which is signiﬁcantly greater than unity for a proﬁle with ﬁnite Ge content. For ﬁnite germanium grading, ∆Eg,SiGe (grade), of more than 1% across the base, τb,SiGe /τb,Si , ratio will be larger than 1. Therefore, grading Ge across the neutral base improves not only base transit time, but also Early voltage. Furthermore, since current gain is essentially enhanced by the diﬀerence in bandgap at the emitter–base junction and Early voltage by Ge grading across the base, respectively, the composite product βVA is signiﬁcantly enhanced by up to two orders of magnitude. Figure 3.9 shows the SiGe/Si ratio for the three parameters of interest—current gain, Early voltage, and the product of current gain times Early voltage [9]. This ﬁgure needs to be interpreted with some care, as the integrated Ge dose across the base has been kept constant in order to provide a meaningful comparison. In this ﬁgure, when ∆Eg,Ge (grade) = 0, a pure Ge box proﬁle of 8.4% Ge is implied, while ∆Eg,Ge (grade) = 125 meV, (the x-axis limit in ﬁgure 3.5), implies a purely triangular proﬁle from 0–18.6% Ge. Any other grading between these limits indicates the corresponding trapezoidal Ge proﬁle. The triangular proﬁle has the largest Early voltage and gain–Early voltage product. The Ge box proﬁle has an

88

Principle of SiGe HBTs

Figure 3.9. Early voltage and current gain Early voltage products. (After Harame et al 1995 IEEE Trans. Electron Devices 42 455–68.)

exponentially increased current gain, by the factor exp(∆Eg,SiGe (Of )/kT ), but the same Early voltage. The βVA product is strongly inﬂuenced by base–collector capacitance Cbc , but there is always a trade-oﬀ between the separate terms. If β is increased, by reducing the base doping, VA will decrease, so it is therefore not desirable to have excessively high current gain. In a SiGe HBT with a box Ge proﬁle, the improvement in βVA is limited by critical thickness considerations. For example, for a base width of about 500 ˚ A, the Matthews–Blakeslee theory predicts a maximum Ge concentration of about 7% corresponding to a bandgap diﬀerence of 55 meV compared to Si. This bandgap diﬀerence translates into ∼5× improvement in the βVA product. In a graded base SiGe HBT, insertion of a very thin Si1−x Gex region between base and collector will reduce base–collector capacitance and increase Early voltage, while leaving the current gain virtually unchanged [16]. The thickness of this Si1−x Gex layer has to be suﬃcient to include the base edge of the base–collector depletion region even at maximum reverse bias Vbc . Since the equilibrium critical thickness decreases with increasing Ge concentration in a strained-Si1−x Gex layer, the improvement possible in the βVA product of a graded-base HBT is greater compared to that of β alone in a box proﬁle HBT. A simple structure to investigate the β versus VA trade-oﬀ in graded base HBTs is a stepped base transistor, where the base consists of two separate p-doped layers with constant bandgap in each layer. Figure 3.10 shows the calculated band diagrams and measured collector current

Early voltage

89

Figure 3.10. Calculated band diagrams and measured collector current characteristics showing the eﬀect of the position of the biggest bandgap region in the base on the output resistance of SiGe HBTs. The devices had an emitter area of 62 × 62 µm. (After Prinz E J 1992 Base transport and vertical proﬁle engineering in Si/Si1−x Gex /Si heterojunction bipolar transistors PhD Dissertation Princeton University.)

characteristics for two stepped-base devices. Both devices had similar current gains because of the similar width and height of the highest barrier for electrons in the base. The output resistance of device in which the narrow gap layer was located at the base–collector junction, however, was vastly increased compared to device which had its narrow gap layer at the emitter–base junction. Prinz and Sturm [16] have experimentally demonstrated βVA products of 168 000 using a two step 14–28% germanium base. State-of-the-art silicon bipolar processes have a βVA product of 6000. The eﬀects of base dopant out-diﬀusion leading to a base–collector

90

Principle of SiGe HBTs

heterojunction barrier on the Early voltage have also been reported [17]. A more complete discussion on the eﬀects of parasitic barriers is given in the following section. 3.5.

HETEROJUNCTION BARRIER EFFECTS

The computed conduction band oﬀset in the silicon to strained-Si1−x Gex heterojunction is small (typically 20 meV) [18]. If a signiﬁcant conduction band oﬀset exists, a reduction in the gain may result. In a heterostructure, compositional grading across the heterojunction may be used to eliminate the conduction band spike. In the case of an Si/SiGe/Si system, the conduction band spike is not a severe problem if the emitter dopant concentration is larger than the base doping concentration, as the band bending appears on the side with lower doping. In an npn transistor any small conduction band spike may be disregarded. However, it is not true for the pnp transistor, as the spike will be large in this case because valence band oﬀsets are much larger than the conduction band oﬀsets. At high current densities or high forward bias, the transport of carriers is strongly inﬂuenced by the potential barrier that develops due to alloy grading potential of the heterojunction. A retrograde Ge proﬁle near the collector junction also creates a barrier to the ﬂow of the minority carriers [19]. Another type of parasitic barrier arises due to the boron out-diﬀusion from the base. Extension of base dopant beyond the Si1−x Gex region occurs during thermal cycling, or improper control of the as-deposited proﬁle [20, 21]. Even small amounts of boron out-diﬀusion from a heavilydoped Si1−x Gex base into the Si emitter and collector cause parasitic barriers in the conduction band which can drastically reduce the collector current enhancement. Shaﬁ et al [22] fabricated a SiGe HBT with a very narrow base width of 214 ˚ A, doped with a boron concentration of 5 × 1019 cm−3 and a Ge concentration of 15%. The width of emitter was 0.3 µm doped with a uniform As concentration 1018 cm−3 , while the doping in the collector was 3 × 1016 cm−3 . The collector current enhancement factor was 13, while the base current was also found to increase sixfold. The authors attributed this increase in base current to a either very low lifetime near the collector region in the base, or a parasitic barrier at the base–collector junction. Shaﬁ et al [23] have also reported the collector current degradation due to out-diﬀusion of boron and creation of parasitic barriers. The minority carrier concentration in the base increases due to the barriers and this will increase the recombination and base current, irrespective of the value of the lifetime of the minority carriers. Out-diﬀusion of boron into the collector results in the formation of a parasitic conduction band barrier, as illustrated in ﬁgure 3.11, where an exponential out-diﬀusion tail region of varying diﬀusion length, LD ,

Heterojunction barrier eﬀects

91

Figure 3.11. Simulation of band diagram and electron concentration for a SiGe HBT with the doping proﬁle of (a). Note the exponential dopant out-diﬀusion tail (diﬀusion length LD ) into the Si collector region. The band diagram (b) shows the parasitic conduction band barrier at the Si1−x Gex /Si interface. (c) and (d) show conduction and valence bands, respectively, at the base–collector junction for various diﬀusion lengths LD . (e) The parasitic conduction band barrier causes a deviation from the triangular electron proﬁle in the base leading to increased minority carrier charge storage in the base even as Ic decreases. (After Prinz E J 1992 Base transport and vertical proﬁle engineering in Si/Si1−x Gex /Si heterojunction bipolar transistors PhD Dissertation Princeton University.)

92

Principle of SiGe HBTs

Figure 3.12. Simulation of normalized collector current enhancement versus inverse temperature for various values of LD . (After Prinz E J 1992 Base transport and vertical proﬁle engineering in Si/Si1−x Gex /Si heterojunction bipolar transistors PhD Dissertation Princeton University.)

extending into the Si collector region, has been superimposed upon an Si0.8 Ge0.2 base with a constant doping of 1019 cm−3 . Even a small amount of boron out-diﬀusion (LD ∼ 30 ˚ A) causes a large parasitic barrier for electrons at the base–collector junction (barrier height ∼85 meV), as shown in ﬁgure 3.11(c). This barrier leads to increased minority carrier storage in the base signiﬁcantly impeding electron diﬀusion through the base, increasing neutral base recombination and degrading the collector current, as shown in ﬁgure 3.11(e). The parasitic barriers thereby reduce the potential enhancement in current gain once the diﬀusion length exceeds 11 ˚ A, as shown in ﬁgure 3.12. With increased minority carrier charge storage in the base, as shown in ﬁgure 3.11(e), the parasitic barriers increase the base transit time, τb , because of the increase in electron charge and the decrease in collector current Ic , as the ideal triangular electron proﬁle for electron concentration in the base is replaced by a trapezoidal proﬁle. This eﬀect, demonstrated by simulation, was experimentally observed by Pruijmboom et al [24] in high-frequency measurements of SiGe HBTs. 3.5.1.

Eﬀect of undoped spacer layers

The deleterious eﬀect of base dopant out-diﬀusion from the Si1−x Gex base into silicon emitter and collector can be limited by inserting thin undoped Si1−x Gex layers on both sides of the base [20, 21]. These

Heterojunction barrier eﬀects

93

Figure 3.13. Doping proﬁle of HBT structure with undoped SiGe spacer layers. (After Prinz E J 1992 Base transport and vertical proﬁle engineering in Si/Si1−x Gex /Si heterojunction bipolar transistors PhD Dissertation Princeton University.)

Figure 3.14. Simulated boron doping proﬁle (SUPREM III) for various anneals. If the Si1−x Gex layer thickness is increased by adding 150 ˚ A thick intrinsic Si1−x Gex spacer layers on both sides of the base, the diﬀused boron proﬁle is still contained inside the Si1−x Gex layer for a temperature below 800 ◦ C. (After Prinz E J 1992 Base transport and vertical proﬁle engineering in Si/Si1−x Gex /Si heterojunction bipolar transistors PhD Dissertation Princeton University.)

94

Principle of SiGe HBTs

spacers have to be wide enough to contain the tail regions of the boron out-diﬀusion. Inevitably, this change increases the overall width of the strained-Si1−x Gex layer, making the structure more likely to relax by forming misﬁt dislocations at the interface. To demonstrate the eﬀect of thermal cycle on SiGe HBT performance, consider the device structure shown in ﬁgure 3.13 with a base doping of 5×1019 cm−3 , a base width of 300 ˚ A and box Ge proﬁle (x = 0.18), leading to a base sheet resistance of ∼800 Ω/square. The 1017 cm−3 collector doping represents a trade-oﬀ between breakdown voltage BVceo and the onset of high level injection in the collector (Kirk eﬀect) [25, 26]. If the base is doped above 2 × 1018 cm−3 a lightly-doped n-Si spacer has to be inserted between base and emitter to prevent tunnelling leakage in the emitter–base junction [27]. Figure 3.14 shows calculated doping proﬁles for a 10 min anneal at various temperatures and ﬁgure 3.15 the corresponding band diagrams for a structure (a) without and (b) with 150 ˚ A thick spacers. Note the absence of parasitic barriers in the device with spacers up to an annealing temperature of 850 ◦ C. However, increase in the thermal budget of the process leads to a strong degradation of the collector current. The intrinsic spacers, therefore, substantially improve the tolerance of the device structure for the thermal budget of the process. These simulations show that in the design of a SiGe HBT process, intrinsic Si1−x Gex spacer layers on both sides of the base, should be considered according to the thermal budget of the process. The critical thickness limitation of the strained-Si1−x Gex layer, however, limits the total permissible thickness of the base including the spacer layers. 3.6.

HIGH LEVEL INJECTION

In a bipolar transistor, two diﬀerent type of high level injection (HLI) can occur. The ﬁrst occurs in the base region from the large number of electrons injected at high emitter–base voltage. The eﬀect was analysed for Si BJTs by Webster [28]. Since the reverse injected base current retains an eqVbe /kT dependence, the current gain falls oﬀ inversely proportional to Ic [3]. In general, this eﬀect does not appear in HBTs if the base dopant concentration is high. The other HLI eﬀect occuring in the collector region is the Kirk eﬀect [25] which arises as the base–collector depletion width spreads into the collector at high current levels due to electron velocity saturation. The eﬀect of velocity saturation at large collector current densities depends on the relative base and collector doping concentrations. Forward bias of the internal base–collector junction increases the base current due to hole injection into the collector and results in a rapid drop in dc current gain. In a SiGe HBT, the valence band oﬀset prevents the injection of holes into the collector and subsequently the collector current saturates at densities

High level injection

95

Figure 3.15. Simulated band diagrams for a structure (a) without and (b) with 150 ˚ A thick spacers for a 10 min anneal at diﬀerent temperatures. (After Prinz E J 1992 Base transport and vertical proﬁle engineering in Si/Si1−x Gex /Si heterojunction bipolar transistors PhD Dissertation Princeton University.)

less than the classical Kirk eﬀect. In addition, excess charge is stored in the base, which results in decreased current gain and fT . Cottrell and Yu [29] and Yu et al [30] attempted to model the valence band barrier eﬀects at high collector current densities for a SiGe HBT. The authors noted that the valence band barrier eﬀect appears at high current densities for npn and at all current densities for pnp devices. Other researchers [31, 32] examined the eﬀect of two-dimensional lateral carrier diﬀusion on the gain. In this case, the electrons accumulating in the

96

Principle of SiGe HBTs

base–collector space-charge layer (SCL) diﬀuse laterally before collection, resulting in an increased eﬀective collector area. Recently, a comprehensive investigation of the impact of the Ge proﬁle shape as well as the scaling of base and collector doping on high injection heterojunction barrier eﬀects has been described [33] over a wide temperature range. The onset of the Kirk eﬀect in a SiGe HBT was shown to expose the Si/SiGe heterojunction which blocks the ﬂow of holes into the collector under the Kirk eﬀect and hence induces an electron barrier in the conduction band. The combined eﬀect reduces collector current, increases base current and rapidly degrades fT . Various strategies to simultaneously reduce the impact of the conduction band barrier, and increase fmax and BVceo were discussed. Experimental evidence of the valence band barrier in a pnp SiGe HBT has been conﬁrmed [19, 34, 35]. The knee current (at which Ic × β is maximum) which increases with applied base–collector bias, is found to be much stronger than can be explained by the Kirk eﬀect. Similarly, the graph of unity gain cut-oﬀ frequency fT versus collector current density also shows a strong dependence on the base–collector bias. From the experiments, the knee current density was found to be much less than the current density calculated by accounting solely for velocity saturation. 3.7.

HIGH-FREQUENCY FIGURES-OF-MERIT

For high-frequency ac operation, bipolar transistors are often assessed according to two ﬁgures-of-merit. The ﬁrst is known as the unity gain cut-oﬀ or transition frequency, fT . The second is known as the maximum oscillation frequency. While both ﬁgures-of-merit may not necessarily be suitable for all applications of SiGe HBTs, both are still widely quoted, particularly in device research publications. 3.7.1.

Unity gain cut-oﬀ frequency, fT

fT is deﬁned as the frequency at which the common emitter short circuit ac current gain is unity [13]. It is related physically to the bipolar device, as the total delay for the minority carrier across the device from emitter to collector, τec [3]. The total delay consists of the minority carrier stored charge delay and the junction capacitance charging delay, and is often related to fT through the equation: fT =

1 2πτec

(3.30)

where the total transit time τec comprises of a number of components: τec = τe + τeb + τb + τbc + τje + τc .

(3.31)

High-frequency ﬁgures-of-merit

97

The major components, due to minority carrier stored charge, are τe for the neutral emitter and τb for the neutral base region (as previously discussed in section 3.3). The term τeb represents minority carrier transit time in the emitter–base depletion region, and is often small enough to be included in the emitter transit time term. The transit time τb , the delay due to the excess minority carrier storage in the base, is generally the most signiﬁcant term in equation (3.31) and the relevant expressions for a SiGe HBT and the eﬀect of Ge grading have been given in equations (3.19)–(3.20). The delay term τbc is known as the collector depletion layer transit time. It can be approximated as [13, 36] τbc =

Wjc 2vscl

(3.32)

where Wjc is the base–collector depletion layer width, vscl is the carrier scattering limited velocity which is approximately equal to 1×107 cm s−1 at room temperature for silicon [37]. For high-speed devices, as the base width is consistently scaled down, τb reduces, and τe and τbc become progressively more signiﬁcant. The delay term τje is the total charging time associated with emitter– base and base–collector depletion layers and is given by [3] τje =

kT (Cje + Cjc ) qIc

(3.33)

where Cje and Cjc are the emitter–base and the base–collector depletion capacitances. As the collector current increases, it is often assumed that this transit time component becomes negligible. However, for low power devices, the eﬀect of low Ic on τje becomes more signiﬁcant, emphasizing very clearly the importance of minimizing the junction capacitances Cje and Cjc . The delay term τc is the collector charging time [3] τc = Rc Cjc .

(3.34)

In a well-designed transistor, Rc is usually quite small and therefore τc is usually not very signiﬁcant. By combining all equations, fT can be conveniently formulated as 1 fT = 2π

kT Wb2 Wjc (Cje + Cjc ) + + τe + τeb + + Rc Cjc qIc αDnb 2vscl

−1 .

(3.35) Figure 3.16 shows the typical variation of fT with collector current. From equation (3.33), it is clear that τje is dominant at low collector current, and therefore fT tends to increase with increase in Ic . However, the inﬂuence of τje reduces drastically as the collector current continues to increase. At

98

Principle of SiGe HBTs

Figure 3.16. Variation of fT with collector current in a SiGe HBT.

peak fT , τe , τb and τbc are usually the dominant terms for an optimal transistor design [13]. Therefore, to improve the peak value of fT , all three terms need to be minimized. Eventually high injection occurs and the base transit time increases at high collector current, causing the reduction in fT as shown in ﬁgure 3.16. 3.7.2.

Maximum oscillation frequency, fmax

The unity gain cut-oﬀ frequency provides a good indication of the intrinsic delay associated with a bipolar transistor. However, it is not a realistic parameter for a circuit environment, as it assumes that the output is short circuited. In addition, it is independent of base resistance and hence does not take the base resistance base–collector depletion capacitance time constant into account. These are important parameters for determining the transient behaviour of bipolar circuits. Therefore, another more practical and widely accepted ﬁgure-of-merit, fmax , is commonly used, which characterizes the power transfer in and out of the bipolar device. fmax is deﬁned as the frequency at which the unilateral power gain becomes unity. Here the output is essentially isolated from the input by an appropriate external matching circuit comprising reactive and resistive components. The load that it drives is also assumed to be conjugately matched to the transistor output impedance. It can be shown [38] that: fmax =

fT 8πCjc Rb

(3.36)

Breakdown voltage, BVceo

99

where Rb is the base resistance. Equation (3.36) shows that it is not suﬃcient to obtain a high value of fT , by decreasing base width, but that base resistance and base–collector capacitance must also be minimized. However, as base width decreases rapidly to achieve high fT , Rb will increase unless the doping is increased. To counter that eﬀect, the base needs to be more highly doped, which means that emitter doping has to be lowered to prevent emitter–base junction tunnelling for very high base doping levels. The increased current gain capability of a SiGe base enables lowering of emitter doping without jeopardizing suﬃcient current gain. An alternative ﬁgure-of-merit, the ECL gate delay (see section 4.7.3) has been used to characterize the eﬀects of transistor parameters at high frequency [39]. Unlike the frequencies fT and fmax , there is no standard expression for the switching time or the propagation delay. The gate delay depends not only on the intrinsic characteristics of the transistor but also the circuit conﬁguration and the values of load resistance and capacitance. In all cases, base resistance and base–collector capacitance appear in the expressions. Even though fmax does not accurately represent the device performance at high frequencies, the qualitative eﬀect of reducing base resistance and base–collector capacitance is apparent. A further discussion on the computational aspects of determining the various components of fT from device simulations will be presented in chapter 5. 3.8.

BREAKDOWN VOLTAGE, BVCEO

Although several breakdown voltages are deﬁned for a bipolar transistor, the most important is the collector–emitter breakdown voltage, BVceo , as it determines the maximum supply voltage that can be applied. The collector–emitter breakdown is limited by two diﬀerent reverse bias junction breakdown mechanisms: Zener and avalanche. Zener breakdown occurs when both sides of a junction have high dopant concentrations. Avalanche breakdown occurs when a large electric ﬁeld appears across the depletion region causing an impact ionization and generation of electron–hole pairs. BVceo , limited by avalanche breakdown, occurs when the product of the avalanche multiplication factor and dc current gain approaches unity. For design purposes it is often approximated by [40] BVceo

BVcbo √ m β

(3.37)

where BVcbo is the base–collector breakdown voltage with emitter opencircuited and m ranges from 2–3 for silicon [41]. In general, the optimization of breakdown voltages for a homojunction transistor and an HBT does not diﬀer. However, extension of the Ge proﬁle into the collector region to avoid the parasitic heterojunction barriers may lead to increased impact ionization. But simulations of carrier energy

100

Principle of SiGe HBTs

seem to indicate that impact ionization is more likely to occur deeper into the collector than originally thought [42]. Therefore, a narrow bandgap Si1−x Gex -base may not aﬀect the breakdown voltage. A trade-oﬀ exists between the breakdown voltage and the collector velocity saturation eﬀects. Increases in breakdown voltage for both emitter–base and base–collector junctions have been obtained by placing lightly-doped spacers on both sides of the heavily-doped base without incurring collector velocity saturation eﬀects [43–45]. 3.9.

SUMMARY

The objective of this chapter has been to describe the basic physics of SiGe HBTs. Use was made of energy band diagrams in deriving the expression for collector current in the most general case of a graded base SiGe HBT. It was evident that signiﬁcant enhancement in current gain, base transit time and Early voltage is possible with the incorporation of germanium in the base region. The way in which the resultant reduction of emitter and base transit times leads to a corresponding enhancement in high-frequency performance measures such as fT and fmax was clearly indicated. The onset of a parasitic conduction band barrier at the base– collector junction through out-diﬀusion of boron from the base was shown to be undesirable, since it increases minority carrier storage in the base, and reduces both collector current and fT . Consequently, the advantage in use of thin undoped SiGe spacer layers between base and emitter and base and collector was discussed.

BIBLIOGRAPHY [1] Shockley W 1951 US Patent Speciﬁcation 2569347 [2] Kroemer H 1957 Theory of a wide-gap emitter for transistors Proc. IRE 45 1535–7 [3] Sze S M 1981 Physics of Semiconductor Devices 2nd edn (New York: Wiley) [4] Slotboom J W and de Graaﬀ H C 1976 Measurement of bandgap narrowing in Si bipolar transistors Solid-State Electron. 19 857–62 [5] Kroemer H 1982 Heterojunction bipolar transistors and integrated circuits Proc. IEEE 70 13–25 [6] Vaidyanathan M and Roulston D J 1995 Eﬀective base–collector time constants for calculating the maximum oscillation frequency of bipolar transistors Solid-State Electron. 38 509–16 [7] Vaidyanathan M and Pulfrey D L 1999 Extrapolated fmax of heterojunction bipolar transistors IEEE Trans. Electron Devices 46 301–9 [8] Tang Y T 2000 Advanced characteristics and modelling of SiGe HBTs PhD Thesis University of Southampton

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[9] Harame D L, Comfort J H, Cressler J D, Crabbe E F, Sun J Y-C, Meyerson B S and Tice T 1995 Si/SiGe epitaxial-base transistors—part I: materials, physics and circuits IEEE Trans. Electron Devices 42 455–68 [10] Kroemer H 1985 Two integral relations pertaining to the electron transport through a bipolar transistor with a nonuniform energy gap in the base region Solid-State Electron. 28 1101–3 [11] Slotboom J W, Streutker G, Pruijmboom A and Gravesteijn D J 1991 Parasitic energy barriers in SiGe HBTs IEEE Electron Device Lett. 12 486–8 [12] Kay L E and Tang T-W 1991 Monte Carlo calculation of strained and unstrained electron mobilities in Si1−x Gex using an improved ionizedimpurity model J. Appl. Phys. 70 1483–1488, 1991. [13] Ashburn P 1988 Design and Realization of Bipolar Transistors (Chichester: Wiley) [14] Lindmayer J and Wrigley C 1961 The high injection level operation of drift transistors Solid-State Electron. 2 79–84 [15] Early J M 1952 Eﬀects of space-charge layer widening in junction transistors Proc. IRE 40 1401–6 [16] Prinz E J and Sturm J C 1991 Current gain-Early voltage products in heterojunction bipolar transistors with nonuniform base bandgaps IEEE Electron Device Lett. 12 691–3 [17] Prinz E J and Sturm J C 1991 Analytical modelling of current gain-Early voltage products in Si/Si1−x Gex /Si heterojunction bipolar transistors IEEE IEDM Tech. Dig. pp 853–6 [18] People R 1986 Physics and applications of Gex Si1−x /Si strained layer heterostructures IEEE J. Quantum Electron. 22 1696–710 [19] Harame D L, Stork J M C, Meyerson B S, Crabbe E F, Scilla G J, de Fresart E, Megdanis A C, Stanis C L, Patton G L, Comfort J H, Bright A A, Johnson J B and Furkay S S 1990 30 GHz polysilicon-emitter and single-crystal-emitter graded SiGe-base pnp transistors IEEE IEDM Tech. Dig. 33–6 [20] Prinz E J, Garone P M, Schwartz P V, Xiao X and Sturm J C 1989 The eﬀect of base-emitter spacers and strain-dependent densities of states in Si/Si1−x Gex /Si heterojunction bipolar transistors IEEE IEDM Tech. Dig. pp 639–42 [21] Prinz E J, Garone P, Schwartz P, Xiao X and Sturm J 1991 The eﬀects of base dopant out-diﬀusion and undoped Si1−x Gex junction space layers in Si/Si1−x Gex /Si heterojunction bipolar transistors IEEE Electron Device Lett. 12 42–4 [22] Shaﬁ Z A, Gibbings C J, Ashburn P, Post I R C, Tuppen C G and Godfrey D J 1991 The importance of neutral base recombination in compromising the gain of Si/SiGe heterojunction bipolar transistors IEEE Trans. Electron Devices 38 1973–6 [23] Shaﬁ Z A, Ashburn P, Post I R C, Robbins D J, Leong W Y, Gibbings C J and Nigrin S 1995 Analysis and modelling of base currents of Si/Si1−x Gex heterojunction bipolar transistors fabricated in high and low oxygen content material J. Appl. Phys. 78 2823–9 [24] Pruijmboom A, Slotboom J W, Gravesteijn D J, Fredriksz C W,

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[25] [26] [27]

[28] [29] [30] [31] [32] [33] [34]

[35]

[36] [37] [38] [39] [40]

Principle of SiGe HBTs van Gorkum A A, van de Heuvel R A, van Rooij-Mulder J M L, Streutker G and van de Walle G F A 1991 Heterojunction bipolar transistors with SiGe base grown by molecular beam epitaxy IEEE Electron Device Lett. 12 357–9 Kirk C T 1962 A theory of transistor cut-oﬀ frequency fT falloﬀ at high current densities IRE Trans. Electron Devices 9 164–74 Poon H C, Gummel H K and Scharfetter D L 1969 High injection in epitaxial transistors IEEE Trans. Electron Devices 16 455–8 Matutinovic-Krstelj Z, Prinz E J, Schwartz P V and Sturm J C 1991 Reduction of p+ –n+ junction tunnelling current for base current improvement in Si/SiGe/Si heterojunction bipolar transistors IEEE Electron Device Lett. 12 163–5 Webster W M 1954 On the variation of junction-transistor current ampliﬁcation with emitter current Proc. IRE 42 914–20 Cottrell P and Yu Z 1990 Velocity saturation in the collector of Si/Gex Si1−x /Si HBTs IEEE Electron Device Lett. 11 431–3 Yu Z, Cottrell P E and Dutton R 1990 Modelling and simulation of high-level injection behaviour in double heterojunction bipolar transistors IEEE BCTM Proc. pp 192–4 Gao G-B, Fan Z-F and Morkoc H 1991 Analysis of cut-oﬀ frequency roll-oﬀ at high currents in SiGe double-heterojunction bipolar transistors Appl. Phys. Lett. 58 2951–3 Mazhari B and Morkoc H 1991 Eﬀect of collector-base valence-band discontinuity on Kirk eﬀect in double-heterojunction bipolar transistors Appl. Phys. Lett. 59 2162–4 Joseph A J, Cressler J D, Richey D M and Niu G 1999 Optimization of SiGe HBTs for operation at high current densities IEEE Trans. Electron Devices 46 1347–54 Harame D L, Stork J M C, Meyerson B S, Crabbe E F, Patton G L, Scilla G J, de Fresart E, Bright A A, Stanis C, Megdanis A C, Manny M P, Petrillo E J, Dimeo M, McIntosh R C and Chan K K 1990 SiGe-base pnp transistors fabricated with n-type UHV/CVD LTE in a ‘No Dt ’ process Dig. Symp. on VLSI Technol. pp 47–8 Harame D L, Meyerson B S, Crabbe E F, Stanis C L, Cotte J, Stork J M C, Megdanis A C, Patton G L, Stiﬄer S, Johnson J B, Warnok J, Comfort J H and Sun J-C 1991 55 GHz polysilicon-emitter graded SiGe-base pnp transistor Proc. Symp. VLSI Tech. pp 71–2 Meyer R G and Muller R S 1987 Charge-control analysis of the collector-base space-charge-region contribution to bipolar transistor time constant τt IEEE Trans. Electron Devices 34 450–2 Smith P, Inoue M and Frey J 1980 Electron velocity in Si and GaAs at very high electric ﬁelds Appl. Phys. Lett. 37 797–8 Pritchard R L 1955 High-frequency power gain of junction transistors Proc. IRE 43 1075–85 Asbeck P M 1990 Bipolar transistors High Speed Semiconductor Devices ed S M Sze (New York: Wiley) pp 335–97 Werner Jr R M and Grung B 1983 Transistors: Fundamentals for the Integrated-Circuit Engineering (New York: Wiley)

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[41] Roulston D J 1990 Bipolar Semiconductor Devices (Singapore: McGrawHill) [42] Patton G L, Stork J M C, Comfort J H, Crabbe E F, Meyerson B S, Harame D L and Sun J Y-C 1990 SiGe-base heterojunction bipolar transistors: physics and design issues IEEE IEDM Tech. Dig. pp 13–16 [43] Comfort J H, Patton G L, Cressler J D, Lee W, Crabbe E F, Meyerson B S, Sun J Y-C, Stork J M C, Lu P-F, Burghartz J N, Warnock J, Scilla G, Toh K-Y, D’Agostino M, Stanis C and Jenkins K 1990 Proﬁle leverage in self-aligned epitaxial Si or SiGe base bipolar technology IEEE IEDM Tech. Dig. pp 21–4 [44] Tang D D and Lu P F 1989 A reduced-ﬁeld design concept for high performance bipolar transistors IEEE Electron Device Lett. 10 67–9 [45] Lu P F, Comfort J H, Tang D D, Meyerson B and Sun J Y-C 1990 The implementation of a reduced-ﬁeld proﬁle design for high-performance bipolar transistors IEEE Electron Device Lett. 11 336–8

Chapter 4 DESIGN OF SIGE HBTS

As semiconductor technology continues to evolve, numerical modelling of the electrical behaviour of advanced devices has become vital. Numerical device modelling based on the self-consistent solution of the fundamental semiconductor equations dates back to the famous work of Gummel in 1964 [1]. In Gummel’s one-dimensional (1D) discretization, the Poisson equation and the current continuity equations are decoupled and solved sequentially until convergence. Gummel’s approach was later extended by de Mari [2] and applied to transient simulations of a 1D p–n junction. A very important breakthrough in the discretization of the current transport equations was reported by Scharfetter and Gummel in 1969 [3]. The Scharfetter–Gummel (SG) discretization scheme has since been used by all important device simulation programs. During the 1970s and 1980s, several 1D and 2D programs were developed, and made freely available to the research community. Examples include SEDAN [4] for 1D simulations, MINIMOS [5] for 2D MOS transistor simulations, BAMBI [6] for arbitrary semiconductor structures and PISCES [7], a 2D ﬁnite-element simulator, which rapidly became an industry standard and formed the basis of future commercial products such as Silvaco–ATLAS [8], Avant–Medici [9] and PISCES–2ET [10]. In 1977, Sutherland and Hauser [11] were the ﬁrst to use numerical techniques to analyse heterojunction devices. They showed that the basic formulation for homojunction devices could easily be generalized to include the eﬀects of a position-dependent band structure. The formulation was further developed [12] to include ﬁeld-dependent mobility to ﬁt the steadystate velocity ﬁeld characteristics, and later expanded to treat degenerate semiconductors via Fermi–Dirac statistics [13–15]. HQUPETS [16] was an early 2D simulation tool developed for SiGe HBTs, and has been extensively used for device design [17]. Several advanced 1D simulators, speciﬁc to SiGe HBTs, such as a simulator for cryogenic research and silicon–germanium bipolar device optimization 104

Design of SiGe HBTs

105

(SCORPIO) [18] and PROSA [19], have been reported. Although the drift–diﬀusion (DD) model is the most widely used and understood tool for semiconductor device simulation, it unfortunately fails to predict non-stationary transport eﬀects. As a derivative of the Boltzmann transport equation (BTE), it also fails to reﬂect the quantum mechanical nature of carrier transport. The continuous push toward smaller devices has led to a need to address these shortcomings, and to the development of more sophisticated physical models, such as the hydrodynamic and energy transport models [20, 21], the spherical harmonics expansion method [22] and the Monte Carlo technique [23–27]. Unfortunately, since the Monte Carlo method involves keeping statistics on a large number carriers undergoing random collisions, it is very expensive in terms of computer time. The simulation of a complete transistor requires tracking a prohibitive number of carriers in order to attain statistical signiﬁcance. This typically limits the Monte Carlo technique to use an aid in studying only part of the transistor, for instance the emitter–base junction. In the hydrodynamic or energy transport model, the ﬁrst three moments of the BTE are taken, yielding the particle, momentum and energy conservation equations [20]. To solve these equations, it is generally necessary to make many assumptions (for instance invocation of the relaxation time approximation). As the drift–diﬀusion model is pushed to its limits, more people are trying the hydrodynamic method of solution. A complete hierarchy of approaches and analyses has been reviewed by Ravaioli [28]. However, the increased rigour of such models comes at the expense of increased CPU time, so for the simulations reported in this book we conﬁne our discussion almost exclusively to the drift–diﬀusion model. Regardless of the modelling methodology used, the ultimate responsibility will always rest on the user of the simulator to intelligently interpret the results and know when the assumptions inherent to the method are being violated. Otherwise, as was pointed out by Tang and Laux [29], ‘. . . computationally sophisticated 2D or even 3D device simulations are rendered merely expensive, and perhaps misleading, curveﬁtting programs’. The aim of this chapter is to give some insight into the formulation of a physical device model for a SiGe HBT and to show how it can be applied for HBT transistor design. The model equations account for the position-dependent variation of energy bandgap, the dependence of mobility on diﬀerent scattering mechanisms, carrier velocity saturation, doping-dependent carrier lifetime and heavy doping eﬀects. The resulting HBT model corresponds closely to that implemented in the Silvaco–ATLAS device simulator [8], which has been used in a number of the examples considered. A number of studies are presented where model prediction is compared to measured data.

106 4.1.

Design of SiGe HBTs DEVICE MODELLING

Physically based device simulation predicts the electrical characteristics associated with a speciﬁed physical structure and bias conditions. This is achieved by mapping the structure onto a two-dimensional or threedimensional grid consisting of a number of grid points called nodes. By applying a set of partial diﬀerential equations, derived from Maxwell’s equations to this grid, the transport of carriers can be simulated. By speciﬁcation of appropriate boundary conditions, dc, ac and transient modes of operation can be modelled. Physical simulation has two important characteristics. It is much quicker and cheaper than performing experiments. In addition it provides information that is diﬃcult or impossible to measure. The main drawback is that all the relevant physics must be incorporated into the simulator. The user must specify the problem to be solved by deﬁning: • • •

the physical structure; the physical models; and the bias conditions for which electrical characteristics are required.

A basic requirement for a successful physical simulation of a semiconductor device is a mathematical model describing its operation. The model is characterized by a set of fundamental equations which link the electrostatic potential and the carrier densities within some predeﬁned simulation domain. These equations are derived from Maxwell’s laws and consist of Poisson’s equation and the continuity equations for electrons and holes. Poisson’s equation relates variations in electrostatic potential to the space-charge density and is given by, ∇ · (∇ψ) = −q p − n + ND+ − NA− − ρs (4.1) where ψ is the electrostatic potential, is the local dielectric permittivity, q is the charge of an electron, p and n are the hole and electron concentrations, ND and NA are the ionized donor and acceptor impurity concentrations and ρs is the surface charge density. The continuity equations, which describe the way that electron and hole carrier densities evolve as a result of transport processes, generation and recombination processes, are given by, 1 ∂n = ∇ · J5n + (G − R) ∂t q

(4.2)

1 ∂p = − ∇ · J5p + (G − R) ∂t q

(4.3)

where Jn and Jp are the electron and hole current densities, and G and R are the generation and the recombination rates, respectively. The above

Device modelling

107

equations provide the general framework for device simulation. However, further secondary equations are necessary to specify particular physical models for current density, generation recombination rates. The current density equations are usually obtained by applying approximations and simpliﬁcation to the BTEs. These assumptions can result in a number of possible transport models such as the drift–diﬀusion model [30], the energy balance and the hydrodynamic models [20]. The choice of transport model can impact on the choice of generation and recombination model. By far the simplest and most commonly used model in device simulation is the drift–diﬀusion model. Until recently this model was adequate for nearly all semiconductor devices but it tends to become less accurate for small feature sizes [28]. In the drift–diﬀusion model, the current densities are expressed in terms of quasi-Fermi levels Φn and Φp as J5n = −qµn n∇φn

(4.4)

J5p = −qµp p∇φp

(4.5)

where µn and µp are the electron and hole mobilities. Using Boltzmann approximations, the quasi-Fermi levels may be related to the carrier concentrations and the potential as given by q (Ψ − φn ) n = nie exp (4.6) kTL −q (Ψ − φp ) p = nie exp (4.7) kTL where nie is the eﬀective intrinsic carrier concentration and TL is the lattice temperature. These two equations may then be rewritten as Φn = ψ −

n kTL ln q nie

(4.8)

p kTL ln . (4.9) q nie By substituting these equations into the current density expressions, one obtains Φp = ψ +

J5n = qDn ∇n − qnµn ∇Ψ − µn nkTL ∇ (ln(nie ))

(4.10)

J5p = −qDp ∇p − qpµp ∇Ψ + µp pkTL ∇ (ln(nie ))

(4.11)

where the last term accounts for the gradient in the eﬀective intrinsic carrier concentration, taking into account bandgap narrowing eﬀects. Eﬀective electric ﬁelds are given by kTL 5 En = −∇ ψ + (4.12) ln nie q

108

Design of SiGe HBTs

kTL ln nie . E5p = −∇ ψ − q

(4.13)

From the above and using Einstein relationships, the familiar drift–diﬀusion expressions are as follows: J5n = qµn E5n + qDn ∇n

(4.14)

J5p = qµp E5p − qDp ∇p.

(4.15)

In the case of Boltzmann statistics, Dn and Dp are given by Dn =

kTL µn q

(4.16)

Dp =

kTL µp . q

(4.17)

In the case of the energy balance (EB) model, a higher-order solution to the generalized BTE is necessary to include an additional coupling of the current density to the carrier temperature (energy). Then the current density and energy ﬂux densities are expressed as J5n = qDn ∇n − µn n∇Ψ + qnDnT ∇Tn kδn 5 Jn Tn S5n = −Kn ∇Tn − q

(4.18)

J5p = qDp ∇p − µp p∇Ψ + qpDpT ∇Tp kδp 5 Jp Tp S5p = −Kp ∇Tp − q

(4.20)

(4.19)

(4.21)

where Kn,p and δn,p are respective transport coeﬃcients for electrons and holes that depend on the corresponding carrier temperatures Tn and Tp . Sn and Sp are the ﬂux of energy (or heat) from the carrier to the lattice. Full details of the formulation are given in [31]. 4.2.

NUMERICAL METHODS

Several diﬀerent numerical methods can be used to solve the semiconductor equations. In general, there are three approaches: decoupled (Gummel method), fully coupled (Newton method) or a combination method. The decoupled method will solve for each unknown in turn keeping other variables constant, repeating the process until a stable unchanging solution is achieved. Fully coupled techniques, such as the Newton method, solve the total system of unknowns together. The combined method will only solve some of the equations fully coupled. The Newton method is the preferred

Numerical methods

109

method as it oﬀers quadratic convergence, provided a suitable initial guess can be estimated. Because of this constraint, it is always advisable to use small incremental changes to the applied voltage. In performing a simulation, the device starts with zero bias on all electrodes. Solutions are obtained by stepping the bias on electrodes from this initial equilibrium condition, using small steps in voltage. Once a solution is obtained, the current ﬂowing through each electrode is calculated by numerical integration. Internal quantities, such as carrier distributions and electric ﬁeld throughout the device, can then be computed or presented graphically. There are several ways to predict the small-signal and large-signal high-frequency properties of semiconductor devices. A review of these diﬀerent techniques has been given by Laux et al [32]. Frequency domain perturbation analysis is used to calculate the small-signal characteristics, while Fourier analysis is required for a large-signal response. In ATLAS, frequency domain perturbation of a dc solution can be used to calculate small-signal characteristics at any frequency. Variables are represented as the sum of a known dc component and an unknown sinusoidal ac component. The semiconductor equations are expanded with diﬀerentiation in time becoming equivalent to multiplication by jω. The dc solution is subtracted, and what remains is a complex linear system whose unknowns are the ac components. Solving this linear system gives the small-signal y-parameters. If the Newton method is used for the dc solution, then the Jacobian matrix associated with the dc operating point can be used directly in the small-signal analysis without recomputation. If the semiconductor device is treated as a two port network, with deﬁned input and output ports, then knowledge of the y-parameters permits all other small-signal parameters to be calculated. The advantage of this approach is that the determination of y-parameters is based solely on the physical structure, and hence does not rely on any predeﬁned lumped element equivalent circuit model. These y-parameters can then be used to ﬁnd diﬀerent power gains [33]. Among the various power gains described so far in the literature several, such as maximum available gain (MAG), maximum stable gain (MSG) and maximum available unilateral gain (MAUG), have found widespread use. Additionally, a ﬁgure-of-merit that has been used extensively for microwave characterization is Mason’s invariant U (or Mason’s gain). These quantities are calculated from the measured small-signal scattering parameters because of the ease of measurement at high frequencies. All the above mentioned gains can be conveniently expressed in y-parameters as follows: y21 M SG = (4.22) y12

110

Design of SiGe HBTs y21 k − k2 − 1 MAG = y12

(4.23)

where 2Re(y11 )Re(y22 ) − Re(y12 y21 ) |y12 y21 |

(4.24)

|y21 − y12 |2 4[Re(y11 )Re(y22 ) − Re(y12 )Re(y21 )]

(4.25)

k= U=

MAU G =

|y21 |2 . 4Re(y11 )Re(y22 )

(4.26)

Maximum available gain is obtained when both input and output are simultaneously conjugately matched. MAG exists only when the device is unconditionally stable when k > 1. As can be seen from equations (4.25) and (4.26), U equals MAUG only if the device is unilateral, i.e., y12 = 0. MAG and MSG are equal to each other once the device is unconditionally stable. The frequency at which MAG becomes unity is often deﬁned as fmax . However, a full discussion on the interpretation of fmax is given in [34]. Since common-emitter microwave transistors may have power gain with no impedance transformation, they can have useful gain when inserted into a 50 Ω system. This gain is identical to |s21 |2 . ATLAS has an option to easily convert y-parameters obtained from ac analysis, to s-, z- or h-parameters. The unity gain cut-oﬀ frequency is extracted from extrapolation of the high-frequency asymptote of a plot of the magnitude of h21 in dB versus log (frequency). Most BJT devices at a suﬃciently low frequency can be represented as single pole devices. This assumption is equivalent to a high-frequency asymptote with a slope of −20 dB per decade. However, both Cbe and Cbc capacitances are bias dependent, and so is the cut-oﬀ frequency. From the MAG (in dB) versus log (frequency) plot, fmax is extracted at the point where MAG becomes 0 dB. 4.3.

MATERIAL PARAMETERS FOR SIMULATION

Electrons and holes in a device are accelerated by electric ﬁelds but lose momentum as a result of various scattering processes. These scattering mechanisms include lattice vibrations, impurity ions, other carriers, interfaces and material imperfection. To simplify these mechanisms for modelling purposes, mobility is usually deﬁned as a function of lattice temperature, local electric ﬁeld and doping concentration. In a device simulator, a mobility model is further subdivided into •

low-ﬁeld behaviour,

Material parameters for simulation • • •

111

high-ﬁeld behaviour, bulk semiconductor regions, and inversion layers.

In the low-ﬁeld region, mobility is principally dependent on phonon and impurity scattering, both of which tend to decrease the low-ﬁeld mobility. High-ﬁeld behaviour shows that carrier mobility decreases with electric ﬁeld. The mean drift velocity no longer increases linearly with increasing electric ﬁeld, but rises more slowly. Eventually the velocity saturates at a constant velocity commonly denoted by the symbol vsat which is principally a function of lattice temperature. Modelling mobility in bulk material involves characterizing µn0 and µp0 as a function of doping and lattice temperature and describing the transition between low-ﬁeld and high-ﬁeld regions. Modelling carrier mobility in inversion layers presents additional complications due to surface scattering and quantum mechanical eﬀects. These eﬀects are important for accurate simulation of MOS devices. The transverse electric ﬁeld is often used to characterize mobility variation within inversion layers. In ATLAS, a wide (and somewhat baﬄing) range of diﬀerent silicon mobility models is available. Full details are given in the ATLAS manual [8]. The low-ﬁeld mobility can be characterized in ﬁve diﬀerent ways: user deﬁned; a lookup table as a function of doping; an analytic function of doping and temperature [35]; a carrier scattering model relating mobility to carrier concentration and temperature; or a uniﬁed model dependent on impurity, lattice and carrier–carrier scattering and temperature [36,37]. For bipolar device simulation, the latter model is recommended as it applies a uniﬁed description of minority and majority carrier mobilities. The model shows excellent agreement with available experimental data. As carriers are accelerated in an electric ﬁeld, their velocity will begin to saturate at a high electric ﬁeld. This eﬀect has to be accounted for by a reduction of eﬀective mobility, since the drift velocity is the product of mobility and electric ﬁeld in the direction of current ﬂow. The following expression [38] is used to implement a ﬁeld-dependent mobility for both holes and electrons, that provides a smooth transition between low-ﬁeld and high-ﬁeld behaviour, µ(E) = µo

1 1+

µo E vsat

β β1 (4.27)

where µo is the low-ﬁeld mobility, E is the electric ﬁeld parallel to the direction of current ﬂow, β is a constant, and vsat is the saturation velocity. The coeﬃcient β is one for holes and two for electrons. The saturation velocity vsat is calculated by default from the temperature-dependent

112

Design of SiGe HBTs

model, vsat (T ) =

2.4 × 107 1 + 0.8 exp (T /600)

(4.28)

but speciﬁc values for holes and electrons can be speciﬁed, if required. The incorporation of germanium signiﬁcantly changes the properties of the base region and the emitter–base and base–collector junctions in a SiGe HBT. While silicon has been well characterized over the past 40 years, still not nearly as much is known about strained-SiGe. Many simplifying assumptions are made in the SiGe material parameters. The addition of Ge reduces the bandgap of Si, leading to the narrow bandgap SiGe base of the HBT, as discussed in chapter 3. The lattice constant of the strainedSi1−x Gex alloy diﬀers considerably from that of Si. The incorporation of Ge also modiﬁes the energy band structure, and density of states in the conduction and valence bands. In addition, carrier mobilities and diﬀusivities change owing to changes in the eﬀective masses and alloy scattering. Finally, the dielectric constant, built-in potentials and depletion widths in the p–n heterojunctions depend on the Ge concentration. As all the device simulations reported in this book have been carried out using the Silvaco–ATLAS simulator [8], we consider in the following section, the material parameters used in the simulations. 4.3.1.

SiGe: hole mobility

There have been few reports on the measurements of mobility in strainedSi1−x Gex alloys. Mansevit et al [39] reported enhanced electron mobilities at room temperature, but the Ge mole fraction of the samples was not accurately known. Monte Carlo simulations of electron mobility heavilydoped SiGe at room temperature indicate that µn will be almost 50% higher than for silicon due to the smaller eﬀective mass in SiGe [40]. Enhanced low-temperature mobilities have been also observed for both holes and electrons [41]. In addition to phonon, impurity and alloy scattering mechanisms, strain is expected to play a major role in determining carrier mobility. Due to strain eﬀects, mobilities in SiGe are diﬀerent for carriers travelling parallel and perpendicular to the direction of growth. In ATLAS version 5.0, there is no speciﬁc SiGe mobility model incorporated, but a separate user speciﬁed model can be created by writing speciﬁc functions in the C programming language, which are then interpreted when running the simulation. For this purpose, a hole mobility model may be based on a model developed by Mau [42] originating from an empirical ﬁt to experimental data. The electron mobility model may be based on theoretical computations by Manku and Nathan [43]. The composition, temperature and doping dependent hole mobility is given by:

Material parameters for simulation

113

(i) for majority carriers µp = 49.0

T 300

−0.45

+

−2.2

−0.45

− 49.0 (T /300) (4.29) −2.4 0.74 1.0 + (T /300) (Ntot /1.7 × 1017 ) 480.0 (T /300)

(ii) for minority carriers −0.45 T 480.0(T /300)−2.2 − 122.3(T /300)−0.45 µp = 122.3 + 0.7 ρ 300 (1.0 + (T /300)−2.4 ) (Ntot /1.4 × 1017 ) −1 1.0 × 1.0 + (4.30) 2 0.5 + (7.2 × 1020 /Ntot ) where

ρ=

µmin (x) +

(µmax (x) − µmin (x)) 1 + (Ntot /2.35 × 1017 )0.88

µmax (0) − µmin (0) × µmin (0) + 1 + (Ntot /2.35 × 1017 )0.88 where and

4.3.2.

−1 (4.31)

µmin (x) = 68.7 exp 51.2x3 − 34.2x2 + 8.7x

(4.32)

µmax (x) = 461.9 exp 32.5x3 − 22.2x2 + 6.4x .

(4.33)

SiGe: electron mobility

The alloy scattering limited electron mobility components for coherently strained Si1−x Gex , along directions perpendicular and parallel to the growth direction are given by [43] µalloy = ⊥

5.5 × 1018 T 22.0Nc x(1 − x)m2t

(4.34)

µalloy =

5.5 × 1018 T 4.0Nc x(1 − x)m2l

(4.35)

where Nc is the eﬀective density of states for silicon. It may be noted that the alloy mobility decreases with increasing Ge content. At low doping levels, alloy scattering and phonon scattering predominate, both of which have an E 1/2 dependence. At high doping levels, impurity scattering becomes important, and it too has the same energy dependence. Since the conduction band of SiGe for x < 0.3 is similar to that of silicon, and all the predominant scattering rates have an

114

Design of SiGe HBTs

E 1/2 dependence, the individual parallel and perpendicular components may be deﬁned. The parallel component of electron mobility in SiGe can thus be obtained by using Mathiessen’s rule 1 1 1 = Si + alloy µSiGe µ µ

(4.36)

and the corresponding perpendicular component becomes 1 µSiGe ⊥

=

1 1 + alloy Si µ⊥ µ⊥

(4.37)

where the mobility of silicon for parallel and perpendicular to the growth plane is expressed as [43] 3.0µSi (mt /ml + 2.0)

(4.38)

3.0µSi 2.0(ml /mt ) + 1.0

(4.39)

µSi ⊥ = µSi =

where ml and mt are longitudinal and transverse density of state masses in silicon. At very high concentrations, the Caughey–Thomas relationship [38] no longer suﬃces to describe the carrier mobility. The eﬀect of ultrahigh concentrations on mobility have been analysed by Klaassen [36], and the modiﬁed expression for majority and minority mobility for electron in silicon is given by: (i) for majority carriers −0.45 T 1430.0(T /300)−2.3 − 74.5(T /300)−0.45 Si Z µ = 74.5 + 300 (1.0 + (T /300)−2.6 (Ntot /8.6 × 1016 )0.77 (4.40) (ii) for minority carriers −0.45 T 1430.0(T /300)−2.3 ) − 200.0(T /300)−0.45 Si µ = 200.0 + 300 (1.0 + (T /300)−2.6 )(Ntot /5.3 × 1016 )0.68 ) (4.41) where 1.0 Z = 1.0 + (4.42) 0.21 + (4.0 × 1020 /Ntot )2 where Ntot is the total doping and the ‘clustering’ function Z(N ) is ﬁtted analytically.

Material parameters for simulation

115

To evaluate the mobility of strained-SiGe, alloy scattering as well as energy shifts in the conduction band have to be included. The shifts are taken into account through the electron concentration, since the total mobility is given by a weighted average of the unstrained electron concentration of the ith conduction band, with the corresponding strained electron concentration. The components of the total electron mobility of strained-SiGe, for the growth plane µxx , and plane parallel to the growth direction µzz , can be represented as [43]

SiGe exp(−∆Ex /kT ) + µSiGe + µ exp(−∆Ez /kT ) µSiGe ⊥ ⊥ µxx = (4.43) 2.0 exp(−∆Ex /kT ) + exp(−∆Ez /kT ) µzz =

exp(−∆Ex /kT ) + µSiGe exp(−∆Ez /kT ) 2.0µSiGe ⊥ 2.0 exp(−∆Ex /kT ) + exp(−∆Ez /kT )

(4.44)

where ∆Ex = −0.21x and ∆Ez = 0.42x are the splitting energies due to the shift in the [001], [010] and [100] bands. Despite the apparent complexities of the latter model, a more straightforward model has been proposed in the 1D SCORPIO simulator [18], which describes the mobility enhancement of both carriers in SiGe as a linear function (4.45) µSiGe (x) = (1 + K.x)µSi where K is a ﬁtting constant taken to be 10. Although there are conﬂicting reports concerning the degree of SiGe mobility enhancement which occurs in a HBT, Richey et al [18] conclude that their much simpler model gives excellent agreement with measured data. 4.3.3.

SiGe: bandgap

The most signiﬁcant material parameter to be speciﬁed in the simulation of SiGe HBTs is the bandgap narrowing induced by incorporation of a Ge fraction x. A number of diﬀerent models have been put forward. Polynomial ﬁts by Bludau et al [44] describe the temperature dependence of the energy bandgap of pure silicon at or below room temperature. The high-temperature model from Sze [45] is slightly modiﬁed to match the room temperature value and is given by Eg (T ) = 1.170 + 1.059 × 10−5 T − 6.05 × 10−7 T 2

0 ≤ T ≤ 170 K (4.46)

Eg (T ) = 1.1785 − 9.025 × 10−5 T − 3.05 × 10−7 T 2 Eg (T ) = 1.170 −

4.73 × 10−4 T 2 T + 624.93

170 ≤ T ≤ 300 K (4.47)

T ≥ 300 K.

(4.48)

116

Design of SiGe HBTs

An empirical a ﬁt to the data provided by People [46] for the bandgap of strained-Si1−x Gex alloys on Si(100) substrates is given by Eg (x) = 1.124 − 1.22x + 0.88x2

x ≤ 0.6.

(4.49)

A linear ﬁt is used for 0.6 < x < 1.0, which assumes that the bandgap of strained pure Ge on (100) Si is 0.6 eV. Note that the bandgap of strainedSiGe is considerably smaller than that of bulk-SiGe. In ATLAS, to give increased accuracy, the SiGe bandgap is modelled by a complex piecewise linear function of x, as deﬁned in full in the ATLAS manual. For values of x likely to be encountered in a SiGe HBT (x < 0.245), the following equation applies Eg (x) = 1.08 + x(0.945 − 1.08)/0.245.

(4.50)

In ATLAS, an alternative temperature dependence of the bandgap Eg (T ) for SiGe is given as T2 αT 2 3002 Eg (T ) = Eg (0) − = Eg (300) + α − (4.51) T +β 300 + β T +β where the composition dependences of α and β are given by: α = (4.73(1 − x) + 4.77x)10−4 β = 636.0(1 − x) + 235.0x. The electron aﬃnity of SiGe is assumed to be independent of the composition x and equal to 4.07 eV, identical to that of Si. In a BJT model, the intrinsic carrier concentration nio , which depends on the eﬀective density of states in the conduction and valence bands and the bandgap, plays an important role. The eﬀective conduction and valence band density of states in silicon are given by the well-known expressions: Nc = 2

2πm∗n kT h2

3/2

Nv = 2

2πm∗p kT h2

3/2 (4.52)

where h is Planck’s constant, and m∗n and m∗p are the eﬀective masses of the electron and hole density of states. The eﬀective density of states decreases with increasing Ge content, because the amount of degeneracy in both the valence and conduction band decreases [43, 47]. In ATLAS, an empirical function used to give the composition dependence of densities of states for SiGe is given by: Nc = 2.8 × 1019 + x(1.04 × 1019 − 2.8 × 1019 )

(4.53)

Nv = 1.04 × 1019 + x(6.0 × 1018 − 1.04 × 1019 ).

(4.54)

Material parameters for simulation

117

By using equations (4.53) and (4.54), one can calculate the intrinsic carrier concentration as a function of the Ge content Eg (x, T ) 2 . (4.55) nio (x) = Nc Nv exp − kT In addition to the Ge-induced bandgap narrowing, the high doping in the base induces additional bandgap narrowing, similar to that observed in silicon. Although several bandgap narrowing and mobility models have been proposed for silicon [48–50], little information is available in the literature for Si1−x Gex [51]. The default model in ATLAS version 5.0 assumes that the bandgap narrowing due to heavy doping is the same as that in silicon. This approach has the advantage that any diﬀerences in the simulation of Si BJT and SiGe HBTs can then be unambiguously attributed to heterojunction action (due to Ge incorporation), rather than diﬀerences in model parameters. This assumption of equal values of dopinginduced bandgap narrowing in silicon and Si1−x Gex is reasonably good for base doping concentrations up to approximately 1 × 1019 cm−3 [51], but for higher concentrations there is some evidence [52] to suggest that the bandgap narrowing in Si1−x Gex is lower than that in silicon. Bandgap narrowing eﬀects due to heavy doping are modelled by replacing the intrinsic carrier concentration nio with an eﬀective carrier concentration nie (x, y) where   1/2  2  N (x, y)  qa N (x, y) 1  ln + ln + a3 nie (x, y) = nio exp   2kT  a2 a2 (4.56) where a1 = 0.00692, a2 = 1.3 × 1017 cm−3 and a3 = 0.5 are model parameters. In ATLAS, the dielectric constant of SiGe as a function of composition is given by = 11.9 + 4.1x. (4.57) 4.3.4.

Recombination and carrier lifetime

The dominant recombination processes in bulk-Si are Shockley–Read–Hall (SRH) and Auger recombination. Radiative recombination is negligible since silicon is an indirect bandgap semiconductor, and recombination involving excitons and shallow-level traps is only important at low temperature. The total recombination rate due to Auger and SRH recombination can be written as: 1 R = An n + Ap p + np − n2ie . (4.58) τn (p + p1 ) + τp (n + n1 )

118

Design of SiGe HBTs

In equation (4.58), An and Ap are the electron and hole Auger recombination coeﬃcients and nie is the eﬀective intrinsic carrier concentration including bandgap narrowing eﬀects. τn and τp are the minority carrier SRH lifetimes and n1 and p1 are constants which depend on the energy of the deep-level traps. Commonly used (default) values for the radiative and Auger recombination coeﬃcients are An = 5.0×10−32 and Ap = 9.9 × 10−32 for silicon [53]. Since strained-SiGe is similar to silicon in band structure, exactly the same recombination model is assumed for SiGe. The minority carrier lifetimes in silicon are doping-dependent. For doping concentrations up to 1019 cm−3 , an empirical ﬁt to experimental data gives τ (0) (4.59) τ (N ) = 1 + N/N0 for both electrons and holes. τ (0) is the minority carrier lifetime in lightlydoped silicon and N0 is the reference doping. A good ﬁt to experimental data is achieved by setting N0 = 7.1 × 1017 cm−3 for both n- and ptype silicon, τ (0) = 3.95 × 10−4 s for holes and τ (0) = 1.70 × 10−5 s for electrons [54]. However, τ (0) is very much process dependent. Studies on the determination of minority carrier lifetime in SiGe have shown that the lifetimes are believed to be somewhat shorter than silicon minority carrier lifetimes (in the nanosecond range), due to the large number of misﬁt dislocations. 4.4.

HISTORY OF SIMULATION OF SIGE HBTS

Numerous papers have appeared in the literature on both the numerical and analytical modelling of the SiGe HBTs [40, 55–61]. Much of the early work on simulation of SiGe HBTs was carried out over a decade ago and signiﬁcant improvements in performance have since been achieved. Smith and Welbourn [40] reported that for a SiGe transistor with a 0.15 µm thick strained layer base (with 15% Ge, ∆Ev = 170 meV and 50% enhancement of electron mobility due to strain) an fT of 20 GHz should be realizable before the onset of base widening. The value of fmax was estimated to be 40 GHz. This represented a threefold increase of speed over the homojunction devices at that time. Pejcinovic et al [56] simulated numerically the small-signal performance of a SiGe HBT. The heavy doping eﬀect in SiGe was assumed to be the same as in Si, and eﬀects of strain and alloy scattering on the mobility were included in the model. The doping concentrations in the emitter, base and collector were 7×1019 , 2×1019 and 4.5 × 1017 cm−3 , respectively. The authors found that for the Ge fraction x = 0.2, the turn-on voltage of the HBT was smaller by 0.12 V as compared to an otherwise identical Si homojunction transistor. The frequency fT was twice as large as in the Si transistor and fmax was even larger.

Experimental SiGe HBTs

119

In early 1989, Won and Morkoc [60] examined theoretically the highspeed capability of the SiGe HBTs. They included alloy scattering and strain eﬀects on the mobility in the model. Several doping concentrations were considered. The collector and base doping concentrations were optimized by making a compromise between speed and breakdown voltage. If the parameters are optimized to obtain an fT of 75 GHz, the estimated fmax value is 35 GHz at a current density of 1×105 A cm−2 and Vbc = 5 V. The theoretical work done during this period showed that the HBTs had great promise, once technological problems encountered in their fabrication were resolved. Hueting et al [61] have optimized a SiGe HBT design for highfrequency performance and claimed that a box type Ge proﬁle with the leading edge approximately in the middle of the base is optimal. The doping concentrations in the emitter, base and collector were 2 × 1021 , 2.2 × 1018 and 1 × 1017 cm−3 , respectively, while the Ge concentration in A the base was 11.5%. An fT value of 45 GHz for a base thickness of 600 ˚ was obtained. Hueting et al studied the eﬀect of grading the Ge proﬁle in the base and concluded that (in their opinion) the grading of Ge in the base is of minor importance. Several other simulation techniques such as Monte Carlo [62–64], energy transport [19, 65] have also been employed for the simulation studies of SiGe HBTs. 4.5.

EXPERIMENTAL SIGE HBTS

Since the introduction of SiGe into conventional Si technology, various research groups have demonstrated high-performance SiGe base HBTs with diﬀering approaches to forming the Ge proﬁle in the base. While the IBM group uses graded Ge proﬁles, the Daimler–Benz group focuses on SiGe HBTs with a uniform Ge box proﬁle. The epitaxial growth of active device regions in Si-based technology is a signiﬁcant departure from past device fabrication, where epitaxy had been used solely for the controlled substrate formation. Epitaxial base technology has many advantages over an ionimplanted technology. A box-like proﬁle provides independent control over base width and doping concentration. Thus, a base width as small as 30 nm, with a very high doping concentration, can be obtained. Even for these small thicknesses, the base resistance is acceptable and punch-through is avoided. This allows reduction of charge storage in the emitter and independent control of base resistance and base transit time. By tailoring the base proﬁle, low values of emitter–base and base–collector capacitance, Cbe and Cbc , can be obtained. The design can also be tailored for optimum ECL performance in a digital circuit by obtaining high fT at low base resistance. Epitaxial base technology provides the opportunity to independently control each of the delays deﬁned in equation (3.31). Transit time is

120

Design of SiGe HBTs

reduced by both vertical scaling and Ge grading in the base. Self-aligned epitaxial base technology also allows reduction of extrinsic capacitances and resistance to reduce the gate delays [66, 67]. Harame et al [68] have developed a high-performance SiGe BiCMOS HBT process. During the emitter formation, considerable out-diﬀusion of boron takes place as the diﬀusion coeﬃcient of boron is considerably larger than that of arsenic. The problem of boron out-diﬀusion can be avoided, and narrow bases can be formed, if arsenic is replaced by phosphorus for doping the emitter [69]. The diﬀusivity of phosphorus is much larger than that of arsenic and is close to that of boron. In the devices designed and fabricated by Crabbe et al [69], phosphorus-doped emitters were used. The epitaxial SiGe bases were grown by UHVCVD [70] at 550 ◦ C. The Ge proﬁle was graded from 0% at the emitter–base junction to 15% at the base–collector junction. The collector doping was 4 × 1017 cm−3 to avoid base widening at high current densities. Lightly-doped spacers were placed in the emitter–base and base–collector junctions to maintain reasonable values of BVebo and BVceo . The narrow base width reduced the intrinsic transit time from 2.1 ps to 1.9 ps [71]. The cut-oﬀ frequency was 73 GHz at a collector current density of 2 mA µm−2 . The peak fmax was only 26 GHz, due to high extrinsic base resistance caused by insuﬃcient activation of boron because of low emitter anneal temperature. Gruhle et al [72] fabricated a high-performance MBE-grown SiGe transistor. Ge concentrations of 21–28% and boron concentrations of up to 2 × 1020 cm−3 were used to obtain simultaneously high current gains and low base resistance. The SiGe HBT with the highest fmax (in 1995) was reported by Schuppen et al [73]. This transistor used a relatively thick (60 nm) base and heavy doping to minimize the intrinsic base resistance. The base transit time was reduced by a strong electric ﬁeld with 0–15% Ge grading. The SiGe base was grown selectively by using a self-aligned CVD technology. The performance achieved was an fmax of 160 GHz and a gate delay of 19 ps in an ECL circuit. In the same year, Meister et al [74] reported a SiGe HBT with a 74 GHz fmax , resulting in a record CML gate delay (at that time) of 11 ps. Recently, a 0.2 µm self-aligned selective epitaxial growth (SEG) SiGe HBT, with shallow-trench and dual deep-trench isolations and Ti–salicide electrodes, has been developed. The process, except for the SEG, is almost completely compatible with well-established silicon BiCMOS technology. The SiGe HBTs exhibited a peak fmax of 107 GHz and a record minimum ECL gate delay of 6.7 ps [75]. An Si/Si0.65 Ge0.35 abrupt HBT with transit frequencies fT of 133 and 213 GHz at 300 and 77 K, respectively, has been announced recently [76]. The corresponding maximum oscillation frequencies are 81 and 115 GHz. A detailed analysis of the intrinsic delay times has shown that the base transit time plays the dominant role.

Device design issues 4.6.

121

DEVICE DESIGN ISSUES

In the following sections, important parameters of SiGe HBTs (fT , fmax and VA ) will be considered in detail and attempts are made to illustrate how simulation has been used to optimize the device design for circuit applications. Base, emitter and collector proﬁle design issues at room temperature will be discussed. All the simulations have been performed using the Silvaco–ATLAS device simulator as described in sections 4.1 and 4.2, using default material parameters.

Figure 4.1. Doping proﬁle and Ge proﬁle (ﬂat or box) of a SiGe HBT.

122 4.6.1.

Design of SiGe HBTs Base design

We consider a uniform (ﬂat or box) Ge proﬁle (x = 0.12) in the base. The device structure and the doping concentration used for simulation is shown in ﬁgure 4.1. A simulated band diagram comparing SiGe and Si transistors is shown in ﬁgure 4.2. As can be seen in ﬁgure 4.3, the uniform Ge box proﬁle produces the sevenfold increase in β for 12% Ge at 300 K, since the enhancement depends exponentially on the bandgap reduction at the emitter–base junction. In the conventional Si BJT, β is inversely

Figure 4.2. Schematic band diagrams of a homojunction (Si BJT) and a heterojunction (SiGe HBT) bipolar transistor.

Device design issues

123

Figure 4.3. Comparison of dc current gain of an Si BJT and a ﬂat base SiGe HBT.

proportional to the integrated base charge. Since base doping cannot be increased indeﬁnitely while maintaining adequate β, the ﬂat Ge proﬁle is particularly useful in realizing a transistor with either a very high β, or a moderate β with lower intrinsic base resistance. However, any signiﬁcant enhancement in peak fT of a SiGe HBT over an Si BJT, depends principally on the utilization of Ge grading across the base. The simulated peak cut-oﬀ frequency of 42 GHz for a uniform Ge proﬁle is shown in ﬁgure 4.4. Now we consider a graded Ge proﬁle (deﬁned for reference purposes as triangular) having 0% Ge at the emitter–base junction and 12% Ge

124

Design of SiGe HBTs

Figure 4.4. Simulated cut-oﬀ frequency of an Si BJT and a ﬂat base SiGe HBT.

at the collector–base junction, as shown in ﬁgure 4.5. The Ge grading (0–12%), is eﬀective for reducing τb , and thus increasing fT . In this type of Ge proﬁle design, there is no Ge-induced bandgap reduction at the emitter–base junction, and the β is reduced compared to the ﬂat Ge proﬁle. However, as the β enhancement depends approximately linearly on the Ge grading when there is no bandgap reduction at the emitter–base junction, an enhancement in β of approximately 5 has been simulated. In high-speed analogue applications, which require a high βVA product, the triangular Ge proﬁle would appear to oﬀer a superior design [77]. Because β is still enhanced for the triangular Ge proﬁle, it is still possible to trade β

Device design issues

125

Figure 4.5. Doping proﬁle and Ge proﬁle (triangular) of a SiGe HBT.

for lower base resistance. Using this approach, both fT and base resistance can be tailored to signiﬁcantly increase fmax . It is seen from ﬁgure 4.6 that for a graded Ge proﬁle in the base, fT has increased from 42 GHz (Ge box proﬁle) to 63 GHz, but the gain has dropped from 360 to 200, as shown in ﬁgure 4.7. A trapezoidal proﬁle would appear to be a logical compromise between the two previous Ge proﬁles. This type of proﬁle was used successfully to realize the ﬁrst 1.0 Gb s−1 12-bit digital-to-analogue converter [77]. Figures 4.8 and 4.9 show a simulation of a trapezoidal proﬁle where the Ge mole fraction at the emitter–base edge is 5% and it has been graded to reach a maximum Ge concentration of 15% at the base–collector junction. It is seen that the trapezoidal grading results in a good compromise between peak current gain of 200, and fT of 50 GHz.

126

Design of SiGe HBTs

Figure 4.6. Comparison of peak cut-oﬀ frequency of a graded base versus a ﬂat base SiGe HBT.

4.6.2.

Emitter design

An ideal emitter should provide low emitter saturation current density, low emitter resistance, low charge storage, low emitter–base depletion capacitance, and good passivation at the perimeter of the emitter. The polysilicon emitter contact used in conventional Si technology meets most of these requirements. The polysilicon–silicon interface also provides a barrier-to-hole injection into the emitter. An alternative approach to the polysilicon emitter contact is to use single-crystal emitter. Such a structure

Device design issues

127

Figure 4.7. Comparison of dc current gain of a graded base and a ﬂat base SiGe HBT.

is ideal to decouple the base from the emitter, thereby allowing arbitrarily high base dopant concentrations. Furthermore, it allows a reduction in emitter–base capacitance, leading to higher fT at lower collector current density, as long as the delay associated with minority carrier charge storage in the quasi-neutral emitter can be minimized by maintaining suﬃcient current gain. A high–low emitter proﬁle, consisting of a heavily-doped polysilicon contact on top of a thin epitaxial emitter cap addresses both requirements [78]. The emitter cap thickness should be small to minimize charge storage and is typically 200–300 ˚ A. The highly-doped polysilicon contact ensures low total emitter resistance.

128

Design of SiGe HBTs

Figure 4.8. Comparison of dc current gains of ﬂat, graded (triangle and trapezoid) base SiGe HBTs.

Three diﬀerent thicknesses of low-doped emitter, namely 100, 200 and 300 ˚ A, have been used for simulation as shown in ﬁgure 4.10. The peak value of Ge fraction x is 0.08. As expected, fT decreases marginally from 30 GHz as the emitter cap thickness is increased from 100 to 300 ˚ A. The location of the Ge proﬁle with respect to the metallurgical emitter–base junction plays a key role in the dc and ac characteristics of the HBT. For an HBT with a linearly graded Ge proﬁle and with a poly emitter contact, locating the emitter–base metallurgical junction right at the bottom of the Ge ramp is a good compromise to ensure moderate current gain while

Device design issues

129

Figure 4.9. Comparison of cut-oﬀ frequency of ﬂat base, graded trapezoidal base SiGe HBTs.

taking full advantage of the Ge grading to minimize the base transit time. The slope of the Ge proﬁle at the edge of the emitter–base space-charge region on the base side can aﬀect the ideality of the collector current [79]. 4.6.3.

Collector design

The design of the collector is dictated by conﬂicting requirements to simultaneously achieve high breakdown voltage BVceo , low base–collector capacitance, low base–collector signal delay τbc , and a high value of

130

Design of SiGe HBTs

Figure 4.10. Emitter with diﬀerent low-doped spacer layers. Ge and Boron proﬁles in the base are also shown.

the knee current density at which fT decreases. The collector doping proﬁle determines two critical performance parameters of the transistor: the base–collector delay time τbc , which is a signiﬁcant component of the total intrinsic delay τec , and the intrinsic base–collector capacitance which governs circuit performance. A conventional approach to suppress base widening is simply to utilize a thin highly-doped epitaxial collector layer. Consequently, base widening is suppressed at the expense of BVceo degradation. One of the methods to increase BVceo , while suppressing base widening, is to introduce a retrograde collector proﬁle [80]. In determining HBT performance, it should be recalled that the collector–emitter breakdown voltage BVceo is directly related to the

Device design issues

131

Figure 4.11. Diﬀerent collector doping proﬁle and Ge proﬁle (triangular) of a SiGe HBT.

cut-oﬀ frequency, according to the theoretical ‘Johnson limit’, and falls monotonically for increasing values of fT [81]. A 50 GHz transistor corresponds to a breakdown voltage of 3.3 V. In general, therefore, some degree of optimization is always required to yield the appropriate higher fT for a lower BVceo . Increasing the peak collector doping density (Ncoll ) above 1 × 1017 cm−3 improves the frequency performance in two ways: (i) a reduction in transit time τbc giving increase in fT ; and (ii) a delay onset of Kirk eﬀect permitting operation at higher collector current density since the Kirk (knee) current density (Jk ) is proportional to the collector doping.

132

Design of SiGe HBTs

In simulations, as a compromise, we have assumed a minimum collector concentration of 5 × 1016 cm−3 at the base–collector junction, and have ramped the doping as shown in ﬁgure 4.11. Proﬁles 1, 2, and 3 correspond to peak values of 1.5 × 1017 cm−3 , 2 × 1017 cm−3 and 4 × 1017 cm−3 at a depth of 0.4 µm. The eﬀects of the diﬀerent collector proﬁles on fT are shown in ﬁgure 4.12. As expected, proﬁle 3 (highest doping) produces the highest fT of 49 GHz. Early work on achieving high fT with SiGe HBTs utilized collector concentrations in the range 2 to 6 × 1017 cm−3 [82, 83]. These higher collector dopings led to unacceptably high values of Cbc for most circuit

Figure 4.12. Eﬀect of collector doping (ramping) on cut-oﬀ frequency.

Device design issues

133

applications, as they increase the input capacitance of the device via the Miller eﬀect. Optimizing the collector proﬁle consists therefore in trading an increased transit time τec , arising from an increase in τbc with reduced collector doping, for a reduction in the base–collector capacitance. This point is considered again in chapter 5 where two variants of a process are considered: one to achieve very short ECL gate delay by using a relatively low collector doping and the other using a much higher collector doping to achieve fT of more than 100 GHz. Figure 4.13 shows the eﬀect of collector doping on the simulated output characteristics. It is evident that the proﬁle with the highest fT yields the lowest BVceo .

Figure 4.13. Eﬀect of collector doping on BVceo .

134 4.7.

Design of SiGe HBTs SMALL-SIGNAL AC ANALYSIS

A useful outcome of physical device simulation is the opportunity to use the results to extract parameters which can be used in a compact model for circuit simulation. The particular virtue of device simulation in this context is the ability to visualize how changes to a particular process or structure aﬀect the overall circuit performance. The whole ﬁeld of compact modelling for bipolar transistors is extensive, with the Gummel–Poon model, and recently the vertical bipolar inter-company (VBIC) model, widely used [84, 85]. A detailed consideration of these models is beyond the scope of this book. However, by way of illustration, we present an example showing how device simulation can yield component values for a rudimentary small-signal lumped element model. In addition, a method of determining the diﬀerent components of the transit time by integration of the carrier distribution is also discussed. 4.7.1.

Small-signal equivalent circuit

By treating the bipolar transistor as a two port network, it has been explained in section 4.2 that a device simulator such as ATLAS has the capability to determine all small-signal parameters. It is therefore possible to use these parameters to extract the components of the hybridπ small-signal equivalent circuit as shown in ﬁgure 4.14. This equivalent circuit represents a somewhat idealized representation of the transistor and neglects distributed eﬀects of minority carrier storage in the quasi-neutral emitter and base regions [86]. It assumes that all parasitic components associated with resistance, inductance and capacitance of probes, pads and

Figure 4.14. Simpliﬁed hybrid-π model of a SiGe HBT.

Small-signal ac analysis

135

interconnects have been successfully de-embedded. In this model, Cbe is the emitter–base capacitance (representing the sum of diﬀusion and depletion capacitance), rbe is the dynamic emitter resistance, Cbc is the base– collector capacitance, rbb is the base resistance, rcc the collector resistance and ree the emitter resistance. The small-signal transconductance is expressed as [87] gm = gmo exp (−jωτd ) (4.60) where gmo is the low-frequency intrinsic transconductance and τd is the transit time phase delay of transconductance. To determine series resistance, it is most convenient to use small-signal z-parameters, where it can be shown [87] Z11 = rbb + ree +

Zπ 1 + gm Zπ

Zπ 1 + gm Zπ gm Zπ 1− = ree + 1 + gm Zπ jωCbc Z12 = ree +

Z21

Z22 = rcc + ree + where

1 1 Zπ + jωCbc 1 + gm Zπ 1 + gm Zπ

Zπ =

rbe . 1 + jωrbe Cbe

(4.61) (4.62) (4.63) (4.64) (4.65)

If small-signal ac simulations are carried out at relatively high frequency (typically in the range 0.02–0.1 fT ), then since gmo ≥ 1/|Zπ | 1 gmo

(4.66)

rbb = Re (Z11 − Z12 )

(4.67)

ree = Re (Z12 ) −

rcc = Re (Z22 − Z21 ) −

Cbe . gmo Cbc

(4.68)

The method of extraction of rbb and ree appears to work well, but extraction of rcc is problematic, because rcc is expressed as the small diﬀerence between the real parts of Z22 and Z21 , and a further term representing the high-frequency ac output resistance. This latter term, involving a ratio of capacitance, tends to be much larger than the unknown value of rcc , so it proves very diﬃcult to obtain a consistent value of rcc which is independent of the frequency at which it is evaluated. In addition, the accuracy of the second term is dependent on the accuracy of the evaluation of the other three parameters Cbe , Cbc and gmo . None

136

Design of SiGe HBTs

of these parameters are known with absolute certainty and have to be extracted using either y- or h-parameters using Cbc = − Cbe =

Im(y12 ) ω

Im(y11 ) (rbb + rbe )2 − Cbc 2 ω rbe

(4.69) (4.70)

and rbe can be reliably obtained from rbe =

1 − Re(y11 )(rbb + ree ) Re(y11 )

(4.71)

at a frequency low enough that the reactance of Cbe does not aﬀect Re(y11 ). Figure 4.15 shows how the value of base resistance, extracted using equation (4.67), varies with frequency, as collector current is increased. The well-established mechanism of reduction in base resistance at higher collector current due to current crowding is evident in this ﬁgure. The choice of frequency is important in so far as one would like to evaluate the base resistance at a frequency where the extracted value is relatively insensitive to the choice of frequency. Based on the pattern of variation seen in ﬁgure 4.15, it would appear that extraction of rbb at a frequency of around 1 GHz, signiﬁcantly below fT would appear to be a reasonable choice.

Figure 4.15. Variation of rbb = Re(Z11 − Z12 ) with frequency.

Small-signal ac analysis

137

Figure 4.16. Extraction of input resistance using (a) h-parameters and (b) z-parameters.

Figure 4.17. Extraction of output resistance using (a) h-parameters and (b) z-parameters.

138

Design of SiGe HBTs

Figure 4.16 shows that the equations (4.67) and (4.68) for rbb and rcc based on z-parameters are relatively independent of frequency in the range 1–8 GHz and it is clear that while rbb can be relatively accurately determined from z-parameters (rather than h-parameters), the small value of rcc , believed to be of the order of 20 ohms from sheet resistance calculations, is masked by the much higher value of more than 200 ohms of the additional term involving the ratio of capacitance. This point is further illustrated in ﬁgure 4.17, which shows that the total output resistance can be estimated by two methods: one using z-parameters, the other using h-parameters. As indicated on the ﬁgure, both expressions nominally give the same value. Neither equation however, is exact. Both involve a degree of approximation, and the expected value of rcc is of the same order as the likely error in using either of the two expressions. This example highlights the diﬃculty which can occur in determining collector series resistance from small-signal parameters. To evaluate gm , it transpires that the most appropriate method is to use h-parameters, rather than y-parameters. It has been shown that for the small-signal equivalent circuit shown [34] gm =

Re(h21 ) . Re(h11 )

(4.72)

Figure 4.18 shows that the above equation involving the ratio of

Figure 4.18. Extraction of gm using (a) y-parameters and (b) h-parameters.

Small-signal ac analysis

139

h-parameters is more reliable in estimating the transconductance, gm . Use of Re(y21 )/ω always underestimates gm , because it takes no account of the eﬀect of the voltage divider ratio due to rbb and rbe . This correction of course requires accurate values of rbb and rbe so the computation using h-parameters is always liable to be more reliable. 4.7.2.

Evaluation of transit time

While small-signal analysis is useful in extracting fT from |h21 |, it does not permit insight into the magnitude of the individual components that comprise the total transit time τec . To ﬁnd the individual components of τec from device simulation, it is necessary to integrate the carrier concentration within deﬁned regions of the transistor, according to the analysis given in [88]. When the semiconductor equations are solved numerically, the carrier concentration is known at every node in the structure. Hence, it is relatively straightforward to integrate the carrier concentration numerically to give the individual components of transit time. The total transit time is given by xbc L xeb q τec = ∆n(x)dx + ∆n(x)dx + ∆n(x)dx . (4.73) ∆Jc 0 xbc xeb Here we deﬁne the individual components by the incremental relationships: •

•

•

•

•

emitter–base depletion charging time xeb q (∆n(x) − ∆p(x)) dx τeb = ∆Jc 0 base–collector depletion charging time L q τbc = (∆n(x) − ∆p(x)) dx ∆Jc xbc emitter transit time τe =

q ∆Jc

τb =

q ∆Jc

base transit time

collector transit time q τc = ∆Jc

xeb

(4.76)

∆n(x)dx

(4.77)

∆p(x)dx.

(4.78)

xbc

xeb

L

xbc

(4.75)

∆p(x)dx

0

(4.74)

140

Design of SiGe HBTs

In the formulation given, the integration is implicitly deﬁned as onedimensional through the active transistor region, where x = 0 deﬁnes the emitter contact, and x = L the collector contact. In this analysis, for simplicity, the parameters xeb and xbc deﬁne the respective positions of emitter–base and base–collector metallurgical junctions. A more rigorous deﬁnition of these two points, as the points of intersection of dp/dJc and dn/dJc , is given in [88]. This deﬁnition is, however, diﬃcult to implement in a 2D device simulator and has not been used. The values of diﬀerential carrier densities ∆n(x) and ∆p(x) can be computed by perturbing the dc bias by a small amount, to induce a small change in collector current density ∆Jc . The value of emitter– collector transit time τec , computed using this method, is comparable (but not exactly identical) to the value of the SPICE parameter τF obtained from the y-intercept of the graph of 1/(2πfT ) versus 1/Ic as deﬁned in equation (3.31) [89]. However, it should be borne in mind that all components of τec will vary to some extent with bias condition, whereas τF is an absolute value deﬁned as 1/Ic → 0. Both emitter and base transit times are relatively insensitive to collector current but increase as expected at the onset of high injection leading to a fall in fT [90]. Figure 4.19 shows the relative magnitudes of the components of transit time based on a simulation of a state-of-the-art HBT with a base width of 40 nm, a Gaussian base doping proﬁle with peak 1.5 × 1019 cm−3 and a low-doped emitter of 1018 cm−3 . The transit times were evaluated as a function of bias condition using equations (4.74)–(4.78). The simulated maximum unity gain cut-oﬀ frequency for this transistor based on h21 is 38 GHz, while the corresponding value of τF from ﬁgure 4.20 is 3.6 ps. For comparison, if transit times are computed directly the

Figure 4.19. Variation of transit time components with collector current.

Small-signal ac analysis

141

Figure 4.20. Extraction of SPICE parameter, τF from variation of fT with collector current.

minimum value of τec before onset of high injection is 3.75 ps at a collector current of 7 mA. It should also be pointed out that, while the y-intercept of the extrapolated straight line in ﬁgure 4.20 gives τF , its slope represents the sum of the depletion capacitance Cje + Cjc as deﬁned in equation (3.35). This represents an alternative method for the determination of parasitic capacitance to the use of y-parameters. 4.7.3.

ECL gate delay

Unlike the frequencies fT and fmax , there is no standard analytical expression universally accepted for the propagation delay of an ECL gate. This gate delay, which normally represents a performance measure for digital circuits, depends not only on the intrinsic characteristics of the transistor, but also on the circuit conﬁguration and the values of load resistance and capacitance. The unloaded ECL gate delay exhibits a similar sensitivity to intrinsic device transit time, parasitic resistance and capacitance as fmax . At low switching current levels, the gate delay is dominated by the base–collector capacitance, which is dependent on the device structure and layout geometry, whereas at high current levels the delay is more strongly coupled to the total base resistance and the transit time of the device. Approximate expressions for the gate delay for speciﬁc circuits have been used by Kroemer [91] and by Shaﬁ et al [92] for the ECL circuits employing SiGe HBTs. The expression used by Kroemer is given by τdel =

5 rbb τF + (3Cbc + CL ) RL rbb Cbc + 2 RL

(4.79)

142

Design of SiGe HBTs

where RL is the load resistance and CL is the load capacitance of the circuit. The importance of reducing the base resistance to improve the speed is obvious from this equation (4.79). It is clear that a reduction in rbb will improve the switching time until the ﬁrst two terms become small and the ﬁnal term involving RL dominates. Further improvement can only be obtained by reducing base–collector capacitance. The importance of the above result lies not in the actual numerical values of diﬀerent terms but in that it demonstrates the relative importance of the various transistor parameters in determining its speed. Shaﬁ et al [92] have used a diﬀerent approach to calculate the gate delay in an ECL circuit. Their calculations are based on the weighting factors developed by Fang [93]. The calculations using this method were compared with direct SPICE simulations and the two results agreed within 5% for the speciﬁc technology considered. The propagation delay is expressed as a sum of RC time constants and stored charge elements: τdel =

Ki Ri Ci + Kj τec

(4.80)

i

where summation over i includes all the resistances and capacitances of the logic gate and those associated with the emitter, base and collector of all the transistors in the circuit. Shaﬁ et al [92] calculated the numerical values of gate delay for SiGe HBTs and compared these with similar computations for homojunction devices. A Ge concentration of 12% was shown to be required in the SiGe base to provide suﬃcient gain enhancement to allow the reversal of the usual emitter and base doping concentrations. This results in a transistor with a low base resistance and low emitter–base depletion capacitance. For a fully optimized device, predicted propagation delays were 15 ps for the SiGe HBT and 29 ps for the Si BJT. Subsequently, as SiGe technology has developed over the last decade, bipolar scaling to ultrathin base and 0.2 µm self-aligned technology has given rise to a propagation delay as low as 6.7 ps by a research group from Hitachi [75]. In order to simulate ECL delay, circuit simulation using SPICE must be used. If the two-dimensional structure of the transistor is known, device simulation can be used to extract key SPICE parameters such as τF , Cje , Cjc and rbb from small-signal ac analysis, as illustrated in the previous section. These SPICE parameters can then be used in a circuit simulation to predict variation in ECL gate delay with collector current. The advantage of this approach is that it provides insight into how the process can aﬀect the circuit performance. Table 4.1 presents a representative sample of key SPICE parameters extracted for a scaled SiGe HBT process based on silicon-on-insulator (SOI) technology [94]. The technology, outlined more fully in chapter 5, utilizes an epitaxial base and lightly-doped emitter. To allow for eﬀects of boron

Small-signal ac analysis

143

out-diﬀusion the base proﬁle is assumed to be Gaussian. In table 4.1, two sets of process parameters are considered. In the set labelled (a) the emitter doping is 1018 cm−3 , while in the set labelled (b), the emitter doping is reduced to 1016 cm−3 . The key issue illustrated by table 4.1 is to examine whether use of a lower doping density in the emitter spacer layer can improve ECL gate delay. A more lightly-doped emitter will of course degrade the overall transit time and hence fT , but does yield a signiﬁcantly lower emitter– base junction capacitance. This lower junction capacitance gives a marked improvement in ECL gate delay particularly at lower collector currents,

Table 4.1. SPICE parameters for a SiGe HBT. Transistor parameters

(a)

(b)

Base dose Emitter doping (n-type) Collector doping Mask alignment tolerances Ge fraction x Low-doped emitter width Wepi Base width Wb

1.2 × 1013 cm−2 1 × 1018 cm−3 1 × 1017 cm−3 0.25 µm 0.1 0.05 µm 0.038 µm

1.2 × 1013 cm−2 1 × 1016 cm−3 5 × 1016 cm−3 0.25 µm 0.1 0.03 µm 0.045 µm

356 3.0 ps 81 Ω 42 Ω 50.8 fF 13.5 fF 2.2 fF 75 V

190 4.2 ps 68 Ω 63 Ω 14.7 fF 10.0 fF 2.2 fF 101 V

38 GHz

29 GHz

48 GHz

56 GHz

36.2 35.1 29.8 39.0 21.7 18.4

31.0 38.3 30.6 24.3 16.7 15.5

Extracted SPICE parameters Forward current gain (β) Transit time τF Base resistance rbb at 1 mA Collector resistance rcc Emitter junction capacitance Cje Collector junction capacitance Cjc Collector substrate capacitance Cjs Early voltage VA Extracted small-signal parameters Cut-oﬀ frequency fT from h21 Maximum oscillation frequency fmax (MAG) SPICE circuit simulations Cut-oﬀ frequency fT at Ic = 5 mA Maximum oscillation frequency fmax SOI Maximum oscillation frequency fmax Si ECL gate delay at 0.5 mA ECL gate delay at 1 mA ECL gate delay at 5 mA

GHz GHz GHz ps ps ps

GHz GHz GHz ps ps ps

144

Design of SiGe HBTs

Figure 4.21. Dependence of fmax on emitter–polySi length.

well below the current level at which peak fT is predicted. In addition, the creation of the bipolar transistor in an SOI rather than a silicon substrate yields approximately 20% improvement in fmax due to lower collector– substrate capacitance in the SOI substrate, as shown in ﬁgure 4.21. In this ﬁgure, circuit simulation using SPICE parameters extracted from ATLAS has been used to determine fmax . With the simulated values of base resistance as an input parameter for SPICE, ECL gate delays have been computed as a function of base resistance and are tabulated in table 4.2. It is seen that, as expected, the ECL gate delay decreases with the decrease in rbb and the minimum value is comparable to the experimentally reported values for a SiGe HBT of comparable dimensions [95]. Table 4.2. The dependence of ECL gate delay on base resistance. SPICE parameters used: VAF = 130 V, Cje = 7.5 pF, Cjs = 13 pF, Cjc = 5.5 pF. Base resistance

Gate delay (ps)

200 100 50 25

17.1 14.7 13.3 12.5

Summary 4.8.

145

SUMMARY

This chapter has considered how a SiGe HBT can be modelled in a device simulator. The relevant equations, relating to current ﬂow in a structure where the bandgap is varying, were considered. Basic concepts employed in a simulation program were given. Key material parameters for SiGe, in so far as they diﬀer from silicon, were outlined. A more accurate strained layer SiGe mobility model should be used to take into account the diﬀerent mobilities (parallel and perpendicular to the growth direction) of the strained-SiGe layer. The way in which ac simulation can be utilized to determine smallsignal y-parameters was considered. Knowledge of y-parameters then permits any other small-signal parameter to be evaluated. In this way, both fT and fmax can be determined. A speciﬁc study of the design of an HBT with a base width of approximately 60 nm was fully described. Base, emitter and collector proﬁle design issues were discussed in detail. High βVA product necessary for analogue applications is of special interest, as it is achievable using SiGe HBTs. Devices with three diﬀerent Ge proﬁles (ﬂat, triangular and trapezoid) were considered. The optimum Ge proﬁle in the base was shown to be a trapezoidal proﬁle. A retrograde collector proﬁle allowed the condition fT = fmax to be optimized, whilst still achieving acceptable BVceo . The signiﬁcance of the ECL gate delay and the way in which device simulation can be used to predict ECL gate delay was outlined. Gate delays of ECL circuits involving SiGe HBTs were computed using SPICE parameters extracted using small-signal analysis. BIBLIOGRAPHY [1] Gummel H K 1964 A self-consistent iterative scheme for one-dimensional steady-state transistor calculations IEEE Trans. Electron Devices 11 455– 65 [2] DeMari A 1968 An accurate numerical steady-state one-dimensional solution of the P–N junction Solid-State Electron. 11 33–58 [3] Scharfetter D L and Gummel H K 1969 Large-signal analysis of a silicon read diode oscillator IEEE Trans. Electron Devices 16 64–77 [4] D’Avanzo D C, Vanzi M and Dutton R W 1979 One-dimensional semiconductor device analysis (SEDAN) Report G-201-5 Stanford University [5] Selberherr S, Schutz A and Potzl H W 1980 MINIMOS—a Two-Dimensional MOST Transistor Analyser IEEE Trans. Electron Devices 27 1540–50 [6] Franz A F and Franz G A 1985 BAMBI—a design model for power MOSFETs IEEE Trans. Comput.-Aided Des. 4 177–89 [7] Pinto M R 1985 PISCES-IIB Manual (Stanford, CA: Stanford University) [8] Silvaco International 1997 Silvaco–ATLAS Manual, Ver 4.0

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Design of SiGe HBTs

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heterostructures IEEE J. Quantum Electron. 22 1696–710 [47] Manku T, McGregor J M, Nathan A, Roulston D J, Noel J-P and Houghton D C 1993 Drift hole mobility in strained and unstrained doped Si1−x Gex alloys IEEE Trans. Electron Devices 40 1990–6 [48] del Alamo J A, Swirhun S and Swanson R M 1985 Simultaneous measurement of hole lifetime, hole mobility and bandgap narrowing in heavily-doped n-type silicon IEEE IEDM Tech. Dig. pp 290–3 [49] Swirhun S E, Kwark Y H and Swanson R M 1986 Measurement of electron lifetime, electron mobility and bandgap narrowing in heavily-doped p-type silicon IEEE IEDM Tech. Dig. pp 24–7 [50] Klaassen D B M, Slotboom J W and de Graaﬀ H C 1992 Uniﬁed apparent bandgap narrowing in n- and p-type silicon Solid-State Electron. 35 125–9 [51] Poortmans J, Jain S C, Totterdell D H J, Caymax M, Nijs J F, Mertens R P and van Overstraeten R 1993 Theoretical calculations and experimental evidence of the real and apparent bandgap narrowing due to heavy doping in p-type Si and strained Si1−x Gex layers Solid-State Electron. 36 1763–71 [52] Jain S C and Roulston D J 1991 A simple expression for band gap narrowing (BGN) in heavily-doped Si, Ge, GaAs and Gex Si1−x strained layers SolidState Electron. 34 453–65 [53] Dziewior J and Schmid W 1977 Auger coeﬃcients for highly-doped and highly excited silicon Appl. Phys. Lett. 31 346–8 [54] Fossum J G 1976 Computer-aided numerical analysis of solar cells SolidState Electron. 19 269–77 [55] McGregor J M, Roulston D J, Hamel J S, Vaidyanathan M, Jain S C and Bulk P 1993 A simple expression for ECL propagation delay including non-quasi-static eﬀects Solid-State Electron. 36 391–6 [56] Pejcinovic B, Kay L E, Tang T W and Navon D H 1989 Numerical simulation and comparison of Si BJTs and Si1−x Gex HBTs IEEE Trans. Electron Devices 36 2129–37 [57] Chen J, Gao G B and Morkoc H 1992 Comparative analysis of the highfrequency performance of Si/Si1−x Gex heterojunction bipolar and Si bipolar transistors Solid-State Electron. 35 1037–44 [58] Roulston D J and McGregor J M 1992 Eﬀect of bandgap gradient in the base region of SiGe heterojunction bipolar transistors Solid-State Electron. 35 1019–20 [59] Gao G-B and Morkoc H 1991 Base transit time for SiGe-base heterojunction bipolar transistors Electron. Lett. 27 1408–10 [60] Won T and Morkoc H 1989 High speed performance of Si/Si1−x Gex heterojunction bipolar transistors IEEE Electron Device Lett. 10 33–5 [61] Hueting R J E, Slotboom J W, Pruijmboom A, de Boer W B, Timmering E C and Cowern N E B 1996 On the optimization of SiGe-base bipolar transistors IEEE Trans. Electron Devices 43 1518–24 [62] Nuernbergk D M, Forster H, Schwierz F, Yuan J S and Paasch G 1997 Comparison of Monte Carlo, energy transport, and drift–diﬀusion simulations for an Si/SiGe/Si HBT High Performance Electron Devices for Microwave and Optoelectronic Applications, EDMO pp 19–24 [63] Jungemann C, Bartels M, Keith S and Meinerzhagen B 1998 Eﬃcient methods for Hall factor and transport coeﬃcient evaluation for electrons

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and holes in Si and SiGe based on a full-band structure Extd. Abstr. Sixth Int. Workshop on Computational Electronics, IWCE-6 pp 104–7 Keith S, Jungemann C, Decker S, Neinhus B, Bartels M and Meinerzhagen B 1999 Full-band Monte Carlo device simulation of an Si/SiGe HBT with a realistic Ge proﬁle Int. Conf. on Simulation of Semiconductor Processes and Devices, SISPAD’99 pp 219–22 Bartels M, Decker S, Neinhus B, Bacht K H, Schuppen A and Meillerzhagen B 1999 Comprehensive hydrodynamic simulation of an industrial SiGe heterobipolar transistor IEEE BCTM Proc. pp 105–8 Comfort J H, Patton G L, Cressler J D, Lee W, Crabbe E F, Meyerson B S, Sun J Y-C, Stork J M C, Lu P-F, Burghartz J N, Warnock J, Scilla G, Toh K-Y, D’Agostino M, Stanis C and Jenkins K 1990 Proﬁle leverage in self-aligned epitaxial Si or SiGe base bipolar technology IEEE IEDM Tech. Dig. pp 21–4 Burghartz J N, Comfort J H, Patton G L, Meyerson B S, Sun J Y-C, Stork J M C, Mader S R, Stanis C L, Scilla G J and Ginsberg B J 1990 Self-aligned SiGe-base heterojunction bipolar transistor by selective epitaxy emitter window (SEEW) technology IEEE Electron Device Lett. 11 288–90 Harame D, Nguyen-Ngoc D, Stern K, Larson L, Case M, Kovacic S, Voinigescu S, Cressler J, Tewksburg T, Gorves R, Eld E, Sunderland D, Rensch D, Jeng S, Malinowski J, Gilbert M, Schonenberg K, Ahlgren D and Meyerson B 1995 SiGe HBT technology: device and application issues IEEE IEDM Tech. Dig. pp 731–4 Crabbe E F, Comfort J H, Lee W, Cressler J D, Meyerson B S, Megdanis A C, Sun J Y-C and Stork J M C 1992 73 GHz self-aligned SiGe-base bipolar transistors with phosphorus-doped polysilicon emitters IEEE Electron Device Lett. 13 259–61 Meyerson B S 1986 Low temperature silicon epitaxy by ultrahigh vacuum/chemical vapor deposition Appl. Phys. Lett. 48 797–9 Patton G L, Stork J M C, Comfort J H, Crabbe E F, Meyerson B S, Harame D L and Sun J Y-C 1990 SiGe-base heterojunction bipolar transistors: physics and design issues IEEE IEDM Tech. Dig. pp 13–16 Gruhle A, Kibbel H, Konig U, Erben U and Kasper E 1992 MBE-grown Si/SiGe HBTs with high β, fT and fmax IEEE Electron Device Lett. 13 206–8 Schuppen A, Erben U, Gruhle A, Kibbel H, Schumacher H and Konig U 1995 Enhanced SiGe heterojunction bipolar transistors with 160 GHz fmax IEEE IEDM Tech. Dig. pp 743–6 Meister T F, Schafer H, Franosch M, Molzer W, Auﬁnger K, Scheler U, Walz C, Stolz M, Boguth S and Bock J 1995 SiGe base bipolar technology with 74 GHz fmax and 11 ps gate delay IEEE IEDM Tech. Dig. pp 739–42 Washio K, Kondo M, Ohue E, Oda K, Hayami R, Tanabe M, Shimamoto H and Harada T 1999 A 0.2 µm self-aligned SiGe HBT featuring 107 GHz fmax and 6.7 ps ECL IEEE IEDM Tech. Dig. pp 557–60 Zerounian N, Aniel F, Adde R and Gruhle A 2000 SiGe heterojunction bipolar transistor with 213 GHz fT at 77 K Electron. Lett. 36 1076–8 Harame D L, Stork J M C, Meyerson B S, Hsu K Y J, Cotte J, Jenkins K A,

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Design of SiGe HBTs Cressler J D, Restle P, Crabbe E F, Subbanna S, Tice T, Scharf B W and Yasaitis J A 1993 Optimization of SiGe HBT technology for high speed analog and mixed-signal applications IEEE IEDM Tech. Dig. pp 874–6 Crabbe E F, Comfort J H, Cressler J D, Sun J Y-C and Stork J M C 1993 High-low polysilicon-emitter SiGe-base bipolar transistors IEEE Electron Device Lett. 14 478–80 Crabbe E F, Cressler J D, Patton G L, Stork J M C, Comfort J H and Sun J Y-C 1993 Current gain rolloﬀ in graded-base SiGe heterojunction bipolar transistors IEEE Electron Device Lett. 14 193–5 Lu P-F, Comfort J H, Tang D D, Meyerson B and Sun J Y-C 1990 The implementation of a reduced-ﬁeld proﬁle design for high-performance bipolar transistors IEEE Electron Device Lett. 11 336–8 Johnson E O 1965 Physical limitation on frequency and power parameters of transistors RCA Rev. pp 163–77 Patton G L, Comfort J H, Meyerson B S, Crabbe E F, Scilla G J, de Fresart E, Stork J M C, Sun J Y-C, Harame D L and Burghartz J 1990 63–75 GHz fT SiGe-base heterojunction bipolar technology Dig. of Symp. on VLSI Technol. pp 49–50 Patton G L, Comfort J H, Meyerson B S, Crabbe E F, Scilla G J, De Fresart E, Stork J M C, Sun J Y-C, Harame D L and Burghartz J N 1990 75 GHz fT SiGe-base heterojunction bipolar transistors IEEE Electron Device Lett. 11 171–3 Antognetti P and Massobrio G 1987 Semiconductor Device Modeling with SPICE (New York: McGraw-Hill) McAndrew C C, Seitchik J A, Bowers D F, Dunn M, Foisy M, Getreu I, McSwain M, Moinian S, Parker J, Roulston D J, Schroter M, van Wijnen P and Wagner L F 1996 VBIC95, the vertical bipolar inter-company model IEEE J. Solid-State Circuits 31 1476–83 Hamel J S 1996 An accurate charge control approach for modelling excess phase shift in the base region of bipolar transistors IEEE Trans. Electron Devices 43 1092–8 Lee S, Ryum B R and Kang S W 1994 A new parameter extraction technique for small-signal equivalent circuit of polysilicon emitter bipolar transistors IEEE Trans. Electron Devices 41 233–8 Van den Biesen J J H 1986 A simple regional analysis of transit times in bipolar transistors Solid-State Electron. 29 529–34 Ashburn P 1988 Design and Realization of Bipolar Transistors (Chichester: Wiley) Roulston D J 1990 Bipolar Semiconductor Devices (Singapore: McGrawHill) Kroemer H 1982 Heterojunction bipolar transistors and integrated circuits Proc. IEEE 70 13–25 Shaﬁ Z A, Ashburn P and Parker G J 1990 Predicted propagation delay of Si/SiGe heterojunction bipolar ECL circuits IEEE J. Solid-State Circuits 25 1268–76 Fang W 1990 Accurate analytical delay expressions for ECL and CML circuits and their applications to optimizing high-speed bipolar circuits IEEE J. Solid-State Circuits 25 572–83

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Chapter 5 SIMULATION OF SIGE HBTS

In chapter 3, we discussed the operating principle of a SiGe HBT, while in chapter 4 we focused on the basics of physical device simulation and gave some examples of its application. In particular, it has been shown that 2D simulations may be used with conﬁdence for an accurate prediction of device performance. In this chapter, we develop this concept further by considering the simulation of some state-of-the-art SiGe HBTs, concentrating on those that have given particularly noteworthy performance. As SiGe technology continues to develop with device scaling, performance will naturally tend to improve, so we are only endeavouring to present particular examples in some detail. In section 5.2, we consider the device described by Meister et al [1]. This device was noteworthy in 1995 as the epitaxial-base (epi-base) bipolar technology was extended to SiGe technology, leading to a maximum oscillation frequency of 74 GHz and a CML gate delay time of 11 ps. In section 5.3, a later generation device [2] is simulated. In this device, particular attention has been paid to reproducing the two-dimensional structure. Excellent agreement in both fT and fmax has been achieved. In section 5.4, we show how, in a transistor with a very thin base, conventional drift–diﬀusion simulation tends to overestimate the transit time and a hydrodynamic simulation can in principle give a more accurate result for a transistor when fT exceeds 100 GHz. If SOI material is used as a substrate in a bipolar transistor, signiﬁcant reduction in collector–substrate capacitance can be achieved with consequent improvement in fmax [3]. However, self-heating of the silicon island in which the HBT is formed can be problematic [4, 5]. In section 5.5, a thermal simulation of a SiGe HBT fabricated in an SOI substrate is presented. Problems encountered for the low-temperature operation of Si BJTs can be solved eﬀectively by using heterojunction technology. Section 5.6 describes examples of low-temperature simulation. Because of its bandgap152

Simulation of SiGe HBTs

153

engineered base, the SiGe HBT is particularly suitable for operation at cryogenic temperature [6–12]. Since the bandgap of the emitter is larger than that of the base, therefore the current gain increases at low temperature. Since doping in the base of an HBT can be very high, carriers do not freeze at low temperature. While most digital applications involve the use of ECL technology, SiGe technology oﬀers the potential for reducing the delay of an integrated injection logic (I2 L) gate. I2 L is a low-power bipolar technology suitable for VLSI which traditionally has suﬀered from a relatively poor dynamic performance. There has been renewed interest in I2 L, motivated by the impressive performance reported for SiGe HBTs [13,14]. The gate delay of I2 L circuits is primarily determined by stored charge in parasitic diodes

Figure 5.1. Doping proﬁle and Ge proﬁle (graded base) of a SiGe HBT.

154

Simulation of SiGe HBTs

associated with the extrinsic base region [15]. The lower bandgap of SiGe therefore has a great impact on the propagation delay of integrated injection logic. It is shown by simulation in section 5.7 that that SiGe I2 L may be a useful technology in high-performance and low-power applications, such as portable electronic systems [16]. As SiGe HBT technology appears to be exceptionally promising for RF and microwave analogue applications, the low-frequency noise performance, a key ﬁgure-of-merit, needs to be studied in detail. Section 5.8 presents a comprehensive study on the noise performance of SiGe HBTs with

Figure 5.2. Gummel plot of a graded base SiGe HBT.

Epitaxial-base SiGe HBT (1995)

155

comparison to AlGaAs/GaAs HBTs and conventional Si BJTs fabricated in diﬀerent technologies. Finally, in section 5.9, the potential for SiGe technology in a radiation intensive environment is considered. 5.1.

EPITAXIAL-BASE SIGE HBT (1995)

In chapter 4, we established that, to design a high-performance HBT, it was desirable to use a low-doped emitter, thin base with a graded Ge proﬁle and retrograde collector proﬁle. In this section, the accuracy of the simulation is assessed, by comparison with devices recently reported in the literature. To optimize the high-frequency performance of a device, a nominal target of fT ∼ fmax was used.

Figure 5.3. The dc current gain of a graded base SiGe HBT.

156

Simulation of SiGe HBTs

Epi-base technology has many advantages over ion-implanted technology. An implantation tail can be avoided and the resultant box-like doping proﬁle provides independent control over base width and doping concentration. Using epi-base technology, Meister et al [1] have reported an experimental SiGe HBT. A base width of about 500 ˚ A and a peak base doping concentration (6 × 1018 cm−3 ) were used. The structure, including the Ge and doping proﬁles used in simulation, is shown in ﬁgure 5.1. The Ge concentration in the base has been graded from 0% at the emitter–base junction to 12% at the centre of the base.

Figure 5.4. Typical output characteristics of a graded base SiGe HBT as a function of collector doping.

Epitaxial-base SiGe HBT (1995)

157

Figure 5.2 shows the simulated Gummel plot and it is seen that almost ideal base current characteristics are observed, with a peak dc current gain of approximately 210, as shown in ﬁgure 5.3. A unilateral power gain of 22 dB at 10 GHz was achieved at a base–collector voltage of 2 V. Even for a base width of about 500 ˚ A, a high base doping (> 6 × 1018 cm−3 ) maintains a low base resistance and avoids punch-through. In particular, the high fmax of 74 GHz originates from the integration of the SiGe base, providing high cut-oﬀ frequency at low intrinsic base resistance. The design can be tailored for optimum ECL or CML performance by obtaining high fT at low base resistance leading to a CML gate delay time of 11 ps. The eﬀect of collector doping on the Early voltage obtained from the simulated output characteristics is shown in ﬁgure 5.4. These characteristics are obtained by utilizing a constant base current, (Ib = 15 nA), as opposed to the more usual ﬁxed base voltage boundary conditions. It is seen that as the collector doping concentration increases, the Early voltage decreases. This reduction in Early voltage with the increase in collector doping density is expected from the consideration of equation (3.25) in chapter 3, as a higher collector concentration gives a higher base–collector capacitance and hence lower Early voltage. The Early voltage for the lowest collector doping of 5 × 1016 cm−3 is 110 V, leading to a βVA product of 22 000. A Ge fraction of 12% at the base–collector junction has helped to provide a high Early voltage. The dependence of cut-oﬀ frequency on the collector current is shown in ﬁgure 5.5 for two diﬀerent base–collector voltages, while ﬁgure 5.6 shows

Figure 5.5. Eﬀect of base–collector reverse bias voltage on the cut-oﬀ frequency of a graded base SiGe HBT.

158

Simulation of SiGe HBTs

Figure 5.6. Cut-oﬀ frequency versus Ic of a graded base SiGe HBT.

a comparison of simulated and measured fT with collector current. It is evident that while the overall match is good, indicating good agreement of emitter–base and base–collector capacitance, the simulated values are slightly below the measured values. It is believed that this may be due to a small inaccuracy in the drift–diﬀusion model in predicting base transit time in thin base transistors. This point is more fully discussed in section 5.3. A direct comparison of major experimental and simulated ﬁgures-of-merit is shown in table 5.1. While excellent agreement has been obtained for fT , the simulation overestimates fmax , possibly due to an underestimate of base resistance.

Table 5.1. Comparison of simulated device parameters. Parameter

Experimental [1]

Simulation

Emitter size, Ae Current gain, β Breakdown voltage, BVceo Early voltage, VA Cut-oﬀ frequency, fT Maximum frequency oscillation, fmax

0.27 × 2.5 µm 220 3.0 130 V 61 GHz 74 GHz

210 3.0 120 V 57 GHz 105 GHz

Double polysilicon self-aligned SiGe HBT (1998) 5.2.

159

DOUBLE POLYSILICON SELF-ALIGNED SIGE HBT (1998)

In this section we consider an alternative SiGe HBT, discussed by Kondo et al [2]. The device structure is illustrated in detail in ﬁgure 5.7. It has the same structure as a conventional double polysilicon bipolar transistor. A borophosphosilicate (BPSG) reﬁlled trench is used for isolation. Since the dielectric constant of BPSG is about one third that of silicon, substrate capacitance is therefore minimized. A wedge-shaped CVD silicon dioxide isolation structure below the p+ -polySi base electrode helps reduce base– collector capacitance. Both SiGe base and polySi SiGe contact are selfaligned on the n-collector and p+ -polySi SiGe sidewall inside the window. Hence, the width of the base–collector junction has been reduced to that of the 0.5 µm emitter window. The intrinsic base consists of a 200 ˚ A undoped SiGe layer, a 300 ˚ A − ˚ p -type graded SiGe layer and a 150 A undoped silicon layer. A SIMS plot is shown in ﬁgure 5.8. For ATLAS simulation, the peak emitter doping of 1020 cm−3 (n+ -type), the peak base doping of 5 × 1018 cm−3 (p-type) and the collector doping of 5×1016 cm−3 (n-type) were considered. The characteristic length of the Gaussian base proﬁle is 0.0145 µm. The germanium fraction x is graded linearly, from a peak value of 0.145, down to zero at the emitter–base junction. Full details of the simulation are given in [17].

Figure 5.7. Schematic cross section of the ultra low-power SiGe base bipolar transistor with a wedge-shaped CVD-SiO2 isolation and a BPSG-reﬁlled trench. (After Kondo M et al 1998 IEEE Trans. Electron Devices 45 1287–94.)

160

Simulation of SiGe HBTs

Figure 5.8. A SIMS impurity proﬁle of the emitter and the base in the intrinsic region. (After Kondo M et al 1998 IEEE Trans. Electron Devices 45 1287–94.)

Figure 5.9. Comparison of Gummel plot for a SiGe HBT. (After Hamel J S and Tang Y T 2000 Proc. ESSDERC pp 620–3.)

The Gummel plot simulated by ATLAS is shown in ﬁgure 5.9, along with the published result for comparison. Since great care has been taken to model both the doping proﬁle and two-dimensional structure, excellent agreement has been achieved for the collector current. The higher

Double polysilicon self-aligned SiGe HBT (1998)

161

Figure 5.10. Comparison of simulated and experimental fmax and fT as a function of collector current. (After Hamel J S and Tang Y T 2000 Proc. ESSDERC pp 620–3.)

base current simulated by ATLAS could be due to lower hole lifetime in the emitter, but insuﬃcient detail regarding the polysilicon interface is available in the original paper [2] to enable more precise modelling. The respective simulated and published values of fT and fmax have been compared in ﬁgure 5.10. The agreement is excellent with the simulation showing a peak fmax of 70 GHz and a peak fT of 40 GHz at around 200 µA. It would appear therefore that inaccuracy in the simulated base current does not aﬀect the accuracy of the high-frequency modelling. Subsequently, this transistor has been used as the basis of a simulation study which oﬀers a comparison between vertical and lateral HBTs [18]. The simulation predicts a potential twofold improvement in fmax , and at signiﬁcantly lower bias current compared to the vertical SiGe HBT, for a given minimum lithography. The relevant comparison is shown in ﬁgure 5.11. The improved fmax is attributed to an order of magnitude improvement in the rbb Cbc time constant in the lateral HBT. Although speciﬁc device structures were utilized, the same active region proﬁles and identical minimum lithography ensured a meaningful comparison. The factor of two improvement predicted for lateral SiGe HBT on SOI technology gives a general indication as to how bipolar technology is likely to evolve over the next decade. As minimum lithography decreases, the SOI layer thickness in the lateral HBT can be made thinner to continue to provide improvement in performance.

162

Simulation of SiGe HBTs

Figure 5.11. Comparison of frequency performance versus dc collector current between vertical and lateral SiGe HBTs. (After Hamel J S and Tang Y T 2000 Proc. ESSDERC pp 620–3.)

5.3.

ENERGY BALANCE SIMULATION

As discussed in chapter 4, the drift–diﬀusion approximation can lead to inaccuracy in the prediction of device characteristics, particularly when the width of the base is reduced below 30 nm. In this instance, it is necessary to perform a simulation involving energy balance [19], where the equations for current ﬂow must be modiﬁed as given in equations (4.18)–(4.21). The conventional drift–diﬀusion model of charge transport neglects non-local transport eﬀects such as velocity overshoot, diﬀusion associated with carrier temperature gradients and dependence of ionization rates on carrier energy distribution. The drift–diﬀusion approximation is a low-order approximation of the Boltzmann transport equation (BTE). Device simulation based on the solution of the full BTE is possible but requires signiﬁcant computing resources. A simpler intermediate level approximation, which oﬀers potential for improved accuracy, is therefore attractive. Essentially, the energy balance model predicts velocity overshoot relative to the carrier saturation velocity deﬁned in equation (4.28). Velocity peaks occur in regions of the device where carrier temperature is a maximum e.g., base–collector junction. High velocity gives rise to reduced transit time compared to the drift–diﬀusion model. The device considered for simulation [20] is a state-of-the-art SiGe HBT, designed to give a very high fT by incorporating a high dose selective collector implant of peak concentration of the order of 1018 cm−3 . The

Energy balance simulation

163

Figure 5.12. Germanium and doping proﬁle for a SiGe HBT with 15% Ge content. (After Oda K et al 1997 IEEE IEDM Tech. Dig. pp 791–4.)

SIMS proﬁle of the transistor, with a 15% graded Ge proﬁle is shown in ﬁgure 5.12. This proﬁle has been accurately reproduced in the input dataﬁle for ATLAS simulation. This transistor is very similar to that described in the previous section. It only diﬀers in two respects: a much higher doping density in the collector and the location of the peak collector doping lying closer to the base–collector. It was reported that the measured peak fT ranges from 110 GHz for a peak Ge content (x = 0.1) to 130 GHz (x = 0.25), as shown in ﬁgure 5.13. The simulated maximum cut-oﬀ frequency has been plotted as a function of peak collector doping in ﬁgure 5.14. It is clear that the drift– diﬀusion model predicts a maximum fT of less than 100 GHz, irrespective of the value of peak collector doping. It seems that in order to predict an fT of more than 100 GHz to match the measured value, the energy balance model appears to be required. This conclusion is in line with the observations in ﬁgure 5.6, where once again the simulated fT is less than the measured value. The diﬀerences between the energy balance and drift–diﬀusion models on emitter and base transit times are shown in ﬁgure 5.15. It is clear that the EB model predicts signiﬁcantly lower values of base transit times, suﬃcient to account for the higher measured values of fT . A comparison of extracted carrier velocity for the DD and EB models,

164

Simulation of SiGe HBTs

Figure 5.13. Maximum cut-oﬀ frequency as a function of Ge content. (After Oda K et al 1997 IEEE IEDM Tech. Dig. pp 791–4.)

Figure 5.14. Cut-oﬀ frequency versus peak collector doping in a graded base SiGe HBT.

Energy balance simulation

165

Figure 5.15. Simulated emitter and base transit time of a SiGe HBT, as a function of collector current for both drift–diﬀusion and energy balance models for Ge mole fraction x = 0.1.

Figure 5.16. Extracted carrier velocity using drift–diﬀusion and energy balance models.

166

Simulation of SiGe HBTs

Figure 5.17. Simulated electron temperature in a SiGe HBT.

as a function of base bias, for two Ge fractions (x = 0.1 and 0.2), is shown in ﬁgure 5.16. The EB model shows a signiﬁcant overshoot in the saturation velocity, suﬃcient to account for the lower base transit time in ﬁgure 5.15, while the maximum velocity possible with the DD model is limited by the saturation velocity, vsat = 8 × 106 cm s−1 . A plot of the simulated electron temperature in ﬁgure 5.17, taken as a one-dimensional section through the active device, shows the expected carrier heating associated with the high-ﬁeld region at the base–collector junction. The maximum of the temperature proﬁle is, however, shifted into the collector region, as the carriers are accelerated through the high-ﬁeld region to reach the maximum temperature. Velocity overshoot occurs in the base region, where the electric ﬁeld is high and the temperature is only beginning to rise. 5.4.

SIGE HBTS ON SOI SUBSTRATES

In Si bipolar technology, the two well-known disadvantages are: high power dissipation and low density. High power dissipation is a result of the high parasitic junction capacitance associated with using silicon as the substrate. Previously, silicon-on-insulator has been used for high-performance deep submicron CMOS, as discussed more fully in section 10.3. The advantages of utilizing a composite substrate comprising a monocrystalline semiconductor layer, such as silicon, epitaxially deposited

SiGe HBTs on SOI substrates

167

on a supporting insulating substrate, are well recognized. Major advantages include the substantial reduction of parasitic capacitance between charged active regions and the substrate, and the eﬀective elimination of leakage currents ﬂowing between adjacent active devices. Modern communication devices also present greater diﬃculties in high level integration because they require digital computing capability (logic and memory) along with analogue and RF circuitry. The need to reduce power consumption in battery powered wireless communication systems is a need which has not previously been met. While bipolar transistors fabricated on SOI substrates have been shown to oﬀer lower parasitic capacitance [21], they do have a greater susceptibility to self-heating [4, 5]. Investigations on the impact of self-heating on transistor performance and eﬀect of introduction of thermal vias to reduce temperature rise have been performed by Armstrong and Gamble [22]. Lattice heating in the SiGe HBT has been simulated by coupling the solution of the heat ﬂow equation along with the semiconductor equations: C

∂TL = ∇ (κ∇TL ) + H ∂t

(5.1)

where TL represents the lattice temperature, C the heat capacitance per unit volume and κ the thermal conductivity. The Joule heating term H, which provides the coupling between the heat ﬂow equation and the semiconductor equations, is given by H=

Jp2 Jn2 + qµn n qµp p

(5.2)

where Jn,p and µn,p represent current density and carrier mobility of electrons and holes, respectively. The temperature dependence of κ in the semiconductor is modelled by [23] κ=

1 a + bTL + cTL2

(5.3)

where for silicon and polysilicon, a = 0.03, b = 1.56×10−3 , c = 1.65×10−6 , while for silicon dioxide κ = 0.014. The SiGe HBT transistor considered for simulation (see ﬁgure 5.18) is based on SiGe technology developed at Southampton University [24]. The novel feature of this technology is selective growth of a silicon collector in an anisotropically etched oxide window, followed by non-selective growth of a SiGe base and low-doped SiGe emitter in the same growth sequence. A key aspect of the technology is the very low junction capacitance at both emitter–base and base–collector junctions. In addition, the fabrication of the transistor in a bonded substrate oﬀers the possibility of including a buried silicide layer to reduce collector resistance. Simulations indicate

168

Simulation of SiGe HBTs

Figure 5.18. Structure of a SiGe HBT on SOI used for simulation.

Figure 5.19. SiGe HBT doping proﬁle used for simulation.

SiGe HBTs on SOI substrates

169

Figure 5.20. A schematic diagram of a SiGe HBT showing diﬀerent regions. (After Armstrong G A and Gamble H S 1999 Silicon-on-Insulator Technology and Devices IX, Electrochemical Society Proceedings Series vol 99-3, ed P L Hemment (Pennington, NJ: Electrochemical Society) pp 249–54.)

that the predicted performance of an optimized Si0.9 Ge0.1 heterojunction transistor produced in SOI material utilizing minimum lithography is fmax in excess of 100 GHz and ECL gate delay of less than 10 ps. To achieve this level of performance, a minimal feature size with an emitter polysilicon width of 0.25 µm and 0.125 µm mask alignment is required. A typical base doping considered for simulation is shown in ﬁgure 5.19. Figure 5.20 illustrates a simpliﬁed structure, representative of the oxide isolated technology, with extended base and collector regions. The buried collector is shown to be thinner than would normally be used, to emphasize any potential heating eﬀect due to collector resistance. Electrical boundary conditions are applied at the emitter, base and collector contacts in the normal way. The substrate (not shown below the oxide) is assumed to be held at a ﬁxed ambient temperature. Figure 5.20 also shows the inclusion of a thermal via through the buried oxide. This via, which is created prior to bonding, acts as a heat conduction path. A thermal boundary condition

170

Simulation of SiGe HBTs

Figure 5.21. Simulated Gummel plot with and without inclusion of the heat equation. (After Armstrong G A and Gamble H S 1999 Silicon-on-Insulator Technology and Devices IX, Electrochemical Society Proceedings Series vol 99-3, ed P L Hemment (Pennington, NJ: Electrochemical Society) pp 249–54.)

is deﬁned at all three electrical contacts such that −κ

∂TL 1 (TL − Text ) = ∂n Rth

(5.4)

where Rth represents thermal resistance in K mW−1 . Figure 5.21 shows the Gummel plots, with and without the inclusion of the heat equation for the lattice heating modelling. Due to poor thermal conductivity in the buried oxide, the junction temperature rises, leading to a deviation from linearity. In the lower curve, heating has caused a 25 K rise in temperature above the ambient. The consequent increase in collector current is consistent with that value of collector current, which would occur for the same increase in ambient temperature. A comparison between the maximum temperature rise in a transistor on an SOI substrate, with two diﬀerent thicknesses of buried oxide, and the maximum temperature rise on a silicon substrate is shown in ﬁgure 5.22. For diﬀerent thermal boundary conditions (Rth ranging from 2–20 K mW−1 ), the sensitivity of the maximum temperature rise to thermal resistance, for a buried oxide of 0.4 µm, and a collector voltage of 3 V, is shown in ﬁgure 5.23. The impact of the thermal via in providing a heat conduction path through the buried oxide is shown in ﬁgure 5.24.

SiGe HBTs on SOI substrates

171

Figure 5.22. Comparison of heating eﬀect between SOI and silicon substrates. (After Armstrong G A and Gamble H S 1999 Silicon-on-Insulator Technology and Devices IX, Electrochemical Society Proceedings Series vol 99-3, ed P L Hemment (Pennington, NJ: Electrochemical Society) pp 249–54.)

Figure 5.23. Dependence of maximum temperature rise on thermal resistance in a SiGe HBT fabricated in a bonded SOI substrate. (After Armstrong G A and Gamble H S 1999 Silicon-on-Insulator Technology and Devices IX, Electrochemical Society Proceedings Series vol 99-3, ed P L Hemment (Pennington, NJ: Electrochemical Society) pp 249–54.)

172

Simulation of SiGe HBTs

Figure 5.24. Contour plots of temperature in a SiGe HBT. (After Armstrong G A and Gamble H S 1999 Silicon-on-Insulator Technology and Devices IX, Electrochemical Society Proceedings Series vol 99-3, ed P L Hemment (Pennington, NJ: Electrochemical Society) pp 249–54.)

The peak temperature occurs, as expected, within the active area of the transistor. However, it is clear that the thermal via is eﬀective in providing a heat conduction path to the silicon substrate. Although an attempt has been made to predict the thermal behaviour of HBT transistors fabricated on SOI substrates, absolute accuracy is diﬃcult to achieve because of the error in estimating the degree of external heat loss, which has been approximated using a thermal resistance boundary condition at the electrical contacts. The variation in temperature within the transistor and the dependence of the maximum temperature rise on thermal resistance have been demonstrated. The reduction in temperature, which occurs if a thermal via is included, depends on its alignment relative to the active area. 5.5.

LOW-TEMPERATURE SIMULATION

The outstanding performance advantages of a SiGe HBT for lowtemperature operation have been demonstrated experimentally in a stateof-the-art silicon bipolar process [7–10]. However, the design and optimization issues associated with the low-temperature operation of SiGe

Low-temperature simulation

173

HBTs remain unclear. Because of its bandgap-engineered base, a SiGe HBT is particularly suitable for operation at cryogenic temperature, where the exponential gain enhancement factor becomes very large. In addition, the built-in drift ﬁeld in the base is more eﬀective at low temperature, compensating for the degradation in base diﬀusivity, resulting in improvement in the cut-oﬀ frequency. It has been demonstrated [7] that present SiGe technology is capable of providing transistors with higher current gain at 77 K than at room temperature, and unloaded ECL circuits which are as fast at 77 K as they are at room temperature. The key design issues for the low operation of SiGe HBTs may be identiﬁed as follows [25]: • • • •

minimization of carrier freeze-out in the base; control of increased parasitic emitter–base tunnelling current at low temperature; design of collector proﬁle to leverage the increase in Kirk knee current density with cooling; and eﬀect of Ge grading on current gain and cut-oﬀ frequency.

Low-temperature semiconductor device simulation is a diﬃcult task because parameters, often assumed constant in conventional simulators, may actually be complex functions of temperature. Phenomena unique to low-temperature operation, such as carrier freeze-out, are typically not accounted for in simulators designed for room temperature use. In addition, the system of equations to be solved for low temperature is much more illconditioned numerically than at room temperature, due to terms having stronger exponential temperature dependency. For these reasons, available simulation programs can have diﬃculty in converging to a solution at 77 K [26, 27]. 5.5.1.

Low-temperature SiGe HBTs

Patton et al [28] studied the low-temperature operation of a SiGe HBT fabricated in a poly-emitter bipolar process. The devices showed improved low-temperature behaviour with extremely high current gains of 1600 at 77 K for devices having 7.5 kΩ/square base resistivity. Crabbe et al [6] investigated the low-temperature behaviour of Si BJTs and SiGe HBTs fabricated and optimized for room temperature operation. The authors demonstrated that introducing a spacer layer in the emitter–base junction reduced the low level parasitic emitter–base tunnelling (leakage current) at low temperature, but gave rise to carrier freeze-out and increase of base resistance at 77 K. The respective current gains were 20–40 for an Si BJT, and 100–140 for a SiGe HBT for the temperature range from 77–300 K. The graded Ge proﬁle in the base improved both the low-temperature current gain and base transit time, resulting in a peak cut-oﬀ frequency of 94 GHz at 85 K, compared to 75 GHz at 298 K.

174

Simulation of SiGe HBTs

A much improved low-temperature SiGe HBT [29], speciﬁcally designed for low-temperature operation, was fabricated using self-aligned epi-base technology [30]. Lightly-doped spacers were used at both the junctions to reduce the electric ﬁeld. The base width was approximately 59 nm and the peak concentration of the graded Ge proﬁle was 9%. For a high-power design (about 10 mW), the ECL gate delay at 84 K was 28.1 ps, roughly the same as at 310 K, yet a factor of two better than the best value obtained at that time with a low-temperature Si BJT. Low power ECL circuits showed a power delay product of 112 fJ at 84 K. The measured gate delays were in reasonable agreement with the theoretical predictions [31]. At that time, these results represented a signiﬁcant advance in performance of silicon-based bipolar technology at 77 K. During the 1990s, the research group at IBM [7, 9, 10] reported progressive further improvements in the low-temperature performance of SiGe HBTs. A low thermal budget allowed a sharp transition from a lowdoped emitter to a heavily-doped base, making the base immune to carrier freeze-out at 77 K. At 84 K, transistors showed a current gain of 500, fT of 61 GHz and ECL gate delay of 21.9 ps, 3.5 ps faster than at room temperature. Typical parameters and performance of the transistors at 310 and 84 K for the epitaxial emitter-cap (no spacer) design and an i–p–i (with spacers) design, are given in table 5.2. The eﬀect of introducing lightly-doped spacer layers at both the emitter–base and base–collector junctions was studied in detail [9]. The

Table 5.2. Typical SiGe HBT parameters at 310 and 84 K at the wafer level. (After Cressler et al 1994 IEEE Electron Device Lett. 15 472–4.) Temperature SiGe proﬁle βmax β at 1.0 mA Peak gm (mS) Rbi (kΩ/square) Re (Ω) Ieb (nA) BVceo (V) BVcbo (V) Cbe (fF µm−2 ) Cbc (fF µm−2 ) Peak fT (GHz) Peak fmax (GHz) ECL delay (ps)

310 K

84 K

Emitter-cap design 102 94 62 7.7 14.3 8.44 × 104 3.1 10.8 5.47 0.46 43 40 25.4

498 99 113 11.0 11.0 1.91 × 103 2.1 9.6 5.13 0.40 61 50 21.9

310 K

84 K

i–p–i design 105 96 74 8.2 82 2.89 3.2 10.8 6.30 1.04 53 37 26.0

82 34 83 15.9 15.9 1.11 3.2 9.5 5.90 0.93 59 48 30.4

Low-temperature simulation

175

spacer layer reduced the low level parasitic base leakage but gave rise to carrier freeze-out and an increase of base resistance at 77 K. However, it was shown that a thin abrupt base proﬁle attainable with epitaxial processing is particularly useful for low-temperature operation since the resultant proﬁle is less sensitive to base freeze-out than ion-implanted proﬁles. The authors also fabricated homojunction Si BJTs and showed that properly designed homojunction transistors also have suﬃcient current gain and switching speed at 77 K for many digital applications. In several applications, however, the ﬂexibility oﬀered by using SiGe for base layer yields great beneﬁts. Gruhle et al [12] have reported a high-performance SiGe HBT, fabricated using MBE, having a base doping of 2 × 1019 cm−3 , largely exceeding the emitter impurity level and a base sheet resistance of about 1 kΩ/square. The device exhibited an Early voltage of 500 V, a maximum room temperature current gain of 550 rising to 13 000 at 77 K. Devices built on buried-layer substrates exhibited an fmax of 40 GHz and an fT of 42 GHz. Sturm et al [32] also fabricated high-quality SiGe HBTs using rapid thermal chemical vapour deposition. Both graded-base and uniform Ge proﬁles in the base were considered. In a transistor with 20% uniform Ge concentration in the base, currents gain of about 2000 at room temperature and 11 000 at 133 K were observed. The performance of SiGe HBTs at liquid helium temperature has been reported by Joseph et al [8]. The current gain of a self-aligned, UHVCVD-grown SiGe HBT showed an increase in current gain from 110 at 300 K to 1045 at 5.85 K, although parasitic base current leakage limits the useful operating current to above about 1.0 µA at 5.84 K. A very high base doping (peak at 8 × 1018 cm−3 ) was used to suppress the base freeze-out at 4.48 K and resulted in a base sheet resistance of 18.3 kΩ/square. 5.5.2.

Low-temperature simulation using ATLAS

In order to understand the impact of the Ge proﬁle and base doping in the design of a low-temperature SiGe HBT, simulations were performed using ATLAS 2D device simulator on two separate base doping proﬁles, and two diﬀerent Ge proﬁle shapes: (i) a box Ge proﬁle (uniform Ge content, x = 0.20, not shown) (ii) a graded Ge proﬁle (see ﬁgure 5.25). Figure 5.26 shows Gummel plots at 300 and 100 K, respectively, for constant Ge concentration. The simulated collector current characteristic is ideal over more than ten decades of current. As the temperature is lowered, the intrinsic carrier concentration decreases exponentially, and for an observable current to ﬂow at low temperature, the emitter–base voltage

176

Simulation of SiGe HBTs

Figure 5.25. Doping proﬁle and Ge proﬁle (graded case) in a SiGe HBT.

must be increased substantially, as may be seen from ﬁgure 5.26. As the dc current gain depends exponentially on the bandgap narrowing present at the emitter edge of the neutral base [33], the box Ge proﬁle (x = 0.2) produces a larger enhancement in β, in ﬁgure 5.27, than the graded proﬁle in ﬁgure 5.25. In the former diagram, a peak dc current gain as high as 11 000 is predicted at 100 K, compared to the more moderate enhancement for the graded Ge. In the latter case, the predicted current gain at 150 K of 900 is more than adequate for successful circuit operation at such a low temperature. A contributory factor to the high current gain at low temperature is the low level of bandgap narrowing in the relatively lightlydoped 5 × 1018 cm−3 single-crystal emitter. Richey et al [34] have shown close agreement with measurements for low-temperature SiGe HBT simulations, using a calibrated doping proﬁle based on SIMS data. The authors have used the 1D simulator SCORPIO to examine the eﬀects of Ge proﬁle shape and base proﬁle scaling on temperature. Some of these results are presented below. It has been

Low-temperature simulation

177

Figure 5.26. Gummel plots of a SiGe HBT (ﬂat base) at 300 and 100 K.

shown in chapter 4 that a triangular Ge proﬁle in the base produces more enhancement in cut-oﬀ frequency and βVA product than a box Ge proﬁle. The bandgap grading associated with the triangular Ge proﬁle induces a drift ﬁeld that helps accelerate electrons across the base, decreasing the base transit time. Figures 5.28–5.30 show dependence of cut-oﬀ frequency fT , relative improvement in fmax and βVA product on temperature, for box and graded Ge proﬁles, at diﬀerent dc bias points. Three separate sets of base doping proﬁle are used and, for each set, two Ge proﬁles—a box proﬁle and a linearly graded proﬁle—are considered. Each Ge proﬁle has the same stability point as deﬁned by Matthews and Blakeslee [35, 36], i.e. the integrated Ge concentration is held constant. Three stability points are referenced. Stability point 1 refers to a state-of-the-art device, with an eﬀective Ge thickness of 120 nm and a base width of 90 nm. For the second stability point, the base proﬁle has been scaled by one half while base

178

Simulation of SiGe HBTs

Figure 5.27. The dc current gain of a ﬂat base SiGe HBT at diﬀerent temperatures. For comparison, dc current gain at 150 K for a graded base transistor is shown.

Figure 5.28. Cut-oﬀ frequency comparisons over temperature. Richey D M et al 1997 IEEE Trans. Electron Devices 44 431–40.)

(After

Low-temperature simulation

179

Figure 5.29. Enhancements in maximum oscillation frequency. Richey D M et al 1997 IEEE Trans. Electron Devices 44 431–40.)

(After

Figure 5.30. Current gain–Early voltage product enhancements. Richey D M et al 1997 IEEE Trans. Electron Devices 44 431–40.)

(After

180

Simulation of SiGe HBTs

doping is increased to maintain the same pinched base resistance. Stability point 3 is identical to the previous case, except that the Ge content is doubled. For all three scaled proﬁles, both the collector proﬁle and emitter depth are unaltered. For all parameters, the enhancement factor increases signiﬁcantly as the temperature is reduced. The relative improvement for the graded Ge proﬁle at low temperature is due to the greater eﬀectiveness of the drift ﬁeld in compensating for degradation in diﬀusivity. The simulation suggests that for low-temperature operation, a box Ge proﬁle may be used for maximizing dc current gain and fT , but this is a more sensitive function of temperature than the triangular proﬁle. In conclusion, the box Ge proﬁle produces the greatest enhancement in β, fT and fmax over temperature, while the triangular Ge proﬁle produces the greatest enhancement in βVA product. 5.6.

I2 L CIRCUITS USING SIGE HBTS

High-performance bipolar logic circuits are usually realized using emitter coupled logic (ECL) which has a relatively low packing density and high power dissipation. The gate delay of I2 L circuits is primarily determined by stored charge in parasitic diodes associated with the extrinsic base regions of the I2 L gate [15]. SiGe technology oﬀers the prospect of using bandgap engineering to minimize the stored charge in the parasitic diodes associated with the I2 L gate. Hence, the use of a heterojunction can add high speed to the other well-known advantages of I2 L technology, namely high packing density, low voltage and low power dissipation. Experimental results on SiGe integrated injection logic circuits (surface-fed and substratefed variants) have been reported [16]. Figure 5.31(a) shows the cross section of an I2 L gate and ﬁgure 5.31(b) a circuit diagram. The cross section shows the merged structure of the I2 L gate, with the SiGe layer used both as the base of the npn transistor and the collector of the pnp transistor. The npn switching transistor operates

Figure 5.31. Schematic cross-section (a) and circuit diagram (b) of an I2 L. (After Wainwright S P et al 1996 Proc. ESSDERC pp 649–52.)

I2 L circuits using SiGe HBTs

181

in the inverse mode, which allows multiple collectors to be produced using n+ -polySi contacts to the top n-type silicon layer. A polysilicon contact is also used to connect to the base of the pnp injector transistor. The emitter (injector) of the pnp transistor is formed in the top 300 nm n-type silicon layer using a BF2 implant through a 50 nm screen oxide. This SiGe I2 L technology therefore uses a vertical pnp transistor in contrast to the lateral pnp transistor used in conventional silicon I2 L technologies. A Gummel plot of a 3 µm npn switching transistor, operated in upward mode in an I2 L gate with three collectors, gave a maximum current gain of 14. The collector current characteristic was ideal over several decades of current, while the ideality factor of the base current was 1.28. The measured output characteristic is shown in ﬁgure 5.32 and indicates a breakdown voltage BVceo of about 2.9 V. A low gain of 1.4 for the pnp transistor was not deemed to be important for the operation of the I2 L gate, provided that the ratio of saturation currents for the pnp and the npn transistors was much greater than unity. Figure 5.33 compares the measured and modelled [37] switching time as a function of injector current per gate. The measured and modelled values agree quite closely, with the measured values being about 40% faster. For optimization of SiGe integrated injection logic (I2 L) circuits, a quasi two-dimensional stored charge model has been developed [16]. It has

Figure 5.32. Output characteristics (upward mode) of the npn SiGe HBT. (After Wainwright S P et al 1996 Proc. ESSDERC pp 649–52.)

182

Simulation of SiGe HBTs

Figure 5.33. Comparison of measured and modelled I2 L gate delay. (After Wainwright S P et al 1996 Proc. ESSDERC pp 649–52.)

been shown that at low injector currents, the use of SiGe oﬀers only a marginal beneﬁt, since the switching speed is dominated by depletion region charge. However, at high injection currents, where the switching speed is dominated by stored minority carrier charge, the use of SiGe in I2 L technology has been shown to have important beneﬁts. The inclusion of 16% Ge in the substrate-fed I2 L gate leads to a decrease in the dominant stored charge by a factor of more than ten, which suggests that gate delays well below 100 ps should be achievable, even at a geometry of 3 µm. The model has also been applied to predictions of the performance of a self-aligned structure, speciﬁcally optimized for SiGe I2 L. For a Ge concentration of 16% in the base, a maximum delay of 34 ps was predicted using 1.4 µm design rules. 5.7.

NOISE PERFORMANCE

Diﬀerent types of noise mechanisms are found to be present in semiconductors [38]. Among them the low-frequency noise, typically observed to exhibit a dependence on frequency, is very important for analogue and mixed-signal applications. Low-frequency noise is known to degrade the spectral purity of nonlinear radio frequency (RF) and

Noise performance

183

microwave circuits, such as oscillators and mixers, where the low-frequency, baseband noise generates noise sidebands around the RF or microwave carrier signal [39]. Low-frequency noise in UHVCVD-grown Si and SiGe bipolar transistors has been studied by Vempati et al [40]. The authors have made a comprehensive study by comparing diﬀerent technologies and have demonstrated that the SiGe devices have excellent noise properties compared to AlGaAs/GaAs HBTs and conventional Si bipolar junction transistors. Low-frequency noise has been characterized as a function of bias, geometry and temperature [41, 42]. The transistors used were fully integrated, self-aligned devices, with shallow and deep trench isolation, silicided extrinsic base and contacts, two levels of metallization and a conventional poly-emitter contact. Two diﬀerent bias conﬁgurations were used to distinguish the various noise sources contributing to noise in the Si and SiGe bipolar transistors. The devices were biased in low injection (Ib ∼ 2.25 µA) in order to eliminate any second-order parasitic resistance eﬀects and spurious noise due to weak impact ionization. The collector current was also limited to several milliamps, so that the shot noise due to the collector current was negligible compared to the base current shot noise. Common-emitter conﬁguration with high input impedance was used for measuring the base noise. In order to determine the collector noise and the contributions, if any, of the parasitic series resistances, the devices were biased in the common-collector conﬁguration. Typical curves of the equivalent input-referred base current noise spectra for Si and SiGe devices are shown in ﬁgure 5.34. At low frequencies, the noise rises over the shot noise and thermal noise background and exhibits an expected spectrum for frequencies below 1 kHz. Within the scatter of data (approximately 50 devices for both Si and SiGe combined were measured) the slope of the spectrum varies as 1/f . The roll-oﬀ of the spectra above 10 kHz is due to the Miller capacitance associated with the device and packaging. As temperature excursions are important in analogue applications, noise measurements were made over the range of −55 ◦ C to 85 ◦ C. Figure 5.35 shows the temperature dependence of the noise spectra of Si and SiGe transistors at a ﬁxed base current of 2.25 µA. It is observed that the noise spectral density exhibits a clear 1/f behaviour without any anomalous behaviour in the slope across this temperature range. The noise spectra for Si and SiGe devices are similar, and have no signiﬁcant temperature dependence. The authors concluded that the combination of an inverse of area dependence on geometry and nearquadratic dependence on base current suggests that the noise sources are homogeneously distributed over the entire emitter area and not restricted only to the emitter periphery. Comparisons with diﬀerent technologies

184

Simulation of SiGe HBTs

Figure 5.34. Equivalent input-referred base noise current spectral density at a base current of 2.25 µA for multi-stripe Si and SiGe transistors with an emitter area 3 × 0.5 µm and comparable doping proﬁles. The inferred 1/f to shot noise corner frequencies are 480 Hz and 373 Hz for Si and SiGe transistors, respectively. (After Vempati L S et al 1996 IEEE J. Solid-State Circuits 31 1458–67.)

Figure 5.35. Noise spectral density at two diﬀerent temperature points (358 and 218 K) of Si and SiGe devices of an emitter area of 3 × 0.5 µm. (After Vempati L S et al 1996 IEEE J. Solid-State Circuits 31 1458–67.)

Noise performance

185

demonstrate that the Ge incorporated in the base does not degrade the noise performance and that SiGe HBTs have better noise performance than AlGaAs/GaAs HBTs and conventional ion-implanted Si BJTs. Even though SiGe HBTs have demonstrated better noise performance over Si BJTs at low frequency, even better high-frequency noise characteristics may be expected if the Ge proﬁle is optimized speciﬁcally to address this issue. The SiGe HBT design issues associated with minimization of broadband noise have been considered by Ansley et al [43]. Using the 1D simulator SCORPIO, the eﬀect of the Ge proﬁle in the base on the minimum noise ﬁgure at high frequency was theoretically investigated. The analysis was based on an equivalent circuit noise model originally formulated by Hawkins [44], as shown in ﬁgure 5.36. The model accounts for thermal noise in the source (vs ), base resistance (vb ), shot noise in the emitter (ve ) and collector partition noise (icp ). The resulting expression for noise factor may be approximated with suﬃcient accuracy by Rb Re (1 − (2πf )Cje Xs )2 2 F 1+ + + (2πf )Cje Rs Rs 2 Rs 1 + (2πf )2 τb2 Rs Xs2 + (5.5) −1 + α0 2Re 2Re Rs where Rs is the source resistance, Xs is the source reactance, Re is the dynamic emitter resistance (thermal voltage divided by emitter current) and Cje is the emitter–base depletion capacitance, α0 is the common base dc current gain and f is the frequency at which the noise factor is evaluated. This formulation helps in determining the relative contribution of each of the terms which control the noise factor. As a guide, the presence of Ge

Figure 5.36. Equivalent circuit schematic of Hawkin’s noise model for bipolar transistors. (After Hawkins R J 1977 Solid-State Electron. 20 191–6.)

186

Simulation of SiGe HBTs

reduces the noise factor by decreasing τb , decreasing base resistance Rb and allowing the possibility of increased current gain. The minimum noise ﬁgure, NFmin is given by 10 log(F) when Rs is set to the optimum source resistance Ropt which may be approximated as Ropt ≈

2Rb Re + a

Re2 2 − Xopt 2

(5.6)

and the optimum source reactance Xopt is given by Xopt ≈ where a≈

(2πf )2 Cje Re2 a 2

(5.7) 2

((2πf )τje ) 1 ((2πf )τb ) + . + β α0 α0

(5.8)

When considering the Ge proﬁle, the best noise performance is achieved with the greatest amount of Ge in the neutral base region, subject to the maximum acceptable β and the strained layer stability constraints. In what was essentially a theoretical study, a novel optimized Ge proﬁle to achieve minimum noise ﬁgure was developed, as shown in ﬁgure 5.37, which compares the new proﬁle with a traditional trapezoidal proﬁle of the same average Ge content. Simulations using this proﬁle at 10 GHz indicated an improvement of almost 1 dB in the minimum noise ﬁgure over an equivalent Si BJT control, and 0.4 dB over the equivalent SiGe HBT with the traditional proﬁle. Base doping has a direct impact on β, intrinsic base resistance Rbi and fT , with all values decreasing as doping increases. The decrease in β and fT (with increases in both base and emitter transit time) would give the impression that NFmin will increase. However, the decrease in the base resistance suggests there may be a decrease in NFmin . Figure 5.38 shows the eﬀect of increasing base doping on the major components of noise factor, as a function of collector current, for a 90 nm base HBT with the calibrated Ge proﬁle of ﬁgure 5.37. An additional extrinsic base sheet resistance of 500 ohms/square has been included in the calculation. It is apparent that an increase in base doping increases NFmin because β decreases and τb increases. Even though an increase in doping reduces Rb , Ropt also decreases which partially oﬀsets the impact of reduction in base thermal noise. 5.8.

RADIATION EFFECTS ON SIGE HBTS

In the following, we describe brieﬂy the eﬀects of proton and gamma radiation on SiGe HBTs fabricated in IBM SiGe BiCMOS technology.

Radiation eﬀects on SiGe HBTs

187

Figure 5.37. Ge proﬁle which allows optimization for NFmin compared to the conventional graded Ge proﬁle. Emitter and base carrier concentrations are shown for reference from polySi interface in emitter to base–collector junction (at right edge). (After Ansley W E et al 1998 IEEE Trans. Microw. Theory Tech. 46 653–60.)

Figure 5.38. Eﬀect of base doping level on the noise factor sources for the scaled base proﬁle using a base link sheet resistance of 500 ohms/square. (After Ansley W E et al 1998 IEEE Trans. Microw. Theory Tech. 46 653–60.)

188

Simulation of SiGe HBTs

Dose-rate eﬀects and proton energy eﬀects have been studied in detail for this technology, mainly by Cressler and his group [45–47]. Characteristics of proton and gamma irradiated SiGe HBTs and gated lateral pnp transistors (GLPNPs) have been reported [48]. MOS devices respond to ionizing radiation in several ways, depending on whether the damage occurs in silicon or in the oxide. In the oxide, charge-generation in the gate/oxide interface or the oxide/silicon interface causes changes in the threshold voltage (VT ), transconductance (gm ), and the leakage current. Two kinds of charges are observed: oxide trapped charge and interface trapped charge, each having diﬀerent eﬀects on device parameters. The major eﬀects of radiation-induced interface states on MOS devices are lowering of transconductance and distortion of I–V characteristics. The generation of electron–hole pairs after a radiation burst is not a long-lived phenomenon because the electrons tunnel into the bulk of the device and the trapped hole charge can lead to signiﬁcant device degradation. For most bipolar devices, the eﬀects of radiation and subsequent performance degradation due to surface states are not as catastrophic as for MOSFETs. Bipolar transistors are, in general, more radiation tolerant than CMOS as they depend on junctions for operation, while MOSFETs depend on surface eﬀects and the interfaces. Also, bipolar transistors are doped up to three orders of magnitude higher than MOSFETs. When irradiated, degradation of current gain and an increase in leakage current are found to occur in the case of bipolar devices. Gain degradation occurs mainly due to the atomic displacement in the bulk of the device. The displacement results in an increase in the number of recombination centres, which reduces the minority-carrier lifetime, and therefore an increase in the base current takes place. The other cause of gain degradation is due to the ionization of the oxide passivation layer, mainly in the emitter–base junction region where charge trapping and the generation of new interface traps occur. The trapped surface charge and the interface states cause an increase in minority-carrier surface recombination velocity, which reduces the gain. Another important eﬀect in bipolar transistors is the increase in the junction leakage currents resulting from ionization in the surface oxide, mainly the region over the base–collector junction. This increase in base– collector leakage current (typically ∼1 nA) is usually due to charge build-up in the oxide layer over the junction producing a surface channel which conducts strongly. Figure 5.39 shows a schematic device cross section of a SiGe HBT and sources of degradation. The SiGe HBT has been successfully integrated with conventional Si CMOS technology to realize a SiGe BiCMOS technology. This technology is more fully discussed in chapter 10.

Radiation eﬀects on SiGe HBTs

189

Figure 5.39. Schematic cross section of a self-aligned UHVCVD SiGe HBT. Sources of degradation are shown in the structure. (After Banerjee G 1999 Master’s Thesis Auburn University.)

5.8.1.

Low dose-rate eﬀects

Low dose-rate (LDR) eﬀects have been investigated in the state-of-the-art SiGe HBTs (see ﬁgure 5.39) which were fabricated using a self-aligned, planar structure with deep and shallow trench isolation and a conventional poly-emitter contact. These SiGe HBTs have 70 GHz fmax frequency response and have been fully integrated into a 0.35 µm SiGe BiCMOS technology for system-on-a-chip applications [49]. The LDR eﬀects on these vertical SiGe HBTs were contrasted with high dose-rate (HDR) data, as well as data from gated lateral pnp transistors from this SiGe BiCMOS process, in order to shed light on the damage mechanisms. In contrast to reports of strongly enhanced LDR degradation in conventional Si bipolar transistors, LDR eﬀects in the SiGe HBTs were found to be nearly non-existent [50]. Figure 5.40 shows the dependence of dc current gain on the energy of protons. A peak β of about 105 is observed which degrades to 100 for 44 MeV and 95 for 196 MeV. Clearly, the β degradation is much larger for the higher energy. It has been observed that an increase in the base current occurs when collector current is more or less independent of radiation. However, the degradation in current gain is not as large in the high current region of the transistor, where it will be biased for most of the high-frequency and high-power RF applications. The LDR eﬀects have been found to be very technologydependent.

190

Simulation of SiGe HBTs

Figure 5.40. Current gain degradation as a function of energy. Banerjee G 1999 Master’s Thesis Auburn University.)

5.8.2.

(After

Simulation of radiation hardness

The eﬀects of proton radiation in a gate-assisted lateral pnp (GLPNP) in an advanced SiGe BiCMOS technology have been studied by Niu et al [48]. The GLPNP is essentially a p-MOSFET whose source and drain serve as the emitter and collector of the lateral bipolar transistor. These transistors avoid the current gain limitation by combining both MOSFET and bipolar operational modes, and thus are commonly used in BiCMOS circuits [51]. Radiation-induced surface and bulk traps were electrically probed using a combination of dc measurements and 2D simulation. Figure 5.41 shows the schematic top view and cross section of a GLPNP, along with the SiGe HBT in the BiCMOS process studied. To understand the physics underlying radiation degradation, extensive 2D simulations using MEDICI [52] were performed by the authors, by placing positive charges in the oxide and introducing a thin surface layer of traps. The simulations show that the radiation-induced threshold voltage increases and the carrier lifetime at the surface decreases. Diﬀerent combinations of trap density and spatial distributions of traps were used, and only those with higher surface trap densities can reproduce the experimentally observed data. Figure 5.42 shows the evolution of the simulated electron and hole densities versus depth with VGB change at Vbe = 0.45 V.

Radiation eﬀects on SiGe HBTs

191

Figure 5.41. Device cross section for the gated lateral pnp transistor and SiGe HBT. (After Niu G et al 1998 IEEE Trans. Nucl. Sci. 45 2361–5.)

Figure 5.42. Simulated electron (solid curve) and hole (dashed curve) densities versus depth with VGB (gate-to-base bias) change at Vbe = 0.45 V. (After Niu G et al 1998 IEEE Trans. Nucl. Sci. 45 2361–5.

192 5.9.

Simulation of SiGe HBTs SUMMARY

In this chapter, further examples of device simulation employing SiGe HBT technology have been considered. Attention has been given to simulation of various advanced technologies leading to high cut-oﬀ frequency and/or low transit time. Good agreement between simulation and measurement provides conﬁdence in the use of device simulation for future development. Simulation of the low-temperature operation of a SiGe HBT has been shown to be applicable for a wide range of applications in low-temperature electronics. Other more specialist applications of SiGe technology in I2 L circuits and radiation hard environment have been considered. BIBLIOGRAPHY [1] Meister T F, Schafer H, Franosch M, Molzer W, Auﬁnger K, Scheler U, Walz C, Stolz M, Boguth S and Bock J 1995 SiGe base bipolar technology with 74 GHz fmax and 11 ps gate delay IEEE IEDM Tech. Dig. pp 739–42 [2] Kondo M, Oda K, Ohue E, Shimamoto H, Tanabe M, Onai T and Washio K 1998 Ultra-low-power and high-speed SiGe base bipolar transistors for wireless telecommunication systems IEEE Trans. Electron Devices 45 1287–94 [3] Armstrong G A and French W D 1995 A model for dependence of maximum oscillation frequency on collector to substrate capacitance in bipolar transistors Solid-State Electron. 38 1505–10 [4] Jomaah J, Ghibaudo G and Balestra F 1995 Analysis and modelling of self-heating in thin ﬁlm SOI MOSFETS as a function of temperature Solid-State Electron. 38 615–8 [5] Dallmann D and Shenai K 1995 Scaling constraints imposed by self-heating in SOI MOSFETs IEEE Trans. Electron Devices 42 489–96 [6] Crabbe E F, Patton G L, Stork J M C, Comfort J H, Meyerson B S and Sun J Y-C 1990 Low-temperature operation of Si and SiGe bipolar transistors IEEE IEDM Tech. Dig. pp 17–20 [7] Cressler J D, Crabbe E F, Comfort J H, Sun J Y-C and Stork J M C 1994 An epitaxial emitter-cap SiGe-base bipolar technology optimized for liquidnitrogen temperature operation IEEE Electron Device Lett. 15 472–4 [8] Joseph A J, Cressler J D and Richey D M 1995 Operation of SiGe heterojunction bipolar transistors in the liquid-helium temperature regime IEEE Electron Device Lett. 16 268–70 [9] Cressler J D, Comfort J H, Crabbe E F, Patton G L, Stork J M C, Sun J Y-C and Meyerson B S 1993 On the proﬁle design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications— part I: Transistor dc design considerations IEEE Trans. Electron Devices 40 525–41 [10] Cressler J D, Comfort J H, Crabbe E F, Patton G L, Stork J M C, Sun J Y-C and Meyerson B S 1993 On the proﬁle design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications—part II: circuit performance issues IEEE Trans. Electron Devices 40 542–56

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[11] Joseph A J, Cressler J D, Richey D M, Jaeger R C and Harame D L 1997 neutral base recombination and its inﬂuence on the temperature dependence of Early voltage and current gain–Early voltage product in UHV/CVD SiGe heterojunction bipolar transistors IEEE Trans. Electron Devices 44 404–13 [12] Gruhle A, Kibbel H, Konig U, Erben U and Kasper E 1992 MBE-grown Si/SiGe HBTs with high β, fT and fmax IEEE Electron Device Lett. 13 206–8 [13] Mazhari B and Morkoc H 1995 Intrinsic gate delay of Si/SiGe integrated injection logic circuits Solid-State Electron. 38 189–96 [14] Karlsteen M and Willander M 1995 Improved switch time of I2 L at low power consumption by using an SiGe heterojunction bipolar transistor Solid-State Electron. 38 1401–7 [15] Berger H H and Helwig K 1979 An investigation of the intrinsic delay (speed limit) in MTL/I2 L IEEE J. Solid-State Circuits 14 327–37 [16] Wainwright S P, Hall S, Ashburn P and Lamb A C 1998 Analysis of Si:Ge heterojunction integrated injection logic (I2 L) structures using a stored charge model IEEE Trans. Electron Devices 45 2437–47 [17] Tang Y T 2000 Advanced characteristics and modelling of SiGe HBTs PhD Thesis University of Southampton [18] Hamel J S and Tang Y T 2000 Numerical simulation and comparison of vertical and lateral SiGe HBTs for RF/microwave applications Proc. ESSDERC 2000 (Cork, Ireland, 12–14 September 2000) [19] Apanovich Y, Lyumkis E, Polsky B, Shur A and Blakey P 1994 Steadystate and transient analysis of submicron devices using energy balance and simpliﬁed hydrodynamic models IEEE Trans. Comput.-Aided Des. 13 702–7 [20] Oda K, Ohue E, Tanabe M, Shimamoto H, Onai T and Washio K 1997 130 GHz fT SiGe HBT technology IEEE IEDM Tech. Dig. pp 791–4 [21] Brodsky J S, Fox R M and Zweidinger D T 1999 A physics-based dynamic thermal impedance model for vertical bipolar transistors on SOI substrates IEEE Trans. Electron Devices 46 2333–9 [22] Armstrong G A and Gamble H S 1999 Simulation of self-heating eﬀects in heterojunction bipolar transistors fabricated in wafer bonded SOI substrates Silicon-on-Insulator Technology and Devices IX, Electrochemical Society Proceedings Series vol 99-3, ed P L Hemment (Pennington, NJ: Electrochemical Society) pp 249–54 [23] Selberherr S 1984 Analysis and Simulation of Semiconductor Devices (Vienna: Springer-Verlag) [24] Schiz J 1999 The eﬀect of ﬂuorine in low thermal budget polysilicon emitters for SiGe heterojunction bipolar transistors PhD Thesis University of Southampton [25] Maiti C K and Armstrong G A 1998 Ge proﬁle on dc current gain of Si1−x Gex HBTs at low temperature Proc. Int. Conf. on Computers and Devices for Communication (CODEC-98) pp 264–7 [26] Selberherr S 1989 MOS device modelling at 77 K IEEE Trans. Electron Devices 36 1464–74 [27] Chrzanowska-Jeske M and Jaeger R C 1989 BILOW-simulation of low-

194

[28] [29]

[30]

[31] [32]

[33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43]

Simulation of SiGe HBTs temperature bipolar device behaviour IEEE Trans. Electron Devices 36 1475–88 Patton G L, Harame B L, Stork J M C, Meyerson B S, Scilla G J and Ganin E 1989 Graded SiGe-base, poly-emitter heterojunction bipolar transistors IEEE Electron Device Lett. 10 534–6 Cressler J D, Comfort J H, Crabbe E F, Patton G L, Lee W, Sun J Y-C, Stork J M C and Meyerson B S 1991 Sub-30 ps ECL circuit operation at liquid-nitrogen temperature using self-aligned epitaxial SiGe-base bipolar transistors IEEE Electron Device Lett. 12 166–8 Comfort J H, Patton G L, Cressler J D, Lee W, Crabbe E F, Meyerson B S, Sun J Y-C, Stork J M C, Lu P-F, Burghartz J N, Warnock J, Scilla G, Toh K-Y, D’Agostino M, Stanis C and Jenkins K 1990 Proﬁle leverage in self-aligned epitaxial Si or SiGe base bipolar technology IEEE IEDM Tech. Dig. pp 21–24 Yuan J S 1992 Modelling Si/Si1−x Gex heterojunction bipolar transistors Solid-State Electron. 35 921–6 Sturm J C, Prinz E J and Magee C W 1991 Graded-base Si/Si1−x Gex /Si heterojunction bipolar transistors grown by rapid thermal chemical vapour deposition with near-ideal electrical characteristics IEEE Electron Device Lett. 12 303–5 Jain S C 1994 Germanium–Silicon Strained Layers and Heterostructures (New York: Academic) Richey D M, Cressler J D and Joseph A J 1997 Scaling issues and Ge proﬁle optimization in advanced UHV/CVD SiGe HBTs IEEE Trans. Electron Devices 44 431–40 Matthews J W and Blakeslee A E 1974 Defects in epitaxial multilayers—I. Misﬁt dislocations in layers J. Cryst. Growth 27 118–25 Matthews J W and Blakeslee A E 1975 Defects in epitaxial multilayers—II. Dislocation pile-ups, threading dislocations, slip lines and cracks J. Cryst. Growth 29 273–80 Wainwright S P, Hall S and Ashburn P 1996 Analysis of SiGe heterojunction injection logic structures using a stored charge model Proc. ESSDERC’96 pp 649–52 Van der Ziel A 1986 Noise in Solid-State Devices and Circuits (New York: Wiley) Hughes B, Fernandez N G and Gladstone J M 1987 GaAs FETs with a ﬂicker-noise corner below 1 MHz IEEE Trans. Electron Devices 34 733– 74 Vempati L S, Cressler J D, Babcock J A, Jaeger R C and Harame D 1996 Low-frequency noise in UHV/CVD epitaxial Si and SiGe bipolar transistors IEEE J. Solid-State Circuits 31 1458–67 Cressler J D, Vempati L, Babcock J A, Jaeger R C and Harame D L 1996 Low-frequency noise characteristics of UHV/CVD epitaxial Si- and SiGebase bipolar transistors IEEE Electron Device Lett. 17 13–15 Vempati L S, Cressler J D, Babcock J A, Jaeger R C and Harame D 1995 Low-frequency noise in UHV/CVD Si- and SiGe-base bipolar transistors IEEE BCTM Proc. pp 129–32 Ansley W E, Cressler J D and Richey D M 1998 Base-proﬁle optimization for

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[52]

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minimum noise ﬁgure in advanced UHV/CVD SiGe HBTs IEEE Trans. Microw. Theory Tech. 46 653–60 Hawkins R J 1977 Limitations of Nielsen’s and related noise equations applied to microwave bipolar transistors, and a new expression for the frequency and current dependent noise ﬁgure Solid-State Electron. 20 191–6 Roldan J M, Niu G, Ansley W E, Cressler J D, Clark S D and Ahlgren D C 1998 An investigation of the spatial location of proton-induced traps in SiGe HBTs IEEE Trans. Nucl. Sci. 45 2424–9 Roldan J M, Ansley W E, Cressler J D, Clark S D and Nguyen-Ngoc D 1997 Neutron radiation tolerance of advanced UHV/CVD SiGe HBT BiCMOS technology IEEE Trans. Nucl. Sci. 44 1965–73 Babcock J A, Cressler J D, Vempati L S, Clark S D, Jaeger R C and Harame D L 1995 Ionizing radiation tolerance of high-performance SiGe HBTs grown by UHV/CVD IEEE Trans. Nucl. Sci. 42 1558–66 Niu G, Banerjee G, Cressler J D, Roldan J M, Clark S D and Ahlgren D C 1998 Electrical probing of surface and bulk traps in proton-irradiated gate-assisted lateral pnp transistors IEEE Trans. Nucl. Sci. 45 2361–5 Subbanna S, Ahlgren D, Harame D and Meyerson B 1999 How SiGe evolved into a manufacturable semiconductor production process IEEE ISSCC Tech. Dig. pp 66–67 Banerjee G 1999 Ionizing radiation eﬀects in silicon–germanium BiCMOS technology Master’s Thesis Auburn University Sunderland D A, Jeng S J, Nguyen-Ngoc D, Martin Jr B, Eld E C, Tewksbury T, Ahlgren D C, Gilbert M M, Malinowski J C, Schonenberg K T, Stein K J, Meyerson B S and Harame D L 1996 Gateassisted lateral pnp active load for analog SiGe-HBT technology IEEE BCTM Proc. pp 23–26 Technology Modelling Associates 1997 MEDICI, 2D Semiconductor Device Simulator, Version 4.0

Chapter 6 STRAINED-SI HETEROSTRUCTURE FETS

In conventional Si technology, the complementary metal–oxide semiconductor dominates the integrated circuit market. Its popularity comes from the simplicity in processing, as well as high input impedance. However, p-channel devices are inferior to n-channel ones in terms of current drive capability and speed performance. This is a consequence of the lower mobility of holes compared to electrons in Si. In order to match the current drive capability of n-channel (n-MOS), p-channel (p-MOS) devices are designed to be about 2–3 times larger than that of n-MOS. This adversely aﬀects the level of integration and device speed. In order to improve the speed of VLSI/ULSI circuits, new materials and device structures are being proposed. The advances in the growth of strained silicon (strained-Si) layers on relaxed-SiGe buﬀer layers, combined with higher values of both the hole and electron mobilities in strained-Si, have led to increased interest in silicon-based heterojunction ﬁeld-eﬀect transistors (HFETs) using conventional Si-processing technology. Heteroepitaxy of semiconductor materials has been an active area of research for the last two decades. Interest is driven by the possibility of creating novel electronic and optical devices, as well as integrating existing devices in diﬀerent material systems, leading to the production of integrated circuits with increased functionality and lower cost. The foundation of heteroepitaxy was laid by two important contributions. The ﬁrst, by Frank and van der Merwe in 1949 [1], showed theoretically that if a lattice mismatched layer is grown on a thick substrate, the layer will be pseudomorphic, provided that the mismatch is small and thickness of the layer is not large. The second by Shockley [2] suggested the use of semiconductors of diﬀerent bandgaps for fabrication of heterostructure devices. The lattice mismatch in the SiGe material system is 4.2%, resulting in a very high misﬁt and threading dislocation density. Most of the research 196

Strained-Si heterostructure FETs

197

Figure 6.1. Band alignments between Si and Si0.70 Ge0.30 on two substrates: (a) Si and (b) Si0.70 Ge0.30 .

has concentrated on devices having strained layers with thicknesses below the critical thickness. Si1−x Gex strained layer heterostructure devices were fabricated on an Si substrate only in the late 1980s. The key features of the growth and electronic properties of the strained-SiGe alloy system and their applications have been described in chapter 2 of this book, and also in more detail in several excellent reviews [3–7]. When a thin ﬁlm with a larger lattice constant (e.g., Si1−x Gex ) is grown on a substrate with a smaller lattice constant (e.g. silicon), the ﬁlm maintains the in-plane lattice constant of the substrate and is under a biaxially compressive strain. Figure 6.1 shows the band oﬀset between a strained-Si0.7 Ge0.3 ﬁlm grown on silicon. This is known as the type I band alignment where virtually all the entire band oﬀset occurs in the valence band (ﬁgure 6.1(a)) with minimal band oﬀset in the conduction band. This type of structure, favourable for hole conﬁnement, has been exploited in several novel heterostructure devices, namely buried channel p-MOSFETs, p-MODFETs and HBTs (see, for example, excellent reviews by Paul [8] and Konig and Daembkes [9]). Similarly, a smaller lattice constant silicon epilayer will be under biaxial tension when grown on a larger lattice constant relaxed-Si1−x Gex substrate. Figure 6.1(b) shows the band oﬀset for a strained-Si epilayer grown on a relaxed Si0.70 Ge0.30 . In this case, type II band oﬀset occurs and the structure has several advantages over the more common type I band alignment, as a large band oﬀset is obtained in both the conduction and valence bands, relative to the relaxed-Si1−x Gex layer [10]. This allows both electron and hole conﬁnements, making it useful for both n- and p-type devices for strained-Si/SiGe based CMOS technology. Since strained-Si provides both larger conduction and valence band oﬀsets and does not suﬀer from alloy scattering (mobility degradation) [11], a signiﬁcant improvement in carrier mobility can be achieved. Strained-Si is more diﬃcult to grow as compared to strained-Si1−x Gex , since an Si1−x Gex substrate is currently not available and, until recently, the growth of relaxed-Si1−x Gex without forming a large concentration of defects due to dislocation was diﬃcult.

198

Strained-Si heterostructure FETs

Studies of the incorporation of a small amount of C atoms into the Si/SiGe material system to develop new types of buﬀer layers with reduced misﬁt dislocations may be useful [12]. However, the ability to achieve both n-MOS and p-MOS devices using strained-Si provides a promising alternative for next generation highperformance SiGe CMOS technology (see, for example, reviews [5, 13] and references therein). Strained-SiGe channel p-MOSFET designs are more fully covered in chapter 7. In this chapter, we discuss the present trends and applications of strained-Si ﬁlms in SiGe-based CMOS technology. Indepth discussion will cover the ﬁlm growth, electronic properties of the strained-Si layers on virtual substrates, design and simulation of strainedSi channel HFETs and MODFETs. Recent progress made in integration issues and the future prospects of strained-Si/SiGe-based high-performance HFETs, which may be integrated into Si VLSI/ULSI production, are also discussed. 6.1.

MOBILITY IN STRAINED-SI

Optimum semiconductor device design is ultimately based upon a full understanding and accurate modelling of charge-carrier transport in semiconductors. Due to their relevance for both basic understanding and for device applications, there has always been a strong interest in accurate model descriptions of the mobility as a function of strain, temperature and dopant concentration. For the estimation of maximum theoretical mobilities that can be achieved in strained-Si/SiGe heterostructures, several theoretical studies incorporating various scattering mechanisms have been reported [14–16]. The main scattering mechanisms to be considered in the strained-Si/SiGe material system are [17]: (i) (ii) (iii) (iv)

lattice scattering; ionized impurity scattering; neutral impurity scattering; and alloy scattering.

In addition, the strain distribution in the lattice mismatched SiGe layer aﬀects the relative importance of intra- and inter-valley scattering, due to strain-induced changes in the conduction and valence bands. 6.1.1.

Theoretical mobility

Stern and Laux [14] considered the dependence of electron mobility on remote doping and background doping in the channel, as well as the contribution of interface roughness and interface charges. Their results are in good agreement with the experimental data when realistic background acceptor densities between 1014 and 1015 cm−3 were

Mobility in strained-Si

199

considered [18–20]. Monroe et al [21] have studied the limitations of various parameters including scattering from remote dopants, background impurities, interface roughness, alloy ﬂuctuations, strain, morphology and threading dislocations on the mobility. Considering all potential scattering mechanisms which are reasonable, the authors predicted a low-temperature electron mobility over 1 000 000 cm2 V−1 s−1 , which is comparable to those reached in GaAs/AlGaAs heterostructures. Several other workers have calculated the expected electron mobility enhancements in strained-Si layers relative to bulk-Si [22–24, 26, 27]. Vogelsang and Hofmann [23] have calculated the in-plane electron drift velocities and mobilities in strained-Si for 300 and 77 K. High-ﬁeld drift velocities were calculated by Monte Carlo (MC) simulations and low-ﬁeld mobilities by the numerical solution of Boltzmann’s equation including intra- and inter-valley phonon and impurity scattering mechanisms. A mobility enhancement of 74% was obtained at 300 K, compared to 36% at 77 K, and a signiﬁcant improvement of the drift velocity relative to bulk-Si was reported. Yamada et al [27] have reported a Monte Carlo study of the low-temperature mobility of electrons. For a device structure having 2×1018 cm−3 doping, mobility values of 2.5×105 cm2 V−1 s−1 at 4.2 K and 3.1 × 105 cm2 V−1 s−1 at 1.5 K for an electron density of 7.5 × 1011 cm−2 were obtained. Peak mobility values of 5.0 × 105 cm2 V−1 s−1 at 4.2 K and 7.6 × 105 cm2 V−1 s−1 at 1.5 K were predicted for a lower channel electron density. Rashed et al [22] have studied electron transport in the inversion layer of strained-Si channel n-MOSFETs using an MC tool, taking into account scattering mechanisms, namely phonon, surface roughness and alloy scattering. Table 6.1 shows the computed low-ﬁeld electron mobility enhancement factors for strained-Si, along with some reported experimental device data. For a low level of strain at low electric ﬁeld, the electron mobility increases with increasing strain. High-ﬁeld velocity saturation and overshoot of electrons in strainedSi [24] show only a slight increase in the saturation velocity at both room temperature and 77 K. As the electric ﬁeld parallel to the current ﬂow is increased, the drift velocity of the electron increases and approaches the saturation velocity. These high electric ﬁelds are common in short-channel devices, and thus the saturation velocity, rather than low-ﬁeld mobility, may ultimately limit the performance of scaled devices [23, 28]. Electron velocity overshoot in strained-Si/Si1−x Gex MOSFETs has also been studied using an MC simulator by Gamiz et al [29] for steadystate and non-steady-state for high longitudinal ﬁeld transport regimes. It was concluded that at high longitudinal ﬁelds, the electron velocity overshoot eﬀects, due mainly to the reduction of the inter-valley scattering rates as the Ge mole fraction increases, improve MOSFET drain current and transconductance.

200

Strained-Si heterostructure FETs

Table 6.1. Low-ﬁeld electron mobility: dependence on strain level in Si. Ge concentration in the buﬀer (%)

Strain in Si (%)

Temperature (K)

Computed mobility enhancement factor

10 20 30

0.4 0.8 1.33

300

1.6 1.8 1.9

[22]

2.5 5 10 15 20 25 2.5 5 10

0.1 0.2 0.4 0.6 0.8 1 0.1 0.2 0.4

300

1.14 1.27 1.5 1.65 1.73 1.74 1.28 1.36 1.36

[23]

16.6 33.3 16.6 33.3

0.66 1.33 0.66 1.33

300

2.67 2.67 1.35 1.35

[24]

77

77

Ref

Experimental mobility enhancement factor 10 20 29 29

0.4 0.8 1.3 1.3

300 77

1.45 1.67 1.75 1.35

[25]

However, the progress in the study of hole mobility in strained-Si has been relatively slow. Nayak and Chun [11] have calculated the low-ﬁeld hole mobility of strained-Si. At room temperature, in-plane hole mobilities were found to be 1103 and 2747 cm2 V−1 s−1 for Ge content of 10% and 20%, several times higher than that of bulk-Si. Table 6.2 shows the computed low-ﬁeld hole mobility for strained-Si, along with some reported experimental hole mobility enhancement factors obtained from device data. 6.1.2.

Experimental mobility

Low-temperature Hall mobility measurements are commonly determine the overall quality of a heterostructure and are optimize the growth parameters. At low temperature, where eﬀects and scattering by phonons are dramatically reduced, the

used to used to thermal electron

Mobility in strained-Si

201

Table 6.2. Low-ﬁeld hole mobility: dependence on strain level in Si. Ge concentration in the buﬀer (%)

Strain in Si (%)

10 15 20 25

0.4 0.6 0.8 1

Temperature (K) 300

Computed mobility cm2 V−1 s−1 1100 1950 2700 3500

Ref [11]

Experimental mobility enhancement factor 29

1.33

300

1.2

[30]

18 18

0.8 0.8

300 77

1.4 2.0

[31]

25

1.0

300

1.5

[32]

mobility becomes very sensitive to residual scattering mechanisms due to background charge impurities, roughness and dislocation. Experimental electron mobility data from strained-Si/SiGe modulationdoped structures may be divided into two categories: (i) data from devices with the uniform composition buﬀer, and (ii) devices with the compositionally graded buﬀer. Figure 6.2 shows the range of values for Hall mobility [18, 28, 33–38] using both uniform composition and graded buﬀer layers. In the case of the uniform composition buﬀer [33, 36, 38], strain relief is a function of buﬀer layer thickness. In order to achieve a strain level of 1% in Si, a partially relaxed 0.2 µm Si0.68 Ge0.32 uniform composition buﬀer is required [39]. For an eﬀective strain level of 1% in Si on a uniform composition buﬀer, record high electron mobilities of 1280 cm2 V−1 s−1 at 300 K [38] and 17 000 cm2 V−1 s−1 at 1.5 K [36] have been reported. In this type of buﬀer, mobility is limited by the presence of a large number of defects (109 –1010 cm−2 ) in the buﬀer layer. The eﬀect of dislocations on electron mobility has been reported by Ismail [40]. It has been found that electron mobility is sensitive to threading dislocations when their density exceeds 3×108 cm−2 , and decreases by two orders of magnitude when the threading dislocation density is 1 × 1011 cm−2 . The introduction of graded buﬀer layers has made a great impact on the electron mobility enhancement. The upper curve in ﬁgure 6.2 represents very high (around 200 000 cm2 V−1 s−1 ) low-temperature mobilities but underestimates the two-dimensional electron gas mobility

202

Strained-Si heterostructure FETs

Figure 6.2. Measured electron Hall mobility versus temperature in modulation-doped strained-Si. The solid symbols are for strained-Si grown on high-quality, graded Si1−x Gex buﬀer layers, while the open symbols refer to ﬁlms with constant Ge content. (After Maiti C K et al 1998 Semicond. Sci. Technol. 13 1225–46.)

at room temperature. This is due to parasitic parallel channels of low mobility and an unknown carrier concentration, which freeze out at a low temperature, but lead to a reduced average value of the Hall mobility at a higher temperature. By carefully designing the doping concentration in a series of samples, Nelson et al [41] could separate the contribution of the 2DEG at room temperature, and extracted room temperature mobility in excess of 2500 cm2 V−1 s−1 for the limiting case of a vanishing parasitic channel. The room temperature mobility enhancement factor is almost twice that of bulk-Si, and a factor of more than three greater than that of an Si-MOSFET. The extremely high electron mobility obtained in modulation-doped layered structures, grown using MBE and UHVCVD, indicates that a similar buﬀer layer quality has been obtained. By optimizing the modulation-doped layer sequence and thickness of strained-Si well [42], the highest mobility values between 300 000 and 400 000 cm2 V−1 s−1 have been

Band structure of strained-Si

203

obtained. Additional wave functioning by front and back gating of some of the structures led to a record low-temperature (0.4 K) electron channel mobility beyond 500 000 cm2 V−1 s−1 [43, 44], which is an improvement of more than a factor of ten compared to the best Si MOSFETs reported. Typical values of room temperature mobility, however, are between 2000 and 2800 cm2 V−1 s−1 for n-channels [28,45], which exceed those in bulk-Si MOSFETs by a factor of four to six. A high hole mobility in excess of 9300 cm2 V−1 s−1 at 4 K in a p-type modulation-doped Si/Si0.87 Ge0.13 /Si heterostructure has been reported by Whall [46]. At room temperature, values between 1400 and 1800 cm2 V−1 s−1 are more typical, still a factor of at least six to nine above that of a bulk-Si p-MOSFET [47].

6.2.

BAND STRUCTURE OF STRAINED-SI

The eﬀect of both strain and alloying on the bandgap of the strainedSi/SiGe material system has been reported in detail by People [10]. In particular, the computed conduction and valence band discontinuities have been based on the calculations of van de Walle and Martin [48]. The extracted valence and conduction band oﬀsets between the strained-Si and relaxed-Si1−x Gex layers [49] are plotted against theoretically estimated values in ﬁgure 6.3, showing a good match, particularly at low Ge concentration. Substituting the extracted conduction and valence band oﬀset values, the overall bandgap of the strained-Si can be obtained and is shown in ﬁgure 6.4, along with the theoretical calculations of People [10]. The heterojunction band oﬀsets (∆Ec , ∆Ev ) in a strained-Si/SiGe heterostructure have also been determined from measurement of the threshold voltages of a surface channel strained-Si p-MOSFET structure (see ﬁgure 6.5(a)) [50]. To determine the threshold voltage at the strainedSi/SiGe interface (VTH ) and the threshold voltage at the strained-Si/SiO2 √ interface (VTS ), the zero current intercept of the IDS –VGS and IDS / gm characteristics were used. The measured values of threshold voltages VTH and VTS were −1.0 V and −1.7 V, respectively [50, 51]. The extracted experimental valence band oﬀset ∆Ev was found to be 160 meV. Using the valence band oﬀset value, conduction band oﬀset was obtained from equations (2.11) and (2.12) where x is the Ge concentration in the top part of a completely relaxed-SiGe buﬀer cap. The conduction band oﬀset ∆Ec was found to be about 126 meV for a Ge mole fraction x = 0.18 in the relaxed-SiGe layer, and agreement with reported results was found to be good [10, 33].

204

Strained-Si heterostructure FETs

Figure 6.3. Band oﬀsets: (a) valence band and (b) conduction band for strained-Si to relaxed Si1−x Gex . Calculated curves are from People R 1986 IEEE J. Quantum Electron. 22 1696–710 and the data are from Braunstein et al 1958 Phys. Rev. 109 695–710.

6.3.

DEVICE APPLICATIONS

Silicon complementary metal–oxide semiconductor transistors are the most important building blocks in digital integrated circuits due to low power consumption and mature technology. The use of strained-Si/SiGe materials promises to improve the speed-power performance of CMOS by oﬀering higher electron and hole mobilities. Device applications of strained-Si/SiGe with special emphasis on heterostructure metal–oxide semiconductor ﬁeldeﬀect transistors are described in this section, while the alternative approach of a Schottky gate modulation-doped ﬁeld-eﬀect transistor is discussed in section 6.5.

Device applications

205

Figure 6.4. Bandgap of strained-Si grown on a relaxed-Si1−x Gex buﬀer layer. Calculated curves are from People R 1986 IEEE J. Quantum Electron. 22 1696–710 and the data are from Braunstein et al 1958 Phys. Rev. 109 695–710.

Figure 6.5. Device structures for strained-Si MOSFETs with (a) Si on the surface, (b) Si buried and (c) dual strained-Si channels.

206 6.3.1.

Strained-Si heterostructure FETs Strained-Si n-MOSFETs

Very high electron mobilities demonstrated in strained-Si layer suggest a great potential for this material in high transconductance n-MOSFETs. To date, in-plane electron mobilities approaching 3000 cm2 V−1 s−1 have been reported in long-channel MOSFETs with both surface and buried channels [52]. Figure 6.5 shows the schematic diagrams of several possible conﬁgurations of strained-Si MOSFETs. All the structures have thick, relaxed-Si1−x Gex buﬀer layers, consisting of a layer with linearlygraded Ge, followed by a constant Ge layer. The surface channel device (ﬁgure 6.5(a)) has a single layer of thin strained-Si grown on top of the relaxed buﬀer layer. This layer is oxidized to form a gate oxide. The buried strained-Si channel device (ﬁgure 6.5(b)) has a layer of strained-Si buried beneath a thin layer of relaxed Si1−x Gex . An additional layer of strained-Si is necessary to form a gate oxide on top of the Si1−x Gex , but ideally this additional Si layer (sacriﬁcial layer) should be consumed during oxidation. If this sacriﬁcial layer is not consumed fully, then a very thin layer of Si, left between the gate oxide and the Si1−x Gex barrier layer (ﬁgure 6.5c) can act as a parallel conducting channel, strongly aﬀecting device performance. Depending on the dopant type in the layers, these structures can be used for n- or p-MOSFETs. Welser et al [52, 53] have fabricated both p- and n-MOSFETs using all these device structures and some of their results on n-MOSFETs are presented below. Long-channel (L × W = 10 µm × 168 µm) surface and buried n-MOSFET devices fabricated on relaxed-Si0.7 Ge0.3 buﬀer layers have shown well-behaved output characteristics. The eﬀective low-ﬁeld mobilities for these device structures are shown in ﬁgure 6.6. For the surface-channel strained-Si device µeﬀ is enhanced compared to the bulk-Si control device and has a similar dependence on the eﬀective electric ﬁeld. The peak mobility is 1000 cm2 V−1 s−1 , which shows an 80% enhancement over Si-control (550 cm2 V−1 s−1 ). The peak mobility value for the buried channel device is over 1600 cm2 V−1 s−1 , which is almost three times that of Si-control device. Room temperature eﬀective mobility versus electric ﬁeld curves of surface-channel, strained-Si n-MOSFETs with diﬀerent Ge content in the buﬀer layer are shown in ﬁgure 6.7, along with the mobility extracted from a bulk-Si control device. Strained-Si mobility increases with increasing strain (more Ge content in the relaxed buﬀer layer) and has little dependence on the eﬀective electric ﬁeld. Rim et al [54] have reported measurements on deep submicron (0.1 µm) strained-Si n-MOSFETs. An electron mobility enhancement by 75%, compared to typical Si MOSFET mobilities, has been reported in spite of the high channel doping and vertical eﬀective ﬁeld present in the device. The ac measurements, used to reduce self-heating eﬀects, have shown an extrinsic transconductance increase by 45% for a channel length

Device applications

207

Figure 6.6. Eﬀective low-ﬁeld mobility versus eﬀective ﬁeld for diﬀerent n-MOSFETs. The surface channel strained-Si mobility shows a fairly constant mobility enhancement compared to that of the control-Si device, while the buried strained-Si mobility peaks at low ﬁelds, but decreases rapidly at higher ﬁelds. (After Welser J J 1994 The application of strained-silicon/relaxed-silicon germanium heterostructures to metal–oxide semiconductor ﬁeld-eﬀect transistors (Stanford University).)

Figure 6.7. Eﬀective mobility of surface-channel, strained-Si n-MOSFETs at room temperature. Strained-Si mobility increases with increasing strain (more Ge content in the relaxed buﬀer layer). (After Welser J J 1994 The application of strained-silicon/relaxed-silicon germanium heterostructures to metal–oxide-semiconductor ﬁeld-eﬀect transistors (Stanford University).)

208

Strained-Si heterostructure FETs

Figure 6.8. Eﬀective mobility, µeﬀ versus vertical eﬀective ﬁeld, Eeﬀ . For high Eeﬀ , µeﬀ is enhanced by 75% for strained-Si compared to the epi control-Si device and state-of-the-art universal MOSFET mobility. Data from Welser J et al 1994 IEEE IEDM Tech. Dig. pp 373–6, Takagi S et al 1994 IEEE Trans. Electron Devices 41 2357–62. (After Rim K et al 1998 IEEE IEDM Tech. Dig. pp 707–10.)

of 0.1 µm. In ﬁgure 6.8, the eﬀective mobility µeﬀ , measured on large devices, is shown as a function of vertical eﬀective ﬁeld Eeﬀ . Even for high Eeﬀ (>0.5 MV cm−1 ), the eﬀective mobility µeﬀ for the strained-Si device is enhanced by ∼75% compared to the epi control-Si. Electron mobility enhancements observed at lower Eeﬀ [25] are thus sustained at higher eﬀective ﬁelds, as predicted theoretically for the phonon-limited mobility in strained-Si MOS inversion layers [16]. The measured µeﬀ for strained-Si (peak µeﬀ ∼ 575 cm2 V−1 s−1 ) is also enhanced over the state-of-the-art n-MOSFET mobility [55]. These results demonstrate that, unlike conventional Si which is constrained to the universal MOSFET mobility curve (ﬁgure 6.8, dotted curve), strained-Si provides mobility improvement at a given Eeﬀ . Such an enhancement in µeﬀ at high channel doping and Eeﬀ enables fabrication of high mobility, deep submicron devices with channel doping suitable to counter short-channel eﬀects (SCE).

Device applications

209

6.3.2. Strained-Si p-MOSFETs Exploiting the demonstrated higher mobility for holes, eﬀorts have been made to fabricate strained-Si p-MOSFETs. Various research groups working on the problem were able to achieve better performance with strained-Si compared to control-Si devices. The tensile strain in silicon grown on a relaxed-SiGe buﬀer raises the light-hole band and lowers the heavy-hole band, leading to a signiﬁcant increase in the low-ﬁeld hole mobility. Observation of hole mobility enhancement in strained-Si pMOSFETs was demonstrated by Nayak et al [32]. The initial devices were fabricated on a 1 µm uniform composition partially relaxed-SiGe buﬀer, which is known to have a very high defect density [56] and this resulted in a limited performance (subthreshold slope 111 mV/decade). An improved device structure and process to fabricate high performance strained-Si p-MOSFETs has been reported, with a highquality (defect density <105 cm−2 ) step-graded completely-relaxed thick (3 µm) SiGe buﬀer layer, a low thermal budget (maximum temperature 700 ◦ C) and a high-quality (100 ˚ A) gate oxide [31,50]. The device structure used is shown in ﬁgure 6.9(a). It was shown that the high-ﬁeld channel mobilities of a device, with a germanium concentration of 0.18 in the SiGe buﬀer, were 40% and 200% higher at 300 K and 77 K respectively, compared to those of a similarly processed bulk-Si p-MOSFET. Rim et al [30] have also reported enhanced hole mobility in a surface-channel p-MOSFET (see ﬁgure 6.9(b)) employing strained-Si on pseudomorphic Si1−y Gey on a fully relaxed-Si1−x Gex buﬀer layer. Figure 6.10 shows the variation of low VDS (−0.1 and −0.3 V) transconductance of strained-Si and control-Si p-MOSFETs at 300 K, for the device structure shown in ﬁgure 6.9(a). The gate voltage at which peak transconductance occurs depends on the value of VDS and the device type, namely control-Si or strained-Si. The control-Si device shows one large peak at −1.7 V. But, for the strained-Si devices, two peaks are perceptible at −1.5 V and −1.9 V at 300 K. The peak at −1.5 V corresponds to hole conﬁnement at strained-Si/SiGe–buﬀer interface. At a higher gate voltage, however, the holes at the SiO2 /strained-Si interface dominate the channel conduction and the device becomes a surface channel device. The transition from buried channel to surface channel is clearly seen from the transconductance plot at 77 K (ﬁgure 6.11). The two peaks (−1.55 V and −2.7 V) are clearly seen. The IDS –VGS characteristics at 77 K for both the strained-Si and control-Si devices are also shown in this ﬁgure 6.11. It will be noticed that there is substantial current at VGS close to zero, particularly for the control-Si device. For the strained-Si device the characteristics indicate an accumulation current threshold of about −1 V. When the temperature is reduced to 77 K, the mobility improves in both silicon and strained-Si, the factor of improvement depending on the scattering mechanisms operating at the applied gate voltage.

210

Strained-Si heterostructure FETs

Figure 6.9. Schematic diagram of a strained-Si p-MOSFET: (a) strained-Si grown on a fully relaxed-SiGe buﬀer layer (abrupt) and (b) strained-Si grown on a grade-back Si1−y Gey layer (graded).

Device applications

211

Figure 6.10. Linear transconductance of a long channel (L×W = 100×300 µm) strained-Si (on an 18% Ge buﬀer layer) and control-Si p-MOSFETs at 300 K. (After Maiti C K et al 1997 Solid-State Electron. 41 1863–9.)

Figure 6.11. Linear transconductance of a long channel (L×W = 100×300 µm) strained-Si and control-Si p-MOSFETs at 77 K. Drain currents for the devices are also shown (right scale). (After Maiti C K et al 1997 Solid-State Electron. 41 1863–9.)

212

Strained-Si heterostructure FETs

The transverse ﬁeld dependence of MOS device parameters has assumed a greater importance because the thinner gate dielectrics and higher doping levels used in submicron MOSFETs lead to very high transverse electric ﬁelds well above 0.5 MV cm−1 . It is well known that such high ﬁelds cause a degradation in device performance. The variation of the eﬀective mobility with electric ﬁeld is often used as a basis of comparison of MOS devices developed for computer-aided design. The transconductance factor, ﬁeld-eﬀect mobility and eﬀective mobility computed from IDS – VGS characteristics at room and liquid nitrogen temperature have been compared for strained-Si and control-Si accumulation p-MOSFET devices [50]. Figure 6.12 shows the variation of computed ﬁeld-eﬀect mobility and eﬀective mobility for strained-Si and control-Si at 77 K. The eﬀective ﬁeld values assume a ﬂat band voltage of −1 V. The presence of the surface and parasitic channels at the strained-Si/SiO2 and SiGe/Si interfaces is

Figure 6.12. Comparison of the ﬁeld-eﬀect and eﬀective hole mobility of long channel strained-Si and control-Si p-MOSFETs at 77 K: (a) µfe of strained-Si; (b) µfe of control-Si; (c) µeﬀ of strained-Si; and (d) µeﬀ of control-Si. The eﬀective electric ﬁeld values applicable at 77 K for a current threshold value of −1.0 V are also indicated. (After Maiti C K et al 1997 Solid-State Electron. 41 1863–9.)

Simulation of strained-Si HFETs

213

indicated by the transconductance (see ﬁgure 6.11). Above VGS = −2.5 V, the strained-Si device shows an improvement in both. 6.4.

SIMULATION OF STRAINED-SI HFETS

Abramo et al [57] have presented a study of a novel Si/SiGe n-MOSFET structure simulated by means of a one-dimensional quantum mechanical approach which accounts for the quantum nature of two-dimensional electron gas. In simulation, energy splitting between degenerate conduction band valleys of strained-Si layer, optical and elastic acoustic phonon scattering among subbands, and surface roughness scattering were implemented. The non-parabolicity eﬀect on the scattering rates and velocities was included by ﬁrst-order perturbation theory following [58]. Room temperature low-ﬁeld peak electron mobility values greater than 2800 cm2 V−1 s−1 were predicted. The authors also showed good turnon characteristics and linear transconductance behaviour for the structure considered. Although two research groups have demonstrated high-performance strained-Si channel n- and p-MOSFETs [30, 31, 50, 52], until recently very little information on the design issues was available in the literature. Careful design considerations are necessary for gate oxide, strained-Si and graded SiGe layer thicknesses, Ge content and proﬁle, and substrate doping required to control the threshold voltage to optimize the device performance. A simulation study of strained-Si short-channel p-MOSFETs has been presented by Armstrong and Maiti [59, 60] and veriﬁed by comparison with experimental device measurements. Analytical models for both electron and hole mobilities in strained-Si and SiGe were incorporated into the ATLAS device simulator to evaluate the strain dependence of transconductance on temperature. In the case of a p-MOSFET, the use of a graded SiGe buﬀer layer reduced the valence band discontinuity at the strained-Si/SiGe interface and decreased the hole concentration in the buried parasitic SiGe channel to give an overall increase in transconductance. The basic device structures considered for simulation are similar to those shown in ﬁgure 6.9 and the device data used in simulation are given in table 6.3. A 0.8 µm strained-Si channel p-MOSFET (ﬁgure 6.9(a), abrupt case) on an Si1−x Gex buﬀer cap (0.9 µm) grown on top of a stepgraded 2.1 µm relaxed-SiGe buﬀer layer, having a 100 ˚ A gate oxide and a 135 ˚ A thick strained-Si layer was considered. However, in this structure, a parasitic buried channel is formed at the strained-Si/SiGe interface and leads to device performance degradation due to lower hole mobility in the relaxed-SiGe channel. In the other device structure considered (ﬁgure 6.9(b), graded case), a thin (300–400 ˚ A) graded strained-Si1−y Gey buﬀer cap (grade-back layer) was sandwiched between the strained-Si layer

214

Strained-Si heterostructure FETs

Table 6.3. Strained-Si channel p-MOSFET device data used in simulation. Device type

Abrupt structure

Graded structure

Strained-Si channel (˚ A) Gate length (µm) Oxide thickness (˚ A) Ge concentration (x) Buﬀer cap (µm) Grade-back layer (˚ A) Relaxed-SiGe layer (µm)

100 0.8 100 0.1–0.3 0.9 – 2.1

150–220 0.8 135 0.04 – 300–400 0.7

(150 ˚ A) and relaxed-Si1−x Gex layer (0.7 µm) to avoid the problem of hole conﬁnement at the strained-Si/SiGe interface, as the valence band discontinuity is reduced because of Ge grading. For simulation, a channel length of 0.8 µm and a 130 ˚ A gate oxide thickness were considered. To account for the enhanced mobility both in strained-Si and SiGe layers, the low-ﬁeld hole mobility for Si1−x Gex was modelled following [61]. The doping concentration and temperature-dependent mobility due to Arora [62] was modiﬁed by using an analytic expression involving Ge content, x, as µ(x, T, N ) = µArora (T, N ) 1 + 4.31x − 2.28x2 (6.1) and µArora is given by µArora (T, N ) = µ1p

T 300

αp

+

β

µ2p (T /300) p γ 1 + N/Ncp (T /300) p

(6.2)

where µ1p = 54.3 cm2 V−1 s−1 , µ2p = 407.0 cm2 V−1 s−1 , αp = −0.57, βp = −2.23, γp = 2.546 and Ncp = 2.67 × 1017 cm−3 . Mobility due to alloy scattering is given by [61] −1

[µalloy ] for x ≤ 0.2 and

= x(1 − x) exp(−7.68x)/124.1 −1

[µalloy ]

= exp(−2.58x)/2150

(6.3) (6.4)

for 0.2 < x < 0.6. The modiﬁed Arora mobility and the mobility due to alloy scattering were combined using Mathiessen’s rule and implemented for SiGe regions in the ATLAS simulator. As the low-ﬁeld hole mobility in strained-Si increases with increasing strain (i.e., with Ge mole fraction, x, in the

Simulation of strained-Si HFETs

215

substrate [61]) and due to the absence of alloy scattering in strainedSi [11], the enhancement in hole mobility in strained-Si was considered to be the same as in SiGe (but without alloy scattering) in accordance with equation (6.1). This model was implemented for the strained-Si region through an external C function, which is accessible to ATLAS through its C-interpreter interface. The eﬀect of Ge content x on the transconductance at low drain voltage is shown in ﬁgure 6.13 and compared with a control bulk-Si device. A strained-Si device with an abrupt SiGe cap layer shows a transconductance (mobility) enhancement factor up to 1.6 for x = 0.3, comparable with the theoretically predicted hole mobility enhancement [31].

Figure 6.13. Simulated linear transconductance at 300 K (VDS = −0.1 V) for an n+ -gate strained-Si p-MOSFET (abrupt case) with Ge content (x = 0.10, 0.20 and 0.30) and control-Si device. (After Armstrong G A and Maiti C K 1998 Solid-State Electron. 42 487–98.)

216

Strained-Si heterostructure FETs

When a grade-back layer is introduced (see ﬁgure 6.9(b)) the problem of conﬁnement of holes at the strained-Si/SiGe interface can be avoided, as valence band discontinuity is reduced because of Ge grading. It has been shown that for a graded cap layer thickness of 40 nm, the discontinuity in the valence band is almost zero. Hence, conﬁnement of holes and subsequent formation of a parasitic buried channel is reduced and the device becomes a surface channel device. The simulations showed agreement with the experimental results of Rim et al [30], who concluded that the optimal conﬁnement of holes occurs for a graded Si0.7 Ge0.3 buﬀer cap thickness of 40 nm, and gives rise to an enhancement in transconductance of 30%. A separate simulation of a surface-channel long-channel strained-Si n-MOSFET (see ﬁgure 6.5(a) for a typical device structure) has been reported by Armstrong et al [60]. The channel doping was 1016 cm−3 . Figure 6.14(a) shows the simulated output characteristics for a transistor having a gate length of 2 µm and a width of 7.5 µm at room temperature for diﬀerent gate bias. The experimental output characteristics are also shown, in ﬁgure 6.14(b); the data are reproduced from ﬁgure 3(a) in [53]. A good agreement between the simulated and experimental data is observed. A hydrodynamic (HD) simulation using TMA–MEDICI [63] has been used to simulate the deep-submicron (0.1 µm) strained-Si n-MOSFETS [54]. Low lateral ﬁeld mobility models ﬁtted to the measured mobilities (see ﬁgure 6.8) for the strained-Si and epi-Si control devices. In the simulations, high-ﬁeld transport was modelled using a Caughey–Thomaslike mobility expression, modiﬁed to account for the velocity overshoot which results from a local solution of the energy balance equation [63, 64].

Figure 6.14. Output characteristics of a surface channel strained-Si n-MOSFET: (a) simulated and (b) experimental data. (After Welser J J et al 1992 IEEE IEDM Tech. Dig. pp 1000–3.)

MODFETs

217

Figure 6.15. Electron velocity in the channel of a 0.1 µm n-MOSFET calculated by hydrodynamic simulation. Higher mobility in strained-Si enhances the carrier velocity. Use of higher values of τω and vsat for strained-Si in hydrodynamic modelling further increases the velocity (see text). (After Rim K et al 1998 IEEE IEDM Tech. Dig. pp 707–10.)

An energy relaxation time of 0.1 ps was obtained by ﬁtting the measured transconductance for the unstrained Si MOSFETs [65]. A small increase in saturation velocity for strained-Si was observed. Figure 6.15 shows the electron velocity along the channel. Comparison of the HD simulations to the measured data indicates that carrier transport is improved in strained-Si MOSFETs by both enhanced low-ﬁeld mobility, and reduced carrier scattering at high ﬁeld and energy. This is consistent with the trends predicted by MC calculations for steady-state and transient carrier transport in strained-Si. 6.5.

MODFETS

In a modulation-doped FET, carriers are separated from their parent donor or acceptor atoms as they fall across a heterojunction to a lower energy undoped layer. A typical MODFET structure consists of a thin (5–30 nm) well with quantized states in which the carriers move collision-free (twodimensional electron or hole gas (2DEG or 2DHG)); n-wells are strainedSi [66, 67], while p-wells are SiGe (typically up to 30% Ge) [68, 69]. Doping

218

Strained-Si heterostructure FETs

Figure 6.16. Typical layer sequence (a) n-MODFETs with Si channel on a relaxed-SiGe buﬀer, (b) p-MODFET with SiGe channel and (c) p-MODFET with Ge channel on a relaxed-SiGe buﬀer. (After Schaﬄer F 1997 Semicond. Sci. Technol. 12 1515–49.)

is accommodated in a neighbouring SiGe layer or in an Si layer separated from the well by a thin undoped spacer (2–20 nm). The doped layer can be several nm thin or only a sub-atomic δ-doped layer. Figure 6.16 shows the layer sequence typically used for n-MODFETs with an Si-channel and graded-SiGe buﬀer layer. The creation of highquality quantum wells requires a careful adjustment of the layer thicknesses, composition, strain states and the doping levels. A detailed discussion on design strategy and layer sequence of a MODFET is given in [13]. Extensive experimental work on the modulation-doped structures (mostly n-MODFETs) involving strained-Si on relaxed-Si1−x Gex layers has been performed by several groups [41, 66]. Early work used a uniform composition SiGe buﬀer, while recent work uses a compositionally graded buﬀer. Linear or step-grading is essential to minimize dislocation faults and buﬀer layers have to be thick (3 µm) for strained-Si channels. Device fabrication steps include low-temperature processing to avoid degradation of the abruptness of the heterointerfaces, mesa etching and a Pt/Ti/Au Schottky gate with a barrier height of about 0.9 eV. Table 6.4 summarizes important parameters of some of the nMODFETs reported in the literature. The dependence of n-MODFET performance on strain in the Si well and the quality of the SiGe buﬀer layer at diﬀerent temperatures are indicated. The improvement in transconductance obtained in employing a compositionally graded buﬀer layer with optimized layer design occurs principally by minimizing the distance between the 2DEG and the Schottky gate. For 1.2% strain in Si, a room temperature transconductance of

MODFETs

219

Table 6.4. Dependence of n-MODFET performance on strain in Si and quality of SiGe buﬀer layer at diﬀerent temperatures. Type of SiGe buﬀer used

Gate length (µm)

Temp. (K)

Low-ﬁeld mobility (cm2 V−1 s−1 )

gm (mS mm−1 ) (∗∗ extrinsic) (∗ intrinsic)

Ref

1% strain in Si channel Uniform comp. Si0.75 Ge0.25 0.2 µm

1.6

300

1550

40∗∗ 70∗

[67]

80∗∗ 88∗

[70] [71]

1.3% strain in Si channel Uniform comp. Si0.68 Ge0.32 0.3 µm Si0.5 Ge0.5 /Si

1.4

Comp. graded Si0.7 Ge0.3 1.5 µm

1.4

Step graded Si0.7 Ge0.03 (defect density 104 cm−2 )

0.25

Step graded Si0.7 Ge0.3

0.5

300

1090

155∗∗ 1.2% strain in Si channel 300 77

60–72∗∗ 100–133∗∗

300 300 77 77

340∗∗ 380∗ 670∗∗ 800∗

[72]

1.2% strain in Si channel 300 77

1500 9500

330∗∗ 600∗∗

[66]

390∗∗ 520∗∗

[73]

1.2% strain in Si channel 300 77

2600

340 mS mm−1 for a 1.4 µm gate length [72], 390 mS mm−1 for a 0.5 µm gate device [66], and 330 mS mm−1 for a 0.25 µm gate device [73] have been obtained. At room temperature, the highest reported Hall mobility was 2830 cm2 V−1 s−1 [72]. At 77 K and for 1.2% strain, transconductance of 670 mS mm−1 for a 1.4 µm gate device [72], 520 mS mm−1 for a 0.5 µm gate device [73] and 600 mS mm−1 for a 0.25 µm gate device [66], have been measured. Ismail et al [73] have also shown an improved gate design that

220

Strained-Si heterostructure FETs

resulted in a lower leakage at high temperature. These encouraging results are comparable to those reported for high electron mobility transistors (HEMTs) fabricated in GaAs [74]. The ﬁrst reported p-channel MODFET in strained-Si grown on a relaxed-SiGe buﬀer was with a TiSi2 Schottky-barrier gate contact [68]. Transconductances of 2.5 and 3.2 mS mm−1 were measured at 300 K for enhancement- and depletion-mode devices, respectively. Arafa et al [75,76] have described a very high-speed p-type SiGe MODFET using Si1−x Gex channel with x ∼ 0.70 and mesa separation with Ti/Pt/Au Schottky gate. The structure is shown in ﬁgure 6.17, where an inverted layer sequence is used. For the channel, the Ge is graded from x = 0.70 to x = 0.55 (from bottom to top) to prevent holes from being pulled to the upper heterointerface under negative gate bias. These structures have resulted in a hole mobility of 800–1000 cm2 V−1 s−1 at room temperature and of 3300–3500 cm2 V−1 s−1 at 77 K. For a gate length of 0.25 µm, a peak transconductance of 230 mS mm−1 (almost double that of an equivalent silicon p-MOSFET), has led to a unity current gain cut-oﬀ frequency of 24 GHz and a maximum oscillation frequency of 37 GHz at room temperature. Further improvements may be expected in shorter gate

Figure 6.17. Device structures for a high-mobility p-MODFET with a SiGe channel on a relaxed-SiGe buﬀer. (After Arafa M et al 1996 IEEE Electron Device Lett. 17 124–6.)

MODFETs

221

Table 6.5. Si/SiGe n-MODFET device structure data used in simulation. Layer sequence

Thickness (˚ A)

Doping (cm−3 )

Si cap SiGe buﬀer Top supply layer Spacer (SiGe) layer Strained-Si channel Spacer (SiGe) layer Bottom supply layer SiGe buﬀer

50 100 40 30 90 30 40 100

1014 – 1.5 × 1019 – – – 8 × 1018 –

Gate length (µm) Ge concentration (x)

0.18 0.4

– –

length devices by introducing self-aligned gate technology for a reduction in gate/source series resistance. In the following, we consider the Si/SiGe n-MODFET described by Gluck et al [77]. This device was noteworthy (in 1997) as a highperformance MODFET could be realized in SiGe technology, leading to a maximum oscillation frequency of 81 GHz. In the following, we present some results on the high-frequency performance of Si/SiGe nMODFETs investigated using a computer simulation for Schottky gate devices. The SiGe MODFET device layer sequence, thickness and doping used in simulation are shown in table 6.5. The device is depletion mode and operates with the formation of an inversion layer at the heterojunction in strained-Si. The spacer layer (30 ˚ A) and strained-Si channel (90 ˚ A) are assumed to be nominally undoped (∼ 1014 cm−3 ) but the substrate (relaxed-SiGe buﬀer) is doped p-type (1000 Ω cm). The top and bottom SiGe supply layers (with doping levels 1.5 × 1019 cm−3 and 8 × 1018 cm−3 , respectively) supply carriers to the channel. The supply layers are separated by spacer layers (30 ˚ A) from the heterojunction to prevent ionized impurity scattering in the channel. The variables for simulation are the substrate doping, spacer layer thickness, supply layer doping and source-to-drain separation. The strained-Si channel is maintained at a thickness of 90 ˚ A throughout and is nominally undoped. A constant gate length of 0.18 µm has been used. The material parameters and models needed for the simulation are similar to those of the SiGe HBTs as discussed in chapter 4. Most of the relevant transistor parameters, such as transconductance, transit frequency and maximum oscillation frequency, are determined from simulation. Figure 6.18 shows the simulated and experimental room

222

Strained-Si heterostructure FETs

Figure 6.18. Simulated and experimental dc output characteristics of a 0.18 µm gate length SiGe MODFET. Experimental data is from Gluck M et al 1997 Electron. Lett. 33 335–7.)

temperature dc output characteristics of a 0.18 µm gate length SiGe MODFET. A comparison of experimental and simulated current gain and maximum unilateral power gain (MUG) is shown in ﬁgure 6.19. The predicted unity gain cut-oﬀ frequency of 46 GHz and maximum oscillation frequency of 80 GHz well match the experimental measurement. In ﬁgure 6.20, it is clear from the simulated transconductance that the quantum well channel is not completely depleted at zero gate bias. Figure 6.21 shows the gate bias dependence of cut-oﬀ frequency of a typical device. The frequency maximum appears at almost the same gate bias as the transconductance maximum. The drain-source voltage dependence of the device (see ﬁgure 6.22) shows that high cut-oﬀ frequency is even obtained at low voltages (VDS ≥ 1–1.5 V). As good performance is achieved at reduced drain bias, these devices are attractive for low-power circuit applications with reduced supply voltages. Over the last few years, SiGe heterostructure FET devices with outstanding RF performance have been demonstrated. Schottky gate MODFETs, with fmax of up to 92 GHz (the highest maximum frequency of oscillation reported so far for any Si-based FET) and a peak transconductance of 470 mS mm−1 , have been achieved [78]. The n-SiGe MODFET combines the advantages of a heterodevice with well-established Si technology. For p-SiGe MODFETs, cut-oﬀ frequencies of 70 GHz and fmax of 84 GHz have been measured.

MODFETs

223

Figure 6.19. Simulated and experimental current gain and maximum unilateral gain (MUG) as a function of frequency. Experimental data is from Gluck M et al 1997 Electron. Lett. 33 335–7.)

Figure 6.20. Transconductance of a 0.18 µm n-MODFET.

224

Strained-Si heterostructure FETs

Figure 6.21. fT as function of gate voltage for a 0.18 µm n-MODFET.

Figure 6.22. fT as function of drain-source voltage for a 0.18 µm n-MODFET.

Figure 6.23 shows computed cut-oﬀ frequency for an n-SiGe MODFET as a function of gate length [78]. The factor of improvement ranges from around four for a 1 µm gate length down to a limiting value of two for the shortest gate length. Much of the projected improvement is due to higher mobility, but a part is attributed to the higher saturation velocity of the SiGe MODFET (107 cm s−1 compared to 6 × 106 cm s−1 for the Si-MOSFET) [79, 80]. Figure 6.24 shows transit and maximum oscillation

MODFETs

225

Figure 6.23. Computed performance potential for n-type HFETs with and without velocity overshoot. (After Konig U et al 1998 J. Vac. Sci. Technol. B 16 2609–14.)

Figure 6.24. RF performance potential for SiGe HFETs. fT and fmax as a function of gate length for n- and p-SiGe MODFETs are shown. (After Konig U et al 1998 J. Vac. Sci. Technol. B 16 2609–14.)

226

Strained-Si heterostructure FETs

Figure 6.25. Calculated gate delays of SiGe hetero-CMOS circuits as a function of gate length and width. Experimental results from n-type SiGe HFET devices are also shown. (After Konig U et al 1998 J. Vac. Sci. Technol. B 16 2609–14.)

frequencies as a function of gate length for measured results on wide ranging devices of both n- and p-SiGe MODFETs manufactured by IBM and Daimler–Benz [78]. A test chip for digital applications containing inverters, level shifters and ring oscillators has been realized [81]. For digital logic design using SiGe HFET inverters, a second stage to shift the output stage to the input levels is required. Large signal measurements at a supply voltage of 2 V have shown a gate delay of 70 ps for a device with a gate length of 0.3 µm and a delay of 25 ps for a 0.15 µm gate length, after correcting the RC delays of the test set using appropriate on-wafer calibration structures. Simulations (ﬁgure 6.25) predict gate delays below 10 ps even at high loads and even for gate lengths exceeding 0.1 µm. A demonstration chip set, including ring oscillators, inverters, diﬀerential ampliﬁers and diﬀerent test devices, has also been developed [82]. 6.6.

HETEROJUNCTION SI/SIGE CMOS

The demonstration of the superior performances of strained-Si MODFETs and MOSFETs has led to the proposal of combining n- and p-channel devices in a CMOS circuit. Owing to a barrier conﬁned carrier transport in quantum wells with higher mobility, higher vsat and higher carrier density,

Heterojunction Si/SiGe CMOS

227

one can expect higher transconductance, higher speed, lower gate delay, lower noise and low power consumption. Due to the enhanced performance of p-HFETs, equally sized p- and n-FETs can be designed for higher packing density. While standard CMOS need a gate length below 0.2 µm for transconductance around 400 mS mm−1 [83, 84], these are even found at gate lengths of 1.2–1.4 µm with HFETs. The advantages to be gained by using strained-Si/SiGe in conventional Si-CMOS technology have been examined by several workers [64,85–88]. As high electron mobility (2200–3000 cm2 V−1 s−1 ) [28] in strained-Si channels under tensile strain and hole mobility (800–1500 cm2 V−1 s−1 ) [89] in compressively strained SiGe channels have been achieved, both n- and ptype modulation-doped FETs have been fabricated using both strained-Si and SiGe layers. For the n-MODFET, the n-doped (phosphorus, 25 keV, 5×1014 cm−2 ) Si0.7 Ge0.3 layer was separated from the Si channel by a spacer of 30 ˚ A thick Si0.7 Ge0.3 . The Schottky gate was formed by Pt. At a 0.4 µm gate length, the measured peak transconductance of 420 mS mm−1 was a factor of two higher than an equivalent Si n-MOSFET, and comparable to GaAs technology. The microwave performance was also impressive, with an fT of 40 GHz and an fmax of 56 GHz for a 0.4 µm gate length [85]. This level of performance is comparable to that of a GaAs/AlGaAs HEMT, and may potentially be further improved if an insulating SOI substrate is used [90]. For the corresponding p-MODFET, the Si0.7 Ge0.3 layer was doped with boron, followed by a 25 ˚ A thick spacer, and then a strained 40 ˚ A Si0.3 Ge0.7 channel, which was ﬁnally capped with a 200 ˚ A thick Si0.7 Ge0.3 layer. The peak intrinsic transconductance of 280 mS mm−1 at a 0.23 µm gate length was more than double the value of the equivalent Si p-MOSFET at the same gate length, with corresponding high values of fT of 30 GHz and fmax of 45 GHz [85]. It has been predicted that sub-0.2 µm SiGe HFETs will yield more than 800 mS mm−1 at room temperature and above 1000 mS mm−1 at 77 K [9]. Figure 6.26 shows the predicted transconductance for HCMOS extrapolated from measurements on 1.2–1.4 µm MODFETs in comparison to the best Si-MOSFETs. These results are corroborated by experimental demonstrations [77,85], which are both based on s-parameter measurements on mesa-type devices with submicron gates deﬁned by ebeam lithography. Based on the above experimental demonstration, using computer simulation, O’Neill and Antoniadis [64, 87] have investigated the highfrequency (microwave) performance of submicron p- and n-channel Si/SiGe-based FETs suitable for CMOS technology. Two-dimensional simulation of devices, having gate lengths down to 0.1 µm using a hydrodynamic model, demonstrated an enhancement in fT of around 50% for n-channel devices and more than 100% for p-channel devices.

228

Strained-Si heterostructure FETs

Figure 6.26. Predicted transconductance of high-performance HCMOS extrapolated from measurements on 1.2–1.4 µm MODFETs, in comparison with best Si-MOSFETs. (After Konig U and Daembkes H 1995 Solid-State Electron. 38 1595–602.)

Ismail [85] has modelled the performance of Schottky gate complementary MODFET structures, where electrons ﬂow through a strained-Si channel and the holes through a strained-SiGe layer, both channels being epitaxially grown on Si substrates (see ﬁgure 6.27). For a 0.1 µm gate length, the calculated peak transconductance of the nMODFET was 820 mS mm−1 , whereas that of the p-MODFET was 610 mS mm−1 . The predicted delay for an inverter was 11 ps at a power dissipation/stage of 0.07 mW. The power delay product of Si/SiGe CMOS is evidently lower than Si CMOS or SOI technology while operating at a lower supply voltage. Due to inherent problems, such as nonplanarity, higher leakage current, diﬃculty in threshold voltage adjustment and reproducibility for manufacturing associated with Schottky gates, the authors also studied Si/SiGe CMOS structures, as shown in ﬁgure 6.28. The structure is planar and uses SiO2 as a gate insulator and polySi as the gate material. In this case, an Si cap layer was used, on which either a low-temperature oxide (LTO) was deposited, or a gate oxide was thermally grown. For an eﬀective gate length of 0.1 µm and with an oxide thickness of 50 ˚ A, the predicted transconductances of n- and p-MOSFETs are 750 and 600 mS mm−1 , respectively. Several authors [86, 88] have proposed the design for an Si/SiGe heterojunction CMOS which is planar and avoids inversion of the parasitic surface channel within the operating voltage range. The schematic cross

Heterojunction Si/SiGe CMOS

229

Figure 6.27. Complementary Si/SiGe MODFET cross section. (After Ismail K 1995 IEEE IEDM Tech. Dig. pp 509–12.)

Figure 6.28. Complementary Si/SiGe MOSFET cross section. (After Ismail K 1995 IEEE IEDM Tech. Dig. pp 509–12.)

230

Strained-Si heterostructure FETs

(a)

(b)

Figure 6.29. (a) Cross section of a proposed Si/SiGe HCMOS technology and (b) schematic diagram of channel layers and conduction and valence band for gate bias just above VT . (After Armstrong M A et al 1995 IEEE IEDM Tech. Dig. pp 761–4.)

section of such a proposed structure is shown in ﬁgure 6.29. As discussed above, the design provides for both a compressively strained-SiGe hole channel and a tensile strained-Si electron channel in a planar structure. The layers are grown on a low defect density (1 × 105 cm−2 ) relaxed graded SiGe buﬀer. The p-well is in situ doped during growth of the relaxed buﬀer, while the n-well is created by ion implantation prior to growth of the channel layers. An undoped spacer is grown above the well doping in order to adjust the threshold voltage. An n-type δ-doped layer is used to bend the energy bands so as to avoid inversion of the low-mobility Si surface channel. The strained-Si electron channel is separated from the δ-doped layer by an undoped setback layer to minimize ionized impurity

Summary

231

Figure 6.30. Power delay product versus stage delay for Si/SiGe HCMOS and bulk-Si CMOS. The corresponding drain bias values are indicated on the curves. (After Armstrong M A et al 1995 IEEE IEDM Tech. Dig. pp 761–4.)

scattering. A graded Ge content is used in the strained-SiGe hole channel to minimize the surface roughness scattering by pushing the carriers away from the oxide interface. A thin Si cap layer allows a high-quality gate oxide to be grown. An in situ doped p+ -polySi gate is used for the devices. Device and circuit simulations show the performance advantage of the proposed technology over bulk-Si CMOS for an eﬀective gate length of 0.2 µm. Figure 6.30 shows the simulated power delay product versus stage delay of an 11-stage inverter ring oscillator, comparing Leﬀ = 0.2 µm Si/SiGe HCMOS to bulk-Si CMOS, for unloaded and loaded (CL = 10 fF) cases. The higher carrier mobility of the HCMOS results in a sixfold improvement in the power delay product at a stage delay of 28 ps for the unloaded case and a fourfold improvement at a delay of 55 ps for the loaded case. A minimum delay of 22 ps is predicted for unloaded Si/SiGe HCMOS running at 1.5 V. 6.7.

SUMMARY

In this chapter, recent progress in strained-Si on relaxed-SiGe buﬀer has been reviewed. Progress in design and fabrication of high mobility nand p-channel strained-Si/SiGe devices (MOSFETs and MODFETs) were

232

Strained-Si heterostructure FETs

presented, as well as some of the materials and processing issues related to the fabrication of these heterostructures. Due to their compatibility with conventional Si-processing technology, mobility enhanced HFETs are expected to provide performance advantage, when down scaling in device dimensions will no longer be possible in bulk-Si. Since low-power mixed-mode circuits are becoming increasingly important for mobile communications, Si/SiGe heterojunction CMOS technology will be useful for the improvement of high-frequency performance. However, from a manufacturing point of view, several issues of concern, such as device isolation, interconnects and reliability, require further experimental investigation in order to assess the true potential of Si/SiGe HCMOS.

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Chapter 7 SIGE HETEROSTRUCTURE FETS

Over the past 20 years, the channel length of MOS transistors has halved at intervals of approximately three or four years. This continual shrinking of the size of MOS transistors has led to increasing performance in electronic systems and increasing packing density. The question that arises now is ‘how long can this trend continue?’ A number of factors are posing a threat to the evolution of CMOS technology. Firstly, the channel length of the MOS transistor is deﬁned using optical lithography, which is limited by the wavelength of the radiation used. The current thinking is that optical lithography can reach channel lengths of around 0.15 µm, but it is not clear that it can meet the challenge of smaller geometries. Other lithography techniques exist, such as electron beam and x-ray lithography, but these have associated problems that remain to be solved. Improvements in MOSFET saturated drain current have been achieved by shrinking the source-to-drain separation or eﬀective gate length (Leﬀ ) and through the use of thinner gate oxides to increase the gate capacitance to improve inversion charge density. Predictions for static random access memory (SRAM) technology anticipate gate oxide thicknesses of the order of 4 nm and gate lengths of 0.15 µm (see table 7.1) [1]. However, the requirement for highly uniform gate oxide ﬁlms across a large wafer calls into question the continuous reduction of gate oxide thickness to improve inversion charge density. Also, below 0.35 µm gate lengths, the carriers in the channel of the MOSFET attain a saturated velocity that is nearly independent of Leﬀ . As a result of these two limits—oxide scaling and carrier velocity saturation—it appears that the MOSFET saturated drain current is approaching a fundamental physical limit. In chapter 6, on strained-Si, it has been shown that electron or hole conﬁnement structures (n-HFET or p-HFET) require more complex growth techniques for strained-Si on relaxed thick SiGe layers, and are limited in terms of processing thermal budget. In contrast, the p-HFET is more easily realized, since it involves the growth of strained-Si1−x Gex epitaxial ﬁlms 238

SiGe heterostructure FETs

239

Table 7.1. CMOS scaling guidelines. (After Davari B 1996 IEEE IEDM Tech. Dig. pp 555–8.)

Lithography resolution µm General Gate level for short L

1995

1998

2001

2004

0.5 0.35

0.35 0.25

0.25 0.18

0.18 0.13

Channel length (µm)

0.35/0.25

0.2/0.15

0.1

0.07

Gate insulator thickness (nm)

9/7

6/5

3.5

2.5

Supply Voltage (V) High performance Low power

3.3/2.5 2.5/1.5

2.5/1.8 1.5/1.2

1.5 1.0

1.2 0.8

Relative speed High performance Low power

2.7/3.4 2.0/2.4

4.2/5.1 3.2/3.5

7.2 4.5

9.6 5.8

Relative power/function High performance Low power

0.47/0.34 0.20/0.09

0.29/0.18 0.08/0.056

0.12 0.036

0.077 0.027

on an Si substrate. In this device, the Si1−x Gex quantum well acts as a channel for holes between the source and drain regions of the device, as shown in ﬁgure 7.1. Improved electrical characteristics of this device over the conventional surface channel Si p-MOSFET are the results of improved carrier transport, quantum conﬁnement and buried channel operation. p-HFETs provide quantum conﬁned carrier conduction with high carrier mobility, which is critical for high-frequency Si-based integrated circuits. Some of the key parameters of several reported SiGe-channel devices are shown in table 7.2. High saturated drift velocity of holes, due to strain-induced transport enhancements in SiGe, allows for equivalently sized n- and p-channel devices and, consequently, increased circuit densities. Coupled to this, the ability to produce quantum devices on the same chip gives SiGe substantial potential for advanced circuits. SiGe channel p-HFETs have the following potential advantages: • • • •

large carrier population in the channel at low gate biases due to quantum conﬁnement; buried channel operation to suppress hot carrier eﬀects; low defect density using conventional Si substrates; and process compatibility with existing CMOS process lines.

240

SiGe heterostructure FETs

Figure 7.1. Device structure for a typical SiGe-channel p-HFET fabricated in a strained-SiGe layer with an Si-cap layer. Layer thicknesses shown are typical.

Table 7.2. Some of the reported results for SiGe p-HFETs. gm,ext (mS mm−1 ) Leﬀ µm

Channel (mode)

300 K

77 K

0.18

buried-SiGe (enhanced)

–

–

0.25

buried-SiGe (enhanced)

167

0.7

buried-SiGe (enhanced)

64

0.9

buried-SiGe (enhanced)

1.0

surface-SiGe (enhanced)

48

1.0

buried-SiGe (depletion)

80

4.0

buried-Ge (enhanced)

–

–

Gate

Gate material

Ref

45 ˚ A Ther.

n+ poly

[2]

201

71 ˚ A Ther.

TiSi2

[3]

–

50 ˚ A Ther.

polySi

[4]

–

70 ˚ A PECVD

n+ poly

[5]

n+ poly

[6]

p+ poly

[7]

Al

[8]

60 – 50

tox (Tech.)

100 ˚ A ECR 65 ˚ A WRTO 500 ˚ A CVD

HFETs: structures and operation

241

In this chapter, a review on the present status of silicon heterostructure ﬁeld eﬀect transistors in the SiGe and SiGeC material systems is presented. The physics and modelling of submicron p-HFETs are explored using numerical simulation to determine the potential applications in ULSI circuits. The key design issues such as Ge mole fraction, gate oxide thickness and choice of gate contact material have been considered in detail. The choice of the cap layer thickness for a buried SiGe channel is an important issue, having a bearing on the performance of a p-HFET, and due consideration is given. Also considered are a number of variants of the basic SiGe HFET, pHFETs built on SOI substrates and SiC/SiGeC channel devices. Vertical SiGe and SiGeC p-HFETs are also attractive for ultra-short channel devices because the channel length is determined by the thickness of an epitaxial layer and not by the lithography resolution. Vertical channel and scaling issues are considered. Poly-Si1−x Gex has shown great potential as a gate material due to its tunable work function, process compatibility and favourable electrical properties, such as low sheet resistance and high dopant activation rate. It can also be used in place of polySi in thinﬁlm transistors on glass. Finally the noise properties of SiGe p-HFETs are considered. 7.1.

HFETS: STRUCTURES AND OPERATION

A SiGe p-HFET with a general structure similar to a conventional MOSFET is shown in ﬁgure 7.1. It has an n+ (or p+ )-polySi or polySiGe gate over a thin gate oxide, with p+ source/drain regions in an ntype body. The main distinctive features are the buried SiGe layer and the optional p+ doping spike (δ-doping) located below it. The SiGe layer actually constitutes a sub-surface quantum well channel for holes between the source/drain regions. It is required to be buried below an Si-cap because a high-quality gate oxide directly on SiGe using thermal techniques is diﬃcult to obtain. If such a direct oxidation of SiGe is attempted, the Si is preferentially oxidized, leading to a pile-up of Ge at the SiGe/SiO2 interface [9, 10]. Plasma enhanced chemical vapour deposited (PECVD) oxides do not have signiﬁcantly lower interface state densities, since the initial stages of this process consist of oxide growth and not deposition [11]. The interface state density of such oxides is greater than 1012 cm−2 eV−1 , a ﬁgure unsuitable for proper operation of a ﬁeld-eﬀect device. Stoichiometric oxides formed directly on SiGe using low-temperature plasma techniques have been reported [12,13] and microwave/ECR plasma grown oxides have been used for device fabrication [6]. The use of an Si-cap layer has been customary as oxidation of the Sicap assures formation of a high-quality gate oxide. But this requirement reduces the eﬃciency of the device, to which the high mobility carriers in

242

SiGe heterostructure FETs

the SiGe layer can be modulated, due to the increased physical separation from the gate potential and the presence of a surface inversion layer that forms at high gate overdrive. However, the buried channel provides beneﬁts, such as the suppression of hot carrier injection into the gate oxide and reduced carrier surface scattering, which tend to enhance device performance and reliability. The next important feature of the device is the presence of an optional δ-doping spike, which is generally realized using boron. The doping spike is separated from the SiGe channel by an Si spacer to reduce ionized acceptor scattering which occurs if the spike is placed too close to the channel. Furthermore, the doping spike is placed below the SiGe channel, so that the application of a negative gate bias draws holes upward towards the SiGe channel. The doping spike has two major functions: (i)

it creates a retarding electric ﬁeld for holes at zero gate bias to suppress source/drain leakage current (threshold adjust); and (ii) it provides holes for the SiGe quantum well for improved device transconductance. For high-speed operation, the p-HFET should be operated under bias conditions in which the hole density in the SiGe well exceeds that in the Si-cap. Determining this bias range requires the calculation of the hole density in the two inversion layers as a function of gate bias. 7.1.1.

Experimental HFETs

Several research groups have fabricated SiGe-channel p-HFETs, mostly using conventional Si-processing technology, and performance enhancement compared to bulk-Si devices has been reported [2–8]. In some designs, the Ge proﬁle was graded to optimize the hole conﬁnement and modulation doping (δ-doping) was used to adjust the threshold voltage. The cross section of such a SiGe-channel p-HFET, also known as a modulation-doped SiGe p-MOSFET (MODMOS), is shown in ﬁgure 7.2 [5]. In table 7.2, some of the key parameters are compared for some of the reported p-HFETs including those fabricated on Ge substrate [8] and on SIMOX [7]. Deep submicron (gate length 0.18 µm) SiGe-channel pHFETs using strained-Si1−x Gex ﬁlms in a standard CMOS process have been reported by Bouillon et al [2]. The channel architecture of the p+ polySi gate Si0.85 Ge0.15 channel p-HFET is shown in ﬁgure 7.3. Several 0.18 µm transistors with diﬀerent architectures were fabricated. Retrograde channel proﬁle, heavy ion implant (HI) using P and As, followed by intrinsic Si epitaxy and conventional processing techniques, were employed. The enhancement of hole mobility in the direction perpendicular to the growth plane of strained-Si1−x Gex , and grading the SiGe channel, are both eﬀective in the enhancement of the drive current. Figure 7.4

HFETs: structures and operation

243

Figure 7.2. Schematic cross section of the modulation-doped SiGe p-MOSFET. An n+ -gate, together with a boron-doped layer placed underneath the SiGe channel, is used to enhance the carrier conﬁnement while obtaining the correct threshold voltage. Devices with three diﬀerent channel gradings are fabricated: (a) the abrupt; (b) the graded; and (c) the retrograded proﬁle. (After Verdonckt-Vandebroek S et al 1994 IEEE Trans. Electron Devices 41 90–102.)

Figure 7.3. Cross section of a 0.18 µm p+ -polySi gate Si0.85 Ge0.15 -channel p-HFET. (After Bouillon P et al 1996 IEEE IEDM Tech. Dig. pp 559–62.)

244

SiGe heterostructure FETs

Figure 7.4. Output characteristics of a 0.18 µm p-HFET with an Si0.85 Ge0.15 channel. Implantation conditions were: AS2, arsenic 200 keV/1E13; AS4, arsenic 120 keV/4E12; AS1+40, arsenic 120 keV/1E13 + 40 nm cap layer. (After Bouillon P et al 1996 IEEE IEDM Tech. Dig. pp 559–62.)

Figure 7.5. Subthreshold characteristics of a 0.18 µm p+ -polySi gate Si0.85 Ge0.15 -channel p-HFET. Implantation conditions were: AS2, arsenic 200 keV/1E13; AS4, arsenic 120 keV/4E12; AS1+40, arsenic 120 keV/1E13 + 40 nm cap layer. (After Bouillon P et al 1996 IEEE IEDM Tech. Dig. pp 559–62.)

Design of SiGe p-HFETs

245

shows the output characteristics, while ﬁgure 7.5 compares short-channel subthreshold characteristics. 7.2.

DESIGN OF SIGE P-HFETS

The SiGe HFET design objective is to maximize the device transconductance. This can be accomplished by maximizing the number of high-mobility holes in the SiGe channel, while minimizing the density of low-mobility holes which ﬂow at the Si/SiO2 interface. The critical SiGe HFET design parameters include the choice of gate material, layer thicknesses and SiGe channel proﬁle. The type of gate material used strongly inﬂuences the degree of hole conﬁnement to the SiGe channel p-HFETs [14]. State-of-the-art CMOS technologies are characterized by dual work function polysilicon gates, such that both the n- and p-channel MOSFETs are surface-channel devices [15, 16]. A single work function CMOS technology leads, however, to signiﬁcant process simpliﬁcation. The impact of each of these design parameters on device performance is investigated with the use of a simulation tool. For the design of deep submicron pMOSFETs necessary for ULSI, two-dimensional numerical modelling is necessary to accurately quantify short-channel eﬀects. Once again the Silvaco–ATLAS device simulation tool has been used. 7.2.1.

SiGe: MOS capacitor simulation

A typical Si/strained-SiGe/Si p-HFET structure, as shown in ﬁgure 7.1, is chosen and subsequent variations in this structure are studied to maximize the hole concentration in the SiGe quantum well over the realizable gate bias swing. It is instructive to see the distribution of the hole density in the Si-cap and SiGe-channel for n+ - and p+ -poly gate contacts. This can be accomplished using a 1D Poisson solver. A 1D self-consistent solution of the Schrodinger and Poisson equations have been reported [17]. However, the use of the Schrodinger–Poisson solver is very time-consuming, so the simple 1D Poisson solver is deemed to be adequate to illustrate the main concept. Quantum eﬀects are therefore neglected. In ﬁgure 7.6 the integrated density (cm−2 ) of holes in both the Si-cap and SiGe quantum well is plotted as a function of gate bias. From this ﬁgure it is seen that, as the negative gate bias is increased, the Si1−x Gex channel turns on ﬁrst, and the hole density in the SiGe quantum well increases, revealing a very interesting eﬀect associated with the buried channel pHFET—charge screening. For a p+ -poly contact, a gate bias in excess of −1.5 V results in a saturation of the hole density in the SiGe quantum well, while the carrier density in the Si-cap continues to increase. This saturation of the SiGe hole population is due to the build-up of holes in

246

SiGe heterostructure FETs

Figure 7.6. One-dimensional Poisson simulations of the Si-cap and SiGe-channel charges for n+ - and p+ -poly gate SiGe HFETs. The channel is 300 ˚ A wide with a ﬂat 30% Ge proﬁle, oxide thickness is 70 ˚ A and substrate doping is 5 × 1016 cm−3 n-type.

the Si-cap with increasing gate bias. As more holes populate the Si-cap inversion layer, the eﬀect of the gate potential is screened out and the quantum well eﬀectively ‘sees’ no increase in the gate potential. The point at which the number of holes in the SiGe well equals the number in the Si-cap is termed the ‘cross-over point’. 7.2.2.

Si-cap/oxide thickness variation

Figure 7.7 is a plot of the integrated hole density in the SiGe well and Sicap layer as a function of cap thickness, for two oxide (tox = 70 and 140 ˚ A) thicknesses. The plot reveals that when VG = −2.0 V, for tox = 140 ˚ A, the hole density in the well decreases slightly as the cap thickness is increased, while the hole density in the Si-cap shows a modest increase. The hole density in the well drops more dramatically (for tox = 70 ˚ A) as the cap thickness is increased while the hole density in the cap increases. Therefore, it is advantageous to keep the cap thickness as small as possible to keep the hole population in the Si cap low and reduce the eﬀects of charge screening on the SiGe quantum well. If the gate oxide is kept thin (∼100 ˚ A), then an initial Si-cap thickness of 50 ˚ A is suﬃcient for a uniform oxide to be grown across a wafer surface. However, it should be noted that a remaining cap thickness of only 10 ˚ A is enough to support an inversion layer. Hence, the charge screening problem

Design of SiGe p-HFETs

247

Figure 7.7. One-dimensional Poisson simulation of areal hole density in the SiGe well and the Si-cap as a function of cap thickness and oxide thickness.

will still be present with such a structure. Consequently, the device can be operated at low gate voltages, where the SiGe quantum well dominates device electrical characteristics. A thinner gate oxide results in a higher current drive and gm due to the improved capacitive coupling between gate and channel charges. These improvements in performance will always overcome the disadvantage of the small reduction in VG arising with the thinner oxide. 7.2.3.

Germanium mole fraction

A higher Ge mole fraction in the channel is desirable from a transport viewpoint, since the hole mobility in pseudomorphic Si1−x Gex ﬁlms increases with increasing Ge content [18]. Figure 7.8 is a plot of integrated hole density as a function of Ge content. From the ﬁgure, it is seen that hole density in the quantum well increases almost linearly with Ge content x, once the cross-over point is reached. A capacitance–voltage (C–V ) measurement of a SiGe HFET is an accurate method to conﬁrm the presence of the 2DHG in the SiGe quantum well and characterize the electrical quality of the gate oxide [19]. Figure 7.9 displays the simulated low-frequency and high-frequency C–V characteristics of a p-HFET at room temperature. The kink in the characteristics between gate biases of −1 and −2 V is a result of the quantum well. Initially, during inversion, holes reside in the SiGe quantum

248

SiGe heterostructure FETs

Figure 7.8. Simulated Si-cap and SiGe-channel hole density for n+ -poly gate SiGe HFETs as a function of mole fraction for a ﬂat Ge proﬁle.

Figure 7.9. Simulated high-frequency (x = 0.2, 0.3 and 0.4) and low-frequency (x = 0.40) capacitance–voltage characteristics showing the hole conﬁnement in a p+ -poly gate SiGe HFET with an Si-cap (70 ˚ A), oxide thickness (65 ˚ A) and a SiGe channel 100 ˚ A wide as a function of Ge mole fraction, x, with a ﬂat Ge proﬁle.

Design of SiGe p-HFETs

249

well. Hence, the structure exhibits a lower eﬀective capacitance due to the series combination of the oxide and Si-cap capacitances. As the structure is biased more negatively, the inversion layer in the Si-cap forms and the capacitance of the structure approaches the oxide capacitance, Cox . 7.2.4.

Choice of gate material

The choice of gate material has a signiﬁcant eﬀect on the turnon characteristics of a p-MOSFET. Typically for surface channel Si p-MOSFETs, a p+ -polySi gate is employed to place the MOSFET threshold voltage close to −0.5 V. If a p+ -polySi gate is used with a buried channel, then the device operates in depletion mode. However, if an n+ polySi gate is used, then the device threshold voltage is shifted towards negative by about 1 V. Consequently, the buried channel device operates in enhancement mode, with the buried channel carrier transport properties determining the MOSFET electrical characteristics at low gate biases. The diﬀerence between n+ - and p+ -polySi gates for the p-HFET structure is illustrated in ﬁgure 7.10. For the n+ -polySi gate, the SiGe layer dominates channel conduction for gate biases up to −1.5 V, after which the Si-cap inversion layer forms. For the p+ -polySi gate, the Si-cap inversion layer is already present at 0 V gate bias, hence the device operates in depletion mode. Hence, an n+ gate design is favourable for the p-HFET, because it promotes SiGe quantum well operation for low gate biases.

Figure 7.10. Threshold voltage versus substrate doping for p+ - and n+ -poly gate SiGe-channel p-HFETs.

250

SiGe heterostructure FETs

Clearly, based on the foregoing discussions, the cap layer should be made as thin as possible. However, a minimum value may be obtained by considering the two primary limitations: avoidance of high interface state densities (a minimum thickness of silicon cap layer of the order of 50–60 ˚ A may be required [11]) and the avoidance of remote carrier scattering (by the insulator–semiconductor interface). Some experimental evidence suggests the latter limitation may require a cap layer thickness of the order of 100 ˚ A [20]. To enable signiﬁcant beneﬁt to be gained from the use of buried strained layer channels in submicron p-HFETs, two options exist: increase the oﬀset potential between the cap and channel layers or reduce the peak ﬁeld in the semiconductor. Growth of the SiGe-channel HFETs on siliconon-insulator (SIMOX) substrates is one approach to ﬁeld reduction [7]. A simpler alternative to increase transconductance is to use a p+ doping spike (δ-doping) below the SiGe quantum well. 7.2.5.

Current–voltage characteristics

The use of a buried channel (see ﬁgure 7.1) is expected to improve carrier mobility and noise performance by reducing the interaction of carriers with the oxide interface. As previously discussed, a major constraint on HFET performance is the onset of parasitic inversion at the Si-cap and oxide interface, where the carriers face mobility degradation. This limits the degree of inversion in the strained channel layer by electrostatic screening and hence degrades the small-signal transconductance. The material parameters and models needed for the simulation of p-HFETs are similar to those of SiGe HBTs discussed in chapter 4. A reduced eﬀective density of state (DOS) in the valence band, Nv , is inherent in the use of compressively strained SiGe channels on Si [21], being intimately linked to the enhanced hole mobility [22, 23]. The lower DOS eﬀective hole mass and the reduced carrier scattering due to the lifting of the valence band degeneracy are both thought to contribute to higher mobility. As the Ge fraction x in a strained SiGe layer is increased, Nv is predicted to fall monotonically [23] by a factor of 5.6 at x = 0.3, an eﬀect that cannot not be ignored in modelling HFETs. The carrier mobility in the surface channel was assumed to be degraded with increasing transverse and longitudinal ﬁelds in a similar manner to a conventional MOSFET using the special purpose (CVT) MOS mobility model [24]. The mobility in the buried SiGe channel was assumed to be insensitive to the transverse ﬁeld and solely a function of doping and longitudinal ﬁeld. Fermi–Dirac statistics for the computation of carrier density and a dense mesh speciﬁcation for the thin epitaxial layers are required for accurate modelling of charge distributions and drift–diﬀusion-based current formulations have been found to be suﬃcient for the range of channel lengths investigated (down to 0.1 µm). An epitaxial Si-cap layer (30 ˚ A)

Design of SiGe p-HFETs

251

˚) are deﬁned to be doped (1 × 1016 cm−3 and and a SiGe layer (300 A 17 −3 1 × 10 cm , respectively), and the underlying substrate (or n-well), uniformly doped to 1 × 1016 cm−3 . The oxide layer thickness is 80 ˚ A and interface states are neglected. An n+ -polySi gate is used and the threshold voltage is allowed to shift freely according to channel doping and layer thicknesses. The dc output characteristics and small-signal transconductance have been generated and the respective inversion layer carrier populations in the Si cap and SiGe channel have been extracted by integrating the carrier proﬁles across the depths of the respective layer. The eﬀect of Ge content on the linear transconductance is shown in ﬁgure 7.11 as a function of gate voltage. When compared to an Si device, the enhanced mobility in the SiGe-channel p-HFETs gives rise to higher transconductance, which increases further with Ge content x. The eﬀect of Ge content on the output characteristics is shown in ﬁgure 7.12. As expected, the drain current increases with Ge content x in a similar manner. A useful measure for characterizing the subthreshold behaviour of a MOSFET is its subthreshold swing, S, which is deﬁned as the slope of the log (ID ) versus VG characteristic, just prior to the threshold voltage, VT . A low value of subthreshold slope is desirable in submicron gate length p-HFETs to achieve low threshold voltage and a negligible oﬀ-state leakage. Figure 7.13 illustrates that the incorporation of Ge merely shifts

Figure 7.11. Simulated linear transconductance of a SiGe p-HFET at 300 K (VDS = 0.1 V) as a function of Ge content in the SiGe channel.

252

SiGe heterostructure FETs

Figure 7.12. Simulated I–V characteristics of a SiGe-channel p-HFET at 300 K for diﬀerent Ge content in the SiGe channel.

the threshold voltage and has a negligible eﬀect on the subthreshold slope. If a δ-doping spike is placed below the active Si1−x Gex channel separated by a spacer, then the subthreshold characteristic can be signiﬁcantly improved [17]. The doping spike creates an electric ﬁeld that repels holes for gate voltages below the threshold voltage, signiﬁcantly improving the subthreshold swing of the p-HFET. 7.2.6.

δ-doped p-HFETs

The δ-doped layer is separated from the SiGe quantum well by a thin spacer to reduce the eﬀects of ionized impurity scattering. The purpose of using a δ-doping spike is primarily to reduce the number of holes at zero bias by creating a retarding electric ﬁeld which improves the subthreshold characteristic of the device. However, the doping spike does not contribute a large number of holes to the SiGe quantum well. The contribution is a function of the spacer thickness, and generally increases with decreasing spacer thickness. It has been shown experimentally that a δ-doped acceptor layer below (but in close proximity to) the SiGe channel allows the inversion layer carrier concentration in the SiGe channel to be increased [11, 25]. In addition, the δ-doping layer reduces the threshold voltage for inversion of the channel and increases VGS . However, locating a narrow highly-doped boron layer immediately underneath the channel of the n+ gate SiGe HFET

Design of SiGe p-HFETs

253

Figure 7.13. Simulated subthreshold characteristics of a SiGe-channel p-HFET at 300 K for diﬀerent Ge content in the SiGe channel.

Figure 7.14. Simulated dc characteristics of an Si0.7 Ge0.3 p-HFET with a δ-doping layer.

254

SiGe heterostructure FETs

places severe limitations on its fabrication since the SiGe channel should remain undoped. Figure 7.14 shows the output characteristics of a device with a 30 ˚ A thick Si cap and eﬀective gate length of 0.5 µm is enhanced by the addition of a 50 ˚ A thick δ-doping layer (Nδ of 2 × 1018 cm−3 ) with a spacer of 30 ˚ A below the channel. This very signiﬁcant increase in the device current demonstrates the improvement in performance possible through epitaxial growth capabilities, such as in situ modulation doping, apart from gains achieved through increased mobility. Note that, in this case, an n+ -polySi gate is required to ensure enhancement mode operation (negative VT ) in the same manner as for a conventional buried channel p-MOSFET. The increase in VGS is largely due to the reduction in the transverse ﬁeld achieved by the presence of the fully depleted δ-doped layer. 7.3.

SIGE P-HFETS ON SOI

As described in the previous section, a SiGe quantum well p-channel HFET has been shown to have a higher channel mobility compared to that of a bulk-Si MOSFET. In order to further improve the channel mobility, the hole conﬁnement in the quantum well must be enhanced. This is particularly diﬃcult to achieve at a higher gate voltage, because the surface channel at the SiO2 /Si interface dominates conduction. As discussed more fully in chapter 10, fully-depleted SOI (FDSOI) devices have been considered for ULSI applications because of improved device isolation, reduced parasitic capacitance and higher circuit speed [26,27]. Due to the presence of a thick buried oxide layer in an FDSOI device, the vertical electric ﬁeld and the band bending at the Si surface are signiﬁcantly reduced, compared to that of a bulk-Si device [26]. This property of reduced band bending of an SOI structure can be used to improve the hole conﬁnement in the buried SiGe quantum well, and hence improve device performance. Schematic diagrams of a device used in simulation for bulk-Si and SiGe SIMOX are shown in ﬁgure 7.15. The SiGe SIMOX substrate consists of a

Figure 7.15. Schematic diagrams of a bulk SIMOX substrate and a SiGe SIMOX substrate in which a p+ -poly gate SiGe-channel HFETs are fabricated. (After Nayak D K et al 1993 IEEE Electron Device Lett. 14 520–2.)

SiGe p-HFETs on SOI

255

Figure 7.16. Comparison of 1D Poisson simulations of the low-frequency capacitance–voltage characteristics (showing the hole conﬁnement) in a p+ -poly gate SiGe HFET on an Si-substrate and on a SIMOX. The simulation was carried out with an Si-cap (70 ˚ A), the oxide thickness (65 ˚ A) and a SiGe channel 100 ˚ A wide with a ﬂat Ge proﬁle (x = 0.30).

conventional SIMOX substrate, a 100 ˚ A Si layer, a 100 ˚ A Si0.7 Ge0.3 strained ˚ layer and a 100 A Si-cap layer. As discussed earlier, one way to verify the hole conﬁnement in the quantum well is to study the low-frequency capacitance, where a plateau in the inversion capacitance signiﬁes the hole conﬁnement [28]. Figure 7.16 shows that the plateau in low-frequency capacitance associated with the buried channel region extends for a wider range of gate voltage for the SIMOX substrate, when compared to the SiGe bulk-Si substrate. Room temperature hole density proﬁles for n+ -poly gate SiGe-channel HFETs on Si and SIMOX substrates are compared in ﬁgure 7.17. It is seen that the hole concentration at the Si surface for the SiGe SIMOX device is about two orders of magnitude smaller than that for the SiGe bulk device. This means that the channel conduction through the parasitic surface channel is signiﬁcantly diminished, due to reduced band bending at the surface. The reduced band bending results in a more uniform hole concentration in the quantum well for the SiGe SIMOX device, a conclusion that has been conﬁrmed by experiment [7]. It has been shown that the linear transconductance remains near its peak value for a wide range of gate voltages at 300 K due to signiﬁcant hole conﬁnement in the quantum well near the threshold, which is not observed for SiGe bulk devices. The centroid of the hole distribution in

256

SiGe heterostructure FETs

Figure 7.17. Comparison of 1D Poisson simulations of hole density proﬁles at room temperature for a n+ -poly gate SiGe-channel HFETs on Si and SIMOX substrates. The simulation was carried out with VG –VT = −0.5 V, an Si-cap (70 ˚ A), the oxide thickness (65 ˚ A) and a SiGe channel 100 ˚ A wide with a ﬂat Ge proﬁle (x = 0.30).

the Si0.7 Ge0.3 quantum well of the SiGe SIMOX device is located farther away from the Si/SiO2 interface when compared to that in the SiGe bulk device, which reduces Si/SiO2 surface scattering for the SiGe SIMOX device and results in a further improvement in channel mobility. Experimentally veriﬁed improvement in channel mobility of a SiGe SIMOX device over that of an identically processed SIMOX device is 90% at 300 K [7], whereas the maximum improvement in channel mobility of a SiGe bulk device over that of an Si device has been found to be 50% [3, 4]. This large enhancement of channel mobility for the SiGe SIMOX device is believed to be due to improved hole conﬁnement in the buried quantum well of this device. Silicon-on-sapphire (SOS) technology, which integrates both the microwave and the VLSI digital/analogue signal processing functions, is ideally suited for microwave circuits since it has a low dielectric loss substrate, low noise ﬁgure, excellent radiation hardness and reduced punch-through eﬀects. Recent studies of SiGe CMOS on sapphire technology [29, 30] have shown improvements in p-MOSFET mobility and transconductance at 300 and 77 K, compared to Si. Both cut-oﬀ frequency and low-ﬁeld mobility, µeﬀ improve with the integrated Ge dose in the SiGe channel. Table 7.3 compares the performances of several devices while ﬁgure 7.18 shows a comparison of the measured and simulated linear transconductance of a SiGe p-HFET (ﬂat Ge 20%) fabricated in sapphire technology at 300 and 85 K.

SiGeC p-HFETs

257

Table 7.3. Summary of room temperature electrical parameters of SiGe HFETs and Si MOSFETs on SOS. (After Mathew S J et al 1999 IEEE Electron Device Lett. 20 173–5.) Device parameters

Flat Ge 20%

Graded Ge 20%

Flat Ge 15%

Si

VT (V)

−0.77

−0.80

−0.82

−0.97

82.8

80.8

80.6

93.4

sub-VT slope (mV dec−1 ) 2

−1

µeﬀ (cm V

s

−1

)

201

Leﬀ µm Peak

fT L2eﬀ

(GHz) µm

2

Hooge constant (×10−6 ) at VGS − VT = −1 V

177

192

130

1.30

1.25

1.25

1.04

7.8

7.0

7.4

5.0

94

81

129

294

Figure 7.18. Comparison of measured linear transconductance versus 2D simulation using TMA–MEDICI of the ﬂat Ge 20% p-HFET at 300 and 85 K. (After Mathew S J et al 1999 IEEE Electron Device Lett. 20 173–5.)

7.4.

SIGEC P-HFETS

Since the increase in the Ge content leads to a larger strain and reduced thermal stability in the pseudomorphic SiGe ﬁlms, limitations exist in the application of the binary SiGe alloys. By incorporating smallersized C atoms substitutionally to form Si1−x−y Gex Cy , the strain can be compensated, extending the Si-based heterostructures to allow more

258

SiGe heterostructure FETs

Figure 7.19. Room temperature IDS –VGS for epitaxial Si, Si0.8 Ge0.2 SiGe and Si0.793 Ge0.2 C0.007 SiGeC p-HFETs for linear and saturation values of VDS for 10 × 10 µm devices. Inset shows IDS versus VDS for increasing values of VGS –VT . The curves have been normalized for oxide thickness variations between the samples. (After John S et al 1999 Appl. Phys. Lett. 74 847–9.)

ﬂexible device design [31, 32]. The ternary alloys are promising for pchannel HFETs, since the addition of C increases the stability of the material and reduces the amount of process-induced strain relaxation [33, 34]. Figure 7.19 shows the normalized room temperature characteristics of 10 µm gate length Si0.8 Ge0.2 , Si0.793 Ge0.2 C0.007 , and control Si transistors with the same doping. The respective subthreshold slopes are 101, 90 and 75 mV dec−1 for Si0.8 Ge0.2 , Si0.793 Ge0.2 C0.007 and control Si devices. All devices exhibit good saturation and turn-oﬀ characteristics. However, the Si0.793 Ge0.2 C0.007 transistor exhibits a higher drive current at the same eﬀective gate voltage, as shown in the inset. In ﬁgure 7.20, the ﬁeld-eﬀect mobilities for Si0.8 Ge0.2 , Si0.793 Ge0.2 C0.007 epitaxial Si and lightly-doped bulk Czochralski–Si (CZ–Si) p-MOS are plotted at room and liquid nitrogen temperatures. The peak mobility at 300 K is enhanced to 190 cm2 V−1 s−1 for Si0.793 Ge0.2 C0.007 in comparison to 140 cm2 V−1 s−1 for the Si0.8 Ge0.2 devices. The ternary alloy sample

Devices using poly-SiGe

259

Figure 7.20. Linear ﬁeld-eﬀect mobility (µFE ) for 1.3 × 1015 cm−3 doped bulk-Si, 2.3 × 1017 cm−3 doped epitaxial Si/Si0.8 Ge0.2 and Si0.793 Ge0.2 C0.007 SiGeC p-HFETs as a function of VGS –VT for 10 × 10 µm devices at room temperature and 77 K. (After John S et al 1999 Appl. Phys. Lett. 74 847–9.)

shows the highest peak mobility, whereas the mobility for the Si0.8 Ge0.2 devices is only slightly higher than that of epitaxial Si and lower than that of a bulk doped CZ–Si device. It is known that the in-plane hole mobility in compressively strained Si1−x Gex is enhanced due to the lifting of valence band degeneracy and modiﬁcation of the band structure. Although performance enhancement has been demonstrated in partially strain-compensated Si1−x−y Gex Cy channel p-HFETs over Si1−x Gex channels as a result of less process-induced relaxation in the Si1−x−y Gex Cy layer, complete strain compensation of the SiGe layers, however, degrades the performance of p-HFET devices. The incorporation of a controlled amount of C can provide a wider process window for device fabrication. 7.5.

DEVICES USING POLY-SIGE

In bipolar transistors, SiGe is used to form a narrow bandgap base region, while in a ﬁeld-eﬀect device it has been used as a channel material. Polycrystalline silicon (polySi) ﬁnds wide applications in all

260

SiGe heterostructure FETs

types of silicon integrated circuit technology. Poly-Si1−x Gex is a promising alternative to polySi as a gate material due to its process compatibility and favourable electrical properties, such as lower sheet resistance, higher dopant activation rate and tunable work function [35, 36]. While considerable research has been carried out on epitaxial SiGe, relatively less work has been done on polycrystalline SiGe (poly-SiGe) and even less on other group IV polycrystalline materials. Potential applications of polycrystalline SiGe or SiGeC include: • • • •

CMOS—tuning of the work function by 200–300 meV towards midgap and reduced gate depletion due to enhanced dopant activation at low temperature; TFTs—higher mobility and lower thermal budget processing than amorphous or polycrystalline silicon; BiCMOS—lower thermal budget polysilicon emitters and increased gain in wide bandgap polycrystalline SiGeC or SiC emitters; resistors—tuning of temperature coeﬃcient of resistance in polycrystalline SiGe or SiGeC resistors.

7.5.1.

Poly-SiGe gate MOSFETs

Poly-Si0:75 Ge0:25 -gated p-MOS transistors with a very thin gate oxide have been fabricated. In addition to reduced gate-depletion eﬀect (GDE) and reduced boron penetration, an enhancement in performance has been reported [37]. As a p+ -poly-SiGe ﬁlm has a tunable work function; the carrier mobility which is aﬀected by the vertical electric ﬁeld diﬀers from that in the device with a conventional polySi gate [38]. Due its superior hole mobility and smaller work function, which leads to a lower eﬀective ﬁeld in the inversion layer, an improved current drive is obtained for poly-SiGe. The output characteristics for both p+ -polySi and poly-SiGe gate devices with various gate biases are shown in ﬁgure 7.21. For each gate voltage, the drain current of the poly-SiGe gated device is higher than that of the polySi gated device. Given its compatibility with current VLSI fabrication processes, incorporating SiGe into existing CMOS processing should be relatively easy and should lead to higher performance of MOSFET devices [37]. The gate tunnelling currents (hole and electron) in p+ -polySi and poly-SiGe gated p-MOS transistors with ultrathin gate oxides of 25 and 29 ˚ A have been measured by employing the charge-separation measurement techniques [39]. The authors have concluded that the hole direct tunnelling is the dominant gate leakage mechanism under normal operating conditions for p+ -polySi gated p-MOS devices with very thin gate oxide.

Devices using poly-SiGe

261

Figure 7.21. IDS –VDS characteristics for both p+ -polySi and poly-SiGe gated devices with various gate biases. For the same VDS and VGS , the drain current of the poly-SiGe gated device is always higher than that of the polySi gated device. (After Lee W-C et al 1999 IEEE Electron Device Lett. 20 232–4.)

7.5.2.

Poly-SiGe thin-ﬁlm transistors

Thin-ﬁlm transistors (TFTs) ﬁnd wide applications in active matrix liquid crystal displays (AMLCD) and static memory (SRAM) and there has been great interest in the possibility of developing a low-cost, glass-compatible polycrystalline TFT process, which will enable a high-performance ﬂat panel displays with integrated drivers. SiGe is of great promise for achieving this goal, due to its lower processing temperature and thermal budget requirements [40, 41]. TFT processes have several characteristics which make them diﬀerent from the standard Si process. For a glass-compatible technology, all processing is done at or below 600 ◦ C, and deposited gate dielectrics is used. Active layers are also deposited, usually by LPCVD or PECVD. The deposition conditions of the active layer and the related process parameters greatly aﬀect the device performance, as does the quality of the gate dielectrics, which is generally inferior in quality to thermally oxidized dielectrics. To enable the rapid optimization of SiGe TFTs for AMLCD applications, a response surface characterization of the SiGe deposition system has been performed [42]. Controlled nucleation and grain growth have enabled the fabrication of large-grain high-performance TFTs. Ge has been deposited selectively through an oxide mask onto the source/drain

262

SiGe heterostructure FETs

regions. The ﬁlm is then crystallized at low temperature. The Ge and Si react to form SiGe at the interface, which crystallizes ﬁrst, and then grows out laterally, resulting in spatially speciﬁed large-grain polysilicon. This process is called germanium-seeded lateral crystallization. The fabricated poly-SiGe TFTs have shown much higher mobility than comparable polySi TFTs, as indicated in ﬁgure 7.21. A comparison of transfer characteristics of n-MOS and p-MOS TFTS at low and high drain voltages is shown in ﬁgure 7.22.

Figure 7.22. Comparison of poly-SiGe TFT transfer characteristics. (After Subramanian V and Saraswat K C 1998 IEEE Trans. Electron Devices 45 1690–5.)

Vertical FETs 7.6.

263

VERTICAL FETS

With increasing chip size, the delay introduced by metal lines interconnecting the various parts of a chip is rapidly becoming a limiting factor for speed and performance. A solution to this problem is a reduction in chip size, which can be accomplished through the use of vertical integration of active devices. MOSFET channel lengths are being continuously scaled down to improve performance and packing density. Extrapolating the critical device dimensions for silicon ICs to the future, it is anticipated that MOS transistors with gate lengths of about 70 nm will be required to realize the 64 GB DRAM around the year 2010 [43]. However, in the vertical transistor technology, channel length scaling is not limited by the minimum lithographic resolution. It has been shown that the package density of the vertical transistor is doubled [44]. 7.6.1.

Vertical SiGe HFETs

The advances in the growth of device quality SiGe epitaxial layers on silicon, combined with the higher values of hole mobility, have led to an increased interest in heterojunction vertical FETs [45, 46]. In the design of the vertical heterojunction p-MOSFET, the SiGe layer and, more speciﬁcally,

Figure 7.23. Schematic diagram of vertical heterostructure ﬁeld-eﬀect transistor. (After Collaert N and De Meyer K 1999 IEEE Trans. Electron Devices 46 933–9.)

264

SiGe heterostructure FETs

the gate inﬂuence on the eﬀective barrier height seen by the carriers play an important role in the device operation. It consists of a source layer, a graded SiGe source layer, a lightly-doped SiGe source layer, an n-type doped channel region and ﬁnally a p-type doped drain layer (as shown in ﬁgure 7.23). The gate dielectrics consists of an oxide grown on the vertical sidewalls and the gate electrode is an in situ doped p-type polysilicon layer. The basic principle of operation of this novel device is: in the onstate, the barrier is decreased by using the gate action on the lightly-doped source layer. In the case of a p-channel device, a strained-SiGe layer on top of an Si substrate is used to create a barrier for the holes [21]. For the n-channel devices, the barrier for the electrons will be formed by a strainedSi source layer on top of a SiGe buﬀer layer, leading to a band alignment of type II [21]. In that case, SiGe will also be used for the channel and drain layers. Using the Si/SiGe layer stack for both p- and n-MOSFETs, it is possible to include source engineering in the vertical transistor design. This is an important improvement to vertical Si-only devices, which lack the possibility of channel engineering that has pushed their planar counterparts toward the deep submicron regime. Vertical MOSFETs suﬀer from draininduced barrier lowering (DIBL), causing reduction threshold voltage rolloﬀ and an increase in subthreshold slope. By using ultrathin pillars (width 100 nm), the channel region can be fully depleted by surrounding gates, resulting in an improved subthreshold slope and a suppression of shortchannel eﬀects [47, 48]. To reduce the DIBL eﬀect, a material-dependent barrier between source and channel may also be introduced [45, 49]. Enhanced in-plane hole mobility in strained-SiGe alloys, compared to bulk-Si has been employed for the fabrication of planar SiGe-channel pHFETs [5, 14, 50]. The enhancement of hole mobility in a direction normal to the growth plane of the strained-Si1−x Gex and graded SiGe channel has also been found to be eﬀective in the enhancement of the drive current in implanted-channel MOSFETs. As the vertical structures combine the merits of a very short channel and enhanced hole mobility in strained-SiGe layers, the results are very promising in terms of the possibilities oﬀered by the SiGe technology. Indeed, a deep submicron vertical SiGe-channel p-HFET using strained-Si1−x Gex grown using solid phase epitaxy and the standard CMOS process has been reported [46]. The scaling of vertical p-MOSFETs with the source and drain doped with boron during low-temperature epitaxy is limited by the diﬀusion of boron during subsequent side wall gate oxidation. By introducing SiGeC diﬀusion barrier layers, boron diﬀusion from source and drain into the channel region has been suppressed during the gate oxidation. The characteristics of scaled vertical p-MOSFETs down to 25 nm in channel length [51] are shown in ﬁgure 7.24. These devices suﬀer from the onset of punch-through, but the gate can still control the drain current in the linear region.

Noise in p-HFETs

265

Figure 7.24. (a) Output I–V and (b) subthreshold drain current versus gate voltage for devices with L = 25 nm with a gate oxide thickness of 10 nm. (After Yang M et al 1999 IEEE Electron Device Lett. 20 301–3.)

An analytical model for the threshold voltage of the p-SiGe channel vertical MOSFET has demonstrated its unique characteristics in suppressing DIBL in sub-100 nm channel length devices [45]. The dependence of the threshold voltage on Ge concentration, channel length, channel doping and SiGe source doping was evaluated. It was shown that with the introduction of a material-dependent barrier between source and channel, roll-oﬀ in threshold voltage can be substantially reduced. 7.7.

NOISE IN P-HFETS

Low-frequency noise is important in RF and microwave circuit applications, because it is upconverted to phase noise and thus sets a fundamental limit on the spectral purity of high-speed communication systems. Although much work has been done on noise in MOSFETs [52], little attention has

266

SiGe heterostructure FETs

Figure 7.25. Spectral density of the input-referred gate voltage noise for the ﬂat Ge 20% and the Si p-MOSFET in saturation. (After Mathew S J et al 1999 IEEE Electron Device Lett. 20 173–5.)

been given to the noise properties of SiGe p-HFETs [29, 53]. The noise in MOSFETs is generally related to the ﬂuctuations in the inversion layer carrier density due to traps located at the Si–SiO2 interface. SiGe p-HFETs are bandgap-engineered such that the holes conﬁned to the SiGe channel are physically separated from the Si–oxide interface by an Si-cap layer. Intuitively, one would expect lower noise in SiGe p-HFETs because of such a physical separation. However, an examination of the trapping-based noise theory [54] shows that this separation changes only the frequency range over which the noise shows a dependence, but not the magnitude of the noise. Figure 7.25 shows the input referred gate voltage noise for Si/SiGe p-HFETs on SOS and bulk-Si. It is observed that all SiGe p-HFETs consistently show a lower noise than Si p-MOSFETs at all gate biases. The SiGe p-HFETs show a 70% lower noise than the Si p-MOSFETs, due to the enlarged separation between the hole quasi-Fermi level and valence band edge, which results in the sampling of a lower density of traps. Thus, the SiGe p-HFETs should have an intrinsic advantage in microwave circuit applications. Collaert et al [55] have measured the low-frequency noise characteristics for several vertical SiGe-channel HFETs. Figures 7.26(a)– 7.26(d) show the noise spectra measured between 3 Hz and 100 KHz for devices with source top and drain top conﬁgurations at constant drain current. As can be seen from the ﬁgures, the source top conﬁguration exhibits a dominant generation–recombination (g–r) noise behaviour while the drain top measurements show 1/f γ -type noise behaviour with γ between 0.9 and 1.5.

Summary

267

Figure 7.26. Low-frequency noise characteristics for (a) an Si0.90 Ge0.10 device; (b) an Si0.80 Ge0.20 device, Nsub = 5 × 1017 cm−3 ; (c) an Si0.90 Ge0.10 device; and (d) a bulk-Si device, Nsub = 1 × 1018 cm−3 . (After Collaert N et al 1999 Proc. ESSDERC pp 308–11.)

7.8.

SUMMARY

In this chapter, the electrical operation and modelling of the SiGe pHFET are presented to provide the device designer with guidelines as to epitaxial layer structure and placement. A range of parameter space has been explored using device simulation to determine the charge distribution within the device under various gate bias conditions. The key design issues for SiGe HFETs have been addressed in detail. The selection of the gate material plays a dominant role, especially for designs with threshold voltages in the range of −0.6 V where the use of n+ -polySi is preferable over p+ -polySi. With a graded Ge proﬁle, a higher

268

SiGe heterostructure FETs

valence band discontinuity can be obtained at the top of the SiGe channel leading to an increase in transconductance for a given integrated Ge dose. It has been shown that for maximum utilization of the strained-Si1−x Gex quantum well, the p-HFET should have the following characteristics: (i) a thin Si-cap layer,; (ii) a high Ge mole fraction for a large 2DHG population in the quantum well; (iii) an n+ -polySi gate to promote buried channel operation for lowvoltage applications; and (iv) a p+ -δ-doping below the SiGe channel to enhance subthreshold properties of the device. A number of possibilities have been shown to enhance performance of SiGe HFETs. From a design point of view, the SiGe p-HFET on an insulating substrate oﬀers better hole conﬁnement in the quantum well. The incorporation of a controlled amount of carbon in a partially strain-compensated SiGeC channel p-HFET can provide a wider process window. A vertical SiGe HFET oﬀers higher packing density, lower DIBL and substrate bias eﬀect, more ﬂexible channel engineering and a simpler fabrication process. BIBLIOGRAPHY [1] Davari B 1996 CMOS technology scaling, 0.1 µm and beyond IEEE IEDM Tech. Dig. pp 555–8 [2] Bouillon P, Skotnicki T, Kelaidis C, Gwoziecki R, Dollfus P, Regolini J-L, Sagnes I and Bodnar S 1996 Search for the optimal channel architecture for 0.18/0.12 µm bulk CMOS experimental study IEEE IEDM Tech. Dig. pp 559–62 [3] Kesan V P, Subbanna S, Restle P J, Tejwani M J, Aitken J M, Iyer S S and Ott J A 1991 High performance 0.25 µm p-MOSFETs with silicon– germanium channels for 300 K and 77 K operation IEEE IEDM Tech. Dig. pp 25–8 [4] Nayak D K, Woo J C S, Park J S, Wang K L and MacWilliams K P 1991 Enhancement-mode quantum-well Gex Si1−x PMOS IEEE Electron Device Lett. 12 154–6 [5] Verdonckt-Vandebroek S, Crabbe F, Meyerson B S, Harame D L, Restle P J, Stork J M C and Johnson J B 1994 SiGe-channel heterojunction pMOSFETs IEEE Trans. Electron Devices 41 90–102 [6] Li P W, Yang E S, Yang Y F, Chu J O and Meyerson B S 1994 SiGe pMOSFETs with gate oxide fabricated by microwave electron cyclotron resonance plasma processing IEEE Electron Device Lett. 15 402–5 [7] Nayak D K, Woo J C S, Yabiku G K, MacWilliams K P, Park J S and Wang K L 1993 High mobility GeSi PMOS on SIMOX IEEE Electron Device Lett. 14 520–2

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[8] Murakami E, Nakagawa K, Nishida A and Miyao M 1994 Fabrication of strain-controlled SiGe/Ge MODFET with ultrahigh hole mobility IEEE Trans. Electron Devices 41 857–61 [9] Liou K K, Mei P, Gennser U and Yang E S 1991 Eﬀects of Ge concentration on SiGe oxidation behaviour Appl. Phys. Lett. 59 1200–2 [10] Eugene J, LeGoues F K, Kesan V P, Iyer S S and d’Heurle F M 1991 Diﬀusion versus oxidation rates in silicon-germanium alloys Appl. Phys. Lett. 59 78–80 [11] Iyer S S, Solomon P M, Kesan V P, Bright A A, Freeouf J L, Nguyen T N and Warren A C 1991 A gate-quality dielectric system for SiGe metal–oxide semiconductor devices IEEE Electron Device Lett. 12 246–8 [12] Mukhopadhyay M, Ray S K, Nayak D K and Maiti C K 1996 Ultrathin oxides using N2 O on strained Si1−x Gex Appl. Phys. Lett. 68 1262–4 [13] Li P W, Liou H K, Yang E S, Iyer S S, Smith III T P and Lu Z 1992 Formation of stoichiometric SiGe oxide by electron cyclotron resonance plasma Appl. Phys. Lett. 60 3265–7 [14] Verdonckt-Vandebroek S, Crabbe E F, Meyerson B S, Harame D L, Restle P J, Stork J M C, Meydanis A C, Stanis C L, Bright A A, Kroesen G M W and Warren A C 1991 High-mobility modulation-doped grades SiGe-channel p-MOSFETs IEEE Electron Device Lett. 12 447–9 [15] Chang W H, Davari B, Wordeman M R, Taur Y, Hsu C C H and Rodriguez M D 1992 A high-performance 0.25 µm CMOS technology: I—design and characterization IEEE Trans. Electron Devices 39 959–66 [16] Davari B, Chang W H, Petrillo K, Wong C Y, Moy D, Taur Y, Wordeman M R, Sun J Y C, Hsu C C H and Polcari M R 1992 A highperformance 0.25 µm CMOS technology: II—technology IEEE Trans. Electron Devices 39 967–75 [17] Bhaumik K and Shacham-Diamand Y 1993 Semi-empirical model for charge control in SiGe quantum well MOS structures Solid-State Electron. 36 961–8 [18] Hinckley J M, Sankaran V and Singh J 1989 Charged carrier transport in Si1−x Gex pseudomorphic alloys matched to Si-strain-related transport improvements Appl. Phys. Lett. 55 2008–10 [19] Bera L K, Ray S K, Nayak D K, Usami N, Shiraki Y and Maiti C K 1999 Gas source molecular beam epitaxy grown strained-Si ﬁlms on step-graded relaxed Si1−x Gex for MOS applications J. Electron. Mater. 28 98–104 [20] Garone P M, Venkataraman V and Sturm J C 1991 Mobility enhancement and quantum mechanical modelling in Gex Si1−x channel MOSFETs from 90 to 300 K IEEE IEDM Tech. Dig. pp 29–32 [21] People R 1986 Physics and applications of Gex Si1−x /Si strained layer heterostructures IEEE J. Quantum Electron. 22 1696–710 [22] Hinckley J M and Singh J 1990 Hole transport theory in pseudomorphic Si1−x Gex alloys grown on Si(100) substrates Phys. Rev. B 41 2912–26 [23] Manku T, McGregor J M, Nathan A, Roulston D J, Noel J-P and Houghton D C 1993 Drift hole mobility in strained and unstrained doped Si1−x Gex alloys IEEE Trans. Electron Devices 40 1990–6 [24] Lombardi C, Manzini S, Saporito A and Vanzi M 1988 A physically based mobility model for numerical simulation of nonplanar devices IEEE Trans.

270

SiGe heterostructure FETs

Comput.-Aided Des. 7 1164–71 [25] Voinigescu S P, Rabkinkin P B, Salama C A T and Blakey P A 1995 2D numerical investigation of the impact of compositional grading on the performance of submicrometre Si–SiGe MOSFETs IEEE Trans. Electron Devices 42 1039–46 [26] Yoshimi M, Hazama H, Takahashi M, Kambayashi S, Wada T, Kato K and Tango H 1989 Two-dimensional simulation and measurement of high performance MOSFETs made on a very thin SOI ﬁlm IEEE Trans. Electron Devices 36 493–503 [27] Kamgar A, Hillenius S J, Cong H I L, Field R L, Lindenberger W S, Celler G K, Trimble L E and Sheng T T 1992 Ultra-fast (0.5 µm) CMOS circuits in fully depleted SOI ﬁlms IEEE Trans. Electron Devices 39 640–7 [28] Garone P M, Venkataraman V and Sturm J C 1991 Hole conﬁnement in MOS-gated Gex Si1−x /Si heterostructures IEEE Electron Device Lett. 12 230–2 [29] Mathew S J, Niu G, Dubbelday W B, Cressler J D, Ott J A, Chu J O, Mooney P M, Kavanagh K L, Meyerson B S and Lagnado I 1999 Hole conﬁnement and low-frequency noise in SiGe pFETs on silicon-onsapphire IEEE Electron Device Lett. 20 173–5 [30] Mathew S J, Ansley W E, Dubbelday W B, Cressler J D, Ott J A, Chu J O, Kavanagh K L, Mooney P M, Meyerson B S and Lagnado I 1997 Eﬀect of Ge proﬁle on the frequency response of a SiGe pFET on sapphire technology IEEE 1997 Device Res. Conf. Dig. pp 130–1 [31] Eberl K, Iyer S S, Zollner S, Tsang J C and LeGoues F K 1992 Growth and strain compensation eﬀects in the ternary Si1−x−y Gex Cy alloy system Appl. Phys. Lett. 60 3033–5 [32] Regolini J L, Gisbert F, Dolino G and Boucaud P 1993 Growth and characterization of strain compensated Si1−x−y Gex Cy epitaxial layers Mater. Lett. 18 57–60 [33] Ray S K, John S, Oswal S and Banerjee S K 1996 Novel SiGeC channel heterojunction pMOSFET IEEE IEDM Tech. Dig. pp 261–4 [34] John S, Ray S K, Quinones E, Oswal S K and Banerjee S K 1999 Heterostructure p-channel metal–oxide semiconductor transistor utilizing an Si1−x−y Gex Cy channel Appl. Phys. Lett. 74 847–9 [35] King T J, McVittie J P, Saraswat K C and Pﬁester J R 1994 Electrical properties of heavily-doped polycrystalline silicon–germanium ﬁlms IEEE Trans. Electron Devices 41 228–32 [36] King T J, Pfriester J R, Scott J D, McVittie J P and Saraswat K C 1990 A polycrystalline SiGe gate CMOS technology IEEE IEDM Tech. Dig. pp 253–6 [37] Lee W C, Watson B, King T J and Hu C 1999 Enhancement of PMOS device performance with poly-SiGe gate IEEE Electron Device Lett. 20 232–4 [38] Hellberg P E, Zhang S-L and Petersson C S 1997 Work function of borondoped polycrystalline Six Ge1−x ﬁlms IEEE Electron Device Lett. 18 456–8 [39] Lee W-C, King T-J and Hu C 1999 Evidence of hole direct tunnelling through ultrathin gate oxide using p poly-SiGe gate IEEE Electron Device Lett. 20 268–70 [40] Wu I-W 1994 Polycrystalline silicon thin-ﬁlm transistors for liquid crystal

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displays Solid-State Phenomena 37–38 553–64 [41] Jurichich S, King T J, Saraswat K and Mehlhaﬀ J 1994 Low thermal budget polycrystalline silicon–germanium thin-ﬁlm transistors fabricated by rapid thermal annealing Japan. J. Appl. Phys. 33 L1139–41 [42] Subramanian V and Saraswat K C 1998 Optimization of silicon-germanium TFTs through the control of amorphous precursor characteristics IEEE Trans. Electron Devices 45 1690–5 [43] National Technology Roadmap for Semiconductors 1997 (San Jose, CA: Semiconductor Industry Association) [44] Behammer D, Zeuner M, Hackbarth T, Herzog J, Schafer M and Grabolla T 1998 Comparison of lateral and vertical Si-MOSFETs with ultra short channels Thin Solid Films 336 313–8 [45] Collaert N and De Meyer K 1999 Modelling the short-channel threshold voltage of a novel vertical heterojunction pMOSFET IEEE Trans. Electron Devices 46 933–9 [46] Liu K C, Ray S K, Oswal S K and Banerjee S K 1998 A deep submicron Si1−x Gex /Si vertical PMOSFET fabricated by Ge ion implantation IEEE Electron Device Lett. 19 13–15 [47] Auth C and Plummer J 1996 Vertical, fully depleted, surrounding gate MOSFETs on sub-0.1 µm thick silicon pillars Proc. 54th Device Res. Conf. pp 108–9 [48] Auth C and Plummer J 1997 Scaling theory for cylindrical, fully depleted, surrounding-gate MOSFETs IEEE Electron Device Lett. 18 74–6 [49] De Meyer K, Caymax M, Collaert N, Loo R and Verheyen P 1998 The vertical heterojunction MOSFET Thin Solid Films 336 299–305 [50] Nayak D K, Woo J C S, Park J S, Wang K L and MacWilliams K P 1993 High-mobility p-channel metal–oxide semiconductor ﬁeld-eﬀect transistor on strained-Si Appl. Phys. Lett. 62 2853–5 [51] Yang M, Chang C-L, Carroll M and Sturm J C 1999 25 nm p-channel vertical MOSFETs with SiGeC source-drains IEEE Electron Device Lett. 20 301–3 [52] Chang J, Abidi A A and Viswanathan C R 1994 Flicker noise in CMOS transistors from subthreshold to strong inversion at various temperatures IEEE Trans. Electron Devices 41 1965–71 [53] Babcock J A, Schroder D K and Tseng Y C 1998 Low-frequency noise in near-fully-depleted TFSOI MOSFETs IEEE Electron Device Lett. 19 40–3 [54] Christensson S, Lundstrom I and Svensson C 1968 Low-frequency noise in MOS transistors—part I Solid State Electron. 11 797–812 [55] Collaert N, Verheyen P and De Meyer K 1999 Low-frequency noise characterization of submicron vertical heterojunction pMOSFETs Proc. ESSDERC’99 pp 308–11

Chapter 8 METALLIZATION AND HETEROSTRUCTURE SCHOTTKY DIODES

Semiconductor–semiconductor and metal–semiconductor interfaces play a crucial role in modern electronic and optoelectronic devices. SiGe heterostructure materials and devices are expected to play an important role due to their compatibility with Si-processing technology. Microelectronic circuit fabrication requires metallization and the study of the metal/SiGe interface is therefore very important. For applications of poly-SiGe as gate material, the interaction of SiGe alloys with noble/refractory metals should also be investigated, as both refractory and noble metal-silicides are widely used for ohmic contacts, Schottky barrier diodes, diﬀusion barriers, low resistivity gates and interconnects. As new devices and structures are being contemplated using group IV alloy ﬁlms, a good control of the metal/semiconductor interface, low or high barriers, are required to improve the device performance. There are two types of metal–semiconductor contacts, one is ohmic and the other is Schottky. Schottky contacts are needed for rectiﬁcation of electrical signals, mixing of microwave signals and optical detection. Silicide/Si1−x Gex Schottky diodes have also been proposed for detection of far-infrared radiation, which will be discussed in chapter 9. In table 8.1, important material properties of commonly used metals for microelectronic device fabrication are presented. During the last few years, several research groups have studied the electrical properties and chemical phase formation of metal/group IV alloy layers. Two approaches to the formation of ohmic contacts with SiGe and other alloy layers have been proposed [1]. The ﬁrst approach involves adding Ge and Si to a thin Al ﬁlm to avoid known substrate dissolution and spiking problems. An Al ﬁlm (3000 ˚ A) is deposited over the strained layer, followed by the deposition of thin layers of Si (20 ˚ A) and Ge (60 ˚ A). 272

Metallization and heterostructure Schottky diodes

273

Table 8.1. Material properties of metals commonly used in microelectronic applications. Property

Al

Au

Pt

Ni

Cr

Molecular weight (amu)

26.98

196.96

195.09

58.69

52.02

Density (g cm−3 )

2.699

19.288

21.452

8.903

7.19

Melting point ( C)

659.4 1.66

1768 does not oxidize

1454

Oxidation potential (V)

1062.2 does not oxidize

1875 does not oxidize

4.25

5.1

5.7

5.1

4.5

0.69

0.79

0.9

0.61

0.61

0.38

0.25

0.51

0.50

0.48

0.59

0.49

◦

Work function at vacuum (eV) Schottky barrier to n-Si (eV) Schottky barrier to p-Si (eV) Schottky barrier to n-Ge (eV) Schottky barrier to p-Ge (eV)

0.25

0.3

A 350 ◦ C anneal for 1 h was used to alloy the capping Si and Ge layers into the Al. Contact resistivity measurements between room temperature and 400 ◦ C demonstrated the stability of the contacts. However, the room temperature contact resistivity of 0.01 Ω cm−2 was considered too high for device applications. The second approach to contact formation involved deposition of a layer of Pd:Si (3:1, 600 ˚ A) on the SiGe, followed by a layer of pure Ge (1000 ˚ A). The contacts were annealed for 1 h at 350 ◦ C. During annealing the Pd3 Si phase was formed. Concurrently, the surface Ge layer diﬀused through the silicide and grew epitaxially on the underlying SiGe layer. Contact resistances for these ﬁlms were typically 5 × 10−4 Ω cm−2 at room temperature. Liou et al [2] reported the interfacial reactions of Pt and Pd with epitaxial Si1−x Gex alloys and the eﬀects of these reactions on Schottky barrier height. They reported that the barrier heights of Pd and Pt on n-Si0.8 Ge0.2 were the same, about 0.68 eV, and were not modiﬁed signiﬁcantly when annealed at a temperature below 550 ◦ C. This value is close to that previously reported by Buxbaum et al [3] for Pd on n-Si1−x Gex ﬁlms. Kanaya et al [4] reported the Schottky barrier height of Pd(Pt)/p-SiGe contacts for infrared detection. It was shown that the barrier height

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Metallization and heterostructure Schottky diodes

decreased with increasing Ge concentration, and that the barrier height of a relaxed ﬁlm was higher than that of a strained-Si1−x Gex ﬁlm. Hong and Mayer [5] studied the Pt/Si1−x Gex system and found a similar behaviour except for the formation of germanide. Thompson et al [6] studied the Ni/Si1−x Gex interfacial reaction and found that Ni was the dominant diﬀusion species below 400 ◦ C and that layers of Ni2 (Si1−x Gex ), Ni(Si1−x Gex ) and NiSi formed in sequence. Above 400 ◦ C, homogenization between NiSi and Ni(Si1−x Gex ) occurs due to interdiﬀusion of Si and Ge. Aubry et al [7] studied the Si1−x Gex /W metal–semiconductor Schottky junction rather than a silicide junction. The authors reported the eﬀects of composition and thickness on the Schottky barrier height of W/p-Si1−x Gex relaxed ﬁlms and showed that the barrier height decreased with the increasing Ge fraction and followed the rate of strain relaxation. Thomas et al [8] investigated the Ti/Si1−x Gex contacts with contact resistance measurements and reported that Si and Ge were the dominant moving species during the reaction. The resistance of contacts was stable and low due to the formation of TiSi2 , Ti(Si1−x Gex )2 and TiGe2 after annealing at 650 ◦ C for 1 h. The above studies revealed that during the metal–Si1−x Gex reaction, Pd and Pt preferentially react with Si, resulting in Ge segregation [2, 9]. These create defects that pin the Fermi level near the midgap leading to a high Schottky barrier height [2]. To avoid Ge segregation, a silicon sacriﬁcial layer was used on top of the SiGe ﬁlm [10]. The important applications of silicide junctions are in IR detectors and will be discussed in chapter 9. In this chapter, the formation and characterization of silicides (using Pt, Pd and Ti on SiGe, SiGeC, Si and strained-Si) using various analytical tools, such as x-ray diﬀraction (XRD), Rutherford backscattering (RBS) and Auger electron spectroscopy, will be discussed. We describe Schottky barrier diodes (SBDs) using Ti, Pt and Pd on p-type SiGe, SiGeC, strainedSi ﬁlms and Si. Experimental results on barrier heights, the ideality factor and energy distribution of the interface state density for various diodes and simulation results using SEMICAD [11] on forward current–voltage characteristics of Schottky diodes are presented. 8.1.

DEPOSITION OF METAL FILMS

One of the various techniques used for metal thin-ﬁlm deposition is ultrahigh vacuum (UHV) electron beam deposition. The schematic diagram of an electron beam evaporation system used for deposition of metals is shown in ﬁgure 8.1. The deposition system consists of a single electron gun (typically 2 kW) and several crucibles, capable of evaporating diﬀerent materials sequentially. A base pressure of about 1 × 10−11 Torr is achieved in the chamber with the help of three kinds of vacuum pumps, e.g.,

Deposition of metal ﬁlms

275

Figure 8.1. Schematic diagram of an e-beam evaporation system.

vac-sorb, ion and titanium sublimation pumps. As there are no oil-based vacuum pumps (rotary and diﬀusion) in the system, the UHV e-beam is free from hydrocarbon contaminations. The vacuum chamber consists of a rotating substrate holder, a crystal monitor for monitoring the deposition rate and thickness of the ﬁlm, a quartz-lamp radiation heater with a heating control unit to maintain the substrate temperature up to 300 ◦ C and an ion gauge to monitor the pressure. The whole system is separated into upper and lower chambers by an isolation valve. The lower chamber houses a series of ion pumps and a liquid nitrogen cryo panel and is maintained at a vacuum of 10−6 Torr or greater by continuous operation of the ion pumps. In a typical deposition process, the upper chamber was vented by passing liquid nitrogen, followed by loading of the pre-cleaned substrates in the chamber. A suﬃcient amount of high-purity source materials in the form of small pellets was put into the crucibles and the electron gun ﬁlament was aligned to it. Initial evacuation of the chamber was carried out by vac-sorb pumps from atmospheric pressure to a minimum

276

Metallization and heterostructure Schottky diodes

pressure of 10 mTorr. Finally, pumping to a pressure of 10−9 Torr was achieved by the combination of sputter ion and titanium sublimation pumps. After attaining the desired base vacuum, deposition was initiated by evaporating metal by applying power to the electron gun (e-gun) from its control unit. The evaporation rate was controlled by changing the ﬁlament current in the e-gun. Thin ﬁlms of Ti, Pt and Pd of required thicknesses were deposited on strained-Si1−x Gex , partially strained compensated Si1−x−y Gex Cy , strained-Si and Si at the desired pressure level. 8.2.

FABRICATION OF SCHOTTKY DIODES

In the fabrication of Schottky diodes, surface preparation for metal deposition is very important. In most cases, the departure of the ideality factor of the diodes from unity is due to the presence of an interfacial layer between the metal and the semiconductor [12, 13]. Another reason may be the existence of a laterally varying potential barrier height, caused by a nonuniform interface of the heterostructures [14]. The nonidealities are mostly due to the states associated with the defects near the surface of the semiconductor. These defects act as recombination centres giving rise to excess current which causes deviation from the ideal thermionic emission behaviour at low voltage and low temperature. The growth temperatures of strained-Si1−x Gex and partially strain-compensated Si1−x−y Gex Cy samples are typically around 600 ◦ C. In order to avoid strain relaxation, the silicidation temperature should not exceed the ﬁlm growth temperature. 8.3.

SILICIDATION OF GROUP IV ALLOY FILMS

More than half of the elements in the periodic table react with silicon to form one or more intermetallic compounds (silicides). In Si technology, uniform and stable contacts are achieved by reacting metal ﬁlms with Si until the most Si-rich silicides are formed. These silicides not only oﬀer a choice in electrical barrier heights but also serve as protective layers against oxidation. Al is commonly used as the ohmic contact metal in Si technology. The solid solubility of Si at 525 ◦ C is 1.5% and Si molecules from the substrate dissolve into Al to satisfy its solubility. Though Al and Al–Si have been successfully used in Si devices, they do not make good contacts to group IV alloy ﬁlms. The choice of metals for ohmic contacts should satisfy several requirements. Firstly, the composition of the unreacted alloys must remain unchanged after contact reactions. Secondly, a single compound, not a mixture of compounds (e.g., silicides and germanides), should be in contact with the alloy ﬁlms. Thirdly, the consumption of alloy ﬁlms during the reaction must be small since the thicknesses of the strained layers are limited by the critical thickness.

Silicidation of group IV alloy ﬁlms

277

The metallization of SiGe and other group IV alloys is complicated compared to that of bulk-Si. In a metal–SiGe reaction, metals react preferentially with one component of the alloy, leading to a compositional change in the unreacted alloy. The compositional change results from the formation of a ternary compound within a narrow range of homogeneity. Ternary metal–SiGe phase diagrams are also required to predict the ﬁnal phases of metal/SiGeC ternary reactions. In a ternary reaction, the identity of moving species is very important in determining the elemental distribution. For example, in a refractory– noble metal alloy, a reaction (with Si) produces a noble metal silicide inner layer and a mixture of noble and refractory silicide outer layer. However, no layered phase separation has been observed in refractory–refractory metal alloy/Si reactions. This has been attributed to the diﬀerent moving species involved in the reactions. Noble metals are known to be highly mobile in silicides at low temperature, while Si is the dominant moving species during reactions with refractory metals. Therefore, in a refractory–noble metal/Si reaction, the noble metal moves ﬁrst to react with Si leaving behind a metallic alloy enriched with the refractory component. At high temperature, Si atoms from the substrate move to react with the metallic alloy to form a mixture of silicides. On the other hand, layered phase separation is absent in the refractory–refractory/Si reactions since Si is the only moving species in the entire temperature range. In the light of the above arguments, the composition of SiGe alloys would remain unchanged if a mobile species was chosen as the contact material or the transport of Ge and Si is similar during the reaction with the refractory metal. It has been reported from the kinetic studies of Ti/SiGe systems that Si and Ge are the dominant moving species during thermal reactions. Resistance of the resulting silicide formed at about 650 ◦ C is stable and low due to the formation of C54 of TiSi2 , along with the Ti(SiGe)2 and TiGe2 phases [8]. Strain relaxation has also been observed during the thermal reaction between Ti and Si1−x−y Gex Cy [15]. Carbon is found to inhibit the strain relaxation process as well as to delay the formation of the C54 phase of TiSi2 . Upon complete silicidation, a decrease of Ge concentration in silicide–germanide/epilayer and an accumulation of C atoms at the interface have been found. To avoid such complexities associated with the thermal reactions between metal and group IV alloy ﬁlms, the use of a thin Si sacriﬁcial layer on top of the strained SiGe or SiGeC layer is common [10]. For Schottky contacts, the general requirement is to adjust the junction parameters, such as barrier height and ideality factor, and to control their reproducibility and stability. Thermal annealing inﬂuences the interface and pinning position of the Fermi level which in turn aﬀects the barrier height of the Schottky junctions [16]. For the Ti–Si system, the Fermi level pins at the midgap region. But incorporation of Ge in Si changes

278

Metallization and heterostructure Schottky diodes

the pinning position of the Fermi level [7]. In Si, reproducible rectifying and low resistance ohmic contacts can be achieved by choosing appropriate transition metals with various Schottky barrier heights and by doping the semiconductor with the desired level. Transition metals react with Si at low temperature so that no liquid phase forms. As a result, uniform silicide layers with reproducible compositions at the silicide/Si interface are formed. The electrical properties of Schottky junctions require the understanding of chemical reactions at the metal–semiconductor interface. In the following, we discuss the formation and characterization of silicides of various group IV alloy ﬁlms with Ti, Pt and Pd.

8.4.

SILICIDATION WITH TITANIUM

Refractory metal silicides, such as TiSi2 , WSi2 , TaSi2 and MoSi2 , have attracted much attention in microelectronic devices due to their low resistivity and high-temperature stability, which are required for VLSI/ULSI interconnects. Among various refractory metal silicides, TiSi2 possesses the lowest resistivity (∼12.4 µΩ cm−1 ) [17], high-temperature stability and excellent compatibility with Si-processing technology, and is widely used for submicron CMOS contacts. Titanium disilicide (TiSi2 ) is a polymorphic material which is formed by thin-ﬁlm reactions between Ti and 100 Si, polySi or amorphous silicon. TiSi2 has two diﬀerent structures: the base-centred orthorhombic C49 structure which forms in the temperature range 450–650 ◦ C and the facecentred orthorhombic C54 structure which forms above 650 ◦ C. The C49 TiSi2 is a metastable phase [18] while C54 is the stable phase with lower resistivity than the C49 phase. But the transformation of C49 TiSi2 to C54 TiSi2 is dependent on the doping level and the thicknesses of the ﬁlm [19]. Both the crystal structures exhibit similar arrangements of atoms in the atomic planes with a hexagonal array of Si atoms around the centre, but the unit cell of each phase shows a diﬀerent stacking arrangement. The C54 phase exhibits lower Schottky barrier heights on both p- and n-type silicon as compared to the C49 phase [20]. The reaction mechanism for the formation of C54 TiSi2 is as follows. First, the Ti layer reacts with crystalline silicon producing an amorphous TiSix phase at a temperature ranging from 400–500 ◦ C. With further heating, the amorphous phase, together with the silicon and Ti, forms C49 TiSi2 between 500–700 ◦ C which eventually transforms into C54 at a temperature above 700 ◦ C [21]. The determination of the chemical phase formation during annealing requires in situ characterization tools, while the ﬁnal phase formation is generally studied ex situ using XPS.

Silicidation with titanium 8.4.1.

279

Rutherford backscattering characterization

Rutherford backscattering (RBS) analysis is carried out to estimate the composition and thickness of the deposited ﬁlms. The advantages of RBS are the following: (i) speed; (ii) ability to perceive depth distribution of atomic species below the surface; (iii) the quantitative nature of the results and the technique is nondestructive. The 1–2 MeV He+2 beam is normally used for RBS and channelling measurements. The random incident backscattering spectra of Ti on Si samples annealed at 600 ◦ C for 20 min is shown in ﬁgure 8.2 with a 2.551 MeV

Figure 8.2. The 2.551 MeV 4 He++ backscattering spectra of the TiSi/Si sample annealed at 600 ◦ C for 20 min: (· · · · · ·) experimental and (——) simulation.

280

Metallization and heterostructure Schottky diodes

Figure 8.3. The 2.551 MeV 4 He++ backscattering spectra of the TiSi/Si0.81 Ge0.19 sample annealed at 600 ◦ C for 20 min: (· · · · · ·) experimental and (——) simulation. 4

He+2 ion beam. The scattered He+2 from the TiSi2 layer appears at higher energies (channel nos 576–541) while those from the Si substrate appear at lower energies (channel nos 445–100). Computer simulation of the backscattered spectra (using the GISA-3.95 program) is usually done to obtain the thickness and composition of diﬀerent layers. Figure 8.3 shows the RBS spectrum for a Ti/SiGe sample annealed at 600 ◦ C. It is evident from ﬁgure 8.3 that the scattered He+2 from Ge appears at a higher energy (channel nos 643–591) and the scattered atoms from Ti and Si appear at relatively lower energies (channel nos 576–543 and 445–200, respectively). From the simulation, it is found that the total Ti signal is contributed partly from the TiSi layer and a part from the unreacted Ti. Similarly, the Si fraction is contributed partly from the TiSi layer and partly from the SiGe epitaxial layer as well as from the Si substrate.

Silicidation with titanium

281

Figure 8.4. The 2.551 MeV 4 He++ backscattering spectra of the TiSi/Si0.79 Ge0.20 C0.01 sample (with Si-cap) annealed at 600 ◦ C for 20 min: (· · · · · ·) experimental and (——) simulation.

RBS spectra of Ti–Si–Si0.79 Ge0.20 C0.01 and Ti–Si0.79 Ge0.20 C0.01 samples (annealed at 600 ◦ C for 30 min) are shown in ﬁgures 8.4 and 8.5, respectively. From the simulation, it is found that the Ti peak is contributed by the unreacted Ti and the TiSi layer. Similarly, the Si edge comes from both the TiSi layer and Si1−x−y Gex Cy (x = 0.2, y = 0.01) epitaxial layer and also from the Si substrate. For all silicide samples, the Ge peak occurs at a higher energy compared to those of Ti and Si. Generally, the Ge peak occurs in the channel region of 645–600 and the Ti peak occurs in the channel range of 576–550 while Si shows a peak around the channel no 445 and below.

282

Metallization and heterostructure Schottky diodes

Figure 8.5. The 2.551 MeV 4 He++ backscattering spectra of the TiSi/Si0.79 Ge0.20 C0.01 sample (without Si-cap) annealed at 600 ◦ C for 20 min: (· · · · · ·) experimental and (——) simulation.

8.4.2.

Auger electron spectroscopy characterization

In Auger electron spectroscopy (AES), a focused beam of electrons in the energy range 2–20 keV irradiates the sample. Atoms up to a depth of 1 µm are ionized in an inner core level, e.g., the K level, and subsequently de-excited by an electron falling from a higher level L1 , with the balance energy removing a third electron from level L3 . The electron emitted with an energy EA is given by EA = EK (Z) − EL1 (Z) − EL2 (Z + ∆) − ξ

(8.1)

where Z is the atomic number of the atom and ξ is the work function of the surface. The third term on the right-hand side of equation (8.1) has an extra component ∆ which is included to take account of the fact

Silicidation with titanium

283

that the atom is in a charged state when the ﬁnal electron is ejected. Experimentally, ∆ is found to have a value between 12 and 32 . In sputter depth proﬁling analysis of thin ﬁlms, an ion beam is used to etch the surface at rates up to 2 µm h−1 . For AES depth proﬁles, the electron beam is placed in the middle of the ion beam crater and, if the system alignment is suitable, the crater size may be limited to 100 µm or less. If a monoenergetic argon ion of current density Ji is used to sputter a target with a sputtering yield of S atoms per ion, the rate of removal is given by Ji SM dz = (8.2) dt qρNA na where M is molecular weight of the material with na atoms per molecule, q is electronic charge, ρ is density and NA is Avogadro’s number. In the above equation, dz/dt is the sputter rate. Thus, for a given material, the removal rate may be determined if Ji and S are known. Figure 8.6 shows typical AES depth proﬁles for Ti, Si and Ge of the A annealed at 600 ◦ C Ti/Si/Si1−x Gex sample having a Ti thickness of 700 ˚ for 20 min. The spot size of the beam was 0.5 µm and the etch rate for proﬁling was 5 ˚ A min−1 . As seen from the depth proﬁle, about 600 ˚ A of Ti remains unreacted and only 100 ˚ A of Ti takes part in silicide formation. It is clear from the proﬁle that TiSi formation is observed up to a depth of about 100 ˚ A below the interface. An accumulation of Ge atoms is also observed below the interfacial region. It is desirable to consume the sacriﬁcial Si-cap layer completely by Ti to obtain a pure TiSi/Si1−x Gex interface.

Figure 8.6. AES depth proﬁles of Ti, Si and Ge for the TiSi/Si0.81 Ge0.19 sample annealed at 600 ◦ C for 20 min.

284 8.4.3.

Metallization and heterostructure Schottky diodes Sheet resistivity

The eﬀects of the alloy composition on the annealing temperature and the electrical resistivities of C54 titanium germano–silicide formed during the Ti/Si1−x Gex (x = 0.0, 0.3, 0.4, 0.7, 1) solid-state reaction have been investigated [22]. The resistivities of C54 Ti(Si1−x Gex )2 were measured to be in the range of 15–20 µΩ cm−1 . The electrical resistivities of alloys are inﬂuenced by the diﬀerence of atomic size, atomic disorder, strain and band structure eﬀects. From electrical measurement, the instability of titanium germano–silicide is manifested by the increase in the resistance with the annealing temperature. The increase has been attributed to both the segregation of Si1−x Gex and the agglomeration and spheroidization of the germanide and germano–silicide and are correlated with the phase transformation. The sheet resistances fell drastically (see ﬁgure 8.7) at 600, 650, 650 and 700 ◦ C in the annealed Ti/Ge, Ti/Si0.3 Ge0.7 , Ti/Si0.6 Ge0.4 and Ti/Si0.7 Ge0.3 samples, respectively. The lowest electrical resistivities which appeared for smooth thin ﬁlms of C54 Ti(Si1−x Gex )2 were found to be 20, 20, 17 and 15 µΩ cm−1 for the 800 ◦ C annealed Ti/Si0.7 Ge0.3 , Ti/Si0.6 Ge0.4 , Ti/Si0.3 Ge0.7 and Ti/Ge samples, respectively. The values of x were estimated to be 0.19, 0.28, 0.55 and 0.98, respectively, by EDS analysis, as shown in ﬁgure 8.8.

Figure 8.7. Sheet resistance versus annealing temperature curves for the Ti/Si1−x Gex and Ti/Ge samples. (After Lai J B and Chen L J 1999 J. Appl. Phys. 86 1340–5.)

Silicidation using Pt and Pd

285

Figure 8.8. The lowest electrical resistivity versus concentration of Ge data in Ti(Si1−x Gex )2 . (After Lai J B and Chen L J 1999 J. Appl. Phys. 86 1340–5.)

8.5.

SILICIDATION USING PT AND PD

During the metal–Si1−x Gex reaction, Pd and Pt react preferentially with Si resulting in Ge segregation. This creates defects which pin the Fermi level near the midgap leading to a high Schottky barrier height [2]. Generally, silicidation studies of Pt and Pd with SiGe alloys are carried out in the temperature range of 300–500 ◦ C. It has been reported that Pt or Pd reacts with SiGe alloys to form ternary compounds such as Pt2 (Si0.8 Ge0.2 )1 or Pt1 (Si0.8 Ge0.2 )1 at 300 and 400 ◦ C for diﬀerent durations of annealing [23]. Thermodynamically, Si is more reactive than Ge with Pt. At 350 ◦ C, the reaction between Pt and Si1−x Gex consists of interdiﬀusion of Pt, Si and Ge with Pt as the dominant diﬀusion species, and while Pt diﬀuses in some Ge diﬀuse out [2, 24]. As Pt atoms reach the silicide/Si1−x Gex interface, they react preferentially with Si to form silicide, and the Ge atoms which are left behind diﬀuse out and pile up at the surface. Experimental evidence suggests that Pt selectively bonds with Si, the bonding between Pt–Si is stronger than that of Pt–Ge, and the formation of PtSi is favoured. Microscopically it creates a nonuniform interface at the PtSi/Si interfacial layer [23]. Annealing at a lower temperature shows some fraction of Ge segregation at the silicide–SiGe interface. However, during annealing at a higher temperature, Ge is repelled from the surface layer and forms a Ge-rich layer underneath the interface. Transmission electron microscope (TEM) analyses of low-temperature annealed Pd-strained Si1−x Gex alloys show the formation of hexagonal

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Metallization and heterostructure Schottky diodes

˚. There is also Pd2 Si or Pd2 Ge with a measured plane symmetry of 5.5 A a report of strain relaxation in the underlying Si1−x Gex layer due to hightemperature annealing of Pd at about 550 ◦ C [25,26]. In these compounds, a decrease in the vertical lattice parameter has been observed. Annealing of Pd–Si1−x Gex at about 550 ◦ C results in the formation of a double layer structure: the top layer contains a relatively small amount of Ge and the adjacent Si1−x Gex layer is enriched with Ge. Hong et al [5] have studied Pt/SiGe systems and have observed the formation of PtGe2 at annealing temperatures beyond 450 ◦ C. XRD spectra for the SiGe sample annealed at 400 ◦ C for 30 min containing 19% Ge and a 50 ˚ A Si sacriﬁcial layer are shown in ﬁgure 8.9. The resulting silicide peaks are oriented along the (200), (021), (¯115) and (222) directions. Figure 8.10 shows the XRD pattern of the SiGe sample with 29% Ge and a 50 ˚ A thick cap layer. As seen in ﬁgure 8.10, the PtSi peak is oriented in the (200), (¯ 222) and (¯115) directions along with the

Figure 8.9. XRD spectrum for PtSi/Si0.81 Ge0.19 ﬁlm annealed at 400 ◦ C for 20 min.

Heterostructure Schottky diodes

287

Figure 8.10. XRD spectrum for PtSi/Si0.71 Ge0.29 ﬁlm annealed at 400 ◦ C for 20 min.

peak arising from the Si(400) plane. It is observed from x-ray analysis that there is no evidence of germanide formation. 8.6.

HETEROSTRUCTURE SCHOTTKY DIODES

Schottky contacts play an important role in determining the performance of semiconductor devices required for various electronic and optoelectronic applications. Barrier heights of Schottky junctions depend strongly on the chemical phases formed by thermal reactions between the metal and semiconductor. Details of the chemical phase formation of Ti, Pt and Pd with group IV alloys have been described earlier. The barrier heights of metal/(SiGe, SiGeC or strained-Si) Schottky junctions are predicted to be lower than the corresponding metal/Si junctions.

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Metallization and heterostructure Schottky diodes

According to the Schottky–Mott model [27], the barrier height of a p-type Schottky junction depends on the metal work function, semiconductor bandgap and electron aﬃnity of the semiconductor. In the drift–diﬀusion emission model, hole current density across the metal– semiconductor interface is usually given by [27, 28] Jp = qvrp (po − ps )

(8.3)

where vrp is the eﬀective hole surface recombination velocity, ps is the density of holes near the interface in the semiconductor and po is hole density that would be there if the potential distribution could remain the same while the hole quasi-Fermi level came into equilibrium with the metal Fermi level. Moreover, due to image force lowering and thermionic ﬁeld emission, which usually occur in a practical Schottky diode, the barrier height can be modelled using the term [14] ! ∆φb =

qEmax + 4πs

3 h Emax 4 2π

2/3

−1/3

(2qm∗ )

(8.4)

where Emax is the electric ﬁeld at the metal–semiconductor interface, s is the dielectric constant of the semiconductor and m∗ is the eﬀective hole mass. In the above expression, the ﬁrst term corresponds to the image force lowering while the second term is responsible for the thermionic ﬁeld emission. Considering these eﬀects, the current in a Schottky barrier diode can be expressed as q∆φb Jp = qvrp (po − ps ) exp (8.5) kT and

po = Nv exp

−qφb kT

(8.6)

where k is the Boltzmann constant and Nv is the eﬀective density of state in the valence band. Assuming thermionic emission as the main mechanism of current ﬂow across a Schottky junction, the barrier height can be calculated using the relation kT AA∗ T 2 φb = (8.7) ln q I0 where A∗ is the eﬀective Richardson constant, A is the area of the diode and I0 is the saturation current. The ideality factor, m, is obtained from the relation [28] q ∂v m= (8.8) kT ∂ (ln I)

Heterostructure Schottky diodes

289

Figure 8.11. Forward and reverse current–voltage characteristics of a PtSi/Si0.81 Ge0.19 Schottky diode at diﬀerent temperatures. ∂v where ∂(ln I) is the slope of the linear extrapolated part of the current– voltage characteristics. The barrier height of a Schottky junction can also be determined from the measured reverse capacitance value. The determination of the Schottky barrier height by the capacitance–voltage method is based upon the voltage dependence of the charge in depletion region of the diode. Capacitance per unit area of a reverse biased Schottky junction is expressed as [27] s qs Na = CD = (8.9) 2(Vbi − V − kT /q) W

where s is the dielectric constant of the semiconductor, Na is the acceptor concentration of the diode, V is the applied reverse bias, Vbi is the built-in potential and W is the depletion width. It is evident from equation (8.9) that the plot of 1/CD 2 versus applied reverse voltage for an ideal Schottky

290

Metallization and heterostructure Schottky diodes

Figure 8.12. Forward and reverse current–voltage characteristics of a PtSi/Si0.71 Ge0.29 Schottky diode at diﬀerent temperatures.

diode will be a straight line. From the intercept on the voltage axis, the barrier height is determined from the relation φb = Vi + ψp +

kT q

(8.10)

where Vi is the voltage intercept and ψp is the potential diﬀerence between the hole quasi-Fermi level and the top of the valence band, which can be computed from the doping concentration and is given by kT Nv . (8.11) ψp = ln q Na The C–V method measures the electrostatic properties of the Schottky barrier and is insensitive to transport eﬀects such as tunnelling and image force lowering. For an inhomogeneous interface, the C–V method

Schottky diodes on strained-Si1−x Gex

291

averages over the whole sample area and measures the mean barrier height. Using the C–V technique, the energy distribution of the interface state density at a metal–semiconductor interface has been measured by Chattopadhyay et al [29]. 8.7.

SCHOTTKY DIODES ON STRAINED-SI1−X GEX

The forward and reverse logarithmic current–voltage characteristics at diﬀerent temperatures of PtSi/Si0.81 Ge0.19 and PtSi/Si0.71 Ge0.29 Schottky diodes are shown in ﬁgures 8.11 and 8.12, respectively. It is seen from the ﬁgures that the diode with a higher Ge concentration shows a higher current. It is also seen from ﬁgures 8.11 and 8.12 that reverse currents do not saturate for PtSi/Si1−x Gex Schottky diodes. The simulated band diagram of a PtSi/Si1−x Gex Schottky diode is shown in ﬁgure 8.13, considering the eﬀect of interface states and the associated series resistance. For simulation, a thin interfacial oxide layer of 10 ˚ A was taken into account. It is seen from the simulated band diagram that the valence band discontinuity is in close proximity to the interface. This happens

Figure 8.13. Simulated energy band diagram of a metal-silicide/strained Si1−x Gex Schottky barrier diode with an interfacial layer and a series resistance.

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Metallization and heterostructure Schottky diodes

as the thickness of the SiGe layer is small (limited by the critical layer thickness) to retain the strain in the epitaxial layer. Moreover, the layers get unintentionally doped during ﬁlm growth in an MBE system. As the valence band discontinuity is in close proximity to the Schottky junction, the total eﬀective barrier can be changed by changing the applied reverse bias. The sensitivity of the barrier height change can be controlled by changing the SiGe layer thickness. As a result, the barrier height decreases with the applied reverse bias [30]. Room temperature experimental and simulated forward current– voltage characteristics of PtSi/Si1−x Gex (x = 0.19 and x = 0.29) Schottky diodes are shown in ﬁgure 8.14 [31]. For simulation of forward current– voltage characteristics, thermionic emission, image force lowering and thermionic ﬁeld emission models were considered. Since the existence of a

Figure 8.14. Experimental and simulated current–voltage characteristics of PtSi/Si1−x Gex (x = 0.19 and 0.29) Schottky diodes.

Schottky diodes on strained-Si1−x Gex

293

thin interfacial layer (typically a few atomic layers) between the Schottky contact and the semiconductor aﬀects the current–voltage characteristics signiﬁcantly, interfacial layers of a thickness of 8 ˚ A and 10 ˚ A were included in the simulation of the current–voltage characteristics of PtSi/Si0.81 Ge0.19 and PtSi/Si0.71 Ge0.29 Schottky diodes, respectively. The interfacial layer was assumed to be transparent to the carriers, so that they tunnel through it without any reﬂection, but able to withstand a potential drop across it. Associated series resistances were computed to be 12.2 Ω cm−2 and 0.70 Ω cm−2 , respectively. Fermi level pinning was also incorporated in the model. To ﬁt the experimental current–voltage characteristics, the interface state density for both the diodes was taken to be the same, 1 × 1012 cm−2 eV−1 . The simulated current–voltage characteristics agree well with the experimental data for both the heterostructure Schottky diodes, as shown in ﬁgure 8.14. 8.7.1.

Barrier height and ideality factor

The saturation current density of a Schottky diode (J0 ) at zero bias is usually obtained by extrapolating the linear portion of the forward current– voltage characteristics to zero applied bias. Using the saturation current, important parameters such as the barrier height and ideality factor for a

Figure 8.15. Schematic structures of Schottky diodes fabricated on solid source MBE grown Si0.81 Ge0.19 and Si0.71 Ge0.29 ﬁlms. (After Dentel D et al 1998 Semicond. Sci. Technol. 13 214–9.)

294

Metallization and heterostructure Schottky diodes

Schottky diode can be determined. However, it is diﬃcult to apply at large biases where the voltage drop across the series resistance of the diode may become a signiﬁcant proportion of the applied voltage. To avoid this diﬃculty, the saturation current and ideality factor are calculated by using a least-squares ﬁtting method [32]. Dentel et al [24] have measured the barrier heights of platinum–silicide Schottky diodes on p-type Si1−x Gex (x = 0.19 and x = 0.29) ﬁlms. The device structures are shown in ﬁgure 8.15. The barrier height and ideality factor were extracted using equations (8.7) and (8.8), respectively. The variation of the barrier height as a function of temperature is shown in ﬁgures 8.16 and 8.17. It is seen from the ﬁgures that the Schottky barrier height (SBH) increases with the increase in temperature. The room temperature SBH values of PtSi/strained Si1−x Gex Schottky diodes extracted were 0.57 eV (x = 0.19) and 0.52 eV (x = 0.29). When the temperature was lowered to 95 K, barrier heights decreased to 0.20 eV and

Figure 8.16. Variation of Schottky barrier heights with temperature of PtSi/Si0.81 Ge0.19 , PdSi/Si0.81 Ge0.19 and TiSi/Si0.81 Ge0.19 Si diodes.

Schottky diodes on strained-Si1−x Gex

295

Figure 8.17. Variation of Schottky barrier heights with temperature of PtSi/Si0.71 Ge0.29 , PdSi/Si0.71 Ge0.29 and TiSi/Si0.71 Ge0.29 Si diodes.

0.19 eV, respectively. For comparison, the temperature dependences of the barrier height of the PtSi/Si Schottky diode are shown in ﬁgure 8.18. The same trend of barrier height variation with temperature is also observed for Si. Such a strong dependence of the barrier height on temperature is due to the fact that the measured current through a Schottky junction is a combination of thermionic and recombination currents. As a result, barrier height values calculated using the thermionic emission model show temperature dependence, since deviation from ideal behaviour due to recombination becomes more pronounced as the temperature is lowered [16, 33, 34]. Also the presence of a thin native oxide layer on the Si surface strongly inﬂuences the temperature dependence of the barrier height [35]. At a particular temperature, the barrier heights of the PtSi/Si1−x Gex (x = 0.19 and 0.29) Schottky diodes are smaller than those of the PtSi/p-Si Schottky diode. The biaxial strain in Si1−x Gex causes a change in the bandgap which is empirically expressed as Eg (x) = 1.11–0.74x eV, where

296

Metallization and heterostructure Schottky diodes

Figure 8.18. Variation of barrier heights with temperature of PtSi/Si, PdSi/Si and TiSi/Si Schottky diodes.

x is the Ge concentration [36]. The bandgap reduction for 19% Ge concentration is 0.13 eV, while it is 0.20 eV for a 29% Ge concentration with respect to Si. This bandgap reduction is the reason for the smaller barrier height obtained for Schottky diodes on p-SiGe ﬁlms with a higher Ge concentration. The room temperature ideality factor, extracted from the experimental I–V characteristics were found to be 1.10 and 1.15 for PtSi/Si1−x Gex diodes for x = 0.19 and 0.29, respectively. The current–voltage characteristics depend on the interface quality. In a Schottky diode, even with a good surface treatment, an interfacial oxide layer, of a thickness of about 5–10 ˚ A with a considerable amount of surface states, is present. According to the Bardeen limit [27], surface states pin the Fermi level at the mid energy gap of the energy band and make the barrier height less sensitive to the metal work function. The greater than unity ideality factor shows the deviation of Schottky diode characteristics from their ideal behaviour.

Schottky diodes on strained-Si1−x Gex

297

2 versus applied reverse bias at room temperature for Figure 8.19. Plots of 1/CD (a) TiSi/Si0.81 Ge0.19 and (b) TiSi/Si0.71 Ge0.29 Schottky diodes.

In thermionic emission theory, which models the ideal Schottky current–voltage characteristics, there is no satisfactory explanation for the greater than unity ideality factor [37, 38]. The departure of the ideality factor from unity may be due to the presence of an interfacial layer between the metal and semiconductor [14] and also due to the existence of a laterally varying potential barrier height, caused by a nonuniform interface [39]. Image force lowering has also been shown to be responsible for a greater than unity ideality factor [27]. The dependence of the ideality factor on temperature is due to thermionic ﬁeld emission and also recombination in the depletion region. As the bias voltage increases, the electric ﬁeld at the Schottky boundary decreases the potential drop across the interface. The bias voltage at which current–voltage characteristics become strongly nonideal depend more on the potential drop across the interfacial layer than on series resistances present in the diodes [35].

298

Metallization and heterostructure Schottky diodes

Table 8.2. Schottky barrier height and ideality factor of group IV alloy layers with Pt, Pd and Ti. Parameter

Film

Si0.71 Ge0.29 with Si-cap

Si0.79 Ge0.20 C0.01 with Si-cap

Metal

Pt

Pd

Ti

Pt

Pd

Ti

Ideality factor (n)

300 K 100 K

1.15 1.32

1.12 1.52

1.03 1.53

1.11 1.48

1.20 1.47

1.20 1.30

Barrier height (eV)

300 K 100 K

0.52 0.19

0.54 0.23

0.56 0.27

0.56 0.21

0.57 0.22

0.58 0.23

Figure 8.20. Plot of forward capacitance–voltage characteristics of a PtSi/Si0.81 Ge0.19 Schottky diode at diﬀerent frequencies.

Schottky diodes on strained-Si1−x Gex

299

Figure 8.21. Forward capacitance–voltage characteristics of a PtSi/Si Schottky diode at diﬀerent frequencies.

From the forward and reverse currents of PdSi/strained Si1−x Gex and TiSi/strained Si1−x Gex Schottky diodes barrier heights have been extracted by Maiti and Chattopadhyay [40]. The variation of the barrier heights of the diodes with temperature is shown in ﬁgures 8.16 and 8.17. In the case of PdSi/strained Si1−x Gex and TiSi/strained Si1−x Gex Schottky diodes, the barrier height increases with the increase in temperature. The room temperature values of the barrier heights for PdSi/strained Si1−x Gex Schottky diodes with x = 0.19 and 0.29 Ge are 0.58 eV and 0.54 eV, respectively. At 100 K, these values reduce to 0.28 eV and 0.23 eV, respectively. The values of the ideality factor of the diodes were within 1.03–1.50. Table 8.2 shows the extracted values of SBH and ideality factors of various metal–ﬁlm combinations at room temperature and 100 K. Barrier heights may also be determined from reverse capacitance– voltage measurements. When a small ac voltage is superimposed upon the dc bias, charges of one sign are induced on the metal surface and charges of

300

Metallization and heterostructure Schottky diodes

Figure 8.22. Forward capacitance–voltage characteristics of PtSi/Si1−x Gex (x = 0.19 and 0.29) Schottky diodes at 10 kHz (LF) and at 1 MHz (HF).

opposite sign in the semiconductor. The relationship between capacitance and reverse applied voltage is given by equation (8.9). Figure 8.19 shows 2 typical plots of 1/CD versus applied reverse voltage of TiSi/Si1−x Gex (x = 0.19 and 0.29) Schottky diodes measured at a frequency of 1 MHz. Using the voltage intercepts (on the x-axis) of 0.35 V and 0.28 V for the samples containing 19% and 29% Ge, the barrier heights extracted were 0.61 eV and 0.56 eV. The diﬀerence in the Schottky barrier height values deduced from current–voltage and C–V measurements is attributed to the eﬀect of inhomogeneities at the interface of the diodes. 8.7.2.

Interface state density distribution

The Schottky barrier diode characteristics deviate from their ideal behaviour due to the presence of an interfacial layer at the junction and the associated interface states. The distribution of the interface state density in metal/SiGe Schottky diodes has been reported by Chattopadhyay et al [29].

Schottky diodes on strained-Si1−x Gex

301

Figure 8.23. Energy distribution of interface state density of TiSi/Si0.81 Ge0.19 , PdSi/Si0.81 Ge0.19 and PtSi/Si0.81 Ge0.19 Schottky diodes.

The distribution of the interface state density in a Schottky diode is determined from capacitance–voltage measurements. Figure 8.20 shows the plots of forward C–V characteristics of the PtSi/Si0.81 Ge0.19 Schottky diode in the frequency range of 10 kHz to 1 MHz. At high frequency, the capacitance value becomes almost constant but in the low-frequency range the capacitance value shows a peak. The peak arises from the contribution of interface states present in the Schottky junction and partly due to the injection of minority carriers from the non-ohmic back side [41]. The corresponding plot for a PtSi/Si Schottky diode is shown in ﬁgure 8.21. It is seen that the variation of capacitance is of same nature as that of PtSi/Si1−x Gex diodes. Figure 8.22 shows only the plots of measured C– V data at 10 kHz and 1 MHz for PtSi/Si0.81 Ge0.19 and PtSi/Si0.71 Ge0.29 diodes. Taking CLF (10 kHz) and CHF (1 MHz) values, the interface state density Dit is extracted.

302

Metallization and heterostructure Schottky diodes

Figure 8.24. Energy distribution of interface state density of TiSi/Si0.71 Ge0.29 and PtSi/Si0.71 Ge0.29 Schottky diodes.

The energy distribution of the interface states of Si1−x Gex (x = 0.19 and 0.29) Schottky diodes using Pt, Pd and Ti are shown in ﬁgures 8.23 and 8.24, respectively. In ﬁgures 8.23 and 8.24, the energy has been plotted from the valence band edge. It is seen that the distribution of the interface state densities for all cases is maximum near the valence band edge and decreases (and remains almost constant) with energy from the valence band edge to the midgap. The minimum value of the interface state density for all the diodes lies in the energy range from 0.5–0.6 eV and has a value in the range of 6 × 1011 cm−2 eV−1 to 4.5 × 1012 cm−2 eV−1 [29]. It is seen from ﬁgures 8.23 and 8.24 that the PtSi/Si1−x Gex Schottky interface has the lowest interface state density as compared to PdSi and TiSi Schottky diodes on Si1−x Gex . The energy distributions of the interface state densities of TiSi/Si and PdSi/Si Schottky diodes are shown in ﬁgure 8.25. It is seen that the

Schottky diodes on strained-Si

303

Figure 8.25. Energy distribution of interface state density of TiSi/Si, PtSi/Si and PdSi/Si Schottky diodes.

distribution of the interface state density with energy is maximum near the valence band edge and it decreases with energy from the band edge to midgap energy for all Schottky diodes. The minimum value of the interface state density for all diodes is in the energy range from 0.50–0.60 eV and its value lies in the range of 1 × 1011 cm−2 eV−1 to 8 × 1011 cm−2 eV−1 . It is also evident from ﬁgure 8.25 that the energy distribution of interface states near the midgap is almost constant for all the diodes. 8.8.

SCHOTTKY DIODES ON STRAINED-SI

Schottky diodes on p-type strained-Si on graded relaxed Si1−x Gex have been characterized by Chattopadhyay et al [13]. The forward logarithmic current–voltage characteristics of as-deposited Pt/strained-Si Schottky diodes at diﬀerent temperatures are shown in ﬁgure 8.26. The current– voltage characteristics of the heterostructure Schottky diodes have also

304

Metallization and heterostructure Schottky diodes

Figure 8.26. Forward current–voltage characteristics of a Pt/strained-Si Schottky diode (as-deposited) at diﬀerent temperatures.

been simulated [35]. The simulated current–voltage characteristics for 95, 150 and 300 K are shown in ﬁgure 8.27. Among Pt, Pd and Ti, Pt shows the lowest barrier height and is not so sensitive to the metal work function. As discussed earlier, this is attributed to Fermi level pinning by the interface states or by metal-induced gap 2 states. Figure 8.28 shows a typical plot of 1/CD versus applied reverse voltage which is a straight line for Ti/strained-Si Schottky diodes. It is seen from the ﬁgure that the intercept on the voltage axis is 0.38 eV and, for a substrate doping concentration of 5 × 1015 cm−3 , the barrier height is found to be 0.60 eV.

Summary

305

Figure 8.27. Experimental and simulated current–voltage characteristics of Pt/strained-Si Schottky diode at 95, 150 and 300 K.

8.9.

SUMMARY

Formation and characterization of noble/refractory metal silicides (Pt, Pd and Ti on SiGe, SiGeC, Si and strained-Si) using x-ray diﬀraction, Rutherford backscattering and Auger electron spectroscopy have been discussed. Diﬀerent phase transformations are observed during silicide formation on SiGe and other alloys. Among all (Pt, Pd and Ti on SiGe, SiGeC and strained-Si), the PtSi/Si1−x Gex Schottky diodes exhibit a minimum barrier height with excellent interfacial quality and are therefore, preferable for far-infrared detector applications, as has also been demonstrated experimentally. Electrical characterization, over a

306

Metallization and heterostructure Schottky diodes

2 Figure 8.28. Plot of 1/CD versus applied reverse bias of Ti/strained-Si Schottky diode at room temperature.

wide range of temperatures to determine Schottky diode parameters, has shown that the barrier heights decrease with the decrease in temperature and increase in Ge mole fraction in the epilayer. Extracted ideality factors have values slightly greater than unity and are found to increase with decrease in temperature for all metal-material systems discussed. The interface state density decreases with increase in energy from the valence band edge for all diodes. The barrier height values determined from the reverse C–V characteristics at room temperature are found to be slightly higher than that extracted from the forward current–voltage characteristics. PtSi/Si1−x Gex and PtSi/Si Schottky photodetectors have been simulated in the wavelength range of 2–8 µm for detector applications and the simulation results compare favourably with reported experimental results as will be presented in chapter 9.

Bibliography

307

BIBLIOGRAPHY [1] Islam M N, Basa D K, Mukhopadhyay M, Bera L K, Ray S K, Banerjee H D and Maiti C K 1997 Schottky barrier height of Ti on strained layer Si/Si1−x Gex ﬁlms IETE. J. Res. 43 179–84 [2] Liou H K, Wu X, Gennser U, Kesan V P, Iyer S S, Tu K N and Yang E S 1992 Interfacial reactions and Schottky barriers of Pt and Pd on epitaxial Si1−x Gex alloys Appl. Phys. Lett. 60 577–9 [3] Buxbaum A, Eizenberg M, Raizman A and Schaﬄer F 1991 Compound formation at the interaction of Pd with strained layers Si1−x Gex epitaxially grown on Si(100) Appl. Phys. Lett. 59 665–7 [4] Kanaya H, Hasegawa F, Yamaka E, Moriyama T and Nakajima M 1989 Reduction of the barrier height of silicide/p-Si1−x Gex Japan. J. Appl. Phys. 28 L544–6 [5] Hong Q Z and Mayer J W 1989 Thermal reaction between Pt thin ﬁlms and Six Ge1−x alloys J. Appl. Phys. 66 611–5 [6] Thompson R D, Tu K N, Angillelo J, Delage S and Iyer S S 1988 Interfacial reaction between Ni and MBE grown SiGe alloys J. Electrochem Soc. 135 3161–3 [7] Aubry V, Meyer F, Warren P and Dutartre D 1993 Schottky barrier heights of W on Si1−x Gex alloys Appl. Phys. Lett. 63 2520–2 [8] Thomas O, Delage S, d’Heurle F M and Scilla G 1989 Reaction of titanium with germanium and silicon–germanium alloys Appl. Phys. Lett. 54 228– 30 [9] Kanaya H, Cho Y, Hasegawa F and Yamaka E 1990 Preferential PtSi formation in thermal reaction between Pt and Si0.80 Ge0.20 MBE layers Japan. J. Appl. Phys. 29 L850–2 [10] Xiao X, Sturm J C, Parihar S R, Lyon S A, Meyerhafer D, Palfrey S and Shallcross F V 1993 Silicide/strained Si1−x Gex Schottky-barrier infrared detectors IEEE Electron Device Lett. 14 199–201 [11] Dawn Technologies Inc 1994 SEMICAD Device Simulator Manual version 1.2 [12] Chattopadhyay S 1999 Studies on optoelectronic applications of SiGe alloys PhD Thesis Jadavpur University [13] Chattopadhyay S, Bera L K, Maharatna K, Chakrabarti S, Ray S K and Maiti C K 1997 Schottky diode characteristics of Ti on strained-Si SolidState Electron. 41 1891–3 [14] Hjelmgren H 1990 Numerical modelling of hot electrons in n-GaAs Schottkybarrier diodes IEEE Trans. Electron Devices 37 1228–34 [15] Eyal R, Brener R, Beserman R, Eizenberg M, Atzmon Z, Smith D J and Mayer J W 1996 The eﬀect of carbon on strain relaxation and phase formation in the Ti/Si1−x−y Gex Cy /Si contact system Appl. Phys. Lett. 69 64–6 [16] Aboelfotoh M O 1990 Temperature dependence of the Schottky-barrier height of tungsten on n-type and p-type silicon J. Appl. Phys. 67 51–5 [17] Engqvist J, Jansson U, Lu J and Carlsson J-O 1994 C49/C54 phase transformation during chemical vapour deposition TiSi2 J. Vac. Sci. Technol. A 12 161–8 [18] Wang M H and Cheng L J 1991 Simultaneous occurrence of multiphases in

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[32] [33] [34] [35]

Metallization and heterostructure Schottky diodes interfacial reactions of ultrahigh vacuum deposited Ti thin ﬁlms on (111) Si Appl. Phys. Lett. 59 2460–2 Lasy J, Nakos J, Chin O and Geiss P 1991 Comparison of transformation to low-resistivity phase and agglomeration of TiSi2 and CoSi2 IEEE Trans. Electron Devices 38 262–9 Murarka S P 1983 Silicides for VLSI applications (New York: Academic) Clevenger L A, Cabral Jr C, Roy R A, Lavoie C, Jordan-Sweet J, Brauer S, Morales G, Ludwig Jr K F and Stephenson G B 1996 Formation of a crystalline metal-rich silicide in thin ﬁlm titanium/silicon reactions Thin Solid Films 289 220–6 Lai J B and Chen L J 1999 Eﬀects of composition on the formation temperatures and electrical resistivities of C54 titanium germanosilicide in Ti-Si1−x Gex systems J. Appl. Phys. 86 1340–5 Kanaya H, Cho Y, Hasegawa F and Yamaka E 1990 Preferential PtSi formation in thermal reaction between Pt and Si0.8 Ge0.2 MBE layers Japan. J. Appl. Phys. 29 L850–2 Dentel D, Kubler L, Bischoﬀ J L, Chattopadhyay S, Bera L K, Ray S K and Maiti C K 1998 Molecular beam epitaxial growth of strained Si1−x Gex layers on graded Si1−y Gey for Pt-silicide Schottky diodes Semicond. Sci. Technol. 13 214–9 Buxbaum A, Eizenberg M, Raizman A and Schaﬄer F 1991 Interaction of Pd with strained layers Si1−x Gex epitaxially grown on Si(100) Japan. J. Appl. Phys. 30 3590–3 Buxbaum A, Zolotoyabko S, Eizenberg M and Schaﬄer F 1992 Strain relaxation in epitaxial Si1−x Gex /Si(100) layers induced by reaction with palladium Thin Solid Films 222 157–60 Sze S M 1981 Physics of Semiconductor Devices 2nd edn (New York: Wiley) Rhoderick E H and Williams R H 1988 Metal–Semiconductor Contacts (Oxford: Clarendon) Chattopadhyay S, Bera L K, Ray S K, Bose P K and Maiti C K 1998 Extraction of interface state density of Pt/p-strained-Si Schottky diode Thin Solid Films 335 142–5 Jimenez J R, Xiao X, Sturm J C and Pellegrini P W 1995 Tunable, longwavelength PtSi/SiGe/Si Schottky diode infrared detectors Appl. Phys. Lett. 67 506–8 Chattopadhyay S, Bera L K, Ray S K, Bose P K, Dentel D, Kubler L, Bischoﬀ J L and Maiti C K 1998 Determination of interface state density of PtSi/strained-Si1−x Gex /Si Schottky diodes J. Mater. Sci., Mater. Electron. 9 403–7 Bennett R J 1987 Interpretation of forward bias behaviour of Schottky barriers IEEE Trans. Electron Devices 34 935–7 Abeolfotoh M O and Tu K N 1986 Schottky-barrier heights of Ti and TiSi2 on n-type and p-type Si(100) Phys. Rev. B 34 2311–8 Abeolfotoh M O 1989 Inﬂuence of thin interfacial silicon oxide layers on the Schottky-barrier behaviour of Ti on Si(100) Phys. Rev. B 39 5070–8 Chattopadhyay S, Bera L K, Ray S K and Maiti C K 1997 Pt/p-strained-Si Schottky diode characteristics at low temperature Appl. Phys. Lett. 71 942–5

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Chapter 9 SIGE OPTOELECTRONIC DEVICES

Elemental silicon and germanium have long been used as photodetectors. The tunability provided by SiGe and SiGeC alloys has recently been exploited for extending the range of application. The fabrication and performance of several classes of photodetector based on a heterostructure are examined in this chapter. Methods of meeting the limitations of indirect band-gap and small allowable thickness of stable strained alloy layers are described. Silicon based optical waveguides and prospects of device integration receive special emphasis. The demand for optoelectronic technology is increasing rapidly and is being driven by the exponential growth in personal computers, high-speed computer interconnections, high-speed telecommunications and other commercial optoelectronic products. Optical communication systems are the most promising candidate for achieving large capacity transmission over high-speed local area networks (LANs) using ﬁbre channel and optical interconnection systems. The wide spread use of multimedia communications will require over 1 Gbit s−1 capacity transmission, even in LANs. Optical communications oﬀer a wide variety of applications toward building the information superhighway, ranging from short distance chip-to-chip communication, LAN, ﬁbre-to-home, to overseas telecommunications. Furthermore, with optical communication systems, optoelectronic integrated circuits (OEICs) have the potential to overcome the limitations in electronic integrated circuits for high speed, wide bandwidth, and high density interconnects as device dimensions shrink to the deep submicron regime. Although silicon is the dominant material in electronics, its indirect bandgap physically restricts its application in electro-optical devices. Most of the high-performance devices in optoelectronics are made from III–V compound semiconductor heterostructures, such as AlGaAs/GaAs and 310

SiGe optoelectronic devices

311

Table 9.1. Optical properties for Si and Ge. Property

Si

Ge

Transparent regions (µm) (absorption coeﬃcient <1 cm−1 ) Dielectric constant Refractive index (optical) Optical–phonon energy (eV) Phonon mean free path (˚ A)

1.1–6.5

1.8–15

11.9 3.455 0.063 76 (electron) 55 (hole)

16 4.001 0.037 105

InGaAsP/InP, because of their direct bandgap and high quantum eﬃciency. There are also several III–V compound semiconductor pairs with excellent lattice matching capability (≤1%), which is favourable for advanced heterostructures and bandgap-engineered devices. However, there are some inherent disadvantages of III–V semiconductors, such as poor mechanical and thermal properties, diﬃculty in processing, incompatibility with silicon and, more importantly, high cost. Cost-eﬀective silicon-based optoelectronics has attracted a great deal of research eﬀort and signiﬁcant progress has been made [1–5]. If the optical properties of silicon-based materials could be enhanced, in both the visible and infrared regions, especially at wavelengths of 1.3 and 1.55 µm, which are beyond the limitation of the Si bandgap but correspond to minimum values of absorption and dispersion in glass optical ﬁbres used for long distance telecommunications, very powerful optoelectronic integrated circuits could be realized entirely in silicon. Incorporation of Ge in Si reduces the bandgap of the resulting SiGe alloys, shifting their absorption wavelengths towards red compared to Si. SiGe strained layer superlattices (SLS) oﬀer the possibility of a fundamental change in optical properties of Si. The important optical properties of Si and Ge are presented in table 9.1. Optical communication systems with a Gbit s−1 capacity require the development of high-speed, highly reliable, low-cost and compact optical terminal ICs, such as Si-based optoelectronics integrated circuits. By incorporating future Si-based optical devices (emitters and detectors) with existing Si-based electronic circuitry all on a single silicon ‘superchip’ (see ﬁgure 1.10), these Si-based OEICs would represent a great cost reduction compared to their III–V counterparts and with added computational power. Eﬀorts to realize silicon-based optoelectronic devices include III–V on-chip light sources grown on silicon [6] or bonded to silicon [7], porous silicon [8–10], erbium-doped silicon [11, 12] and group IV semiconductor heterostructures [4]. In hybrid optoelectronic integration on Si, III–V photonic devices and Si or SiGe electronic devices are bonded on an Si

312

SiGe optoelectronic devices

Table 9.2. ICs for optical ﬁbre communication systems fabricated by using SiGe HBTs. Circuit

Maximum speed/bandwidth

Multiplexer Pre-ampliﬁer AGC ampliﬁer Decision circuit Demultiplexer Static frequency divider

40 Gb s−1 35.1 GHz 31.6–32.7 GHz 40 Gb s−1 40 Gb s−1 50 GHz

chip. This approach combines the high-speed and light emission advantages of III–V semiconductors and the mature and reliable Si technology. It is practical and has achieved some success for optoelectronic signal processing in the last few years [7, 13]. However, the fabrication of hybrid OEICs is more complicated, expensive and less reliable than monolithic OEICs. Also, interconnection density and speed in hybrid OEICs are limited. As applications of SiGe HBTs, various ICs for optical-ﬁbre-link systems, have been developed (see table 9.2) [14, 15]. These include both digital ICs of a static frequency divider and a time-division multiplexer (MUX), demultiplexer (DEMUX) and analogue ICs of a pre-ampliﬁer, an AGC ampliﬁer core and a decision circuit. A maximum operating frequency of up to 50 GHz for a 1/8 static frequency divider has been achieved. A 2:1 time-division MUX and a 1:2 DEMUX built from basic circuit core modules operated at 40 Gb s−1 . In a pre-ampliﬁer with an input stage consisting of a common base transistor, a bandwidth of 35 GHz was also achieved. In an AGC ampliﬁer core, a bandwidth of about 32 GHz with a dynamic range of 19 dB was obtained by using a transimpedance ampliﬁer as an active load circuit and a peaking capacitor. Highly porous silicon (PS) has attracted much attention because it exhibits strong photoluminescence (PL) from the near-infrared to visible green–blue range by varying the porosity at room temperature [9, 16]. The external quantum eﬃciencies of light emission of highly porous silicon can be as high as 1–10%. There is still a debate in the scientiﬁc community regarding the physics of this phenomenon. The common views of the origin of light emission are: (i) (ii) (iii) (iv)

the two-dimensional quantum-size eﬀects; surface molecular species coating the porous skeleton; radiative decay at surface/interface states; and hydrogenated amorphous silicon as a product of the invasive electrochemistry [10].

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313

Similar observations of strong visible PL from MBE grown B-doped porous Si0.7 Ge0.3 grown on p-type Si wafers have been reported [17]. The porous layers were formed by an electrochemical etching process. A signiﬁcant shift in the emission energy of porous Si0.7 Ge0.3 grown on Si has been observed for various anodization conditions and the temperature range 78–295 K. The PL emission energy has been found to remain almost unchanged on varying excitation energy, and to increase linearly with reciprocal temperature. The position of the PL emission, however, was observed to be strongly dependent upon the anodization current density and the duration of the etching process. The origin of visible PL of the porous MBE grown SiGe ﬁlms is interpreted by considering the quantum conﬁnement eﬀect, as in the interpretation of PL from porous Si. Despite its high eﬃciency, highly porous silicon has a problem with integration due to mechanical fragility and poor thermal conductivity and ohmic contacts. When doped with rare earth ions, silicon produces intense PL [11, 18]. Erbium is of great interest among these rare earth ions, because its luminescence spectrum, due to the transitions from the ﬁrst excited spinorbit state to the ﬁrst ground state, is centred around 1.54 µm which is the absorption window in silica-based optical ﬁbres. However, coupling between Er and the host Si remains a problem. Absorption of infrared radiation of 8–12 µm in atmosphere is small and this wavelength range is important for night vision applications. The group II–VI compound semiconductor (HgCdTe) IR sensor is most sensitive in this wavelength range. But monolithic integration on Si substrates for large scale use with charge coupled devices is diﬃcult. PtSi/p-Si Schottky diodes are presently being used but operate only in the 3–5 µm wavelength range. IrSi/p-Si Schottky diodes have a low barrier height with a cut-oﬀ wavelength of about 7.3 µm [19]. PtSi/Si1−x Gex Schottky diodes are also promising for sensing far-infrared radiation due to its smaller barrier height compared to PtSi/Si or IrSi/Si Schottky diodes. SiGe alloys have led to the realization of many novel bandgapengineered high-speed optoelectronic devices with signiﬁcantly improved performance and are easily integrated with conventional Si technology [1, 2, 5]. For compatibility with Si technology, strained layer superlattices are generally grown on an Si substrate. Using Si/SiGe/Si SLS, it is possible to convert the indirect bandgap of Si to a quasi-direct bandgap via Brillouin zone folding and to exploit the new optical properties in terms of Si-based optical devices. The aim is the fabrication of Si-based active and passive optical devices (light emitters and receivers such as LEDs and photodetectors) which could be integrated in silicon together with the electronic driver circuits [20]. Experimental studies have shown that infrared (>1.2 µm) light can be waveguided, detected, emitted, modulated and switched in Si and in binary group IV alloy ﬁlms [21]. However, a 4.2% lattice mismatch between silicon and germanium is

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a serious constraint in the design of SiGe heterostructures necessary for optical applications [22–25]. Most of the earlier investigations have involved SiGe heterostructures with a limited Ge content (<30%). In order to obtain a reasonable photoresponse in the 1.3 µm wavelength region, the Ge concentration should be more than 50%, whereas the critical thickness for a strained pseudomorphic SiGe epilayer with x = 0.5 is limited to only 100 ˚ A or less [4]. As described in chapter 2, for epilayers with a thickness greater than the critical thickness, misﬁt dislocations are introduced at the interface and the quality of the epilayer is degraded, aﬀecting the performance of the devices. In general, the group IV alloy system includes three binary alloys: SiGe, SiC and GeC. By adding a small substitutional C to the SiGe system, it is possible to adjust the lattice constant and strain (from compressive to tensile) and obtain an adjustable bandgap (from 0.67 eV to 5.48 eV by varying the composition) [26]. Ternary SiGeC and quarternary SiGeSnC systems oﬀer an additional degree of freedom for strain and bandgap engineering in Si-based alloys. Guarin et al [27] have reported the growth of ternary Si0.955 Sn0.03 C0.015 alloys up to 4500 ˚ A in thickness and quarternaries of composition in the neighbourhood of Si0.835 Ge0.125 Sn0.03 C0.01 . Infrared absorption spectroscopy and PL data have provided evidence of the potential for signiﬁcant bandgap modiﬁcation in these alloys. For this reason, renewed attention has shifted to the novel ternary Si1−x−y Gex Cy and SiGeSnC material systems [28, 29]. The other group IV alloy material with a potential for applications in the fabrication of Si-based infrared devices is metastable Snx Ge1−x ﬁlms [30]. Band structure calculations have suggested that the Snx Ge1−x alloys have direct energy gaps continuously tunable from 0.55 eV to 0 eV for compositions x from 0.2 to 0.6 with very small electron eﬀective masses. The relatively low growth temperature of Snx Ge1−x (∼200 ◦ C) opens the possibility of direct monolithic integration of detector arrays on Si integrated circuits. The bandgap of a–SiGe:H can be varied from 1.75 to 1.0 eV by changing the Ge content, and makes the material suitable for detection of light emitted from commercial laser diodes or LED. Films can be deposited at a low temperature of about 250 ◦ C on glass as well. Hydrogenated a–SiGe:H has been used for implementing phototransistors in the infrared range, solar cells, for optical detection and image sensing. Dilution with hydrogen causes a small decrease of the bandgap and improves the structural and electronic properties [31]. However, a simulation study of carrier multiplication in the Si1−x Gex material system shows that only a small increase of solar cell eﬃciency is expected from the impact ionization of hot carriers [32]. The objective of this chapter is to review the recent developments and the possible applications of group IV (SiGe, GeC, SiGeC, SiGeSnC

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and strained-Si) alloys in optoelectronics for integrated circuits entirely on silicon. Photoresponsivity and refractive index data obtained from experimental SiGe, SiGeC and GeC photodiodes are presented. Simulation of PtSi/Si1−x Gex and PtSi/Si Schottky photodetectors in the wavelength range of 2–8 µm, p-doped/intrinsic/n-doped (p–i–n) photodetectors, photoresponse characteristics of Si1−x Gex metal–semiconductor–metal (MSM) photodetectors and Si1−x Gex /Si waveguide photodetectors will be considered.

9.1.

OPTOELECTRONIC DEVICES IN SILICON

A photodetector converts an incident optical signal to an electrical signal that can be processed electronically to extract the required information carried by the incident optical signal. Semiconductor photodetectors are made by forming a p–n junction within the semiconductor or by forming a metal–semiconductor junction. On application of a suitable reverse bias to the device, an electric ﬁeld is created which separates the photogenerated electron–hole pairs. The device can operate either in photovoltaic or photoconductive mode. Photodetectors play an important role in optical ﬁbre communication systems and are generally used in optical receivers. The requirements for a good photodetector include high quantum eﬃciency at the operating wavelength, high speed, wide bandwidth, high reliability, low noise and low cost. An optical transmission and processing system consists of light sources (LED), photodetectors, modulators, electronic devices, and other passive or quasi-passive optical components. In a photoreceiver, a photodetector is monolithically integrated with a pre-ampliﬁer which uses an FET or an HBT. Diﬀerent types of photodetectors proposed for optical ﬁbre communication are: p–n junction photodiodes (PNPDs), p–i–n photodiodes (PIN-PDs), avalanche photodetectors (APDs), optical ﬁeld eﬀect transistors (OPFETs), MSM photodetectors (MSMPDs), p-heterojunction bipolar transistors (PHBTs) and photoconductors. Electron–hole pairs can be produced in a semiconductor by incident light through two diﬀerent processes. For incident radiation with an energy hν > Eg , where ν is the frequency of light and Eg is the semiconductor bandgap. The intrinsic photoexcitation process occurs where electron–hole pairs are generated by band-to-band transitions. In the other process, the extrinsic excitation process, the incident photon excites an electron from a donor level into the conduction band, or an electron is excited from the valence band to an acceptor level creating a hole in the semiconductor. Most photodiodes are of the intrinsic type. For intrinsic excitation processes, the long wavelength cut-oﬀ λc is

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given by λc =

hc 1.24 = Eg Eg

(9.1)

where c is the velocity of light. The external quantum eﬃciency of the photodiode is deﬁned as the number of electron–hole pairs generated per incident photon and is given by η=

Ip /q Popt /hν

(9.2)

where Ip is the photogenerated current, Popt is the incident optical power, and hν is the photon energy with a wavelength of λ. A related ﬁgure-ofmerit is photoresponsivity, which is given by Rphoto =

ηλ Ip ηq = . = Popt hν 1.24

(9.3)

The most common type of photodetection device is the depletion layer photodiode, which includes a p–n junction diode or a p–i–n diode. Another common type which exhibits gain is the avalanche photodiode. The other members of the photodiode family are Schottky barrier and MSM diodes. 9.1.1.

p–n junction photodiode

A p–n junction photodiode is the simplest type of junction diode. It works under relatively large reverse bias, which is substantially below the avalanche breakdown voltage. The incident optical signal produces electron–hole pairs in the photodiode, but only the carriers created within the depletion region or within a diﬀusion length of the depletion edge contribute. The reverse bias ﬁeld in the depletion region sweeps the photogenerated carriers towards the contacts and gives rise to a photocurrent in the external circuit. The holes and electrons, separated by the electrical ﬁeld, travel at diﬀerent velocities towards the contacts due to their diﬀerent eﬀective masses. A large reverse bias reduces the transit time through the depletion region as well as the depletion region capacitance, thus improving the diode capability for high-frequency operation. Free carriers generated by incident photons move by drift and diﬀusion and the total current density through the reverse biased depletion layer is Jtot = Jdrift + Jdiﬀ

(9.4)

where Jdrift and Jdiﬀ are the drift and diﬀusion components, respectively. For a p+ –n junction diode, the total current is given by e−αW Dp Jtot = qφopt 1 − + qpn0 (9.5) (1 + αLp ) Lp

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where φopt is the total photon ﬂux, W is the width of the depletion layer, q is the free electron charge, α is the optical inter-band absorption coeﬃcient, pn0 is the equilibrium hole density, and Lp and Dp are the diﬀusion length and the diﬀusion constant, respectively, for holes. The last term in equation (9.5) represents the reverse leakage current (dark current). When the reverse leakage current is very small, then the quantum eﬃciency, η is given by e−αW Ip /q =1− η= . (9.6) Popt /hν 1 + αLp It is clear that the quantum eﬃciency is determined mainly by the absorption coeﬃcient, α, of the semiconductor. In order to maximize η, it is desirable to make the products αW and αLp as large as possible, i.e., the depletion layer must be suﬃciently wide to allow a large fraction of the incident light to be absorbed. On the other hand, the depletion region must be kept narrow to reduce the transit time for high-speed devices. The avalanche photodiode is essentially a p–n junction operated in a reverse bias condition at or above the avalanche breakdown voltage. Photogenerated carriers in the depletion region travel at their saturation velocities. When these photogenerated carriers acquire enough energy from the electric ﬁeld, impact ionization occurs and results in avalanche multiplication of the carriers. Therefore, the gain of the APD can be substantially increased over conventional p–i–n photodiodes, but with elevated noise inherent to the avalanche process. 9.1.2.

Schottky barrier photodiode

Metal–semiconductor contacts (Schottky diodes) are used as very eﬃcient photodetectors as these are majority carrier devices. The barrier height, φb depends on the particular metal–semiconductor combination. As these devices do not suﬀer from minority carrier storage and removal problems, one can expect high speed and operation bandwidth. The temporal response, speed and frequency bandwidth of detectors are controlled by the transit time of the carriers through the absorption region and external circuit parameters. In high-speed diodes, the absorption region is between 0.2–0.5 µm which ensures full depletion of the region even at low values of reverse bias, and both electrons and holes can travel at their respective saturation velocities. Schottky barrier photodetectors can operate in two modes. (i)

When qφb < hν < Eg , i.e., the energy of incident photon ﬂux is higher than the corresponding Schottky barrier height but smaller than the bandgap energy of the semiconductor, electrons will be photoexcited in metal and surmount the barrier by thermionic emission. Emitted electrons transit through the semiconductor and are collected at the

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contact electrodes. The process extends the spectral range towards red (as it absorbs an energy lower than the bandgap energy) but decreases device speed as thermionic process is a slow one. (ii) When hν > Eg , the photon ﬂux penetrates through the semitransparent metal layer and gets absorbed in the semiconductor. The photogenerated electron–hole (e–h) pairs move in opposite directions due to the existing electric ﬁeld with their respective saturation velocities and are collected at the electrodes. This is a very eﬃcient mode of operation of Schottky diodes and is similar to that of a highspeed p–i–n diode. The fabrication of a Schottky barrier photodiode is also easy and lends itself for integrated applications. 9.1.3.

p–i–n photodetectors

p–i–n photodetectors are ﬁnding extensive applications in long haul and high bit rate optical communication systems and in local area networks for operation in the infrared region (0.8–1.6 µm). In addition to optical communication, these devices are also useful for sensing applications as they have superior electro-optical characteristics, namely low dark current, high quantum eﬃciency, greater sensitivity and high speed of response [33–35]. An important mode of operation of a p–i–n photodiode under the exposure of photon ﬂux is the reverse biased conﬁguration. In order to maximize the quantum eﬃciency of the diode, an intrinsic layer (i-layer) is inserted between two heavily-doped p+ - and n+ -layers and the resulting structure is a p–i–n diode. When a reverse bias is applied across the device, entire i-region becomes depleted. Due to high resistivity and total depletion of the i-layer, almost all the electric ﬁeld appears across it. The applied reverse bias should not be so high that breakdown can take place. The dark current is independent of applied reverse bias. As light impinges from the top surface, most of the photon ﬂux passes through the relatively thin top layer. The absorbed photons generate electron–hole pairs which drift towards the electrodes due to the existing electric ﬁeld to give rise to a photocurrent in the external circuit. One of the advantages of heterojunction p–i–n photodiodes is that the device characteristics are tunable by changing the composition of the i-layer. Another is the resonant–cavity eﬀect, due to the refractive index change at the heterojunction, which increases the photoresponsivity of the diode without aﬀecting the transit-time-limited bandwidth [36]. 9.1.4.

Metal–semiconductor–metal photodetectors

Metal–semiconductor–metal photodetectors (MSM-PDs) are made up of interdigitated metal ﬁngers forming back-to-back Schottky diodes on an undoped semiconductor surface (see ﬁgure 9.1). These detectors

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Figure 9.1. (a) Schematic structure of an MSM photodiode and (b) analysing area. (After Chattopadhyay S and Maiti C K, unpublished data.)

are very attractive for many optoelectronic applications, particularly for high-frequency wideband operation and are used in multi-gigabit optical communication with high sensitivity. MSM devices can be integrated in conventional IC-processing technology. On application of the bias, one junction becomes forward-biased while the other becomes reverse-biased. It can be designed so that the region between the two electrodes is almost depleted. When the incident photon ﬂux impinges on the photo-active area (interdigitated area), the diode responds as a Schottky photodetector discussed above. Some of the important design parameters for MSM-PDs

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SiGe optoelectronic devices

are responsivity, dark current and capacitance, which are discussed below. The dark current (which decides the minimum detectable power) of a photodetector signiﬁcantly contributes to the noise at the input of an optical receiver, which in turn plays a crucial role in deciding the sensitivity of a receiver. Excess carriers responsible for dark current increase the capacitance and decrease the response speed of a detector. The detector noise associated with its dark current is a shot noise and its mean square value is given by i2d = 2qId ∆f. (9.7) Furthermore, the minimum optical power required to achieve a photocurrent equal to the noise current id is usually regarded as the minimum detectable power of a detector. In an MSM structure, the dark current is a metal/semiconductor interface phenomenon and is attributed to thermionic emission of the carriers across the Schottky barriers [37]. Usually, thermionic emission of the carriers across a reverse-biased Schottky junction accounts for the dark current in MSM photodiodes [38] and the dark current density is given by J = A∗n T 2 e−q(φb −∆φb )/kT .

(9.8)

It is noted that a low Schottky barrier height would result in excess carrier injection in the semiconductor from the cathode and would lead to a large dark current. It has been proposed that equation (9.8) is valid until the conduction band proﬁle of an MSM photodiode does not reach the ﬂat band condition at the forward-biased contact [39]. When the conduction band at the anode reaches the ﬂat band condition, thermionic emission of holes across the barrier at anode starts and is accounted for the dark current which is given by J = A∗n T 2 e−q(φb −∆φb )/kT + A∗p T 2 e−q(φb −∆φb )/kT

(9.9)

where A∗ are the respective Richardson constants and ∆φ are the respective barrier height lowering due to image force. The ﬂatband voltage VFB can be expressed as [37] qNd S 2 VFB = (9.10) 2s 0 where S is the electrode spacing and Nd is the donor concentration in the layer. The dark capacitance of an MSM photodetector is contributed by the electrostatic ﬁeld around the alternatively charged parallel metal ﬁngers. The speed of an MSM detector is limited by RL C time constant if it is longer than the transit time or recombination time. Here, RL consists of the load resistance and series resistance of the metal ﬁngers. The detector capacitance can be estimated by using a model based on conformal

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321

mapping [40]. If W is the ﬁnger width and P is the ﬁnger pitch (sum of width and spacing, i.e., P = W +S), the total detector capacitance is given by C0 A (9.11) Ctotal = P where A is active area of the detector. 9.2.

OPTICAL PROPERTIES OF SIGE AND SIGEC FILMS

It has been shown that quantum eﬃciency is determined mainly by the absorption coeﬃcient of the semiconductor. The measured optical absorption coeﬃcient, α, and refractive indices of Si and Si1−x Gex for diﬀerent values of the Ge fraction, x, are shown in ﬁgures 9.2 and 9.3. The

Figure 9.2. Optical absorption coeﬃcients of Si, Ge and undoped SiGe alloys.

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Figure 9.3. Refractive indices of Si, Ge and undoped SiGe alloys.

data are taken from [41]. It is seen from ﬁgure 9.2 that Si is transparent in the wavelength region 1.20–1.60 µm, while the SiGe absorption edge shifts towards the red with increasing Ge concentration in the alloy. The shift oﬀers a means for absorbing 1.3–1.6 µm light, by choosing x > 0.3 for 1.3 µm and x > 0.85 for 1.55 µm. From ﬁgure 9.3, it may be noted that the refractive index increases with the increase in Ge concentration. While intrinsic Si and Ge are transparent from near-infrared up to 20 µm and beyond, the optical transmission of group IV alloys is found to reduce by heavy doping [2]. For unstrained (bulk) SiGe alloys, the absorption data have been provided by Braunstein et al [42]. Orner et al [43] have measured the optical absorption at phonon energies near the bandgap of a Ge-rich SiGeC (x ≈ 0.90, y ≤ 0.02) ﬁlm by employing Fourier transform infrared (FTIR) spectroscopy. As the ﬁlm

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323

Figure 9.4. Optical absorption coeﬃcient (α) of a Ge-rich Si0.11 Ge0.88 C0.01 ﬁlm: (a) C is primarily substitutional and (b) C is primarily interstitial. (After Orner B A et al 1996 Appl. Phys. Lett. 69 2557–9.)

was Ge-rich, their bandgap energies are less than that of Si. Absorption data and the best ﬁt curves are as shown in ﬁgure 9.4. Figure 9.4(b) shows a comparison between two ﬁlms with carbon at the interstitial and substitutional sites. In both cases the infrared absorption edge of the alloy shifts towards the red. Figure 9.5 shows the refractive index of the epitaxial Ge1−x Cx as a function of donor concentration and compares it to Ge epitaxial layers grown under identical conditions. Introducing carbon into epitaxial Ge ﬁlms doped with P decreases the refractive index near the absorption edge. Figure 9.6 illustrates the absorption coeﬃcient, α, of phosphorus-

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Figure 9.5. Refractive index versus donor concentration for Ge1−y Cy and Ge epitaxial ﬁlms on Si(100). (After Dashiell M W et al 1998 Thin Solid Films 321 47–50.)

Figure 9.6. Absorption coeﬃcient versus photon energy of Ge1−y Cy layers on Si(100) for ND = 7 × 1019 cm−3 , ND = 2 × 1018 cm−3 and undoped. Included are values for intrinsic bulk-Ge. (After Dashiell M W et al 1998 Thin Solid Films 321 47–50.)

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325

doped Ge1−y Cy ﬁlms grown epitaxially on Si(100) for α > 100 cm−1 . The absorption edge experiences a redshift with increasing phosphorus concentrations for both Ge1−y Cy and Ge ﬁlms. High-purity Ge data are also included in the ﬁgure. Note that undoped Ge1−y Cy epitaxial layers exhibit the same absorption coeﬃcient as does intrinsic bulk germanium for α > 100 cm−1 . Thus, a signiﬁcant band structure modiﬁcation was not observed by optical absorption for these C concentrations. 9.3.

OPTICAL DEVICES USING SIGE ALLOYS

The main aims of SiGe optoelectronics are: high responsivity, low noise, fast response and integration with the conventional Si-processing technology. Most of the reported studies include: (i)

p–i–n diode for 1.3 µm wavelength with 50% internal quantum eﬃciency, 200 ps impulse response and 10 pA µm−2 dark current at 15 V bias [2, 44–46]; (ii) waveguided p–i–n photodetectors with 50% internal quantum eﬃciency at 1.3 µm and 200 nA dark current at −15 V in a 10×750 µm device [25, 47]; and (iii) a waveguided metal–semiconductor–metal photodiode [48].

A responsivity of 0.2 A W−1 was measured at 1.3 µm over a 1 nm detector length with a 500 pA µm−2 dark current at 5 V bias. Si1−x Gex rib waveguide avalanche photodetectors for operation at 1.3 µm and strained layer superlattice waveguide photodetectors have also been reported [49–52]. Silicide/Si1−x Gex Schottky diodes have been proposed for detecting far-infrared radiation, taking advantage of the controllable bandgap of SiGe. For such diodes, the general requirement is to adjust the parameters such as the barrier height and ideality factor. PtSi/Si1−x Gex Schottky photodetectors have been proposed for detection of infrared radiation of wavelengths up to 10 µm [19]. Xiao et al [53] have demonstrated Pd2 Si/Si1−x Gex and PtSi/Si1−x Gex Schottky-barrier long-wavelength infrared detectors The cut-oﬀ wavelength is found to be dependent on the amount of Ge present in the strained layer. Figure 9.7(a) shows the measured Fowler plots for three Pd2 Si/Si1−x Gex (x = 0, 0.20 and 0.35) detectors using an FTIR spectrometer at 77 K. As expected, the cut-oﬀ wavelength clearly increases with the increasing Ge fraction, x, for the Pd2 Si/Si1−x Gex detectors. The spectral response of a PtSi/Si0.85 Ge0.15 detector is shown in ﬁgure 9.7(b) along with that of a PtSi/Si control device. The cut-oﬀ wavelength is extended from 5.2 to 8.8 µm with only 15% Ge in the alloy, corresponding to a barrier height reduction of 100 meV. By extrapolation, a cut-oﬀ wavelength beyond 10 µm is expected for a PtSi/Si1−x Gex detector

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Figure 9.7. Infrared photoresponse at 77 K of (a) Pd2 Si/Si1−x Gex and (b) PtSi/Si1−x Gex Schottky barrier detectors. (After Xiao X et al 1993 IEEE Electron Device Lett. 14 199–201.)

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327

Figure 9.8. Comparison of measured external responsivities of PtSi/Si0.80 Ge0.15 and PtSi/Si infrared detectors. The points represent data obtained with a calibrated infrared monochromator (40 K), while the lines are scaled results from FTIR measurements. (After Xiao X et al 1993 IEEE Electron Device Lett. 14 199–201.)

with as little as 18% Ge in the alloy. The measured external responsivities (40 K) of the PtSi/Si0.85 Ge0.15 detector and the PtSi/Si control device are shown in ﬁgure 9.8. Although the actual measurement was limited to 4 µm, extrapolated full responsivity curves for the PtSi/Si0.85 Ge0.15 detector showed superior responsivity to the conventional PtSi/Si detector over the whole wavelength range. Low-loss waveguides have been proposed using group IV alloy ﬁlms. Light can propagate in four types of group IV waveguides: lightlydoped silicon on heavily-doped silicon [54–57], epitaxial Si1−x Gex on Si [58–62], silicon-on-sapphire [63] and silicon-on-insulator [64–68]. In addition to epitaxial SiGe, SiC or SiGeC can be used as waveguide cores. Crystallographic defects such as threading dislocations need to be kept below 104 defects/cm2 in order to keep losses below 1 dB cm−1 in silicon-oninsulator and SiGe/Si waveguides [68]. A loss of 0.5 dB cm−1 for transverse electric (TE) and 0.6 dB cm−1 for transverse magnetic (TM) modes at 1.32 µm have been reported in chemical vapour deposited Si0.99 Ge0.01 ribs on Si [60]. The propagation loss in a polarization independent single-mode rib made from Ge-diﬀused Si has been found to be 0.3 dB/cm at 1.3 and

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Figure 9.9. Schematic view of integrated SiGe/Si planar photodetector with trench for optical ﬁbre guide. The optical ﬁbre is attached to the trench and the core of optical ﬁbre is coupled to the photodetector with alignment-free. (After Tashiro T et al 1997 IEEE Trans. Electron Devices 44 545–50.)

1.55 µm. In a single-mode SOI/SIMOX rib, the reported propagation loss is about 0.4 dB cm−1 for polarization independent 1.3 and 1.55 µm infrared radiations [65]. An integrated p–i–n SiGe/Si-superlattice photodetector (as shown in ﬁgure 9.9) with a planar structure has been developed on a bonded siliconon-insulator for Si-based optoelectronic integrated circuits [69, 70]. An Si, 30 periods, superlattice absorption layer, a 0.1 µm p-Si buﬀer layer and a 0.2 p+ –Si contact layer were deposited on a bonded SOI. The bonded SOI is used to increase the external quantum eﬃciency, ηext of the photodetector. Moreover, to achieve simple and stable coupling of an optical ﬁbre to the photodetector, a 63 µm deep and 128 µm wide trench is formed in the silicon chip. The p–i–n planar photodetector exhibits a high ηext of 25–29% with a low dark current of 0.5 pA m−2 and a high-frequency photoresponse of 10.5 GHz (3 dB bandwidth) at a wavelength of 0.98 µm. A vertical-cavity p–i–n SiGe/Si photodetector in bonded SOI substrate has been reported to exhibit a high external quantum eﬃciency of 60% with a low dark current of 0.5 pA µm−2 and a high photoresponse of 7.8 Gbit s−1 at λ = 980 nm as shown in ﬁgure 9.10. Light emission has been observed in various structures, such as rare earth metal-doped Si, strained-SiGe quantum wells, porous-Si, quasi-direct gap short period SiGe superlattices and Si quantum wires [71,72]. Si1−x Gex quantum well structures exhibit type I band alignment, where most of the band oﬀset occurs in the valence band when the Ge concentration is low. This type of structure allows for only holes to be eﬀectively conﬁned in

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Figure 9.10. Frequency response of a photodetector at an area of 5000 µm2 . A 3 dB bandwidth of 7.8 GHz is conﬁrmed at 5 V reverse bias at λ = 980 nm. (After Morikawa T et al 1996 IEEE IEDM Tech. Dig. pp 661–4.)

the quantum wells, whereas to form a light emitter, it is necessary to have an asymmetric type II structure which conﬁnes electrons in the conduction band. Neighbouring conﬁnement structures (NCS) using Si1−x Gex have been developed [73]. NCS structures consist of a thick (>3 µm) Si0.82 Ge0.18 buﬀer in which a step-graded Si1−x Gex layer with x ranging from 0 to 0.18 is grown, and then capped with a uniform 2.5 µm Si0.82 Ge0.18 layer. The NCS structure is then grown on Si0.82 Ge0.18 in which a tensile strained 10 ˚ A Si-only QW is grown for electron conﬁnement, and a 10 ˚ A Si0.64 Ge0.36 QW is grown for hole conﬁnement. This structure allows for a nearly ‘direct’ transition as evidenced by orders of magnitude enhancement of no-phonon low-temperature PL, as compared to SiGe QWs using type I and symmetric type II QWs. The NCS technique, when coupled with growth on relaxedSiGe buﬀers, is a promising approach in the production of Si-based light emitters [71]. Some reports on Si1−x Gex /Si quantum well infrared photodetectors (QWIP) have appeared [1, 74]. An integrated waveguide photodetector, as shown in ﬁgure 9.11, deposited on a SIMOX substrate, has been fabricated and an external quantum eﬃciency of 11% with an impulse response time of 400 ps has been observed. For the mid-IR range (3–5 µm) highly p-doped

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Figure 9.11. Schematic layout of a waveguide/detector device on a SIMOX substrate. (After Presting H 1998 Thin Solid Films 321 186–95.)

Si/SiGe QW detectors have been deposited on an undoped, double-sided polished Si substrate based on hetero-internal photoemission (HIP) over the Si/SiGe barrier. The absorption and photocurrent spectra have been measured from fabricated mesa detectors at 77 K. The photoresponse spectrum of the HIP detectors is found to be widely tunable in the technological important wavelength band of 3–5 µm by choice of Ge content, well thickness and doping level. Quantum eﬃciencies of 1% at 4 µm and 77 K have been achieved from SiGe HIP structures, dark currents as low as 10 × 10−8 A cm−2 can be obtained by modulation doping. The key features of a p-Si1−x Gex /Si QWIP are shown in ﬁgure 9.12. The alloy layers are grown pseudomorphically on an Si substrate, and are compressively strained. The alloy bandgap is smaller than that of Si for a fully strained layer [75]. The higher density of states in SiGe subbands suggests that SiGe QWIPs are inherently superior to AlGaAs QWIPs. Valence band technology is preferred for 8–14 µm SiGe/Si QWIPs because it allows normal incidence of light on the detectors. The polarization of normal light is always perpendicular to the growth direction of the QW layers. Although low noise and good responsivity have been realized, a

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Figure 9.12. Energy band diagram showing the shift of the absorption edges in a symmetrically strained-Si1−x Gex /Si multiple quantum wells (MQWs). Electrons are conﬁned in the wider bandgap of Si layers and holes are conﬁned in the narrower bandgap of Si1−x Gex layers. E1 and HH1 are the minimum electron and hole energy levels in the quantum wells. L is the width of the quantum well.

long length in the waveguided diode is needed due to a low absorption coeﬃcient. This long length tends to raise the parasitic capacitance of the distributed diodes. It becomes diﬃcult to obtain better responsivity at higher wavelengths as the stability of strained-SiGe QWs decreases rapidly as the Ge fraction increases. Photocurrent and absorption characteristics of SiGe QWs and Sim Gen SLS have been measured at room temperature by Presting [1]. The wavelength-dependent photocurrent spectrum has been measured using a grating monochromator illuminated by a tungsten lamp, and the electrical signal has been detected by a lock-in ampliﬁer technique. When comparing the absorption characteristics of the SLS and QW structures, it is evident that substantial absorption at 1.3 µm occurs for both structures. The diﬀerent long wavelength absorption limits between the two were explained

332

SiGe optoelectronic devices

Figure 9.13. Circuit diagram of a SiGe–Si p–i–n HBT photoreceiver. (After Rieh J-S et al 1997 IEEE Photonics Technol. Lett. 10 415–7.)

by taking into account the diﬀerent buﬀer layer thicknesses and Ge content in the structures. A monolithic SiGe/Si p–i–n HBT front-end transimpedance photoreceiver circuit, as shown in ﬁgure 9.13, has been fabricated by Rieh et al [76]. Figure 9.13 shows the circuit diagram with a transimpedance ampliﬁer which consists of a photodiode, common-emitter gain stages, two emitter follower buﬀers and a resistive feedback loop. For fabrication, a mesa-type SiGe/Si p–i–n HBT technology was used. Fabricated HBTs showed an fmax of 34 GHz with dc gain of 25. SiGe/Si p–i–n photodiodes, which share base and collector layers of HBTs, demonstrated a responsivity of 0.3 A W−1 at λ = 850 nm (incident optical power of 22 mW) at a reverse bias of 5 V, and steadily increased as the reverse bias was increased. The corresponding external quantum eﬃciency was 43%. The bandwidth of the photodiode was about 450 MHz (see ﬁgure 9.14(a)). The frequency response of the monolithically integrated single-feedback p–i–n HBT photoreceiver, excited with λ = 850 nm light, is shown in ﬁgure 9.14(b) and exhibited a bandwidth of about 460 MHz, which is limited by the bandwidth of p–i–n photodiode. The integration of Ge photodetectors on silicon substrates is also advantageous for various Si-based optoelectronics applications [77]. Figure 9.15 shows the schematic diagram of an integrated p–n mesa

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333

Figure 9.14. (a) Measured frequency response of the SiGe p–i–n photodiode and (b) measured frequency response of the SiGe photoreceiver. The solid curves show the ﬁt to the measured response. (After Rieh J-S et al 1997 IEEE Photonics Technol. Lett. 10 415–7.)

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Figure 9.15. A schematic diagram showing the optimized relaxed graded buﬀer growth sequence with the Ge mesa photodiode on top. (After Samavedam S B et al 1998 Appl. Phys. Lett. 73 2125–7.)

photodiode. Integrated mesa Ge photodiodes on an optimized graded relaxed-SiGe buﬀer on Si showed a very low dark current of 0.15 mA cm−2 . Capacitance measurements indicate that the detectors are capable of operating at high frequencies (2.35 GHz). The photodiodes showed an external quantum eﬃciency of 12.6% at 1.3 µm wavelength laser excitation in the photodiodes. 9.4.

OPTICAL DEVICES WITH SIGEC AND GEC ALLOYS

Conventional Si Schottky photodiodes and MSM photodetectors operate at wavelengths in the UV and visible region (<700 nm) of the spectrum [78, 79]. Si photodetectors operating at an 830 nm wavelength have been reported [80]. Normal incidence strained or relaxed SiGe and SiGeC p–i–n photodiodes have been studied by several researchers [46, 81, 82]. Although these devices used a thin intrinsic layer of 800–4000 ˚ A, the

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335

external quantum eﬃciencies were less than 1%. These results show that Ge-rich SiGeC diodes have a higher photoresponse to 1.3 µm excitation than Si-rich SiGeC diodes, because of the narrower bandgap of Ge-rich SiGeC, and hence the larger absorption coeﬃcient at a 1.3 µm wavelength. It was observed that the C blueshifted the photoresponse edge from the spectral response, suggesting that carbon increased the bandgap of the Gerich SiGeC alloys. This is consistent with the decrease of quantum eﬃciency with the increase of carbon composition in p-GeC/n-Si photodiodes, which agrees with the absorption studies [43]. However, SiGe and/or SiGeC MSM photodiodes operating in the near-infrared or infrared wavelength region have not yet been explored. p–n heterojunction photodiodes on epitaxial p-type Ge1−x Cx ﬁlms with carbon percentages of 0.2, 0.8, 1.4 and 2% on n-Si substrates have also been studied. Photoresponse characteristics of the diodes are shown in ﬁgure 9.16. The photocurrents of the p-Ge0.992 C0.008 /n-Si, pGe0.986 C0.014 /n-Si, and p-Ge0.98 C0.02 /n-Si photodiodes under an applied reverse bias of −20 V are 4.4, 4.0 and 2.6 µA, respectively, corresponding to external quantum eﬃciencies of 2.2%, 2% and 1.3%, respectively, for an incident power of 192 µW. The measured external quantum eﬃciencies at λ = 1.3 µm for diﬀerent diodes are shown in ﬁgure 9.17. For the purposes of ηext comparison, data of a p–i–n diode using SiGeC ﬁlms are shown.

Figure 9.16. The photoresponsivity of p-type Ge0.992 C0.008 , p-type Ge0.986 C0.014 and p-type Ge0.98 C0.02 on n-Si photodiodes. (After Shao X 1997 Structural and electrical characterization of SiGeC and GeC alloys and their application to optical detectors PhD Dissertation University of Delaware.)

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Figure 9.17. The measured external quantum eﬃciency at λ = 1.3 µm for the p-Ge1−x Cx /n-Si photodiodes and compared to a SiGeC p–i–n diode. (After Shao X 1997 Structural and electrical characterization of SiGeC and GeC alloys and their application to optical detectors PhD Dissertation University of Delaware.)

9.5.

SIMULATION OF OPTOELECTRONIC DEVICES

For the design and simulation of photodetectors, an understanding of the behaviour of photogenerated carriers under the inﬂuence of drift and diﬀusion is essential. The basic semiconductor equations, namely Poisson’s and current continuity equations for electrons and holes, are solved, along with a rate equation for the charged traps. Additionally, the optical generation term Gopt and recombination term Ropt are incorporated in the current continuity equations. A general purpose two-dimensional drift–diﬀusion simulator, SEMICAD, capable of simulating a wide range of semiconductor devices, has been used for simulation purposes. Important optical parameters, namely the absorption coeﬃcient and refractive indices, were supplied. Several additional mechanisms particularly applicable to optoelectronic devices are incorporated. These comprise: (i)

dynamic capture and emission of carriers by multiple trap levels of bulk and surface traps; (ii) carrier generation due to light or other ionizing radiation; and (iii) quantum-mechanical tunnelling between traps.

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337

The performance of a photodetector depends on the material parameters, device structure and conﬁguration, thickness of diﬀerent layers, doping levels, ohmic contact at electrode boundaries and anti-reﬂection coating. The selected material should have a high absorption coeﬃcient at wavelengths of interest, high carrier mobility, direct bandgap and the possibility to tailor the bandgap for high quantum eﬃciency and wide bandwidth. Besides the material selection, other important issues include: (i) (ii) (iii) (iv) (v)

reduction of surface reﬂection loss by using a transparent antireﬂective coating on the incident surface; for high detection eﬃciency, absorption at the depletion layer should be large by increasing the depletion width; to improve the eﬃciency and noise performance, generation recombination of the carriers in the depletion region should be small; to minimize the transit time, depletion width should be narrow; and to reduce the capacitance, detector area should be small.

Clearly an element of design trade-oﬀ is necessary to balance these somewhat conﬂicting requirements. In addition to the above considerations, the device time response is controlled by the external circuit components. For a good frequency response, both the capacitance and resistance need to be minimized, by reduction in area. However, if the depletion width is increased too much, the device is limited by the transit time eﬀects. The transit time, ttr is controlled by the width of depletion region and the saturation velocity, vs of the carriers, and is given by ttr =

W . vs

(9.12)

For a high-frequency response, optimization of the depletion width is necessary. In simulation, the basic semiconductor equations—Poisson’s, the current continuity equations for electrons and holes and a rate equation for the charged traps—need to be solved for the determination of electrostatic potential and total carrier concentration in the structure. These have been discussed in detail in chapter 4. Additionally, an optical generation term Gopt and the recombination term Ropt must be incorporated in the continuity equations for the analysis of p–i–n photodetectors. Two of the three recombination mechanisms, Shockley– Read–Hall (SRH) and Auger recombination, have been considered in chapter 4. The additional optical recombination rate term in the current continuity equations due to the creation of photons is given by (9.13) Ropt = Ccopt np − n2io where Ccopt is the optical capture rate.

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SiGe optoelectronic devices

The rate of carrier generation due to photon absorption is calculated from the rate of decay of the photon ﬂux. For a spatially uniform absorption coeﬃcient, the photon ﬂux, φopt decreases exponentially with distance as φ = φopt exp (−αy) .

(9.14)

The initial photon ﬂux can be calculated from the incident optical power density and from the wavelength as φopt =

Popt hν

(9.15)

where h is Planck’s constant and ν is the optical frequency. The generation rate of photo carriers can be expressed as Gopt = −

dφ = αφ dy

(9.16)

where dy is the diﬀerential distance along the direction of propagation of the incident beam and α is the absorption coeﬃcient. The quantum eﬃciency, η is calculated from the equivalent beam current at unity quantum eﬃciency [83] and is given by Ia η= (9.17) Ieq where Ia is the p–i–n diode terminal current and Ieq is the equivalent beam current at unity quantum eﬃciency. The responsivity is the ratio of photocurrent and incident optical power and is obtained from the external quantum eﬃciency. The diode capacitance can be computed from smallsignal ac analysis using y-parameters in a similar manner to that described in chapter 4. 9.5.1.

PtSi/SiGe Schottky photodetectors

In this section, we compare the performance of a PtSi/Si1−x Gex Schottky diode with that of a PtSi/Si Schottky diode. The structure considered for simulation is a cylindrical Schottky diode of 1 µm radius. The top Si1−x Gex epitaxial layer is grown on a graded Si1−y Gey (y : 0 → x) layer. The graded layer prevents the formation of a parasitic hole barrier at the substrate/Si1−x Gex interface. The thicknesses of both graded and epitaxial layers are 500 ˚ A. An ohmic contact has been taken from the back side of the photodetector. The power of the incident beam normal to the front side of the diode has been taken to be 10 µW. Figure 9.18 shows the simulated photoresponse characteristics of a PtSi–Si1−x Gex Schottky diode with that of a PtSi/Si Schottky diode of identical geometry, in the wavelength range of 2–8 µm. It is seen from ﬁgure 9.18 that the maximum value of responsivity in the wavelength range

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339

Figure 9.18. Simulated photoresponse of PtSi/Si1−x Gex and PtSi/Si infrared Schottky photodetectors. (After Chattopadhyay S and Maiti C K, unpublished data.)

considered here is 0.106 A W−1 , and in the 8 µm wavelength region the diode has a responsivity of approximately 0.032 A W−1 . For comparison, the spectral response of a PtSi/Si Schottky diode has also been simulated. It is seen from ﬁgure 9.18 that a PtSi/Si1−x Gex Schottky diode has a higher responsivity than a PtSi/Si Schottky diode. Above a wavelength of 5 µm, the responsivity of the PtSi/Si Schottky diode is negligible. The cut-oﬀ wavelength of PtSi/Si1−x Gex is also higher than that of a PtSi/Si Schottky diode. This is expected as the PtSi/Si1−x Gex diode has a lower barrier height. The reduction of barrier height of the PtSi/Si1−x Gex Schottky diode is responsible for the detection of a longer wavelength. It is also evident in ﬁgure 9.18 that the computed results agree well with the reported experimental results for a similar structure [53]. Also, the simulated responsivity is comparable to the highest reported responsivities found in Si/Si1−x Gex hetero-internal photodetectors [84, 85].

340

SiGe optoelectronic devices

Figure 9.19. (a) Schematic structure of Si0.7 Ge0.3 p–i–n diode; (b) computed band diagram; (c) doping proﬁle; (d) electric ﬁeld; and (e) optical generation. (After Chattopadhyay S et al 1999 Solid-State Electron. 43 1741–5.)

Figure 9.20. p+ –Si–n− (SiGe)–n− (SiGe) photodiode structure. (After Lee J et al 1995 Appl. Phys. Lett. 66 204–5.)

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341

Figure 9.21. Dark current versus reverse voltage characteristics of Si1−x Gex p–i–n photodiodes: (a) x = 0; (b) x = 0.2; (c) x = 0.3. (After Chattopadhyay S et al 1999 Solid-State Electron. 43 1741–5.)

9.5.2.

SiGe p–i–n photodetectors

A schematic structure of a SiGe p–i–n photodiode considered for simulation is shown in ﬁgure 9.19(a). The diode has a Si1−x Gex cylindrical-shaped intrinsic layer typically 1–3 µm thick on an n+ –Si substrate. The top and bottom surfaces have radii of 70 µm and 90 µm, respectively, with an average area of 2 µm × 104 µm. Electrical contacts are taken from the top and bottom surfaces [86]. The structure shown in ﬁgure 9.20 was considered for simulation as there are reliable experimental data for a similar structure [87,88]. At a reverse bias of 5 V, the computed energy band diagram for an Si1−x Gex (x = 0.30) photodiode is shown in ﬁgure 9.19(b). Figures 9.19(c) and (d) show the doping concentration and electrical ﬁeld across the diode, respectively. The optical carrier generation in the photodiode is shown in ﬁgure 9.19(e).

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SiGe optoelectronic devices

Figure 9.22. Computed spectral response of Si1−x Gex p–i–n photodiodes for: (a) x = 0; (b) x = 0.1; (c) x = 0.2; (d) x = 0.3; (e) x = 0.5; (f ) x = 0.75. (After Chattopadhyay S et al 1999 Solid-State Electron. 43 1741–5.)

Figure 9.21 shows the dark currents in three photodiodes (Si, Si0.8 Ge0.2 and Si0.7 Ge0.3 ) of identical geometry with a 1 µm thick intrinsic layer. It is seen from ﬁgure 9.21 that the dark current increases as the Ge mole fraction is increased. This is attributed to the decrease of bandgap due to the increase in Ge content in the intrinsic layer. For a 30% Ge content in the i-layer, the value of the dark current is in the nA range and saturates at a reverse bias of about 3 V or above. Figure 9.22 shows the computed responsivities of Si1−x Gex photodiodes of diﬀerent Ge concentrations (x = 0.0, 0.1, 0.2, 0.3, 0.5 and 0.75) as a function of wavelength (0.6–1.5 µm). It is seen from ﬁgure 9.22 that the cut-oﬀ wavelength of the photoresponse curves increases as Ge content in the absorbing i-layer increases. It is observed that the cut-oﬀ wavelengths for x = 0.0 (i.e., for Si) and for x = 0.75 are about 1.10 µm and 1.50 µm, respectively. This is due to the fact that, as the Ge content

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343

Figure 9.23. Simulated photoresponse of an Si1−x Gex p–i–n photodiode for: (a) x = 0.1 and (b) x = 0.3. (- - - -) computed and (——) experimental. (After Chattopadhyay S et al 1999 Solid-State Electron. 43 1741–5.)

is increased in the i-layer, the bandgap decreases which in turn extends the absorption tail towards the higher wavelength region. The reported experimental value of the photoresponse for Si1−x Gex p–i–n photodiodes (x = 0.08–0.69) in this wavelength range is about 0.4–0.5 A W−1 [87, 88] and is compared with simulation results in ﬁgure 9.23 for x = 0.1 and 0.3. The agreement is found to be very good. Photoresponse characteristics of a constant Ge content (x = 0.30) photodiode as a function of i-layer thickness (1.0, 1.5, 2.0 and 2.5 µm) are shown in ﬁgure 9.24 in the wavelength range of 0.6–1.4 µm. It is seen that, for a particular wavelength of the incident photon, responsivity increases with the thickness of i-layer. This is obvious because as the i-layer thickness increases, more incident photons get absorbed in the thicker i-layer region which in turn generates more photo-carriers.

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SiGe optoelectronic devices

Figure 9.24. Plot of photoresponse versus wavelength of an Si0.7 Ge0.3 p–i–n diode for diﬀerent i-layer thicknesses. (After Chattopadhyay S et al 1999 Solid-State Electron. 43 1741–5.)

Figure 9.25 shows the variation of the reverse capacitance of a 30% Ge content photodiode as a function of i-layer thickness. The capacitance decreases with the increase in i-layer thickness at a particular reverse bias. Figure 9.26 shows the variation of computed dark capacitance of an Si1−x Gex p–i–n photodiode having a 1 µm i-layer thickness for diﬀerent Ge mole fractions (x = 0.10, 0.20 and 0.30). It is seen that for a particular i-layer thickness, the dark capacitance increases as the Ge content in the i-layer increases, as expected. The capacitance of a p–i–n diode is basically the depletion capacitance and it is clear from ﬁgure 9.26 that above 1 V reverse bias, the diode has a capacitance in the range 2.3–2.5 pF. Such a low value of depletion capacitance is essential for ultra high-speed applications.

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345

Figure 9.25. Variation of capacitance with applied reverse bias of an Si0.7 Ge0.3 p–i–n diode for: (a) W = 1.0 µm; (b) W = 1.2 µm; (c) W = 1.5 µm and (d) W = 2.0 µm. (After Chattopadhyay S et al 1999 Solid-State Electron. 43 1741–5.)

9.5.3.

MSM photodetectors

The schematic view of an interdigitated MSM photodiode considered for simulation is shown in ﬁgure 9.1(a). Due to the symmetry of the structure of the MSM photodiode, the region chosen for analysis is shown in ﬁgure 9.1(b). Spacing between the positive electrode (anode) and the grounded electrode (cathode) is 2 µm and the ﬁnger widths are taken to be 1.5 µm. The responsivity and other important parameters of a representative unit cell of the device, in which the illumination is uniform, have been simulated. The responsivity has been calculated assuming the beam to be centred within the unit cell and the metallic ﬁngers are completely transparent.

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SiGe optoelectronic devices

Figure 9.26. Variation of capacitance with applied reverse bias of an Si1−x Gex p–i–n diode for: (a) x = 0.1; (b) x = 0.2 and (c) x = 0.3. (After Chattopadhyay S et al Solid-State Electron. 43 1741–5.)

Metal ﬁngers on the surface of MSM photodetectors form a Schottky barrier between the metal and semiconductor and therefore there will be a voltage-dependent depletion region beneath the metal ﬁngers. Figure 9.27 shows the computed depletion layer capacitance as a function of bias voltage for Si and Si0.80 Ge0.20 MSM photodetectors. An active area of 500 × 500 µm of the photodetector was considered. The capacitance values computed at 1 MHz for both detectors show an increase in depletion capacitance with increasing bias voltage, due to the fact that the absorption length exceeds the depletion layer width. At high bias voltage, the dependence of capacitance on voltage is weak. As seen from ﬁgure 9.27, the variation of capacitance with voltage of Si0.80 Ge0.20 MSM photodetector is similar to that of Si MSM-PDs. Si0.80 Ge0.20 MSM photodetectors show a slightly higher capacitance because of the higher dielectric constant of Si0.80 Ge0.20 .

Simulation of optoelectronic devices

347

Figure 9.27. Computed capacitance versus applied voltage for (a) Si and (b) Si0.80 Ge0.20 MSM photodetectors. Detectors have an active area of 500 × 500 µm with 1.5 µm ﬁnger width and 2 µm ﬁnger spacing. (After Chattopadhyay S and Maiti C K, unpublished data.)

Computed dark and photo currents for Si, Si0.80 Ge0.20 and Si0.70 Ge0.30 MSM-PDs are shown in ﬁgure 9.28. The dark current I–V characteristics are typical for a back-to-back Schottky contact. The Si0.80 Ge0.20 MSM-PDs have higher dark current compared to Si, increasing with the increase in Ge concentration in the Si1−x Gex epitaxial layer. Si has a dark current of 15 µA at 8 V and Si1−x Gex has a dark current of 60 µA (x = 0.2) and 95 µA (x = 0.3) at 6 V. Figure 9.29 shows the plot of computed responsivities of an Si MSM-PD in the wavelength range 0.4–1.20 µm for diﬀerent voltages (1, 3 and 5 V). An active area of 500 Kc ×500 µm, a ﬁnger spacing of 2 µm and a ﬁnger width of 1.5 µm were simulated. It is seen that the photoresponses are strongly dependent on applied reverse bias. It is expected that the cut-oﬀ wavelength of an Si MSM-PD will correspond to its bandgap energy. Figure 9.30 shows the plot of computed responsivities of an Si1−x Gex MSMPD in the wavelength range 0.4–1.40 µm, for diﬀerent values of x (0.10, 0.20 and 0.30) at 3 V. As shown in ﬁgure 9.30, the responsivity drops rapidly

348

SiGe optoelectronic devices

Figure 9.28. Dark and photo currents versus applied voltage of Si and Si1−x Gex MSM photodetectors. The detectors have an active area of 500 × 500 µm with 1.5 µm ﬁnger width and 2 µm ﬁnger spacing. (After Chattopadhyay S and Maiti C K, unpublished data.)

as photon energy decreases close to bandgap energy, while at a particular wavelength responsivity increases with increasing Ge content. Figure 9.31 shows the variation of computed responsivity with wavelength for diﬀerent ﬁnger widths and spacings. Curve a shows the responsivity of an Si0.8 Ge0.2 MSM photodiode for a ﬁnger width of 1.5 µm and spacing 2 µm while curve b shows the responsivity a for ﬁnger width and spacing of 2 µm and 1 µm, respectively. From curves a and b, one notices that the responsivity does not change much. Curve c shows the responsivity of an MSM-PD with the same Ge content but the ﬁnger width and spacing were 2 µm and 1 µm, respectively. We see that the responsivity has increased signiﬁcantly. This is due to the increase of the active area, which in turn increases the depletion area underneath the metal

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349

Figure 9.29. Plots of responsivity versus wavelength of an Si MSM photodetector at diﬀerent voltages. The area of the detector is 500 × 500 µm with a ﬁnger width of 1.5 µm and a spacing of 2 µm. (After Chattopadhyay S and Maiti C K, unpublished data.)

ﬁngers. Figure 9.32 shows the responsivity variation of an Si0.8 Ge0.2 MSMPD with diﬀerent thicknesses of top absorbing layer. It is seen that the responsivity increases as the top absorbing layer thickness under the metal ﬁngers increases. This is expected because a thicker layer will absorb more photons, which in turn increases the photocurrents. The Si1−x Gex MSM-PDs have a dark current which increases with the increase in Ge concentration. Si has a dark current of 10 µA at 6 V and Si1−x Gex has dark currents of 60 µA (x = 0.2) and 90 µA (x = 0.3, not shown in ﬁgure 9.32) at 6 V. Si MSM-PDs have a peak photoresponsivity of 0.60 A W−1 at 0.72 µm at an applied voltage 5 V. Si0.80 Ge0.20 PDs have peak responsivities of 0.76 A W−1 at 0.80 µm at an applied voltage of 3 V while Si0.70 Ge0.30 MSM-PDs have the responsivity of 0.88 A W−1

350

SiGe optoelectronic devices

Figure 9.30. Plot of responsivity versus wavelength of an Si1−x Gex MSM photodiode at 1 V for diﬀerent Ge mole fractions: (a) x = 0.1; (b) x = 0.2; (c) x = 0.3. The area of the diode is 500 × 500 µm with ﬁnger width and spacing of 1.5 µm and 2 µm, respectively. (After Chattopadhyay S and Maiti C K, unpublished data.)

at the same conditions. Si PDs have a cut-oﬀ wavelength of 1.10 µm which corresponds to its bandgap energy. The cut-oﬀ wavelength of SiGe PDs varies with Ge mole fraction. For a 30% Ge content, the cut-oﬀ wavelength is about 1.3 µm. 9.5.4.

SiGe/Si waveguide photodetectors

The inﬂuence of various design parameters in determining the external quantum eﬃciency of waveguide detectors based on Si/Si1−x Gex /Si strained layer superlattices, for use in optical communications at λ = 1.3 µm has been studied in detail by Naval et al [89]. The authors have presented an algorithm that automatically generates structurally stable

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351

Figure 9.31. Photoresponse characteristics of an Si0.80 Ge0.20 MSM-PD for diﬀerent geometry: (a) W = 1.5 µm, S = 2.0 µm; (b) W = 2.0 µm, S = 1.0 µm; (c) W = 2.0 µm, S = 2.0 µm, with an active area of 500 × 500 µm. (After Chattopadhyay S and Maiti C K, unpublished data.)

SLS. The simulation includes various design parameters such as optical waveguiding, absorption, quantum size eﬀect as well as thermodynamics of the strained layers. A conservative model for the critical thickness, hc , corresponding to the equilibrium regime has been shown to be important for relatively high Ge content, necessary to achieve moderate eﬃciency. Limiting the superlattice thickness and detector length to 1 µm and 1 mm, respectively, yielded discrete maximum values for ηext (around 12%) and ηint (around 30%) that were mainly dependent on the alloy absorption. A more optimistic model for hc , corresponding to the metastable regime, produced considerably higher ηext (around 60%), which shows the great importance of ﬁbre-to-waveguide coupling eﬃciency. The importance of the passive waveguide coupler geometry was investigated using the beam propagation method.

352

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Figure 9.32. Photoresponse characteristics of an Si0.80 Ge0.20 MSM photodiode for diﬀerent absorbing layer thicknesses at 1 V applied bias. (After Chattopadhyay S and Maiti C K, unpublished data.)

9.6.

SUMMARY

The highly-developed Si technology makes SiGe and other group IV alloys, ideal materials for realizing optical devices in the near-IR as well as in the mid- to far-IR regime, monolithically integrated with electronic driver circuits for optical communication systems. In this chapter, recent developments and the possible applications of group IV (SiGe, GeC, SiGeC, SiGeSnC and strained-Si) alloys in optoelectronics for integrated circuits entirely on silicon have been discussed. Photoresponsivity and refractive index data obtained from experimental SiGe, SiGeC and GeC photodiodes were presented. Simulation results, obtained using a 2D heterostructure device simulator, for PtSi/Si1−x Gex and PtSi/Si Schottky photodetectors in the wavelength range of 2–8 µm, have been presented. It was found

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that the PtSi/Si1−x Gex photodetectors oﬀer superior responsivity and higher cut-oﬀ wavelength compared to conventional PtSi/Si Schottky photodetectors. Simulation results compare favourably with reported experimental results. Responsivity, dark current and cut-oﬀ wavelength of an Si1−x Gex p–i–n photodetector increase with increasing Ge mole fraction in the absorbing i-layer and cover a wavelength range of 1.10–1.50 µm as the Ge mole fraction increases from 0.0 to 0.75. Simulated high responsivity, low dark current (in the range of nA) and low capacitance suggest that these detectors are good candidates for infrared light detection in the wavelength range of 1.30–1.50 µm. The photoresponse of Si1−x Gex MSM-PDs has been found to increase with increasing Ge mole fraction. However, the dark current of a SiGe detector is higher than that of an Si photodetector. Due to lack of experimental data, no comparison could be made for SiGe MSM-PDs. It was also observed that the responsivity increases with the increase of the absorption layer thickness underneath the metal ﬁngers. However, the main hindrance for a total Si-based integrated optic solution is the lack of a suﬃciently intense Si-based transmitter at 1.3 µm. BIBLIOGRAPHY [1] Presting H 1998 Near and mid infrared silicon/germanium based photodetection Thin Solid Films 321 186–95 [2] Soref R A 1993 Silicon-based optoelectronics Proc. IEEE 81 1687–706 [3] Kasper E and Presting H 1991 Device concepts for SiGe optoelectronics Proc. of Physical Concepts of Materials for Novel Optoelectronic Device Applications I: Materials Growth and Characterization 1361 302–12 [4] Bean J C 1992 Silicon-based semiconductor heterostructures: column IV bandgap engineering Proc. IEEE 80 571–87 [5] People R 1986 Physics and applications of Gex Si1−x /Si strained layer heterostructures IEEE J. Quantum Electron. 22 1696–710 [6] El-Masry N A, Tarn J C L and Bedair S M 1989 Combined eﬀect of strainedlayer superlattice and annealing in defects reduction in GaAs grown on Si substrates Appl. Phys. Lett. 55 1442–4 [7] Lo Y H, Bhat R, Hwang D M, Chua C and Lin C-H 1993 Semiconductor lasers on Si substrates using the technology of bonding by atomic rearrangement Appl. Phys. Lett. 62 1038–40 [8] Pavesi L, Guardini R and Bellutti P 1997 Porous silicon n–p light emitting diode Thin Solid Films 297 272–6 [9] Canham L T 1990 Silicon quantum wire array fabrication by electrochemical and chemical dissolution of wafers Appl. Phys. Lett. 57 1046–8 [10] Hamilton B 1995 Porous silicon Semicond. Sci. Technol. 10 1187–207 [11] Ennen H, Pomrenke G, Axmann A, Eisele K, Haydl W and Schneider J 1985 1.54 µm electroluminescence of erbium-doped silicon grown by molecular beam epitaxy Appl. Phys. Lett. 46 381–3 [12] Ren F Y G, Michael J, Sun-Paduano Q, Zheng B, Kttagawa K,

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[47] Jalali B, Naval L, Levi A F and Watson P 1992 GeSi infrared photodetectors grown by rapid thermal CVD SPIE Proc. 1802 94–107 [48] Splett A, Schuppert B, Petermann K, Kasper E, Kibbel H and Herjog H J 1992 Waveguide/photodetector combination in SiGe for long wavelength operation Dig. Conf. on Integrated Photonic Res. 10 122–3 [49] Temkin H, Pearsall T P, Bean J C, Logan R A and Luryi S 1986 Gex Si1−x strained-layer superlattice waveguide photodetectors operating near 1.3 µm Appl. Phys. Lett. 48 963–5 [50] Temkin H, Bean J C, Pearsall T P, Olsson N A and Lang D V 1986 Ge0.6 Si0.4 rib waveguide avalanche photodetector for 1.3 µm operation Appl. Phys. Lett. 49 809–11 [51] Splett A, Zinke T, Petermann K, Kasper E, Kibbel H, Herzog H-J and Presting H 1994 Integration of waveguides and photodetectors in SiGe for 1.3 µm operation IEEE Photonics Technol. Lett. 6 59–61 [52] Kesan V P, May P G, Bassous E and Iyer S S 1990 Integrated waveguidephotodetector using Si/SiGe multiple quantum wells for long wavelength applications IEEE IEDM Tech. Dig. pp 637–40 [53] Xiao X, Sturm J C, Parihar S R, Lyon S A, Meyerhafer D, Palfrey S and Shallcross F V 1993 Silicide/strained Si1−x Gex Schottky-barrier infrared detectors IEEE Electron Device Lett. 14 199–201 [54] Soref R A and Lorenzo J P 1985 Single-crystal—a new material for 1.3 and 1.6 µm integrated-optical components Electron. Lett. 21 953–4 [55] Soref R A and Lorenzo J P 1986 Epitaxial silicon guided-wave components for λ = 1.3 µm OSA Integrated and Guided-Wave Optics Conf. Dig. Papers (26 February 1986) pp 18–19 [56] Soref R A and Lorenzo J P 1986 All-silicon active and passive guided-wave components for λ = 1.3 µm IEEE J. Quantum Electron. 22 873–9 [57] Brown T G, Bradﬁeld P L, Hall D G and Soref R A 1987 Optical emission from impurities within an epitaxial silicon optical waveguide Opt. Lett. 12 753–5 [58] Soref R A, Namavar F and Lorenzo J P 1989 Optical waveguiding in a singlecrystal layer of germanium–silicon grown on silicon SPIE Proc. 1177 175– 84 [59] Soref R A, Namavar F and Lorenzo J P 1990 Optical waveguiding in a single-crystal layer of germanium–silicon grown on silicon Opt. Lett. 15 270–2 [60] Pesarcik S F, Treyz G V, Iyer S S and Halbout J M 1992 Silicon–germanium optical waveguides with 0.5 dB/cm losses for single-mode ﬁbre optic systems Electron. Lett. 28 159–60 [61] Mayer R A, Jung K H, Hsieh T Y, Kwong D-L and Campbell J C 1991 Gex Si1−x optical directional coupler Appl. Phys. Lett. 58 2744–5 [62] Liu Y M and Prucnal P R 1992 Deeply etched singlemode GeSi rib waveguides for silicon-based optoelectronic integration Electron. Lett. 28 1434–5 [63] Namavar F and Soref R A 1991 Optical waveguiding in Si/Si1−x Gex /Si heterostructures J. Appl. Phys. 70 3370–2 [64] Soref R A and Lorenzo J P 1989 Light-by-light modulation in silicon-oninsulator waveguides Proc. IGWO’89 (OSA Tech. Dig. Series) 4 86–9

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Chapter 10 RF APPLICATIONS OF SIGE HBTS

The revolution in wireless communications has been brought about by the recent advances made in the areas of digital integrated circuits, radio frequency components and circuits, digital communications and networking techniques. Mobile communication is now the fastest growing consumer electronics segment in all parts of the world. Digital services, internet and multimedia are all becoming mobile. The last few years have seen a remarkable expansion in the use of cellular and cordless phones and other personal communication systems and, as a result, the demand for transceivers with small size, fewer oﬀ-chip components, better integration and low operating voltage has increased dramatically. According to the market research ﬁrm Dataquest, the production of wireless devices is expected to grow to over 450 million units annually by the year 2002. The opportunity for chips that process radio frequency signals alone is expected to reach $7 billion by 2002. A recent US Department of Commerce report indicates that global positioning satellite (GPS) equipment sales will reach $16 billion in 2003. RF communication systems can be broadly classiﬁed into two sectors, namely ‘low-end’, such as pagers, cordless phones etc, and ‘high-end’, such as PCS, GSM, IS-136 etc. DECT (digital enhanced cordless telecommunications) is also an acknowledged standard in many countries all over the world, replacing conventional analogue systems for wired and cordless telephones. DECT holds substantial promise for residential cordless, wireless PBX and wireless local loop (WLL) applications. This high-performance micro-cellular technology is a particularly attractive WLL alternative in areas where laying a wired infrastructure poses problems, or in urban areas where traditional cordless telephones are overburdened. The DECT standard speciﬁes that communications will be done in a frequency band with a bandwidth of 17 MHz centred at 359

360

RF applications of SiGe HBTs Table 10.1. Comparison of wireless communications standards.

Standard

System

Frequency band

Channel BW/SP

Maximum user average

Power peak

GSM AMPS PACS PCS-1900 IS-136

Cellular Cellular PCS-TAG-3 PCS-TAG-5 PCS-TAG-4

900 MHz 800 MHz 1.9 GHz 1.9 GHz 1.9 GHz

200 kHz 30 kHz 300 kHz 200 kHz 30 kHz

250 mW 600 mW 25 mW 125 mW 200 mW

2W 600 mW 200 mW 1W 600 mW

approximately 1.89 GHz, making it a narrowband communications system which requires a peak output power of 250 mW. In the United States and Canada, the 902–928 MHz ISM (industrial– scientiﬁc–medical) frequency band has been established as a licence-free spectrum, for use by low-power communication devices such as cordless telephones. The ISM standard speciﬁes operation from 902–928 MHz and 1 mW transmitted power. Table 10.1 summarizes the speciﬁcations for some of the wireless communications systems presently in use. It is clear that a variety of frequencies, modulation schemes and output power requirements have proliferated on a worldwide basis, and that no one single standard or frequency can be expected to dominate wireless data systems for the foreseeable future. Instead, in order to address a broad market, radio transceivers must increasingly satisfy the competing constraints of ﬂexibility and low cost [1]. Present wireless communication systems, in the frequency range 0.8–2.5 GHz, will require integrated low-noise front-end circuits, active ﬁlters, wideband AGC ampliﬁers, AD/DA converters, mixers, synthesizers with voltage controlled oscillators and power ampliﬁers. The circuits are battery operated and must function at relatively high currents and low voltages. While integration in the baseband has been pursued relentlessly resulting in very high density circuits, attention has only recently been focused on radio frequency integrated circuits (RFICs) for communication. The standard transceiver architecture for most wireless systems has so far been based on the superheterodyne principle since its initial development by E Armstrong in the early 1900s. In this conﬁguration, the radio signal received at the receiving antenna is sent to a low-noise ampliﬁer (LNA), whose purpose is to boost the signal level without reducing the signal-to-noise ratio signiﬁcantly. Following the LNA, the signal is passed through a mixer, which essentially multiplies the input signal by a local oscillator signal of constant frequency, producing an output signal, whose frequency is the diﬀerence between the two inputs, the so-called

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361

‘intermediate frequency’ (IF), the amplitude of which is proportional to the original input signal. Preceding the mixer, an analogue ﬁlter eliminates the response to an undesired input signal at (2flo –frf ) that would also downconvert to the intermediate frequency. This ‘image reject’ ﬁlter is typically implemented with a physically large surface acoustic wave (SAW) ﬁlter. The basic limitation of the traditional frequency translating mixers and the heterodyne architecture is their sensitivity to ‘spurious responses’ resulting from nonlinearities in the preceding ampliﬁer and mixer. In highly integrated transceivers, one may allow these ﬁlters to be dispensed with, signiﬁcantly reducing the power dissipation and the physical size. The spurious responses must be carefully controlled through bulky and expensive oﬀ-chip ﬁlters which are not suitable for monolithic integration, the key to lower power operation. Signiﬁcant improvements in the area of receiver architecture have been made recently by the use of quadrature signal processing techniques, also known as the Hartley phasing method and ‘direct downconversion’ or homodyne approaches for wireless receivers, which eliminate the need for image rejection ﬁlters and are better suited to monolithic integration. However, the direct conversion receiver has not gained widespread acceptance due to its intrinsic sensitivity to dc oﬀset problems, even order harmonics of the input signal that interfere with the desired signal, and local oscillator leakage problems back to the antenna which are being actively pursued by several research groups. Several excellent reviews of research in this ﬁeld are presented in [2, 3]. Rudell et al [4] have reported an interesting variation in the superheterodyne/homodyne receiver architecture using the wide band IF double conversion technique. Field-eﬀect transistors in III–V semiconductors have so far been the workhorse of the microwave industry because of their excellent highfrequency performance and, with the introduction of heterojunction FETs, low noise ﬁgures. The integration of highly complex digital circuits on GaAs is often prohibitive because of cost, limited wafer sizes, processing complexities and poor yield. A current solution to this problem is to mix GaAs and Si technologies using a multichip module (MCM) platform. But GaAs monolithic microwave integrated circuits (MMICs) are expensive and there are diﬃculties associated with high pin count ﬂip-chip solder bonding. Silicon, although not traditionally the material of choice for RF and microwave applications, has become a serious challenger to other semiconductor technologies for high-frequency applications. Passive microwave components have been demonstrated on high resistivity silicon substrates. Arnold and Pedder [5] reported transmission lines and spiral inductors working at microwave frequencies on high resistivity substrates. Fine-line electron beam and photolithographic techniques are now capable of fabricating geometries as small as 0.1 µm while high resistivity silicon

362

RF applications of SiGe HBTs

wafers support low loss microwave transmission lines. An integrated Si-based MMIC technology circumvents some of the diﬃculties encountered in III–V material systems, oﬀers improved thermal management by virtue of a higher thermal conductivity, and the design capabilities of CMOS for complex logic circuits and more compact modules. All-Si MMIC technologies have been investigated previously. Hanes et al [6] have reported such a technology, based on the SIMOX process with high resistivity substrates, and obtained a maximum frequency of oscillation of 32 GHz. Evidence from the literature suggests that the impedance of a high resistivity (104 Ω cm−1 ) Si substrate will allow microwave/millimetre wave operation, although it is anticipated to be a more diﬃcult design consideration than the GaAs MMICs. Surface pinning, which is a feature of GaAs, does not occur in Si which may oﬀer some advantage in terms of reducing parasitic capacitances. These advances, coupled with SiGe, open the possibility of silicon integrated circuits (ICs) with the speed required for increasingly higherfrequency applications. Manufacturing costs are the key to SiGe success, which are about one ﬁfth of the costs of GaAs for equivalent performance [7]. Applying SiGe does not mean using a completely new process as the technology and manufacturing are very similar to well-proven methods, but have considerably extended features. A complete RF transceiver (see ﬁgure 10.1), including VCO and synthesizer, has been integrated on one chip. A second IC, implemented

Figure 10.1. A schematic diagram of an RF transceiver including SiGe front-end. (After Bopp M et al 1999 IEEE ISSCC Tech. Dig. pp 68–9.)

SiGe: perspective for wireless communication

363

in SiGe technology, includes an LNA in the receive path as well as a power ampliﬁer for the transmit path and a driver for an external PIN diode switch [8]. The circuit conﬁgurations for the LNA, oscillator, mixer and the devices selected must be such as to ensure low power and low noise. Since in a portable wireless environment all circuits are drawing power from a small battery, it is clear that one of the most important aspects of the circuits that needs to be optimized is power consumption. Additionally, since these devices must be used in a low-cost product, the cost of the circuits must be lowered as well. High-quality microwave switches are a key building block of communication systems as they perform the crucial task of switching between the transmit and receive modes. Microwave switches are commonly realized with high-quality p–i–n diodes. However, the large control currents required by these devices have traditionally necessitated the use of GaAs FET-based switches for most hand-held applications, due to their low dc power consumption [9]. In contrast, a SiGe switch designed to be part of a transceiver front-end for DECT and DCS-1800 applications, requires no external dc bias and gives 25 dB receiver insertion loss at the operating frequency, with 25 dB isolation [10]. Discrete passive components dominate in the RF part. More than 90% of all components are passive, and roughly 70% of the cost comes from these. The level of integration is increasing, but the most space consuming components—ﬁlters, resonators, matching circuitry, oscillators—are diﬃcult to integrate. Capacitors, resistors and inductors are needed for biasing, bypassing, and interference ﬁltering. The use of integrated spiral inductors in many RF applications can reduce the number of external elements and, by using the appropriate design technique, the overall noise behaviour of the circuit is minimized. 10.1.

SIGE: PERSPECTIVE FOR WIRELESS COMMUNICATION

In the beginning, SiGe HBT technology was investigated with a view to high-speed digital applications, which is the area that best ﬁts SiGe HBTs with low base resistance, low noise, excellent high-frequency response and large gain-bandwidth product. A 12-bit digital-to-analogue converter, designed and produced jointly by IBM and Analog Devices [11,12] was the ﬁrst commercially available SiGe IC until 1997. At that time, it matched the speed of the best such circuits built using GaAs technology, while operating at a lower voltage. This 1 Giga samples/s chip utilized 2854 SiGe HBTs and 1465 polysilicon resistors with three levels of metallization. In the intervening years, other companies such as TEMIC Semiconductors, Daimler–Chrysler and Hitachi have clearly demonstrated a high-performance SiGe HBT technology, now capable of mass production.

364

RF applications of SiGe HBTs

As of 2000, SiGe-based HBTs exhibiting fT and fmax values above 100 GHz (values which are 50% higher than the best Si BJTs, but some two to six times lower than the best GaAs devices). Only ﬁve years previously, many applications such as optical networks and wireless RF technology in the 1–20 GHz range, which had been diﬃcult to achieve with conventional CMOS and bipolar technologies, were demonstrated with SiGe HBT technology, as evidenced by reports of circuits for 20 Gb s−1 optical networks [13] and RF wireless circuits up to 24 GHz [14–17]. At that time, the availability of SiGe BiCMOS technology [18], with both very high-performance HBTs with fmax of 60 GHz and 0.25 µm Leﬀ CMOS for logic and memory, oﬀered the possibility of combining analogue and digital components on the same chip in a new ‘single chip’ architecture. The ﬁrst evidence that SiGe HBT technology can successfully compete with GaAs technology in the rapidly emerging wireless communication market, with comparable performance in high volume production, was ﬁrst demonstrated by Harame et al [19] using a commercial UHVCVD system for SiGe ﬁlm growth. Within ﬁve years, this technology has matured to a volume production, very high-performance SiGe BiCMOS process [20] which can be tailored for low-voltage, low-power RF and mixed-signal applications. The utilization of SiGe has modiﬁed the original market split between silicon and GaAs technology and allows for a silicon-based technology to address existing wireless communication market applications, as well as future requirements in the 5700–5800 MHz ISM band. The ﬁgures-of-merit that apply to SiGe HBTs for use in wireless communication ICs are: • • • • • •

cut-oﬀ frequencies beyond 100 GHz are possible; maximum frequency of oscillation beyond 100 GHz demonstrated; high transconductance and output resistance provide high voltage gain; high current density and high breakdown voltage combine for high output powers, particularly under pulsed condition; low 1/f corner frequency, low noise, and high nonlinearity provide excellent oscillator and mixer performance; high power added eﬃciency. The SiGe process provides the designer with additional beneﬁts:

• • • • • •

vertical npn HBTs having a small emitter size; lateral homojunction pnp; three types of resistors; nitride capacitors with high speciﬁc capacitance; on-chip spiral inductors with high-quality factors for the 1–10 GHz range; ESD structures to avoid damage to the IC;

SiGe: perspective for wireless communication • •

365

cost-eﬀective solutions as SiGe does not sacriﬁce the economies of silicon manufacturing; and high power output makes designs feasible which are now possible in GaAs only.

SiGe HBT bipolar/BiCMOS technology has a unique opportunity in the wireless marketplace because of its high-performance and integration/cost beneﬁts of silicon bipolar/BiCMOS [21]. It has been shown that low-noise operation, unparallelled in other bipolar devices, can be obtained in Si/SiGe double HBTs. A microwave noise ﬁgure below 1 dB at 10 GHz has been reported [22, 23]. Typical applications include integrated RF front-ends where low-noise ampliﬁcation is desired in addition to low phase-noise oscillation and mixing which typically beneﬁt from bipolar devices. SiGe HBT technology is also ideally suited to other analogue applications. These include high bandwidth ampliﬁers, mixers and voltage controlled oscillators, all key functions for radio frequency and low-end microwave communication systems. Power added eﬃciency (PAE), a key ﬁgure-of-merit for high bandwidth ampliﬁer design, has been measured to be as high as 70% in SiGe HBTs, nearly double that of silicon junction transistors and comparable to the ﬁgure-of-merit for GaAs MESFETs. Transistor noise often constrains the design of communication systems. Measurements of SiGe HBTs indicate that for low-frequency (less than 10 kHz) and high-frequency (2–10 GHz) noise, they are comparable to the best available GaAs devices. The microwave noise performance of SiGe HBTs has been evaluated on-wafer, for frequencies ranging from 2 to 26 GHz with corner frequencies as low as 300–400 Hz. Noise ﬁgures of 0.6 dB at 2 GHz and 1.2 dB at 10 GHz were found to be among the lowest reported for bipolar transistors in general. SiGe technology provides easy access to diﬀerent integrated active and passive devices. For high-frequency applications, most important are the SiGe HBT itself and the passive inductor, capacitor, and transmission line elements that are the key to RF design. Current gain, Early voltage and noise properties of SiGe HBTs are better compared to FETs and other bipolar technologies, resulting in a better phase noise performance in mixers and VCOs. The 1/f noise has an extremely low corner frequency for SiGe HBTs. For high-power applications, high gain, good eﬃciency and linearity are also obtained in SiGe. Table 10.2 shows a wide variety of circuits that have been demonstrated in the SiGe technology, showing the versatility of the technology and demonstrating performance and/or power improvement compared to other fabrications. BiCMOS also reduces component count and improves overall system performance by combining optimized functional blocks using either bipolar or CMOS [9].

366

RF applications of SiGe HBTs

Table 10.2. Demonstrated circuits using SiGe technology. (After Subbanna S et al 1999 IEEE ISSCC Tech. Dig. pp 66–7.) Circuit type Performance

Year

Process

1994

ADI/IBM

1995 1998

NORTEL/IBM Hitachi

1995

NORTEL/IBM

1996 1997

Hughes/IBM IBM

1996

Hughes/IBM

1999

Hitachi

1995

Philips

1996 1999

NORTEL/IBM IBM

1998

TEMIC

1996 1998

NORTEL/IBM Hitachi

1996

NORTEL/IBM

1998

IBM

D/A converter 12-bit, 1.2 Gbits s−1 , 750 mW Frequency divider Divide-by-128, 6.4–23 GHz, 1.5W Divide-by-8, up to 50 GHz, 226 mW FF−1 , 5.5 V Return-to-zero comparator 5 GHz, 1.5 V, 89 mW Monolithic VCO 12 GHz, l9 dBm, 5% tuning, −80 dBc phase noise 17 GHz, −110 dBc, on-chip LC resonator Active mixer 12 GHz, >0 dB gain @ +3 dBm LO ECL ring oscillator 6.7 ps, 0.25 V swing at 1.3 mA, 400 mV swing ECL ring oscillator 13.7 ps, 8 mA/stage, 200 mV swing LNA 2.4 GHz, 10.5 dB gain, 0.95 dB NF PCS CDMA, 12 dB gain, 13 dB NF, 3 V/5 mA, IIP3 > +10 dBm DECT, 1.8 GHz, 20 dB gain, 1.8 dB NF Broadband ampliﬁer 8 dB gain, 17 GHz BW, 16.8 mA @ 2.5 V 35 GHz BW, 270 mW Timing circuit 10 Gb s−1 , 150 mA @ 5 V Power transmitter 2.4 GHz, 1W Pout , 48% PAE, 3.5 V, @ 1.5 V 150 mW Pout W, 47% PAE

Technology comparison

367

Table 10.2. (continued) Circuit type Performance

Year

Process

1997 1999 1998

IBM IBM TEMIC

1998

IBM

1998

Hitachi

1997

Siemens

1998

IBM

1999

IBM

Power ampliﬁer Tx, 900 MHz, 70%PAE, 16 dB gain 30 dBm, 16 dB gain, 75% PAE, 3.5 V 27 dBm, 26 dB gain, 45% PAE, 3.6 V, 1.9 GHz CMOS ASIC chip Multiplexer 2:1, 40 Gb s−1 output Demultiplexer 1:2, 60 Gb s−1 output 5.5 GHz LNA 14.1 dB gain, 2 dB NF Mixer, VCO Mixer: 16.4 dB Power conversion gain, IIP3 11.1 dBm, NF 6.6 dB, <10 mA/3 V VCO:diﬀerential, 15% tuning range, −90 dBc Hz−1 @ 100 kHz oﬀset, 22 mW/3 V I/Q modulator/demodulator synthesizer chip 11 MBits s−1 radio bit rate

10.2.

TECHNOLOGY COMPARISON

Silicon bipolar IC processes tailored for low-voltage, low-power RF and mixed-signal applications have reached the performance and cost required for mass production of RF transceivers operating in the 1–2 GHz range. GaAs, which initially was the only contender above 2 GHz, is being challenged by small geometry SiGe HBTs. Table 10.3 summarizes the performance of competing technologies for RFIC applications. It is seen that Si technology compares extremely well with GaAs in terms of performance, with the advantage of providing an existing low-cost, high-volume production base. Also, miniaturization of CMOS devices has signiﬁcantly improved the CMOS

368

RF applications of SiGe HBTs

Table 10.3. Comparison of key ﬁgures-of-merit for diﬀerent technologies. (After Kermarrec C et al 1997 IEEE RFIC Symp. Dig. pp 65–8.)

Emitter size (µm) BVceo /BVDS (V) fT (GHz) fmax (GHz) Gmax (dB) @2 GHz @10 GHz Fmin (dB) @2 GHz @10 GHz IIP3/P1dB PAE(%) @3 V 1/f corner frequency (kHz)

SiGe HBT

Si BJT

AlGaAs/ GaAs HBT

GaAs MESFET

Si BJT BiCMOS

0.5 × 1 4 50 55 28 16 0.5 0.9 9 70 0.1–1

0.5 × 1 4 32 35 24 11

2×5 15 50 70 19 13 1.5

1.2 × 1.5 6 13 11 17 1

9

16 60 @ 5 V 1–10

0.5 × 5 8 30 60 20 13 0.3 0.9 12 70 10 000

0.1–1

9 40 0.1–1

IIP3: third-order input intercept point. PAE: power added eﬃciency.

RF characteristics [24]. Submicron low-voltage CMOS technologies have attained fT and fmax in excess of 40 GHz, less than 2 dB noise ﬁgure at 2 GHz, and excellent linearity up to 2 GHz. These will be discussed in section 10.3. SiGe HBTs oﬀer the high performance of GaAs devices with lower power consumption. In addition, these provide higher gain and less noise than silicon BJTs. These powerful features, combined with a cost and complexity level comparable to a silicon process, make SiGe BiCMOS technology an ideal solution for high-frequency applications, including cellular telephones and radio transceivers. The key to the replacement of GaAs with SiGe HBTs lies in the fact that SiGe not only oﬀers high speed, it also enables high levels of integration. For example, chips containing voltage controlled oscillator circuits are fully monolithic and contain no external components, such as inductors and varactor diodes. Fully diﬀerential architecture, which minimizes noise coupling from digital parts of a highly-integrated chip into a sensitive analogue VCO, has been possible in SiGe technology with minimum increase in power consumption. Noise is a very important parameter for telecommunication circuits and a minimum noise ﬁgure is commonly used to compare the noise performance of a technology [25]. For the realization of mobile communication products in the low GHz range, several technologies

MOS versus bipolar

369

Figure 10.2. Comparison of minimum noise ﬁgures of diﬀerent technologies. (After Plouchart J-O et al 1999 IEEE CICC Proc. pp 217–20.)

are available. The well-known GaAs technologies with MESFETs and heterostructures are in keen competition with Si and SiGe bipolar and CMOS technologies. Thus, an evaluation of the diﬀerent technologies with respect to noise performance is important. A comparison of minimum noise ﬁgures reported in various technologies is shown in ﬁgure 10.2. The minimum noise ﬁgure is close to that of a 0.5 µm MESFET technology and, due to lower parasitic, is better than that of GaAs HBT technology [26,27]. 10.3.

MOS VERSUS BIPOLAR

The availability of inexpensive, high-quality silicon wafers and an extensive manufacturing experience favours standard CMOS for most applications. At present, complex integrated circuits are fabricated almost exclusively in CMOS on standard silicon substrates. Low power consumption, high input impedance, excellent noise immunity, high integration levels and proven reliability are amongst the MOS attributes. With each new generation, there are improvements in speed, current drive and noise performance along with reductions in supply voltage. Recently, much attention has been paid to the development of dedicated RF CMOS technologies [28]. Building blocks implementing the RF and baseband circuits in a 900 MHz wireless transceiver have been developed. Many of the problem areas in the quest for a one-chip solution to cellular phones using CMOS technology are being researched with some success, but the design bottleneck, preventing further integration, is the

370

RF applications of SiGe HBTs

RF section, where the key issue is high-frequency performance. In 1996, a 1 µm CMOS circuit for a 900 MHz spread-spectrum wireless transceiver was demonstrated, showing the operation of an entire transceiver on a single-chip, to give a level of performance previously only possible by combining advanced silicon bipolar technology with specialized passive components [29]. However, recent miniaturization of CMOS devices has signiﬁcantly improved the CMOS RF characteristics. For example, typical values of fT and fmax for 0.25 µm n-MOSFETs already exceed 40 GHz, and those for 0.1 µm n-MOSFETs are more than 100 GHz [30]. The RF noise ﬁgure of the MOSFETs is less than 1 dB at 2 GHz operation. Modern wireless systems increasingly blend digital blocks into conventional analogue front-ends for frequency synthesis, adaptivity, multimode operation and detection. This raises questions such as how well digital CMOS circuits can coexist on the same chip as the RF front-end, or whether there is suﬃcient on-chip isolation. In conventional CMOS processes, circuits are built on silicon wafers about 500 microns thick, but all the circuitry is actually formed in the top 1 µm thick layer of the substrate. These standard silicon devices are far from ideal as the circuits interact with the conductive silicon substrate, causing many parasitic eﬀects. In particular, capacitance between the circuitry and the substrate causes power consumption to increase with switching speed and creates undesirable coupling between circuits. The bulk substrate’s dispersion of high-frequency signals precludes the construction of microwave devices. These eﬀects become more pronounced as advances in manufacturing technology lead to smaller transistor dimensions and lower operating voltages. Nevertheless, in the long run, CMOS technology is expected to overcome many of these problems by using alternative technologies and Si bipolar and GaAs technologies will ﬁnd themselves increasingly pressed by competition with CMOS in the 1–2.5 GHz frequency range. When transistors are fabricated in a very thin layer of silicon nearideal devices can be realized. This is the reason for the surge in interest in silicon-on-insulator technology. SOI circuits are attractive because of their enhanced performance for deep submicron CMOS. Over the past twenty years, a variety of possible structures based on the concept of a buried oxide have been researched, with the aim of separating the active device area from the silicon substrate. An early SOI process was siliconon-sapphire (SOS), in which a thin ﬁlm of silicon is grown on a sapphire wafer. SOS is an established technology used primarily in military and space applications, where its inherent resistance to the eﬀects of radiation is essential. While SOS has been proven manufacturable and has signiﬁcant performance advantages, it has seen little commercial use because it is unsuitable to the fabrication of the deep submicron transistors needed for modern, high-density circuits, principally because of the high density of defects at the silicon–sapphire interface.

MOS versus bipolar

371

Alternative technologies, such as wafer bonding or separation by implanted oxygen (SIMOX) [31], have been proposed to produce a thin silicon layer on top of a silicon–dioxide layer, on a bulk-Si substrate. However, crystalline silicon cannot be grown on amorphous silicon dioxide and both methods need an insulating oxide layer between the existing layers of silicon. In the wafer bonding process, two oxidized bulk wafers are bonded together. Polishing or etching the top wafer leaves a thin layer of silicon supported by the bottom wafer, but insulated from it by an oxide layer. This is a mechanical process, requiring an extremely clean wafer surface to prevent voids. Doping procedures used to control the etching of the thick upper wafer increase the defect density in the ﬁnal silicon layer. In the SIMOX process, oxygen atoms implanted just beneath the wafer surface create a thin, buried layer of silicon dioxide. High implant energies and multiple implant-and-anneal cycles are required, since the implantation process severely damages the silicon surface. The recent novel UNIBOND process uses deep implantation of hydrogen. After bonding and annealing, the wafers separate naturally at a depth deﬁned by the location of hydrogen microcavities. This mechanism has been given the acronym SMART-CUT [32]. SMARTCUT has a number of advantages as a production process. Perhaps the most signiﬁcant, from a CMOS scaling viewpoint, is the relative simplicity in realizing a speciﬁc combination of buried oxide thickness and Si layer thickness. All SOI technologies have been used for the fabrication of smaller transistors, particular deep submicron CMOS. It is in the highly competitive ﬁeld of low-power circuits that SOI is most attractive. SOI oﬀers the possibility to achieve the almost ideal subthreshold slope of 60 mV per decade at room temperature and consequent lower threshold voltage. Low leakage currents limit static power dissipation while the combined eﬀects of lower parasitic capacitance and reduced supply voltage minimize dynamic power dissipation. Some compromises in performance are however, inevitable. As silicon dioxide is a poor thermal conductor, selfheating eﬀects degrade transistor performance, as discussed in chapter 5. Although circuits in SOI material are better electrically isolated from the conductive silicon below, than those produced in bulk-Si wafers, they remain subject to many of the parasitic eﬀects seen in conventional bulksilicon circuits, although the reduced capacitance from the active device area to the substrate is a particular beneﬁt. However, high-frequency dispersion losses still persist. It is still a matter of considerable controversy whether or not SOI will hold the key to the future successful implementation of CMOS circuits when the gate length is shrunk even further. An excellent review of the state of the art and future of SOI technology, material and devices is given in [33]. Particularly novel applications of SOI in the future are likely to

372

RF applications of SiGe HBTs

include buried ground planes for reduction in cross talk [34], ultrathin layer MOSFETs [35] and eventually double gate transistors [36] for realization of volume inversion, leading to enhanced mobility, subthreshold swing and reduced 1/f noise. SiGe HBTs have also recently been successfully produced on SOI substrates fabricated using wafer bonding. Associated with this approach is the creation of thermal vias to remove heat from the SOI islands. Thermal vias have been produced with high breakdown voltage, and a factor of four improvement in thermal conductivity over a conventional buried oxide. The wafer bonding approach [37] can also permit the incorporation of a buried silicide layer above the insulator layer, to minimize collector resistance. Such is the ﬂexibility of this approach that the buried silicide can be created below the insulator layer (GPSOI). This substrate is intended for use as a buried ground plane in electronic systems that combine digital and analogue circuitry on the same chip. Measurements of cross talk on patterned GPSOI ground planes show world record suppression of cross talk at frequencies in the range 1–50 GHz [34]. The trade-oﬀ between the use of GaAs, Si bipolar and/or MOS devices for RF applications is a very complicated task due a number of factors. RF transceiver circuits have a very broad range of requirements, including noise ﬁgure, linearity, gain, phase noise and power dissipation. The advantages and disadvantages of each of the competing technologies Si-CMOS, BJTs, Si/SiGe HBTs, and GaAs MESFETs, p-HEMTs and HBTs has been examined recently by Larson in the light of these requirements [9]. CMOS technology development proceeds at a rapid pace, so any comparisons can only relate to the state of the art at a particular time. However, as an example, in a 1995 CMOS process, a 0.5 µm n-MOS device exhibited peak fT and fmax of approximately 20 and 40 GHz, respectively. By comparison, the peak fT and fmax of the corresponding npn bipolar transistor fabricated in a comparable process are 20 and 28 GHz, respectively. The improvement in microwave gain of MOS devices is primarily due to the lower gate resistance compared to the base resistance of a bipolar device. MOS devices exhibit a substantial speed advantage at low currents compared to bipolar devices, but bipolar devices exhibit better performance at low voltages as shown in ﬁgure 10.3. When properly scaled for width and normalized for power dissipation, MOS devices exhibit a slightly lower minimum noise ﬁgure than bipolar devices, but their associated optimum source resistance is not well matched to 50 Ω (close to an open circuit because of the low equivalent input noise current), making optimum low-noise impedance matching diﬃcult. The optimum source impedance can be moved closer to 50 Ω in a MOS device, but only at the expense of increased power dissipation or noise ﬁgure [38]. With SiGe, there are excellent prospects of rejuvenating CMOS technology. The major potential market for heterostructure FETs

MOS versus bipolar

373

Figure 10.3. Measured high-frequency performance of Si BJT and n-MOS devices: (a) fT and fmax versus collector/drain current; (b) fT = fmax versus collector/drain voltage. (After Larson L E 1998 IEEE J. Solid-State Circuits 33 387–99.)

374

RF applications of SiGe HBTs

(discussed in chapters 6 and 7) is for low-power applications. The enhanced carrier mobility in strained group IV alloy layers, particularly at low vertical ﬁelds, is useful for high-speed low-voltage and low-power circuits involving MOSFETs [39]. The ability to integrate SiGe-channel p-MOSFETs with CMOS is a great advantage over III–V technologies and opens up the possibility of SiGe ultimately receiving a larger market share than III–Vs. Higher mobility improves the p-MOSFET performance, and gives rise to better linearity, higher current drive, better noise performance and reductions in the supply voltage. Figures 10.4, 10.5 and 10.6 compare the enhanced eﬀective hole and electron mobilities measured in various MOSFET/MODFET structures demonstrated in SiGe technology. It is possible to design layer structures with both electron and hole channels with balanced conductance, therefore allowing high-performance heterostructure CMOS designs. The possibility of matched n- and pchannel performance in CMOS considerably facilitates the design of ampliﬁers, mixers and ﬁlters. Major problems of integration of strained

Figure 10.4. Reported experimental hole eﬀective mobilities at room temperature obtained in pseudomorphic Si/Si1−x Gex /Si structures plotted against eﬀective ﬁeld (Eeﬀ ). The bars indicate the range of Eeﬀ values present in micropower, 1 and 0.1 µm CMOS technologies. (After Parker E H C and Whall T E 1999 Solid-State Electron. 43 1497–506.)

SiGe BiCMOS technology

375

Figure 10.5. Reported experimental hole eﬀective mobilities at room temperature in compressively strained Si1−x Gex and tensile strained-Si grown on virtual substrates with terminating composition Si1−y Gey . The upper section shows mobilities for remote-doped hetero-interface and the lower section for oxide-gated/strained-Si (tensile) interfaces. (After Parker E H C and Whall T E 1999 Solid-State Electron. 43 1497–506.)

layers into a CMOS production line are: (i)

the structures should be as far as possible compatible with conventional processing; (ii) the high thermal budgets used in present CMOS production are not ideal for strained layers and may cause strain relaxation or diﬀusion; (iii) any strained layer incorporated must be below the equilibrium critical thickness, otherwise dislocations and defects will result reducing performance and yield. 10.4.

SIGE BICMOS TECHNOLOGY

To retain the yield in the basic CMOS process, it is important to keep the actual physical process steps the same, as far as possible (see ﬁgure 10.7). Several SiGe bipolar-only processes have been proposed or are in development. Robust and manufacturable SiGe HBT technologies, potentially suitable for commercial applications, now exist in the US, Europe and Japan [13, 19, 26, 40–44]. SiGe HBTs can be integrated with

376

RF applications of SiGe HBTs

Figure 10.6. Reported experimental electron eﬀective mobilities at room temperature in strained-Si grown on virtual substrates with terminating composition Si1−y Gey . The upper section shows mobilities at remote-doped hetero-interface and the lower section refers to oxide-gated/strained-Si (tensile) interfaces. (After Parker E H C and Whall T E 1999 Solid-State Electron. 43 1497–506.)

Figure 10.7. SiGe BiCMOS process modules in comparison to CMOS. (After Subbanna S et al 1999 IEEE ISSCC Tech. Dig. pp 66–7.)

SiGe BiCMOS technology

377

conventional CMOS silicon circuits to form a BiCMOS technology in which the bipolar transistors. SiGe HBTs can be exploited for critical highspeed analogue or digital functions and the silicon CMOS can serve for very high-density memory or compact on-chip signal processing functions in system-on-a-chip (SOC) applications. This ability sets SiGe HBT technology apart from the competing III–V technologies, which cannot supply the high-quality native oxide essential to implementations in CMOS. At the time of completing this book, IBM [45] have developed and reported a production technology, based on 15 years research and development and four generations of scaling CMOS compatible SiGe technology. Performance of the SiGe HBT can be optimized to a particular application, and both fT and fmax of 90 GHz have been simultaneously achieved in a single transistor, with 0.18 µm lithography [46]. IBM’s SiGe BiCMOS technology with 3.3 V, 0.5 µm CMOS is a unique and versatile process integrating high-performance SiGe HBTs [20]. The standard device (3.3 V/50 GHz) is targeted at high-speed, small-signal applications, while a high breakdown device (5.8 V/30 GHz) is targeted at power ampliﬁer applications. Table 10.4 summarizes the key ﬁguresof-merit. The SiGe HBT can operate at current densities in excess of 1.5 mA µm−2 and with near perfect ideality and ﬂat β over a current range of seven orders of magnitude. Unique to the SiGe HBT is the fact

Table 10.4. Summary of the key ﬁgures-of-merit of the devices realized in SiGe BiCMOS technology. SiGe HBTs (npn)

Small-signal/low voltage high-speed device

High power/high voltage low-noise device

VA

3.3 V 100 47 GHz 65 GHz @ Vbc = 1 V Vbe = 0.72 V 65 V

5.5 V 80 30 GHz 55 GHz @ Vbc = 1 V Vbe = 0.72 V 124 V

FETs

n-FET (W/L = 10 µm/0.5 µm)

p-FET (W/L = 10 µm/0.5 µm)

Tox Leﬀ Gm,sat VT,lin Rext ID,sat

7.8 nm 0.39 103 mS mm−1 0.55 V 500 Ω mm−1 400 µA mm−1

7.8 nm 0.39 180 mS mm−1 0.6 V 500 Ω mm−1 400 µA mm−1

BVceo Gain fT fmax

378

RF applications of SiGe HBTs

that β also remains virtually ﬂat over a broad temperature range. Because of its large peak fT , the SiGe HBT retains signiﬁcant high-frequency performance even at low currents, allowing the designer the choice to tradeoﬀ speed for low-power operation. This HBT and CMOS integration, without any loss of HBT performance, makes it possible to implement a complete system on a chip with, for example, high-performance analogue functionality and A/D conversion implemented using the SiGe HBT device, combined with CMOS for digital signal processing. 10.5.

RF CIRCUITS

In this section, we discuss some of the technology considerations involved in the implementation of key wireless system building blocks. 10.5.1.

Low-noise ampliﬁers

Low-noise ampliﬁers are one of the key building blocks in an RF system. They are required to contend with a variety of signals coming from the antenna, often of larger amplitude than the desired signal and hence both low noise and high linearity are required simultaneously. These requirements are often contradictory with an additional requirement for low-power dissipation. The radio signal received at the receiving antenna is sent to the LNA, whose purpose is to boost the signal level without reducing the signal-to-noise ratio signiﬁcantly. The signal level at the antenna can range between 1–100 mV rms. At the low end of the signal range, the LNA performance is fundamentally limited by thermodynamic issues, while at the high end of the signal range, the challenge is to minimize the eﬀects of nonlinearities on receiver performance. The measures for these requirements are the ampliﬁer noise ﬁgure, which determines the minimum detectable signal (MDS), and the third-order input intercept point (IIP3). In addition, high gain and low dc power consumption are other requirements of an LNA. A very simpliﬁed expression for transistor minimum noise ﬁgure, which is applicable to both BJTs and FETs, is given by [47] f NF ≈ 1 + kgm rb/g (10.1) fT where gm is the device transconductance, rb/g is the base or gate resistance, depending on whether the device is a bipolar transistor or FET, and k is a material-dependent constant. Clearly, the noise ﬁgure of the ampliﬁer will be improved by employing a technology that operates with as low a resistance as possible at a given current [1]. Low-noise ampliﬁcation at microwave frequencies has been the exclusive domain of MESFETs and HEMTs. Bipolar transistors are traditionally excluded from these

RF circuits

379

applications despite their popularity in other analogue circuits in the lower microwave range. The outstanding high-frequency performance of Si/SiGe HBT technology has been well established [11, 21]. In addition, for a given required fT or fmax , SiGe HBTs require roughly one third the collector current of an ‘equivalent’ Si BJT for equivalently sized devices. In many applications, this speed performance advantage can be ‘traded oﬀ’ in a very satisfactory way for reducing the power dissipation. It is at these low-power levels that Si/SiGe HBT technology has a distinct advantage compared to Si BJT or CMOS technology. As a result, technology scaling will have a signiﬁcant impact on LNA performance, as has been shown in a review by Larson [9]. Figure 10.8 plots ampliﬁer gain/dc power dissipation (in dB mW−1 ) as a function of noise ﬁgure (in dB) for a variety of reported LNAs in silicon and GaAs technology at 2 GHz. However, one must be careful in comparing reported circuit performance, since it represents an intermingling of intrinsic device performance, process features and circuit design. Nevertheless, by comparing the best reported results in each technology, the fundamental device performance limits can be assessed. These results demonstrate the potential performance advantage of SiGe technology at this frequency, if dc power dissipation is a major consideration.

Figure 10.8. Gain-to-dc power ratio plotted versus noise ﬁgure for state-of-the-art 2 GHz LNAs. Note that the SiGe HBT circuit provides the best result when power dissipation is a critical factor. (After Larson L E 1998 IEEE J. Solid-State Circuits 33 387–99.)

380

RF applications of SiGe HBTs

Because of the extreme dynamic range considerations of the lownoise front-end, linearity is an equally important ﬁgure-of-merit for LNAs. In this case, a linearity ﬁgure-of-merit is the ratio of the input third-order intercept point (IIP3) to the dc power dissipation. Fieldeﬀect transistors generally exhibit improved third-order intermodulation distortion compared with bipolar devices, due to their near square-law current versus voltage behaviour. On the other hand, bipolar transistor ampliﬁers have demonstrated outstanding linearity performance as well, apparently due to the partial cancellation of the resistive and capacitive nonlinearities in the emitter–base junction at certain frequencies [48]. Figure 10.9 compares this linearity ﬁgure-of-merit for a variety of recently reported monolithic LNA circuits, all operating at approximately 2 GHz. As with the case of noise ﬁgure, the performance advantages of SiGe and GaAs technologies are signiﬁcant if dc power dissipation is a critical parameter, although the improvement is less dramatic. The best LNA results have a ratio of IIP3/dc power of approximately 0.15, as shown in ﬁgure 10.9. The gain characteristic of a SiGe LNA, with a 19 dB gain and 1.7 dB noise ﬁgure, is shown in ﬁgure 10.10. SiGe LNAs have even been implemented at even higher frequencies. A 5.8 GHz LNA [49] with a

Figure 10.9. Ampliﬁer linearity ﬁgure-of-merit plotted for the same monolithic 2 GHz ampliﬁers. The best results fall on a line of approximately 0.15 mW mW−1 . The advantages of SiGe HBT technology are not as dramatic. (After Larson L E 1998 J. Vac. Sci. Technol. B 16 1541–8.)

RF circuits

381

Figure 10.10. Performance characteristics of a low-noise ampliﬁer in a SiGe front-end. (After Bopp M et al 1999 IEEE ISSCC Tech. Dig. pp 68–9.)

minimum noise ﬁgure of 1.65 dB and an associated gain of 15 dB dissipates only 13 mW from a 1 V supply (with only 9 mW in the gain stages), while a 6.25 GHz monolithic LNA [50] operating from a 2.5 V supply shows a minimum noise ﬁgure of 2.2 dB and an associated gain of 20.4 dB. 10.5.2.

Power ampliﬁers

The power ampliﬁer (PA) is a component of the total RF system that takes the signal to be transmitted and ampliﬁes it to the necessary level needed to drive the antenna. For applications requiring moderate-to-high output power, the PA contributes signiﬁcantly to the total transceiver power consumption, making the PA eﬃciency crucial to the overall system performance. The total power consumed by the PA is greater than the power output, as there will always be some power consumed in the active devices and peripheral circuitry. Because the power output speciﬁcation itself is often larger than the power consumption of the rest of the blocks in the RF system, and the power consumption of the PA will be greater than the speciﬁed power output, the PA is decidedly the major power consumer of the system [51]. The integration of the PA also remains a diﬃcult challenge. Power ampliﬁers need to deliver a wide range of output powers to the antenna, as the user moves throughout the cell site. The eﬃciency deﬁned in traditional approaches (e.g., classes A, B, AB and C), is often optimized merely at the maximum output power. Three diﬀerent types of eﬃciency are generally quoted. Firstly, the collector/drain

382

RF applications of SiGe HBTs

eﬃciency, ηc/d which is deﬁned as [52] ηc/d =

Prf,out Pdc

(10.2)

where Prf,out is the power delivered to the load at the desired RF frequency and Pdc is the total power taken from the dc supply. Secondly, the power added eﬃciency (PAE) of a power ampliﬁer is given by the well-known expression Prf,out − Prf,in (10.3) P AE = Pdc where Prf,in is the power needed to drive the input. Thirdly, the overall eﬃciency is deﬁned as Prf,out . (10.4) η= Pdc + Prf,in Both the PAE and the overall eﬃciency are better gauges of the true performance of a PA, since they include the power needed to drive the PA in the determination of the eﬃciency. The complications associated with power ampliﬁers for RF applications are challenging, as in the case of LNAs. The PA must satisfy the requirements of linearity, gain, output power and power added eﬃciency. In addition, mobile applications which require a lower power supply (3 V and even lower), have made it diﬃcult to maintain the required output power and eﬃciency due to impedance matching limitations. Ideally, the PAE of the ampliﬁer should not degrade signiﬁcantly, as the output power varies from near zero to its maximum value. In the past, a host of diﬀerent architectures in which a PA could be implemented have been proposed [53]. The number of diﬀerent types of classes of power ampliﬁers is too numerous, and they range from entirely linear to entirely nonlinear, as well as from quite simple to a very complex one. A class A PA is the simplest and most basic form of power ampliﬁer. In a class A operation, the transistor is in its active region for the entire input cycle, and thus is always conducting current. As such, the device maintains approximately the same gain throughout the entire region and, in the case of a MOS device, is linear in that region. The problem with class A structures, however, is their inherently poor eﬃciency since it is on at all times, and the current represents a continuous loss of power in the device. The eﬃciency of an RF class A PA is limited to 50%. As a result, class A ampliﬁers are used only in those situations where the linearity requirements are stringent. In a class B structure, there are two devices: one which provides current to the load during the positive half cycle and one which removes current from the load during the negative half cycle. The structure is usually called a push–pull structure. When no signal is applied, however,

RF circuits

383

there is no current ﬂowing, as both the devices are biased at their turn-on voltages. As a result, in an ideal case, any current through either device goes directly to the load, and thus attempts to maximize the eﬃciency. Although this is generally a linear ampliﬁer, there is an instant during each cycle when both devices are oﬀ, which produces distortion in the output known as crossover distortion. This architecture allows for very high eﬃciencies, as theoretically the eﬃciency can approach 78%. Hence, this architecture can be useful in applications where the linearity requirements are a little less stringent. In situations where the linearity is still an important issue, the class AB structure, a cross between a class A and a class B structure, is used. The above classes are examples of linear structures, where the output amplitude and phase are linearly related to the input amplitude and phase. In a communication system, power ampliﬁers are used to amplify the signal to the proper power level to reliably transmit the signal which is often quite high. In many applications, the amount of power consumed by the ampliﬁer is not critical, as long as the signal being transmitted has adequate power. However, in a situation where there is a limited amount of energy available, e.g., in mobile communication systems, the power consumed by all devices must be minimized in order to maximize the length of time for which that energy is available. Power ampliﬁers are typically operated in class AB mode for most RFIC applications, in an attempt to achieve a compromise between linearity and power added eﬃciency. In this case, the factors of key importance for ampliﬁer performance are the transistor speciﬁcation (for high power gain), linearity (for lowest possible adjacent channel interference) and breakdown voltage (BVceo for bipolar devices). However, the breakdown voltage has become less critical for handsets in recent years, due to the reduction of operating voltages in most handheld units. In cases where linearity is not critical, and eﬃciency is highly critical, class C power ampliﬁers are used. A class C power ampliﬁer is the most basic of the nonlinear power ampliﬁers used at RF frequencies. This architecture is based on the idea of a class B structure, where the device is biased at the edge of conduction and the device conduction angle is less than 180◦ . As a result of the pulsed nature of the output current, the input and output voltages are not linearly related, and the output of the PA will be highly distorted if the input voltage amplitude changes. Since gain is very critical for achieving the best performance, most high-performance power ampliﬁers in the 2 GHz frequency range have been implemented in GaAs or SiGe technology, to achieve the highest possible power added eﬃciency. At lower frequencies, silicon MOS devices are often employed for power ampliﬁers because of their low cost and robust operation, despite their poor performance compared to GaAs technology. A comparison of monolithic power ampliﬁer performances for mobile

384

RF applications of SiGe HBTs

Table 10.5. Summary of maximum PAE, Pout at maximum PAE, gain, PAE at 3 dB compression and Pout at 3 dB compression under four biasing conditions, tuned for maximum PAE. (After Greenberg D et al 1997 IEEE IEDM Tech. Dig. pp 799–803.) Bias (mA)

Maximum PAE (%)

Pout @ maximum PAE (dBm)

Gain (dB)

PAE @ 3 dB (%)

Pout 3 dB (dBm)

2 (B) 6.5 (AB) 12.5 (AB) 25 (A)

69 60 52 42

15.2 15.2 15.2 15.2

24.9 28.9 29 30.1

67 48 42.3 26.2

14.2 12.3 12.9 12.7

telephone PHS applications at 1900 MHz, where the adjacent channel leakage speciﬁcation of 55 dBc is speciﬁed at 600 kHz from the carrier centre, is available in [54]. Power ampliﬁers with high breakdown voltage (6 V) HBTs for 3 V wireless applications have been demonstrated in IBM’s 200 mm SiGe technology [55]. At 0.9 GHz and 1.8 GHz, excellent power densities of up to 1.36 mW µm−2 , an outstanding PAE reaching 70% and no performance degradation in integrating the HBT with CMOS have been observed. These results suggest that SiGe can meet the demands of many large-signal wireless applications. Table 10.5 summarizes the peak PAE and 3 dB compression point load–pull data for the four biases tuned for maximum PAE. Despite the extra processing steps associated with integrating a SiGe HBT process with CMOS, it was observed that the BiCMOS version achieves virtually identical performance to the device from the HBT+pFET process. The detail of the HBT+p-FET and BiCMOS processes used to fabricate the devices may be found in [56]. A fully integrated RF transceiver for a DECT application [8] comprises two bipolar ICs including a power ampliﬁer, a low-noise ampliﬁer and a VCO. The SiGe HBT power ampliﬁer has a 33 dB small-signal gain, 38% max PAE and 26.6 dBm saturated output power at a 3 V supply. The performance of the transceiver is shown in ﬁgure 10.11. 10.5.3.

VCOs and frequency synthesizers

The voltage controlled oscillator (VCO) represents one of the most diﬃcult challenges for a design engineer. The ideal VCO output should exhibit no phase noise, tune over a ﬁxed frequency range and be insensitive to temperature, process drift, output loading or power supply variations. While hybrid VCOs, which typically employ discrete silicon bipolar

RF circuits

385

Figure 10.11. Performance characteristics of a power ampliﬁer in SiGe front-end. (After Bopp M et al 1999 IEEE ISSCC Tech. Dig. pp 68–9.)

transistors, high-quality surface mount inductors and varactor diodes, and are temperature compensated and laser trimmed to the proper centre frequency, closely match these ideal conditions, monolithic integrated VCOs suﬀer from low-quality monolithic inductors and varactor diodes and a diﬃculty in trimming the centre frequency to accommodate its inevitable drift due to process variations [57, 58]. The quality factor of the VCO resonator, which is mostly determined by the inductor in the resonator, is especially important due to its eﬀect on the phase noise of the resulting oscillator. A simpliﬁed expression for oscillator phase noise, in good agreement with experimental data over a broad range of oscillator circuits, derived by Leeson [59] to account for ﬂicker noise is given by 2 ωo ωc Sφ (ωm ) = S∆θ 1 + 1+ (10.5) 2Qωm ωm where Sφ (ωm ) is the output power spectral density at frequency ωm oﬀset from the oscillator centre frequency, S∆θ is the power spectral density of the oscillator input phase error, Q is the resonator loaded quality factor, ωo is the centre frequency of the oscillator output and ωc is the ﬂicker noise corner frequency. Several VCO conﬁgurations have been implemented in SiGe technology. Monolithically integrated 26 GHz and 40 GHz VCOs were fabricated on high resistivity substrates using SiGe HBTs and on-chip varactors. A hybrid 8–12 GHz VCO has also been built using a SiGe HBT in common-emitter conﬁguration [60]. With a tuning range of more than 3 GHz, the output power behind an on-chip 10 dB attenuator reached −13 dBm. The transistors had an fmax of approximately 60 GHz, and were operated in common-emitter series feedback conﬁguration.

386

RF applications of SiGe HBTs

A 2.4 GHz VCO for wireless local loop (WLL) applications, with a power dissipation of 28 mW and phase noise of −110 dBc Hz−1 (at 1 MHz oﬀ carrier), has been fabricated using RPCVD-grown SiGe HBTs and a resonator consisting of a chip varactor and a microstrip line inductor [61]. An 11 GHz 3 V SiGe VCO with integrated resonator has been reported by Soyuer et al [62] with a fully diﬀerential architecture. This architecture minimizes noise coupling from digital parts of a highly-integrated chip into a sensitive analogue VCO. The added circuitry of a fully diﬀerential architecture typically comes at the cost of increased power levels, but SiGe achieves this result with minimum increase in power consumption. In the case of SiGe, the VCOs are fully monolithic and contain no external components, such as inductors or varactor diodes. Recently, IBM has reported a VCO operating at 17.1 GHz, an ultrahigh transmission frequency recently allocated for wireless uses in Europe (HiperLAN). The record setting VCO, operating on a single 3.3 V supply, could be tuned over a 600 MHz range and exhibited a phase noise of −104 dBc Hz−1 at a 1 MHz oﬀset from centre frequency, with an output power of −5 dBm, dissipating only 65 mW. Another VCO, tuned for a new American standard of 5.x GHz (U-NII), has also performed exceptionally well, with a tuning range of 840 MHz and a phase noise of −115 dBc Hz−1 at 1 MHz oﬀset at the centre frequency of 5.6 GHz [63].

10.6.

PASSIVE COMPONENTS

The demands placed on portable wireless communication equipment include low cost, low voltage, low power dissipation, low noise, high frequency of operation and low distortion for bandwidth reduction. These design requirements cannot be met satisfactorily without the use of RF inductors. Spiral inductors have found an important place in the wireless communications market, where they can be used to improve the performance of key RF building blocks. Since the introduction of spiral inductors, many authors have reported higher performance inductors on Si substrates, using advances in processing technology [64]. Inductors up to about a 10 nH range in a reasonable area, with Q limited to about 5 at 1 GHz and 10 at 2 GHz by metal series resistance for standard technologies have been achieved. This has included: (i) higher conductivity metal layers to reduce the loss of the inductor; (ii) multi-layer metal to either shunt inductors to reduce loss, or to reduce the area; (iii) low loss substrates to reduce losses in the substrate at high frequency; and (iv) thick oxide to isolate the inductor from the lossy substrate.

Passive components

387

Table 10.6. Passive components and diodes realized in SiGe BiCMOS technology for RF communication systems. (Source: IBM.) Spiral inductors 2-turn: 4-turn: 6-turn: 8-turn:

Q Q Q Q

(12 GHz) = 10, 1.5 nH (2 GHz) = 7.5, 4.2 nH (1 GHz) = 5.8, 9.8 nH (1 GHz) = 5.2, 16.6 nH

Capacitors MIS capacitor MIM capacitor

C = 1.5 fF µm−2 C = 0.7 fF µm−2

Resistors Polysilicon resistors Implant resistors

340 Ω/square and 220 Ω/square 1.7K Ω/square, 23 Ω/square and 8 Ω/square

Diodes Schottky barrier diode PIN Varactor ESD

Vf = 300 mV@100 µA Vf = 790 mV@100 µA 1.4 fF µm−1 @ 0 V, Vf = 810 mV @ 100 µA 2000 VHBM

In table 10.6, the performances of several passive components and diodes realized in IBM’s SiGe BiCMOS technology for RF communication systems are shown. Self-resonance due to the large parasitic capacitance to the substrate is a substantial problem, and Q drops to about 2 for a 10 nH inductor in a typical technology. Since the inductor is usually used to match impedance or to tune a gate or base diﬀusion capacitance, the parasitic capacitance can usually be incorporated in the design process, as long as the self-resonant frequency is far above the frequency of interest. The lossy silicon substrate makes the design of high Q reactive components diﬃcult. Despite this diﬃculty, the low cost of silicon IC fabrication over GaAs IC fabrication and the potential for integration with baseband circuits make silicon the process of choice. Accordingly, the use of silicon spiral inductors has proliferated in recent years [65]. Onchip inductors are necessary for matching networks and LC resonators for silicon-based RFICs for wireless communication ICs. Transmission lines with losses of less than 1.5 dB cm−1 measured up to 20 GHz have been realized. This value is comparable to III–V technologies and is an order of magnitude better than conventional silicon.

388

RF applications of SiGe HBTs

Another important issue is whether microwave transmission line losses caused by the conductive silicon substrate will limit the highfrequency response of SiGe HBT ampliﬁers. Several research groups have explored the use of high-resistivity Si substrates for the realization of SiGe MMICs, but very high resistivities (>20 Ω cm−1 ) of the substrate lead to severe processing problems associated with such wafers (speciﬁcally slip dislocations and warpage). 10.7.

COMMERCIALLY AVAILABLE PRODUCTS

IBM and Daimler–Chrysler have been involved in the SiGe area for a long time. Corporations such as Lucent, Motorola, ST-Microelectronics, Philips, Inﬁneon, Maxim, Temic, Hitachi and many others have recently begun development or deployment of SiGe-based HBT processes, and are likely to make the transition from present eﬀorts in discrete technology to integrated SiGe BiCMOS technology. SiGe-based mixed-signal technology is rapidly making its way into the consumer mainstream, at the high end of the telecommunications market. Present trends indicate that SiGe technology will ﬁnd applications in the frequency range 2–30 GHz, above which GaAs is well established. Components for personal communication services devices operating between 1.8–2.2 GHz are a fast growing market segment, along with pagers and wireless local area networks. Other wireless opportunities might include direct-broadcast satellite TV and local multipoint distribution services (LMDS). Devices based on SiGe technology will be able to move data across networks at speeds traditionally considered beyond the reach of silicon technology. This will bring better performance at low costs to ﬁbre transport networks, high-speed cellular voice/data phones and wireless devices such as global positioning satellite (GPS) receivers. Another application is a diﬀerential global positioning system (DGPS) satellite receiver that uses several GPS channels centred on 1.5 GHz. A related product is targeted for the automobile industry, which has signiﬁcant potential to use wireless technology for traﬃc management and control, and collision avoidance systems. Inexpensive 24 GHz collision warning radar systems for mainstream automobiles are also needed. 10.7.1.

TEMIC Semiconductors

Temic Semiconductors supplies integrated circuits to the communications, automotive, data processing and aerospace markets. As a leader in SiGe technology, it provides high-performance SiGe solutions in highvolume production. Its SiGe process is a suitable technology for RF chip applications. It provides signiﬁcant cost beneﬁts on the component and system level side versus GaAs and, in a market where prices are falling, this will be the key issue for manufacturers. The SiGe process for high-

Commercially available products

389

volume production was set up on a well-proven ultrahigh-frequency (UHF) process. The wafer fabrication uses a progressive and widely automated 6 in wafer line, high-volume quantities can be provided reliably. Temic Semiconductors replaced the usual GaAs PA and LNA devices by SiGe integrated solutions in the frequency range of 400–2400 MHz. Thanks to SiGe, the U7004B, U7006B, T7024 and T0980 provide extremely low noise ﬁgures (e.g., 1.6 dB at 1.9 GHz in 50 Ω systems) and high integration. Figure 10.12 shows a typical application circuit using the U7004B SiGe front-end IC. As the LNA, PA and transmit–receive switch driver are included, a large number of external components, and thus system cost, can be saved. They also provide very eﬃcient power ampliﬁers. The PAE of the T0980 front-end for 400 MHz reaches a typical value of 60%.

Figure 10.12. Application circuit using U7004B SiGe front-end IC. (After Temic Semiconductors, Germany.)

390

RF applications of SiGe HBTs

Solutions using GaAs devices are expensive and normally require a negative auxiliary voltage. The front-end ICs U7004B, U7006B, T7024 and T0980 manufactured in SiGe technology need only a single, positive 3 V supply voltage. This results in lower system and production costs as well as extended talk and standby times due to the low current consumption. The TST091x family members enable the cost-eﬀective production of a new mobile phone generation. End products are expected to be smaller and lighter as 3 V operation makes use of a single battery cell. The high PAE and low-power operation of SiGe PAs allow for longer talk times. Since SiGe does not require negative supply voltage or a battery disconnect switch as needed by competing devices using GaAs technology, both system and production costs will be reduced. Temic Semiconductors oﬀers SiGe PAs for single-band operation in the 900 MHz frequency range (GSM 900) and GSM 1800/1900, as well as for dual-band operation (GSM 900 and 1800/1900). With the CW capable T0930, Temic provides a high-performance, SiGe integrated solution with maximum eﬃciency for two-way pagers. A power ampliﬁer, RF power control and a standby circuit are included. With SiGe, the current consumption in power-down mode is signiﬁcantly reduced, eliminating the need for a high-side switch. This results in less external components—board space, and thus overall size can be reduced dramatically. The LNAs TST095x with a two-stage ampliﬁer and switchable gain provide the perfect combination of low noise (NF = 2.2 dB in high gain mode), large signal capability (IIP 3 = −7 dBm in low gain mode) and high reverse isolation (minimum −40 dB). Both the low current consumption and power-down function help to extend battery lifetime. 10.7.2.

IBM

The mainstream SiGe chips introduced by IBM include basic building blocks—low noise ampliﬁers, voltage controlled oscillators, power ampliﬁers and discrete transistors. SiGe is well suited to realize innovative highfrequency products, e.g. antenna switches for the transmit/receive path, satellite communication applications or wireless local area networks. Several of the chips are designed as low-cost, highly-reliable direct replacements for gallium arsenide parts for a broad spectrum of communications applications and are listed below. Several system-level hardware and software products [66] are now in production and a brief list is given in table 10.7: • • • •

SiGe SiGe SiGe SiGe

3 V GSM tri-band low-noise ampliﬁer 3 V tri-band image reject mixer with low-noise ampliﬁer 3 V GSM tri-band voltage controlled oscillator PDC linear power ampliﬁer

Commercially available products • • •

391

SiGe high dynamic range 1900 MHz low-noise ampliﬁer SiGe high dynamic 900 MHz low-noise ampliﬁer SiGe high dynamic range low-noise transistor

IBM has also been a partner in a number of collaborative ventures, involving application of their SiGe technology to other companies products. Alcatel has developed several 40 Gb s−1 SONET optical data transmission systems operating with the bit decision circuit based upon the IBM 50 GHz SiGe technology. A Harris Prism II chip set, a low-cost wireless local area network (WLAN) product operating on the IEEE 802.11 standard at 2.4 GHz, has been converted to SiGe technology. A factor of two reduction in chip count and cost, a factor of four improvement in range and a ﬁvefold increase in bit rate have been achieved. A recent announcement by Siemens revealed the use of the IBM SiGe technology in developing third-generation (3G) cellular base station electronics. As 3G is a wideband CDMA protocol, the combination of high linearity at low power makes SiGe technology extremely well suited to this application.

Table 10.7. A brief listing of mixed-signal SiGe-based product oﬀerings and their market status. (After Meyerson B S 2000 IBM Res. Dev. J. 44 391–420.) Company

Product category

Description

AMCC

Wired

Alcatel

Wired

Harris Intersil

Wireless

IBM Leica Siemens

Wireless

3.2 Gb s−1 17 × 17 diﬀerential crosspoint switch OC-192 SONET/SDH transimpedance ampliﬁer OC-48 multi-rate clock and data recovery solution multi-rate OC-48 transceiver 2.5 Gb s−1 multi-rate clock recovery and limiting ampliﬁer device 3.3 V OC-48 transimpedance ampliﬁer for WDM and TDM applications Complete 10 Gb s−1 SONET system with all electronics PRISM II chip set 11 Mb s−1 (5 ICs 5 complete data comm radio operating at 2.4 GHz bands up to 11 Mb s−1 ) Power ampliﬁer and detector (SiGe) RF-to-IF converter (SiGe) I/Q modulator/demodulator and synthesizer (SiGe) Direct-conversion digital GPS receiver and GPS engine Third-generation mobile cellular base station

Wireless

392 10.8.

RF applications of SiGe HBTs SUMMARY

In applications, SiGe-based devices and circuits represent an outstanding extension of conventional Si technologies, opening up frequency ranges which have previously only been the domain of III/IV compound semiconductors such as GaAs. SiGe HBT technology has the potential to revolutionize high-frequency transceiver design in a way comparable to the revolution in digital integrated circuit technology brought about by CMOS in the 1970s. Its unique combination of outstanding high-frequency performance, low manufacturing cost and high yield will provide abundant opportunities for new architectures and new systems in the near future. Many semiconductor companies, other than IBM and TEMIC, have recently begun development or deployment of SiGe-based technology and are likely to make the transition from discrete technology, particularly in BiCMOS applications. In the longer term, heterostructure CMOS technology may well take over at even higher frequencies. For mobile applications, the recent announcement of commercially viable implementation of silicon-on-insulator technology will have far reaching consequences in the semiconductor industry. The harnessing of SOI technology will result in faster chips that also require less power—a key requirement for extending the battery life of small handheld devices that will be pervasive in the future. Research on fabricating SiGe devices in a thin layer of silicon on top of an insulator (such as silicon oxide) has been initiated. If it becomes successful, this breakthrough may advance the microelectronics technology one or two years ahead of where it would have been with conventional bulk-Si technology. As early as 1995, IBM reported at the Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) that they believed an important application of SiGe technology will be a ‘single chip solution’ for wireless applications. Such a chip which will handle both RF and digital functions is now a reality! BIBLIOGRAPHY [1] Larson L E 1998 High-speed Si/SiGe technology for next generation wireless system applications J. Vac. Sci. Technol. B 16 1541–8 [2] Abidi A A 1995 Direct-conversion radio transceivers for digital communications IEEE J. Solid-State Circuits 30 1399–410 [3] Gray P and Meyer R 1995 Future directions of silicon ICs for RF personal communications IEEE CICC Proc. pp 83–90 [4] Rudell J C, Ou J-J, Cho T B, Chien G, Brianti F, Weldon J A and Gray P 1997 A 1.9 GHz wide-band IF double conversion CMOS receiver for cordless telephone applications IEEE J. Solid-State Circuits 32 2071–87 [5] Arnold R G and Pedder D J 1992 Microwave characterization of microstrip lines and spiral inductors in MCM-D technology IEEE Trans. Compon. Hybrids Manuf. Technol. 15 1038–45

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Index

Acoustic scattering, 60 Activation energy, 34, 58 Alloy scattering, 39, 60–62, 112, 197, 214 Atmospheric pressure CVD, 48 Auger electron spectroscopy, 44, 274, 282 Auger recombination, 82, 117, 337 Avalanche breakdown, 99, 316 multiplication, 82, 317 photodiode, 316, 317 Band oﬀset, 38, 51, 52, 54, 56, 58, 60, 90, 197, 203, 328 Bandgap narrowing, 59, 74, 115, 117, 118, 176 Barrier eﬀect, 90, 95 Base design, 122 Base resistance, 4, 5, 7, 8, 13, 75, 82, 99, 119, 120, 125, 135, 136, 142, 144, 157, 185, 186 Base transit time, 8, 13, 14, 83, 84, 92, 100, 120, 129, 139, 140, 158, 165, 177 Base width modulation eﬀect, 85 BICFET, 20 BiCMOS technology, 2, 9, 24, 120, 186, 188–190, 260, 364, 365, 368, 375, 377, 387, 388 Bipolar technology, 3, 5, 8, 9, 13,

18, 25, 153, 161, 166, 174, 370 Boltzmann statistics, 108 Boltzmann transport equation, 105, 108, 162 Breakdown voltage, 99 Buﬀer layer, xiv, 17, 18, 21, 40, 41, 50, 198, 201, 206, 213, 219 Bulk recombination, 117 Carrier freeze-out, 173 Chemical vapour deposition, 11, 42, 46, 48 CMOS, 2, 16, 18, 196, 204, 226, 228, 238, 245, 367, 370, 372, 375 Collector breakdown voltage, 130 design, 129 Transit time, 97, 139 Conduction band discontinuity, 32, 55, 77 Critical thickness, 13, 35–38, 64, 88, 197, 276, 314, 351 Cross section TEM, 41 Current crowding, 136 Current gain, 7, 10, 11, 13, 74, 77, 83, 87, 89, 94, 120, 158, 173–175, 365 Cut-oﬀ frequency, 3, 14, 84, 96, 110, 120, 123, 131, 140, 143, 157, 163, 177, 222, 364 397

398

Index

δ-doping, 252 Density of states, 80, 113, 116 Deposition techniques, 42, 274 Dielectric constant, 34, 112, 117, 159, 288, 289, 311 Direct bandgap, 311, 337 Drift–diﬀusion equation, 108 model, 105, 107, 158, 162, 163 simulation, 152, 336 Early voltage, 13, 85, 87, 143, 157, 158, 175 ECL gate delay, 9, 99, 133, 141– 144, 174 Eﬀective mass, 34, 59, 61, 116 Electron gas, 213 Emitter design, 126 transit time, 84, 97, 139, 163 Energy balance equation, 216 model, 162, 163 simulation, 162 Epi-base technology, 152, 156, 174 Fermi–Dirac statistics, 104, 250 Field-eﬀect transistor, xiv, 2, 6, 16, 263, 361, 380 Figure-of-merit, 87, 96, 98, 99, 109, 154, 316, 365, 380 Flicker noise, 385 Forward active mode, 75, 77 Freeze-out eﬀect, 60, 62, 175 Gas source MBE, 46, 50 GeC, 314, 315, 334 Gummel method, 104, 108 Gummel–Poon model, 134 HCMOS, 17, 227, 231 Heavy doping eﬀect, 59, 80, 82, 118

Heterojunction, 10, 13, 19, 35, 42, 50, 57, 58, 90, 96, 152, 180, 226, 232, 318 Heterojunction bipolar transistor, 2, 9, 73, 76, 77, 119, 120 HFET, xv, 17, 196, 198, 213, 227, 238–242, 245, 250, 252, 254, 257, 263, 265, 268 High electron mobility transistor, 17, 25, 220 High level injection eﬀect, 94 Hole gas, 60, 62, 217 Hot carrier, 239, 242, 314 Hot electron, 7, 20 Hydrodynamic model, 105, 107, 216, 227 Ideality factor, 274, 276, 277, 288, 293, 296–298, 306 Impact ionization, 99, 183, 314, 317 Impurity scattering, 111, 113, 199 Inductors, 361, 363, 364, 368, 385–387 Infrared detector, 305, 325, 327, 329 Injection eﬃciency, 9, 10, 74, 75 Input impedance, 183, 196, 369 Inter-valley scattering, 198, 199 Interface state density, 241, 274, 291, 293, 300–302 Interface traps, 188 Intermodulation distortion, 380 Ionized impurity scattering, 60, 62, 198, 221, 230, 252 Ionizing radiation, 188, 336 Kirk eﬀect, 94–96, 131 Lattice constant, 13, 32–35, 38, 49, 50, 54, 112, 197, 314 Lattice scattering, 198 Limited reaction processing, 47

Index Limited reaction processing CVD, 42, 47 Low-noise ampliﬁer, 360, 363, 378–380 Low-temperature simulation, 152, 172, 175 Mason’s gain, 109 Maximum available gain, 109, 110 Maximum oscillation frequency, xiii, 8, 75, 96, 98, 143, 152, 220, 221 Metal–organic CVD, 10 Metallization, 11, 183, 272, 277, 363 Metastable layer, 38, 49, 51 Misﬁt dislocation, 35, 36, 38, 41, 51, 52, 94, 118, 314 Mobility, 59, 63, 112, 113, 198, 200 MODFET, xv, 17, 217, 219–222, 224, 374 Modulation-doped heterostructures, 63, 201, 203, 218 Molecular beam epitaxy, xiii, 10, 37, 42, 44 Moll–Ross current relation, 79 Monolithic microwave integrated circuit, 361, 362, 388 Monte Carlo method, 105 Monte Carlo simulation, 112, 199 MOS capacitor, 52, 57, 245 MOSFET, xiv, xv, 5, 7, 17, 18, 188, 190, 199, 206, 209, 212, 214, 238, 249, 251, 257, 260, 263–265, 374 MSM, 315, 316, 318, 320, 334, 345–348 Multiple quantum well, 58, 331 Neutral base recombination, 92 Noise ﬁgure, 185, 186, 365, 368, 369, 372, 378, 379

399

Numerical methods, 108 Ohmic contact, 272, 276, 278 Optical absorption, 58, 321–323, 325 Optical detectors, 325 Optoelectronic devices, 20 Optoelectronic integrated circuits, 310, 311, 315, 328 Out-diﬀusion eﬀects, 90, 92, 120 Oxidation, 51, 241, 264, 276 p–i–n diode, 315, 318, 325, 332, 334, 335, 341, 343, 363 Parasitic channel, 202, 212, 213, 216, 228 Passive component, 25, 363, 386, 387 Phase noise, 23, 265, 365, 372, 384–386 Phonon scattering, 60, 61, 63, 111, 113, 199, 200, 213 Photoconductor, 315 Photodetector, 306, 310, 315, 317–320, 325, 328, 329, 332, 334, 336–338, 341, 345, 346, 350 Photodiodes, 315, 318, 320, 332, 334, 335, 342 Photoluminescence, 50, 57, 312 Phototransistor, 314 Plasma processing, 48, 241 Poly-SiGe, 259–261 Power added eﬃciency, 364, 365, 382, 383 Power ampliﬁer, 12, 23, 24, 363, 367, 377, 381–384 Power delay product, 174, 228, 231 Propagation delay, 4, 99, 141, 142, 154 Quality factor, 385 Quantum device, 20, 239

400

Index

Quantum eﬃciency, 316–318, 321, 328, 329, 332, 334, 337, 338, 350 Quantum well, 17, 44, 218, 222, 239, 242, 245, 247, 255, 328 Radiation eﬀect, 186 Radiation hardness, 190, 256 Raman spectroscopy, 51 Rapid thermal CVD, 47, 175 Remote plasma CVD, 48 Responsivity, 320, 325, 327, 331, 332, 338, 343, 345, 347, 348, 353 RF communication, xiii, 21, 359, 387 RFIC, 360, 367, 383 Rutherford backscattering spectrometry, 279 Scattering mechanisms, 105, 110, 198, 199 Scattering parameters, 109 Schottky barrier diode, 293, 317 Schottky barrier height, 293 Schottky gate FET, 204, 221, 222, 228 Secondary ion mass spectrometry, 41 Self-aligned technology, 8, 120, 142, 159, 221 Self-heating eﬀect, 152, 167, 206, 371 Setback layer, 230 Shockley–Read–Hall recombination, 117, 337 Shot noise, 183, 185, 320 SiC, 1, 10, 241, 314, 327 SiGe, xiii, 1, 2, 9, 13–15, 35, 40, 42, 54, 59, 77, 115, 254, 263, 321, 325 SiGeC, xiv, 13, 15, 18, 32, 42, 49, 50, 56, 59, 241, 257, 260,

264, 277, 310, 314, 321, 327, 334 SiGeSnC, 314, 352 Silicides, 272, 274, 276–278 SIMOX, 242, 250, 255, 256, 329, 362, 371 Small-signal analysis, 109, 134, 139, 338 SOI, 7, 142, 152, 161, 166, 172, 241, 254, 328, 370–372, 392 Solid phase epitaxy, 49 Space-charge recombination, 36 Spacer layer, 92, 94, 100, 143, 173, 174, 221 SPICE parameter, 140, 142–144 Strain compensation, 60, 259 Strain relaxation, 36, 40, 258, 276, 277, 286, 375 Strained layer epitaxy, 33 Strained silicon, 36, 196 Superlattice, 311, 313, 328, 351 Surface passivation, 47 Surface recombination velocity, 188, 288 Surface scattering, 111, 242, 256 Technology comparison, 367 Tensile strain, 60, 209 Thermal noise, 183, 185 stability, 52, 257 Thermal oxidation, 51 Thermal stability, 51 Thermionic emission, 276, 288, 292, 297, 317, 320 Thermionic ﬁeld emission, 288, 292, 297 Thin-ﬁlm technology, 261, 274 Third-order intermodulation, 380 Transmission electron microscope, 285 Transport, 60, 105, 107, 217 Tunnelling, 94, 99, 290, 336

Index Tunnelling current, 8, 75, 173, 260 ULSI, 196, 241 Ultrahigh vacuum CVD, 13, 46 Valence band, 58, 330 discontinuity, 55, 77, 203, 216, 291 Valence band oﬀset, 39, 49, 52, 53, 57, 58, 90, 94, 197, 203 Velocity overshoot, 162, 199, 216

401

Velocity saturation, 94, 100, 111, 199, 217 Vertical transistor, 181, 241, 263, 264 Very low pressure CVD, 48 Voltage controlled oscillator, 24, 366, 384, 386 Wireless communication, 363 X-ray diﬀraction, 51, 274