Radiation Effects Challenges for 21st Century Space Systems

1996 IEEE NSREC IEEE Nuclear and Space Radiation Effects Conference Short Course

Radiation Effects Challenges for 21st Century Space Systems

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July 15,1996 Renaissance Esmeralda Resort Indian Wells, California Sponsored by IEEE NPSS Radiation Effects Committee Cosponsored by Defense Nuclear Agency Sandia National Laboratories Phillips Laboratory NASA Goddard Space Flight Center Jet Propulsion Laboratory

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1996 IEEE NSREC IEEE Nuclear and Space Radiation Effects Conference

Short Course

Radiation Effects Challenges for 21st Century Space Systems

July 15, 1996 Renaissance Esmeralda Resort Indian Wells, California

Copyright @ 1996 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Instructors are permitted to photocopy isolated articles for noncommercial classroom use without Ifee. For all other copying, reprint, or replication permission, write to Copyrights and Permissions Department, IEEE Publishing Services, 445 Hoes Lane, Piscataway, NJ, 08855-1331.

Table of Contents

SECTION

I

FOREWORD Ronald

.............................................................................I 1-4

L. Pease

RLP Research,

Inc.

SECTIONII

SPA CECRAFTANOMALIES AND FUTURE TRENDS ............................................................. . . . . 111-52 James C. Ritter Naval SECTION

Research

Laboratory

III

TOTAL DOSE RESPONSE OF BIPOLAR MICROCIRCUITS ..................+......................................... . . . .. 1111-78 David W. Emily Naval Surface Warfhre Center, Crane Division SECTIONIV

CATASTROPHIC SINGLE-EVENT EFFECTS IN THE NATURALS PACEENVIRONMENT Kenneth F. Galloway and Gregory H. Johnson The University of Arizona SECTION

................ . . . ..IV 1-72

V

DESIGN ISSUES FOR RADIA TION TOLERANT MICROCIRCUITS FOR SPACE ....................................... . . . . . v 1-54 David R. Alexander Mission Research Corporation

1996 NSREC SHORT COURSE

SECTION1

FOREWORD

Ronald L. Pease RLP Research, Inc.

FOREWORD

This is the seventeenth year that a Short Course has been offered at the IEEE Nuclear and Space Radiation Effects Cotierence. The Short Course format provides the opportunity to cover topics in more depth than is possible with contributed papers, but is intended to be tutorial in nature. The theme for the 1996 Short Course is Radiation Effects Challenges for 21st Century Space Systems. The general approach for this year’s course, which has been taken with many of the past short courses, is to have topics on systems, ionizing radiation effects, heavy ion effects and hardening solutions. For each of these areas material has been selected that either has not been covered in the past or has not been covered in depth. The four topics relate to the overall theme in the following manner. The first topic is divided into two parts and sets the stage for the topics to follow. Background irdiormation is given on satellite anomalies to demonstrate that, to date, availability of hardened parts and conservative design practices have resulted in few system failures resulting from degradation or fictional failure of microelectronic parts. In the second part of the first topic trends for fbture satellites are discussed, showing that, unless system designers remain vigilant, a greater number of failures maybe expected in fiture systems. In the second topic, a new challenge in the area of ionization damage is presented for bipolar linear circuits, which are still widely used in space systems. In the third topic a challenge in the area of heavy ion phenomena is presented for catastrophic failure of microelectronic devices and circuits. In the final topic the challenge of designing with fewer radiation hardened components is addressed. A solution using a radiation tolerant design and layout methodology with a commercial foundry is presented. Much of the material presented this year is quite recent and covers research areas that are still very active. However, the intent has been to provide sufficient background ifiormation to make the material appeal to a wide audience. As mentioned above, the course is divided into four sections. The first section, Spacecraft Anomalies and Future Trends, discusses the various types of effects which produce anomalies in space systems, giving historical and other examples of such anomalies. A description is given for how system engineers search for the cause of the aberrant behavior of the system, and the accompanying phenomena which ofien provide valuable clues to the cause. Because the causes of many anomalies are never determined, it is difficult to accumulate comprehensive statistics on the distribution of causes of anomalies or failures in satellites. How anomalies are handled through onorbit comections or reprogramming is described, as well as how they are handled for fiture generations of the same space system. The second subject covered under this topic is trends in fiture space systems, and how those trends are tiected by radiation effects in microelectronics and photonic devices and systems. The future holds new types of systems such as cellular telephones and data transfer systems, and, equally important, greatly increasing numbers of satellites. The second section, Total Dose Response of Bipolar Microcircuits, discusses total dose effects in bipolar microcircuits, with emphasis on the recently discovered low dose rate sensitivity of many linear devices. Because past short courses have focused on CMOS microcircuits, the section begins

I-1

.

with fimdamentals of bipolar transistors operation and presents basic processing and device design details, contrasting the difference between vertical, lateral and substrate transistors. Basic total dose effects in bipolar transistors and digital and linear integrated circuits are presented as an introduction to the important low dose rate sensitivity in linear circuits. The remainder of the section is devoted to a discussion of the response of bipolar linear transistors and microcircuits as a fimction of dose rate and irradiation temperature. Recent theories to explain the dose rate mechanism are presented along with implications for hardness assurance. The third section, Catastrophic Single-Event Effects in the Natural Space Radiation Environment, covers catastrophic single particle effects in semiconductor devices and microcircuits. The section begins with an introduction to the space particle environment and the interaction of energetic particles with devices and circuits. The remainder of the section is divided according to the various catastrophic effects: burnout, gate rupture, dielectric rupture and latchup. Although many of these effects have been discussed briefly in previous short courses, none have been addressed in depth. For each of these effects the status of the experimental data is presented, followed by a discussion of modeling to understand the physical mechanisms. Based on the understanding of mechanisms, techniques for reducing susceptibility are presented. The section concludes with a summary of the important features of each effect as it relates to space applications. The fourth section, Design Issues for Radiation Tolerant Microcircuits for Space, presents design-related issues for space applications of radiation tolerant microcircuits, The section begins with a discussion of a general methodology for assessing the impact of different design approaches on the radiation hardness of integrated circuits. A typical microcircuit is partitioned into its fictional blocks, and the primary failure mechanisms associated with each fictional block are identified. Both heavy ion and total dose ionizing radiation effects are addressed. Several electrical and layout design alternatives for each fictional block are evaluated for their contributions to radiation tolerance. The general approach is illustrated for digital CMOS microcircuits, but suggestions for application to other integrated circuit types is also given. The section concludes with an application of the methodology to a radiation tolerant microcircuit. I would like to thank the five authors/presenters, Jim Ritter, Dave Emily, Ken Galloway, Greg Johnson, and Dave Alexander, for their efforts in making this short course a success. A great deal of personal time, on weekends and evenings, is required to meet the schedules and still filfill the commitments of a family and full time job. Although most of the authors have probably had second thoughts about accepting the responsibility of preparing the manuscripts and presentation material, I hope that, on reflection, they will be very satisfied with the results, as I’m sure are all of the short course attendees and readers of these notes. I would like to thank Lew Cohn of DNA for his efforts in reviewing the manuscripts and assuring that the material was cleared for public release. I would also like to thank the DNA Printing OffIce for printing the notebook. Without their efforts this Short Course Notebook would not have been possible. Ronald L. Pease Albuquerque, New Mexico

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Biographies Ronald L. Pease Short Course Organizer RLP Research, Inc. Ronald L. Pease received his B. S. degree in physics from Indiana University in 1965 and pursued graduate studies in physics at the University of Washington, Seattle the following year. He joined NAD Crane (now NSWC-Crane Division) in 1966, where he performed radiation testing of missile components and headed the DNA Bipolar Program. From 1977-1979 he was with the BDM Corporation in Albuquerque, NM. In 1979 he joined Mission Research Corporation in Albuquerque where he was Manager of the Microelectronics Division. At MRC he was the principal investigator on several hardening and hardness assurance programs. In 1993 he formed his own company, RLP Research, where he is now a technical advisor and radiation effects analyst. Mr. Pease has been involved in the NSREC for many years, having served in a number of positions. He has over 40 publications and has won several outstanding and meritorious paper awards at the conference. James C. Ritter Naval Research Laboratory James C. Ritter is head of the Radiation Effects Branch of the Naval Research Laboratory where he has worked since 1962. For ten years at NRL he pursued basic research in nuclear physics. In 1971 he began peflorming and directing research in radiation effects in microelectronics. He has worked on the radiation hardening of satellite systems and has participated in revising the Joint Chiefs of Staff Guidelines for hardening satellites. He has been a Program Manager or Principal Investigator on a number of space experiments such as the Microelectronics and Photonics Test Bed and the Combined Release and Radiation Effects Satellite Microelectronics Experiment. He currently directs an extensive research program in radiation effects in semiconductor and superconductor devices and materials. Mr. Ritter was an instructor for the 1989 NSREC Short Course. David W. Emily Naval Surface Warfare Center, Crane Division David W. Emily received his B. S. degree with honors in electrical engineering from Purdue University in 1976. He has been employed by the Naval Surface Warfare Center, Crane Division since 1973. Initial assignments included reliability assessments and failure analysis of microelectronics. He has been involved in radiation effects research and testing since 1980. Responsibilities have included radiation hardness assurance evaluation of strategic missile components, development and testing of advanced technologies, and research into radiation effects on bipolar and BiCMOS processes. He currently manages the Technology Development Branch which support the research development and testing of radiation hardened microelectronics. Mr. Emily is active with NSREC and has served as official reviewer, session chairman and finance chairman. He has authored several papers in radiation effects, including the 1983 Outstanding Conference Paper.

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Kenneth F. Galloway and Gregory H. Johnson The University of Arizona Kenneth F. Galloway is currently serving as a Professor and Department Head of Electrical and Computer Engineering at the University of Arizona. Prior to joining the University of Wlzona, Dr. Galloway held appointments at Indiana University(1966-’72), the Naval Weapons Support Center (1972-1974), the University of Maryland (1980-1986), and the National Bureau of Standards (19741986). He joined the University of tilzona in 1986. Dr. Galloway’s research interests include solidstate devices and semiconductor technology. He has authored or co-authored more than 100 technical publications. He was elected an IEEE Fellow in 1986 for “Contributions to the study of radiation effects in microelectronics”. He received the Medal of Honor from the University of Monpellier II. He has served in many capacities with the NSREC and RESG, including the positions of 1985 General Conference Chairman and Chairman of the RESG. Dr. Galloway received the B. A. degree from Vanderbilt University in 1962 and the Ph. D. degree from the University of South Carolina in 1966. Gregory H. Johnson received the B. S., M. S., and Ph. D. degrees in Electrical Engineering from the University of Arizona in 1988, 1990, and 1992, respectively. He held a National Research Council Post-Doctoral Fellowship at the USAF Phillips Laborato~ for two years following his graduate studies. Dr, Johnson is currently a Research Assistant Professor at the University of Arizona, where his research interests include radiation effects on microelectronics, microelectronic device physics, and long term aging effects on microelectronic device reliability. Gregory has presented several papers at previous NSRECS, including the Outstanding Cotierence Paper in 1991. David R Alexander Mission Research Corporation David R. Alexander received his B. S. in Electrical Engineering from the U. S. Air Force Academy in 1968 and his M. S. in Electrical Engineering from the University of New Mexico in 1973. From 1968 to 1973 he was an Air Force officer assigned to the Air Force Weapons Laboratory in Albuquerque, New Mexico, In 1973, he joined the BDM Corporation and was the principal investigator for several programs in radiation response modeling of microcircuits. In 1980, he became a member of the technical staff at %ndia National Laboratories. He is currently with Mission Research Corporation and has been Manager of MRC’s Microelectronics Division since 1993. At MRC, he has been responsible for applying computer-aided design and modeling practices to microcircuits. Mr. Alexander has been active in the NSREC for several years and has served in several positions. He has numerous teclin.ical publications and was a recipient of the Distinguished Poster Paper Award in 1988.

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1996 NSREC SHORT COURSE

SECTIONII

SPA CECRAFTANOMALIES FUTURE TMNDS

James C. Ritter Naval Research Laboratory

AND

SPACECRAFT

ANOMALIES

AND FUTURE

TRENDS

JAMES C. RITTER NAVAL RESEARCH LABORATORY RADIATION EFFECTS BRANCH 1.0 2.0

3.0 4.0

5.0

6.0

7.0 8.0

Abstract Introduction Definition of Anomaly 2.1 Importance of Anomalies to Space Systems 2.2 2.3 Causes of Anomalies Space Environment Data Types of Anomalies 4.1 Radiation-Induced Anomalies 4.1.1 Spacecraft Charging 4.1.2 Single Event Effects 4.1.3 Total Dose 4.1.4 Displacement Damage Non-Radiation-Induced Anomalies 4.2 4.2.1 Mechanical 4.2.2 Software Learning from Anomalies Anomalies Can Lead to New Understanding 5.1 Preventing Software Anomalies 5.2 Publishing Anomaly Analyses 5.3 Future Trends 6.1 New Types of Military Space Systems Projected Increases in Numbers and Types of Commercial Spacecraft 6.2 6.3 Space Experiments to Get High Tech to Space in Record Time New Technologies and Radiation Effects Challenges 6.4 6.5 Use of COTS in Future Spacecraft Testing, Hardness Assurance and Shielding 6.6 6.7 Use of Plastic Parts New Technologies and new Effects in Future Systems 6.8 Conclusions and Summary References 1.0 ABSTRACT

This short course paper will discuss the various types of effects which produce anomalies in space systems giving historical and other examples of such anomalies and the results they have on the space systems. It will describe how system engineers search for the cause for the aberrant behavior of the system and the accompanying phenomena which often provide valuable clues to the cause (such as knowledge that a solar flare had recently occurred or that the spacecraft was in a geostationary orbit and the event happened shortly after 01996

IEEE II-1

,,

,

midnight). Because the causes of many anomalies are never determined, it is difficult to accumulate comprehensive statistics on the distribution of causes of anomalies or failures in satellites. It will describe how anomalies are handled through on-orbit corrections or reprogramming and how they are handled for future generations of the same space system. The second subject covered in this talk will be trends in future space systems and how those trends will be affected by radiation effects in microelectronic and photonic devices and systems. The future holds new types of systems such as cellular telephones and data transfer systems and, equally importantly, greatly increasing numbers of satellites. Both these trends and the introduction of new technologies will provide a variety of new radiation effects and new challenges for us and for future generations of scientists and engineers. 2.0 INTRODUCTION There have been spacecraft anomalies almost as long as there have been spacecraft. There were early examples of unexplained behavior and failure of spacecraft devices, subsystems and even of entire spacecraft dating from the late 1950’s when spacecraft were first placed into orbit. A number of the early failures occurred while we were learning to build space systems which had to do a large number of complex operations remotely. This is an expected part of the learning curve in any complicated operation. Many of these failures occurred in the start-up phase of the spacecraft following launch and injection into the proper orbit while the solar arrays and antennas were being deployed, the batteries charged, and subsystems checked out. Nevertheless even after we learned how to build space systems that worked reasonably reliably and far beyond the design lifetime, we were still plagued by a number of occurrences of what appeared to be random upsets or failures in spacecraft after they had been operating for some time. These anomalies particularly seemed to be noticed in the early 1970’s There may have been several reasons for this. By then we felt we knew how to build satellites and we expected the number of problems to decrease dramatically. At the same time, satellites were becoming much more complex which produced many more possible Microelectronic devices were also becoming much more (and more subtle) ways to fail. capable, but yet smaller, faster and lower power. This increased the vulnerability of the devices to effects produced by the natural space environment, and increased the probability of radiation-induced anomalies. 2.1 DEFINITION

OF ANOMALY

Definition: An anomaly is...an abnormality...an regular arrangement, general rule, or usual method.

irregularity...a

deviation from the

The above definition was taken from Webster’s Dictionary. In the scientific community, the above definition applies quite well; the only thing we might add is: ...an unexpected problem or failure. 2.2 IMPORTANCE

OF ANOMALIES

TO SPACE SYSTEMS

Sometimes anomalies can be just small perturbations on an otherwise perfectly operating system and can be unimportant in the larger scheme of things. For example, a single event upset (SEU) can occur in a sensor or memory which contains a lot of data. By its very nature, the error is sometimes obvious, or unimportant. A picture that contains one erroneous II-2

pixel would probably not even be detectable. One erroneous count out of 1000in data, introduces a O.10/0 error in the result and is generally negligible. An upset can also occur in a circuit which has an error detection and correction (EDAC) circuit in it. These types of anomalies cause little, if any, problem. Unfortunately, anomalies can also be of enormous importance to space systems. If an anomaly occurs and the solution isn’t found quickly, the affected device or subsystem or even the entire spacecraft can be lost. Anomalies present very tough problems to space system operators, because, by their very nature they are unexpected, and by Murphy’s Law, they always happen to the most important subsystem and at the worst possible time. The anomaly itself can cause a very serious problem, or the spacecraft operators can not understand the anomaly fully, and take an action which would ordinarily be safe, but which is not safe in the presence of the anomaly. The worst case examples of anomalies can involve turning on a thruster, or spinning up a reaction wheel, misprinting a critical antenna, producing excessive radiation damage in a solar array, or even causing an explosion. Good design practice generally excludes actions like turning on a thruster by a single anomaly. Serious actions like turning on a thruster require a series of steps like activating the thruster control circuit, applying power to the circuit, then giving the command. Such an action would require three separate anomalies and, hence, are very unlikely, but not unheard of as we shall see later. Excess radiation damage to the solar arrays, caused by a large solar flare, is, unfortunately, not as easily excluded by good design; the array is sized to accommodate the expected number of large flares and one can rarely afford to oversize the array, j ust in case a larger number of flares than expected, should occur. 2.3 CAUSES OF ANOMALIES Determining the cause of the anomaly is often not easy. There are usually a variety of clues that can be of significant help. The information needed to analyze the anomaly is listed in Table 1, along with some examples. The first thing to do is to describe just what happened and determine as closely as possible when it was first observed, noting what the spacecraft was doing at the time and what instructions it was carrying out. This often limits the type of anomaly, and the time is useful in later steps. The type of orbit and where the satellite was in the orbit when the anomaly occurred is a very valuable clue. The first example given in Table 1. under the orbit is a geostationary orbit. If the local time is between midnight and six AM, local satellite time, then there is an increased probability that the anomaly is an electrostatic discharge from surface charging, as we will see in the next section; if it occurs in the early afternoon, it is more likely to be caused by a deep dielectric discharge. Determining what the satellite’s radiation environment was at the time of, and shortly before the anomaly occurred, can provide information about the particle that produced the anomaly. If it occurred in the peak of the proton belts or in the South Atlantic Anomaly, it is very likely it was caused by a radiation belt proton. One of the most valuable clues is to look for a disturbance in the radiation environment during, or shortly before the anomaly occurred such as a large solar flare. Large solar flares can produce a number of effects in spacecraft, such as SEU’S and solar cell damage. Previous anomalies on the same satellite or simultaneous anomalies on other satellites in similar orbits are very useful in determining the cause. In the next sections we will illustrate these and other examples by a more detailed discussion.

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3.0 SPACE ENVIRONMENT

!

DATA

The space radiation environment around the time of an anomaly is often of a great deal of importance. It will be useful to describe briefly the space radiation environments which produce many anomalies. A detailed description of the space radiation environments would not be useful here. What is is an needed order of magnitude understanding of each of important the For most environments. _ 1 The Earth’s Radiation <s. effects, the most important environments are the Earth’s radiation belts, sometimes known as the Van Allen belts after their discoverer. The Earth’s radiation belts are shown pictorially in Figure 1 [After II-4

The figure shows the Stassinopoulosz. Earth’s proton and electron belts. One point to note is the asymmetry on the right mouse ear lobe which appears just off the coast of South America. This is known as the South Atlantic Anomaly (SAA). It is caused by the fact that the geometric center of the Earth’s magnetic field is not exactly at the center of the Earth and the field is inclined at 11 degrees to the equatorial plane. When spacecraft pass through the SAA they encounter large increases in particle fluences and this produces many anomalies. Figure 2 shows the integral fluences of protons with energy less than 30 MeV in units of protons/cm2-day as a function of satellite altitude for circular orbits of selected inclinations based on the AP-8 Minimum Mode13. Note that the belts peak at about 3300 km (1800 nmi). Most spacecraft operate either above or below these intense belts to reduce the undesired radiation unless the mission requires it. Figure 3 shows the

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Figure 2 Earth’s Proton Belts

integral fluences of electrons with energy greater than 40 keV and also 1 MeV in units of electrons/cm2-day as a function of satellite altitude for circular orbits of selected inclination based on the AE-6 and AE-4 NASA Models4. The electron belts peak at about 5600 km (3000 nmi) without any material present. About 80 roils of aluminum will absorb one MeV electrons, so the lower curves can be used to get an indication of how the peak intensity shifts inside a spacecraft. F@we 4 shows the integrated proton fluences intercepted by a spacecraft in a Low Earth Orbit (LEO) when it crosses the SAAS. Notice how much time a LEO spacecraft spends in the SAA, nearly 30 minutes out of a 90 minute orbital period for a 1111 km orbit. The size and shape of the SAA is a strong function of orbital altitude and also of particle energy. If an anomaly occurs while a spacecraft is crossing the SAA, the anomaly was very likely caused by a proton.

II-5

We have discussed the Earth’s radiation belts now let us describe the cosmic ray and solar flare environments. Figure 5 shows the relative intensity of cosmic ray protons for solar maximum and minimum and a solar proton flare for comparison. The cosmic rays are much more energetic than solar flare protons. It is important to recognize that the solar minimum cosmic ray environment is more intense than that of the solar maximum. the cosmic rays penetrate more easily when the sun is less active. The I I I 1 I I I \!u\ Uv , J ,Dimlnm main point of this figure, however, is that if a “ ammmmmm 9@ mmlWcwu’rnmww~ solar flare occurs it dominates the cosmic ray environment by five or six orders of magnitude. Two very intense anomalously -4 Roton Fluence in the SAA [after large flares are shown in Figure 6, the very Stassinopoulos, Ref 5] energetic flare of February 26, 1956 and the very intense flare of August 4, 19727. When the term “ten percent worst case flare” is used, it means that there is only a 10 % chance of encountering a higher solar flare environment than it. Note that for the worst case environment the envelope of the 1972 flare is used above the intersection of the two curves, and the 1956 curve is used below that point. This envelope represents an extremely intense, high energy flare which has not actually been seen in nature. Figure 7 shows that even very ,.9 INTEGRAL PRow4

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Figure 5 Comparison of Cosmic Rays and Solar Flares [after Adarns, Ref q II-6

large amounts of shielding (up to 2 inches of aluminum) do not change the cosmic ray spectrum by very muchs. Large variations in the Earth’s radiation environment are caused by changing conditions on the sun and by the magnetic fields in the solar system which modify the access of solar and galactic particles to the near-Earth regions of space. The sun has an d over-all pattern of activity with an 11 year ml * ,,WI ml , cycle. This is shown in Figure 8 which shows lid 10-’ Id I& 10” D’ ~’ 10 I the pattern for both sunspot numbers and for LET In MeV em’ Is magnetically disturbed days (in which the geomagnetic index, Ap, is greater than 40)9. The incidence of many types of spacecraft _ 7 Cosmic My Spectra Behind anomalks such as electrostatic discharges from Various Shielding [After Adams Ref 8] surface charging follows this over-all pattern too. Figure 9 shows a more detailed look at the solar flare distribution with timel”. It is clear that solar flares are less likely to occur at solar minimum and they seem to have a higher probability of occurring on the leading and trailing edges of the solar cycle. The seasonal distribution of magnetic disturbances is shown in Figure 10’1. Note that the magnetic storms vary by about a factor of two over the year and are highest at the spring and fall equinoxes. This m-ak& upsets more probable during those seasons. ‘This same seasonal pattern is seen in spacecraft anomalies caused by surface charging.

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* 9 Solar Flare Protons for Cycles 20-22 [After Barth Ref 10]

II-7

4.0 TYPES OF ANOMALIES Anomalks can be separated into two for our purposes, broad categories non-radiationradiation-induced and induced. It seems clear that the Nuclear and Space Radiation Effects Conference attendees would be primarily interested in radiation-induced anomalies, and I will concentrate on them. Nevertheless, other anomalies will also be discussed because they are often important causes of the upset or loss of major space systems and it is necessary to have some understanding of them in order to gain some perspective. One important example of a mechanical anomaly will be discussed in some detail because it probably caused the loss of the Mars Observer spacecraft.

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Figure 10 Monthly Distribution of Magnetic The various types of spacecraft Storms [After allen, Ref 11] anomalies are shown in Table 2. The include anomalies radiation-induced electrostatic discharges that occur as a result of either surface or deep dielectric charge that builds up on the spacecraft. When such discharges occur, they can cause changes of state in memories, telemetry resets, breaMown paths across dielectrics, or they can short out a device. A second important type of anomaly is single event effects. SEE’s include single event upsets (SEU), single event Iatchup (SEL), single event burnout (SEB), and single event gate rupture (SEGR), among the better known effects. AU single event effects occur as the result of a single particle depositing energy along the path of a particle either directly or by means of a nuclear interaction with the material which can produce other particles. SEU often occurs in memories where it changes the state of one or more bits in the region where the particle strikes. SEUS can also give an undesired instruction to a microprocessor or even jump it to an undefined state. SELS can cause a device to burn out if the latched state draws enough current. A large pulse of current produced by a single particle can also cause a gate under bias to ruptu~ destroying the device (SEGR). Total ionizing dose can cause threshold voltage shifts or increased leakage current in CMOS devices which drives them out of specifications and causes failure. It can also cause failure in bipolar devices (operation outside of specifications) by reducing the gain or by increasing the leakage current. Displacement damage results from particles interacting directly with the atoms of the lattice and displacing them, causing charge trapping and recombination centers. This results, for example, in gain reductions in bulk devices and reductions in charge transfer efficiency in Charge Coupled Devices (CCD’S). We will discuss the four types of radiation-induced anomalies listed in Table 2 in order.

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4.1 RADIATION-INDUCED

ANOMALIES

4.1.1 Spacecraft Charging Spacecraft anomalies such as upsets, switching errors and resets had been occurring regularly in some space systems in the early 1970’s. Just what was causing them was not understood. They seemed to be happening often to our major communication satellite systems which operate in a geostationary orbit. It was happening to both military systems such as the Defense SateUite Communication System (DSCS II) and the Defense Support Program (DSP) spacecraft and to commercial satellites as well such as Intelsat and Telesat. An example of the

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type of anomalies occurring in synchronous satellites is shownn in Table 3. The anomalies include a number of examples of logic or control circuit switching and other erroneous operations. It was noticed that when the locations of the anomalies were plotted as a function of when they occurred in terms of satelMe local time, the anomalies clustered into one large group (see Figure ll)n. -use a synchronous satellite has a 24-hour orbit, it circles the earth once per day and therefore stays over a fixed point on the equator. The time at that fixed point on 1 the earth is the spacecraft local time]. An v DSP LOGIC UPSEIS n i 0 OscsII RCAUPSETS unusually large fraction of the spacecraft v lMlfLSM IV o INIELSA1 Ill anomalies occurred in the midnight to six a.m. quadrant in the satellite’s local time (much larger than the expected 12). The -11 Local Tme dependence of Upset [After McPherson, Ref 13] probability that 31 out of 47 “anomalous events” would occur at random in a single quadrant was calculated as 3 chances in 109. Other work by DeForest14 indicated that synchronous satellites were probably being charged to high potentials by particles. The explanation suggested was that events occur preferentially just after midnight because the spacecraft passes through the geomagnetic tail where electrons, accelerated by geomagnetic activity, are injected and drift from midnight toward dawn. In addition, if the spacecraft is out of view of the sun, then solar photoelectrons can no longer provide a discharge mechanism. This problem was viewed as serious enough that an experimental spacecraft, was designed and launched specifically to study spacecraft charging, the Spacecraft Charging AT High Altitudes satellite, (SCATHA). One signature of dielectric discharges caused by spacecraft surface charging is the high probability of finding a large number of events occurring between midnight and dawn local time in a spacecraft having a high altitude orbit such as geosynchronous. If the discharges group in the afternoon local time there is a good probability that they result from deep dielectric discharges. These examples illustrate how environmental information can provide the necessary clues to recognize the source of the problem causing the anomaly. Figure 12 shows the insulator pulses (ESD’S) detected on the Internal Discharge Monitor instrument that were recorded onboard the Combined Release and Radiation Effects Satellite (CRRES) in a carefully

Figure 12 Orbital Distribution of CRRES Insulator Pulses [After Violet, Ref 15J 11-10

The flux of electrons with energy greater than 300 keV is also shown designed experiments. for comparison. The CRRES orbit ranges from about 200 nmi to 20,000 nmi in a geostationary transfer orbit inclined at 18 degrees to the equatorial plane. The x-axis is given in Earth radii in units of L, the Mclllwain L parameterlf, where L=l is the surface of the Earth. The geostationary orbit is at about L = 6.6. The spacecraft starts at the left side of the figure and moves down through the radiation belts until near L = 1 it passes under the belts then climbs back through them ending near its geosynchronous apogee on the right. The ESDS correlate well with the electron flux shown in the top part of the figure. The SEUS shown at the bottom nearly all occurred in the proton belts. It was a surprise that over 90 ‘A of the upsets were produced by protons. Before CRRES was launched it was predicted that most of the upsets would be produced by cosmic rays. 4.1.2 Single Event Effects Another effect which produces a large number of anomalies in space systems is Single Event Upset (SEU). The history of single event upsets is interesting. It started with a paper by Wallmark and MarcusI’, of RCA, published in 1962, in which the authors speculated that cosmic rays would be able to produce upsets in microcircuits as the microminiaturization trend continued and that cosmic ray upsets would set the ultimate limit on how small a device could be made. Their paper, however, was so far ahead of its time that it was largely overlooked. The next significant event took place 13 years later, in 1975, when Binder, Smith and Ho1man18, of the Hughes Corp., observed unexpected triggering of digital circuits in an operating sateUite and postulated that the bipolar flip-flop circuits were being upset by charge collected from the dense ionization track of an energetic heavy ion cosmic ray passing through an individual transistor. Binder, Smith and Holman calculated an upset rate which was within a factor of two of the observed results. This paper too was ahead of its time and did not awaken the community to the potential seriousness of the problem. In 1978, May and Woods19, of Intel Corp., discovered that anomalous upsets which were occurring in dynamic random access memories on the ground, were being caused by alpha particles emitted from trace amounts of thorium and uranium in the materials from which the device’s packages were made In 1978 also, Pickel and Blandford20, of the Rockwell Corp., studied anomalous upsets which were being obsemxl in NMOS dynamic RAMs used in a satellite system and concluded that these upsets were due to heavy ion cosmic rays. They also developed an approach for calculating upset rates to be expected in a cosmic ray environment. The Pickel and Blandford paper finally alerted the radiation effects community to the problem of heavy ion-induced cosmic ray upsets in microcircuits. It quickly became clear that both protons and neutrons could also induce SEU’S (Guenze#l and McNult#). Since the discovery of SEU’S, the number of Single Event Effects (SEE) has expanded greatly to Single Event Latch-up (SEL), Single Event Burnout (SEB), etc. One particular device has become famous (or infamous) for causing an unusually large number of upsets in operational spacecraft, the 93422 or 93L422. This device has been responsible for producing upsets in TDRS, LANDSAT, and DSCS and potential latchup in this device also caused the costly redesign of the Galileo spacecraft. The effect of a large solar flare such as that of October 1989 on the SEU rate is dramatic Solar flares are made up of a large number of particle types but are predominately protons. As shown in the top of Figure 13, the GOES-7 spacecraft detected x-rays emitted by the Sun during that solar flare ‘. The x-rays travel in a straight line toward the Earth. The solar flare particles are bent by the magnetic fields between the Sun and the Earth and they 11-11

,,

may or may not couple well to the- Earth, arriving somewhat later. Notice how the SEUS shown in the center of the figure follow the solar particle fluence. The fact that the SEUS track the proton fluences rather than the x-ray rates is illustrated clearly in Figure 14 for the March, 1991 solar flare event?4. Figure 15 shows the SEU rate observed on the TDRS 1 illustrating spacecraft the cosmic ray and solar flare It is important to effects2s. notice that the SEU rate peaks during solar minimum indicating that those SEU’S were produced by cosmic rays. There are also spikes on the curves cortwponding to the large solar flares of 1989 and 1991. Upsets on the UOSAT satellite observed from 1988 to 1992 in TMS 4416 64 bit NMOS dynamic RAMs are shown in Figure 1626. The upsets occur predominantly as the satellite passes through the SAA. This is typical behavior for a LEO satellite. Let us now look at single event latchup in an NEC 64 K CMOS RAM used in a geostationary and a LEO satellite. The details of the observations are given in Table 4 for the Engineering Test Satellite V launched by the NASDA into a geostationary orbit. The eight devices produced about 2.4 SEL per week and 0.76 SEU per week as shown during a period of 3.5 years. During the large solar flares of September 29, 1989 and October 19,1989 satellite 80-180

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_ 14 CAMS-7Solar-Terrestrial Environment for March 1991 showing SEU’S [After Allen, Ref 24] 11-12

SEL and 50-70 SEU were observed respectively. The onorbit data are shown in Figure 1727. A more careful look at the data (Figure 18)28 shows that nearly 80 SEL’S were accumulated in a little over a day, an increase of over 200 in SEL rate. This same device (in a slightly different version) was also used in the ESA Earth Resources Satellite-1, a LEO satellite launched in 1991. This satellite had an on-board experiment called the Precision Rate and Range Range Experiment which only operated for five days before being destroyed by an overcurrent in the power supply shown in Table 5. Before shutdown, a number of SEU’S were observed and a processor reboot was required29 . The experimenters decided that UOSAT-Z

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Figure 16 Dynamic RAM Upsets on UOSAT-1 [After Dyer, Ref 261

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the burnout was possibly caused by a proton induced They therefore Iatchup. the Engineering tested Development Model and Iatchups found that occurred in the 64 K RAM at the fluences shown. The burnout currents required in the ground tests matched the from seen those telemetry, were consistent with the total accumulated fluence and occurred in the SAA as shown in Figure 1930. SEL is going to be discussed in a great deal more detail in the later talk by Ken Galloway.

4.1.3 Total Dose The first anomaly in operation (and later, the loss) of a spacecraft due to total dose effects occurred very unexpectedly as shown in Table 6. A Bell Telephone Labs satellite called II- 13

,,

II -14

Telstar was launched into a 515 nmi by 3044 nmi orbit with 44.8 degrees of inclination on July 10, 1962. This is an orbit that passes through intense regions of the Van Allen belts. Telstar was launched just one day after a very large nuclear weapon (over 1 Megaton) was detonated at a high altitude of about 400 km. This Starfish nuclear test produced a large number of beta particles (electrons) which became trapped in the Earth’s magnetic field causing an intense, artificial radiation belt to form which lasted until the early 1970’s. This new radiation belt increased the expected total accumulated dose in the Telstar spacecraft by a factor of over 1000 This additional dose produced what was probably the first instance of the loss of a spacecraft due to total ionizing dose damage in a semiconductor device. The command decoder on Telstar I, consisting of diodes and narrow base transistors was not sensitive to displacement damage+ but was sensitive to total ionizing dose In mid-November, it became sluggish and on November 24, 1962 it failed. A series of creative steps were taken and it eventually recovered its function, but again failed, this time permanently, on February 21, 1963. Ground tests on two transistors with the same date code showed failure after 0.6 and 2.3 megarads and were consistent with the dose observed on The failure behavior Telstar. was also the same and it was concluded by Mayo et. al.31 that the failure was caused by surface damage to the Command

ON-ORBIT LATCH-UP ANDUPSETINNECM KCMOS R4MSONTHENASDAETS-VSPACECRAFT

F&n 17 On-Orbit Latchup and Upset of DRAMs [After Goka, Ref 271

ON-ORBIT LATCH-UP ANDUPSETIN NEC64K CMOS RAMSONTHENASDAETS-VSPACE~

Figure 18 On-Orbit SEUS and Latchup-in During Solar Flare [After Goka, Ref 28] II- 15

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Decoder caused by radiation enhanced from the Van Allen belts. In this case, the radiation unusual environment provided the clue to the cause of the anomaly and ground tests provided the proof or at least confirmed that a similar amount of radiation could cause a very similar effect in the suspected device. When the STARFISH burst was detonated in 1962 it destroyed a total of seven satellites within seven months, primarily due to solar cell damage. It gives pause to one contemplate how many military and

ON-ORBIT LATCH-UP IN AN NEC 64 K CMOS RAM ON THE ESA ERS-1 SPACECRAFT’

Figure 19 Orbii Positions of On-orbit Latchups in DRAMs [After Adarus, Ref 30] II -16

commercial satellites such a burst would destroy today considering the much larger number of spacecraft in orbit now and how rapidly the number is rising! 4.1.4 Displacement

Damage

Displacement damage is also sometimes the cause of spacecraft anomalies. Most displacement damage was historically associated with massive events such as large solar flares and it generally took place in analog rather than digital devices. It is often easier to determine the cause of damage in analog devices because they change in a continuous manner, rather than in one step, and when unexpected behavior starts to occur, it can often be monitored. The monitoring of a slow, but continuous change in an electronic part’s operational parameters is easier to detect than spotting a single, random event, such as a SEU. There is another reason that it was often easier to pin down in the past; it often caused problems in the spacecraft power system which is usually monitored in real time so that the anomaly was observed as it was happening. If you can see the power reducing as a solar flare occurs it is pretty easy to determine the cause. In this section we will begin by discussing some examples of classic displacement damage caused by charged particles such as protons or other heavier particles. There are many examples, but not much mystery. We will then go on to a more recent example where there aren’t many examples, but there is still a good deal of mystery. Solar cells are exceptionally vulnerable because they are on the outside of the spacecraft where they do not benefit from inherent shielding. They typically have 6-30 mil cover slips on the front and a light weight aluminum backing on the back The first example of displacement damage causing the loss of a space system from solar cell damage occurred in 1962. The Starfkh nuclear 70 weapon test, discussed r above under total dose, produced electrons and redistributed protons which caused premature degradation and failure in the solar arrays of three satellites in low-altitude orbits at the time. The three satellites, Transit 4B, Traac and Ariel became inoperable because of degradation in their solar cell power systems32. One I failed in 4 days, one in 24 and a third in 36 days. The solar cell output as a function of time in orbit is shown for Transit 4B and Traac33 in Figure 20. This

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Figure 21 GOES-6 and GOES-7 Solar Cell Degradation [After Allen, Ref 3Sl

Produced by a Solar Flare

figure demonstrates the dramatic effects of Startlsh. With the quality of telemetry shown in Figure 20, it was pretty clear that solar panel degradation was responsible for the loss of the spacecraft, but the cause was a little more obscure. Did the trapped electrons from the weapon cause the degradation or was it caused by the protons which were redistributed by the weapon’s disturbance to the Earth’s magnetic field? One can tell whether damage is caused primarily by electrons or by protons by looking at how damage depends on the depth of shielding material. It happened that on the TELSTAR satellite (launched just after Startlsh) there were a series of solar cells with different coverslip thicknesses. By comparing the damage observed to that expected from electrons or protons of appropriate energies, the experimenters34 deduced that most of the damage was caused by protons. For comparison, we will now look at the more recent effects produced by a solar flare in the GOES-6 and GOES-7 spacecraft during the March 1991 solar flare, shown35 in Figure 21. As the Figure shows, in just nine days, the solar array lost as much power as was expected for three years of operation in a “normal” geostationary orbit environment. We now turn to some rather interesting new results of damage caused by very small fluences of protons. I have placed this under the displacement damage section because it is H- 18

caused by protons and not by Co 60 gamma rays. The problem is that this damage takes place at a very low dose or fluence level, much below that of classic displacement damage. The damage mechanism is not yet understood. The first anomaly appeared in 1993 when the Remote Command Unit (RCU) on a spacecraft failed after about three years in orbit. Fortunately there were redundant RCU’S on board. This same RCU was used on other spacecraft and after about three years in a similar orbit an RCU on the second spacecraft also failed. A year and half later, in 1995, a second RCU on the first spacecraft again failed (there are a number of RCU’S on board) but this time the failure was captured in real time telemetry. Since these RCU’S are used on a number of satellites the problem had a lot of urgency to be solved before another spacecraft with this type of RCU on board was launched. There was another, even more urgent reason for the Responsible Engineer to solve the problem quickly. When a spacecraft anomaly occurs, someone’s name and phone number is on the top of the list to be called at any time of the day or the night. When the first failure occurred, he was in California on business. When the second failure occurred, he was on a trip celebrating his anniversary with his wife in the wilderness. When the third anomaly occurred, he was golfing in Florida. Now, disturbing a business trip is annoying and ruining an anniversary trip with your wife is even worse, but being called back from a golf trip is unthinkable! Clearly something had to be done to solve this problem, and quickly!

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l?igure 22 Opto-isolator Ref 36]

Gain Degradation

vs Dose [After Stapor,

II -19

The basic information for the for solution the problem was by now available. The units started to fail after a fixed time on orbit. That could be either a time or a radiation related failure. The anomalies investigation by the Tiger Team indicated that the failures were related to power switching in The the RCU’S. power switching was done by a TRW 4N24A Gtis optoisolator. This device is used to turn the unit on or off. With optical coupling, the chance of parasitic noise getting into the unit is minimized. The 4N24A devices had been tested by

the contractor and shown to work well, 4 l_ll_lHlll_f_’_7-~ l_T17’1--T” TT-rTl 11 ~ even after a dose of 1= 1 hundreds of kilorads & ; :“ v of Cobalt 60 gamma ● *O’ 800 rays. But there was 3 0 0 one disturbing bit of information; tests - 700 ❑ 0 i several conducted ❑ years earlier on a o slightly different - 600 ❑ 0 version had shown o 4N24A’s the that 1 “w v 500 141nAt3@t started failing after n o a lomspec only the equivalent of Q o 2mAspec o 0 5-10 Krads of protons. 1 1 1 1 t 1I 11 I 1 1 1 1 t 111 0 & t I 1 111 01 al A new set of 4N24’s 1 1 lo W was tested (along with TOTM DOSEOQad@O) a large variety of optoGAIN DM3RADAT30NIN TRW 4N24AOFTCHSOLA*RS “d isolators from other A FUNCITON OF 63 MeV FROTON DAMAGE IN THE MODIFIED manufacturers) at the III(3HT CIRCU~. SPECMEANSTHE CURREJ’TT’ TIUNSFER RATIO WAS MEASUREDWITH NO LOAQ FLIOHT MEANS IT WAS U.C. Davis cyclotron MEASUREDAS FLOWN W~ A LOAD (FROM REFERENCE16). using 63 MeV protons. The data is shown~ in which Figure 22. _ 23 Opt-isolator Gain Degradation Vs Dose for Higher shows how rapidly the Drive Currents [After Stapor, Ref 371 gain degrades after a 63 MeV proton dose of only a few Krads, especially in circuits which draw low drive currents. Further testing with higher drive currents (Figure 2337) or with other devices has shown methods of reducing the problem. As a result of the tesq two frees were identified: 1) modify the flight circuit to draw more drive current (20 ma, rather than 2 ma), and 2) shift to other devices e.g., the 4N49 from different manufacturers (OPTEK and Micropac).

I

This example has shown how sensitive opto-electronic devices can be to proton displacement damage compared to total ionizing dose from Cobalt 60 gamma rays. With the use of more opto-electronic devices in the future, this looks like an increasingly important problem for new space systems. Charge transfer devices - Charge Coupled Devices (CCD’S), Charge Injected Devices (CID’s), etc., have similar vulnerabilities at the same low levels and will also be a potential problem for future spacecraft. It seems probable that as we put more electro-optical devices on spacecraft, we will begin to have more of these anomalies caused by low fluences of protons or other particles. The Tiger Team believes that it has solved the problem which they believe was a radiation failure. I am not so sure, because, as shown in Table 7., I have also noted a coincidence which has occurred with 100VO frequency in this example~, namely that the Responsible Engineer has been out of town every time the anomaly has occurred! I suspect that it is correlated with time+ mther than with radiation, and that the solution is to keep him home and on the job! [In this example it has been necessary to delete a number of details (such as names) in order to protect the gu .... er, innocent] II -20

*

**

Ground tests show failures in 4N24A’s at similar doses. Emergency phone calls verify that Responsible Engineer is not at work

4.2 NON-RADIATION-INDUCED

ANOMALIES

Non-radiation-induced anomalies can result from random failures in devices, operator errors, such as sending an improper command, a malfunction in a mechanical subsystem, such as a reaction wheel, a software error through a transmitted or stored command, or from a variety of other causes. 4.2.1 Mechanical Determining the cause of an anomaly can be a very serious problem requiring a large team of experienced satellite designers and software experts. This is particularly true if a spacecraft is currently non operational and a Tiger Team is assembled to try to recover the spacecraft or if a failure has occurred and the failure is being investigated. A good example of a group assembled to determine the cause of a mission failure is illustrated in the Mars Observer Mission Failure Investigation Board39 which investigated what appears to be a failure in one of the mechanical subsystems, the propulsion subsystem. The Mars Observer program was conceived starting in 1981 and initiated as a new start in 1985. The scientific objectives of the project were to study the surface and atmosphere of Mars, its topography and magnetic field. The details of the program are shown in Table 8. The total program cost was expected to be about $415 M. It was originally planned for a shuttle launch, but after the Challenger explosion, the launch vehicle was shifted to a Titan III, and the planned launch was delayed for 26 months (the next Earth-Mars proper orientation). The Mars Observer was launched on 25 September, 1992 into a low altitude parking orbit and then it was injected into an interplanetary trajectory to begin its 11 month cruise phase (see Figure 24)40. 11-21

TABLE $415 M PROGRAM

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MARS OBSERVER

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LAUNCHED 25 SEPT 1992 INTO LEO THEN INJECTED INTO INTERPLANETARY TRAJECTORY TOWARD MARS AT 0021 ON 22 AUG 1993 BEGAN MARS ORBIT INSERTION UNDER CONTROL OF SOFTWARE NO DATA RECEIVED FROM SPACECRAFT

MANEUVERS

SINCE SEQUENCE

INITIATED

FAILURE REVIEW BOARD ASKED TO INVESTIGATE

Figure 24 Mars Observer Minion II -22

[after Ref 40]

All went well during the cruise phase, with only a few anomalies noted until the spacecraft was to begin the first step of its Mars orbit insertion. At 21 minutes after midnight GMT on 22 August 1993 a series of events was started to begin the Mars orbit insertion maneuvers. The system was under control of a sequence of software commands previously stored in the spacecraft computer. During all other events on the journey, a serious anomaly would activate a maneuver abort command, but at this critical time of insertion into the Mars orbit, which had to occur at a precise time, an abort could not be tolerated and hence all spacecraft abort criteria were temporarily disabled. The first step of the sequence was to pressurize the propulsion system. Because of concern that the traveling wave tubes in the RF power amplifiers might be damaged by the shock caused by the firing of the pyro valves, the RF amplifiers were turned off, as planned, just before the sequence was initiated. Unfortunately this meant that there would be no telemetry during the propellant tank pressurization sequence. No data have been received from the spacecraft since the sequence was initiated. Within three weeks of the telemetry failure of the Mars Observer, Daniel S. Goldin, NASA Administrator had requested Dr. Timothy Coffey, NRL’s Director of Research to establish a Failure Investigation Board to look into the failure. The Board consisted of eight other members and 29 technical advisom from NRL, NASA, NOAA, AFPL, the US Navy and the DMSP program ofilce. The Board was broken into six teams responsible for the spacecraft subsystems, namely: Electrical Power, Attitude and Articulation Control, Command and Data Handling, Mechanical, Telecommunications and Software. The Board presented its results after a four month investigation. The Board’s problem was to find the probable cause of the mishap when there was neither telemetry data nor any physical evidence available within 19 light minutes. The Board’s approach was to identify the possible failure modes that could have resulted in the immediate loss of telemetry. Many of these were random failures. The Board considered random failures to be highly improbable since the spacecraft had operated for nearly a year and a random failure would have had to occur during the 14 minute interval during which the telemetry was off and in which a very critical process was occurring. Accordingly, random failure modes were eliminated. Next the Board eliminated failure modes which were not compatible with the detection capabilities of the NASA Deep Space Network and the fact that they had received no further telemetry from the spacecraft. Finally the Board focussed on the commands, actions and software associated with the pressurization sequence which was This effort resulted in an evaluation of 59 to take place during the 14 minute interval. possible scenarios. The justifications for these conclusions are presented in Table 9. The first potential cause was a power supply electronics (PSE) power diode insulation failure. The PSE contains several diodes connected to the power bus. Inspection of the spare PSE box revealed several discrepancies including a misalignment of three often stud-mounted power diodes permitting the diode to come into, or very close to, direct contact with the chassis. On some diodes, a thin kapton insulator had embedded metal particles and scratches in a thermal insulator on both sides of the kapton. The shock from firing the pyro valves could have caused a breakthrough in the insulation causing a permanent short in any of these diodes which would short-circuit the power supply, destroying the spacecraft. Based on the inspectionof the sparePSE, the Board believes that this scenm”o must be retained as a possible cause of the loss of the downlink. II -23

*

**

Noted on spare PSE box. ESA and NASA initiators designed to same specifications,

but are not identical.

The second potential cause was a pressure regulator failure. If the pressure regulator failed in the open position it would cause a rapid over-pressure and a rupture of the nitrogen tetroxide tank, destroying the spacecraft. Failure of the regulator could have been caused by nitrogen tetroxide frozen in the regulator orifice, by contamination blocking the orifice, or by contamination in the seat causing leaking. Since nopost-assemblytestshadbeen cam”edout to vemfithatthesystemwascleanandthe temperatureof the regulatorwasnot known,theBoard reta”ned thisscenarioasapossiblecausefor the loss of the downlink The third potential cause was the failure of a pyro valve charge initiator. Some European Space Agency (ESA) initiator tests have resulted in initiator ejection from the valve body at speeds of 200 m& The ESA initiators are designed to the same specifications as the NASA initiators, but are not identical. The ESA initiators failure mode is from thread erosion. The Board had the acceptance test lot of NASA initiators examined and found erosion of about 50’% of their threads, though none had failed by initiator ejection. For these reasons the Board believes that pyro valvecharge initiator failure is apossiblecauseof loss of the downlink.

II -24

The cause listed as most probable was leaking of nitrogen tetroxide through the check valves which separated the nitrogen tetroxide from the rest of the pressurization side of the system. Since the valves were cold for most of the 11 month cruise, a scenario was proposed in which nitrogen tetroxide leaked through the check valves and condensed on the cold tubing upstream. The nitrogen tetroxide could then mix rapidly with monomethylhydrazine when the pressurization sequence was initiated, causing a rapid heating, rupturing of tubing, or an explosion. Tests indicated that as much as one to two grams of nitrogen tetroxide could have migrated through the valves, much more than enough to cause an explosion. Because nitrogen tetroxz”dewas shown in tests to be able to m“grate through check valves posing a n“sk of explosion, because of the correlation with the pressurization sequence, and due to the lack of other more compelling scenarios, the Board determined that the most probable cause was the unintended mixing of nitrogen tetroxide and monomethylhydrm”ne in the titanium tubing on the prasu~~”on sib of thepropufswnsystimcausedby m“gratkn through MO check vtdves during the 11 month cruisefrom Earth to Mam This example illustrates just how difficult it is to pin down completely the cause of a spacecraft anomaly, especially when telemetry or tapes of the event are not available. 4.2.2 Software The Clementine spacecraft was developed by the Naval Research Laboratory for the Ballistic Missile Defense Organization and it involved the participation of Lawrence Livermore National Laboratory, NASA, and the Jet Propulsion Laboratory as shown in Table 10. The program required only 22 months from program initiation to its launch on January 25,1994 and itdemonstrated the use of advanced technology sensors, light weight components and new computer and digital processing technologies. The program involved making a detailed map of the lunar surface then a fly-by of the near-Earth asteroid Geographos. Clementine provided the first space-based photos of the moon since the last Apollo lunar landing in 1972, taking over 1.8 million multi-spectral images in the visible, infrared, and

ON MAY 7 AN ANOMALY

OCCURRED DURING A TEST

TELEMETRY LOST FOR 20 MINUTES, WHEN RECOVERED SPINNING AT 82 rpm

II -25

CLEMENTINE

WAS

ultraviolet. The first part of the mission, the 70-day mapping of the moon, was remarkably successful as illustrated in Figure 25 which is a map of the south polar region of the moon taken through a red filter by Clementine41. Following completion of the lunar mapping phase, Clementine was supposed to leave the Earth-moon system and head for Geographos. On May 4, 1994 Clementine left lunar orbit and performed a series of maneuvers to make a gravity assisted fly-by of Geographos. New software for the Geographos portion of the mission was uploaded and tested. On May 7, during a centroiding test, the spacecraft experienced an onboard anomaly at 13:39:432 and all telemetry data was lost from the housekeeping processor for no reason. apparent For about twenty minutes the ground controllers struggled F@UW 25 CJementine Map of the South Polar Region of the Moon to recover telemetry. [After Ref 41] When the telemetry was finally recovered it was discovered that the spacecraft was in a rapidly spinning mode (at 82 RPM) and that the attitude control fuel supply was exhausted. The sequence of command events surrounding the anomaly is shown in Table 11. After six weeks of intensive investigation the cause of the anomaly was determined42 to be in the flight software. The anomaly was caused by software in the housekeeping processor. The software defect was in an error handling code that only showed up when a) an arithmetic underflow condition occurred and b) when certain lunar software routines were present. The defect caused the housekeeping processor to become corrupted and placed its instruction counter in an indeterminate location and allowed data execution to go forward from that point. This permitted indeterminate data to be placed on the housekeeping bus which under certain conditions fired the attitude control thrusters during autonomous operations. In the asteroid encounter which was being simulated at the time, the thrusters were purposely enabled to allow for autonomous operations. II -26

II -27

Before any action is taken on a spacecraft it is first simulated on a test bed which is an identical system on the ground which is supposed to be programmed with an identical set of instructions. Unfortunately, the housekeeping processor had been undergoing some unexpected resets during the mission and one reset had occurred on May 4. The spacecraft operators had been trying to discover the source of these resets. In doing so they had decided not to include two software patches in the spacecraft computer configuration. When they later loaded the centroiding program they inadvertently also left out three other patches. It was discovered later that none of these patches was present in the spacecraft computer, but they were present in the ground-based operations test bed, violating the assumption of identical In the dry run on the test bed which was carried out before software configurations. attempting the asteroid encounter simulation, the test bed (with the patches loaded) did not fire the thrusters and hence gave no warning of what was about to occur on the spacecraft. In later simulations without the Datches loaded it was seen that under certain conditions the test bed also gave the order to fire the thrusters. The Clementine example just discussed illustrates just how complex some spacecraft software anomalies can be. It only occurred under circumstances in which a latent defect in the program was permitted to take an unintended action because some other program which would protect the spacecraft was not in place. Under luckier circumstances, the program would have been ground-tested without the patches in place and would have shown that the thrusters could fire under these conditions. After investigation, the defect would have been removed or it would have then been required to check the spacecraft computer configuration for the patches before initiation of the asteroid fly-by simulation. Alternately, if the patches had been loaded in the spacecraft processor, the thrusters would not have fired and the defect in the code may never have been discovered. It is also possible that if the Program had had more time than 22 months, the program defect might have been discovered and corrected before launch. 5.0 LEARNING

FROM ANOMALIES

5.1 ANOMALIES

CAN LEAD TO NEW UNDERSTANDING

The history of the observation of anomalies in space systems began shortly after Sputnik I was launched on October 4, 1957. The first successful U.S. spacecraft was Explorer I, launched on January 31, 1958. A Geiger counter experiment put on board by J. A. Van Allen~ suddenly stopped counting. This anomalous behavior was investigated and it was found that the reason that the Geiger counter stopped counting was that it was, in fact, saturated by an extremely high count rate (much higher than had been expected) Van Allen concluded that the high count rate was caused by a very large number of charged particles trapped in the Earth’s radiation belts. Resolution of this anomaly led to the discovery of the earth’s radiation belts (now called the Van Allen belts). Anomalies which are carefully investigated can result in new discoveries such as the Earth’s radiation belts or in new radiation effects or damage mechanisms. 5.2 PREVENTING

SOFTWARE ANOMALIES

Preventing software anomalies is, almost by definition, very dif!lcult since they are unexpected. One way is to thoroughly check out the software. By repeatedly running the 11-28

program under a variety of conditions, potential defects can be discovered through ground simulation before launch. Even if a software defect escapes detection before launch, it can be found using the ground simulator which is kept in the same configuration as the space computer. If an anomaly is discovered in this way, it can be corrected before an action which makes use of the command containing the defect is taken by the spacecraft computer. The defect can even be discovered after activating the code, provided the action inadvertently taken by the spacecraft computer is not catastrophic. Software fixes can then be uploaded to prevent future recurrences. Even if a spacecraft is damaged or lost due to a software error, there is still a reason for investigating it thoroughly so that it can be corrected in other versions of the same or similar spacecraft or in the next generation of the spacecraft. 5.3 PUBLISHING

ANOMALY

ANALYSES

All spacecraft anomalies are taken very seriously because of their potential for producing a disaster. If the result of a spacecraft anomaly is not very visible however, e. g. if a device just upsets and can be recovered without a problem, the incident is likely to be examined briefly and noted in the log book (including the necessary corrective action), then forgotten. It is only when a spacecraft is lost, nearly lost, or if its status remains uncertain for an extended period of time that a Tiger Team is called in to trouble shoot the problem or a Board is convened to discover the cause. Very few anomalies or anomaly analyses will ever be published. There are several reasons for this. In most cases the cause is not found or pinned down completely. Many anomalies are unique to the particular spacecraft and reporting them through publication would not be useful to anyone other than the spacecraft operators. In addition most SPOS are not prone to publishing their errors or problems. In many ways it would be better if more anomalies were resolved and the results published. These anomalies could then be compiled and the probabilities of each type of anomaly could then be assessed for guidance to future spacecraft designers. 6.0 FUTURE TRENDS 6.1 NEW TYPES OF MILITARY

SPACE SYSTEMS

Future military space systems are facing an unusual opportunity now. With the decline of the cold war, the radiation hardness levels required for military systems are being dramatically reduced. At the same time, the Mid-east War has demonstrated the substantial advantages of space based communication, navigation and surveillance systems, and has also greatly increased performance requirements on such systems. For example, as shown in Table 12, before Desert Storm in the cold war era, there was little tactical use of space. Surveillance satellites were used primarily for intelligence purposes and so a slow revisit time of a few days or even weeks was considered quite acceptable as long as the pictures were of high quality and long term tendencies in the Soviet Union’s development of new weapons or facilities were detected in a timely manner. These satellite systems had large area coverage at low or moderate resolution and could make use of small area coverage at high resolution if a target was found to be of high interest. They also transferred their data to other satellites or to the ground at relatively low data rates. Communication among U.S. strategic assets and with the Navy’s fleet was handled primarily through the use of survivable geosynchronous communication satellite systems such as II -29

FLEETSATCOM, DSCS II and III, UHF FOLLOW-ON, and MILSTAR The Global Positioning System (GPS) was nearing completion and was operational, but its tremendous advantages for self location by ground troops was not fully realized and small, cheap, hand sets were not very available. The satellite systems built in this era were very large, heavy, capable, billion dollar systems. II -30

After Desert Storm, the military has become highly dependent on GPS for location and tracking of troops and equipment and for other uses as well. Space surveillance is now needed for tactical purposes (such as locating SCUDS), therefore high resolution coverage of large areas (such as entire battlefields) is desired and Field Commanders want continuous, rather than intermittent, coverage which in practice means very fast revisit times. In addition, we now expect to interface our satellite systems directly with our ground and sea weapons systems in real time. For example in overcoming the SCUD problem, we wanted to detect the (hidden) SCUDS or spot them on the launch pad, detect their launch, track them, determine their trajectory at a ground-based computer in the United States, and communicate with a missile launcher on the battle field, supplying proper coordinates in time to launch a Patriot missile to intercept and destroy them. The whole process could take no more than a few minutes. According to most reports that didn’t work very well, in general, but it did work at least in part, sometimes! Now it will be expected to work correctly, all the time. MILSTAR has recently demonstrated a successful crosslink between satellites. This technology will also be used more in the future. With the changes in the political and military landscape of Europe (including Bosnia), the dissolution of the Soviet Union, and the development of new and changing alliances, there will be demands for increased flexibility in future military space systems. The prospect of shrinking defense budgets assures that the solutions must be cost effective. In this environment of reduced threats and budgets, but enhanced demand for increased capabilities, higher data rates, better coverage, and more flexibility, there will be a great deal of pressure on the military to develop an entirely new generation of more capable, but cheaper, satellite systems. Furthermore, the reduced budgets and new policies on procurement of commercial parts whenever possible may require that the future systems be developed with commercial microelectronics and maybe using some, or even all, commercial spacecraft. This new generation of satellite systems will almost surely not be as large or as heavy, or as expensive as present systems, but it will have to be more capable and flexible. 6.2 PROJECTED SPACECRAFT

INCREASES

IN NUMBERS

AND

TYPES

OF COMMERCIAL

During the last several years, there has been an explosion in interest in commercial satellite systems. They have been proposed for world-wide cellular telephones, data transmission, faxing, direct broadcast television, movies and video conferencing as shown in Table 13. The projected investment in these new satellite systems is truly phenomenal, and the companies involved propose to build well more than 1000 spacecraft in the next ten years. The largest proposed system is that of Teledesic with 840 satellites plus spares for a total of nearly 1000 satellites in that one system alone. The cost of this system is projected at $9 B. Teledesic and other commercial communication satellite systems are shown in Table 14. The five systems described above in Table 14. are by no means the complete complement of proposed systems; there are at least 10-15 more that regularly are reported in newspapers. It is doubtful that all of these satellite systems will be able to obtain funding, FCC licenses, and be built. The five shown above are the larger cellular telephone satellites and are in general more likely to be developed than some others. As illustrated above, world-wide cellular telephone systems require very large numbers of spacecraft to provide global coverage and hence they require very large investments. There are certain trade-offs which are critical 11-31

,,

II -32

,

to the design of the system. The lower the orbit the smaller the ground antenna and the lower the power required for good signal strength. For hand held personal communications this is a critical need. Unfortunately, the lower the orbit, the larger the number of satellites required to obtain adequate coverage and the expense of the system goes up. To reduce the number of satellites, a designer must raise the orbit and this means larger antennas and more powerful transmitters. This type of system is more suitable for large, fixed ground stations. Of course as the orbits rise up into the intense radiation belts, the radiation-induced anomalies will increase too. There are other classes of commercial satellites including navigation, meteorological and remote imaging spacecraf~ The direct broadcast television system, which recently became operational is a satellite system designed to compete with cable TV. These commercial space systems are, in general, substantially smaller and lighter than military systems, but are remarkably capable. Not all of these systems will be economically viable and some of them will not be completed, but in the long run, competition for business will determine which ones succeed and which ones fail. This intense competition will generate strong pressure to use the latest state of the art devices in new systems to gain increased capability, but it will also require using devices which are sufficiently hard to survive in the orbits in which the spacecraft operate. Note that some of the systems shown in Table 14 operate in very severe orbits from a radiation standpoint. Any commercial space systems which develop a large number of anomalies will have serious problems if the anomalies cannot be resolved quickly and without significant impact on their users. Future commercial users will be even less understanding about anomalies, downtimes, and failures than present military and NASA users are. 6.3 SPACE EXPERIMENTS

TO GET HIGH TECH TO SPACE IN RECORD TIME

In the current design and construction of space systems, it is typical for it to require five to seven years from the time that the technology of choice is frozen until the spacecraft is actually launched. As shownain Figure 26, the devices must be chosen early in the program in order to provide time to order the devices, radiation test them, build an engineering model, build a flight qualified model, build a flight model, perform flight qualification testing, integrate the subsystem into the spacecraft, and launch it. The lead time gets even worse if there is a delay in launching the satellite. Satellite systems would benefit greatly if we could find a way to reduce the amount of time between the technology freeze date and the start of actual satellite operations. The use of smaller, less complex, less costly satellite systems will help reduce these times somewhat. There is a tremendous advantage of using the latest state of the art devices in space systems. These devices may represent breakthroughs in technology which can increase performance by several orders of magnitude, or they maybe just the latest device which has a factor of two or less gain in performance. In either case, there is a strong reason to try to get the devices or technology into space as rapidly as possible. There is only one small problem; namely, space System Project Offices (SPO’S) have been badly burned in the past by using new technologies in which the new vulnerabilities were not fully understood. This has a tendency to make them very sensitive to new technologies and to make them reluctant (with good reason) to rapidly introduce new technologies into their systems if they have not been For small changes, such as the newest generation of previously flight qualified. II -33

F~re

26 Typical Times Required to Build Space Hardware

[After Fox, Ref 44]

microelectronics, the problem is rather easily solvable. Thorough testing of the new devices at ground-based radiation facilities is generally suftlcient. The rest of the space qualification occurs as a part of qualification testing for the system. For the breakthroughs in technology, however, it is an entirely different matter; flight qualification is essential. The problem is, of course, how does a new technology get space qualified if no one is willing to fly it first? The only viable answer for the future, in my opinion, is to fly the newest technology in space experiments. In the future, space experiments will be used to demonstrate the performance gains of the new technology, and to show that they do not have any radiation effects or anomaly show stoppers. In this way we can get our latest generation of new devices and technologies into space in the most rapid time possible and increase the performance (and 11-34

reduce costs) of our next generation of space systems. In a properly designed space experiment, devices can be operating in space for the first time about one year after their initial acquisition. Before spacecraft System Program OffIces (SPOS) would be comfortable flying new technologies, the risk of using such technologies will have to be reduced. To reduce risk will require space testing of the modern generation of devices (sub-micron feature size) with concurrent more accurate ground testing and modelling programs and the development of prediction methods which more accurately predict the on-orbit performance of sub-micron devices. Better models are, of course, also needed for each significant change in technology It will also require better measurements of the space environment which occurs. simultaneously with measurement of space upset rates to reduce uncertainties. By using more accurate tests, models and environments we can reduce the over-all uncertainty associated with these new devices or technologies and therefore reduce the safety factors required for assurance of space system survivability and operability with a minimum of anomalies. If the uncertainties in predictions of radiation effects can be reduced, then spacecraft can be safely flown with much smaller safety margins. This will permit more modern devices to be flown. Carefully designed space experiments can make it possible for the next generation of space systems to have significant increases in performance, while maintaining the same reliability and operability. 6.4 NEW TECHNOLOGIES

AND RADIATION

EFFECTS CHALLENGES

When considering what the new technologies for space are going to be, it is never a good bet to bet against silicon. Silicon has run up against limit after limit and the Gurus have predicted it would lose out to a new technology only to see it overcome this new hurdle and out-perform its rival. It is a safe bet to say that for the foreseeable future silicon will be the technology of choice for the great bulk of the applications as shown in Table 15. There is a new emphasis on developing very large silicon solid state memories to replace less capable and less reliable tape units in spacecraft. These new solid state memories are like a loaf of bread made up of many slices. Each slice, however, is the latest state of the art memory unit available, currently a 16 Mbit or 64 Mbit Dynamic Random Access Memog (DRAM). There may be as many as 50-100 slices to produce multi-gigabit memory units. These large memories are extremely capable, but they are also very vulnerable to total dose, SEE, and probably to future anomalies. Large RAM’s, gate arrays, application specific integrated circuits (ASIC’S), and other logic circuits are the most used digital parts in space systems today. Gate arrays are finding a multitude of new uses in space. It appears likely that in the future we will have a very large number of new, high technology space systems. The effects of new technologies on new military and NASA space systems can already be seen. There is a shift from copper wired spacecraft with very large, heavy and expensive cable harnesses to a new generation of spacecraft which use Fiber Optic Data Busses (FODB) in place of wires as shown in Table 16. This can provide data transfer systems which are not only much lighter and less expensive, but also much higher speed (up to a few gigabits now) and more flexible. These new FODB’S will also contribute greatly to the ease of assembly of new spacecraft. The various spacecraft subsystems can be connected much more easily with fiber optic connections, rather than the more expensive and complex wiring harnesses. Furthermore, the wiring harnesses have to be soldered into place and if any II -35

connections need to be changed, it is very difllcult to make those reconnection, whereas, with a FODB system, recoupling is easy. It is expected that spacecraft will be able to be assembled in a matter of days rather than weeks, using the fiber optic technology. A typical ring data bus is i11ustrated4Sin Figure 27. The shift toward the use of fiber optic devices in space and toward faster subsystems and higher data rates has forced us to move from slower silicon devices to faster GaAs devices and very recently to even faster InP devices. Such moves can have large consequences from

II -36

the standpoint of vulnerability to SEE phenomena, total dose effects, and the occurrence of spacecraft anomalies. For example, GaAs has been shown to be somewhat less sensitive than silicon to total dose effects, but extremely sensitive to SEE. A new technique for growing GaAs at low temperatures (LT GaAs) has recently been shown to produce GaAs devices which have many orders of magnitude lower SEU cross sections~. A buffer layer is first grown at low temperatures of a few hundred degrees C, then annealed at higher temperature forming arsenic precipitates. These form charge trapping and recombination centers which do not allow any charge which may be deposited in the device to be collected thus providing a reduced SEU cross section. As illustrated in Table 17, these LT GaAs devices have the advantage of high speed performance, less sensitivity to backdating, Figure 27 TRW_HONEYWELL FODB Ring and low SEU cross sections similar to those [After Dale, Ref 45] of silicon devices. Figure 28 illustrates47 the reduction in sensitivity of LT GaAs over regular GaAs. The standard GaAs cross section is shown for a 336 stage shift register as a function of LET. When the same tests were made for an identical device with a LT GaAs buffer layer, no upsets were observed up to an LET of 90!

-d

‘!jijbk?. FODBRing

lnP has great potential for use in space. It is useful both as solar cells and as high speed devices. Its characteristics are shown in Table 18. Figure 29 showsa the radiation response of a selection of silicon, GaAs and InP solar cells. The beginning of life etllciency of both GaAs and InP are comparable and both have higher etliciency than silicon. Notice how much flatter the InP curves are than the silicon or GaAs curves. InP on silicon is not as well developed as InP on InP so its beginning of life efllciency is not as high but it is a much better material and much less expensive. InP has the potential to be a technology enabling technology because it II -37

HONE~LL G NQ 5

v ‘0-6

~

10-’

[+”’0

o

~ *= dl

“m

v

E 0 v

v

v C-12

98

MeV

FI-19 130 MoV Cl-35 209 MoV NI-58 260 M@V 1-127 320 MeV

10-8

1?

IJJ .* m

GaAs SEIUAL

m

8

9

10-5

~ 8 8 d

336 STAGE STANDA~ SHIFT REGISTERS

100

10”9

0

Serial

Mbps

m 40

m 20 LET

Data

Rata 1 60

9 80

100

(Me V*cm2/mg)

NO UPSETS OBSERVED ON DEVICES WITH LT BUFFER LAYERS UP TO AN LET OF 90

Figure 28 Reduction in Sensitivity in LTGaAs Shift Registers Compared to GaAs Devices [After Marshall, Ref 47] can be operated anywhere in the Earth’s radiation belts. This will permit satellites to be launched ‘much more-cheaply into a LEO orbit, then powered by low thrust thrusters to reach a geosynchronous orbit in weeks or even months and yet still have excellent solar power when they get there. InP is also a useful material for use in devices with its low SEU cross section, total dose insensitivity, and its very high speed performance; its only problem right now is that it is not easy to produce and package. InP is even less sensitive to total dose effects, and has been recently shown to be very insensitive to SEU49 as well. Figure 30 shows the cross section as a function of proton energy for an InP data sequence generator chip compared to unhardened GaAs. As the speed of a device increases its upset cross section also increases as shown in the II -38

figure for GaAs. The GaAs operates at 400 M bps, whereas the InP device operates at 13 G bps and yet has a SEU cross section three orders of magnitude lower.

Radiation Response of lnP/lnP lnP/Si, GaAslGe, and Si Solar Cells .

-20 $

AMO

c 6.5 USE OF COTS IN FUTURE SPACECRAFT

.{) .; w 10 c o -

In June 1994 Defense Secretary William ● InP/inP Perry issued a directive to . lnP/Si (2x4 cm2, Spire, 1995) t! military to use COTS a?s - ■ G~Ge parts in military systems (Solar Cell Radiation Handbook Addendum) c whenever possible. v Csi Regardless of the 6 (Solar Cell Radiation Handbook) , u directive, it is becoming a :.,2’ “’’;.,3’ “’1’014’ “’1 0,6’ 10’6 10’7 diftlcult problem to build spacecraft because of the 1 MeV Electron Fluence (cm-2) lack of hardened parts. .,. Military, NASA, and commercial spacecraft Figure 29 Radiation Response of InP Solar Cells Compared to builders may be forced to Silicon and GaAs Cells [After Walters, Ref 48] use COTS, even if they don’t want to, in future space systems. However, use of COTS in space systems contains significant risk. Let us examine the use of COTS parts in future space systems. ●

The advantages of using COTS devices in future space systems are shown in Table 19. The primary reason for wanting to use COTS devices is that they are state of the art devices,

II -39

whereas rad hard devices are hardened several years later than the same COTS device and hence Hughes lnP\ Proton Upset Test Results use several year old This means technology. I 1 1 1 10-9 that COTS devices are an Hughes 13 Gbps’ lnP ve. Unhardened Motorola GaAs ! order of magnitude more capable than rad hard devices. The choice is between a COTS Pentium or a rad hard 286-386 The microprocessor. choice is between a 64 M bit DRAM or a 1 M bit ,o-f4~ In addition, SR4M. 70 10 are COTS devices less substantially Proton Energy (Mev) expensive than rad hard devices. The worst case difference in price which I have encountered is for an RH 3000 which we wanted to buy for a space Figure 3(J Cross Section vs Proton Energy for InP Sequence The experiment. Generator Chip Compared to GaAs [After Marshall, Ref 49] microprocessor plus four or five glue chips would alone was $17 K and there was a lon~ and have cost nearly $100 K. The micromocessor . uncertain delivery time. We chose a less capable rad hard 3081 microprocessor, but in the 1

H -40

I

I

1

1

1

right orbit, we could have purchased a 64 bit IDT 4650 microprocessor for a few $ K, and had a more capable device. Commercial software is often much more available for COTS devices than for rad hard devices. Software development is a very costly part of building space systems today and is growing rapidly in complexity. If rad hard devices are not identical to an earlier version of a commercial device, then space system designers will have to develop much, if not all of the software for it. This is both expensive and time consuming. In addition, non-commercial software must be checked extra carefully for any errors and for its response to unexpected situations. It could become a prime candidate fo-rlater spacecraft anomalies. The U. S. rad hard electronics market was < 0.4°/0 of the commercial market and is shrinking rapidly. In 1991, there more were than 20 manufacturers of rad hard devices. Now, it is hard to count more than three or four (see Figure 31). The reasons why rad hard manufacturers are going out of business (or have gone) are illustrated in Table 20. The Cold War is over. Large and costly strategic systems such as nuclear missiles and radiation hardened satellite systems are going to be built in much fewer numbers. This leads to a perceived loss of future in the field and so it does not encourage investment in the area. Secondly, because of increases in commercial electronics orders (including those destined for commercial

CURRENT UNITED STATES RADIATION-HARDENED DEVICE SUPPLIERS ● ●

Honaywell Natkrlal

●

Loral

●

UTMC

DEVICE SUPPLIERS WHO NO LONGER SUPPORT THE RAD-HARD MARKET LSI ● TI

●

● ● ● ● ●

TRw Rockwell Im GE (RCA) sandia

● ●

Hughaa Raythaon

●

Martin-Marbtta

●

McDonnalkDougka

●

Motorola

● ●

Ford Mlcroekotronks AT&T

F@re 31 Current Radiation Hard Device Suppliers vs Suppliers in 1991

II -41

,.

,

space systems), the demand for commercial devices is beyond the current manufacturing capability. In addition, the commercial market is more profitable. When a company has unfulfilled orders for a high profit item and very few orders for a low profit item, it doesn’t take a rocket scientist to predict their course of action. Finally, equipment for each new generation of devices is becoming more expensive. A major change in device technology may cost up to $1 B or more for new equipment. Device manufacturers have to make these large investments every few years. Such an investment is not made lightly. In this environment, a large investment would certainly not be made for what could be perceived as a niche market. We have outlined the reasons for wanting to use COTS devices in future space systems, but there are many reasons why it will be difficult to use COTS devices in space. Some of the reasons are shown in Table 21. Survivability in even the natural space environment would now be ditllcult with many COTS devices, some of which are harder than 100 Krads and some of which are softer than 10 Krads. Of course, it depends on the orbit, and requirements for a system may vary from 10-20 Krads to 100 Krads or more. Many COTS devices are soft now, and advanced devices will be softer. In addition, COTS hardness varies somewhat making COTS hardness assurance an important new research area. Furthermore, while the reliability of COTS devices used in normal environments is no problem, their reliability in stressing environments (radiation, thermal, vibration, etc.) is uncertain. SPO’S will need to perform a large amount of measurements and testing to gain confidence in the space reliability of COTS devices in stressing environments. In order to be able to use COTS devices in future satellite systems, SPOS will need to buy them in large lots, possibly directly from the manufacturer, test them for radiation and other stresses, and place them in bonded storage until used (effectively space qualify the devices).

TABLE

21.

COTS

IIISAI)VANTAGES

Survivability In Many Desirable Orbits is Difficult Using Some COTS Devices, Other COTS Devices Will Survive in Most Orbits Many COTS Devices Fail Now at 10-50 Krads - Advanced Devices Will Be Softer Cots Hardness Is Not Controlfed and Varies Widely Reliability Of COTS Devices In Stressing Environments

Is Uncertain

COTS Devices Will Need To Be Tested And Placed Into Bonded Storage Cots Devices Will Have To Be Space Qualified There Is A New Generation Of COTS Devices Every 6-18 Months Safetv Factors Currentlv Used Are Too 13i@hfor Manv COTS

~evices

Another problem which will have to be faced is that COTS devices change rapidly; there is a new generation every 6-18 months, and small changes are made more often than that. This is both good and bad news. The good news is how rapidly a new device becomes available which is faster, more capable, or lower power. The bad news is that if you need a few II -42

more devices, after you have built the system, you may not be able to buy them because they are obsolete. Finally, the large safety factors often used in satellite systems are frequently too big for using COTS devices. For one space system we are working on, in the early 1980’s we somewhat arbitrarily set a specification of 100 Krads. We did this because it was not very difficult to get 100 K rad parts, and they were safe to use. Gradually we began getting more and more exceptions to the specification. We have recently reexamined the specification and now sometimes use 30 K rad parts and sometimes even less. Our on-orbit dosimeters show an expected dose of about 10 Krads in the spacecraft lifetime This safety factor has been reduced over the years and having an on-orbit dosimeter has certainly helped us to make that decision. We still buy 100 K rad parts whenever they are available. Any satellite system that plans to use COTS devices will have to depend on smaller safety factors; safety factors of ten will become increasingly diftlcult to obtain. 6.6 TESTING,

HARDNESS

ASSURANCE

AND SHIELDING

A space program which plans to use COTS devices has several alternatives for implementing radiation survivability. (It must be said at the outset that the thinking for implementing such a program has not been completed yet). First as shown in Table 22, an extensive testing program must be planned and implemented. It will be necessary to test a larger number of COTS devices to get a selection of devices which is suitable for use in a space program. It will be necessary to test devices from several manufacturers. It will also be necessary to invest in large lot buys of the devices so that if a device tests out well, or if the device manufacturer makes a change in the device there will be sutlicient devices for the space system. Poor lots will have to be used in breadboards, engineering development models, flight In many cases use of shielding will be qualified models, ground systems or discarded. required. If the system requirement is 50 Krads and only 25 K rad devices are available, then shielding is perhaps an optimal solution. Shielding is much cheaper than redesign. If only a

TABLE

EXTENSIVE

22.

USE OF COTS IN SPACE SYSTEMS

TESTING PROGRAM

REQUIRED

LOT BUYS SHIELDING ON-ORBIT UN-POWERED

SPARES

LATCHUP SCREENS EDC OR TMR MAY BE REQUIRED MUST DEVELOP NEW TECHNIQUES

FOR HARDENING

II -43

CRITICAL DEVICES

small number of devices with insutlicient hardness are to be used, then spot shielding is the preferred option. If a large number of devices with insufficient hardness are to be used in the system, then box shielding is likely to be more effective. The tendency toward building smaller, monopurpose spacecraft such as proposed by NASA may acerbate this problem. A possible solution which has not yet been proven, but which may be employed in future systems, is the use of on-orbi~ unpowered spares. To the extent that unpowered devices damage much less in a radiation environment, it may be possible to fly a small number of devices, e.g. two to four, in place of one very sensitive device. As the device damages a new, previously unpowered, device is switched in as a replacement. This would be a high risk procedure at present and the concept must be tested in a space experiment before it could be implemented in an operational space system. It may also be necessary to use a small number of devices for which none of the above approaches will work For example if the devices contemplated for the system have a measurable Single Event Latchup (SEL) cross section, most SPOS would not permit their use in their system. A device with a high SEU cross section or a very low total dose tolerance could also result in the proscription of its use. Alternatives such as Error Detection and Correction (EDC) codes or Triple Modular Redundancy (TMR) could certainly be used to help reduce the SEU problem in many cases, but at a cost of system efficiency. There would almost certainly remain a number of devices for which the above solutions would not work but yet were necessary to operate the system. In order to use these devices the SPO would have to harden them to total dose, SEU, and SEL. 6.7 USE OF PLASTIC PARTS At present many SPOS are being forced to consider the use of parts in plastic packaging because so many commercial parts come that way. There is still the feeling that these plastic parts still have lower reliability. Table 23 shows some of the considerations involved in making a decision to use plastic parts. There is currently a large disagreement among SPOS about the use of parts in plastic packages in their space systems. Some SPOS say they would redesign the whole system rather than use a plastic part. Others say that in the future they may have no choice but to use plastic parts because of the unavailability of parts in space qualified packaging. In the past parts in plastic packaging have not been as reliable as parts in ceramic or metal containers. There are some indications that this is changing, but the question is will they be reliable in stressing environments such as space with high radiation levels, a wide temperature range, high vibrational levels, etc.? This information simply is not known at present. Furthermore a new problem has recently surfaced. Devices have been shownW to exhibit different behavior in a radiation environment after burn-in than they do if they are not burned-in as shown hJ Figure 32. For devices in ceramic or metal packaging the problem is small, but for devices in plastic packaging, the problem appears critical. The flight qualified parts must be treated in exactly the same manner as the parts which will be flown. 6.8 NEW TECHNOLOGIES

AND NEW EFFECTS IN FUTURE SYSTEMS

Whenever new technologies are introduced into a new radiation environment such as space, new effects and anomalies are discovered. Furthermore, as shown in Table 24, the II -44

advances in technology in recent years has resulted in devices which have: (1) smaller feature sizes; (2) faster operation; (3) lower voltage and lower All of these power. desirable goals lead to devices which are more vulnerable to the effects of radiation. Smaller feature size means less capacitance, for example, and hence information is stored with less charge. Faster operation means that a decision that a zero or a one should be stored is made with less charge for the same current. Use of lower voltage or lower power devices means that less charge or energy is required to store

Cilii9

ICCJ-IMax vs. Dose/AnrIealfor Four Groups at High Dose Rate

Ckm

_Maxbnum

ICCHSrIK

+mE-oa 1.DOE44

1.00E48

1-* imlE-09 low-n 1.WE.11

PmRad

m Oow

(1%

180

Ambd

Figure 32 Difference in Behavior of Devices in a Radiation Environment Before and After Bum-in [After Clark, Ref 50]

II -45

,.

information. In each casq the information is stored using a smaller number of electrons. Each of these effects makes the device more vulnerable to radiation and means that small effects which were once negligible such as a cosmic ray or a proton passing through the devices are now much more likely to produce upset or damage. In the future this can only get worse. In this environment military, NASA, and commercial spacecraft builders will have to find costeffective ways of using devices which have become more vulnerable while at the same time controlling the effects of radiation-produced anomalies, upsets, and failures. If a new, serious, radiation effects problem were to come up as a result of reduced feature sizes or new technology, for example, then it is clear that we will not have the enormous resources at our disposal that DoD put into radiation hardening in the 1970’s and 1980’s.

II -46

Suppose the trends that we have been discussing come into practice in the near future. be? This question is addressed in Table 25, The device changes What will the consequences listed seem unavoidabk The technology changes and implementation choices are options for the SPO to decide, although he may ultimately have little choice about COTS or plastic packaging

use.

If the changes shown in Table 25 occur then there are going to be consequences which rmult direct4y from these changes. These projected consequence are shown in Table 26. Most of the changes will result in an increase in the number of anomalies and effects which have been hidden by the use of large safety factors will begin to show up, such as dose rate effects. One should not be unduly alarmed by the consequences listed in Table 26. Introduction of changes into new space systems is a self limiting process. If SPOS begin to get in trouble, they will become more consemative and introduce fewer changes. If they introduce a large number of these changes and still do not have insurmountable problems, they will end up with very flexible, high performance systems. The radiation effects community needs to provide them with a variety of good alternatives.

TABLE

26.

PROJECTED

PROBLEMS

FOR

FUTURE

SPACE

SYSTEMS

I

ACTION

CONSEQUENCE INCREASE

DEVICE

IN SINGLE

EVENT EFFECT$

MORE TOTAL DOSE EFFECTS

CHANGES

MORE DISPMCEMENT DEVICE AND TECHNOLOGY CHANGES

DAMAGE

I INCREASE IN ANOMALIES

I NEW

TYPES OF ANOMALIES

R4DIATION HARD DEVICE AVAHABILITY CHANGES

INCREASE IN ALL RADIATION INDUCED ANOMALIES AND FAILURES

IMPLEMENTATION

TNCREA$E IN ANOMALIES

CHOICES

I DOSE RATE EFFECTS APPEAR

7.0

CONCLUSIONS

AND SUMMARY

The first part of the paper has discussed the various effects which can produce anomalies in space systems concentrating on radiation-induced anomalies. The types of radiation-induced anomali~ discussed were ESD-surface and deep dielectric, SEE, total dose, and displacement damage effects. Other non radiation-induced anomalies were also discussed including operator error, mechanical malfunction, and software errors. The impact that anomalies can have on a space system has been illustrated with a number of examples. The II -47

causes of the anomalies are always important, but are usually very difficult to pin down. There are a number of clues to the causes such as the description and time of the anomaly, orbit, position in orbit, radiation environment and the previous anomalies observed on the spacecraft (or in similar spacecraft). Space environment data provides very valuable clues as to the causes particularly if a solar flare is present at the time or if the spacecraft is in an intense part of the radiation belts when the anomaly occurs or if the spacecraft is in a geosynchronous orbit and the anomalies occur predominately at a specific local time range. The Mars Observer and Clementine anomalies were discussed in some detail to illustrate how a Failure Review Board works and how many possible causes there can be for a complex anomaly. The second part of the paper discussed the new types of military, NASA, and other space systems which are being built or are in the planning stages. The use of new technology was described and the use of COTS and devices in plastic packages was discussed. The impact of the use of new technologies and devicm was also described.

II -48

8.0 REFERENCES

1.

Webster’s New Unive~l Unabridged Dictionary, and Schuster, New York, New York, p 75, 1983

2.

E. G. Stassinopoulos,

3.

D. M. Sawyer and J. I. Vette, “AP-8 Tnapped Proton Environment for Solar Maximum and Solar Minimum,” NSSDC/WDC-A-R&S 7(X)6, GSFC, Greenbelt, MD, (Dee 1976).

4.

M. J. Teague, K. W. Chan and J. I. Vette, “AE:6, A Model Environment of Trapped Electrons for Solar Maximum, ” NSSDC/WDC-A-R&S 76-04, GSFC, Greenbelt, MD, (May 1976) and G. W. Singley and J. I. Vette, “The AE-4 Model of the Outer Radiation Zone Electron Environment, HNSSDC 72-06, GSFC Greenbelt, MD, (August 1972). E. G. Stassinopoulos,

Second Edition,

Sirnon

NASA Goddard SFC, Private Communication,

NASA Goddard SFC, Private Communication,

1978.

1984.

J. H. Adams Jr., R. Silberberg, and C. H. Tsao, “Cosmic Ray Effects on Microelectronics, Part I: The Near Earth Particle Environment, ” NRL Nlemorandum Report 4506, (1981). 7.

J. H. Adams Jr. and A. Gelman, “ The Effects of Solar Flar~ on Single Event Upset Rates”, IEEE Tnm.s. Nut. Sci., NS-31, 1212, (1984).

8.

J. H. Adams Jr. and A. Gehnan, HThe Effects of Solar Flares on Single Event Upset Rat~”, IEEE Trans. Nut. Sci., NS-31, 1212, (1984).

9.

J. H. Allen and D. C. Wilkinson, “Solar-Terrestrial Activity Affecting Systems in Space and on Earth” PUblished in So lar-Terrestrial R-e clicticmsIV Proceedings, Vol 1, pp 75-107.

10.

J. H. Allen and D. C. Wilkinson, ‘Solar-Terrdrial Activity Affecting Systems in Space and on Earthn Pub lished in Solar-Terrestrial PredictionslV Proceed imzs, Vol 1, pp 75-107.

11.

J. H. Allen and D. C. Wilkinson, ‘Solar-Terre&rial Activity Affecting Systems in Space and on Earth” PUblishe(l in So lar-Terr@rial PreclictionsIV Proceedin~s, Vol 1, pp 75-107.

12.

D. A. hlcphe~on and D. R. Schober, “Spacecraft Charging at High Altitudes: The SCATHA Satellite Program, ” presented at the AIAA 13th Aerospace Scienc= Meeting, Pasadena, CA, January 20-22, 1975.

13.

D. A. McPhemon and D. R. Schober, “Spacecraft Charging at High Altitudes: The SCATHA Satellite Program, ” presented at the AIAA 13th Aerospace Scienc~ Meeting, Pasadena, CA, January 20-22, 1975. II -49

14.

S. E. DeForest, “Spacecraft charging at synchronous Gecm hysical Resea rch, Vol. 77, 651 (1972)

15.

M. D. Violet and A. R. Fredrickson, “Spacecraft anomali= on the CRRES Satellite Correlated With the Environment and Insulator Samples”, IEEE Tnm.s. Nut. Sci.,NS-40, Dec. 1993

16.

C. E. McIllwain, “Coordinates for Mapping the Distribution of Magnetically Tmpped Particles”J. Geophys. Res., Vol 66, p 3681, (1%1).

17.

J. T. Wallmark and S. M. Marcus, “Minimum Size and maximum Packaging Density of Nonredundant Semiconductor Devices”, Proc. IRE, ~, 286 (1962).

18.

D. Binder, E. C,. Smith, and A. B. Hohnan, “Satellite Anomalies From Galactic Cosmic Rays, ” IEEE Trans. Nut. Sci., NS-22, 2675 (1975).

19.

T. C. Nlay and M. H. Woods, “Alpha Particle Induced Soft Errors in Dynamic Memories, ” IEEE Trans. Elec. DeV. ED-26, 2 (1979).

20.

J. C. Pickel and J. T. Blandford, “Cosmic Ray Induced Errors in MOS Memory Cells, n IEEE Trans. Nut. Sci., NS-25, 1166 (1978).

21.

C. S. Guenzer, E. A. Wolicki, and R. G. Allas, “Single Event Upset of Dynamic RAMS by Neutrons and Protons, n IEEE Trans. Nut. Sci., NS26, 5048(1979)

22.

R. C. Wyatt, P. J. McNulty, P. Toumbas, P. L. Rothwell, and R. C. F&, “Soft Errors Induced by Energetic Protons, ” IEEE Trans. Nut. Sci., NS26, 4905(1979).

23.

J. H. Allen and D. C. Wilkinson, “Solar-Terrestrial Activity Affecting Systems in Space and on Earth” PUblished in So lar-Terrest rial PredictionslV Proceed inm, Vol 1, pp 75-107

24.

J. H. Allen and D. C. Wilkinson, “Solar-Terr@rial Activit y Affecting Systems in Space and on Earth” PUbli,shed in Solar-Terrestrial PreclicticmsIV Proceed inm, Vol 1, pp 75-107

25.

C. Barillot, 1995.

26.

C. Dyer, ‘In-Flight

27.

T. Goka, S. Kuboyama, Y. Shimano, and T. Kawaanishi, “The On-Orbit hle.asurements of Single Event Phenomena By ETS-V Spacecraft”, IEEE Trans. Nut. Sci., NS-38, 1693 (1991).

“In Flight Observed Anomalies,

Experiments,

II -50

” RADECS

orbits, ” Journal of

RADECS 95 Short Course,

95 Short Course,

1995.

28.

T. Goka, S. Kuboyama, Y. Shimano, and T. Kmwaanishi, “The On-Orbit Measurements of Single Event Phenomena By ETS-V Spacecmift”, IEEE Trans. Nut. Sci., NS-38, 1693 (1991).

29.

L. Adams, E. J. Daly, R. Harboe-Sorensen, R. NickSon, J. Haines, W. Schafer, M. Conrad, H. Griech, J. Merkel, T. Schwall, and R. Henneck, ‘A Verified Proton Induced btchup in Space”, IEEE Trans. Nut. Sci. NS-39, 1804 (1992).

30.

L. Adams, E. J. Daly, R. Harboe-Sorensen, R. Nickson, J. Haines, W. Schafer, M. Commd, H. Griech, J. Merkel, T. Schwall, and R. Henneck, “A Verfiled Proton Induced btchup in Space”, KEEE Trans. Nut. Sci. NS-39, 1804 (1992).

31.

J. S. Mayo, H. Mann, F. J. Witt, D. S. Peck, H. K. Gurnmel, and W. L. Brown, “The Command System Malfunction of the TeLstar Satellite, ” NASA SP-32, Vol. 2, June 1%3.

32.

E. Weuaas, “Spacecraft Charging Effects on Satellites Following the Starf~h Event, ” CSC Report H/3-J-280, February 1978.

33.

R. E. Fischell, “ANNA-lB Solar Cell Damage Experiment, ” Tram ril)t _ of jhe Photovoltaic Suecialists Co fere ce. April 10, 1963, Washington D.C. (Available from Defense Docu;enta;ion Center as PIC-SOL 209/3 July 1963).

34.

W. L. Brown, J. D. Gabbe and W. Rosenzweig, ‘Results Radiation Experiments”, NASA SP-32, Vol 2. June 1%3.

35.

J. H. Allen and D. C. Wilkinson, “Solar-Terrestrial Activity Affecting Systems in Space and on Earth” N blishecl in So lar-Terrestrial Predicticmsrv proceed inm, Vol 1, pp 75-107.

36.

W. J. Stapor, A. B. Campbell, J. Golba, and P. T. McDonald, “Spacecraft Anomalies and Testing: OptO-isolators”, to be published.

37.

W. J. Stapor, A. B. Campbell, J. Golba, and P. T. McDonald, “Spacecraft Anomalies and Testing: OptO-isolators”, to be published.

38.

W. J. Stapor has assisted in the analysis of this correlation. Communication.

39.

Report of the Marx Observer Mission Failure Investigation Board. A Report to the Administrator, National Aeronautics and Space Administration on the Investigation of the August 1993 mission failure of the Itlars Observer spacecraft. Submitted by the Mars Observer Mission Failure Board. 31 December 1993.

11-51

of the Telstar

Private

40.

Report of the Man Observer Mission Failure Investigation Board. A Report to the Administrator, National Aeronautics and Space Administration on the Investigation of the August 1993 mission failure of the Mars Observer spacecraft. Submitted by the Mars Observer Mission Failure Board. 31 December 1993.

41.

“A Clementine

42.

Clementine Report

43.

J. A. Van Allen and L. A. Frank, ‘Radiation Radial Distance of 107,400 km”, Nature, Vol J. A. Van Allen, C. E. Mcllwain, and G. H. Observations With Satellite 1958 Epsilon,” J. (1959).

44.

A. J. Fox, NRL, Private Communication.

45.

C. J. Dale, NRL Private Communication.

46.

C. J. Dale, NRL Private Communication.

47.

P. Marshall,

48.

R. Walters, NRL, Private Communication.

49.

P. hlarshall,

50.

S. D. Clark, J. P. Bings, M. C. Maher, M. K. Williams, D. R. Alexander and R. L. Pease, “Plastic Packaging and Burn-in Effects on Ionizing Dose Response in CMOS MicrocircuitsH, IEEE Trans. Nut. Sci., Vol 42, No. 6, (Dee, 1995).

Collection”,

Spacecraft

NRL/SFA

NRL/SFA

NRL/PU/1230-94-261,

Failure

Report,

June, 1994

June 24, 1994 (IX-aft Version) NRL

Around the Earth to a 183, p 430, (1959) and Ludwig, ‘Radiation Geophys. Res. Vol 64, p 271,

Inc. Private Communication.

Inc. Private Communication.

II -52

1996 NSREC SHORT COURSE

SECTION

III

TOTAL DOSE RESPONSE OF BIPOLAR MICROCIRCUITS

Naval Stiace

David W. Emily Warfh.re Center, Crane Division

TOTAL DOSE RESPONSE OF BIPOLAR MICROCIRCUITS

David W. Emily Crane Division Naval Surface Warfare Center

This work was supported in part by the Naval Surface Warfare Center, Crane Division, and the Defense Nuclear Agency

III-1

III-2

TOTAL

DOSE RESPONSE OF BIPOLAR

MICROCIRCUITS

David W. Emily Naval Surface Warfare Center, Crane Division Technology Development Branch 1.0

2,0 3.0

4.0

5.0

6.0

7.0

8.0

Introduction Bipolar Integrated Circuits in Modern Space Systems 1.1 Historical Perspective 1.2 Fundamentals of Bipolar Transistor Operation Bipolar Transistor Structures Vertical, Lateral, and Substrate Devices 3.1 Fabrication 3.2 Circuit Implementation 3.3 Transistor Total Dose Effects 4.1 Substrate, Sidewall, and Surface Inversion Gain Degradation 4.2 Integrated Circuit Response Digital 5.1 Linear 5.2 Low-Rate Effects Introduction 5.3 Low-Rate Effects Basic Mechanisms Theories 6.1 Transistor and Circuit Response 6.2 6.2.1 Bias Effects 6.2.2 Temperature Effects 6.2.3 Anneal Effects Modeling 6.3 SEM Irradiation 6.4 Hardness Assurance Test Method Development High-Temperature Irradiation 7.1 Post-Irradiation Anneal 7.2 Overtest 7.3 Future Trends and Conclusions

1.0 INTRODUCTION This session of the short course will discuss total dose effects in bipolar devices and microcircuits. Research into total dose effects in bipolar technology has long been overshadowed by CMOS research, especially since CMOS became the dominant integrated circuit (IC) technology for digital circuits during the 1980s. However, bipolar technology has continued to play an important role in mixed-signal and analog microcircuits used in current space systems. Recently, there has been a renewed interest in bipolar total dose effects due to the discovery of a

III-3

low dose rate effect in bipolar transistors and circuits. Considerable information has been presented recently on complex time-dependent effects in numerous bipolar processes. These may cause substantially lower failure levels at low dose rates with possible serious implications for space systems employing such devices. The response of bipolar microcircuits to total ionizing dose can be complex compared to CMOS. This complex response is due to several factors. Several types of bipolar transistors, each with a different total dose response, can be present in a single circuit. Additionally, different methods of transistor fabrication by manufacturers and the sensitivity of analog and mixedsignal circuit designs to small shifts in transistor parameters all contribute to complex IC responses. This discussion will cover the spectrum of bipolar total dose effects information, from basic transistor operation to the most recent microcircuit low-rate response theories, to provide a comprehensive review of total dose effects in bipolar microcircuits. The discussion will start with an overview of the important applications that bipolar integrated circuits have in modern spacecraft power, control, and signal processing systems. A historical perspective of radiation effects in bipolar devices over the years will then be presented. The fundamental operation of the bipolar transistor will be reviewed, along with different bipolar transistor structures, fabrication techniques, and typical circuit design implementations. Next, the dominant total-dose degradation mechanisms for bipolar transistors and how they affect the response of various integrated circuit types will be discussed. This will be used to introduce the recently reported excess degradation of bipolar integrated circuits when irradiated at low dose rates. Several case studies will be presented. Potential basic mechanisms responsible for the lowrate effect will be explored. Techniques used to investigate the low-rate response and results will be presented. These include temperature, bias and anneal tests, circuit modeling, and scanning electron microscope spot irradiation. Progress in the development of a hardness assurance test method for the low-rate effect will be reviewed. This short course section will conclude with a discussion of future bipolar technology trends and the potential effect on total-dose hardness. 1.1 Bipolar Integrated Circuits in Modern Space Systems CMOS has dominated as the fabrication process for digital ICS since the 1980s. For present-day digital microcircuits, bipolar is primarily limited to niche applications such as highspeed cache memories and limited mixed-technology areas such as output drivers for highWith the continual improvement in performance BiCMOS memories and microprocessors. CMOS performance, even these niche applications are rapidly converting to entirely CMOS. Bipolar remains the dominant process for linear and mixed-signal circuits, and BiCMOS is becoming an important process for high-performance analog-to-digital converters (ADCS) and The BiCMOS processes used for ADCS are considerably other mixed-signal microcircuits. different than the digital BiCMOS processes in that they are primarily bipolar or fully integrated bipolar-CMOS processes rather than CMOS with a sub-optimum bipolar device added. Bipolar is the dominant linear process due to performance advantages of higher voltage operation and current drive capability, lower noise, better linearity, and superior device matching. Figure 1 illustrates applications for bipolar microcircuits in a typical space satellite signal processing system. Bipolar microcircuits are the primary ICS used in the modern satellite power, signal processing, and control systems. III-4

The parts lists of five current production satellite systems were reviewed to identify commonly used bipolar linear ICS [1]. This review identified 162 different high-usage bipolar part types for the five satellites. Examples of the major functions that are used include operational amplifiers, analog-to-digital converters, comparators, digital-to-analog converters, analog switches, multiplexer, voltage regulators, voltage references, and pulse width modulators. Bipolar ICS account for 40?Z0to 50?Z0of the total microcircuits used in the average satellite or strategic missile system requiring radiation-hardened components. The electrical performance and parametric degradation of bipolar linear ICS are critical in many system applications. Input bias current or offset voltage is critical for an application such as a sensor buffer amplifier. Unlike digital ICS, where parametric degradation may need to be significant before having an impact on system performance, an offset voltage shift of millivolts or input bias current increase of microamps may cause serious system performance degradation. These small parametric shifts make testing linear and mixed-signal microcircuits response challenging.

ANALOG

& MIXED

Cryo Readout Multiplexer & Signal Processing

.-. r Ocal

High Precision Op-Amps

Signal

Processing

SIGNAL

APPLICATIONS Clock &

Analog-toDigital

Timing

Con;erter

GeneraIOr

Plane A may

High-Speed lnpuUOutput Interface Buffer m

Precision voltage Reference

Cfvlos Memory & Data Processor

/ J 28 Volts In –

Signal PrOcessin~COmputer Power Converter

Figure 1:

voltage Regulator

Bipolar

Microcircuit

Usagein TypicalSatelliteSystems.

1.2 Historical Perspective of Bipolar Total Dose Effects It is interesting to review the development, over the years, of information concerning total dose effects in bipolar devices and microcircuits. The evolution of bipolar technology, especially linear processes and product, has proceeded at a slow pace when compared to CMOS. To calibrate ourselves, the first commercially available monolithic bipolar amplifier to gain wide acceptance (the 709) was first introduced 31 years ago in 1965 [2]. This was followed shortly by the LM 101A amplifier in 1968[3]. This same part, with minor changes in circuit design and fabrication process, is still being designed into current and future satellites 28 years later in 1996.

III-5

As we go through this historical overview, it is also interesting to note that many of the problems then are still problems now. Research and testing performed on devices and circuits from about 30 years ago are still very relevant to the testing and research being performed in 1996. A compendium of papers primarily from the December IEEE Transactions on Nuclear Science concerning total dose effects in bipolar devices and partially used in this review is listed in Appendix A. 1967- Acceptor-Like Surface Recombination States Identified as Dominant Mechanism for NPN Transistor Gain Degradation[4] In this paper by Maier of the Naval Radiological Defense Laboratory, it was reported that, until very recently, the accumulation of positive charge has been reported as the dominant mechanism responsible for the surface effect in oxide-passivated devices. A bipolar planar npn transistor with MOS field electrodes was used to verify the existence of the positive charge effect and to introduce the existence of acceptor-like surface recombination states. The additional surface recombination states were shown to be the dominant mechanism for loss in gain. 1968- Prediction and Selection System for Radiation Effects in Planar Transistors to Identify and Eliminate “Maverick” Devices[5] In this paper by Poch and Holmes-Siedle of RCA, an irradiate-anneal test is developed to identify “maverick” transistors. During testing of many bipolar devices under Cobalt-60 gamma radiation, infrequent cases were noted where the surface damage levels exceeded those predicted. Some devices were anomalously sensitive, with damage levels falling well outside the normal statistical distribution of sensitivity. It was, thus, important to identify a method of detecting these rare, but excessively sensitive, units. These maverick devices could occur even within a production lot, all manufactured and processed in the same manner. The method developed was a 50 krad(SiOz) irradiation followed by a 250”C bake for 16 hours to return the transistor parameters to approximately pre-radiation value. The devices behaved the same on a subsequent irradiation; thus, the irradiation-anneal was a stressing method for pre-selection. 1970- Radiation-Insensitive

Silicon Oxynitride Films for Use in Silicon Devices [6]

A silicon oxynitride film deposited on the surface of a planar npn transistor and then annealed in hydrogen was shown to improve the total dose hardness by up to 30 times in this paper by Schmidt and Ashner of Bell Telephone Laboratories. 1970- Selective Irradiation to Identify Sensitive Junctions, Hardening by Elevated Temperature Irradiation and Eff:cts of Plastic Packaging on Total Dose Hardness[7] A number of topics are discussed in this paper by Bauerlein of Siemens AG Research Laboratories. Selective irradiation of npn and pnp planar bipolar transistors was performed with a narrow electron beam to show that the increase in base current occurs only if the beam is directed to the immediate vicinity of the emitter-base pn-junction. Irradiation of the remainder of the transistor surface had no effect on the current gain. In a second topic, it was reported that npn bipolar planar transistors could be total-dose-hardened if they were irradiated to a high dose at

III-6

the same time the temperature biased.

of the devices is held between 200° and 250°C while forward-

In a third topic, the effects of plastic versus hermetic metal can packaging on the total dose hardness of planar npn and pnp bipolar transistors under various bias conditions were investigated. It was reported that, in all cases, there was no additional degradation of the gain for the plastic-packaged transistors. For the npn transistors packaged in hermetic metal cans and irradiated under collector-to-base reverse voltage, it was reported that there were increased degradation in current gain and increased scatter between individual test units. For the pnp transistors packaged in metal cans and irradiated under an emitter-to-base reverse voltage, it was reported that there was a considerable increase in the degradation of current gain, 1972- Roles of Charge Accumulation Degradation[8] [9]

and Interface States in NPN Surface

The relative roles of the radiation-induced interface states and oxide charges on the surface degradation of npn bipolar planar transistors are explained in these two papers by Sivo of Boeing. Sivo reports that, in general, the new interface states are the more important factor in the surface degradation of npn transistors as long as a strong inversion of the base surface is not developed that causes a “channel” between the emitter and base contact. Charge buildup would then become the primary factor if extensive channeling did develop, which would primarily occur at high doses. It was also reported that a strong inversion of the surface by a high enough positive oxide charge would be substantially retarded by a coincident high density of interface states due to the buildup of negative charges on the acceptor-like surface states in inversion. This effect will cause an arumrent saturation in the charge accumulation with dose. The nonuniform nature of the charge buildup and the charge of the interface states can contribute significantly to low-current gain degradation at low and medium doses. At high doses, once the channeling occurs, the high-cument gain can be seriously affected as well. 1974- Use of a Scanning Electron Microscope for Screening Bipolar Surface Effects[ 10] This is the first reported use of a Scanning Electron Microscope (SEM) to irradiate pnp transistors in a paper by Lipman, Bruncke, and Crosthwait of Texas Instruments and Galloway and Pease of the Naval Ammunition Depot. Correlation of gain degradation was demonstrated between Cobalt-60 and the 20-keV electrons from the SEM.

1975- Total Dose Response of Bipolar Digital Devices [11][12][13] The first papers concerning total dose effects in digital bipolar microcircuits discuss the total dose results on high-speed emitter coupled logic (ECL) gates [11] by Daniel and Coppage of Sandia. Two papers report the effects of total dose gamma irradiation on the electrical characteristics of integrated injection logic (1%) devices and circuits [12] [13] by Pease of Naval Weapons Support Center and Raymond of Northrop Research and Technology Center.

III-7

1975- Testing and Hardening of Linear Microcircuits

14]

Ionizing radiation results are reported for a number of linear circuits, including the LM101A,LM102,LM108,LM111 , LM124, LM139, HA2520, HA2600, HA2620, and HA2700. The irradiate and anneal (IIWN) hardening technique was attempted on a number of part types and was reported to be an acceptable method for a few specific part types, while, in others, there were problems such as excessive degradation for the second irradiation. 1976- Process Investigations

of Total Dose Hard, 108 Op Amps[15]

Testing, analysis, and total dose hardening were performed on a 108 op amp in this paper by Palkuti of NRL and Sivo and Greegor of Boeing. The analysis was initiated with a total dose characterization of 108-type op amps that indicated that total dose sensitive devices could be radiation-hardened by modifying their standard processing. Extensive lot sampling over extended periods of time indicated significant lot-to-lot variation in the total dose sensitivity. The lot sampling indicated that devices from about 30% of the tested wafer lots exhibited Subsequent failure analysis by selective circuit significantly greater radiation sensitivity. irradiation with a SEM identified the critical op amp failure modes as primarily the result of super-beta-gain loss and leakage increase. A process-flow analysis with MOS capacitors on the selected baseline fabrication sequence was followed by a study of specific processing steps on the 108 hardness. Specific process steps were modified and the results presented. Using the defined process, it was possible to fabricate 108-type devices with minimal degradation at 1 Mrad(Si02). 1976- Irradiate-Anneal

Screening of Total Dose Effects[16]

The identification and elimination of maverick devices that exhibit much greater total dose sensitivity than the normal lot hardness distribution is again a topic in this paper by Stanley and Price of JPL. The effects of irradiate-anneal were measured for a number of linear bipolar devices, where normal and anomalous values obtained after the first irradiation and annealing were determined. It was found that, in almost all cases, reirradiation produced substantially greater shifts than the first irradiation. Unusual annealing behavior was also observed on some devices, such as the LM1 11. 1977- Analysis of Total Dose Response in Linear Integrated Circuits[17][18][

19]

A number of papers, through various analysis techniques, attempt to explain the response of linear integrated circuits to total dc~e irradiation. The first by Stanley and Gauthier of JPL [17] uses SEM irradiation at various levels of magnification to identi& sensitive areas and components that are responsible for the total dose degradation. Also discussed is the large variation in total dose response from device to device within the same date code. The second by Galloway and Roitman [18] of the National Bureau of Standards discusses a number of factors that must be considered in using the SEM, such as the depth-dose distribution of kilovolt electrons, dose rate uniformity, and the importance of biasing. The third paper by Johnston of Boeing [19] discusses neutron degradation in four common linear integrated circuits, but the circuit analysis discussed is very relevant to total dose degradation.

III-8

1977- Discussion of a Hard Off-the-Shelf SG1524 PWM and Total Dose Hardness Variation in LM 139s from Four Manufacturers[20] In this paper by Newell and Picciano of Ford Aerospace, the off-the-shelf total dose hardness of the SG1 524 pulse width modulator is analyzed and an attempt made to explain what is responsible for the significant total dose hardness. The wide variation in hardness of LM 139s from four different manufacturers is discussed, along with the test results and proposed explanation for the hardness differences. 1977- Evaluation of Integrated Injection Logic[21][22] Total dose results and analysis are reported on I% devices from five different manufacturers in this paper by Raymond of MRC and Pease of NWSC Crane. The use of bipolar processes for digital circuits, including memories and microprocessors, is rapidly increasing; and this paper and one by Donovan, Simons, and Burger of RTI discuss the future of LSI technologies. A subjective comparison of IS technologies in [21] rates FL slightly ahead of CMOS as the superior process in performance and hardness. Paper [22] also projects an optimistic future for 12L, with CMOS/SOS a close competitor. 1978- Hardness Assurance Considerations Structures[23]

for Total Dose Effects on Bipolar

This work assessed the theoretical understanding of long-term total dose effects in bipolar devices in support of the development of a hardness assurance technique in a paper by Hart, Smyth, van Lint, Snowden, and Leadon of MRC and IRT. The principal effort was directed at studying transistor gain degradation mechanisms by use of models relating semiconductor physical and electrical parameters to surface properties. Total dose effects on surface properties were used to identify critical physical parameters for use in hardness assurance procedures. Model implications and predictions were compared with existing data to evaluate their accuracy and usefulness as a tool. 1979-

Total Dose Homogeneity Study of the 108A Operational Amplifier[24]

Identification of maverick devices exhibiting a significantly lower total dose hardness was the subject of this paper by Johnston and Lancaster of JPL. This study investigated the homogeneity of the radiation response of components and complete 108A circuits at various levels of traceability, including diffusion lot-to-lot, wafer-to-wafer, and sub-wafer. Significant differences were found in the radiation hardness of the different diffusion lots. Even the variability of devices from a single wafer was larger than expected and was comparable to variability of devices from a single diffusion lot. Examination of the circuit data for large numbers of devices from single diffusion lots revealed that a small number of devices, approximate y 1?ZO, had a much different radiation response than the rest of the devices. In some cases, different failure mechanisms were responsible; but some devices simply had a different sensitivity to total dose. No electrical parameter could be identified that could be used to screen these devices.

III-9

,.

1981- SEM Analysis of Total Dose EffectsinAD571 Converter[25]

.

1% Analog-to-Digital

This paper by Gauthier of JPL investigated the total dose degradation mechanisms in the AD571 ADC, Sensitive areas of the circuit were identified by SEM irradiation, and then responsible components were identified. 1981- Total Dose Hardening of 108 Amplifier with Nitride Passivation[26] This paper by Condito, Lambert, and Schwartz of Precision Monolithic investigates the effect of different processing steps on the total dose hardness of the OP- 108A precision operational amplifier. Process lots with and without a silicon nitride surface passivation layer demonstrated that the nitride layer is the dominant step in assuring radiation-resistant circuits. Standard processed parts with the nitride layer demonstrated significantly lower degradation by a factor of 10 to 18 than the parts manufactured without it. 1981- Total Dose Hardness of Integrated Schottky Logic [27][28] Two papers by Johnson of Raytheon and Blice of NWSC Crane reported the total dose hardness of integrated Schottky logic transistors and circuits to be 10 Mrad(Si02). 1982- Total Dose Hardness of FL Logic Devices and SBP9989 Microprocessor[29]

[30]

Total dose hardness of six custom digital circuits designed and fabricated in an 1% process for the Global Position System is reported in this paper by Poblenz of Texas Instruments[29]. The circuits were found to be relatively hard to total doses of 1 Mrad(Si02). Similar hardness results were reported for the SBP9989 microprocessor in a paper by Woods of MIT[30]. 1983- Total Dose Effects in Recessed Oxide Digital Bipolar Microcircuits[3 1][32] Total dose failure levels of as low as 5 krad(Si02) are first reported in oxide-isolated In the first paper by Buschbom of Texas bipolar technologies in these two papers. Instruments[3 1], the failure of an advanced oxide isolated process is identified to be inversion of the base region along the oxide sidewall. In the second paper by Pease of MRC[32], low total dose failure levels of 10 to 100 krad(SiOz) are reported in oxide-isolated bipolar processes from five manufacturers. Failure modes are identified as (1) inversion of the p+ region at the bottom of the recessed oxide, causing channeling between adjacent buried layers; (2) inversion of the ptype base region along the recessed oxide sidewall, causing channeling between the emitter and collector of the npn transistor; and (3) an increase in surface recombination velocity along the sidewall due to fast surface states, causing an increase in p region sidewall currents. 1983- Comparison of Total Dose Effects in Linear ICS from Cobalt-60 and Electrons[33] Total ionizing dose response for fourteen linear IC types from eight manufacturers using Cobalt-60 and 2.2-MeV electrons sources is reported by Gauthier and Nichols of JPL. Electrons

III-10

are reported to almost always cause greater degradation Cobalt-60.

and lower device failure levels than

1984- Degradation Analysis of Lateral PNP Transistors[34] Degraded current gain due to x-ray irradiation in lateral pnp transistors is analyzed by Kato of Hitachi CentraI Research Laboratory. Base current is evaluated for two regions -- the depletion region of the emitter-base junction and the nondepleted charge-neutral region of the base surface. 1985- Total Dose Induced Hole Trapping and Interface State Generation in Bipolar Recessed Field 0xides[35] In an extension of the previous year’s reported work[32], the total-dose-induced trappedhole density, N.t, and interface state density, Nit, are investigated in bipolar recessed field oxides using test structures. New results include the effects of pn junction fringing fields on inversion voltage shift, 1987- Models for Total Dose Degradation of Linear Integrated Circuits[36] Mechanisms for total dose degradation of linear integrated circuits are discussed, including bulk effects, oxide charge buildup, and recombination at the Si-SiOz interface in this paper by Johnston and Plaag of Boeing. The dependence of damage on bias, dose, particle type, and energy is used in conjunction with two-dimensional modeling to identify the failure mechanism in a specific linear device type. The importance of surface recombination, along with the absence of bias dependence, is discussed in this paper. Substantial differences between Cobalt-60 and electrons are shown to be due to bulk darnage added to the surface darnage in the wide-base lateral and substrate pnp transistors. 1987- Total Dose Failure Levels for Circuits Using Bipolar Recessed Field Oxide Processes[37] [38] [39] The total dose failure levels for circuits fabricated in bipolar processes using recessed field oxide isolation are discussed in three papers. The papers by Schi~37] and Maurer[38] both discuss the hardness of these processes at low dose rates typical of space operation. Both papers report significantly higher failure threshold when the imadiation tests are conducted at low dose rates. This is due to the recessed field oxide failure mechanism and the annealing behavior. In the paper by Titus[39], the total dose failure threshold uniformity is mapped for several wafers. These include both standard processed wafers and ones with an enhanced field implant to improve total dose hardness. 1988- Bipolar Integrated Circuits Fabricated on Oxygen Implanted Silicon-on-Insulator Wafers[40] This paper by Platteter of NWSC Crane and Cheek of Texas Instruments describes the radiation improvements obtained by fabricating bipolar digital integrated circuits on oxygenMultiple low dose oxygen implants were used to implanted silicon-on-insulator substrates. 111-11

fabricate the wafers. Total dose hardness was reported to be significantly circuits compared to the bulk circuits.

higher for the SOI

1988- Comparison of Heavy Ion, Electrons, and Cobalt-60 Degradation Effects on an Advanced Digital Bipolar Process[41] Results are presented in this paper by Zoutendyk and Goben of JPL and Bemdt of Honeywell on measurements of the degradation effects of bromine heavy ions, electrons, and Cobalt-60 radiation on the current gain of bipolar transistors fabricated in an advanced process. Bromine was reported to produce the most degradation and Cobalt-60 the least. 1989- Total Dose Effects in Trench Isolation[42] Total dose effects in polysilicon-fflled trenches used for component isolation in an advanced commercial bipolar technology are reported on for the fust time in this paper by Enlow and Pease of MRC and Combs and Platteter of NWSC Crane. Test structures were designed and processed in an advanced trench-isolated bipolar process to study the total dose basic mechanisms. The generation and annealing behavior and effect on bias on Nil and NOt are reported. 1990- Radiation Hardening of BCDMOS Technology[43] The hardening of a power integrated circuit technology, containing bipolar, CMOS, and DMOS components, is reported in this paper by Desko, DarWish, Dolly, and Goodwin of AT&T and Titus of NWSC Crane. 1991- Low Dose Rate Effects in Advanced Bipolar Processes[44][45] The first report of increased gain degradation in bipolm devices irradiated at low dose rates is reported in this paper by Enlow and Pease of MRC, Combs of NWSC Crane, and Schrimpf and Nowlin of University of Arizona[44]. Implications of this finding on the 1019.4 test method are discussed in a paper by Fleetwood, Winokur, and Meisenheimer of Sandia[45]. In the paper by Enlow, total-dose-induced gain degradation in polysilicon and crystalline emitter The effects of bias, dose rate, and anneal temperatures are bipolar transistors is investigated. The bipolar test structures reported on are from four commercial technologies. discussed. Polysilicon emitter transistors show improved hardness over crystalline emitter transistors. Two of the three polysilicon technologies tested showed a continued decrease in gain during room temperature annealing, which may be due to post-imadiation buildup of interface traps. The gain degradation at a given total dose significantly increased as the dose rate was lowered, suggesting the existence of a dose rate phenomenon. The difference in dose for a given gain degradation at 1,1 versus 300 rad(SiOz)/s irradiations was near 50 for one of the polysilicon technologies. Both this paper and Fleetwood[45] suggest that Test Method 1019.4 hardness assurance test may not represent a worst case test for space environments.

III-12

1992- Trends in the Total Dose Response of Modem Bipolar Transistors[46] Factors that influence the total dose response of bipolar transistors, including emitter bias, transistor polarity, emitter technology, emitter geometry, base design, and irradiation dose rate, are reported in this paper by Nowlin and Schrimpf of University of Arizona, Erdow of MRC, and Combs of NSWC Crane. Advanced polysilicon and standard emitter transistors of both npn and pnp polarity processed in a trench-isolated, silicon-on-insulator technology were the subject of this study. Findings that were reported (for this technology) include: npn transistors degrade more than pnp transistors; devices with higher surface concentration degrade less; devices with smaller emitter perimeter-to-area ratios degrade less; collector bias does not affect gain degradation; reverse bias on the emitter is worst-case bias; increases in base current are larger at smaller base-emitter voltages; poly-ernitter devices are initially harder than standard emitter devices at low doses, but may become worse at large total doses; and degradation is worse at low dose rates. 1993- Charge Separation and Low Rate Effects h“Bipolar Transistors[47] [48] The role of net positive oxide-trapped charge and surface recombination velocity on excess base current in bipolar transistors is the subject of the paper by Kosier of University of Arizona[47]. Using test structures and transistors, two simple approaches for separating the effects of oxide charge and surface recombination velocity in bipolar transistors is described. Both are based on analysis of the log plot of the excess base current versus the emitter-base voltage. In the paper by Nowlin of the University of Arizona[48], the dose rate dependence of bipolar current-gain degradation is mapped over a wide range of dose rates for the fwst time. Annealing experiments following irradiation showed negligible change in base current at room temperature, but significant recovery at 100”C and above. Implications reported are that Test Method 1019.4 irradiate-anneal will not predict the worst case gain degradation. 1993- Converting a Bulk Radiation-Hardened Dielectrically Isolated Process[49]

BiCMOS Technology into a

The development and radiation test results of a dielectrically isolated radiation-hardened BiCMOS process are reported in a paper by DeLaus of Analog Devices, Emily and Mappes of NSWC Crane, and Pease of RLP Research. The process is fabricated on a bonded-wafer siliconon-insulator (S01) substrate and employs deep trenches for complete oxide isolation. Total dose hardness of the process was not affected, and the dose rate hardness exhibited substantial improvement. 1994- Low Rate Total Dose Response of Bipolar Transistors[50][5

1][52][53]

Investigations into identifying, understanding, and assessing the implications of low dose rate effects in bipolar transistors increased greatly in 1994 with three papers on this topic. A fourth paper reported on synergetic effects of radiation stress and hot carrier stress on the current In the first paper by Kosier of University of Arizona[SO], it is gain of bipolar transistors. reported that the excess base current in an irradiated bipolar transistor increases superlinearly with total dose at low total dose levels. In this regime, the excess base current depends on the charge-trapping properties of the oxide that covers the emitter-base junction. At higher total dose III-13

.

,,

-..

levels, the excess base current saturates at a value that is independent of how the charge accumulates. In the second paper by Fleetwood of Sandia[5 1], a physical model of the mechanisms responsible for enhanced low-rate gain degradation in bipolar devices is presented. The model suggests the presence of slowly transiting or metastably trapped holes in the bulk of the oxides. These act in tandem with more deeply trapped holes near the Si-Si02 interface to reduce the charge yield in the bulk of the oxide and increase the number of compensated holes in the oxide above the emitter-base junction. In the third paper by Nowlin[52], an apparent saturation of the dose rate dependence for gain degradation at dose rates below 10 rad(Si02)/s is reported. The results on elevated temperature irradiation are discussed and proposed as a possible hardness assurance test method. 1994- Low Rate Effects in Bipolar Circuits[54][55] [56][57] Four papers discuss the total dose response of bipolar linear and mixed-signal microcircuits, including total dose dose rate sensitivities. In the paper by Johnston[54], total dose degradation and dose rate effects in conventional transistors and linear integrated circuits are discussed. It was reported for some circuits and processes that the dose rate dependence may continue as low as .005 rad(Si02)/s. It was also presented that elevated temperature irradiation of a microcircuit at 60”C produced more degradation than at the same dose rate and normal temperature, but did not bound the low-rate degradation. In a paper by Beaucour[55], total dose response of LM 137 voltage regulators from four manufacturers is reported. Enhanced low dose rate degradation is reported in two of the manufacturers’ circuits. Selective SEM irradiation and mechanical probing were used to identi~ a lateral multi-collector pnp transistor as the sensitive circuit element. In a paper by McClure[56], total dose response of three bipolar linear microcircuits is reported at various dose rates, In all cases, lower dose rates produced greater degradation. In some cases, anneals following the high dose rate irradiation caused further degradation, but did not bound the low rate response. In a paper by Lee[57], the total dose response of three high-resolution BiCMOS analog-to-digital converters is reported at various dose rates. The dominant failure mode reported was due to the thick gate oxides. Rebound effects caused the response to be markedly different at high and low dose rates. 1995- Low Rate Effects in Bipolar Transistors[58] [59] [60][61] Low rate effect studies continue to be strong with three papers on the topic of low rate effects in bipolar transistors and a fourth on the effect of irradiate and anneal cycling. In the paper by Schmidt[58], the total-dose-induced gain degradation of lateral, substrate, and vertical pnp bipolar transistors is reported at various dose rates. Physical mechanisms are proposed to explain the greater degradation at low rates. In the paper by Schrimpf159], the gain degradation of a lateral pnp transistor is measured after irradiation at various elevated temperatures and several dose rates and then annealed at various temperatures. It is reported that the excess base “current for irradiation at 125°C and 167 rad(Si02)/s is nearly equal to that at 0.1 rad (Si02)/s. In the Belyakov[60] paper, a MOS test structure is used to identi~ the mechanism believed responsible for the increased low dose rate degradation in bipolar transistor gain, Shallow electron traps are reported to influence an increase in the positive charge yield. In the paper by Witczak[61], it is reported that gain degradation due to ionizing radiation in complimentary single-crystalline emitter bipolar transistors grew progressively worse after repeated cycles of

I-II-14

.

irradiation and anneal. A correlation is drawn between this degradation and mechanical stress in the oxide. 1995- Low Rate Effects in Bipolar Microcircuits[62] [63] The total dose response of five bipolar linear microcircuits from several manufacturers and irradiated at various dose rates and bias conditions is presented and analyzed in the paper by Johnston[62]. In one circuit, saturation damage is reported to be about 10 times greater at low dose rates than high dose rates, In another device, the dose rate response was reported to be very nonlinear with only minimal degradation occurring at 50 and .005 rad(Si)/s, but large degradation occurring at .002 rad(Si)/s. In other devices, the enhanced low rate degradation was reported to be very bias-dependent. In a paper by Carrii3re[63], total dose irradiation and anneal response is reported on several bipolar linear devices. Enhanced low rate degradation was reported on several devices, but post-irradiation anneal did not correlate with low rate sensitivity. 1995- Total Dose Response of BiCMOS and SiGe Processes[64][65 ][66] The total dose response of high-resolution analog-to-digital converters is reported in a paper by Lee[64]. Significant total dose hardness variation was reported with date code and dose rate. The cause of the low dose rate sensitivity was reported to be due to the CMOS circuit elements. The total dose response of a DC/DC Converter fabricated in a high-voltage bipolarCMOS process is reported in a paper by Titus[65]. Minimal degradation is reported to a total dose of 9 Mrad(Si02). In a third paper by Babcock, total dose response of high-perfommnce SiGe heterojunction bipolar transistors is reported. Minimal gain degradation was observed to 1 Mrad(Si) for transistors irradiated at 300”K and 77”K.

2.0 FUNDAMENTALS

OF BIPOLAR TRANSISTOR

OPERATION

This section will give a basic overview of bipolar transistor operation and commonly used For a more detailed description of the operation of bipolar terminology and definitions. transistors, there are many excellent sources of information, such as Physics of Semiconductor Devices by Sze. For comparison, MOS transistors are a majority carrier device with the current flowing through a channel formed between two junctions and controlled by an electric field from a gate electrode. By contrast, bipolar junction transistors are minority carrier devices with current flow through a base region between two semiconductor junctions and controlled by charge injection into the base region. Figure 2 shows the symbols and nomenclatures of the two polarities of bipolar junction transistors. In the following discussion, the more common npn transistor will be described; the results are applicable to the pnp transistor with an appropriate change of polarities.

rrI-15

,.

EMITTER

,

BASE COLLECTOR

~

-’

(a)

p-n-p

TRANSISTOR

(b)

n-p-n

TRANSISTOR

Figure2 Symbolsand Nomenclaturesof npn and pnp Transistors.

The normal operating conditions for an npn transistor are with the base emitter junction forward-biased and the collector base junction reverse-biased. Under these conditions, the transistor is said to be operating in the active region. For our transistor, this mearts that minority carrier electrons are injected into the p-type base region. The predominant current flow in the transistor is from collector to emitter and is controlled by the small base current due to the forward-biased base-emitter junction and which increases strongly as the forward voltage at the emitter junction increases, The gain (Q of a transistor is determined by the percentage of the electrons that escape recombination and transit the base region from collector to emitter divided by the base current. The base current is determined by a number of factors, but is primarily determined by the rate at which holes are lost from the base by injection across the emitter junction and the rate of hole recombination with electrons in the base, In each case, the lost holes must be resupplied through the base current 1~. For our purposes, the base current IB is divided into two components to analyze the effects of radiation -- a bulk component (_&ulk)and a surface component (I,Uti.u). For radiation effects concerns, changes in the bulk component of IB are primarily due to recombination centers in the base region, such as from neutron or electron displacement damage effects. The primary concern for total ionizing dose damage is the increase in the surface component of the base current. This will be discussed in more detail in section 4.2. B= ~/IB = ~(I~ul~+ ItiW=)

(1)

A Gummel plot is the primary means of showing the base and collector currents. In a Gummel plot, log 1, and log k are plotted versus V,,. The transistor gain ~fl,) is derived from the Gummel plots and is plotted as current gain versus V~ or L. Examples of these plots are shown in Figure 3.

III-16

1.0

IN 1 0-s

.

0.8

8

Iv 10-7

1 o~

lN 10-10

)

10-11

0.0

10-12

0.4

0.5

0.6

0.7

0.6

0.9

0.4

VEB(-v)

I

I

I

I

0.5

0.6

0.7

0.6

0.9

Vm (v)

Figure 3 (a) ExampleGummelPlots of IBand ~; (b) DerivedCurrentGainCurve.

3.0 BIPOLAR TRANSISTOR

STRUCTURES

Due to the long product lifetimes of some bipolar processes, there are currently many different bipolar processes being used to fabricate linear and mixed-signal microcircuits. The radiation response of the different processes and different transistors within each process may vary significantly. Factors that may influence the radiation response include transistor vertical geometry, layout, presence of electrical fields due to field plates and other vertical fields, fringing fields, surface doping concentration, surface oxide quality and thickness, and many other factors. This chapter will attempt to give a brief overview of the principal transistor devices currently used, fabrication differences that may influence the radiation response, and common circuit implementations. One rule that should be applied throughout this study is to always assume there is an exception to every rule. There are many variations to the devices and processes that are discussed in this chapter, so firsthand knowledge of the device of interest is important to understand the radiation response. 3.1 Vertical,

Lateral,

and Substrate

Transistors

The first major class of devices that we will discuss is the vertical, lateral, and substrate transistors used in the classical junction-isolated, medium-voltage, linear process. This process has evolved slowly since it was introduced in the late 1960s and is still commonly used to

III-17

.,

,,

,

fabricate the standard 40-volt linear product such as the LM- and OP-series of microcircuits. Figure 4, from [36], shows a cross section of the three common transistors implemented in this process.

EmitterBase Collector o

0

0

Emitter

Collector

0

0

w

p+

Base

1 p+

n-epi n+ p-substrate

p-substrate

Vertical npn

Lateral pnp

(a)

(b)

Emitter ?

Base ?

P2ss25! Substrate pnp (c)

Figure 4 Cross Sectionof TransistorStructuresUsed in MediumVoltageLinearICS

ShowingDominantCurrentFlow Paths.[36]

The vertical npn transistor shown in Figure 4(a) is typically the most common circuit element used in the medium-voltage linear circuits. The npn transistor is a high-gain vertical structure with minimal base surface area. The dominant current flow in this device is vertically, so surface oxides are expected to affect only the minor lateral component of the base current. The lateral pnp transistor shown in Figure 4(b) is a suboptimal device using the same diffusions that were optimized for the vertical npn. The lateral pnp transistor is formed with a buried layer that inhibits vertical current flow to the substrate (for this structure the substrate transistor is a parasitic transistor that reduces the gain). Typically. 95% to 97% of the current is in the lateral direction. Most lateral transistors use a collector ring or square that surrounds most of the emitter and confines the base area to the region between the two diffusions. Because the base surface in the active transistor region is predominantly low surface concentration n-epi, a field plate is commonly used to control surface effect. The field plate was first developed due to the low-quality surface oxides in the early days of IC fabrication and the tendency for ionic contamination to invert the base region, The field plate is typically an extension of the emitter metallization over the base region, but separated from it by the surface oxide. The presence or absence of a field plate and the surface layout and bias can have a strong effect on the total dose response of the lateral pnp. The substrate pnp transistor shown in Figure 4(c) is designed so that the dominant current flow occurs vertically. No buried layer is used. However, current can also flow laterally to the isolation diffusion, which is also the collector of this transistor. Depending on the base width of the vertical pnp component versus the lateral pnp component, the ratio of

III-18

vertical-to-lateral current flow can vary. Typically, the vertical component of the current flow is about 80% and the lateral about 20’-ZO.The substrate transistor also typically has a larger base surface area than the lateral transistor and so is sensitive to surface damage. Field plates are also used on some substrate devices to control surface effects and, thus, can also be a significant influence on the total dose response. A more modern bipolar process used to fabricate linear and mixed-signal ICS capable of operating at 10 volts or less and at circuit frequencies of up to 1 GHz is shown in Figure 5. This class of processes typically contains both high-performance vertical npn and pnp transistors. The Lateral cross section in Figure 5 shows devices fabricated on buried oxide SOI substrates. isolation is achieved with etched vertical trenches that have a regrown liner oxide and which are then refilled with polysilicon. Variations of this process, and especially earlier processes, may be processed on bulk wafers and employ recessed field oxide isolation. Although not common, a lateral pnp transistor may be implemented in these processes when a higher voltage device is required than the vertical npn or pnp transistor can support. The vertical npn and pnp transistors shown in Figure 5 typically have cutoff frequencies (f-r) from 2 to 10 GHz. The transistors have much shallower junctions and narrower bases than the previously discussed process due to the use of ion implantation, rather than diffusions, to form the junctions. The base is, typically, formed as a two-step process with a shallower and lighter implanted intrinsic base to form the active base region and a higher-doped extrinsic base to decrease base resistance and improve efficiency. This extrinsic base also gives a higher-doped surface concentration to reduce surface effects. The surface oxide at the critical emitter-base junction can vary greatly, depending on the process, resulting in much different radiation response. This will be discussed in more detail later.

PNP

NPN

1

I

Figure 5 DeviceCross Sectionof a Trench/SOIComplementaryBipolarProcess.[67]

111-19

,.

,

A major advance in bipolar technology has been the development of polysilicon emitters. Figure 6[44] shows the difference between a typical crystalline emitter npn transistor Fig. 6(a) and a polysilicon emitter npn transistor Fig. 6(b). The speed of the polysilicon emitter transistors, as measured by fT, is increased to 15 to 25 GHz for a 5-volt device. For 3.3-volt devices, the fTcan be increased to 30 to 50 GHz by scaling. N+ Polysilicon ilicon

Collector

N+

N+

Collector

(a)

(b)

(a) TypicalCross Sectionof a CrystallineEmitternpn Transistorand (b) TypicalCross Sectionof a PolysiliconEmitternpnTransistor.[44]

Figure 6

3.2 Bipolar Transistor Fabrication The principal fabrication factors that contribute to the total dose response of bipolar transistors are the quality and thickness of the surface oxide, especially at the emitter base junction and over the base area; the base and emitter doping concentration at the Si-Si02 interface; and, for displacement damage effects, the base width and lifetime. For the medium-voltage linear process shown in Figure 4, successive depositions (or, in some cases, implants) are performed followed by high-temperature diffusions. Successive layers of oxides that have been exposed to the different dopants are grown during these hightemperature steps and are, thus, heavily damaged. For example, the junction isolation diffusion that drives the p-isolation to the substrate is performed at 1200”C for five hours. Whether the oxide grown during this lengthy process step is removed for subsequent processing has been demonstrated to have a significant effect on total dose hardness[ 15]. Other fabrication steps that have been demonstrated to affect the total dose hardness are densification of the CVD after emitter formation, the use of a forming gas during emitter anneal, and the use of phosphorusdoped glassivation. It has been demonstrated that replacement of the surface oxide with a silicon nitride surface passivation layer can significantly improve total dose hardness [26]. There is no standard bipolar process, and variations between manufacturers may cause significantly different total dose responses for electrically similar transistors.

111-20

Crystalline emitter transistors are fabricated by direct ion implantation of the base and emitter regions. Direct implantation limits how shallow the junctions can be formed and also the base width that can be achieved. Also, metal contacts cannot be used on junctions that are less than 1 pm in depth. Typically, the surface concentrations of ion-implanted bipolar transistors are higher than diffused junctions. The oxide over the emitter-base junction region is also thinner due to the shorter process times associated with ion-implanted junctions compared to diffused junctions. One factor that varies between manufacturers is the amount of damage that is done to the surface oxide during the implant steps. In some processes, the surface oxide is removed in the emitter base region and replaced with a composite grown and deposited spacer oxide. This can create a large difference in radiation response. Polysilicon emitter transistors have several performance advantages over the crystalline Polysilicon can contact shallower emitters than with metal contacts. As emitter transistors. vertical device scaling produces shallower emitters, base current increases due to carrier Polysilicon emitters eliminate this high recombination at the metal.lsilicon interface[67]. recombination interface and also can be used as a diffusion source to form ultra-shallow emitters. The most advanced bipolar processes employ a self-aligned, double-polysilicon transistor. The double-polysilicon transistor uses a second layer of polysilicon to contact the base region. Advantages include reduced base area and, therefore, reduced collector-base capacitance. This also allows closer base-emitter contact and reduced base resistance. The radiation tolerance of polysilicon transistors has been demonstrated to be significantly better than crystalline emitter transistors[46] [50]. 3.3 Circuit Implementation Circuit design can have a significant effect on the total dose response of linear and mixedsignal circuits. Especially important is how the total dose sensitive lateral and substrate transistors are used in the circuit design. Some circuits, such as the LM1 11, LM139, and LM 124, use a substrate or lateral pnp directly in the input stage. The LM111 input stage is shown in Figure 7[36] along with the increase in input bias current. In this type of design, the input bias current k inversely proportional to the substrate transistor gain so that, as the transistor gain decreases, the input bias current increases.

111-21

~ +

Cobalt-60 2 MeV Electon

150

150

LM1l 1 Input Stage

Vm

100 A

50

Input

:

0

o 0

50

100

150

200

250

Total Dose (krad(Si)) Figure 7 LM111Input Bias Stageand InputBias Currentvs. Total Dose.[36]

Lateral and substrate pnp transistors are often used in current sources that are internal to the input or output stage and, thus, are difficult to monitor for degradation. These current sources are designed to tolerate a wide range of gain. However, even in these applications, once the gain drops below a threshold level, the circuit will fail suddenly and catastrophically. This has been reported for the LM 108 operational amplifier[36] and the LM 137 voltage regulator[55]. In the case of the LM 137, a multi-collector lateral pnp, used as a current source in the startup stage, dropped below a critical gain value of 8, causing sudden failure. In many linear circuits, careful matching of components is required for proper circuit operation. In these circuits, identical transistors are laid out symmetrically to minimize any It has been reported[ 17] that small unbalancing due to temperature and loading effects. differential changes in gain degradation for these balanced pairs can cause substantial degradation of circuit performance. Different gain degradation in identical matched devices may be due to the influence of internal bias differentials during irradiation or to nonhomogeneous transistor radiation response. It has been reported that the assumption of homogeneous wafer response has limited validity [24]. In many cases, the uniformity of the total dose response of devices from a single wafer was substantially larger than expected and no better than that of several wafers from the same diffusion lot.

4.0 TRANSISTOR

TOTAL DOSE EFFECTS

Transistor total dose response is dependent on the type of process used for fabrication. In this section, the transistor response to total dose irradiation for each of the major processes The first section will deal with surface inversion discussed previously will be presented.

III-22

mechanisms, transistors.

and the second section will deal with gain degradation

in the different types of

4.1 Substrate, Sidewall, and Surface Inversion Inversion can occur in several locations in an oxide-isolated process. Typically, it occurs where a lightly doped, p-type silicon layer is adjacent to a thick field oxide. Figure 8 [35] shows a bipolar transistor with recessed field oxide isolation and several potential inversion regions.

=zz

X= N+ BURIED LAYER

N+ BURIED LAYER

~~ P SUBSTRATE

Figure 8 Typical Cross Section of Recessed Field Oxide Bipolar Transistor with Walled Emitters.[35]

Location 1 of Figure 8 is the inversion of the p+ region at the bottom of the recessed oxide, which causes channeling between adjacent buried layers. Inversion of p-type silicon at an Si02 interface is due to positive-type charge trapped in the SiOz next to the interface that depletes the p-type silicon surface to a maximum value. This was reported in five digital bipolar processes in [35] with failure thresholds as low as 5 krad(SiOz). Location 2 of Figure 8 is the inversion of the p-type base region along the recessed oxide sidewall, causing channeling between the collector and emitter of the npn transistor. Figure 9 shows a detailed view of the inversion area. Similar positive charge trapping in the recessed field oxide, as with the substrate inversion, causes the sidewall inversion. This failure mode was reported in two digital bipolar processes in [35] and was recently reported in [75] for a BiCMOS process where inversion of the base region of a walled npn transistor occurred. The tran~istor layout was redesigned to nest the emitter so that the emitter implant falls entirely within the active area. Devices with the nested emitter were fabricated and total dose testing performed. No collector-to-emitter leakage was observed to 1 Mrad(SiOz) for the redesigned, walled, bipolar transistor.

III-23

Inversion

n+

Emitter

p-Base

n-Epi

n+DUF

)

p-Substrate

Figure 9 Inversion Mechanism in Walled EmitterTransistor.[31]

Inversion can also occur in more advanced isolation methods and has been reported in trench isolation structures [42]. Figure 10 [42], shows a deep trench that has been formed by reactive ion-etching a deep groove through the n-epi and n+ buried layers and into the p-substrate. A p+ channel stop is implanted into the bottom of the trench, and then a thin liner oxide is grown. Under ionizing radiation, positive charge is The trench is finally refilled with poly-silicon. generated and trapped in the liner oxide, which -- depending on oxide thickness, trapping characteristics, and the doping concentration of the p-substrate and p+ channel implant -- can invert the p areas and cause a channel between the two n+ buried layers. In all cases of inversion, the formation of an inversion layer is strongly bias-dependent and is aided by a positive electric field.

Surface Field Oxide

Metallization

";j;;jjjj;~j.!!!; .:.".`.'}.`.'.".f {{<{..'.'.'.' \."'.".";." .jj;jjjj;;;i~.`i~, ~ N+ Buried

Thermal

N+ Buried

Layer .

Oxide ~

“ :~

Layer

Polysilicon

Leakage P- Substrate

:1

--+w--

c-.! L

Figure 10

Cross

Section

Current

P+ Implant ‘

of Parasitic

Trench

MOSFET.

[42]

Surface inversion can occur in some structures, depending on surface oxide thickness, oxide charge-trapping characteristics, surface doping concentration, dose rate, and electric fields. Inversion has been reported in the p-isolation[ 17] for some devices. In general, the surface

III-24

oxides are much thimer than recesssed field oxides; and surface concentrations of most active elements are high enough to prevent inversion. However, many linear circuits operate at very low currents, particularly in input structures and bias circuits that establish the operating conditions for the input stage. These circuits are inherently sensitive to small increases in leakage currents, such that even partial channeling can have a major impact on circuit performance and parametric degradation. 4.2 Transistor Gain Degradation A decrease in transistor gain can be due to a decrease in collector current or an increase in base current at a given base-emitter voltage. As discussed in Section 3.2, there are two basic components to the base current, a bulk and surface component; and gain can be expressed as the equation[23]: 13= L/I, = Ic/(Iti, + I~ru).

(2)

This course will primarily discuss the surface component of the base current; however, it has been shown that bulk darnage can have a significant effect on gain degradation on wide-base structures such as the lateral pnp and substrate pnp transistors [23][33][36] and even on advanced narrow-base npn transistors[41 ] and, thus, should not be ignored. Gain degradation due to bulk darnage is especially important when concerned with potential degradation from electrons and heavy ions. Since the bulk darnage adds to the surface darnage effects, much lower failure levels may occur in actual space environments than in conventional Cobalt-60 laborato~ testing. Since low-energy x-rays do not cause bulk darnage, they are a possible tool to help separate the bulk component from the surface component. Care must be taken in its use, however, due to the low fields present in most bipolar structures and the potential for lower charge yields from the x-rays. The surface component of base cument can increase from ionizing radiation because of several mechanisms, but is primarily due to an increase in interface states at the surface of the base and positive charge buildup near the emitter-base junction, which affect the surface potential and the extent of the emitter-base depletion region. Both result in an increase in the base recombination current and resultant decrease in gain. Many factors can affect the buildup of interface states and positive trapped charge and their effect on recombination current. Each factor will be considered separately in this discussion, but the total effect on a “real device” may be a complex combination of multiple factors. Care must be taken in comparing differences between similar devices to be sure that all factors are understood and considered in the total response comparison. The ionizing radiation response of an npn transistor is illustrated in Figure 11 in terms of the normalized ~ degradation, ~/flo, and log ~ and log IB versus VBE where POis the initial gain for a dose rate of 100 rad(Si)/s and dose levels up to 500 krads. The general features of this degradation are: (1) the gain degrades more rapidly at values of VBE below peak gain, (2) the gain peak moves to higher values of VBEat higher total doses, and (3) the gain degradation is a result of increases in IB with ~ remaining essentially unchanged. In some process technologies, ~ has been observed to increase with dose, especially under reverse emitter-base bias [52]; however, the dominant mechanism is excess base current, MB.

III-25

,.

,

-1

t

L

E

10’

“\.

-J

H“ 10-7 d

/.

:ficg;( } ‘“: 10-12

0.4

0.5

0.6

0.7

0.8

0.9

0.4

0.5

0.6

VBE (v)

0.7

0.8

0.9

v~~(v)

Figure 11 (a)Normalized Current Gain for Typical Vertical npn and (b) Gummel Characteristics Showing the Increase in Base Current with Total Dose.[46]

Ionizing radiation response mechanisms of an npn transistor have been treated in depth by Kosier, et al. [47] [50]. An analytical expression has been developed for the excess base current, AIB, that is caused by the oxide-trapped charge and interface states. The structure modeled is shown in Figure 12.

I

I

II

Figure 12 Representative Cross Section of the Devices Studied in This Work (Technology B).[70]

III-26

Intrinsic

Base

b

Lm

z

I Figure 13

L In

CoordinateConventionand GeometricDefinitions.[70]

The qualitative features of the analytic expression have been verified with a 2D device physics code using sheet charge in the oxide to represent the trapped oxide charge and a degraded surface recombination velocity to represent interface traps. Layout of the structure modeled is shown in Figure 13. The expression for the surface component of excess base current [70] is

(3)

where Nox is the trapped oxide charge, NS the interface doping density in the base, ~ Debye length, and ni is the intrinsic camier concentration.

is the

The mechanism for the increase in MB is an integration of the change in surface potential (which is caused by the oxide-trapped charge and affects the recombination rate at the base surface) and the radiation-induced increase in the surface recombination velocity, v~ti. The surface recombination rate is a strong function of surface potential, reaching a maximum when the surface is depleted and the hole and carrier concentrations are equal. This strong dependence is seen in the exponential factor exp(Nox2). This term is multiplied by the degraded surface recombination velocity, v~~, giving a superlinear dependence of MB on total dose. Once the surface becomes filly depleted and Nox is further increased, the surface becomes inverted,

III-27

driving the peak of the recombination below the surface. At this point, a maximum is reached for AIBj and the gain degradation saturates. Although an inversion layer forms ‘over the lightly doped portion of the base, a channel usually does not form from emitter to collector because the extrinsic base p+ base contact region blocks the channel. However, as discussed previously, in recessed field oxide walled emitter structures, a collector-to-emitter channel may be formed. The geometry dependence of& is observed in the ratio of the perimeter-to-area for the emitter-base junction at the surface. The other geometry term is the total surface area of the lighter doped intrinsic base surface. The emitter-base bias influences the initial rate increase in AIB because the emitter-base junction fringing electric field influences the buildup and spatial distribution of Nox and V~~. The worst-case bias is a reverse bias of the emitter-base, whereas the best case is forward bias. The oxide thickness and hole trapping cross sections also influence Nox. The depletion of the base region is affected by Nox and the surface doping density. The higher base surface doping will result in a lower increase in MB. As will be shown later, the low dose rate sensitivity is a result of a dose-rate-dependent value for both trapped charge and interface traps. Although the mechanism for MB in npn transistors is relatively well understood, the theory for lateral and substrate pnp transistors is not. An advanced state-of-the-art lateral pnp built with a polysilicon emitter and collector with LOCOS isolation has recently been modeled. The mechanisms for ~B appear to be Results will be presented at this year’s conference. dominated by an increase in v,ti in a region very close to the emitter-base junction surface perimeter. The effect of oxide-trapped charge is to accumulate the n-type base surface, which emitter occurs because the actually offsets the effect of vsti. Very little depletion of the p-ty r surface doping density of the polysilicon emitter is ve~ high (> 101 cm-3). Thus, in this structure, the effects of Nox and Vsutioppose rather than enhance each other; and the dependence of ~B with dose is sublinear rather than superlinear. However, the conventional diffused/impla.nted emitter of the lateral pnp shown in Figure 4b has a surface doping density comparable to the base Thus, in the conventional lateral pnp transistor, MB is region of a vertical npn transistor. expected to consist of a term, due to depletion of the emitter, that would be comparable to the MB of the npn. Since the principal component of emitter current is lateral rather than vertical, MB is expected to be much higher than in the npn transistor, resulting in much greater gain degradation. Efforts are underway to model this structure in PISCES. The dependence of/& and P on dose at high dose rates has been studied as a function of the process, device design, and test parameters in [46]. Each one will be addressed individually here, but remember that there may be complex interactions in a real device. Transistor polarity is the first factor considered. From the previous discussion, the positive oxide charge and interface states interact over the p-type base in the npn transistor to cause significant base current increase. In the pnp case, the positive charge and interface traps offset and result in less base current decrease. In general, with all other factors being equal, a pnp transistor will degrade less than an npn transistor. Figure 14 [46] shows the relative difference between similar vertical npn and pnp transistors.

III-28

1.0

-u----..

-::

-0.

-.

0.0 i

10

-..

“.

-,

L

-----u. -0.

‘.

. .

.

-u .

- v.

1

●

1 0.6

$ 0.4 0.1

02

0.0

0.01

10

Im

Total Dose (krad(Si)) Figure 14 Total Dose Response of Similar

Vertical

npn and pnp Transistors.[46]

A second factor is oxide thickness, especially over the emitter-base junction area. In general, the thicker the oxide is over the base and base-emitter junction areas, the greater the total trapped charge and the larger the increase in base current. This has been reported in [62]. A third factor is the charge-trapping characteristics of the oxide over the emitter-base junction area. It has been shown by several[ 15][51 ] that oxide damaged during the fabrication process and left over the emitter-base area can have significantly higher charge-trapping efficiency than an oxide grown after most of the processing steps. This was demonstrated in [15] when the oxide that was present during the isolation diffusion process ( 1200”C for five hours) was stripped and regrown. It has also been demonstrated in [51] screen oxides that were implanted through and characterized. A fourth factor is the surface doping concentration, especially for the base and emitter areas. The more heavily doped the base or emitter surface is, the less depletion effect that the trapped charge will have on the surface. This is shown in Figure 15(a) [46] where a highly doped p+ ring was added to the base. More improvement would be obtained by increasing the doping of the entire base surface, but this would have a negative impact on the breakdown voltage. Figure 15(b) [46] shows the improvement with a higher-doped emitter. Since these are two different emitter technologies, other factors may also be influencing the improvement in hardness, such as improved emitter efficiency.

III-29

10

1.0

0.8 1 0.6

0.6

$

9’0.4

0.4

0.1

0.1

0.2

0.2 a

0.0

,

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r

I , ,I

10

,

8

,

0.O1

AIBflBoPoly-Emitler

0.0

100

0.01 10

100

Total Dose (krad(Si))

Total Dose (krad(Si))

Figure 15 (a)Effect of Increased Base Doping Ring on Improved Hardness (b) Comparison of Poly-Emitter with Silicon Emitter.[46]

A fifth factor Since the majority of the perimeter-to-area Figure 16 [46] shows

that influences transistor hardness is the emitter perimeter-to-area ratio. the increased base current occurs at the base-emitter perimeter, minimizing ratio will result in less base current increase and less gain degradation. the improvement from reducing the perimeter-to-area ratio.

1.0

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0.8

e: ::....

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---

10

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O.--”.q ..

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4 7

0.1

0.2 (

0.01

0.0 ~ 10

100

Total Dose (krad(Si)) Figure 16 The Emitter Perimeter-to-Area Effect on the Total Dose Response of an npn Transistor.[46]

111-30

Transistor geomehy can be a significant factor in transistor total dose response. Especially important is the ratio of lateral current flow to surface current flow in the base area. In general, vertical transistors will be harder than surface devices. Figure 17 shows the total dose response of a vertical, substrate, and lateral pnp. In the vertical device, almost all of the current flow is in the vertical direction; and only a few percent is at the surface. For the substrate device, we previously showed that about 80?10of the current flow was vertical and 209i0 lateral. For the lateral device, the majority of the current flow is in the lateral direction. In Figure 17, we see that the vertical pnp transistor has the least degradation; the substrate pnp transistor degradation is second; and the lateral pnp transistor has the most degradation.

1.0

‘“O~ c

~

0.5

EzEl 0.0

~

LPNP(167

rsd(SIOJ/s)

~

SPNP(167

rsd(SIOJ/s)

~

VPNP(156

rsd(SIOJ/s)

I 1“0

1

I

101

l&

Total Dose

f

0.0

1P

(krad(SiOJ)

Figure 17 Normalized Current Gain (13)vs. Total Dose for Vertical, Substrate, and Lateral pnp.

Electric field in the oxide can be a significant factor in the total dose response. Determining the electric field can be quite complex, since there are nonuniform fringing fields induced by the junctions and vertical fields formed by any metallization or polysilicon layers that may lay on top of the device or area of interest. It has been shown previously that the field plates that are on most lateral and substrate devices can substantially improve the hardness. Many early experiments with gated transistor structures showed a strong dependence on total trapped charge and applied electric field. Figure 18 [46] shows the effect of different biases on a vertical npn For this transistor and layout, reverse bias during irradiation caused larger transistor. One must carefully analyze the device being tested to make sure all “parasitic” degradation. vertical fields that may be induced by overlying conductors are accounted for, because they may dominate a fringing field. Another factor in the total dose hardness is the injection level at which the gain degradation is measured. In almost all cases, gain degradation is worst at lower injection levels.

III-3 1

This occurs because there are increased surface effects at low injection levels. This can be observed in the L degradation at low V,E values for the Gummel characteristics in Figure 19, where the effects of characterizing a device at different injection levels is shown. One last factor that is important, but will be discussed in Section 6, is the dose rate and temperature at which irradiation is performed. It will be shown later, depending on many of the factors discussed here, that there may be increased degradation at low dose rates. In summary, factors which affect bipolar transistor hardness include: ● Transistor polarity (npn or pnp) ● Oxide thickness over base-emitter region ● Oxide trap efficiency ● Vertical electric field ● Fringing electric field ● Base surface concentration ● Emitter surface concentration ● Emitter perimeter-to-area ratio ● Transistor geometry (ratio of lateral to vertical current flow) ● Injection level ● Dose rate ● Temperature

1.0 m ::

=Z

k 10

@%:; ;8 ---

: : .

0.8

0-

P/P. - VBE= 0.5V

- . ❑ . plpo -

- -

0.6

~ . -a-

:

.

0.

‘%::

VBE= -2.OV

. ..Q . .

1

AIBnEKJ - VBE= 0.5V Al&

- VBE = -2.OV

Al&O-v~~=O.OV

0.4

0.1

0.2

[

0.0 ~ 10

0-01 100

Total Dose (krad(Si)) Figure 18 The Effects of Bias During Irradiation.[46]

III-32

1.0

Q. . . . -.

L

0..

-

10

-.

0.8

. .

1 0.6 $

s .

0.4

.

0.1 .0.

0.2

~/~0- Measurement

. ❑ . ~/~0- Measurement +

AI#Bo

Bias.

0.6V

Bias=

0.7V

- Measurement

Bias = 0.6V

0.0

0.01 10

100

Total Dose (krad(Si)) Figure 19 The Effect of Characterizing a Device at Different Injection Levels.[46]

5.0 INTEGRATED

CIRCUIT RESPONSE

This section will discuss the response of bipolar microcircuits to ionizing radiation. The first section will discuss the response of digital microcircuits that are primarily fabricated in oxide-isolated processes. The second section will discuss the more complex response of linear ICS and introduce low rate effects. 5.1 Total Dose Response of Digital Microcircuits Many of the early bipolar digital processes that have been reported on have been discontinued. These include integrated injection logic (12L) and integrated Schottky logic (ISL). Other processes, such as recessed field oxide bipolar processes, are still in limited production and are used for some mixed-signal applications. The failure modes for these processes are primarily associated with inversion associated with the recessed field oxide isolation, as discussed in Section 4.1. The radiation sensitivity of the circuits is found to be very sensitive to bias conditions during irradiation. In several cases, the failure mechanism is identified as substrate inversion, which causes a parasitic leakage path to form between the input transistor and a guard ring. When the input is biased high during irradiation, parametric failure occurs in 100% of the samples by 100 krad(Si). When the inputs are grounded during irradiation and normal power bias applied, all parameters and functionality are nearly constant and within specification up to 10 Mrad(Si). Failure analysis of these devices identifies a metallization run over the field oxide between the input structure and the guard ring. This metallization run acts as a gate for the

III-33

,,

,.

parasitic structure shown in Figure 8. The substrate will not invert unless a sufficient vertical field induced by this metallization run is present. Unless a careful analysis is performed to identi~ potential leakage paths, then testing should be performed with multiple bias conditions. Another common failure mode in digital bipolar circuits is sudden failure due to inversion of walled-emitter transistors. Testing of circuits that contain these transistors shows a gradual increase in supply current and then sudden circuit failure. With this type failure, in-situ bias was less critical. Circuits require bias to fail, but no pattern sensitivity was observed for specific structures. This is most likely due to the short channel that is required to invert the sidewall and the presence of adequate fringing field in most cases. Wafer mapping of the recessed field oxide failures[39] shows uniformity across the wafer, and from wafer to wafer within the same lot, to be good. Failure distributions were found to be within two sigma from wafer to wafer, indicating that a statistical sampling program can be used to predict the radiation response of the devices from lot sampling. Failure of digital bipolar devices fabricated in soft recessed field oxide processes is ve~ similar to CMOS fabricated in similar processes. The failure modes are predominantly inversion under or along the recessed oxide isolation and appear to have the same time response as CMOS. Test method 1019.4 should provide a conservative total dose test to predict the performance of these devices in space. 5.2 Linear Integrated Circuit Total Dose Response One of the earlier papers on total dose response of bipolar linear integrated circuits was published in 1975[ 14] and concerns the characterization and screening of devices for the Mariner Jupiter/Saturn spacecraft launched in 1977. Many of the linear integrated circuits of interest then are still being evaluated for current designs. These include the LM101A, LM108, LM124, HA2600, HA2620, and HA2700. Much of the concern at that time was identifying and screening out “maverick” devices that exhibited significantly greater total dose sensitivity, even though they were from the same lot and were processed no differently. No pre-irradiation electrical parameters could be identified that could screen out these devices. Considerable effort at that time was spent on developing an Irradiate-Anneal (IRAN) test method to irradiate devices to a low-to-moderate level and then perform a high-temperature anneal to anneal the radiation damage out. It was then projected that the devices would behave the same the second time and could be used as mission parts. Over the years, as data were collected on this test method, it was found that some devices did not respond the same on reirradiation or that the initial irradiation had to be so high that the damage could not be annealed out. This test method seemed to die out in the late 1970s. There was considerable information published on maverick devices [5] [ 14][ 15] [ 16][ 17][24] until 1980, but the cause of the unusual sensitivity or an effective screen was not identified in open publications. The primary test method for bipolar linear devices is to perform a step stress irradiation and characterize all ac and dc parameters at each level. Parameters that typically degraded or failed were input bias and offset currents and output offset voltage. A considerable amount of spot irradiation was performed in the late 1970s to identify the sensitive components that were causing the normal degradation 17][25]. As expected, the lateral and substrate pnp transistors III-34

were identified as being the sensitive elements in most designs. An excellent study by Johnston published in 1979[24] evaluated breakout transistors and LM108A operational amplifiers to investigate subwafer, wafer-to-wafer, and lot-to-lot variability. Again, the lateral pnp and substrate pnp were identified as being the sensitive elements. Maverick devices were still a problem with 1% identified as having a significant and sometimes different degradation than the normal lot distribution. No electrical parameter was identified that could be used to screen these devices. Some lots showed a very tight distribution in parameter degradation, while others showed a very broad distribution. Figure 20[24] shows this type distribution for two of the parameters on three lots.

35

35

~

mLots

A&B

I

o

L

o 0

10

20

30

40

50

60

01234567891011121314

AIB (lA)

AVO~(mV)

Figure 20 Distribution of Input bias Current and Output Offset Voltage Response to Total Dose for Three Lots of LM 108A.

Significant differences in response to electron irradiation compared to Cobalt-60 irradiation were reported in [33] [36] [41]. Previously, Figure 7 showed 2-MeV electrons producing three times the change and no signs of saturation at 250 kRad(Si) in input bias current for the LM111 comparator. Cobalt-60 saturated at 100 kRad(Si). This was identified as bulk damage in the wide-base substrate and lateral pnp. However, [41] reports an enhanced electron effect for an advanced bipolar technology with a fairly narrow base. If electrons are the predominant environment of concern, then irradiation in an electron source maybe advisable. 5.3 Low-Rate

Effects Introduction

It was first reported in 1991 by Enlow[44] that an advanced bipolar technology exhibited increased degradation when irradiated at lower dose rates. These initial data reported that the effect was observed for npn transistors in two processes from one manufacturer. Figure 21 shows the data from this first paper on the low-rate effect. Since the publication of this first paper, more than fifteen papers have been published on low-rate effects in bipolar transistors and microcircuits, showing bipolar processes and circuits from multiple manufacturers exhibit the Figure 22 is a well-published summary plot of the low-rate effect by low-rate effect. Johnston[54]. Figure 22 shows data on microcircuits from two manufacturers. For one circuit (LM108), no dose rate effect is observed. For another circuit (LM 101), the low-rate effect is

III-35

.,

observed to saturate at a factor of approximately 2x at dose rates below 1 rad(Si)/s. For other circuits (LM111 and LM324), no saturation in the effect is observed down to dose rates of .01 rad(Si)/s with factors of 5x and greater in degradation compared to irradiation at 50 rad(Si)/s. The remainder of the course will be spent on the recent research performed on low-rate effects in transistors and circuits and the progress toward identifying the basic mechanisms responsible and acceptable hardness assurance test methods. ,

().1 i

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F

t

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❑

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,

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,

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1 - 1.1 2 -1.1 1 -300 2-300

Process

Procese Process Process

I , (36

,05

Total

Dose

radls radh radls radk

I

[

t

,0.4

107

(rad(SiOZ))

Figure 21 Change in A1/f3for npn in Two Processes vs. Total Dose at Two Dose Rates.[44]

* +

● A ■

LM108(npn) LM1o I (npn) LM1ll (pnp) LM324 (pnp)

-5

+ –4

-3

-2

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Discrete Transistors

0.001

0.01

0.1 Dose

Rate

1

10

100

(rad(Si)/see)

Figure 22 Effect of Dose Rate on Total Dose Damage Normalized to 50 Rad(Si)/s.

III-36

6.0 BIPOLAR LOW-RATE EFFECTS Enhanced total dose darnage at low dose rates has been studied extensively the last four years in bipolar processes, transistors, and microcircuits from multiple manufacturers. Test structures, transistors, or microcircuits are defined to exhibit enhanced low dose rate degradation when a measured parameter exhibits increased degradation at lower irradiation dose rates compared to the degradation at the same total dose at higher dose rates. The low-rate effect has been found to be nonexistent to minimal in some bipolar processes and severe in others. Even for processes that are known to exhibit the low-rate effect, only certain circuits maybe affected; and only some parameters may exhibit the enhanced degradation. It has also been observed to be bias-sensitive in some circuits, exhibit lot-to-lot variations, and -- in some devices -- to be extremely nonlinear. If one statement can be made to summarize the low rate effect, it is that it appears to be consistently inconsistent. In this section of the course, we will attempt to bring some consistency to our understanding of the dose rate effect. 6.1 Basic Mechanisms The enhanced low dose rate effect is a “true” dose rate effect rather than a timedependent effect as seen in MOS oxides. Thus, a post-irradiation anneal following a high dose rate irradiation will not produce the same results as observed at the end of a low dose rate irradiation. The “true” dose rate effect has been studied using MOS capacitors fabricated using a bipolar base oxide. A complete description of the study maybe found in the literature [51]. The major results of this investigation are: (1) the enhanced low dose rate effect occurs for a near zero electric field in the oxide during irradiation; and (2) the net trapped-hole density at low rate is larger, even though large numbers of holes and electrons are trapped at high and low dose rate. In addition to the “true” dose rate effects that occur as a result of different transport, recombination, and trapping properties during irradiation, there are also time-dependent effects following irradiations, especially after high dose rate irradiations. There are two models that have been proposed to explain the “true” dose rate effects [51 ][60]. A common feature of these models is that, if the irradiations are performed at either high electric field or at elevated temperature, the enhanced low dose rate effect should be minimized. The first model [51] suggests that, “during higher-rate irradiation, the large number of defects in the bulk of the oxide evidently retard the hole transport process by several decades over its normal duration. The slowly transporting or metastably trapped holes in the bulk of the oxide act in conjunction with the building space charge due to more deeply trapped holes near the Si/ SiOz interface to reduce the charge yield in the bulk of the oxide in the high-rate case as compared to the low-rate case. This reduction is due to the decreased local potential gradient (decreased local time-dependent electric field) between the trapped holes near the silicon interface and the gate, caused by increased positive charge in the oxide bulk or near the gate interface, as shown in Figure 23(a). The slowly transporting and/or metastably trapped holes III-37

.!

,.

.

in the bulk of the oxides also provide additional electrostatic fields during highrate irradiation that causes holes to be trapped, on average, a little closer to the Si/Si02 interface than during low-rate irradiation.”

m

@

++ + + +++ + +++++++++ +-

+

Delocalized Hole / Centers\

++

+ +

+

+

Holes in Deep Traps

+ ~++

+-

+- 4

-e-h Dipoles

1 —

+ ++ b +-

+++++++

I —

(a)

(b)

High Rate

Low Rate

Figure 23 Schematic Illustration of Mechanisms Contributing to Enhanced Net Positive Charge in Bipolar Screen Oxides at Low Dose Rates. Figure (a) Refers to High-Rate Irradiation and Figure (b) to Low-Rate Exposure. Mechanisms Apply to Soft Oxides at Low ElectricFields.[51 ]

“The reduction in charge yield at high rates due to these space charge effects, coupled with the relatively slow trapped-hole neutralization rate at O V for these devices, evidently accounts for the increase in trapped-hole density at low rates. That some holes are forced by the bulk space charge to be trapped a little closer to the silicon at high rates than they otherwise would be at lower rates facilitates the formation of neutral trapped-hole/electron dipoles near the silicon. Some dipoles will function electrically as border traps, and others will be electrically indistinguishable from annealed holes. This leads to the enhanced density near the Si/SiOz interface during the high-rate trapped-electron irradiations. Finally, space-charge and electrostatic back-pressure effects only dominate device response at low fields because the applied electric field dominates local fields for higher-field exposure.” The second model proposed in [60] suggests that “electron-trapped charge is smaller for large electric fields in oxides and low dose rates. For low dose rate conditions, the total positive charge in the oxide depends of the number of holes that escape recombination during dispersion transport. It is usually assumed that a hole combines with a free electron, but the interaction of a free hole with trapped electron must be taken into account. Thus, the presence of

III-38

negative-trapped charge in oxide can dramatically decrease the hole yield because of free hole recombination. The electron traps m important in bipolar screen oxides because the following conditions are satisfied. First, the electric field in the oxide is small. Therefore, the radiation-induced electron traps are occupied. Second, the conventional screen oxide is not radiation-hard, The capturing of holes takes place in the bulk of the oxide; therefore, the electron traps are generated along the entire path of the holes to the Si/Si02 interface. Under low dose rate irradiation, the occupation of electron traps is smaller than for moderate dose rates. It causes the decrease of hole loss due to the capture of holes at occupied electron traps, which leads to the increase of positive charge buildup. It means that the positive oxide-trapped charge in screen oxides increases with the decrease of dose rate. The thermal annealing of positive oxide-trapped charge at room temperature during long-time, low dose rate irradiation cannot compensate their growth caused by the increasing of positive charge yield.” Another model has been suggested [62] that may account for the time-dependent effects following the higher dose rate irradiation, such as the continued gain degradation in lateral and substrate pnp transistors. This model proposed in [62] suggests that “the hole transport, as described by the CTRW (continuous time random walk) model, can be applied to the thick field oxides and low electric fields present over the base-emitter junctions of bipolar transistors. Very thick oxides (= 1pm) are present over the base-emitter junction of substrate and lateral pnp transistors. It is assumed that the lowest dose rate for which devices still exhibit dose rate effects is due to the time required for charge to transport to the interface, which is extended to much longer time periods under low field conditions and also increases with oxide thickness. Previous field oxide work also showed that the fraction of the charge that remains trapped in the oxide bulk region is strongly This may explain why pnp transistors in the affected by the oxide thickness. junction-isolated processes exhibit more damage than npn transistors; oxides over the emitter-base region of pnp devices are approximately three times as thick as for npn transistors. Based on npn and pnp oxide thickness of 3500 and 10000 angstroms, respectively, the npn transistors should be affected by dose rates down to 1 rad(Si)/s and the pnp transistors down to .008 rad(Si)/s. Based on limited oxide thickness results, it predicts that the relative damage in npn transistors will be approximately a factor of two or three higher when bulk trapping is taken into Still account at low dose rates, compared to trapped charge at the interface. higher relative damage is expected for the thicker oxides in the pnp transistors, but it is not possible to estimate the magnitude of increased damage from the limited data available from field oxides. One possible explanation for the dose rate dependence is radiation-induced recombination, which would reduce the fraction of holes that are trapped in the bulk of the oxide. In order to test this assumption, an experiment was performed using the LM111 comparator under mixed dose rate conditions to examine the effect of nonconstant dose rates on enhanced damage.

III-39

One set of devices was initially irradiated at a low dose rate, increasing the dose rate to a much higher level after the initial irradiation was completed. The opposite dose rate scenario was used for a second set of devices. The results are shown in Figure 24, along with earlier results from a different group of devices irradiated at high rates. From the figure, it can be seen that high- and low-rate damage effects appear to be independent. These data suggest that, at least in thick oxides, once charge is trapped within the body of the oxide, little recombination occurs from the excess electron density produced by ionization. The implication is that charge in the bulk region acts independently from the mobile charge, a rather surprising result.”

500

500

50

rad(Si)/s

400

300 m

m “i

200

200

t t 100

50 rad(Si),

0

0

<

0

10

20

30

40

50

Total Dose (krad(Si)) Figure 24 Degradation of Input Bias Current of an LM111 Comparator under Mixed Dose-Rate Conditions. [62]

In addition to the slow transport of holes in thick oxides at low fields, there may also be a slow buildup of interface states. If the primary mechanism for interface state buildup is the twostage process described by Winokur, et al.[71 ] and McLean, et al. [72], then the second stage buildup would be significantly increased in time for thick oxides at low field. However, there is some question about the actual nature of the interface state buildup in thick bipolar oxides, since it has been shown that there are prompt interface states in bipolar oxides that occur within milliseconds[73] [74]. Although models have been proposed to explain the enhanced low dose rate response, none of the models explains all of the observed behavior. Additional work will be required to fully explain both the irradiation and post-irradiation response.

111-40

6.2 Transistor and Circuit Response Increased gain degradation in bipolar transistors irradiated at low dose rates has been studied extensively for bipolar processes from several manufacturers since the first report in 1991. Figures 25 and 26 from [44] show the change in A1/~ for modern vertical crystalline emitter npn and pnp transistors irradiated to 70 krad(Si02) at three different dose rates and then annealed at room temperature. In each case, the gain degradation increased with decreasing dose rates and was a factor of two greater for the npn and three greater for the pnp for 1.1 versus 300 rad(Si02)/s at 70 krad. Minimal annealing was observed at room temperature for either transistor type.

1 ()-1

\\

10-2

~

VENDORA NPN 70 krad(SiO ) 1.1

rad(Si)jsec

-a-

16

rad(Si)/sec

~

3013 rad(Si)/sec

.

0 0

103

1(J4

105

106

Time (see) Figure 25 Change in A1/~ for Vertical Crystalline Emitter npn Transistor vs. Dose Rate.

III-4 1

10-’-T+~ VENDORA PNP

I ~

10-’

70 krad(SiO ) 1.1 rad(Si)/?sec

~

16

~

300

rad(Si)/sec rad(Si)/sec

-10-2

o%~ 0

0

103

104

105

106

Time (see) Figure 26 Change in A1/~ for Vertical Crystalline Emitter pnp Transistor vs. Dose Rate.

For a second process from Vendor B reported in [44], the A( l/~) degradation of a vertical polysilicon emitter npn transistor is a factor of four to seven greater for 1.1 versus 300 rad(Si02)/s at a total dose of 200 krad (SiOL). Additionally, for the Vendor B process, there was a continued decrease in gain for the devices irradiated at the higher dose rates during a room temperature anneal following irradiation. For the two Vendor C processes shown previously in Figure 21, the vertical polysilicon emitter npn transistor A( l/~) degradation was a factor of ten greater for process 1 and fifty times greater for process 2 for 1.1 versus 300 rad(SiOz)/s at a total dose of 200 krad (Si02). For the room temperature anneal testing of the process 1 and 2 devices irradiated at 300 rad(SiOz)/s, the process 1 device continued to decrease in gain, while the process 2 device gain was stable. Additional data on standard crystalline emitter npn transistor processes from [46] and [48] report a factor of 2x to 3x in base current increase when comparing low rate of 1 rad(SiOz)/s to 300 rad(Si02)/s Cobalt-60 irradiation. Figure 27 from [48] shows the additional increase in base current for this process at five different dose rates.

III-42

20

20

15-

1.5pm x 1.5~m Emitter

10-

-15

-10

5-

-5

—v o

BE- Ov I

100

101

I lr

I

o

1P

Dose Rata (rad(Si02)Asec)

Figure 27 Dose Rate Dependence of Standwd Crystalline Emitter Vertical npn Transistor.[48]

Similar dose-rate-dependent gain degradation has been shown for polysilicon emitter pnp transistors. The increase in base current for a lateral, substrate, and vertical geome~ device is shown in Figure 28 from [58]. All three devices show a strong dose rate dependence on gain degradation with the substrate device exhibiting a factor of 20x larger increase in excess base current and 10x greater increase for the lateral device for. 1 versus 1000 rad(Si02)/s. Although a limited dose rate range was presented for the vertical device, previous data from [44] would indicate an expected 10x to 20x factor for excess base current for the vertical pnp transistor over a. 1 to 1000 rad(Si02)/s dose rate range. Figure 29 from [58] replots the data from Figure 28 to The substrate pnp transistor still has show normalized current gain versus dose rate. approximately 7090 of its original gain after 100 krad (Si02) at the highest dose rate, but only about 1590 at the lowest dose rate. Similarly, the lateral pnp has about 2090 of the original gain after 100 krad (Si02) at the highest dose rate, but only about 3% at the lowest dose rate. For a circuit that may be designed to operate with a fixed minimum gain of 10 for a lateral pnp transistor and assuming an initial gain of 100, the circuit irradiated at the high rate would still have 2x margin for operation, while the circuit irradiated at the low dose rate would have failed long before 100 krad. Also, it should be noted that there is no indication that the dose rate dependence of gain degradation is saturating, even at dose rates below .1 rad(SiOz)/s.

III-43

.

,

,,

,

~1

I@

1 Figure 2s Excess Base Current

VPMP (500 kmd@lo*)) t

vs.

Dose

Rate

for Vertical, Substrate, and Laterai pnp Transistors.[58]

“L--

X.J) -

-

1

SPNP (loo

VPNP (500

kmd(sloJ) hmd(sloJ)

1~ ~

lIY

1~

101

101

lIY

DOW Rate

l(p

,@

,@

(rad(SiOJ/aec)

Figure 29 Normalized Current Gain vs. Dose Rate for Vertical, Substrate, and Lateral pnp Transistors.[58]

For some circuit parameters, the interaction between transistor degradation and the effect it will have on circuit parameter degradation are straightforward to analyze in some cases. Input bias current is one such case. A typical input structure was shown previously in Figure 7. In many cases, the input is directly driving the base of an input transistor; and, therefore, the input bias current is inversely proportional to the input transistor gain. The LM101 has a conventional vertical npn transistor for the input transistor. Figure 30 from [54] shows the change in input bias current for the LM 101 op amp versus total dose for several dose rates. Note that the degmdation is saturated at dose rates below .37 rad(Si)/s. Also, the low rate input bias current is

III-44

about a factor of two times greater at low rate versus high rate. This is similar to the transistor gain degradation reported for crystalline emitter vertical npn transistors shown in Figures 25 and 27, which exhibited a similar two to three times increase in base current for low rate versus high rate. Other circuits, such as the LM111 and LM324, utilize a substrate pnp transistor for the input transistor. Figure 31 from [54] shows the input bias current versus total dose at several dose rates for the LM324 comparator, which has a substrate pnp input transistor. For this circuit, there is a six times greater increase in input bias current between the high rate of 50 rad(Si)/s and the low rate of .005 rad(Si)/s at 15 krad(Si). Similarly, in [58], a much larger dose rate dependence was observed for the substrate pnp transistor, which was approximately twenty times over four decades of dose rate. Note also, in this case, that the dose rate dependence is not saturating until .005 to .002 rad(Si)/s.

20

20

15

➤

10

-10

-5

5 ~

0.02 red(Sl~sec 0.37 rad(SiYsec

~

50.0

❑

0

15

rad(si)kc

1“

I

I

I

I

0

10

20

30

40

o 50

Total Dose (rad(Si)) Figure 30 Change in Input Bias Cur-rentvs. Total Dose for LM 101 Op-Amp with Vertical npn Input Transistor for Several Dose Rates. [54]

III-45

350

350

300

300

250

200

150

100

50

50

0

0 0

5

10

15

20

25

Total Dose (rad(Si)) Figure 31 Change in Input Bias Current vs. Total Dose for LM324 Op Amp with pnp Substrate Input Transistor for Several Dose Rates.[54]

In the previous two examples, the parametric degradation was generally linear over a wide total dose range and was observable for a wide range of dose rates until saturating at very low dose rates. Other parameters exhibit more complex dose rate behavior. Figure 32 from [62] shows the change in input offset voltage (Vos) versus total dose for the LM324 op amp for several dose rates. For this parameter, there is minimal degradation in Vos versus total dose at dose rates of 50 or .005 rad(Si)/s out to a total dose of 70 krad(Si). However, when the dose rate is decreased to .002 rad(Si)/s, there is a large increase in Vos by 30 krad(Si). This large nonlinear response has serious hardness assurance implications in that, in this case, testing at higher rates and extrapolating the response to low rates do not predict the abrupt failure. The likely explanation for this type behavior is degradation of internal bias circuits, which causes sudden parametric or functional changes after the threshold for normal operation is exceeded. Many linear designs use lateral pnp transistors in the current sources and are designed to operate with a wide range of transistor gains. However, once the gain decreases below a minimum design value, the effect is to “starve” internal current sources, causing large changes in circuit parametric or functional performance once the operating threshold is exceeded. Further evidence of the degradation of internal current bias sources is shown in Figure 33 from [62]. Normalized power supply current versus total dose is shown for the same part type LM324, as shown in Figure 32, for several dose rates. The power supply current is decreasing with dose rate and total dose so that, at 25 krad(Si) at .002 rad(Si)/s, the total power supply current has decreased to less than 60’%0of the initial pre-rad value.

III-46

5

s

O.oozrlM(Sl)/COC

~

0.005rad(slysee 50.0 I’@slyeoc

~

~ 0’

0

s g -5-

--5

~B

-10-

--10 1.Ma94 ~tldAmpMlk blanlIhMhlmEmCbrOh Hu~ pup Input Tnndabr

-15

I

0

I

1

1

I

I

1020304050 Toti

Ikse

-15

1,

s070

so

(krad(Sl))

Figure 32 Input Offset Voltage vs. Total Dose for the LM324 Op Amp at Various Dose Rates. [62]

1.0

1.0

0.9

0.s

0.7

0.0

0.5

1,, ,, 0

1

5

10

1

15

1

1

20

2s

t 0.6 ao

Total Dme (krad(Si)) Figure 33 Normalized Power Supply Current vs. Total Dose for the LM324 Op-Amp at Various Dose Rates. [62]

The operating threshold for the current bias sources and circuits can vary greatly from circuit to circuit, even within the same process, and is primarily determined by the design margin that the circuit designer incorporates into the circuit. Also critical is the bias point for the transistors since, as shown previously, the transistor gain decreases much more rapidly at lower operating current levels. Since these are commercial Iineiu circuits, the circuit designer has chosen the operating point to achieve the targeted electrical performance, including power dksipation. Design margin is included to accommodate operation over the rated temperature

LII-47

.,

.

range, supply voltage, and normal manufacturing process variations while achieving required electrical performance and high manufacturing yield. A circuit with more design margin is likely to be more total-dose tolerant if all other factors are equal. For example, a circuit may be designed for a process that has a nominal lateral pnp gain of fifty, but will still operate within specification down to a minimum gain of ten. Some performance was probably sacrificed so that the circuit could operate over a wide range of conditions. Assume another circuit designed in the same process and designed for a minimum lateral pnp gain of twenty to achieve better performance. If the gain decreases the same for the lateral pnp in both circuits, the one designed to operate with a minimum gain of ten will be more total-dose tolerant (at least for nominal operating conditions) than the circuit requiring a gain of twenty. The LM137 voltage regulator is another circuit for which the gain degradation of a lateral pnp transistor was identified as the cause of low-rate failures at total dose levels below 15 krad(Si) for several manufacturers [55]. Selective irradiation with a scanning electron microscope, mechanical probing, and circuit analysis was used to identi~ a multi-collector lateral pnp in the startup circuit that was responsible for total dose failure. Devices that were irradiated at higher dose rates failed at two to three times higher levels. Probing of the lateral pnp transistors measured initial pre-rad gains of twenty that decreased to less than five at 15 krad(Si). Measurement and simulation of the circuit indicated that, when gain decreased below ten, a small additional gain decrease led to a large increase in the threshold voltage required for startup. The transistor identified as causing the failure also degraded faster than other lateral pnp transistors, which was attributed to the geome~ that had a larger perimeter region. Although no measurements were made directly relating pnp gain degradation to dose rate for this circuit, if the same trend as observed for the pnp transistor dose rate sensitivity reported in Figure 29 is applied, the failure levels observed and dose rate sensitivity would be similar. 6.2.1 Bias Effects The sensitivity of bipolw transistor gain degradation to applied bias during irradiation can vtu-y greatly between processes. In [46], it was reported that collector-base bias had a negligible effect on total dose gain degradation, which is consistent with the surface distance in the neutral base between the emitter-base junction and the collector. For the emitter-base junction, reverse bias produced slightly more gain degradation than no bias or a fonvard-biased emitter-base. However, in [54], it is reported that -- for discrete transistors -- gain degradation is strongly affected by collector-base voltage applied during irradiation. Much greater degradation occurred when the collector was biased at high voltage during irradiation and is four times greater for 50 volts collector-emitter bias than 10 volts. For most discrete devices, darnage was approximately a factor of two more when devices were irradiated under reverse bias (-2 volts) compared to moderate forward bias (0.5 volts). However, these results were for discrete transistors, whose fabrication process is significantly different than for monolithic integrated circuits. When four types of integrated circuits were irradiated at 50 rad(Si)/s in an unbiased condition, the darnage was nearly the same as in the biased case[54]. Similar results were reported in [63] when no bias was compared to static dc bias. Differences in total dose hardness between these two bias conditions were comparable to the part-to-part variation. Other similar results on many bipolar linear ICS were referred to in [56]. More significant bias effects were reported for high dose rate conditions in

III-48

[62] and are shown in Figures 34 and 35. Figure 34 shows the change in input bias current for the OP-27 op amp from one manufacturer for two dose rates and bias conditions. With the devices unbiased during irradiation, only a slight positive increase was measured for the input bias current, similar to the low dose response. When the circuit was irradiated under bias, a large negative input bias current occurred above 25 krad(Si) at high dose rates. Devices from a second manufacturer exhibited larger increases for the unbiased than the biased condition at the higher dose rate of 50 rad(Si)/s, as shown in Figure 35. These examples illustrate the different responses that can occur in the same part type from different manufacturers for various bias conditions and dose rates. The first time that a part type is radiation-tested, a conservative approach should be taken by evaluating the bias sensitivity for that particular device and not depending on extrapolating results from a similar part or same part type from a different manufacturer. Multiple mechanisms may also be involved in explaining the circuit response, each with a respective bias sensitivity.

m

r

1

H

400

-200

400

High Dose Rate =50 rad(SIYs

4oo -

Low Dose Rate = 0.005 rad(Si)ls ~ I-llghDoss Rats - Biased ~ l+lghDOSSRate - Unbiased ~ LOW DOSS R~e . Bias~

-soo -

-s00

,,,,,,l\,,l,.,, -1 Wo

0

I 10

r

-1000 20

30

40

so

Total Dose (krad(Si)) Figure 34 Input Bias Current vs. Total Dose for Linear Technology OP-27 Op Amp. [62]

11149

..

.

m 450 400 250 ~

Low DoseRate= 0.005rad(SIYaec

/F

m 250 2W 150 100 50 0

---

o

10

20

30

40

50

Total Dom @rad(Si))

Figure35 Input Bias Current vs. Total Dose for Analog Devices OP-27 Op Amp. [62]

6.2.2 Temperature

Effects

One of the models to explain the dose rate effect is that charge yield is reduced at high dose rates due to the large number of defects in the bulk of the oxide that retard the hole transport process by several decades of time, The slowly transporting or metastably trapped holes in the bulk of the oxide act in conjunction with the building space charge to reduce the charge yield in the bulk of the oxide in the high-rate case as compared to the yield in the low-rate case. To perform an independent check of this model, it was well known that hole transport is thermally activated. Moreover, delocalized hole centecs are typically neutralized at temperatures well below that at which deep hole traps anneal. An experiment was performed to see if capacitors, which simulated the screen-oxide over the base-emitter region, could be irradiated at a temperature high enough to speed the transport and/or annihilation of the metastable holes in the bulk of the oxide without significantly affecting the deeper trapped-hole distribution near the SiSi02 interface. The results of this experiment are shown in Figure 36 from [51], which shows the rnidgap voltage shift for a number of irradiations over a range of dose rates at 25°C compared to the shift at 60°C and 200 rad(SiOz)/s. Clearly, the midgap shift is larger after irradiation at 60°C than 25°C. Additionally, the 60”C at 200 rad(SiO#s irradiation shift is almost identical to the 25°C at 1 rad(SiOz)/s shift. To further validate the model, bipolar junction transistors were irradiated at 25°C and 60°C at varying dose rates. The results of this experiment are shown in Figure 37 from [51]. Again, the 200 rad (SiOz)/s irradiation at 60”C causes approximately three times greater increase in excess base current (and also in gain degradation, since the collector

nl-50

current is unaffected) than 25°C irradiation, consistent with the capacitor irradiation in Figure 36. At 20 rad(Si02)/s, the excess base current is even greater: However, at 1.7 rad(Si02)/s, significant annealing or compensation of holes in deep traps also occurs during the higher temperature irradiations, reducing the excess base current at 60”C. Still, the bipolar transistor response at elevated temperature and high dose rate is promising as a potential test technique to predict the low-rate response.

4.0

-4.0

900krad Biae = OV 25°C ● ● 60°c Dose=

B

45

E

-

●

4.5

25°C

--5.0

\ ●

--5.5

●

--6.0 ●

+5

I 10

1 Dme

Rate

I 100

-6.5 1000

(rad(SiOa)/see)

Figure 36 Midgap Voltage Shift vs. Dose Rate for 25 and 60°C Irradiation of Screen Oxide Showing Large Shift at 60°C, and High Rate is Equivalent to Low-RateShift.[51]

III-51

.,

,,

-

6

6 A

25°C 600C

~

-5

-4

A

-3 A

1!

-2

42 Is 01

A

-1

z

o 0.1

I 1 Do6e

I 10 Rate

I 100

I lmo

o

(rad(SiOJ/6ec)

Figure 37 Normalized Excess Base Current vs. Dose Rate at 100 krad(Si02) for 25 and 60”C Irradiation of npn Bipolar Transistor Showing 60°C and High Rate Bound Low Rate Increase.

A similar experiment was performed on lateral pnp bipolar transistors to validate the applicability of the theory for a different class of devices than discussed previously, Extensive high temperature testing was performed by irradiating devices at 24,45, 60, 80, 100, and 125°C at a dose rate of 167 rad(Si02)/s. Figure 38 from [59] shows the excess base current at V~ = 0.7V for lateral pnp devices irradiated to 100 krad(Si02). For comparison, the dashed line represents the degradation in devices irradiated at 0.1 rad (Si02)/s, but at room temperature. The excess base current increases approximately linearly with irradiation temperature in this temperature range, The continued increase in excess base current as a function of irradiation at the highest temperature of 125°C used in these experiments is surprising. However, devices irradiated at room temperature, but annealed at high temperature, show the damage begins to recover at 150”C. This suggests that 125°C may be close to the maximum temperature to maximize darnage for this process. The excess base current for the same devices is shown in Figure 39 from [59] versus total dose for devices irradiated at a variety of dose rates. It can be seen that the excess base current increase of the device irradiated at 100”C and the high dose rate of 167 rad(SiOz)/s is larger than any of the devices irradiated at lower dose rates and 25”C, including the devices at .01 rad(Si02)/s. High-temperature irradiation, as a method to predict the low-rate response, will be discussed in greater detail in a later section.

III-52

S.o —

3

-’

S.o

1S7 radh (x-ray)

5.0

-6.0

4.0

-4.0

3.0

-3.0

2 ———

———

20

—

Irmdlaiud

Dwl~

-2.0

at 0.1 MCUS(CO-so) -1.0

1.0

0.0

1 I 020408060100 Irradiation

1

1

1

I

0.0

120140

Temperature (“C)

Figure 3S Excess Base Current at V~~ = 0.7 V vs. Irradiation Temperature for Lateral pnp Transistor Irradiated to 100 krad(SiOJ at 167 rad (SiOJ/s in an X-ray Source. The Dashed Line Represents Devices Irradiated at 0.1 Rad (SiOJ/s in a CO-60 Source. The X-ray Data Have Been Scaled to Account for Source Differences. [59]

lW

10

1

Total Dose (krad(SiOJ) Figure 39 Excess Base Current vs. Total Dose for Devices Irradiated at a Variety of Dose Rates. The HighTemperature ( 10O°C), High-Rate (167 Rad(SiO#s Excess Base Current is Higher Than Any of the Low-Rate Devices. [59]

III-53

.,

.

.

,,

.

High temperature irradiation of circuits produced less dramatic results than the individual transistor testing. Figure 40 from [54] shows the results of irradiating LM111 comparators at various dose rates and temperatures. A substantial increase in input bias current occurred when the devices were irradiated at an elevated temperature of 60”C at 50 rad(Si02)/s compared to room temperature at the same dose rate. However, the net increase, a factor of about 1.7, was only about a third of the increase at low dose rates. Similar results were reported for elevated temperature irradiation of LM101, LM 124, and LM 139 circuits [1], where devices were irradiated at 125°C and 100 rad(SiOz)/s. This was compared to data taken at room temperature and .001 and .01 rad(SiOz)/s. Input bias current increased by about a factor of three for the elevated temperature high rate over the room temperature high rate, but was a factor of two to as much as eight less than the input bias current increase for the low-rate parts. Therefore, while elevated temperature irradiation of transistors appeared to be a promising test method to predict the low-rate response, it has not been validated for circuits. Additional work will be necessary to investigate optimal irradiation temperature and possible combination with overtest and annealing.

300

+ +

0.005 rad(Si)/s 0.02 rad(Si)/s

+ . . .

50 rad(Si)/s

I

60”C -50 rad/s

300

/

1

200

100 !-

0 0

5

10

15

20

25

30

35

40

Total Dose (rad(Si)) Figure 40 Effect of Elevated Temperature Irradiation on Input Bias Current Increase forLM111 Comparator Showing Elevated Temperature Causes Increased Damage vs. Room Temperature, But Does Not Bound Low Rate Damage.[54]

6.2.3 Post-Irradiation

Response

The post-irradiation response of bipolar transistors and circuits is varied, depending on the fabrication process, circuit type and manufacturer, measured parameter, and post-irradiation temperature. Figure 41 from [48] shows the post-irradiation response of a standard emitter vertical npn transistor that was irradiated to 500 krad(SiOz) at 240 rad(SiOz)/s and then annealed

III-54

under 2-V base-emitter reverse bias at various temperatures. For the room temperature annealing condition, the base current recovered slightly after the 150-minute anneal. For the isochronal anneal, slightly more recovery was observed from the 30-minute 60”C anneal; but significant recovery was observed after an additional 30-minute 100°C anneal and 30-rninute 150”C anneal. Continued, but smaller, recove~ was observed after 30-rninute 200 and 250”C 30-minute anneals shown. Similar nxults are shown in Figure 42 from [44] for a polysilicon emitter npn transistor that was annealed at 100”C. However, during the first 1000 to 3000 seconds of the anneal, there was a continued slight decrease in gain (presumably increase in base current); and then the gain continued to recover until the end of the 168-hour anneal.

12

1

J

I

I ------

----

---

12

. ..---..

- -10

10BtandardEmtttar

-0

82V Ravamse Elm 1.5pmx 1.5pm Emitter

6-

-6

4-

-4

-2

2— o

l~hronal Annaallng ROemI Tamparatura Annsallng

I Inlt

Poatrad

60”C

Anneal

I 1 W“C

1 150°c

I moot

o 250”C

Temperature

Figure41 Room Temperature and Isochronal Anneal of Reverse-Biased Standard Emitter npn after 50C-krad Irradiation at 240 rad(SiOJ/s Showing Recovery after 30-Minute Anneals at (A)60, (B)1OO,(C) 150, (D)200, (E)250°C. [48]

III-55

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Elevated Temperature Anneal of Polysilicon Emitter npn after 200- to 300-hd rad(Si02)/s Showing Continued Degradation and Then Recovery. [44]

Irradiation at 300

A set of experiments was designed to evaluate the post-radiation response of polysilicon emitter lateral pnp transistors. Unlike the npn transistors discussed previously, the laterid pnp transistors continued to degrade during room-temperature and elevated-temperature annealing. Figure 43 from [59] shows the excess base current versus time after being irradiated to 100 krad(Si02) at 10 rad(Si02)/s and annealed at room temperature. The excess base current continues to increase following irradiation and approaches the amount of degradation in devices irradiated at low dose rates, as shown by the dashed line(,05 rad(Si02)/s). After 48 hours, the increase in excess base current saturated and remained almost constant until the end of the 168hour post-irradiation test. Additional lateral pnp transistors were irradiated to 100 krad(Si02) at 167 rad(Si02)/s and then an isochronal anneal performed for 30 minutes at each temperature up to 150°C. Figure 44 from [59] shows the excess base current at Vw = 0.7 V versus anneal temperature. The base current increases slightly during the w,neals up to 125°C , before decreasing slightly during the 150°C anneal. These transistor results suggest that circuits may respond differently during postirradiation anneals, depending on the dominant degradation mechanism. If either crystalline or polysilicon emitter npn transistors are responsible for the degradation, the circuit may exhibit recovery during the post-irradiation anneal, especially if the anneal is performed at elevated temperature, If lateral pnp transistors dominate the circuit parametric or functional degradation,

III-56

the circuits may show additional degradation during the post-irradiation anneal and even degrade slightly more if the anneal is performed at elevated temperatures up to 125°C. If a third mechanism is involved, such as leakage current due to inversion of a p-surface layer, the device will likely show more response at a higher dose rate and recover during a post-irradiation anneal. Since many bipolar circuits can have all three mechanisms occurring simultaneously, the initial and post-radiation response can be quite complex.

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Figure 44 Excess Base Current vs. PostIrradiation Anneal Temperature for Lateral pnp Irradiated to 100 krad (Si02) at 167 rad(Si02)/s Cobalt-60 Showing Continued Degradation up to 125°C Anneal Temperature. [59]

Degradation Post-Irradiation. [59]

The different post-irradiation response of circuits at various post-irradiation temperatures is shown in the following examples. In [54], annealing tests were done after both low and high dose rate irradiations to see if the damage was stable. Devices were measured after annealing at room temperature for time periods of approximately 200 hours. Changes of only a few percent occurred in input bias current. Post-irradiation response was quite different for the Motorola LM139 comparator. Figure 45 from [63] shows this device to be dose rate sensitive with minimal degradation occurring in J&f,etat 200 kradh and significant degradation occurring at 15 krad/h and 300 rad/h. The postirradiation response of the 200 Icrad/h devices after an irradiation to 37 krad is shown in Figure 46 from [63]. ~ff~~ increased slightly at 25°C until 200 hours after irradiation, after which it However, when annealed at elevated temperature, ~ff~t increased decreased slightly. significantly at a post-irradiation temperature of 70”C and even more at 10O°C. This response may also be due to the balance between the input transistor matched pair and less to the absolute degradation in gain.

III-57

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Figure 45 ~m~,vs. Total Dose at Three Dose Rates for Motorola LM 139.[63]

Post-imadiation room-temperature response for the 0P400 is shown in Figure 47 from [63]. The device exhibits little dose rate sensitivity with a 40-krad irradiation producing nearly equal increases in input bias current. However, the post-irradiation response is significantly different between the three dose rates. The highest rate device recovered 75% of the end-ofirradiation increase in input bias current. The lowest rate device recovered only about 20% of the end-of-irradiation increase. This is unusual in that no irradiation dose rate sensitivity was observed, but the post-irradiation anneal is sensitive to the irradiation dose rate.

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600

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Figure 47 25°C Annealing of 0P400 after 40 krad Irradiation Showing Significant Difference in Post-Irradiation Response, Depending on Irradiation Dose Rate.[63]

III-58

The post-irradiation response for the LMl 37 voltage regulator was evaluated for four different manufacturers in [55]. The post-irradiation response measurements for these devices consisted of a 24-hour at 25°C anneal immediately after irradiation, followed by a 168-hour at 100”C anneal. Parts from manufacturers A, B, and C exhibited the same functional failure mode of failure to regulate below a minimum voltage, referred to as VO~. Previous discussion of this device identified a lateral pnp transistor as believed to be responsible for the failure. The manufacturer D part exhibited only minor degradation. If a lateral pnp is responsible, it would be expected that the circuit would degrade further during the post-irradiation anneal. However, the devices from manufacturers A and C showed minimal change after the 24-hour and 25°C anneal, while the manufacturer B devices exhibited significant recove~ after the 24-hour anneal. All three manufacture’ devices exhibited almost complete recovery after the 168-hour and 100”C anneal. These results indicate that either the lateral pnp transistor is not the responsible failure mechanism or this pnp transistor has a different post-imadiation response than previously discussed. The post-irradiation response of the LM124, LM137, and LM139 ICS is discussed in [56] for a 168-hour at 25°C anneal followed by a 300-hour at 100”C anneal. The LM124 has a pnp input transistor, so input bias current is inversely proportional to the pnp transistor gain. The LM124 post-irradiation response follows the expected behavior by increasing slightly for the 25°C anneal, and then both the high rate and low rate increase substantially after the 100”C anneal. Most of the other LM124 parameters have some post-irradiation response, but the responsible circuit element is difllcult to identi@ without doing a detailed circuit analysis. The LM139 input bias current had a similar response to the LM124 with a slight increase for the 25°C anneal and then a substantial increase after the 100”C anneal. Again, this would be expected, since the LM 139 also has a pnp input transistor. The LM137 had a different post-irradiation response in that the device showed significant recovery after the anneal, as reported previously. This would also indicate that the pnp transistor gain degradation is not responsible for the degradation. It is obvious that, since many of the bipolar linear circuits contain a combination of lateral pnp, substrate pnp, and vertical npn transistors, the dose rate and post-irradiation response can be a complex combination of gain degradation for the three; and identi~ing the responsible circuit element(s) can require more sophisticated analysis tools. These will be discussed in the next two sections on circuit modeling and scanning electron microscope spot irradiation. 6.3 Circuit Modeling Circuit analysis is primarily performed using a combination of hand analysis by experienced circuit analysts and SPICE simulations. SPICE analysis requires an accurate netlist describing the complete circuit, as well as accurate bipolar transistor models to describe the preand post-electrical characteristics of the transistors. The netlist can be generated by cooperation from the manufacturer (which may be difficult) or by reverse engineering (which can be timeconsuming). A photomicrograph is taken of each circuit to be reverse-engineered and analyzed to determine transistor polarity, layout, and emitter area and geometry. One difllcult aspect of generating an accurate netlist is including all parasitic elements and potential parasitic elements Either breakout transistors (transistor die from a test chip that may be formed post-irradiation. typically dropped into a few circuit locations on the wafer) must be obtained from the manufacturer or transistors isolated from the circuit and microprobe to obtain pre-irradiation

III-59

.

electrical characteristics. At least one transistor of each polarity and, ideally, several with various geometries should be characterized to extract geometrical dependence of SPICE parameters, including radiation effects due to emitter area and perimeter. The transistor’s electrical data are input into a parameter extraction program such as UTMOSV to extract the Gurnrnel model parameters. These parameters are scaled by emitter area or emitter perimeter for each transistor and verified by running a SPICE curve-tracer plot and comparing actual data to the actual parameters. Once a set of pre-irradiation parameters is obtained, a circuit simulation is performed to verify the pre-irradiation electrical characteristics of the circuit and compare simulated to measured values. Irradiations are then performed on the breakouts or isolated transistors at high and low dose rates for several dose levels. Breakouts are much easier to characterize, since they can be packaged and irradiated with bias applied, such as in the application circuit design. Isolated transistors are much more difficult to work with, since no bias can be applied during irradiation; and obtaining good contact repeatedly can be difficult These irradiation data are fit to extract the degraded transistor model using microprobe. parameters and the simulation repeated to simulate the post-irradiation performance. Simulations are then compared to the actual measured response. Once a set pre- and post-rad model has been established and agreement has been obtained between simulated and measured response, the circuit model can be modified to identify the critical elements that determine the radiation response. The most difficult task in performing accurate circuit simulation is obtaining accurate degraded transistor models that incorporate all parasitic effects, such as electric field from layout and metallization runs. The SPICE simulations are also useful in obtaining the worst case dc bias conditions for the circuit irradiations, if the worst-case transistor bias is known. 6.4 SEM Irradiation Spot irradiation with a scanning electron microscope has long been a valuable tool for identifying sensitive circuit elements and even transistor areas [7] [10] [15] [17] [18] [25] [55] and was a popular tool in the 1970’s before x-ray irradiators became popular. The advantage of a SEM is that it can be focused to a very small area and used to selectively irradiate a single transistor junction, a single transistor, an area of an IC, or even an entire IC. The SEM has been used previously to identi~ the emitter-base junction as the total dose sensitive area of the bipolar transistor [7] and was used to identify transistors responsible for circuit failure [15] [17] [25]. Attention must be paid to the depth dose profile as the typical SEM has an energy of about 20-40 keV, so penetration depth is limited. Correlation to Cobalt-60 irradiations should be established if quantitative results are important. The SEM has been used more recently to identify a multi-collector lateral pnp transistor as the circuit element responsible for the failure of the LM 137 voltage regulator [55]. Typically, a SEM irradiation experiment is performed by setting up the circuit under investigation to monitor critical electrical parameters in situ. An entire circuit irradiation may then be made to correlate the Cobalt-60 irradiation results with the SEM irradiation and also establish dosimetry calibration. Depending on how much is known about the circuit design and potential sensitive areas or transistors, selective areas are irradiated to isolate the degradation down to the desired sensitive area. Caution must be observed when only irradiating small circuit areas, because gain balances may be upset, which may cause unrealistic degradation that would not occur when more uniform gain degradation occurs during Cobalt-60 degradation.

111-60

7.0 HARDNESS ASSURANCE

TEST METHOD DEVELOPMENT

The development of an efllcient and reliable test method to predict the low-rate response of bipolar circuits, while keeping the test time reasonable (especially in the radiation source), is critical to identifying robust devices for long-term space applications. Few facilities can afford to dedicate a radiation source for the months to years that would be required to test to the lowest rates at which the dose rate effects saturate. Few systems can afford the time that would be required to conduct such long-term tests. This next section will look at some potential test methods to accelerate the test time required to accurately and reliably predict the low-rate response. 7.1 High Temperature

Irradiation

Elevated temperature irradiation of transistors and circuits was discussed extensively in the previous section. Figure 35 showed that a conventional npn transistor irradiated at 60°C and at 20 to 200 rad(Si02)/s had a larger excess base current increase than an npn transistor irradiated at 25°C and at lower dose rates of 0.4 to 2 rad(SiOz)/s. Figures 36 and 37 showed similar results for a polysilicon emitter lateral pnp where an irradiation temperature of 100°C at 167 rad(Si02)/s bounded the excess base current increase for dose rates down to .01 rad(Si02)/s. While these transistor results were promising, they were both on developmental processes for which no doserate-sensitive circuits were available to validate the circuit response at elevated temperature. Elevated temperature irradiation at high dose rates of the LM101, LM1 11, LM124, and LM 139 circuits found that they failed to predict the low-rate response by a factor of two to eight, as reported previously and shown in Figure 38. Only one elevated temperature was tried for each of these circuits, so it is unlikely that the optimum elevated temperature was selected for the experiment, Unfortunately, these circuits were from a commercial process for which there were no test transistors available to help optimize the irradiation temperature. As noted before, the npn and pnp transistors have different acceleration factors; so there may not be one optimal temperature for circuits that contain both type devices. Additional work is needed to see if an optimal irradiation temperature exists for the processes and circuits that exhibit excessive low-rate degradation. Test transistors from the same process and, ideally, from the same lot as the circuits would greatly assist the effort. Even if an optimal low-rate temperature can be identified, it may not completely bound the low-rate response. A combination of high-temperature irradiation, overtest, and post-irradiation anneal may be required to completely bound the low-rate response and serve as a reliable test method. 7.2

Post-Irradiation

Anneal

Post-imadiation anneal testing of conventional and polysilicon npn and polysilicon NPN transistors tend to emitter lateral pnp transistors indicates that they behave opposite. recover slightly during room temperature anneal and recover significantly at higher temperature The lateral pnp transistors behave the opposite and exhibit significant additional anneals. degradation during room temperature anneal and degrade slightly more at elevated temperatures. Figures 39 through 42 previously indicated this behavior. As expected, there was a varied circuit response during the post-irradiation anneal, depending on what was the dominant circuit element

III-6 1

causing the degradation. Some circuits exhibited recovery, and others showed additional degradation. However, in almost all the reported cases, the post-irradiation degradation did not bound the low-rate response. Figure 48 from [56] shows the post-irradiation response tier a 168-hour 25°C anneal followed by a 100”C 30Q-hour anneal. For most of the parameters, the anneal did not bound the low-rate response, although it did for a few parameters. Additional testing would be required to see if this were valid for very low dose rates. Similar results were reported for the LM 124 as shown in Figure 49 from [56]. For some parameters, the anneal is still a factor of two short of predicting the low-rate response. Since, in most circuit cases, the dominant circuit element is not known, a 25°C anneal may be the optimal temperature to accelerate the pnp degradation without causing too much recovery in the npn transistors. Also, again, an anneal by itself as a test technique may not totally bound the-low-rate response.

III-62

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III-63

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7.3 Overt.est Overtesting, by irradiating a circuit at high dose rate to a high enough level beyond the requirement to simulate the low-rate response, will only be effective if the high-rate degradation keeps increasing linearly. In many cases, this method is not effective due to saturation at the high dose rates or nordinear increases at the low dose rates. Figure 50 from [62] shows the saturation of the high-rate response for the LM1 11, No reasonable amount of overtest at the high dose rate will predict the low-rate response that is saturating at a value of about ten times the high rate response. Another example is shown in Figure 51 from [62], where there is minimal response at the high dose rate (and even at low dose rates above the low-rate threshold for effect). It is, again, unlikely that any amount of reasonable overtest will be an effective predictor of the lowrate response.

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Figure 50 Saturation Characteristics of LM I I 1 Comparator Input Current at Low and High Dose Rate. [62]

Can an effective test method be developed to predict the low rate response at reasonably high dose rates? Recent data from [68] indicate that there may be combinations of hightemperature irradiation, overtest, and post-irradiation anneal that can bound the low-rate response. Figures 52, 53, and 54 from [68] show the results from a combination of overtest with post-irradiation room temperature anneal. Figure 52 shows the input bias current increase for the LM139 comparator versus total dose and post-irradiation anneal time for various dose rates. Several devices are irradiated at a low rate of about 1.5 rad(Si02)/s to 200 krads. Other devices are irradiated to 500 (2.5x overtest) and 600 krads (3x overtest) at about 150 rad(SiOz)/s. Even at these factors of overtest, the highrate response is less than the low rate at 200 krads immediately after irradiation. However, after a 150-day unbiased room temperature anneal, the 2.5x overtest is only slightly less than the lowrate response (including low-rate anneal) and the 3x overtest bounds the low-rate response. Of coume, this technique would have to be validated for lower dose rates and additional devices and processes; but it is promising.

III-65

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Figure 52 LMl 39 Comparator Overtest and Anneal Results. [68]

Figure 53 shows the increase in input bias cument for the LM111 comparator versus total dose and post-irradiation anneal for various dose rates. One device is irradiated at a low rate of 1.5 rad(Si02)/s to 200 krads. A second device is irradiated to 600 krads (3x overtest) at a higher dose rate of about 165 rad(SiOz)/s. The high-rate irradiation stop point was past saturation and on the decline, so that the 200-krad low-rate point had about three times the input bias current increase as the high-rate point. At the end of the 150-day room temperature anneal, the high-rate device was only about 10% less than the low-rate device.

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III-66

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Figure 54 shows the increase in input bias current for the LM124 op amp versus total dose and post-irradiation anneal time for two dose rates. One device was irradiated at a low dose rate of 1.4 rad(Si02)/s to a dose of 200 krads, and a second device was irradiated at a higher rate of 150 rad(Si02)/s to a dose 500 krads for an overtest of 2.5x. Even with the overtest, the increase in input bias current was less than the low-rate part immediately after irradiation. However, after a 150-day room temperature anneal, the input bias current for the higher-rate part had exceeded the low-rate increase. Although the sample size and type of circuits were limited, a combination of 2.5 to 3 times room-temperature irradiation at high dose rate followed by a 50day room-temperature anneal bounds the low-rate response. Additional verification testing needs to be confirmed at lower dose rates and on a larger set of circuits. Including an elevated temperature irradiation or anneal combination may allow for a reduced overtest or reduced anneal time.

8.0 FUTURE TRENDS Although bipolar technologies are not advancing at nearly the same rate as CMOS, there have been significant advances recently with polysilicon and double-poly emitters and bases, bonded-wafer substrates, device scaling, and silicon-germanium devices. Single and doublepolysilicon base and emitters permit extremely shallow emitter and base regions. These allow for narrower base widths of 500~ and less, which contribute to much higher cutoff frequencies (fT). Many current mainstream advanced-performance bipolar processes have fm of 5 to 10 GHz. State-of-the-art bipolar processes that are just becoming commercially available have frs of up to 25 GHz and support circuit applications with operational bandwidths of 1 to 2 GHz. Total dose test results are limited, but reports such as [69] indicate hardness of up to 1 Mrad(Si02) with minimal circuit performance degradation. This is likely due to the use of only vertical npn and pnp transistors and the high surface concentrations due to ion-implanted or polysilicon-doped base and emitter junctions and thinner surface oxides. Unfortunately, many of these processes and circuits are for low voltage operation of 5 V and less; so considerable system redesign would be required to utilize these circuits. Also, the broad “standard product” base of circuits, such as the LM- and OP-series of devices that many cument systems utilize, is not available in advanced technologies. Several bipolar processes, such as Analog Devices XFCB, Harris UHF, and UTMC ACUTE, employ bonded-wafer substrates and trench isolation for complete oxide isolation of each circuit element. A cross section of typical devices was shown previously in Figure 5. The oxide isolation gives improved noise performance and reduced parasitic capacitance, which allows for faster devices and circuits. The biggest radiation improvement is in the high dose rate environment, where latchup is eliminated and photocurrent collection reduced, resulting in improved upset. Total dose hardness can be improved because there are no potential device-todevice leakage paths; and the need for a long-temn isolation diffusion, which has been shown The circuit total dose hardness is previously to degrade total dose hardness, is eliminated. primarily determined by the transistor fabrication method, as has been previously discussed. One of the most recent bipolar advances is the development of the silicon-germanium heterojunction bipolar transistor (HBT). With base widths of 350~ or less, frs of up to 117 GHz III-67

Preliminary radiation test results on transistors from this process [66] have been reported. indicate the potential forgood total dose hardness. Applications forthis technology are targeted for 10- to 20-GH2 RF applications.

9.0 ACKNOWLEDGMENTS I would like to acknowledge the support of our sponsors, Mr. Lewis Cohn of the Defense Nuclem Agency and Mr. Al Kuehl of the US Army Space and Strategic Defense Command, for providing the funding that has made much of the research in this area possible. The many researchers who have dedicated years to performing research and publishing in this area have provided invaluable historical material that has been used extensively in the preparation of this Mr. Ron Pease has provided guidance into organizing what, at times, has course material. seemed like chaos. Mr. John Bings has re-engineered the figures and drawings into a high Mrs. Linda Ramsden has provided invaluable editorial support in turning quality format. fractured barely intelligible English into coherent material. Most of all, I am thankful for my wife, Pam, who has helped, many a late night, to keep me going on this.

III-68

REFERENCES

[1]

R. L. Pease, H.J. Tausch, H. Barnaby, R.D. Schrimpf, D.M. Schmidt, “Radiation Analysis Transistors of Bipolar and Circuits,” MRC/ABQ-R- 1764 final report to NAVSURFWARCENDIV Crane (December 1995).

[2]

R.J. Widlar, “A Unique Circuit Design For a High Performance Operational Especially Suited to Monolithic Construction,” Proc. NEC, Vol. XXI, p. 85 (October 1965).

[3]

R.J. Widlar, “Op Amp With Improved Input-current Characteristics,” 7, p. 38 (December 1968).

[4]

R. J. Maier, “Radiation Induced Surface Recombination in Oxide Passivated Transistors,” IEEE Transactions on Nuclear Science, Vol. NS-14, No. 6, pp. 252-259 (1967).

[5]

A. G. Stanley, “Electron Irradiation of NPN Bipolar Transistors with Silicon Nitride Passivation,” IEEE Transactions on Nuclear Science, Vol. NS- 15, No. 6, pp. 168-175 (1968).

[6]

P. F. Schmidt and J. D. Ashner, “Radiation-Insensitive Silicon Oxynitride Films for Use in Silicon Devices,” IEEE Transactions on Nuclear Science, Vol. NS-17, No. 6, pp. 11-17 (1970).

[7]

R. Bauerlein, “Investigation of the Surface Ionization Effect on Planar Silicon Bipolar Transistors and the Improvement of the Resistance to Radiation by an IrradiationAnnealing Treatment,” IEEE Transactions on Nuclear Science, Vol. NS-17, No. 6, pp. 52-62 ( 1970).

[8]

L. L. Sivo, “Relative Roles of Charge Accumulation and Interface States in Surface Degradation (NPN Planar Transistors),” IEEE Transactions on Nuclear Science, Vol. NS19, No. 6, pp. 305-312 (1972).

[9]

L. L. Sivo, “Investigation of Radiation-Induced Interface States Utilizing Gated-Bipolar and MOS Structures,” IEEE Transactions on Nuclear Science, Vol. NS - 19, No. 6, pp. 313-319 (1972).

[10]

J. A. Lipman, W.C. Bruncke, D. L. Crosthwait, K. F. Galloway, and R. L. Pease, “Use of a Scanning Electron Microscope for Screening Bipolar Surface Effects,” IEEE Transactions on Nuclear Science, Vol. NS-21, No. 6, pp. 383-386(1974).

[11.

M. E. Daniel and F. N. Coppage, “Radiation Hardness of a High Speed ECL Microcircuit,” IEEE Transactions on Nuclear Science, Vol. NS-22, No. 6, pp. 2595-2599 (1975).

[12.

R. L. Pease, “Radiation Damage to Integrated Injection Logic Cells,” IEEE Transactions on Nuclear Science, Vol. NS-22, No. 6, pp. 2600-2604 (1975). III-69

,.

EEE, Vol. 16, No.

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J. P. Raymond, T. Y. Wong, and K. K. Schuegraf, “Radiation Effects on Bipolar Integrated Injection Logic,” IEEE Transactions on Nuclear Science, Vol. NS-22, No. 6, pp. 2605-2610 (1975).

[14]

W. E. Price and A. G. Stanley, “Hardening of MJS77 Spacecraft Against the Jupiter Radiation Belts,” IEEE Transactions on Nuclear Science, Vol. NS-22, No. 6, pp. 26692674 (1975).

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L. J. Palkuti, L. L. Sivo, R. B. Greegor, “Process Investigations of Total-Dose Hard, Type-108 Op Amps,” IEEE Transactions on Nuclear Science, Vol. NS-23, No. 6, pp. 1756-1761 (1976).

[16]

A. G. Stanley and W. E. Price, “Irradiate-Anneal Screening of Total Dose Effects in Semiconductor Devices, ” IEEE Transactions on Nuclear Science, Vol. NS-23, No. 6, pp. 2035-2040 ( 1976).

[17]

A. G. Stanley and M. K. Gauthier, “SEM Analysis of Ionizing Radiation Effects in Linear Integrated Circuits,” IEEE Transactions on Nuclear Science, Vol. NS-24, No. 6, pp. 2060-2065 (1977).

[18]

K. F. Galloway and P. Roitman, “Important Considerations for SEM Total Dose Testing,” IEEE Transactions on Nuclear Science, Vol. NS-24, No. 6, pp. 2066-2070 (1977).

[19]

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[20]

D, M. Newell and W. T. Picciano, “A Hard Off-the-Shelf SG1524 Pulse Width Modulator,” IEEE Transactions on Nuclear Science, Vol. NS-24, No. 6, pp. 2079-2083 (1977).

[21]

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[22]

R. P. Donovan, M. Simons, R. M. Gurger, “Radiation Hardened LSI for the 1980’s: CMOS/SOS vs. 12L,” IEEE Transactions on Nuclear Science, Vol. NS-24, No. 6, pp. 2336-2340 (1977).

,[23]

A. R, Hart, J. B. Smyth, Jr., V. A. J. vanLint, D. P. Snowden, and R. E. Leaden, “Hardness Assurance Considerations for Long-Term Ionizing Radiation Effects on Bipolar Structures,” IEEE Transactions on Nuclear Sciences, Vol. NS-25, No. 6, pp. 1502-1507 (1978).

[24]

A. H. Johnston and C. A. Lancaster, “A Total Dose Homogeneity Study of the 108A Operational Amplifier,” IEEE Transactions on Nuclear Sciences, Vol. NS-26, No. 6, pp. 4769-4774 (1979).

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M. K. Gauthier, J. Perret, and K. C. Evans, “SEM Analysis of Ionizing Radiation Effects in an Analog to Digital Converter (AD571 ),” IEEE Transactions on Nuclear Science, Vol. NS-28, No. 6, pp. 4051-4055 (1981),

[26]

V. Condito, N. Lambert, T. J. Schwartz, and S. Dodge, “The Effects of Nitride Passivation on the Total Dose Radiation Resistance of a Precision Operational Amplifier,” IEEE Transactions on Nuclear Science, Vol. NS-28, No. 6, pp. 4325-4327 (1981).

[27]

R. B. Johnson, R. R. Travis, B, W. Schupp, and M. H. Seavey, “Radiation Response of Integrated Schottky Logic Circuits,” IEEE Transactions on Nuclear Science, Vol. NS-28, No. 6, pp. 4060-4065 (1981).

[28]

R. D. Blice and J. H. Collins, “Analysis of the Behavior of Integrated Schottky Logic in Neutron, Total Dose, and Dose Rate Environments,” IEEE Transactions on Nuclear Science, Vol. NS-28, No. 6, pp. 4366-4375 (1981).

[29]

F. W. Poblenz, R. G. Carroll, D. A. Whitmire, B. W. Cheney, and D. L. Walthall, “Total Dose Response of STL and 12L Logic Devices,” JEEE Transactions on Nuclear Science, Vol. NS-29, No. 6, pp. 1727-1732 (1982).

[30]

J. P. Woods and J. V. MacPhee, “Total Dose Susceptibility of the SBP 9989 Microprocessor,” IEEE Transactions on Nuclear Science, Vol. NS-29, No. 6, pp. 17401743 (1982).

[31]

M. L. Buschbom, E. N. Jeffrey, L. E. Rhine, and D. B. Spratt, “Garnrna Total Dose Effects on ALS Bipolar Oxide Sidewall Isolated Devices,” IEEE Transactions on Nuclear Science, Vol. NS-30, No. 6, pp. 4105-4109 (1983).

[32]

R. L. Pease, R. M. Turfler, D. G. Platteter, D. W. Emily, and R. Blice, “Total Dose Effects in Recessed Oxide Digital Bipolar Microcircuits,” IEEE Transactions on Nuclear Science, Vol. NS-30, No. 6, pp. 4216-4223 (1983).

[33]

M, K. Gauthier and D. K. Nichols, “A Comparison of Radiation Damage in Linear IC’S from Cobalt-60 Gamma Rays and 2.2 MeV Electrons,” IEEE Transactions on Nuclear Science, Vol. NS-30, No. 60, pp. 4192-4196 (1983).

[34]

M. Kate, T. Nakamura, T. Toyabe, T. Okabe, and M. Nagata, “Degradation Analysis of Lateral PNP Transistors Exposed to X-Ray Irradiation,” IEEE Transactions on Nuclear Science, Vol. NS-31, No. 6, pp. 1513-1517 (1984).

[35]

R. L. Pease, D. W. Emily, and H. E. Boesch, Jr., “Total Dose Induced Hole Trapping and Interface State Generation in Bipolar Recessed Field Oxides,” IEEE Transactions on Nuclear Science, Vol. NS-32, No. 6, pp. 3946-3952 (1985).

III-7 1

. .

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A, H. Johnston and R. E. Plaag, “Models for Total Dose Degradation of Linear Integrated Circuits,” IEEE Transactions on Nuclear Science, Vol. NS-34, No. 6, pp. 1474-1480 (1987).

[37]

D. Schiff, “Prediction of Dose to Failure Versus Dose Rate for a Recessed Oxide Digital Bipolar Microcircuit,” IEEE Transactions on Nuclear Science, Vol. NS-34, No. 6, pp. 1742-1744 (1987).

[38]

R. H. Maurer and J. J. Suter, ‘Total-Dose Hardness Assurance for Low Earth Orbit,” IEEE Transactions on Nuclear Science, Vol. NS-34, No. 6, pp. 1757-1762 (1987).

[39]

J. L. Titus and D. G. Platteter, “Wafer Mapping of Total Dose Failure Thresholds in a Bipolar Recessed Field Oxide Technology,” IEEE Transactions on Nuclear Science, Vol. NS-34, No. 6, pp. 1751-1756 (1987).

[40]

D. G. Platteter and T. F. Cheek, Jr., ‘“The Use of Multiple Oxygen Implants for Fabrication of Bipolar Silicon-on-Insulator Integrated Circuits,” IEEE Transactions on Nuclear Science, Vol. NS-35, No. 6, pp. 1350-1354 (1988).

[41]

J. A. Zoutendyk, C. A. Goben, and D. F. Berndt, “Comparison of the Degradation Effects of Heavy Ion, Electron, and Cobalt-60 Irradiation in an Advanced Bipolar Process,” IEEE Transactions on Nuclear Science, Vol. NS-35, No. 6, pp. 1428-1431 (1988).

[42]

E. W. Enlow, R. L. Pease, W. E. Combs, amd D. G. Platteter, “Total Dose Induced Hole Trapping in Trench Oxides,” IEEE Transactions on Nuclear Science, Vol. NS-36, No. 6, pp. 2415-2422 (1989).

[43]

J. C. Desko, Jr., J. N. Darwish, M. C. Dolly, C. A. Goodwin, W. R. Dawes, Jr., and J. L. Titus, “Radiation Hardening of a High Voltage IC Technology (BCDMOS),” IEEE Transactions on Nuclear Science, Vol. NS-37, No. 6, pp. 2083-2088 (1990).

[44]

E. W. Enlow, R. L. Pease, W. E. Combs, R. D. Schrimpf, and R, N. Nowlin, “Response of Advanced Bipolar Process to Ionizing Radiation,” IEEE Transactions on Nuclear Science, Vol. NS-38, No. 6, pp. 1342-1351 (1991).

[45]

D. M. Fleetwood, P. S. Winokur, and T. L. Meisenheimer, “Hardness Assurance for LowDose Space Applications,” IEEE Transactions on Nuclear Science, Vol. NS-38, No. 6, pp. 1552-1559 (1991).

[46]

R.N. Nowlin, E. W. Enlow, R. D. Schrimpf, and W. E. Combs, “Trends in the TotalDose Response of Modem Bipolar Transistors,” IEEE Transactions on Nuclear Science, VO1.NS-39, No. 6, pp. 2026-2035 (1992).

[47]

S. L. Kosier, R. D. Schrimpf, R. N. Nowlin, D. M. Fleetwood, M. DeLaus, R. L. Pease, W. E. Combs, A. Wei, and F. Chai, “Charge Separation for Bipolar Transistors,” IEEE Transactions on Nuclear Science, Vol. NS40, No. 6, pp. 1276-1285 (1993).

111-72

[48]

R.N. Nowlin, D. M. Fleetwood,-R. D. Schrimpf, R. L. Pease, and W. E. Combs, “Hardness-Assurance and Testing Issues for Bipolar/BiCMOS Devices,” IEEE Transactions on Nuclear Science, Vol. NS-40, No. 6, pp. 1686-1693 (1993).

[49]

M. DeLaus, D. Emily, B. Mappes, and R. Pease, “Converting a Bulk Radiation-Hardened BiCMOS Technology into a Dielectrically Isolated Process,” IEEE Transactions on Nuclear Science, Vol. NS-40, No. 6, pp. 1774-1779 (1993).

[50]

S. L. Kosier, W. E. Combs, A. Wei, R. D. Schrimpf, D. M. FleetWood, M. DeLaus, and R. L. Pease, “Bounding the Total-Dose Response of Modern Bipolar Transistors,” IEEE Transactions on Nuclear Science, Vol. NS-41, No. 6, pp. 1864-1870 (1994).

[51]

D. M. Fleetwood, S. L. Kosier, R. N. Nowlin, R. D. Schrimpf, R. A. Reber, Jr,, M. DeLaus, P. S. Winokur, A. Wei, W. E. Combs, and R. L. Pease, “Physical Mechanisms Contributing to Enhanced Bipolar Gain Degradation at Low Dose Rates,” IEEE Transactions on Nuclear Science, NS41, No. 6, pp. 1871-1883 (1994).

[52]

S. C. WitcX S. L. Kosier, R. D. Schrimpf, and K. F, Galloway, “Synergetic Effects on Radiation Stress and Hot-Carrier Stress on the Current Gain of NPN Bipolar Junction Transistors,” IEEE Transactions on Nuclear Science, Vol. NS-41, No. 6, pp. 2412-2419 (1994).

[53]

R.N. Nowlin, D. M. Fleetwood, and R. D. Schrimpf, “Saturation of the Dose-Rate Response of Bipolar Transistors Below 10 Rad(Si02)/s: Implications for Hardness Assurance,” IEEE Transactions on Nuclear Science, Vol. NS-41, No. 6, pp. 2637-2641 (1994).

[54]

A. H. Johnston, G. M. Swift, and B. G. Rax, “Total Dose Effects in Conventional Bipolar Transistors and Linear Integrated Circuits,” IEEE Transactions on Nuclear Science, Vol. NS-41, No. 6, pp. 2427-2436 (1994).

[55]

J. Beaucour, T. Carriere, A. Gach, D. Laxague, and P. Poirot, “Total Dose Effects on Negative Voltage Regulator,” IEEE Transactions on Nuclear Science, Vol. NS-41, No. 6, pp. 2420-2426 ( 1994).

[56]

S. McClure, R. Pease, W. Will, and G. Peny, “Dependence of Total Dose Response of Bipolar Linear Microcircuits on Applied Dose Rate:’ IEEE Transactions on Nuclear

Science, Vol. NS41, No. 6., pp. 2544-2549 (1994). [57]

C. I. Lee, B, G. Rax, and A. H. Johnston, “Total Ionizing Dose Effects on High Resolution ( 12-/l4-bit) Analog-to-DigitaI Converted,” IEEE Transactions on Nuclear Science, Vol. NS-41, No. 6, pp. 2459-2466(1994).

[58]

D. M. Schmidt, D. M. Fleetwood, R. D. Schrimpf, R. L. Pease, R. J. Graves, G. H. Johnson, K. F. Galloway, and W. E. Combs, “Comparison of Ionizing-Radiation-Induced Gain Degradation in Lateral, Substrate, and Vertical PNP BJTs,” IEEE Transactions on Nuclear Science, Vol. NS-42, No. 6, pp. 1541-1549 (1995).

III-73

[59]

R. D. Schrimpf, R. J. Graves, D. M. Schmidt, D. M. FleetWood, R. L. Pease, W. E. Combs, and M. DeLaus, “Hardness-Assurance Issues for Lateral PNP Bipolar Junction Transistors,” IEEE Transactions on Nuclear Science, Vol. NS-42, No. 6, pp. 1641-1649 (1995).

[60]

V. V. Belyakov, V. S. Pershenkov, A. V. Shalnov, and I. N. Shvetzov-Shilovsky, “Use of MOS Structures for the Investigation of Low-Dose-Rate Effects in Bipolar Transistors,” IEEE Transactions on Nuclear Science, Vol. NS-42, No. 6, pp. 1660-1666 (1995).

[61]

S. C. Witczak, K. F. Galloway, R. D. Schrimpf, and J. S. Suehle, “Relaxation of Si-Si02 Interracial Stress in Bipolar Screen Oxides Due to Ionizing Radiation,” IEEE Transactions on Nuclear Science, Vol. NS-42, No. 6, pp. 1689-1697 (1995).

[62]

A. H. Johnston, B. G. Rax, and C. I. Lee, “Enhanced Damage in Linear Bipolar Integrated Circuits at Low Dose Rate,” IEEE Transactions on Nuclear Science, Vol. NS-42, No. 6, pp. 1650-1659 (1995).

[63]

T. Carriere, J. Beaucour, A. Gach, B. Johlander, and L. Adams, “Dose Rate and Annealing Effects on Total Dose Response of MOS and Bipolar Circuits,” IEEE Transactions on Nuclear Science, Vol. NS-42, No. 6, pp. 1567-1574 (1995).

[64]

C. I. Lee, B. G. Rax, and A. H. Johnston, “Hardness Assurance and Testing Techniques for High Resolution (12- to 16-bit) Analog-to-Digital Converters,” IEEE Transactions on Nuclear Science, Vol. NS-42, No. 6, pp. 1681-1688 (1995).

[65]

J. L. Titus, M. A. Gehlhausen, J. C. Desko, Jr., T. T. Nguyen, M. A. Shibib, K. E. Hollenbach, and D. J. Roberts, “Characterization of a Fully Resonant, l-MHz, 25-Watt, DC/DC Converter Fabricated in a Rad-Hard BiCMOS/High-Voltage Process,” IEEE Transactions on Nuclear Science, Vol. NS-42, No. 6, pp. 2143-2149 (1995).

[66]

J. A. Babcock, J. D. Cressler, L. S. Vempati, S. D. Clark, R. C. Jaeger, and D. L. Hararne, “Ionizing Radiation Tolerance of High-Performance SiGe HBT’s Grown by UHV/CVD,” IEEE Transactions on Nuclear Science, Vol. NS-42, No. 6, pp. 1558-1566 (1995).

[67]

M. DeLaus, “Radiation Concerns in State-of-the-Art Processing Technologies,” Nuclear and Space Radiation Effects Conference Short Course, p. HI-18 (1994).

[68]

P. Cole, D. Emily, W. Combs, M. Gehlhausen, R. Pease, “Post-Irradiation Degradation of Input Bias Current on Commercial Linear Circuits”, submitted to 1996 IEEE Nuclear and Space Radiation Effects Conference.

[69]

M. DeLaus, W. Combs “ Total-Dose and SEU Results for the AD8001, a Higha Dielectrically-Isolated, Fabricated in Performance Commercial Op-amp Complementary-Bipolar Process,” IEEE Radiation Effects Data Workshop, p. 104-109 (1994)

111-74

IEEE

[70]

[71]

S. L. Kosier, “Modeling Gain Degradation in Bipolar Junction Transistors Due to Ionizing Radiation and Hot-Carrier Stressing,” Doctorate Thesis, University of Arizona, (1994). P. S. Winokur, J. M. McGarrity, H. E. Boesch, Jr., “Dependence of Interface-State Buildup on Hole-Generation and Transport in Irradiated MOS Capacitors,” IEEE Transactions on Nuclear Science, Vol. NS-23, No. 6, pp. 1580-1585 (1976).

[72]

F. B. McLean, H. E. Boesch, Jr., J. M. McGarrity, “Hole Transport and Recovery Characteristics of SiOz Gate ksulators,” IEEE Transaction on Nuclear Science, Vol. NS23, No. 6, pp. 1506-1512 (1976).

[73]

H.E. Boesch, Jr., “Interface-State Generation in Thick SiOz Layers,” IEEE Transactions on Nuclear Science, Vol. NS-29, pp. 1446-1451 (1982).

[74]

H.E. Boesch, Jr., T. L. Taylor, “Charge Interface State Generation in Field Oxides,” IEEE Transactions on Nuclear Science, Vol. NS-3 13, No. 6, pp. 1273-1279 (1984).

[75]

R. Fuller and W. Newman, “Development of a Radiation Hardened NPN Bipolar Transistor for a (54K CMOS Fusible-link PROM,” IEEE Transactions on Nuclear Science, Vol. NS-41, No. 6, pp. 2474-2480 (1994).

III-75

III-76

,,

.. . .

APPENDIX A ADDITIONAL

PAPERS ON RADIATION

EFFECTS IN BIPOLAR DEVICES

1. W. Poch and A. G. Holmes-Siedle, “A Prediction and Selection System for Radiation Effects in Planar Transistors,” IEEE Transactions on Nuclear Science, Vol. NS- 15, No. 6, pp. 213223 (1968). 2. C. A. Goben and C. H. Irani, “Electric Field Strength Dependence of Surface Damage in Oxide Passivated Silicon Planar Transistors,” IEEE Transactions on Nuclear Science, Vol. NS-17, No. 6, pp. 18-26 (1970). 3. F. N. Coppage and E. D. Graham, Jr., “Device Degradation from the Effects of Nuclear Radiation on Passivation Materials,” IEEE Transactions on Nuclear Science, Vol. NS- 19, No. 6, pp. 320-324 (1972). 4. R. A. Berger and J. L. Azarewicz, “Packaging Effects on Transistor Radiation Response,” IEEE Transactions on Nuclear Science, Vol. NS-22, No. 6, pp. 2568-2572 (1975). lK-Bit 5. T. J. Sanders, J. W. Boarman, G. M. Wood, and A. J. Kasten, “A Radiation-Hardened Dielectrically Isolated Random Access Memory,” IEEE Transactions on Nuclear Science, Vol. NS-29, No. 6, pp. 1733-1736 (1982). 6. G. M. Wood , T. J. Sanders, and R. H. Casey, “A Radiation-Hardened Gate Array Family Using an Advanced DI Bipolar Technology,” IEEE Transactions on Nuclear Science, Vol. NS-30, No. 6, pp. 4187-4191 (1983). 7. D. Schiff, J. Bruun, M. Montesalvo, and C..-C. D. Wong, “A Comparison of Conventional Dose Rate and Low Dose Rate CO-60 Testing of IDT Static Rams and FSC MultiplexerS,” IEEE Transactions on Nuclear Science, Vol. NS-32, No. 6, pp. 4050-4055 (1985). 8. S. H. Stewart, A. Polman, K. E. Monson, N. vanVonno, S. J, Gaul, D. A. Woodbury, R. B. Rose, V. Strahan, and T. Stell, “A Radiation Hardened Linear Macrocell Array,” IEEE Transactions on Nuclear Science, Vol. NS-33, No. 6, pp. 1706-1709 (1986). 9. W. C. Jenkins, “Dose-Rate-Independent Total Dose Failure in 54F1O Bipolar Logic Circuits,” IEEE Transactions on Nuclear Science, Vol. NS-39, No. 6, pp. 1899-1902 (1992). 10, M. Dentan, E. Delagnes, N. Fourches, M. Rouger, MC. Habrard, L. Blanquart, P. Delpierre, R. Potheau, R. Truche, JP. Blank, E. Delevoye, J. Gautier, JL. Pelloie, J. dePontchma, O. Flarnent, JL. Leray, JL. Martin, J. Montaron, and O. Musseau, “Study of a CMOS-JFETBipolar Radiation Hard Analog-Digital Technology Suitable for High Energy Physics Electronics,” IEEE Transactions on Nuclear Science, Vol. NS40, No. 6, pp. 1555-1560 (1993).

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1996 NSREC SHORT COURSE

SECTIONIV

CATASTROPHIC SINGLE-EVEN?’ EFFECTS IN THE NATVRAL SPACE ENVIRONMENT

Kenneth F. Gallovvay and Gregory H. Johnson The University of Arizona

Catastrophic

Single-Event

Effects in the Natural

Space Radiation Environment

Gregory H. Johnson and Kenneth F. Galloway Department of Electrical and Computer Engineering The University of Arizona Tucson, AZ 85721

The views expressed in this article are those of the authors and do not reflect the official policy or position of the Department of Defense or the U.S. Governnlent. This work was supported by the Defense Nuclear Agency.

IV–1

,.

Catastrophic Single-Event Effects in the Natural Space Radiation Environment Gregory H. Johnson and Kenneth F. Galloway Department of Electrical and Computer Engineering The University of Arizona Thcson, AZ 85721

Table of Contents 1.

IPJTIIODUaON

........................................................................................... ..................... ................ ..... ...........

4

1,1. Catamophic Single-EventEffects .................................................................................................... 4

2.

1.2.

Energetic Particles in the Space Radiation Environment ................................................................. 5

1.3.

Interaction of Energetic Particles and Device Materials .................................................................. 7

1.4.

SingleiEvent Measurements and hdysis

SINGU?-EVENTBURNOW m Pon 2.1.

2.2.

2.3. 3.

................................................................................................. 11

Experimental Status ........................................................................................................................ 13 2.1.1.

Testing Twtiques

.......................................................................................................... 13

2.1.2.

~pical SEE Data ........................................................................................................... 15

Physical Modeling .......................................................................................................................... 18 2.2.1.

Current InduAAvdack

............................................................................................. 18

2.2.2.

Hn.Btiy

2.2.3.

Semi-Analytical Model ................................................................................................... 21

2.2.4.

2-D Numerical Simulation - MEDICI .......i.................................................................... 25

2.2.5.

2-D Numerical Simulation - EPICS ............................................................................... 33

Avdmche .................................................................................................... 20

Reducing SEB Susceptibility .......................................................................................................... 35

SINGLE-EVRW GATERUFTURE m Powtm MOSFETS .................................................................................... 36 3.1.

3.2.

3.3. 4.

Dm=

Ex@nmental Status ...........................i............................................................................................ 36 3.1.1.

Testing Twhtiqufi .......................................................................................................... 37

3.1.2.

SEGRDab ...................................................................................................................... 3’7

Physical Modeling .......................................................................................................................... 40 3.2.1

Analytical Charge Sheet Model .....................................................................................#40

3.2,2

2-D Numerical Simulation Model .................................................................................. 40

Reducing SEGR Susceptibility ....................................................................................................... 42

c FAILURE JNCMOS ............................................................................................. 44 SJNGIJ+EWNT DrRLHTRI

4.1.

Experimental Status ........................................................................................................................ 44 4.1.1.

Micro-Dose Failures ....................................................................................................... 44

4.1.2.

Micro-Damage or SEDR Failures .................................................................................. 46

Iv-2

.. .

—.

........................................................................................ 7

-----

..

... .

.—-----

----

4.2.

4.3. 5.

Physical Modeling .......................................................................................................................... 49 4.2.1

Micro-Dose Modeling .................................................................................................... 49

4.2.2

Micro-Damage Modeling ............................................................................................... 50

Reducing Single-Event Dielectric Failure Susceptibility ............................................................... 51

SUNGLE-EVENT LATCHUP . . . . . . . . . . . .. . . . . . . . . . . . .. .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . .......

5.1.

5.2.

5.3.

52

Experimental Status ........................................................................................................................ 53 5.1.1.

Testing Methods .............................................................................................................. 53

5.1.2.

Typical Data .................................................................................................................... 53

Physical Modeling .......................................................................................................................... 55 5.2.1

Two-Transistor Model for Latchup ................................................................................. 56

5.2.2.

Charge Collection ........................................................................................................... 58

5.2.3.

Triggering SEL ............................................................................................................... 61

5.2.4.

Temperature Dependence of SEL ................................................................................... 61

5.2.5.

Holding Current and Voltage .......................................................................................... 62

Reducing SEL Susceptibility .......................................................................................................... 63

6.

SUMMARY AND CONCLUSIONS . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . 64

7.

ACWOWLEffiMWS

8.

REFERENCES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .........................

. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............

IV–3

,.

64 65

1.

INTRODUCTION

Energetic particles are ubiquitous in the natural space radiation environment.

When energetic

particles pass through sensitive regions of certain electronic devices, catastrophic failures can occur. This Short Course will give examples of catastrophic discrete transistors and integrated circuits.

failures that have been observed in

This section introduces the catastrophic

single-event

effects to be discussed and provides some background material on the space radiation environment and single-event phenomena. 1.1.

Catastrophic Single-event

Single-Event

Effects

burnout (SEB) and single-event

semiconductor-field-effect

transistors

gate rupture (SEGR), of power metal-oxide-

(MOSFETS) are catastrophic

failure mechanisms

initiated by the passage of a heavy ion through sensitive regions of the device structure.

that are Power

bipolar junction transistors (BJTs) are susceptible to SEB as well. SEB of power MOSFETS was first reported by Waskiewicz, et. al. [1], SEB of power BJTs was first reported by Titus, et. al. [2], and SEGR of power MOSFETS was first reported by Fischer [3, 4]. Reduction of the minimum feature size in complimentary metal-oxide-semiconductor circuits has increased the sensitivity of CMOS technologies

to catastrophic

single-event

(CMOS) latchup

(SEL) and single-event dielectric failure. SEL was first reported in ground tests by Kolasinski, et. al..

[5]. It was shown that energetic heavy particles in space and the upper atmosphere of the earth

were capable of triggering SEL. Corroborating results have been reported by [6-9]. In addition, protons have been shown to trigger SEL in highly sensitive devices [10], and Adams et. al. [1 1] have reported proton SEL in operational satellites.

SEL in space systems has recently been re-

viewed by Johnston [12]. Two different mechanisms for single-event dielectric failure have been observed and discussed in the literature.

In 1993, Oldham, et al., reported single-event dielectric

failure due to micro-dose [13]. Swift, et al., describe a new class of single-event hard errors which have referred to as single-event dielectric rupture in 1994 [14]. SEB of power transistors, SEGR of power MOSFETS, single-event dielectric failure, and SEL, all catastrophic single-event effects, are discussed in this Short Course. For each of these effects: (1) the status of experimental data and laboratory testing methods are presented; (2) physical models for the failure mechanism are presented; and (3) possible methods for reducing device vulnerability to the particular failure mechanism are presented.

IV-4

-,,

,.,

..c#—+&l

MAGNETIC FIELD LINE .

Figure 1.1. Magnetic field lines of the earth and trapped particlejlow

J

afier [16].

1.2. Energetic Particles in the Space Radiation Environment The natural space radiation environment contains high-energy photons, protons, and electrons that can cause total-dose ionizing radiation damage. It contains high-energy protons, neutrons, and heavy ions that can cause displacement

damage.

It also contains high-energy protons and heavy

ions that can introduce transient, dense charge filaments along the path of the ion through an electronic device that can interact with sensitive regions of the device to trigger catastrophic

failure

mechanisms. The concentrations

and types of ions vary significantly with altitude and inclination of angle

of an orbit, recent solar activity, and the amount of protective shielding. difficult to quantify one particular typical space environment.

Careful consideration of the particu-

lar flight path must be taken for reliable mission life estimation. radiation environment

These variations make it

Most particles found in the space

of the earth can be classified two ways: (1) trapped particles in the mag-

netic field of the earth - primarily protons and electrons; and (2) cosmic rays - heavy ions or protons of solar or galactic origin [15-17]. The magnetic field of the earth creates a geomagnetic cavity called the magnetosphere.

The

magnetic field lines trap low-energetic charged particles and govern their motion as illustrated in Figure 1.1. The distribution of proton flux as a function of energy and radial distance from the earth is shown in Figure 1.2. Trapped protons with energies as high as 500 MeV have been reported [1617]. Cosmic rays are high-energy heavy ions that originate from either the sun (solar cosmic rays) or from outside our solar system (galactic cosmic rays). The flux of solar cosmic rays depends on the amount of solar activity (i.e., solar flares). In Figure 1.3, a plot of the angular flux of cosmic ray particles (solar and galactic) during solar minimum and solar maximum for a geosynchronous IV–5

.,

,!

orbit

1

2

3

s

6

7

Earth4Radii Figure 1.2. The distribution of pmtonflu

10-3

as afinction

1 @2

of enetgy and radial distance fmm the earth afier [16].

I&l

100

1(J$

102

LET (MeV/mg/cm2) Figure 1.3. The angularflux of cosmic ray particles (solar and galactic) during solar minimum, solar maximum, and the Adam k 107o worst-case environment for a particular geosynchronous orbit a~er [18].

IV–6

is shown. Also shown in Figure 1.3 is the Adam’s 10% worst case environment that the actual space environment

[18]. This means

is worse only 10% of the time. The flux distributions

in Figure

1.3 are plotted against the linear energy transfer (LET) of the incident energetic particle. The LET of an ion quantifies the amount of energy deposited along the ion track.

The units of LET are

typically given by MeV-cmQ/mg [19]. 1.3. Interaction of Energetic Particles and Device Materials The various models for catastrophic single-event effects (SEE) that will be presented later in this part of the 1996 NSREC Short Course all have a common starting point, in that they use an energetic particle generated current filament or a energetic particle generated charge distribution. Physically based, detailed studies of charge generation and redistribution have been performed [20-24].

following an ion strike

The SEE models that have been developed to date begin with an

initial charge distribution or a current source positioned along the ion track. This works quite well for identifying and/or modifying the device parameters and bias conditions integral to the mechanisms for catastrophic

SEE. Relative failure levels between devices with different parameters or

bias conditions can be compared in the models, but absolute ion energies or LETs (linear energy transfer) are not always obtainable from the models (particularly the analytical models). The details relating the LET of an incident ion to a resulting charge distribution are not always provided in the various models seen in the literature.

A simple first-order analysis that is used

(either implicitly or explicitly) in many Qf the models follows. To first order, the LET is multiplied by the mass density of the target material to obtain the energy deposited per unit track length (typical units of MeV/~m).

It takes 3.6 eV to create one electron hole pair (ehp) in silicon [19], so

the energy deposited per unit track length is divided by 3.6 eV to obtain the number of ehps per track length (units of carriers/pm).

In order to obtain a quantity having units more applicable

to

device operation (e.g., cm-3), the number of ehps per track length is divided by an assumed value of the initial cross-sectional particle-induced

area of the charge filament.

Many of the subtle details of energetic

charge generation can be lost in this analysis, but this provides an elementary

starting point for understanding 1.4. Single-Event

the details of the mechanisms for catastrophic SEE is gained.

Measurements

and Analysis

The effects heavy ions on semiconductor

devices operated in the space environment

are ex-

perimentally material.

simulated using techniques that generate a dense plasma of free carriers in the target Particle accelerators, alpha-emitting radioactive isotopes (e.g., zAIAm and 208P1), and

naturally fissioning radioisotopes for single-event measurements.

(e.g., 252Cf) provide controlled sources of high energy particles

A brief discussion of single-event measurement techniques is given IV–7

10-4

10-5

-

Ide \

r --1

+

1 II II I

10-6 10-7

--------

‘sat

I I

-

10-8 10-9

1

0

25

50

100

75

125

LET [MeV-cmz/mg] Figure 1.4. A typical measured and ideal cross-section curve. The saturated cross-section LET of the incident ion.

is plotted against the

in this section. During the course of this discussion, some of the nomenclature particular to singleevent effects is described. Conference,

Over the past few years of the Nuclear and Space Radiation Effects

there have been some excellent Short Courses covering various aspects of single-

event phenomena

[25-29]. This material provides excellent reviews and collateral reading.

The sensitivity of a semiconductor

device to single-event phenomena is expressed as the ratio

of the number of events to the total particle fluence.

This results in units of [number of events]

divided by the [number of particles / cmz]. The resulting ratio is referred to as the error crosssection since it has units of cmz (the number of events and particles cancel).

Laboratory cross-

section data is often presented as a ftmction of the linear energy transfer (LET) of the incident ion - for particles striking normal to the surface. There are two key parameters from such data: the saturation

cross-section,

cr~at, and the threshold

LET, &h. The saturation

cross-section

is related to

the total area of the sensitive regions of the component, and the threshold LET is a measure of the critical, or minimum, charge required tu trigger the event. These parameters are essential in estimating the single-event saturation cross-section

error rate for a particular environment. and threshold LET are illustrated.

In Figure 1.4, the concepts of

Atypical measured cross-section

curve

is shown along with the ideal cross-section curve in Figure 1.4. The ideal curve is a step-function (i.e., all circuit elements have exactly equal thresholds), while the measured cross-section has a gradual threshold and asymptotically

approaches saturation.

IV-8

curve

Beam Diagnostics (scintillators, surface Q
-~

~; \ 0 ~~ ~@ ,/’ \\ \’\v/’ Gate Valves

Test Chamber

\\ \ \ \\

\\ Device Board \\ Beam Shutter

“\

View Pent

Figure 1.5.

Rough schematic of experimental test set-up for single-event phenomena afier [26].

An experimental

set-up for single-event phenomena testing requires a high-energy heavy-ion

source (including diagnostic tools for ion beam analysis), a test chamber, and the devices to be tested (including any apparatus required to maintain biases and desired stressing conditions).

A

rough sketch of an experimental set-up for single-event phenomena is shown in Figure 1.5, where the accelerator, beam diagnostics, and test chamber are noted. The test chamber must provide the following:

(1) a means of positioning the device under test (DUT) in front of the ion beam; (2) a

means of accurately adjusting the angle of incidence of the ion beam; and (3) a means of bringing electrical signals to the DUT from a tester located outside of the testing chamber.

Since ions

provided by accelerator facilities are attenuated by packaging material and air, devices are delidded prior to testing, and the testing chamber is evacuated to a vacuum of about 10-6 torr. To provide some idea of the species and energies available for single-event testing, Table 1.1 lists typical ions used for single-event testing at the Brookhaven National Laboratories tandem van de Graaff Accelerator.

IV-9

,.

Ion

c F Si cl Ni Br Ag I Au

AMU

12 19 28 35 58 79 107 127 197

Max Energy

LET

Range

[MeV]

[MeV-cm2/mg]

[pm]

105 150 195 210 255 285 300 230 345

1.39 302 7.7 11.5 27 37.3 53.1 59.9 82.3

202 133 81 63.1 40.3 36.4 30.9 30.7 27.9

Table I. 1. Typical ions used for single-event testing at the Brookhuven National .Laboratones tandem van de GraaffAccelerator after [26].

IV -10

2.

SINGLE-EVENTBURNOUTIN POWERDEVICES

The double-diffused

metal oxide semiconductor

(DMOS) power transistor and the power bi-

polar junction transistor (BJT) are vulnerable to single-event burnout (SEB). pable of conducting large currents when turned ON and withstanding OFF. The cross-section

Each device is ca-

large voltages when turned

of an n-channel DMOS power transistor showing typical device dimen-

sions appears in Figure 2.1. This device is termed double-diffimed because both the source and the body are diffused using the polysilicon gate as a mask. The channel length is determined by the difference in diffusion rates of the dopants, rather than by photolithography

limitations [30].

Contact to the drain is made on the bottom surface of the silicon chip, rather than on the top surface as in a lateral MOSFET. The rather thick epitaxial drain region is required to drop the large drain to source voltages that the power transistor must block while operating in the OFT state. Typically, thousands of cells are connected in parallel to effectively create a very wide channel (while retaining the channel length of the individual cell) to achieve the large currents

required in

the ON state. This is illustrated in Figure 2.1. When turned ON, the channel forms and current flows as shown in Figure 2.2. Note the parasitic npn BJT inherent to the DMOS structure. This is shown in Figure 2.3. The source, body, and drain regions of the MOSFET comprise the emitter, base, and collector regions of the parasitic BJT, respectively.

During normal operation of the power MOSFET, this parasitic BJT

is always turned off due to the common source-body metallization that shorts out the base-emitter junction . The power BJT device structure is shown in Figure 2.4. Note the similarities between the vertical structure of the power BJT in Figure 2.4 and the parasitic BJT of the power MOSFET in

Figure 2.1. The cross-section

of an n-chunnel Dh40S power transistor

N-11

Figure 2.2. Currentflow

in an n-channel DMOS power transisto~

Figure 2.3. Parasitic BJT inherent to power DMOS device structure.

Figure 2.3. It is this similarity in device structure that makes both device types vulnerable to SEB. SEB is triggered when a heavy ion passes through a power MOSFET or power BJT biased in the OIW state (blocking a high drain-source voltage).

Transient currents generated by the heavy

ion turn on the parasitic BJT of the power MOSFET (or active device in power BJT).

Due to a

regenerative feedback mechanism, collector currents in the BJT increase to the point where second breakdown

sets in, creating a permanent

MOSFET or BJT useless. generated

hole current

A key component

in the collector

not been reported in the literature.

short between the source and drain and rendering the of the regenerative

feedback

mechanism

is avalanche-

region of the BJT. SEB of p-channel power MOSFETS has

While p-channel power MOSFETS may be susceptible to SEB,

it is less probable than for n-channel devices because the impact ionization rate for holes is much less than that for electrons, making the magnitude of avalanche-generated

currents lower in p-

channel devices than for n-channel devices [31 ]. SEB of p-channel power MOSFETS will not be discussed further in this paper.

IV – 12

Base

Numerous

Emitter

Base

research groups have reported experimental

results on SEB.

This section will

briefly review testing techniques and present some typical data. Titus and Wheatley have recently published an overview paper on this topic [32]. 2.1.1.

Testing

Techniques

The purpose of this section is not to prepare the reader to perform SEB measurements instead, to provide insight into the motivation behind the various modeling techniques. plete experimental

but,

More com-

procedures are given in [32-39]. SEB experiments are inherently expensive to

perform because they require the use of a reliable mono-energetic beam of heavy ions (e.g., tandem Van de Graaff accelerator or cyclotron facility), and often require a large number of devices due to the catastrophic

nature of the failure mechanisms.

During irradiation, the power MOSFETS are

biased in the OF’F state with a large drain-source bias applied. Atypical experimental test set-up is shown in Figure 2.5. In SEB measurements,

the gate and source are typically shorted together, and

the drain is biased to the desired level. The drain-source current is monitored during irradiation. The devices are exposed until a pre-specified ion fluence is obtained. If SEB has not occurred after the specified ion fluence, the bias conditions are increased and another exposure is performed. Using this method, one can obtain data relating bias conditions and ion energy necessary for SEB to occur. For power BJT’s, SEB measurements

are very similar to those for power MOSFETS [2].

The base and emitter terminals are grounded, and the collector is biased to the desired level. If SEB does not occur, then the collector bias is increased for the next exposure.

IV– 13

Figure 2.5. A typical SEB experimental test set-up.

Non-destructive

techniques are sometimes used in SEB measurements

(this significantly

re-

duces the number of devices needed for an adequate sample size) [38]. A resistor is inserted between the drain and the power supply that limits the maximum drain-source current and prevents the high current levels that trigger second breakdown of the parasitic BJT. A counter is used to track the number of current pulses. The sensitive cross-section of the device is obtained by dividing the number of pulses by the total ion fluence.

SEB cross-section

versus ion energy or drain-

source bias can be obtained with this method. Non-destructive

tests at high current levels (i.e., small limiting resistor) are possible if a sup-

ply cut-off system is added [39-40].

It was observed that the current shapes may vary without

changing the experimental conditions. An example is presented in Figure 2.6. For some events, the current can spontaneously position.

vanish.

It was argued that the effect of the ion depends on its impact

The effect of the impact location was further demonstrated

by isolating one cell with a

drilled mask [41]. The techniques described above monitor current levels and/or count current pulses. An alternate method has been introduced that instead measures the charge collected during a SEB event [42]. A pulse height analyzer and a charge sensitive amplifier are used in the Energetic Particle Induced Charge Spectroscopy

(EPICS) technique to measure collected charge.

ables a different experimental

picture of the mechanisms leading to SEB. The details of the SEB

mechanisms

revealed by EPICS are discussed later in the paper.

IV – 14

This method en-

‘~ 500

o

Time [ns] Figure 2.6. Examples of experimentally

2.1.2.

Typical

observed SEB current wavefomns.

SEB Data

Using nondestructive lows the experimentalist

test techniques to measure SEB cross sections on the same device alto investigate numerous operating parameters such as the angle of the

incident ion and temperature dependence. tional SEB cross-section

Two types of SEB cross-sections

exist: (1) a conven-

can be determined by fixing the VDS and VGS and computing the cross-

section, ~SEB, for several values of LET, producing a curve of crs~~ versus LET, and (2) a nonconventional

SEB cross-section can be experimentally

determined by fixing VGS and finding CSEB

at a fixed LET for several values of VDS, producing a curve of OSEBversus VDS. In Figure 2.7, a typical CSEBversus VDSplot is shown for an IRF120 power MOSFET exposed to a mono-energetic [32]. In Figure 2.8, the aSEB versus VDS plot

copper ion beam with an LET of 30 MeV-cmz-mg-l

is shown for an IRF150 power MOSFET exposed to a mono-energetic angles of incidence (00 and 600) with an LET of 30 MeV-cm2-mg-l incidence of the ion beam is increased, the SEB susceptibility

copper ion beam at two

[32]. Note that as the angle of

decreases.

This is not the same

sec((l) dependence observed in other single-event studies (usually the LET of the incident ion is increased by a factor of sec(t3)). Other experimental studies on SEB have also shown a reduction in SEB susceptibility Experimental

with an increase in the angle of incidence of the ion beam [36, 43-44]. studies [37, 43-44] have shown that the susceptibility

increasing temperature.

to SEB decreases with

Figure 2.9 shows as,EB versus VDS data for an IRF150 power MOSFET at

different operating temperatures exposed to a copper ion beam with an LET of 30 MeV-cm2-mg-1 [43]. Experimental

studies have also shown that power MOSFETS operated in a static operating

mode are more vulnerable to SEB than those devices operated in a dynamic mode of operation [4546]. The CTSEB versus LET data with VDS = 70V for an IRF150 power MOSFET is shown in Figure IV-15

.!

,,

Copper (LET =30 MeV-cm2/mg)

10-1 .

10-2 IRF120 10-3 10-4 10-5 10-6 . 10-7 50

I

I

I

I

1

I

60

70

80

90

100

110

v’s

120

[v]

Figure 2.7. Typical ~~m versus V~~plot is shown for an IRF120 power MOSFET exposed to a mono-enetgetic copper ion beam with an LET of 30 Me V-cm2-mg-’ after [32].

-

100

%~

10-1 .

~ -

10-2 -

~ m +

10-3 -

6

10-5 -

g

10-6 -

Copper (LET =30 MeV-cm2/mg)

●

10-4 .

I

10-7

40

50

60

70

80

90

100

110

v~~ [v] Figure 2.8. Typical a~. versus V~~plot is shown for an IRF150 power MOSFET exposed to a mono-ene~etic copper ion beam at two angles of incidence (OOand 6P) with an LET of 30 Me V-cm2-mg-1 after [32].

IV – 16

100

tG-

~ E

Copper (LET =30 MeV-cr#/mg)

10-1 . 10-2 10-3 10-4 10-5 10-6 -

10-7 50

60

70

80

90

100

110

120

v~~ [v] Figure 2.9. Typical CJSmversus V~~data for an IRF150 power MOSFET at different operating temperatures exposed to a copper ion beam with an LET of 30 Me V-cm2-mg-’ after [32].

100

m-

E

●

lwl~E-

m

z ~

10-4 -

dynamic 5

n g

bias

10-5 vD~ = 70 v 10-6 10-7

20

I

I

I

I

I

I

I

30

40

50

60

70

80

90

LET [MeV-cm2/mg] Figure 2.10 The a~m versus LET data with V~~= 70Vfor an 1RF150 power MOSFET at both static and dynumic bias afier [32]. IV-17

,,

2.10 for both static and dynamic bias [45]. In Figure 2.15a, the SEB failure levels for several power BIT device types are shown [2]. The data indicate that the parasitic base resistance plays a key role in the SEB susceptibility.

Power

BJTs with the lowest base resistance required the highest collector-emitter bias for SEB. This is consistent with power MOSFET SEB, where devices with larger p+ plug regions (e.g., lower base

resistance in the parasitic BJT) are less vulnerable to SEB. The effects of the base resistance on SEB sensitivity will be investigated in more detail in the next section on modeling SEB. 22

Physical Modeling

SEB is triggered when a heavy ion passes through a power MOSFET or power BJT biased in the OIW state (blocking a high drain-source voltage). Transient currents generated by the heavy ion turn on the parasitic BJT of the power MOSFET (or active device in power BJT). Due to a regenerative feedback mechanisn collector currents in the BJT increase to the point where second breakdown sets in, creating a perrnunent short between the source and drain and rendering the MOSFET useless. The first attempt to model the physical mechanisms leading to SEB is attributed to Hobl and Galloway [47]. This work helped to motivak the later modeling effo~

that are pre-

sented here. In the context of this paper, the terms analytical and simulation areused to distinguish between the relative level of complexity between two classes of SEB modeling techniques:

(1) 1-

D and quasi- l-D models that make use of the ‘standard’ equations governing transistor operation are classified in this paper as analytical models; and (2) 2-D models that make use of device simulation

tools we classified in this paper as simulation models.

This section is devoted to

discussion of key analytical and numerical simulation models for SEB. A comprehensive of modeling single~vent 2.2.1.

a

review

effects in power MOS devices has recently appeared [48].

Current Induced Avalanche On the surface, the early SEB modeling efforts may seem crude compared to the more elabo-

rate simulation models in use today. However, their importance in helping to establish the SEB failure mechanism and in paving the way for more complex methods can not be overlooked. modeling techniques are discussed in this section:

‘IWO

(1) a simple 1-D current-induced avalanche

(CIA) model, and (2) a more complex distributed 1-D model. The model presented by Wrobel, et. aL, [49-51], is based on current induced avalanche (CIA) in the collector of the parasitic bipolar junction transistor (BJT). Figtm 2.11 shows the qualitative change in the electric field profiles for a one-sided abrupt junction with a reverse bias of Vc~

applied for increasing levels of meal current density,J[51 ]. The one-sided abrupt junction is used to model the base-collector junction of the parasitic BJT (the emitter region and then+ substrate are shown for illustrative purposes).

Note that as J is increased, the location of the maximum electric

IV-18

.

.

.

.

...

.

. .. . . . .

Figure2.11. The qualitativechangein the electricjiehipmjiks for a one-si&d abruptjunctwn with a reversebias of Vm appliedfor incnwsing levelsof aml currentdensity J afier [491.

field changes from the base-collector junction (Ml), to the n-n+ boundary in the collector region. This redistribution

of the electric field profiles is analogous to the base push-out phenomenon

in

BJTs. Because the applied voltage is the same for each value of J, the ama under each electric field profde is equal. As J is increased, the charge that determines the electric field profile includes not only the space charge of the ionized dopants, but also the charge due to the mobile camiers. The current density at which the peak electric field changes from the metallurgical junction to the episubstrate interface (Figure 2.1 ld) is defined to be Jc. The electric field profile in Figwe 2.1 ld is integmted to obtain

1

“J

J== qv Nn + 2eVc~ I qWn2

(1)

where q is the electronic charge, v~ is the electron saturation velmity, ZVnis the ionized doping concentration

in the epi-region, &is the pennittivity

of silicon, and Wmis the epi-region thickness.

As J is increased above Jc to the level where base push out occurs, Jh, the distance the effective base region extends into the collector, Wcm is given by:

w cm =wn{l - J(J.-O’Yn)/

(Jh-w%)}

IV-19

,.

.,,

(2)

As J is increased, the peak electric field continues to increase at the epi-substrate Eventually the peak electric field can reach a level to sustain avalanche multiplication in majority carrier injection (holes) into the base region.

interface.

which results

Once injection occurs, the base-emitter

junction is turned on, and the emitter injects electrons across the base into the high field region of the collector where more avalanching and subsequent injection occurs, and so on. Once this regenerative feedback mechanism is initiated, the parasitic BJT eventually enters second breakdown and SEB occurs. The CIA model helps to explain the regenerative feedback mechanism inherent to the parasitic BJT, but it does not incorporate mechanism.

all of the basic components

of the regenerative

feedback

A more detailed treatment is required to better quantify the SEB mechanism

what levels must J achieve to initiate significant avalanching for a given combination

(e.g.,

of device

dimensions, doping densities, and bias conditions ?). The impact that avalanche multiplication

has

on the regenerative feedback mechanism that leads to SEB motivated the next stage in modeling: drain-body avalanche. 2.2.2.

Drain-Body Avalanche In order to better quantify the regenerative feedback mechanism in SEB, it is necessary to

solve the following problem:

given the doping densities and thickness of the base and collector

regions in the parasitic BJT of a power MOSFET, find the density of avalanche-generated that return to the base for a given density of electrons injected into the base-collector region (BCDR).

holes

depletion

This model was outlined by Hohl and Galloway in [47] and later developed by

Hohl and Johnson in [52]. The ratio of avalanche generated holes to injected electrons

is defined

to be M, which is a function of the electric field, impact ionization rate, and electron density within the BCDR. In this model, the 1-D Poisson equation is solved across the BCDR taking into account the space charge associated with the mobile carriers. The analytical expressions,

sample calculations

of electric field, ionization rate, potential,

carrier densities, and other details of this calculation appear in [52]. The end result is plotted in Figure 2.12. There are three distinct regions present in each avalanche curve shown in Figure 2.12. The first region is the distinct hump appearing for values of n(x#ND <1. This corresponds

to an

initial decrease in the avalanching rate that results when the peak electric field at the metallurgical junction decreases and the BCDR extends deeper into the collector region at low levels of electron injection from the emitter into the base. The second region is the valley region or local minimum appearing for values of n(xP)Z7V~ = 1. This corresponds to a near zero avalanching rate at a current level where the injected electron density and collector doping density are comparable.

The third

region of the avalanche curve appears for values of n(xP)fl~ > 1, where the hole concentration increases at approximately

the same rate as the electron concentration.

lanche curve, the peak electric field (and correspondingly IV-20

In this region of the ava-

the peak impact ionization) has shifted to

vD~ = 95 v/

I

BVD~ = 1(M)V

0.0

I

0s

/

1.5

1.0

2.0

25

n/ND Figure 2.12. The avahche curve: a solutionto the Poissonequatim relatingthe amount of avA.nchegeneratedholesfor a given amount of injectedelectrvns. Electronand hole concentmtionshave been normalized10 the &ping density of the collectormgwm

the epi-substrate

interface in the collector.

In terms of the feedback mechanism for SEB, the appropriate value for M can be obtained from a curve similar to those in Figure 2,12.

Note that it is necessag

to calculate a separate

avalanche curve for each device structure and each applied drain-source bias. The calculation of any given avalanche curve is fairly time intensive; therefore, a matrix of avalanche curves is archived for the set of desired device structures and bias conditions prior to implementation

in the semi-

analytical model that is described in the next section. 2.2.3.

Semi-Analytical Model The semi-analytical

model of the feedback mechanism proposed by Johnson, et. al., assumes

that the parasitic BJT has already been turned on by the transient currents generated by the heavy ion strike [31 ]. Depending on how hard the parasitic BJT is initially turned on, the model shows that currents within the device will either: (1) regeneratively

increase until the simultaneous

high

current and high voltage in the device trigger second breakdown leading to thermal meltdown; or (2) the currents will die out to zero leaving the device unharmed. A stable station~

solution of the

feedback mechanism defines the boundary separating whether the currents will regeneratively

in-

crease or decrease. The feedback mechanism relates: (1) electron injection from the emitter across the active base into the collector (using standard and high-level injection BJT electron cummt density expres-

IV-21

sions); (2) avalanche-generated

hole current returning from the collector into the base (using the

avalanche curves described in the previous section); (3) subsequent lateral hole current through the base to its contacts ; and (4) the induced base-emitter

voltage

resulting

from this lateral base

current [31 ]. The coordinate system for this model is shown in Figure 2.13. The origin is defined at the point of the ion strike, which is assumed to be at the drain edge of the MOSFET channel. The regions labeled E, B, and C are the emitter, base, and collector of the parasitic BJT. The length of the source region in they direction is defined as y., and the position of the p body p+ plug interface is defined at yP. The extent that the p+ plug extends under then+ source region, y,, is defined as the difference between y. and yP. The details and solutions of the equations used in this model appear in [31]. Given the geometry in Figure 2.13 and the physical boundary conditions, a single stable stationary solution exists that defines the boundary between non-destructive the regenerative

parasitic BJT transient currents and initiation of

feedback mechanism leading to SEB.

This boundary is defined as the critical

condition for burnout. The following algorithm is then used in the semi-analytical

model to calculate the LET burn-

out threshold for a given DMOS structure: (1) given the structural parameters and drain-source voltage, the critical condition is calculated;

0

YLJ

i

I

Ys

WB

jHc(j)

x : +

———

—.—

———

———

— i

I

Figure 2.13. The coordinate system used in solving for the critical condition of the feedback mechanism. distributed one-dimensional model for the parasitic BJT inherent to the power DMOS device structure.

Iv – 22

This is a

55

1 !

= 150V

‘DS

175V 200V 225V 250V 275V

b}

A A

290V

./

15 012345678 Extent of p+plug [~m] Figure 2.14. Using the semi-analytical model to assess the SEB sensitivi~ of the power DMOS device to changes in drain-source bias and changes in the size of the p+ plug region.

(2) given the critical condition, the critical electron current density in the collector is calculated; (3) the critical collector current density is integrated over one cell in the DMOS structure to obtain the critical collector current; and (4) the LET necessary to initiate the critical current for SEB is calculated (recall the introduction section in this paper). The effects of drain bias and the effects of the lateral extent of the p+plug on the LET threshold for SEB of this device structure can be calculated. The lateral extent of the p+ plug, y=,is defined to be: Ye= Y,-Yp

9

(4)

(i.e., the length that the p+plug extends under then+ source as shown in Figure 2. 13). For example, y,=O pm means that the p+plug does not extend under the source region and ye=5~m means that the p+ plug extends 5 pm under the source region. The results of this calculation are shown in Figure 2.14, where ye is varied from O ~m to 8 pm and l’~s is varied from 150 V to 290 V (the device has an ideal breakdown voltage of 300 V). The semi-analytical

model was applied to the power BJT device structure by Titus, et. al. [2].

The results obtained from the semi-analytical

model when applied to the power BJT device struc-

IV – 23

.

I

MJ15003 -------

----

------

----2N

2N562

2N6284 2NXXXX

Figure 2.15. Using the semi-analytical model to assess the SEB sensitivifl of the uower BJT.~tructure. The dark shaded regions correspond to devices which exhibited burnout, and the light regions correspond to devices which did not burnout. The y-axis is the ratio of the emitter finger width to the Gummel numbe< which is pmpotiional to the internal base resistance. The parts with lowest base resistance did not burnout. ..l

T = 400K

- T = 300K

“

25

I ,,

I 95

110

I

I

125

140

,

I

155

I

170

t

185

vD~[v] Figure 2.16. Using the semi-analytical model to assess the SEB sensitivityof the power DMOS device to changes in ambient temperature. The higher te~perature requires more current to initiate burnout. This corresponds to a higher LET of the incident ion.

IV -24

,!

ture, along with corresponding

experimental data are shown in Figure 2.15 [2]. In the data shown

in Figure 2.15a, the devices with the highest collector+mitter

bias SEB thresholds

also had the

lowest base resistance [2]. Note that the trends seen in the experimental data are also demonstrated by the model. The effects of elevated temperature on SEB were incorporated into this model by Johnson, et. aL, in [37]. The major change to the model described above was made in the drain-body avalanche model. As temperature increases, the impact ionization rate for a given electric field decreases due to a shorter mean free path between collisions.

A decrease in the impact ionization rate results in a

decrease in the avalanche multiplication rate which leads to a decrease in the SEB susceptibility. To understand this result, consider two i&ntical devices with the same drain-source bias, but having different ambient temperatures

during irradiation.

If each device is hit by similar ions such that

each parasitic BJT is turned on with equal injected electron cument densities, the device at the lower temperature cument.

(higher avalanche multiplication)

will have a higher avalanche generated hole

This leads to a critical condition (solution to regenerative feedback mechanism

model)

with lower critical current densities required to initiate SEB. The results are shown in Figure 2.16. These results were supported both experimentally

[37] and with two-dimensional

simulations [53].

The analytical models presented in this section have been very helpful in gaining meaningful insight into the physical failure mechanisms that contribute to SEB. The decrease in SEB susceptibility (i.e., an increase in the threshold LET of an incident ion required to tigger

SEB) due to a

reduction in drain-source bias, a reduction of resistance in the base of the parasitic BJT (increasing size of the p+ plug), and an increase in ambient temperature was predicted in the models and verified experimentally. 2.2.4.

2-D Numerical Simulation - MEDICI The analytical models summarized above are important as they help to provide insight into the

SEB failure mechanism. for time dependence,

However, the use of numerical simulation tools is necessruy to account

and is necessmy to account for higher order effects in the standard device

equations (eg., they may include various models for non linear effects on mobility, recombination, or band gap). Furthermore, it is necesstuy to use two-dimensional

or even three-dimensional

simu-

lations to study the effects of geometrical layout of the DMOS hzmsistor, and to study, for example, the effects of ion impact position on SEB susceptibility.

Difficult problems may arise due to tech-

nical limitations of the numerical simulatom. For example, 2D simulators are appropriate for cylindrical symmetry or stripe geometries perpendicular to the simdated

x-y plane. Many of the exist-

ing 3D simulators limit themselves to a small number of x-y planes along the z axis. The measured drain-source cument versus time during a SEB experiment shows two different behaviors.

This is illustrated in Figure 2.6 as well as in previously published work by Roubaud, et

aL [39]. Cases where the drain-source cument was self-sustaining IV-25

(i.e., for high VDs, in general)

would eventually lead to thermal runaway conditions (second breakdown) and SEB, if the power supply was not physically disabled. subsequently

Cases where the measured current rises to a peak value and

decays to zero (i.e., for the lower drain voltages, in general) would lead to a non

destructive event. The previously discussed analytical models do not explain this dynamic behavioq however, the decaying currents may be explained by the critical condition (semi-analytical model) that defines the boundary between triggering and not triggering the regenerative feedback mechanism that leads to SEB. The desire to model the dynamic aspects of the regenerative back mechanism

necessitates the use of more complex simulation tools.

different 2-D SEB simulation models that have been developed:

feed-

There are at least two

(1) a model based on the 2-D

device simulator MEDICI [54], and (2) a model based on an original 2-D device simulator [55]. These models are described next in terms of the required inputs to the simulators, implemented

within the simulators, and the results of the simulations.

The first simulation model to be discussed uses MEDICI [39-40]. simulator that models the potential and carrier distributions electrical characteristics

MEDICI is a 2-D device

within a given device to predict the

of the device for any given bias conditions [54]. The Poisson equation and

the electron and hole current continuity equations are solved simultaneously Newton non-linear iteration methods. semi-empirical

the models

using Gurnmel and

The following models were used in the simulations:

carrier mobility model that accounts for the carrier-carrier

with high carrier densities [39]; (2) a field-dependent

(1) a

scattering that occurs

carrier mobility model that accounts for the

effects of high electric fields in the direction of current flow; (3) the Schockley-Read-Hall

recom-

bination method using carrier concentration dependent life time; (4) the Auger recombination model; (5) the impact ionization model; and (6) a band-gap narrowing model.

The cell structure and

device parameters are given in [39]. A capacitor, C, was inserted in the model in parallel with the drain and source of the MOSFET to model the parasitic capacitance of all the other cells in the device. A load resistance, RL, was placed in series between the drain and power supply to model the resistance used in the experimental test set-up by Roubaud et. al. [39]. Roubaud, et. al. also point out that in their simulations that result in a sustained current (SEB events), the entire cell turns on. This is in direct agreement with the analytical models and gives strong evidence of the role that the regenerative feedback mechanism plays in determining whether or not SEB occurs.

It has been observed experimentally

[53] that it is possible for SEB to occur

before the entire cell has a chance to turn on. A possible explanation for this phenomenon

is that

neither the analytical nor simulation model incorporates a thermal runaway model that physically explains the final destruction of the device (melting of metal and silicon). Subsequent efforts with the MEDICI-based

simulation model were carried out to account for

experimental

results on SEB current shapes (i.e. amplitude, rise and fall time) and the existence of

spontaneously

vanishing and destructive events [39-40]. The effect of the ion impact location was

investigated

and shown to be responsible for the variety of responses (see Figure 2.6) observed IV – 26

.10

-20

--

30

..

40

pm

pm+ JC/pm J

0.6 0.5

N

0.2

N

N

0.13

N

N

N

0.11

N

N

NNN

0.105

N

N

NNN

0.102

N

N

NNN,

0.1002

N

N

NNNN

0.1

N

N

NNNNf###NNN

0.05

N

N

NNNNNNNN

Nw

w

Figure 2.17. MEDICI simulation results showing the effects of va~ing the location of the ion impact position ajier

[40]. experimentally

for given test conditions [40]. It was demonstrated

that the device sensitivity to

SEB is highest if the ion is incident in the neck region close to the channel. More refined results are shown in Figure 2.17 (the device structure was based on the IRF 450-ST power MOSFET).

Simu-

lations were used to test device structures with increased radiation tolerance [56, 57]. Effectiveness of decreasing emitter doping, increasing the base recombination,

and increasing p+ plug size

were verified. These modifications reduce the injection efllciency and overall gain of the parasitic BJT, thus reducing the SEB susceptibility. Simulations intended to improve insight into the SEB mechanism were also performed. Two demonstrative

examples on simplified structures are shown in Figure 2.18.

One structure is in-

tended to model an ion strike that passes through each region of the parasitic BJT (emitter, base and collector). The second structure is intended to model anion strike that passes near the channelhwk region of the power MOSFET (outside the emitter of the parasitic BJT). The discussion that follows describes some of the subtle steps that take place during the burnout mechanism.

Conditions

have been intentionally exaggerated (low V~~ and very high LET) in order to make as obvious or legible as possible the effect of the ion. The first example, is devoted to the case where the ion crosses the entire source-body-drainsubstrate stack. Potential and flow lines are shown at two times in Figure 2.19. Figure 2.20 shows IV-27

,.

Figure 2.18. Simplified structures used in MEDICI simulation. Structure (a) is intended to model an ion strike that passes through each region of the parasitic BJT (emittec base and collector). Structure (b) is intended to model an ion strike that passes near the channeb’heck region of the power MOSFET (outside the emitter of the parasitic BJT) ajler [56].

IXst,ax:i.? {Miwor@}

Figure 2.19. Potential andflow [56].

Dismncc: !kfierom)

lines for two times fmm the numerical simulation of simpll~ed structure (a) ajler

IV – 28

..

..

w-.

Figure 2.20. Impact ionization rates for two times from the numerical simulation of simplified structure (a) ajler [56].

the corresponding

impact ionization rate patterns. The current versus time is given in Figure 2.21,

and Figure 2.22 presents the electric field evolution. It can be seen that the first effect of the ion action is to create the high conductivity tion. After 5 picosecond,

filament and to drastically change the potential distribu-

the field is uniform along the filament core. Favorable conditions for a

high impact ionization rate are at the substrate edge, where the density of electrons is very large, and at the edges of both filament and collector-base junction where high field and rather large carrier density are present. This is shown in Figure 2.20a, where each contour line represents a factor often increase in the impact ionization rate. A carrier supply is necessary to compensate the carrier density decrease due to the filament expansion.

As avalanche furnishes carriers, electron

injection in the collector can increase and force the field to be higher at the n-n+ boundary. This is shown in Figure 2. 19b (note the compression

of equipotential

lines near the n-n+ boundary) and

Figure 2.22 (note the electric field evolution in time). CIA model tendencies are confirmed (the peak electric field moves to the n-n+ junction), but the field is not negligible between the collectorbase junction and WC1~. Strong generation is developed at the substrate junction. ing toward the source can compensate

The holes flow-

the electrons flowing toward the substrate, allowing the

charge density to remain small in the low field region, thus maintaining the high electric field at the n-n+ boundary (if charge compensation

in the low field region is not maintained, the electric field

profile reverts to the equilibrium distribution with the peak electric field located at the base-collector junction).

The region within the parasitic BJT where high conduction occurs can increase in

size because the size of the two avalanching regions in the collector increase simultaneously

(note

the increase of the area where impact ionization is occurring in Figures 20a and 20b). When all the source area (emitter of the parasitic BJT) is forward biased, the increase of the region of high conduction stops at the base-collector junction, while the area where impact ionization is occurring IV -29

102

/A\

structure b I 10-2 . I

I

I

I

10-10

10-9

10-8

10-3

10-12

10-11

1(J-2 10-3 10-7

Time [s]

Figure 2.21. Drain-source

current versus timefim

the numerical simulation of the simplified structures ajler [56].

,.

5 ps \

0 o

5

10

15

Distance [pm]

Figure 2.22.

Evolution of the electric fieldfiom

the numerics! simulation of the simplified structures ajter [56].

Iv -30

continues to increase at the substrate.

This corresponds to the quick increase of current in Figure

2.21 and to the last step of the process. The second example is devoted to the case where the ion only crosses the body-drain-substrate stack, as it does in the actual devices when it strikes the channel. Potential and flow lines are shown in Figure 2.23. The first effect of the ion action is to cause a great part of the drain potential to drop horizontally

between the track and the source (note the compression

of equipotential

lines in the

upper part of the simulated structure). The horizontal potential distribution is not uniform due to a positive net charge (hole excess) at the body part of the column boundary. electric field and impact ionization immediately

occurs.

This results in a high

After some picosecond,

high electric

field conditions are still present, but electron injection from the emitter is initiated by turning on the part of the emitter-base junction closest to the ion track (see the flow lines of Figure 2.23a). As the injection increases, the net charge decreases and the electric field is pushed down towards the drain as can be seen in Figure 2.23b (note the compression of equipotential

lines near the n-n+ bound-

ary). The high electric field is now at the epi-substrate junction where strong avalanche occurs. The last step of the process will start with the extension of the avalanche region area (note, in Figure 2.23c, the expansion of the area concerned by the compression of equipotential the n-n+ boundary).

lines near

A lower LET would produce the same process except that avalanche would

fail to sustain the current during the last step. A lower LET is also necessary to initiate SEB in the second example.

This is consistent with the results presented in Figure 2.17 which show a higher

sensitivity in the channel. These two examples have been chosen to illustrate that the details of the process leading to SEB maybe different. The first one indicates that the direct activation of the parasitic transistor in the CIA mode is possible (i.e., the ion impact location is within the parasitic bipolar transistor).

In

the second case, the ion impact location is in the channel region of the power MOSFET, and the CIA mode is entered progressively as the filament diffuses laterally. More complex situations may occur in actual structures, especially for short ion penetration depths. To help further illustrate the SEB mechanism, a structure without contact to the base of the parasitic BJT (floating base) was considered by Dachs [53]. It was shown that SEB can still occur without providing a conduction path to ground for the avalanche generated holes. In this scenario, the parasitic BJT is not turned on by an Ohmic drop in the base region [31, 37, 47, 52] (no current can flow), but rather by the potential drop that occurs from the redistribution region.

Simulations

of carriers in the base

performed on the simplified structure in Figure 2.18a indicate that a lower

LET is required to initiate SEB for an open base configuration [53].

IV–31

than with the base-emitter

shorted

Difstzmce[Microns)

DisixirIce

Figure 2.23. ajler [56].

Potential andjlow

(Micmm)

lines for three times fmm the numerical simulation of simplljied structure (b)

IV – 32

,,,

,

,.

2.2.5.

2-D Numerical Sinudktion - EPICS A novel SEB experiment was performed by Kuboy~

et. al., with a measurement

system

called Energetic Particle Induced Charge Speetroseopy (EPICS) [42]. h EPICS, the charge collected at the drain contact of a power MOSFET is monitored instead of the current. ~pical

spectra

obtained fkom EPICS for drain-source biases between 50-300 V are illustrated in Figure 2.24 as a function of the total number of counts versus logarithmic charge. In each spec~

there are two

distinct initial pesks. The fmt peak corresponds to the initial current resulting km

the heavy ion

generated charge distribution.

The second peak comesponds to the cument resulting fim

on of the parasitic BJT. The spectra for the highest two drain-source which corresponds

the turn-

biases show a third peak

to SEB. This supports predictions from the previous semi-analytical

and 2-D

simulation models that the turn-on of the parasitic BJT can lead to SEB if the regenerative feedback mechanism

is initiated, othe~ise

the currents in the parasitic BJT decay leaving the device un-

harmed. A 2-D device simulator similar to PISCES was developed to investigate the SEB mechanism. This simulator solves the Poisson equation and the continuity equation in cylindrical coordinates [55]. Simulations MOSFET (SMOS).

were performed on a large-source MOSFET (LMOS) and on a small-source The LMOS and SMOS devices were chosen to model the effects of ion strike

position. The LMOS device represents the case where the ion strike is further fbm the base contact of the parasitic BJT (further from ground), while the SMOS device represents the case where the ion strike is closer to the base contact.

Simulation results that show the eleetron, hole, and total

current as a function of time are sketched in Figure 2.25. The simulations illustrated in Figure 2.25 represent

VDs = 50 V (the example devices had a breakdown voltage of approximately

200 V). The

bias applied was not high enough to initiate the regenerative feedback mechanism in the parasitic BJT, because the electron current component in each device is not sustained. verify that the parasitic BJT was initially turned on by investigating

The authors did

the potentials through the

device [55]. There were no simulations

performed on the LMOS or SMOS structures at higher drain-

source biases (i.e., sustained and/or regeneratively

increasing currents in BJT was not simulated),

so it is difficult to compare the results illustrated in Figure 2.25 directly with those from the previous 2-D modeling.

However, useful insight into the SEB mechanism is still obtained.

This model

gives evidence that transport of charge following a heavy ion strike can result in turn-on of the parasitic BJT. The importance of including the conductivity of the heavy ion induced charge distribution when determining MOSFET is illustrated.

the electric field distribution throughout the drain region of the power The dynamic evolution of the electric field distributions

that lead to the

currents illustrated in Figure 2.25 are shown in [55]. Kuboyama et. aL. argue that if avalanche multiplication

is high enough that the rate of injected electrons (from the emitter of the parasitic

Iv-33

..

—

.

I

280V 1

‘ 250V

+

~ u

200

v

150v v~~=50v iw

102

I@

1~

Charge [pC]

Figure 2.24. EPICS charge collection for SEB after [42].

20

Ion: Si Total

g

B I

h 5

I 1

-----------

--, ---

-5- :

o

20

40 60 Elapsed Time [ps]

80

100

Figure 2.25. EPICS numerical simulation results for a long-source MOS (LMOS) structure and a short-source MOS (SMOS) structure after [55].

IV – 34

BJT) surpasses the diffusion rate of carriers in the charge filament, the current in the charge filament can be sustained.

2.3.

Reducing SEB Susceptibility To summarize this section on single-event burnout, possible methods for reducing the single-

event burnout (SEB) susceptibility

of power MOSFETS will be high-lighted.

solutions have been discussed in detail in the preceding sections. reducing SEB susceptibility

These hardening

The most effective method for

is to extend the length of the p+ plug as far as possible, without inter-

fering with the channel region.

Recall that this reduces the resistance of the base region of the

parasitic bipolar junction transistor (BJT) inherent to the power MOSFET.

By reducing the base

resistance, the currents (base and collector) necessary to get regenerative feedback (and ultimately SEB) are increased. creased. MOSFET.

By increasing the base and collector currents, the SEB susceptibility

A second way to reduce SEB susceptibility

is to decrease the drain-source

bias of the

Reducing the drain-source bias reduces the electric field in the base-collector

region. The impact ionization is therefore reduced, and the SEB susceptibility way to reduce SEB susceptibility

depletion

is reduced. A third

is to use p-channel power MOSFETS. This may not always be

possible for any given circuit configuration, electrons reduces the SEB susceptibility SEB susceptibility

is de-

but the lower impact ionization rate for holes than

for p-channel compared to n-channel power MOSFETS.

is also reduced at elevated temperatures,

due to the reduced impact ionization

rate; however, long-term reliability problems associated with higher temperatures

may prohibit

such a solution. In summary, SEB susceptibility is reduced when: (1) p+ plug is extended as far as possible; (2) drain-source bias is reduced; (3) p-channel MOSFET used instead of n-channel; and (4) the operating temperature is increased. Currently, power MOSFETS that are tolerant to single-event burnout are available from one or more commercial semiconductor

manufacturers.

IV-35

3.

SINGLE-EVENTGATE RUPTURE m POWER MOSFETS

Although single-event burnout (SEB) and single-event gate rupture (SEGR) are both caused by the passage of a heavy ion through the device, the failure mechanisms are altogether different. Recall, SEB occurs when the parasitic BJT is turned on such that the critical condition is met and the regenerative feedback mechanism is triggered. ion-induced

SEGR, on the other hand, is caused by heavy-

localized dielectric breakdown of the gate oxide.

In Figure 3.1, a DMOS device is

shown with an incident ion track in the gate-drain overlap (neck) region. Under appropriate bias conditions, accumulation

of charge in the silicon (generated by the heavy ion) at the Si-SiOz inter-

face in the gate-drain overlap region (i.e., the neck region) can result in sufilciently high electric fields across the gate oxide to cause a localized gate rupture (i.e., localized dielectric breakdown). Subsequent gate to drain current results in a thermal runaway condition melting a permanent

short

between the gate and drain rendering the MOSFET useless. 3.1.

Experimental

Status

Several research groups have reported experimental results on SEGR. This section will briefly review testing techniques and present some typical data. In addition, an overview paper summarizing many of the parametric dependencies for SEGR has recently been published by Titus and Wheatley [32].

n+ substrate

Figure 3.1. SEGR is initiated when an incident ion passes through the gate-drain overlap (neck) region of the DMOS power transistor

IV – 36

3.1.1.

Testing Techniques Most test systems used to characterize power MOSFETS for SEGR are similar to the test set-

up used for single-event burnout (SEB) shown in Figure 2.5. To date, there exists no nondestructive SEGR testing method [32]; therefore, due to the destructive nature of SEGR, many deviees are required for evaluation.

In addition to drain-source voltage control and monitoring, the gate-source

voltage must be controlled and the gate current monitomd during an SEGR experiment.

The fol-

lowing test method deseribed by Titus and Wheatley can be used to determine the SEGR failure threshold for a given ion [32]. For the fmt device: (1) seleet an ion beam and energy; (2) fi the valUe of VDSat =m volts; (3) aSsUme ~ ifitid

startkg Vohge for VGS;

(4) expose the device (usually delidded) while monitoring the gate and drain current; (5) shut off the beam upon achieving the desired ion fluence or SEGR detected; (6) test for gate current with an applied field> lMV/cm; (7) if SEGR is not observed, increment VGS; and (8) repeat 4-7 until SEGR is observed or electrical breakdown is miehed [32]. For eaeh subsequent device, the test sequence is similar exeept step 2 is changed by increasing the drain voltage to the next bias condition and steps 3-8 are repeated.

The procedure is repeated

for several drain biases and several different ions. 3.1.2.

SEGR Data The following list of SEGR experimental results is not intended to be inclusive.

Wheatley,

Titus, et al., [35] obtained an extensive matrix of the gate to source biases, V~s, and drain to source biases, V~s, necessary to induce SEGR in a particular power MOSFET structure exposed to monoenergetic heavy ions at a given LET. Over 400 transistors from the same wafer lot and heavy ions with LETs that ranged from Oto 83 MeVcm2/mg were used in the study (an LET of zero means no ion was incident and represents the control case for the experiment).

In later work Wheatley, Titus,

et al, extended their matrix and included gate oxide dependence [58]. Much of their work is summarized in a recent overview paper [32]. Nichols, et al., have presented data a variety of commercially available power MOSFETS [59]. Additional data including temperature and angular dependence for SEGR was published by Mouret, et al. [60]. Wheatley and Titus were able to fit their results to a semi-empirical experimental

results and the semi-empirical

model [32, 35, 58]. The

fit to the data are schematically

shown in Figure 3.2.

The manufacturer recommended maximum allowed operation limits and the gate-source and drainsouree breakdown voltages are also shown in Figure 3.2. iv-37

o-

t ~1 6

v

-1o-

v

----

I

,A

t 8

-20-

,“

8

o I

ttA

b

A

Control 0 Flourine V Magnesium ● Chlorine W Titanium A Nickel V Bromine O Iodine •l Gold A

I

-30-

1:

A ●

-40-

.——

■

I

——

BVG~~ 0

20

40

-0

—~

60

T=300K

80

100

vD~ [v]

Figure 3.2. SEGR experimental data and the corresponding semi-empirical

model fit ajler [35].

For a given value of LET, VGSand VDSare linearly related by:

VG~= {0.84[1 - exp (-LET/

17.8)]} V~~- {50 /(1+ LET/ 53)},

where the slope and VG~- intercept of the line corresponding

(3.1)

to a given LET (see Figure 3.2) are

represented by the first and second bracketed terms, respectively [35]. The slope and VGS- intercept relationships

were obtained through curve fitting.

The complete details of the curve fit are

addressed in [35]. Note that Equation (3.1) only directly applies to the device type used in the experiment.

Other device structures would need similar experimental

and data reduction tech-

niques performed in order to obtain a relationship similar to Equation (3.1). However, the relationships between VDs, VGS, and heavy ion LET would be qualitatively the same. Useful insight into the SEGR phenomenon can be obtained from this data. As the LET of the incident ion is increased, SEGR is induced with lower (in magnitude) bias conditions. supports the SEGR failure mechanism initiated by heavy-ion-induced

This data

charge accumulation

at the

Si-Si02 interface in the gate-drain overlap region (which results in localized critically high electric fields across the gate oxide region and ultimately leads to SEGR). Most importantly, the information contained in Figure 3.2 clearly shows the dependence of SEGR on VDS. Often one is primarily interested in Vcs when considering the electric fields across the gate oxide region. Clearly, when addressing SEGR vulnerability, both VD~and VG~need to be considered along with the heavy ion IV – 38

LET. SEGR is more sensitive to changes in VG~than VDS, as shown in Figure 3.2. This study also shows that power MOSFETS may be susceptible to SEGR over a fairly large range of bias conditions within the recommended

operating limits. A study like this could be performed to redefine

the locus of safe bias conditions

for a given power MOSFET intended for use in a heavy ion

environment. To gain more insight into the SEGR mechanism, the effects of temperature and angle of the incident ion were investigated summarized. temperature

experimentally

[60]. The major findings from this study are now

Most of the parts tested show a large amount of dispersion in their experimental dependence.

The room temperature

and high temperature drain-source

bias ranges

overlap; therefore, no general rule can be derived. There is a slight angular dependence for SEGR however.

The greatest sensitivity to SEGR occurs with normal incidence, and the sensitivity de-

creases as the angle is changed from normal incidence. Most SEGR data has traditionally been displayed like the data shown in Figure 3.2. Due to the destructive nature of SEGR, it has been difilcult to display the data in conventional

single-event

cross-section format. In Section 1.4 of this Short Course, the single-event cross-section was given as the ratio of the total number of events to the total ion fluence.

In the case of SEGR, the total

number of events is one, and the ion fluence is the number of ions required to trigger SEGR.

In

Figure 3.3, an example of an SEGR cross-section is given [61]. For this analysis, the cross-section versus the SEGR threshold drain-source bias was obtained.

The data clearly show that the SEGR

threshold drain-source bias is very abrupt.

v~~(v) Figure 3.3. Measured SEGR cross-section

versus drain-source bias afier [61].

IV – 39

3.2.

Physical Modeling Two SEGR modeling techniques of differing complexity are presented in this section.

models were developed to help explain the trends seen in the semi-empirical early modeling efforts that lead to a charge sheet model are discussed.

The

model above. First,

Next, a numerical simula-

tion model based on a 2-D device simulator is presented, 3.2.1

Analytical

Charge

Sheet

Model

In the SEGR failure mechanism, high electric fields that are initially dropped across the thick epitaxial drain region are transferred to the gate oxide region.

For n-channel power MOSFETS,

electrons are drawn towards the positively biased drain, and holes are drawn towards ground (and/ or a negatively biased gate). (See Figure 3.1.) In order to physically explain the increase in gateoxide electric field, an understanding

of carrier transport along the ion track and radial diffusion of

the carriers was needed. To address these issues, a charge-sheet description analogous to that used for lateral MOSFETS [62] was developed by Brews et. al., [63]. In this model, a current source is used to model the flow of holes up along the ion track to the Si-SiOz interface. The magnitude of the current source decreases exponentially

with time to model

the radial diffusion of the charge filament. The path of hole transport along the Si-SiOz surface is modeled as a distributed R-C line. The circuit model that represents this is shown in Figure 3.4. The parameters of the distributed R-C line are calculated using a charge-sheet model that relates the distributed resistance to the hole areal density in the inversion layer. The mathematical

details of

this model appear in [63]. Calculated results in terms of oxide electric field versus radial distance from the ion track as a function of time are illustrated in Figure 3.5. As illustrated in Figure 3.5, the model indicates that electric fields in the MV/cm range exist for times of picosecond.

This model does not indicate whether the fields persist long enough for

SEGR to occur, but it does lend some insight into making the power MOSFET less vulnerableto SEGR. Clearly, the smaller the R-C time constant is for the circuit, the quicker the holes can move to ground.

So if the resistive path to ground is reduced, or if the oxide and/or depletion layer

capacitances are reduced, the device should be less vulnerable to SEGR [63]. 3.2.2

2-D Numerical Simulation Model In order to elucidate the dependence of SEGR on power MOSFET design parameters, a model

based on ATLAS-II [64], a two-dimensional

microelectronic

device simulator, was developed by

Allenspach et. al. [65-66]. For this model, device parameters were obtained from ATHENA [67], a two-dimensional

microelectronic

process simulator.

Typical simulation results from ATLAS-II are given by potential distributions,

electric field

profiles, and carrier densities at any point within the device structure, for example. To predict bias

IV – 40

Figu~ 3.4. DistributedR-C cinwit num%lfir the chqe sheet mcm!eljbrSEGRajler [63].

0123456 Radius r [pm] Figure3.5. Calcukztedmsultsjbm the chaqe sheet modelin tenm of omii?elec~”cjieldversus radialdistance fmm the ion tmck as ajimction of timeafter [63].

conditions for a given LET of the incident ion that leads to SEGR, it was necessary to develop a method of relating A~AS-11

simulation results to a criterion for initiating SEGR.

A modified

version of an empirical model originated by Wrobel [50] was used to relate the critical electric field across the gate oxide, Ec~, required for onset of SEGR to the gate oxide thickness, tu, and the LET of the incident ion. This model also separates the electric field across the gate oxide into two components:

(1) the transient gate oxide electric field resulting from hole accumulation

at the Si-

Si02 interface, Em and (2) the static gate oxide electric field due to VG~,EN. A comparison of Ec~, to the transient and static components

of the peak electric field in the gate oxide provides the

IV-41

,.,

necessary criterion for determining

the onset of SEGR.

Using the following algorithm by R.L.

Pease [66], the values of V~S and VGsrequired to initiate SEGR for a given LET of the incident ion were determined: (1)

Define the input deck for 2-D simulator including device geometry and parameters, bias conditions, and the ion-generated charge distribution;

(2)

Perform transient simulation to obtain oxide field distribution and extract the peak field, lZP.;

(3)

Repeat simulation without using ion-generated charge distribution to obtain E~c.;

(4)

Compute peak value of Et, from E,,~m = E, - ELX.; and

(5)

compute

versus time

a critical value of VGs for initiating SEGR with VGscr= L. (ECR -

EtmzJ Results obtained from this model using the algorithm above are compared with experimental data in Figure 3.6 [66]. The value of tOXis varied from 50-150 nm for these simulations. using the previously discussed empirical model are also shown. The experimental

Results

data and simu-

lation results show excellent agreement with one another indicating that this model may become a good alternative to performing rather costly SEGR experiments.

The results also show that in-

creasing the value of tOXin a given power MOSFET is a viable means of reducing the SEGR vulner-

ability. Finally, a simple geometrical model was applied with SEGR simulations by Mouret, et. al., in [60, 68] to help explain changes in SEGR sensitivity due to variations in the angle of the incident heavy ion. These findings agree with experimental data by Nichols, et. al., in [59] and Mouret, et. al.., in [68] that indicate that SEGR vulnerability

is reduced with increasing angle from normal

incidence. In a paper to be presented at the 1996 NSREC, numerical simulations are used to model the positional dependence of the ion strike on SEGR [69]. In this paper, the neck region of the power MOSFET is identified as the most sensitive region for SEGR. Furthermore, it is shown that removing the poly-Si above the neck region of the power MOSFET helps to significantly reduce SEGR sensitivity. 3.3.

Reducing SEGR Susceptibility To summarize this section on single-event

gate rupture, possible methods for reducing the

single-event gate rupture (SEGR) susceptibility of power MOSFETS will be reviewed. These hardening solutions have been discussed in detail in the preceding sections. The most effective way to reduce SEGR susceptibility is to increase the gate oxide thickness, tow Increasing toxincreases the

IV-42

o+f-

-20” ~ b

8

-40V •l o IA

-60-

tOX= 50 nm tOX= 70 nm tox=100 nm tox= 150nml

-80-

1:

I

0

Figure 3.6. Comparison of two-dimensional SEGR after [66].

1

I

1

1

I

10

20

I I

I 1

30 vD~ ~]

I

1

40

simulation results, semi-empirical

1

i

50

model, and experimental data for

SEGR threshold drain-source and gate-source biases. This increases the allowed range of operation, which may be important in certain switching applications. susceptibility

A second way to reduce SEGR

is to remove the poly-Si gate that lies above the neck region of the power MOSFET.

The SEGR threshold drain-source and gate-source biases are increased for ions that strike in the neck region. The area of the power MOSFET that is sensitive to SEGR is reduced; therefore, the SEGR cross-section

is reduced. A third way to reduce SEGR susceptibility is to reduce the drain-

source bias of the power MOSFET.

Reducing the drain-source bias increases the SEGR threshold

gate-source bias. In some switching applications it may be desirable to increase the range that the gate-source bias can swing in order to achieve a faster switching speed. SEGR susceptibility is also reduced when the angle of the incident ion moves significantly away from normal. This is important in understanding

the physics of the SEGR mechanism, but since one cannot control the direc-

tion of cosmic rays in the space radiation environment, this is of little consequence

for space craft

designers. In summary, SEGR susceptibility is reduced when: (1) tox is increased; (2) poly-Si is removed from over the neck region; (3) drain-source bias is reduced; and (4) the operating temperature is increased. SEGR resistant power MOSFETS have been introduced by one or more commercial semiconductor

manufacturers. Iv-43

4.

SINGLE-EVENT DIELECTRIC FAILURE IN CMOS

Heavy ions have been observed to cause catastrophic failures in advanced commercial CMOS integrated

circuits.

Both dynamic-random-access

memory (SRAM) technologies

memory (DRAM) and static-random-access

have shown susceptibility to these hard error mechanisms.

are two distinct classes of hard errors: a single ion total-dose failure mechanism, reported mechanism

that resembles the single-event

There

and a recently

gate rupture (SEGR) phenomenon

seen in

power MOSFETS. The first mechanism

is related to localized trapped charge collected following a heavy ion

strike. The effects of two ion strikes within close proximity are additive, making this phenomenon similar to total dose in nature. This should not be confused with the traditional notion of total-dose damage where all devices in a circuit are exposed to more or less the same level of radiation. phenomenon

This

is a localized total-dose effect; the total dose degradation occurs at the location of the

ion strike. Because of the localized nature of this mechanism, the total dose delivered by a single ion strike is often called a micro-dose. The second mechanism is not yet well established, although it has been shown to differ from micro-dose

hard errors in several fundamental

ways.

This mechanism

differs from micro-dose

hard errors in the direction and time scale of data retention time degradation. damage is not additive between ion hits, and the damage does not anneal.

In addition, this Experimental

data

suggest that this mechanism may be similar to SEGR that is observed in power MOSFETS.

This

failure mechanism is referred to as micro-damage or single-event dielectric rupture (SEDR). In the remainder of this section, the various experimental testing techniques are discussed, physical modeling techniques

are discussed,

darnage susceptibility 4.1.

4.1.1.

Experimental

and finally, possible methods to reduce micro-dose

and rnicro-

are discussed. Status

Micro-Dose Failures The notion of total-dose hard errors from heavy ions was first examined by Oldham and

McGarrity in 1981 [70]. At that time, they concluded that it would take quite a while for device dimensions to shrink to the point where micro-dose failures were a major concern. In 1991, Koga, et al.,

reported the first hard errors attributed to heavy ion micro-dose failure in commercial SRAMS

[71]. Similar findings were reported in SRAMS by Dufour et al. [72]. The hard errors reported for the SRAMS were the result of stuck bits (i.e., the memory cell was permanently stuck in one state or the other and cannot be reset). The charge generated from the ion strike can become trapped at the Si-Si02 interface. Resulting threshold voltage shifts in the transistors that make up the SRAM cell can result in the cell remaining in one state. The state that the bit IV–44

0

❑ :: o A

0

0 A

❑ MICRON (5V) 0 A O A +

40

MICRON (5V) HITACHI (~ HtTAcHl (~ HITACHI (2V) HITACHI (Zv)

60 80 100 LET [MeV-cn#Ymg]

120

(a)

’04

~

m

o A

,o-lo~

40

120

80 80 100 LET [MeV+nWmg]

(b) Figurv4.1.

Measutd

had envr cmss-sectwns for (a)

5 Vnormal opemtwn and (b) 2 Vdata mtentwn

mm% t$ier

[72].

is stuck in depends on which transistor is hit. This mechanism is discussed further in a later section. Typical results from heavy ion irrtidiation are shown in Figure 4.1 [72]. In this experiment M SRAMS were exposed to a nominal ion fluence of 2 x 106 particles/cm2. 0.75 cmz, this resulted in a total particle count of 1.5 x 106 ionslchip.

1

Since the chip area was

The hard emor cross-section

shown in Figure 4.1a was obtained with the power supply set to 5 V (normal operation).

The

resulting hard error cross-section is about 1D6 to I@ cmz. This result indicates that about 1 to 100 stuck bits result per million incident ions - regardless of the linear energy transfer (LET) in the range tested.

The hard error cross-section

shown in Figure 4. lb was obtained with the power

supply set to 2 V (data retention mode)., At this bias condition, hard emors only occur at the highest

IV-45

..

!

. .. .

..

106 105 u)

z z

104

3

103

‘5 *

102 101

100 .-

102

101

103

Data Retention Time [s] Figure 4.2. The data retention time distribution for an unirradiated 4M DRAM after [14].

LET tested. The difference between Figures 4. la and 4. lb indicates that there is a power supply bias dependence for this phenomenon. 4.1.2.

Micro-Damage

or SEDR Failures

In 1994, hard errors in 4M DRAMs were reported by Swift et al. [ 14]. The definition of hard error for DRAMs in the initial investigation was a cell with a data retention time of less than 1 ms (considerably

below the manufacturer’s

specified value of 16 ins). It was first believed that the

mechanism responsible for these errors was the micro-dose failure seen in the SRAMS. A subsequent high temperature anneal did not reduce the number of hard errors, indicating that the mechanism responsible for this type of error was not due to threshold voltage shifts induced by trapped charge in the oxide. Since the data retention time is a key parameter in DRAM reliability, it is used as the hard error failure criteria.

The retention time distribution for an unirradiated 4M DRAM is shown in

Figure 4.2. Each data point in Figure 4.2 is obtained by writing data into the DRAM, and then after the specified time has elapsed, the number of lost bits is recorded.

Note that it takes about 12

seconds for the first bit to be lost and hundreds to thousands of seconds for all the data to be lost. In performing data retention measurements,

it is possible for either state of the DRAM cell to be lost

(i.e., either 1‘s or O’s can be lost). For the purpose of this discussion,

1‘s are defined to be the

DRAM cell state that reads out as if no charge were stored in the cell, and O’s are defined to be the DRAM cell state that reads out charge storage. In further investigations by Swift et al. [14], the data retention time for O’s was separated from the data retention time for 1‘s. The results appear in Figure 4.3, where the number of lost bits versus retention time for both O’s and 1‘s following irradiation with gold (Au) ions is shown. The

IV – 46

106 Lost Ones

105 co

“~

104

t—————

Lost Zeros f h’————

‘6

102

# 101

100

E

OKI 4Mb DRAM (std)

10-6

Spec

(300

ms) \

10-4

i

1(’)-2

100

102

Data Retention Time [s]

Figure 4.3. The data retention time distribution for 4 M DRAM with lost O’s and lost 1 k seperated ajler [14].

105 m “;

104

G ~ 103

n

I

I

Lost Ones

I

I I

I

OKI 4Mb DRAM (std)

~

Lost Zeros

~

102 101

1(’)0 —

I

10-6

1

1

J

(300 ms) 7

Spec

t-

~ I I 1

I

10-4

I

10-2

I

I

I I

I

I

I 1(’)0

I 102

Data Retention Time [s]

Figure 4.4. The data retention time distribution for 4 M DRAM with lost Ok and lost 1‘s seperated, and the effect of double counting eliminated ajier [14]. IV-47

106

_

01, Large Angle, O’s ● Au, Normal, O’s O Au, Large Angle, O’s ■ Au, Normal, 1‘s ❑ Au, Large Angle, 1‘s

I I I

$$( i

300 ms)

100 — 10-6

10-4

10-2

100

102

Data Retention Time [s]

Figure 4.5. The angular dependence of the incident ion beam on data retention times for 4 M DRAM after [14].

behavior of this data led Swift, et al., to believe that some data was counted twice (e.g., some bits were losing both O’s and 1‘s). When duplicated bits were eliminated, Figure 4.4 resulted. With the data properly accounted for, there is a clear distinction between lost O’s and lost 1‘s. Note the similarity in the distribution of data retention times for the lost O’s in Figure 4.4 and the distribution seen in Figure 4.2 (unirradiated). diation, the mean retention time is reduced.

The distribution is the same, but following irra-

This trend is similar to that seen when DRAMs are

exposed to total-dose irradiation [73]. This phenomenon occurs because as the total dose increases, the threshold voltage of the pass transistor decreases.

The leakage current increases through the

pass transistor, and the stored charge leaks out more quickly. For this reason, lost O’s are attributed to micro-dose failure. The distribution either the distribution

of data retention times for the lost 1‘s in Figure 4.4 is very different from for the lost O’s or the unirradiated

distribution.

The distribution

of data

retention times for lost 1‘s is almost constant over all retention times. The mechanism for lost 1‘s is clearly different from that for lost 0’s. Lost 1‘s are attributed to micro-damage

or SEDR failure.

The angular dependence of the incident ion beam on data retention times was also investigated by Swift et al. [14].

The results are shown in Figure 4.5. Note that irradiation with iodine (I) ions

resulted in no micro-damage,

but irradiation with much heavier gold (Au) ions did. In general, for

a given fluence, the high angle irradiation impacts more cells with micro-dose retention time deg-

IV – 48

Vdd

lost ones

lost both

lost zeros (@lOsec)

5.5 5.0 4.5

326,630 153,844 8,971

32,600 12,463 995

120,676 160,552 245,735

Table 4.1. Bias dependence of the data retention time distribution ajler [14].

radation, while the normal incident irradiation causes more than twice the number of micro-damage hard errors. The bias dependence on data retention times was also investigated by Swift et al. [14]. The data is presented in Table 4.1. Note that an increase in bias increases the micro-damage ity, while reducing the micro-dose susceptibility. dose susceptibility a proportional 4.2.

susceptibil-

Swift et al., maintain that the reduction in micro-

is probably due to reduced sense amp margin at lower voltages combined with

reduction in the charge stored in a cell’s capacitor.

Physical Modeling

4.2.1

Micro-Dose Modeling To understand the physical mechanism that lies behind micro-dose hard errors, it is helpful to

study the four-transistor

(4T) configuration

that makes up the standard SRAM cell. As shown in

Figure 4.6, a typical SRAM cell contains two poly-Si load resistors and four n-channel transistors. The heavy ion upset of this cell is well understood and was first explained by Diehl [74]. In singleevent upset (SEU), if either node A or B in Figure 4.6 is struck by a heavy ion while it is in a high state, the resulting transient current can pull the node low. The node is then erroneously low for a period of time that is governed by the choice of load resistance. The cell eventually recovers to the correct state; but if the cell is read before the correct level is restored, an incorrect reading may

result. The micro-dose hard error mechanism is explained by Oldham et aL to be closely related to the SEU phenomenon

[13]. They propose that if the threshold voltage of either of the four transis-

tors that make up the SRAM cell reduces to the point that corresponding leakage currents are about 1 pA or more, then the bit will be stuck. (In typical lM SRAMS, the load resistors limit the current that can flow to about 1 pA [75]).

IV – 49

B

I N2 (Off)

WL

*

N3 (On)l

WL

Vss

Figure 4.6. Typical SIMM cell with four transistors and two poly-Si load resistors.

A physical analysis of the charge collection and trapping at the Si-Si02 interface following a heavy ion strike was performed [13]. An ion strike will create a few hundred to a few thousand interface-trapped

holes in a roughly circular spot 200 to 300 nm in diameter. This charge is suffi-

cient to reduce the threshold voltage of the corresponding threshold voltage shift (particularly

transistor by tens of millivolts.

This

after multiple strikes in close proximity), is large enough to

increase the leakage current by 1 pA or more. An increase in the leakage current of this magnitude makes the leakage current comparable to the on-state current. This current imbalance can be sufficient to permanently 4.2.2

Micro-Damage

latch (or stick) the cell in a particular memory state. Modeling

The physical mechanism for micro-damage

hard errors is not clearly defined at this point in

time; therefore, there are no robust physical models available. may possibly lend some insight into the nature of micro-damage that much of the experimental (SEGR) phenomenon bias dependence;

However, the experimental hard errors. Swift

et al.,

trends suggest

data points to a mechanism similar to the single-event gate rupture

observed in power MOSFETS [14]. The supporting data are: (1) the strong

(2) the decrease in susceptibility with increasing angle of the ion strike; (3) the

sharp decrease in susceptibility

with decreasing atomic number; and (4) the non-additive

ion strikes in close proximity.

IV – 50

nature of

Lx (~)

Initial N(charges)

Applied Field

Nominal Trapping

Number Trapped

126 124

(Vlcm)

200 180

240 216

2.OX1O5 2.2X105

50% 50%

150 125

100

180 150 120

2.7x1OS 3.3X105 4.OX1O5

15% 8% 5%

33 12 9

75

90

5.4X105

<170

0

Table 4.2. Estimating the change in trapped charge at the Si-SiOz inte~ace as afin.ction of oxide thickness.

4.3.

Reducing

Single-Event

Dielectric Failure Susceptibility

At first glance, one might think that the drive toward scaling to smaller geometry devices would make the micro-dose failure mechanism more likely to occur. Oldham et al., suggest that there are three factors at work that will reduce or even eliminate micro-dose failures in SRAMS [13]. First, the four transistor-resistive

load SRAM cell is expected to be phased out of the industry.

The trend is to use a thin film transistor (TFT) as an active load, rather than the poly-Si resistors. The benefit is that the on current is several orders of magnitude greater than the off current, making picoampere increases in leakage nonconsequential. the charge trapping efilciency significantly.

Second, thinning of the gate oxide will reduce

Computations

were performed to estimate the change

in trapped charge at the Si-Si02 interface as a function of oxide thickness [13]. The results are summarized

in Table 4.2. Third, a 64M DRAM has been developed that has a built in self test

(BIST) and self repair (BISR) [76]. The DRAM software tests for failed bits, and then those locations are not used any more. Since there is no definitive model for micro-damage

hard errors, speculation regarding hard-

ening solutions has been limited. If the phenomenon is indeed intimately related to SEGR, then a slight thickening of the oxide would help alleviate this problem; however, this is probably not a viable solution in view of current industry trends.

IV-51

5.

SINGLE-EVENTLATCHUPm CMOS

Dramatic changes have occurred in integrated circuit technology during the last twenty-five years that have increased the number of active transistors on a single chip by nearly five orders of magnitude [77-78]. Reduction of minimum feature size from approximately minimization

of device-to-device

separation have been key factors in the move towards higher

The improvement

density integrated circuits. without a trade-off, however.

6 ~m to 0.35 ~m and

in computational

ability per chip does not come

Highly scaled integrated circuits are more susceptible to radiation-

induced latchup than their lower density counterparts [12]. It is possible for latchup to be initiated by electrical transients on input or output lines, elevated temperature, or improper sequencing of power supply biases [12, 79]. Most manufacturers are concerned about preventing latchup that is initiated this way. Latchup can also be initiated by energetic particles (heavy ions and even protons) that pass through sensitive regions of the device structure.

This type of latchup is called single-event latchup (SEL). Regions that are resistant to

electrically-induced

latchup may still be sensitive to SEL. For this reason, unhardened commercial

electronics that have been designed to be immune to electrically-induced

latchup during normal

operation may be vulnerable to SEL when operated in the natural space radiation environment. Many of these issues have recently been reviewed by Johnston [12]. SEL has been an important technological problem for many years. Despite this recognition, there have been few systematic studies performed to relate SEL dependencies to device technology and layout.

Furthermore,

there have been few systematic studies on the internal regions of com-

plex devices that are responsible for SEL, because diagnostic tools are not readily available that can be used within the vacuum chambers required for such testing [12]. For these reasons, SEL is typically related to electrically-induced periments

latchup through computer modeling and pulsed-laser

[12]. In the remainder of this section on SEL, the various experimental

ex-

testing tech-

niques are discussed, physical modeling techniques are discussed, and finally, methods used to reduce SEL susceptibility

are discussed.

IV – 52

5.1. Experimental

Status

5.1.1. Testing Methods Heavy ion SEL testing is done in a vacuum system, using devices without package lids. The packages are delidded to allow the devices to strike the surface and penetrate as far as possible into the active device regions.

The basic approach is very similar to the approach used for standard

single-event upset (SEU) testing [5]. According to Johnston, the major changes that must be made to SEU test methods for SEL testing areas follows [12]: (1)

provision of a suitable way of detecting Iatchup and shutting down power within a short time interval;

(2)

provision of temperature control within the experimental

chamber up to the

maximum expected device operation temperature; (3)

give careful attention to incident ion range;

(4)

account for the finite dead time required to restore power to the device after Iatchup when computing the SEL rate;

(5)

circuit biasing conditions must be selected that take latchup processes into account (worst-case conditions for SEL maybe different from worst-case conditions for SEU); and

(6)

the power distribution

and grounding scheme must be free from excessive

inductance or ringing, and it must allow latchup to proceed once it is triggered. 5.1.2.

~pical

Data

Single-event upset is often characterized by a step-function, with a steep slope corresponding to the threshold LET that rises to a saturation level that corresponds Single-event

latchup (SEL) cross-sections

to the SEU cross-section.

behave differently in two ways.

First, since Iatchup

triggering depends on the resistance between the ion strike location and the well contact, at the threshold LET only ion strides near the anode can trigger latchup. strikes further away from the anode can also trigger latchup.

For higher values of LET, ion

This causes the cross-section

to

gradually increase with increasing LET until it approaches the entire well area (as opposed to an abrupt threshold seen in SEU testing).

Secondly, the cross-section

never truly saturates because

above the threshold LET level, charge diffusion from regions outside the well also contributes to the triggering process. This further increases the effective area involved in triggering latchup. At still higher levels of LET, cathode triggering can also occur - further increasing the effective area. These cause the latchup cross-section

to gradually increase and prevent true saturation.

IV – 53

A typical

10-3 10-4 10-5 10-6 10-7

P

10-8

o

I

I

I

10 20 30 40 LET [MeV-cm2/mg]

50

Figure 5.1. An example of a latchup cross-section for a bulk CMOS SRAM ajler [12].

1(’)-3

10-5

10-6

10

12

14

16

Fe Ion Range in Si

18

20

[pm]

Figure 5.2. An example of a latchup cross-section versus ion range for a bulk CMOS device after [12].

IV – 54

Iatchup cross-section

is shown in Figure 5.1 for a bulk CMOS SRAM. An alternate way to illus-

trate the latchup cross-section

is shown in Figure 5.2. In Figure 5.2, the latchup cross-section

versus ion range is given. This illustrates that other factors besides the energy of the incident ion can affect the sensitive areas of the device.

5.2.

Physical Modeling Latchup is a low-resistance phenomenon that can occur in p-n-p-n semiconductor structures

in which the middle junction is reverse biased and the other two junctions are forward biased. This four-layer structure is regenerative in nature, i.e., a mechanism exists that can regeneratively

in-

crease internal currents to very high values once triggered. Atypical p-n-p-n structure is shown in Figure 5.3. Note the two interconnected parasitic bipolar junction transistors (BJTs) inherent to the p-n-p-n structure.

The two parasitic BJTs are responsible

for the regenerative

mechanism

that

results in latchup. The I-V characteristics

of such a four-layer structure that is susceptible to latchup is shown in

Figure 5.4. There are three distinct regions shown in Figure 5.4: the forward blocking region, the (2N region, and the negative resistance region.

Once the break-over voltage is surpassed, the de-

vice leaves the forward blocking region, and passes through the negative resistance region to the ON region.

Transient currents within the p-n-p-n structure then increase to a level dictated by

external circuitry.

J-

v

=1

I

?

rsl

‘bl

rs 1

. Figure 5.3. A typical p-n-p-n structure used for latch-up modeling ajier [12].

IV – 55

p-substrate

~

k

3

Forward

u lH

------

Breakover

L I I I I I

Voltage

VH

Figure 5.4. Current-Voltage characteristics for the four-layerp-n-p-n

structure that is vulnerable to latch-up.

If the operating point is such that the device current is higher than the holding current, ZH,and thevoltage

isgreater tianthe

holding voltage, V~,latchup ismaintained.

Inorder toeliminate

the

latchup condition, it is necessary to disconnect the power supply. If power is not removed quickly enough, catastrophic failure may occur from excessive heating in active devices, or failure of metallization or bond wires [80-81]. For Iatchup to occur, it is not necessary to apply a bias in excess of the break-over voltage. Any condition that places operating point in the ON region of Figure 5.3 can trigger latchup.

An

energetic particle (heavy ion or proton) that passes through the p-n-p-n structure may turn on either of the two parasitic bipolar junction transistors (BJTs). The resulting operating point of the p-n-pn structure may then result in a Iatchup condition.

Latchup that is triggered after a heavy ion or

proton traverses the p-n-p-n structure is called single-event modeling SEL called the two-transistor 5.2.1

‘Ilvo-’llansistor

latchup (SEL).

A starting point for

model will now be discussed.

Model for Latchup

The first model developed to explain the latchup phenomenon is the two-transistor

model by

Fang and Moll [82]. The two transistor model is shown in Figure 5.5. Note that a vertical pnp BJT results from the p-source (or drain) diffusion used for p-channel MOS (PMOS) devices within the well, the n-well, and the p-substrate.

Also note that a lateral npn BJT results from the n-well, the p-

IV – 56

— al I

v

A

r~l

‘bl

rs

p-substrate

{ —

Figure 5.5. The two-transistor

model usedto help explain the latch-up phenomenon after [12].

Process

Vertical transistor gain

Lateral transistor gain

lH normal [pA/pm]

VH [v]

2P, bulk

250 at 0.1 mA 55 at 1.0 mA

3.4 at 0.1 mA 3.7 at 1.0 mA

6.5

1.1

1.2P, bulk

35 at 0.1 mA 12 at 2.0 mA

5.1 at 0.1 mA 7.8 at 2.0 mA

9.0

1.2

1.2p, epi

60 at 0.1 mA 43 at 1.0 mA

4.0 at 0.1 mA 3.3 at 1.0 mA

220.0

2.0

Table 5. I. Typical BJTparameters for a variety of CMOS processes. Included are the holding current and holding voltage required to sustain latch-up in the p-n-p-n structure after [12].

IV – 57

substrate, and the n-source (or drain) diffusion used for n-channel MOS (NMOS) devices within the substrate. For a bulk complementary

MOS (CMOS) process, the gain of the vertical pnp transistor, ~v,

can be in the range of =30-100, and the gain of the lateral npn transistor, fl~, can be in the range of =2-20 [12]. ~pical

parameters of the parasitic BJT structures are given in Table 5.1 for a variety of

CMOS processes.

Included in Table 5.1 are values for the holding current, ZH, and the holding

voltage, VH, required to sustain the latchup condition. In Figure 5,5, it is evident that the two parasitic BJT structures are interconnected

such that the

collector current of each BJT feeds the base cument of the other BJT. This positive feedback configuration

(an increase in pnp collector current gives an increase in npn base current - the result-

ing increase in npn collector current gives an increase in pnp base current, etc.) is the key to triggering the latchup mechanism.

If the overall gain of the p-n-p-n structure is high enough, any pertur-

bation (e.g., an energetic particle strike) that turns on one of the parasitic BJT structures can trigger latchup. A first order requirement

on the overall gain of the p-n-p-n structure necessary to trigger

latchup is ~v ~~ >1 [79]. This first order criterion does not take into consideration

any of the

resistances shown in Figure 5.5. When the effects of the well resistance and the substrate resistance are included, a much higher gain product is required to trigger latchup. The more refined criterion is given by: pvpL>

lRS$ v ~ ~ , A– RW

1A+

(1)

where 1A is the anode current, IRS is the substrate current, and ZRWis the well current [12]. The substrate current level depends on the gain of the vertical BJT, arid the well current level depends on the well geometry and contact spacing.

In most cases, the gain product of the parasitic BJTs is

large enough to allow latchup. The parasitic shunting resistances act to reduce the current regeneration and help to circumvent latchup in devices with a gain product that would ordinarily result in latchup. 5.2.2.

Charge Collection When an energetic particle passes through the device structure, electron-hole pairs are gener-

ated along the track length. The manner in which this charge is coll~ted

is important in under-

standing latchup behavior. There are two basic charge collection mechanisms:

drift and diffusion.

The amount of charge collected by drift often exceeds the amount deposited within the volume of the ionization track through the equilibrium depletion region. This increased drift collection mechanism is called funneling, and the region of the track involved in drift collection is called the funnel

IV-58

B

PROMpT (Q. +

ICR

‘F)

c“’)

0.2

o

0.4

1

10

100

TIME (ns)

Figure 5.6. Illustration of funneling and difision [15].

I $ ,,, ,11

5

r ,,, ,,,

mechanisms for churge collection following an ion strike after

11

,,*, , , ,ITml

4-

g3

“

~2

.

f

/

/

/

/

, ‘,8,*I ,

,n-1-m

Bulk process He ------/

-

Epitaxial prooess

/

1-

0 ~~-i2

,.-10

10-8

f@

Time (s)

5.7. Three-dimensional substrates after [12].

Figure

modeling used to calculate the time-dependence

Iv – 59

of co!lected chacge in diodes with n-

[83-84]. Carrier densities in excess of the surrounding majority carrier levels (i.e., high injection) are necessary for the funneling mechanism.

When carrier densities drop below the level required

for funneling, any remaining charge in the depletion region is collected by drift and any charge outside the depletion region is collected by difision. There are a couple of important differences between the funneling mechanism collection and charge collection by diffusion. track onto the hit node.

for charge

Funneling directs the collected charge along the ion

Diffusion can distribute the deposited charge along many nodes.

This

phenomenon is illustrated in Figure 5.6 [84], where the charge collected by funneling and diffusion is shown versus radial distance from the strike. Also, since funneling is a drift process, charge is transported more rapidly by funneling than by diffusion. used by Dodd, et. al., to calculate the time-dependence

Three-dimensional

modeling has been

of collected charge in diodes with n-sub-

strates [85]. In this work they showed that for more heavily doped substrates (typical of submicron CMOS devices), drift collection could occur as long as several nanoseconds after the ion strike, and that drift and diffusion components were comparable in such structures.

Typical results from that

work are shown in Figure 5.7. Analytical forms of the charge collection mechanism are given in [84, 86-89], and numerical simulation studies of the charge collection mechanism are given in [9093].

Figure 5.8. A typical test-structure geometry for studing latchup ajier [12].

IV -60

5.2.3.

lliggering

SEL

Atypical test-structure geometry for studying latchup is shown in Figure 5.8 [12]. The important dimensions shown include the spacing between the anode and cathode (affects parasitic BJT gain), and the distance between the well and substrate contacts (determines shunting resistances).

values of parasitic

Single-event latchup (SEL) is triggered when one of the two parasitic BJTs

is turned on following an energetic particle strike. The p-n-p-n structure can be triggered into SEL in two ways: anode triggering (the vertical transistor is turned on first), and cathode triggering (the lateral transistor is turned on first). In a typical CMOS process, more charge is required to trigger the lateral BJT than the vertical one - making anode triggering the more sensitive SEL mechanism [94]. Anode triggering of SEL involves four different steps that will now be discussed [12]. First, the transient current generated by the energetic particle strike sets up a transient current in the wellsubstrate junction.

The current flows from the well contact to the substrate contact resulting in a

voltage drop within the well that depends on the distance from the ion strike location to the well contact (the further from the well contact - the higher the voltage).

Second, if the voltage drop is

sufficient, the vertical transistor becomes forward biased and produces a much larger current due to its gain that flows from the anode to the substrate.

Third, the voltage drop that results from the

increased current flow (second step) forward biases the lateral transistor causing it to turn on. Once the second transistor turns on, the regenerative current mechanism begins. Fourth, the regenerative current mechanism causes both parasitic transistors to enter the saturation region of operation. The structure remains latched until the power supply is interrupted. gering mechanism

Numerical simulations of the trig-

indicate that the subtleties of the currents involved more complex than that

outlined here, but the essence is the same [95-96]. 5.2.4.

Temperature Dependence of SEL SEL exhibits a very strong temperature dependence [97-98]. Figure 5.9 shows the SEL tem-

perature dependence on (a) the test structure and (b) a 64 K SRAM [98]. The threshold LET for SEL drops by a factor of two and the SEL cross-section highest temperature compared to room temperature.

(or sensitive device area) increases at the

The decrease in threshold LET is due to two

properties of the parasitic BJT structures: the = -2 mV/OC change in base-emitter voltage, VBE; and the increase in well resistance at elevated temperature.

The increase in the SEL cross-section

is due

to the decrease in threshold LET. As the threshold LET drops, more of the well area can contribute to the cross-section at a given LET. Since it is possible that some devices that don’t exhibit latchup at room temperature may exhibit latchup at elevated temperatures, the temperature dependence of SEL is important and should not be overlooked.

IV–61

,.

10-3

F

I

saturation cross-section

~:

>>

0 G ,()-6

~

10

o

20

30

O

10

5

15

20

25

LET [MeV-cm?lmg]

LET [MeV-cm?mg]

Figure 5.9. The single-event latchup temperature dependence on (a) the test structure and (b) a 64 K SRAM after [12].

5.2.5.

Holding Current and Voltage

The holding

current,

ZH, and holding voltage, VH, are generally much easier to model than the

SEL triggering mechanism.

The values for ZHand VH do not depend on how the latchup condition

is triggered, so models for ZHand VH that have been developed for electrically-induced often used by the radiation effects community.

latchup are

In general, IH and VH both increase as the spacing

between parasitic BJT is increased. In typical CMOS structures most of the current through the p-n-p-n parasitic structure flows from the anode to the substrate contact, making IH very sensitive to substrate properties.

The

holding current in epitaxial structures is much greater than that of bulk structures. This is due to the lower resistance of the bulk substrate decreases the parasitic resistance of the lateral transistor, and because the epitaxial structure lowers the transistor gain. It has been shown that the holding current is =5-10 times greater for epitaxial structures (p-substrates) increased significantly,

VH is

[99-100].

Even though ZH can be

usually the more effective parameter to monitor. This is because, in

most circuits sufficient current is available from the power supply to support latchup, even if ZHis very high. Designing internal structures with the holding voltage higher than the available power supply voltage is away to prevent SEL. If the holding voltage cannot be maintained, then the latch cannot be sustained.

Chatterjee et al., have shown that the holding voltage for epitaxial structures scales as

Lltepi, where

L is the anode-cathode spacing of an n-well epi process, and tePi is the thickness of the

epitaxial layer [101]. A larger anode-cathode

spacing and a thinner epitaxial layer will result in a

higher holding voltage. The holding voltage can also be affected by choices in the process.

IV – 62

Thin, retrograde wells

(have a much higher doping level near the bottom of the well) have a much lower sheet resistivity.

The lower sheet resistivity acts to increase the holding voltage of the structure [102-103]. Trench isolation has also been shown to be an effective means to increase the holding voltage [104- 105]. It is possible to eliminate latchup by using oxide isolation rather than junction isolation; however, technical difficulties in producing large-scale devices have limited the development of this technology. 5.3.

Reducing SEL Susceptibility To

summarize this section, possible ways of reducing SEL susceptibility will be reviewed.

The threshold LET for SEL drops and the SEL cross-section (or sensitive device area) increases at elevated temperatures compared to room temperature. So, to reduce the sensitivity to latchup, the device should not be operated at elevated temperatures. The most effective means to reduce or eliminate SEL susceptibility is to increase the holding voltage higher than the power supply voltage. This can be accomplished by careful layout, through the use of a thin epitaxial layer, or by using dielectric isolation rather than junction isolation.

IV-63

-,

.!

6.

Sumww In this Short Course, catastrophic single-event phenomena in the natural space radiation envi-

ronment have been reviewed. Single-event burnout (SEB) of power MOSFETS and power BJTs, single-event gate rupture (SEGR) of power MOSFETS, single-event dielectric failure of SRAMS and DIL4.Ms, and single-event latchup (SEL) of CMOS technologies have been discussed.

For

each of these phenomena laboratory testing procedures, physical models, and possible hardening solutions have been presented. As devices continue to scale to greater complexities, some singleevent phenomena will no longer be of concern; however, challenges for developing electronic devices immune to catastrophic single+vent effects will remain.

7.

ACKNOWIXDG~

The authors would like to thank the following individuals for technical insights, guidance, and

useful discussion of topics related to these Short Course Notes: Ron Schrimpf, Mark Allenspach, Johu Brews, Marie-Catherine Calvet, Philipp Calvel, Lew Cohn, Charles Dachs, Dave Emily, Jean Gasio~ Jakob Hohl, Allan Johnston, Roc& Koga, Ken LaBel, Isabelle Mouret, Jean-Marie Palau, Ron Pease, Dale Platteter, Frank Roubaud, Piene Taste4 Jeff Titus, Frank Wheatley, and T&l Wrobel. Over the course of several years, research on SEE in power devices at the University of Arizona has been sponsored by the Defense Nuclear Agency, NSWC-Crane, Espace, and A&ospatiale.

We greatly appreciate the encouragement

and our colleagues.

IV-64

NASA-Goddar4

Alcatel

and advice of our sponsors

8.

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M. Allenspach, I. Mouret, J.L. Titus, C.F. Wheatley Jr., R.L. Pease, J.R. Brews, R.D. Schrimpf, and K.F. Galloway, “Single-Event Gate-Rupture in Power MOSFETS; Oxide Thickness Dependence and Computer Simulated Prediction of Breakdown Biases,” IEEE Trans. ZVuc.Sci., vol. NS-42, pp. 1922-1927, 1995.

67.

Silvaco International,

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I. Mouret, M. Allenspach, R.D. Schrimpf, J.R. Brews, K.F. Galloway, and P. Calvel, “Temperature and Angular Dependence of Substrate Response in SEGR,” IEEE Trans. NUCL Sci., vol.

41, pp. 2216-2221,

Model of the MOSFET,” Solid-State Electronics, vol. 21, pp.

“ATLAS: Device Simulation Software,” 1995.

“ATHENA:

2D Process Simulation Software,” 1995.

1994.

69.

M. Allenspach, C. Dachs, G.H. Johnson, E. Lorfevre, R.D. Schrimpf, J.M. Palau, J.R. Brews, and K.F. Galloway, “SEB and SEGR in N-Channel Power MOSFETS,” IEEE Trans. NUCL Sci., vol. 43, to be published, 1996.

70.

T.R. Oldham and J.M. McGarrity, “Ionization of Si02 by Heavy Charged Particle,” IEEE Trans. Nucl. Sci., vol. NS-28, pp. 3975, 1981.

71.

R. Koga, W.R. Crain, K.B. Crawford, D.D. Lau, S.D. Pinkerton, B.K. Yi, and R. Chitty, “On the Suitability of Non-Hardened High Density SRAMS for Space Applications,” IEEE Trans. NUCL Sci., vol. NS-38, pp. 1507, 1991.

IV – 69

!,

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C. Dufour, P. Gamier, T. Carriere, J. Beaucour, R. Ecoffet, and M. Labrunee, “Heavy Ion Induced Single Hard Errors on Submicronic Memories,” IEEE Trans. Nucl. Sci., vol. NS-39, pp. 1693, 1992.

73.

D.C. Shaw G.M. Swift, D.J. Padgett, A.H. Johnston, “Radiation Effects in Five Volt and Advanced Lower Voltage DRAMs,” IEEE Trans. Nuc1. Sci., vol. NS-41, pp. 2452-2458,1994.

74.

S.E. Diehl-Nagle, “A New Class of Single-Event 31, Pp. 1145, 1984.

75.

T. Hirose, “A 20-ns 4-Mb CMOS SRAM,” IEEE J. Sol. St. Circuits, vol. 25, pp. 1068, 1990.

76.

A. Tanabe and e. al., “A 30-ns 64-Mb DRAM,” IEEE J. Sol. St. Circuits, vol. 27, pp. 1525, 1992.

77.

P.K. Chatterjee and G.B. Larabee, “Gagibit-Age Microelectronics and Their Manufacture,” IEEE Trans. on Very Lurge Integration Systems, vol. 1, pp. 7, 1993.

78.

C. Hu, “Future CMOS Scaling and Reliability,” Proc. of the IEEE, vol. 81, pp. 682, 1993,

79.

R.R. Troutman, Latchup in CMOS Technology: demic Publishers, 1986.

80.

N. Khurana, “Pulsed Infrared Microscopy for Debugging Latchup on CMOS Product,” Proc. of 1984 IEEE International Reliability Symposium, pp. 122, 1984.

81.

C. Canali, F. Corsi, M. Muschitiello, and E. Zanoni, “Infrared Microscopy Study of Anomalous Latchup Characteristics Due to Current Redistribution in Different Parasitic Paths,” IEEE Trans. Elec. Dev., vol. ED-36, pp. 969, 1989.

82.

R. Fang and J. Moll, “Latchup Model for the Parasitic p-n-p-n Path in Bulk CMOS,” IEEE Trans. Elec. Dev., vol. ED-31, pp. 113, 1984.

83.

C.M. Hsieh, P.C. Murley, and R.R. O’Brien, “A Field-Funneling Effect on the Collection of Alpha-Particle-Generated Carriers in Silicon Devices:’ IEEE Electron Device Lett., vol. EDL2, pp. 103-105, 1981.

84.

F.B. McLean and T.R. Oldham, “Charge Funneling in N- and P-Type Si Substrates,” ZEEE Trans. Nucl. Sci., vol. NS-29, pp. 2018-2023, 1982.

85,

P.E. Dodd, F.W. Sexton, and P.S. Winokur, “Three-Dimensional Simulation of Charge Collection and Multiple-Bit Upset in Si Devices,” IEEE Trans. Nucl. Sci., vol. NS-41, pp. 2005, 1994.

86.

G.C. Messenger, “Collection of Charge on Junction Nodes from Ion Tracks,” ZEEE Trans. Nucl. Sci., vol. NS-29, pp. 2024-2031, 1982.

87.

C. Hu, “Alpha-Particle-Induced Field and Enhanced Collection of Carriers,” ZEEE Electron Device Lett., vol. EDL-3, pp. 31-34, 1982.

IV – 70

Soft Errors,” IEEE Trans. Nucl. Sci., vol.

The Problem and Its Cure.

Kluwer Aca-

88.

T.R. Oldham and F.B. McLean, “Charge Collection Measurements for Heavy Ions Incident on N- and P-Type Silicon,” IEEE Trans. Nucl. Sci., vol. NS-30, pp. 4493-4500, 1983.

89.

T.R. Oldham, F.B. McLean, and J.M. Hartman, “Revised Funnel Calculations for Heavy Particles with High dE/dx,” IEEE Trans. Nucl. Sci., vol. NS-33, pp. 1646-1650, 1986.

90.

C.M. Hsieh, P.C. Murley, and R.R. O’Brien, “A Field-Funneling Effect on the Collection of Alpha-Particle-Generated Carriers in Silicon Devices,” IEEE Electom Device Left., vol. EDL2, pp. 103-105, 1981.

91.

C.M, Hsieh, P.C. Murley, and R.R. O’Brien, “Dynamics of Charge Collection from AlphaParticle Tracks in Integrated Circuits,” Proc. Reliability Phys. Con., pp. 38-42, April 1981.

92.

C.M. Hsieh, P.C. Murley, and R.R. O’Brien, “Collection of Charge from Alpha-Particle Tracks in Silicon Devices,” IEEE Trans. Elect. Dev., vol. ED-30, pp. 686-693, 1983.

93.

H.L. Grubin, J.P. Kreskovsky, and B.C. Weinberg, “Numerical Studies of Charge Collection and Funneling in Silicon Devices,” IEEE Trans. Nucl. Sci., vol.NS-31, pp. 1161-1166, 1984.

94.

G. Goto, H. Takahashi, and T. Nakamura, “Modeling and Analysis of Transient Latchup in Double-Well Bulk CMOS,” IEEE Trans. Elect. Dev., vol. ED-33, pp. 1341, 1986.

95.

T. Aoki, “Dynamics of Heavy-Ion Latchup in CMOS Structures,” IEEE Trans. Elect. Dev., vol. ED-29, pp. 292, 1982.

96.

J. Rollins, “Numerical Simulation of SEU-Induced NS-33, pp. 1565, 1986.

97.

W. Kolasinski, R. Koga, E. Schnauss, and J. Duffey, “The Effect of Elevated Temperature on Latchup and Bit Errors in CMOS Devices,” IEEE Trans. Nucl. Sci., vol. NS-33, pp. 1605, 1986.

98.

A.H. Johnston, B.W. Hughlock, and R.E. Plaag, “The Effect of Temperature on Single-Particle Latchup,” IEEE Trans. Nucl. Sci., vol. NS-38, pp. 1435, 1991.

99.

D. Takacs, “Comparison of Latchup in p- and n-Well CMOS Circuits,” IEDM Technical Digest, pp. 159, 1983.

Latchup,” IEEE Trans. Nucl. Sci., vol.

100. E. Sangiorgi, “Two-Dimentional Numerical Analysis of Latchup in a VLSI CMOS Technology,” IEEE Trans. Computer-Aided Design, vol. CAD-4, pp. 561, 1985. 101. A. Chatterjee, “Direct Evidence Supporting the Premise of a Two-Dimensional Diode Model for the Parasitic Thyristor in CMOS Circuits Built on Thin Epi,” IEEE Elect. Dev. Left., vol. 9, PP. 509, 1988. 102. Y. Taur, “A Self-Aligned l-Lm-Channel CMOS Technology with Retrograde n-Well and Thin Epitaxy,” IEEE J. Solid-State Circuits, vol. 20, pp. 123, 1985.

IV–71

103. R.R. Rung, C.J. Dell’Oca, and L.G. Walker, “ARetrograde p-Well for Higher Density CMOS,” IEEE Trans. Elect. Dev., vol. 28, pp. 1115, 1981. 104. H.P. Zappe, “Advanced Techniques for CMOS Performance Enhancement and Latchup Control,” Ph. D., University of California, Berkeley, 1989. 105. P.V. Gilbert, P.E. Crabtree, and S.W. Sun, “Latch-Up Performance of a Sub-O.5 Micron InterWell Deep Trench Technology,” IEDM Technical Digest, pp.731, 1993.

IV -72

1996 NSREC SHORT COURSE

z

SECTION v

DESIGN ISSUES FOR RADIATION TOLEMNT MICROCIRCUITS FOR SPACE

David R. Alexander IWsslon Research Corporation

Design Issues for Radiation Tolerant Microcircuits

in Space

David R. Alexander and David G. Mavis Mission Research Corporation 1720 Randolph Road Albuquerque, New Mexico 87106 Charles P. Brothers and Joseph R. Chavez U.S. Air Force Phillips Laboratory Kirtland Air Force Base, New Mexico 87117

The views expressed in this article are those of the authors and do not reflect the official policy or position of the Department of Defense or the U.S. Government. This work supported in part by U.S. Air Force Phillips Laboratory Contract F29601 -89-C-0014.

v-1

-v. Design Issues for Radiation Tolerant Microcircuits Space

in

David R. Alexander and David G. Mavis Mission Research Corporation 1720 Randolph Road Albuquerque, New Mexico 87106 Charles P. Brothers and Joseph R. Chavez U.S. Air Force Phillips Laboratory Kirtland Ah- Force Base, New Mexico 87117 1.0

Introduction

2.0

Domain of Radiation Tolerant Design Practices The Impact of Radiation Effects on the Microcircuit Design Hierarchy Total Ionizing Dose Affects on Parasitic Elements Single Ion Effects (Latchup) on Parasitic Elements Radiation Response Mechanisms Affecting Transistors Radiation Response Mechanisms for Parasitic Edge Transistors Single Particle Strike Mechanisms Affecting Transistors Total Ionizing Dose Mechanisms Affecting Primitive Cells

3.0 4.0 5.0 6.0 7.0 8.0 9.0

10. 11. 12. 13. 14. 15. 16. 17.

Single Particle Effects Affecting Primitive Cells Total Ionizing Dose Mechanisms Affecting Macrocells Single Particle Effects Affecting Macro-Cells Demonstration of Radiation Tolerance Enhancement Through Design Test Structures for Supporting Radiation Tolerant Design Application of Radiation Characterization Data to Cell Design Performance Characteristics of the Design Tolerant Gate Array Summary 1.0 Introduction

The objective of this short course presentation is to provide an overview of the kinds of design (electrical and layout) issues that contribute to the radiation tolerance of commercial parts and parts fabricated in commercial foundries. The developer of electronics for space applications in the late 1990s is challenged with acquiring microelectronics which will reliably perform his mission without breaking his parts budget or derailing his schedule. He is no longer able to rely on the parts base developed and maintained by strategic weapons systems. Those systems have ended their production phase, and their replacements have generally been postponed for an indeterminate time. Furthermore, there is an ongoing emphasis within the government to reduce costs by eliminating specifications and encouraging the use of parts built with best commercial v-3

practices. The result is a greatly reduced vendor pool for radiation hardened parts and a widening gap between the performance and cost of microcircuits used in commercial electronics and those developed to fimction in a radiation environment. Consequently, the space applications developer is forced to take a much more active role in the evaluation of microcircuits and to accept a much greater risk in parts selection. One view of the parts acquisition process is depicted in the flow chart in Figure 1. It begins with a clear description of the radiation environment to be encountered and functional and performance The radiation environment varies significantly with the requirements of the microcircuits. altitude, inclination of the orbit, and solar activity. More benign environments and shorter duration missions obviously expand the candidates for the application. However, the developer is well advised to first consider the availability of radiation hardened parts even for modest radiation exposures. The savings in characterization testing, data reduction and analysis, and hardness assurance activities can far outweigh any initially perceived differences in item costs. The remaining manufacturers of QML/RHA (Qualified Manufacturers’ List/Radiation Hardness Assurance) [l] [2][3] microcircuits provide products with a legacy of built-in radiation hardness derived from a balanced technology flow which considers design, fabrication, packaging, and testing issues. The resulting components cannot be matched for robust performance in the space environment. In the event radiation hardened parts are not an available option, the applications developer has the alternatives of 1) selecting a commercial part and performing testing to determine its radiation tolerance level or 2) designing a radiation tolerant part. If a commercial part is selected, a radiation test strategy must be developed to determine its tolerance. Many commercial microcircuits have large numbers of terminals, and the selection of a test approach can be a challenging task. An approach based on considering the dominant ftilure mechanisms typical of specific parts of the commercial design can be useful in performing a test which will yield valuable insight into radiation performance of the microcircuit. There are two major risks in selecting a commercial microcircuit for use in space. First, the portions of the fabrication process that determine radiation hardness may not be tightly controlled by the vendor. Hence, the radiation tolerance of commercial parts typically have large standard deviation to mean ratios[4]. A second major risk stems from design and process changes which may be implemented at any time. Either of these may drastically change the radiation tolerance of the part. Indeed, a common industry practice is to bring out a product at a conservative feature size, and then perform a dimension shrink to improve yield and increase the number of die per wafer once a market has been established. Consequently, different revision numbers of the same part can exhibit widely varying radiation tolerance, especially with respect to single event latchup (SEL), which is very sensitive to spacing between elements on the microcircuit. The system developer can reduce these risks by acquiring all his part population from a single processing lot or wafer and by testing enough parts to obtain a valid statistical estimate of the population. Such acquisition strategies may be difficult to implement for small quantity purchases. In addition, this is often hard to accomplish because commercial tracking of parts may not reflect this wafer or even lot information.

v-4

Space Environment

& Microcircuit

No

.

t Yes +

Develop Rad Tolerant Part

I

Perform Hardness

Insert in

PEl_JkE!!4 Figure 1. Simplified Part Selection Flow Chart In the absence of a radiation hardened part and as an alternative to commercial parts, the space application developer may choose to design a radiation tolerant part. This option may be particularly attractive if a commercial function can be combined with application specific circuitry in a single ASIC (application specific integrated circuit) die. Many commercial functions are available in synthesizable VHDL or Verilog models. With appropriate design discipline in the macrocell library, a synthesized circuit can achieve radiation tolerance consistent with the requirements of many space missions. In general, the type of design discipline required trades-off packing density and pre-irradiation electrical performance to enhance radiation tolerance. 2.0 Domain of Radiation

Tolerant Design Practices

As illustrated in Figure 2, traditional radiation hardened microcircuit development has been based on contributions from rad hard processes, rad hard electrical design practices, and rad

v-5

hard layout rules. However, in this presentation, hardening approaches will be restricted to electrical design and layout practices. Only a commercial CMOS process is considered to be available for fabrication. This means that no specific hardening provisions can be relied upon for the gate oxide (GOX), the field oxide (FOX), or the transition region between gate and field oxides (edge oxides). Note however, that the industry trend is toward thinner gate oxides (e.g., 170~ for a 0.8 pm technology) as features scale into submicron dimensions. Since the oxide trapped charge is roughly proportional to tOX-2[5] in this oxide thickness range, its contribution to total ionizing dose degradation becomes less important with advancing technology. This is especially the case since tunneling mechanisms are effective in annihilating trapped charge within approximately 50 ~[6] of the Si02/Si interface. This does not necessarily pertain to interface state creation. No process-oriented provisions for single event effects hardening will be considered. This means that no high resistivity polysilicon is available for inserting high resistance elements in the cross coupling path for memory elements and latches. Also, no retrograde diffision profiles or silicon-on-insulator technology can be relied upon for latchup suppression. However, many commercial technologies are built on wafers with a lightly doped epitaxial (epi) layer on a heavily doped substrate to assist in electrically induced latchup suppression. Often, the use of epi technology is not advertised and can only be discovered by performing a destructive physical analysis on sample parts. Where epi substrates are used, they can be very beneficial in SEL suppression. Although process hardening is not a topic for this presentation, it should be pointed out that even a modest process hardening effort can produce great benefits in developing radiation tolerant parts for space. The chief benefit lies in tightening the distribution of radiation tolerance

Figure 2. Domain of radiation tolerant design practices.

V-6

This will permit less conservative design practices to be used with for the population. subsequent improvements in performance and packing density. The Defense Nuclear Agency programs[7] directed at modest improvements in hardness (Total dose = 50-200 Krad(Si), SEL LET =50- 120 MeV cm2/mg, and SEU LET = 40-65 MeV cm2/mg) in baseline commercial technologies have the potential to greatly benefit satellite applications. Radiation tolerant electrical design practices are related to the organization and interconnection of electrical elements (transistors, diodes, capacitors, and resistors) to perform the required function. Typically, the electrical design is represented by schematics or by the equivalent netlist, which is a textual description of the graphical information in the schematic. In complex microcircuits, the electrical design is depicted hierarchically. The top level describes the information processing organization within the device in terms of macrocell functional blocks and data buses. Lower levels are oriented toward primitive cell interconnections needed to form the functional blocks, and ultimately to transistor-level interconnections required to form primitive cells. Top-level netlists are typically written as behavioral blocks in a hardware description language (e.g., Verilog or VHDL). Intermediate levels may be described in register transfer language (RTL) or as pure structural language in which each macrocell is modeled by its Boolean fimction. Usually, the lowest-level netlist is written in a SPICE format in which each electrical element and node is modeled. Radiation tolerant design practices will be identified at each level of the hierarchy. They should be considered from the inception of the design process in order to be used most effectively. Radiation tolerant layout practices deal with the polygon representation of the microcircuit electrical design. The schematic/netlist description must be translated into entities which can be physically created through the photolithographic and fabrication technology to construct a microcircuit. By restricting the geometrical shapes and dimensions of the electrical elements and controlling the spacing and number of contacts between elements, substantial In general, a microcircuit designed with improvements can be made in radiation tolerance. radiation tolerant design practices will be larger and slower than the same fiction designed with no restrictions. The increased size typically translates to a lower yield and more expensive parts. Also, the complexity of functions which can be fabricated using only rad tolerant design practices is restricted by the die size and operating speed. Most likely, one would not attempt to build a state-of-the-art microprocessor or a large SRAM with rad tolerant design practices, but a moderately complex ASIC function could be appropriate.

3.0 The Impact of Radiation Effects on the Microcircuit

Design Hierarchy

To effectively employ radiation-tolerant design practices, the designer needs a clear understanding of the interactions among radiation sensitive elements at each level of the design hierarchy -depicted in Figure 3. Actually, many of the radiation effects which limit the hardness of a microcircuit are associated with parasitic elements which are typically not considered as part of the design process. These elements are an inherent part of the semiconductor technology chosen, but their influence is often not experienced until they are activated by the radiation environment. One of the major differences between radiation-hardened and commercial fabrication technologies is the attention given to controlling parasitic elements. Two parasitic elements that are particular problems for space applications are (1) field oxide (FOX) N-channel

v-7

transistors which provide leakage paths between adjacent gate oxide (GOX) N+hannel devices and between Vdd and Vss, snd (2) the four-layer (PNPN) SCR (silicon controlled rectifier) devices that consist of P-source/dr@ N-well, P-substrate, and N-source/drain. The parasitic SCR can be turned on by a heavy ion strike and produce a latchup condition that may catastrophically damage the microcircuit. These two effects often constitute the primary failure mectisms for co--ercial microcircuits.

MICROCIRCUIT FUNCTION

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Figure 3. The microcircuit design hierarchy. The radiation effects associated with the GOX transistors also play a dominant role in determining radiation tolerance. Total ionizing dose effects produce both increases in the “offstate” leakage in N-channel devices and changes that tiect the switching point and “on-state” I/V (current/voltage) characteristics of both N-channel and P-channel transistors. A single particle strike can produce an ionization track which generates a current pulse that may temporarily discharge or charge the drain nodes of N-channel and P-channel transistors, respectively. Since transistors form the basic switching elements, changes in their operating characteristics are manifested as variations in performance throughout the microcircuit. The radiation-induced changes in tisistor characteristics and the activation of parasitic elements require the designer of a radiation tolerant part to modi~ the layout and electrical design of primitive logic cells such as gates (NAND, NOR, etc.), latches (D type, J-K etc.), and memory cells. For total ionizing dose, he must consider the changes in propagation delay and V-8

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. . . .

.. . . . .++

,_

imbalance propagation from low-to-high (t@lh) and high-to-low (t@l). He may also limit the fan-in (i.e., the number of inputs to a cell), fan-out (i.e., the number of other cells connected to the output), and the maximum load attached to the output (fan-out load plus interconnect load). Primitive cell types (e.g., multiplexer) which are particularly sensitive to leakage current and/or crosstalk between logic states of adjacent devices may require significant changes in transistor geometry and cell layout for radiation effect mitigation. Similarly, single particle effects usually require changes in primitive cell design. Spacing between elements which constitute potential Iatchup paths may be changed, additional well and substrate contacts may be added, and guard bands may be used. Additional elements such as capacitors and resistors may be added to memory and latch cells to increase the charge associated with a node logic state or to filter the high frequency ionization transient. These restrictions cause the electrical circuit and layout topography of primitive cells for radiation tolerant designs to be much different than those found in commercial implementations. The importance of using radiation tolerant design principles extends to the highest level of the design hierarchy. The organizational structure of the design is affected by preference for such approaches as (1) synchronous designs over asynchronous, (2) logic cell implementations of state machines rather than ROM implementations, (3) limitation of connections to data and address buses, and (4) addition of bits to data path elements to support error detection and correction. Issues associated with post-irradiation timing control make the design of a robust clock driver and clock distribution scheme particularly important to ensure that clock skew problems (i.e., one block of the circuit receiving the clock before another block) do not occur. In general, radiation tolerant design practices for both single event effects and total ionizing dose restrict design flexibility and typically require larger die to perform the same microcircuit function. A few specific examples in the following paragraphs will help to highlight the interdependence of radiation tolerant design practices at all levels of the design hierarchy. 4.0 Total Ionizing Dose Effects on Parasitic

Elements

An illustration of the structure of the parasitic FOX transistor is shown in Figure 4. The leakage paths are formed when positive charge is trapped in the field oxide and inverts the surface of the P-type material[8]. A P-epi technology is depicted in the figure, hence the leakage path is associated with the substrate region. If a N-substrate/P-well technology were used, the leakage would be associated with the P-well. Two types of leakage paths are possible. The first is between the N-well (which is typically connected to Vdd), and an N-plus source (which is connected to Vss). The leakage path connects Vdd to Vss, producing a change in supply current with increasing radiation. Usually, the supply current increases to a maximum value as the trapped charge builds up and then decreases to a relatively constant value as interface states increase, offsetting the trapped positive charge effects. The development of the leakage path is aggravated by polysilicon interconnects overlaying the leakage path region. The pol ysilicon acts as a gate to the parasitic FOX and, if biased at Vdd, produces a field which increases hole trapping. Radiation tolerant design practices should not permit polysilicon to extend over the well-to-substrate boundary. Field oxide leakage paths can also span the N-plus source/drain regions between adjacent N-channel transistors. This will increase the Vdd to Vss leakage, and is particularly problematic v-9

if dynamic logic is used. It will bleed off charge which is used to represent a logic state between refresh cycles. Since this can result in logic errors, radiation tolerant design practices should not permit dynamic logic or logic states that do not swing all the way to the rail voltages (Vdd and Vss). Furthermore, adjacent N-plus source/drain regions should not be allowed without an intervening channel stop. A channel stop is a more heavily doped P-region implanted at the interface between the field oxide and the silicon. The increased doping makes the channel stop region more difficult to invert and effectively breaks the leakage path. Most commercial processes include some type of channel stop or field threshold adjust step to control mobile ion effects. However, the step may not be carefully monitored, and the tendency of the P-type implant (i.e., boron) to be leached out during the field oxide growth process results in considerable variability in lot-to-lot leakage characteristics in commercial microcircuits.

Vdd

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Figure 4. Field oxide leakage path from N-well to N+ source. The results of field oxide leakage characterization of a typical commercial, submicron technology are shown in Figure 5. Prior to irradiation the parasitic field oxide transistor required approximately 15 volts to turn on the leakage path. The turn-on characteristic is clearly degraded at low doses. An accumulation of 10 Krad(Si) produces significant leakage at 5 volts, and 30 Krad(Si) produces leakages which would render the microcircuit inoperable. Field oxide inversion is the dominant failure mechanism in many commercial microcircuits. The failure may be due to supply current greatly exceeding its specification (e.g., SRAM standby current), input and output leakage currents exceeding parametric specification (e.g., output tri-state leakage), or catastrophic fictional failure. Large increases in static supply “current with dose are indicative of field inversion. Since there is an interaction between trapped holes and interface states which causes the supply current to peak and then decrease, the supply current must be monitored at intermediate doses as well as the maximum dose required. For commercial parts, a test sequence with intermediate read points at 5, 10, 20, 40, 80, 160 Krads, etc. is convenient and samples the radiation effects frequently enough to estimate the peak Idd response. To detect logic errors in microcircuits which may contain dynamic logic, the slowest specified clock and refresh rate should be used to allow the leakage path to discharge data nodes. v-lo

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In space radiation environments, the total ionizing dose is built up very slowly. Since there is some compensation of trapped positive charge by interface states, a low- dose rate test or a high dose rate test with room temperature anneal may by more representative of the performance to be expected in the actual space application[9]. However, caution should be exercised in interpreting the data, since the time dependent mechanisms associated with trapped charge annealing and interface state formation in field oxides with low electric fields are not well understood.

5.0 Single Ion Effects (Latchup) on Parasitic Elements The latchup path structure for a P-epi technology is shown schematically in Figure 6[1 O]. The path has been shown in terms of the traditional cross coupled transistor model of an SCR. Under normal bias conditions the P-substrate is held to the lowest potential in the circuit, and the N-well is held to the highest potential. None of the junctions associated with the PNPN structure are forward biased, and the SCR is off. However, an ionization track associated with single particle strike can produce a current transient which will inject charge into either the cathode or anode gate regions[l 1]. The voltage drop associated with this current flowing to either the well or the substrate contacts can be sufficient to forward bias a local portion of the junction. This

v-l]

results in bipolar transistor action that rapidly becomes regenerative as the parasitic SCR turns on. The latch path will conduct until the voltage across the path fidls below the holding voltage, typically Vh, + V=* Since this is a low impedance path and often occurs between adjacent Vdd and Vss contacts, the currents may be large enough to burn out metallization and catastrophically damage the microcircuit. In huge microcircuits, the resistance in the power bus Such an may be large enough to limit the cument to a level below the burnout threshold.

occurrence is called a micro-latch and is often encountered in testing commercial microcircuits. Although the micro-latch is not catastrophic in the sense that burnout occurs within a matter of minutes, its impact on reliability will depend on the cell layout snd metalhzation dimensions. As a general rule, high current density in microcircuit metdli.zation should be avoided if possible.

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Figure 6. Latch path for P-epi CMOS technology (Ochoa and Dressendorfer,

8 1).

Test procedures to determine the susceptibility to latchup of commercial microcircuits must be performed carefidly to ensure that they are thoroughly evaluated. Testing should be performed at the maximum temperature to be experienced in the application, since devices are more susceptible to latchup at elevated temperature. Power supply voltage should be kept at its maximum operational value. The power supply current should be monitored carefully, and the clock frequency should be kept as low as possible so that operating currents do not mask the As noted previously, different revisions of the same microcircuit may be latch currents. implemented using significantly different feature sizes, wafer material, and processing, and hence, have different latchup susceptibility. Care must be taken to ensure that the same version that has been tested is used for the flight parts. There are several design practices which can reduce susceptibility to latchup. A cross coupled transistor model of the parasitic SCR suggests that if the gain product of the parasitic NPN and PNP transistors is reduced below 1 (i.e., ~m~mP < 1) over the possible range of collector curren~ the latchup condition cannot be sustained. Also, if the anode or cathode gate junctions are shorted so that a Vh. cannot be maintained, the path will not latch. This model for latchup maybe overly simplistic for modem microcircuits with small fkature size. Research by

V-12

Sleeter and Enlow[l 1] has suggested a functional relationship between holding voltage, holding current, epitaxial layer thickness, N-plus to P-plus spacing, and doping profiles. For example, Figure 7 contains the results of an analysis for 10 pm spacing between anode and cathode in a typical CMOS process (single well without retrograde). It indicates that an epi thickness less than 3.5 pm may be necessary to maintain holding voltages above Vdd even for 3.3 volt technologies. Their model suggests the drift conduction processes play a more important role than would be suggested by the transistor-based model. However, the design practices employed to reduce susceptibility remain the same. They include (1) increasing the spacing between the Nplus and P-plus source/drain regions and the well edge, (2) adding N-plus guardbands in the Nwell and P-plus guardbands in the P-substrate to reduce the gain of the parasitic transistors and control the potential of the well and substrate in the latch patlz and (3) increasing the number of well and substrate contac~ and decreasing the distance between the contacts and the latch path (see Figure 22 in Section 13).

Latchup Holding Points for Various Epi Thicknesses 1000.0

r

r

100.0

10.0

No epi 1.0

0,1

0

1

2

3

4

Holding

voltage

5

e

7

8

(volts)

Figure 7. Radiation induced shifts if field oxide transistor

characteristics (Sleeter and Erdow, 1992) 6.0 Radiation

Response Mechanisms

Affecting

Transistors

The radiation effects mechanisms affecting the intrinsic MOS transistor include hole trapping in the gate oxide and interface state generational 3]. Positive charge trapping in the gate oxide results in threshold voltage shifts which push N-channel transistors toward depletion mode operation and P-channel devices toward enhancement mode. Interface state buildup shifts both N-channel and P-channel devices toward enhancement and decreases the slope of the

V-13

,..

.

..

.

subthreshold L/V (current/voltage) characteristic. In addition, the mobility of the devices is decreased resulting in a reduction in drain cument as a fimction of gate voltage (i.e., reduced transconductance). These effkcts are readily observable in the pre- and post-imadiation IN characteristics as shown in Figures 8 and 9 which display N-channel and P-channel data from The reader should note that the N-channel commercially processed 0.8~m technology. measurement has been taken on a re-entrant transistor (i.e., an annular gate with no edge). This permits the radiation effixts of the intrinsic gate oxide transistor to be obsenwd independently from the edge efkcts which will be discussed in Section 7.0.

Re-antrant

-1

0

N-channel

in 0.81.LCMOS

1

2

3

Technology

4

5

Gate Voltage (volts)

Figure 8. Total ionizing dose data for a re-entrant N-channel transistor from a commercial CMOS technology. Manifestations of the radiation mechanisms include: (1) increased leakage due to a decrease in the slope of the subthreshold characteristic, (2) time dependent changes in leskage

and drive current as N-channel threshold voltage initially shifts toward depletion mode under the influence of oxide trapped charge aad then toward enhancement mode as interface states buildup, (3) mismatch in N-channel snd P-channel drive current as trapped charge and interfhce states move the P-channel further into enhancement. Ultimately, the changes in the I/V characteristics of the transistors will decrease the frequency of operation aud the functionality of the microcircuit.

V-14

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Subthreshold Characteristic for 0.8 micron P-channel -5 1e-3

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Figure 9. Total ionizing technology.

dose data for a P-channel

transistor

from a commercial

CMOS

To observe the worst case effects of these changes on microcircuit operation, testing must consider the effects of dose, time, and bias on the post-irradiation results[l 4]. In most laboratory testing the dose rates used in accumulating total dose are usually quite high (50 to 300 rad(Si)/s for CO-60 and 104 rad(Si)/s or greater for X-ray irradiation sources). This may be conbasted to typical space irradiation rates of 1 mrad(Si)/s or less. The high dose rates tend to maximize the effects of trapped charge, especially emly in the irradiation cycle. Effects fi-om interface states, which require a longer time to build up, are most observable later in the irradiation. In order to determine the maximum effects of interfme states, a high-temperature anneal (1OO”C for 168 hours is specified in Mil Std 883 Method 1019.4 [15]) is typically performed to significantly reduce the amount of ~sitive trapped charge. The results of such an anneal for both the Nchannel and P-channel transistors can be seen in Figures 8 and 9. The post-anneal characteristics bound the changes expected from interface state effects resulting from lowdose-rate space irradiations. Biasing voltages also significantly affect the post-irradiation characteristics. A positive voltage on the gate with respect to the substrate enhances the sepmation of hole and electron pairs generated by the ionizing radiation and causes the centroid of trapped charge to be located closer to the oxide/siliccm interface where it has the greatest effect on charge carriers in the silicon. Bias voltage effects on trapped chmge and interface states are summmizd in Table 1. V-15

Table 1. Bias Condition Effects on Total Ionizing Dose Mechanisms DeviceType

Max Trapped

Min Interface

Charge

Min Trapped Charge

Max Interface

Terminal

statm

states

NMOS - Gate

Vdd

Gnd

Vdd

Gnd

NMos - Drain

Gnd

Vdd

Gnd

Gnd

NMos - source

Gnd

Vdd

Gnd

Gnd

Gnd

Gnd

Gnd

Gnd

PMOS - Gate

Vdd

Gnd

Vdd

Gnd

PMOS - Drain

Gnd

Vdd

Gnd

Vdd

PMOS- Source

Gnd

Vdd

Gnd

Vdd

PMOS - Substrate

Vdd

Vdd

Vdd

Vdd

NMOS - Substrate

As noted previously, the trend in commercitd CMOS technologies is toward thinner gate oxides for the intrinsic transistors. This translates into improved radiation tolerance since the trapped charge is proportional to the square of the reciprocal of the oxide thickness. However, interface states do not exhibit the same strong correlation and exhibit a complex dependence on post-processing conditions (temperature and atmosphere). Commercial processes may not Consequently, interface state effects show maintain tight control on such conditions. considerable variability from lot to lot. Space systems using commercial parts should design their test program to monitor microcircuit pefiormance changes due to interkce state effects[16].

7.0 Radiation Response Mechanisms

for Parasitic Edge Transistors

As illustrated in Figure 10, MOS transistors are typically designed for a self aligned process in which the polysilicon gate material is deposited over a thin oxide region. The source/drain implant is then performed and fills the region not covered by field oxide and poly. This process is very manufacturable and produces very dense circuits. Unfortunately, the material at the transition between the field oxide and the thin oxide produces a parasitic transistor that is very susceptible to total ionizing dose effects.[17] The silicon dioxide in this region (known as the bird’s beak) is under mechanical stress produced by the dynamics of the oxide growth process and the transition from thin to thick oxide. It is also subject to implant damage from exposure to the heavy sourceklmi.n implants. The transition region oxide is of variable thickness and experiences a relatively high electric field from the combination of poly gate bias and the fringing fields fi-om the source to drain bias. When this region is exposed to ionizing radiatiom

affects the W characteristic increased by approximately increasing doses, more of the leakage will quickly rise to transistor.

significant hole trapping occurs and as shown in Figure 11. At 150 Krad(Si), the edge leakage has three orders of magnitude over its pre-irradiation value. At edge parasitic will become involved in the conduction path, and the become roughly equivalent to the on-state current of the intrinsic

V-16

.,

.

-.

.

BIR=AK “N=AL”

FIELD-OXIDE REGION

REGION CHANNEL REGION POSITIVE TRAPPEDCHARGE INDUCED CURRENT LEAKAGE PATH

Figure 10. MOS transistor cross section indicating charge trapping in the bird’s beak region (McLean and Oldham, 1987).

Conventional

N-Channel

FET (#11)

1 e-3

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1 e-4 1 e-5

z

1 e-6

1 le-14

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Prerad 150K rad Anneal

~

-2-1012345

Gate Voltage (V) Figure 11. Conventional commercial technology 2-edge N-channel transistor exhibiting edge effects induced by total ionizing dose.

V-17

Edge leakage increasing total dose, intinsic Transistor. becomes permanently

effects are typically manifested as a rapid increase in supply current with as the parasitic edge transistors shunt the source-todrain current around the They may also produce fictional failure as the composite N-channel “on”.

Parasitic edge effits

can be distinguished

from field oxide leakage and intrinsic transistor effects by testing transistors of equivalent width in two edge and multi-edge (i.e., paralleled 2-edge transistors) varisnts. Alternatively, two edge transistor characteristics can be compared with re-entrant transistors which have no edge connecting the source to drain. Commercial foundries pay little attention to the characteristics of the edge transition region since the edge parasitic is not turned on in commercial applications. Thus, edge parasitic in commercial devices are quite susceptible to radiation effects, and there is large variability in radiation tolerance since there is little control of the process parameters af%eting hardness. Therefore, edge effect mitigation for commercial processes usually requires layout modification. Three radiation tolerant layout approaches are illustrated in Figure 12. The most effkctive layout uses the re-entrant design for the N-channel transistor which totally eliminates the thin-tothick oxide edge between source and drain. Chily the N-channel requires a re-entrant design since the P-channel does not experience edge inversion. There are several disadvantages to using a re-entrant layout including: (1) increased area requirements in comparison to a 2-edge, (2) increased capacitance (gate and source/drain), (3) difficult width scaling due to comers and differences in inside and outside perimeters, (4) lack of symmetry between source/drain and drain/source characteristics (i.e., not bilateral), and (5) complication in sizing a P-channel tmmsistor with equivalent drive strength. The least intrusive layout mitigation technique is the dog bone design. It widens the poly at the step over the edge. This produces a longer parasitic channel and decreases the leakage cument by changing the effective width-to-length ratio. It also reduces some of the tinging field intensity associated with drain-to-source bias. The net effect is a reduction in leakage current but not an elimination. Other disadvantages include: (1) a decrease in the effective width of the intrinsic transistor, (2) increased gate capacitance, and (3) additional complication in layout. A third layout alternative is the use of nested transistors. It employs a mask-defied source/drain implant region nested inside the thin oxide. One end of the poly may also be nested inside the thin oxide as depicted in Figure 7. In concept, edge leakage is eliminated since only thin oxide interfaces with the source and drain, In practice, edge leakage usually occurs along the edge of the poly to the bird’s beak region and back along the opposite poly edge to connect the source/drain. This is a much longer path length than a normal 2-edge device and significantly delays the onset and magnitude of the leakage current. However, many commercial processes do not include provisions for a nested source/drain. Other disadvantages include: (1) increased capacitance, and (2) reduced circuit density. Edge leakage poses a serious limitation microcircuits, and layout mitigation techniques complexity for increased hardness.

V-18

on the radiation tolerance of commercial require significant tradeoff of area and

Thin oxide boundary _./ a. Conventional

2 edge NMOS

Thin oxide boundary~ b. Nested 2 edge NMOS

Thin oxide boundary / c. Dog bone 2 edge NMOS N+ some

I

Polysilicon gate \

Thin oxide boundary d. Re-entrant NMOS

N+ drain

J

Figure 12. MOS transistor layout alternatives.

V-19

.,

8.0 Single Particle Strike Mechanisms

Affecting

Transistors

At the transistor level, a single ion strike is experienced as a cument transient appearing at the sourcddrah node [18]. If the magnitude of the charge in the transient is sufllciently higl-q the tiormation stored as charge on the node may be lost. The amplitude and duration of the transient is determined by the ion species, its energy, and the fabrication technology of the microcircuit. Experimental and predicted waveforms of single ion strikes on silicon diodes for heli~ silico~ and iron are shown in Figure 13 [19]. A normally incident iron ion of 100 MeV has an LET (linear energy transfer) = 28 MeV-cm2/mg. Since the effective LET scales as sec9 (where 0 is the incident angle of the ion with respect to the perpendicular), the iron ion incident at 45° and 60° would have LETs =40 and 56 MeV-cm2/mg, respectively. These values cover the low end of acceptable SEU and SEL tolerance. While these waveforms represent a good starting point for simulation of SEU in a design, the waveforms in actual commercial CMOS microchcuits may be much different. The shape and amplitude of the transient will be dated by the existence and thickness of an epitaxial layer, the doping profile and depth of the well, and the lateral spacing between adjacent transistors, Consequently, experimental evah.ution of LET thresholds and cross sections is important to determine the SEU tolerance of the design. Testing should be performed on arrays of cells which are typical of the layout geometries to be used in microcircuit designs. Where the designs are based on a cell library (e.g., gate array and standard cell designs), arrays of flip flops can make an effective test structure. Ex amination of the waveforms in Figure 13 reveals the FWHM (W width at half maximum) pulse width to be greater than 100 ps for the fastest transient. Typically, the propagation delay for simple logic gates in submicron CMOS can vary from 50 to 200 ps depending on the design approach used. This means that single event transients can be propagated through combinational logic quite readily. Therefore, the effects of propagated upsets must be considered in the design of the radiation tolerant microcircuit [20]. Several approaches exist which may be considered for mitigating single ion transients for better SEU performance. They begin with selection of a technology with a structure to minimize charge collection. An epi process with the thinnest epi layer and the highest substrate doping is most desirable to reduce fi.umehng effects (i.e., early enhancement of charge collection by the acceleration of charge carriers in the cylindrical ionkmtion sheath by the distorted electrical field from the junction depletion region) [21]. The funneling effat is proportional to LETn (where q is an empirical value between 1 and 1.33) [22] [23]. For an LET of 28, the maximum enhancement due to fimneling will be a factor of 3 (i.e., enhancement= 281’33/28).

An alternate technology selection approach would be to choose an SOI technology. Access to SOI foundries is becoming more generally available to designers. In addition to commercial foundries in Europe, projects by DARPA with IBM and MIT/Lincoln Labs and by Sematech may result in commercial SOI foundries in the fhture. Caution is required in selecting a commercial U.S. SOI foundry, because the technology may not make provisions for body ties. In that case, the parasitic bipolar gain multiplication of the initial current transient may negate the benefits of the reduced collection volume [24].

V-20

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Figure 13. Cunenttransients

I

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aoo

400

600

(p@

strikes (Qudson

and Cmpbell,

l99l).

Layout modifications can also be used to mitigate single ion transients at the transistor level. Forexample, thearea of thedrain region can beminimized toreduce tocross section of vulnerable nodes. For conventional 2-edge designs, this means eliminating extended drains used as crossunders or intermediate routing layers. This is particularly important where silicided source/drain regions provide low resistivity material. For re-entrant designs, it means using the interior of the annulus as the drain because of its smaller area, and using a single contact per drain. Since a significant amount of the charge in an ionization path can be collected by diffision (particularly for high LET strikes), layout modifications to increase the distance between adjacent devices and to introduce recombination regions can be helpful. Introduction of v-2 1

,.

substrate and well contacts between devices can help prevent multiple bit upsets from a single particle strike. In general, SEU is extremely challenging for radiation tolerant designs using commercial technologies. The transient amplitude at the transistor level will be prirnarily determined by the starting material and the process used by the foundry. Most of the improvement in tolerance will have to come from design at the primitive cell, macrocell, and system level.

9. Total Ionizing Dose Mechanisms

Affecting

Primitive

Cells

The transistor-level radiation effkcts mechanisms and mitigation approaches discussed in the preceding sections are the foundation for designing primitive cells with the required radiation tolerance. Additional discipline in the design process at the primitive cell level can minimke or In general, the radiation sensitive intensi@ the manifestations of radiation degradation. parameters of interest at the primitive cell level are associated with the DC and AC performance DC parameters include supply curren~ input noise mar~ and output drive characteristics. levels as a function of Vdd, temperature, output loL@ and radiation dose. AC parameters include risetime, fdltime, and propagation delay. The degree to which these primitive cell parameters are affected depends on the circuit topography selected for the cell as well as the changes in transistor characteristics. Two extremes of cell topography are represented by the basic NOR and NAND gates as illustrated in Figure 14, The NOR gate combines a series connection of P-channel transistors and a parallel connection of N-channel transistors to perform the logic fimction. As the N-channel transistors are exposed to an ionizing radiation dose (in a time frame where oxide trapped charge effkcts dominate), their leakage current increases, and their threshold voltage moves toward depletion operation. The net effect on NOR gate pefiormance is to (1) increase the supply current in the high state, (2) decrease VWin (tiput high state threshold), (3) lower VOH (output high state voltage), (4) decrease the fall time, and (5) reduce ~~l. A the P-channels are exposed to an ionizing radiation dose, their threshold voltage moves further into enhancement and their maximum drive current decreases. The effect on NOR performance is to (1) increase the supply current switching transient, (2) decrease V1~~w (input low state threshold), (3) lower Vo~, (4) increase the rise time, and (5) increase ~~. . These effects are enhanced by the parallel connection of the N-channel transistors and series connection of P-channels. Larger NOR gate fan-ins aggravate the effects by pitting more series Pdm.nels against more parallel N-channels. This is often designate-d as a “stacking height” problem in reference to the stack of P-channels in series. In radiation tolerant designs, stacking height is usually restricted to 4 transistors as part of the design discipline. Typically, NAND primitives are somewhat less sensitive than NOW to total ionizing dose degradation. The parallel combination of the P-channels helps compensate for their reduced drive capability, and the series combination of the N-channels compensates for their increased leakage and lower threshold voltage. For this reaso~ NAND configurations are often chosen for radiation tolerant designs. However, the impact of specific Wnsistor radiation degradation mechanisms for a selected technology must be considered in selecting a topography.

v-22

NAND Topography

NOR Topography Vd In 4 d h 3 4 In 4

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14. NOR and NAND topographies illustrating transistor stacking height.

The effects of cell topography on post-irradiation performance should also be considered in selecting worst case test conditions for primitive cell. Both the NOR and NAND should be irradiated with a high state on all inputs. However, the worst case post-irradiation test condition for leakage will be with all inputs held low for the NOR and all but one input held high for the NAND. The discussions

above have only considered

oxide trapped charge effects.

The postirradiation behavior will be quite different in the regime where interface states dominate. Both regimes (as appropriate to the mission application) should be analyzed as part of the design process and tested for worst case performance [25]. The full testing and annealing sequence specified in Mil Std 883 Method 1019.4 should be conducted to bound the oxide trapped charge and interface state effects. As a general rule, radiation tolerant designs should prefer NAND-type topographies. Even in those configurations, the stacking height should be limited to prevent significant disparities in high-to-low and low-to-high switching characteristics: Other configurations to be avoided can be deduced from a consideration of the interaction between the manifestations of radiation damage in the transistor and the function to be performed by the circuit. For example, the use of N-channel pass gates in cells such as multiplexer and flip flops should be avoided due to their tendency to develop source-to-drain leakage paths. P-channel pass gates also create problems because of their increase in on-state resistance with total dose. Careful primitive cell designs

can mitigate

many of the radiation

effects introduced

10. Single Particle Effects Affecting

at the transistor

Primitive

level.

Cells

The generation of bit errors which are detected as single event upsets occur at the primitive cell level as the circuit interacts with the current transient generated by the ion strike. Consequently, the electrical design and layout of the cell have a major impact on SEU tolerance. Similarly, the layout rules used at the cell level determine placement ‘of well and- substrate contacts

and the spacing

between

adjacent

elements

V-23

that

can participate

in a latchup

path.

Therefore, most of the design work directed at reducing the occurrence of single event effects occurs at the cell level. Commercial CMOS circuits designed for the highest possible packing density will minimize the spacing between N-channel and P-channel sources and the well edge and use infrequent well and substrate contacts. These practices do not pose a problem for commercial applications, but are highly likely to produce SEL problems. Testing at a particle accelerator is the only way to conclusively determine the SEL susceptibility. However, inspection of the die surface can provide valuable insight into the layout practices used. Also, a spreading resistance measurement can provide information on the existence and thickness of an epi layer and the depth of the well. The metallization layers must be removed to observe the relationship of the well edges to the -istor sources, but the polysilicon layer should be left in tact to facilitate identification of transistors. Commercial ftilure analysis laboratories can perform the delayering and photography for approximately $400. Spreading resistance measurements can be made for $150 per site. Typically, two sites are suilicient to determine well depth and epi thickness. For $700 (approximately the cost of one hour of accelerator time), a great deal of information can be

gathered on critical design practices, In the opinion of the authors, any radiation testing of commercial microcircuits should be preceded by die surface inspection and spreading resistance measurements. Furthermore, this Mormation should be documented in the test report so that fbture applications of the microcircuit can be verified to be the same version as previously tested. The critical design issues for improved tolerance to SEU can be identified by considering Petersen’s equation for estimating errors per bit day [26]. R= 5x10-10 abc2/QC2 where R = error rate in errors per bit day ab = area for the critical node in square microns c = collection depth in microns Q.= critical charge in picocolombs.

The area of the critical node is under the layout designer’s control and should be kept as small as possible within the constraints of the design rules for the technology, Extended drains should especially be avoided since they increase the sensitive node area. The collection depth is determined by the processing technology and is not within the control of the designer after the processing foundry has been chosen. The collection depth is essentially the epitaxial layer thickness, which can be determined from spreading resistance measurements. For 0.8 to 1.2 pm CMOS commercial technologies, a typical epi thickness is 12.5 microns. Since the error rate goes as the square of the collection depth, choosing the process technology with the thinnest epi is clearly advantageous. The designer has the most direct control of the critical charge required to upset the cell. By choosing transistor dimensions and cell topography, he can determine the value of Q,. In ASIC designs, many different types of latches can be used, and their design requires carefid attention. The latch shown in Figure 15 was selected by a commercial standard cell designer for a data register. It uses transmission gates to control the presentation of the data to the latch. In

V-24

the first section, the principal inverter is kept relatively small to permit it to track the input data quickly. The drive current of the cross coupled inverter is kept low (W/L = 0.4) so that it is easily overpowered by the input driver. While the clock is low, the first stage tracks the data. When the clock goes high, the first stage is decoupled from the input and connected to the second stage. The high clock also breaks the cross coupling between second stage inverters so that the main second stage inverter is driven by the main first stage inverter. When the clock goes low again, the cross coupling is reactivated in the second stage and the state is latched. The schematic of the latch cell contains all of the resistive elements associated with the source/drain regions and the poly used for interconnect. The SPICE model used for the SEU evaluation also contained all the parasitic capacitances associated with the silicon, poly, and metal layers. ~---..~T..__

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The critical charge for the data-latched case can be estimated by driving the various nodes in the design with a current source representing a transient from an ion strike [27]. The wave shape shown in Figure 16 is for an 18 MeV silicon ion (LET= 14 MeV-cm2/mg and range >25 ~m). The upset response for a simulated strike on node 132 is shown in the figure. Although there is sufficient charge in the f$EU transient to deeply discharge the node, significant replacement current is provided by the PMOS transistor M26. Indeed, the node begins to recover, but the state transition has already begun in the primary inverter, and the feedback drives the latch to a complete state transition. Additional simulation shows that a strike at node 18 is similarly effective in initiating an upset. Integrating the waveforms yields a critical charge of approximately 200 fC. The area of the nodes is 16.6 ~m2, and Peterson’s equation gives an

V-25

estimate of 3 .2x 10-5 errors per bit day. This would be an unacceptable error rate for many space systems. However, many latch designs used in commercial microcircuits upset at even higher rates. Although the topography of the example design is not good for an SEU tolerant latch, relatively simple modifications could be made to decrease the error rate by an order of magnitude. These include: (1) increasing the size of the restoring transistors M25 and M26, (2) rearranging the layout to reduce parasitic resistance in the restoring path, and (3) increasing the time constant in the feedback loop of the second stage.

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A V(1321 Time Ezzzx%l

Figure 16. Results from SEU analysis of commercial latch. Although SPICE analyses are helpful in identifying design issues relevant to SEU tolerance, they are not definitive. In the example used here, the ionization transient has been treated as a simple photocurrent source involving only the drain. In reality, the ionization track is a complex, three-dimensional phenomenon involving dimensions similar to the layout dimensions of CMOS transistors. Consequently, the response of the transistor may be complex and involve the turn-on of “off’ devices due to lowering of the potential at the source. Furthermore, the conduction mechanisms associated with the ionization track are quite complex [28] [29]. Our analysis has used wave shapes from measurements on simple silicon diodes. However, CMOS structures have four layers of material including the sourcejdrain implant, the well, the lightly doped epi layer, and the heavily doped substrate. The ionization track can form

V-26

.,

a shunt path through the layers, transferring charge between layers at different potentials. only does this tied transient arnplities, it also significantly tiects wave shape.

Not

Testing for SEU and SEL must be performed to detenn.ine definitive cross sections and LET thresholds [30]. Where radiation tolerant designs are being implemented in commercial processes, test chips should be characterized early in the development effort. circuits representing expected sourceklmin and well spacing, well contact spacing, and substrate contact arrangement should be included for SEL evaluation. Arrays of typical latch designs and memory Comparison of empirical LET cells should be included for SEU error rate determination. threshold and cross section data with doping profiles, layout dimensions, and SPICE predictions can be used to reil.ne modeling procedures for fiture designs. In general, worst case SEL tests should be conducted at the maximum temperature and Parasitic bipolar gain increases with temperature, supply voltage expected in the application. making the device more susceptible to latchup. Maximum voltage results in wider depletion regions and more charge collection to give the worst case transient amplitude. Some SEL testing should be performed at the lowest possible clock rate. Since the supply current is proportional to clock flequency, operating circuits at high speed may produce supply currents that are much higher than micro-latch currents. Reducing the operating frequency increases the likelihood of observing small supply current increases from micro-latches. Worst case SEU testing should be conducted at elevated temperatures and the lowest voltage expected in the application. Elevated temperatures reduce the drive current in MOS transistors. Consequently, less restoring current is available to overcome the SEU transient. Since the cument of a CMOS transistor in saturation is proportional to (V~ - V~2, the restoring current at vdd = 4.5 volts will be 2/3 of the current at 5.5 volts.

There are numerous electrical and layout design techniques which can be used to improve SEL and SEU tolerance. They include: (1) the use of guard bands, (2) closely spaced well and substrate contacts, (3) selection of robust latch topographies, and (4) maximizing replacement currents while minimizing critical node area, Some of these techniques will be illustrated in the design example at the end of this article. 11.

Total Ionizing Dose Mechanisms

Affecting

Macrocells

Integrated circuits are often referred to a systems-on-a-chip; many of the design disciplines historically associated with systems must now be applied to ICS. As shown in Figure 17, microcircuits are typically organized as blocks of rnacrocells which interact with each other at well defined interfaces. Functions such as register files, arithmetic logic units, decoders, barrel shifters, mukiplexers, etc. are referred to as macrocells. They are also referred to as data path elements, megacells, and several other names. The design and layout of these macrocells and their interconnect networks can have a significant impact on their radiation tolerance. At the macrocell level most of the unique total ionizing dose issues have to do with timing. Three general mechanisms can be identified which manifest themselves as timing problems. They include: (1) non-uniform changes in rise time, fall time, and propagation delay in different cell types, (2) changes in clock drivers which reduce the maximum drive current, and (3) changes in leakage current which degrade the charge stored on a node.

V-27

,,

.

TMS320C40

CPU BLOCK DIAGRAM

ON-CHIP 20na CACHE. RAM ANO ROM

.“,%ww%%ki?

MBYWSISWDIRECT PROCESSOR TO PROCESSOR COMMUNICATION

120

Figure 17. Block diagram of Texas Instruments 320C40 digital signal processor showing major fictional blocks. As discussed previously, transistor-level degradation mechanisms can be mitigated or aggravated by different logic cell topographies (e.g., NAND vs NOR gates). Differences in the degree of degradation among different cell types can also be enhanced by different biasing conditions [31 ]. If a particular instantiation of a NOR is predominantly biased in a worst case condition (all inputs high) while a NAND is biased in the best case condition, differences in postAdditional disparities in performance can result irradiation performance will be exacerbated. from differences in stacking height, fanout, and interconnect capacitance. If the gates with asymmetric propagation delays are located in different data paths that converge on a logic cell, an undesirable “glitch” can occur at the output. It is solely the result of differences in path delays and not an error in logic. Nevertheless, the glitch can propagate and be interpreted down stream Such an error is known as a race condition (also as valid data with unknown consequences. referred to as a hazard in some systems of nomenclature). These effects may occur in either combinational or sequential systems. A race condition is possible in a sequential system any time the transition from the PRESENT_STATE to the NEXT_STATE involves two or more bits (state variables) [32]. In general, race condition problems are alleviated (not eliminated) by designing synchronous systems in which data are only considered valid at fixed intervals as defined by a clock. This has the effect of allowing the “noise” associated with glitches to be filtered out by setting the interval to be longer than the maximum accumulated propagation delay. Clearly, the clock interval must be set to accommodate worst case cell propagation delays as affected by temperature, fanin/fanout, loading, and process variation (as reflected in transistor I/v characteristics). For radiation tolerant microcircuits, the affects of total ionizing dose as affected by dose rate and irradiation bias condition must also be included. V-28

Despite its obvious benefits in mitigating race condition errors iu both combinational and sequential designs, the clock can also be a source of post-irradiation problems. These problems stem from generating the clock waveforms and distributing them throughout the die. Most complex microcircuits use a two-phase, non-overlapping clock system. A two-phase clock is used to permit combinational operations on PRESENT_STATE vectors to be completely settled prior to latching in NEXT_STATE values. The issues are illustrated by the Mealy model of a finite state machine with a two-phase clock and annotated clock wave form shown in Figure 18.

Phase’1

clock

Phasb 2 clock

Clock Phase 1 Clock Phase 2 I I

Epoch

I

I

I Phaae

1

;

T12

~

2

~T2;

I

I

‘1 time-

Phaae

I

I I

I I I I

Delay

;

I

* -‘=-wmmd Icglc 4—-——————————

-

delay

d

—————

L-

-~

P.aet

time

4

clock period

Figure 18. Two-phase clocking scheme illustrated for a Mealy machine (Mead & Conway 1980). During the Phase 1 epoch, the PRESENT_STATE vectors are latcheci into the inputs of the combinational logic block. The duration of the Phase 1 epoch must be sufficient to ensure that valid transfer has occurred. It is followed by the Phase 1 non-overlap epoch, T12, which ensures that race condition noise does not ripple through to corrupt the PRESENT_STATE vectors. The Phase 2 epoch allows the results of the combinational operations to settle at the

V-29

,.

.,

input of the NEXT_STATE latch. Its duration must be long enough to accommodate the combinational logic propagation delay and the preset data requirements of the latch. The Phase 2 non_overlap epoch, T21, is unproductive system time and is included to accommodate skew in the distribution of the clock. Skew is defined as the “variation in the effective tival time required of the clock at different clocked elements” in the microcircuit [33]. It is a function of the interconnection system and the drive strength of the clock. Commercial designers are motivated to reduce T21 to the shortest duration to improve performance. Unfortunately, total ionizing dose irradiation will affect clock skew by unsymmetrically changing the drive strength of the clock, A NOR implementation of the two-phase clock generation would produce the worst change, but it is the con.llguration found in many commercial designs. Radiation tolerant designs prefer NAND implementations for the clock electrical design. Careful attention should also be given to layout of the clock distribution network to ensure roughly equivalent interconnect distances between the clock and all clocked elements is an important consideration for radiation tolerance. While the discussion of race conditions and clock skew seem very straight forward when viewed from the perspective of a conceptual state machine and cloclq we must remember that the sequential and combinational elements are widely distributed over the surface of the microcircuit die and that communication is via data and address busses. In this context, leakage currents contribute to timing problems. Data buses are parallel interconnects connecting logic blocks and permitting data words to be transferred horn one block to the next. Typically, those blocks which can drive data onto the bus connect to its individual lines via tri-state bufkrs. When a logic block is authorized to place data on the bus, its buffkrs act as nomml gates, driving the line to either a high or low state. Otherwise, the buiTer is placed in a high impedance @i-Z) condition in which both transistors connected to the bus are turned off or disconnected from Vdd and Vss. Many logic blocks may be connected to a bus, but only one is authorized to drive it at any time. Unfortunately, after irradiation, N-channel transistors in the buiTers can develop serious leakage problems due to turn on of field oxide paths, parasitic edge transistors, or intrinsic ~istor threshold voltage shift into depletion mode. Therefore, the bufTer driving the bus must provide cument to charge the bus to the correct logic state and to overcome all the leakage currents. In the extreme case, the buffer may not be able to drive the bus to the correct logic state at all. More frequently, it takes longer to attain the required state, and the increased time may exceed the allocation of the clocking scheme. In some microcircuits the data bus is maintained in its last state by bus keeper latches until the next logic block is authorized to write new data. By their nature, bus keeper latches are small and easily overpowered by the driver buffers. For that same reaso~ they may be overcome by leakage currents. In either case, the resulting errors may be intermitten~ occurring for only some data vectors, power supply voltages, clock rates, and temperatures. Clearly commercial microcircuits, with their emphasis on packing density, high speed performance, and maximum fimctionality, are likely to be susceptible to timing errors from any of the three sources described above. Test strategies must be carefi.dly chosen to reveal such errors. Consideration must be given to irradiation bias conditions for both the I/O terminals and the internal logic. Internal logic bias should be selected for worst case conditions for those circuits susceptible to timing, leakage, or combined failure mechanisms. The irradiation test sequencing is also critically important. Some errors may only be observed under conditions of V-30

maximum hole trapping, while others occur only under rebound (interface-state-dominated) conditions. Techniques such as monitoring the supply current during irradiation may help the experimenter determine when leakage current effects are dominating. In-situ measurements of key parameters at intermediate radiation levels are essential to ensuring that subtle timing errors are not overlooked. Since in situ test resources are usually limited, analyses should be performed to select the most critical timing tests. These should be supplemented with thorough postirradiation characterization using the entire test vector suite. The designer developing radiation tolerant designs for fabrication in a commercial foundry must be especially meticulous in performing the design timing evaluation at the Robust clock designs with adequate margin to account for total dose macrocell level. degradation are especially important. Layouts should emphasize the shortest possible clock distribution nets and well matched interconnect lengths to all blocks. Clock duration and nonoverlap intervals should be selected to account for post-irradiation propagation delays. The number of connections to data buses (i.e., bus drops) should be minimized. Driver buffers and bus keepers should be sized to supply post-irradiation leakage current. Certainly, there are many more design techniques which can be employed to mitigate total ionizing dose effects at the macrocell level. These depend on the type of design architecture being implemented and the choice of macrocell building blocks. Most importantly, the designer must realize that decisions made at the highest level of the design can significantly affect postAlmost certainly, there will be some reduction in performance and irradiation performance. density required to achieve the needed radiation tolerance.

12. Single Particle Effects Affecting

Macro-Cells

The design objective at the macrocell level is to manage the effects of SEU bit errors generated at the primitive cell level. The designer must be concerned with the propagation of SEU transients through combinational logic, the capture of propagated errors in memory elements, and the effects of memory errors. The memory elements in question may be either data registers (latches) or MM (random access memory). In their discussion

of SEU effects in complex logic systems, Diehl-Nagle

et al. [34]

identified four criteria for a single event transient in combinational logic creating an error. They include: (1) the voltage transient created by the single event must be capable of propagating into

the local circuitry, (2) a critical logic pathway must exist between the struck node and a latch, (3) the transient must have sufficient amplitude and duration to write the latch input (i.e. exceed the noise margin), and (4) there must be a coincidence of the transient and the latch write enable. Figure 19 illustrates the circuit context for these criteria in tracing a node upset through the logic to a latch. Consideration of the four criteria can be helpfid in designing macrocells with improved SEU tolerance and in selecting test approaches for commercial microcircuits.

V-31

{*’D ,: ‘_ Yi5iEiElw CK

Controlinput

DQ

so -.

clocked D,atch

S1 xl YI

.8

c

Figure 19. SEU error propagation paths in a 2 bit fidl adder (Diehl-Nagle and Vinson 1984) As discussed in Section 8, the duration and amplitude of SEU transients are typically sufficient to permit their propagation through primitive cells. As feature sizes are reduced with advancing microcircuit technology, the cells become fmter, and transients are more likely to be passed as logic signals. The cell design practices for reducing the amplitude and duration of SEU transients which were discussed in Section 8 for latches are generally applicable for combinational cells. Namely, the ~istor dimensions and layout should be chosen to provide as much restoring current as possible to the struck node. Also, the capacitance of the cell inputs should be as large as is consistent with the performance requirements of the circuit. Fortunately, the very nature of a combimtional logic system prevents some transients horn propagating. If a node that is in a low state is struck such as to create a discharging transient no enor propagation will occur, because there is no state change. Similarly, an AND gate will only propagate a 1-to-O error if its other terminals are in a high state. Thus, the probability of the cell output being upset by an SEU transient on an input terminal is usually less than one. The actual probability is the product of the probabilities of physical upset for each state and the probability of occurrence of each state. The probability that an error will propagate from the struck node to a given latch is the cumulative probability from all the intervening cells. The assignment of cell upset probabilities and their use in cumulative path upset rate estimates are illustrated in Figure 20. Baze, et al. [35] have developed a formalism for estimating error propagation probabilities which has been demonstrated for static errors and is being extended to

V-32

.,

..

,,..,,

transient errors. Such a tool will be extremely helpfkl to the designer in identi~ing those data paths which limit SEU tolerance. In the interim, the designer should select the cells with the most robust SEU tolerance to drive latch inputs.

C /D

Ao-

D

p—

OUT

)-O

E

BO A

B

c

D

E

OUT

OUT-A

OUT-B

STATE PROB

0

0

0

0

0

0

0

1

0.1

0

0.1

0

1

0

1

1

1

1

1

0.4

0.4

0.4

1

0

0

0

0

0

0

0

0.1

0

0

1

1

1

0

1

0

1

0

0.4

0.4

0

umulatwe

.

IC

EOUT= POUT-AEA+ POUT-BEB = 0.8EA + Figure 20. Output error rate calculation for combinational

‘OUT-A

P~uT.~

.

1

O*SEB

network (Baze, et al 1995)

In order for a transient to be latched into a memory element, it must be able to charge (or discharge) the input capacitance to the erroneous state. If the capacitance can be made large enough to keep the node from charging (or discharging) to the noise margin during the transient, SEU tolerance can be improved. The transient can be expected to have undergone some wave shaping as part of the propagation process so that it may appear as a typical digital noise glitch at the latch input. If the input capacitance of the latch can be sized to make the RC time constant too long for an SEU-induced transient to reach the noise margin threshold, improved SEU tolerance to propagated errors can be expected. Any change in input capacitance for a cell (combinational or sequential) will slow its performance and usually increase its layout dimensions. The clocking scheme can provide some errors. As we saw in Figure 18, a system using a with effects that persist into the preset time. Any affect the latch. Transients in Phase 2 will only error that persists to the onset of preset. None of the design efforts upsets. Consequently, the designer may manifest themselves as corrupt errors may produce corrupt state processing proceeds. In processors, in the program

control

registers

benefit in discriminating against propagated two-phase clock is only susceptible to glitches transients in the Phase 1, T12, or T21 will not affect the latch if they have generated a logic

mentioned above or previously in Section 8 will eliminate must be prepared to manage the resulting errors. The errors information anywhere in the system. In state machines, the vectors which lead to inappropriate event sequencing as the errors may corrupt the data in latches or the information

(i.e., program

counter,

v-33

stack pointer,

and processor

status)

[36].

While data errors can certainly be serious, upsets in the program control registers can be particularly disastrous, since they control the sequencing of processor functions. Usually, a great deal of attention is given to upset in main memory (MM) since those upsets can affect both data and program information. Management of those errors is typically the role of the system designer. However, many processors and ASICS contain significant amounts of on-chip memory used as cache, supplements to data registers, and dual port buffers for block data transfers with off-chip circuits. The chip designer must determine his strategy for managing errors in the on-chip R4M. Since commercial designers are unconcerned about SEU-generated errors (mitigation of alpha particle effects are handled with selection of packaging material and die overcoating), engineers tasked with radiation characterization of commercial parts must ensure that the test effort addresses worst case macrocell affects, This includes considering the effects of ion selection and clocking on propagated transients. Since the duration of the SEU transient typically increases with the LET of the particle, worst case propagated SEU should be conducted with the largest LET available at the source. Also, a maximum clock frequency will produce the greatest propagated SEU vulnerability since the period of vulnerability (around preset) will be a larger percentage of the clock cycle time, The test program should be designed to detect errors occurring in program and data registers as well as on-chip memory. Designers developing radiation tolerant circuits for fabrication in commercial foundries have several design options available at the macrocell level to manage SEU errors. Synchronous designs with a two-phase clock are clearly advantageous. Particular care should be given to the design of a robust clock. An SEU transient on the clock distribution network is sure to cause malfunctions throughout the chip. Carefid engineering of the input time constants for latches can balance improved SEU tolerance with performance. For certain critical registers (e.g., program counter), a special design of a non-upsettable latch may be justified. Several circuit topographies have been recommended which can enhance SEU tolerance by (1) storing redundant bits in separate physical locations, (2) designing feedback into the cell to ensure that a node is forced to recover to its previous state following an ionization transient, and (3) using the inherent SEU immunity of certain devicektate relationships (low state data stored by an “on” N-channel transistor cannot be upset by an Nchannel strike) [37]. These designs invariably require more layout are% but they can be very valuable in protecting critical registers. Error detection and correction (EDAC) can be an extremely effkctive management approach for SEU errors. In some applications, error detection may be all that is required. It may be used to initiate reset sequences or even a cold reboot procedure. The penalty for error detection is at least an additional bit and the extra circuitry required to generate and check for parity. Full correction and detection has been estimated to impose a 17V0 to 50’% area penalty [38], Therefore, it must be used judiciously. Other similarly area intensive schemes, such as voting redundant elements, are also alternatives which can be employed for crucial functions. In summary, macrocell level design must include consideration of SEU error management. However, the selection of specific mitigation techniques must consider the LET

v-34

spectrum likely to be encountered during the mission and the trade off between the effect of errors and the performance penalties imposed by the hardened design.

13. Demonstration

of Radiation Tolerance Enhancement

Through Design

An example of the application of radiation tolerant design practices to a problem may help to illustrate many of the concepts presented in the previous sections. In a recent project, the USAF Phillips Laboratory wished to develop a design-hardened gate array to support fielding small space experiments investigating advanced signal processing and packaging techniques. The concept was to design and build fret-turn-around, low-cost experimental packages with low size, weight and power requirements. As opportunities arise, the packages would be added to launch vehicles which could accommodatethe extra payload. Since the launch vehicle and satellite may be targets of opportunity, the experimental electronics must be sufficiently robust to operate in a wide variety of orbits and to survive in minimally shielded placement in the satellite. The target radiation tolerance levels were 100 Krad(Si) total ionizing dose over all dose rates and no single event latchup. In addition, the gate array should support design of SEU tolerant cells. The functions to be implemented in the gate array were to be relatively low performance ASIC applications such as instrumentation controllers and aggravations of glue logic to replace SS1 and MSI die in multi-chip modules. Only a few die (15 to 20) of each gate array personalimtion were expected to be needed. Since there was likely to be short notice of the availability of a launch platiorm, total cycle time for an experiment was to be kept under six months. Also, the cost for the design and fabrication of a new personalization was targetted for less than $20,000. Before discussing the application of the hardened design practices to the gate array and test chip, we will first discuss the commercial foundry alternative. With the cost, production quantity and schedule constraints on the program, the MOSIS (MOS Implementation Service) clearing house developed by DARPA and managed by 1S1 (~ormation Sciences Institute) was selected as an attractive alternative for die fabrication [39], MOSIS subcontracts with several different commercial foundries to process lots on a periodic basis. As the scheduled time for the lot start arrives, MOSIS assembles microcircuit layouts submitted by their customers into a reticule and passes it to the foundry. The foundries are high volume commercial lines capable of very high performance. The Hewlett Packard 0.8 ~ CMOS foundry is particularly attractive for a design hardened gate may. A process doping profile for a section through the P-plus source/dr@ N-well, P-epi, and P-plus substrate is shown in Figure 21. The epi layer is relatively thick (= 12.5 pm), but it will still be helpful in suppressing latchup. The process uses one level of polysilicon and three levels of metal. The poly and source/drain regions are silicided with a resistivity of approximately 2 ohms per square, The gate oxide thickness is 170 ~ thickness. Design rules for the technology are available through Intemet at I?p.mosis.edu. Fabrication costs for the HP foundry are determined by the die area at the rate of approximately $600 and $650 per mmz for government and non-government organizations, respectively. The customer is guaranteed 25 die for this cost. Dedicated wafers (150 mm) can be purchased with a minimum of three wafers costing $88,700. The reticule size is 17mm x 17mm, and there is a leverage of 40 reticules per wafer. MOSIS purchases the wtiers to the foundry’s parametric specifications. The customer is responsible for ensuring that his design works within v-35

the range of the parametric limits. Layouts for the HP foundry must be submitted by the 4th Thursday of each month, and the fabrication cycle is 8 to 9 weeks. Packaging is available for a nominal fee and the cost of the packages. Table 2 gives the cost scaling for a number of different size die. The size of the Phillips Laboratory gate array (total number of primitive cells) and the number of pads (Vdd, Vss, and 1/0) are indicated. Columns show the cost for the initial 25 units and additional increments of 25 parts. Packaging costs for appropriately sized PGAs (pin grid arrays) are included in the table entries. By using design hardening practices, the cost and schedule benefits of the MOSIS/HP foundry service can be used to support space experiments. The specifics of the layout hardening approach can be seen in the primitive cell in Figure 22. It consists of two re-entrant N-channel transistors and two 2-edge P-channel transistors sized for equivalent drive strength. As discussed in Section 7, edge leakage effects are eliminated by the re-entrant design. The area Penaltv associated

with the re-entrant

transistors

.

is apparent.

p

~ti (au-3)

P

m-miusms

Figure 21. Doping profile for HP commercial CMOS process.

V-36

.

Ta e 2. Cost Scaling for Gate Array Fabrication Through MOSIS Die Dimensions

Size of Gate Army

Coststo non-Gov’t Organizations

Cost to Gov’t Organizations

inrnm

(Number of L/0)

1st25 Units

1st25 Units

(Additional 25 Units)

(Additional 25 Units)

2K

$3600

$3125

(36)

($3000)

($2605)

12K

$11,400

$9,725

(76)

($9,000)

($7645)

31K

$24,400

$20,725

(1 16)

($19,000)

($16,045)

57K

$44,850

$38,125

(156)

($35,250)

($29,805)

92K

$69,000

$58,425

(196)

($54,000)

(45,425)

2x2

4x4

6x6

8x8

10X1O

The field oxide leakage is eliminated by enclosing the N-channel thin oxide regions (source/drain) with a channel stop composed of the P-plus source/drain implant of the P-channel transistors. The P-plus sourcehkain must be used because there is no other mask definable layer for a P-type channel stop available through MOSIS. The polysilicon gate cannot be allowed to cross the P-plus, because it would create a gap in channel stop since the sourcdmin implants are self alligned to the poly. The gap would provide a possible source-to-well leakage path. Obviously, a significant area penalty has been paid for the channel stop and elimination of polysilicon interconnect to P-channel gates. However, all of the potential total-dose-induced leakage paths have been mitigated with the exception of those associated with the intrinsic transistor. The channel stop also acts as a guardband for latchup suppression. It reduces the gain of any surface lateral NPN transistor by introducing a P-plus region in the base. It also keeps the base of the NPN very close to ground potential by providing a low impedance path to Vss. The HP process is silicided so the resistivity of the polysilicon and the sourceMrain regions is approximately 2 ohms per square. The guardband has five Vss contacts located along the right edge. To be doubly sure that no SEL problems would be encountered, an N-plus guardband was placed in the N-well around the P-channel transistors. This spoils the gain of any surface lateral PNP transisistor and ties the PNP base to Vdd through a low impedance path to five contacts located along the left edge. Clearly, the double guardbands result is an additional area penalty, but the area tradeoff was considered worthwhile to minimize the prospects of latchup.

v-37

P-channels Sized forBalanced Drive Current -7

Re-entrant N-channel transistors

7

Frequent N-well & Guard Ring Contacts <

L

OQ

Frequent Substrate and A Guard Ring Contacts

N-plus Guard Ring Around N-well -f Figure 22. Primitive Cell Design for Radiation Tolerant Gate Array

~P-plus

Channel Stop& Guard Ring

There are other more subtle aspects of the primitive cell design that should be considered. The use of source/drain implants for channel stops makes the design more portable than if a separate mask-defined channel stop layer were available. The design is consistent with a very generic CMOS technology, and consequently, could be readily moved to another foundry if HP were no longer available for any reason. Also, the use of the double guardbands makes the latchup suppression more foundry-portable. HP uses a relatively thick epitaxial layer as shown in the spreading resistance measurement in Figure 21. As noted previously, the P-plus substrate helps supress latchup by reducing the cathode-gate resistance of the parasitic SCR. However, another foundry might not employ an epi-substrate technology, and latchup suppression would have to rely solely on the guardbands. In the current economic environment where foundries are running at fidl capacity and corporate buyouts are common place, consideration of design portability is important. The application of the primitive cell in a gate array is illustrated in Figure 22. The upper left quadrant shows two of the primitive cells tiled together. The guardbands between adjacent primitives are shared to give some improvement in layout density. The metallization pattern to form a 4-input NOR gate is shown in the upper right quadrant. It is applied to the primitive cells in the lower left quadrant. The lower right quadrant shows the NOR implementation in the context of the full gate array with interconnects to adjacent devices. A gate array approach was selected for radiation tolerant ASICS because of its simplicity.

All the radiation tolerance is achieved in the underlayers and in restriction of macrocell stacking height. New macrocell designs can be performed by designers with a wide variety of radiation hardness background without compromising the hardness of the result. A standard cell approach which provides the designer more flexibility in the layout of the macrocell, also provides a greater opportunity for hardness compromise. The intent of the Phillips Laboratory gate array is to permit designers to add to the library as new cell types are needed. The library will be widely distributed through an Intemet site, and the hope is that outside users will submit their designs to the library as they develop special cells to meet a particular application. Gate array electrical design and layout software has been chosen to keep cost low and provide maximum access. All layout has been done in MAGIC version 6.4.4, which is available over the Intemet at gatekeeper.dec.tom, Versions are available for both Spare work stations and Pcs running 0S2. The MAGIC layout editor incorporates an on-line DRC (design rule check) capability, which minimks or eliminates the need for additional DRC tools. All schematic capture for the electronic design of the cells has been done with ORCAD, a PC-based tool. Models for the library cells are available in SPICE format. Parameters are available for the MOSEQ3 transistor models. VHDL models for the most frequently used cells are available with timing parameters reflecting best, nominal, and worst case performance. Routing is done with the widely used GARDS router from SVR (Silicon Valley Researc~

Inc.). All of these tools are available as public domain software, low cost PC based software, and as a service by several third party companies.

v-39

14. Test Structures

for Supporting

Radiation

Tolerant Design

To actually support development of microcircuit fimctions in the gate array, information is needed on the pre- and post-irradiation electrical characteristics of the transistors and primitive cells. Also, the effectiveness of the design for SEL immunity must be verified, and an empirical estimate of critical charge is needed to support design of SEU tolerant cells. Ag@ many of the test concepts can be illustrated by the test chip shown in Figure 24 developed for test and evaluation of transistor and primitive cell performance. A list of the structures on the test chip is given in Table 3. The location of the structures is indicated by the pad coordinates with the pad columns designated by letters and the rows designated by numbers, both beginning at the lower left comer of the die. The test chip is arranged to facilitate radiation effects testing. The structures which need to be bonded out for testing are located around the periphery of the die, and they are interconnected to bonding pads which are sized (100 x 100 pm) for easy bonding. Structures for experimentation are placed on the interior of the die and connected to probe pads. A 2x1 O internal pad geometry permits use of NIST standard probe cards. N-channel transistors are located along the left edge of the test chip. Two identical devices (NGOX_l and NGOX_2) are bonded out to support radiation testing at different bias levels. All four terminals (source, dra@ gate, and substrate) are available to permit a fidl suite of I/V characteristics to be measured to support model parameter extraction. Two field oxide transistors (MG_NFOX and POLY_NFOX) are also bonded out to permit monitoring of field oxide leakage without channel stops. The FOX transistors have been designed so that the gates Such a design is required to permit the pre-irradiation do not overlay thin oxide regions. threshold voltage to be determined without over~essing and rupturing the thin oxide. All of these transistors are attached to probe pads as well as bonding pads to permit them to be tested on an Aracor X-ray source. In addition there are six N-channel transistors located between probe columns D and E which may be probed only. They represent a series of experiments with nesting the source/drain inside the thin oxide region by varying amounts. Two independen~ P-channel transistors with all terminals brought out are located along the right edge of the test chip. Thus, both P-channel and N-channel devices can be independently biased, irradiated, and tested in a single package. Two latchup test structures are bonded out at the upper and lower comers of the right side of the test chip. The LATCH_OO structure has no guard bands directly across the latch path. LATCH_l 1 has double guard bands (N-plus and P-plus), LATCH_OO is a worst case structure and LATCH_l 1 is the best case structure (the scheme used in the gate array). They can be used to monitor the intrinsic latchup susceptibility of the technology and the effectiveness of the design hardening techniques. Additionally, a full suite of latchup test structures with all combinations of guardbands is included on interior pads.

V-40

Primitive cell array Personalization metal_

/

NOR cells n delay chail 7

/

Cells with metal Figure 23. Overview of gate array cell implementation

MGNPOX

-GATE

E

i!Q!J ,uoo.-w,..c~c,

12 11

L!LUOO P-PLUSCNTCT

E2

10

LQ LUOO N-PLUS CNTCI

NGOX_l -DRAIN

B

9

NGOX_l -sOURCE

~

8

~ PGOX_l -SOURCE

NGOX_l -GATE

El

7

9 PGOX_l -GATS

NGOX-2 -DRAIN

D

6

k 10 PGOX.2 -DRAIN

NGOX_2 -sOURCE

E!

5

U PGOX_2

NGOX.2 -GATE

G!

4

u PGOX.2 -GATE

PGNFOX -DRAIN

G2

3

~ DGLu N-PLUS CNTCT

PGNFOX -SOURCE

Q

2

PGNPOX -GATE

HI

1

MGNFOX

MGNFOX

-DRAIN

SOURCE

D1

B PGOX_l -DRAIN

SOURCE

11 DGLU P-PLUSCNTCT

I 8 DGLU NWELL CNTCT

ABC

DEFGH

JKLMNP

Figure 24. Test chip for design hardened gate array.

V-42

Table 3. Test Structure 1 ]cation on Rad Tolerant Gal Array Te A

I

12 MG NFOX

B

I

VDD

I

12

12

I

c

I

NOR1 VDD I

D

I

E

I

12

12

12

NOR1 IN

I NORI OUT I

N-WELL

GATE 11 [QNFOXDRAIN

10 MG

G

F

H

I

I

chip L

M

N

P

12

12 NOR2 IN

12 LAmoo PFP

12

NOR2OUT

12 NOR2 VDD

J

=FF

II

11

11

11

11

11

11

11

hiGNFOXGATE

NC

NOR1IN

NOR1 OUT

NC

NOR-2

NOR-2

NC

Vss

10

10

10

10

our 10

JN

10

NNMOS_l

NC

LATCH 00

NC

Vss

NNMos_l

NFox

DRAIN

GATE

9 NNMm_2

10

P-PLUS

I

LATCH 00

10

I

NC

10

LATCH~

N-WELL

11 LATCH00

I

F-PLUS

10 Mm

Vss

00

N-PLUS

N-PLUS

SOURCE 9

9

9

9

NGOX_l

Vss

NC

NOR_l

8

8

8

NGOX_l

NC

NC

7

7

DIWN

VDD

GATE

8 NNMm_3

DIWN

7

NGOX_l

GATE

s NNMos_2

SOURCE

I

NC

I

N.

=FF

VXS

6

6 Vss

6 NC

DR41N

5

5

5

NG0X_2

NC

NC

NC

LATCH 01

6

6

NNMos_4

GATE

DRAIN

5 NANr_l

GATE

VDD

LATCH

LATCH10

VDD

N-WELL

4

NNMos_5

NC

3

3

3

POLY NFOX

Vss

NC

2 POLY NFGX SOURCE

2 mLY NFOX GATE

2 NC

1

1

GATE

DRAIN

3

3

3

NC

NC

2 N~_l LN

2 NC

=l=T 1

3

3

sHrFrREG I

Vss

,

I

I

rN

CU3CK

1

SJXI’RCE

7

PGclx_l

I

DATA

I

t

IN

4

4

LATCH 11

LATCH11

NC

NC

PiNx_2

N-PLUS

P-PLUS

SOURCE

GATE

NC

Ml-cl-r mLY

LATCH 11

NC

VDD

I

SmFrREo

NAND_2

DATA IN

VDD

POLYNFOX= p Latch 10= N-plus

v-43

4

3

WEFTREG

Latch01 = p-plus g udbsnd

4

3

1

hansistor.

NC

3

1

PGox_2

NC

3

1

CLm

OUT

NGOX= N-Chsrmelgate ox!

Latch00= worstcase latchsbucturelnogum-dbands

7

3

DW

OUT

7

8

Kmx_l

10

5

NNMos_6

I

NC

‘INCINCI

NANC_2

NC

VDD

NC

N-PLUS

5

NC

I

01

NC

NG0X_2

1

8

N-PLUS

4

1

8

9 FGQx_l

6

6 NC

4

2 NANt_l OUT

9 VDD

N-WELL

4

NNMos_6

LATCH

9 NC

DRAIN

7

lNNMGS_31

4

I

01

7

NNMos_4

MGNFOX = metal gate field oxidebrmsistor.

8

FPLUS

4

1

VDD

8

LATCH

NC

4

DRADd

N-WELL

7

5

GATE

NoR_2

7

NNMcl_5

SOURCE

LATCH00

8

DRAIN

NGOX_2

GATE

9

GAm

7

I

9 NC

3

LATCH1l N-PLUS

FIELDPLATE

N-WELL

2

2

2

2

2

NANL_2

NAlW_2

NC

VW

LATCH 11

IN

OUT 1

1

FPLUS

1 NANL_2

NANK_2

IN ysilimn

gate

uardband

id

I

tiX

OUT I CAP oxidetransistor.

1

I

LATCH

I

I

PFP

I

LATCH1l N-WELL

NNMOS= Nested N-channellmmsistor Latch 11= best w@%phls & p-plus guardbands

The latchup structures also serve as field oxide leakage monitors. A polysilicon field plate has been routed over the region between the N-well and the N-plus source/drain. It can be used to investigate the effect of an applied field on latchup characteristics, or it can serve as the gate of a field oxide transistors with the N-plus sourcddrain acting as the source and the N-well acting as the drain. Thus, the LATCH_OO structure represents the worst case leakage horn Nchannel sourdlra.in to N-well. LATCH_l 1 and LATCH_O 1 can identifi the benefits of using a P-plus channel stop to interrupt the leakage path. A set of four, 101-cell delay chains are included on the test chip.

They maybe

accessed

either through peripheral pads for packaging or through internal pads for probing. Two NAND delays and two NOR delays are used to permit comparison of NAND versus NOR pefiorrnance. A stacking height of 4 (the maximum allowed for library cells) is used for both types of delay chains, and each NAND or NOR cell drives all four inputs of the succeeding cell. The primary function of the delay chains is to provide data for adjusting the timing related SPICE model parameters to provide good AC simulations. In addition to their role in evaluating AC performance, the delay chains have been configured to evaluate SEL susceptibility. The NOR1 and NAND1 delay chains have been laid out with full guardbanding for latchup suppression. The NAND2 delay chain has no guardbanding in the direct latch path and consequently represents a worst case for SEL susceptibility. The NOR2 chain has a single P-plus guardband. Each of the delay chains has an independent Vdd connection which permits an SEL instance to be isolated to the delay chain involved. The delay chains greatly increase the area which may be subject to SEL and make testing at the heavy ion accelerators possible without accumulating excessive total dose. An 8-bit shift register constructed from a series of D_LATCH cells is included in the test chip to evaluate petiorrnance of sequential circuits before and after irradiation. The interface between latch cells has been varied to include different drive strength and input capacitance values to evaluate their impact on SEU susceptibility and post-irradiation (total dose) performance. The sensitive area of the shift register is probably too small for efficient testing at an accelerator; however, microbearn SEU experiments on the shift register would be very informative. The test chip contains a number of other structures which are usefid for radiation characterization. A large area gate oxide capacitor (TOXCAP = 20 pF) is included to support quasi-static capacitance/voltage (C/V) charactetition for separating oxide trapped charge and interface states. A bipolar transistor and two diodes have also be included to support modeling of the parasitic and to support direct measurement of single event transients from a rnicrobeam source. In addition to its role as a radiation effects characterization vehicle, the test chip can also be used as a radiation effects process monitor for hardness assurance. Its small size (2. 18 mm x 1,86 mm) makes it possible to fabricate for a small additional cost ($3600 for 25 packaged units) in the same MOSIS lot used for a gate array personalization. Since the designer has no control over process variations in the foundries used by MOSIS, a low cost hardness assurance monitor is a prudent investment.

v-44

15. Application

of Radiation

Characterization

Data to Cell Design

The initial p~ose of a test chip radiation characterization effort is to gain information which will permit realistically conservative circuit designs to be performed. For digital designs, conservative practices are usually understood in the context of the design domain diagram in Figure 25. The fabrication process is viewed as producing transistors with a targeted nominal performance which is a good starting point for developing new designs. However, any process should be expected to produce variations in transistor ckteristics from wafer to wafer and lot to lot as a consequence of statistical changes in fabrication parameters. These variations are reflected in the current drive strength of the N-channel and P-channel transistors. By evaluating the performance of a design for the best (strongest drive) and the worst (weakest drive) case @resistor performance expected horn the fabrication process, the designer can ensure the needed conservatism. Usually, the N-channel and P-channel are assumed to vary independently so that simulations performed at the four comers of the design domain coverall possibilities.

DigitalCMOS Design Domain

,

I

1( I

NMOSslmng

NMosstrong

I

PMOSweak

PMOSstrong

I I

Nominal

I

o

I I

I

I I

I I I I I(

I I I I I

I

NMOSweak

NMosweak

PMOSweak

PMOSstrong

L—

I I I I

Expand for Rad Effects 1

Figure 25. Depiction of the parametric design domain for digital CMOS.

To establish the comers of the design domain, the designer must consider processing variations, changes due to radiation effkcts, variations due to interconnect (i.e., loading), and the effects of temperature. Typically, high volume commercial foundries employ statistical process control (SPC) techniques to maintain yield and ensure quality and reliability. Again, we can use the Phillips Laboratory experience to illustrate. The SPC limits are indirectly reflected in the parametric limits that are the basis for acceptance of the lot by MOSIS. A comparison of the limits for MOSIS acceptance and the distribution of measured parameters for 14 HP 0.8 pm lots is shown in Table 4 for some key N-channel and P-channel parameters. Since the *3~ points generally lie considerably inside the MOSIS acceptance limits, the comers for the design domain have been chosen as the *3u points as a realistically conservative limit for simulations.

v-45

Table 4. Comparison of Lot Acceptance Limits and Lot Averages Vth- 3U

Mean

Vth + 3(T

Kp - 3tJ

Vth NMos Lots

0.612

NMos Lot Accept

0.550

PMOS Lots

-0.797

PMOS Lot Accept

-0.55

0.723

-0.878

Mean

Kp + 3U

AL-30

Kp 0.834

40.47

1.00

35

-0.894

12.75

-1.0

10

48.18

15.04

Mean

&+3fl

AL 55.89

-.01

70

-0.4

17.33

-0.124

25

-0.4

0.194

0.485

+().4

0.089

0.302

+0.4

Establishing the design domain comers for radiation effects is a challenging task when working with small quantities of parts produced in a commercial foundry. The advantages of thin oxides for mitigating charge trapping effects has been discussed previously. Review of the gate oxide thickness for 14 lots shows the mean gate oxide thickness to be 176.1 ~ with a standard deviation of 0.96 ~. However, the control of other processing related parameters tiecting both trapped charge and interface states is not known. Given this lack of information, the small quantity of parts available for tes~ and the expense of radiation testing, an over-test approach was chosen to expand the design domain to include radiation effects. Although the target hardness for the gate array was 100 Krad(Si) the variation in the radiation parameters were taken from 320 Krad(Si) data. Furthermore, the best and worst case models were so that the best case N-channel had all the pre-anneal AVot subtracted from its threshold voltage for the worst case bias condition and the value of mobility for the pre-irradiation condition was retained. The worst case N-channel added all of the post-anneal AVit to to pre-irradiation +3u threshold voltage and subtracted the post-anneal change in mobility from the pre-anneal -3u value. A similar approach was used for the P-channel. Temperature and loading effects have been addressed by pefiorrning simulations at -55 ‘C and 125 ‘C for the transistor pairings defining the comers of the design domain. Simulations were performed for three different capacitive loads to define a linear relationship between propagation delay, rise time, and fall time as a fimction of load for each comer of the domain at each of the three temperatures. The result is a 5x3 matrix of slope and intercept values defhing the timing performance of each cell over temperature and load and accounts for processing and radiation variations. These simulations represent a significant investment of resources, requiring 45 SPICE runs for each library cell. Currently, there are 55 cells in the Phillips Laboratory gate array library as listed in Table 5.

The performance definition matrix is the basis for VHDL timing simulations for any personalization of the gate array. A typical design sequence for the gate array begins with schematic capture of the fiction and generation of a netlist. The design is simulated in a gate level simulator with timing parameters based on capacitive loads calculated from the fanout to other cells. Once the design is verifie~ it is routed and the additional capacitive load due to

V46

,.

..

..

interconnect is added to the appropriate nodes in the netlist. The verified routing implementation is then submitted for fabrication. Table 5. Radiation Tolerant Gate Array Cell Library Drive Strength Number of Inputs Type NOR NAND

Description NOR gate NANDgate

111v

inverter Tri-stateInverter

1

ive NOR gate

TINV RI .- JF TilJF .—-.

buffer ... -----.O –..-–..

Nnn-invertin@

2 4 4

3 4 4

4

4 4 d

lx 4 d 4

2x

4x

8x

4

4

4

d

d

d

d

d

d

non-invertingbuffer 4 4 4 4 4 ‘“- 2 Tem ‘“-n Multi-gate OAI & AOI 21 &22 d d _-mMulti-gate oAI&Ao1211 221222 - 3 Terr 4 ) flio fiOD D---= --r w/o&. . O-bar --DFF , , 1 1 1 [ 1 1 d 4 4 D flip flop w/ set, reset,& DFFS, DFFR,DFFSR setlreset 4 4 I Trarwarent latchw/Q& OB TLAT t d 4 4 TLATSITLATRITLATSR Tlatchw/set, reset,set.!res;t d Multiplexer2, 4,&8 input MUX2,MUX4,MUX8 4 4 d Decode 2,4, & 8 column 4 DEC2,DEC4,DEC8 REGBIT CLKBUF08 CLKINV08 CLK2PHAS SRAM Cell ZOUTBUF & ZOUTINV INBUF & ININV

t

Tri-state -----

Register bit macro Clock buffer driver Inverting clock buffer driver Two phase clock generator 6 Transistor SRAM Tri-state & Inv Tri-state Out Input buffers w/ESD protect

16. Performance

Characteristics

I I

4

4 d

4 4

i

4 d

4

of the Design Tolerant Gate Array

The Phillips Laboratory gate array demonstrates many of the radiation tolerant design techniques which can be employed with purely commercial foundries to achieve hardness levels Clearly, the approaches used are very conservative and result in consistent with space missions. significantly restricted circuit density and reduced performance. However, there is a subset of microcircuits of interest in space applications which can be implemented at the level of complexity satellite

represented

by the gate array, and the cost and quantities

are consistent

with many

requirements.

To date, four designs have been completed in the PL gate array project. They include: (1) a 1.2 ~m test chip developed for proof of concept, (2) the 0.8 pm test chip discussed above, (2) a dual register file (DRF), shown in Figure 26, and (3) a microcontroller, which is in fabrication. The test chips and DRF were developed primarily for radiation characterization. Performance results from the delay chains on the 0.8 ~m test chips are shown in Figures 27 and 28. The pulse width corresponds to the total (101-cell) chain delay. Both pre-irradiation and The NOR chain is somewhat slower due to the series post-irradiation delays are shown. connection

of the P-channels,

and its post-irradiation v-47

..

change

is slightly

greater

than the NAND.

Both the NAND and NOR chains show minimal change in performance at doses significantly in excess of the design goal. The difference in NAND and NOR post-rad performance change is minor due to the use of re-entrant N-channels which eliminate edge leakage. SEE testing is scheduled for the test chip and DRF in early summer. A preliminary microbeam test on the test chip showed no latchup in any of the test structures, but it was inconclusive, because the ion energy may not have been adequate to penetrate the overlayers and extend a significant distance into the silicon. Construction analysis on test chip die has show excellent metallization quality and uniform step coverage as indicated in the SEM photograph of the metal 1 over polysilicon step shown in Figure 30. The die are considered to be of suitable quality for space applications. However, packaging would have to be performed in a qualified assembly line.

Figure 26. Dual register file implemented in the design hardened gate array.

V-48

..

,.

NAND

Gate

Delay

Chain

7 65-

,b f

4a! z 5

~

/ 1

3-

1 (.

f

+!.+

Delta 0.6ns

2I

-2e-6

}

-1e-8 Oe+O 1e-8

2e-8

3e-8

4e-8

5e-8

6e-8

Time (See)

Figure 27. Pre- and post-irradiation

performance of the NAND delay chain.

NOR GATE Delay Chain

7~

4 a)3 m g S2 1

0

I

I

-1 e-8

Oe+O

1e-8

2e-8

3e-6 Time

28. Pre- and post-irradiation

5e-8

6e-8

7e-8

(See)

performance of the NOR delay chain.

v-49

.,

4e-8

,,

Figure 29. Metal

step over polysilicon gate from 0.8p test chip processed at Iewlett Packard (photograph courtesy of Space Electronics, Inc.) 17.

Summary

This presentation has identified a few of the design and layout issues associated with the radiation tolerance of microcircuits. Commercial designs typically do not address these issues, because they are not within the scope of anticipated operating environments. Many of the design techniques required to mitigate the radiation effects are contrary to the density and performance criteria required for a competitive commercial part. Indeed the trends in commercial parts toward smaller feature sizes and tighter spacing naturally lead to lower radiation tolerance (thinner gate oxides not withstanding). Industry standard practices, such as routine electrical design changes and layout shrinks for improved yield and greater die quantities per wafer, must be taken into consideration by those who would qualifi a commercial part by radiation testing. If tests are conducted on a different version number than that of the flight parts, the results are at best inappropriate and at worst As a minimum, a photomicrograph and spreading resistance profiles dangerously misleading. should be part of the test report for all COTS devices as a means to document their pedigree. Even modest changes to commercial processes to improve their radiation tolerance can make an immense difference in the level of design tradeoffs which must be made to achieve required hardness. Slight adjustments and improved controls for field threshold adjust implants can reduce leakage signific~tly and permit microcircuits to be designed with 2-edge transistors and still achieve 100 Krad(Si) tolerance. In many cases, such process modifications have no adverse impact on process complexity, yield, quality, or reliability. Ongoing programs to

V-50

<.

.. .

commercial manufacturers to employ such minor adjustment are expected to reap great benefits for the radiation effects community.

encourage

Where only pure commercial processes must be used, design practices can be employed to achieve levels of radiation tolerance consistent with many space applications. In general, these practices trade off area and performance for hardness. Consequently, they are limited in the functions they can address (i.e., no Pentium processors or 1 Mbit SRAMS). However, there are niche applications where design hardening can be usefid -- small quantity, low cost, modest performance, etc. It is one of the tools which will be available for designers of radiation tolerant space systems in the late 1990s and beyond. The example of radiation tolerant design presented here was quite straightforward and conservative. There are several groups (Boeing, Aerospace, TRW, UNM, and others) who are working on very elegant approaches which promise less restrictive compromises between radiation tolerance and performance. Also, developments in fabrication processes promise to open new routes for application of design hardening techniques. For example, Figure 30 shows a layout of the 0.8 pm NOR delay chain scaled down to a 0.25 ~m, filly depleted SOI (silicon on insulator) technology being developed by MIT/Lincoln Labs. The technology is being developed for commercial applications and hence will require the re-entrant N-channel transistors to eliminate edge leakage. Clearly, there is a significant area penalty compared to what could be achieved with 2-edge transistors, but there will still be room for a large number of the primitive cells. Furthermore, SEL will no longer be an issue. Such processing technologies may be expected to offer expanding opportunities for radiation tolerant design practices.

Figure 30. Design hardened gate array cell sized for 0.25pm SOI test chip. v-5 1

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4.

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5.

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of Radiation-Hardened

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P.S. Winokur, K.G. Kerris, and L. Harper, “Predicting CMOS Inverter Response Nuclear and Space Environments,” IEEE Trans. Nucl. Sci. 30,4326, 1983.

8.

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P.S. Winokur, K.G. Kerris, and L. Harper, “Predicting CMOS Inverter Nuclear and Space Environments,” IEEE Trans., Nucl. Sci. 30,4326, 1983.

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12.

D.J. Sleeter and E. W. Enlow, “The Relationship of Holding Points and a General Solution for CMOS Latchup,” IEEE Trans. on Elec. Dev. 39,2592,, 1992.

13.

Ionizing Radiation Efects in MOS Devices and Circuits, Editors: John Wiley & Sons, New York, 1989.

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Winokur, F.W. Sexton, J.R. Schwank, D.M. Fleetwood, P.V. Dressendorfer, T.F. Wrobel, and D.C. Turpin, “Total-Dose Radiation and Annealing Studies: Implications for Hardness Assurance Testing,” IEEE Trans. Nucl. Sci. 33, 1343, 1986.

15.

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“Latchup

in CMOS

State Generation

from

Single

in

in Field

Response

in

Effects on

Particles,”

IEEE

Ma and Dressendorfer,

P.S.

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MIL-STD-883D,

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17.

F.B. McLean and T.R. Oldham, “Basic Mechanisms of Radiation Effects in Electronic Materials and Devices,” Harry Diamond Laboratories, Technical Report HDL-TR-2129, 1987.

18.

J.C. Pickel and J.T. Bkmdford, Jr., “Cosmic Ray Induced Errors in MOS Memory Cells,” IEEE Trans. Nucl. Sci. 25, 1166, 1978.

19.

A.R. Knudson and A.B. Campbell, “Comparison of Experimental Charge Collection Waveforms with PISCES Calculations,” IEEE Trans. AJucl. Sci. 38, 1540, 1991.

20.

S.E. Diehl-Nagle, J.E. Vinson, and E.L. Peterson, “Single-Event Upset Rate Predictions for Complex Logic Systems, “ IEEE Trans. iVucl. Sci. 31, 1132, 1984.

21.

F. W. Sexton, “Measurement of Single-Event Phenomena in Devices and ICS,” 1992 Nuclear and Space Radiation E#ects Short Course, Chapter 3, New Orleans, July 1992.

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F.B. McLean

and T.R. Oldham,

Trans. Nucl. Sci. 29,2018, 23.

T.R. Oldham, Particles

24.

F.B. McLean,

with High dEldx,”

S.E. Kerns, L.W. L.R. Hite, “Model

36,2305, 25.

“Charge

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inn-

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“Revised

Calculations

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27.

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