1994 IEEE NSREC IEEE Nuclear and Space Radiation Effects Conference Short Course
Radiation
Effects
in Commercial
Electronics
July 18,1994 Westin La Paloma Resort Tucson, Arizona
II
Sponsored by IEEE NPSS Radiation Effects Committee
@
IEEE
Cosponsored by Defense Nuclear Agency / DOD Jet Propulsion Laboratory / NASA Sandia National Laboratories/DOE Phillips Laboratory / USAF
1994 IEEE NSREC IEEE Nuclear and Space Radiation Effects Conference Short Course
Radiation
Effects
in Commercial
Electronics
July 18,1994 Westin La Paloma Resort Tucson, Arizona
Copyright 01994 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. For all other copying, reprint, or replication permission, write to Copyrights and Permissions Department, IEEE Publishirw Services. 445 Hoes Lane. Piscatawav. NJ. 08855-1331.
TABLEOF CONTENTS
SECTION I P~ELUDE .................................................................................................1 1-6 Lloyd Massengill, Vanderbilt University SECTION II BASIC MECHAIVISMSOFRADIATIONEFFECTSIN THE NATURALSPAcEENVIRONMENT.........................................................Il 1-109 James Schwank, Sandia National Laboratories SECTION III RADIATIONCONCERNSINSTATE-OF-THE-ART PROCESSINGTECHNOLOGIES............................................................. III 1-27 Michael DeLaus, Analog Devices SECTION IV ADAPTINGCOMMERCIALELECTRONICSTOTHE NATURALLYOCCURRINGRADIATIONENVIRONMENT......................... IV 1-30 Nadim Haddad, Loral Federal Systems Thomas Scott, Loral Federal Systems SECTION V SINGLE-EVENTEFFECTSIN SYSTEMSUSINGCOMMERCIAL ELECTRONICSIN HARSHENWRONMENTS............................................V 1-77 Eugene Normand, Boeing Defense and Space Group
1994 NSREC SHORT COURSE
SECTION I
PRELUDE
LLOYD W. MASSENGILL VANDERBILTUNIVERSITY
This is the fifteenth year that a Tutorial Short Course has been offered on the first day of the IEEE International Nuclear and Space Radiation Effects Conference. In the past, these courses have proven to be interesting and informative for new and repeat conference attendees alike. My sincere desire is that this course will likewise be useful to you, whatever your background may be. Previous courses have also set an exceptionally high standard of professionalism and scientific merit; the authors of this course and I have endeavored to uphold this tradition. The theme of this year’s short course is “Radiation Effects in Commercial Electronics.” This is a very timely topic for several reasons. First, nonhardened integrated circuits are finding their way into space and other hostile environments due to several drivers, not the least of which is budgetary constraints. Second, there is a considerable recent effort in the areas of semi-tolerant and dual-use technologies which draw upon the strengths of advances in commercial technologies, yet maintain a level of radiation tolerance for certain well-defined hostile environments. Third, the growing sensitivity of electronics to natural radiation due to device and density scaling, as well as radiation introduced during state-of-the-art integrated circuit processing steps, is driving radiation-effects concerns into the totally commercial realm; that is, concerns about the relatively benign environments in the office or on a desktop. This course touches all three of these areas from various vantage points: basic physics, integrated circuit processing, circuit design, and systems effects; and with various perspectives: physics, engineering, and programmatic. This organization tack (several diverse treatments of a single topic), as well as the topic itself, is quite distinct from previous short courses. My hope is that this course is both enlightening and useful to you. This course follows a hierarchical path through the topic, from physical device effects up to system-level effects. The fwst topic, Basic Mechanisms of Radiation Effects, emphasizes the response of It provides commercial and hardened devices to natural radiation environments. background and tutorial information on radiation interactions with matter, and provides a foundation for the following topics. The second topic, Radiation Concerns in State-of-the-Art Processing Technologies, focuses on the technology-level issues of radiation effects on commercial integrated circuits. It presents a description of processing techniques for several technologies It also presents and compares commercial and military fabrication techniques. radiation sensitivities due to device scaling and novel processing techniques.
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The third topic, Adapting Commercial Efechvnics b h Radi@”on Environment, descrhs the circuit-level interactions of radiation with cornmercd“ electronic designs. It discusses the response of mnmerci al memory and microprocessor designs to radiation, tie adaptation of commercial cimuits to harsh environments, and the enhancement of commercial designs to improve radiation tolerance. The fourth topic, Singlk Event Effects in Systems Using Commercial Electwaics in Hamh Environments, focuses on system-level considerations in the use of commercial electronics in harsh environments. It detibes the single-event radiation environment which threatens cornmemial syskms and covers system considerations such as acceptability, mitigation, and reliability. I would like to thank the five authors/presenters for their hard work and tireless efforts. A project of this magnitude requires a dedication of countless hours not seen on the surface; I commend the authors on their donation of time and energy for the ongoing tradition of this course and the NSRE conference. I would also like to thank Dr. Timothy Oklham, the 1994 General Conference Chairman, for giving me the opportunity to organize this year’s course. Tm was very supportive and of great help throughout the year’s work cuh-ni.nating in this course. I also thank Lewis Cohn of DNA for his support of this course. The document you now hold would not have been made possible without the printing services of DNA, coordinated through Lew.
Lloyd W. Massengill Nashville, Tennessee
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BIOGRAPHIES Lloyd Massengill Short Course Organizer Vanderbilt University Lloyd Massengill is Associate Professor of Elecrncal and Computer Engineering and serves as the Microelectronics Group Leader at Vanderbilt University in Nashville TN. He has been involved in the radiation effects area since 1983, developing circuit/device models and CAD tools for rad-effects simulation. He has over 40 publications on these and other subjects, and has served the NSRE Conference as short course speaker, session chairman, awards committee member, and reviewer. In 1993, he received a Meritorious Paper award for the NSRE Conference. In the area of radiation effects contributions, Prof. Massengill identified and fwst modeled the railspan collapse dose-rate failure mechanism. He helped develop SEU models which demonstrated the localized charge-enhancement upset mechanism in SOI devices. He has developed SEU hardening techniques for semi-commercial circuits, such as the charge-partitioned resistive-load SRAM, and is presently working on circuit designs for semi-hard commercial DRAM technologies. He is also involved in the development of improved single-event error rate prediction techniques for integrated circuits in technologies such as SOI. Prof. Massengill has served the IEEE, of which he is a member, as a reviewer for the IEEE Transactions on Electron Devices, the Electron Device Letters, the Transactions on Nuclear Science, the Journal of SolidState Circuits, the Transactions on Circuits and Systems, and the Transactions on Neural Networks.
James Schwank Sandia National Laboratories James R. Schwank received his BS, MS and Ph.D. degrees in electrical engineering at the University of California at Los Angeles in 1970, 1974, and 1978 respectively. He joined Sandia National Laboratories in 1979 where he is a senior member of the technical staff, At Sandia he has been involved in numerous studies investigating the mechanisms of radiation effects in semiconductor devices, in developing techniques for improving the radiation hardness of MOS devices, and in hardness assurance activities. He discovered and identified the mechanisms for device “rebound”, a long-term IC failure mechanism important to space systems. Dr. Schwank has served the IEEE Nuclear and Space Radiation Effects Conference as session chairman, publicity chairman, and reviewer, and the Hardened Electronics and Radiation Technology (HEART) Conference as session chairman, guest editor, and technical program
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chairman. He won the Outstanding Conference Paper Awards at the 1984 and 1988 Nuclear and Space Radiation Effects Conferences and the 1985 and 1990 HEART Conferences. He has authored more than 60 papers on radiation effects in electronic devices. Dr. Schwank is a Fellow of the IEEE.
Michael DeLaus Analog Devices Michael D. DeLaus received his BS degree in Materials Science Engineering from the Massachusetts Institute of Technology in 1982. He began his career as a process/yield enhancement engineer at Harris Semiconductor. During his tenure at Harris, he worked on the Trident and SICBM programs. He was responsible for process enhancements designed to increase the manufacturability of both linear and digital radiation-hardened IC processes. In 1988 he joined the Advanced Process Development Group at Analog Devices. He heads a team tasked with radiationhardening a state-of-the-art commercial BiCMOS process for BMDO signal processing applications. Mr. DeLaus is a member of the IEEE and has been a reviewer for the Nuclear and Space Radiation Effects Conference and the IEEE Transactions on Nuclear Science. He was the Chairman of the 1993 NSREC Radiation Effects Data Workshop.
Thomas Scott Loral Federal Systems Thomas Scott received his BS degree from the University of Texas in 1986 and his MS from the University of Maryland in 1991. From 1978 to 1986, he was employed by TI to produce test stations for large scale computers. From 1987 to date, IBM (now Loral) has employed Mr. Scott to produce and head the Radiation Center of Competence for the Federal Systems portion of the company. He has authored four papers published at various radiation conferences both in the US and abroad. Two IBM technical disclosures have been published by him; one described a method to calculate Single Event Effect Failure rates based solely on test data that would be applicable to any failure mechanism. The second described a method to deriving proton cross-section versus energy data from heavy ion test results.
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Nadim Haddad Loral Federal Systems Nadim Haddad is a Senior Technical Staff Member at IBM Federal Systems Company in Manassas, VA. He received his BA in physics and mathematics from Kansas Wesleyan University in 1965, and MS in electrical engineering from Michigan State University in 1966 before joining IBM in 1967. Mr. Haddad was the driver behind the development of radiation hardened technology at IBM, and is responsible for the development and implementation of the VLSI technology strategy in FSC Manassas. He is currently the chief engineer for the radiation hardened lM SRAM development, and the principal investigator of a fully scaled 0.5 micrometer CMC)S, as well as submicrometer CMOS/SOI development IRAD tasks. Previous experience includes the management of semiconductor process development and device/process Mr. Haddad has ten inventions filed with the U.S. Patent engineering departments. Office, and has published over 20 papers in various technical journals and conference proceedings.
Eugene Normand Boeing Defense and Space Group Eugene Normand received his BS degree in chemical engineering from the Polytechnic Institute of Brooklyn in 1964, and his MS and Ph.D. degrees in nuclear engineering fi-om the University of Washington in 1966 and 1970, respectively. He began his professional career on the NERVA nuclear rocket with Aerojet Nuclear Systems Company in 1969. He moved to the architectural-engineering fm, Sargent and Lundy, in 1971. From 1979-84, he worked for the Puget Sound Power & Light Company. He joined Boeing in 1984 where he is currently group leader of the single event and energetic particle applications group within the Boeing Radiation Effects Laboratory (part of Boeing Defense & Space Group). He has served as principal investigator of the Boeing multi-megawatt space power reactor project and has investigated possible SEU effects on the IUS computer from neutrons produced by the RTGs powering the Galileo spacecraft. He has focused his attention on neutroninduced SEE and through several key papers, demonstrated the occurrence of SEU in avionics systems. His SEE group has been responsible for the testing and analysis of all microelectronics in the Work Package 01 portion of the Space Station and he has served as part of the working group that developed the Space Station ionizing radiation specifications. Dr. Normand has published more than 20 papers, primarily in the IEEE Transactions on Nuclear Science and the Transactions of the American Nuclear Society, authored a similar number of internal technical reports, chaired and served on three ANSI nuclear standards subcommittees and serves on the ANS Special Committee on Space Applications.
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1994 NSREC
II /
SHORT COURSE
SECTION 11
BASIC MECIiXNISMS OF RADIATION EFFECTS IN THE NATURAL SPACE ENVIRONMENT
J~ES SCHWmK SANDIANATIONtiLABORATORIES
Basic Mechanisms of Radiation Effects in the
Natural Space Radiation Environment
James Sandia
R. Schwank
National
Albuquerque,
NM
Laboratories 87185-1083
This work was supported by the U. S. Department of Energy through contract number DE-AC04-94AL85000.
Basic Mechanisms of Radiation Effects Natural Space Environment
in the
James R. Schwank Sandia National Laboratories Radiation Technology and Assurance Department 1.0 2.0
3.0
4.0
5.0
6.0
7.0
Introduction Natural Space Radiation Environment Particles trapped by the earth’s magnetic field 2.1 Cosmic rays 2.2 2.3 Radiation environment inside a spacecraft Laboratol”y radiation sources 2.4 Interaction of Radiation with Materials Ionization effects 3.1 Displacement effects 3.2 Total-Dose Effects — MOS Devices 4.1 Measurement techniques Electron-hole yield 4.2 Hole transport 4.3 4.4 Oxide traps 4.5 Interface traps Border traps 4.6 4.7 Device properties 4.8 Case studies 4.9 Special concerns for commercial devices Total-Dose Effects — Other Device Types SOI devices 5.1 Nitrided oxide devices 5.2 Single-Event Phenomena Mechanisms of charge collection 6.1 6.2 Hard errors Summary
1.0 INTRODUCTION Electronics in a satellite system can be degraded significantly by the natural space radiation environment, A major goal of the radiation effects community has been to provide devices that can function as intended in the harsh environment of space. This has required the development of process techniques to fabricate radiation-hardened devices and the development of reliable, cost-effective hardness assurance test procedures. To qualify a device for use in a space system, one must rely on laboratory measurements typically at dose rates from 50 to 300 rad/s in which the radiation exposure may take only minutes to hours to complete. These laboratory measurements must be correlated to a space environment in which the radiation
II-2
exposure may take place over a period of many years. To make these correlations, it is necessary to have a thorough understanding of the mechanisms that govern the radiation response of the devices to be used. This is especially true for systems employing commercial, non-radiationhardened devices where the margin between system requirements and device capability is much lower than for radiation-hardened devices. Thus, as commercial devices become increasingly more popular, the need for understanding radiation-response mechanisms becomes increasingly more important. Knowledge of the mechanisms of device radiation response has also enabled the fabrication of radiation-hardened devices. Therefore, understanding the basic mechanisms of radiation effects is of practical importance to the system, design, and technology engineer. In this portion of the Short Course, the basic mechanisms of radiation effects in the natural space environment are presented. The primary manners in which the natural space environment can cause degradation of electrical devices and systems are through total-dose ionizing-radiation damage, single-event related soft and hard errors, and displacement damage. Of these three, I cover total-dose and single-event effects. The goal of this portion of the course is to provide the student with the basic knowledge required to understand the mechanisms underlying the development of hardness assurance test guidelines and hardened-process technologies. Knowledge of the mechanisms will give the student more confidence in applying hardness assurance test guidelines for space and other applications. This portion of the Short Course is also intended to set the stage and provide the fundamentals for the remainder of the Short Course. Although the material presented focuses on device response in the natural space environment, much of the material presented is also applicable to the mechanisms of device response at short times after a pulse of irradiation (e.g., weapon application) and device response for moderate-dose-rate exposures. We begin with a description of the natural space radiation environment. This is the first step in determining the mechanisms governing device response. The mechanisms of device response depend on the type, energy, and concentrations of particles present in the space environment. The second step is to study the manner in which the particles interact with materials. For instance, protons can cause total-ionizing-radiation damage, single-event upset, and displacement damage. On the other hand, electrons cause primarily total-dose ionizing radiation damage and high-energy ions cause primarily single-event soft and hard errors. Once the manner in which radiation interacts with materials is determined, the third step is to determine the mechanisms that govern the response for the device type of interest for the particle(s) of interest. I focus in this portion of the Short Course on the mechanisms that govern the total-dose response of MOS devices. MOS devices constitute a major portion of the electronics of nearly all modern space systems. The material presented can be applied to the understanding of both commercial and radiation-hardened device response. Knowledge of the mechanisms that govern MOS device response can also be used to understand the mechanisms governing a number of other device types, including SOI and SOS devices and leakage current in advanced bipolar integrated circuits. I present the mechanisms of MOS device response at short times following high-dose-rate irradiations. Although knowledge of the short time response is not important for characterizing low-dose-rate space irradiations, the short-time response provides insight into the mechanisms governing radiation effects in both high- and low-dose-rate environments. Examples of case studies where knowledge of the basic mechanisms of radiation
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effects has led to technological improvements in device hardening and in hardness assurance test methodology are presented, I next discuss the basic mechanisms of device response for two device types that may see increased commercial use in the future: SOI and nitrided oxide devices. Finally, I cover the basic mechanisms of charge collection in silicon and GaAs devices leading to single-event effects. Mechanisms are covered at the transistor level. The mechanisms for heavyion induced single-vent burnout and single+vent gate rupture rre also discussed. 2.0 NATURAL SPACE IL4DIATION ENVIRONMENT The natural space environment can cause darnage to electronic systems in a number of ways. It contains high energy protons and electrons that can cause total-dose ionizing radiationinduced damage. Protons can also cause displacement damage. Heavy ions and high-energy protons can upset system operation and sometimes cause permanent darnage to electronics. The concentration and types of particles vary significantly with altitude and angle of inclination, recent solar activity, and amount of spacecraft shielding. As such, it is nearly impossible to define a “typical” space environment. Particles present in the earth’s natural space radiation environment can be grouped into two general categories: 1) particles trapped by the earth’s magnetic field (primarily electrons and protons), and 2) cosmic rays: heavy ions and high-energy protons of galactic or solar origin. In this section, some of the general properties of the natural space environment are presented. 2.1
Particles Trapped by the Earth’s Magnetic Field
The earths magnetic field creates a geomagnetic cavity known as the magnetosphere [1]. The magnetic field lines trap low-energy charged particles. These trapped particles consist primarily of electrons and protons, although some heavy ions are also trapped. The trapped particles gyrate spirally around the magnetic field lines and are reflected back and forth between the poles where the fields are confined. The motion of the trapped particles is illustrated in Fig. 1 [1]. As charged particles gyrate along the magnetic field lines, they also drift around the earth with electrons drifting in an easterly direction and protons drifting in a westerly direction. The motion of charged particles forms bands (or domains) of electrons and protons around the earth and form the earth’s radiation belts. The boundaries of the domains at the equator are illustrated in Fig. 2 [1]. Distances are specified in earth radii (one earth radius is equal to 6380 km) referenced to the center of the earth, i.e., one earth radius is at the earth’s surface. Because of the variation in the magnetic field lines with latitude, the boundaries of the domains vary with latitude (angle of inclination). Most satellites are operated in near-earth orbits at altitudes from slightly above 1 earth radius to 10 earth radii. Geosynchronous orbit (GEO) is at an altitude of approximately 35,800 km corresponding to approximately 6,6 earth radii. The domains can be divided into five regions. The trapped proton distribution exists primarily in regions one and two that extend from slightly above 1 earth radius to 3.8 earth radii. The distribution of proton flux as a function of energy and radial distance is given in Fig. 3 [1]. Flux is the rate at which particles impinge upon a unit surface area. It is normally given in units of particles/cm2-s. The time integral of flux is the fluence. Thus, fluence is equal to the total number of particles that impinge upon a unit surface
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Figure 1: Motion of trapped particles in the earth’s magnetosphere. (After Ref. 1) area for a given time interval and it is normally given in units of particles/cm2.] Trapped protons can have energies as high as 500 MeV [1]. Note that the altitude corresponding to the peak in flux decreases with proton energy for any given energy. Protons with energies greater than 10 MeV primarily occupy regions one and two below 3.8 earth radii [1]. Typical spacecraft shielding attenuates protons with energies below 10 MeV [2]. Thus, the predominant y lowenergy trapped protons present above 3.8 earth radii are normally ineffective in producing radiation-induced damage. For proton energies greater than 30 MeV, the highest proton flux occurs at about 1.5 earth radii. Protons originating from solar flares (discussed below) are present predominantly in regions four and five (Fig. 2) and extend from -5 earth radii to beyond 14 earth radii. Above the Atlantic Ocean off the coast of South America the geomagnetic sphere dips toward the earth causing a region of increased proton flux at relatively low altitudes. This region is called the South Atlantic anomaly (SAA). In this region, the flux for protons with energies greater than 30 MeV can be as much as 104 times higher than in comparable altitudes over other regions of the earth. At higher altitudes the magnetic sphere is more uniform and the South Atlantic anomaly disappears [3]. Electrons are present predominantly in regions one to four and extend up to 12 earth radii [1]. The electron domain is divided into two zones, an inner zone extending to about 2.8 earth radii and an outer zone extending from 2.8 to 12 earth radii. The outer zone electrons have higher fluxes (-10 times) and energies than the inner zone electrons. For electrons with energies greater than 1 MeV, the peak in flux is located between 3 and 4 earth radii [4]. The maximum energy of trapped electrons is approximately 7 MeV in the outer zone; whereas, the maximum energy is less than 5 MeV for electrons in the inner zone [1]. At these energies electron interactions are unimportant for single-event effects, but must be considered in determining totaldose effects.
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Region Solar Flare Protons Trapped Protons Outer Zone Electrons Inner Zone Electrons 1234567891011121314
Earth Radii
Inner Zone Electrons
Trapped Protons
Figure 2: Boundaries of the domains for solar flare and trapped protons and outer and inner zone electrons. (After Ref. 1) Fluxes of electrons and protons in particular orbits can be estimated from existing models. Two models that provide reasonable estimates of the proton and electron fluxes as a function of the satellite orbit are AP8 [5] for protons and AE8 [6] for electrons. An example of a calculation for a low earth orbit (LEO) (altitude of 500 km and latitude of 60 degrees) at solar minimum and maximum is presented in Fig. 4 [1]. Solar minimum and maximum refer to periods of minimum and maximum solar activity. Note that the flux of electrons decreases rapidly at high energies. 2.2
Cosmic Rays
Cosmic rays originate from two sources, the sun (solar) and sources outside our solar system (galactic). Galactic cosmic rays are always present. In the absence of solar activity, cosmic radiation is composed entirely of galactic radiation. Outside of our solar system, the spectrum of galactic cosmic rays is believed to be uniform. Its composition as a function of atomic mass is given in Fig. 5 [2,7]. It consists mostly of protons (85%) and alpha particles (helium nuclei) (14%). Less than 1% of the galactic cosmic ray spectrum is composed of highenergy heavy ions. This is not an indication that heavy ions are not as important as protons in
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Earth Radii Figure 3: Distribution of proton flux as a function of energy and radial distance. (After Ref. 1) space radiation effects. As will be discussed below, heavy ions deposit more energy per unit depth in a material than protons, and can actually cause greater numbers of single-event effects. As illustrated in Fig. 5, the flux of protons is more than two orders of magnitude higher than the flux of either carbon or oxygen and approximately five orders of magnitude higher than the flux of nickel. The energy spectrum of galactic cosmic rays is given in Fig. 6 [8]. Note that the x-axis of Fig. 6 is given in units of MeV/nucleon. Thus, for carbon with 12 nucleons, the point at 100 MeV/nucleon on the x-axis corresponds to an energy of 1.2 GeV. For most ions, the flux peaks between 100 and 1000 MeV/nucleon. For carbon, the peak flux is at an energy of approximately 2.4 GeV. For protons and alpha particles, the energy of the ion can be more than 100 GeV/nucleon. At these high energies, it is nearly impossible to shield electronics inside a spacecraft from cosmic rays. As cosmic rays penetrate into the magnetosphere, low-energy particles are attenuated, modifying the cosmic ray speetrum. Only the more energetic particles are able to penetrate the magnetosphere. Figure 7 [1] illustrates the attenuation of low-energy particles for a low-earth
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Figure 4: Calculated flux of electrons using the AE8 model for a low-earth orbit. (After Ref. 1) orbit (LEO) for several angles of inclination. Note that geomagnetic shielding decreases with higher inclination orbits as the magnetic field lines converge near the poles. The amount of solar cosmic rays is naturally dependent on the amount of solar activity. Solar flares are random in nature and account for a large part of all solar cosmic rays. After a solru flare occurs, particles begin to arrive near the earth within tens of minutes, peak in intensity within two hours to one day, and are gone within a few days to one week (except for some solar flare particles which are trapped in the earth’s radiation belts). In a solar flare, energetic protons, alpha particles and heavy ions are emitted. In most solar flares the majority of emitted particles are protons (90-95Yo) and alpha particles. Heavy ions constitute only a small fraction of the emitted particles, and the number of heavy ions is normally insignificant compared to the background concentration of heavy ions from galactic cosmic rays. In a large solar flare the number of protons and alpha particles can be greatly enhanced (-104 times) over the background galactic cosmic ray spectrum; whereas, the number of heavy ions for a large solar flare approaches up to -50% of the background galactic cosmic concentration of heavy ions [9]. Associated with a solar flare is the solar wind or solar plasma. The solar wind usually arrives near the earth within one to two days after a solar flare [10]. As the solar wind strikes the magnetosphere, it can cause disturbances in the geomagnetic fields (geomagnetic storm), compressing them towards the earth. As a result, the solar wind can enhance the total-dose that a device receives in a low-earth orbit.
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ATOMIC MASS Flux of galactic cosmic ray particles for atomic masses up to 60. (After Refs. 2 and 7) Figure 8 [11] is a plot of the angular flux of cosmic ray particles (both solar and galactic) during solar minimum and maximum inside a spacecraft in geosynchronous orbit with 25 roils of aluminum shielding as a function of linear energy transfer (LET). [LET is the mass stopping power of cosmic rays and is given in the units of MeV/mg/cm2. It is a measure of the amount of energy a particle transfers to a material per unit path length.] The solar cycle is approximately 22 years long with peaks in intensity approximately every 11 yeas. Solar maximum refers to periods of maximum solar activity, and solar minimum refers to periods of minimum solar activity. The solar wind during periods of high solar activity reduces the galactic cosmic ray flux. Thus, the minimum in galactic cosmic ray flux occurs during solar maximum, and the maximum in galactic cosmic ray flux occurs during solar minimum. The flux at solar minimum describes the actual environment for 40% of the time. Also shown in Fig. 8 is the Adams’ 10% worst-case environment. The actual environment is more intense than the Adams’ 10qo worstcase environment only 10% of the time. It includes contributions from both galactic and solar cosmic rays. This environment is often used in assessing the single-event upset hardness of electronic devices. 2.3
Radiation Environment
Inside a Spacecraft
Thus far, we have explored the natural space radiation environment outside a spacecraft. To determine the effects of the natural space environment on electronics inside the spacecraft, the effects of shielding must be taken into account. Shielding not only modifies the radiation environment inside a spacecraft by altering the energy and concentration of incoming particles,
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Figure 6: Energy spectrum of galactic cosmic rays. (After Ref. 8) but also can create secondary particles as the incoming particles pass through the shielding. For instance, bremsstrahlung radiation in the form of x rays is emitted as energetic electrons decelerate in the shielding. For modest amounts of shielding, the effects of shielding can be estimated by taking into account only the energy loss of particles as they pass through the shielding [11 ]. The amount of energy loss as a particle passes through shielding depends on the thickness of the material. Typical spacecraft shielding is in the range of 100 to 250 roils. Figure 9a [12] is a plot of flux for a large solar flare versus LET for aluminum thicknesses of 0.173 to 10.8 g/cm2. Note that increasing aluminum thickness results in decreasing solar flare flux for the relatively low-energy particles associated with a solar flare. However, the qualitative variation in flux with LET is relatively unaffected by the shielding. For LETs above 30 MeV-cmz/mg increasing the shielding thickness from 0.17 g/cm2 (25 roils) to 10.8 g/cm2 (1570 roils) reduces the intensity of the spectrum by five orders of magnitude. The effect of spacecraft thickness on galactic cosmic ray flux is shown in Fig. 9b [12]. It takes much more shielding to reduce the intensity of galactic cosmic rays. Spacecraft thicknesses of aluminum from zero up to 10 g/cm2 (1450 roils) only slightly affect the LET spectrum. By comparing Figs. 9a and 9b, we conclude that spacecraft shielding can attenuate the low-energy nuclei from a solar flare, but has little effect on the attenuation of nuclei in the galactic cosmic ray spectrum. Thus, for practical shielding thicknesses, additional shielding may prove effective against soft components of a solar flare environment, but is relatively ineffective in reducing the galactic cosmic ray spectrum [2].
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ENERGY (MeV/nucleon) Figure 7: Attenuation of electron flux as a function of electron energy and angle of inclination for a low-earth orbit. (After Ref. 1) Figure 10 [13] is a plot of the contribution of protons, electrons, and bremsstrahlung to the total dose received after a period of 139 days as a function of aluminum thickness measured aboard the Explorer 55 spacecraft [13]. The data were taken during a period of minimum solar activity. [Note that we have specified total-dose in units of rad(Al). A rad is defined as radiation absorbed dose. It is a measure of the amount of energy deposited in the material and is equal to 100 ergs of energy deposited per gram of material. The energy deposited in a device must be specified for the material of interest. Thus, for a MOS transistor, total dose is measured in units of rad(Si) or rad(Si02).] For small aluminum thicknesses, both electrons and protons contribute to the total-absorbed dose. However, for aluminum thicknesses greater than -150 roils, the electron contribution to the total dose is negligible. The contribution of bremsstrahlung radiation to the total absorbed dose is negligible for all aluminum thicknesses. Increasing the shielding thickness from 100 to 250 roils of aluminum decreases the proton dose by less than a factor of two. Although these data are for a specific satellite orbit, the trends indicated in Fig, 10 are typical for those of other orbits. As is apparent from Figs. 2 and 3, the total dose that a device is exposed to in a space environment is highly dependent on the orbit. To determine the total dose, one must include contributions from both electrons and protons. The dose rate can vary over a wide range, from less than 10-6 to mid 10-3 rad(Si)/s. For a five year mission life, these dose rates correspond to a
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LET (MeV/mg/cm2) Figure 8: Flux of cosmic ray particles at solar maximum, at solar minimum, and for Adams’ 10% worst-case environment. (After Ref. 11) total-dose range of less than 1 krad(Si) to more than 5 Mrad(Si). For low-earth orbits at high inclination, 200 roils of aluminum shielding can limit the total proton dose to less than 1 krad(Si) per year [14]. Other orbits can result in total doses several orders of magnitude higher. At altitudes corresponding to roughly 1/2 the altitude at geosynchronous orbit (near worst case), the total dose that a device can receive inside a spacecraft with light shielding can approach 1 Mrad(Si) per year [1,15]. 2.4
Laboratory Radiation Sources
A wide range of laboratory sources are available to characterize the response of electronic devices. For total-dose effects, these sources range from very high-dose-rate sources for characterizing device response in weapon environments or for investigating the basic mechanisms of radiation effects to very low-dose-rate sources for simulating the total-dose response of electronic devices in the natural space environment. The most common laboratory sources are moderate-dose-rate CO-60 and x-ray sources. CO-60 sources emit gamma rays with a nominal energy of 1.25 MeV. These sources can have dose rates up to 400 rad(Si)/s. The present U, S. military standard test guideline MIL-STD-883D, Method 1019.4 specifies that laborato~ acceptance testing must be performed at dose rates from 50 to 300 rad(Si)/s. Thus, Co-60 sources can normally meet these requirements. Another common type of laboratory
It-12
=5 ‘?
%0
‘P-%
:0.675 @cr#
f
E u
x 2 u
-15
j
.,0 ~ 1@
10-2
1(-J-1 l@J
101
102
2 @cd
10
-5
Y ~ x
.10
j
.20 ~
102
l@
g/cr#
50 @cmz
100 g/cm2
10-2 10-1 l@
101
LET (MeV-cm2 /mg)
LET (MeV-cm2 /mg)
a)
b)
102
102
Figure 9: The effects of aluminum shielding on the attenuation of the flux from a large solar flare a) and of the flux from the galactic cosmic ray speetrum b) as a function of the LET of the incident particles. (After Ref. 12) source is the 10-keV x-ray source. Laboratory x-ray sources are available that can achieve dose rates from below 300 rad(Si)/s to above 3600 rad(Si)/s and that can test unlidded package devices or devices on a wafer. X-ray sources have a nominal energy of 10 keV. The high dose rate of x-ray sources and the capability for testing at the wafer level allows for rapid feedback on radiation hardness during device fabrication [16]. Two high-dose-rate sources that can be used to investigate the total-dose response of electronic devices at short times after a pulse of radiation are electron linear accelerators (LINACS) and proton cyclotrons. Electron LINACS are pulse type sources with pulse widths ranging from less than 20 ns to more than 10 w with energies from 10 MeV to more than 40 MeV. Dose rates greater than 101] rad(Si)/s can be obtained from electron LINACS. Proton cyclotrons are quasi-continuous sources and can have dose rates as high as 1 Mrad(Si)/s with energies from around 40 MeV to greater than 200 MeV. They can also be operated in low current modes suitable for characterizing proton-induced single-event effects. For simulating low-dose-rate total-dose effects, CO-60 and Cs- 137 sources are available. Cs- 137 sources emit gamma rays with a nominal energy of 0.66 MeV. Dose rates below 0.01 rad(Si)/s can be obtained from Cs- 137 radiation sources, There are a wide range of sources available for characterizing heavy-ion induced singleevent effects. These sources vary widely in ion species, energy, and flux. Two often used sources in the U. S, are Brookhaven National Laboratories’ Twin Tandem van de Graaff accelerator and Lawrence Berkeley Laboratories’ 88-inch cyclotron. At the Brookhaven facility, ions are available, ranging from protons with energies of 30 MeV (maximum) and LETs of 0.02 MeV-cm2/mg to gold with energies of 350 MeV and LETs of 81 MeV-cm2/mg (in silicon at normal incidence and maximum energy). At Berkeley’s facility, ions are available ranging from protons with energies of 60 MeV (maximum) and LETs of 0.009 MeV-cm2/mg to bismuth with energies of 803 MeV and LETs of 95 MeV-cm2/mg (in silicon at normal incidence and
II-13
RADIATION ENVIRONMENT
\
EXPLORER 55 139 DAYS IN ORBK SLAB DOSES
. \
\
,
-
TOTAL
‘ PROTONS -
.
ELECTRONS \*
.
BREMSSTRAHLUNG
100
200
300
SHIELD THICKNESS (roils of Al) Figure 10: Contributions of protons, ekctrons, and bremsstrahlung to total dose as a function of aluminum shielding. The data were taken after a 139-day exposure during the Explorer 55 space mission. (After Ref. 13) maximum energy).
Xnaddition to these fiwilities, other facilities are available in the U. S. and throughoutthe worldfor characterizing the single-eventupsetpropertiesof electronicdevices, 3,0 IRTERACTK)N
OF RADIATION
WITH MATERIALS
The manner in which radiation interacts with solid material depends on the type, kinetic energy, mass, and charge state of the incoming prticIe and the mass, atomic number, and density of the target material. In thk sectiun, we discuss the manner in which the different types of radiation interact with materials.
II- 14
~
EMllTED
ELECTRON
PHOTOELECTRONIC PHOTON
INCOMING PHOTON
●
“a a) EMIITED
ELECTRON
COMPTON PHOTON ~o~
6 b) ELECTRON
–o \ ●
c)
/
‘1
POSITRON
Figure 11: Schematic drawing of three processes through which photons interact with material: a) photoelectric effect, b) Compton scattering, and c) pair production. 3.1
Ionization Effects
Ionization of the target material occurs for photons, electrons, protons, and energetic heavy ions. Photon interactions are not a primary concern for satellites in the natural space environment. However, we include photon interactions in this discussion because of their importance in hardness assurance testing. Most laboratory sources used to simulate total-dose space environment effects emit either low-energy x rays or high-energy gamma rays.
3.1.1 Photon Effects Photons interact with material through three different processes, namely the photoelectric (or fluorescent) effect, the Compton effect, and pair production [17]. These processes are illustrated in Fig. 11. For each of these processes, the primary result of the interaction is the creation of energetic secondaq electrons. Low-energy photons interact with material predominantly through the photoelectric effect. The photoelectric effect is illustrated in Fig. 11a. In this process, an incident photon excites an electron from an inner shell of a target atom to a high enough state to be emitted free
II-15
r
120
# , , , ,I I
,
r , , , , , ,I
,
1 , , 1 , 1I
,
,
1 , 1 11
1
100
-
PHOTOELECTRIC
EFFECT
&
80 60 COMPTON
40 N
SCAITERING
20 0
0.01
10
0.1 PHOTON E&RGY
100
(MeV)
Figure 12: Relative importance of the photoelectric effect, Compton scattering, and pair production as a function of photon energy. (After Ref. 18) of the target atom. For the photoelectric effect, the incident photon is completely absorbed. Thus, the photoelectric effect creates a free electron (photoelectric electron) and an ionized atom. In addition, as the photoelectric electron is emitted, an electron in an outer orbit of the atom will fall into the spot vacated by the photoelectron causing a low energy photon to be emitted. For higher energy photons, Compton scattering will dominate over the photoelectric effect, Compton scattering is illustrated in Fig. 11b. In this process, as a photon collides with an atom, the photon transfers a fraction of its energy to an electron of the target atom, giving the electron sufficient energy to be emitted free of the target atom. For Compton scattering, a photon of lower energy is created which is free to interact with other target atoms. It also creates a free electron and an ionized atom. Pair production occurs only for very-high energy photons in Fig. 1lc. In pair production, the incident photon collides electron-positron pair. A positron has the same properties as except that the charge is positive. The incident photon is production.
(E> 1.02 MeV). It is illustrated with a target atom creating an an electron (charge and mass), completely annihilated in pair
The relative importance of the three processes as a function of photon energy and atomic mass of the target material is illustrated in Fig. 12 [18]. Indicated in the Fig. 12 are the regions where each process dominates. The solid lines correspond to equal probabilities for the different interactions. The dashed line corresponds to the atomic mass of silicon (2=14). Thus for silicon, x rays emitted from a low-energy (typically 10 keV) x-ray irradiator will interact predominantly
II-16
through the photoelectric effect, while high-energy gamma rays (typically 1.25 MeV) from a Co60 source will interact predominantly through Compton scattering. 3.1.2
Electron-Hole
Pair Generation
High-energy electrons (secondary electrons generated by photon interactions or electrons present in the environment) and protons can ionize atoms, generating electron-hole pairs. As long as the energies of the electrons and holes generated are higher than the minimum energy required to create an electron-hole pair, they can in turn generate additional electron-hole pairs. In this manner, a single, high enough energy incident photon, electron, or proton can create thousands or even millions of electron-hole pairs. The minimum energy required for creating an AISO electron-hole pair, EP, in silicon, silicon/dioxide and GaAs is given in Table I [17,19,20]. given in Table I are the densities [21] for the three materials and the initial charge pair density per rad deposited in the material, go [17]. The latter quantity is obtained from the product of the material density and the deposited energy per rad ( 1 rad = 100 erg/g = 6.24 x 1013eV/g) divided by EP [17]. Table I: Minimum energies for creating electron-hole silicon, and silicon dioxide. Material
EP (eV)
Density (g/cm3)
GaAs Silicon Silicon Dioxide
-4.8 3.6 17
5.32 2.328 2.2
3.1.3
pairs and densities
for GaAs,
Pair density generated per rad, go (pairs/cms) -7 x 1013 4x 10’3 8.1x1012
Dose Enhancement
One additional factor that must be taken into account in determining the total number of electron-hole pairs generated in a material is dose enhancement. Dose enhancement arises when an incident particle travels through two adj scent materials with different atomic masses. Close to the interface of two materials, charge particle equilibrium is not maintained. Charge particle equilibrium is defined as the condition where the total energy carried out of a given mass element by electrons is equal to the energy carried into it by electrons [4]. For two adjacent materials with different atomic masses, close to the interface of the materials the number of electrons generated in the low-atomic mass material will be higher than for the case where charge particle This effect is called dose equilibrium is maintained (i.e., far away from the interface). enhancement. It is illustrated in Fig. 13 [4]. In charge particle equilibrium (Fig. 13a) the ratio of the relative doses in two materials depends on the absorption properties of the materials. It can be defined as
II- 17
4.5 r RELATIVE DOSE
Si
3.5
Au
3.0 [ 2.5 t
3mm
2mm
lmm
50pm
O
100pm 150pm
(a)
4.5
EQULMRIUM
2.5
3mm
2mm
DIRECTION OF ‘ RADIATION
lmm
O
50pm
I
100pm 150pm
(b)
4.5
RELATIVE DOSE
4.0
-----
SI
EQULMRIUM DOSE
3.5 L
EQUILIBRIUM DOSE - ----------
Au
3.0
J) 2.5 ~
3mm
I
I
2mm
lmm
O
DIRECTION OF RADIATION 50pm
I
100pm 150pm
(c) Figure 13: Relative dose enhancement at the silicon/gold interface. Figure 13a is the relative dose in charge-particle equilibrium, b) for the direction of the incident radiation going from the silicon to the gold, and c) for the direction of the incident radiation going from the gold to the silicon. (After Ref. 4)
II-18
D,,(l) Deq(2)
= (We.lP)]
(1)
(P’,n 1 P)2 ‘
where Dw( 1,2) are the relative doses for materials 1 and 2, and (~~p)l,z are the mass energy absorption coefficients of materials 1 and 2. p I and p2 are the material densities. However, close to the interface of the materials, charge particle equilibrium is not maintained and the relative dose in the low atomic mass material can be much higher than it is in charge particle equilibrium as indicated in Figs. 13b and 13c. For example, as indicated in Fig. 13b, charge particle equilibrium is maintained for distances of more than -1.5 mm in the silicon away from the However, close to the interface, dose interface and of more than -75 mm in the gold. enhancement has increased the relative dose in the silicon by approximately 409Z0. Note that the direction of the incident particles significantly affects the magnitude of dose enhancement. The amount of dose enhancement will depend on the mechanism by which an incident photon interacts with a material. It will be largest for low-energy photons (ccl MeV) which interact through the photoelectric effect [22]. For an MOS transistor with a polysilicon gate, the atomic mass of silicon is slightly above the atomic mass of silicon dioxide and the amount of dose enhancement is negligible for 1.25 MeV CO-60 gamma rays (which interact through the Compton scattering). On the other hand, for low-energy 10-keV x rays (which interact through the photoelectric effect) the amount of dose enhancement can be relatively large (-1.8) [23,24]. Thus, for 1.25 MeV gamma rays, dose[rad(Si)] = dose[rad(SiOz)] and for 10-keV x rays, dose[rad(Si)] = 1.8xdose[rad(Si02)]. Higher dose enhancement factors will result for metal silicide gates with higher atomic masses (e.g., tungsten and tantalum) [22,25]. For those materials in which significant dose enhancement can occur, the number of electron-hole pairs generated by the incident radiation must be multiplied by a dose-enhancement factor to determine the total number of electron-hole pairs generated. 3.2
Displacement
Effects
In this section, we give a very brief overview of the basics of displacement damage in materials. In addition to ionization effects, high-energy protons can also cause displacement darnage in silicon and other semiconductor materials [17,26-28]. As a high-energy proton collides with an atom, the atom will recoil from its lattice site. If the energy transferred to the atom is high enough, the atom can be knocked free from its lattice site to an interstitial site. The minimum energy required to knock an atom free of its lattice site is called the displacement threshold energy. As the atom is displaced from its original position it leaves behind a vacancy. The combination of the interstitial atom and its vacancy is called a Frenkel pair. If the displaced atom has sufficient energy it can in turn displace other atoms. Thus, for very high energy recoils a defect cascade can be created with large defect clusters. A “typical” distribution of clusters produced by a 50-keV silicon recoil atom is illustrated in Fig. 14 [26]. As the primary silicon atom travels through the silicon, it knocks free other atoms and it is in turn reflected, altering its path. Towards the ends of the paths of the reflected atoms (and the primary atom) large clusters of defects may be formed (terminal clusters). About 90?I0 of the displaced atom and vacancy pairs recombine within a minute after irradiation at room temperature.
II-19
800 AZN
EWE:L
‘.’,‘./
\\ f# /’ \’
600
t
400
50 keV Si I
‘TERMINAL CLUSTER 1
TERMINAL
200
CLUSTER
TERMINAL CLUSTER
~F\ \
#./ -~
\ “, -. .-
Q&!’
0 -360
-240
-120
0
120
240 360
DISTANCE (~) Figure 14: Defect cascade created by a 50-keV silicon recoil atom. (After Ref. 26) The primary effect of displacement darnage is the creation of deep and shallow level traps in the material [26-28]. The shallow level traps can compensate majority carriers and cause carrier removal. Deep level traps can act as generation, recombination, or trapping centers. These centers can decrease the minority carrier lifetime, increase the thermal generation rate of electron-hole pairs, and reduce the mobility of carriers. As a result, displacement damage is a concern primarily for minority carrier (e.g., bipolar transistors) and optoelectronic devices. It is relatively unimportant for MOS transistors, 4.0 TOTAL-DOSE
EFFECTS — MOS DEVICES
If an MOS transistor is exposed to high-energy ionizing irradiation, electron-hole pairs will be created uniformly throughout the oxide. The generated carriers induce the buildup of charge which can lead to device degradation. The mechanisms by which device degradation occurs are depicted in Fig. 15 [17]. Figure 15 is a plot of an MOS band diagram for a positively applied gate bias. Immediately after irradiation, electrons will rapidly drift (within picosecond) toward the gate and holes will drift toward the Si/Si02 interface, However, even before the electrons leave the oxide, some fraction will recombine with holes. The fraction of electron-hole pairs that escape recombination is the electron-hole yield. Those holes which escape “initial”
11-20
)EEP HOLE TRAPPING IEAR THE SVS02 INTERFACE 1+ +.
+
+
r
ELECTRON-HOLE PAIRS GENERATED BY IONIZING RADIATION / /
POLY-Si
RESULTING FROM INTERACTION OF HOLES
~~b / ●
HOPPING TRANSPORT OF HOLES THROUGH LOCALIZED STATES IN S102 BULK
✏ ●
/@
*
,1
Figure 15: Band diagram of an MOS device with a positive gate bias. Illustrated are the main processes for radiation-induced charge generation. (After Ref. 17) recombination will transport through the oxide toward the Si/Si02 interface by hopping through localized states in the oxide. As the holes approach the interface, some fraction of the holes will be trapped, forming a positive oxide-trap charge. Large concentrations of oxide-trap charge can cause increased leakage current of an integrated circuit. Hydrogen ions are likely released as holes “hop” through the oxide or as they are trapped near the Si/Si02 interface. The hydrogen ions can drift to the Si/Si02 where they may react to form interface traps. At threshold, interface traps are predominantly positively charged for p-channel transistors and negatively charged for nchannel transistors. Large concentrations of interface-trap charge can decrease the mobility of carriers and increase the threshold voltage of n-channel transistors. These effects will tend to decrease the drive of transistors, degrading timing parameters of an IC. In this section, we present the details of oxide-trap and interface-trap charge buildup in MOS transistors. 4.1
Measurement Techniques
Before we begin to discuss mechanisms and device properties for the buildup of charge in MOS transistors and capacitors, let us first take a look at some of the measurement techniques used to electrically and microscopically characterize defects in MOS capacitors and transistor. In this section, we discuss some of the more common characterization techniques.
H-2 1
100 80 60 40 20
0r
-10
I
1
-8
1
1
I
1
I
I
I
-6 -4 -2 0 GATE VOLTAGE (V)
1
I
2
1
1 4
Figure 16: Typical C-V traces taken on an MOS capacitor preirradiation and 2.2 s after a 1 Mrad(Si) irradiation. Noted on the C-V traces are the points corresponding to flatband (CtJ, midgap (Cw), and inversion (Cinv)capacitance. 4.1.1
Electrical Techniques
To characterize hole transport and oxide-trap and interface-trap charge buildup, either capacitor and transistor test structures are used. MOS capacitors are characterized by analyzing high-frequency and/or low-frequency quasi-static capacitance-voltage (C-V) curves. Figure 16 is a typical set of high-frequency C-V traces pre- and postirradiation. Plotted is the capacitance versus gate voltage for an n-substrate capacitor preirradiation and 2.2 s after irradiating to 1 Mrad(Si). The C-V curves were taken using a 1 MHz sinusoidal signal superimposed on top of a 10 mV/s ramp. Noted on the C-V traces are the points corresponding to flatband, midgap, and inversion capacitance. These points are defined as the silicon surface potential at O, @B,and 2$~, respectively, where $B is the bulk potential given by [21]
OB. ~hl*, (7,
[)
(2)
q is the magnitude of the charge of an electron, k is Boltzmann’s constant, T is the absolute temperature, and ND and Ni are the substrate and intrinsic carrier doping concentrations,
II-22
respectively. Assuming that interface traps are approximately charge-neutral at midgap [29-32], the difference in the voltage shift at midgap between the pre- and postirradiation C-V curves is equal to the threshold-voltage shift due to oxide-trap charge, AVOt. The number of interface traps can be estimated from the stretchout in the C-V curves. For instance, the number of interface traps from flatband to midgap can be determined from the voltage shift at flatband, pre- and postirradiation, minus the voltage shift at rnidgap, pre- and postirradiation. Similarly, the number of interface traps from midgap to inversion can be determined from the voltage shift at midgap, pre- and postirradiation, minus the voltage shift at inversion, pre- and postirradiation. Defining the voltage stretchout in the C-V curves as AVit, the number of radiation-induced interface traps, ANit, is given by
(3)
where COXis the oxide capacitance per unit area. For C-V curves taken on an n-type substrate as shown in Fig. 16, analyzing the C-V curves from midgap to inversion gives the number of interface traps in the lower part of the silicon band gap corresponding to the number of interface traps near threshold for a p-channel transistor. The flatband-voltage shift contains contributions from both interface-trap and oxide-trap charge. However, short times after a pulse of irradiation, interface-trap buildup may be small (see Section 4.5.1), and the flatband-voltage shift is dominated often by the number of holes in the oxide: either those in transport through the oxide or trapped at defects near the Si/Si02 interface. Time constants are short at flatband [30] making it possible to make high-speed C-V measurements near flatband. Thus, flatband-voltage shift measurements are a good monitor of hole transport and trapping effects shortly after a pulse of irradiation. There are a number of techniques that have been used to electrically characterize radiation-induced defects in MOS transistors. Threshold voltages are normally determined by measuring I-V curves in either the linear region (small drain bias) or in the saturation region (large drain bias). For small drain bias (V~s << V~s - v~h), the drain current in the linear region, I~s(lin), varies as [21]
IDS(k)
=
wcox~ ~GS‘~h)v~s
L(
(4)
,
where L is the carrier mobility, W is the width of the device, L is the length, Vcs is the gate-tosource bias, VDs is the drain-to-source bias, and Vth is the threshold voltage. Thus, the threshold voltage can be determined from the voltage intercept of a plot of IDSversus VGs curve. Note that the threshold voltage determined from Eq. (4) does not give the same value as the inversion voltage for capacitors defined as the surface potential equal to 2$B [29,33]. The carrier mobility can be determined from the slope of the curve ~
II-23
1 ()-3 )
I
I
I
I
I
I
1 ()-5
1-
Z w m a
I 0-7
1 ()-9
500 krad 10-11
# ,## ,,H”””””””””””””;P’: , N’ 44 I I
10-13
10-15
-1.5
-1.0
””-””’ 1
MIDGAP (Y= @B) I
I 1.5
-0.5
GAT~VOLT&GE
2.0
(V;mo
Figure 17: I-V traces taken on an MOS transistor preirradiation and after irradiating to 500 krad(Si). Noted on the I-V traces are the points corresponding to threshold and midgap. In the saturation region, the drain current, I~~(sat), varies as [21]
(5)
where m is a constant dependent on the doping concentration and approaches a value of 1/2 at low doping levels. The threshold voltage in the saturation region can be determined from the voltage intercept of the square root of the drain-current versus gate-voltage curve. To characterize the individual contributions of interface- and/or oxide-trap charge in transistors, two common techniques are the midgap I-V technique [29] and the charge-pumping technique [34,35]. The midgap technique is very similar in nature to the high-frequency C-V technique discussed above. It can be used to obtain estimates of the threshold-voltage shifts due to interface-trap and oxide-trap charge. Figure 17 is a set of I-V curves for an n-channel transistor taken preirradiation and after irradiating to 500 krad(Si). The I-V curves were taken by ramping the gate voltage from -1.5 V to 2 V at a ramp rate of -4 V/s and with a drain voltage of 5 V. Noted on the I-V curves are the points corresponding to the threshold and midgap voltage points. The midgap voltage is determined by calculating the midgap current [21] and extrapolating the I-V curves to the voltage point corresponding to the calculated midgap current. Similar to high-frequency C-V analysis, the threshold-voltage shift due to oxide-trap charge, AVOI,is determined from the voltage shift between the pre- and postirradiation I-V curves at the rnidgap point, and the total-threshold-voltage shift, AVti, is determined from the voltage shift between the pre- and postimadiation I-V curves at the threshold-voltage point. The threshold-
11-24
voltage shift due to interface-trap charge, AVit, is determined from the stretchout curves, i.e., the difference in the voltage shift at threshold pre- and postirradiation voltage shift at midgap pre- and postirradiation.
in the I-V minus the
In addition to these techniques, other techniques for determining AVit and AVOthave been developed, These include single-transistor techniques based on mobility measurements [36,37] and dual-transistor techniques combining mobility and threshold-voltage measurements [38,39]. The charge-pumping technique is a very sensitive technique that can be used to measure small changes in interface-trap density, ADit [34,35]. It is considerably more sensitive in this regard than either the midgap I-V technique or high-frequency C-V techniques. It is also relatively insensitive to charge lateral non-uniformities [35] and can be used for short time (<1 s) measurements [35]. However, charge pumping directly measures neither ADil nor AVil. Instead, both of these parameters are inferred from the charge-pumping current. By itself, charge pumping cannot be used to provide accurate and direct measurements of AVO,[33]. When a transistor is continuously pulsed from inversion to accumulation by applying a charge-pumping signal between its gate and substrate, a charge-pumping current in the substrate results, as minority and majority carriers are captured and emitted from traps at the Si/Si02 interface. For a triangular charge-pumping waveform, the charge-pumping current, ~P, is related to the average density of interface traps, Dit, through the equation [34]
(6)
where A is the transistor area, Vti is the thermal velocity of the carriers, Ni is the intrinsic carrier concentration, On and 6P are the electron and hole capture cross-sections, Vh is the flatband voltage, and f and AVE are the frequency and amplitude of the measurement signal, respectively, To accurately calculate Dit, one must know the effective interface-trap capture cross-section as a function of dose [40]. Also, due to uncertainties caused by geometric components of the chargepumping current, there is some question about the accuracy of calculating Di~ in some devices from the charge-pumping current [34,4 1,42]. In addition, there are difficulties in converting ADil into AVit due to uncertainty about which portion of the band gap contributes to the chargepumping current [33]. Nevertheless, charge pumping is a very useful tool for characterizing interface-trap buildup in MOS transistors. 4.1.2
Microstructural
Techniques — Electron Spin Resonance
A powerful measurement technique that has greatly increased our knowledge of the structure of defects in Si02 at the microscopic level is electron paramagnetic resonance (EPR) or electron spin resonance (ESR) [43]. In EPR, the energy associated with the intrinsic angular momentum (spin) of an electron is measured. Spin is quantized with quantum number 1/2, i.e., it can have only two orientations with respect to the axis of an applied magnetic field. The
II-25
3366
3364
3368
3370
3372
3374
Magnetic Field (Gauss) Figure 18: Typical electron paramagnetic resonance spectrum. (After Ref. 44) difference in energy between two states with different spin is given by E = hv = g~H, where v is the microwave frequency, H is the magnetic field strength, ~ is the Bohr magneton (~ = eh/4mnc), and g is a dimensionless tensor which gives information on the amount of splitting, characteristic of the atom or ion, and information regarding the symmetry of the defect. In an electron paramagnetic resonance system, the sample under test is placed in a microwave cavity and a DC magnetic field is applied, The magnetic field is varied. If a point is reached where the microwave energy, hv, is equal to g~H, an unpaired electron can resonate between the two energy levels. Measurement of the “resonance absorption” point gives information on the gvalue or tensor. Note that the atom or ion must be paramagnetic, i.e., have an unpaired electron or electrons, in order to observe a rmonance absorption (EPR signal). If the atom or ion is diamagnetic, i.e., it has no net electronic magnetic moment, an EPR signal will not be measured. An example of an EPR spectrum taken on an irradiated thermally grown oxide is shown in Fig, 18 [44]. The double humped feature is characteristic of axially symmetric point defects in amorphous materials. The defect contributing to the signal in Fig. 18 is called an E’ center. Details of the E’ center are given in Section 4.4.3. Information on the g-tensor as a function of the angle of the magnetic field, hyperllne interactions or multiple signals, and the width of the absorption lines can often be used to identi~ the structure of the atom or ion. 4.2
Electron-Hole
Yield
We now begin our discussion of radiation effects in MOS devices which builds on the previous discussion of the interaction of radiation with materials (Section 3.0). If an electric field exists across the oxide of an MOS transistor, once generated, electrons in the conduction band and holes in the valence band will immediately begin to transport in opposite directions.
II-26
I
I
I
I
1.0
0.0
0.6
0.4
700-keV
PROTONS
0.2
0 o
1
2
3
4
5
ELECTRIC FIELD (MV/cm) Figure 19: Charge yield for x rays, protons, gamma rays, and alpha particles. (After Refs. 17 and 48) Electrons are extremely mobile in silicon dioxide and are normally swept out of silicon dioxide in picosecond [45,46], However, even before the electrons can leave the oxide, some fraction of the electrons will recombine with holes in the oxide valence band. This is referred to as initial recombination. The amount of initial recombination is highly dependent on the electric field in the oxide and the energy and type of incident particle [47]. In general, strongly ionizing particles form dense columns of charge where the recombination rate is relatively high. On the other hand, weakly ionizing particles generate relatively isolated charge pairs, and the recombination rate is lower [47]. The dependence of initial recombination on the electric field strength in the oxide for protons, alpha particles, gamma rays (CO-60), and x rays is illustrated in Fig. 19 [17,48]. Plotted in Fig. 19 is the fraction of unrecombined holes (hole yield) versus electric field in the oxide, The data for the CO-60 and 10-keV x-ray curves were taken from Ref. 48. The remainder of the curves were taken from Ref. 17. For all particles, the fraction of unrecombined holes increases as the electric field strength increases. Taking into account the effects of hole yield and electron-hole pair generation, the total number of holes generated in the oxide (not including dose enhancement effects) that escape initial recombination, Nh, is given by [17] Nh =
f(%x )go~fo.
(7)
,
where f(EOX)is the hole yield as a function of oxide electric field, D is the dose, and ~X is the oxide thickness (in units of cm). Values of go for Ga.As, silicon, and silicon dioxide are given in Table I. Specifying the dose in rad(Si02), Eq. (7) becomes,
II-27
.
(8)
N~ = 8.1x1012~(Efl=)Dt,)= .
If metal or silicide gate materials with a high atomic mass are used, Nh must be multiplied by a dose-enhancement factor. Assuming all holes are created uniformly throughout the oxide, the maximum threshold-voltage shift prior to hole transport is given by [17] A~,-
(9)
= - 1.9xlo”8f(Eo= )Df,,=2 .
Eq. (9) is determined by integrating over the charge distribution Eq. (20)]. 4.3
in the oxide [See Section 4.7,
Hole Transport
Holes generated in the oxide transport much more slowly through the lattice than electrons. In the presence of an electric field, holes can transport to either the gate/Si02 or Si/Si02 interface. Due to its charge, as a hole moves through the Si02 it causes a distortion of the local potential field of the Si02 lattice. This local distortion increases the trap depth at the localized site, which tends to confine the hole to its immediate vicinity. Thus, in effect, the hole tends to trap itself at the localized site. The combination of the charged carrier (hole) and its strain field is known as a polaron [49]. As a hole transports through the lattice, the distortion follows the hole. Hence, holes transport through Si02 by “polaron hopping” [17,50,51], Polarons increase the effective mass of the holes and decrease their mobility. Polaron hopping makes hole transport dispersive (causing hole transport to occur over many decades in time after a radiation pulse) and highly temperature and oxide thickness dependent [17,50,5 1]. The dispersive nature of hole transport and its temperature dependence is illustrated in Fig. 20 [52]. In this figure the flatband-voltage shift (AVfi), normalized to its value immediately after a pulse of ionizing irradiation, measured on a MOS capacitor is shown as a function of temperature. The thickness of the oxide was 96.5 nm, the silicon substrate was ntype, and the oxide electric field was 1 MV/cm. For these measurements, the flatband-voltage shift is an indication of the number of holes in the oxide. As holes transport out of the gate oxide, the flatband voltage will tend to recover to its initial value preirradiation. Note in Fig. 20 that the recovery of the flatband voltage (and hence hole transport) occurs over many decades and is a strongly thermally activated process. At T = 293 K, the time for 50!Z0 recove~ is less than 1 ms; whereas, for T = 181 K, the time for 50% recovery is approximately 500s. For temperatures of 124 and 141 K, very little recovery (-20%) occurs for times as long as 1000s. The dependence of hole-transport time on electric field strength is illustrated in Fig. 21 [53]. In this figure, the flatband-voltage shift is shown measured on 96.3 nm oxide capacitors normalized to its value immediately after a pulse of ionizing irradiation. The capacitors were irradiated and annealed at 79 K in order to minimize hole transport at low electric fields. The As noted in the figure, the flatband voltage electric field was varied from 3 to 6 MV/cm. recovery time, and hence, the hole transport time, is strongly dependent on the electric field strength. For an electric field of 3 MV/cm very little recovery occurs at the longest measurement II-28
0.0
I
I
I
000
I
00
(’T=293K) O
0.25
o 0
o
❑
(247K) ❑
0
❑u
•1
A
AA
AA
❑
A
❑
0.75-cl AA #
n
A
@
(194K)
n
n
n
C 00 oO-
~
(181K)0
00
+c
(160KJn
0000
*Q
@
b
~
(141 K)
$8 000 *00 E+%~ij000 ‘$%(124K; vi hJN14 Vv nQ
I ()-3
n-
on
0
no n
n
A
A
❑
AA
A
(217K) A
❑ ❑
A
•1
n
0.50
1.0 10+
o*d 00
10-2 10-1 100
101
I 02
(
I (’)3
TIME AFTER PULSE (S) Figure 20: Temperature dependence of the flatband-voltage shift after a single radiation pulse. For this curve the flatband-voltage shift is a measure of the number of holes in the oxide. (After Ref. 52) time (1000 s). Thus, without a large electric field across the oxide, at low temperatures holes are relatively immobile in the oxide. At higher electric field strengths, the hole transport time is greatly reduced. For an eleetric field of 6 MV/cm the time for 50% reeovery of the flatband voltage is approximately 0.02s. The temperature and eleetric field dependence of the reeovery time, ~, follow the relationship [53], ‘T-
T(0)e[-cE’kr’
(lo)
,
where E is the electric field strength, T is the temperature, behavior is characteristic of polaron hopping.
and c and z(O) are constants.
This
The dependence of flatband voltage reeovery time on oxide thickness is illustrated in Fig. 22 [53]. This figure is a plot of the recovery time at a temperature of 220 K and an eleetric field of 1 MV/cm. Plotted is the flatband voltage normalized to its value immediately after a pulse of ionizing irradiation versus the logarithm of time as a function of oxide thickness. The capacitors
II-29
0.0
n ‘=
0.25 (EOX 6MWCM) A A
>=
.
A
~
0
o
o
(5Mv/cM)o o
A 0
❑
•1
(4Mv/cM) ❑ ❑
~=
0.75
1.0
TIME AFTER PULSE
(S)
Figure 21: Electric field dependence of the flatband-voltage shift after a single radiation pulse. For this curve the flatband-vohage shift is a measure of the number of holes in the oxide. (After Ref. 53) were fabricated with the oxides grown at different times. approximately a&4 thickness dependence [53]. 4.4
The time for 5090 recovery follows
Oxide Traps
With the application of a positive gate bias, holes transport to the Si/Si02 interface. Close to the interface there are a large number of oxide vacancies due to the out-diffusion of oxygen in the oxide [54] and lattice mismatch at the surface. These oxide vacancies can act as trapping centers. As holes approach the interface, some fraction of the holes will become trapped. The number of holes that are trapped is given by the capture cross-section near the interface which is highly device fabrication dependent, with only a few percent of the holes being trapped in hardened oxides to as much as 50 to 100% for soft oxides. The positive charge associated with trapped holes causes a negative threshold-voltage shift for both n- and p-channel transistors.
11-30
b
-n
218A
0/
❑ 376A
o
() 566A O 963A
0
10-4
1()-3
10-2
1 ()-1
100
TIME AFTER PULSE
101
102
103
(S)
Figure 22: Oxide thickness dependence of the flatband-voltage shift after a single radiation pulse. For this curve the flatband-voltage shift is a measure of the number of holes in the oxide. (After Ref. 53) The effect of the capture cross-section on trapped-hole buildup can be observed in the electric field dependence of the buildup of oxide traps shortly after irradiation. Figure 23 [55] is a plot of the threshold-voltage shift due to oxide-trap charge, AVO[,versus oxide electric field. The solid circles are the measured data, the open circles are the measured data adjusted for hole yield, and the dashed line is a plot of E-l’*. For electric fields greater than 0.5 V/cm, AVOI adjusted for hole yield decreases with approximately an E-l’* electric field dependence. This is the same electric field dependence for the hole capture cross-section near the Si/Si02 interface [47,56-60]. This indicates that the field dependence of oxide-trap charge buildup is determined primarily by the hole capture cross-section. 4.4.1
Time, Temperature,
and Electric Field Dependence of Oxide-Trap Charge Neutralization
Immediately after oxide-trap charge is created it begins to be neutralized. Insight into the mechanisms for oxide-trap charge neutralization can be obtained from the time dependence of neutralization, its temperature, and its electric field dependence. The time dependence for trapped-hole neutralization at room temperature is illustrated in Fig. 24 [61] where the voltage shift due to oxide-trap charge, AVOt, is plotted versus time for hardened n-channel polysilicon gate transistors irradiated to 100 krad(Si02) at dose rates from 6X109 to 0.05 rad(Si02)/s and then annealed at room temperature. The bias during irradiation and anneal was 6 V and the gate oxide
II-3 1
10
1
I
1
1
1
1
1
1
I
\
\ \ \
;T$
\ 3’”<
2
/’-”2 \\ *
●
MEASURED
1
1
1
POLY GATE: 45 nm 500 krad(SiOz) X-RAY, 4170 krad/s
ADJUSTED 5
1
●
\ -’
°
2 ●
●
●
●
0.5
0.5
0.2
0.1
ELECTRIC
1
2
5
FIELD (MV/cm)
Figure 23: Electric field dependence of AVO,versus electric field. Shown is the measured data (solid circles) and the measured data adjusted for charge yield (open circles). (After Ref. 55) thickness of the transistors was 60 nm. During anneal, the decrease in AVOIfollows a logarithmic time dependence. At each dose rate, AVO~falls on the same straight line. Thus, the rate at which AVO[is neutralized is dose-rate independent. The qualitative nature of the time dependence for neutralization of AVOt given in Fig. 24 is typical of that for devices fabricated using other hardened and most commercial technologies, However, the rate at which AVO~is neutralized can depend on the details of the device fabrication process [62]. The logarithmic decrease in AVMcan be described by linear system response analysis [6365]. Several investigators have found that the long-term annealing response can be empirically characterized using the equation [63,64]
–Aln -A~, (t) =
[1
~ +C o
70
(11) ‘
where AVO(t) is the transient annealing curve per unit dose, yOis the total dose used to obtain the transient annealing curve, A is the magnitude of the slope of the transient annealing curve, and C is the intercept at t = h. Assuming device response is linear with dose, Eq. (11) can be used to
II-32
o~
I
I
I
I
I
I
I
I
Cs-137 (0.05 radls) -0.4 0 -0.8
CS-137 (0.165 radk)
X-RAY, 52 rsd
-1.2 -
(~02)/s
X-RAY, 5550 rad (SiOJh -1.6
LINAC, 2 PULSES, 6 xl@
-2.0 0.1
I
I
1.0
10
rad (SiOJs
I
I
1
ltP
lW
I@
TIME
1 lCF
I 106
107
(S)
Figure 24: The change in AVd during anneal at room temperature for transistors irradiated at dose rates from 6 x 109to 0.05 rad(Si)/s. (After Ref. 61) determine AVOtby convolving the dose rate, ~(t), with the transient annealing curve, AVO, i. e., [63,64]
W,=
(12)
jW)AW-.)d.. o
Using Eq. (12), one can determine AVO~at any dose or dose rate from a single set of irradiation and anneal measurements. This is especially important for space systems, where it is not practical to test devices at space-like dose rates. Thus, using linear systems theory, AVo~can be predicted using standard laboratory measurements [63-65]. The logarithmic decrease in AVO~in time is characteristic of most hardened and Some commercial technologies exhibit much less oxide-trap charge commercial technologies. neutralization [66]. For these technologies, nearly the same value of AVOt may be measured whether one irradiates at moderate dose rates or at very low dose rates due to the low chargeneutralization rate. We will next discuss the temperature and bias dependence for the neutralization of oxidetrap charge. The neutralization of oxide-trap charge has been found to be a function of temperature for some technologies [67,68] and nearly independent of temperature for other technologies [69-7 1]. An example of a technology with a temperature dependence is illustrated in Fig. 25 [67]. This figure is a plot of the threshold voltage versus time for hardened n-channel transistors irradiated at room temperature to 1 Mrad(Si) and then annealed under bias at varying temperatures. The bias during irradiation and anneal was 10 V and the oxide thickness was
II-33
4
1 1 1 111f
1
1
1 I
Fs’’’’””
~
A=125°C O=loo”c ● =75°c lJ=50°c 0=25°C 1 1 1 11111 1 1 1 11111
F PRE
ANNEAL -
0.1
1.0
10
100
1 I 1 1111~
1000
(106 rad)
TIME (h) Figure 25: Temperature dependence of trapped-positive charge neutralization. For this data the change in threshold voltage is dominated by a decrease in oxide-trap charge. (After Ref. 67) 45 nm. For these transistors the increase in threshold voltage is due almost entirely to a decrease in oxide-trap charge. Very little change in interface-trap charge (discussed below) occurs during anneal for these transistor. It is clear in Fig. 25 that the increase in the threshold voltage, and thus, the decrease in oxide-trap charge, is a strongly thermally activated process. The time for 50% neutralization of the threshold voltage varies from approximately 4.3x 106s at 125°C to 1.lx 104s at 25”C. This gives an activation energy of -0.41 eV [67]. These data suggest that for this technology it should be possible to simulate the neutralization of oxide-trap charge that occurs for a low-dose-rate space irradiation by irradiating the transistors using a laboratory radiation source and then annealing the transistors at elevated temperatures, Whether or not a technology exhibits a temperature dependence will depend on the energy distribution of the oxide traps as discussed below in Section 4.4.2. Neutralization of oxide-trap charge for hardened transistors is also bias dependent as is illustrated in Fig. 26 [67] for transistors from a hardened technology. This figure is a plot of AVO~ versus time for n-channel transistors irradiated at room temperature to 1 Mrad(Si) and annealed at 100°C under bias. The irradiation bias was 10 V and the anneal bias was varied from O to 10 V. Transistors were annealed at 100”C to accelerate the neutralization of oxide-trap charge. Qualitatively similar results are obtained for room temperature anneals. For these transistors,
II-34
1
1
1
-1
-2
~
IRRADIATION
-3
s“’’’’” PRE
0.1
1
1
1
1 1 1
I
1
1
1 1 11 11
1.0 (lOG rad)
10
1
1
1
1 1 111
100
1
1
1
1 1
u
1000
TIME (h) Figure 26: Bias dependence for the neutralization of oxide-trap charge. (After Ref. 67) increasing the anneal bias greatly accelerates the neutralization of oxide-trap charge and increases the amount of neutralized charge [67,72]. For an anneal bias of O V, only 5090 of the oxide-trap charge is neutralized, as compared to virtually 10090 of the oxide-trap charge for an anneal bias of 10 v. The neutralization of oxide-trap charge is often reversible [67,69,73]. Figure 27 [67] is a plot of AVO~for n-channel transistors irradiated to 1 Mrad(Si) at room temperature, annealed with a 10 V bias for 200 h at 100”C, and then annealed with a -10 V bias for an additional 30 h at 100°C. During the anneal with positive bias (+10 V), AVOIis completely neutralized (within experimental uncertainty). After the bias is switched from positive to negative, some oxide-trap charge reappears. This indicates that for these devices a large fraction of the oxide-trap charge is not permanently annealed under these anneal, bias, and temperature conditions. Instead, the defect centers associated with the oxide-trap charge are still present and the charge is merely compensated. The decrease and increase in oxide-trap charge by switching bias can continue for many cycles [69,73]. The energy distribution of oxide traps has been inferred from combined thermallystimulated-current (TSC) and capacitance-voltage measurements [74]. In a TSC measurement, a MOS capacitor is slowly heated under bias. This causes a gate-to-substrate current (TSC current)
rI-35
I
‘F)
1 1 1 11111
I
1
1 1 1111
1
1
1 1 1111
n
1
1
1 1 1111
1
1
1 11111 I
\ -\ \ \
-1 :& ~~~
-2 t
\ (B)
ANNEAL 1Oo”c
k2!(11111 -~111 IRRADIATION
-3
(A)
ANNEAL 1Oo”c
PRE
vG~=+lo ovG~=o
vG~=-lo o vG~=+lo
❑
“
0.1
10.0
❑
100.0
1
10
100
(ltKad)
TIME (h) Figure 27: The change in oxide-trap charge for transistors irradiated with a +10 V bias, annealed with a +10 V for 200 h, and annealed with a -10 V bias for 30 h (squares), and for transistors irradiated with a +10 V bias, annealed with a -10 V for 200 h, and annealed with a +10 V bias for 30 h (circles). (After Ref. 67) as holes are de-trapped [75], The TSC current is recorded as a function of temperature. From these measurements the concentration of oxide-trap charge can be determined as a function of energy in the band gap. Figure 28 is a plot of the energy distribution of oxide traps measured on capacitors fabricated in five different technologies [74]. All of the devices show an energy distribution of the same basic form. Except for possibly the AT&T 18-rim technology, each technology shows a minor peak at around 1.2 eV and they all show a larger broad peak at around 1.7 to 2.0 eV. 4.4.2
Mechanisms for Neutralization
The bias, temperature and logarithmic time dependence of the neutralization of oxide-trap charge can be accounted for by invoking two mechanisms: 1) the tunneling of electrons from the silicon into oxide traps, and 2) the thermal emission of electrons from the oxide valence band into oxide traps. These two mechanisms are depicted in Fig. 29 [76]. The tunneling of electrons has been examined by several workers [62,76-79]. The probability of an electron tunneling from the silicon to an oxide trap is given by [62,76,77],
Pt.. =
W-M ,
(13)
n-36
.—
Energy (eV) ~-
1.2
1.4
1.6
1.8
2.0
2.2
@●“’ qj”%, .* ‘\* ●
. Soft 45-rim, 20k,@-~..Z..~””z
# ~ -(IV)/
. Hard
45-rim, 2M 0 z ---
0
--
~
@
,+~”(iij-’-.
z
i -:
\
4
\
0’ 0“ - Wet 23 nm, 2M ,.’-%.%. \* ‘Dry25nm,
lM
AT&T 18 nnp 5M
0
I 50
●“1. ..** 100
,,, m,s I
I
I
I
150
200
250
300
.. . 350
Temperature (“C) Figure 28: Energy distribution of hole traps determined from combined TSC and C-V measurements for f;ve technologies. (After Ref._74) where a is the attempt to escape frequency, x is the distance of the trap from the Si/SiOz interface, and ~ is a tunneling parameter related to the electron barrier height. Note that ptu” is independent of temperature, but varies exponentially with the distance of the trap from the Si./Si02 interface. The tunneling process can be depicted as a tunneling front moving into the oxide. If the tunneling front is defined as the position corresponding to the maximum rate of tunneling, x~(t), then the distance of the front into the oxide at a given time t is given by [62,76,77],
Xm = ‘ln(cxt) 2p
(14)
.
Note that the distance that the front moves into the oxide varies logarithmically with time. Therefore, for an electron to tunnel into a trap on a reasonably short time scale, the trap must be very close to the Si/Si02 interface. For Si02, the tunneling front moves into the oxide at a rate of 0.2 to 0.4 nrd(decade in time) [62]. If the trap is more than -4 nm from the interface, it will be essentially inaccessible to an electron tunneling from the silicon into the trap. Thus, the rate and number of oxide traps neutralized by electron tunneling is highly dependent on the spatial distribution of traps in the oxide. The spatial distribution of traps in the oxide is in turn highly dependent on the device fabrication process. Thus, the rate and number of traps neutralized by electron tunneling will also depend on device fabrication techniques [62].
II-37
OXIDE
SILICON
E= Ev
be-
ELECTRON TUNNELING
GATE @
Figure 29: Schematic diagram illustrating the neutralization of oxide-trap charge by electron tunneling from the silicon and by thermal emission of electrons from the oxide valence band. (After Ref. 76) Trap neutralization by thermal emission of electrons from the oxide valence band has also been examined by several workers [68,76,80,81]. For a thermal emission process, the probability, p.~, of an electron being emitted from the oxide valence band into a trap is given by [76,80,81]
P em
= A~ze-hd@~J
(15)
9
where @ is the difference in energy between the trap and the oxide valence band and A is a constant which depends on the capture cross-section of the trap and other parameters. For the thermal emission process, p.~ varies exponentially with temperature, but is independent of the spatial position of the trap. This mechanism accounts for the strongly thermally activated neutralization of holes noted in Fig. 25. Similar to a tunneling front, a thermal emission front as a function of time can also be defined. Defining the thermal emission front as the time corresponding to the point of maximum emission, $~(t), it can be written as [76,80,81]
$.(t)
= ~ln(AT2t)
.
(16)
II-38
McWhorter, et al. [76], combined tunneling and thermal emission into a single model of trapped-hole annealing. Combining tunneling and thermal emission, the distribution of trapped holes p,(x,~, t) as a function of position, energy, and time can be written as [76]
P,(Ao,, ~) = PO(X30, )e-(pf-+p-)’ s
(17)
where po(x,@) is the initial density of trapped holes in energy and position immediately following irradiation. Using Eq. (17) the temperature and electric field dependence of oxide-trap charge neutralization can be determined. Clearly, the spatial and energy distributions of the oxide traps will strongly affect the rate at which charge neutralization occurs. For tunneling, the spatial distribution of the oxide traps must be close enough to the Si/Si02 interface. For thermal emission, the energy distribution of the oxide traps must be close enough to the oxide valence band. Not only will the spatial and energy distributions of the oxide traps affect the rate of neutralization at room temperature and constant bias, but they will also affect its temperature and bias dependence. The spatial and energy distributions are affected by device fabrication conditions [62]. For the hardened device data of Figs. 25-27 which show a temperature and bias dependence, the oxide traps are apparently accessible to neutralization by both thermal emission and tunneling. For commercial transistors which show less neutralization [66], the oxide traps are apparently less accessible by thermal emission or tunneling for the bias and temperature conditions examined. By reversing the bias, the oxide charge can be recovered [67,68,73]. Similar requirements apply for an electron to leave a hole trap as for an electron to neutralize a trap. For an electron to be emitted from a neutralized hole trap, thermal emission requires an empty hole in the oxide valence band and tunneling requires an empty hole in the silicon valence band. In addition to the neutralization of oxide-traps by electron tunneling or thermal emission, oxide-trap charge also can be compensated as electrons are trapped at electron trap sites associated with the trapped holes. Combined TSC and C-V measurements have shown that there can be large concentrations of electron traps in a thermal oxide [74]. Figure 30 is a plot of the number of electron traps relative to the number of hole traps for two different technologies [74]. Note that for the dry-gate oxide technology, the number of electron traps is approximately 1/2 (0.48H.09) that of the number of hole traps. For these devices with a positive gate bias, a large fraction of the total number of trapped holes can be compensated by trapped electrons quickly after irradiation (or even during irradiation), For the wet-gate oxide technology, where the fraction of electron traps (O.16MI.06) is considerably less, the oxide traps will be compensated at a much slower rate. 4.4.3
Microscopic Defect Centers
Several microscopic point defects have been identified in irradiated thermally grown oxides [44,82-90]. The most important of these is the E center [44,82-85]. At least nine variations of the E center have been identified in either thermally grown oxides or in bulk
H-39
0.75
f/1 1/ J
0.60 i’
/l
0.45 0.30
/-41
m
0.15 0.00
I
348
I
I
I
100
47
23
104
36
I
I
28
98
OXIDE THICKNESS
98
45
18
(rim)
o
WET GATE DRY GATE Figure 30: Ratio of trapped electrons to trapped holes for wet- and dry-gate oxide transistors with varying oxide thicknesses. (After Ref. 74) crystalline or fused oxides. These variations are summarized in Table II [44]. Listed in Table II are the name of the defect (type), precursor state, EPR active state, charge state, g-tensor elements, and the reliability of the assessment of its properties (how sure workers are of the identification with four stars being the most reliable). As a guide for deciphering the notation, the combination Si=03 indicates a silicon atom bonded to three oxygen atoms and an arrow, 1’or., indicates a net magnetic moment (EPR center). Most E centers are characterized by an unpaired electron highly localized on a silicon atom bonded to three oxygen atoms. The chemical notation for the generic E center is given by ~Si=03 or d3i=03. An EPR trace illustrating an E’ signal was given in Fig. 18. The double-humped structure of the E’ EPR signal in Fig. 18 is characteristic of an axially symmetric point defect in an amorphous material [44]. One of the more common types of E centers identified in thermally grown oxides is the E’Y center. The chemical notation for the EY center is given by 03=Sio ‘Si=03. This notation indicates that an E’Ycenter is a trivalent silicon atom bonded to three oxygen atoms. It becomes pararnagnetic and positively charged when a radiation-induced hole becomes trapped at the vacancy site of one of the silicon atoms. It is identified by an EPR signal with a zero crossing at g = 2.0005. A schematic illustration of the precursor and the EPR active state of the EY center is given in Fig. 31 [44]. For thermal oxides, the precursor state exists prior to irradiation. (This is not necessarily true for bulk crystalline oxides [44].) It occurs naturally, usually in greatest densityclose to the Si/Si02 interfacedue to the lattice mismatchbetween the silicon substrate and the oxide (which may be an indication of an incomplete oxidation process) or due to outdiffusion of oxygen in the oxide [54]. Three other types of E’ centers identified in irradiated thermal oxides are the E’~ [87] and the 74-G [88-90] and 1O.4-G doublets [90]. The E’a center likely results from capturing a hole at a silicon interstitial/oxygen vacancy complex. It is identified spectroscopically by differing gtensors than the E’r The E’b center also anneals at lower temperatures than the E’Ycenter [91],
11-40
TABLE II: List and chemical structure of E’ centers that have been identified in thermal gate oxides. Type
Precursor
E’l
O@i-O-Si=Oa
E’y
o~=sl-sl=cl~
E’,
l’Si=03
E’d
03=s1-0-s1=03
E’a
03=Si-O-Si=03
E’b
0@31-Si=03 + Ho
ESR Active State
o#l-ql-sl=03
E’la~
0#i-~i=02 H ?
g,= 2.00176 g2= 2.00049 g~= 2.00029
‘Sl+
Positive ?
03=SIT
‘sq
Positive
-kl=03
03=SIT
-kl=03
Neutral
g,= 2.0018 g2= 2.0006 ga= 2.0003 g,= 2.0018 gz= 2.0003 g~= 2.0003
Reliability
**
****
***
Neutral ?
gl= 2.00153 g2= 2.00012 g3= 2.00000
**
‘sl=o~
Positive ?
g,= 2.0018 g2= 2.0013 g3= 1.9998
*
H-Sl=03
Neutral ?
g,= 2.0018 g~= 2.0004 ga= 2.0004
*
Positive
g,= 2.0018 g2= 2.0021 g3= 2.0021
● **
Posltlve
g = 2.0016 Zem-mcdng
***
?
g,= 2.0018 g2= 2.0006 ga= 2.0004
*
bSi=03
o-o-&02
11! ~:?!..,
03*1
:,
s;
E’Tu
g-tensor Elements
O.#it
Ill SI
E’b
Charge State
H-;=02
S1 ; Si=03
----s:
‘sl+
H-O-~=02
Like the E’Ycenter, the E’6 center has a positive paramagnetic charge state, The 74-G and 1O.4-G doublets are hydrogen-associated E’ centers [88-90]. The structure of the 74-G doublet has been determined to be an unpaired spin on a silicon atom bonded to two oxygen atoms and one hydrogen atom. Its chemical notation is given by H–Si=020 ‘Si=O~. It has a positive paramagnetic charge state. In order to observe the 74-G doublet, thermal oxides must be irradiated to very high radiation levels (-10a rad) [89], or subjected to hydrogen following irradiation [90]. Lenahan and Dressendorfer [82] were the first to show a strong correlation between the E’ center and radiation-induced positive charge (oxide-trap charge) for some thermal oxides, Using they observed an electron spin resonance, C-V, annealing, and etchback measurements, approximate one-to-one correlation between positive charge and the number of E’ centers. Similar increases were observed during irradiation and similar decreases were observed during anneal. This correlation is illustrated as a function of dose in Fig. 32 [82], Plotted in Fig. 32 are the number of E’ centers measured using EPR and AV~~COX/qmeasured on capacitors versus dose. AVmEis the voltage shift at midgap in units of 1012/cm2 and COXis the oxide capacitance. Assuming that interface-trap charge is neutral at rnidgap and that oxide-trap charge is located
II-4 1
.—..
very close to the Si/Si02 interface, AV~gCOX/qis approximately equal to the concentration of oxide-trap charge. Thus, as noted in Fig. 32, (a) there is approximately a one-to-one correlation between the increase in the number of E’ centers and concentration of trapped charge in the oxide with dose. Using etch-back measurements, they also found the same spatial distribution in the oxide for the number of E’ centers as for the number of oxide-trap charge. Most of the E’ centers and oxide-trap charge were determined to be located close to the Si/Si02 interface (within 10 nm for a 1100 nm thick oxide). Additional work has shown that, by selectively injecting electrons and holes into the oxide using ultraviolet illumination, the charge of the E Figure 31: Schematic illustration of the center (and the trapped positive charge in the precursor a) and EPR active state b) of the E’Y oxide) could be reversed [82,92]. These results center. (After Ref. 44) are consistent with the data of Fig. 27. Even though the work of Lenahan and Dressendorfer showed a good correlation between the number of E’ centers and oxide-trap charge for some oxides, recent works on thick buried oxides for silicon-on-insulator technology (see Section 5.1 ) and on thermally grown gate oxides [91] have raised several questions about the general correlation between the number of E’ centers and oxide-trap charge. Work performed on SIMOX [93,94], BESOI [91], and thermal oxide [91] material has shown the absence of a correlation between the number of E’ centers and oxide-trap charge (See Section 5.1). For the buried oxide materials, this is especially puzzling for BESOI materials which are two thermally grown oxides bonded together. One would expect that for BESOI materials they should have the same spectroscopic properties as for standard thermally grown gate oxides except near the bond region. Thus, in general there may or may not be a correlation between the number of E’ centers and oxide-trap charge. 4.5
Interface Traps
In addition to oxide traps, radiation also induces interface traps at the Si/SiOz intefiace [95]. Interface traps exist within the silicon band gap at the interface. Because of their location at the interface, the charge of an interface trap can be changed easily by applying an external bias. Interface traps can be positive, neutral, or negative. Traps in the lower portion of the band gap are predominantly donors, i.e., if the Fermi level at the interface is below the trap energy level, the trap “donates” an electron to the silicon. In this case, the trap is positively charged. A p-channel transistor at threshold samples primarily interface traps in the lower region of the band gap. Therefore, for a p-channel transistor, interface traps are predominantly positive, causing negative threshold-voltage shifts. Conversely, traps in the upper portion of the band gap
II-42
3
●
A
2
A ● E’ , 1
A
AVmgCOX/q
●
b o
5
A
10
DOSE (Mrad) Figure 32: The increase in the number of E’ centers and oxide-trap charge (approximated by AVwCo,/q) with dose. (After Ref. 82) are predominantly acceptors, i.e., if the Fermi level is above the trap energy level, the trap “accepts” an electron from the silicon. In this case, the trap is negatively charged. Art n-channel transistor at threshold samples interface traps predominantly in the upper region of the band gap. Therefore, for an n-channel transistor, interface traps are predominantly negative, causing positive threshold-voltage shifts. At midgap, interface-trap charge is approximately neutral [2932]. Because oxide-trap charge is positive for both p- and n-channel transistors, oxide-trap charge and interface-trap charge compensate each other for n-channel transistors and add together for p-channel transistors. Interface-trap buildup occurs on time frames much slower than oxide-trap charge buildup. Interface-trap buildup can take thousands of seconds to saturate after a pulse of ionizing irradiation. Unlike oxide-trap charge, interface-trap charge does not anneal at room temperature. These properties make interface-trap charge effects very important for low dose-rate applications, e.g., space. For an n-channel transistor, interface-traps affect device performance primarily through an increase in threshold voltage and a decrease in channel mobility. Both of these degradation mechanisms tend to reduce the drive current of “ON” transistors, leading to increases in timing parameters of an IC.
II-43
I 1 , 11111 1 , 1, 1111 , r , 11111 r , 1, 1111 1 1 111111 1 1 I 11111 , 1 1, 1111
25 J-
10-MeV
LINAC
-.
1
4 PULSES/s -75 krad CONSTANT BIAS +1 MV/cm
ADMm) ~
:U
20
15
%IR
10
‘--
DOSE RATE
PULSES,
o ●
5
5, 1.4x1Ograd/s 70, 1.lxl O%ad/s
V 572, 1.3x107rad/s 1
01 10-1
1
1
1 1 1111
1
lCF
,
1 1 ,,,
,
101
1
1
1 1
11, ,
,
,
1 I ,111
I 02
,
,
1 1 111,
1
104
1
1 1 1111
lCF
1
1 1 1 ,,,1
106
TIME (:; Figure 33: Interface-trap buildup as a function of time after irradiation.
4.5.1
(After Ref. 100)
Properties of Buildup
With a positive bias applied to a gate oxide, immediately after a radiation pulse, some “early” interface-trap buildup can occur [96-98]. This early buildup of interface traps is present by the time of the first measurement (a few milliseconds) after a pulse of radiation. Early buildup of interface traps does not occur with a negative gate bias. This is an indication that the early buildup is not created directly by irradiation, but rather is induced by secondary processes. The early buildup is normally a small fraction of the total buildup. It has been shown to account for approximately O to 25% of the total buildup [97]. The amount of early buildup depends on the device fabrication process [97]. Most of the buildup of interface traps occurs seconds to thousands of seconds after a pulse of ionizing radiation [99,100]. Fig. 33 [100] is a plot of the density of interface-traps, Dit, The density of interface traps is the average versus time after a high-dose-rate irradiation. number of traps in a given interval of the band gap, and has the units of traps/cmz-eV. The data for this plot were taken on polysilicon gate transistors irradiated to 75 krad(Si) in 5,70, and 572 pulses at a 4-Hz repetition rate. The gate oxide thickness was 47 nm and the electric field across the oxide during irradiation and anneal was 1 MV/cm. For these measurements, interface-trap buildup had begun by the time of the first measurement (1 s for the data taken with 5 pulses). However, interface-trap buildup does not begin to saturate until - 10f s. This curve is typical of that for interface-trap buildup. For the curve taken with 5 pulses, the time for 5090 buildup is approximately 35 s. II-44
14 1 1 111111! 1 t 1[1111 1 1111111 [ [ 111111 1 111
111!
+2
12
1
1
1
1 111,
1
1
1
11
I
10 Y
.*
0.01s I
8
‘o
6
w
n=
4
a
2 0 10-1
100
101
TIME AFTER
102
103
RADIATION
104
105
106
PULSE (S)
Interface buildup as a function of time after irradiation for transistors irradiated and annealed with a +2 V bias (control) and for transistors irradiated and annealed during the initial stages with a -2 V bias and annealed with a +2 V bias after switching at the time indicated. (After Ref. 101 )
Figure 34:
Little or insignificant buildup of interface traps occurs if a negative bias is maintained during irradiation and anneal. However, interface-trap buildup can occur for a negative bias during irradiation if the bias is switched positive shortly after irradiation. Figure 34 [101] is a plot of interface trap buildup measured on polysilicon gate transistors irradiated to between 25 and 40 krad(Si) in a single 1.5-ps radiation pulse. The gate oxide thickness was 35 nm. For the data marked “control,” the bias during irradiation and anneal was 2 V. The rate of interface-trap buildup depicted in this curve is very similar to the data of Fig. 33. For the data marked 0.001 s, 0.01 s, 300 s, or 1000 s, the bias during irradiation and during the initial stages of annealing was -2 V, and then switched to +2 V at the time indicated. For the case where the bias was switched 0.001 s after irradiation, about 85% of the buildup is obtained as compared to the control (continuous+2 V bias). Note that the initial buildup of interfacetraps occurs at approximately 10s for the 0.001 s switched bias irradiations; whereas, for the control data, interface-trap buildup occurs by the time of the first measurement -0.3 s. The longer time for initial buildup for the switched bias irradiations is likely due to that fact that for the negative bias irradiations holes transport toward the gate-Si02 interface releasing hydrogen ions near the gate-Si02 interface and/or in the bulk of the oxide. The longer time for buildup is caused by the time it takes for hydrogen ions to drift to the Si/Si02 interface after the bias is switched positive. At the interface the hydrogen ions can react to form interface traps (see Section 4.5.5). For the positive bias irradiations, holes transport toward the Si/Si02 interface and hydrogen ions are released rI-45
I t ox=
I
I
I
I
I
I 03
104
26 nm 355
VG~= +5.2 V
375
j (-J-2
10-1
100
1@
102
105
TIME (S) Figure 35: Interface-trap buildup after a radiation pulse for temperatures from 278 to 375 K. (After Ref. 97) much closer to the Si/Si02 interface and the time it takes for hydrogen ions to drift to the Si/SiOz interface is significantly less. The longer the negative bias is left on, the lower is the eventual buildup. Very little interface-trap buildup occurs for either the 300s or 1000 s switched biased irradiations. The rate at which interface traps build up depends on the temperature of the anneal following irradiation [97, 102]. Figure 35 [97] is a plot of the density of interface-trap buildup divided by the irradiation dose versus time for polysilicon-gate transistors irradiated to -50 krad(Si) in a single 1.5-w radiation pulse for temperatures from 278 to 375 K. The oxide electric field during irradiation and anneal was 2 MV/cm and the oxide thickness was 26 nm. The rate at which buildup occurs increases as the anneal temperature increases. The activation energy for the buildup of interface traps is -0.71 eV for these devices. Similar activation energies have been measured on 42 nm polysilicon-gate transistors (0.79 eV) [97] and 96.5 nm metal-gate capacitors (0.8 eV) [102]. At low temperatures (<150 K), the buildup of interface traps is significantly retarded [103]. Figure 36 [103] is a plot of the density of interface traps for transistors irradiated in a single pulse at a temperature of 78 K. After irradiation, the temperature was increased, transistors were annealed at the indicated temperature for twenty minutes and then re-cooled to 78 K, and measurements were repeated. The gate bias during irradiation was 5.2 V, and the bias was varied from -5.2 to 10.4 V during anneal. From 78 to 150 K, very little interface trap buildup occurs (1 to 10% of the total). Most of the buildup (>90%) occurs at temperatures from 200 to 300 K.
II-46
10 [
~,= 26 nm 0.74 Mrad VG~(rad) = +5.2V
J??!
1 “0
A
w
w
n=0.1
VGS(finned)
❑ +5.2V
/
4
A -5.2 ~[
0.01 70
/%
; ,
I
100
200
■ ,,‘1
:10.4 295K,60 300
h 400
ANNEAL TEMP (K) Figure 36: Interface-trap buildup after a radiation pulse for transistors annealed at temperatures from 78 to 300 K. (After Ref. 103) For low-dose-rate irradiations, the temperature during irradiation can have a large impact on the number of radiation-induced interface traps. Figure 37 [104] is a plot of AVti, AVil, and AVOtversus temperature for transistors irradiated to 500 krad(Si) at a dose rate of 0.27 rad(Si)/s at temperatures from 25 to 125°C with a bias of 5 V. All measurements were taken at room temperature. As the temperature during irradiation increases, the amount of radiation-induced charge increases. There are approximately twice the number of interface traps for transistors irradiated at a temperature of 125°C than for transistors irradiated at a temperature of 25”C. This large increase in interface-trap charge, coupled with a small decrease in oxide-trap charge, leads to significantly higher threshold voltages for transistors irradiated at 125°C. The large increase in threshold voltage cannot be explain by the combination of room temperature radiation response and the preirradiation dependence of the threshold voltage on anneal temperature. These data indicate that there are significant interactions between radiation and temperature for MOS device response. A large difference in threshold voltage was not observed for transistors irradiated with a gate bias of zero volts. Figure 38 [104] is a plot of the threshold-voltage shift versus temperature during irradiation for transistors irradiated to 500 krad(Si) with a gate bias of O and 5 V. Note that there is relatively little change in threshold voltage with the temperature during irradiation for transistors irradiated with VG,S= O V. The difference in response at O and 5 V can lead to a large “imbalance” (1.6 V at 125°C) in the threshold voltages of “ON’ and “OFF” transistors which can cause unexpected IC failure. This can be of special importance to electronics in a space system operating at elevated temperatures (e.g., space-based nuclear reactor platform [105]).
II-47
2.0 AVlt
1.0
y= 500 krad(Sl)
Measured at 25°C y= 0.27 rad (Si)/s 0
-1.0
20
60
100
TEMPERATURE
140
(“C)
37: Dependence of the change in AVOt,AViL,and AVh with the temperature during irradiation. (After Ref. 104)
Figure
For polysilicon-gate transistors the electric field dependence of interface-trap buildup is very similar to the electric field dependence of oxide-trap charge buildup [55,96]. Figure 39 [55] is a plot of the density of interface traps versus oxide electric field during irradiation for nchannel transistors irradiated to 500 krad(Si02) and annealed under bias. The oxide electric field during irradiation was varied from 0.3 to 5 MV/cm and kept constant at 3 MV/cm during a oneweek anneal. Shown are the measured data (solid circles) and data adjusted for charge yield (open circles) by dividing the measured data by the hole yield (see Section 4.2 above). The adjusted data follow an E“””bfield dependence (dashed line), within experimental uncertainty equal to the electric field dependence of oxide-trap charge trapping and the hole capture crosssection near the interface. This is an indication that both oxide-trap charge and interface-trap charge buildup are linked to hole trapping near the Si/Si02 interface. For metal-gate technologies, interface-trap charge buildup may or may not follow the same electric field dependence as for polysilicon-gate technologies. For metal-gate technologies, interface-trap charge has been found to increase with increasing electric field strength [102,106] and to decrease with increasing electric field strength [55].
n-48
2.0 y= 500 krad(Si) Cs source 1.0
v ~~ = 5.0
Measured at 25°C ~ ❑ 0.27 rad (Si)/s 1.6V IMBALANCE
0
NO IMBALANCE
n
v ~~ = 0.0 v
-1.0
20
60
100
TEMPERATURE
140
‘C
Figure 38: The change in threshold-voltage shift with the temperature during irradiation for tr&istors irradiated w;th a gate-to-source bias of Oand 5 V. (After Ref. 104)
4.5.2
Latent Buildup of Interface Traps
Following the “normal” saturation of interface traps within 102 to 105 s after irradiation, large increases in the number of interface traps can occur [107,108]. This second buildup of interface traps can occur at long times after irradiation (> 10b s), and can be quite significant. Figure 40 [107,108] illustrates the “latent” buildup with a plot of the threshold-voltage shift due to interface traps, AVit, normalized to its maximum value versus time for commercial p-channel transistors irradiated to 75 krad(Si02) and annealed at 25°C. The bias during irradiation and anneal was 6 V. Conventional interface-trap buildup stops at approximate y AVit/AVil~U = 0.3 within 300 s after irradiation. After this, there is a window from -300s to 106 s in which no At approximately 10b s after irradiation, interface-trap buildup occurs (“normal” saturation). there is a sudden increase (on a log scale) in interface-trap charge. This latter increase is the “latent” buildup of interface traps. As illustrated in Fig. 40, this latent buildup of interface traps can increase the interface-trap charge density to levels as much as four times higher than the “normal” saturated interface-trap charge density, measured 300s after irradiation. The data of Fig. 40 were taken from transistors fabricated in a commercial technology. A latent buildup has been observed also for some hardened technologies [108]. However, in some cases, hardened technologies did not exhibit a latent buildup (for the times, biases, and temperatures examined)
II-49
10
POLY GATE: 45 nm 500 krad(Si02) X-RAY, 4170 krad/s
5 ADJUSTED
2 ~ 51
0.5 ●✍
0.2 0.1
0.2
0.5
1
2
5
ELECTRIC FIELD (MV/cm) Figure 39: Electric field dependence for interface-trap buildup for as measured data (solid circles) and data adjusted for charge yield (open circles). During the one-week anneal the oxide electric field was 3 MV/cm. (After Ref. 55) [108]. Coincident with the latent buildup is a rapid decrease in carrier mobility and in the magnitude of oxide-trap charge [107,108]. The latent buildup of intetiace traps is a strongly thermally activated process with an activation energy of 0.47 eV [107,108]. Note that this activation energy is much lower than the activation energy for the “normal” buildup of interface traps (-0.7-0,8 eV [97,102], see Section 4,5. 1). However, the activation energy for the latent buildup is equal within experimental uncertainty to the activation energy for trapped-hole annealing (-0.41 eV [67], see Section 4.4.1) and the activation energy for the diffusion of molecular hydrogen in bulk-fused silica (-0.45 eV) [109], Two possible mechanisms for the latent buildup have been proposed [108]. The first is the direct conversion of oxide traps into interface traps or “border traps.” Border traps are oxide traps that can communicate with the silicon on the time scale of a measurement and can act electrically like interface traps (see Section 4.6) [11O]. The conversion of oxide traps into interface traps may occur as electrons from the silicon tunnel into oxide traps during a biased anneal. As electrons neutralize the oxide traps, there will be a decrease in oxide-trap charge and possibly a corresponding buildup of interface traps from the release of hydrogen ions (discussed
11-50
1.4
+~
NORMAL 1.2
1.0
~
>4 1 >= 4
LATENT b ~
* --
-
m
OKI P-CHANNEL
x ~ 0.8
INTERFACE -TRAP “WINDOW”
.
0.6
.
0.4
.
0.2
. /
0
0
0.0 PRE
I 03
I 04
I 05
TIME
106
107
108
(S)
Figure 40: Latent buildup of interface traps measured on commercial transistors. 107,108)
(After Refs.
below) in the neutralization process. A second possible mechanism for the latent buildup is due to the release of hydrogen atoms during irradiation in an adjacent structure and the diffusion of the hydrogen atoms to the Si/Si02 interface. The activation energy for the latent buildup is equal within experimental uncertainty to the activation energy for diffusion of molecular hydrogen in bulk fused silica (-0.45 eV) [109]. Near the interface the hydrogen atoms can crack at positively charged oxide traps forming hydrogen ions [11 1]. The hydrogen ions are then free to drift to the Si/SiOz interface to form interface traps (see Section 4.5.5). The large buildup of interface traps at late times is clearly a concern for space systems. The latent buildup of interface traps can degrade the performance of ICS in space systems and may cause system failure at long times. The latent buildup of interface traps may not be predictable from laboratory measurements. For technologies in which a latent buildup is known to occur, one may increase the overtest margin or time of post-irradiation anneals used to simulate the space environment [108].
H-5 1
1.2
I
I
I
1.0
I
I
I
I
Cs-137 (0.165 radh)
0.8
o
&
0.6 A
X-ray, 52 rad (S1OJS
A
Cs-137 (0.05 rad/s)
0.4 X-ray, 5550 rad (SIOJ/s 0.2
\
0.1
LINAC, 2 PULSES, 6 X 10grad (SIOJ/s 1.0
10
102
102
104
1 (J5
106
107
TIME (S) Figure 41: Interface-trap buildup for transistors imadiated at dose rates from 6 x 109 to 0.05 rad(Si)/s and annealed under bias at room temperature. (After Ref. 61) 4.5.3
Dose-Rate Dependence
There does not appear to be a “true” dose-rate dependence for the buildup of interface traps [61], Figure 41 [61] is a plot of AVit versus time for transistors irradiated to a total dose of 100 krad(Si02) at dose rates from 6x 109 to 0.05 rad(Si02)/s, After irradiation each transistor was annealed under bias. The bias during irradiation and annerd was 6 V. Note that as long as the total irradiation plus anneal time is the same, the same threshold-voltage shift due to interface traps is measured, regardless of the dose rate of the radiation source. If there were a “true” doserate dependence, the data taken at different dose rates would not fall on the same response curve. However, if transistors are not annealed, irradiating at different dose rates can result in different values of AVit [1 12]. Figure 42 [112] is a plot of AVit and AVO, versus dose for transistors irradiated at dose rates from 0.1 to 200 rad(Si)/s with no post-irradiation anneal. At the lower dose rates, AVit is higher and the magnitudeof AVO,is lower than at the higher dose rates. The lower values for AVil at high dose rates occur because for these transistors, the buildup of interface traps has not saturated for the shorter times associated with the higher dose rates. The lower values for the magnitude of AVOI at low dose rates occur because more neutralization of oxide-trap charge takes place during irradiation for the longer times associated with the low-dose-rate irradiations. Thus, if transistors are not annealed after irradiation, a laboratory irradiation (e.g., 200 rad(Si)/s) will overestimate the amount of oxide-trap charge and underestimate the amount of interface-trap charge in space. Since these two parameters tend to compensate each other for an n-channel transistor, the net effect is a higher threshold-voltage shift for a low-dose-rate irradiation, For the data of Fig. 42, after irradiating to 1 Mrad(Si), there
II-52
5 G0250AIVV21 N-CHANNEL v ~~ =1 Ov
4
Avit
3 2 1
0 -1 -2 -3
■
-
-4
104
20
A2 + 0.10
1
I 1I 35
I 05
35
106
DOSE [rad (Si)] Figure 42: Interface-trap and oxide-trap charge voltage shifts for transistors irradiated at dose rates from 0.10 to 200 rad(Si)/s. (After Ref. 112) is approximately a 3 V difference in threshold-voltage 0.1 and 200 rad(Si)/s. 4.5,4
shift between the transistors irradiated at
Anneal of Interface Traps
Unlike oxide-trap charge, interface traps do not anneal at room temperature. Some interface-trap annealing at 100°C has been reported by several workers [101,113,114]. However, higher temperatures are normally required to have significant interface-trap annealing [70, 115]. Figure 43 [70] is a plot of AV[h, AVil, and AVOIfor polysilicon gate transistors irradiated to 3 Mrad(Si) and then subjected to isochronal anneals at successively higher temperatures. At each temperature transistors were annealed for 30 minutes. The oxide electric field during irradiation and anneal was 2.5 MV/cm. For temperatures from 25 to 125°C there is a buildup of interface traps. For temperatures greater than 125”C, the number of interface traps begins to decrease. After annealing at 300”C, AVit has decreased by more than a factor of five from its peak value at
II-53
.
—
..
.
2.5 ~
I
I
I
I
I
I
I
I
I
I
2 1.5 f
1 0.5
L
1
0
>
0.5 1
E..= 2.5 MVlcm 3&MlN ANNEAL AT EACH TEMPERATURE
1.5< 2 25
I
I
I
I
I
I
I
I
I
50
75
100
125
150
175
200
225
250
TEMPERATURE
I
275 300
(“C)
Figure 43: Annealing of interface-trap charge at elevated temperatures. (After Ref. 70) 125°C. Even though asignificant amount of the interface traps have been annealed, there isstill some interface-trap buildup present afterthe300°C anneal. 4.5.5
Mechanisms for Interface-Trap Buildup
The mechanisms for interface-trap buildup presently are much more uncertain than the mechanisms for the buildup and neutralization of oxide charge. Several different mechanisms for interface-trap buildup have been proposed, including the direct creation of interface traps by ionizing irradiation, interface-trap creation by hole trapping, or interface-trap buildup through secondary mechanisms, The direct creation of interface traps by ionizing irradiation can be ruled out as a significant contributor to interface-trap buildup. Vacuum uhraviolet rddiation experiments [11 6-11 8] showed that interface traps can be created by non-penetrating radiation, In these experiments, the top of capacitors with thin metal gates were illuminated with nonpenetrating VUV radiation. All light was absorbed within the top oxide layer and none of the light reached the Si/Si02 interface. However, with a positively applied bias, interface trap buildup was observed to occur, similar to that for penetrating irradiation (high-energy gamma irradiation) [11 6,11 7]. These experiments confirmed that a negligible number of interface traps are created directly by irradiation. Instead. these experiments suggest that a necess~ precursor to interface-trap buildup is the generation of electron-hole pairs in the bulk of the oxide and the subsequent transport of holes through the oxide.
II-54
The role of hole transport in interface-trap buildup is not well understood. Recall from Section 4.5.1 above, that interface-trap buildup takes place over relatively long times: from seconds to thousands of seconds. On the other hand, for thin gate oxides, holes can transport through a gate oxide in microseconds. Thus, the time frames for interface-trap buildup are many orders of magnitude longer than the time frames associated with hole transport. Interface-trap buildup cannot depend solely on hole trapping at the interface. Insight into the role of hole transport in interface-trap buildup was first provided by Svensson [119] and later by Winokur, et al. [113], and McLean [120]. Svensson was the first to propose a two-stage model for interface-trap buildup. In the first stage, radiation-generated holes break Si–H bonds in the bulk of the oxide, liberating neutral interstitial hydrogen atoms. In the second stage of buildup, the liberated hydrogen atoms are free to diffuse to the Si/Si02 interface and break Si–H bonds at the interface creating dangling silicon bonds (interface traps) and molecular hydrogen. This model accounts for the slow buildup of interface traps. However, this model is inconsistent with the experimental observation that interface-trap buildup only occurs with a positive bias following irradiation. For a diffusion process, interface-trap buildup should occur for either a negative or positive bias. This inconsistency was resolved by Winokur and McLean, who also proposed a modified two-stage model. The first stage of Winokur and McLean’s model is similar to the first stage of Svensson’s model. With an applied bias (either positive or negative), radiation-generated holes in the oxide can transport by polaron hopping toward either the Si./Si02 or gate-Si02 interface. As they transport through the bulk of the oxide or become trapped, they can release sufficient energy (-5 eV) by localized excitation to break a strained Si-O bond or a weak H or OH bond with trivalent silicon. However, unlike the model of Svensson, the model of Winokur and McLean assumes that, instead of a neutral hydrogen atom being released, a charged ion is released as a bond is broken. The ion that is released is most likely a hydrogen ion [103,119-126]. In the second stage of buildup, with an applied positive bias, the ions can drift to the Si/SiOz interface. As ions reach the interface, they can rapidly break either Si–H or Si-OH bonds to form interface traps. In this model, the time dependence of buildup is governed by the time it takes for positive ions to drift to the Si/Si02 interface and buildup will occur only with a positive gate bias, consistent with experimental data. The magnitude of the buildup is governed by the number of ions released in the bulk of the oxide during the first stage of buildup. Even though the Winokur and McLean model can explain the time dependence of interface-trap buildup, it is inconsistent with the experimentally observed electric field dependence for interface-trap buildup in Polysilicon-gate and some metal-gate devices. In the Winokur and McLean model, ions are released as holes transport through the oxide by polaron hopping. As a hole transports through the bulk of the oxide, one expects [120] that an increase in electric field strength will increase the energy a hole imparts to the Si02 lattice, increasing the probability of releasing an ion and hence subsequently creating an interface trap. Thus, for the Winokur and McLean model, interface-trap buildup should increase with increasing electric field strength. Such a dependence was observed in early work on Al-gate capacitors [102,106]. However, as noted in Fi 39 for polysilicon-gate transistors, interface-trap buildup decreuses .!6 with approximately an E field dependence. A model which can account for this electric field
II-55
1.2
9
1
,
1 1 119
1
I 10-Mev
1
1
mI
1,,
1
v
1
,
I
111
,
1
1
1 1 111
#
1
1
1 111,
1
,
1
1 1
I
LINAC
1.0
0.8
0.6
nm T 35.8 nm ● 27.7
0.4
■ 47.6 nm
A 63.9 nm 0.2
+ 104nm n
0.0 1(P
,
1
mm ,,1
I
m
01
n
m m,
,11
I(P
1
m ,
1 1 111
1
,
1 ,
1(F
111
10’4
1
,
,
,
1 111
I(F
1
J
1
1
1
!
106
TIME (S) Figure 44: Interface-trap buildup after irradiation for dry-oxide polysilicon-gate transistors with
gate-oxide thicknesses from 27.7 to 104 nm. (After Ref. 100) dependence is the hole-trapping/hydrogen transport (HT)2 model of Shaneyfelt, et al. [100]. According to the (HT)2 model, for positive bias during irradiation, holes transport toward the Si/Si02 interface and become trapped near the interface. As the holes are trapped, nearinterfacial hydrogen ions are released, which transport to the Si./SiO* interface, interact at the interface, and create interface traps. The rate-limiting step according to Shaneyfelt’s model is the rate at which hydrogen ions drift to the interface. The electric field dependence according to this model will be governed predominantly by the capture cross-section for holes near the interface. This has been shown to follow approximately an E-in field dependence. Thus, Shaneyfelt’s model correctly predicts the experimentally observed electric field dependence. If interface-trap buildup results from hole trapping close to the Si/Si02 interface, there is no obvious reason for the rate of interface-trap buildup to depend significantly on gate oxide Except for very thick oxides, hole transport is complete within thickness [97, 100, 127]. milliseconds after irradiation. Thus, for moderately thick or thin oxides, hole transport is over before significant interface-trap buildup occurs. However, if interface-trap buildup results from the drift of hydrogen ions generated in the bulk of the oxide, the thicker the oxide, the longer it will take for hydrogen ions to drift to the Si/Si02 interface and the rate of interface-trap buildup should depend on gate oxide thickness. Figure 44 [100] is a plot of interface-trap buildup for gate oxides grown in dry oxygen (dry oxides) versus time after irradiation for transistors with gate oxide thicknesses from 27.7 to 104 nm. To first order, there is no dependence of the rate of interface-trap buildup on gate oxide thickness. Therefore, this data tends to support the (HT)2
II-56
II
10-MeV LINAC I
1.0
b= a
n
0.8 0.6 ●
0.4
Y
■
A *
0.2
23.2 nm 32.2 nm 47.1 nm 64.4 nm 100nm
t
0.0
I ,
1
,
,
, ,,,
100
,
1
1
101
1 , 1,,
1
1
,
102
1111
1
103
1
,
, ,11
104
1
1
1 , 111
105
,
1
, ,
1 ,
106
TIME (S) Figure 45: Interface-trap buildup after irradiation for wet-oxide polysilicon-gate transistors with gate-oxide thicknesses from 23.2 to 100 nm. (After Ref. 100) model, In contrast, Fig. 45 [100] is a plot of interface-trap buildup for gate oxides grown by steam oxidation (wet oxides) versus time after irradiation for transistors with gate oxide thicknesses from 23.2 to 100 nm. For the wet oxide transistors, there is a large difference in the time dependence of buildup between the 100 nm oxides and the other oxides, At longer times, there is also a difference in the amount of buildup for all oxide thicknesses, The data for the wet oxide devices doesn’t support either the (HT)2 model or the model of Winokur and McLean. For these devices, it is possible that for the thicker oxide transistors, there is some interface-trap buildup from hole-trapping near the interface and some from drift of hydrogen ions from the bulk of the oxide. Additional work investigating the dependence of the rate of interface-trap buildup on oxide thickness has shown a stronger oxide-thickness dependence versus time for interfacetrap buildup [97, 127]. This work suggests that, in other types of devices, most of the hydrogen ions are released in the bulk of the oxide. Clearly, more work needs to be performed to clarify the role of hole trapping and transport in interface-trap buildup. The ion that is released causing interface-trap buildup is almost certainly hydrogen. Hydrogen has long been known or suspected of being a key player in radiation-induced interfacetrap buildup [1 19,125,128]. The amount of hydrogen used in the ambient gases of high temperature anneals during device fabrication has been shown to strongly affect the number of radiation-induced interface traps [126]. The physical reaction to produce an interface trap is likely [109, 124, 129] H++e-+H–
Si=Si+
Hz+
●Si=Si, II-57
(18)
where H–Si=Si indicates a silicon atom bonded to one hydrogen atom back bonded to three silicon atoms, and Si=Si indicates a silicon atom with a dangling bond (interface trap) back bonded to three silicon atoms. This equation indicates that an interface trap is created as a hydrogen atom breaks a H–Si bond at the interface. ●
Note that, even though the details of the Winokur and McLean and the (HT)2 models are different, the general concepts of the two models are very similar. Both of the models depend on the generation of holes in the oxide, hole transport, and the release of hydrogen in order for interface-trap buildup to occur. These two models are the two most convincing models for interface-trap buildup. Whether hydrogen is more often released in the bulk of the oxide, near the Si/Si02 interface, or a combination of the two remains to be seen. In summary, the details of the mechanisms for interface-trap buildup still need to be resolved. However, several important observations can be made. First, interface-trap buildup depends on the generation of electron-hole pairs in the bulk of oxide. Interface-trap buildup is not caused directly by irradiation. Second, interface-trap buildup is linked in some manner to hole transport and/or trapping either in the bulk of the oxide or at traps near the Si/SiOz interface. Third, the release of hydrogen ions is apparently involved in most, if not all, interface-trap buildup. 4.5.6
Microscopic Defect Centers
The microscopic structure of the radiation-induced interface-trap defect center has been identified as a pb defect [82-85,130,131]. A pb center is a trivalent silicon defect site [132-134], similar to the E’ center except that the pb center is back bonded by three silicon atoms. The chemical notation for the pb center is ●3i=Si~. It has a magnetic field zero crossing at 2.008 with the magnetic field perpendicular to the (111) axis and a magnetic field zero crossing at 2.0014 for the magnetic field parallel to the (111) axis. It was first identified in irradiated MOS capacitors on (1 11) silicon using electron spin resonance. Within a factor of two in experimental uncertainty, the absolute magnitude of the number of pb centers was correlated to the number of interface-traps measured using capacitance-voltage measurements during irradiation and during post-irradiation anneals [82, 130]. The distribution of pb centers peaks at midgap and decreases toward either the conduction or valence band [82,130]. This distribution is consistent with the assumption that at midgap an interface-trap is paramagnetic and neutral [82]. In the upper part of the band gap, an interface trap is acceptor-like (can accept an electron), negatively charged, contains two electrons, and the pb center diamagnetic. Recall that for an EPR signal to be observed it must be paramagnetic (contain an unpaired electron). In the lower part of the band gap, an interface trap is donor-like (can give up an electron), positively charged, contains no electrons, and diamagnetic. In the middle of the band gap the interface trap is neutral, contains one electron, and paramagnetic. In (100) silicon, two distinct types of pb centers have been identified preirradiation [135, 136]. These centers are noted pb~ and pbl. The g tensor for the phi)center is similar to the g tensor for the pb center, indicating that these two centers are structurally similar [135,136]. The
II-58
Gate
Oxide
Sub
II /’” Interface Trap< Figure 46: Illustration of the concept of border traps. Note that border traps are near-interracial oxide traps. (After Ref. 110) ~-tensor for the Pbl center is unlike most all other centers in either silicon or silicon dioxide [135,136]. The nature of the l’bl center is presently unknown. Early work [135,136] suggested that it is a vari~t of the PM ~nkr. k ~s~t to c~std symme~, the pbl cen~r is consistent with ●3i=Si20 centers [135, 136]. However, theoretical calculations [137] and 170 experiments [138] strongly indicate that this isn’t the chemical identity. In fact, in these studies it appears as though the l’bl center is a closer analog to the pb in (111) than the PM. More work needs to be performed to identi~ the chemical structure of the PM and pbl centers. For irradiated oxides on (100) silicon, the dominant type of pb center appears to be the PM center [31]. 4.6
Border Traps
In the above discussion, we have identified two types of radiation-induced defects in MOS oxides, i.e., interface traps and oxide-trap charge. As we discussed in Section 4.4.2, oxide traps may be neutralized by electrons tunneling from the silicon into an oxide trap. This process cart be reversed with the application of a negative bias. The time that it takes for an oxide trap to be neutralized depends on the distance the trap is from the Si/Si02 interface. Thus, traps close to the interface can transfer charge back and forth from the silicon relatively easily and traps far from the interface may not transfer charge at all. If a trap can exchange charge with the silicon on the time frame of an electrical measurement, it will act like an interface trap rather than an oxide trap. These types of traps are called border traps [110]. The location of border traps, oxide traps, and interface traps in a MOS device is illustrated in Fig. 46 [110]. They are nearinterfacial traps in the oxide, but act electrically like an interface trap. For electron tumeling, the rate of tunneling from the silicon into an oxide charge is given by Eq. (13). As the distance from the interface increases, the time frame for tunneling increases exponentially. Thus, a border trap must be very close to the silicon/silicon dioxide interface. In one minute, tumeling electrons will passivate virtually all of the trapped charge in Si02 that lies within -3 nm of either the Si/Si02 or
II-59
3.0 x 10-12
1.5X1042
o 1(P
, I@
102
102
104
1(F
1(Y
Frequency [Hz] Figure 47: Amount of recombined charge versus measurement frequency. Increase in recombined charge is due to the filling and emptying of border traps. (After Ref. 142) the gate Si02 interface [47,62,110,139]. For an order of magnitude more or less increase in tunneling time, this distance changes by only iO.25 nm. Thus, near-interracial traps less than -3 nm of the interface are likely to be border traps in typical measurements, while traps more than 3 nm from the interface are likely to be oxide traps [110,140]. However, the exact “cutoff’ line between oxide traps and border traps will depend on process and measurement conditions. Note that for both border traps and oxide traps the defect center may be the same (e.g., E’Y center). To estimate the number of border traps, a new analysis technique has recently been developed [14 1]. This analysis technique combines threshold-voltage and charge-pumping measurements on n- and p-channel transistors. In some cases, the number of border traps measured on irradiated MOS transistors exceed the number of radiation-induced interface traps. This indicates that the number of border traps can be quite significant in some devices. The frequency of the measurement signal obviously plays an important role in determining whether a trap acts like a border trap or an oxide trap. For instance, I-V measurements which are routinely measured with sweep rates -4 V/s (equivalent to -1-4 Hz), may count an oxide trap as an interface trap if the oxide trap is within -3 nm of the interface. On the other hand, charge-pumping measurements which are typically performed at higher frequencies (-1 MHz), may not measure traps as interface traps as far into the oxide as the I-V measurements. This is illustrated in Fig. 47 [142]. Figure 47 is a plot of charge captured and emitted from traps (from interface traps or border traps) during a charge pumping measurement as the charge pumping signal is swept from inversion to accumulation (recombined charge per cycle) versus measurement fi-equency for an MOS transistor irradiated to 1 Mrad. For
11-60
frequencies below lowered. At the emptying a higher increasing number
-1 kHz, there is a rapid increase in recombined charge as the frequency is lower frequencies, electrons can tunnel farther into the oxide filling and number of oxide traps. Thus, as the frequency is decreased, there will be an of border traps.
The concept of border traps has been useful in clarifying several phenomena that depend on “near-interracial traps.” For example, present evidence indicates that 1/’ noise is caused Depending on the almost entirely by near-interfaciai oxide traps [1 10,140,143-148]. measurement method, a near-interracial oxide trap can be measured as either an oxide trap or an interface trap. Thus, although the same defect is involved, in some cases lf noise has been correlated with the number of oxide traps [144-147] and in other cases it has been correlated with the number of interface traps [143,147-150]. The latter case suggests that 1/f noise is associated with the number of pb centers which is unlikely. l/~ noise most likely correlates to the number of border traps. Thus, by distinguishing between interface traps (pb) and border traps one can explain the confusion in the literature on l/’noise [11O]. 4,7
Device Properties
The total threshold-voltage shift for a transistor is the sum of the threshold-voltage due to oxide-trap and interface-trap charge, i.e.,
shifts
AVOtand AVit can be determined from
A~),,i, = ~f’”
(20)
p(x)xdx ,
C(,xt(,x ‘J
where p(x) is the charge distribution of radiation-induced charge. It includes contributions from both radiation-induced oxide-trap and interface-trap charge. Note the change in sign between the charge distribution and the threshold-voltage shift. For positive charge, the threshold-voltage shift is negative; conversely, for a negative charge, the threshold-voltage shift is positive. Thus, for devices where oxide-trap charge dominates, the threshold-voltage shift will be predominantly negative. At high dose rates and short times, little neutralization of oxide-trap charge will occur and AVOtcan be large and negative. Conversely, interface-trap charge at high dose rates and short times will have had insufficient time to build up and AVit is normally small. Thus, at high dose rates and short times for either n- or p-channel transistors the threshold-voltage shift can be large and negative, For an n-channel transistor, large negative threshold-voltage shifts will significantly increase the drain-to-source leakage current, which in will turn cause significant increases in IC static supply leakage current, IDD,leading to potential IC failure.
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3 I Mrad(Si) N-CHANNEL 2
1 s -c >“ Q()
-1
-2 1 ()-2
10-1
100
101
102
I (’)3
DOSE RATE [rad(Si)/s] Figure 48: The change in threshold voltage versus dose rate. The data for this figure were taken from the data of Fig. 42. At moderate dose rates, some neutralization of oxide-trap charge will take place and some buildup of interface traps will also occur. Thus, for this case, both AVOtand AVi[ can be large. For an n-channel transistor, AVOtand AVit tend to compensate each other. Therefore, at moderate dose rates, even though the individual components (AVOtand AVi[) of the threshold-voltage shift can be large, the net threshold-voltage shift for an n-channel transistor can be small and the failure level of an IC may be relatively high. For the long times associated with low-dose-rate irradiations, a large fraction of the oxide-trap charge in hardened transistors will be neutralized during irradiation. Thus, AVO, is normally small. In contrast, the long times associated with low-dose-rate irradiations allow for interface-trap buildup to saturate. This results in a positive increase in threshold voltage in n-channel transistors and a decrease in carrier mobility which tend to reduce the current drive of a transistor and can lead to timing related failures for an IC. The dependence of thresholdvoltage shift on dose rate is illustrated in Fig. 48. The data for this figure were taken from the data of Fig, 42. Note that at the highest dose rate (200 rad(Si)/s), the threshold-voltage shift is
II-62
4
I I I I IIIT
r“’’””l
3 2 1 0 – -3 – -2 – # c # 8
-3
PRE
I
1 I 1111
I
I
I
1 111(
I
1
0.1
10.0
100
1000
(l O~”~ad)
TIME (h) Figure 49: The variation in AVh, AV@,and AVitduring room temperature irradiation and after a postirradiation biased anneal at temperatures of 25 and 125°C. This figure illustrates the concept of rebound. (After Ref. 67) large and negative. At the lowest dose rate (O.1 rad(Si)/s), the threshold-voltage shift is large and positive. At a dose rate of 2 rad(Si)/s, the threshold-voltage shift is approximately zero. For some commercial technologies, much less oxide-trap neutralization will occur even for the long times associated with space irradiations [66]. For these devices, the device response may be dominated by oxide-trap charge buildup similar to that for the short time response of hardened transistors after a pulse of radiation. Thus, for some commercial technologies, the cause of IC failure in a space environment may be dominated by large negative threshold-voltage shifts of n-channel transistors, leading to large increases in static supply leakage current of an IC. For other commercial technologies and most hardened technologies the cause of IC failure in a space environment may be dominated by large positive threshold-voltage shifts. (Note that, for a few hardened technologies, the rate of oxide-trap charge neutralization can be low and IC failure at low dose rates also can be dominated by increases in IC leakage [15 l].) One consequence of the time dependence of oxide-trap charge neutralization and interface-trap charge buildup is “rebound” [67,152,153]. Figure 49 [67] is a plot of threshold voltage versus irradiation and anneal for n-channel transistors irradiated at room temperature and annealed at either room temperature or at 125”C. An elevated temperature biased anneal
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I
100
n Ill N
80
i
a = a o
60
HIGH Nit , NOt
40
z
20 0
o
Nit , NOt
O N-ON AN-OFF
●
•l v
■ P-OFF TP-ON
N-ON
AN-OFF
P-OFF P-ON
4
8
1
I
12
16
ANit(lO“cm-2) Figure 50: The change in carrier mobility versus interface-trap charge buildup. (After Ref. 154) performed after irradiation is often referred to as a rebound test. A typical temperature for a rebound test is 10O°C. The bias during irradiation and both anneals was 10 V. The total threshold voltage is divided into its components due to oxide-trap and interface-trap charge. Note that for this plot AVOtand AVit are referenced to the initial threshold voltage value (-1 V). During irradiation, there is a large buildup of oxide-trap charge and interface-trap charge. For these devices and radiation conditions, the buildup of oxide-trap charge is larger than the buildup of interface-trap charge leading to a negative threshold-voltage shift. This is common for many technologies for a laborato~ irradiation at a moderate dose rate. During either the room temperature or the 125°C anneal, oxide-trap charge is neutralized. During the same time period there is little change in interface-trap charge (a slight increase). The net result is that after either anneal the threshold voltage is large and positive. The threshold voltage has thus “rebounded” from a value lower than its preirradiation value right after irradiation to a value greater than its preirradiation value after anneal. In effect, the rebound test has simulated a space environment by neutralizing a large fraction of the oxide-trap charge, without annealing interface-trap charge. An increase in the number of interface traps will reduce carrier mobility. The degradation of mobility with interface-trap buildup is illustrated in Fig. 50 [154] where the effective channel mobility normalized to its preirradiation value is plotted versus the number of interface traps for devices fabricated using several different process conditions. High and low Nit and NOtrefer to devices that were intentionally processed to result in high or low concentrations of radiationinduced interface-trap and oxide-trap charge. The degradation in mobility with interface-trap charge follows the general relationship [154],
II-64
w=
‘0
(21)
l+cx. ANi, ‘
where M is the preirradiation mobility and u is a constant. This equation is often referred to as the Sun-Plummer relation [155], which was derived for the change in mobility due to preirradiation fixed oxide charge, This relationship has been used to determine AVi[ from mobility [36,37] and combined threshold and mobility measurements [38 ,39]. Equation 21 has been found to be valid under most conditions, except for short times (d. 1 s) after a pulse of At early times after irradiation (-0.01 s), there can be a significant irradiation [156]. concentration of oxide-trap charge close to the Si/Si02 interface which can affect, and in some cases dominate, the degradation in mobility, However, as the electron tunneling front moves into the oxide, neutralizing oxide charge close to the intefiace, the importance of charged hole traps on mobility becomes increasingly less [156]. Recent work by Zupac, et al. [157], has also suggested that for some technologies Eq. 21 must be modified to include oxide-trap charge scattering even for long times after irradiation. 4.8
Application of the Knowledge of Basic Mechanisms — Case Studies
The time and effort that has been spent in investigating the mechanisms of radiation effects cannot be justified if the only benefit was to the academic community. To justify the costs, one must be able to apply the understanding of radiation effects towards improved In practice, the knowledge of the basic technological capabilities for system applications. mechanisms of radiation effects has enabled the scientist and engineer to make significant advances in technology development and hardness assurance testing. In this section, three examples are presented of where the knowledge of the basic mechanisms of radiation effects has been used to advance capabilities. 4,8.1
Process Hardening
Historically, to develop a hardened technology, process steps were usually chosen on the basis of those that minimized the radiation-induced threshold-voltage shift of n-channel transistors using a moderate dose-rate laborato~ radiation source (e.g., CO-60). This criterion was chosen in order to prevent n-channel transistors from going into depletion mode and, thus, to minimize the radiation-induced increase in static supply leakage current of an IC. As we discussed above, for an n-channel transistor irradiated at moderate laboratory dose rates, oxidetrap charge and interface-trap charge tend to compensate each other. This can lead to small threshold-voltage shifts, even though the individual components of oxide- and interface-trap charge are large. At very low dose rates, hardened transistor response is often governed primarily by interface-trap charge, while at very high dose rates, transistor response is governed primarily by oxide-trap charge. Thus, minimization of the n-threshold voltage at laboratory dose rates does not necessarily guarantee maximal performance in either a low-dose-rate (e.g., satellite) or highdose-rate (e.g., weapon) application. In fact, as shown below, in some cases those process steps that minimize the radiation-induced threshold-voltage shift for laboratory irradiation at one particular dose rate may lead to degraded response in a satellite or weapon environment.
II-65
4
3 2 1 0
L
.
-1
-2 “3 -4 FG ANNEAL
N2 ANNEAL
Figure 51: The variation in AVh, AVO[,and AVi[ for devices fabricated with an intermediate oxide annealed in forming gas (90% nitrogen, 10% hydrogen) or in pure nitrogen. (After Ref. 106) Based on our knowledge of radiation effects, we can hypothesize that it would be better to identi~ and use process steps that minimize individually either (or both) interface-tmp charge or oxide-trap charge, Note that, by separately minimizing the individual components of radiationinduced charge, the threshold-voltage shift for a laborato~ CO-60 irradiation rndy be larger, but the threshold-voltage shift for either a satellite or weapon exposure will be smaller. This is illustrated in Fig. 51 where the total threshold-voltage shift and the threshold-voltage shifts due to interface-trap and oxide-trap charge measured on capacitors are shown for anneals of a deposited oxide in different ambient gases [106]. The deposited oxide was used as an intermediate oxide between polysilicon and metal in a hardened technology, The anneals were all at a temperature of 900”C. The original process step included a forming gas anneal ( 10~0 hydrogen, 90% nitrogen) of the deposited oxide. This step was chosen to minimize the threshold-voltage shift as shown in Fig. 51 where Av[h was only -0.08 V after irradiating to 1 Mrad(Si). However, as noted above, incorporating hydrogen in the ambient gases of anneals after polysilicon deposition increases the amount of interface-trap charge [126]. To minimize interface-trap charge, an anneal without hydrogen in pure nitrogen was evaluated. As shown in Fig. 51, the pure nitrogen anneal lead to a decrease in oxide-trap charge and a larger decrease in interface-trap charge. As a result, the total threshold-voltage shift was larger for the capacitors annealed in nitrogen than for the capacitors annealed in forming gas. Based on the old method of determining process procedures, the nitrogen anneal would have been discarded because it resulted in a larger, negative threshold-voltage shift. However, because it reduced the amount of interface-trap charge (important for space applications) and oxide-trap charge (important for both space and weapon applications), this process step was adopted in developing an improved hardened technology. Note that, in order to minimize the threshold-voltage shift, the old process
II-66
step incorporating hydrogen actually caused more degradation in device response in a satellite or weapon environment. 4.8.2
Development of Reliable Hardness Assurance Test Guidelines
Radiation test guidelines have been written with the intent to ensure device functionality in either a tactical or space environment. One such guideline in the U. S. is MIL-STD 883, Method 1019. The latest version of this test guideline is MIL-STD 883D, Method 1019.4 [15 1,158,159]. Earlier versions of this test guideline were written based on the often erroneous assumption that, if a device was irradiated at low dose rates, significant annealing of the radiation damage would occur during irradiation exposure leading to less degradation than for moderatedose-rate laborato~ irradiations. Thus, it was assumed for a satellite environment, a simple test to the dose level of the system application would be sufficient to guarantee system performance requirements. As we noted above, this assumption is only true if oxide-trap charge dominates space response. Significant neutralization of oxide-trap charge can occur for a low-dose-rate irradiation. However, interface-trap charge is at a maximum for low-dose-rate irradiations. Thus, for low-dose-rate irradiations, oxide-trap charge provides less compensation of interfacetrap charge, leading to larger positive threshold-voltage shifts for an n-channel transistor. The magnitude of the threshold-voltage shift may be larger for a low-dose-rate irradiation than for a moderate-dose-rate irradiation. Note that, for a moderate-dose-rate laboratory irradiation, the threshold-voltage shift of an n-channel transistor is often negative leading to increases in leakage current of an IC, For a low-dose-rate irradiation, the increase in threshold voltage and decrease in camier mobility lead to degradation in timing parameters of an IC. Not only are the thresholdvoltage shifts different, the potential failure mechanisms may be also different [112]. lf fhe failure mechanisms of a device using a laboratory radiation source and in the intended environment are different, one cannot directly simulate the intended environment using a laborato~ source. Knowledge of the basic mechanisms of radiation effects led to an improvement in the test method which was incorporated into Method 1019.4 [15 1,158, 160]. The improvement consisted of a two-part test to ensure that a device will function within acceptable, bounded limits during its lifetime. The first part of the test is a laboratory irradiation at a dose rate between 50 to 300 rad(Si)/s to the specification requirement. As long as the laborato~ dose rate is greater than the expected space dose rate, this test will ensure that the threshold-voltage shift of gate- or fieldoxide transistors will be more negative for the laboratory irradiation than in space. Thus, this part of the test bounds the contribution of oxide-trap charge. The second part of the test is a 100”C, l-week “rebound” test following an additional irradiation to 50% of the specification requirement. As long as the rebound anneal does not anneal interface-trap charge, this test will ensure that the threshold-voltage shift will be more positive than in space, and, thus, provide an effective way to test for interface-trap related failures. 4.8.3
Process Control
To reduce costs and the time associated with device qualification, the U. S. Government is pursuing the Qualified Manufacturer’s List (QML) methodology to qualify integrated circuits
IF67
I
IN LINE SPC
OF RELEVENT
S
A
v
1 TEST STRUCTURE TO IC
($)
r
DETAILED
EXPERIMENTS
I N G s
RADIATION
PARAMETERS
ON TEST
STRUCTURES
R1
ENVIRONMENT
US~HREAT
KNOWLEDGE Figure 52: Illustration of increased cost savings that can be obtained in device qualification by increasing our knowledge base. (After Ref. 161) for high reliability and radiation hardness. There are three phases to QML implementation: certification, qualification, and quality assurance [16 1]. During certification a manufacturer’s process is “baselined” and the radiation hardness assurance capability level for the technology is During quality assurance the radiation hardness of individual wafer lots is demonstrated. verified. As our knowledge base increases, higher levels of QML methodology can be employed, resulting in increased cost savings as illustrated in Fig. 52 [161]. The highest level of QML implementation involves in-line statistical process control (SPC) of relevant radiation parameters and test structures for certification and quality assurance. Key to defining relevant radiation parameters is a thorough understanding of mechanisms of radiation response and improved physical models, statistical models, circuit simulators, etc. At present, our knowledge base is not sufficient to fully implement in-line SPC QML methodology. However, as our knowledge base increases, we will eventually be able to quali~ integrated circuits for radiation hardness using inline process controls. This will result in considerable cost savings in qualification testing.
II-68
-10.0 -8.0 -6.0 4.0
I
I
I
I
DRY OXIDE n=l.65
-2.0
-1.0 -0.8
-0.6 -0.4
100
.
a)
-1
1-
-0.2
200
400
OXIDE THICKNESS
-10.0 -8.0 -6.0
I
I
I
(~)
I
DRY OXIDE n=l.45
-4.0
i
-2.0
~
~ >= d
6008001000
WET OXIDE n=l.61
-1.0 -0.8 -0.6 -0.4 -0.2 -0.1
b)
100
200
400
6008001000
OXIDE THICKNESS
(~)
Figure 53: The dependence of the threshold-voltage shift due to oxide-trap and interface-trap charge on oxide thickness. 4.9
Special Concerns for Commercial Devices
4.9.1
Ultra-Thin Oxides
The general trend in commercial MOS devices is towards ultra-thin oxides. As the oxide thickness decreases, the amount of interface-trap and oxide-trap charge decreases with slightly less than a t~=thickness dependence [162,163]. This is illustrated in Fig. 53 where AVil and AVOt are plotted versus gate oxide thickness for dry and wet gate oxide transistors. The thickness dependence varies from - ~X-]”5to LX-l“a. For very thin oxides (<20 rim), there is evidence that the amount of radiation-induced oxide-trap charge decreases with even a faster dependence on
II-69
oxide thickness [164]. Thus, the total-dose hardness of commercial gate oxides should improve as the gate oxide thickness is decreased, However, the basic mechanisms of radiation effects for ultra-thin oxides is different than that for moderately-thick gate oxides. For ultra-thin oxides, oxide-trap charge can be neutralized by electrons tunneling from either the gate or the Si/Si02 interface. As presented in Section 4.4.2, the distance of the tunneling front into the oxide is given by Eq. (14). A tunneling front can be described for each interface. If the distances the tunneling fronts extend into the oxide are defined as x~~ and x~$i for the gate and silicon interfaces, respectively, then the total depth of oxide charge that is neutralized is given by x~~ + x~si. If the sum of the two fronts is equal to the gate oxide thickness, all oxide traps in the oxide will be neutralized. The rapid loss of trapped holes in the oxide for very thin oxides (<20 nm) is caused by tunneling of electrons from the gate or silicon interface [164]. Because a relatively higher number of the oxide traps will be accessible to electron tunneling, there will also be a relatively higher number of oxide traps that can act as border traps [1 10]. Recall that border traps are traps in the oxide that can communicate with the silicon on the time frames of an electrical measurement. In fact, for very thin oxides (<6 rim), there may be no “bulk-like” traps, and all traps in the oxide have the potential to function as border traps. Thus, for ultra-thin oxides, it is possible that to have no net positive radiation-induced oxide-trap charge, and all traps may function electrically like interface traps (either true interface traps or border traps). 4.9.2
Field Oxides
Even though the radiation hardness of commercial gate oxides may improve as the IC industry tends towards ultra-thin oxides, field oxides of advanced commercial technologies may still be very soft to ionizing irradiation. A relatively small dose in a field oxide [-10 krad(Si) for many commercial devices] can induce sufficient charge to cause field-oxide induced IC failure. Field oxides are much thicker than gate oxides. Typical field-oxide thicknesses are in the range of 200 nm to 1000 nm [47]. Unlike gate oxides, which are routinely grown by thermal oxidation, field oxides are produced using a wide variety of deposition techniques. Thus, the trapping properties of a field oxide may be poorly controlled and can be considerably different than for a gate oxide. Even for thermally grown thick oxides, the buildup of charge in gate and field oxides can be qualitatively different [165,166]. In thick Si02 capacitors (>100 rim), interface-trap buildup has been observed within 4 ms following a pulse of ionizing irradiation [165]. The buildup was found to be independent of oxide field and polarity and occurred with approximately the same efficiency at room temperature and 77 K. This suggests that some “prompt” interface traps could have been created directly by irradiation. On similar devices, a significant amount of hole trapping was observed in the bulk of the oxide [166].
11-70
~ / .,
———
n+ .,,
———
1
SOURCE
,,,~..i. .:,
——
FIELD OXIDE T
.;.,’
-,+—
—— ,,. ,., .,,.,..’:, *,.*—,—-
-—
LEAKAGE PATH
GATE METAL \
/
1 —— __
GATE ‘x’DE
—
FIELD OXIDE
?
(W20NNEL
POSITIVE :FW:D
Figure 54: Cross-section of a parasitic field oxide transistor showing the primary leakage current paths. (After Ref. 167) A cross-section of a typical commercial field oxide is shown in Fig. 54 [167]. The threshold voltages of parasitic field oxide transistors are initially very large. As radiationinduced oxide charge builds up in a field oxide, it causes the threshold voltage of the field oxide to tend to go toward depletion mode for field oxides over a p substrate (equivalent to an nchannel field oxide transistor). If the buildup of charge is large enough, excessive leakage current can flow from the source to drain of the gate-oxide transistors and between transistors. The excess leakage current is illustrated in Fig. 55 [167]. Plotted in Fig. 55 are the drain-tosource leakage current versus gate-to source voltage curves for an n-channel gate-oxide transistor with (combined curve) and without field-oxide leakage and for a parasitic field-oxide transistor. The field-oxide leakage significantly adds to the drain-to-source current at zero gate voltage. Thus, the field-oxide leakage prevents the transistor from being completely turned off. This will greatly add to the static supply leakage current of an IC, Field oxide leakage current limits the radiation hardness of most commercial integrated circuits and it is a major problem for advanced hardened technologies, both at high and low dose rates. Details of commercial field-oxide fabrication and its affect on IC performance are given in part three of this Short Course.
n-7 1
10-2
1
1
I
I
I
I
1
I
I
IN COMBINED
10+ 10-5
10-7
_~
I ()-8
0’
.
I@ g
POSTRAD \ - (field or edge)
-
10-9
\/-
PRERAD (gate)
“
‘RERAD (field or edge) \
/
.
10-10 :/
1011 I (’J-12
-6
-4
-2
0
2
4
6
8
10
12
14
vG~(v) Figure 55: I-V curves for a gate-oxide transistor and a parasitic field-oxide transistor showing the increase in leakage current of the gate oxide-transistor caused by the parasitic field-oxide transistor. (After Ref. 167)
4.9.3
Process-Induced
Defects
To fabricate commercial (and hardened) integrated circuits, it is sometimes necessary to use fabrication techniques that can lead to radiation-induced interface traps and oxide charge. This is especially true for advanced technologies that require special tools for defining small geometries, including electron, ion, and x-ray sources used to replace optical lithography; ion and plasma sources used for etching; and plasma and e-beam sources used for material deposition. The total dose that a device may be exposed to during fabrication can easily exceed that during device operation in the natural space environment. For example, the total dose that a device may be exposed to during a single resist patterning step using e-beam or x-ray techniques can well exceed 10 Mrad(Si) [168]. Fortunately, most darnage created by these sources is annealed out during the normal course of the process flow in high-temperature anneals and oxidations following the process exposure. Most of the damage caused by eleetron, x-ray, and ion irradiation can be annealed out by a moderate temperature metal sinter (-450”C) step, as long as a large number of new vacancies are not created in the oxide [169]. However, in some cases higher temperature anneals are required to prevent increased radiation-induced degradation [168]. Details of process-induced defects are discussed in part three of this Short Course.
II-72
POLY-SI GATE BACK CHANNEL
GATE OXIDE
n+ SOURCE
Si SUBSTRATE
~
“DEWALL
SIDEWALL CHANNEL
S1 SUBSTRATE
Figure 56: Cross-sections ofasilicon-on-insulator 5.0 TOTAL-DOSE 5.1
v
transistor (SOI). (After Ref. 162)
EFFECTS — OTHER DEVICE TYPES
SOI Devices
Silicon-on-insulator (S01) devices are an attractive alternative to bulk CMOS devices for space applications. A cross-section of a SOI transistor is illustrated in Fig. 56 [162]. As shown in the figure, the active silicon channel region is an “island” built on top of an insulating (buried oxide) layer instead of a silicon substrate. Two common fabrication methods are separation by implanted oxygen (SIMOX) and bonded and etch back SOI (BESOI). SIMOX substrates are prepared by implanting oxygen into a silicon substrate at very high energies and to very high implant levels. After implantation, the substrate must be annealed at very high temperatures. BESOI substrates are prepared by growing thermal oxides on two silicon wafers, bonding the wafers together at moderate temperatures (-900”C), and etching down one of the sufiaces to obtain the active channel. Because SOL/MOS transistors are fabricated on an insulating layer, the amount of p-n junction area is greatly reduced. The reduced junction area leads to lower parasitic capacitance for faster operation, and to a reduction in the generation volume leading to a considerable reduction in the sensitivity of SOI ICS to single-event upset and other transient effects. The absence of a conducting path underneath the MOS transistor completely eliminates parasitic pnpn paths that can cause latchup. However, the fabrication conditions of a SOI transistor add to the complexity of the total-dose response of SOI devices. In this section, the mechanisms for total-dose ionizing radiation effects in SOI transistors are presented. The total-dose hardness of an SOI transistor depends primarily on the radiation hardness of three oxides: 1) gate, 2) sidewall, and 3) buried oxide. The mechanisms for the radiationinduced degradation of the gate oxide of a MOS/SOI transistor are identical to the mechanisms for the gate oxide of a MOS transistor fabricated on a bulk silicon substrate discussed above. The sidewall and back-channel (associated with the buried oxide) leakage paths are illustrated in Fig, 56. The sidewall oxide exists as the gate oxide extends over the edges of the silicon island
II-73
I
I
POST-RAD
BACK-CHANNEL CURRENT
SIDEWALL CURRENT
1
-8
I
-6
1
I
-4
I
1
-2
I
1
0
1
I
2
1
4
GATE VOLTAGE (V) Figure 57: I-V curves for a gate oxide transistor on a silicon-on-sapphire substrate, Illustrated are the contributions of back-channel and sidewall leakage to the leakage current. (After Ref. 170) and forms a parasitic transistor in parallel with the top transistor. In some cases, the sidewall oxide is less radiation tolerant than the top oxide and can greatly increase the top oxide transistor leakage current, The sidewall oxide induced leakage forms a shoulder in the MOS transistor I-V curve as illustrated in Fig. 57 [170]. (Figure 57 was actually taken from an MOS transistor fabricated on a silicon-on-sapphire (SOS) substrate. However, an MOS transistor fabricated in a SOI substrate has the same qualitative nature for sidewall and back-channel leakage current.) Note that the leakage current caused by a parasitic sidewall transistor is similar to that caused by a parasitic field-oxide transistor for a bulk silicon MOS transistor. The sidewall leakage can be eliminated by proper processing of the sidewalls [170-173]. For example, heavily doping the sidewall by selective implantation can be used to increase the threshold voltage of the parasitic sidewall transistor, reducing its importance to the radiation response [170,171]. Ionizing radiation induces the buildup of positive charge near the silicon/buried oxide interface and interface traps at the interface. The radiation-induced charge can invert the bottom surface of the silicon channel forming a conducting channel (back channel) between the source and the drain of the transistor. If the channel is not fully depleted, the gate bias of the MOS transistor has only a weak effect on the back-channel leakage current. Thus, for non-fully depleted channels, the buried oxide causes a fixed increase in leakage current which is relatively independent of gate bias as illustrated in Fig. 57.
II-74
5
-5 -\
“15
-o-m-MI
-25 1(P
%,
-5V v ,u~ = -3V V ~u~= Ov
V sub =
I
1
I
I
1
‘>< \ -w
, 1
I
I
I
I
1
105
1
I
I [
106
GAMMA DOSE [rad(Si)] Figure58: Back-channel transistor threshold-voltage shift versus dose for varying substrate biases. (After Ref. 174) However, the bias on the bottom substrate can strongly affect the radiation response. By applying a negative bias to the bottom substrate, holes generated in oxide during irradiation will preferentially drift toward the back electrode, reducing the charge accumulated at the surface of the silicon channelhwied oxide interface, thus, reducing the back-channel leakage current. This is illustrated in Fig. 58 [174] where the back-channel threshold-voltage shift is plotted versus dose for n-channel transistors. (Note from Fig. 56 that, if the SOI transistor structure is flipped upside down, the transistor still looks like an MOS capacitor with the substrate as the gate electrode. This is often referred to as a back-channel transistor.) The data of Fig. 58 were taken from SIMOX SOI transistors with the front (top) channel transistor biased in accumulation to separate the effects of the front- and back-channel transistors. For an n-channel transistor (p-type island), a large negative threshold-voltage shift of the back channel will invert the bottom surface of the channel leading to leakage current. The negative threshold-voltage shift for n-channel back channel transistors is greatly suppressed by applying a large negative substrate bias, which will lead to a reduction in back-channel leakage current. The radiation response of buried oxides has been found to be highly dependent on the fabrication process [175, 176]. SIMOX buried oxides are fabricated by implanting substrates with oxygen at high dose levels and energies. As such, it is natural to expect that the oxide may include numerous implant related defects throughout the buried oxide that can trap radiationPrevious work [176- 180] has shown that up to 100% of the radiationgenerated charge. generated holes are trapped in the bulk of the oxide at deep trap sites close to their point of origin. This is in contrast to thermal oxides where a smaller fraction (-3Y0 for hardened oxides) of the radiation-generated holes are trapped near the Si/SiOz interface. Once trapped, some of the holes are slowly neutralized by electrons by thermal detrapping at room temperature [176180]. No significant transport of holes through the buried oxide has been observed [176,181] for SIMOX buried oxides fabricated using normal process conditions [181]. However, for SIMOX buried oxides receiving a supplemental oxygen implant and a low temperature anneal, photocurrents have been observed indicating the transport of radiation-induced charge carriers
II-75
through theoxide [181]. Inaddition toholetrapping, electrons arealso trapped throughout the bulkofthe buried oxide [176]. Mostofthe trapped electrons aretherrnally detrappedwithinels after a pulse of irradiation. This makes electron trapping relatively unimportant for the natural space environment. After the electrons are detrapped, the resultant charge is due to a high concentration of trapped holes causing large negative threshold-voltage shifts of the buried oxide. BESOI buried oxides are fabricated by bonding together two thermal oxides. As long as the bonding process does not degrade the properties of the thermal oxides, BESOI buried oxides should look more like standard thermal oxides than SIMOX buried oxides [175,182]. Only moderate hole trapping in the bulk of BESOI buried oxides has been observed [175]. However, some electron trapping can occur, presumably at the bond interface [175]. Several microscopic defects have been identified using EPR in SOI buried layers. These defects play a role in instabilities in the buried oxides in radiation environments. The SOI technology most extensively studied is SIMOX technology. In SIMOX material all of the defects in the buried oxide are due to excess silicon indicating that the post-implantation, high temperature anneal step used to form the buried oxide is the source of the defects [91]. The primary defect identified by EPR in SIMOX material is the E’Ycenter [93,94,183-187] similar to that for gate oxides. However, in contrast to gate oxides, the variation in the number of E’Y centers does not track with the variation in positive charge in the buried oxide. Thus, E’Yare not the primary source of radiation-induced oxide-trap charge [93,94]. The concentration of E’ centers has been coupled to electron trap sites in the buried oxide in which a substantial fraction of the E’ centers are positive and compensated by trapped negative charge [188]. In addition to the E’Y center, several other types of defect centers have been identified. One of these is a relatively new class of defect center which has been categorized as a delocalized spin center [186, 187,189]. The defect center is delocalized in the sense that the unpaired electron is not associated with any one particular atom. Both E’Y and delocalized spin centers have also been identified in BESOI material [190]. The delocalized spin center in BESOI material was found to be hydrogen related [190]. In BESOI material, the radiation-induced EPR centers are located near the bonded interface [91 ]. Therefore, the bonded interface is a potential hole-trap site and may lead to radiation-induced back-channel leakage. In addition, to the defects in BESOI buried oxides, EPR has also identified a new oxygen-related donor defect in the silicon substrate near the bottom Si/Si02 interface [191]. The donors appear to result from the nonoxidizing anneal during the bonding process. These donors are also present in SIMOX material [192] and may change the doping concentrations of the substrates. 5.2
Nitrided Oxide Devices
Attractive alternatives to thermal silicon dioxide for ultra-thin oxides for advanced deep submicron technologies are nitrided oxides and deoxidized nitrided oxides (RNO) [193-198]. Nitrided oxides have a lower pin-hole density than SiOz, can be grown at high temperatures permitting better uniformity and less compressive stress and fixed charge, and can retard the diffusion of dopants through the insulator which can affect the channel resistivity [194]. These properties make nitrided and RNO dielectrics attractive for ultra-thin gate-oxide commercial and
II-76
hardened devices [194]. RNO oxides have been shown to be superior to thermal oxides in radiation hardness [199,200] and hot-carrier degradation [20 1]. Nitrided oxides can be fabricated by several different methods. One of the most straightforward methods is to anneal a thermal oxide in an ammonia (NHq) ambient. An ammonia anneal results in a large concentration of nitrogen throughout the dielectric with peak concentrations at both interfaces. Nitridation of thermal oxides can result in a large number of electron traps [202]. The electron traps are responsible for higher preirradiation threshold voltages and lower carrier nobilities [202,203]. The nitrided oxide can be deoxidized using a high temperature oxygen anneal, forming a deoxidized nitrided oxide dielectric (RNO). Deoxidizing the nitrided oxide further reduces the amount of nitrogen in the bulk of the dielectric and at the gate interface, leaving a large peak near the dielectric/silicon interface. The RNO process can be optimized to result in transistors with preirradiation interf%ce-trap densities comparable to thermal oxides. Reoxidation also reduces the number of electron traps [204], but it can result in higher preirradiation fixed charge concentrations [199]. The primary difference between thermal and RNO dielectrics in ionizing radiation environments is the nearly total lack of interface-trap buildup for RNO dielectrics [199]. RNO dielectrics can be fabricated in which there is no measurable interface-trap buildup for transistors irradiated to total doses in excess of 50 Mrad(Si) [199]. This makes RNO gates attractive for space applications. For those cases where some interface-trap buildup was observed, the number of interface traps does not increase in time after irradiation [200]. This likely occurs because hydrogen released in the bulk of the dielectric or near the interface (which is responsible for interface-trap buildup in thermal oxides), cannot penetrate the nitrogen rich oxynitride layer near the interface and create an interface trap [200]. RNO dielectrics can be fabricated so that the amount of oxide-trap charge buildup for a RNO oxide is lower to or comparable to that for a thermal oxide. Fig. 59 [199] is a plot of the threshold-voltage shift at midgap for p-channel transistors fabricated with a hardened oxide and with a RNO oxide versus dose. The oxide and RNO dielectric thicknesses were 37 nm and the preirradiation fixed charge levels were -3x 1010 and 1011 cm-2, respectively. At midgap, interface-trap charge is neutral, thus the threshold-voltage shift at midgap corresponds to the threshold-voltage shift due to oxide-trap charge. The bias during irradiation for the hardened thermal oxide was +5 V and the bias for the RNO oxides was either +5 or -5 V. After irradiating to 10 Mrad(Si02), the amount of oxide-trap charge buildup in the hardened thermal oxides is more than twice that for the RNO oxides. Note that for the RNO oxide transistors, the shifts are nearly equal for biases of +5 and -5 V. The temperature and electric field dependence of hole transport in RNO dielectrics have been investigated [205]. Results show that the charge yield in RNO dielectrics is equal to that in thermal oxides and that the hole transport properties in RNO dielectrics are qualitatively similar to that for hardened thermal oxides in that, for both RNO dielectrics and thermal oxides, hole transport is dispersive in time and strongly temperature and electric field dependent. However, the temperature dependence and electric field dependence are quantitatively different for the two types of oxides [205]. Figure 60 [205] is a comparison of the time for 25, 40, and 50% recovery
II-77
o ● HARD OXIDE, +5V ■ REOX NIT OX, +5V ❑ REOX NIT OX, -5V .V -1 >
-m E
>
4
.2
-3
0.1
10
1
100
DOSE [Mrad(Si02)] Figure 59: The change in midgap voltage measured on RNO and thermal oxide transistors versus dose. The midgap voltage shift corresponds to the threshold-voltage shift due to oxidetrap charge. (After Ref. 199) The of threshold-voltage shifts for RNO and thermal oxides as a function of temperature. threshold voltage was measured in the linear region. The electric field in the insulators was 1.35 MV/cm. Note that, at 193 K, the time for 40% recove~ is more than 3 orders of magnitude longer in RNO dielectrics (solid symbols) than in thermal oxides (open symbols). For an electric field of 1.35 MV/cm, the thermal activation energies for the RNO and thermal oxides are 0.32 and 0.50 eV, respectively. At higher electric fields and at low temperatures, the recovery time in RNO dielectrics is considerably lower (opposite to that for lower electric fields and higher temperature irradiation and anneals) than for thermal oxides as illustrated in Fig. 61 [205]. For the data of Fig. 61, the temperature during irradiation and anneal was 77 K. Note that, in all cases examined, at electric fields from 2 to 4 MV/cm, the time for recove~ in RNO dielectrics is more than an order of magnitude less than for thermal oxides. To identify the microscopic nature of point defects in nitrided dielectrics, EPR measurements have been performed on nitrided and deoxidized nitrided dielectrics [206]. Nitridation of a thermal oxide tends to reduce the number of radiation-induced E’ centers, In Bridging nitrogen addition, nitridation introduces bridging-nitrogen defect-center precursors.
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TEMPERATURE (K) 300
250
150
200
7
3
10:0/TEMPERATURE
(K-1;
Figure 60: The recovery time versus temperature for RNO and thermal-oxide transistors. (After Ref. 205) centers are a nitrogen atom bonded to two silicon atoms. This leaves two nitrogen bonds available for trapping charge. Reoxidation causes an increase in the number of radiation-induced E’ centers and reduces the number of bridging nitrogen precursors. The bridging nitrogen centers appem to be related to electron trapping effects in nitrided oxides. The E’ centers present after reoxidation appear to be different from those in thermal oxides in that they are electrically neutral when paramagnetic [206]. Thus, most of the E’ centers in RNO dielectrics do not appear to be associated with radiation-induced oxide-trap charge. Based on etch-back measurements on nitrided and RNO dielectrics, the distribution of bridging nitrogen centers peaks near the gate/Si02 interface and radiation-induced E’ centers are located uniformly throughout the dielectrics. Recall that for a thermal oxide, radiation-induced E’ centers can be located near the Si/Si02 interface. Therefore, the nitridation process changes the distribution of radiation-induced E’ centers.
II-79
103
102 s
T=77K ii
‘0’
i= * u
OXIDE --100
w > g 10-1 Ill E
t~,= 37 nm
RNO
=
—
•l 25% RECOVERY A 50% RECOVERY
\
■
O 75% RECOVERY
BEST FITS TO SL~PES~~, qa/2kT OXIDE 6.0 cm/ MV ~A RNO 3.7cm/MV 5A
I ()-2
\
b
w
1 ()-3
2
4
3
INSULATOR
5
FIELD (MV/cm)
Figure 61: Recovery time versus electric field for RNO and thermal-oxide transistors. (After Ref. 205) 6.0 SINGLE-EVENT
PHENOMENA
One of the most detrimental effects of the natural space environment on electronics is single-event effects (SEE). Single event effects were first postulated in 1962 by Wallmark and Marcus [207] and first observed in spacecraft electronics in 1975 by Binder and Smith [208]. In memory circuits, information is stored at nodes in a circuit. If a high-energy heavy ion strikes a circuit node, it can create sufficient charge in a transistor to change the state of the node and cause false information to be stored, This type of failure is known as single-event upset (SEU), This is a non-destructive or soft error. In addition to heavy ions, protons and neutrons can also cause single-event upset. A soft error can be corrected by reprogramming the circuit into its correct logic state or by restarting an algorithm in a central processing unit. The number of soft errors is normally specified in units of errors/bit-day. If the error rate is too large, it can result in performance degradation of a system and potentially mission failure. Another class of single-event effect that is not correctable by reprogramming is termed a hard error. Hard errors include single-event burnout (SEB), single-event gate rupture (SEGR), latchup, and snapback. If a hard error occurs, a circuit element can be physically damaged and the error cannot be corrected by reprogramming. Latchup is a high current condition that results
11-80
from parasitic thyristor (SCR) action in 4-layer structures (e.g., CMOS ICS). Snapback is a high current, low resistance condition that occurs only in n-channel transistors. Both latchup and snapback can be triggered by large current transients created by the incident particle. Once a circuit is “latched up”, large currents can flow, and remain unless the power supply to the circuit is interrupted. Unless the power supply current is limited, latchup and snapback can cause permanent damage to a circuit. In this section the basic mechanisms of single-event upset at the transistor level are presented. In addition, we discuss the mechanisms for two types of heavy-ion induced hard errors: single-event burnout and single-event gate rupture. Single-event induced latchup and snapback are discussed in detail in other parts of this Short Course. For any given transistor, the number of soft errors is highly dependent on the circuit design. Circuit effects also are discussed in other parts of this Short Course. 6.1
Mechanisms of Charge Collection
As a high-energy ion passes through a material, it loses energy by excitation and ionization of atoms, creating a very high density electron-hole plasma along the path of the ion [2]. The amount of energy that an ion deposits per unit depth in a material is given by its stopping power. The mass-stopping power is defined as the linear energy transfer, LET, and is given by 1 dE LET = –—
(22)
pdx
dE where p is the density of the material and — is the rate of energy loss in the material. LET has h the units MeV-cm2/mg. The integral of LET over path length gives the total deposited energy. Figure 62 [2] is a plot of stopping power (LET) for 2.5-MeV helium ions as a function of depth in silicon. The point of maximum stopping power is called the Bragg peak. The LET for a given ion depends on the target material and energy. Experimental and theoreticzd values of stopping power for most ions in several materials have been published by Northcliffe and Schilling [209] and Ziegler [210]. Stopping powers can be calculated for silicon, germanium, GaAs, and many compounds using the TRIM code [211 ] on most IBM compatible personal computers [2]. In addition to heavy ions, high-energy protons can deposit sufficient energy to cause a single-event upset. However, protons cannot directly cause single-event upsets in most presentday GaAs or silicon circuits. For instance, for proton energies from 50 to 200 MeV, the linearenergy transfer (LET) for protons in GaAs varies from -3x 10-s to 8X10-S MeV-cm2/mg and is below that necessary to cause single-event upset. (For digital GaAs enhancementidepletion mode MESFET circuits, typical LET thresholds are -0.5 to 2 MeV-cm2/mg.) However, protons can induce upsets by dislodging atoms from their lattice sites or through nuclear interactions with lattice atoms. Because the resulting secondary particles (e.g., alpha particles or displaced atoms)
11-81
1.8
1
1
1
1
I
1
1
1
1
I
I
1
1
I
1.6
BRAGGPEAK
1.4 1.2
1.0 0.8 1W -1
0.6 0.4 0.2
1
0.0 0
10
5
15
DEPTH (pm) Figure
62:
Stopping power (LET) versus depth for a 2.5-MeV helium ion in silicon.
(After Ref. 2) have higher stopping powers, i.e., LET, the secondary particles can cause sufficient ionization to induce single-event upsets. For single-event effects, an important parameter is the charge deposited in the material. The total deposited charge in a particle track, Q1,can be calculated from [2 12]
Q,=
1,6x10-2. LET, p E,
(23)
‘
where ~ is the electron-hole pair ionization energy (minimum energy required to create an electron-hole pair) given in units of eV (see Table I), LET is in units of MeV-cm2/mg, p is in units of g/cm3, and Q1 is given in the units of pC/pm, For silicon, E.h = 3.6 eV and for GaAs, E.h = 4.8 eV. Thus, for an LET of 50-MeV-cmz/mg, the charge deposited is approximately 0.5 pC/pm and 0.89 pC/~m in silicon and GaAs, respectively. If electrodes electrodes in Fig. 63
the ion passes through a p-n junction, immediately after charge is collected at the by drift of carriers from within the depletion region. The drift of carriers to the occurs within hundreds of picosecond after a heavy-ion strike. This is depicted as QD [2].
II-82
PROMPT (QD + Q~) ICR
DRH FUNNELING
I o
0.2
aDF) 0.4
“1
10
100
-
TIME (ns)
DIFFUSION
Figure 63: Schematic dia~am and time dependence for charge collection by drift, funneling,
and diffusion. (After Ref. 2)
Diffusion of carriers to the edge of the junction depletion or funnel region contributes a component to the collected charge. The diffusion of carriers takes much longer (up to hundreds of nanoseconds to microseconds) than the drift component. The diffusion of carriers is notes as QDFin Figure 63. another
The amount of charge that is collected by drift of carriers within the depletion region can be greatly enhanced by “field funneling.” Funneling was fmt proposed by Hsieh, et al. [213,214], in 1981. The density of the electron-hole plasma (1018 to 1021cm-3) created by the ion strike is considerably greater than the doping concentration of typical p-n junctions [215]. The high concentrations of electron and holes in the plasma will distort the original depletion region of the junction into a cylinder which follows the path of the ion [2,213-216]. As a consequence, the junction field region creates a “funnel region” that extends down into the substrate as depicted in Fig. 63 [2,17,213-216]. The electric fields within the funnel region will cause carriers to be collected rapidly by drift to the electrodes, The funnel will exist as long as the concentration of electron-hole pairs in the plasma created by the ion strike is large compared to the doping concentration of the substrate. The temporal peak of collected current from the drift of carriers by field funneling corresponds roughly to the dielectric relaxation time [216]. The dielectric relaxation time, ~D,is the characteristic time it takes for a solid to respond to charge imbalance [217], It is given by ~D = E/o, where e is the permittivity and o is the conductivity of the material. For silicon substrates with a doping concentration of 1015cm-3, ~Dis approximately 14 ps, and the potential spreading of the funnel reaches a maximum in approximately 25 ps [216]. For silicon devices, the amount of charge that is collected by drift is greatly enhanced by the funnel region, increasing the sensitivity of silicon ICS to single event upset. The time, G, that it takes for charge to be collected at a node from within the funnel region can be estimated from [215,218]
II-83
(24)
where NOis the plasma line density at the surface [215], NA is the doping concentration, VPis the effective charge separation (hole escape) velocity, and D is the ambipolar diffusion constant. The “fI-factor” can be estimated from
(25)
where <...> denotes an appropriate time average over the drift collection times [215]. Equations (24 and 25) are valid for most particles, but break down for ve~ highly ionizing particles [218]. Based on experimental data, the collection time increases with ionization density. As the collection time increases, the funnel time will collapse before all charge is collected and diffusion of carriers will occur. At this point, carriers can diffuse to adjacent nodes of a circuit causing multiple bit upsets [218]. For GaAs devices built on a semi-insulating substrate, the dielectric relaxation time is long (-100 W) and the recombination time is very short (1-10 ns). Thus, many of the carriers will recombine or be collected by other processes long before funneling is established [217]. Therefore, funneling is relatively unimportant for GaAs devices fabricated on semi-insulating substrates. For GaAs devices built on serniconducting substrates, the effects of funneling are comparable to those for silicon devices [219]. The reduced importance of funneling for GaAs devices fabricated on a semi-insulating substrate does not necessarily imply that GaAs devices are more immune to single-event upset than equivalent silicon devices. In addition to the collection mechanisms discussed above, other collection mechanisms contribute to charge collection in GaAs devices. In some cases, these collection mechanisms result in more charge (up to 8 times) being collected than is deposited by the incident particle [220-225]. Several “enhanced” collection mechanisms have been proposed for GaAs and/or silicon devices. These include 1) a back-channel turn-on mechanism [223,226228], 2) a bipolar source-drain, or bipolar gain mechanism [220-222,224,225,228], and 3) an ion shunt mechanism [229-23 1], Significant enhancement of the collected charge can result from the bipolar source-drain or bipolar gain mechanism. Under normal bias conditions for a depletion- or enhancement-mode MESFET, immediately after a heavy ion strike electrons will be collected at the drain and holes will be collected at the gate as is illustrated in Fig. 64. This is the drift component of charge collection discussed above. As the electric field of the depletion region changes in response to the column of charge created by the heavy ion, holes will also begin to drift toward the source. As the holes approach the source, they will lower the potential barrier at the source. The lowering of the source potential barrier will turn on the transistor causing enhanced electron flow
IT84
Source
Drain
Gate
+
+–
Ih \
n+-GaAs
n-GaAs
1=
+ -/
— +
n+-GaAs
+
+ + +
Semi-Insulating GaAs Substrate
+ +
l—
I
Ion Strike
Figure 64: Cross-section of a GaAs MESFET fabricated in a semi-insulating substrate illustrating charge collection mechanisms. from the source to the drain of the transistor. This effect is referred to as the bipolar source-drain or bipolar gain effect. A large fraction of the electron flow occurs through the bulk of the substrate beneath the implanted n-type channel layer [220]. Electron flow through the bulk of the substrate will continue as long as the concentration of free carriers is more than or comparable to the built-in space charge in the channel-substrate junction [220]. The number of electrons emitted by lowering of the source potential can be significant. The total charge collected at the drdin can be as much as 30 times that of the total charge collected at the gate [220]. Figure 65 [232] is a plot of the collected current at the drain, gate, and source for a 1.O-~ enhancementmode GaAs MESFET illuminated with a 1-ps laser pulse positioned between the drain and gate. The transistor was biased in the “OFF’ state with VGs = O V and VDs = 1.0 V . The charge collected at the gate peaks at approximately 50 ps after the laser pulse. Similar results were obtained for a high-energy helium strike [232]. This peak corresponds to the time it takes for holes to drift from within the depletion region to the gate electrode. The charge collected at the drain is composed of two signals. The first signal is due to the drift of electrons to the drain. This signal is similar to the gate signal which peaks in approximately 50 ps. The second signal is
II-85
1.0
1z w a a = o ~ ~ d
a E g
-
E-MESFET LASER v~~=l .Ov v~~=o.ov
AL 0.8 -
0.6 0.4
0.2 -
0.0 0
200
400
600
800
TIME (PS) Figure 65: Current collected at the drain, gate, and source of a GaAs MESFET after a 1-ps laser pulse. (After Ref. 232)
much wider than the first signal and peaks at approximately 200 ps. The second signal is probably due to lowering of the source potential resulting a large flow of electrons from the source to drain. The charge collected at the source shows only one peak, qualitatively similar to the second drain peak, which peaks at approximately 200 ps. The source signal also results from the lowering of the source potential. Note that the total collected charge at the drain (the integral of the collected current curve) is greatly enhanced by the bipolar gain effect. This effect can greatly increase the number of soft errors for GAs parts in a space environment. Another mechartism that has been suggested to result in enhanced charge collection is the ion shunt mechanism [229-23 1]. This mechanism is applicable to both silicon and GaAs devices with multiple p-n structures (e.g., silicon bipolar and CMOS transistors and GaAs heterostructure bipolar transistors). The ion-shunt mechanism is illustrated in Fig. 66 [230]. As depicted in Fig. 66, a heavy-ion passes through an n+-p-n-n+ junction and deposits charge along the ion track. The high density of charge created by the ion is initially considerably larger than the background concentration of the n and p layers. The charge deposited by the ion effectively shorts together the bottom and top n+ layers. If a potential field exists between the electrodes, charge will flow between the n+ layers and a single-event upset can result. Note that, for this mechanism to occur, the ion track must penettate both n+ regions. The amount of charge collected by the ion shunt mechanism will increase with the LET of the incident ion [231], and in some cases can be more than that deposited by the ion [231], The effect of the ion-shunt mechanism on the single-event upset sensitivity will depend on the device structure and operating conditions. In a memory circuit, a node will change state if the deposited charge is more than the “critical” charge. The critical charge is defined as the minimum charge necessmy to upset a
II-86
———
———
———
—— –+–––––––
n
+-
/
-
n+
-
Figure 66:
Schematic diagram of a heavy ion penetrating an n+-p-n-n+junction. hatched regions correspond to the n-p junction depletion regions. (After Ref. 230)
The cross-
memo~ bit [2]. For a DRAM this is the difference between the amount of charge stored on the node and the minimum charge that the sense amplifiers require to reliably read the stored data. The critical charge is highly device and circuit dependent. It can be as low as 50 fC [233]. This is equivalent to 3x105 electrons. 6.2
Hard Errors
In addition to soft errors that can be recovered by reprogramrning, in some cases heavy ions can cause permanent darnage to the transistor [234-244]. This type of error is often referred to as a “hard” error. Two types of hard errors discussed here are single-event burnout (SEB) and single-event gate rupture (SEGR). 6.2.1
Single-Event Burnout
Single-event “burnout can cause permanent darnage to bipolar power transistors and to power MOSFETS [237-244]. A cross-section of a power MOSFET is shown in Fig. 67 [243]. Note that the structure of a power MOSFET is much different than for a standard MOSFET. The
II-87
I
source-body contact
ion track \ ////y/////
n+ Y
p+-plug
nT-
‘source \
+
body
+
emitter
+ +
‘ base
+
+ .
‘+
collector
+ drain ----
----
----
+
----
----
n epi ----
----
n+ substrate drain contact
1
\
I
A+vD~
I
1
Figure 67: Cross-section of a power MOSFET. (After Ref. 243)
substrate of a power MOSFET acts as the drain. The channel (body) and source regions are formed by a double diffusion. Inherent to this process is a bipolar npn transistor (for the nchannel power MOSFET of Fig. 67) with the drain acting as the collector, the channel region as the base, and the source as the emitter. For normal operation a positive bias on the gate allows electrons to flow from the source to drain near the surface. The bipolar j unction is always biased in the “OFF” mode during normal operation by shorting the source to the channel at the surface of the device. If a heavy ion strikes the parasitic transistor, as shown in Fig. 67, the charge deposited by the ion strike will cause current to flow in the base region and it will raise the local potential of the emitter-base junction. If the current flow is high enough, it can forward bias the At this point the parasitic transistor turns “ON”. After the parasitic emitter-base junction. bipolar transistor is turned “ON”, second breakdown of the bipolar junction transistor can occur. This second breakdown has been referred to as current-induced avalanche [242]. In addition to increased electron injection from the emitter to the base, the avalanche breakdown will also cause holes to flow from the collector to the base. Depending on the current density during currentinduced avalanche (and the current supply of the external circuit), the current induced in the parasitic transistor by the heavy ion will either dissipate with no device degradation or will regeneratively increase until (in absence of current limiting elements) the device is destroyed [2,243].
II-88
1000 BURNOUT, DEVICE DESTROYED
100 10 ‘~
a g
I
1
i f
-[
~
PROMPT PHOTOCURRENT BURNOUT NOT INITIATED I
0.001
10-9
NOT DESTROYED
i
0.1 0.01
BURNOUT INITIATED BUT DEVICE
, ~8
I
I
I
10-7
10=
10-5
, ()-4
TIME (S) Figure 68: Increase in drain-to-source current in apower MOSFET during varying degrees of
single-event burnout. (AfterRef. 238) Experimental results [238] have shown that there is a threshold for the drain-to-source voltage, VDs, in order for SEB to occur. This threshold has been referred to as the failurethreshold voltage (VFti). If VDs is below the failure-threshold voltage, the heavy-ion strike causes a small prompt photocurrent lasting for approximately 5 ns as depicted in Fig. 68 [238]. Observation of the prompt signal is normally an indication that VDs is close to the failurethreshold voltage. As VD,Sexceeds VF(h burnout can occur, and the drain-to-source current increases dramatically. If the current is below a critical value, burnout will not destroy the device as indicated in Fig. 68. However, if the current is sufficiently high, SEB will destroy the device. The voltage level at which a device is destroyed is highly device dependent and can vary from 22 to 90% of the rated breakdown voltage for an n-channel transistor [238]. Breakdown voltages for a power MOSEFT can vary widely, from less than 80 V to more than 500 V. Thus, the range of VDs required to initiate burnout can vaty from less than 20 V to hundreds of volts. The closer VDs is to V~,~, the lower the current density is in order to initiate burnout [238].
II-89
The failure-threshold voltage has also been found to depend on the LET of the incident ion [238]. As the ion LET is increased, it generates higher current densities along its path. A lower voltage is required to sustain current-avalanche breakdown as the current density is increased [242]. Thus, the failure-threshold voltage decreases as LET increases, consistent with experimental results [238]. Increasing temperature has been found [243] to decrease the susceptibility of power MOSFETS to SEB by lowering the avalanche multiplication factor. Several methods for reducing or eliminating include 1) using pnp transistors to utilize the lower graded junctions to increase the length of the silicon and 3) using current limiting (inductance, resistance, current, high-voltage condition. 6,2.2
SEB have been proposed [237]. These ionization coefficients of holes, 2) using region over which the voltage is dropped, or both) to prevent the simultaneous high-
Single-Event Gate Rupture
A single-event gate rupture can occur as a single heavy ion passes through a gate oxide. SEGR occurs only at high oxide electric fields, such as those during a write or clear operation in a nonvolatile SRAM or E2PROM [2,234,235]. It was first observed [234,235] for metal nitride oxide semiconductor (MNOS) dielectrics used for memory applications. In later works, SEGR was observed in power MOSFETS [238] and MOS transistors [236]. SEGR is caused by the combination of the applied electric field and the energy deposited by the ion [236]. As an ion passes through a gate oxide it forms a highly conducting plasma path between the silicon substrate and the gate dielectric [2,235,236]. With an electric field across the oxide, charge will flow along the plasma path depositing energy in the oxide. If the energy is high enough, it can cause localized heating of the dielectric and potentially a thermal runaway condition. If thermal runaway occurs, the local temperatures along the plasma will be high enough to cause thermal diffusion of the gate material, cause the dielectric to melt, and evaporate overlying conductive materials [2,236]. The resistance of the initial ion track is inversely proportional to the ion LET. If the LET is increased, resistance is lowered and the required voltage across the device to sustain conduction is reduced [236]. In Fig. 69 [236] the failure threshold, Vm, versus LET is shown for 45 nm Si02 oxides (bottom curve) and composite oxides composed of 2.2 nm Si02 oxide and 35 nm of SiqN4 dielectric (top curve). Note that for both the composite and Si02 dielectrics the failure threshold increases linearly with the inverse of LET. For thermal SiOz oxides with the incident ion normal to the surface, the critical electric field, EC,, for SEGR is given by [236,238,245]
EC, =
41 (LET)”2
X106 V/cm.
(26)
For a 180 MeV Ge ion with an LET of 36.8 MeV-cm2/mg, this gives a critical electric field of approximately 6.7 MV/cm. Typical intrinsic breakdown electric field strengths for a thermal gate oxide are in the range of 10 MV/cm [245]. Thus, the critical electric field for SEGR is roughly 67% of the intrinsic breakdown electric field strength under these conditions.
11-90
70
LET [MeV/(mg/cm2)] 100 50 33
25
20
60 50 40 t >
30 20
10 0 0.00 Figure 69: Failure (After Ref. 236)
0.01
0.02 - 0.03 0.04 l/LET [MeV/(mg/cm2)]-l
threshold
for single-event
gate rupture
0.05
versus heavy-ion
LET.
In addition to depending on the oxide electric field and LET, the failure threshold also depends on the incident angle of the ion strike. In Fig. 70 [236] the angular dependence of failure threshold is shown. The failure threshold is noted to increase linearly with l/cos9 where e is the incident angle. As the incident angle increases, the path length between the silicon substrate and gate material increases, increasing the effective resistance along the ion track. This has been proposed as the cause of the angular dependence [236]. For a memory transistor, the probability of a SEGR will depend on the time that the device is in a write, clear, or other high-electric field mode of operation. For a number of nonvolatile memory applications this may be only a small percentage of the total operation time. Clearly the probability of a SEGR is highly dependent on the system application. 7.0 SUMMARY We have covered the basic mechanisms of radiation effects in the natural space The natural space environment can cause significant darnage to spacecraft environment.
1191
e (DEGREES) O 3036
47
53
60
66
25
~
10
t > 15
.
A MEASURED
DATA
180 MeV Ge IONS
10 1.0
1.5
2.0 Ilcose
2.5
3.0
Figure 70: Failure threshold for single-event gate rupture versus heavy-ion incident angle (After
Ref. 236) electronics. It can cause degradation through total-dose ionizing radiation damage, single-event related soft and hard errors, and displacement damage. Of these three, total-dose and singleAlthough we have focused on the natural space radiation event effects were discussed. environment, the information learned for the most part is applicable to high, moderate, and lowdose-rate applications. Particles present in the space environment vary widely with altitude and angle of inclination. They can be grouped into two general categories: 1) particles trapped by the earth’s magnetic field (primarily electrons and protons) and 2) cosmic rays: heavy ions and high-energy protons of galactic or solar origin. The earth’s magnetic field lines form domains or bands of electrons and protons around the earth. Trapped electrons are present predominantly from 1 to 12 earth radii, while trapped protons are present predominantly from 1 to 3.8 earth radii. The galactic cosmic ray spectrum consists mostly of protons (85%) and alpha particles (14%). Less than 1% of the galactic cosmic ray spectrum is composed of heavy ions. In most solar flares, the majority of particles are energetic protons. The number of heavy ions in a solar flare is normally insignificant compared to the background concentration of heavy ions from the galactic cosmic
II-92
ray spectrum. The total dose that a device can be exposed to in one year can vary from less than 1 krad(Si) for some low-earth orbits up to 1 Mrad(Si) for other orbits. Particles present in the space environment can ionize atoms in a material creating electron-hole pairs. For energetic particles present in the space environment, each incident particle can create thousands or even millions of electron-hole pairs. The generated carriers can lead to device degradation. For an irradiated MOS transistor, electrons created in the oxide will rapidly leave the oxide in picosecond. However, even before the electrons leave the oxide some fmction of the The fraction of electron-hole pairs that escape electrons will recombine with holes. recombination is the electron-hole yield. The time for hole transport via polaron hopping is much slower than it is for electrons and depends on temperature, bias, and oxide thickness. At room temperature, hole transport takes on the order of microseconds for a gate oxide. With a positively applied gate bias, holes will transport toward the Si/Si02 interface, where some fraction of the holes will be trapped at defects near the Si/Si02 interface forming a positive oxide-trap charge. Immediately after oxide-trap charge is formed, it begins to be neutralized by electrons tunneling from the silicon or by the thermal emission of electrons from the oxide valance band. The neutralization of oxide-trap charge can be both bias and temperature dependent. Large concentrations of oxide-trap charge can cause increased static supply leakage current in an IC. Thus, for irradiation conditions and for technologies where oxide-trap charge dominates IC radiation response, the primary failure mechanism tends to be increases in leakage current. As holes “hop” through the oxide or as they are trapped near the Si/Si02 interface hydrogen ions are likely released. These hydrogen ions can drift to the Si/Si02 interface where they may react to form interface traps. Interface-trap buildup can take thousands of seconds to saturate. The buildup of interface traps is temperature, bias, and time dependent. However, there does not appear to be a “true” dose rate dependence for the buildup of interface traps. Unlike oxide charge, interface traps do not anneal at room temperature. At threshold, interface traps are predominantly positively charged for p-channel transistors and negatively charged for n-channel transistors. Thus, interface-charge charge tends to compensate oxide-trap charge for n-channel transistors and add together for p-channel transistors. Large concentrations of interface-trap charge can decrease the mobility of carriers and increase the threshold voltage of n-channel transistors. These effects tend to decrease the drive of transistors, degrading timing parameters of anIC. Due to cost and performance requirements, commercial devices are seeing increased use in space systems. Commercial technologies have been fabricated where significant oxide-trap charge neutralization occurs and also where little or no oxide-trap charge neutralization occurs. Thus, in a space environment, the radiation response of some commercial technologies may be dominated by interface-trap charge and for other technologies the radiation response may be dominated by oxide-trap charge. As the IC industry tends towards ultra-thin gate oxides, even commercial gate oxides can be fabricated that are radiation hardened. In both high- and lowdose-rate environments, commercial IC radiation response may be dominated by field oxide
II-93
induced leakage current. Even at relatively low dose levels, -10 krad(Si), field oxides can cause IC failure for some commercial technologies. An additional concern for advanced technologies (commercial and radiation hardened) are process-induced effects caused by the special tools required for defining small geometries, Although most of the damage can be annealed out by a moderate temperature metal sinter step, in some cases higher temperatures are required to prevent increased radiation-induced degradation. Two technologies that may see increased use in the future are silicon-on-insulator (S01) and nitrided oxide dielectrics. SOI transistors are built on an insulating layer reducing the amount of p-n junction area. The reduced junction area leads to lower parasitic capacitance for faster operation, and to a reduction in the generation volume leading to a considerable reduction in the sensitivity of SOI ICS to single-event upset and other transient effects. The absence of a conducting path underneath the MOS transistor completely eliminates parasitic pnpn paths that can cause Iatchup. The major difference between the radiation response of MOS transistors fabricated on bulk silicon substrates and SOI transistors is due to the buried oxide of SOI transistors. Up to 100% of the holes generated by irradiation can be trapped in defects in the bulk of the buried oxide. The buildup of charge can invert the bottom surface of the silicon channel of a MOS/SOI transistor creating a back-channel leakage current, Deoxidized nitrided oxides (RNO) can be fabricated such that there is no measurable interface-trap buildup and with less oxide-trap charge buildup than comparable thermal oxides. The lack of interface-trap buildup for RNO transistors is likely due to the fact that hydrogen released in the dielectric cannot penetrate the nitrogen rich oxynitride layer present near the interface and create an interface trap. If a high-energy proton or ion strikes a circuit node it may create sufficient charge in a transistor to change the state of the node and cause false information to be stored. This type of failure is known as a single-event upset. (SEU). This is a non-destructive or soft error. A soft error can be corrected by reprogramming. The number of soft errors will depend on the amount of charge that is deposited in the material by the ion or proton. Charge is collected primarily through three mechanisms: 1) drift of carriers within the depletion region of a p-n junction, 2) field funneling, and 3) diffusion. The drift of carriers normally occurs within hundreds of picosecond after a heavy ion strike. The high density of electron-hole pairs generated by the ion can distort the depletion region of a p-n junction creating a “funnel region” that extends down into the substrate. For silicon transistors, field funneling can significantly increase the charge collected by drift of carriers. For GaAs transistors fabricated on a semi-insulating substrate, field funneling is not an important contributor to charge collection. Another class of single-event effect that is not correctable by reprogramming is termed a hard error. Hard errors include single-event burnout (SEB), single-event gate rupture (SEGR), latchup, and snapback. In this portion of the Short Course, only SEB and SEGR were covered. SEB can cause permanent damage to a bipolar power transistor and to a power MOSFET. For a power MOSFET, SEB is caused by large current flows induced by a heavy ion turning “ON’ a ‘----’”transistor inherent to the power MOSFET structure, As long the drain-to-source Ul~Ultll ~~tilll~ “--’-bias is above a threshold value, SEB can be initiated. SEGR occurs as a heavy ion passes
II-94
through a gate oxide. It has been observed in metal nitride oxide semiconductor dielectrics used for memories, in power MOSFETS, and in thermal gate oxides. It is caused by the combination of an applied electric field and the energy deposited by an ion. The critical electric field for SEGR varies inversely with the square of the LET of the incident ion. It is hoped that the student has gained an appreciation of the need for basic mechanisms studies. Without the knowledge gained by these studies, we would not be in the position to develop hardened technologies and to develop cost-effective, reliable hardness assurance test guidelines, Acknowledgments The author is greatly indebted to numerous discussions and suggestions from his colleagues at Sandia National Laboratories and especially Dan Fleetwood, Marty Shaneyfelt, Bill Wamen, Peter Winokur, Fred Sexton, and Gerald Hash. I also wish a special thanks to Peter Winokur for his support during the course of writing this manuscript.
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1994 NSREC SHORT COURSE
SECTION III
RADIATION CONCERNS INSTATE-OF-THE-ART PROCESSING TECHNOLOGIES
MICHmL DELAUS AWLZOG DEVICES
Radiation
Concerns in State-of-the Art Processing Technologies Michael DeLaus Analog Devices Wilmington, MA
OUTLINE 1. Introduction 2. CMOS Technology 2.1 Technology trends 2.2 Device enhancements 2.2.1 Source/drain engineering 2.2.2 Gate dielectrics 2.3 SOI 3. CMOS Radiation Sensitivities 3.1 SEU 3.2 Total-dose effects 4. Bipolar Technology 4.1 Current technology 4.2 SiGe HBT devices 4.3 Trends in bipolar devices 4.4 SOI 5. Bipolar Sensitivities 5.1 Displacement damage 5.2 Ionizing radiation 5.3 SEE 5.4 BiCMOS technology 6. Device Fabrication 6.1 Ionizing radiation in processing 6.2 Commercial manufacturing 7. Summary
1. INTRODUCTION As seen in Fig. III-1, military IC sales as a percentage of total are now projected to account for less then 270 of all IC saIes in situation from the 1960’s, when military ICS were a significant grams are disappearing (some do no reappear), and budgets are
IC sales have fallen steadily, and 1995. This is a radically different portion of total ICS. Military proshrinking.
120
16%
100 80
Mdilary as a % of bid market
\
60 40 20 I
o
$0.7
1975
I
1985
1W5*
●pro@ions
Fig. III- 1 Microcircuit sales worldwide ($ in billions) [1]. All of this is placing extreme economic pressure on the manufacturers of radiation-hardened parts. There has been a reduction in the number of rad-hard IC wafer fabs, and it is not clear how many vendors. the market can economically support, The growth of the commercial space market is helping to offset the decline in strategic military programs. To reduce costs, many programs are examining the viability of using non-hardened commercial ICS. labeled COTS (Commercial Off The Shelf). While caution must be observed, it would be extremely beneficial for milimry IC technologies to become more aligned with the commercial market technologies. In this way, the military and commercial space markets can capitalize on the huge investments being made in commercial IC technologies. The commercial semiconductor market is driven by the need for higher performance, lower power, and lower costifunction. Each new generation of devices delivers better performance at a lower cost per function. To accomplish this, new generations offer reduced feature sizes, higher levels of integration, and lower defect densities. These past trends are continuing at a staggering pace. Table 111-1 contains technology trends compiled by the Semiconductor Industry Association. Military IC technologies. while offering high levels of reliability and radiation tolerance, are usually a genemtion or more behind the commercial state-of-the-art technologies. This includes both circuit design and process technology. The use of commercial ICS in military and space systems would provide access to the lates[ advancements in commercial technologies, but must be tempered by the unique requirements for rtidia[ion hardness and high reliability.
111-2
SELECTION
PARAMETER Bits/Chip - DRAM - SRAM Chip Area - DRAM - Logic/MProcessor Cell Area - DRAM - SRAM
❑ U
OF TRENDS FROM SEMICONDUCTOR ASSOCIATION REPORT UNITS
INDUSTRY
1992
1995
1998
2001
2004
2007
16M 4M
64M 16M
256M 64fvf
lG 256M
4G lG
16G 4G
132 250
200 400
320 600
500 800
700 1000
1000 1250
4 18
1.5 8
0.5 5
0.15 3.5
TBD TBD
TBD TBD
0.12 TBD 1.035-0.050 37 x 37 1369 TBD
0.1 TBD TBD TBD TBD TBD
don-optical
TBD
4.5 25
4 10
(mm)’
(pm)’
Exposure
(rim)
0.5 0.33 0.15 20 x 20 400
[email protected] 365
Gate Dielectric Junction Depth Interconnect Levels - DRAM - Logic/MProcessor
(rim) (rim)
12 150
9 100
7 60
2 3or4
2-3 4or5
5or6
5or6
3 6or7
3 6or7
200
200
200-400
200-400
200-400
200-400
Resolution (Design Rule) SFQD Overlay Field Size Field Size Defect Density
Wafer Diameter
(pm) (pm) (pm) (mm) (mm)z layer-cmz)’
(mm)
0.35 0.23 0.10-0.12 22 x 22 484
0.18 0.12 ).050-0.070 32 X 32 729 1024 1.oo5@o,07 ).oo3@o,05 ).0021@0,03 365wIPS & 248wlp$j & 248 wips & 3ffset Illum 3ffset Illum Offset Illum 248 193 193 w/Ps 0.25 0.17 ).075-0.090 27 X 27
2-3
Compiled from SIA March 1993 Reporl
~dble III-1 Technology trends 12].
:0 3
As commercial IC technologies continue to advance, we find that some radiation sensitivities disappear while new ones are created. Some technology trends favor increased radiation tolerance, while others work to degrade the radiation hardness. In this part of the short course, these trends will be discussed. The current state-of-the-art in CMOS and bipolar technologies will be reviewed. In discussing the future trends of these technologies, areas of potential radiation hardness concerns will be highlighted. In addition to the processing technologies, it is also important to examine the manufacturing techniques and practices used for fabricating commercial ICS. If these parts are to be used in military and space systems, it is essential that the manufacturing process support the hardness assurance and reliability levels that these systems require.
2. CMOS technology 2.1 Technology Tiends The 1980s saw the emergence of CMOS as the dominant IC technology. This is true in both the commercial and military markets. Due to it’s market dominance, CMOS has become the process technology driver for the semiconductor industry. According to Moore’s Law [3], a new CMOS generation appears every 3 years, with a 4X increase in density and a 1.5X increase in performance. While this trend has held up throughout the 1980s and 1990s, there are some signs that it is beginning to saturate. One reason for the saturation is economics. The largest IC manufacturers routinely talk about building $1 billion wafer fabs. Most of this amount goes into the capital equipment as opposed to the facilities. Another reason for the slow down is the uncertainty of the technology as devices approach 0.1 ym, Most of the process development R&D dollars go into the areas of lithography, etching, and developing new structures. Due to their huge volume, DRAMs are, and will continue to be, the process technology investment driver, Logic devices (gate arrays and microprocessors) generally lag 2-3 years behind memory devices on the technology curve as seen in Fig. III-2. Recently, the processes used for memory and logic devices have diverged, due to the specific requirements of each class of devices. In CMOS development, the trade-off is between performance and reliability. Process designers try to balance the competing requirements for high performance and sufficient reliability. Subsequent CMOS generations improve device performance by maximizing transconductance, reducing series resistance and parasitic capacitance, and minimizing off-state leakage. At the same time, adequate device breakdown must be maintained and sufficient device lifetime achieved. Table III2 shows that the gate oxide thickness has been reduced in proportion to the supply voltage, thus maintaining the E-field across the gate oxide. In general, new CMOS generations achieve increased performance
111-4
through device scaling, thin-
ner gate oxides, shallower junctions, and smaller feature sizes, Structural changes, which add to the complexity of the process, also contribute to the enhanced perfonrxmce. Table III-3 shows the evolution of CMOS processes as measured by the number of mask layers, films, metal levels, and process steps.
.
Mslllory
O @k 1
1975
Iw
I
1925
I*
190s
Yam
Fig. III-2 Historical trends of minimum dimensions of LSIS in memory and logic [4].
Supply Voltage (V)
10.0
5.0
3.3
2.5
Gate Thickness (~)
350
200
120
90
E-field (MV/cm)
2.9
2.5
2.8
2.8
Table III-2 Gate oxide E-fields.
2.2 Device Enhancements CMOS device enhancements are structural changes that contribute to improved device performance. These enhancements fall into two major categories, those relating to the sourcekirain regions and those relating to the gate dielectrics. There is considerable ongoing R&D in both of these areas, and both will be discussed in detail. 2.2.1 Source/Drain Engineering The most significant change to the source/drain suucture was the induction of tie LDD (Lightly Doped Drain) structure in the early 1980s. This change was driven primarily by the need to reduce the E-field at the drain junction to reduce hot-earner induced device degradation. LDD structures are used almost universally in processes with channel lengths c 2.0 ~m.
HI -5
There are a variety of LDD structures in use today, Most employ a permanent or a disposable spacer to offset the heavily doped drain region away horn the device channel. Figure III-3 is a cross-section of a typical LDD structure that contains a permanent silicon-nitride spacer, This effectively reduces the E-field in this area, and reduces the amount of hot-camier injection [6]. Spacers are formed from oxide or oxide/nitride layers, At this time, LDD structures do not present a significant hardening liability.
#
Design Rules
# Masks
# Films
Metal Levels
# Steps
2 pm
9
10
1
-’150
1 ~m
12
15
2
-200
0.5 ~m
16
19
3
-250
0.25 pm
18
22
4
-300
hble
III-3 Evolution of CMOS process technology [5].
Polysilicon Gate +
Si3N4
&
Fig, III-3 Conventional
LDD structure.
A number of advanced LDD structures have been proposed for future CMOS technologies. Crosssections of these devices are shown in Fig. III-4. The structures are the gate overlapped LDD, the shallow source/drain extension LDD, and the elevated source/drain. Advanced structures such as these will be required as gate lengths and feature sizes continue to shrink. These structural
III -6
changes should not impact the hardness of future MOS devices.
Gate-Overlapped
Shallow
LDD Narrow
S/D Extension
Spacer
e Elevated
Source/Drain
Fig. III-4 Advanced CMOS device structures [7]. 2.2.2 Gate Dielectrics Perhaps the most significant impact on the radiation hardness of future CMOS processes will stem from the choice of gate dielectric. It is likely, that in the near future, processes will appear that do not employ the conventional thermal oxide gate dielectric. Today’s gate oxides are grown in furnaces in a wet or dry oxygen ambient, or by means of RTP (Rapid Thermal Processing) which provides improved thickness control for thin oxides. Alternate gate dielectrics are being developed to provide improved immunity to hot-carriers and reduced defect densities. Stacked dielecrncs are one option being investigated [8]. Other alternatives include Nitrided Oxides (NO) and Deoxidized Nitrided Oxides (RNO). RNO gate dielectrics are attractive because they provide improved gate oxide reliability, reduced hot-carrier degradation, and resistance to boron penetration from P+ polysilicon [9]-[ 11], This latter attribute is becoming increasingly important as processes move to boron doped polysilicon for the PMOS gate electrode, The benefits of RNO for radiation hardness include suppression of interface state generation and reduction in threshold voltage shifts and gm degradation [12]. Two popular methods for creating nitrided oxides include a RTA cycle in a NH3 ambient or a furnace anneal in a N20 ambient. The trend of thinner gate dielectrics has improved the radiation tolerance of modem MOSFET devices. The benefit of thinner oxides is clearly demonstrated in Fig. III-5, which shows the relationship between gate oxide thickness and flat-band voltage shift. Gate oxides below 20 nm deviate from the AVm - ~x2 relationship, relationship predicts.
thus providing
more hardness improvement
than this
In the area of CMOS device isolation, the LOCOS (LOCal Oxidation of Silicon) process, and its
III -7
variants, remain the dominant form of isolation for sub-micron processes. The basic LOCOS process has been modified to reduce bird’s beak encroachment to increase packing densities. Shallow trenches are also used for device isolation [14]. Field leakage and MOSFET sidewall leakage are generally the predominant total-dose failure mechanism for today’s commercial CMOS circuits.
10’
T= M*K q), = +2.0Mvla Piss-owm ?aV-sl
/
Alum EATE
1o”’ t
& o
Fig. HI-5 Delta VFB vs. gate oxide thickness [13].
Figures III-6 and III-7 present data on the total-dose response of commercial, non-hardened gate and field oxides, respectively. In Fig. IH-6(a), extreme edge leakage is observed in addition to the threshold voltage shift for the NMOS device that was tested. The parasitic sidewall FET appears to turn-on at a dose of approximately 5 Krad(Si). In Fig. III-6(b), an enclosed or edgeless device has been measured. Here the sidewall leakage is eliminated and the total-dose response of the gate oxide is observed. The shift in the threshold voltage is approximately -0.8V at a dose of 25 Krad(Si). At Vg~ = OV, leakage > 100pA is noted at doses> 6 Krad(Si). The total-dose response of a P-field MOSFET device from the same commercial technology is shown in Fig. III-7. The pre-rad field threshold, which is >20 volts, quickly degrades. Field inversion, measured at Vg~ = OV, occurs at a dose of 3 Krad(Si). 2.3 SOI SOI (Silicon-On-Insulator) technology is presently used for niche markets such as radiation-hardened and high-temperature applications. [n recent years, SOI technology has been studied as a way to enhance CMOS technology, particularly as geomernes reach deep sub-micron levels. The radiation effects community has long recognized the benefits of CMOS/SOI technology, These benefits include reduced sensitivity to SEE (Single Event Effects) and improved circuit pefiormance in high dose-rate environments. Should SOI technology be adopted by the mainstream commercial CMOS markets, it would prove extremely beneficial to designers of military and space systems.
111-8
1.
-
1.-si6-
I
1.-0810s
~’ PRE
(A)
1.6
1e-#7-
3.0
--
1e-03-
l*-esl-
l?AD
Krad(Si) Krad
(S;)
4.5
Kr,
d(
6.0
Kr,
d(Si)
10.0
Krsd(si)
1S.0
Krad(Si)
20,0
Krmd(Si)
26.0
Kr.
S;)
J
d(Si)
t
-
I
1.-10+ -1.0
-0.8
-0,8
-4.4
-0.2
0.0
0,2
0.4
8.8
VGS STANDARD
Nkl OS
EXPOSURE
eI
(W/
As,
UEASURENENT
L=8/E.
l.e
1.2
1,6
1.4
1.3
2.6
(V)
)
VD=VS=VO=e.
BIAS,
%.8
VS=VB=O,
eV,
VG=+E.
.6V
.3V,
VD=@.
IV,
VG=-l.
OV
TO
2.@v
1.-02
T
1
I.-m,
I 1.-s74 1
I.-es
10s (A)
26.
OKr.
d(Si)
L
1.-06
PRE 1,6 3.
1.-67
d(Si)
4,
Sh.
.d(Si)
8.
OK.
.d(Si)
OK.
.d(Sij
10. 16,0 1.-0e
RAD
Krad(Si) OKr.
Krmd(Si)
20.
OKr.
26.
OKrad(Si)
d(Si)
!
1.-e9-
-
1.-163 -1.0
-0.8
-0.6
-2. .4
-0.2
0.0
0.2
0,4
0.8
VGs ENCLOSED
NMOS
EXP03URE
BIAs:
MEASUREMENT
(W/
BIAS,
L=48a
0.8
I.B
1.2
1.4
1.6
I
8
2.2,
(v)
/4]
VD=VS=VO=e,
eV,
VG=+5.
VSz
fiV,
VD=8,1V,
VB=SI.
t7V vG.
-1.
@v
Fig. 111-6Total-dose response of commercial dard layout, (b) enclosed (edgeless) layout.
To
Z.ev
NMOS transistor with 350 ~ gate oxide: (a) stan-
III -9
1 *-,1 Pt.
#
K..
I
d(sl)
I.-#?
1*-*3
1.-*4
1.-,
s
lDS (A) 1.
PRE
-*O
L K.md
Krmd($l)
4.6
Krmd(Sl)
0,0
I.-er
-#m
~
16,
G
2S.
I
1.-89
●
,.,.L-@-@i -A
-2
@
‘2
4
8
a
10
14
12
P-
FIELO
UOS
EXPOSUQE
TRAKSIETOR
EI AS: BIAs,
(w,
VDw VS=VB=n. VS.
VB-4.9V,
18
?@
#
Krnd
(31)
Kr.
d[Sl)
Mr.
d[Si)
Kr.
d(Sl)
RE ~AO 22
24
26
2B
,,
(v)
Vas
UEA.SU@EUENT
10
(S})
Krsd(.Si)
1,.
20,0
].
RkD
1.s
3.0
Lm&4 #,7] #V,
VC-+l
B.#V
VD-l.
#V,
VC--4.0V
TO
l#.
#V
Fig. 111-7Total-dose response of a commercial field oxide FET (field oxide= 6400 ~).
SIMOX (Separation by Implantation of Oxygen) is probably the most mature SOI technology for prtiucing CMOS circuits. The material is produced by the implantation of a high dose of oxygen ions into silicon. After a subsequent anneal step, an insulating layer of silicon dioxide is formed beneath the silicon device layer. The technique was developed by Izurni and co-workers in 1978 at NIT [15], Early SIMOX work focused on the materials issues, but much of the current work is centered on the device and modelling issues associated with producing CMOS circuits, Today, SIMOX substrates are available from commercial vendors In recent years, bonded-wafer SOI has also emerged as a potential CMOSJSOI substrate. Historically, this material was produced using mechanical grind and polish techniques and was only considered for applications requiring thicker (> 1.0 ~m) silicon films. Recently developed techniques employing chemical etch stop layers or plasma etch processes have produced material with the thin uniform silicon films required for CMOS/SOI applications [ 16]. The insertion of CMOS/SOI technology into commercial markets will be driven by cost and performance. Cost not only includes the price of the SOI substrate, but also other factors that impact the circuit die cost such as the cost of fabrication and the wafer yield. The use of SOI substrates can simplify the fabrication process, and by reducing the area of leakage sensitive junctions, actually improve the circuit yields, The smaller junction area translates to reduced parasitic capacitances, This results in improved performance. Circuit designers have seen a 20-3070 speed
111-10
improvement
for 256K SRAMS fabricated on SIMOX [17].
Before SOI technology is embraced by the commercial CMOS markets, it must be able to solve some of the technology barriers of deep sub-micron CMOS. Only then will SOI begin to replace bulk silicon. Many observers feel that SOI is likely to solve many of the problems encountered by sub 0.25 ~m CMOS. These problems include extreme short channel effects such as low device breakdown voltage. Figure III-8 demonstrates that higher breakdown voltages can be achieved for sub 0.25 ~m devices when they are built on SOI substrates.
ILK)
1-1Advamage
SO1
—
.
Ad, an(ageBulk
. .. ... , , -
,d-,~”
---
“j
.O
i
_
1 :
-
Fosol. exp FOSOI. stm.1 Bulk. CXP
~ -
Bulk. simul
1
1
10 Effecuve
gz!/e Iengh
[pm]
Fig. III-8 BVD~ vs. gate length for bulk and SOI devices [16].
One of the dominant focuses of future CMOS technology is on low power applications. SOI offers two advantages for these applications. As already mentioned, oxide isolation reduces parasitic capacitance which implies that circuits will consume less power for a given level of performance. The other advantage is that fully-depleted SOI MOS devices have a steeper subthreshold slope than bulk devices, This difference is seen in Fig. III-9. As power supplies continue to shrink (5.OV -> 3.3V -> 2.5V ->?), the steeper subthreshold slope of SOI devices will become extremely attractive. Threshold voltages can be set lower without compromising the off-state leakage current.
2 ~
-8 -
102 mV/dec
G
n m ~ .12
-15
-0.5
Fig. III-9 Subthreshold
0.0
characteristics
0.5 1.0 (V) Gate Voltage
1.5
2.0
of a bulk and a fully depleted SOI transistor [16].
111-11
Two major concerns with SOI devices are their low drain-source breakdown voltages and hot-carrier degradation. As shown in Fig. III-8, SOI devices have lower breakdown voltages at gate lengths > 0.3 ~m. Below this gate length, device punchthrough, which dominates for bulk devices, is more severe than the reduced breakdown caused by the parasitic lateral bipolm on the SOI devices. In fully depleted SOI devices, hot-carriers degrade the device parameters primarily through carrier injection into the buried oxide. There is no clear consensus on the sensitivity of SOI devices to hot-carrier effects, with researchers obtaining both positive and negative results when attempting to determine the robustness of SOI MOSFETS [18]. The demand for SOI wafers, primarily driven by the needs of commercial markets, is expected to increase dramatically y by the year 2000. This trend is shown in Fig. 111-10. It should be noted that the bonded wafer requirements includes the needs of IC and non-IC (for example, sensors) users. Serious interest in SIMOX from commercial memory manufacturers is beginning to materialize. At recent conferences, a number of IC vendors have discussed 64K DRAMs fabricated on SIMOX [19], [20]. Advantages of this implementation include a wider operating voltage range, longer storage times, and a reduced cell area.
WORLDWIDE SILICON-ON-INSULATOR (SOI) WAFER MARKET
w
*USI
+
200Tolal S0
I
150 I
lm -
eo-!acd
wafers
‘/J
S#4m
)
50-
0 19bo
1
19’s)1
I 1992
I 1993
I 1994
I 1995
I 1996
I 1997
I 1998
I 1999
I 2003
fwfa &YnEo
Wfefs K-ckne sdmn@@e4ian, camke m nwcnanf ccamm
SXILXF
~
~M
Fig. III- 10 Worldwide SOI wafer demand 1990-2000, actual and forecast.
3. CMOS Radiation
Sensitivities
Previously, the total-dose sensitivity of commercial CMOS processes has been discussed with regards to the response of the gate and field oxides. In this section, Single Event Effects (SEE) will be examined. SEE has been getting an increased amount of attention in the commercial sector, especially with respect to Single Event Upset (SEU). SEU is now a major concern for designers of commercial DRAM and SRAM circuits. The other SEE topic that will be discussed is the total-dose effects due to single ions. This effect is also know as Single Hard Errors (SHE). In
111-12
recent years, this phenomenon
has been observed in a number of commercial memory ICS.
3.1 SEU Interest in SEU began in the late seventies when May and Woods, among others, noted cz-particle induced soft errors in commercial DRAMs [21], [22]. These upsets were caused et-particles emitted by the radioactive decay of impurities in the chip packaging material. In the commercial sector, the SEU phenomenon is most commonly referred to as the Soft Error Rate (SER). Reducing the SER is now a critical design parameter in CMOS memory designs [23], [24]. Commercial IC makers are concerned about external (cosmic rays) and internal (metal lines, Pb/ Sn bumps, ceramic package materials) ion and et-particle sources. The cosmic rays that bombard the Earth produce high-energy neutrons at the Earth’s surface that can cause bit upsets. The et-particle sources are impurities and isotopes in the chip and packaging materials. Commercial IC designers have developed sophisticated simulation tools to model SER [25]. These tools take into account not only cosmic ray secondary particle environments, but also model upsets caused by the metal interconnect located adjacent to the sensitive cell volumes. An example of one such simulation is shown in Fig. III- 11. These simulations allow chip designers to optimize the circuit layout and device design to reduce error rates. 4
IL
C4
1E-01
1E-02
1E-02
lE-04
I
1E-05
lE.06 o
100
200
3C41
400
5&l
Varied Critical Charge
Fig. III- 11 Soft Error Rate predictions as a function of critical charge.
Radiationeffectsresearchershavefoundthat manyof today’scommercial,non-hardenedmemories are not suitable for space applications [26]. This conclusion is based on the high upset rates and Iatchup conditions that were observed. Multiple bit upsets can also be a severe problem for commercial parts, as single bit EDAC schemes may not be sufficient. Technology trends appear to have both positive and negative effects on the SEU sensitivity of commercial parts. Figure III- 12 shows the trends of memory cell capacitance for SRAM and DRAM circuits. While the cell capacitance for the DRAMs has remained fairly constant, the SRAM cell capacitance has steadily decreased with each generation. Device scaling suggests that the critical charge increases exponentially with feature size [27]. Lower supply voltages will also
111-13
make future CMOS generations more susceptible to SEU.
100,
DRAM
t
g:
::
\’i ~
u 1DRAM SRAM
&
s.%
DRAM:: IEDM&ISSCC SRAM: MOTOROLA , 64K 16K
, 256K 64K
1 lMb 256K
I 4Mb lMb
, 16Mb 64Mb 4MIJ 16Mb
Fig. III- 12 Capacitance trends for SRAMS and DRAMs [23].
Fortunately, there are trends that should offset some of the negative effects. As polysilicon resistors reach their scaling limits, designers are moving to Thin-Film Transistors (’ITT) for SWM bitcell loads [28]. This will reduce the SER levels. The use of thinner epi will reduce the charge collection volume. The adoption of SOI substrates by the commercial IC manufacturers would provide the greatest benefit to the military/space systems designers. 3.2 Total-Dose Effects Due to Single Ions Single ions can deposit enough charge to cause hard errors in CMOS circuits. This effect was fist examined by Oldham and McGarrity in 1981 [29]. At the time, it was not an issue because of the current device geomehies. The failure mechanism is a stuck bit caused by excessive leakage current in a cell. The leakage current increase is the result of a shift in the MOSFET threshold voltage. In 1991, Koga and his colleagues first reported stuck bits in commercial SRAMS during heavy ion testing [26]. The phenomenon was characterized as “A semi-permanently stored pattern”. Stuck bits were observed in a number of 1Mbit SRAMS. Some stuck bits annealed, while others did not. Dufour et al. have seen a similar effect [30]. Recently, Oldharn and his coworkers have examined current transistor and circuit geomernes and shown through analysis that total-dose induced hard errors in DRAMs and SRAMS are likely to occur [31 ]. Scaling in device dimensions, both laterally (device footprint), and vertically (gate oxide thickness), could exacerbate the problem. The rapid decrease in charge trapping efficiency with thin oxides (c 100~) will help the situation. Also, the change in SRAM cell design from polysilicon loads to ‘ITT loads will reduce the sensitivity of future SRAM circuits.
III -14
4. Bipolar Technology Bipolar transistors have been around for almost 50 years. Although they do not enjoy the dominance they did prior to CMOS development in the 1970s, they still play an important role in the semiconductor industry. Bipolar transistors are still favored for their high speed, low noise, and high current carrying capability. 4.1 Current Technology The biggest change in bipolar technology in the last 10 years has been the transition from single crystal emitters to polysilicon emitters. Virtually all bipolar processes developed since the late 1980s employ polysilicon emitters. Polysilicon emitters are required because metal contacted single crystal emitters are not compatible with shallow (<1 ~m) emitters. As vertical device scaling produced shallower emitters, base current increased due to carrier recombination at the metal/silicon interface. Polysilicon emitters eliminate this high recombination interface and also can be used as a diffusion source to form ultra-shallow emitters. The most advanced bipolar processes employ a self-aligned double-polysilicon transistor. A cross section of a typical device is shown in Fig. III-13. The double-polysilicon transistor uses a second layer of polysilicon to contact the base region. This structure has two important features. By contacting the base with polysilicon, the area of the base diffusion is reduced. This decreases the Cjc (collector-base capacitance) of the device. In addition, since the base and emitter are self-aligned to each other, the base contact can be placed closer to the emitter. This has the effect of reducing the base resistance. Typical double-polysilicon transistors that are in production have minimum emitter dimensions of 0.8 ~m. Most have breakdown voltages (BVCEO) of 5-6 volts. The speed of these devices, as measured by the unity gain frequency fT, ranges between 15-25 GHz. Processes
are beginning to
appear with 3.3 volt breakdowns. These processes have minimum emitter sizes of 0.5 ~m, and fT values anywhere from 30-50 GHz. The basic trade-off between breakdown voltage and fT for bipolar transistors is demonstrated in Fig 111-14.Devices are scaled vertically to reduce the capacitance and the base width. This leads to faster devices, but also reduces the voltages that the device will support. 4.2 SiGe HBT Devices A recent development in bipolar process technology that has the potential to dramatically enhance the performance of bipolar processes is the development of the SiGe Hetero-junction Bipolar Transistor (HBT). Devices with cutoff frequencies greater than 75 GHz have been reported [33]. SiGe hetero-junction technology was developed at IBM in the mid 1980s. Researchers at IBM and at other companies have used “bandgap” engineering to develop these high-speed devices. Germanium, which has a smaller bandgap than silicon, is introduced into the base of the bipolar transistor. By grading the bandgap across the active base region, the base transit time can be
III -15
,Base
Emitter
m
Fig. III- 13 Advanced self-aligned double-polysilicon
transistor.
decreased, thus increasing f~ The smaller bandgap in the base also increases the device gain by increasing the electron injection from the emitter.
la
‘1 f:;GHz)
Fig. 111-14Measured cutoff frequency vs. breakdown voltage from recent publications
[32].
The technology advancement that enabled the development of SiGe HBT devices was the development of low temperature epitaxy that is required to deposit the Ge graded base region. The epitaxy is done at low temperatures, in an ultra-high vacuum system, to prevent the redisrnbution of the dopants. Since the Ge atom is slightly larger than the silicon atoms it replaces, care must be taken not to generate defects in the silicon. Ranges of Ge doping levels are typically 5-10 atomic%. Figure III- 15 is a device cross section of a SiGe HBT structure.
Fig. III- 15 SiGe Hetero-junction
bipolar Dansistor device structure [34].
One of the major advantages of a SiGe process is that it is a silicon based technology. The low temperature epitaxy step is the only unique step that is added to the basic silicon bipolar process. Because of this advantage, SiGe can leverage off the huge installed base of silicon processes. This is a clear advantage over other hetero-junction technologies such as GaAs.
111-17
While SiGe was first developed for high-speed ECL applications, it is also finding use in linear applications. In addition to the speed of the devices, analog designers can take advantage of the high beta/Early voltage product that these devices exhibit. Recently, a 12-bit DAC operating at over 1 GHz has been demonstrated [35]. SiGe devices are attractive for low-power applications because they consume less power for a given speed than conventional bipolar devices. SiGe processes can also be optimized for low-temperature (77”K) operation [36]. Historically, bipolar devices were not used for these applications because their gain decreases with temperature. 4.3 Trends in Bipolar Devices As with CMOS technology, device scaling of bipolar devices is fairly predictable, while the development of new structures is not as predictable. Bipolar device scaling in the vertical dimension results in shallower j unction. This increases device performance by decreasing the width of the active base region. Lateral scaling decreases parasitic capacitance by reducing the footprint of the device. Double-polysilicon structures will remain the dominant bipolar device for the near future. This structure, and the inevitable device scaling have important impacts on device hardness which will de discussed later. 4.4 soI Commercial bipolar processes lead their CMOS counterparts in the use of SOI substrates. A number of companies have recently developed complementary-bipolar processes that employ bonded wafer SOI substrates and lateral trench isolation [37], [38]. Figure HI-16 is a device cross section of a complementary-bipolar trench/SOI process. The process features full dielectric isolation. Promising radiation test results have been seen for circuits fabricated on these trench/SOI technologies [39j.
NPN
PNP
P~YSlLlC0?4
[
Fig. III- 16 Device cross section of a trench/SOI complementary
bipolar process [37].
Commercial bipolar technologies are adopting oxide isolation schemes for a number of reasons. For complementary bipolar processes, the use of trench/SOI can greatly simplify the task of device isolation. The elimination of latchup is also a benefit. Oxide isolation reduces parasitic capacitances, improving both device and circuit performance. Performance over temperature and supply voltages is improve by eliminating junctions. Employing trench/SOI cart be cost effective by reducing the mask count and, as a result of increased packing density, decreasing the die size. Clearly, the use of full oxide isolation on commercial bipolar processes will greatly benefit designers of military and space systems. Trench isolation is used on many NPN only bipolar and BiCMOS processes now in development. In this scheme, trenches are used to laterally isolate devices which are fabricated on a bulk silicon substrate. This can cause problems because the trenches are lined with oxide and the trench sidewalls can invert with exposure to ionizing radiation. 5. Bipolar Sensitivities The radiation sensitivities of bipolar devices and circuits have changed dramatically over the last 10 years. In general, devices are less sensitive to displacement damage, ionizing radiation remains a problem, and circuit effects due to single ions have emerged as a new problem. 5.1 Displacement
Damage
Bulk displacement damage is no longer a problem with today’s high frequency devices. For older technologies, the gain of the bipolar devices is limited by minority carrier recombination in the base region. Newer processes have very narrow base widths, some <1,000 ~. The current gain for these narrow base devices is limited by other Components of base current. Figure III-17 is a graph of bipolar gain degradation versus neutron fluence as a function of transistor fT For the case of a 10-voh transistor with a fT = 3-GHz, the device will still maintain 75% of its initial current gain after exposure to a neutron fluence of 1014 N/cm2. 11 npn
translator,
t-MOV
neutron.
-=6
K,(I.) — Iwt,
VP.
i-h
100
+(w)
K,. t .lO* ,0 =,00
em’
s-’
l==lmA
0 0 .
\ ~
\
●
m z
~ ~
\
\
\
so -A. \,I
I*
: % . ●
\
; a o 109
1010
,.11 Neutron
fluencw
10’2 e
ncm”’
(1-
*.v
.wIv.I.*1)
Figure III- 17 Bipolar gain vs. neutron fluence as a function of cutoff frequency [40].
HI -19
5.2 Ionizing Radiation Total dose induced gain degradation is a major concern with bipolar transistors, including doublepolysilicon devices. As the device junctions are made shallower, the transistors become more sensitive to surface effects. Ionizing radiation degrades the oxide above the emitter-base junction, leading to an increase in base current due to recombination at the silicon/silicon dioxide interface. Researchers have characterized the radiation response of advanced bipolar transistors [41], [42]. Figure III- 18 shows the total-dose induced gain degradation of a typical bipolar transistor. The current gain degradation, particularly at low currents, can be dramatic. f;%
0.0
Total Dose
[krad(Si02)] +fJ
0.6
0.4
0.2
0.0
6.4
0.s
0.6
0.?
0.8
*
10
+
20
+
50
+
100
~
200
+
6oo
o.g
v~~ (v)
Figure 111-18 Current gain degradation in a bipolar transistor exposed to ionizing radiation [43].
In advanced double-polysilicon transistors, the material above the emitter-base junction can be a combination of thermal oxides, deposited oxides, or nitrides. This makes predicting the radiation response of these devices particularly difficult. Total-dose induced collector-to-emitter leakage does not appear to be a problem in modem bipolar devices. This is probably the result of higher doping levels in the base which makes inverting the surface of the base unlikely. The total-dose response of advanced bipolar transistors has been shown to be dose-rate dependent [43], This raises the concern that MIL-STD-883B Test Method 1019.4 hardness assurance tests may not represent a worst case test. The gain degradation has been found to be greater at low dose rates. High dose rate and anneal tests may not be adequate to predict the response of these devices in space environments. 5.3 SEE Single Event Effects (SEE) are emerging as a potentially serious problem for state-of-the-art bipolar technologies. Bipolar circuits have been shown to latch with high dose-rate transient radiation, and more recently, during single events [44]. A number of the technology trends associated with bipolar processes suggest that the occurrence of Single Event Latchup (SEL) will perhaps become more likely in the future. Tighter packing densities can lead to higher p~asihc bipolar gains.
HI -20
Smaller geometries will reduce the critical charge required to induce latchup. Also, in an effort to reduce collector-substrate capacitance (Cj~) processes are being designed with a lower substrate doping. Lightly doped substrates have higher minority carrier lifetimes, increasing the charge collected fkom the substrate. The use of SOI substrates will offset many of these effects. SEU has been observed in bipolar circuits. Koga et al. have studied this effect in op-amps and voltage comparators using heavy ions and laser probes [45]. In this work, upsets were seen but latchup was not observed. It was proposed that charge collected in the sensitive front-end nodes was amplified to the output, appearing as an upset. Other researchers have studied SEU in analogto-digital converters [46]. Here, two types of upsets were observed, upsets in the digital portion of the cimuit caused random bits to appear at the outpu~ while upsets in the analog portion of the circuit caused spreading in the output distribution. 5.4 BiCMOS Technology BiCMOS processes have gained popularity because they combine the high speed and current drive capabilities of bipolar transistors with the low power and high packing density of CMOS devices. Uses for digital BiCMOS processes include high speed SRAMS and microprwessors. Linear (analog) BiCMOS processes are used for high-performance analog-to-digital converters. The difference between digital and analog BiCMOS processes is primarily whether the bipolar (analog) or the CMOS (digital) device characteristics are optimized. Most BiCMOS prcxesses are developed by adding a bipolar device, generally an NPN, to a core CMOS process. Depending on the bipolar performance needed, the addition of the bipolar device may require anywhere from 1 to 4 mask levels. One of the simplest implementation involves using the MOS gate polysilicon as the emitter of the NPN transistor. The polysilicon is most likely already doped n-type, and the only additional mask is used to selectively dope the P-base regions. It should be noted that bipolar devices already exist in all CMOS devices, but they are low performance substrate and lateral devices. The trade-off in developing a BiCMOS process is one of cost (additional process steps) vs. performance. If the highest performance is required, buried layer, collector plug and emitter layers may be introduced. In general, because they contain a wider variety of transistors, BiCMOS processes are more sensitive to radiation than either bipolar or CMOS processes. In the simple BiCMOS scheme described above, where the MOS gate polysilicon is used to form the emitter of the bipolar mmsistor, the emitter is driven after the gate oxide is grown. This high-temperature step (up to 1000”C) significantly degrades the gate oxide, resulting in large threshold shifts during exposure to ionizing radiation. BiCMOS processes have been developed using SIMOX substrates [47]. These processes have the liability of incorporating a lateral bipolar device which is extremely sensitive to ionizing radiation, Field inversion and leakage caused by excessive hole trapping in the field oxide can be a problem in BiCMOS processes, just as it is for bipolar and CMOS processes. Latchup and SEU are also a concern. The number of potential latchup paths is increased when a bipolar device is introduced into a CMOS process. If a buried layer and deep collector plug are added to the process, they can be used to reduce the chance of Iatchup,
111-21
The use of BiCMOS processes has not accelerated as fast as some had predicted. While it is clearly a mainstream semiconductor IC process technology, is has a long way to go before challenging CMOS as the dominant IC technology. Some trends in BiCMOS technology may benefit the rnilitarylspace systems designers. High performance BiCMOS processes are being developed that incorporate trench or trench/SOI isolation techniques. Also, newer processes, due to reduced thermal budgets, make use of lower temperature emitter drives. This should reduce the gate oxide degradation. RTA cycles, which are now commonly used for the emitter drive, may not degrade the gate oxide as severely as conventional furnace cycles.
6. Device Fabrication 6.1 Ionizing Radiation in Processing Them are an increasing number of ionizing radiation processes in today’s IC technologies These processes include:
[48].
X-ray lithography Plasma etching of oxides, metals, polysilicon, and other films Plasma photoresist stripping Sputtering of thin films (A1-CU, Ti, W, SiCr, NiCr, Mo, Co) Plasma Enhanced Chemical Vapor Deposition (PECVD) Of these steps, X-ray lithography has probably received the most attention. It is being explored as a next generation lithography tool as the limits of optical lithography are reached. Current 0.5 Lm technologies employ 365 nm optical lithography. In order to define smaller features, shorter wavelengths will be required. New resist chemistries and phase-shift masks will extend the range of optical lithography to at least 0.25 pm. Present X-ray lithography systems are expensive (X-ray source and masks) and will only become viable when optical lithography reaches it limits. Researchers have examined the effects of X-ray lithography on MOS devices [49], [50]. The concern is that the exposure to X-rays will affect the reliability and/or radiation response of the devices. Typical X-ray exposures are in the 50-100 Mrad(Si02) range, The effects of this sizable dose are minimized because no bias is applied during the exposure and trapped charged is annealed during the high temperature (45WC) anneal cycle following metal patterning. Neutral electron traps may be an issue because they do not anneal at this temperature. 6.2 Commercial Manufacturing The result of all these ionizing radiation steps in today’s process technologies may be that processes are designed to be more resistant to ionizing radiation. Commercial processes are driven by reliability concerns that in many ways parallel radiation concerns. One example of this is the similarity of MOS and bipolar hot-carrier effects to total-dose effects [51]. Another example is the growing concern with SEU in the design of commercial ICS.
III -22
The similarity of the reliability and radiation concerns can only help military and space system designem as the commercial markets require more robust parts. Certainly the use of SOI substrates in commercial circuits must excite military IC users. Excitement about these technology changes that improve the performance of commercial ICS in radiation environments must be tempered by the fact that the circuits will still be produced by the commercial manufacturers that operate in a much different environment than their militay IC counterparts. The cost structures of commercial IC producers drives continuous change. Process may change as a new piece of equipment is brought on-line, as the process is moved to larger wafers, or through improvements necessitated by yield enhancement activities. Evaluations of commercial IC technologies provide only a snapshot of the radiation tolerance of a process. Changes that improve yields and electrical performance can adversely impact the radiation response of a part.
7. Summary The radiation sensitivities of current state-of-the-art and future generation commercial IC technologies has been discussed. In general, as old radiation concerns go away, new ones arise to take their place.
III -23
References
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Military imd Aero-
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MOS
13- N. S. Saks, M. G. Ancona, and J. A. Modolo, “Radiation Effects in MOS Capacitors with Very Thin Oxides at 80K,” IEEE Trans. Nucl. Sci., ~S-31, 1249 (1984). 14- T. Yamaguchi, S. Morimoto, G. Kawamoto, H. Park, G. Eiden, “High-Speed
III -24
Latchup-Free
0.5 pm-Channel CMOS Using Self-Aligned
TW2 and Deep-Trench
Isolation Technologies,”
JEDM Tech. Digest, 522, (1983). 15 -K. Izumi, M. Doken, and H. Ariyoshi, Electronics Letters, 14,593,
(1978).
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“ISSCC: Digital Technology,” Electronic Design, 72, (1994).
20 -T. Eimori, T. Oashi, H. Kimura, Y. Yamagughi, T. Iwanatsu, T. Tsuruda, K. Sums, H. Hidaka, Y. Inoue, T. Nishimum, S. Satoh, and H. Miyoshi, “ULSI DRAM/SIMOX with Stacked Capacitor Cells for Low-Voltage Operation,” IEDM Tech. Digest, 45, (1993). 21- T. C. May and M. H. Woods, “Alpha-Particle-Induced IEEE Trans. Electron Devices, ED-26, 2 (1979).
Soft Errors in Dynamic Memories,”
22- D. Yaney, J. Nelson, L. Vanskike, “Alpha-particle Tracks in Silicon and Their Effects on Dynamic MOS RAM reliability,” IEEE Trans. Electron Devices, ED-26, 10 (1979). 23- C. Lage, D. Burnett, T. McNelly, K. Baker, A. Bormann, D, Dreier, and V. Soorholtz, “Soft Emor Rate and Stored Charge Requirements in Advanced High-Density SRAMS,” IEDM Tech. Dig., 821 (1993). 24- T. J. O’German, “The Effect of Cosmic Rays on the Soft Emor Rate of a DRAM at Ground Level,” IEEE Trans. Elec. Dev., ED-41, 553, (1994). 25 -G. Srinivasan, P. Murley, H. Tang, “Accurate, Predictive Modeling of Soft Error Rate Due to Cosmic Rays and Chip Alpha Radiation,” Proceedings of the 32nd Annual International Reliability Physics Symposium, 12, (1994). 26- R. Koga, W. R. Crain, K. B. Crawford, D. D. Lau, S. D. Pinkerton, B. K. Yi, and R. Chitty, “On the Suitability of Non-Hardened High Density SRAMS for Space Applications,” IEEE Trans. Nucl. Sci., NS-38, 1507 (1991). 27- G. C. Messenger, and M. S. Ash, “The Effects of Radiation on Electronic Nostrand Reinhold, New York, 2nd Ed., 1992.
Systems”, Van
28- J. Hayden, K. Cooper, S. Roth, H. Kirsch, “A New Toroidal TIT Structure for Future Gener-
111-25
ation SRAMS,” IEDM Tech. Dig., 825 (1993). 29 -T. R. Oldham and J, M. McGarrity, “Ionization of Si02 by Heavy Charged Particles~’ IEEE Trans. Nucl. Sci., NS-2& 3975 (1981). 30- C. Dufour, P. Gamier, T. Carriere, J. Beaucour, R. Ecoffet, and M. Labrunee, “Heavy Ion Induced Single Hard Errors on Submicronic Memories,” IEEE Trans. Nucl. Sci., JW-39, 1693 (1992). 31 -T. R. Oldham, K. W. Bennett, J. Beaucour, T. Carriere, C. Polvey, and P. Gamier, “Total Dose Failures in Advanced Electronics from Single Ions,” IEEE Trans. Nucl. Sci., NS-40, 1820 (1993). 32- T. Nakarnura, “Bipolar and BiCMOS Devices and Circuits for ULSI”, Proceedings of the Fourth International Symposium on ULSI Science and Technology, Vol. 93-13,55-71, 1993. 33 -E. F. Crabbe, J, H. Comfort, W. Lee, J. D. Cressler, B. S. Meyerson, A. C. Megdanis, J. Y.-C. Sun, and J. M. C. Stork, “73-GHz Self-Aligned SiGe-Base Bipolar Transistors with PhosphorousDoped Polysilicon Emitters,” IEEE Elec. Device Letters, EDL-13, 259 (1992). 34- J. Comfort, E. F. Crabbe, W. Lee, J. D. Cressler, B. S. Meyerson, J. Y.-C. Sun, G. Patton, P. Lu, J. Burghartz, J. Warnock, G. Scilla, K. Toh, M. Agostino, C. Stanis, K. Jenkins, and J. M. C. Stork, “Profile leverage in a Self-Aligned Epitaxial Si or SiGe Base Bipolar Technology,” IEDM Tech. Digest, 21 (1990). 35- D. L. Harame, et al, “Optimization of SiGe HBT Technology for High Speed Analog and Mixed-Signal Applications,” IEDM Tech. Digest, 71 (1993). 36 -J. D. Cressler, E. F. Cmbbe, J. H. Comfort, B. S. Meyerson, J. Y.-C. Sun, G. L. Patton, and J. M. C. Stork, “On the Profile Design and Optimization of Epitaxial Si- and SiGe-Base Bipolar Technology for 77K Applications - Parts I and II,” IEEE Trans. Elec. Dev., ED-40, 525 (1993). 37- S. Feindt, J-J. J. Hajjar, J. Lapham, and D. Buss, “XFCB: A High Speed Complementary Bipolar Process on Bonded SOI,” BCTM Proceedings, 264 (1992). 38- C. Davis et al, “UHF-1: A High Speed Complementary BCTM Proceedings, 260(1992).
Bipolar Analog Process on SOI,”
39 -M. DeLaus, W. Combs, and N. Nowlin, “Total-Dose Results for the AD8001, a High Performance Commercial Op-Amp Fabricated in a Dielectrically Isolated Complementary Bipolar PRocess,” To be Published, Workshop Record, 1994 Radiation Effects Data Workshop. 40- A. Holmes-Siedle, Press, Oxford, 1993.
and L. Adams, “Handbook
of Radiation
Effects”, Oxford University
41- E. W. Enlow, R. L. Pease, W. E. Combs, R. D. Schnmpf, and R. N. Nowlin, “Response of Advanced Bipolar Processes to Ionizing Radiation,” IEEE Trans. Nucl. Sci., JW3-38, 1342 (1991).
III -26
42- R. N. Nowlin, E. W. Enlow, R. D. Schrimpf, and W, E. Combs, “Trends in the Total-Dose Response of Modern Bipolar Transistors,” IEEE Trans. Nucl. Sci., NS-39, 2026 (1992). 43- R. N. Nowlin, D. M. Fleetwood, R. D. Schrimpf, R. L. Pease, W. E. Combs, “HardnessAssurance and Testing Issues for Bipolar/BiCMOS Devices,” IEEE Tm.ns. Nucl. Sci., lW-4Q 1686 (1993). 44- M. Shoga, J, Gorelick, R. Rau, R. Koga, and A. Martinez, “Observation of Single Event Latchup in Bipolar Devices,” Workshop Record, 1993 Radiation Effects Data Workshop, IEEE, 118, (1993). 45- R. Koga, S. D. Pinkerton, S.C. Moss, D.C. Mayer, S. LaLumondiere, S. J. Hansel, K. B. Crawford, and W.R. Crain, “Observation of Single Event Upsets in Analog Microcircuits,” IEEE Trans. Nucl. Sci., NS-4Q, 1838 (1993). 46- T. Turflinger, “Single Event Effects in Analog-to-Digital Converters: Test Results and Future Plans,” Seventh Single Event Effects Symposium, April, 1990. 47 -R. Dekker, W. T. A. v.d. einden, and H. G. R. Maas, “An Ultra Low Power Polysilicon Emitter Technology on SOI,” IEDM Tech. Dig., 75 (1993). 48- T. P, Ma, and P. V. Dressendorfer, (Ed.), “Ionizing Radiation Effects in MOS Devices& cuits”, Wiley Interscience, New York, 1989.
Cir-
49- A. J. Lelis, and T. R. Oldham, “Reliability Effects of X-Ray Lithography Exposures on Submicron-Channel MOSFETS,” IEEE Trans. Nucl. Sci., JW-40, 1367 (1993) 50 -R. Klein, N. Saks, G. Campisi, and J. Logue, “Neutral Electron Traps in X-Ray Imadiated and Annealed MOSFETS”, Proceedings of the Symposium on Reliability for Semiconductor Devices, Interconnects, and Thin-Insulator Materials, Vol. 93-25,461-469, 1993. 51- D. H. Huang, E. E. King, J. J. Wang, R. Ormond, and L. J. Palkuti, “Correlation Between Channel Hot-Electron Degradation and Radiation-Induced Interface Trapping in N-channel LDD Devices,” IEEE Trans. Nucl. Sci., NS-3& 1336 (1991).
111-27
1994 NSREC SHORT COURSE
SECTION IV
ADAP~I~G COMMERCIAL ELECTROiVICSTO THE NATURALLY OCCURRING RADIATION EWIRONMENT
NADIM HADDAD AND THOMAS SCOTT LORAL FEDERAL SYSTEMS
,,
Chapter IV Adapting Commercial Electronics to the Naturally Occurring Radiation Environment
Nadim
Haddad
Tom Scott LORAL Federal Systems Company Manassas, VA. 22110
Section IV - A The Use of COTS Components in the Natural By: 1
Space Environment
Tom Scott
Introduction
The previous talks discussed the environment and it’s effects as well as state of the art processes, devices and petiormance. This talk will attempt to give an ovemiew of the implementation of commercial components into systems intended for use in the radiation environment. The reasons for selecting Commercial Off The Shelf devices (COTS), those devices that were not intended to perform in a radiation environment, are (Chart IV-1 ): + They are cheaper due to their high production volumes and minimal initial screening. However, the screening costs are normally added back in as soon as the part is purchased for flight since reliability must be assured to higher degree than is normally acceptable in commercial applications. Screening is necessary due, in part, to the environmental concerns but primarily due to the cost of retrieval for repair or direct replacement. As an example, the electronics in a box may cost $10,000 not including design cost etc., but to put the system into orbit may run >$250/oz,. With a payload of 50#’s the end product delivered to it’s application orbit would cost >$200,000, to say nothing of retrieval or in flight repair costs. ● COTS speed and density are constantly driving the advancement of technology. The denser the product the greater the yield per fi,mction and the cheaper the product. The faster the product the more demand the consumer will generate for it, especially if the cost (driven again by yield) is competitive with a slower product. Denser devices are in general faster due to the principles of scaling. + COTS also have a larger spectrum of offerings, product fimction, speed selections, package styles, and source of supply; and their availability is in general better than custom designed devices on Rad-Hard lines. These may seem obvious, but it will be demonstrated that the motivation for using COTS devices often becomes negated by the techniques of implementing them into the system, and assuring their performance; making a hardened products initial cost of less consequence. Now that we have discussed the reasons why COTS are attractive, it maybe well to understand how the program specification (system specification) allows or hinders the utilization of non-hardened devices.
IV- 1
Reasons for use . Reduced Emphasis on Military Applications - No Dose Rste Requirements -Some Applications Are Low Total Dose(ex. LEO) . Cheaper - Highprodudion volumes - Less srxeaning Speed Densly - Commercial msrket driven by Yield .Availabili - Product build is mors frequent and stocks are larger Dwersily A larger market base creates diversify and aliews for niches to be profitable
Chart IV- 1
2 2.1
COTS Usage Program Development
Impact
As the standard program development proceeds from inception to field delivery, most steps within the process determine whether COTS devices can be utilized, or specifically hardened devices are necessary. To demonstrate the flow, a simple program development and some of the major steps accompanied by their impacts on device selection, are outlined in Chart IV-2.
. ....... .
.
. . ..
Mlss!on
Requirements
.. . .... .... . .. .........
Program
Outtlned
COnce@On
Q Rad!abon
SpecificatKms
Incorporated
I
Program
SpecfwaMn
4
Program U ndersbrdmg
Radmbon
of Radtatlon
Performance
Environment
Enluatsd
lmDlemented
Bid
1 I
Chart IV-2
IV-2
I I
I
Design BUIM
1
Delver
I
At program conception, the system’s mission may define the environment or position of operation by the nature of mission itself. If the mission is to map the electron belts about the earth the product must operate in a low dose environment for such a long period just by definition. Over the life of the mission, given the long time required to complete such a task, hardened parts will be required. Past this point, the development of the system specification may overemphasize the need for Radiation Hardened devices. This may occur by either requiring them out-right or by the creation of specifications that portray worst case environments, doesn’t acknowledge the improvement due to shielding or allow for tradeoffs by system abatement techniques. This is oflen the case where the specification writer is uninformed of the cost impact, or is unwilling to entertain a risk versus cost tradeoff. If on the other hand this has been accounted for, and reasonable amounts of information are passed onto the contractor, some cost, space, etc. improvements may be implemented by a COTS selection. If only minimal emphasis or reference is made to radiation concerns, or if the topic is ignored, the bidding process may neglect the radiation impact on cost and device availability. However a well informed contracting agency generally incorporates a Radiation Hardness Assurance Plan (RHAP) and requires that the vendor demonstrate his awareness and capabilities of dealing with the Radiation environment. The RHAP may consist of tracking each device, test procedure documentation, validation/test for each device’s performance and impact on the system. The RHAP not only assures that the vendor understands what will be required and what he must be concerned about but it also allows him freedom in how the Rad Hard Assurance can be designed into the implementation. If the system ends up in the hands of the low bidder, who is unfamiliar with the environmental concern, the need for redesign may not become evident until the final phase of reliability assessment. Previous prototype and software development may all have to be scrapped unless suitable hardened devices can be obtained as replacements. But what if COTS components weren’t available in hardened processes, or the system design had already been performed and a hardened device implementation would cause a major redesign? Hardening COTS, utilizing hardened process technology and without major device redesign is an option that will be discussed in the second half of this talk,
2.2
Diversity in Environment
Could a single environment specification be produced and thus eliminate all of the questions and complexities of system design and hardness assurance techniques? The answer is a resounding yes, but this would require every system produced to meet excessive standards. Cost effectiveness and possibly even system viability would suffer for all but a minute number of systems due to such a verbose standard. As an extreme example, imagine a cable TV satellite having to withstand a nuclear explosion. The cost of HBO would probably be more expensive than buying a video store. Chart IV-3, demonstrates some of the radical differences in mission environments to which satellites are exposed. It is clear that COTS can only be used safely within benign, low earth and low angle of inclination environments. Any other application using COTS
IV-3
will be limited to a short mission life. To give a more global picture of the various environments and part performance, Chart IV-4 is presented
—————
-.—.—
./”-
‘\
TE:.2
I (
1 ,1
1
1 9
1 ,0
1 ZM
I
1, ‘\ \ -.—.—.———.—. .—.—.——..——— —-— —— .—— ——— — —-
/
Chart IV-3.
VLSI b-m’.
,
[email protected]
=
A.llabky
Chart IV-4. 2.3
Determining
COTS Component
Radiation Performance
In all likelihood, by the time the radiation performance is seriously considered , system design is very close to the final stages. This isn’t unreasonable when one considers that the designer is rarely both a system designer and a radiation expefi. Similarly, the radiation expert is not a system designer and is normally working with just a Bill of Materials (BOM). The best that can be hoped for in this case is that the radiation engineer has been consulted during the initial design phases to understand what category of devices are not an issue, and how the box and peripherals
rv-4
can be implemented to help shield the more sensitive components. Often the most sensitive features of a satellite are it’s sensors or transmission components. These are by nature delicate instruments, and quite oflen take the worst abuse from the elements as they are normally mounted on the exterior of the platform. To get back to the subject at hand we will look at how the system specification relates to the radiation requirements.
Hidden Radlat&a Spactftcations
. RdlabiRy .%tcmants . System Perlamance . En*rnm-snts . References
Statenwnts
Definb cms to Sandards
nnd Mettwds
. Incbslve Erwimmment .%tements ?e., Syslem perfcm-wce shsll .c4 be affected by the enwrmmenf c4 cperatkn, hcluding ratiatim:
Chart IV-5. To demonstrate some of the less obvious ways that radiation performance maybe specified with a procurement document and the reason for the radiation levels and part hardness requirements, see Chart IV-5. The specs. may come in the form of system reliability requirements (e.g.. Only 1 system reset per year is allowed), system performance impact statements, (e.g.. the system performance shall not be effected by radiation during the life of the mission), an appendix of environment descriptions accompanied by a statement that all environmental impacts shall be considered, and finally, “ the statement maybe as vague as performance shall be calculated based on device performance in accordance with MIL, Handbook XXXX, where XXXX refers to radiation concerns.
●
●
●
As mentioned previously the more vaguely the radiation concern is stated the less likely it will be dealt with adequately or cost effectively. Once an initial BOM is obtained, the search for previously available radiation test data begins. It should be noted that the fitility or success of this effort is more often than not based on the environmental concerns, e.g. if you are looking for an EEPROM that is 128Kx8, has a 100ns access time, and is 1Mrad hard the search can be terminated. Yet for a 2. 5K rad application such as Space Station, nearly 3/4 of the parts were found to have been tested, or similar device’s test data was suilicient to assure the device used would perform adequately. The data bases available for search are listed in Chart W-6. The vendor would often appear to be the most likely place to begin the search; but rarely is the data ever reported back to the manufacturer, This is normally the case since test data is taken as a last resort, and quite oilen testing is done near the end of a programs completion. Documentation back to a vendor, or for
Iv-5
that matter, any data base becomes a very low priority when you’re spending your own nickel It has been proposed in the past that the government, being the largest supporter of testing, should create a data base where one could expect all results to be uniformly logged and accessible. Yet this is still not a requirement, even though government supported data bases do exist. It has been the authors experience to find the bulk of the test results through the NSREC proceedings.
L.0~ ,-.-t-
VLSI 5.= Radiation Data Sources . COTS
Vendor
. Inhmous
Inhouse
dab
base
. ERRIC . RADDATA-J . NSREC
PL
Proceedings
. etc.
Chart IV-6. As Chart IV-7 demonstrates, even if previous data is available, the test data may not be valid for the current application. This is due in part to the dependency of radiation performance on part usage. If a part is powered off for the majority of a flight it will probably survive to higher Total Dose levels than a device which is tested under worst case bias. It is not just these extremes that cause the data to be irrelevant. In fact, device radiation performance is quite often a strong fi.mction of temperature, bias, frequency and/or mode of operation. As a quick example, consider the case where a manufacturer’s part has an extremely low supply current requirement and when tested fails at a very low dose. This same device may finction adequately to 10x this dose if the supply current is allowed to exceed the manufacturers spec..
Previous Teat Data Problems . Dmtm,$ c-+ wa,!abk w inmsng auad dda - B,.,
co”dl, m$
.Port$on ddticend - Freqwncy
ledcd
Temperature, or Mode dependenaes
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Chart IV-7.
Iv-6
Even if the data does exist, the device tested may not represent wafer to wafer variation, lot to lot variations, current process, or the current design. To trace these, the vendor must be consulted assuming you have the lot that was tested or perhaps a datecode. It has been the authors experience that even armed with this information you may run into the suppliers claiming that nothing between then and now should have affected device performance. This maybe true but unless the manufacturer is aware of what affects the device radiation pefiormance the statement is of no value. This is the same reason why the manufacturer will not supply you hardness assurance to begin with. Remember that the form fit and fimction are the only assurances that commercial suppliers will generally provide any customer. As an example, the company the author works for went to purchase 10,000 commercial pieces fi-om a commercial vendor. All we asked for was a special screen be put in place based on data they already were taking. Since they wouldn’t supply the data directly to us, due to confidentiality concerns, the screen was our only option. Yet the vendor decided not to bid this part to us at any price due to the trivial quantities we were asking for (10,000 pieces). Their reason, simply put, was that this would have changed the flow of their process, they don’t deal in small quantity orders, and their current customer base might be impacted by the change in flow for these parts, In this COTS business it is safe to assume that the only Rad Assurance that you will get is what you generate. A final thought on this issue is presented. It should not be assumed that the test results on one device from a process will represent any other device in that process. As an example, let’s assume a microprocessor design were to be used in a flight system. A device from the same process is tested for Single Event Effects(SEE) to demonstrate the microprocessors petiormance. Less complicated devices normally use a standard component library to create several different devices. However more complicated devices require specialized circuits, layouts, timing tweaks, etc. to increase performance density, and reduce power consumption. These changes affect SEE performance, and present part performance cannot be correlated back to the previous test networks. The only way that this type of correlation can exist is when only a library of components specially designed with radiation performance in mind are utilized. Even then, design checks must be implemented to assure performance in all radiation environments. In general you will either have to test the part yourself or become intimately aware of the how the test was performed, limitations of the test, applicability of the tests, and device process and circuit changes. The latter is a very difficult path but financially viable when considering the alternative.
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Chart IV-8. A list of some of the applicable standards for test can be found in Chart IV-8. The list contains guidelines, procedures and methods, In general, they do not tell you specifically how each device type is to be stimulated, characterized, and biased, This field is still a science and requires the test personnel to be keenly aware of the use conditions of the components, and how this impacts the method of radiation characterization. Take for instance the Total Dose Test Method 1019.4. Certain bipolar devices have been found to be more susceptible to low dose rates, (dose rates more closely representative of the naturally occurring space environments, <1 rad/day, as compared to the test methods direction of 100rads/sec.) Even with the annual cycle, the part’s performance is not accurately modeled by this test. It would appear that generalities are very elusive in this field and even the environment itself is not easily modeled. Factors of 2 in both short and long mission exposures are not uncommon. So system survivability/reliability appears elusive at best. The ability to apply the test data to the environment of use is also somewhat in contention. Again, Method 1019.4 only tries to produce worst case boundaries for Total Dose performance. The dose rates used in this method are obviously not equal to those in the space environment but they do produce a conservative trapped oxide failure rate. To produce a conservative interface trap failure rate, testing is suggested at 1.5x the required dose levels and then devices annealed for 168 hours at 100C, As an example a set of part data has been included in Chart IV-9. It demonstrates the wide spectrum of performance and introduces the next section on Abatement of COTS Radiation Susceptibility. Observe the SEE results for the 16M DRAM, long considered unusable for Space application due to it’s low SEE susceptibility and Total Dose performance. The failure rate is typically zero when the on device EDAC is enabled. Yes, the IBM 16M DRAM has internal
Iv-8
Error Detection And Correction (EDAC).
Pef$urmance Examples
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Chart IV-9 2.4
Abatement
Techniques
and
Their
Limits
Introduced
Often the part by itself demonstrates unacceptable failures in the environment of concern. But, with some system design modifications the COTS performance may become acceptable. Charts IV- 10 through IV-12 represent some of the methods available to the system designer and programmer to counter the effects of less than adequate device performance. ●
✎
✎
✎
✎
✎
ECC(Error Correction Codes) are utilized to repair losses in data in memory due to SEE, and possibly correcting bits damaged by total dose. Most engineers and software programmers are familiar with ECC’S predecessor the parity check. By adding bits to stored or transmitted data or commands, test hardware (called hamming codes) can periodically test and correct flipped bits in memory, verifi transmitted data equals received data, and either correct or request re-transmission or halt the system during non-correctable conditions. It should also be noted that if this data is transmitted, recorded, and interpreted, it can lead to an understanding of the probability of failures that can’t be corrected either due to degradation by total dose effects or by fluctuation in the environment spectrum. Lock Step: This is simply duplicate processing by duplicate systems utilizing the same data, normally with the same system clock or some method of synchronization. If a disagreement occurs, processing is halted and may invoke a restarter request intervention, Voting: Same as lock step but normally refers to more than 2 systems running independently. In this case majority rules unless a critical decisions requires full agreement(quorum vs. unanimous) Watch-Dog Timers: These are just simple networks that require servicing by the system, If the service does not occur, the timer reboots the system assuming that it has locked up. Self Diagnostics: If a system hasn’t been utilized over an extended period of time, preliminary testing of a subordinate system can assure functionality prior to utilization. Power cycling: Unbiased dosing extends some parts performance life,
IV-9
Reduction in Bias: By reducing the bias voltage during operation the probability of Iatchup and burnout of some device types is significantly reduced, but single event upset is aggravated. . Shielding: If shielding can indeed shield the radiation, this will obviously reduce system effects. Moderate shielding can reduce some environment concerns by orders of magnitude. Shielding does have its limits and comes with a penalty. Past about a 250mils additional shielding is rarely worth the cost. Yet some shielding does not incur penalty if it simply means moving the most sensitive components to the center of the unit, Often only the box is considered in shielding calculation, it should be assured that the components and the printed circuit boards are also included. It should also be noted that an in-depth shielding analysis may demonstrate an improvement in one portion of the environment and seriously worsen another. “ Neutron Irradiation: Reduces Iatchup potential by reducing gains of parasitic bipolar devices. Doesn’t reliably work on all devices, and the effect somewhat anneals out in time. Self Correcting Software: Simply put these are software codes that verifj the system and data integrity and modifi system architecture(say if a section of memory went south) or when data flow is reinitiated based on data verification. “ Big Red Switch (Ground level intervention) Self explanato~. ●
●
I I I
Chart IV-10
Iv-lo
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Chart IV-12. If the abatement techniques did not have draw backs in their implementation they would be universally used, and Rad-Hard components would be unnecessary in all but the worst cases. Yet often the abatement technique increases power consumption, the components used in the abatement are soiler than the COTS they are trying to fix, throughput is decreased, weight and volume constraints are imperiled, as depicted in Chart IV-13. These plus costs of abatement and the possible ineffectiveness of the technique brings us to our final topic; and that is hardening the COTS components.
IV-II
--,
— -. ..-. -.—..——...
Above and Beyond Abatement . Abatement tachnquas may impeda system @ormance operating requirements
beyond
- Decreased through~t - Increased W+Wr requlrementsldtsslpatbn - Increased w4ghtMlume . Even extremely low probability may be unaccqtatk, I&latch control decom~esslon ol Me support moduk . Permanent Damage maybe unavoidabb through abatement devke sensuw~ doesn’t allow its ap@icat&n. . Cost of abatement over-rides berwlts
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Chart IV-13.
IV- 12
Section IV - B By: Nadim Haddad s Enhancing Commercial
Technology
for Rad Hard Applications
In cases where radiation requirements are not adequately satisfied by available commercial technologies, enhancements are required. Since the cost of redesigning or developing new operating soilware can be prohibitive in a low volume market, the development of a design transparent process technology is very beneficial. but, can this be accomplished without changing the operating characteristics of the system? The answer is yes if one presewes the inherent technology characteristics such as: layout rules transistor characteristics performance characteristics These restrictions prohibit the use of guard rings or body straps/ties not normally used in commercial designs, They also prohibit the requirement for increased device spacing, or slower operating speeds. The device design must be identical to the commercial design if possible; or can accommodate minor changes without forcing a total redesign, or a system modification. We will discuss enhancements to total dose, latch-up, and single event upset. Prompt dose upset and survivability are unique to the weapons environment and will not be discussed; even though enhancement to latch-up resistance can in itself result in significant improvement in prompt dose upset and survivability characteristics. 3.1 Total Dose Enhancement A dramatic improvement in total dose tolerance in state-of-the-art microelectronics has been achieved due to technology scaling. Ionizing radiation affects device behavior in two ways: the first is alteration of active device behavior such as threshold voltage shift and transconductance degradation; the second is the turn-on of parasitic leakages such as loss of device isolation (inter-device leakage), and device edge leakage (intra-device leakage). The thinning of gate oxide in today’s scaled technologies have resulted in reduced threshold voltage shifi (Chart IV-1 4) (ref 1) and interface state build-up to a degree where they are no longer the limiting factors in device hardness, Parasitic leakages are the primary cause of failure in today’s devices. 3.1.1
Gate oxide hardening
It was once believed that “radiation hard” oxide balances hole trap build-up with interface trap build up, so as to cancel the net effect of charge trapping (ref. 2). Even though this approach sounds attractive at the surface, it can lead to disastrous consequences. Charge trapping in oxides is a time dependent phenomena, and the rates of trapping and detrapping are fimctions of
IV- 13
TOTALDOSE ENHANCEMENTS -- GATE OXIDE TOTAL DOSE EFFECTS
o
EFFECT
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Chart IV-1 4
TOTAL DOSE ENHANCEMENTS
-- GATE OXIDE
TOTAL DOSE EFFECTS
O
RADIATIONI Delta
NDUCEDT HRESHOLDSHIFT
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Chart IV- I 5
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IV- 15) (ref 3). Devices that were known to work properly immediately idler irradiation, have fh.iled in the field due to annealing of hole traps and building up of interface traps in what came to be called “rebound”. It is important therefore, when developing a radiation hard gate oxide, to pursue reduction in both oxide and interface traps. There is no one magic recipe for the growth of radiation hard oxide. Success has been achieved with dry oxides as well as pyrogen.ic, as high as 1000”C growth temperature or as low as 850°C, It is important to investigate the growth parameters in context with the entire process, What happens to the oxide tier it is grown might well be more important than the growth conditions themselves. The general rule, however, is to grow a stress free oxide and preserve it throughout the process. Avoid ion implantation through the gate oxide, such as threshold adjustment implants; and avoid high temperature and stress generating processing once the gate material is deposited. Everything done after gate oxidation can have a significant impact on gate oxide radiation response (ref 4). Had it not been for field associated parasitic leakages, a well designed commercial digital circuit should be able to withstand parametric shifts associated with a Mega-rad of total dose without redesign, if process hardening is employed. In any case transistor models accounting for radiation induced behavior should be used to assess circuit tolerance over operating temperature and process spreads. Radiation tolerance should then be classified accordingly (e.g.. 10OK ra~ 200K rad, 1M rad, etc.). Chart IV-16 presents the post radiation data for a commercial submicrometer process (a) and the corresponding enhanced process (b). Both processes yield the same pre-radiation device characteristics, and only differ in trapping characteristics. temperature
3.1.2
(Chart
Field (Isolation)
Oxide Hardening
Due to their increased thickness, field (isolation) oxides are much more sensitive to ionizing radiation than thin gate oxides. This is true whether one is using local oxidation (LOCOS), shallow trench isolation (STI) or silicon-on-insulator (S01) technologies. A state of the art commercial field oxide process can withstand 10K-3 OK rad with acceptable leakage. Since this is lower than the tolerance of the thinner gate oxide, itnormally is the limiting factor in radiation tolerance of commercial technologies. Our objective is to harden the field oxide without relying on alternate isolation schemes i.e. field shield, guard ring, or diffision bounded channel. We also want to preserve the design layout, parasitic capacitances and produceablity. Classified processes have been developed to accomplish just that. Chart IV- 17 presents a comparison of radiation induced interdevice leakage of a commercial field oxide (a) in comparison with a radiation enhanced field oxide (b). Note that for 5.OV operation the commercial process loses isolation at 25K rad. The enhanced process on the other hand can tolerate multi-Mega-rad dose(ref. 5). Intra-device edge leakage is caused by the inversion of the device edge (bird’s beak in LOCOS or side-wall in STI) due to radiation induced trapped charges. (Chart IV-18) (ref 6). The device edge will conduct with OV gate voltage. Chart IV-19 clearly shows that the commercial device started to exhibit edge leakage after 15K rad (a), while the enhanced process shows no evidence of edge leakage afler multi-megarad dose (b) (re~ 5),
IV-15
TOTAL DOSE ENHANCEMENTS
-- GATE OXIDE
(TOTAL DOSE RESULTS) (tox = 12.5tim)
Original
Process
(~)
Process
Enhanced
[b’)
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2.7/0.65
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30
40
0
(Mrad(Si))
I
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20
30
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Chart IV- 16
TOTAL DOSE ENHANCEMENTS
-- FIELD OXIDE
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IV- 16
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TOTAL DOSE EFFECTS
o
RADIATION
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Chart IV-1 8
TOTAL DOSE ENHANCEMENTS
-- FIELD OXIDE
,.-2
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IV-17
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3.1.3
Technology
scaling effects
Since migration to submicrometer devices implies the use of thinner gate oxide, active device threshold shift is less of a problem. The normal thinning of field oxide is still not adequate to prevent inter-device and intra-device leakage’s, thus limiting total dose tolerance level to approx. 20-30K rad. Field hardening is therefore still required if scaled devices are to be used for anything but the most benign space applications. 3.2 Latch-up Enhancement In commercial technologies Latch-up (L/U) is usually addressed by using guard rings in the I/O circuitry. This protection is aimed at electrical transients at the I/Os but will do little to prevent L/U internally to the chip. L/U susceptibility is inherent in four element structures (such as CMOS) where the holding voltage (V(hold)) is lower than the operating voltage (V(op.)) (chart IV-20(a)). Since there is more than one stable point where the load line intersects the structures characteristic curve, an external stimulus (radiation pulse) can trigger and lock the structure into a high current mode. The most effective method to combat latch-up is to increase the holding voltage safely above the operating voltage, or to eliminate the holding voltage characteristics altogether. 3.2.1
Condition for L/U immunity
Chart IV-20(b) represents the coupling of bipolar devices responsible for latch-up in CMOS technology. Epitaxial N-well CMOS is assumed. A condition for L/U immunity can be represented by the inequality
Where aP and ct. are the bipolar_ for the parasitic pnp and npn transistors respectively. Rw is the series well resistance, Rs is the series substrate resistance, and Rn and Rp are the emitter resistance of the npn and pnp transistors(ref, 7). The limiting case where Rw and Rs approach zero is the familiar expression: an+ap< 3.2.2
1
Process modification
It is clear that achieving latch-up immunity without redesign (e.g. increased spacing or guard rings) implies the suppression of bipolar parasitic gains and the reduction in well and substrate
IV- 18
IATCH-UP
o
CAUSE
ENHANCEMENT
OF UU IN VLSI
FOUR ELEMENT PARASITIC DEVICES (p-n-p-n) HOLDING VOLTAGE (Vhold) < OPERATING VOLTAGE(Vop.) LOAD LINE INTERSECTS I-V CURVE AT MORE THAN ONE POINT
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Chart IV-2 1
IV- 19
850!3
lM.00
series resistance. The use of retrograde doping in the N-well serves the purpose of reducing the parasitic pnp gain and N-well series resistance by allowing a high peak doping concentration in the N-well (ref. 8). The use of a shallow retrograde well enables the use of a thin epitaxial layer, which in turn reduces the effective substrate resistance. The standard field boron implantation in turn reduces the parasitic npn bipolar gain. Chart IV-21 shows the parasitic bipolar gains for a deep sub-groundmle latch-up structure vs. temperature for a retrograde N-well, shallow epi-process. It is evident that such a technology enhancement will prevent latch-up at any operating temperature. 3.2.3
Technology
scaling
Contrary to initial notions, the migration to submicrometer technologies is less likely to cause L/U problems than >1.0 urn technologies. This is because the suggested modifications are oflen inherently built into the process in order to support high density submicrometer devices. 3.3
Single-Event-Upset
(SEU) Enhancement
Single event upset occurs in a storage element (RAM cell, Latch) if the collected charge (Qcol) exceeds the critical charge for upset (Qcrit ), Single event upset immunity therefore is achieved if Qcol(Max) < Qcrit The above inequality can be used to achieve SEU enhancement by limiting charge collection at circuit nodes, by improving circuit stability, or a combination of both.
3.3.1
Reducing Qcol
In the event of a charge particle hit to the circuit node, charge collection takes place in the depletion region as well as along the charge fhnnel created by the particle’s path (ref. 9). To limit the length of the fi,mnel, one may use epitaxial layers on top of heavily doped substrates, or isolated substrate technology, The fimnel will be truncated near the substrate-epi interface, thus limiting the charge collection to the epi layer (ref. 10). Thinning down the epi layer results in a corresponding reduction in charge collection. It is evident that the latch-up enhancement of thin epi and retrograde well also results in a single-event-upset enhancement. Up to an order of magnitude reducti~n in sofi error rate can be achieved by fabricating a commercial design on thin epitaxial substrates.
IV-20
3.3.2
increasing Qcrit
Several techniques have been developed to increase circuit Qcrit. They rely on capacitive hardening, resistive hardening or circuit hardening (ref. 11.12), The first two have an impact on circuit petiormance while the last generally occupies more area. Trade-off between these hardening approaches is presented in Chart IV-22 (ref. 12). Component SEU hardening can be achieved by replacing commercial storage elements (RAM cells and latches) with the hardened version. But can this be done without significant redesign or impact on system performance? An example of resistive hardening will be considered. Resistive hardening relies on decoupling of circuit nodes by high value (polysilicon) resistors that increase the RC time-constant in the cell (ref. 13). This has no impact on “read” performance since no switching is taking place during a “read” operation. The “write” operation however is significantly impacted, especially at low temperature due to the negative temperatures coefficient of high resistivity polysilicon. Chart IV-23 shows the effect of resistive hardening on the perilormance of a microprocessor operating at 25MHz. At 85°C the critical path delay of 36 ns is increased to 38 ns due to resistive hardening of RAM cells and Register Latches. As the temperature is reduced to-2@C, the switching times of RAM cells and Registers increase significantly; but they are more than compensated for by the speeding-up of the logic path. The 25 MHz performance is therefore preserved! This storage element substitution is straight forward in synchronous designs but require carefil timing analysis in asynchronous designs. 3.3.3
How Much Qcrit Is Enough?
There is a penalty to be paid for SEU over-protection. So, how much is enough? Chart IV-24 shows the integral particle flux at a geosynchronous orbit(ref 14). As is clearly evident, the flux drops off by orders of magnitude at LET -30 MeV. cmz/mg (LCT -0.3 pC/um). A Qcrit is enough if the circuit can tolerate a hit without upset from a particle with LET = 30 MeV.cm2/mg at an oblique angle (Chart IV-25). Qcrit > (0,3pC) (tepi) (See 8) Where tepi is the thickness of the epitaxial layer (in urn) and 0 is the angle of incidence of the particle path. A 9 = 60°-70° is normally adequate due to charge sharing with other nodes at a more oblique angle. With 2. 5um epi and 70° angle, Qcrit = 2.2 pC is adequate to guarantee SEU immunity in the space environment. The required Qcrit is presented in Chart IV-26 for various epi thicknesses and incident angles. 3.3.4
Technology
Scaling Effect
The effect of technology scaling on SEU sensitivity is a complex one. On one hand power supply voltage and nodal capacitances are reduced making circuits more sensitive to upset. On the other hand scaled circuits require thin epitaxial layers resulting in reduced charge collection; employ high drive current transistors compensating for the drop in supply voltage; and have
IV-21
SINGLE
O
HARDENING
EVENT
APPROACH
UPSET
COMPARISON
Hardening
Unhard
Requirement
Temp
Design-Hard
Latch
Added
Latch
(R = 500 K Ohms)*
Time
> 3.0 pc
1.0 ns
1.7 ns
8.5 ns
...
None
None
pc
(. O.3V)
Sensitivity . 125°C
(R .250
0.2
Qcrit Write
Time
Temp
= .55°C
pc
1.2 ns
> 3.0 pc
> 3.0 pc
2.1 ns
7.5 ns (R .1.0
0.2
Qcrit Time
pc
0.7 ns
> 3.0 pc
> 3.0 pc
1.2 ns
15.5 ns
...
None
Yes
Groundrule
Update
...
None
Yes
Latch
Penalty
...
< 40%
< 200/0
Process
Latch
Resistors*
> 3.0 pc
0.2
Temp
R-Hard
Devices
= 25’C
Vt Shift
Write
(EXAMPLE)
...
Qcrit
Write
(SEU) ENHANCEMENT
Complexity
Area
K Ohms)’
M Ohms)*
Chart IV-22 SINGLE
EVENT
UPSET
(SEU) ENHANCEMENT
PERFORMANCE IMPACT OF HARDENED LATCHES RHCMOS-E, 4.5V, W.C. PROCESS
Total
Cycle
Time
40
-~”---—
30
I
—
20
10
I 0
85
25
0
-.
-20
IJ
-
Logtc
Delay
1...:..: Cell
Write
Time
Chart IV-23
IV-22
~
Register
PropDly
FLUX AT ORBIT 2
INTEGRAL PARTICLE GEOSYNCHRONOUS
McV .
11[
Lll![hl{
[:!LRGY
lRNi5r[R,
L[l
‘j;
[—
cnl
mg
10‘ : -2 . 10
,.-3 :
-,1 : 10 ,.5
:.
1(1-6 . ,.-7
..
~o-8 :. ,.-9 ,.-1
~
u ‘. , ,.
-ul
lo-”~
m-s
4 10
10
10-1 10°
10-2
LItdrAR CIIARCETRAt4sFCR,LCT ..!!
,,,
(.,,,) !!
Chart IV-24
Gate 1 Source
Chart IV-25
IV-23
I
SINGLE EVENT UPSET (SEU) ENHANCEMENT
.
CONDtTION
FOR SEU IMMUNITY
REQUIRED
.
REQUIRED
(tepi) (SEC B)
Cnt
1.5 pm
2.0 pm
2.5 pm
60°
0.9 pc
12pc
1.5 PC
70°
1.3 pc
1.8 pc
2.2 PC
80°
2.6 pc
3.5 pc
4.3 PC
e \
NOTE:
Qcrit > (cM?C)
tepi
60°-700 OBLIQUE
PROTECTION ANGLES.
IS NORMALLY
ADEQUATE
DUE TO CHARGE SHARING AT
Chart IV-26
RADIATION
HARDENING
RISC SYSTEM
RESULTS
6000
RAD 6000
RAD 6000 (SEU)
TOTAL DOSE (Krad)
20
>2,000
>2,000
L/U LET (MeV/mg/cmA2)
50
IMMUNE
IMMUNE
SEU LET (MeV/mg/cmA2)
5
15
Chart IV-27
IV-24
>80
smaller upset cross sections. It is clear that as one migrates to smaller dimensions, it is important to look beyond the traditional circuits (storage elements) to assure SEU immunity. 3.4 Example: Radiation Hardening of a Commercial
Processor
The IBM RISC System 6000 32-bit processor is used to illustrate the hardening approaches discussed above. It represents the adaptation of a commercial high performance processor design for radiation applications (RAD 6000). The five part-number 1.Oum CMOS designs were fabricated in the radiation hardened technology, and substituted to the commercial devices on the workstation board. The workstation continued to operate at its rated frequency, even after 2Mrad irradiation. Chart IV-27 presents a comparison of hardness levels of the commercial processor and the RAD 6000, before and atler SEU enhancement.
3.4.1
Total Dose Response
Chart IV-28 and IV-29 illustrate the total dose response of the Fixed Point Processor (FXP), fabricated in the commercial, and radiation hardened technologies. The commercial part failed to operate beyond 20K rad due to loss of isolation; while the radiation enhanced part continued to perform through 2M rad with no increase in leakage or degradation in worst case delay. 3.4.2
Latch-Up Response
Even though the commercial FXP did not latch-up under heavy ion testing, the commercial Data Cash Unit (DCU) did at a LET of 50 MeV, cm’/mg. The RAD-6000 is immune to latch-up.
3.4.3
Single-Event-Upset
Response
Fabricating the processor in the RAD hard process in itself increased the LET threshold by a factor of 3, from 5 to 15 MeV. cm2/mg (Chart IV-30) and rendered the design immune to proton upset (Chart IV-3 1). The SEU hardened latch design increases the LET threshold firther to >80 MeV. cm2/mg. Chart IV-32 presents the sofl error performance (days between errors) of the three versions of the processor in various space environments. With 25mils of Aluminum shielding, the commercial processor is expected to experience 1 event every 13 days in the geosynchronous 90°/0 worst case environment, Fabricating the commercial design in the hardened process increases the time between events to 5 months; while replacing the latches with a design hardened version results in > 40years between events. Fabricating the commercial design in the rad hard processes. in itself, meets the requirement for most commercial space applications.
IV-25
Total
Dose
Response
- FXPT
Flush
Delay
I 1
------1----L–-4------J-..
I I
,.
320 -—-
1E+o
I
,,, ,.
I I
!
E+l
7 ,1.
.
1E+3
1E+6
1E+7
Dose
Process L-H
Hardened Process H-L m
T
~~
.,
1E+5
Accumulated
COTS L-H COTS H-L Hardened
,:
Tom Scott 4194
Chart IV-28
Total I
Dose
Response
- FXPT
Idd(stdby) I
I
+
COTS m Hardened Process A
----
j
____j+
---
[
~
,
-
~
;--
, :, 1 _.j____
~ 1
I I 1
1
I
I
I
I ‘. 1
, I
.---— —-——-—–-7-
-—.
.
—
[ A +
Accumulated
Dose
Tom Scott 4194
Chart IV-29
IV-26
—
RISC 6000 Heavy
Ion Upset
Test
Results
3E43
I .
1E-8
.—.-r
___
-—
;
COTS
L-l
_____
Hardened Procese
+
?
‘
—.
~“ _. . –-_
➤
3E-11 p--
IF-11 .-. .
0
40
20
60
80
LET(MeV/mg/cmA2) Tom Scott 4194 Chart
IV-30
RISC 6000 Proton Upset
Test
Results
lE-13
5E-14
—--
= ~ 3E-14 r
-
I
~~ -~ ---------
–
&
I
s
~ lE-14 z g 5 3
.-T.—-- —-. —______ 2E-15
-
m +
lE-15 20
40
60
80 100 Proton Energy(Me~
Tom .%it 4/94
Chart IV- 31
IV-27
120
140
160
I
RISC 6000 SER Response IE+12
1E+1O
1E+a
1E+6
I 1
1E+4
1
1E+2
A 1
I
I
lE+O 1 ‘ “–5~OK 27Deg
500K 57Deg
500K 90Deg
Geo(O.1”)
Environment COTS
Hardened Proceas
Enhanced Hardened PMaa
~~
.
Chart IV-32
lV-28
I Geo(O.025”)
4 Conclusion Commercial technologies are finding their way to radiation hardened applications. We must not underestimate the amount of trouble a user can get into if he uses such technology indiscriminately, without paying a carefil attention to the true performance of such technology in the intended use environment. An apparent cost savings during the planning phase of a mission may end-up costing the mission itself. Some state-of-the-art commercial technology is suited for radiation tolerant applications due to the incorporation of hardening techniques to prevent latch-up; others require significant modifications. We discussed techniques that allow us to adapt commercial technologies, while preserving basic technology parameters, in order to capitalize on significant investments in design, operating systems and software.
IV-29
References: 1. 2. 3. 4, 5. 6. 7, 8. 9.
10. 11. 12. 13. 14.
J.M. McGarrity, IEEE Trans. Nucl. Sci., NS-27, 1739 (1980 D.M. Fleetwood, et. al., “Accounting for Dose-Enhancement effkcts with CMOS Transistors”, IEEE Trans. Nucl. Sci, Vol NS-32, No. 6, Dec. 1985 J.R. Schwank, P.S. Winoker, P. J. McWhorter, F. W. Sexton, P. V. Diessendorfer, and D. Turpih, IEEE Trans. Nucl. Sci,NS-31 (1984) L. Lipkin, S. Hyland and T. Craigo “Effect of Key Processing Stepson Post Radiation Midgap Voltage”, Journal of Electrochemical Society, Vol 140, No. 10, Oct. 1993. N. Haddad, W. Henley, and C. Schier, “A Radiation Hardened Half Micron Technology”, 1988 GOMAC Digest McLean, E, B, and Oldham, T. R. “Basic Mechanism of Radiation Effects in Electronics Material and Devices”, HDL-2129 (Sept. 1987) Haddad, N. F. “Consideration for the Development of Radiation Resistant Devices and VLSI Circuits”, Journal of Electronic Materials, Vol. 19, No. 7, 1990. Y. Taur, et. al., “A Self-aligned 1urn Channel CMOS Technology with Retrograde N-well and Thin Epitaxy”, IEEE Trans. Electron Devices, Vol, ED-32, 1985. C. M. Hsie~ et. al., IEEE Trans. Electron Devices Lettes, EDL 2, 103 (1981) J. G. Rollins, et. al., “Cost Effective Numerical Simulator of SEU”, IEEE Trans. Nut. Sci, Vol. 35, No. 6, Dec. 1988. S, Diehl, et. al., “Consideratons for Single Event Immune VLSI logic”, Trans, Nucl. Sci., Vol. NS-30, No. 6, Dec. 1983 L. R. Rockett, Jr., “An SEU-Hardened CMOS Data Latch Design”, Trans. Nucl. Sci., NS-35, 1988. J. L. hdrews, et. al., “Single Event Error Immerse CMOS RAM”, IEEE Trans, Nucl. Sci, Vol. NS-29, Dec. 1982. E. Peterson, et. al., Trans. Nucl. Sci, Dec. 1982.
IV-30
1994 NSREC SHORT COURSE
SECTION
V
W~GLE-EVENT EFFECTS IN SYSTEMS USING COMMERCIAL ELECTRONICS IN H~SH ENVIRONMENTS
EUGENE NORMmD BOEING DEFENSE AND SPACE GROUP
SINGLE
EVENT
EFFECTS IN SYSTEMS USING ELECTRONICS IN HARSH ENVIRONMENTS TABLE OF CONTENTS
1.
INTRODUCTION
2.
ENVIRONMENTS
2.1
SPACE
2.2
2.3
2.1.1
Galactic Cosmic Rays
2.1.2
Trapped Belt Radiation
2.1.3
Solar Energetic Particles
ATMOSPHERE 2.2.1
Neutrons
2.2.2
Charged Particles
MAN-MADE SOURCES 2.3.1
Nuclear Reactor
2.3.2
Radioisotopic Sources
2.3.3
Accelerators
3.
SINGLE EVENT EFFECTS
3.1
TYPES OF EFFECTS
3.2
3.3
3.1.1.
Upset (Single, Multiple Bit)
3.1.2
Latchup (large current, mini-latch)
3.1.3
Burnout and Gate Rupture
3.1.4
Single Event Induced Hard Errors
CALCULATING
EFFECT RATES
3.2.1
Heavy Ions
3.2.2
Protons and Neutrons
EXAMPLES OF SEE RATES IN HARSH ENVIRONMENTS 3.3.1
Space
v-1
COMMERCIAL
TABLE OF CONTENTS (Continued) 3.3.2
Atmosphere
3.3.3
Man-made Sources
4.
SYSTEMS CONSIDERATIONS
4,1
PROBABILISTIC NATURE OF SEE
4.2
ACCEPTABILITY OF EFFECT RATES FOR DESIGN 4.2.1
Determination of SEU and SEL Acceptability
4.2.2
SEU Impacts
4.2.3
SEL Impacts
4.2.4
Statistical Treatment of SEE
5.
ACKNOWLEDGMENTS
6.
REFERENCES
v-2
SINGLE
EVENT
EFFECTS IN SYSTEMS USING ELECTRONICS IN HARSH ENVIRONMENTS
COMMERCIAL
LIST OF TABLES
v-1
Normalized Elemental Abundances of Solar Energetic Particle Events.
v-2
Comparison of Proton Fluences for Large 1989 SEP Events as Measured by Two Different Spacecraft
v-3
Ratio of Protons to the Total Penetrating Component in the Atmosphere
v-4
Simplifying Assumptions Used in Calculating the Heavy Ion SEE Rate
v-5
Compilation of p-Channel Power MOSFETS Based on Susceptibility to Gate Rupture
V-6
Comparison of Measured and Predicted Single Event Upset in Various Devices within the Microelectronics Package on the CRRES Satellite
V-7
Comparison of Measured and Predicted Single Event Upset in Hitachi SRAMS aboard UOSAT Satellite
V-8
Examples of Multiple Independent Upsets, MIU (Cross Chip Upsets at Essentially the Same Time)
v-9
Examples of Consecutive Multiple Bit Upset in Space
v-lo
Measured In-Flight Occurrences of Single Event Upset (SEU)
V-n
Comparison of Upset Rates in 1 Mbit SRAMS Measured in WNR and as Calculated
v-3
SINGLE
EVENT
EFFECTS IN SYSTEMS USING ELECTRONICS IN HARSH ENVIRONMENTS
COMMERCIAL
LIST OF FIGURES
v-1
The measured abundances of the elements, relative to carbon, in the galactic cosmic radiation (GCR, solid line), compared to the solar system abundance (dotted line) [4]
v-2
Galactic cosmic ray
v-3
The 8-27 MeV/nucleon oxygen flux horn 1%8-92 based mainly on Caltech experiments on IMP-7 and 8 (black dots). The 1992 data (open dots) are scaled from MAST/SAMPEX measurements. The continuous curve is the ML Washington neutron monitor rate scaled according to a formula in [8].
v-4
World-wide map of iso-rigidity lines [9]
v-5
Schematic representation of the effect of the geomagnetic field on the GCR environment as functions of particle rigidity and orbital inclination. The top three spectra represent the GCR spectrum outside the earth’s magnetic field. The second set of figures shows the orbit-averaged geomagnetic transmission factor which is a function of rigidity and orbit inclination. The lowest curves show the result of convolving the two upper sets of curves, and is the orbit-averaged exposure as a function of rigidity for 0°,30° and 50° inclination orbits [10]
V-6
The earth’s proton radiation belts according to the AI-%model. The averaged omnidirectional fluxes are shown [12].
v-7
The inner trapped belt flux in the area of the South Atlantic Anomaly (SAA) for protons of energy> 30 MeV [13].
V-8
A simplified picture of the 1991 injection event. The positive and negative particles move around the earth in opposite dimztions, and as they move, they spread out because of differing energies [14].
v-9
Three panels showing the radial profiles before during and after the 1991 injection event for protons (20-80 MeV) and electrons (> 13 MeV). The first panel is immediately before the event, the second is during and the lowest is 6 months afterwards. The change in the population of energetic protons and electrons due to the injection event is evident, as is its decay over time [14].
v-lo
The geographic distribution of oxygen ions (> 15 MeV/nucleon) observed on MAST/SAMPEX (82° orbig -600 km). Three types of symbols are used: diamonds (events with a rigidity above that estimated for vertical oxygen with q = 6); asterisks (those with an energy less than estimated for q = 1.5) and circles (those with intermediate rigidities). The oxygen ions trapped in the SAA are consistent with their originating as anomalous cosmic rays (q = 1) [19].
energy spectra of the more abundant elements near the earth. Below a few GeV/nucleon, the spectra are strongly influenced by the solar modulation. For the same spwies, the highest intensity curve occurs at solar minimum conditions and the lowest intensity curve at solar maximum conditions [5]
v-4
LIST OF FIGURES (Continued) V-II
Pictorial representation of solar emissions from a solar flare. The time ~ales for the various emissions to reach the earth are also shown [9].
V-12
Conceptual figure illustrating solar proton propagation from the sun to the earth. The coronal propagation distance from the site of the flare on the sun to the location of the favorable propagation path for solar particles to reach the earth is shown by the arc connecting to the two solar location arrows. [nterplanetiiry propagation proceeds along the Archimedean spiral path from sun to the earth [9].
V-13
Relative time scales of solar particle emission (at lAU). The increase in particle flux at the time of the arrival of the interplanetary shock is from additional acceleration of the ambient particle flux caused by particle interaction with the shock [9].
V-14
Partial ionization state of solar flare heavy ions in terms of the reduction in the effective Z of the ions [20, 49].
V-15
Comparison of integral proton fluences J(z E) for worst-case solar energetic particle event [22,25].
V-16
Peak 1989 were 1956
V-17
Differential and integral fluxes for protons and alpha particles for the Sept. 29, 1989 and Oct. 19, 1989 solar energetic particle events bawd on GOES measurements and the acceleration model [25, 28, 29].
V-18
Spectrum of the average differential neulron flux in the atmosphere at 40,000 ft- and 45° latitude based on the measurements of NASA-Ames and normalized to a 1-10 MeV neutron flux of 0.85 n/cm2 sec [32,36].
V-19
The 1-10 MeV atmospheric neutron flux as a function of altitude based on aircraft and balloon measurements [35].
V-20
The 1-10 MeV atmospheric neulron flux as a function of
proton integral fluxes for three ground level event solar flares, Feb. 1956, Sep~ and June 1991. Satellite and ground-based neutron detector measurements used for the 1989 event and balloon and ground-based measurements for the event [9, 25,26, 135]
atmospheric
dep*
(gmkm2)
basedon balloonmeasurements(Holt)andcalculations(ArmstrongandWilsonNealy) [33, 35] V-21
The 1-10 MeV neutron flux as a function of geographical latitude based on aircraft neutron measurements and the vertical rigidity cutoffs of Smart and Shea [33].
v-22
The longitudinally averaged rigidity cutoffs at 65,000 ft. as a function of geographical latitude [33, see Fig. V-4]
V-23
Correlation of the inflight SEU rate in the IMS 1601 SRAM with atmospheric neutron flux as a function of altitude. The SRAM was operated at 2.5V [32].
V-24
Correlation of the inflight SEU rate in the lMS 1601 SRAM with atmospheric neutron flux as a function of geographical latitude. The SRAM was operated at 5V [33].
v-5
LIST OF FIGURES (Continued) V-25
Correlation of the energy deposition spectrum in the CREAM detector flown on Concorde with the spectra measured in silicon surface barrier detectors (SBD) exposed to the WNR beam. The CREAM detector has a 172 Lm depletion thickness and the main SBD, 300pm [37, 117].
V-26
Comparison of the neutron spectrum at the Weapons Neutron Research facility (WNR) of Los Alamos National Lab with the atmospheric neutron spectrum [1 17].
V-27
Comparison of ground-level atmospheric neutron spectra with the spectrum of neutrons at 40,000 ft. [118, 136].
V-28
Comparison of measured and calculated differential energy spectra of atmospheric vertical protons at altitudes of -16-18 km (52,000 -59,000 ft.) for various geomagnetic cutoffs. The three sets of measurements by Bogomolov are for rigidity cutoffs of 0.4-0.5 GV, 0.3-4 GV and 6.9-7.4 GV (high, middle and low plots respectively). The four calculated curves by Aitbaev et al., are for cutoff rigidities of 0.5 GV, 3 GV, 5 GV and 7 GV, curves 1-4 respectively (100 .gm/cm2--53,0W ft.) [35].
V-29
The vertical proton intensity in the atmosphere as a function of atmospheric depth for protons with E>l GeV [35].
V-30
Ratio of the charged pions to protons in the atmosphere as a function of energy at depths of 500,700 and 1000 gm/cm2 (20,000, 12,000 and 1000 ft.) for a pion interaction mean free path of 100 gm/cm2 [35].
v-3 1
Differential flux of stopping nuclei in the atmosphere detected in nuclear emulsions for charges 6< Z <9 as a function of atmospheric depth [35].
V-32
Differential flux of stopping nuclei in the atmosphere detected in nuclear emulsions for charges Z z 10 as a function of atmospheric depth [35].
v-33
Comparison of charged particle LET spectra measured with CR-39 on high altitude, high latitude aircraft (ER-2) and on three different Space Shuttle missions [31].
v-34
Comparison of differential neutron spectra for four different neutron environments, all normalized to 1 n/cm2 (Ezl MeV) [36,43].
v-35
Cutaway drawing of the General Purpose Heat Source (GPHS) Radioisotope Thermoelectric Generator (RTG) [44).
V-36
Differential neutron spectrum measured at the KEK Proton Synchrotrons (detector position B-3) [47].
v-37
Differential neutron spectrum measured at the TNF (beam stop) of the 500 MeV TRIUMF proton accelerator [48].
V-38
Differential neu~on spectra measured at two locations around the TEVATRON 800 GeV proton accelerator [58, 59].
V-6
LIST OF FIGURES (Continued) v-39
Heavy ion SEU cross section for the IMS 1601 SRAM, as measured, using a 3-part stair step fit and using a least-squares Weibull fit (60= .688, Lo = 1.28, s = 1.729 and W = 13.39) [33].
V-4)
Comparison of heavy ion upset predictions and flight results for six different microelectronic devices flown on CRRES [109].
V-41
Comparison of observed and predicted SEU rates in general purpose computer (GPC) onboard Shuttle in a) South Atlantic Anomaly - protons only and b) other portions of the orbit - GCR only [120].
V42
Comptison [120].
of observed and predicted upsets in Space Shuttle main engine controller
v-7
SINGLE
EVENT
EFFECTS IN SYSTEMS USING ELECTRONICS IN HARSH ENVIRONMENTS
COMMERCIAL
Eugene Normand Boeing Defense & Space Gm.qI, Seattle, WA 98124-2499 1.
INTRODUCTION
This course will deal with single event effects (SEE) in commercial electronics that are being used in harsh environments. While the effects occur in individual components, their impacts are experienced by the specific systems within which the components are used. This course will focus on three main aspects of this overall problem: the environment, calculating the rate of the effects within the environment, and systems considerations of SEE. The environment section will significantly expand upon the widely accepted ideas of which radiation fields constitute potential threats to induce single event effects. Particular attention will be paid to a variety of neutron environments capable of inducing SEE. The effect rate section will not only update the conventional approaches to calculating SEE rates with the most recent refinements, but also present methods appropriate to neutron environments, as well as those being used in the design of the Space Station electronics. The systems considerations section will provide information showing how SEE rates on the parts level can be used to assess and mitigate impacts on the system. 2.
ENVIRONMENTS 2.1
SPACE
The first environment in which single event effects were experienced was space. In 1975 Binder, et al., [11 discovered that anomalies in J K flip flop circuits in a communications satellite could be attributed to energy deposited by cosmic ray heavy ions. This was the first observed case of single event upset (SEU) but many more quickly followed. In 1978 Pickel and Blandford showed that errors occurring in the dynamic MOS RAMs of a satellite system could also be explained as SEU [2]. A year later Sivo, et al., [3] showed that the same SEU mechanism was responsible for soft errors in static MOS memory devices, a CMOS RAM and PMOS shift register in the Voyager and Pioneer-Venus spacecraft. Since then a wide variety of single event effect occurrences in space- craft are reported each year at the IEEE Nuclear and Space Radiation Effects Conference. Even today space is the environment in which the vast majority of SEE events has been recorded, but effects have also been seen in other environments. There are three major portions of the space radiation environment that can cause SEE: galactic cosmic rays (GCR), trapped belt radiation and solar energetic particles (SEP) which are sporadically emitted by the sun and colloquially referred to as solar flare particles. 2.1.1
GALACTIC
COSMIC
RAYS
The galactic cosmic radiation is composed of atomic nuclei that have been ionized and subsequently accelerated to very high energies. Galactic cosmic rays consist of about 83% protons, 16% alpha particles and K 2% heavy ions. These percentages vary depending on factors
V-8
such as solar activity (minimum or maximum conditions) and the energy range of the particles (MeV/nucleon). Fig. V-1 shows the relative abundance of all elements from hydrogen to iron based on satellite measurements of the GCR ions near the earth (solid curve). [.41. Heavy ions, occasionally referred to as H’ZE (high Z, high energy) particles, refer to all ions with atomic number, Z, > 2. As seen in Fig. V-1, the major HZE ions are C, N, O, Ne, Mg, Si and Fe. From the SEE perspective, Fe is often considered the most important ion because it has the highest linear energy transfer, LET, in silicon. The energy spectra of the dominant ions is shown in fig. V-2 [5]. Several curves are shown for each ion indicating the effect of solar modulation (upper curve for solar minimum, lower curve for solar maximum). It is also clear that all the ions have very similar energy spectra. The cosmic rays too can be subdivided into two groupings. The classical cosmic rays, GCR, which originate outside of the solar system, and the anomalous component. The GCR ions are all full y stripped of their electrons, thus their charge is identical to their atomic number, +-z. lo-
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I
242=2s .
.m.
Figure V-1. The measured abundances of the eiements, relative to carbon, in the galactic cosmic rad~ation (GCR, solid line), compared to the solar system abundance (dotted line) [4]
v-9
+=f?fi”n”u’” .-
7t=’-
lo-
ICINETICENEROY(GW/nucleon)
Figure V-2. Galactic cosmic ray energy spectra of the more abundant elements near the earth. Below a few GeV/nucleon, the spectra are strongly influenced by the solar modulation. For the same species, the highest intesnity curve occurs at solar minimum conditions and the lowest intensity curve at solar maximum conditions [5]
The anomalous component comprises only a very small portion of the GCR and extends only over the low energy range of 1-70 MeV/nucleon. The anomalous costnic-ray, ACR, component was discovered following the last years of the 20th solar cycle (1964-1975) when anomalies were found in the low-energy cosmic ray background [6]. Certain ions, such as helium and carbon were at levels as much as 10 times higher than expected for energies of- 10 MeV/nucleon. These ACR ions were found to be essentially singly ionized [7], and are observable near the earth only at the time of solar minimum conditions. They are thought to be created when interstellar neutral gas approaches the sun and is ionized by solar ultraviolet emissions or the solar wind. These ACR ions attain their higher energy through interplanetary acceleration processes such as the solar wind termination shock. ACR ions which show the anomalous increase in flux above the low energy GCR spectrum include He, C, N, O, Ne and Ar. The flux of 8-27 MeV/nucleon
v-lo
oxygen ions (observed near the earth) over the years 1968-92 is depicted in fig. V-3 [8] and clearly shows the rise in oxygen abundance level and its correlation with solar cycle [Note: 1954, 1965, 1976, 1986 and 1995 are the approximate endpoints of the last five solar cycles, cycles 1822, and therefore the times of minimum solar activity.] 10-3-
I
I
I
I 1
I
r
1 I
I I
1
I
1 AU Oxygen
8 -
I
I
I
I
I
I
I
I
I
1
I
I
27 MeV/nuc
3X1 O-’ l--
N II , 1“! 10-’
~
I
1968
I
I
1970
I
t 1972
I
I 1 I 1 I 1 I 1974 1976 1978 1980
1
I
I 1982
1984
1
1986
I
I
1988
I
t
1990
1992
I
Year
Figure V-3. The 8-27 MeV/nucleon oxygen flux from 1968-92 based mainly on Caltech experiments on IMP-7 and 8 (black dots). The 1992 data (open dots) are scaled from MAST/SAMPEX measurements. The continuous curve is the Mt. Washington neutron monitor rate scaled according to a formula in [8].
At geosynchronous orbit (often referred to as geo which is approximately 36,000 km or 6 earth radii), the earth’s magnetic field is weak enough that for all practical purposes it can be considered as having a negligible effect on the GCR ions. The GCR intensity varies as it is modulated by the interplanetary medium. The complex radiation transport involved has been modeled through the fokker-planck equation for the modulated particle number density which is expressed as a factor of the heliocentric radius and particle energy. The GCR flux increases with increasing radial distance from the sun but near the earth, i.e., at 1 au, the gradient is < 10% [5]. With respect to its variation over time, the solar wind modulates the GCR flux inversely with the 11 year solar cycle, i.e., They are anti-correlated. As shown in fig. V-2, their variation can be a factor of 4-8, depending on the ion and its energy. The “frozen-in” magnetic field irregularities within the solar wind are mainly responsible for this modulation. Disturbances in this magnetic field, such as those associated with solar activity during solar maximum conditions, makes the propagation of the GCR particles more difficult i.e., the particles can be scattered out more effectively. Conversely, during the quieter solar wind magnetic field conditions associated with solar minimum, the GCR particles can more easily reach the inner solar system.
V-n
The earth’s magnetic field shields incoming charged GCR particles. Depending on the particle’s energy, E, mass, m, and charge, q, the distance that the particle can penetrate down to the earth may not be all the way to the surface. This ability to penetrate the geomagnetic field is determined by the GCR particle’s momentum divided by its charge which is called the particle rigidity, P,
1
P = &Tzz
(1)
The rigidity is typically expressed in MV or GV. For every point in the magnetosphere, and for each direction at that point, there exists a rigidity called the geomagnetic cutoff rigidity, below which cosmic ray particles cannot penetrate. For GCR particles with rigidities greater than a particular cutoff, the particles can arrive without any shielding by the magnetic field. Regions in the outer magnetosphere and near the poles can be reached by particles with much lower rigidities than near the earth’s equator. For low earth orbit, the ACR ions, with a charge of +1, become more important relative to the +Z charged GCR ions, because of their greater ability to penetrate the geomagnetic field, i.e., higher rigidity. Cutoff rigidities around the earth have been measured and fig. V-4, from Shea and Smart , [9] show how they are distributed. Fig. V-5, also from Smart and Shea [10] shows how effective the geomagnetic shielding can be for three different 400 km orbits, those having inclinations of 0°, 30° and 50°. Each orbit has a different geomagnetic transmission factor based on the rigidity of all points along the orbit. When the transmission function is folded in with the GCR rigidity spectrum, three significantly different orbit averaged GCR fluxes result (fig. V-5, bottom panel). EPOCH = 1980.0 9“” ~-’
1
r
I
1 .—
.=X?
,
1 -
-~--l~ ;
.-
.:.
7
I 4
.,o;wk~.—~,oo
60” WEST
Figure V-4.
30” LONGITUDE
EAST
World-wide map of iso-rigidity lines [9]
V-12
j . m 0“
INCLINATION
30” INCLINATION
..”<” @ SO* INCLINATION
10-’ I 0-3
COSMIC RAY
7 L -@!_-CLn
DIFFERENTIAL RIGIDITY SPECTRUM
IO“g
#
t
#
ORBIT AVERAGED GEOMAGNETIC TRANSMITTANCE
Oa 10-{ I
10-’ , ()-3
10-g
ORBIT AvERAGED COSMIC RAY EXPOSURE
II
I
10 100
I
10 100
RIGIDITY
,
I
m\
10 100
(GV)
Figure V-5. Schematic representation of the effect of the geomagnetic field on the GCR en~ironment as functions of particle rigidity and orbital incfinatio~. The top three spectra represent the GCR spectrum outside the earth’s magnetic field. The second set of figures shows the orbit-averaged geomagnetic transmission factor which is a function of rigidity and orbit inclination. The lowest curves show the result of convolving the two upper sets of curves, and is the orbit-averaged exposure as a function of rigidity for 0°,30° and 50° inclination orbits [10]
2.1.2
TRAPPED
BELT
RADIATION
Charged particles revolving around the earth interact with the earth’s magnetic field. The net result is that these particles become “trapped” by the magnetic field. The details of the magnetic field and electric field interactions are available in numerous sources (11] (see also “Basic Mechanisms of Radiation Effects in the Natural Space Environment,” this short course). Two persistent belts of charged particles, have been created, an inner belt, consisting of protons and electrons and an outer belt of electrons. At least that had been the picture until about 1991. The trapped belt protons can induce SEE but the electrons cannot, so we shall focus only on the protons. Based on satellite measurements during the 1960’s, models were developed for
V-13
describing the spatial distribution of the trapped protons. The latest of these models is AP-8 [12] and it has remained the NASA standard for about 15 years. The AP-8 model gives average omnidirectional proton fluxes at various energies in the range 50 keV -500 MeV. In actuality there are two models, one for solar minimum AP-8 MIN and one for solar maximum, AP-8 MAX. These two differ only for altitudes K 1000 km. Fig. V-6 shows the distribution of the proton flux (E> 10 MeV) in space as given by AP-8 MIN. [ 12]. Time-dependent variations of the proton fiuxes, such as are due to geomagnetic storms or solar modulations, are not included. The model is stated to have an uncertainty factor of 2. Below about 10OOkm, the main trapped proton beIt consists primarily of those protons within the South Atlantic Anomaly (SAA) where the geomagnetic field abrupt]y becomes much weaker. Fig. V-7 shows the isoflux lines for protons of energy >30 MeV at an altitude of 500 km. [ 13].
1.0
*
I
1.0 AP8FWJPROTONFLUXES (cm-2 .sec-1] 1.0
above 10 MeV
2*O
3.0
410 X(Re)
I
Figure V-6. The earth’s proton radiation omnidirectional fluxes are shown [12].
belts according
V-14
to the AP8 model.
The averaged
0° qno
A
1oh
10
# 1
1
70W
50W
10W 30W Longitude
,
o“ 10E 20E 30E
Figure V-7. The inner trapped belt flux in the area of the South Atlantic Anomaly (SAA) for protons of energy> 30 MeV [13].
There have been two very recent changes to our picture of the trapped radiation belts, the introduction of an intermediate belt and the discovery of trapped heavy ions. The new “middle” belt was discovered by the CRRES satellite launched in July, 1990 into a highly elliptical orbit. On March 22, 1991, two solar flares, both x-ray and solar energetic particle events, occurred 4 hours apart. About a day later, while the energetic particles were in the vicinity of the earth, a strong shock in the solar wind arrived. It injected the protons and electrons forming a new intermediate trapped radiation belt (see Fig. V-8) [14]. After its creation, the new belt contained protons, in the 20-80 MeV energy range, about 1000 times that of the inner belt protons, as shown in Fig. V-9. After about 6 months, the new belt had decayed by about a factor of 10 [14]. The injection event may have been a unique occurrence, but our understanding of the processes that go into the formation, evolution and decay of radiation belts is currently inadequate to determine this.
V-15
.
Particle
Electrons
Injection Region
/
1
Protons
Figure V-8. A simplified picture of the 1991 injection event. The positive and negative particles move around the earth in opposite directions, and as they move, they spread out because of differing energies ~14].
V-16
p 20-80
Mev
104 }
1.00
/
1.50
2.00
2.50
3.00
3.5o
4.00
4.5o
1.00
1.50 2.00
2.50
3.00
3.50
4.00
4.50
L
L
CRRES ORBIT 1001
DAY 2S7
1991
105 ~
p 20-80
104 -t
1.00
e > 13 Mev
A
1.50
Mel
2.00
2.50
3.00
3.50
4.00
4.50
L
Figure V-9. Three panels showing the radial profiles before during and after the 1991 injection event for protons (20-80 MeV) and electrons (> 13 MeV). The fkst panel is immediately before the event, the second is during and the lowest is 6 months afterwards. The change in the population of energetic protons and electrons due to the injection event is evident, as is its decay over time [14].
Regarding the trapped heavy ions, Blake and Friesien were the first to suggest a mechanism for trapping ACR ions in the magnetosphere [15]. As indicated previousl y, ACR are singly charged ions. When such an ion with a rigidity slightly above the geomagnetic cutoff penetrates into the magnetosphere and loses some or all of its remaining electrons within the upper atmosphere, its resulting rigidity is suddenly below the cutoff and it is trapped, At least three separate research groups have independently found evidence of trapped heavy ions. Grigoreo, et al., [16] analyzed passive detectors flown on the COSMOS spacecraft during the 1985-88 solar minimum period
V-17
and found ions with 5-30 MeV/nucleon with a composition, angular distribution and time behavior consistent with an ACR origin, however the spatial distribution of the ions could not be measured. The Chinese satellite, Fengyun- 1B, in polar orbit (99° inclination) at 900 km was launched in September, 1990. It contains a Cosmic Ray Composition Monitor designed to measure protons and alphas as well as the ions C, N, O and Fe, all in the energy range 4-23 MeV/nucleon. Alpha particles and the four ions were measured every day during passes through the South Atlantic Anomaly [17]. The measured annual alpha fluence of 7E3 alpha/cm2 for 4-23 MeV/nucleon [17] compares favorably with the annual alpha fluence of 9E3 alpha/cm2 that can be derived for the same orbit from the trapped belt alpha fluences tabulated by Stassinopolous and Barth (for average energy of 13.5 MeV/nucleon) [18]. The fluxes of the C, N, O and Fe ions measured on Feng yun- 1B were about a factor of 3-5 lower than the alpha flux. Most recently measurements by the Mass Spectrometer Telescope (MAST) on the Solar Anomalous and Magnetospheric Particle Explorer (SAMPEX) have also indicated the presence of trapped O ions in the SAA [191. Oxygen ions with >15 MeV/nucleon were measured and found to comprise three distinct groups: a) at high geomagnetic latitudes there is a mixture of GCR (almost fully stripped, q = 6) and ACR (q = 1.5) ions, b) at mid latitudes GCR ions are not allowed but some ACR O ions are uresent and c) at low latitudes (the SAA) there are low enerpv singly-ionized ACR oxygen [19]. ~his distribution is shown in F~g.V- 10. ‘ -—m.
b
,
,
I
,
* . . . . . . .
. . . . . . .
. . . . ..m.
.
.
Figure V-10. The geographic distribution of oxygen ions (> 15 MeV/nucleon) observed on MAST/SAMPEX ~82°-orbit, - 600 km). Three ~yjes of symbols are used: diamonds (events with a rigidity above that estimated for vertical oxygen with q = 6); asterisks (those with an energy less than estimated for q = 1.5) and circles (those with intermediate rigidities). The oxygen ions trapped in the SAA are consistent with their originating as anomalous cosmic rays (q = 1) [19].
V-18
2.1.3
SOLAR
ENERGETIC
PARTICLES
For more than 40 years it has been known that during sporadic events the sun can accelerate particles to very high energies. These events are called by a variety of different names including solar cosmic ray events, solar energetic particle (SEP) events, solar proton events, polar cap absorption (PCA) events and ground level events (GLEs). The solar flare process in which very strong magnetic field interactions on the sun leads to large and sudden electrotnagnetic emissions, is generally considered to be the source of the SEPS. During a flare x-ray and radio frequency emissions reach the earth in about 8 minutes (see Fig. V-11) [9]. The solar energetic particles take much longer to reach the earth, usually on the order of an hour. The path and duration of these particles depends on their energy and the location of the flare relative to the arrival point. X-rays travel in a straight path since they have no charge, but protons and ions, being charged particles, spiral along the interplanetary magnetic field lines between the sun and the arrival point (see Fig. V-12).
/
/
///:’
p’--)! v
//
“
Figure V-11. Pictorial representation of solar emissions from a solar flare. The time scales for the various emissions to reach the earth are also shown [9].
V-19
Figure V-12. Conceptual figure illustrating solar proton propagation from the sun to the earth. The coronal propagation distance from the site of the flare on the sun to the location of the favorable propagation path for solar particles to reach the earth is shown by the arc connecting to the two solar location arrows. Interplanetary propagation proceeds along the Archimedean spiral path from sun to the earth [9].
Following a flare, the sun releases enhanced solar plasma into the interplanetary medium. This dense plasma takes 1-3 days to reach the earth. When it does, it interacts with the earth’s magnetic field, giving rise to geomagnetic disturbances and aurora. The extent of these magnetic disturbances varies greatly, depending on both the interplanetary plasma and magnetic field characteristics at the time of the shock arrival. When the shock arrives, it can severely disturb the ambient particle environment, re-accelerating solar energetic particles or even injecting protons and electrons into a new trapped belt, as was previously discussed. The arrival times of some of the key components, and the effect of the shock are shown in Fig, V-13 [9].
V-20
104r
PROTONS > 2oM@V ,.3
RELATIVF UNITS
Iw
)
II
, \i,
t
ll,ll
10
I TIME (hours)
1
H
1 I 1
1111
1
\
1
I
100
10AY 2DAYS
i 1 WEEK
Figure V-13 Relative time scales of solar particle emission (at 1AU). The increase in particle flux at the time of the arrival of the interplanetary shock is from additional acceleration of the ambient particle flux caused by particle interaction with the shock [9].
Compared to the GCR composition, the SEP composition is even more heavily dominated by protons which constitute > 98%, with about 1.5% alpha particles and heavy ions K O.1%. There is no widely accepted definition of “normal” composition of SEP ions, or any certainty that a “normal” composition exists. Each SEP may have unique composition dependent on many factors, but there appears to be good correlation between SEP abundancesand solarspectroscopic abundances [20 }. Table V-1 lists four separate such tabulations that are in relatively good agreement with one another [9]. Regarding the heavy ion portion, there is now considerable evidence indicating that the heavy ions are only partially ionized, i.e., having a charge state somewhere between fully stripped, like the GCR, and singly ionized like the ACR. By using some of the available data sets [20, 49] and plotting the reduction in effective charge as a function of Z, a useful quadratic fit can be obtained for the charge reduction factor (see Fig. V-14). It should be noted that the data in these curves is based mainly on low energy ions, e.g., 1 MeV/nucleon, however recently Adams has shown that the charge state for Fe is the same at 600 MeV/nucleon [21], and so the reduced charge state appears to be independent of energy.
V-21
0
0 0
5
10
15
20
25
30
Z of Ion Figure V-14. Partial ionization state of solar flare heavy ions in terms of the reduction in the effective Z of the ions [20, 49]. For applicability to single event effect calculations, the main concerns are the flux of particles at the peak of the-event ~nd the fluence over the duration of the event. SEP protons have been measured directly, by satellite-borne instruments since the early 1960’s, and for about 10 years before that, indirectly, using terrestrial instrument readings (cosmic ray neutron detectors and radio wave absorption riometers). Satellite-borne proton measurements are clearly preferred, but the full spectrum out to at least 500 MeV/nucleon is needed to support SEE calculations. High energy data is infrequently provided because most proton telescopes were not designed to measure in this region. For astronomical purposes the standard characteristic to describe in SEP is the proton flux for energies >10 M;V, but for SEE purposes this is inadequate because 10 MeV protons are completely shielded by as little as 25 roils of aluminum.
v-22
Table V-1. Normalized Elemental Abundances of Solar Energetic Particle Events [9].
z 1 2 3 41Bel 5 6 7 8 9 10 11
121MQI I
H He Li B c N
1.OX 10-7
4.8 X
6.0 1.2 9.6 2.7 2.2 1.0 3.1 2.6
4.8 x. . 1O-J . . . --
1I
?.9 x. . 1[)-~ . . . --
‘3’5X1(M ..-.-. . --
I
3 ‘5X .In-h -----
0
5.1 x 10-5 1.6 X 1(1-~
Si P
s c1 Ar K Ca Sc TI v Cr Mn Fe co Ni
I
Cook et. atl. (1984) 10 MeV 1.()
1.5 1.5 1.2 2.8 2.2 4.3 3.5 3.5
F Ne Na “
Gloeckler (1979) 1-20 MeV 1.0 1.5 x 10-2 I
1.6 X 10-4 3.8 X 10-s 3.2 X 10-1
131AII
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Adams et al. (1981) Mason et al. (1980) -1 MeV 1.0 2.2 x 10-2
Element
3.8 X 10-s 2.3 X 10-7 1.8 X 10-s 1.7 x 10-7 3.9 x 10-6 1.3 x 10-7 2.3 10-6
x lo--~ x 10-7 x 10-4 X 10-s x 10-4 x 10-7 x 10-5 x 10-~
2.8 X 10-5 4.3 x 10-7 5.7 x 10-~ 8.7 X 10-7 ,
2.6
X
10-6
10x 10-7 5.7 4.2 4.1 1.0 2.2
x X x x x
10-7 10-7 10-5 10-7 10-6
3.3 x 10-5
10-8 X 10-9 x 10-8 X 10-5 X 10-s x 10-4 x 10-8 x 10-5 x 10-6
McGuire et al. (1986) 6.7-15 MeV 1.0 1.5 x 10-2 2.8 X 10-6 1.4 x 10-’7 1.4 x 10”7 1.3 x 10-4 3.7 x 10-5 2.8 X 10-4 1.4 x 10-7 3.6 X 10-s 2.4 X 10-b
l+!%%%=
1.7 x 10-7 7.8 X 10-6 7.1 x lo”~ 7.3 x 10-7 1.0 x 10-7 3.1 x 10-6 7.8 X 10-9 1.2 x 10-7 1.2 x 10-8 5.0 x 10-7 1.8 X 10-7 3.4 x 10-5 4.8 X 10-7 1.2 x 10-6
4.0 x 10-’7 6.5 X 10-6 4.6 X 10-6 3.2
X
10-6
Previous compilations of SEP proton fluence data for earlier events noted the wide disparity in intensity among them. This lead to an artificial categorization of events as “ordinary” and “anomalously large” or “typical”, “worst case” and “anomalously large. ” Feynman et al.then showed that once proton fluence data on a sufficient number of flares were compiled, the data fit a single log normal distribution, so there was no longer a need for the “anomalously large” category. Her original model JPL 85, based on data from a variety of instruments has been superseded by a new model, JPL 1991, based on data from eight close] y related instruments on a series of eight satellites [22]. The new model provides event fluences as a function of the cumulative probability of occurrence for proton energies of 1, 4, 10, 30, and 60 MeV. The data cover the years 1963 to mid-1991, and for more than half of this time period the data is from one instrument, the CPME on IMP-8 (elliptical orbit, 22x 45 earth radii) [23, 24].
V-23
The GOES (Geostationary Operational Environmental Satellite) spacecraft operated by the NOAA Space Environment Laboratory also provides very useful data on SEP proton fluxes. It monitors the energetic particle populations at geostationary orbit with a solid state proton telescope, sitnilar to CPME, which provides proton integral fluxes up to 100” MeV, and through HEPAD, a Cerenkov solid state telescope on GOES-6, integral fluxes for proton energies >355 MeV and > 685 MeV [25, 26]. The GOES data is very useful not only because of the two high energy channels, but also because its hourly differential fluxes for all the large SEP events of 1989 have been published. The CPME and GOES proton SEP fluxes are generally consistent. In Table V-2 we compare the event proton integral fluxes from these instruments for the three largest 1989 flares August 12, September 29, and October 19, which illustrates the relatively good agreement between the two sets of data. In order to make the JPL 91 SEP proton fluence model more useful for single event effects calculations, the energy spectra inherent in the model needs to be accounted for directly, and the high energy portion needs to be expanded. This has been done in Fig. V-15 which plots the model’s proton fluences for 4, 10, 30 and 60 MeV for different probability of occurrence levels for two conditions, individual flares, and the sum of flares over an entire solar cycle (taken as the seven active years). Also shown are the CPME and GOES measurements for the October 1989 event which can be seen to be an approximately 99% worst case event. Fluence for the August 1972 event which has previously been used as a worst case event is also shown. While this event appears to be one which is more than 99% worst case based on the 10 and 30 MeV fluences, at higher energies it falls off much more rapidly. Fig. V-15 indicates that the October 1989 SEP event, which is much better defined than the August 1972 event, as is shown below, is probably a better choice to be used as a worst case event. -
.
1.00E+I 1
in A
Y I.00E+Io
■
P=.95, Id Flare
●
P=,99,
A
P=.999,
❑
Ott
*
Ott 89-GOES
----
1.00E+09
Id
Flare
Id
Flare
89-CPME
0ct89
Fit
@
Aug-72
o
Feb-56
x
P=
+
P=.5,7 Yr
9,7 Yr
1.00E+08 1
Proton Figure. V-15. Comparison particle event [22,25].
100
10
of integral
Energy,
1000
MeV
proton fluences
V-24
J(> E) for worst-case
solar energetic
Table V-2. Comparison of Proton Fluences for Large 1989 SEP Events as Measured bv4 Two Different Spacecraft [22, 25]. SEP J (>10 MeV) J (>30 MeV) J (>60 Mev) Event Instrument P/cm2 P/cm2 P/cm2 Aug. 12, 1289 GOES 7.9E9 1.5E9 2.2E8 CPME 6.9E9 1.8E9 8.3E8 Sept. 29, 1989 GOES 3.9E9 1.4E9 4.9E8 CPME 3.4E9 1.3E9 7.0E8 Oct. 19, 1989 GOES 1.9E1O 4.3E9 1.2E9 CPME 1.3E1O 4.7E9 3.0E9 A few events have a sufficiently large portion with very high energies (> 1 GeV or rigidity >1.7 GV) that they reach the ground where they are detected by cosmic ray neutron detectors. These are called ground level events, GLEs. The September 1989 event was a GLE and Fig. V-16 shows the peak integral flux spectra for it as well as for two other GLEs, Feb. 1956 and June, 1991. The Sept. 1989 and June, 1991 spectra are based mainly on GOES satellite measurements [25, 26], but the Sept. 1989 data points for E >2 GeV were derived from ground-based detectors [9]. The Feb. 1956 GLE is considered to be the worst such event ever. The data for it are derived from balloon and ground-based measurements [134]. For this reason only upper and lower bounds on its proton flux are provided [135]. Cosmic ray physicists have used a variety of functional forms to represent the SEP differential proton fluence in both energy and rigidity. A favorite for its simplicity is the power law in energy, dJ/dE = AE-l’ where y is the power law; it yields a straight line in log-log plots. However, Fig. V-16 shows that the dJ/dE data points display curvature. We therefore prefer the acceleration model suggested by Forman [27], that results in a Bessel function in momentum which simplifies to the following form in energy: dJ/dE
= KE3’8
exp
(
-
gE”4
where K and g are constants, and g is related to the standard acceleration parameters, UT the acceleration efficiency cmfficient and T the escape time) by cxT = 1/(3.26
(2)
) (u
is
(3)
g4)
The integral fluence, J(> E), obtained from (1) is [28] gE1/4)
(4)
J (> E) = 4 (K / g) E9’8 exp ( - gE1’4)
(5)
J(
>E)
= 4K(l/g5”5
)r(5.5,
where r is the incomplete gamma function. This simplifies to
The curve fits in Fig. V-15 and V-16, use Eq. (5) and (2) for the integral and differential fluxes respectively. Figure V-16 shows that the acceleration model, based on only GOES data, works well even for GLE events, at least for E c 1 GeV.
V-25
10000
E
E
+
1.
IL
+
●---
+
.-.-n
+ =.
1000
-.
●---
❑ -k =.
‘.-
-m -. 8
-tie.
-.
‘Aa
100
❑
‘.
‘.
+ ❑
•+ +
-.
-.
-.
‘. -..
‘A.
+
‘%
‘..
10
I -‘~
-
Sept 89, GOES
- ~
-
June 91, GOES
+
1
❑
[
0.1
“. ‘.
-. .
‘-6.
●.
Feb 56 up bound
1
*
,
10
●
‘X.
Feb 5610 bcund
100
Proton
..
‘4. s .
.. ❑ .
●
1
1000
Energy,
,0
u . b
(
10000
MeV
Figure V-16. Peak proton integral fluxes forthree ground level event solar flares, Feb. 1956, Sept. 1989 and June 1991. Satellite and ground-based neutron detector measurements were used for the 1989 event and balloon and ground-based measurements for the 1956 event [9, 25, 26, 135]
As previously indicated, alpha particles and heavy ions are also present in the SEP. The CPME telescope measures 6 channels of alpha particles and 4 channels of heavy ions, but this data has received only very limited analysis [24]. Along with the protons, the GOES-6 telescope also records alpha particle fluxes in 6 channels, the highest one with an average energy of 110 MeV/nucleon. The alpha particle fluxes from GOES-6 were obtained for the two large 1989 flares, September 29 and October 19 [29]. The alpha and proton integral and differential fluxes for these two 1989 SEP events are shown in Fig. V-17 along with the Eqs. (2) and (4) acceleration model fits. At 10 MeV/nucleon the 1- 1.5E-2 He/H ratio is consistent with that in Table V-1, but at 100 MeV/nucleon the ratio is about lE-3. The acceleration model appears to fit both particle fluences for both events equally well. The alpha particle differential flux falls off more rapidly than that for protons at higher energies. Consistent with this are the values of the g parameter which characterizes the shape of the curves. From Fig. V-17 we see that the g value of alphas is always higher than that for protons, and both g (alpha) = g (proton) + 1.7 and g (alpha) = 1.7 g (proton) appear to work equally well. The heavy ion fluxes within the SEP could be obtained by using the alpha particle differential flux distribution and scaling it with the Table V- 1
abundancesfor the other ions, an approachwhichhas recentlybeen used on the Space Station program [56].
V-26
1.00E+ll 1 Fit=lC(E/A)A.375”exp[-g”(E/A)A.25]
.OOE+1O
Protons
Sept--K=l
29E 11,g=36
Alphas:
Sepl--K=529EI
m
O, g=53
----
.00E+09
— --al -B
.00E+07
—
.00E+06
—
9/89 Protons, Msr’d 9/69 Prol Fit, g=3.6 10/89 Alphas -Msr’d 10/69 Alph Ffi, g=5.7
* \
Msr’d
9/69 Alp Ffi, g=5.3 A
.00E+08
9/69 Alphas,
10/89 Prot-Msr’d 10/89 Prot Ft. g.4
.
.00E+05 s \
1.00E+04
f
-
. . . . ..-.
1
100
10
1
Particle
Energy,
1000
MeV/Nucleon
Figure V-17. Differential and integral fluxes for protons and alpha particles for the Sept. 29, 19~9 and Oct. 19, 1989 solar ener~etic particle e;ents based on’GOES measurements and the acceleration model [25, 28, 29]. 2.2
ATMOSPHERE
The atmosphere is the second environment in which single event effects have been measured, but it is only single event upset, SEU, that has been observed. SEU researchers had predicted that the neutrons and charged particles in the atmosphere would cause upsets in sensitive microelectronics devices as early as 1984 [30]. However, it was not until a 1992 presentation by Taber and Normand that the occurrence of single event upsets in SRAMS during flight was firmly documented [31]. In their study, upsets were recorded in 64K SRAMS flying at both 29,000 and 65,000 feet at a variety of latitudes, and when operated in both the standard 5V and 2.5V data retention modes. In all cases upsets were measured. In the data retention mode, RAM boards were flown by IBM on close to 60 flights, accumulating nearly 300 flight hours and yielding about 75 upsets. Upsets were accumulated during each of three flight phases and read out at the end of each phase. Both the NASA ER-2 and Boeing E3/AWACS aircraft were used. In the fully operational mode, data were collected from the CC-2E computer containing the same 64K SRAM, aboard military aircraft in two separate European areas. Since the CC-2E is protected by error detection and correction (EDAC), all upsets were detected, corrected and recorded by the computer for each flight. In this case there were 118 flights accounting for 783 flight hours which resulted in 136 upsets [32]. Since this initial study, two other papers have been published which further document in-flight SEU events. Normand and Baker reported on upsets in the CC-2E computer in the TS-3 Boeing E-3/AWACS that flies out of Boeing Field [33]. Its altitude is 29,000 feet but it flew to a variety
V-27
of northern latitude locations, so upset data was obtained as a function of latitude for latitudes ranging from 300 to 600. A total of 162 upsets were recorded in 130 flights, and 100 of these had latitude information available. J. Olsen et al., reported observation of 14 SEUS in the 256K SRAMS of a hand-held computer used in the cockpit of commercial aircraft flying at 39,000 feet [34]. There have been other anecdotal accounts of SEU in flight, but the aforementioned reports firmly establish that this is an effect that avionics designers need to be aware of. The following sections describe the main components of the atmospheric environment capable of causing SEE. 2.2.1
NEUTRONS
Since energetic neutrons have been shown to cause SEU, this portion of the atmospheric environment will be described first, followed by that of charged particles, i.e., protons and heavy ions. Atmospheric neutrons have been identified as the main cause of single event effects at elevated altitudes. The neutrons in the atmosphere are created by the interaction of cosmic rays with the oxygen and nitrogen atoms. They extend in energy to > 1()()()MeV as can be seen in Fig. V-18 which shows the differential neutron energy spectrutn as measured by Hewitt et al, [36]. It has been found convenient to fit the spectrum of Fig. V-18 as a function of neutron energy E
dN —= dE
-~~~~~-.92l9
x exp [ -.01522
(lnE)2 ]
n/cm2
sec
MeV
which applies at 40,000 feet and 45° latitude. 1
x 0.1
0.01
0,001
0.0001 1
10
Neutron
100
1000
Energy (MeV)
Figure V-18. Spectrum of the average differential neutron flux in the atmosphere at 40,000 ft. and 45° latitude based on the measurements of NASA-Ames and normalized to a 1-10 MeV neutron flux of 0.85 n/cm2 sec [32,36].
V-28
(6)
Others who have measured the atmospheric neutron spectrum obtained similar results, although in some cases the spectrum was found to reach a plateau at - 30-70” MeV before falling off as l/E [35]. The neutrons in the atmosphere vary with both altitude and latitude. The altitude variation derives from the competition between the various production and removal processes that affect how the neutrons and the initiating cosmic rays interact with the atmosphere. The net result is a maximum in the flux at about 60,000 feet, called the Pfotzer maximum as seen in Fig. V-19 [32]. Fig. V-20 shows a similar variation in a semi-log plot of the 1-10 MeV neutron flux as a function of atmospheric depth [35] and further shows that at sea level (1033 gm/cm2) the neutron flux is several hundred times lower than at aircraft altitudes. Although these two curves are only for the 1-10 MeV neutrons, the neutron spectrum changes very little with altitude. Thus, the variation of the 1- 1() MeV neutron flux with atmospheric depth or altitude is representative of the variation of the entire neutron spectrum, Normand and Baker have verified this by observing the satne behavior of the 1-10 MeV and 10-100 MeV fluxes as a function of altitude. [33] The latitude variation is mainly influenced by the geomagnetic field manifested by the cutoff rigidities (see Fig. V-4). At the equator where the magnetic field is strongest, the cosmic rays are least likely to penetrate. The lower cosmic ray flux leads to a lower atmospheric neutron intensity. Fig. V-21 shows the variation of the 1-10 MeV neutron flux with latitude [32].
1.6
1.4
1.4 1.2
x 1= ii g- 0.8 ii
> g
0.4
0.4
0 + 0.2
0.2 0
0.0 0
5
10
15
20
25
30
35
40
45
Altitude, Thousands
50
55
60
65
70
75
80
of Ft
Figure V-19 The 1-10 MeV atmospheric neutron flux as a function of altitude based on aircraft and balloon measurements [35].
V-29
10
1
B -.*-.. -.-.---.. .= -.-.-.
“-y
0.1
●
●
●
0.01
0.001
0
200
400 Atmospheric
600 Depth,
800
1000
1200
g/cm2
Figure V-20. The 1-10 MeV atmospheric neutron flux as a function of atmospheric depth (gtn/cm2) based on balloon measurements (Holt) and calculations (Armstrong and Wilson-Nealy) [33, 35].
Fig. V-21 is based on measurements made aboard aircraft at 35,000 feet but it is only a simplified yet useful approximation. In order to obtain it, we averaged the vertical rigidity cutoffs in Fig. V4 over geographical longitude for each 5° in geographical latitude. This averaged latitude vs. rigidity cutoff curve is shown in Fig. V-22 [33]. In combination, Figs. V-18, V-19 and V-21 define a simplified atmospheric neutron distribution model. It assumes that the neutron flux is separable into three factors, one that varies with altitude, one with geographical latitude and one to account for energy. A better model, independent of the energy spectrum, is the Wilson-Nealy model [33]. In this model latitude and altitude are not treated as separable, nor are they defined in terms of conventional parameters, latitude (degrees) and altitude (ft), but rather in terms of rigidity cutoff (GV) and atmospheric depth (gm/cm2). This model also accounts for the effect of solar modulation.
V-30
1.6 1.4
1,2
x“ 3
Z
o
1.2
1
0.4
0.2
0.2
0
0
0
10
20
30
40
50
60
80
70
90
Latitude, degrees Figure V-21. Thel-10 MeVneuEon flux asafunction ofgeographical 1atitude based on aircraft neutron measurements and the vertical rigidity cutoffs of Smart and Shea [33].
I
o
10
20
30
50
40
Geographical
Figure V-22. The longitudinally averaged geographical latitude [33, see Fig. V-4]
Latitude,
rigidity
V-31
70
60
80
90
Degrees cutoffs
at 65,000
ft. as a function
of
Attributing the in-flight single event upsets to the atmospheric neutrons is based upon several factors. First, with the limited in-flight data available, Taber and Normand were able to plot the measured upset rates against altitude and latitude. These upset data were then correlated with the atmospheric neutron curves as functions of altitude and latitude and the agreement is good. Fig. V-23 shows the altitude variation [32] and Fig. V-24 the latitude variation [33]. Since the in-flight upset rates as functions of altitude and latitude directly follow the variation of the atmospheric neutron flux with the same variables. it is clear that the atmospheric neutrons are the dominant . radiation environment influencing the upset rate.
10 Neutron
Flux Measured
at Alt!tude
,
, .
.
-, #.
.
.-
I r z
0.01
0
1
,
I
1
t
1
1
10
20
30
40
50
60
70
80
Altitude, Thousands of Feet Figure V-23. Correlation of the inflight SEU rate in the IMS 1601 SRAM with atmospheric ne~tron flux as a function of altitude. ‘fie SRAM was operated at 2.5V [32].
V-32
2,5
2
1.5
1
0.5
0
0
10
20
30
40
Latitude
50
60
70
80
90
(degrees)
Figure V-24. Correlation of the inflight SEU rate in the IMS 1601 SRAM with atmospheric neutron flux as a function of geographical latitude. The SRAM was operated at 5V [33].
A second confirmation of the primary role of the atmospheric neutrons is offered by the energy deposition measurements made by the CREAM instrument aboard the Concorde. [37, 38] CREAM was originally developed to measure the energy deposition spectra in silicon on the Shuttle. It consists of ten pin diode detectors operated at 172 p,m of depletion and with a total sensitive area of 10 cmz” It was installed and flown on the Concorde supersonic aircraft in 1988 and data was recorded from 1988-90 at altitudes above 50,000 feet.. Energy deposition is collected in 9 separate channels, but on all flights the two highest channels never recorded any counts. Across the seven lower channels the count rates were remarkably similar for such flight paths as London-New York, London-Washington and Washington-Miami. We converted the count rate data into the burst generation rate format, cm2/p,m3, and these are shown in Fig. V-25.
v-33
lE-12 —
$a
E
$
WNR, 300 urn SBD ●
lE-13 ---,E14
CREAM onlmard WNR,
u
Concorde
10 urn SBD
ZOO MeV
protons,
300 urn SBD
E o
. lE-15 E m lE-16 co m ~ lE-17 .co ~ g
lE-18
lE-19
8
1
1
10
Energy
100
Deposited,
I 1000
MeV
Figure V-25. Correlation of the energy deposition spectrum in the CREAM detector flown on Concorde with the spectra measured in silicon surface barrier detectors (SBD) exposed to the WNR beam. The CREAM detector has a 172 ~m depletion thickness and the main SBD, 300 ~m [37, 117].
Normand et al. recently performed a charge collection experiment at the Weapons Neutron Research (WNR) facility at Los Alamos National Laboratory. The spectrum of the WNR neutron beam shown in Fig. V-26 is very similar to that of the atmosphere (Fig. V-18) except it is approximately 1.5E5 times more intense [117]. A silicon surface barrier detector (300 ~m fully depleted) was exposed to the WNR neutron beam and the energy deposition spectrum measured [1 17]. This too is shown in Fig. V-25 and it is evident that the CREAM data measured in flight perfectly parallels the neutron bombardment energy deposition. The WNR deposition spectrum is higher because the depletion depth of our detector is larger than that of the CREAM detectors (300 ym vs. 172~m). Fig. V-25 also shows that about 120 MeV is the maximum energy that can be deposited by atmospheric neutrons. This is consistent with the CREAM data since no counts were recorded in channel 8 (182 MeV).
v-34
1.0E+09
E K
1
.0E+08 - :
.0E+07 - ,
.0E+06 - ,
■
1.0E+05
I
1
I
1
100
10
Neutron
✍✎
Energy,
1000
MeV
Figure V-26. Comparison of the neutron spectrum at the Weapons Neutron Research facility (WNR) of Los Alamos National Lab with the atmospheric neutron spectrum [1 17].
Both the simplified model, Figs. V-18, V19 and V-21, and the more accurate Wilson-Nealy model, apply at all altitudes. With commercial air traffic, the altitude at which airplanes fly is a complicated matter based on many factors (weight of aircraft, fuel reserve requirements, air traffic control instructions, etc.). However, setting aside these limitations, there are default altitudes established by the ICAO (International Civil Aeronautical Organization) which are as follows: a) for eastbound flights - from sea level to 29,000 ft. at odd-numbered altitudes, and above 29,000 ft., at 33,000, 37,000, 41,000 and 45,000 ft. and b) for westbound flights - from sea level to 28,000 ft., at even-numbered altitudes, and above 28,000 ft., at 31000, 35,000, 39,000 and 43,000 ft.. The Concorde flies at about 55,000 feet and the next generation supersonic airplane, the HSCT (high speed civil transport) is being designed for a flight altitude in the range of 55,000-65,000 feet.. For military aircraft which fly at distinctly different altitudes depending on the mission, determining a single flight altitude to characterize the neutron environment is not straightforward. An initial estimate can be made based on flight profilesinMIL-HDBK-781 [39]. For jet fighters on escort and operational missions, MIL-HDBK781 gives 35,000-42,000 feet as the range of relevant altitudes, for electronic countermeasures and reconnaissance aircraft, it is 35,000-40,000 feet, and for helicopters it gives 5000 feet as the altitude at which they fly from base to area of operation. The neutron environment at ground level can also be defined using Figs. V-18, V-19 and V-21 or the Wilson-Nealy model, with the recognition that the elevation of a particular location above sea level needs to be specified. Limited data from a sophisticated ground-based detector system made at 100, 5000 and 10,000 feet above sea level indicate that the 10-100 MeV flux falls off approximately linearly with elevation [33]. Very few measurements of the neutron spectrum at ground level have been made, especially over the entire energy range. We have used one of the most recent measurements, made in Japan [118], and normalized it to the spectrum expected in the US based on airplane measurements over Japan and the US [36]. These spectra are shown in
v-35
Fig. V-27, which also contains a few data points measured at Cape Girardeau, Missouri [136]. An early study showed that when a large number of memories were monitored for single event upset at three locations of varying altitude (5000 feet, sea level and in a mine), the upset rate decreased with decreasing elevation, indicating that atmospheric neutrons are the likely cause [40]. This study has been very recently published in a much updated format [57] that carefully separates out the upsets caused by alpha particles emitted by trace elements in the device package from those caused by the atmospheric neutrons. Using the atmospheric upset rate component at three locations with in the US, the variation with altitude is the same as the atmospheric neutron flux variation with altitude [57]. Furthermore, there is even more recent evidence of upsets on the ground. The large computer system ACPMAPS at Fermilab contains about 160 Gbits of DRAM memory, which, when full y monitored, exhibit approximately 2.5 upset/day [119]. This upset rate appears to be consistent with the rate calculated using the ground level neutron flux, Fig. V27, and a DRAM upset rate in the WNR beam [1 17] to within about a factor of 3 to 6.
.00E-03
x“
3 ii
.00E-04
1.00E-05
“
1.00E-06
~Japan
(Nakamura)
: ~US “ - ‘--
(Nak adjusted) Atmos x1.5 E-3
1.00E-07
8
1
100
10
Neutron Figure V-27. Comparison of ground-level neutrons at 40,000 ft. [118, 136].
2.2.2
Charged neutrons, nuclei in decaying elevations primarily neutrons.
CHARGED
1000
Energy, MeV
atmospheric
neutron spectra with the spectrum
of
PARTICLES
particles have also been measured in the atmosphere, most of which are, like the reaction products from the interaction of the primary cosmic rays with the O and N the air. These include protons, pions, kaons and electrons, with the pions and kaons to muons. Most of the measurements were made on the ground at mountainous (> 7000 feet), but these have been augmented by data from balloons. Our interest is on the protons because they can cause single event effects in a manner very similar to the
V-36
Fig. V-28 shows the proton differential energy spectra at altitudes of 53,000-59,000 feet (16-18 km, 101-76 gm/cm2) at locations with three different cutoff rigidities (roughly polar, high latitude and mid-latitude) [35]. The fall-off with energy is more severe than in the case for neutrons. This is also true of the falloff with respect to altitude or atmospheric depth. The altitude dependence of energetic protons is shown in Fig. V-29 which can be compared to Fig. V-20 for neutrons.
I
I
1 +
1
%
m-’ I
-L C/i
10-2
-itn C-4
‘E
x 1 ()-1
10-3
IL
10-4
.
I 1
I
1
10
100
ENERGY
(MeV
1000 )
Figure V-28. Comparison of measured and calculated differential energy spectra of atmospheric vertical protons at altitudes of -16-18 km (52,000 -59,000 ft.) for various geomagnetic cutoffs. The three sets of measurements by Bogomolov are for rigidity cutoffs of 0.4-0.5 GV, 0.3-4 GV and 6.9-7.4 GV (high, middle and low plots respectively). The four calculated curves by Aitbaev et al., are for cutoff rigidities of 0.5 GV, 3 GV, 5 GV and 7 GV, curves 1-4 respectively (100 gm/cm2--53,000 ft.) [35].
v-37
z
10–1 5 2
1(J-Z 5 2
1 (3-3 5 2 1
0–4 5 2
10–~
Figure V-29. The vertical proton intensity in the atmosphere as a function of atmospheric depth for protons with E>l GeV [35].
Another indication of the minor role of protons in the atmosphere relative to that of the neutrons comes from measurements of the ratio of protons to the total penetrating component (protons, neutrons and pions) given in Table V-3. It applies to an altitude of about 10,000 feet (750 gm/cm2). Further, Fig. V-30 shows the ratio of charged pions to protons, indicating that at the conditions of the Table V-3 measurements, (300 MeV, - 10,000 feet) the pions constitute a small component [35]. Therefore, Table V-3 indicates that at 10,000 feet protons constitute about 1020% of the penetrating component and neutrons roughly 80-90%. At 30,000 ft., Table V-3 shows that the magnitude of the energetic proton and neutron fluxes are roughly equal. However, with respect to inducing SEE in avionics, because the protons are much more readily shielded by the aircraft structure than the neutrons, the neutrons constitute the main SEE threat. For example, 100 MeV protons have a range of 9.8 gm/cm2 (- 1.4 inches) in aluminum so for any shielding greater than this value, the protons are completely absorbed and none get through. In contrast, 100 MeV neutrons have an effective attenuation length in aluminum of - 104 gm/cm2, so after 1.4 inches of aluminum shielding, the neutron flux is reduced by only 10%.
V-38
3
I
2.5 Q
I
1
I
I
I
I
1
I
I
.
.
7L~= 100g cm-z
2
.
z 1.5
z
1
0.5 c1
1+
“o
+
+
I
I
1
10
I
1
100
1
I
i
1000
ENERGY (GeV ) Figure V-30. Ratio of the charged pions to protons in the atmosphere as a function of energy at depths of 500, 700 and 1000 gicrn2 (20,000, 12,000 and 1000’ft.) for a pion interaction rn~an free path of 100 gm/cm2 [35].
Table V-3. Ratio of Protons to the Total Penetrating Component in the Atmosphere [35]. Altitude, km 2.96 2.96 3.1 3.2 3.25 3.25 3.4 3.4 3.5 3.65 5.2 9
Energy, Gev 1.06-50 1.06-20 .96-20 >.4 1.02-14 .998 -2.68 9.08-17 >.985 1.17-2.21 >.3 >.988 1.06-50 1.37-5.09
Proton Content, % 16~3 19.7 f 3 20.8 *3 7.9 12 14*1 4.8 19*2 20*2 12 11*1 24*3 50* 10
Very few measurements have been made of the heavy ions in the atmosphere. The flux of the heavy ions within the primary cosmic rays is very rapidly attenuated with increasing atmospheric
v-39
depth due to fragmentation (interactions with the atmosphere that fragment and thereby remove these heavy ions). Nuclear emulsion and plastic track detectors have been used to measure the flux of enders, ie., ions that are stopped within the detector. It was found that the flux of enders, incident from a specific zenith angle, is a function of the path length measured from the top of the atmosphere. Fig. V-3 1 shows the heavy ion flux as a function of the product of vertical atmospheric depth X, and the secant of the zenith angle, i.e., X sec 0 for heavy ions with charge 6 S Z S 9 (CNO and), a similar curve for the heavier ions, Z 210 is shown in Fig. V-32 [35]. These apply at the top of the atmosphere (O - 80 gm/cm23 equivalent to > 58,000 feet). Comparing Figs. V-3 1 and V-32 to Fig. V-28 for the protons illustrates how drastically the heavy ions are reduced.
.
4
.
I 10-2
10-3
.4 .. .. \
4 ++ A I \ + al \. ,:
.. ..
10-4 o
t
ATMOSPHERIC
t 20
●
9 40
9 60
DEPTH
80
.x 100
(g -cm-*)
Figure V-3 1. Differential flux of stopping nuclei in the atmosphere detected in nuclear emulsions for charges 6sZ<9 as a function of atmospheric depth [35].
V-40
m= i
, ~-3
.
. . .
E
. .
.
aJ -
G -J
v z
10-4 . . . .
,*-5
‘c)
ATMOSPHERIC
20
40
60
DEPTH
80
100
( g -cm-z)
Figure V-32. Differential flux of stopping nuclei in the atmosphere detected in nuclear emulsions for charges Zzl(l as a function of atmospheric depth [35].
The data shown in Figs. V-31 and V-32 give no direct indication how the geomagnetic field, i.e., rigidity cutoffs, affect the heavy ion flux, although we would expect it to be somewhat similar to the effect on protons (Fig. V-28). More recent measurements were made on the aircraft flying the IBM avionics SEU experiment referred to in section 2.2. CR-39 track etch detectors were flown on three flight paths: mid-latitude (low and high altitude) and high latitude, high altitude. Heavy ion strikes were measured on only the high latitude (polar), high altitude flight. The resulting LET spectrum of these heavy ions is shown in Fig. V-33 [31]. For comparison purposes, Fig. V-33 also shows the heavy ion spectra measured on several Space Shuttle flights. The atmospheric heavy ion spectrum appears to fall off precipitously for LET >1 MeV cm2/mg and so would not be expected to pose much of an SEE threat. About 90% of the atmospheric spectrum is due to short range particles, those which did not penetrate through two CR-39 layers (80 roils). The penetrating particle component is thought to comprise mainly primary cosmic rays.
V-41
-1
1.OE-OZ
1,OE-01
1.OE+oo
1.oEto1
LET, MeVcm2/mg in Wuter Figure V-33. Comparison of charged particle LET spectra measured with CR-39 on high altitude, high latitude aircraft (ER-2) and on three different Space Shuttle missions [3 1].
Future aircraft radiation environment programs may better define this heavy ion component. An ambitious program to measure all ionizing radiation components within the atmosphere at aircraft altitudes has been proposed by the DOE-EML [41]. It would involve simultaneous measurements by about 10 different instruments aboard a single aircraft to record the neutron, proton and heavy ion particle fluxes and dose rate responses at different latitudes and altitudes.
V-42
2.3
MAN-MADE
SOURCES
Man-made sources also produce environments that are capable of inducing single event upsets. Our focus here is on the accessible environment around these sources where electronic equipment may be placed. In almost all cases the environments of interest consist of high energy neutrons. The neutron environments produced by most types of man-made sources have neutron energies of about 1-10 MeV, aside from accelerators where much higher energy neutrons are generated. Except for the very most sensitive devices, most microelectronics may be considered to be susceptible to single event upset from neutrons with a minimum of 5 MeV. This is because it is the recoils produced by neutron interactions with semiconductor material (primarily silicon but also gallium arsenide) that deposit enough energy to cause the upset. Almost all of the high energy recoils are produced by inelastic reactions such as (n,p) and (n, alpha), which are threshold reactions. Only for neutrons with energies greater than the threshold do the reactions occur. In silicon, using an interaction cross section of 1 mbarn to define the effective threshold, the threshold energy for the (n, p) reaction is 4.5 MeV and for (n, cx)it is 3.7 MeV. In GaAs it is 5.5 MeV for (n, p) and 2.5 MeV for (n, et) [42]. In addition, some recoils produced by elastic scattering, which has no threshold, also deposit energy. For a given value of critical charge needed to cause upset in a sensitive device, neutrons with energies down to a threshold level can deposit the requisite energy through several different reactions. We have chosen the representative low value of critical charge as 0.03 pC (equivalent to 0.675 MeV in silicon) to base the neutron threshold. For 0.03 pC the corresponding neutron threshold energy is 5 MeV. Thus man-made sources that generate neutron environments with a portion of the spectrum greater than about 5 MeV can be considered to be capable of inducing single event upset [43]. 2.3.1 A
nuclear
NUCLEAR
reactor
is a complex
REACTOR system
designed
to produce
usable
heat
or power
from
the energy
fission. Nuclear reactors extend over a very wide range of sizes. Large commercial reactors, producing more than 1000 MWe, have active reactor cores where the fissioning occurs that are more than 12 feet high and 6 feet in diameter. Small advanced reactors may be designed to produce as little as 1 KWe of power from a small reactor core extending out to less than a foot. released
by
nuclear
For the purpose of inducing single event effects, the key characteristic of a nuclear reactor is the neutron spectrum. In this regard, reactors are classified as either “thermal” or “fast”. In a thermal reactor, almost all the nuclear fissioning is initiated by thermal neutrons, with energies of -0.025 eV. Since the -2.5 neutrons released in each fission have an average energy of 2 MeV (see Fig. V-34 which shows a number of neutron spectra including the pure fission energy spectrum), the thermal spectrum is achieved by the water moderator surroundi n.g the uranium. The water “slows down” these high energy neutrons very efficiently (in pure hydrogen, a 2 MeV neutron, after undergoing 18 collisions, will have its energy reduced to (.).025 eV, but in pure oxygen 150 collisions are needed). Commercial power reactors also have additional cooling water surrounding the core. Thus, the neutrons escaping the pressure vessel which houses the reactor core, water moderator and water coolant, will have essentially no neutrons with energies above 5 MeV, and so single event upset is not an issue. Fast reactors present a totally different situation. In most designs hydrogenous material is specifically excluded. Fast reactors use materials such as lithium (coolant), B, Be and C as part of the reflector and control drums and oxide and carbide fuel (uranium and thorium). From Fig. V34, there will be some high energy neutrons from fission, so that even after a number of collisions, these neutrons will have energies above 5 MeV. In addition there will also be high v-43
energy neutrons produced from (rz, n) reactions. and there are a number of pathways by which these reactions can proceed. In oxide and carbide fuel that has operated for some time, a variety of actinide radionuclides are produced yielding 4-6 MeV alpha particles by decay which can initiate (u, n) reactions in C 13, 017 and 018 [50, 51]. High energy, fission neutrons will interact in B4C/Be2C with the B, Be and C to yield alphas via (n, u) reactions, which can subsequently be absorbed in the B, Be and C to produce neutrons via the (et, n) reactions. Most neutronics calculations do not account for the buildup of alpha emitting radionuclides and the subsequent generation of high energy neutrons from (cx, n) reactions. An idea of this high energy neutron spectrum can be obtained from the PuBe spectrum shown in Fig. V-34.
1
0,1
0.01
0,001 +
0,0001 0.1
1
Neutron
10
Energy,
100
MeV
Figure V-34. Comparison of differential neutron spectra for four different neutron environments, all normalized to 1 n/cm2 (Ez1 MeV) [36,43].
The net result is that for some fast neutron designs, a small but not negligible portion of the neutrons leaving the reactor pressure vessel will have energies above 5 MeV. Furthermore, since these high energy neutrons are less attenuated/slowed down by the radiation shielding protecting instrumentation areas, we might expect 1-2% or more of the neutrons reaching these areas to have single event upset is an effect that should be energies > 5 MeV. Thus, neutron-induced considered in such designs. At present, however, it is doubtful that neutron-induced SEU has been considered in even recent advanced reactor designs for two reasons: 1) in the areas in which the electronics have to function are other harsh environments, e.g., very high temperatures and high radiation dose rates which are recognized as the first level of concern to be addressed and b) lack of familiarity by the reactor design organizations of the neutron-induced SEU effect and methods for dealing with it.
v-44
2.3.2
RADIOISOTOPIC
SOURCES
For interplanetary missions beyond Mars, spacecraft conventionally use radioisotope thermoelectric generators (RTGs) to provide the power. The RTG, also called the General Purpose Heat Source (GPHS) RTG, is a large cylinder made up of modules containing plutonium, mainly Pu-238 as shown in Fig. V-35 [44]. The plutonium produces heat by emitting alpha particles which is directly converted into electricity by SiGe thermocouples. Each RTG contains about 11 kg of plutonium , equivalent to about 132,000 curies of Pu-238 and produces 4500 W(th).
I-
OuterShallAs$embly
Haat SourceSupport r
~
RT(? Mounting Flange \
GM Mmmgement Assembly
Figure V-35. Cutaway drawing of the General Purpose Heat Source (GPHS) Radioisotope Thermoelectric Generator (RTG) [44).
The fuel is in the form of plutonium oxide, Pu02, and there are several other Pu isotopes in addition to Pu-238. Neutrons are produced from three types of reactions: (cx, n) reactions, spontaneous fissionin of some decay products, and neutron induced fission. The (u, n) neutrons come from 01 ? and 018 reactions with alphas emitted from the Pu-238 decay, The main naturally occurring oxygen isotope, 016 does not undergo (et, n) reactions with the Pu238 al ha particles. To reduce the neutron emission rate, the Pu02 has been depleted in the 017 and O f 8 isotopes. This isotope depletion decreases the neutron emission rate in the GPHS source by about 70%. The neutron spectrum from the GPHS RTG is shown in Fig. V-34 [44]. This reduction in the (et, n) reaction is even more important for the neutrons >5 MeV, almost all of which are produced by the 017 and 018 reactions. Another radioisotope source used in spacecraft is the radioisotope heater unit (RHU). It is similar to the RTG but lower in power (provides heat only, about 1 Watt per unit). A 1W unit requires only 34 curies of Pu isotope. As in the RTG, the Pu is in the form of Pu02, so the neutron spectrum for the RHU can be taken to be the same as that for the RTG (see Fig. V-34).
v-45
However, the magnitude of the neutron flux from the RHU is lower than that from the RTG by roughly the ratio of the number of curies of Pu-238 contained in each. There are other radioisotope sources, e.g., PuBe, AmBe, etc., that emit high energy neutrons but these are used in specialized applications (calibration sources and reactor startup sources) that generally do not involve microelectronics. The neutron spectrum from a PuBe source is essentially the same as that of the GPHS. Because these sources are readily available, they have been used to simulate the neutron environment in the atmosphere and that of the GPHS RTG, since the RTG is not readily available because of its special storage requirements [34,93]. The last radioisotope of interest is Cf-252 which spontaneously fissions. Encapsulated Cf-252 is used in a wide variety of applications, primarily as a portable neutron source. The neutron spectrum it emits is very similar to that of the fission spectrum in Fig. V-34 Microelectronics are not expected to be used near Cf-252 sources. Even if they are, the potential for neutron-induced SEU is very small. However, since the intensity of Cf-252 sources varies over many orders of magnitude, this potential should be evaluated on a case by case basis. 2.3.3
ACCELERATORS
Areas around particle accelerators will have high energy neutron fields, i.e., energies > than 100 MeV. This follows from the fact that the purpose of accelerators is to produce high energy particle beams. When the beams collide with structural materials they produce high energy neutrons in the same manner that the GCR protons interacting with the gases in the atmosphere generate the atmospheric neutrons. Our interest is on the neutron spectra in areas where electronic equipment is permanently located or where it may be moved temporarily. Massive radiation shields are used at accelerators to reduce the radiation dose rate in these areas to tolerable levels, but single event effects were not considered in those shielding designs. The National Laboratory for High Energy Physics in Japan, known as KEK, is one such facility. Its 12 GeV proton beam passes through several meson production targets located in the wellshielded beam tunnel. The neutron leakage spectra outside the tunnel were measured with a multisphere detector system and a carbon activation detector. The neutron spectra were unfolded from these measurements using two different unfolding codes, LOUHI and BUNKI [45, 46]. The resulting spectrum in the detector hall at location B-3 is shown in Fig. V-36 [47]. Shown on the same figure is the atmospheric neutron spectrum at 40,000 feet from Fig. V-18, and the two spectra are within about a factor of 2. However, at other locations in the detector hall, e.g., outside the beam dump, the KEK spectrum is higher than at B-3 by at least a factor of 10.
V-46
1
0.1
0.01
:
‘. “.
0.001
0,0001
●
0.000014 1
I 10
Neutron
I
I
100
1000
Energy,
.\ 10000
MeV
Figure V-36. Differential neutron spectrum measured at the KEK Proton Synchrotrons (detector position B-3) [47].
The Tri-University Meson Production Facility, TRIUMF, in Vancouver, Canada is a 500-MeV, high power cyclotron used to produce meson beams for research studies. The same multisphere detector system supplemented with carbon activation detector was used to measure the neutron leakage spectra at two Iocations near the TNF (thermal neutron facility which functions as the beam dump). The resulting spectra are shown in Fig. V-37 [48]. The spectra near the TNF are about a factor of 30 higher than the atmospheric neutron spectrum at 40,000 feet. At other TRIUMF locations the measured spectra are lower. Thus, the neutron spectra immediately outside of the shielding at KEK and TR IUMF are higher than at ordinary sea level locations (e. g., beyond the boundary of these accelerator sites) by at least a factor of 1[)0-1000. The occurrence of single event effects in the microelectronics in these areas outside the shielding should therefore be considered.
v-47
—4_T0P
TNF-LOUHI
~TqITNF-BUNKl
,~TNF
ti-LOUHl
~TNF
----
k-BUNKl
Alm Nauls, 4E4 R
100
10
---
1
0.1
0.01
r
-.
.
0.001 0.1
r
,
,
1
10
100
Neutron
Energy,
1000
MeV
Figure V-37. Differential neutron spectrum measured at the TNF (beam stop) of the 500 MeV TRIUMF proton accelerator [48]. The TEVATRON is a synchrotrons at the Fermi National Accelerator Laboratory with an 800 GeV accelerated proton beam. Neutron spectra have been measured at a number of external locations using a Bonner sphere system [58, 59]. The specha at two of these locations are found in Fig. V38. At location D the depicted spectrum is in absolute units but that at location E is in relative units. Location D is far downstream of a large target and beam dump and is shielded by iron and concrete. Location E is lateral to a large electromagnet and views the bare iron return yoke of the magnet. 1
.00E+02 .--A--
I
x=
1
A
.00E+OI
Lwation
D
--~---Loc
E. RelTv
—Atm
Neutrons,
Spec 4E4
Ft
E c% Es
1 .00E+OO
~g
z: ~ ‘E
1.00E-01
=0 Q2 s z .-
1.00E-02
-~
n 1 .00E-03
1
100
10
Neutron
Energy,
1000
MeV
Figure V-38. Differential neutron spectra measured at two locations around theTEVATRON GeV proton accelerator [58, 59].
V-48
800
3.
SINGLE
EVENT
EFFECTS
The deposition of energy within electronic devices by a single energetic particle can lead to deleterious effects in the devices. These are called single event effects, and they can have a significant impact on the operation of a system within which the devices are used. Some effects, such as single event upset, are temporary and can be overridden by rewriting to the device or rebooting. Other effects, such as latchup, require powering down and repowering back up. In other cases, such as with latchup or burnout, the devices can be permanently damaged.
3.1
TYPES
OF EFFECTS
The following sections will review the major types of single event effects namely, upset, latchup, burnout, and gate rupture. They will also review a more recent effect, single event induced hard error. It is very likely that still newer effects will be found, such as the very recent single event functional interrupt (in which a vendor’s test mode bits are upset [137], as new devices undergo SEE testing. 3.1.1
UPSET
(SINGLE,
MULTIPLE
BIT)
Single event upset, SEU, is the most common type of single event effect. SEU is caused by the deposition of charge in a device by a single particle that is sufficient to change the logic state of a single bit (from one binary state to the other). Single bit upsets are sometimes called soft errors because they can be readily corrected. Some memory devices are also susceptible to multiple bit upset, MBU, in which more than one bit is upset. Three types of multiple bit upsets can be distinguished the first two caused by a single particle and the third due to two independent particles. The MBU types areas follows: 1)that due to heavy ions traveling essentially parallel to the die surface depositing energy in the sensitive volumes of a consecutive line of memory cells [60], 2) the case in which the particle (heavy ion or proton) strikes the die close to normal, depositing sufficient charge in two or three adjacent cells to upset them [60], and 3) near-simultaneous single bit upsets in two separate devices (multiple independent upset, MIU), due to energy deposited by two separate particles. In general multiple bit upsets can be expected to involve more than a single logic word, i.e., the affected bits are likely to belong to different words. However, in the type 1) MBU, energetic particles may also upset two or more bits in a single word [60, 61]. This type of upset depends on the physical arrangement and size and distribution of the memory cells [60, 62], but it can have the largest system impact because it is not easily correctable. Heavy ions can cause all three types of multiple bit upsets [60]. Protons [63] and neutrons [64] can cause only the type 2) and type 3) of MBUS. Single event upset can also be caused by the generation of a transient which a device may interpret as a new bit of information. These transients are spurious signals that can propagate through the circuit path during one clock cycle. These signals can either propagate to a latch and become fixed or be overwhelmed by the legitimate synchronous signals of the circuit in which case they are ignored. Transients in combinatorial logic can pose special problems and are for more complicated to characterize [65-67]. This is particularly true in logic devices. More recently it was found that single event upset transients can occur in analog devices and the effects can be significant [68]. While such analog SEU transients are normally short-lived, they can have a longer-lasting impact on the digital circuits to which they are connected, but this strongly depends on the nature of the interconnection [68].
v-49
3.1.2 LATCHUP Latchup is a regenerative current flow condition in which a parasitic n-p-n-p pathway is turned on by the deposition of charge by a single particle, It has generally been a concern only in bulk CMOS devices, but it has also been seen in CMOS devices with relatively thick (> 10pm) epitaxial layers [69]. In addition a few bipolar parts have recently been shown to experience latchup e.g., those using an advanced bipolar process incorporating ECL [70,71]. The regenerative circuit provides a path for large current flow. If the energy created by the current path exceeds the thermal dissipation capacity of the surrounding material, melting and electromigration can occur, leading to a destructive breakdown. Even if the breakdown does not occur, the latched path will persist until power is removed from the device [65]. Prior to 1992, single event induced latchup had been seen only with heavy ions. In 1992 three groups published reports indicating that three different parts latched up with energetic protons, an SRAM (64k NEC D4464G [76]) and two microprocessors (NSC32C016 [77] and IDT R3000 [78]). A year later a beam of energetic neutrons was found capable of inducing Iatchup in LSI Logic lOOK gate array [79]. To date, two recent models have been proposed to explain the proton/neutron induced latchup phenomenon [80, 81] but it is unclear how comprehensive the,se models are. Since it is very likely that additional parts will be found that are susceptible to protonheutron induced Iatchup, the availability of such Iatchup data may become large enough to verify the adequacy of these and future models. 3.1.3
BURNOUT
AND GATE
RUPTURE
N-channel power MOSFET devices, which have large applied biases and high internal electric fields, are susceptible to single event induced burnout (SEBO). The penetration of the sourcebody-drain region by the charge deposited by a heavy ion can forward bias the thin body region under the source. If the terminal bias applied to the drain exceeds the local breakdown voltage of the parasitic bipolar, the single event induced pulse can initiate avalanching in the drain depletion region [72]. Local power dissipation due to the large drain-source current leads to destructive burnout. In commercial N-channel power MOSFETS, this effect can occur with drain voltages lower than the rated voltage of the device. A similar effect has ken seen in power bipolar devices, with ions having LET >27 MeV cm2/mg [82]. In that case, of the four commercial devices which exhibited repeated burnout behavior, two were Darlirtgton pairs that failed at drain voltages well below rated voltage while the other two required voltages well above rated voltage to achieve burnout [82]. Both N-channel and P-channel power MOSFETS are subject to single event gate rupture (SEGR). This effect is explained via the transient plasma filament created by a heavy ion track when it strikes the MOSFET through the gate oxide. The sheath of electron-hole pairs surrounding the track creates a conducting path which short circuits the normal drain to the gate oxide/silicon interface [73]. As a result of this ion track filament, a large fraction of the drain voltage drops across the gate oxide, causing a localized increase in the oxide field. If the transient increase in the oxide field is large enough and lasts long enough, oxide breakdown occurs leading first to gate leakage and finally to gate rupture. 3.1.4
SINGLE
EVENT
INDUCED
HARD ERROR
Koga [62] fust reported evidence that heavy ions can cause “stuck bits” in SRAMS. Dufour et al, [74] also found evidence of “stuck bits” which they called single hard errors (SHE). Dufour argued that these hard errors are due to total dose effects from a few ions impinging on the gate oxide of sensitive transistors. These errors occurred in random, isolated bits and could be annealed by exposure to UV light or raising the temperature. In all testing to date, the minimum
V-50
LET of an ion required to cause hard errors is 60 MeV cm2/mg [75]. Oldham has shown that hard errors have been seen only in commercial SRAMS with 4-transistor cells and resistive loads, although there is some evidence that the effect has been seen in DRAMs too [70, 75].
3.2
CALCULATING
EFFECT
RATES
In order to determine how a system that contains parts which are susceptible to SEE will perform, the SEE occurrence has to be quantified. Usually this is done by calculating the SEE rate of occurrence. The rate calculation requires two components, an SEE cross section as a function of particle energy or particle LET, and the flux of particles expected to be encountered in the environment of interest. Section 2 described the various environments capable of inducing SEE, and Section 3.1 described the major types of single event effects. Device responses to the various effects are generally quantified in terms of a cross section (in units of cm2/bit or cm2/device). These SEE cross sections are obtained from measurements of SEE events within a device while it is operated in a simulated accelerator beam environment. Test techniques to measure the SEE cross sections are extensively discussed in a number of useful references [83, 84, 123] and the data is published in may sources such as the papers presented at the annual IEEE Nuclear and Space Radiation Effects Conference (published in the annual December issue of IEEE Transactions on Nuclear Science). Particularly useful is the tabulation of SEE measured data published biannually by researchers at JPL and Aerospace Corporation [e.g., 85, 86]. 3.2.1
HEAVY
IONS
For heavy ions, measured SEE cross sections are commonly plotted as a function of the LET of the particle. The heavy ion cross section curve is generally plotted semi-logarithmically as shown in Fig. V-38. There are a number of subtleties involved in these cross section measurements and curves that have been extensively discussed in the literature (e.g., effect of angle of incidence of ion beam, particle range, ion species, LET vs. particle energy relationship, track recombination, etc.). These are described in detail in two excellent review articles [87, 88]. A group of SEE experts reviewed man y aspects of the cross section representation and recommended that the most useful fit in terms of a continuous function to model measured cross section data is that of the Weibull distribution [87].
G= CYO{l -exp{-[(L where
- LO)/W]s}}
O. is the asymptotic cross section Lois the LET cutoff S and W are fitting parameters
Fig. V-39 also shows how good a fit can be obtained with the Weibull function. Heavy ion SEE cross sections have been reported for more than 10 years encompassing >400 parts. However, the most accessible compilations, by JPL and Aerospace Corp. [85, 86], contain a condensation of the test results in terms of two device parameters, the LET threshold, LETth, and the asymptotic cross section, Go. LETth is an experimental parameter which is not always defined in the same manner by all test groups, e.g., the value of LET corresponding to a cross section that is either 190 or 10% of the asymptotic cross section. LETth is usually close to but not the identical to Lo in Eq. (7 ), which is essentially a mathematical fitting parameter. Go is the same as in the Weibull fit. Researchers have recently begun reporting the Weibull fitting parameters for measured SEE cross sections for a number of devices [87, 88]. Having no additional information other than
V-51
(7)
LETth and go, default values of S = 2 and W = 20 give a “normal” looking SEE cross section curve. However for parts with a very sharp, step function-like fall-off, values of S =10 and W = 1 are more appropriate,
1
1
.
..
.-
---
m-
-------
--#--
-------
-------
---
.
9,.’ .%
0.1
# 11 8 . W8
■
1
f“
u) 0,01 u)
Measured
—
Stair-step Fit
----
Weibull Fit
1 t
0
w’ t
6
1 ●
t * # t
0.001
o
1
1
,
I
I
1
5
10
15
20
25
30
LET,
n
I
35
40
MeV-cmA2/mg
Figure. V-39. Heavy ion SEU cross section for the IMS 1601 SRAM, as measured, using a 3part stair step fit and using a least-squares Weibull fit (cro = .688, Lo= 1.28, s = 1.729 and W = 13.39) [33]. The methodologies used to calculate heavy ion latchup and upset rates are discussed in great detail in the two previously cited review articles [87, 88]. Following the experts’ approach [87], the rate equation is initially expressed in very general terms. A number of simplifying assumptions are then made to reduce its complexity. The key assumptions are listed in Table V-4. A number of computer codes, such as CREME [52] and SPACERAD [131], may then be used, based on the assumption that the sensitive volume is a rectangular parallelipiped (RPP), to carry out the rate calculations. The codes use one of two approaches to implement the integration: a) an integral chord length distribution is convolved with the differential flux distribution or alternatively, b) a differential chord length distribution is convolved with an integral flux distribution.
V-52
1. L First Level Assumptions 1. Energy deposited in the sensitive volume (SV) of a device equals the energy loss of an energetic ion passing through the SV as calculated using its LET 2. Ions with the same linear energy transfer, LET, have the same SEE effect 3. The change in LET along the ion track through the region of interest is negligible 4. Charge generated in the SV equals the product of LET of the ion and the chord of the pathlength through the SV augmented by a funnel region and possibly a diffusion region 5. Charge collection path is independent of LET 6.
The SV is a convex parallelipiped (RPP)
body, and it is further
assumed
to be a rectangular
7, The particle flux is isotropic at the device and therefore the LET spectrum is the same in all directions ‘ B.
Second Level Assumptions (to Use CREME-like Codes) 1. There is a distribution of threshold LETs for the various SVS of a device which is given by the measured o (L), and the normalized distribution is CT(L)/@ 2. All SVS have the same thickness, h, and individual surface areas, SA, that account for the number of bits/device (usually 1 SV per bit). For each SV of dimensions 1, w and h, 1 = w = (SA)l/2 Qc = L x h where L=LET The sensitive thickness h, is chosen based on knowledge microelectronics technology
of the part or its
3. Rates are calculated by codes like CREME based only on SA and L Rate = C(QC, 1, w, h) =
C(SA,L) = Code output
4< The rate over the entire range of LET values is obtained differential rate contributions, AR (L)
by summing
AR (L)= R(LJ - R(Li+l) AR (L)= C(SA, Li) * @LJ/cJo - C(SA, Li+l) * @Li+i)/~o Rate = ~ [@Li)/~o] * [C(SA,Li) - C(SA, Li+I] i
v-53
tht
For a given critical charge, Qc and RPP dimensions 1, w, and h and the LET flux distribution these codes return a rate, rate= C(QC, 1, w, h). According to the standard methodology [87], these codes are combined with the SEE cross section as a function of LET, i.e., a (L), by making the second level assumptions listed in Table V-4. The final rate, shown in Table V-4 represents the summed rate contribution from particles over the entire LET range. The important parameter h, the sensitive thickness, is further discussed in Section 3.2.2. One variation on this rate calculation which is not covered in the review articles is provided by the Space Station program. Space Station represents a sizable effort to characterize the SEE response of a large number of parts, undertaken by at least 5 experienced SEE groups. Through its defining document [53] the Space Station heavy ion rate calculation method is to convert the usual heavy ion environment in space, typically expressed as an integral flux as a function of LET, into “redistributed” LET flux [54]. The “redistribution” accoun~s for the longer path lengths afforded by heavy ions impinging on the devices at an angle, thus giving the ion a larger effective LET. Watts has shown this to be equivalent to the standard approach discussed above [133]. For addressing single event induced burnout and gate rupture the Space Station program has again taken a non-conventional approach [55]. It is widely known by SEE test groups that when testing power MOSFETS for burnout or gate rupture, the increased effective LET concept due only to a particle’s increased pathlength because of the angle of incidence does not apply. Thus, the highest LET ion to be encountered in the cosmic ray environmmt is iron with an LET of approximately 26 MeV cm2/mg. Since an LET of 26 represents the worst case, the Space Station approach is to require all power MOSFETS to be immune from SEBO or SEGR when exposed to LET = 26 ions at a fluence of 1E5 ion/cm2. In practice the power MOSFETS are exposed to this fluence at each of several different drain voltage settings, and the maximum drain voltage at which no effect occurs is the passing voltage. This voltage is further reduced by a 0.75 factor apparently to account for part-to-part variations in response. The net result is a deterministic approach rather than a probabilistic one based on the rate of occurrence. Table V-5 contains a combined list of pchannel MOSFETS compiled by three SEE test groups for gate rupture with LET = 26 MeV cm2/mg ions [114,115]. Most of these devices passed at the rated voltage but four did not. A larger list of n-channel MOSFETS has also been developed, containing the limiting passing voltages based on failure due to either burnout or gate rupture [1 14, 115].
V-54
Table V-5. Compilation of p-Channel Power MOSFETS Based on Susceptibility to Gate Rupture
P-Channel Ordered by IR Die No. P-channel IR# Part Type
Mfg
9110” 9120 9130
Test group RI RI RI
Power MOSFETS
Rated
BVdss Pass
Usable
at 25C Imax
If Different 2N#
RFL1P1O Harris 100 100 1.0 75 2N6845 IR 100 100 75 4.0 2N6804 IR 100 100 12.0 75 2N6849 IR 100 100 75 6.5 2N6849 Harris Boeing 100 100 75 6.5 9140 IRF9140* IR 100 45 18.0 JPL 60 9150 FRK9150 Harris 26.0 RI 100 100 2N7322 75 IRF9150 IR 100 25.0 RI 100 75 Harris 9160 FRK9 160 RI 100 40.0 70 53 2N7328 R 2N6806 IR 9230 200 NT NT 6.5 2N6851* lR Boeing 200 160 120 4.0 -----Harris 2N6851 200 NT NT 4.0 9240 FRM9240* Harris 200 118 2N7318 JPL 89 7.0 IRF9240* IR 11.0 200 80 60 2N7237 JPL 2N7237 IR 150 11.0 Boeing 200 200 *These parts experienced gate rupture or leakage beyond manufacturer’s specification at Vds less than rated voltage. NT= not tested; RI = Rockwell International; JPL = Jet Propulsion Lab. 3.2.2
PROTONS
AND NEUTRONS
Compared to the heavy ion cross sections, far less experimental SEE data has been taken with proton beams. Proton SEU cross sections have been measured for roughly 60-80 parts, but 2030 of these are for older parts, many that are no longer in use. Fortunately a sizable number of parts have been tested with protons over the last few years by several different European groups [124, 125]. The proton SEU cross section was initially modeled using the so-called l-parameter Bendel model [89]. An improved 2-parameter Bendel model was suggested by two groups at about the same time and this is the form that currently has the widest acceptance [90, 91]. 4
o(E)
= (B/ A)14[1 –exp(–.18Y1’2)]
2
IE -12 ~it~~OtOn
Y=(18/A)l’2(E-A) where A and B are constants
Calculating the rate of proton-induced upset is relatively straightforward [89] once the proton differential flux and the proton upset cross sections are specified. Because of the aforementioned limited number of devices with proton SEU data, a number of models have been developed to try to simulate the proton-silicon nuclear reactions and subsequent charge deposition [95-98].
v-55
(8)
Other approaches have tried to utilize the heavy ion upset cross section data more directly. Rollins [99] developed a relationship between the asymptotic SEU cross sections for heavy ions and protons which was refined by Petersen [100]. A different approach is provided by the Burst Generation Rate (BGR) method frost put forth by Ziegler and Lanford [101]. In this method, all the energy deposited through nuclear reactions that lead to upset is associated with the energy transferred to the recoils. The recoils have low energies (QO MeV) and therefore have ranges of a few micrometers in silicon so that almost all of this energy can be deposited within the device sensitive volume. Thus protons cause SEU not through direct ionization (their LET is too low), but rather through nuclear reactions resulting in recoils which can deposit enough energy in the sensitive volume to generate an upset. The burst generation rate, BGR(EP,Er), quantifies this in terms of the probability that a particle (proton or neutron) of energy EP will generate recoils with energy 2 Er in silicon. Thus for a given deposition energy, ~, the deposition rate due to a flux of protons of energy Ep, O( ), in the sensitive volume V is given by C V BGR(Ep,Er) $(E ) where C is the collection % e lency that accounts for not all of the recoil energy being deposl “telwithin V. The BGR for proton and neutrons, in units of cm2/pm3 x 10-16, are very similar for both particles for E> 100 MeV, and have bem calculated using basic nuclear interaction data [30, 43, 102-104]. The BGR method has been refined to enable full use to be made of the information contained in the heavy ion cross section vs. LET curve by viewing a device as a population of ceUs. Each cell will upset when an amount of energy, characterized by an effective LET, is deposited in the cell. All cells are differen~ and the cross section curve is really the integral over a population with different critical charges and different amounts of charge collection [87]. The heavy ion cross section curve, given by the Weibull fit [Eq. (7)], is divided into LET intervals, each representing a different energy deposition, and normalized by the conesponding cross section over that interval. The contribution by neulrons or protons to each energy deposition interval is given [33] in terms of the BGR as follows: Upset Rate = C~ 1 Where
AVi~BGR(E,E,i)(dV E
(9)
/ dE)dE
t Afi
= sensitive thickness, ~m = heavy ion SEU cross section for ith portion of curve, cm2
AVi L~l Eri BGR
= = = =
c
t A ai, ~mq = sensitive volume representative LET for ith portion of curve, MeV cm2/mg t x LETi, MeV burst generation rate, cm2/pm3, probability that particle of energy E will produce recoils of energy 2 Eri = collection efllciency
An additional important parameter required in all of the aforementioned
proton SEU methods is
the collectiondepth, sometimescalled the sensitivethickness. The sensitivethicknesscan be considered as comprisedof three parts: the depletionregion, a funnel region and a diffusion
region [105]. Using a value of l~m for the thickness would be conservative in that it would lead to overestimating the upset rate. McNulty has discussed a number of techniques for measuring the thickness [106, 107] and Petersen has tabulated values of the thickness for a numkr of different parts [88, 100], Neutron SEU cross sections have been measured for only a very few devices. There are several reasons for this. Until recently, actuaI neutron environments had not been considerwl capable of
V-56
inducing SEE and in addition there is a lack of monoenergetic neutron beams. SEU measurements have been made with: a) 14 MeV neutron generator (essentially monoenergetic) [31], b) 40 and 62 MeV pseudo-monoenergetic neutrons from the Lj (p, n) reaction (neutrons in the lower energy tail comprise more than half the population [92], c) PuBe source (see section - for spectrum) [93], d) broad-peak neutrons from accelerator (cleuterons on Be target) [94] and, e) the Weapons Neutron Research (WNR) facility at Los Alamos which has the same spectrum as neutrons in the atmosphere and at accelerator facilities [64]. Experts have argued that for particles with energies above approximately 100 MeV, the SEU response of a microelectronic part will be the same for both neutrons and protons. Thus proton SEU data can be used for neutron energies >100 MeV, and even for energies <100 MeV but with additional uncertainty. A limited study involving three parts (2 silicon, 1 GaAs) showed that at about 60 MeV, the proton cross section was larger than the neutron cross section by about a factor of 1,5-2 [92]. This reversed the earlier conclusion that the neutron cross sedon was higher [125] which had been based on an analysis that had ignored the cormibution of the neutrons in the low energy tail [92] Since high energy proton data can be used for neutrons, the 2-parameter Bendel fi~ can also lx applied to neutrons. Having only heavy ion SEU data, neutron upset rates can be calculated using approaches such as the BGR method [33, 43], or the Petersen/Rollins method[100]. 3.3
EXAMPLES
3.3.1
SPACE
OF SEE RATES
IN HARSH
ENVIRONMENTS
To indicate the usefulness but also the limitations of the SEE rate calculation methods, a few examples will be provided. The first relates to the CRRES (Combhxl Release Radiation Effects Satellite) launched in July, 1990 into a highly elliptical orbit. The Microelectronics Package on CRRES contaimxi a number of different SEU-sensitive devices which were exposed to both the heavy ion GCR and trapped belt environments during the course of its orbits. These included the 64K DRAM (Intel 2164A) which is part of the Ratemeter experiment [108] and the 93422 bipolar SRAMS. SEU response to both heavy ions and protons is well known [90, 108]. Upsets were measured in the inner radiation belts as well as in deep space. Upset rates were calculated due to the protons using the AP8 trapped belt model and due to the heavy ions using the GCR model contained in CREME [52], The calculated rates are compared with the measured values in Table V-6 and the agreement appears to k quite good for both protons and heavy ions. Table V-6. Comparison of Measured and Predicted Single Event Upset in Various Devices within the Microelectronics Package on the CRRES Satellite [63, 108].
Memory Intel 2164 DRAM Intel 2164 DRA M
Causing SEU Protons Heavy Ions
93L422SRAM
Protons
93L422 SRAM 93422 SRAM
Heavy Ions Protons
(Upset/bh day) 8.1 E-5
3.5 E-5
14 E-6 3:1 E-3 2.7 E-4 4,2 E-3
1.5 E-6 2 E-3 7 E-4 1,7 E-3
A number of other devices were contained within the Microelectronics Package on CRRES, and their measured upset rates due to heavy ions provide a useful set of data to judge different SEU rate prediction models [109]. The in-flight and calculated rates for 6 of the devices are shown in Fig. V-40 [109]. The calculation method labeled R-I (Rate-Integral) is closest to the approach discussed in section 3.2.1. The R-I method gives the best agreement with in-flight results and the
v-57
R-O approach, which conservatively assumes that the devices have a single threshold for upset corresponding to LETth, significantly overpredicts the upset rate. In the R-I approach, the SEU cross section curve was divided into 10 equal parts, CREME [52] was used to calculate the upset rate for each portion, using the appropriate LET values, and the 10 contributions were combined. By using a Weibull fit as suggested in section 3.2.1, the SEU cross section curve can be divided into as many parts as desired. Fig. V-40 shows that this simple step integral method gives the best agreement with the in-flight results, within about a factor of 2 for two of the parts, and a factor of 3-5for the other four parts.
10000
n e
+
v
6 A
●
9
9 ●
A
A
● ❑
o 93422 + 93L422
A
A
i
● 82S212
● ❑
❑
❑ 92L44
A
A
A 21 L47
A 2164
1 0
R-O m n 1
R-.25 1
R-S 1 3
2
Figure V-40. Comparison of heavy ion upset predictions microelectronics devices flown on CRRES [109].
R-1 1 4
Flight Resu ts 5
and flight results for six different
The European UOSAT series of polar-orbiting satellites also contain a number of different static and dynamic RAMs. They therefore provide a data base of measured upset rates against which calculated rates can be compared. In a recent study [110], upset rates in 4 different Hitachi SRAMS were measured on board the three UOSAT satellites, numbers 2,3 and 5. Analysis of the in-orbit data allowed the upsets to be separated into three categories, those due to GCR heavy ions, trapped belt protons and solar flare particles. SEU cross section curves from both heavy ions and protons are available for all the SRAMS [110]. The results are summarized in Table V-7. In examining Table V-7, it is clear that the proton upsets are well predicted for three of the four parts, the heavy ion upsets are well predicted for two parts (< factor 2) and not so well predicted (factor of 7-9) for the other two parts, and very poorly predicted (factor of - 200) for the solar flare. An earlier analysis of solar flare induced upsets for a geosynchronous satellite [28] showed good agreement with predictions could be obtained when the shielding was accurately accounted for. It is also not clear which proton spectrum for the Oct. 19, 1989 solar flare was used (e.g., that in Fig. V-17) nor how the protons were transmitted to the orbit of interest.
V-58
Table V-7. Comparison of Measured and Predicted Single Event Upset In Hitachi SRAMS Aboard UOSAT Satellite [1 101. Calculated Memory Particle Causing Rate (Up/bit Observed Rate Day) SEU (Up/bit Day) Protons 4.7 E-7 4E-7 HM6116 1.36 E-6 HM6116 Heavy Ions 1.7E-7 HM6116 Oct. 89*** Flare 5.7 E-5 3.lE-3 ** 2.7 E-7 Proton* 2.9 E-7 HM6264 7.6 E-7 Heavy Ion l.l E-7 HM6264 HM6264 4.2 E-5 9.8 E-3** Oct. 89*** Flare Proton* 5.4E-7 HM62256 1.3 E-6 2E-7 Heavy Ions 1.lE-7 HM62256 Protons* 2.7 E-7 4.7 E-7 HM628128 4.lE-8 3.3 E-8 HM628128 Heavy Ions * Proton Upsets occur only in the South Atlantic Anomaly portion of the orbit ** Heavy ions contribute > 90% of this rate *** Upset rates are per event rather than per day c..
Electronics on the Shuttle also offer examples of RAMs that experience upsets in space. The three general purpose computers (GPCS) on Shuttle each have 200 IMS 1601 64K SRAMS which are protected by EDAC. The upset rates observed have been compared to those calculated by NASAJSC [120] in Fig. V-41. To do this the observed upsets are divided into two groups, those occurring during passage through the SAA, which are all attributed to protons, and those occurring during all other portions of the orbit, which are all attributed to heavy ions. Predictions were in good agreement with the measured upset rates for both heavy ions and protons for all shuttle flights except STS-61. On STS-61, the Hubble repair flight, about 3 times as many upsets were experienced as were calculated. There is as yet no good explanation for this, although the trapped heavy ions (section 2.1.2) may provide a possible answer. The digital control units (DCUS) governing the shuttle’s main engine also contain SRAMS, the 16K IDT61 16. Even though they only operate for 10 minutes, there are 6 DCUS and each has 32 SRAMS. Fig. V-42 shows how the predicted SEU rates compare to those measured on the last 14 shuttle missions. Agreement is good in almost all cases.
v-59
15 14 13 12 11
I
10 9 8 7 6 5 4 3 2
0
1 0 012345678910
1112131415
Actual Upset Rate, Upsets/GPC Day 10 % ~ u &
9 0
$7 g 56 ~2
Pk=O.1
5
0 0
34 S3 u 82 z : 1 0 012345678
9
Actual Upset Rate, Upsets/GPC
10
Day
Figure V-41, Comparison of observed and predicted SEU rates in general purpose computer (GPC) onboard Shuttle in a) South Atlantic Anomaly - protons only and b) other portions of the orbit - GCR only [120].
V-60
1.6
1
predicated
~
a’
n
1,2-
\
0.8
0.4
3.5 V operation < —..
c
5 V operation +
I
——
1 —
49 50 46 47 52 5354
56 5557
51 58 61 60
STS MISSION Figure V-42. Com~arison controller [120]. ‘
of observed
and .medicted
uDsets in SDace Shuttle main engine . .
The compilation of upsets in the Shuttle GPCS, 1950 upset event occurrences on 17 flights, also provides an excellent set of data for examining multiple bit upsets, MBUS. All three of the MBU types discussed in section 3.1.1 can be distinguished within the total of 82 MBUS out of the total 1950 SEU occurrences. The most dramatic are the six instances of cross chip upsets, i.e., multiple independent upsets, MHJs, three of which occurred on one flight, two on a second flight and one on a third flight. It appears that the MIUS can be explained on a probabilistic basis, i.e., the MIU rate is the rate corresponding to the probability of two SEUS occurring at the same time, i.e., PSEU *PSEU, where PSEU is the probability of an SEU occurrence (see section 4 for the relation between SEU rate, RSEU and PSEU). Table V-8 summarizes the MIU data from the Shuttle observed and calculated in accord with the simple model discussed above. There was also one instance of an MIU on CRRES [122] and this is also summarized in Table V-8. The simple model appears to be good to within an order of magnitude in predicted MIUS.
V-61
Table V-8. Examples of Multiple Independent Upsets, MIU (Cross Chip Upsets at Essentially the Same Time)., Observed SEU Calculated Rate/Per MIU Rate/ Observed Calculated MIU Dev. Day MIU Reference
5 Days) Shuttle. STS-61 (28.5° Orbit,
I
2
[ 120]
1.3E-33
3.8
3
[ 120]
3.7E-3~
18.4
I
II
IMS1601
4.3E-2*
1
[63] , [121], 9E-6# [122] o [63], CRRES [121], (240 Days) 93422 1.6E-5# 4E-3t [122] *Assumed to apply equally to protons and heavy ions; R,sEu = P u tUp/’bit day, due only to protons, heavy ion contribution is negligible $MIU rate= 2 * P.SELJ* PSEU # Upset/bit day, MIU rate = psEu x psEu
*E
4.5
I
8
The next most dramatic MBU occurrences in the Shuttle GPCS are the two instances of long strings of list upsets, 11 bits in one case and 14 bits in the second. This is the type 1) MBU discussed previously which is very dependent on chip layout. Koga obtained the device-specific layout data for several SRAMS and was able to calculate this MBU rate [60, 127], which we refer to as the CMBU (consecutive multiple bit upset) rate. Assuming that the 64K SRAM in Shuttle and the 256K SRAM that Koga modeled are similar enough to apply the ratio of rates, CMBU/SEU, allows us to estimate the number of type 1) MBU occurrences. This procedure is summarized in Table V-9. It appears to be good only to within an order of magnitude and possibly more. While this is not good agreement, the model does provide an approach that could be significantly improved upon once the actual chip-specific layout data is obtained. The most common type of MBU involves 2 adjacent bits being upset at the same time, what was referred to as a type 2) MBU. It can be caused by both heavy ions and protons. The Shuttle data of the SEU rate. This agrees with the indicates a total of 68 such MBUS, which amounts to 3.5?t0 occurrence rate that others have found, the type 2’)MBU rate is a few percent of the SEU rate [63, 64, 128]. Further, the MBU rate for the seven 57° orbit flights, those in which both heavy ions and protrons contribute is about double the rate for the 28.5° orbit flights in which almost all the MBUS are from the SAA protons.
V-62
Table V-9, Examples of Consecutive Multiple Bit Upset in Space
RAM Satellite nvolvData ed
7 Shuttle flights at 57° (Total of 55 B
IMS 1601
filghts (Total of 55 + **
T k 1
IMS1601
Observed SEURate per Dev. Day
L3E-2
Observed Con@cutive occurence oj #of ConSRAM Bits secuUpset, tive Bit Upsets CSB -12*
1.3E-2
4
~alculatexi Rate of consecu# Contive secutive Multiple MultiUpset ple Bits CMBU (17) at Upset, :MBU** GEO
2
17
5
17
lE-4t
Ratio of
Calculated Rates @ GEO CMBU 17)/SEU
2MBU (CSB) CMBU (17)!
Calculated occur:nces of CSB@
1.3E-4*
2
0.2
1.3E-4$
18
1.8
i one case of 11 upsets and one case of 14 upsets Basis is IDT 70256 SRAM, in which each bit in a word is separated by 15 other bits Basis is CMBU(17) calculation by Koga [60, 127] Basis is CMBU(17) and SEU calculation by Boeing Calculated CSB = [CMBU(17)/SEU] x [CMBU(CSB)/CMBU( 17)] x SEU Rate x 3.3E4 dev. days Ratio = (17/CSB)2 3.3.2
ATMOSPHERE
As discussed in section 2.2, the atmospheric neutrons can cause SEU microelectronics at aircraft altitudes. One of the proofs for this is the good agreement between the observed in-flight upset rates and the calculated rates. Table V-10 illustrates this with the most comprehensive compilation of currently available in-flight aircraft upset rates. For all devices the calculated rates include the rates calculated by the BGR method discussed in section 3.2.2 and implemented for atmospheric neutrons using the data of [32] and [43]. In addition, for those SRAMS like the IMS 1601 for which proton and neutron SEU cross sections are available [32], the rate calculated by the proton/neutron cross section method [89] is also given, and it is usually a lower rate. As indicated in section 2.2, the atmospheric neutron flux varies with both altitude and latitude, and these variations have been accounted for in the calculated rates.
V-63
Table V-IO. Measured in-Flight Occunences of Single Event Upset (SEU)
Aircraft/ Reference E-3/32
M;tuy Flight Path Seattle
~er:g
ER-2/32
N. California Norway.
65
ER-2/32
Norway.
65
Similar to E-3/32 Similar to E-3/32 E-3/33
European
29
g 2.5 V standby 2.5 V standby 2.5 V standby 2.5 V standby 5V
29
5V
29
5V
ER-2/32
Area 1 European Area 2 out of Seattle TransAtlantic Worldwide
29 65
IMS 64K
Measured Rate, up/bit hr 5E-9
Calculated Rate,* up/bit hr 4.4-8 E-9
IMS 64K
1.lE-8
1-2 E-8
IMS 64K SRAM EDI 256K
2.3 E-8
2-4 E-8
4.6E-9
8-14 E-9
lMS 64K
2.3 E-9
1.8-4 .7E-9
IMS 64K SRAM IMS 64K SRAM EDI 256K
1.6 E-9
1.3-2 .7 E-9
1.6E-9
1.3-2 .7 E-9
Ele:~nic
SRAM SRAM SRAM SRAM
Corn’cl -35 2E-9 5V lE-9 Jetliner/34 SRAM Fleet of -33 IDT 256K 5E-10 5V 3.3E-10 Corn’cl SRAM Jets/l 11 * Calculated rates are Riven as either a single value, in which case the rate is from the BGR method, or as a-b, wh&e a is the rate from-the neutron cross section method, and b is from the BGR method. 3.3.3
MAN-MADE
SOURCES
As indicated in section 2.3, man-made sources produce environments that are also capable of inducing single event effects. There are no actual confirmed field measurements of such upsets but we do have SEU and SEL occurrences induced in devices by man-made sources during the course of accelerated tests. Perhaps the best example is offered by the WNR neutron beam at Los Alamos (spectrum given in Fig. V-26). Several different lM SRAMS were tested in the WNR beam [64], and the resulting upset rates are given normalized to the atmospheric neutron spectrum at 40,000 feet. These normalized SEU rates measured at the WNR are given in Table V-11 along with rates calculated using the BGR method with the Weibull fit i.e. Eq. (9). Good agreement is achieved in almost all cases, however, this is not true if only a single threshold value for the SEU cross section were used [641. The importance of using the entire SEU cross section curve, i.e., integrating over the full curve of LET cross section, was noted for heavy ions as well in section 3.3.1 (see Fig. V-40 R-O and R-I columns). The large difference in the calculated rate for the Sony lM SRAM is to be noted in Table V-11 when the SEU cross sections from two different SEU tests were used [62, 113]. This is consistent with a recent finding for this part [128] that the inherent variability between devices and bit-pattern sensitivity dependence makes predicting error rates for Sony SRAMS very difficult [128].
V-64
Table V-11. Calculated
SRAM Mfr.
Comparison
of Upset Rates in lMbit
SRAM Part #
Reference for Heavy Ion SEU Data
Micron MT5C1OO8 Micron MT5C1OO8 Hitachi HM628 128 Hitachi HM628128 Sony CXK58 1000 Sony CXK581OOO *Calculated using the proton cross section
[112] [62] [110] [110] [113] [62] method
V-65
SRAMS Measured
Calculated (BGR Meth w/Multi-step SEU cross section) [33] 2.70E-09 1.00E-W 4.1 OE-10 *6.3E_lo 1.64E-10 2.4E-11
in WNR and as
Measured Rate at WNR SEU/bit hr 164] lE-W lE-W 7E-10 7E-10 2E-10 2E-10
4.
SYSTEMS 4.1
CONSIDERATIONS
PROBABILISTIC
NATURE
OF SEE
Single event effects are probabilistic in nature. They are governed by the Poisson distribution because they represent the occurrence of independent events that take place at a fixed rate. If the SEE rate is R and the time interval of interest is T then M = RT = mean or expected number of effects over the time interval, and by the Poisson distribution.
(lo)
P (n, M) = Mne-M / n! where n = number of effects during the time interval P (n,M ) = probability of exactly n effects over the time interval The results of greatest interest are the probabilities effects, P (1 +, M ) which are related as
of no effects, P(O, M ) and of one or more
P(l+, M)= 1- P(O, M)
(11)
P (O,M) = e-M
12)
The cumulative probability of an effect, P( 1 +, M) is shown in Fig. V-37. When M is small, i.e., HO. 1, the SEE probability and the rate multiplied by the time interval are the same.
P(l+, M)=l-P(O,
M) S1-(1-M)ZM
(13)
This is not true when the probability is large, i.e., >0.1. Thus if the rate and time interval are such that M, the expected number of effects is 0.1, then the probability is ().1. This means that if the time interval were 1/10 of the mean time between effects, O.I/R, then M = (. I/R) x R =.1 and there is still a 109i0chance of 1 or more effects occurring. However, if RT were 1, i.e., T, the time interval was the mean time between effects or l/R, then the probability of experiencing 1 or more effects is only 0.63 and even for a time interval 3 times as long, 3/R, the probability is larger, 0.95, but still not up to the 0.99 level . 4.2
ACCEPTABILITY
OF EFFECT
RATES
FOR DESIGN
Each program must develop its own acceptability criteria regarding SEE rates to demonstrate that the SEE responses do not cause of the equipment to fail to meet their functional and/or parametric However, at the outset, a large number of parts such as diodes, discrete bipolar specifications. transistors, signal MOSFETS (low voltage), etc., maybe excluded because their only known SEE responses are transient noise spikes. These noise spikes will be unimportant for equipment that is designed to tolerate noise from other sources such as shot noise and EMI. Second, depending on the environment in which the system will be used, the program may determine an acceptable maximum LET threshold for upset and latchup. Parts that exhibit upset or latchup only for LET values greater than this maximum threshold are assumed to be essentially immune from these single event effects, or equivalently, the probability is small enough as to be completely negligible. For example, for proton and neutron environments (e.g., South Atlantic Anomaly, aircraft altitudes, and accelerators), based on past experience with microelectronic parts, a reasonable LET threshold for SEL and SEU is in the range of 6-10 MeVcm2/mg[53]. Although an LET of 10 MeVcm2/mg is the generally accepted upper bound for proton effects, there are some opinions that it could be larger [100]. Higher LET thresholds could result from technology v-66
dependent and/or geometry dependent (e.g. strong differences along different axes of rotation [138]) gain mechanisms that might be initiated by protons in some devices [106]. More generally, however, parts with an LET threshold> 10 MeVcm2/mg can be considered as immune to SEE in proton and neutron environments. The demonstration of system hardness to SEE should be accomplished by an application analysis, possibly in conjunction with specific testing. If the required acceptability is not demonstrated, measures that can be used to “harden” the design include part substitutions and implementation of hardware and/or software mitigation measures such as error detection and correction (EDAC), redundancy schemes, etc., (see [123, 129, 130]). 4.2.1
DETERMINATION
OF SEU
AND
SEL
ACCEPTABILITY
The detailed demonstration of SEL and SEU acceptability should account not only the total number of SEE occurrences expected during the mission, but also for the worst case peak SEE rates resulting from the peak environment to which the equipment is exposed. Examples of peak environments include low earth orbit missions (proton flux is encountered only when passing through South Atlantic Anomaly about four 15 minute periods/day and the heavy ions and protons brought on for a few hours by a solar energetic particle event. If SEL detection and reset is used, it should be shown that the peak occurrence rate and the total number of occurrences can be handled by the detection/reset approach without jeopardizing the system level operational requirements of the equipment even during the worst case peak particle flux. For SEU, it should be shown that error correction mechanisms such as self correcting circuitry or EDAC will remain effective even during the worst case peak particle flux. 4.2.2
SEU IMPACTS
Depending on circuit design, system architecture, and system operational specifications, some SEUS may have no impact on specified equipment performance. In cases where this can be demonstrated by either analysis or test, the associated subelements or parts are acceptable in the equipment. The hardware/software details which can result in SEU acceptability are numerous and depend on equipment and system design. They therefore must be treated by the equipment designer on a case-by-case basis through a detailed application analysis. Example situations which are expected to lead to acceptability areas follows: 1) Transient SEUS with maximum amplitudes and durations smaller than those which could result in failure of the 2) Memory elements or parts for which the equipment equipment to meet it’s requirements. performance does not depend on a single reading of an upsetable memory bit and for which the upsetable memory bit will be reset by continual input data at a rate which is adequate to preclude error propagation and/or system performance beyond specified tolerance limits, 3) Equipment or subelements which have effective mitigation techniques such as error detection and correction (EDAC) built in. 4.2.3
SEL
IMPACTS
Because latchup may affect a system more seriously than upset, SEL acceptability may be more strictly imposed. One approach to this is to require that SEL for any particular part/application in a system is considered acceptable if all of the following conditions are met: a) There is a means for detecting any SEL in the equipment and resetting the latched part or equipment to normal operation. b) The operational consequences of the SEL for the maximum possible time period between the onset of SEL and reset to normal operation, as well as the maximum frequency of occurrence, are acceptable to the subsystems and personnel with which the equipment interfaces. V-67
c) No damage will occur to the part as a consequence of remaining in the latched condition during the time between latchup and power shut down. 4.2.4
STATISTICAL
TREATMENT
OF SEE
Due to the probabilistic nature of SEE occurrence as discussed in section 4.1 one method for The statistical dealing with the acceptability of SEE rates is through a statistical requirement. requirement can be specified in terms of the overall system SEE rate, Rs or a probability of failure from SEE, Pfe The system SEE rate is assumed to be equal to the sum of the individual device by a usage factor that depends on the system architecture, software and SEE rates, each weighted application [11 6]. Thus, total
R, = ~ Rd (n) U~ (n) U~ (n) Us (n) U, (n) rl=l
(14)
where Rs = system SEE rate n = device number Rd(n) = SEE rate for device n Uh (n)= hardware usage factor for device n Uf (n) = firmware usage factor for device n Us (n) = software usage factor for device n Ua (n)= application usage factor devices n The hardware factors, Uh, are obtained from examination of the circuit wiring and timing characteristics of the system design. In cases where it is clear that portions of a device could never be exercised or timing restrictions would clearly limit the upset rates, than a hardware usage factor of less than one is assigned. In cases where the usage is not certain, or there is not enough information to base a decision, a usage factor of one (or worst case usage) is assumed. The firmware factors, Uf, are obtained by examining characteristics of the firmware that would determine the pattern and frequency of read/write operations in individual storage locations. For instance, the firmware may be designed such that a particular storage location is always refreshed with correct data just prior to reading it, thus limiting the available window of susceptibility to upsets. In other cases, the firmware may be designed such that some physically available storage locations are never used, so that upsets in these locations would never have any effect. These fiimware usage factors are typically more difficult to determine than the hardware usage factors. The software factors, Us, are obtained by examining characteristics of the software that would affect observed upset rates. For example, if the software never uses all available storage locations, then upsets in those unused locations would not cause an error. Also, the software may limit the chance of upsets in the time domain. For example, the software may periodically refresh storage locations that have been sitting idle, thus reducing the chance of upsets accumulating. This may take the form of background memory scrubbing, stale-data flags for cache memory, etc. These software usage factors are typically more difficult to determine than the firmware usage factors described above.
The application factors, Ua, are obtained by examining characteristics of the application that would affect observed upset rates. For example, if a memory array was used to refresh a video screen every few milliseconds, then upsets would not normally be seen by an operator except in the rare event that the screen was “frozen” for diagnostic purposes and left that way for several hours. In other cases, an application may never use certain portions of the hardware, firmware,
v-68
or software at all. These application usage factors are typicaUy more difficult to determine than the software usage factors described above, Again, if they are not known in advance, 100% usage, or an application factor of one, must be assumed. From Eqs ( 11) and ( 12), the probability of failure, Pf, due to one or more SEE occurrences during the time interval T is, Pf
(15)
=1-exp(-RST)
Thus, the acceptability of the system SEE rate can then be judged according to one of two types of requirements that may be imposed by a program on systems using electronic components. One requirement is based on the SEE rate, and the other on the probability of failure due to an SEE occurrence. Alternately, the reliability, expressed as 1- Pf, rather than the failure probability, may be specified. In the first case the system SEE rate may be specified to be less than a stipulated fraction of the standard reliability rate covering physical failures calculated for the system using conventional reliability models. These models are based on the methodology established by MIL-Handbook-217[ 132]. A further requirement may be added to show that through a Failure Modes and Effects Analysis (FMEA) any SEE occurrence would be detected if it caused the system to operate outside of equipment specifications. The second approach is to specify that the failure probability (or alternately the reliability) allowed in a system due to one or more SEE occurrences is less than (or greater than) a stipulated value. The program may set the specified fraction of standard reliability or failure probability, or the design organization may establish such values and then justify them to the program. In either case the design organization must demonstrate that it has adequately accounted for the occurrence of single event effects within the system. 5.
ACKNOWLEDGMENTS
I would like to acknowledge the assistance of the following colleagues for providing useful data and engaging in valuable technical discussions: D. L. Oberg, D. W. Egelkrout, P. P. Majewski, J. L. Wert and P. R. Measel of the Boeing Radiation Effects Laboratory (BREL), L. Moritz of TRIUMF, A, Taber of Loral Federal Systems, P. M. O’Neill of NASA-JSC, M. A, Shea and D. F, Smart of Phillips Laboratory and R. Koga of the Aerospace Corporation. I would also like to thank the following BREL personnel, E. L. Craft for the preparation of the manuscrip~ and G. A. Perry for his assistance, and finally, my wife for her patience.
V-69
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6. 1.
D. Binder, E. C. Smith and A. B. Holman, “Satellite Anomalies Rays”, IEEE Trans. Nucl. Soc ., NS-22, 2675, Dec. 1975
2.
J. C. Pickel and J. T. Blandford “Cosmic Ray Induced Errors in MOS Memory Cells”, IEEE Trans. Nucl. Sot. NS-25, 1166, Dec. 1978
3.
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