Symbolic Analysis and Reduction of VLSI Circuits

Symbolic Analysis and Reduction of VLSI Circuits

This page intentionally left blank

Zhanhai Qin Sheldon X. D. Tan Chung-Kuan Cheng

Symbolic Analysis and Reduction of VLSI Circuits

Springer

eBook ISBN: Print ISBN:

0-387-23905-7 0-387-23904-9

©2005 Springer Science + Business Media, Inc.

Print ©2005 Springer Science + Business Media, Inc. Boston All rights reserved

No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher

Created in the United States of America

Visit Springer's eBookstore at: and the Springer Global Website Online at:

http://ebooks.springerlink.com http://www.springeronline.com

To our wives Li, Yan, and Jenny.

This page intentionally left blank

Contents

Dedication List of Figures List of Tables Preface Acknowledgments

v xiii xix xxi xxiii

Part I Fundamentals 3

1. INTRODUCTION 1 What is Symbolic Analysis 1.1 A “Hello-World” Example 1.2 Problem Formulation for Symbolic Analysis 2 Linear Circuit Reduction 2.1 Projection-Based Model Order Reduction 2.2 Generalized Transformation 3 Symbolic Analysis for Analog Circuit in a Nutshell 3.1 Topological Analysis 3.2 Determinant Decision Diagram 3.3 Symbolic Analysis of Nonlinear Circuits 4 What’s Covered in this Book 4.1 Symbolic Analysis in Digital Circuitry 4.2 Symbolic Analysis in Analog Circuitry 5 Summary

3 4 4 6 6 6 7 8 9 11 12 12 13 13

2. BASICS OF CIRCUIT ANALYSIS 1 Time Domain Analysis 1.1 RC Interconnect Circuit Formulation

15 16 16

viii

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

1.2 1.3 1.4 2

3

4

RLC Interconnect Circuit Formulation General RLC Interconnect Circuit Formulation Remarks

Responses in Time Domain 2.1 Responses in Closed Form 2.2 Taylor Expansion in Time Domain Domain Analysis 3.1 Transfer Function 3.2 Responses from Domain to Time Domain Preliminaries of Symbolic Analysis 4.1 Matrix, Determinant, and Cofactors 4.2 Cramer’s Rule

18 20 23 24 24 24 27 27 28 29 29 30

Part II Linear VLSI Circuits 3. MODEL-ORDER REDUCTION 1 Domain Analysis 2 Moments and Moment-Matching Method 2.1 Concept of Moments 2.2 Delay Estimation Using Moments 2.3 Deriving Moments from MNA Formulation 2.4 Deriving Moments for RLC Trees Realizable Topological Reduction Methods 3 3.1 TICER 3.2 Realizable RLC Reduction 3.3 Scattering-Parameter-Based Macro Model Reduction 4 Summary 4.

GENERALIZED TRANSFORMATION — FUNDAMENTAL THEORY 1 Introduction 2 Classical Transformation 2.1 Numerical Example Transformation and Gauss Elimination 2.2 2.3 Notations and Terminologies to be Used 3 Generalized Reduction 3.1 Branch with RCLK Elements 3.2 Branches with Current and Voltage Sources

35 35 35 35 36 41 41 46 48 51 54 61 63 64 65 65 66 67 67 68 70

ix

Contents

4 5 6

3.3 RCLK-VJ Generalized Formulae for 3.4 Higher-Order Truncation Node Ordering Generalized Reduction Flow Summary

Transformation 71 72

TRANSFORMATION — 5. GENERALIZED ADVANCE TOPICS 1 Common-Factor Effects 1.1 Example on Common-Factor Effects 1.2 Existence of Common Factors 1.3 Common Factors in Current Source Transformation 2 Revised Generalized Reduction Flow—A Redundancy-Free Version 3

4

5 6 7

6.

Multiport Reduction 3.1 Backward-Solving in LU Factorization Recovery 3.2 Multiport Reduction Flow 3.3 Treating Roundoff Errors 4.1 Fundamentals of Roundoff Errors 4.2 Roundoff Errors in Transformations Transformation 4.3 Solution to Roundoff Problems in

73 74 76 77 77 77 79 82 83 85 85 87 89 89 89 91 92 95 97 97 97 103

Experimental Results Summary Appendices 7.1 Existence of Type-II Common Factor 7.2 Recursive Existence of Type-II Common Factor 7.3 Existence of Type-I and Type-II Common Factors in Current 103 Source Transformation 111 7.4 Simplest Form of Transformation

TRANSFORMATION: 117 APPLICATION I — MODEL STABILIZATION 117 1 Hurwitz Polynomial 118 2 The Routh-Hurwitz Criterion 118 2.1 Necessary Conditions 2.2 The Routh-Hurwitz Criterion—A Necessary and Sufficient 119 Condition 123 2.3 Proof of the Routh-Hurwitz Criterion

x

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

3 4 5

7.

Stabilizing Models After Experimental Results Summary

Reduction

TRANSFORMATION: APPLICATION II — REALIZABLE PARASITIC REDUCTION 1 First-Order realization 2 Admittance Not Realizable in Nature 3 Idea of Templates 4 Geometric Programming 4.1 Intuitions 4.2 Primal and Dual Functions 4.3 Orthogonality Conditions 4.4 Solution Space of Dual Problems 4.5 Geometric Programming with Constraints 5 6 7

Template Realization Using Geometric Programming Experimental Results Summary

136 140 140

141 141 142 143 144 144 145 146 146 146 149 150 152

Part III Analog VLSI Circuits 8. TOPOLOGICAL ANALYSIS OF PASSIVE NETWORKS 1 Review of Node Admittance Matrix 1.1 Incidence Matrix of Undirected Graph 1.2 Incidence Matrix of Directed Graph 1.3 Composition of Node Admittance Matrix 2 Problem Formulation 2.1 Driving-Point Admittance 2.2 Open-Circuit Impedance 2.3 Network Transfer Functions 3 Topological Formulas 3.1 Topological Formula for Determinant 3.2 Topological Formula for 3.3 Time Complexity 4 Flow-Graph Technique 5 Summary

155 155 155 156 159 160 161 162 164 164 165 168 173 174 183

Contents

xi

9. EXACT SYMBOLIC ANALYSIS USING DETERMINANT DECISION DIAGRAMS 1 Combination Set Systems and Zero-Suppressed Binary Decision Diagrams 2 DDD Representation of Symbolic Matrix Determinant 3 An Effective Vertex Ordering Heuristic 4 Manipulation and Construction of DDD Graphs 4.1 Implementation of Basic Operations 4.2 Illustration of Basic Operations and its Use in Circuit Sensitivity 5 DDD-based Exact Symbolic Analysis Flow 6 Related to Other Decision Diagram Concepts 7 Application to Symbolic Analysis of Analog Circuits 8 Summary 9 Historical Notes on Symbolic Analysis Techniques

200 203 204 206 208 209

10. S-EXPANDED DETERMINANT DECISION DIAGRAMS FOR SYMBOLIC ANALYSIS 1 Introduction 2 s-Expanded Symbolic Representations 3 Vertex Ordering for s-Expanded DDDs 4 Construction of s-Expanded DDDs 4.1 The Construction Algorithm 4.2 Time and Space Complexity Analysis 5 Applications of Deriving Transfer Functions 6 Summary

211 211 212 215 217 217 218 221 222

11. DDD BASED APPROXIMATION FOR ANALOG BEHAVIORAL MODELING 1 Introduction 2 Symbolic Cancellation and De-cancellation 3 Dynamic Programming based Generation of Dominant Terms 4 Incremental k-Shortest Path Algorithm 4.1 DDD-based Approximation Flow 5 Application to AC Characterization of Analog Circuits 6 Summary 7 Historical Notes on Symbolic Approximation 8 Appendix

225 225 226 228 231 237 238 240 240 241

185 185 187 191 196 197

xii

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

12. HIERARCHICAL SYMBOLIC ANALYSIS AND HIERARCHICAL MODEL ORDER REDUCTION 245 1 DDD-based Hierarchical Decomposition 246 246 1.1 Subcircuit Reduction 1.2 Overview of The Simulation and Reduction Algorithm 249 2 DDD-based Hierarchical Decomposition 250 3 Cancellation Analysis for Subcircuit Reduction 253 3.1 Cancellation Due to Circuit Devices 253 254 3.2 Cancellation Due to Subcircuit Reduction 3.3 Theoretical Analysis of Cancellation Conditions 257 3.4 Device-Level Cancellation From Subcircuit Reduction’s Perspective 259 3.5 Cancellation at Different Hierarchical Circuit Levels 259 4 General s-Domain Hierarchical Network Modeling and Simulation Algorithm 261 4.1 Cancellation-Free Rational Admittance 261 4.2 Y-expanded DDDs 262 4.3 Computation of Cancellation-Free Rational Admittances 264 4.4 Clustering Algorithm 267 5 Hierarchical Analysis of Analog Circuits – Examples 267 6 Summary 270 7 Historical Notes on the Model Order Reduction 271

References

273

Index

281

List of Figures

1.1

Symbolic analysis of a simple RC circuit

1.2

RC circuit for illustration of DDD

10

1.3

A matrix determinant and its DDD representation.

11

2.1

A RC tree demonstrating nodal analysis formulation: current flowing out of a node is equal to currents flowing into the node

16

RLC parasitics of a segment of interconnect on metal layers:(a) illustration of orthogonal interconnect layers (b) RLC parasitic model of an interconnect segment in layer 3.

18

RLC circuit meeting the two prerequisites. Shaded ones are the so-called intra-branch nodes

19

2.2

2.3

4

2.4

A RLC tree demonstrating modified nodal analysis formulation. 22

2.5

A linear network with two inputs and three outputs.

28

3.1

Scenario that the median and mean points mismatch: when the unit impulse response (scaled) is not symmetric, 50% delay of unit step response or the median point of does not overlap with the mean point of

37

Scenario that the median and mean points of overlap: when is symmetric, 50% delay point of matches the mean point of i. e., the approximation is exact.

38

3.3

The original RLC tree in Example 3.3.

43

3.4

The “resistive tree” for computing

3.5

The “resistive tree” modified based on the original RLC circuit by zeroing out inputs and replacing capacitors and inductors with current and voltage sources, respectively.

3.2

in Example 3.3.

45

46

xiv

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

3.6

3.7 3.8 3.9

3.10

Illustration showing a type of non-tree circuit configuration having trivial DC solutions: (a) A RLC network; (b) the companion network of (a) for which all the links can be specified by current sources (or capacitors in the original network).

47

Two models connected in series. (a) The original circuit; (b) the reduced circuit.

51

Two models connected in parallel. (a) The original circuit; (b) the reduced circuit.

51

Transfer function evaluation and propagation. Each branch in the tree is a RLC model.

53

2-port network showing incident waves and reflected waves used in scattering parameter definitions.

55

3.11 A multiport representation 3.12 Merge the two networks denoted by perfectly interconnected nodes and

57

and

at two 58

3.13 Illustration of self merging

60

A numerical example on transformation: (a) before the transformation; (b) after the transformation.

65

Conversion on mutual K in (a)given mutual K element; (b) converted self K elements.

69

transformation with current source involved: (a)circuit schematic before the transformation; (b)circuit schematic after the transformation.

70

transformation with voltage source involved: (a)circuit schematic before the transformation; (b)circuit schematic after the transformation.

70

A numerical example showing common factor existence: (a) is to be eliminated; (b) is to be eliminated; (c) after both and are eliminated.

78

Example revisit transformations: (a) original circuit; (b) after the transformation on node (c) after the transformation on

85

5.3

An example floating point number system

90

5.4

enumeration of the numerator of (a) algorithm requiring addition and multiplication operations only; (b) algorithm requiring extra division operation.

93

4.1 4.2 4.3

4.4

5.1

5.2

5.5

Finding common partial terms in the numerator of

by partition. 94

xv

List of Figures

Transient response evaluated using transformation with Hurwitz approximation as compared to AWE method and SPICE simulations for coupled RLC bus lines. transformation with recogniz5.7 Order of admittance after ing common factors as compared to a naive implementation without recognizing common factors. Transformations in Proof of Th. 5.3: (a) elimi5.8 Three nating (b) eliminating (c) eliminating Transformations in Proof of Th. 5.4: (a) 5.9 A Series of eliminating (b) eliminating (c) eliminating (d) eliminating Transformations in Proof of Th. 5.3: (a) elimi5.10 Three nating (b) eliminating (c) eliminating transformation on 5.11 Illustrating orders of admittances in 6-node complete graph: (a) (b)

5.6

(c)

96

97 99

104 106

(d)

111 (e) 5.12 Illustration for proof of Theorem 5.6: (a) are to be eliminated; (b) are to be eliminated; (c) is to 114 be eliminated; (d)transformation finished. 124 plot showing vectors 6.1 A 6.2 Examples showing the sign difference of and for 129 different locations. must lie on the imaginary axis to make and agree 6.3 130 on sign. 133 6.4 2-D and 3-D Plots of when 134 when 6.5 2-D and 3-D Plots of 135 when 6.6 2-D and 3-D Plots of 136 6.7 Plot of root locations for different values. transformation with Hurwitz ap6.8 Pole analysis using proximation as compared to transformation only and AWE method for RLC power/ground mesh. 140 7.1 First Order Realization: (a) RC configuration; (b) RL configuration 142 transformation and 143 7.2 Unrealizable admittance after 144 7.3 Brune’s Admittance Structure Comparison of two reduced circuits 151 7.4 151 7.5 Comparison of responses of a RC network 152 7.6 Comparison of responses of a RLC network

xvi

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9

8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 8.21 8.22 8.23 8.24 9.1

An undirected graph with 4 vertices and 6 edges. 156 A directed and connected graph with 4 vertices and 6 edges. 157 A directed and unconnected graph with 7 vertices and 9 edges.158 A 4-node linear network used in Example 8.4. 160 One-port network driven by single current source 161 Two-port network driven by two current sources and 162 Illustration of the two-port in determining open-circuit impedances.163 A loaded passive two-port N 164 Removing leaf node one at a time corresponds to expanding the row of the node in and its minor matrices. 167 An illustrative one-port example. 168 All the possible trees of the one-port with resistive branches only.169 Minor matrix 169 Computing minor matrix from and 170 Network deduced from N from Fig. 8.4 by merging and the ground. 171 A 2-tree example used in Example 8.15. 171 Using topological formulas to solve for open-circuit transfer 172 impedance of a 2-port. Using topological formulas to solve for open-circuit transfer impedance of a 2-port. 173 Counter-example showing invalid 2-trees in the computation of cofactors 173 The flow graph of (4.2). 175 The subgraph of in (4.2). 177 The two connections of 177 The four one-connections of (a)(b) The two one-connections 178 from 1 to (c)(d) The two one-connections from 1 to Graph of the proof of Lemma 8.1. 181 181 Graph of the proof of Lemma 8.2. (a) A ZBDD example. (b) An illustration of the zero-suppression 186 rule.

9.2

A ZBDD representing {adgi, adhi, afej, cbij, cbgh} under order-

9.3 9.4 9.5

ing A signed ZBDD for representing symbolic terms. A determinant decision diagram for matrix M. DDD representing det(M) under ordering

188 189 191 192

List of Figures

9.6 9.7 9.8 9.9

9.10 9.11 9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 9.20 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9

A ODD vertex ordering heuristic. An illustration of DDD vertex ordering heuristic. An illustration of DDD construction for band matrices. A comparison of DDD sizes verse numbers of product terms for band matrices. A three-section ladder network. Illustrations of DDD graph operations. DDD-based derivation of cofactors. Illustration of DDD-based cofactoring. DDD-based exact symbolic analysis flow A determinant expansion and its DDD representation. The MOSFET small-signal model. The Bipolar transistor model. The circuit schematic of bipolar The circuit schematic of MOS cascode Opamp. frequency responses versus COMP values An example circuit A complex DDD for a matrix determinant An s-expanded DDD by using the labeling scheme The s-expanded DDD construction with the second labeling scheme The basic s-expanded DDD construction algorithms operation operation Product term distribution of by the second labeling scheme. Sizes of DDDs vs sizes of the complex DDDs. A simplified two-stage CMOS opamp. Matrix patterns causing term cancellation. Cancellation-free COEFFMULTIPLY. Cancellation-free multi-root DDD. Dynamic programming based dominant term generation. Implementation of SUBTRACT() for symbolic analysis and applications. A reverse DDD. Incremental k-shortest path algorithm. Incremental k-shortest path based dominant term generation

xvii 193 193 195 196 196 198 202 202 204 205 206 207 207 208 209 213 214 216 218 218 219 220 222 223 226 227 228 228 230 231 233 234 235

xviii

11.10 11.11 11.12 11.13 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 12.12 12.13 12.14 12.15 12.16

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

THE RELAX() operation. DDD-based symbolic approximation flow CPU time vs number of ladder sections. Memory use vs number of ladder sections. A hierarchical circuit The general hierarchical network reduction algorithm flow Illustration of Theorem 12.1 Matrix patterns causing term cancellation. A simple RC circuit. Cancellation pattern due to subcircuit reduction An impedance stamp and the stamp in the reduced matrix. A determinant and its YDDD. Y-expanded DDD construction. Term-Cancellation Free YDDDMULTIPLY. Computation of the cancellation-free rational function from a YDDD. A second-order active filter. A linear model of an Opamp circuit. An active low-pass filter. An FDNR subcircuit. The frequency response of the active filters (exact vs 8th, 10th, 16th order approximation).

235 237 239 239 247 251 252 253 254 256 260 263 263 265 266 268 268 269 269 270

List of Tables

CPU runtime using technique as compared to SPICE3f4 for five industrial circuits. 7.1 Efficiency comparison 9.1 Summary of Basic Operations. 11.1 Poles and zeros for opamp TwoStage. 5.1

96 152 197 238

This page intentionally left blank

Preface

Symbolic analysis is an intriguing topic in VLSI designs. The analysis methods are crucial for the applications to the parasitic reduction and analog circuit evaluation. However, analyzing circuits symbolically remains a challenging research issue. Therefore, in this book, we survey the recent results as the progress of on-going works rather than as the solution of the field. For parasitic reduction, we approximate a huge amount of electrical parameters into a simplified RLC network. This reduction allows us to handle very large integrated circuits with given memory capacity and CPU time. A symbolic analysis approach reduces the circuit according to the network topology. Thus, the designer can maintain the meaning of the original network and perform the analysis hierarchically. For analog circuit designs, symbolic analysis provides the relation between the tunable parameters and the characteristics of the circuit. The analysis allows us to optimize the circuit behavior. The book is divided into three parts. Part I touches on the basics of circuit analysis in time domain and in domain. For an domain expression, the Taylor’s expansion with approaching infinity is equivalent to the time domain solution after the inverse Laplace transform. On the other hand, the Taylor’s expansion when approaches zero derives the moments of the output responses in time domain. Part II focuses on the techniques for parasitic reduction. In Chapter 3, we present the approximation methods to match the first few moments with reduced circuit orders. In Chapter 4 we apply a generalized Y-Delta transformation to reduce the dynamic linear network. The method finds the exact values of the low order coefficients of the numerator and denominator of the transfer function and thus matches part of the moments. In Chapter 5, we handle two major issues of the generalized Y-Delta transformation: common factors in fractional expressions and round-off errors. Chapter 6 explains the stability of the reduced expression, in particular the Ruth-Hurwitz Criterion. We make an effort to

xxii

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

describe the proof of the Criterion because the details are omitted in most of the contemporary textbooks. In Chapter 7, we present techniques to synthesize circuits to approximate the reduced expressions after the transformation. In Part III, we discuss symbolic generation of the determinants and cofactors for the application to analog designs. In Chapter 8, we depict the classical topological analysis approach. In Chapter 9, we describe a determinant decision diagram (DDD) approach that exploits the sparsity of circuit matrices for a compact representation of a symbolic determinant. In Chapter 10, we apply the DDD approach to deriving the s-expanded polynomial from a determinant. In Chapter 11, we take only significant terms when we search through determinant decision diagram to approximate the solution. In Chapter 12, we extend the determinant decision diagram to a hierarchical model. The construction of the modules through the hierarchy is similar to the generalized Y-Delta transformation in the sense that a byproduct of common factors appears in the numerator and denominator. Therefore, we describe the method to prune the common factors.

ZHANHAI QIN, SHELDON X.-D. TAN, AND CHUNG-KUAN CHENG

Acknowledgments

Jeff Qin is obliged to Professor Chung-Kuan Cheng for his guidance and enlightenment during his graduate study at University of California, San Diego. Jeff Qin is grateful to Dr. Li-Pen Yuan for his encouragement while Jeff works at Synopsys. Sheldon X.-D. Tan is grateful to Professor Richard C.-J. Shi for his advising during his graduate studies at the University of Iowa and the University of Washington, which leads to some of the works presented in this book. Chung-Kuan Cheng is indebted to Professor Ernest Kuh for his guidance and inspiration toward circuit analysis research. Jeff Qin thanks his wife Li Yang, Sheldon X.-D. Tan thanks his wife, Yan Ye, and Chung-Kuan Cheng thanks his wife Jenny Cheng for their consistent patience and encouragement throughout the course of writing this book. Jeff Qin and Chung-Kuan Cheng would like to acknowledge the support of the NSF, GSRC, SRC, Cal IT2, and California MICRO program matched by Altera, Conexant, Fujitsu, HP, Mentor Graphics, NEC, Qualcomm, Sun Microsystems, and Synopsys. The support is essential to keep the project surviving throughout Jeff’s Ph.D. program and the composition process of the book. Sheldon X.-D. Tan would like to thank for the support of UC Regent’s Faculty Fellowship.

This page intentionally left blank

PART I

FUNDAMENTALS

This page intentionally left blank

Chapter 1 INTRODUCTION

1.

What is Symbolic Analysis?

Symbolic analysis is to calculate the behavior or the characteristics of a circuit in terms of symbolic parameters. Symbolic analysis was pioneered by topological analysis methods such as the spanning tree enumeration methods [12] and signal flow graph methods [58], which were based on the topology of given circuits. Symbolic expressions can also be generated directly from admittance matrix as shown in the some modern symbolic analyzers [37, 77]. Symbolic analysis offers great advantages over numerical simulators such as SPICE [63], which only provide numerical results, in that symbolic simulators present the relationship between circuit parameters and circuit behavior in symbolic closed-form expressions. As contribution of circuit parameters to circuit characteristics becomes obvious to designers when symbolic analysis is used. The technique is being used in many applications such as optimum topology selection, design space exploration, behavioral model generation, and fault detection, which have been summarized and illustrated by researchers [38]. On the other hand, symbolic analysis cannot replace the numerical analysis as it cannot analyze very large circuits in general. Instead it is an essential complement to numerical simulation. This is especially the case for analog circuit designers where the circuit sizes are not very large, yet circuit performance characteristics are dynamically determined by settings of many different circuit parameters [29]. Algebraic analysis lies between symbolic analysis and numerical simulation. Thus it has the advantages of both, i. e., circuit parameters are numerical values and transfer functions are presented in closed-form. Thus it explicitly shows the relationship of circuit inputs and outputs and it is able to handle very large circuits.

4

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

1.1

A “Hello-World” Example

As a simple example, Fig. 1.1 shows a circuit with two resistors and two capacitors. This circuit is stimulated by a voltage source, and the other end is

Figure 1.1. Symbolic analysis of a simple RC circuit

grounded. Symbolically in domain,

can be written as

This symbolic equation tells us that it is a second order low-pass filter with DC gain = 1. Of course for this simple circuit, every electrical engineer can write up the actual equation in the old pencil-and-paper style. But when circuits become large, such kind of transfer functions can grow exponentially in terms of number of product terms such as On the other hand, symbolic analysis may be able to generate them automatically. If a symbolic analyzer produces a symbolic transfer function with hundreds or thousands of symbolic product terms and with all circuit parameters mixed together, it’s hard to identify the influence of every parameter to the whole function. Simplification can be applied to sort out the dominant terms of parameters. There are two strategies of doing this: Mixed symbolic-algebraic analysis keeps only a small number of circuit parameters as symbols and the rest as numerical values. It helps reduce the number of total product terms and the length of each of them. The extreme of this approach is the algebraic analysis in which all circuit parameters are numerical values and the only symbol in the expressions is the complex frequency Symbolic simplification discards insignificant terms based on the relative magnitudes of symbolic parameters and the frequency defined at some nominal design points or over some ranges. It can be performed before, during, or after the generation of symbolic terms [8, 42, 73, 107, 27, 37, 98].

1.2

Problem Formulation for Symbolic Analysis

Consider a lumped linear(ized) time-invariant analog circuit in frequency domain. Its circuit equation can be formulated, for example, by the nodal

Introduction

5

analysis approach in the following general form [96]:

The circuit unknown vector x may be composed of node voltages, and the admittance matrix A is an sparse symbolic matrix, is a vector of external sources. Symbolic analysis of analog circuits can be stated as the problem of solving the symbolic equation (1.1), i. e., to find a symbolic expression of any circuit unknowns in terms of symbolic parameters in A and symbolic excitations expressed by According to Cramer’s rule, the component of the unknown vector x is obtained as follows:

where det(A) is the determinant of matrix A, and in (1.2) is the cofactor of det(A) with respect to element of matrix A at row and column Most symbolic simulators are targeted at finding various network functions, each being defined as the ratio of an output from x to an input from Generally, a transfer function of a linear(ized) circuit can be obtained as a rational function in the complex frequency variable

where and are symbolic polynomial functions in circuit parameters These polynomials in turn can be expressed in a nested form or an expanded sum-of-product form. Again, we can categorize symbolic analysis in terms of number of symbols in a given circuit: and 1 If the polynomial coefficients, it is named fully or exact symbolic analysis.

contain only symbols,

2 If only some circuit parameters are represented as symbols, it is named partial or mixed symbolic analysis.

has only one symbol – the 3 In the extreme case is that transfer function complex frequency which happens when all circuit parameters are numerical values and the symbolic analysis degenerates to algebraic analysis. The central issue in symbolic analysis is to find symbolic expressions of det(A) and the cofactors of det(A).

6

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Linear Circuit Reduction

2.

linear circuits targeted in this book refer to interconnect parasitics in modern VLSI designs. Interconnects become more important to digital circuit designers than never before, because the quality of the interconnects needs to be examined in every aspect from delay to signal integrity issues. Although accurate analysis is preferable, turn-around time is never a negligible factor to be considered. Because a huge amount of interconnects are present in typical VLSI designs. Nowadays, a million-transistor design can easily accommodate miles of interconnects. To analyze interconnect parasitics accurately and quickly, linear circuit reduction has to be adopted. Researchers have devised a lot of techniques on this hot topic. Their works can be classified into two categories: projection-based model order reduction, generalized

2.1

transformation.

Projection-Based Model Order Reduction

Modeling complicated linear circuits with simple yet accurate circuits is called model order reduction. The idea is to analyze or simulate the simplified models to reduce circuit verification time. A number of projection-based model-order reduction based techniques have been introduced [23, 24, 25, 64, 66, 80, 79] to analyze the transient behavior of interconnects. Those projection-based algorithms mainly work for passive linear networks as the computation of moments and Krylov space base vectors requires a special partitioning of circuit matrices and solving of the partitioned circuit matrices iteratively. The reduction is typically done in frequency or domain, where is the complex frequency variable and defined as where is the radical frequency in complex domain analysis. In frequency domain analysis, storage elements such as capacitors and conductors all have their impedance written in in frequency domain. For example, a capacitor with capacitance value 0.1 farad can be written as in frequency domain as its impedance value.

2.2 Generalized

Transformation

Another different approach to circuit complexity reduction is by means of local node reduction and realization of reduced networks based on local node elimination and realization [22, 74, 2, 69, 75, 82]. The main idea is to reduce the number of nodes in the circuits and approximate the elements of the reduced system with either order-reduced rational functions or realized low order RLCM networks. The major advantage of these methods over projection-based methods is that the reduction can be done in a local manner and no overall solutions

Introduction

7

of the entire circuit are required, which makes these methods very amenable to attack large linear networks. This idea was first explored by selective node elimination for RC circuits [22, 74], where time constant analysis is used to select nodes for elimination. Generalized transformation [69, 68], RLCK circuit crunching [2], and branch merging [75] have been developed based on nodal analysis, where inductance becomes susceptance in the admittance matrix. Generalized transformation provides a general node elimination based parasitic reduction technique [68]. A generalized block transformation based on modified nodal analysis formulation has been proposed [82, 83] recently, which leads to the general hierarchical model order reduction techniques and it can be applied to any linear circuits with any linear device. Both Generalized transformation and hierarchical model order reduction techniques will be discussed in detail in the following chapters. Both projection-based and node elimination based model order reduction methods can be viewed a special symbolic analysis where only the complex frequency variable is the symbol. In general, transfer functions are functions of which are called semi-symbolic analysis format from the perspective of symbolic analysis.

3.

Symbolic Analysis for Analog Circuit in a Nutshell

Research on symbolic analysis can be dated back to the last century. Developments in this field gained real momentum in 1950’s when electric computers were introduced and used in circuit analysis. Methods developed from the 1950’s to the 1980’s can be basically categorized as: 1 Tree Enumeration methods, 2 Signal Flow Graph methods, 3 Parameter Extraction methods, 4 Numerical Interpolation methods and 5 Matrix-Determinant methods.

The details of these method can be found in [38, 53]. In the late 1980’s, symbolic analysis gains renewed interests as industrial demands for analog design automation increased. Various methods are proposed to solve the long-standing circuit-size problem. The strategies used in modern symbolic analyzers in general come in two categories: those based on hierarchical decompositions [41, 81, 91] and those based on approximations [30, 98, 107, 42, 107, 18, 48, 49, 86].

8

3.1

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Topological Analysis

Symbolic analysis started with topological analysis [53]. The most two important algorithms are tree enumeration methods and signal flow graph methods. Tree enumeration method is one of the oldest, fully symbolic analysis methods proposed in the last century when Kirchoff and Maxwell first stated their results on RLC networks, which include only resistance, inductance and capacitance, in their classical works. In this method, a passive RLC network is represented as an undirected weighted graph G(N,E), where N is the set of nodes in the network and E is the set of edges with each edge representing a circuit element between the nodes the edge connects. The weight of each edge is the admittance of the corresponding circuit element. The basic idea in this method is that the determinant of the node admittance of an RLC network equals the sum of all tree-admittance products of the graph G(N, E). A tree-admittance product is the product of all the edge weights in a spanning tree of the G(N, E). So network transfer function calculation amounts to enumerating spanning trees of the undirected weighted graph. Some transfer functions, such as trans-impedance or voltage gain, may require finding a 2-tree. A 2-tree is a pair of node-disjoint subgraphs that individually are connected, acyclic, and together include all nodes. The attractive feature of this method is that all the product terms generated are irreducible or term-cancellation free.1 For an active network (with voltage-controlled current source), however, the original tree enumeration method cannot be directly applied. Two extension methods were proposed to solve this problem. The first is 2-graph approach [60] and the second is directed-tree approach [11]. In the 2-graph approach, each admittance of RLC circuit element is treated as a voltagecontrolled current source (VCCS) with controlling and controlled nodes coinciding. Signal-flow graph based methods are based on the signal-flow diagrams [58], which is a weighted, directed graph representing a set of linear equations, which can be expressed in the following general form:

where X is the vector formed by the dependent node variables, U is the vector formed by the independent node (source node) variables, and A and B are transmittance matrices constructed from the coefficients of the linear equations. Given a linear equation set in the form of (3.1), a signal flow graph can be constructed by the following rules: (1) Node weights represent variables (known 1

Term cancellation is due to the fact that two symbolic terms with the same symbol combination but opposite signs cancel each other.

9

Introduction

or unknown). (2) Branch weights (transmittance) represent the coefficients in the relationships among node variables. (3) Each dependent node variable equals the sum of the products of the incoming branch weight and the node variable from which the branch originates. Any transfer function from an input variable to an output variable can be computed by Mason’s rule [58] as follows:

where - (sum of all loop weights) + (sum of all second-order loop weights) - (sum of all third-order loop weights) + …, = weight of the

path from the source nodes

= sum of those terms in path

to the dependent node

without any constituent loops touching the

The loop is defined as the loop set formed by non-touching loops. The weight of the order loop is the sum (over all possible loop sets) of the products of the branch weights in these non-touching loops. Signal-flow graph method can be applied to various types (passive or active) of circuit networks, as the signal-flow graph is directly derived from linear equations and is independent of circuit formulations. This method, however, also suffers from the term-cancellation problem.

3.2

Determinant Decision Diagram

As we have introduced, symbolic analysis can be performed on topology of a given circuit, it can also be based on system matrix of the circuit. Determinant decision diagram belongs to the latter category. Determinant decision diagram is based on the two observations on symbolic analysis of large analog circuits: (a) the admittance matrix is sparse and (b) a symbolic expression often shares many sub-expressions. Under the assumption that all the matrix elements are distinct, each product term can be viewed as a subset of all the symbolic parameters. Therefore, a special data structure called Zero-suppressed Binary Decision Diagrams (ZBDDs) is adopted, which was introduced originally for representing sparse subset systems [61]. ZBDD is a variant of Binary Decision Diagram(BDD) introduced by Akers [1] and popularized by Bryant [4]. The decision graph based symbolic analysis method is inspired by the success of BDDs as an enabling technology for industrial use of symbolic analysis and formal verification in digital logic design [5]. This leads to a new graph

10

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

representation of a symbolic determinant, called Determinant Decision Diagram(DDD). As determinant is the building block of the explicit solution of any linear systems based on the Cramer’s rule, a fully symbolic analysis of any linear system will become possible with the DDD graphs. DDD representation has several advantages over both the expanded and arbitrarily nested forms of a symbolic expression. First, similar to the nested form, DDD-graph representation is compact for a large class of analog circuits. A ladder-structured network can be represented by a diagram where the number of vertices in the diagram (called its size) is equal to the number of symbolic parameters. As indicated by the experiments, the size of DDD is usually dramatically smaller than the number of product terms. For example, terms can be represented by a diagram with 398 vertices [77]. Second, similar to the expanded form, DDD representation is canonical, i.e., every determinant has a unique representation, and is amenable to symbolic manipulation. The canonical property is critical to efficient symbolic analysis [62]. Finally, evaluation and manipulation of symbolic determinants (such as sensitivity calculation) have time complexity proportional to the DDD sizes. The formal definition of DDDs will be introduced in Chapter 9. Here we just use the example circuit in 1.1 to illustrate the basic idea of the DDD representation of a determinant. By using the nodal analysis, the simple RC circuit in Fig. 1.2 can be formu-

Figure 1.2. RC circuit for illustration of DDD

lated as

The 3 × 3 matrix is the admittance matrix that we are interested. We view each entry in the admittance matrix as one distinct symbol, and rewrite its system determinant in the left-hand side of Fig. 1.3. Then its DDD representation is shown in the right-hand side.

11

Introduction

Figure 1.3. A matrix determinant and its DDD representation.

A DDD is directed acyclic graph and each non-terminal DDD vertex has two outgoing edges, called 1-edge and 0-edge. A 1-path in a DDD corresponds a product term in the original DDD, which is defined as a path from the root vertex (A in our example) to the 1-terminal including all symbolic symbols and signs of the vertices that originate all the 1-edges along the 1-path. In our example, there exist three 1-paths representing three product terms: ADG, – AFE and –CBG. The root vertex represents the sum of these product terms. Size of a DDD is the number of DDD vertices, denoted by DDD graph is also an ordered graph like Binary Decision Diagrams . This implies that the order of each symbol in any 1-path from (root vertex to 1terminal) is fixed with respect to other symbols. The ordering used in our example is A > C > B > D > F > E > G. Notice that the size of a DDD depends on the size of a circuit in a complicated way. Both circuit topology and vertex ordering have huge impacts on the DDD sizes. Given the best vertex ordering, if the underlying circuit is a ladder circuit, is a linear function of the sizes of the circuit. For general circuits, the size of DDD graph may grow exponentially in the worse case. But like BDDs, with proper vertex ordering, the DDD representations are very compact for many real circuits [77, 78].

3.3

Symbolic Analysis of Nonlinear Circuits

For wireless/communication applications, a number of circuits which operate at radio frequencies (RF) typically exhibits so-called mildly or weakly nonlinear properties where devices typically have a fixed dc operating point and the inputs are ac signals. When the amplitude of these input signals is small (such that their operation points do not change too much), the nonlinearities in these

12

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

circuit can be approximated adequately Volterra functional series [71] in both time and frequency domains. Volterra functional series can represent a weakly nonlinear function in terms of a number of linear functions called Volterra kernels. From circuit theory’s perspective, it leads to a set of linear circuits, called Volterra circuits, whose responses can adequately approximate the response of the original nonlinear circuit. Volterra function series based symbolic analysis has been explored in [97, 100]. Symbolic analysis of harmonic distortion in weakly nonlinear circuits was also reported by the same author in [100]. Symbolic analysis based on DDD graph and Volterra series for transient and distortion analysis was proposed in [101]. Symbolic analysis for hard nonlinear analysis based on piecewise linear concept was reported in [57, 56], which is based on the ideal diode modeling of piecewise linear functions and solves the so-called complementary linear program (CLP) symbolically using complementary-decision diagrams. The new method can derive the symbolic expressions for the nonlinear circuit responses in time domain. But its modeling and simulation capacity is still limited due to limitation of exact DDD-graph based symbolic analysis [77].

4.

What’s Covered in this Book

We start with review of the basics of circuit analysis methods in chapter 2. We discuss the nodal and modified nodal analysis formulation of RLC circuits and computation of their response in both time and frequency domains. We also review some of basic mathematic concepts in the symbolic analysis.

4.1

Symbolic Analysis in Digital Circuitry

Part II of the book focuses on the techniques for linear parasitic circuit reduction. The corresponding chapters are presented in Chapter 3 to Chapter 7. In Chapter 3 presents moment-based model order reduction technique for fast RLC linear circuit analysis. A realizable topological analysis based on local node elimination and first-order approximation will be discussed. Chapter 4 presents a generalized transformation to reduce the dynamic linear networks in frequency domain. The method finds the exact values of the low order coefficients of the numerator and denominator of the transfer function and thus matches part of the moments. Chapter 5 discusses in detail two major issues in the general transformation: common factors in fractional expressions and round-off numerical errors. The theoretical analysis and cancellations during the transformation are presented. Chapter 6 gives theoretical analysis of the stability of the reduced expressions from transformation via Ruth-Hurwitz Criterion. We make an effort to

Introduction

13

describe the proof of the Criterion because the details are omitted in most of the contemporary textbooks. Chapter 7 presents a template-based circuit realization technique to approximate the reduced expressions after the transformation.

4.2

Symbolic Analysis in Analog Circuitry

In Part III of this book, we discuss symbolic generation of the determinants and cofactors for the application to analog circuit analysis and designs. The corresponding chapters in this book are Chapter 8 to Chapter 12. We mainly present DDD-based symbolic analysis techniques as they represent the startof-the-art approaches to the symbolic analysis. Chapter 8 shows the relationships of circuit responses and circuit topologies, using the matrix approach. Because the topology-based circuit analysis method provides essential physical insights of circuits, a combination of it with model order reduction concepts raises special interest to researchers in layout-driven circuit reduction. Chapter 9 introduces the concept of determinant decision diagrams and their basic operations for symbolic analysis. A variable ordering heuristic is also presented and is shown to be optimal for ladder circuits. Chapter 10 introduces the concept of determinant decision diagrams for symbolically representing polynomials from a determinant. We show how DDD can be constructed from complex DDDs and the variable ordering used for DDDs. Chapter 11 presents several efficient algorithms for obtaining approximate symbolic expressions based DDD presentation of symbolic expressions. We show a dominant term of a determinant can be found by searching shortest paths in the DDD graphs. A incremental shortest paths search scheme was developed, which can efficiently find dominant product terms from DDD graphs presenting a determinant. Chapter 12 presents a general hierarchical model order reduction techniques, which is generalized transformation algorithms discussed in previous chapters. Some theoretical results regarding the term cancellation in the context of general hierarchical reduction are presented.

5.

Summary

In this section, we briefly review the concept of symbolic analysis and present the general formulation of symbolic analysis. Symbolic analysis has a long history and in a broad sense includes from classic topological based symbolic analysis methods to modern model order reduction techniques as frequency or domain analysis can be viewed as a special symbolic analysis. We then briefly survey existing symbolic analysis

14

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

and parasitic model order reduction methods reported in the past several years. We briefly review the generalized transformation and DDD graph-based symbolic analysis methods, which will be presented in detail in the following chapters. Analyzing circuits symbolically, however, still remains a challenging research issue. Instead of providing a solution of this field, we survey the recent advances in symbolic analysis in this book. Specifically, we will present the start of the art general transformation based parasitic reduction technique and DDD graph-based symbolic analysis methods. We hope those promising techniques will lead to more efficient modelin and analysis solutions to the current and future VLSI designs.

Chapter 2 BASICS OF CIRCUIT ANALYSIS

There has been striking progress in linear circuit reduction since the last two decades or so. Linear circuits that we will discuss throughout the book refer to parasitic RC and RLC circuits that represent interconnects on metal layers in modern ICs. As we are entering the very deep submicron era with the smallest CMOS transistor less than 65nm in width, interconnects start playing a significant role than ever before. Interconnects are important to designers in terms of timing, crosstalk, electro-migration, power, process variation, etc. Having stressed on the importance of interconnects, analyzing the effects caused by congested interconnects are still the bottleneck in state-of-the-art commercial EDA softwares. The reason is very simple: there are too many to analyze. A typical interconnect connecting two gates in one design module is about a few microns long. To accurately model the interconnect, a parasitic circuit with tens of RC or RLC segments shown in has to be used to model the interconnects’ electrical characteristics. For all the RC and RLC circuits that we are interested, each node has one or more resistive path to others. It is an important assumption. All the reduction methods that will be introduced in this chapter take it as a prerequisite. This chapter reviews some, but not all, of the representative work that is well established in theory and widely used in circuit reduction and simulation. A trend in linear circuit reduction is that reduced circuits are preferably passive or realizable, so that they can be simulated in standard circuit simulators such as SPICE [63]. We start the chapter by introducing time and domain analysis methods used in circuit simulation. Then we review linear circuit reduction techniques, which can be classified into three categories: moment-matching reduction via Padé

16

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

approximation, passive reduction, and realizable reduction, with each more sophisticated than the previous one.

1.

Time Domain Analysis

In this section, we describe RC and RLC network analysis in time domain progressively in three steps. Our first step is to present an approach to analyzing RC circuits. And then the second step is to formulate RLC circuits with certain special structure. Our last step is to introduce the formulation of RLC circuits of general structure. Each of them begins with a simple example and are presented formally in matrix terminologies afterwards.

1.1

RC Interconnect Circuit Formulation

RC interconnect circuits can be formulated using nodal analysis formulation. Nodal analysis is a classical circuit analysis method based on Kirchhoff’s Current Law1 (KCL) and branch constitutive equations2. For a given RC linear circuit with nodes, nodal analysis formulates the problem in the following two steps: step 1. choose a ground or reference node, which usually is taken to be at a potential of zero volt. All other node voltages constitute unknowns 3 ; step 2. establish KCL equations for all the nodes by representing branch currents in terms of node voltages using branch constitutive equations. Example 2.1. Refer to the RC tree in Fig. 2.1. In nodal analysis formulation of the circuit, we first determine the unknowns. Since is equal to which

Figure 2.1. A RC tree demonstrating nodal analysis formulation: current flowing out of a node is equal to currents flowing into the node

is the given input, we use node voltages 1

and

as unknown variables to

Kirchhoff’s Current Law: for lumped circuits, the algebraic sum of the currents entering (leaving) a node is zero. 2 A branch constitutive equations are relationships for circuit elements such as resistors, capacitors, inductors, dependent and controlled sources, etc. For example, the branch constitutive equation for a resistor of value is 3 The node voltages are independent because they linearly represent independent voltage drops on tree trunks on any tree of the circuit.

Basics of Circuit Analysis

17

write the three KCL equations

or if we order the unknown variables on the right-hand side of the equations, we may have

The matrix form of the above three simultaneous equations would be

Note that we have put a minus sign outside the square matrix. Without loss of generality, we assume that the voltage drop and the current from to are two output variables that we are interested,i. e., ans are circuit outputs:

As the reader can imagine, we can use some linear combination of the unknowns to obtain voltages between any two nodes or currents on any branch in the circuit. In (1.7), each row is derived from KCL for each node in Fig. 2.1. For example, the first equation states that the current flowing out of node through , i. e., is equal to the currents flowing into the node through and which are and respectively. In general, RC circuit formulation can be expressed as

where V denotes the unknown nodal voltages in RC circuits. In (1.9), the matrices and represent the conductance and capacitance elements, respectively. Please note that matrix C may be singular, i. e., some rows in C may be zero. It happens when the corresponding node does not connect to any capacitor. It is

18

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

worth noting as well that the G matrix in (1.7) is non-singular if and only if the RC interconnect circuits meet the requirement that each node has one or more resistive path to some other nodes. Being a non-singular matrix is a necessary condition for the most linear reduction techniques.

1.2

RLC Interconnect Circuit Formulation

Formulation of a type of RLC circuits can be easily obtained by augmenting the RC formulation we have introduced. The RLC circuits in this class require that every inductor must be in series with a resistor. In fact when L is considered, the parasitics of an interconnect segment typically is modeled as a RLC branch as shown in Fig. 2.2. The branch constitutive equation of L in Fig. 2.2 is given

Figure 2.2. RLC parasitics of a segment of interconnect on metal layers:(a) illustration of orthogonal interconnect layers (b) RLC parasitic model of an interconnect segment in layer 3.

by where and are the two nodal voltages of the inductor. The formulation method that we described for RC circuits can be used to formulate RLC circuits with minor modifications. We have known that each row in the formulation is constituted by KCL. KCL equations are established in terms of nodal voltages and their derivatives as unknowns. If we want to keep the formulation, has to be represented with nodal voltages. In general, can be calculated by

This integral equation, however, is apparently not a fit to our RC formulations because only nodal voltages and their derivatives can be used as unknowns. Fortunately, provided that the inductor is in series with a resistor in our RLC circuits, is equal to the current flowing through the resistor as well, i.e.,

Basics of Circuit Analysis

19

where and are the two nodal voltages of the resistor. Therefore, insert (1.13) into (1.11), we can rewrite (1.11) into the form of

Essentially we have used the nodal voltages of the resistor to represent the current of the inductor. RLC circuit formulation can be augmented based on RC formulation as follows: step 1. choose a ground or reference node, which usually is taken to be at a potential of zero volt. All other node voltages constitute unknowns; step 2. establish KCL equations for all the inter-branch nodes (those on the joints of branches) by representing branch currents in terms of node voltages using branch constitutive equations. For branch that is an inductor, use (1.13) to represent the current in the inductor. step 3. establish (1.14) for all intra-branch nodes (those inside branches between resistors and inductors). Example 2.2. We change the circuit in Fig. 2.1 to the one in Fig. 2.3 by adding two inductors and in series with and respectively. This circuit structure meets our requirement: is in series with and is in series with

Figure 2.3. RLC circuit meeting the two prerequisites. Shaded ones are the so-called intrabranch nodes

The circuit can be formulated as (1.15). The first three equations are established based on Step 2. While the last two are based on Step 3. In terms of nodes, the first three rows are derived from KCL for three inter-branch nodes. The last two rows are modified branch constitutive equations (1.14) for two

20

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

intra-branch nodes.

Letting the branch current and voltage of

be the outputs, we have

In general, RLC circuit formulation can be expressed as

Similar to the RC formulation, V denotes the unknown nodal voltages in RLC circuits, and matrices and represent the conductance and capacitance elements. In addition, the two matrices contain other elements such as 1 and GL due to the introduction of modified branch constitutive equations (1.14). Same as the RC formulation, matrix C may be singular. We assume that this will not happen in RLC circuits throughout our discussion. The same assumption for RC circuits applies to the RLC circuits to ensure that matrix G is non-singular.

1.3

General RLC Interconnect Circuit Formulation

For more general RLC circuits of which our assumption to the topology of L does not hold, a more general formulation is needed. Modified nodal analysis is yet another classical circuit formulation method which improves nodal analysis method by adding currents in inductors as unknown variables. The introduction of the inductance current variables would help keep modified nodal analysis formulation in the differential form.

Basics of Circuit Analysis

21

For example, the branch constitutive equation of an inductor is

where L is the inductance value. If we had to use nodal analysis, in the KCL equations involving the inductor, has to be represented in terms of i. e., While in the modified version, introducing into the unknowns would keep the KCL equations in the differential form. The cost, however, is an additional equation (1.19). Our general RLC circuit formulation can take one step further from modified nodal analysis, additional inductance current variables can be removed from the formulation by block Gauss elimination. However, this can be done only in domain. step 1. choose a ground or reference node, which usually is taken to be at a potential of zero volt. All other node voltages constitute unknowns; step 2. create a current variable for each inductor with certain direction defined; step 3. establish KCL equations for all the nodes by representing branch currents of RC elements in terms of node voltages and current variables pre-defined in step 2; step 4. establish the branch constitutive equation of inductance in differential form of (1.19) using pre-defined current and nodal voltage variables; step 5 (optional). remove current variables using block Gauss elimination in domain. are the procedure of modified nodal analysis on general RLC circuits. Step 5 is the post-procedure for removal of current variables. Example 2.3. Fig. 2.4 shows an RLC circuit with a mutual inductance M between and Note that in the circuit does not meet our assumption in 1.2, i. e., it does not run in series with any resistor. In order to formulate the circuit using modified nodal analysis, and are two current variables in addition to the four nodal voltages. The modified nodal

22

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 2.4. A RLC tree demonstrating modifi ed nodal analysis formulation.

analysis formulation of the circuit is given by

Let

be the output voltage; then we have

In (1.20), the first four rows are derived from KCL for the five circled nodes. The last two rows are branch constitutive equations of the two inductors and the mutual one, which are added because of the two extra variables, and In general, modified nodal analysis formulation can be expressed as

Basics of Circuit Analysis

23

where

where V and I are the modified nodal analysis variables (yielding a total number of unknowns in (1.22)) corresponding to the node voltages and the branch currents for floating voltage sources and inductors. In (1.22), the matrices and represent the conductance and susceptance matrices (except that the rows corresponding to the current variables are negated). In (1.24), C and L are generally capacitance and inductance matrices of the circuit. However, please note that C may be singular, i. e., some rows in C may be zero. It happens when the corresponding node does not connect to any capacitor. Similarly, L may be singular too, and it happens when the corresponding branch is a floating voltage source. To go one step further to remove the extra variables in domain, (1.21) can be symbolically represented by

or

Using block Gauss elimination, I can be first written as

Replace I in (1.26) with (1.27),

1.4

Remarks

We reviewed three kinds of circuit analysis approaches: 1) RC formulation, 2) RLC formulation, and 3) general RLC formulation. The first one, also known as nodal analysis, is widely used in circuit simulation tools such as SPICE[63] for its robustness and simplicity in implementation. The second formulation method is augmented based on the RC formulation and it is different from the well-known modified nodal analysis, for it does not introduce current variables into the formulation. Therefore, our RLC formulation is more compact, and has the nice property that it guarantees the non-singularity of matrix M in (1.22) under certain assumptions. The last one is to be used on general RLC circuits which may also contain mutual inductance. Further simplification can be done to reduce the matrix size in domain.

24

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

In the next subsection, we will give a closed form for circuit responses to RC and RLC formulations that we have introduced. In some ill cases, matrix M in (1.22) may be singular. When it happens, the closed form solution will not be available. Therefore we reiterate our assumptions to the RC and RLC circuits of our interest: when an inductor is present in circuits, there has to be a series resistor with it; each inter-node has a coupling or ground capacitor. Under these assumptions, M is non-singular.

2. Responses in Time Domain 2.1 Responses in Closed Form Before proceeding to domain analysis, we discuss the time domain solution of linear networks derived from RC and RLC formulations in the previous subsection. Let us pre-multiply matrix on both sides of (1.22); then we have

where can be written as

and

Pre-multiply

on both sides, (2.1)

The solution to the above differential equation is the time-domain response on circuit nodes:

where is the initial condition, i. e., The output response in time domain is derived from (2.3) by pre-multiplying matrix Q:

The first term is the output at time The second term is the convolution of the impulse response and the input waveform. The result can be verified by Laplace and inverse Laplace transformations.

2.2

Taylor Expansion in Time Domain

The matrix exponential

is defined by Taylor expansion:

25

Basics of Circuit Analysis

Therefore, the solution (2.3), with rewritten as:

If we approximate

by first

without losing any generality, can be

terms:

Define

Therefore,

We can get all the by Matrix-Vector multiplications. If the matrix is in Harwell-Boeing Format, the complexity of Matrix-Vector multiplication grows linearly with the number of non-zero elements in Matrix. The evaluation of needs to take the source vector into account. For a vector of constant sources,

For a vector of linear sources,

Sources with classical waveforms, such as exponential or sinusoidal function, have also closed form representation of (2.10). Some sources, on the other hand, are combinations of different ones mentioned above. One of its kind is piecewise linear voltage or current source, which is a combination of a series of timed

26

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

ramp inputs. Because system analyzed here is a linear network, if system has different kinds of source, we can calculate for each independent source alone and sum the response together. Please note that and have no relation to source and time thus and need to be computed only once. For each interested time point calculate the substitute into (2.10), we can get the result value. The choice of will greatly affect the accuracy of this method. For a given error tolerance, we want to find out the smallest that satisfies the accuracy requirement. Since the value of is bounded in real circuit(e. g., less than 5V), We consider is constant Substitute (2.11) into (2.10), local truncation error LTE can be approximated as:

Here is or of matrix. must be smaller than 1, otherwise the local truncation error does not converge. Because is a fixed value for a given circuit, and can be adjusted mutually to satisfy the convergence condition. Specifically, if is equal to T, the time point when circuit response is desired, then has to be large enough such that is greater than T. On the other hand, if is set to a fixed value, e. g., 100, T may have to be time stepped such that individual time step is small enough to make smaller than In summary, the smaller is, the smaller could be. For a given time point T, the absolute truncation error i. e.,

Theoretically because self-multiplication of matrix A is more expensive than matrix-vector multiplication in (2.10), and is much smaller than the square matrix A in terms of dimension, we can select time step as small as possible. Thus for the same absolute truncation error, smaller is allowed. For non-stiff systems, Taylor expansion method can approach the accuracy of SPICE with about one or two order less computing time. For stiff systems, this method requires small time steps compared to the interested time interval. It will generate extremely long simulation time. Practically, is a reasonable number for most of systems.

27

Basics of Circuit Analysis

3.

Domain Analysis

In this section, we discuss how to obtain the transfer function matrix of a linear network from the modified nodal analysis formulation in domain, and how to convert the responses in domain to the time domain.

3.1

Transfer Function

The Laplace transformation of the modified nodal analysis equations (1.22) and (1.23) is given by

Recall that multiply

is the initial condition of the time domain vector on both sides of (3.1) and obtain

Pre-

or where Therefore, we can derive the solution to (3.1) as

Insert (3.6) into (3.2); the output,

can be represented by

So the transfer function matrix defining the relationship between the input and the output is given by

Example 2.4. To interpret the definition of the transfer function matrix let us consider a linear network with two input terminals and three output terminals shown in Fig. 2.5. The I/O terminals are related by the transfer function matrix below:

In the transfer function matrix, is the impulse response at output has an impulse input and the other input terminal is off 4 .

when

4 To turn off the input terminal, if it is connected to a voltage source, it has to be grounded; if connected to a current source, it has to be disconnected.

28

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 2.5. A linear network with two inputs and three outputs.

3.2

Responses from Domain to Time Domain

In general, matrix in (3.8) would be a M × N matrix, where M and N are the numbers of inputs and outputs of the system, respectively. Due to term in (3.8), each entry in is a real rational function of i.e.,

where and are real coefficients of the polynomial expressions of and and are the zeros and poles of the transfer function, respectively. Furthermore, all the entries share the same denominator. In fact, the partial fraction decomposition of is given by

or where

is the eigenvalue of square matrix It is worth noting that which is the relationship between system poles and eigenvalues. Particularly, from the expression in partial fraction decomposition, the time domain impulse response at output terminal to the impulse input at input terminal can be obtained via inverse Laplace transformation:

For an arbitrary input signal at performing convolution on the impulse response and the signal gives us the time domain response at For arbitrary input signals at all input terminals, time domain output responses at can be obtained via principle of superposition.

29

Basics of Circuit Analysis

4.

Preliminaries of Symbolic Analysis

In this section, we briefly review some mathematic notations and theories relevant to the graph-based symbolic analysis techniques to be discussed in details in the later chapters.

4.1

Matrix, Determinant, and Cofactors

Let be a set of integers. Let A denote a set of elements, called symbolic parameters or simply symbols, where and each symbol is labeled by a unique pair where and Often, we write A as an (square) matrix, denoted by A, and use to denote the element of matrix A at row and column c. We sometimes use and to denote, respectively, the row and column indices of element

If the matrix is said to be full. If the matrix is said to be sparse. The determinant of A, denoted by det(A), is defined by

Here is a permutation of and is the number of permutations needed to make the sequence monotonically increasing. The right hand side of (4.1) is a symbolic expression of det(A) in the expanded form, more precisely, the sum-of-product form, where each term is an algebraic product of symbolic parameters. We note that each symbol can be assigned a real or complex value for analog circuit simulation. Let and such that The square matrix obtained from the matrix A by deleting those rows not in and columns not in forms a submatrix of A, and is represented by It has dimension by Let be the element of A at row and column Let be the obtained from the matrix A by deleting row and column and let be the obtained from A by setting Then, the determinant of matrix A can be expanded as below in a way similar to Shannon expansion for Boolean functions: where to and

is referred to as the cofactor of det(A) with respect as the remainder of det(A) with respect to The

30

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

determinant is called the minor of det(A) with respect to We note that the following two special cases of the expansion above are well known as Laplace expansions along row and column respectively:

4.2

Cramer’s Rule

Cramer’s rule gives the explicit solution of a system of linear equations which is foundation for all the symbolic analysis. Give a system of a linear equations

Assuming written as

Where

based on the Cramer’s rule, the unknown

is a

can be

matrix defined as

With the Cramer’s rule, we can solve for any any unknowns explicitly. The solution can be represented by the ratio of two determinants as shown in (4.6). If we determine along the column, the Cramer’s rule for the unknown can be written in the following form:

Where is the minor of det(A) with respect to element As a result, symbolic simulators are targeted at finding various network functions, each being defined as the ratio of an output unknown from to a input from

Basics of Circuit Analysis

31

These are special cases of (4.8) or (4.6). The critical issue left is how to efficiently represent the determinants symbolically given the fact the number of symbolic product terms will grow exponentially with the size of the determinant.

This page intentionally left blank

PART II

LINEAR VLSI CIRCUITS

This page intentionally left blank

Chapter 3 MODEL-ORDER REDUCTION

1.

Domain Analysis

In this section, we discuss how to obtain the transfer function matrix of a linear network from the MNA formulation in domain, and how to convert the responses in domain to the time domain.

2. Moments and Moment-Matching Method 2.1 Concept of Moments In domain, since the Laplace transform of the impulse function, unity 1 , the response at a port is the transfer function itself.

is

Definition 3.1 (Moments of Impulse Response). The moments of an impulse response are the coefficients of powers of in Maclaurin expansion of the transfer function, in domain, i. e.,

1Impulse function is defined as:

Therefore, its Laplace transform is given by

36

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

where

2.2

Delay Estimation Using Moments

moments, delay In this section, we examine the connections of moments and delay estimation of interconnect circuits in two-fold. First, we investigate the reason why moments give good measurement for delay estimation. Secondly, we see how to approximate delays, provided that a set of moments are already given.

2.2.1 Moments: Characteristics of Impulse Response Moments, metric in domain, are tightly related to the impulse response waveform in time domain. Indeed, they characterize the shape of the waveform. Let be the impulse response in the time domain, we rewrite moments defined in (2.2) in terms of by using Maclaurin expansion of in the Laplace transform i. e.,

Comparing (2.3) with the definition that be rewritten as:

moments can

or

is the total area under the response curve which is unity in the case that no resistive load is grounded. We will discuss more on this in Section 2.4. load. Since the requirement is applicable to most of the linear circuits in the thesis, we can assume that The mean of the impulse response,

Model-Order Reduction

37

is widely used as an approximation of step response delays. As the step response in domain is given by basic Laplace transformation properties tell us that the step response in the time domain is as shown in Fig. 3.1. Therefore, the 50% delay of

Figure 3.1. Scenario that the median and mean points mismatch: when the unit impulse response (scaled) is not symmetric, 50% delay of unit step response or the median point of does not overlap with the mean point of

is essentially the median point of the unit impulse response. Furthermore, if is symmetric, the mean of the impulse response is exactly the median point, i. e., 50% delay of is accurately (Fig. 3.2). The first moment of the impulse response also known as Elmore delay, is used as a dominant time constant approximation for RC trees. Indeed, provides an upper bound of delays for RC trees due to the resistance shielding effect[67]. Higher order moments give more sophisticated measurement for the distribution of the impulse response [52]. Therefore, functions that match moments of the impulse response are expected to give a good approximation to the waveform. 2.2.2 Padé Approximation Provided that a set of moments of the impulse response are given, Padé approximation is a method that generates a family of rational functions whose moments agree with those of the impulse response. The rational functions are further decomposed into partial fractions, whose inverse Laplace transforms are used to constitute the approximated response waveforms.

38

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 3.2. Scenario that the median and mean points of 50% delay point of matches the mean point of

overlap: when is symmetric, i. e., the approximation is exact.

Definition 3.2 (Padé Approximation). Given two integers and approximation of the transfer function is a rational function

The Maclaurin expansion of terms, i. e.,

agrees with the that of

Padé

in the first

As there are unknowns in (2.7), we need to establish independent equations to solve for them. Assuming that is a proper transfer function, i. e., we can get coefficients in denominator of (2.7) by solving the following equations:

39

Model-Order Reduction

And the coefficients

of numerator

satisfy the equation:

Equations (2.9) and (2.10) can be verified by honoring the fact that the first moments of match those of i. e.,

where inator

is a polynomial function of we have

Multiplying both sides with denom-

By equating the coefficients of powers of on both sides, we are able to write the two equations in (2.9) and (2.10). Example 3.1. Given a set of moments to obtain a (1,2) Padé approximation, (2.9) can be instantiated as

Inserting (2.13) to the equation above, we have

Therefore, tiated as

and

And to get the numerator, (2.10) is instan-

or So,

and

Thus,

40

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

2.2.3 Partial Fraction Decomposition In order to get the full response waveform, after getting rational function from Padé approximation, one needs to derive the partial fraction decomposition of it. Assuming that the input is the partial fraction decomposition of is given by

The roots of are obtained by solving the polynomial function directly. And for the residues in (2.15), since

we multiply factor

To derive

on both sides and obtain

we substitute for

in the above equation, thus

Example 3.2. Continuing Example 3.1, we evaluate the partial fraction decomposition of in (2.14). The two roots of are and Assuming that the input is then

Thus,

41

Model-Order Reduction

2.3

Deriving Moments from MNA Formulation

Definition 2.2 can be readily extended to the matrix form for multi-port systems (e. g., Fig. 2.5). We do so by examining the MNA formulation method given in Section 1.2. We rewrite the formulation in time domain (1.22) and (1.23) here:

Assuming that X (0) = 0, the Laplace transformation of the above two equations are given by

or

By substituting

for (2.17), we can write

as:

The transfer function in (2.19) is defined by

And refer to Definition 2.2, moments of Maclaurin expansion of are given by:

in (2.20), i. e., the coefficients of

where Computation of moments requires G to be invertible. This requirement is easily satisfied by most interconnect circuits in which each node has a DC path to the ground.

2.4

Deriving Moments for RLC Trees

In the previous section we showed the general approach to computing moments of any linear circuits. In this section, we demonstrate the ease of moment computations for a family of special linear circuits, RLC trees.

42

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

In (2.21), suppose we consider all the entries in the unknown vector outputs, i. e., Q is an identity matrix, we have

We find out from the equations above, that

as

can be solved in a linear equation

And furthermore, higher order moments can be evaluated by utilizing the previous ones, i. e.,

We investigate on how to evaluate moments iteratively. First of all, let us start with To solve for in (2.25, we notice that matrix G is the admittance matrix of a resistive tree derived from the original RLC tree by removing all the capacitors and inductors. The inputs, however, are kept unchanged. Fortunately, for most of the RLC trees or tree-like circuits in the thesis-wise scope, the DC solution is trivial. We will show this in an example later. now is supposedly given, let look at how to derive from Refer to (2.28), matrix G is not changed, i. e., again we need to solve the DC solution of the resistive tree. However, the system’s inputs are now changed to In (1.24) we showed that M is in the form of

where matrix C is the conductive matrix, and L is the inductive matrix. Due to the way that MNA formulation defines the two matrices, entries in C correspond to the currents flowing through capacitors, and entries in L correspond to the voltages across inductors. In other words, C is a part of the KCL formulation, while L is a part of the KVL formulation. Therefore, if we partition according to the composition of M,

Model-Order Reduction

43

then in which is also the right-hand side (RHS) of (2.28), is a vector of current sources, and is a set of voltage sources. An entry in is a product of capacitance and the moment of the voltage across it, and an entry in is a product of inductance and the moment of the current through it. Accordingly, we can generate a new “resistive tree” from the old one by adding current sources and voltage sources at locations of capacitors and inductors of the original RLC tree, respectively, and zeroing out the voltage sources in the old “resistive tree”. The solution to such circuit is also trivial: one can evaluate branch currents and voltage drops in an inverse breadth-firstsearch (BFS) fashion, starting from the leaf nodes; when the root is reached, a BFS or DFS (depth-first-search) can be performed from the root to the leaves to update node voltages.

Example 3.3. The circuit given in Fig. 3.3 is a general RLC tree. The input is an unit impulse function. An important property of the RLC tree is that each node in the tree has a DC path to the ground, and this path has to go through the voltage source. In other words, no resistors or inductors are connected to the ground directly.

Figure 3.3. The original RLC tree in Example 3.3.

The symbolic MNA formulation of the circuit is given by

44

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

The above equation is written in domain. Comparing it with the time domain counterpart in (1.22), we have

Each unknown in (2.30) is a rational function of due to Cramer’s rule (more on this in the next chapter). And the Maclaurin expansion is given by

According to (2.25),

is the solution to the equation

Or if we go by inspection of the “resistive tree” (Fig. 3.4) obtained from Fig. 3.3 by removing all the capacitors and inductors. It is trivially seen that voltage at any node of the circuit is and there is no current from to or from to Therefore,

We can verify that it is the solution to (2.38).

45

Model-Order Reduction

Figure 3.4. The “resistive tree” for computing

in Example 3.3.

To get

we utilize (2.29):

Accordingly, we modify Fig. 3.3 by zeroing out the voltage source and replacing capacitors with current sources and inductors with voltage sources. The modified circuit is depicted in Fig. 3.5. Again if we go by inspection, the solution to the new “resistive tree” is trivial: is equal to and is uniquely determined by have gleaning all the down-stream currents of is simply After we get all the branch currents and voltages, we need another tree-walk from the root to finally get node voltages, e. g., and Thus, these new node voltages and voltage-source currents constitute the first-order moment vector And these values are then used to evaluate new voltage and current source values for the next moment computation.

46

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 3.5. The “resistive tree”modified based on the original RLC circuit by zeroing out inputs and replacing capacitors and inductors with current and voltage sources, respectively.

2.4.1 Remarks The moment-matching method is summarized as follows: given an RLC tree, one first computes a number of moments iteratively, each iteration is to get the DC solution to a “simplified” resistive tree-structured circuit. After the computation of moments, Padé approximation is used to find a rational function which matches the moments just evaluated. Finally, one can use partial fraction decomposition on the rational function and inverse Laplace transformation to get the approximated waveform. This work is the so-called asymptotic waveform evaluation method, or AWE, invented by Pillage and Rohrer [66] in 1990. The complexity of AWE method is i. e., it is linear in terms of both the number of moments desired and the number of nodes in the circuit. An explicit solution to the circuit with capacitors replaced by current sources and inductors by voltage sources —the so-called “companion network” —is also possible for circuit configuration other than strict RLC trees. Any such companion circuit for which a tree can be specified by only voltage sources or a co-tree can be specified by only current sources and no more current sources in the tree2 has a trivial DC solution. For instance, the coupling interconnect circuit shown in Fig. 3.6 can be solved explicitly, because all the current sources in (b) are in the co-tree, and only resistors and voltage sources are in the tree.

3.

Realizable Topological Reduction Methods

In the last section, we showed that moments provide good approximations to interconnect circuit responses. Essentially, the more moments are matched, the more accurate the approximation may become. And this is how AWE[66] is named. Although no rigorous proof could be given, it has already become a

2

For a network for which a tree can be specified by only voltage sources, Then the node voltage can be trivially evaluated by a one-way tree-walk. This is due to KVL. On the other hand, for a network for which a co-tree can be specifi ed by only current sources, then currents in any tree branch can be trivially solved. This is due to KCL. Furthermore, if no more current sources are in the tree, then voltage drops across tree branches, or equivalently node voltages, can be explicitly evaluated as well.

Model-Order Reduction

47

Figure 3.6. Illustration showing a type of non-tree circuit configuration having trivial DC solutions: (a) A RLC network; (b) the companion network of (a) for which all the links can be specified by current sources (or capacitors in the original network).

thumb rule. An obvious drawback of AWE, however, is that Padé approximation it uses may generate unstable poles3. To preserve the stability and passivity of the original circuit, realizable reduction is preferred. Definition 3.3 (Realizable Reduction). A realizable reduction method preserves the stability and passivity of a given linear network by guaranteeing that the reduced models are realizable, i. e., all the RCLK elements in the reduced network are positive. Realizability of impedances or admittances is a very hard problem in network synthesis. Realizability checking calls for a very complicated procedure called

3

An unstable transfer function (system) has some pole(s) located on the right-half of the complex plane. Such poles are so-called unstable poles. For a stable system, if the input is bounded, the output must also be bounded. And this is not true for unstable systems. One can use partial fraction decomposition introduced in Section 2.2.3 to understand why systems with poles on the right-half complex plane are unstable.

48

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

“positive real”. We will postpone the definition to Chapter 7. In this section, we review some realizable reduction techniques. Realizable reduction have been attracting a lot of attention from researchers. Although these techniques are state-of-the-art, they still impose various limitations on configurations of reducible circuits.

3.1

TICER

Sheehan proposed TICER —a realizable reduction method for RC circuits in 1999[74]. In Sheehan’s implementation, a star network is considered. A branch consists of a conductance and capacitance in parallel —denoted by and for the branch incident to node Some elements may be missing, in which case the corresponding or is zero. The configuration covers generally all RC networks. However, no inductive elements are allowed. The response of the central node when a step voltage is applied to the terminal of it, all other terminals being grounded, is given by

where

Since is in the form of time constant for general step responses of RC circuits, it is introduced by Sheehan as the time constant of node in the circuit. Since this time constant is independent of which neighbor or combination of neighbors is agitated, it is the characteristics of the node. nodes can be grouped in terms of their time constants: nodes with greatest and smallest time constants are called slow and quick nodes, respectively, and the others are called normal nodes. The classification can be quantified approximately by using some conversion of a range of time constants to a range of frequencies, e. g., The importance of this classification comes from the fact that both quick and slow nodes can be eliminated from the network without significantly altering its behavior in the frequency range of interest. Beginning from the nodal equations of a RC network in domain:

or

49

Model-Order Reduction

For simplicity, assume that the node we wish to eliminate is the last node Writing (3.4) as a block system

We can solve for from the second block equation and substitute it into the first block equation to obtain

where

In these equations sion, i. e.,

and

Our goal is to realize (3.7), we have

are defined analogously to the previous discus-

with positive RCLK elements. If we extend

We now discuss the two extreme cases. 1. Quick Nodes. node is a quick node, i. e., Therefore, we approximate element by

in

In this case, from elimination

To realize it, the second-order term is simply neglected; hence,

The last equation can be translated into a procedure for physically modifying the circuit. To eliminate a quick node from a network, first remove all resistors and capacitors connecting other nodes to node Then insert new resistors and capacitors between former neighbors of according to the following two rules. If node and had been connected to through conductances and insert a conductance if node had a capacitor to and had a conductance to then insert capacitor of value between and

50

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

2. Slow Nodes. node is a slow node, i. e., Therefore, we approximate element

In this case, in (3.9) by

It is worth noting that, even though (3.12) can be realized by RLC in parallel, the to-be-realized circuit does not preserve the DC solution to the original one. This is because the 0-th order moment is not matched, i. e., To preserve DC characteristics, is used in place of whatever constant terms come from the expansion. In order to prevent causing ringing waveforms due to the co-existence of inductors and capacitors, is not included in the realization either; that is,

From this we get the following slow-node elimination procedure. To eliminate a slow node from a network, first remove all resistors and capacitors connecting any nodes to node Then, as before, if nodes and had been connected to through conductances and insert conductance from to if node had a capacitor to and node had a capacitor to inert capacitor between and 3.1.1 Remarks TICER employs Gauss elimination as the foundation of its node elimination strategies. And Gauss elimination is mathematically equivalent to transformation in graph theory. This topic will be fully discussed from Chapter 4. The moments of can be evaluated easily from (3.9):

Generally, one can not guarantee that Therefore, TICER is not able to achieve the realizability and 1st-order moment matching simultaneously. As a direct result, the coefficient of for both the quick node and slow node elimination in (3.11) and (3.13) does not match in (3.14). TICER’s accuracy control is achieved by setting thresholds as the selection criteria for both quick and slow nodes. Plus, it is a first-order reduction method4, so it is not devised to achieve high reduction ratio (< 90%).

4

The reduced models are 1st-order RC circuits.

51

Model-Order Reduction

3.2

Realizable RLC

Reduction

Given a tree for which each branch is a RLC model, the two fundamental topologies within the tree is series connection (Fig. 3.7) and parallel connection (Fig. 3.8). There is a way to reduce the the original circuits in either topology.

Figure 3.7. Two

models connected in series. (a) The original circuit; (b) the reduced circuit.

Figure 3.8. Two

models connected in parallel. (a) The original circuit; (b) the reduced circuit.

The reduced models are realizable and kept in the structure. Furthermore, the driving-point admittances at the ports of reduced circuits match the originals up to the 3rd order.

52

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

For the series topology, the driving-point admittance i.e.,

at

can be derived;

where

After we get the coefficients, the next step is to assign values to the elements in Fig. (3.7):

Since

by definition the reduced model is realizable. The driving-point admittance at in Fig. (3.7) is given by

Model-Order Reduction

53

One can further verify, using the values given in (3.17)(3.18), that its first three moments match those of the original circuit, i. e., and in (3.15). For the parallel topology, everything is the same as the scenario of the series topology, except that the coefficients (and thus moments) of the rational function in (3.15) are different from (3.16). Equipped with these two kinds of realizable topological reduction, one can reduce a RLC tree of any topology in the bottom-up fashion. Ultimately, the driving-point load is approximated by a single RLC The response at the driving-point thus be evaluated using any gate delay calculators. However, to evaluate responses at any node in the tree, we have to evaluate transfer functions for each branch of the tree when doing the reduction, and propagate higher-level transfer functions all the way down to the nodes where responses are of interest. This can be better explained using Fig. 3.9. Transfer functions from to and can be trivially obtained since and are leaf nodes. Suppose the

Figure 3.9. Transfer function evaluation and propagation. Each branch in the tree is a RLC model.

two transfer functions are available and denoted as and And the transfer function from to can be easily computed after the two downstream branches at are merged using the given procedure, i. e., it is to compute the response at the junction node of two series-connected models. Therefore, the computation of transfer functions of branches are conducted along the bottomup reduction, and when is of interest, the transfer function from the driving node to is the product of all the transfer functions within the path from the driving node to Since the circuit is in tree structure, such a path is unique and guaranteed present.

Lemma 3.1. Given two order stable transfer functions and there is a order stable transfer function which preserves the first moments of

54

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

We will discuss more on this in Chapter. 7. In the following we use a 3rdorder case as an example: suppose

are both stable, can be approximated by (3.20), which is also stable and preserves the first three moments:

where

3.2.1 Remarks The realizable RLC model reduction was first proposed by Yang[102]. The method is able to achieve realizable reduction, and the reduced models are guaranteed stable. However, the method does have some limitations. The first limitation is on the geometry of the reducible circuits: it is only applicable to RLC trees. Secondly, the realizable model has to be one-port only. To obtain responses at internal nodes of a tree, all we can get are reduced models (transfer functions), not realizable reduced circuits, which are more desirable.

3.3

Scattering-Parameter-Based Macro Model Reduction

3.3.1 What are Scattering Parameters? To facilitate understanding of scattering parameters, we borrow an idea from billiards, or pool. One takes a cue ball and fires it up the table at a collection of other balls. After the impact, the energy and momentum in the cue ball is divided between all the balls involved in the impact. The cue ball scatters the stationary target balls and in turn is deflected or scattered by them. In a distributed circuit, the equivalent to the energy and momentum of the cue ball is the amplitude and phase of the incoming wave on a port. This incoming wave is scattered by the circuit and its energy is partitioned between all the possible outgoing waves on all the other ports of the circuit. Definition 3.4 (Scattering Parameters). Scattering parameters, which are commonly referred to as S-parameters, are a parameter set that relates those voltage waves scattered or reflected from the network to those voltage waves incident upon the network. Particularly for the 2-port network depicted in Fig. 3.10,

55

Model-Order Reduction

Figure 3.10. 2-port network showing incident waves in scattering parameter definitions.

and reflected waves

used

is the reflection coefficient of the incident voltage wave is the reflection coefficient of the incident voltage wave is the transmission gain from the incident voltage wave port;

to the left

is the transmission gain from the incident voltage wave port.

to the right

In addition, the total voltage waves at the two ports are

and the currents at the ports are defined as

where

is the characteristic impedances.

The definition can be easily extended for network Suppose a network has ports, then the S-parameters of the network will be a matrix. According to the definition,

we connect all ports by resistors whose resistance are equal to their respective characteristic impedances, which makes for Then set initial incident wave at port be unity, i. e., and measure reflective waves at all port for From above definition, we have In this way, we will measure all the S-parameters of the network.

56

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

So far, we have introduced S-parameters and admittance matrix (Y -parameters) of linear multi-port networks. Note that we have used different sets of independent and dependent variables for the two kinds of parameters5, However, all parameter sets contain the same information about a network, and it is always possible to calculate any set in term of any other set. For example, S-parameters can be written in terms of Y-parameters as

And alternatively, Y-parameters can be represented by S-parameters:

3.3.2 Scattering-Parameter-Based Reduction We would derive the reduction merely based on S-matrix first. And we will explain the result using the original multi-port network on which the S-matrix is defined. Let us start with the most general case in (3.31), where each entry in the S-parameter matrix is a symbol (full matrix). We want to eliminate two independent variable and using Gauss elimination.

From the first equation of (3.31),

Replace using the above equation, the last rewritten as

equations in (3.31) can be

5 We have used incident waves and reflective waves as independent and dependent variables in S-parameters,

and nodal voltages and branch currents as independent and dependent variables in Y -parameters, respectively.

57

Model-Order Reduction

Now we go through another similar iteration to eliminate have

in (3.33); we

where

and

In (3.35), although the matrix size has be reduced by 2, is still related to and As and are used to represent and it is impossible to eliminate and without introducing and into the reduced system, except that and are zero. We can continue the elimination process to further reduce the size of Smatrix. But let us stop here and turn to look at the physical meaning of eliminating two nodes in S-matrix from the circuit point of view. The network reduction problem based on S-parameters can be defined as follows: given a linear distributed-lumped network, find a multiport representation of the network as illustrated by Fig. 3.11, where the multiport is characterized by its S-matrix. All nodes in the network are internal to the multiport except the node connected to the driving source and the loads of interest through These external nodes are specified by the user.

Figure 3.11. A multiport representation

To obtain such a multiport representation with external ports from an arbitrary distributed-lumped network of original nodes, the network is reduced

58

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

by merging the nodes into the multiport one at a time while keeping all user specified nodes external. There are two basic reduction rules: Adjoined Merging Rule:

Figure 3.12. Merge the two networks denoted by nected nodes and

and

at two perfectly intercon-

Let X and Y be two multiport network in Fig. 3.12. If the two networks share the same ground, but are not connected at and the S-matrix for the two networks are given by

in which,

Now if the two networks are perfectly interconnected at and then the voltages at the two nodes are equal; and for the central node in between, KCL holds. Therefore, besides (3.37), we have two additional equations, i. e.,

Model-Order Reduction

59

or because and are actually the same node, so Insert (3.41) into (3.37) by replacing and we have

where Note that in (3.42 only boxed entries are changed. Comparing (3.31) with the above equation, if we eliminate and it is equivalent to eliminate the two rows with –1 in (3.42). Because of some special values (e. g., 0, –1) in the above equation, we could rewrite (3.35) and (3.36),

Note that (3.43) is derived because of the two zeros in the left column in (3.42). Self Merging Rule: Let X be an network with a self loop connected to and in X (see Fig. 3.13). The only difference of the self-merging scenario from adjoined-merging is that the equation (3.38) can not be applied in self-merging rule. However, (3.41) still holds when is replaced by i.e.,

60

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 3.13. Illustration of self merging

Therefore, if we eliminate the first two rows from the above system, then the entries are given by

where Given an arbitrary distributed-lumped network, let be the set of external nodes. The network reduction process begins with merging all internal components by repeatedly utilizing the adjoined merging rule for all the nodes that does not belong to The self merging rule is applied to eliminate all the self loops introduced by the adjoined merging process. Finally, an network characterized by its scattering parameters is derived. Note that the S-parameters are approximated by their lower order moments. 3.3.3 Getting Transfer Functions Once we have obtained the reduced S-matrix, we can use (3.25) and (3.27) to covert and into port voltages and currents. Thus, we can use various combinations of them to get any transfer function of interest. Once the transfer function is obtained, the Padé approximation method introduced before can be used to analyze the system. 3.3.4 Remarks S-parameter based macro model of distributed-lumped networks was first introduced by Liao[51]. The S-parameter based macromodel is flexible that the accuracy of the model can be controlled by adjusting the order of approximation. However, it uses Padé approximation to obtain macromodels. Later

Model-Order Reduction

61

on, Liao proposed a realizable reduction method[50] based on S-parameters. Yet the method is only applicable to RC circuits only, and realizable circuit is first order only. Another limitation of the proposed macromodel method is that scattering parameters are used only as an intermediate result, as the given distributed-lumped networks and desired transfer functions (macromodels) are all in Laplace transform. Therefore, it is apparently more preferable to use Laplace transforms directly. Generalized transformation is just one such method (Chapter 4).

4.

Summary

In this chapter, we first laid the foundation for linear circuit simulation and reduction —basics of circuit analysis in time domain and We then presented two state-of-the-art research directions in linear reduction area: explicit moment-matching method with Padé approximation and realizable topological reduction methods. The two directions have their advantages and limitations. Nowadays, these the methods are all implemented and widely used to solve real industry designs. And their limitations, however, are the motivations of the research in this thesis —generalized transformation.

This page intentionally left blank

Chapter 4 GENERALIZED TRANSFORMATION — FUNDAMENTAL THEORY

In the previous part of this thesis, we have equipped ourselves with all the elements necessary to further investigate the problem, which is the topic of the remaining of the thesis: linear model order reduction using generalized transformation. Particularly, we have been familiar with various state-of-the-art methodologies. In Chapter 3, we have seen analysis methods in both time and domains. Particularly in domain, the moment-matching technique proposed by Pillage [66] has been used widely to approximate waveforms of a linear interconnect network by matching lower order moments with Padé approximation. As each moment can be computed in linear time after an one-time LU factorization, the algorithm runs very efficiently. However, it is well known that Padé approximation may generate undesired positive poles. To overcome the drawback, [74] [102] [51] [50] proposed a series of stable and realizable reduction methods. But they have different levels of limitation on either the reducible circuit topology or the types of reducible elements. In another aspect, topological analysis introduced in Chapter 8 is an approach to calculating driving-point admittances using Cramer’s rule in The determinant of an admittance matrix of a passive network without mutual inductances is equal to the sum of all the tree admittance products of the network. The advantage of topological analysis formula over conventional methods evaluating determinants is that it avoids the usual cancelations inherent in the expansion of determinants in the latter. But enumerating all the trees in a large network is impractical. Recently Ismail[43] proposes a direct transfer-function truncation method to approximate transfer functions in tree-structured RCL networks in The transfer functions are kept in rational expressions in and an approximation is acquired by directly truncating high-order terms. Such an approximation

64

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

also matches low-order time moments implicitly, but truncated characteristic denominator may not be stable any more. The method is able to obtain very high-order transfer functions, when AWE fails because of numerical problems.

1.

Introduction

We have proposed a new model order reduction method based on transformation [69, 68] for general RCLK-VJ linear networks. In this approach, we classify nodes in a network into two categories:

1 external nodes: nodes where responses are of interest; 2 internal nodes: all other nodes in the network. The principal idea is that, given a linear network, we perform transformation on every internal node, until all such nodes are eliminated. Note that the more the external nodes are specified, the sooner the algorithm terminates. After each transformation, any admittance of order higher than user-specified threshold will be truncated. For example, suppose

is an admittance after a would result in a

transformation, the truncation with respect to admittance

which is an approximation to the exact admittance in (1.1). Different from topological analysis and other traditional symbolic analysis, the approach keeps admittances of order All higher-order terms are discarded. The terms kept, however, are precisely the first terms in exact admittances. The main contributions are: 1

admittances are kept in the original rational forms of but their orders are reduced to no more than In admittances, all coefficients of powers of agree with those in exact admittances up to the order

2 First truncated

time moments of exact admittances are matched implicitly by admittances, including the 0th moment

transforma3 Two kinds of common-factor effects are first discovered in tion. The findings lead to essential numerical improvement in traditional transformation, and hence more accurate pole/zero approximation;

Generalized

Transformation — Fundamental Theory

65

4 A Hurwitz polynomial approximation method is employed to treat transfer

functions from truncated functions are guaranteed.

admittances, so that stable reduced transfer

5 The proposed algorithm is more general than DTT method [43], as it handles linear networks in arbitrary topology with current/voltage sources and inductive K elements proposed by Devgan [20].

6 A Geometric-Programming optimized circuit reduction methodology is proposed based on reduction method. This methodology is more general than other realizable approaches in terms of the reducible circuit topology and the types of reducible elements. The remaining of the thesis is organized as follows. In this chapter, we first briefly review the traditional transformation. Then we generalize the idea from different aspects in order to suit linear reduction needs. The overall reduction flow will be the summary in the end. Chapter-wise, advanced topics related to the generalized transformation is presented in Chapter 5. This includes common-factor cancelations, treating round-off errors, etc. In Chapter 6, we present the Hurwitz polynomial approximation method. Chapter 7 shows our yet another application: realizable parasitic reduction.

2. Classical Transformation 2.1 Numerical Example

Figure4.1. A numerical example on the transformation.

transformation: (a) before the transformation;(b) after

For the two circuits (a) and (b) depicted in Fig. 4.1, they are equivalent at three ports: and This can be shown using transformation. In (a), is adjacent to and Kirchhoff’s Current Law (KCL)

66

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

equations for node

and

can be established as follows:

where through are voltages at nodes through (2.1), we can denote in terms of and as:

respectively. From

Inserting (2.5) into (2.2)–(2.4) yields

Considering (2.6)–(2.8) as KCL equations for and in Fig. 4.1(b), respectively, we can find out values for admittances in the circuit:

2.2

Transformation and Gauss Elimination

transformation shown in the example is equivalent to Gauss elimination on the system equations(2.1)–(2.4), in which (2.1) is used to eliminate in (2.2)–(2.4). However, with the formulae we will derive in Section 3, we will see that we do not need to establish system equations in transformation as we did in this example. It is worth noting that we may only need to perform an incomplete symbolic1 LU factorization, because the transformation terminates earlier if more than two external nodes are specified. The symbolic LU factorization is not even full-fledged, in the sense that we always chop off a high-order term in admittances when the power of in this term is larger than a given threshold. All the coefficients of powers of in truncated admittances, however, agree 1The

symbol is

in Laplace transforms.

67

Transformation —Fundamental Theory

Generalized

with those obtained using full-fledged symbolic computation, up to the order Polynomial long division suggests us that first time moments of the admittances are precisely matched with the exact admittance.

2.3

Notations and Terminologies to be Used

We would like to summarize the notations and conventions we are going to use throughout the book before we continue. A current source is said to be floating when it flows from one non-datum node to another non-datum node. Decoupling it is to remove the current source, and insert two concatenated ones of the same amount of current between the two end-nodes. They are concatenated at the ground node. Through this equivalent source transformation, current sources become grounded and associated with nodes but not branches, which makes our algorithm simpler. Similarly, voltage sources can be transformed to current sources and decoupled if necessary. For a given linear network: is denoted as the labeled node, where eliminated in the order labeled;

starts from 0. Nodes are

when the node is eliminated, the network will be updated accordingly. We label the network (graph) before the elimination as and the network (graph) after as is the branch between

and

the admittance of

the current source impinging on and stands for “in graph Here superscript

the neighbor set of

The first neighbor of

with the smallest label;

in

is the node in

When it is not ambiguous, superscripts will be ignored, i.e., represents the branch between node and the admittance of branch and the decoupled current source impinging on node in the graph in the context.

3. Generalized The traditional ing four aspects:

Reduction transformation is generalized in this paper in the follow-

1 RCL, and especially Mutual K elements are integrated in the transformation through a simple conversion, so that circuits with mutual inductances can be handled as well. 2 Current/Voltage sources are handled together with admittances in formation.

trans-

68

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

3 Since many nodes will be eliminated in a general circuit using the transformation, the importance of the order of picking the nodes is studied and treated. The first three points are so important that we dedicate Section 1 and 4 to them. In the next sub-section, we illustrate the conversion of mutual K elements to self K elements. And present the general transformation formulae at the last sub-section. For the sake of simplicity in our presentation, we assume that all storage elements here have no initial conditions. Initial conditions can be simply modeled in as constant current or voltage sources.

3.1

Branch with RCLK Elements

Resistors(R), capacitors(C), and self inductors(L) can be handled easily in transformation. Circuit in Section 2.1 is such an example. This is because RCL elements have well-known admittance forms in Mutual inductors, on the contrary have no simple admittance form. Because the branch voltage of a mutual inductor may be dependent of current variations of multiple branches other than itself

Including mutual inductors is difficult, because we are not able to eliminate a node if one of its incident branch inductively couples with more than one branch. Alternatively, we use K elements. With K elements, inductive coupling is modeled such that branch current can be written in terms of multiple coupling branch voltages. (14) of [44] gives the branch equation for a self K element

where and are voltage and current of the same branch. mutual K element is given by

where

are branch voltages. In

relationship of a

(3.1) can be written as:

A circuit conversion on mutual K elements will allow us to integrate them into our transformation formulae. In Fig. 4.2(a), the KCL equations for the four

Generalized

Transformation — Fundamental Theory

Figure 4.2. Conversion on mutual K in self K elements.

nodes in terms of

and

69

(a)given mutual K element; (b) converted

can be written as

One can check that the KCL equations for the four nodes in Fig. 4.2(b) are exactly the same as (3.3), so that (b) is equivalent to (a). However, (b) has only self-K elements. Although some values in (b) are negative, the circuit is still passive because K-based method guarantees the extracted K matrix to be positive definite

70

3.2

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Branches with Current and Voltage Sources

Branches involved in transformation can not only include resistors, capacitors and self inductors, but also current/voltage sources and mutual inductors. We will give the transformation formula for circuits with current and voltage sources in this sub-section, and K elements in the next sub-section. Following the similar procedure in Section 2.1, we apply transformation to node in Fig. 4.3(a),

Figure 4.3. transformation with current source involved: (a)circuit schematic before the transformation; (b)circuit schematic after the transformation.

And performing

transformation to node

in Fig. 4.4(a) gives

Figure 4.4. transformation with voltage source involved: (a)circuit schematic before the transformation; (b)circuit schematic after the transformation.

Generalized

Transformation —Fundamental Theory

71

One can also derive (3.4) and (3.5) from Norton’s theorem. A generalization of the two transformation formulas will be given in Theorem 4.1.

3.3

RCLK-VJ Generalized Formulae for Transformation

The generalized transformation formulae cover linear resistors, capacitors, self inductors and K elements, and current/voltage sources (RCLK-VL). Theorem 4.1. Suppose in is calculated as

is the node being eliminated. after is eliminated. And the admittance

where

If

For admittances and current sources not mentioned above, they will be inherited by from Th. 4.1 can be proven by the analysis used in the example in Section 2. The theorem states that when we perform transformation on neighbors of in will become pairwise adjacent in In practice, we calculate in (3.6) up to the term of order only. Since computation of higherorder terms is skipped, we get an approximation of

whose numerator

and denominator are equal to the first

numerator and de-

terms in

nominator, respectively. in (3.8) is calculated in the same way. Th. 4.1 does not cover voltage sources, because they can be changed to current sources via source transformation before any elimination begins. It is worth noting from Th. 4.1, that in transformation, coefficients of admittance are derived directly from admittance in original circuits and are kept in its original rational form. Stable reduced-order models can be derived from

72

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

low-order truncated admittances using Hurwitz polynomial approximation in Section 6. Corollary 4.1. If all RLC elements in a linear network are positive, (3.6) is a rational function of

and

in

in (3.9) are non-negative.

Corollary. 4.1 holds immediately due to (3.6) in Th. 4.1.

3.4

Higher-Order Truncation

Generally speaking, input admittance of any two nodes in a non-degenerated network (no loop capacitors or cut-set inductors) with lumped capacitors and/or inductors and any amount of resistors is a rational function of Even though could be huge, we only need to keep coefficients of lower-order terms, i.e., and in (3.9). Th. 4.2 assures us that for any admittance keeping coefficients of powers of in its numerator and denominator throughout the whole reduction process will make the final admittance be a order truncation of the exact admittance. With no loss of generality, let us refer to (3.7). We assume that and Y are admittances from transformation with and without truncation, respectively. When is to be eliminated, a newly admittance can be computed

as

Here

and

is in the form

is the

order approximate of

Theorem 4.2 (Fidelity of Truncated order truncated approximation of

i.e.,

Transformation). If then is the

are the order

Generalized

Transformation —Fundamental Theory

truncated approximation of ator and denominator of

that is, the agree with the first

73

coefficients in the numercoefficients in the

numerator and denominator of

The theorem can be proven using mathematical induction. Note that the result is based on transformation with consideration of common factor cancelation.

4.

Node Ordering

The order of picking nodes to eliminate is important, because eliminating nodes in a network via Transformation is equivalent to LU factorizing the corresponding MNA formulated linear equations. Non-zero fill-ins in LU factorization corresponds to new branches in the reduced network. Therefore different elimination orders will result in a different number of new branches. And the complexity of transformation on a node of degree is We employ an ordering scheme in sparse matrix computation: MMD algorithm. The most widely used general-purpose ordering scheme is the minimumdegree algorithm [35]. Given a simple graph, the node with the minimum degree is eliminated from the graph and degrees of affected nodes are updated, and the node with the new minimum degree in the new graph is taken next. It is used as a practical approximate solution to the NP-complete fill minimization problem [103]. The concept of indistinguishable nodes in MMD was developed to eliminate a subset of nodes all at the same time instead of just one node at a time. In the elimination process, nodes and that satisfy

in a graph are said to become indistinguishable. means the set of neighbors. These nodes can be numbered consecutively in the minimum-degree ordering. Because we keep some nodes as external nodes, these nodes do not appear in a node elimination sequence. So we modify MMD algorithm to adapt our requirements. The algorithm is given below.

74

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Theorem 4.3 (Invariance of Transformation). Let and denote any different node elimination sequences for a given network. Suppose and are two external nodes of the circuit. Let and are the input admittance of port after transformation by following elimination sequence and respectively. The following equation holds:

The theorem can be proven using matrix algebra: permutation of rows in a system matrix does not affect its solution. The theorem tells us that even though different node elimination sequences could have dramatically different impact on the performance of reduction, the admittance is independent of them.

5.

Generalized

Reduction Flow

Alg. 4 gives a overall view of the proposed reduction flow. Before a reduction begins, we use node ordering algorithm introduced in Section 4 to come up with a node elimination sequence. A series of transformation will then be performed on nodes upon the sequence. After transformation ends, we invoke Hurwitz polynomial approximation in the next section to derive stable transfer functions out of truncated admittances.

Generalized

Transformation —Fundamental Theory

75

The algorithm takes where N is the number of nodes in an elimination sequence, D is the maximum degree of nodes in and K is the preset number of orders being preserved for each admittance. Because each rational addition operation takes scalar multiplications and additions, so is in the formula. The estimation is conservative though, because only a few percent of nodes have degrees near the upper bound D (10% to 20% in our experiments).

Different from LU decomposition in SPICE, our algorithm allows dynamical memory de-allocation, as branches of nodes eliminated are no longer needed and can be freed. As a result, the memory requirement grows up in the middle of the reduction process and goes down when it ends. The peak memory consumption is proportional to the maximum number of branches in graphs etc. in a reduction process.

76

6.

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Summary

We propose a new linear network reduction algorithm based on transformation technique in admittances are kept in their original rational forms of and their orders are reduced through high-order truncations. Therefore, transfer functions resulted from truncated admittances match the low-order terms of exact transfer functions. Advanced topics with regard to the newly proposed transformation are outlined and discussed in the next chapter. Without the solutions provided in that chapter, the proposed method can not be effectively utilized to deal with empirical design data.

Chapter 5 GENERALIZED TRANSFORMATION — ADVANCE TOPICS

1.

Common-Factor Effects

Common factors are introduced into the numerator and denominator of new admittance and current source in (3.6) and (3.8), respectively. Common factors are harmful to our reduction algorithm because: (1) they cause exponential growth of the magnitude of coefficients in the numerators and denominators; (2) they create fake zeros/poles that hamper pole/zero approximation. Commonfactor effects exist even though we truncate new admittance and current source all the time. Let us go through an example to show when these common factors are generated and what they are composed of. Then we give theorems for their existence. The impact of common-factor effects on admittances are discussed in the experiments.

1.1

Example on Common-Factor Effects

We first give an example on the composition of a common factor and when it is formed. In Fig. 5.1(a), a third-order circuit is given, with one inductor, two capacitors and three resistors. Suppose we want to compute the input admittance of port n2-n3 via transformation, we will need to eliminate and using transformation. We apply transformation using (3.6) on the first node in in Fig. 5.1(a). Because and are four neighbors, they form a clique in in (b). Thus we have six new admittances:

78

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 5.1. A numerical example showing common factor existence: (a) (b) is to be eliminated; (c) after both and are eliminated.

is to be eliminated;

Let us denote which appears as a factor in all the denominators of the new admittances in (1.1), and we call it “type-I common factor”. Next we apply transformation on the second node in in Fig.5.1(b). Again due to (3.6), in (c) is computed as follows

Generalized

Transformation —Advance Topics

79

Insert (1.1) into (1.2), we have the denominator part

By identifying

as a common factor, we get a simplified result

We have seen that type-I common factor is shared explicitly among denominators of new admittances. Note that we eliminated the first neighbor of in Fig. 5. 1(a) immediately after The existence of type-I common factor is not straightforward in the case that in Fig. 5.1(b) is also adjacent to other nodes besides and and in the case that other nodes are eliminated before and after and admittance merging happens. To show the other kind of form of common factor let us first complete the computation of (1.2). Knowing type-I common factor we have

Note that is present in not only the denominator, but also the numerator of because can be factorized as We compute and in the same way, and it turns out that is present in their numerators and denominators as well. Because the presence of is implicit in the numerators, we call it “type-II common factor”. In summary, Type-I emerges explicitly only in the denominator of every new admittance when is eliminated. Type-II emerges implicitly in both the numerator and denominator of every new admittance only when first neighbor is eliminated. Redundancy due to of type-I common factor can be avoided once it is identified as shown in (1.3), but type-II common factor has to be canceled after its emergence. Refer to Section 2 for the definition of a node’s first neighbor.

1.2

Existence of Common Factors

Type-I and type-II common factors introduced in the last example exist in transformation for general linear networks, no matter admittances are truncated or not. We formally state the two kinds of common-factor effects in admittances in Th. 5.1–Th. 5.4. Th. 5.5 says the existence of two types of common factors in current source transformation. All the proofs can be found in appendices.

80

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Theorem 5.1. suppose is to be eliminated, has neighbors in and the admittances of branches incident to are denoted as Type-I and type-II common factors resulted from are equal to which is defined as:

where

and

is the number of denominators in

that carry factor

Th. 5.1 defines the composition of type-I and type-II common factors in a recursive way, based on (3.6) and (3.8) in Th. 4.1. Basically, the common factor, comes from the denominator of the new admittance in (3.7) before the merging happens, and it is simplified by considering type-I common factors in denominators Each node has its own, unique which is called associated with the node It is worth noting that each emerges at different time in different forms: it appears explicitly in denominators as a type-I common factor; and it appears implicitly in numerators and explicitly in denominators as a type-II common factor. are atomic common factors, defined in (1.5) can be composed of multiple different atomic common factors. We first look at the existence of type-I common factors. A Type-I common factor associated with a node appears immediately after the node is eliminated. Referring to (3.6), we know that in (1.4) defines a factor that the denominator of every new admittance in (3.7) will have after is eliminated. Even when the admittance merging happens, i.e.,

this factor is still carried

by the denominator of the resultant admittance, This is because when two admittances are merged their denominators are multiplied together, so that a factor in any denominator before the merging is still a factor in the new denominator after the merging. We formally state the observation in Th. 5.2. Theorem 5.2 (Existence of Type-I Common Factor). after eliminated, the denominator of new admittance has a factor defined by (1.4) associated with

in in

is

Before we continue to investigate other type of common factors, we first introduce the concept of a node’s first neighbor. Definition 5.1 (A Node’s First Neighbor). Let be the node being eliminated in The first neighbor of is the node in the neighbor set of node with the smallest label.

Generalized

Transformation —Advance Topics

81

Example 5.1. Suppose that a node elimination sequence is followed. Let be the node being eliminated. And let be the neighbors of in the current graph. Then is the first neighbor of Because among the two neighbors of is the first to be eliminated after

A Type-II common factor associated with a node appears in both numerators and denominators of new admittances after the node’s first neighbor is eliminated. Its existence is explicit in denominators, but implicit in numerators. Th. 5.3 states its implicit and explicit presence in numerators and denominators, respectively. And Th. 5.4 states that cancelling it does not affect other type-II ones’ appearance.

Theorem 5.3 (Existence of Type-II Common Factor). suppose the first neighbor of in After and are eliminated, the numerator and denominator of new admittance has a common factor defined by (1.4) associated with

is in

Theorem 5.4 (Recursive Existence of Type-II Common Factor). suppose is the first neighbor of in and defined by (1.4) is associated with Th. 5.3 holds no matter how many nodes are eliminated and how many type-II common factors are cancelled in admittances between and eliminations.

Similar to mathematical induction, Th. 5.3 assures the foundation of our reduction algorithm, and Th. 5.4 makes our reduction process work recursively. The two theorems together support the overall reduction algorithm, which will be presented in Section 4. Alg. V.1 presents the algorithm of eliminating one node using generalized transformation based on Th. 4.1–Th. 5.4.

82

1.3

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Common Factors in Current Source Transformation

Current source transformation is performed along with transformation. Common-factor effects in the latter occur in the former as well. We summarize them in Th. 5.5. Theorem 5.5 (Existence of Type-II Common Factor in Current Source Transformation). assume is the first neighbor of in and defined by (1.4) is associated with

1 If has a current source then after is eliminated, denominator of new current source in has a factor

the

Generalized

83

Transformation —Advance Topics

2 After and are eliminated, and denominator of new current source

in the numerator has a common factor

3 2) holds no matter how many nodes are eliminated and how many type-II common factors are cancelled in admittances and transformed current sources between the elimination of and Alg. V.2 presents an algorithm of current source transformation based on the theorem.

2.

Revised Generalized Reduction Flow —A Redundancy-Free Version

Alg. V.3 gives a overall view of the proposed reduction flow. Before a reduction begins, we use node ordering algorithm introduced in Section 4 to

84

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

come up with a node elimination sequence. A series of transformation will then be performed on nodes upon the sequence. After transformation ends, we invoke Hurwitz polynomial approximation in the next section to derive stable transfer functions out of truncated admittances. The algorithm takes where N is the number of nodes in an elimination sequence, D is the maximum degree of nodes in and K is the preset number of orders being preserved for each admittance. Because each rational addition operation takes scalar multiplications and additions, so is in the formula. The estimation is conservative though, because only a few percent of nodes have degrees near the upper bound D (10% to 20% in our experiments).

Different from LU decomposition in SPICE, our algorithm allows dynamical memory de-allocation, as branches of nodes eliminated are no longer needed and can be freed. As a result, the memory requirement grows up in the middle of the reduction process and goes down when it ends. The peak memory consumption is proportional to the maximum number of branches in graphs etc. in a reduction process.

Generalized

Transformation —Advance Topics

85

Theorem 5.6 (Simplest Form of Transformation). For a given linear time-invariant network, the proposed reduction flow in Alg. V.3 keeps each admittance in a transformed network in its simplest form, i.e., if then the driving-point admittance of the transformed network has exactly the same order as that of the original network.

3. Multiport

Reduction

The generalized transformation we have introduced so far can solve two-port problems. That is, given a two-port system, we can derive the transfer function from single input to single output. In order to derive transfer functions from multiple input ports to multiple output ports, a straightforward way is to reduce the original system to the one with port nodes only, and then reduce the system further multiple times for multiple transfer functions. Apparently, this is not an efficient approach to the problem, especially for systems with hundreds of ports. In this section, we pursue an method that reduces the original system only once, and solve unknown transfer functions from solved ones, by an approach called recovery.

3.1

Backward-Solving in LU Factorization

Traditional transformation is equivalent to Gauss elimination, as we have illustrated this idea using the example in Section 2.2. Essentially the generalized transformation is derived from the classical method, hence it also inherits the strongly connection with Gauss elimination. We start this section by revisiting the example in Section 2.2. And then we will unveil the equivalence of the backward-solving in LU factorization and recovery.

Example 5.2. We redraw the circuits before and after transformations in Fig. 5.2. The nodal equations for the four nodes are given by

Figure 5.2. Example revisit transformations: (a) original circuit; (b) after the transformation on node (c) after the transformation on node

86

By denoting

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

using the other three unknown voltages, i. e.,

we have derived the admittances after the first

Similarly, if we denote (b), i. e.,

transformation:

using the other two unknown voltages,

and

in

For the two-port system (c), the transfer function can be easily obtained if we provide a voltage supply at node and a load admittance at node Once and become known, then and can be solved sequentially, per (3.7) and (3.5). On the other hand, if we apply LU factorization on the simultaneous equations (3.1)-(3.4), we have

With the matrix LU factorized, one solves first; and solves V from UV= Y afterwards. The first is the so-called forward-solving, and the second one is the so-called backward-solving. Comparing the first two rows in (3.8) and (3.5)(3.7), it is apparent that the LU backward-solving is the same process as doing recovery, i. e., solving the voltage of deleted node from its ex-neighbors’ voltages. The last row of (3.8) is zero, showing that the system is singular. It is so because we have written four equations for the original circuit (a) and only three of them are independent. The singularity is resolved if nodes and are

Generalized

Transformation —Advance Topics

87

hooked up with supply and load, when both the last two rows of (3.8) and the right-hand side will be changing. Theorem 5.7. Traditional transformation is equivalent to LU factorizing the admittance matrix and forward-solving of the L matrix, and recovery is equivalent to the backward-solving of the U matrix.

3.2

Recovery

Cramer’s rule states that the solution to each unknown variable of a linear system is a rational function of which shares the same de1 nominator, i. e., the determinant of the matrix . Therefore, we have the following lemma: Lemma 5.1. For any given a family of transfer functions and have the same denominator. With Lemma 5.1 in mind, the following theorem can be proven to be true. And the proof itself constructs a formula of doing recovery after complete transformation. Theorem 5.8 Recovery). For any node if the voltages of all its exneighbors are given by where is the input, then is equal to where Q and P are polynomial expressions in P is the common denominator of the transfer function family and

Proof. Without any loss of generality, we suppose that the voltage variable that we want to recover is Let node ex-neighbors are and the admittances from to the other nodes are The KCL equation for node is

or

1

Please refer to Section 4 for more details of the rule.

88

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Some simple derivation makes us be able to denote transfer functions, i. e.,

in terms of

and given

where

Per Lemma 5.1, all the transfer functions regarding to denominator, P, so

Therefore,

have the same

can be written as

Again due to the lemma, should also have the same denominator as other given with no exception. In other words, it is guaranteed that the numerator has a factor that is,

(3.16) suggests a way of doing the next section.

recovery, which will be summarized in

Generalized

Transformation —Advance Topics

3.3 Multiport

89

Reduction Flow

To evaluate transfer functions for a multi-port system, one has to perform transformation at first. The transformation has to be complete, meaning that only one input port and one output port are kept. All other nodes must be eliminated. Then, we use recovery formula in the last section to evaluate transfer functions from the input to other output ports. When multiple inputs are present, Algorithm V.4 has to be used once for each input to evaluate transfer functions regarding to the input.

The recovery sequence is rather important. It has to be the reversed order of which nodes are eliminated at Step. 2. This is to guarantee that all the transfer functions used in the right-hand side of (3.16) have been evaluated.

4. Treating Roundoff Errors 4.1 Fundamentals of Roundoff Errors When calculations are performed on a computer, each arithmetic operation is generally affected by roundoff error. This error arises because the machine hardware can only represent a subset of the real numbers. Following the conventions set for in [32], we denote this subset by F and refer to its elements as floating point numbers. The floating point number system on a particular computer is characterized by four integers, the machine base the precision the underflow limit L, and the overflow limit U. In particular, F consists of all numbers f of the form

together with zero.

90

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

As an example, if L = –1, and U = 2, then the elements of F are represented by hash marks on the axis of Fig. 5.3. Notice that the floating point numbers are not equally spaced.

Figure 5.3. An example floating point number system

For all real number to be mapped to a finite floating point number system F, an important question to be answered concerns the accuracy of the mapping. Mathematically, given that chopped arithmetic is used, we set to be the nearest to satisfying The f l operator can be shown to satisfy

where

is the unit roundoff defined by

and is the smallest exponent range of F that belongs to. Pictorially, in Fig. 5.3, the roundoff error is the distance from to the first hash mark on its left. Therefore, generally speaking, larger corresponds to larger upper bound of the possible roundoff error. Because F has coarser resolution when numbers get larger. For the example floating point number system in Fig. 5.3, the unit roundoff is given by = 1/8. If the smallest exponent range that falls into is Therefore, the roundoff error is no more than which in this case is 1/4. From the pictorial point of view, 1/4 is exactly the resolution of F at However, if the smallest exponent range it belongs to is So the roundoff error which is one magnitude less than its previous value. Another important issue of finite precision arithmetic is the phenomenon of catastrophic cancelation. Roughly speaking, this term refers to the extreme loss of correct significant digits when small numbers are additively computed from large numbers. A well-known example is the computation of via Maclaurin series. Terms in the series are in the form of For large higher order terms would result in large roundoff error for the reason

Generalized

Transformation —Advance Topics

91

elaborated above. And this error can actually be greater than the exponential itself.

4.2

Roundoff Errors in

Transformations

The cancelation phenomenon, although it is not catastrophic, does exist in our algorithm implementation. The problem stems from common-factor cancelations. Because the cancelations are essential, Therefore the key point in the implementation is to avoid any unnecessary division operations. We present the idea of the avoidance first by a simple example. Suppose we are computing a new admittance, using transformation,

The numerator of

is given by

and can be further simplified in two different ways. The first way, which is most straightforward but may incur more severe roundoff errors, is to compute the denominator’s denominator once, and then divide it by the numerator’ denominator For the example in (4.3),

and

Ideally, But

and

in a floating point number system with L = 15 and U = –15. In such a system,

92

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Comparing (4.8) with (4.5), we find that we have lost the less significant in the coefficient of in (4.8). The missing term results in the entire loss of the first order in i. e.,

which is apparently not equal to any more. Alternatively, we can also compute the numerator of directly without performing Because we have already known that can be divided completely by at all times, we should not include in first and cancel it out later on. We formulate this approach in the next sub-section. The simplest, yet nontrivial case of this approach is on the transformations with three branches only. For example, the numerator of in (4.3) is simply the last term in (4.4), i. e., which is obtained without any computation.

4.3

Solution to Roundoff Problems in

Transformation

For all nodes with neighbors, provided that all the incident admittances are in the form of and the denominators are prime to each other, transformation is given by

In order to avoid unnecessary cancelations of to be computed as

in the numerator,

has

In short, unlike the scenario in (4.10), where we compute the denominator’s denominator, only once and divide it by in (4.11) we have to compute for all new admittances Fig. 5.4 row by row enumerates the numerators of all admittances At the first look at algorithm (a), the complexity is while (b) is only But after some careful investigation on (a), we have found out that there are some repeated patterns within and among the groups. Taking this fact into consideration, Fig. 5.5 shows a way to partition the groups in (a). Generally, in each group are partitioned into three sections, upper-triangle

Generalized

Transformation —Advance Topics

93

Figure 5.4. enumeration of the numerator of (a) algorithm requiring addition and multiplication operations only; (b) algorithm requiring extra division operation.

94

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 5.5. Finding common partial terms in the numerator of

by partition.

Generalized

Transformation —Advance Topics

95

section, lower-triangle section, and left-column section. Upper-triangle section belonging to in Fig. 5.5 is the largest, which can be obtained by computing row by row starting from the bottom, i. e., Other UBs are subsets of Lower-triangle section in can be obtained by multiplying on each entry(row) of in Therefore, essentially LBs can be grown from the lower-right corner starting with The complexity of the growing operations is Entries within each CB are exactly the same, and So we can grow CBs from left to right, i. e., In summary, we give a procedure for computing the differing numerator of with consideration of common-factors in That is, we withdraw our previous assumption that are prime to each other. step 1. step 2. is to get the expression with the maximum number of terms in step 3. step 4. step 5. step 6. step 7.

5.

Experimental Results

A linear network simulation package was developed based on the proposed transformation reduction algorithms. Hurwitz approximation method was also implemented for waveform evaluation and pole analysis. Several industrial interconnect and power/ground circuits were used in our experiments. The CPU runtime was tested on a HP C3000 workstation. Two tree-like circuits were tested. One was a set of uniform bus lines with resistance, inductance, fringe coupling capacitance and grounded capacitance. Inductance is in the magnitude of and capacitance is Rise time of input signal was 50ps, and simulation time range was from 0 to 150ps. The other was a clock distribution with similar RLC and simulation configurations. reduction was tested with 15 preserved order . Note that none of the two circuits was strictly tree structured. Fig. 5.6 shows transient response evaluated using 7-th Hurwitz approximants of admittance from transformation, as compared to AWE method and SPICE simulations for the

96

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

two circuits. We only used 3rd order transfer functions from AWE method as higher order ones were not stable. Based on the circuits that we have, an average 10-fold improvement over SPICE in CPU runtime has been achieved with negligible errors from SPICE.

Figure 5.6. Transient response evaluated using transformation with Hurwitz approximation as compared to AWE method and SPICE simulations for coupled RLC bus lines.

Fig. 5.7 shows the number of orders of admittance from our implementation of with consideration of common factor effects, compared to a naïve implementation without the consideration. The figure shows that the latter one grew exponentially, for both tree-like circuits and mesh-like circuits. As we expected, orders of admittance in mesh-like circuits grew even faster than in tree-like circuits, as average degree of nodes in the former cases was larger than that of nodes in the latter cases. Our implementation shows that when

Generalized

Transformation —Advance Topics

97

Figure 5.7. Order of admittance after transformation with recognizing common factors as compared to a naive implementation without recognizing common factors.

reduction completes with two nodes left, the order of the resultant admittance was the same as the order of original circuits, fitting the line.

6.

Summary

We have proposed a generalized transformation for linear network model reduction. The proposed algorithms can handle linear resistors, capacitors, self and mutual K elements and independent sources. The algorithm integrated common-factor-cancelation operations that were not seen in the literature. Admittance in reduced circuits has the guaranteed simplest form, without redundant common factors.

7. Appendices 7.1 Existence of Type-II Common Factor Theorem 5.4 (Existence of Type-II Common Factor). Given a node whose degree is larger than 2, we suppose is the first neighbor of in After both and are eliminated, for all pairs of the remaining neighbors of i.e., the new admittance between and has a common factor in both its numerator and denominator, where is defined by (1.4) associated with Proof. We first clarify the notations used in the proof. Firstly, to simplify our explanation, we assume that and Therefore,

98

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

and and

We further assume that has neighbors, i.e., Finally, we denote admittance between any node as and any two different nodes

i.e.,

The proof consists of three steps as shown in Fig. 5.8. First of all, we eliminate and define the type-II common factor associated with it; secondly, we consider the general case when another node is eliminated after and before then in the third step, we eliminate and prove that the existence of in the new admittance is independent of Finally in the remarks, we discuss the impact of type-I common factors on type-II. Step 1: transformation on This transformation will eliminate and generate a new admittance between any pair of neighbors, so the total number of new admittances would be For any pair of its neighbors, and is denoted as the new admittance, as shown in Fig. 5.8(b). According to (3.7),

or

where

Step 2: transformation on Generally, nodes other than and may be eliminated after and before in Fig. 5.8(b) is such a node. The transformation on will eliminate and generate a new admittance between and Note that and are two arbitrary neighbors of both and

Generalized

Figure 5.8. Three (c) eliminating

Transformation —Advance Topics

Transformations in Proof of Th. 5.3: (a) eliminating

99

(b) eliminating

100

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

After this step, the admittance when is to be eliminated, is the combination of three admittances, as shown in Fig. 5.8(c).

or

where follows:

Combining (7.4) and (7.8), we can rewrite (7.8) as

Step 3: transformation on As some of incident branches of may not belong to the clique formed by we use to denote the sum of admittances of such branches. Admittance between any pair of the remaining neighbors of is denoted as where According to (3.6),

We now prove that both (7.11) yields

and

and

have a factor

Inserting (7.9) into

Generalized

Transformation —Advance Topics

101

is a factor in Let us investigate Expand the rightApparently, we have hand side of (7.12) and separate terms with and without

where

102

Plugging

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

in (7.6) into (7.13) yields

Thus Both and in (7.11) have a factor And the existence is independent of the effective admittances introduced in Step 2.

Generalized

Transformation —Advance Topics

103

Remarks: note that we have assumed that all the denominators of in (7.1) are prime to each other. Due to the existence of type-I common factors, the assumption is not true. However, our proof is valid still if we modify the definition of in (7.5) by dividing it by duplicated type-I common factors. As modified is a factor of the original whose existence has been proved, the existence of modified is straightforward. The formal definition of type-II common factors can be found in (5.1).

7.2 Recursive Existence of Type-II Common Factor Theorem 5.5 (Recursive Existence of Type-II Common Factor). Th. 5.3 holds no matter how many other type-II common factors are found and canceled before is eliminated. Proof. We have understood that in the process of transformation, nodes and their incident branches are eliminated, and at the same time, new admittances are merged with existing ones. The correctness of the theorem is easy to understand if we do not merge admittances. i.e., we allow more than one admittance(branch) between any two nodes. For all pairs of neighbors, i.e., the new admittance due to the elimination of will not be touched until is to be eliminated. Therefore associated with will still emerge as a type-II common factor when is eliminated, no matter how many other type-II common factors are canceled before the elimination of We illustrate the idea in Fig. 5.9. In the figure, three bold admittances due to the elimination of in (a) are not touched until is to be eliminated in (d). For example, In (c), a new admittances between and is due to the elimination of And in (d), another new admittance between them is due to the elimination of Because is the first neighbor of in (b), the two new admittances, if merged in (d), would have a common factor associated with One key point is that the cancelation of this common factor does not affect the bold admittance, which acts as an effective admittance when is eliminated. Another key point is that we are free to cancel out this common factor without affecting the emergence of the type-II common factor Because these admittances in turn will be considered as an effective admittance2 when is eliminated.

7.3

Existence of Type-I and Type-II Common Factors in Current Source Transformation

Theorem 5.6 (Existence of Type-I and Type-II Common Factors in Current Source Transformation). 2

We do not care about the actual contents of effective admittances.

104

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 5.9. A Series of Transformations in Proof of Th. 5.4: (a) eliminating eliminating (c) eliminating (d) eliminating

Given a node we suppose that is the first neighbor of associated with is defined by (1.4).

in

(b)

and

1 If has a current source then after is eliminated, for all the neighbors of i.e., the denominator of new current source in has a type-I common factor

Generalized

2 After both i.e., source

Transformation —Advance Topics

105

and

are eliminated, for all the remaining neighbors of the numerator and denominator of new current has a type-II common factor

3 Statement 2) holds no matter how many other type-II common factors are canceled in admittances and transformed current sources before is eliminated.

Proof. Statement 1) Similar to Th. 5.2, the first part of the theorem is easy to prove according to (3.8). Statement 2) We first clarify some notations to simplify the explanation. We assume that and Therefore, and We further assume that has neighbors, i.e., For arbitrary and in represents the admittance between and the admittance between and and the current source of Each admittance is a rational function, i.e.,

The proof consists of three steps as shown in Fig. 5.10. First of all, we eliminate and define the type-II common factor associated with it; secondly, we consider the general case when another node is eliminated after and before then in the third step, we eliminate and prove that the existence of in the new current source is independent of Finally in the remarks, we discuss the impact of type-I common factors on type-II. Step 1: transformation on The transformation will generate a new admittance between any pair of neighbors. Additionally, each neighbor will have a new current source. i.e., for and in the new admittance and current source are given by

106

Figure 5.10. Three (c) eliminating

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Transformations in Proof of Th.5.3: (a) eliminating

(b) eliminating

Generalized

Transformation —Advance Topics

107

or

where

Step 2: transformation on Generally, nodes other than and may be eliminated after and before in Fig. 5.10(b) is such a node. The transformation on will generate a new admittance between and and new current sources and for and respectively. Note that and are any two neighbors of both and After this step, the admittance when is to be eliminated, is the combination of three admittances, as shown in Fig. 5.10(c). Likewise, the current source when is to be eliminated, is the combination of three current sources. i.e.,

or

108

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

and Referring to (7.19) and (7.20), where we can rewrite the above (7.26)(7.27) as follows:

Step3:

transformation on

in Fig. 5.10 has the similar definition3.

Current source for any remaining neighbor of

is denoted as

where

After the transformation, we now prove that both the numerator and denominator of have a factor Inserting (7.28)(7.29) into (7.30) yields

The denominator explicitly has a factor

3

As some of incident branches of may not belong to the clique formed by sum of admittances of such branches. This definition is also given in Fig. 5.8

we use

to denote the

Generalized

Transformation —Advance Topics

109

Let us investigate the numerator. From (7.31), the numerator is given by

Expand right-hand side of (7.33) and separate terms with and without have

we

110

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

By inserting (7.22)(7.23) into (7.34), we have

Therefore is also a factor of the numerator. And the existence of this type-II common factor is independent of the effective admittances introduced in Step 2. Statement 3) The idea used to prove Th. 5.4 can be applies here. Let us switch back to the notation used in the theorem. For all the neighbors of except i.e., if no common-factor cancelation is allowed, the current source of since is eliminated are equal to

where are current sources merged to when transformations are performed between and eliminations. On the other hand, we note that if a certain type-II common factor emerges and is cancelled on right-hand side of (7.35)–(7.38), will act as an effective current source and will not be altered. Therefore when is to be eliminated, is still in and will emerge as a type-II common factor.

Generalized

7.4

Transformation —Advance Topics

Simplest Form of

111

Transformation

If we apply Alg. V.3 on complete graphs, the final solution is optimal, meaning it does not has any common factors and it is of the same order as the original network. Let us first look at a 6-node complete graph. Its transformation process is shown in Fig. 5.11. Solid nodes in the figure are to be eliminated at the snapshot. denotes the form of admittance in the step, where denominators are given and numerators are simply ignored as star (*). Please keep in mind that these numerators have the same order as their correspondent denominators. In Fig. 5.11(1), five bold branches are going to be eliminated

Figure 5.11. Illustrating orders of admittances in (a) (b)

transformation on 6-node complete graph: (d)

along with the central node. New branches are in the form of

112

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Order of is equal to 5. When these new branches are to be combined with those existing in parallel

which constitute in Fig. 5.11(2). Let us go one step further. When we eliminate the second node(Fig. 5.11(2)), new branches are in the form of

After the similar step as (7.39), the final admittance evaluated as

Due to Th. 5.3,

in Fig. 5.11(3) can be

in (7.41) can be canceled. So in Fig. 5.11(3),

So on and so forth, when the network is reduced into one port(Fig. 5.11(e)), the order of the admittance is which is equal to the number of branches in Fig. 5.11(1). Theorem 5.9 (Simplest Form of Transformation). For a given linear time-invariant network, the proposed reduction flow in Alg. V.3 keeps each admittance in a transformed network in its simplest form, i.e., if then the driving-point admittance of the transformed network has exactly the same order as that of the original network. Proof. We use an example shown in Fig. 5.12 to help us explain the idea of the proof. Fig. 5.12 illustrate a series of transformation. Solid nodes shown in each graph are the ones to be eliminated at that step. We assume each branch in has different admittance and we assign a distinct integer to each of them (Fig. 5.12(a)). Graphs in a series of transformation are generally denoted as respectively, where Along with each branch in each graph is a set S, where each member W is a set of branches. Here Definition 5.2. We define that a branch is associated with a branch exists a of such that where and

if there

Generalized

Transformation —Advance Topics

113

114

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 5.12. Illustration for proof of Theorem 5.6: (a) are to be eliminated; (b) are to be eliminated; (c) is to be eliminated; (d)transformation finished.

For instance, branch 1 between and in Fig. 5.12(a) is associated with the branch between and in (b), because in {{1,2}}. 1 is also associated with the branch between and in (c), because

Conceptually, transformation defined in Alg. V.3 can be interpreted in graph theory: a transformation on a node generates a clique among the node’s neighbors. After the transformation, each branch in the clique carries all the branches impinging on the node before it is eliminated. So that S of each branch in the clique will have a new member: a set which collects all of the node’s branches. E.g., in Fig. 5.12(b), which is newly created because branch does not exist in (a), has a new element {1,8}, which is a merging of the elements in and in (a). When is eliminated, a new element {1,2,3,8,9} is being inserted to and in (c); when is eliminated, a new element {4,5,6,7,10} is being inserted to and in (d). Finally when is eliminated, and in (d) are used to construct a new set {1,2,3,4,5,6,7,8,9,10,11,12}, and because the two sets in are subsets of the new one, they are simply removed when merging with the new branch in (e). From the example, we conjecture that in any step of a series of transformations, any sets in the same S are disjunct, and sets in different S are either equal, or disjunct. Claims given below formalize our conjectures. 1 When a node is to be eliminated,

(a)

incident to the node

(b) W needs to be inserted into S of branches between any two of the node’s neighbors. (c) before the insertion, or if then has to be removed from S after the insertion of W. 2 For S of any branch, 3 For S of any two different branches, or

and

and

Generalized

Transformation —Advance Topics

115

4 For S of any branch, is equal to the number of branches in that have associated with the branch.

If 1), 2), 3) and 4) are true, Th. 5.6 is true automatically because finally all branches in will be associated with the last branch and the order of its admittance is the same as that of the original network In Claim 1), a) and b) are directly from transformation formula (3.6). And c) corresponds to type-II common-factor cancelation, as a type-II common factor emerges when admittance(branch) merging happens. Claim 2) and 3) are true due to 1). Duplications, if any, will be removed at a) and c). a) removes duplication by flattening members of involved branch sets, and this corresponds to type-I common factor identification. c) removes duplication by deleting redundant existing members in new sets, which corresponds to type-II common factor cancelation. These two claims also show that associated with nodes are unique and prime to each other. Claim 4) is a direct result of 2) and 3).

This page intentionally left blank

Chapter 6 TRANSFORMATION: APPLICATION I — MODEL STABILIZATION

1.

Hurwitz Polynomial Let denote the open left half complex plane Let denote all the polynomials in whose coefficients are real numbers.

Definition 6.1. A polynomial in

is said to be Hurwitz if all its roots lie

Clearly, if

is of degree 1 with positive leading coefficient, that is, if with then P is stable if, and only if, Our goal is an counterpart of this simple observation: we seek algebraic conditions on the coefficients of a general polynomial which are both necessary and sufficient to ensure that P is Hurwitz. The key reason that we care about Hurwitz polynomial is because when a transfer function has a Hurwitz denominator (the system’s characteristic polynomial), then the system’s response to any bounded input would be exponentially decaying to a limited amplitude range within a finite period of time. For more details about how to get system responses from a given transfer function in rational form, please refer to Chapter 3. Example 6.1. Suppose a transfer function is

The poles of

are given by

Since all the poles lie in is stable. No matter what the coefficients are, the system is always analytical (continuous) on the closed right half complex plane for any bounded input.

118

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

2. The Routh-Hurwitz Criterion 2.1 Necessary Conditions Before we dig into the very powerful “Routh-Hurwitz stability criterion”, there are some rules that a Hurwitz polynomial has to obey, that is, some of the necessary conditions of Hurwitz polynomials. These rules are much simpler to check than the criterion, yet they can filter out many impossible Hurwitz candidates. Let us first review some fundamental algebraic theorems without proof. Lemma 6.1 (Fundamental Theorem of Algebra). an algebraic expression of the polynomial form:

where has exactly course, possible).

complex or real roots

(repetition is, of

Lemma 6.2. If the coefficients of a polynomial etc.) are real, then any complex roots will come in conjugate pairs, i. e. where is the imaginary operator and and are real numbers, so that is the “real part”of (i.e., and the “imaginary part” of (i.e. The two necessary conditions of Hurwitz polynomials is given in the following theorem. Theorem 6.1 (Necessary Conditions of Hurwitz Polynomials). If is a Hurwitz polynomial, then

1 no coefficient is missing, 2 all the coefficients are of the same sign, either + or –. Proof. For all polynomial that is,

it can be factored using all the roots of

where and pairs are the real and complex roots of respectively. This is a direct result from Theorem 6.1 and 6.2. Per definition 6.1, and have to be negative real numbers, which means that the coefficients of and in factors and

Transformation: Application I — Model Stabilization

119

are all positive real numbers. Hence, the coefficients of all the powers of in the polynomial expanded from these factors are all positive real numbers as well. That concludes the proof.

2.2

The Routh-Hurwitz Criterion —A Necessary and Sufficient Condition

The Routh-Hurwitz stability criterion is a method for determining whether or not a system is stable based upon the coefficients in the system’s characteristic equation. It is particularly useful for higher-order (> 5) systems because it does not require the polynomial expressions in the transfer function to be factored. On the other hand, calculating analytically the roots of a polynomial of order higher than two is very cumbersome and in general impossible if the order is larger than five. Therefore, the Routh-Hurwitz criterion is exactly the mathematical tool we want for the topic in this chapter. Because we want to do stability analysis on a characteristic polynomial given from previous computation. To answer the question on stability you don’t need the roots of the polynomial. We only want to know whether all roots have negative real parts or not. And here comes the neat theorem of Routh and Hurwitz. Let us consider the following polynomial of degree

and decompose it into its even and odd parts as

where

and

with

Theorem 6.2 (Routh-Hurwitz Criterion). For all polynomial the form

of

120

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

let us denote

Arrange the coefficients in rows and columns in the following pattern:

for

is odd

is even); and

for is even is odd). and are the coefficients of and in decreasing order of The row of the table is the coefficients of the residue, in decreasing order of of dividing the polynomial into the polynomial by the common process of long division, however, ceasing after only a single term in the quotient is determined. The number of roots with positive real parts is equal to the number of changes in sign of the coefficients in the first column of the table etc.). Example 6.2. Let us look at an example on how to build a Routh table. Consider the system with characteristic equation

Since

22, the coefficient of the residue, would be the third row of the Routh table. And similarly, because

Transformation: Application I — Model Stabilization

121

24 would be the last row of the table. That is,

Since at least one of the coefficients (–22) is less than zero, this system is unstable. In fact, it has two roots in the right half-plane. Example 6.3. As another example, consider the system with characteristic equation We construct the Routh table as in the other examples,

At this point, we cannot continue since we have a 0 in the first column. We are interested only in the sign of the coefficients, so the workaround is to replace the 0 with a small, positive number, call it Then we have

with and us that there are two sign changes, thus the system is unstable.

This shows

Clearly, the entries of every row of the Routh table coincide with the coefficients of the decreasing powers of in the (even or odd) polynomials

formed from (2.6) and (2.7) according to the Euclidean recursion

where

is the quotient between the coefficients of and in and respectively (leading coefficients). Clearly, this recursion also defines a sequence,

122

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Indeed, one can construct

out of the sequence, i. e.,

or

Corollary 6.1. A necessary and sufficient condition that polynomial is that all the quotients be positive.

be a Hurwitz

The necessary and sufficient condition stated in Corollary 6.1 focuses the quotients, while Theorem 6.2 is looking at the the leading coefficients of residues, which is produced by the quotients. Therefore, the two conditions are mathematically equivalent to each other. Example 6.4. To interpret Corollary 6.1, let us look at an example in stead of going through tedious proofs. Let us refer to the polynomial in Example 6.2. The quotients are and Because all the quotients are not positive, is, again, not stable. We see that it is the negativeness of the leading coefficient of the residue in (2.11) that results in the negativeness of So we stated that the two necessary and sufficient conditions are equivalent. Optionally, another quotient sequence can be obtained from

Transformation: Application I — Model Stabilization

123

or

The necessary and sufficient condition that be a Hurwitz polynomial is that all the quotients in (2.18) or (2.19) be positive. These conditions are once again entirely equivalent to the ones in the other sequence given by (2.16). although they are different in their detailed appearance. It should be clear, however, that the quantities as functions of the coefficients in terms of these coefficients except that the consecutive order of the subscripts 0,1,2, on the is inverted. In other words, if in the expressions for one makes the substitutions indicated by

the corresponding ones for are obtained. is the quotient sequence we will use later in this chapter, and we will refer it simply as without any confusion.

2.3

Proof of the Routh-Hurwitz Criterion

We have seen that if for any polynomial expression the stability of the physical system with as its characteristic polynomial (i. e., the denominator of any transfer function) is assured if it can be shown that all the zeros of lie in the left half of the s-plane. And a polynomial having this property is called a Hurwitz polynomial. In the last few paragraphs, we have presented the well-known Routh-Hurwitz stability criterion. Most undergraduate control courses, and the related textbooks, include the criterion. A recent survey[26], conducted by the Working Group on Curriculum Development of the IEEE Control Systems Society, shows that this topic is covered in 90% of Electrical Engineering departments and 89% of Mechanical Engineering departments. The proof of the criterion, however, is very often omitted. The classical proofs available in the literature are diverse; the main approaches are based on Cauchy’s indices and Sturm sequences, on continued

124

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

fraction expansions, on the Hermite-Biehler theorem, and on the second method of Lyapunov[33, 9, 15]. The importance of this topic and the complexity of the mathematical tools required in most of the above proofs motivate the continual interest in the subject. Another reason why the proofs are often omitted in standard textbooks is that they give little insight into the nature of the algorithm. In this sub-section, we presents an alternative proof [39] of the Routh rules for determining the zero distribution (with respect to the imaginary axis) of a polynomial with real coefficients. The advantage of the suggested approach consists of the simplicity of the mathematical tools required: it only uses elementary and well-known notions about polynomials. 2.3.1 Correlations of Vectors in Suppose that are the zeros of the correlations among and using all the zeros is then given by

in

We first investigate factored

With being a variable, or a free point, in and individually represent different vectors in the plane. This is shown in Fig. 6.1.

Figure 6.1. A

plot showing vectors

It may be seen that if is replaced by its conjugate value the factors collectively represent the same set of magnitude. In other words, vectors from zeros to the points which are images with respect to the real axis have the same magnitude. The reason why it is so is because all the zeros are either on or symmetric with respect to the real axis.

Transformation: Application I — Model Stabilization

125

It should be clear from the representation of the above figure, that if all the zeros are on the left-half plane, then for any point in the right-half plane, the magnitude of the polynomial is larger than it is for the corresponding point1 in the left-half plane. Together with the last paragraph,

2.3.2 Functions Letting

and

Developed From

one may alternatively express the results of (2.22) by

It should be clearly recognized that these statements hold only if is a Hurwitz polynomial for if has any zeros in the right-half plane, points can certainly be found for which these statements collectively are no longer true 2 . Therefore, these statements are necessary and sufficient conditions that a given polynomial have zeros in the left-half plane only, i. e., is a Hurwitz polynomial. Introduce function

This transformation maps the interior of the unit circle in the the left-half of the Note that Because if to 1, then which conflicts with the condition that

upon were equal when

1 Points which are images with respect to the imaginary axis are regarded as corresponding points in the left and right half planes. 2 It gets a little confused in the case that zeros and are images with respect to the imaginary axis and is the only zero in the right-half plane. Because is always equal to so it seems that these factors can be canceled on both sides of any of (2.22). If they are canceled, the effect of being in the right-half plane is invisible, and neither of the three properties in (2.22) is violated. However, we can cancel the factors only if they are not zero. On the other hand, one can easily fi nd out that some of the factors are zero if is equal to or When either the first or the last property is violated.

126

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Hence one has3

and, with the use of (2.24), one obtains

2.3.3 Emergence of Routh-Hurwitz Criterion If the polynomial is written in the form

in which represents the terms involving even powers of and sents the terms involving odd powers of one has

repre-

It is thus established that if and are the even and odd parts respectively of a Hurwitz polynomial, the rational function (2.28) has the properties expressed by the conditions (2.27), and conversely, if the ratio of the even and 3

Suppose that

So, the real part of

Since

honoring that

one has

is given by

for any

Transformation: Application I — Model Stabilization

127

odd parts of a given polynomial yields a rational function having the properties (2.27), that polynomial must be a Hurwitz polynomial. Now let us examine how the properties expressed by the conditions (2.27) can be translated to restrictions on the poles and residues on the rational function Suppose has a pole of the order at some point The Laurent series for in this vicinity then reads:

For points very close to

one may write

Letting

and one has

hence It is thus seen that, in the immediate vicinity of the pole, the real part of assumes large negative as well as large positive values. More specifically, as is allowed to vary from 0 to (the vicinity of the pole is explored through passing around it on a concentric circle of small radius), the real part of is observed to change sign times. With reference to the conditions (2.27) together with (2.34), one is forced to conclude immediately that the function can not have poles in either the right or the left half plane, and can only change sign twice around the vicinity of In other words, the only conditions under which (2.34) does not conflict with the restrictions (2.27) are that the pole is on the imaginary axis with and for then (2.34) reads

Fig. 6.2 plots the different scenario when has poles not on the imaginary axis while the other two conditions are satisfied, i. e., and It is seen that in those cases, and are not guaranteed to agree on sign. Hence, one can neither guarantee that and agree on sign, because

128

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

129

Transformation: Application I — Model Stabilization

Figure 6.2. Examples showing the sign difference of and —

for different

locations.

130

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

and are in the same direction on (they only differ with a positive constant factor). On the other hand, Fig. 6.3 shows the only situation of the pole under

Figure 6.3.

must lie on the imaginary axis to make and

agree on sign.

which (2.34) does not conflict with the restrictions (2.27), that is, when is on the imaginary axis, always has the same sign with and so does

Transformation: Application I — Model Stabilization

131

According to (2.32), corresponds to – and corresponds to whereas for (2.35) is thus seen to yield a real part of which behaves in agreement with the conditions (2.27). The restriction that means that the pole must be simple, and requires that the residue of in this pole be real and positive. The conditions (2.27), therefore, require that the rational function have poles on the imaginary axis only and that these poles be simple and have positive real residues. In order to see that these requirements on the function are also sufficient to assure the fulfillment of the conditions (2.27), one need only regard a typical term in the partial fraction expansion of Such a term reads

Since the residue is real and positive, and is a pure imaginary quantity, it is evident that the term (2.37) has the properties demanded by the conditions (2.27), and hence the finite sum of such terms which represents has these properties. One has thus gained a new formulation for the necessary and sufficient conditions that be a Hurwitz polynomial. Namely, the quotient of its even and odd parts must be a function having simple poles on the imaginary axis only, and with positive real residues in these poles. And since is in the form of

one can always write

as

For the partial factor is on the imaginary axis, and the residue should be a positive real number as we have elaborated previously. Using (2.28) for the evaluation of the residue one has

which is exactly the first quotient in the continuous fraction of in (2.18). To keep the criterion rolling forward, which is equivalent to getting succeeding quotients in (2.18), there are two points that we need to clarify. First of all, it should be clearly recognized that in (2.39) is positive real and the remainder function should have the same properties (2.27) as does, if and only if is a Hurwitz polynomial. This is because the remainder function is the sum of all the partial fraction terms of except Since the

132

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

sufficient and necessary condition for to be Hurwitz polynomial is that the corresponding has only imaginary poles and positive real residues, this condition is also true for the remainder function and so the remainder function satisfies properties (2.27) as well. Secondly, the reciprocal of the remainder function complies with the conditions (2.27) if and only if the remainder function itself conforms to it. Denoting the reciprocal of the remainder function by one has, according to (2.28) and (2.38),

Note that the numerator and denominator of should collectively one order less than those of in non-degenerated cases. One can continue the criterion process by performing the partial fraction decomposition on and the residue of the pole should have the same property as in (2.38), if and only if is a Hurwitz Polynomial. 2.3.4 Example We use some figures to visualize the change of sign of that is given by

in (2.38). Suppose

or

The remainder function in (2.41) satisfies the conditions (2.27). Thus, the sign of determines whether or not fulfills the conditions. When e. g., must fulfill the conditions. with respect to and is depicted in the 3-dimensional plot in Fig. 6.4 (the upper part), and with respect to only is depicted in the 2-dimensional plot (the lower part). Although may not be continuous somewhere along 4 the imaginary axis , it can be seen that restrictively distributes in the negative region when is negative, and in the positive region when is positive. Furthermore, when is also zero5 at any defined points on the imaginary axis. Therefore, does fulfill the conditions (2.27).

4

The function is not continuous at the zeros of its denominator. It is also called ‘hot analytical” at the zeros in some other references. 5 When the numerator of has real part only, and its denominator has imaginary part only. Therefore, has imaginary part only.

Transformation: Application I — Model Stabilization

Figure 6.4. 2-D and 3-D Plots of

133

when

When degenerates to the remainder function, so that still should satisfy (2.27). The plots are given in Fig. 6.5. The 2-dimensional plot is a good analogy to that in Fig. 6.4. Fig. 6.6 is the 2-dimensional and 3-dimensional plots of when It is seen that in the region, has a big plunge below 0, while

134

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 6.5. 2-D and 3-D Plots of

in the region, there is a big surge of the conditions (2.27). Finally, Fig. 6.7 shows the trace of a root of

when

above 0. This violates

Transformation: Application I — Model Stabilization

Figure 6.6. 2-D and 3-D Plots of

135

when

with the change of from +5 to –5. We see that the trace travels from negative region (when through the origin (when to the positive region (when

136

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 6.7. Plot of root locations for different

3.

Stabilizing Models After

values.

Reduction

A Hurwitz polynomial approximation method is proposed in this section. The method treats transfer functions derived from truncated admittance from Alg. 2 to stabilize transfer function approximations. The problem of representing a high-order linear system by a reduced-order linear model is of considerable importance in simulation. One class of solutions, the so-called Padé approximation methods have been extremely successful in VLSI interconnect model reductions. AWE and some of its variants are in this class. There is, however, one disadvantage of these, but not all, Padé methods. They may produce unstable reduced models from stable large-order models. Due to Th. 4.2, reduced order admittance derived from transformation agrees with exact admittance upto the first order terms in both its numerator and denominator. So that a transfer function derived from these reduced-order admittances also agrees with the corresponding exact transfer function on up to order terms. DTT method [43] has no post-process on low-order transfer functions. A truncated low-order transfer function of an originally passive linear system may not be stable, simply because a truncated low-order polynomial of a high-order Hurwitz polynomial may not be a Hurwitz polynomial any more. We employ a method that utilizes truncated transfer functions to generate stable transfer functions. The stable transfer functions approximate exact ones by matching the first a few time moments.

Transformation: Application I — Model Stabilization

137

To derive stable transfer functions out of truncated ones, let us look at a real rational function

with the even and odd parts of

for even, and with the last terms interchanged if the order is odd. Here we suppose, merely to be specific, that the denominator of the given rational function is of even order. is said to be a Hurwitz polynomial if coefficients of quotient terms from continuous fraction of in (3.3) are all positive [47]

Actually the quotient in (3.3) depends only on the first terms in (3.1). Thus if in (3.1) is a Hurwitz polynomial, the first continuous fraction quotients of are the same as those of in (3.4) below:

where is a truncated order polynomial of Therefore these quotients are guaranteed positive. In order to get a Hurwitz polynomial approximating we take all the quotients of in (3.4) from the first, up to and excluding the first negative one, and then we have a rational approximant of as

By definition, the polynomial

138

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

is a order Hurwitz polynomial, which is also an approximation of Finally, a stable transfer function approximating in (3.1) can be derived as follows. Because transformation helps preserve low-order terms of a high-order linear transfer function, we can perform a continuous fraction on the denominator of the reduced-order transfer function, and construct a Hurwitz characteristic polynomial is the denominator of our new transfer function

To evaluate the numerator in (3.7), we match the moments of those of in (3.1) up to the order term, i.e.,

in order for

with

to be proper.

We go through a numerical example to illustrate the algorithm. Given a real rational function

we can write

and

defined in (3.2) as

139

Transformation: Application I — Model Stabilization

We make a continuous fraction on

then we have

Because all the coefficients of the quotients are positive, in (3.9) is a Hurwitz polynomial. is considered here as a transfer function of a linear network. The 4th-order transfer function, from 4-th order truncated admittances out of transformation, can be written as

Following the same procedure in (3.2), we write

and

of

as

A continuous fraction on

The first two quotients in (3.11) are positive and the same as those in (3.10), which is consistent with our conclusion above. The remaining two quotients have negative coefficients so that we simply ignore them. Following (3.6), we have the Hurwitz approximant

As and are the first two moments of in (3.9), it is straightforward to find out that makes the first two moments of equal to those of in (3.9). Thus is a low-order stable transfer function which approximates

140

4.

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Experimental Results

Fig. 6.8 plots locations of poles on complex plane. These poles are approximated for a mesh-like circuit in entry 4 of Table 1. A 30 order reduction was performed, and a 16 order Hurwitz approximant was obtained, because in this test case, we happened to get one more positive quotient from the 30-order transfer function, which led to one more moment matched. Padé approximations and direct result of transformation had all resulted in positive real parts in some poles.

Figure 6.8. Pole analysis using transformation with Hurwitz approximation as compared to transformation only and AWE method for RLC power/ground mesh.

5.

Summary

This chapter showed an application based on generalized reduction, proposed in Chapter 4 and 5. Transfer functions are derived from reduced circuit models. and resultant transfer functions are further treated via a Hurwitz polynomial approximation to guarantee stability. The transfer functions can be used in pole/zero approximation and time domain waveform evaluation.

Chapter 7 TRANSFORMATION: APPLICATION II — REALIZABLE PARASITIC REDUCTION

After eliminating all internal nodes using transformation, we realize each branch by calling for a positive real function approximation. Since all the coefficients in admittances are non-negative, first order realization is guaranteed. Therefore Elmore delays of original networks are preserved. Higher order realization of admittances1 are achieved by choosing a passive template structure with the same order and do the approximation with the constraints that each element needs to be positive and the moments are kept approximately the same.

1.

First-Order realization For any second-order

admittance of the form

it is seen from Corollary 4.1 that

If

in (1.1) can be realized using circuit in Fig. 7.1 (a), where

otherwise it can be realized using circuit in (b), where

142

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 7.1. First Order Realization: (a) RC configuration; (b) RL configuration

Consider RC networks with each branch consisting of a conductance and capacitance in parallel. Some elements may be absent, in which case the corresponding or is zero. For such a network with two branches, the admittance after the center node is eliminated is

It can be seen that

so that can be realized using RC model shown in Fig. 7.1(a). It can be proven by induction that any admittance reduced from any RC network can be realized by the RC model.

2.

Admittance Not Realizable in Nature

After we have proved for the first-order realizability of admittances after transformation, naturally our next question is: are they realizable for any order? Unfortunately, the answer is no. Lemma 7.1 (Unrealizability of Admittances). For any admittance derived from transformation, no matter it is truncated or not, if its order is higher than 1, then it is not guaranteed to be realizable. We have a simple example to support our conclusion. Example 7.1. The circuit is shown in Fig. 7.2. Neither nor is realizable, which can be verified by any modern network synthesis theory, e. g., positive real function criterion[47].

1

admittances can be changed to stable admittances before the realization is called.

Transformation: Application II — Realizable Parasitic Reduction

Figure 7.2. Unrealizable admittance after

The admittances in the above equation are transformation without any truncation. functions, therefore, they are not realizable.

3.

transformation

143

and

admittances derived from and are not positive real

Idea of Templates

To achieve high-order approximation to admittances, we devise high-order templates borrowed from circuit structures in admittance realization theory. For example, the circuit shown in Fig. 7.3 is a structure used in Brune’s synthesis procedure[104]. When serial-parallel withdrawal does not work for a realizable admittance, one can always invoke Brune’s procedure to realize it using a similar structure. The method, however, can not be applied directly to admittances, because these admittances are truncated so that they may not be realizable. But since the admittances preserve low-order terms of exact input admittances, which are positive real functions, we can expect that the admittances are positive and real within some moderate frequency range. This inspires us to use the general Brune’s admittance structure as templates to approximate the admittances, with the constraint that each element needs to be positive and the objective that the coefficients of the admittances are matched as much as possible. In Fig. 7.3, the shunt RLC box repeats the same circuit topology from the left, but elements may have different values. It is there because Brune’s realization process may have multiple cycles. In each cycle, it uses the network on the left to the RLC box to reduce the order of the input admittance by two, until the RLC box can be realized by a conductance. In Brune’s realized networks, is allowed to be either positive or negative, and always has an opposite sign to All other elements in Fig. 7.3 are positive. Admittance in the form of Fig. 7.3 is a positive real function of and the T inductor series can be replaced by an ideal transformer with positive primary and secondary inductances.

144

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 7.3. Brune’s Admittance Structure

Geometric Programming

4.

As a special sub-class of nonlinear programming problems, geometric programming problems can be transformed so that their nonlinear constraints become linear. Thus some concepts and ideas from linear programming can be borrowed.

4.1

Intuitions

Given two non-negative numbers and we know that their arithmetic mean is always larger than or equal to their geometric mean, giving

To prove this, it is the same to prove that

It is clear that

Inequality (4.1) can be generalized as

where are arbitrary non-negative numbers and arbitrary positive weights that satisfy the normality condition

are

Transformation: Application II — Realizable Parasitic Reduction

145

A proof can be found in [46].

4.2

Primal and Dual Functions

Now we express

as a power function

Here the coefficient but the exponents are arbitrary real constants. The parameters are taken to be positive variables. If we consider as a component cost and as the sum of all component costs, then

We term it the primal function. If follows from inequality (4.2) that

Here the exponents

are the linear combinations

Suppose it is possible to choose the weights so that all the exponents zero. The does not depend on t any more. Thus

are

and we term it the dual function. Let us take a look at a small example. Suppose we want to minimize a primal function

From inequality (4.6) we know

subject to the normality condition

If we choose

it follows that

So no matter what t is chosen, the lower bound of

would be 30.

146

4.3

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Orthogonality Conditions

From (4.7), it is clear that if we can solve a set of linear simultaneous equations

subject to the normality condition (4.3), then all the exponents are zero and the normality condition will be satisfied. The equations in (4.9) are called orthogonality conditions. and are dual because it is possible to satisfy the orthogonality conditions with positive weights and that the maximum of the dual function is equal to the minimum of the primal function

4.4

Solution Space of Dual Problems

Suppose orthogonality conditions (4.9) are linearly independent on each other. Particularly, (1) if the number of orthogonality conditions is less than the number of variables by one, i.e. then there is only one solution because the dimension of the solution space is zero; (2) if then there are infinite solutions, and the dimension of the solution space is (3) if the number of orthogonality conditions is greater than or equal to the number of variables, i.e. then I think it is not a feasible geometric programming problem. The discussion about dimensions of solution space here is just like what we learned about convex sets in Linear Programming. But because our objective function is nonlinear, maximum or minimum values on convex sets are not on the vertices any more. So the Simplex method could not be used.

4.5

Geometric Programming with Constraints

Instead of tediously enumerating formula filled with symbols, I would prefer to give an example to show how to solve a geometric programming problem with a constraint. In this example, we use the assumption that the maximum of the dual function is equal to the minimum of the primal function And the solution of satisfy the orthogonality conditions with positive weights Please refer to [21] to check out how to get the primal solution from a dual solution. The example is given by

subject to a constraint

Transformation: Application II — Realizable Parasitic Reduction

147

From geometric inequality (4.6), it is clear that

and

We now multiply the geometric inequality (4.10) by the two extreme sides of the constraint inequality (4.11)

With the primal function orthogonality conditions

we can write the dual function as follows: the

looks different from (4.8) because we add a constraint in the problem. However, and which correspond to the two product terms of the constraint, are not subject to a normality condition such as

The normality and orthogonality conditions go as follows:

To satisfy both the normality condition (4.14) and the orthogonality conditions (4.15), we have to solve (4.14) and (4.15) simultaneously. It turns out that the dimension of the solution space is one, because there are three equations and four variables. Because the number of solutions is infinite, we need to find a basic vector of the solution space to represent all possible solutions. To do this, let us first look at the orthogonality conditions (4.15) only. Because there are four variables, the problem is located in a 4-dimensional Euclidean space and the two row vectors in matrix

build up a 2-dimensional sub-space of So we have to find another two linearly independent vectors in to build up the complimentary space of it.

148

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Let us write the two row vectors above into columns and use elementary column operations on the matrix to diagonalize it, giving

Because

and the two row vectors in

are linearly independent, these two are basic vectors of the complimentary space. Dividing the first row vector of (4.16) by the sum of its first two components, we obtain a vector

which satisfies both the orthogonality condition and the normality condition. Thus is a normality vector for the dual problem. We add the first two components of the remaining row vector of (4.16) and subtract from this vector the product of this sum with the normality vector giving

The general solution to the normality and orthogonality conditions is

149

Transformation: Application II — Realizable Parasitic Reduction

or, in component form,

It is clear from these equations that so that

satisfies

only when

is restricted

Template Realization Using Geometric Programming

5.

We formulate the realization problem in Geometric Programming[21]. Suppose is a admittance in the form of

Here tance

and

and

are positive real numbers. We build a in Fig. 7.3, can be written as

order Brune’s admit-

are given by

where

and In (5.3) and (5.4), are element variables in the template and are the numbers of and in and respectively. Note that they are not variables. Once a template is determined, and are

150

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

known. We formulate the Geometric Programming problem as follows: Objective function:

subject to

For example, given a 2nd-order

admittance

we substitute for R and for the RLC box in Fig. 7.3 and use the resultant network as a template. Hence the input admittance of the template is

where and In this case, and in (5.5) are product terms in the numerator and denominator of (5.9) respectively; in (5.6) is elements in the template; and are symbolic coefficients of powers of in (5.9), and and are numerical coefficients in (5.8). The objective function tries to minimize the reciprocals of and On the other hand under the constraints that these terms can not be greater than the numerical coefficients in (5.8). When the objective function is minimized and the inequalities in the constraints all become equalities, then the coefficients in (5.8) are matched, and so are the moments.

6.

Experimental Results

We use a few examples in order to show the superiority of proposed realizable parasitic reduction in terms of orders of reduced models and reduction efficiency. The first example is a high-performance clock distribution circuit in a real design case. The circuit with 78564 nodes is a mixture of RC trees and meshes. Our method can reduce it to a simple RLC circuit with four nodes only. Circuit given in Fig. 7.4(b) is such a realization. In this case, if we use TICER to achieve the same reduction ratio2, the reduced circuit is given in Fig. 7.4(a). 2

The original TICER algorithm uses time constant of each node as an error control mechanism, therefore such a high reduction ratio may not be allowed in the algorithm. The point of our comparison is that achieves a better reduction ratio, yet the result is close enough to SPICE.

Transformation: Application II — Realizable Parasitic Reduction

151

Figure 7.4. Comparison of two reduced circuits

Both methods realize each admittance using passive elements. But none of them in (a) matches first-order moments. In (b) the two shunt admittances to ground match to the first order, and the floating one matches to the second order. In Fig. 7.5, we use a reduced circuit with higher order branch admittance to generate the waveform. The waveform for TICER-reduced circuit (Fig. 7.4(a)) is also given in the figure for comparison. We find out that the waveform of are closer to the SPICE result without reduction.

Figure 7.5. Comparison of responses of a RC network

The response of a 62-node RLC network with 7 ports is plotted in Fig. 7.6. The response evaluated from the reduced network is very close to PRIMA’s curve, and both of them are very close to SPICE output. Table 7.1 summarize the reduction ratio versus reduction efficiency. It is clear that minimizing non-zero fill-ins is a good ordering scheme in transformation-based reduction techniques. For instance, TICER eliminates nodes by picking those with extreme time constants first. Because it does not consider the degrees of

152

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 7.6. Comparison of responses of a RLC network

nodes when eliminating them, this ordering scheme is inferior in terms of efficiency when high reduction ratio is preferred. Although one can specify a limit on reduction ratio in TICER, the complexity may be passed to the following simulation stage because the sparsity of circuits has been tampered already. A compromise of the two ordering schemes is also promising.

7.

Summary

In summary, first-order realization of admittances is guaranteed, and highorder realization is accomplished by template optimization. The new realization procedure works effectively for templates of order ten or less in our experiments. And the merit of the method is that templates are realized and preserve electrical properties at the port simultaneously.

PART III

ANALOG VLSI CIRCUITS

This page intentionally left blank

Chapter 8 TOPOLOGICAL ANALYSIS OF PASSIVE NETWORKS

Aside from the model order reduction techniques that we have introduced in the previous chapter, topological analysis is another powerful circuit analysis tool. The method shows the relationships of circuit responses and circuit topologies, using the matrix approach. Because the topology-based circuit analysis method provides essential physical insights of circuits, a combination of it with model order reduction concepts raises special interest to researchers in layout-driven circuit reduction. In this chapter, we shall derive the topological formulas for the passive oneport and various network functions of a two-port with zero initial conditions and without mutual inductances. First, we shall develop the relationship of responses of a passive one-port and the determinant and cofactors of its node admittance matrix. Then after the definitions of the various transfer functions—such as the open-circuit impedances, short-circuit admittances, and voltage transfer functions —for a passive two-port, we further explore the expressions of these functions in terms of the determinant and cofactors. Finally we introduce the interesting idea of solving a linear network by the use of graphs —a direct application of flow graph techniques of linear system analysis.

1.

Review of Node Admittance Matrix

In this section, we shall introduce the composition of node admittance matrix from incidence matrix and branch constitutive relations.

1.1

Incidence Matrix of Undirected Graph

Definition 8.1. Given an undirected graph with vertices and edges. A vertex is chosen arbitrarily as reference (ground). the incidence

156

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

matrix of G is a matrix A of order with each row identified by one of the other vertices and each column by an edge; i. e.,

Example 8.1. Let be a undirected and connected graph shown in Fig. 8.1. The incidence matrix of is given by

Figure 8.1. An undirected graph

If we add a row for the ground vertex in is given by

with 4 vertices and 6 edges.

the resultant incidence matrix

Remarks: is a singular matrix, because the rows are linearly dependent. Generally for any graph there are at most independent rows in the incidence matrix A. We will give the properties of incidence matrix of directed graphs in the next subsection.

1.2

Incidence Matrix of Directed Graph

Definition 8.2. Given an undirected graph with vertices and edges. A vertex is chosen arbitrarily as reference (ground). The incidence

157

Topological Analysis of Passive Networks

matrix of G is a matrix A of order with each row identified by one of the other vertices and each column by an edge; i. e.,

Comparing (1.2) with (1.1), the only difference is that nonzero entries in incidence matrices of directed graphs can be either 1 or –1, depending on the direction of edges. Example 8.2. Let be the directed and connected graph depicted by Fig. 8.2. The incidence matrix of the directed graph is given by

Figure 8.2. A directed and connected graph

with 4 vertices and 6 edges.

Similarly, the incidence matrix with an extra row for the ground is given by

Example 8.3. Let be the directed, unconnected graph shown in Fig. 8.3. The incidence matrix of is

158

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 8.3. A directed and unconnected graph

with 7 vertices and 9 edges.

From the previous examples, we observe the following properties of the incidence matrix A of a directed graph

1 There must be no zero row in the matrix for a connected graph. For a zero row corresponds to an isolated vertex in the graph. 2 The matrix can not be partitioned in the form of

in Example 8.3)

through any number of row and column permutations. Because a matrix in such a form corresponds to an unconnected graph with at least two connected subgraphs. 3 The incidence matrix with an extra row representing the reference vertex

has dependent rows. Because the algebraic sum of all the is a zero row. 4 The

rows

rows in the matrix are linearly independent for a connected graph. Assume that these rows are not independent, that means there exists a set of constants, not all zero, such that

Topological Analysis of Passive Networks

159

Notice that the column identified by any edge incident with the reference and another vertex, say has only one nonzero (1 or –1). In order for (1.3) to hold, has to be zero. Effectively, and the reference vertex collapse into one vertex, the new reference vertex. The problem is down-sized to prove that the remaining rows are linearly dependent. We continue this process. Because G is a connected graph, finally all constants in (1.3) must be zero. Thus the conclusion contradicts our assumption, i.e., the rows in the matrix must be linearly independent for a connected, directed graph. It is worth noting that this proof is also valid for connected, undirected graphs.

1.3

Composition of Node Admittance Matrix

We have derived the node admittance matrix in the differential form in 1.2 by the use of KCL and branch constitutive equations. In this subsection, we rewrite the node admittance matrix in terms of incidence matrix and branch constitutive equations. Essentially, the two derivations are equivalent, but the latter gives a better insight for topological analysis. Given a linear network with nodes and branches, the KCL equations for the non-datum nodes are given in the matrix form by where the matrix A is the incidence matrix of the directed network1. is a diagonal matrix whose nonzero entries correspond to branch admittances. is the vector of branch voltages. And is the vector of current sources injecting into non-datum nodes. represents the currents flowing in branches in the network. Thus, each row of is the algebraic sum of currents on admittance branches leaving a node, which, due to KCL, should be equal to the current source coming into the node. Given nodal voltages in the vector the branch voltages are given by

Insert the above equation into (1.4),

Therefore, the node admittance matrix Y is composed of

Example 8.4. The node admittance matrix Y of the linear network depicted in Fig. 8.4 is given by 1 Branches in the directed network has pre-defi ned current directions. Thus the directed network is considered as a directed graph.

160

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 8.4. A 4-node linear network used in Example 8.4.

Therefore, the nodal analysis equations in the matrix form are given by

2.

Problem Formulation

Starting from the node equations (1.6) for a network with have

nodes, we

Topological Analysis of Passive Networks

161

where is the nodal voltage at node and is the amount of current from current sources injecting into The general expression for the voltage is

where is the determinant of the node admittance matrix Y, and cofactor of or

the

and

is the minor matrix formed by deleting row and column from Y . Drivingpoint impedance, open-circuit impedance, transfer impedance, and voltageratio transfer functions can all be obtained from (2.2).

2.1

Driving-Point Admittance

The simplest network that one can utilize topological formulas to analyze is an one-port driven by a single current source at the port, as depicted in Fig. 8.5. Since is the only source and from (2.2), we find out that

Figure 8.5. One-port network driven by single current source

Hence, the driving-point admittance function, and its reciprocal, namely, the driving-point impedance function are readily obtained from (2.5) as

162

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

and

respectively.

2.2

Open-Circuit Impedance

In the two-port network shown in Fig. 8.6, and are the only two sources. The port voltages can be obtained from nodal voltages; that is,

From (2.2), we have

Figure 8.6. Two-port network driven by two current sources

Noting that

and

and

(2.9) can be rewritten as

Topological Analysis of Passive Networks

163

Substituting (2.10) into (2.8), we find that

>From (2.11) we know that and may be expressed in terms of the currents and at the two ports. Thus we write

where

Let us observe the physical significance of the coefficients and in (2.12). Suppose that we open the port by removing the current source from the system (Fig. 8.7). Then and (2.12) becomes

Figure 8.7. Illustration of the two-port in determining open-circuit impedances.

or Similarly, the other coefficients can be obtained by

Hence these functions are called the open-circuit impedance functions of the passive two-port network shown in Fig. 8.6. More precisely, and are the open-circuit driving-point impedances at ports Gnd) and and and are the open-circuit transfer impedances of the two-port.

164

2.3

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Network Transfer Functions

Let the passive two-port N be driven by a current source at port Gnd) with a load admittance at port as shown in Fig. 8.8. Then

Figure 8.8. A loaded passive two-port N

since

is the only source, from (2.2), we get

and

The transfer impedance to the stimulating current by

is defined as the ratio of the output voltage From (2.19), the transfer impedance is given

The voltage-ratio transfer function voltage to the input voltage function is given by

is defined as the ratio of the output From (2.18) and (2.19), the transfer

Remarks: All the network functions that we have listed above are all written in terms of the determinant of the node admittance matrix and its various cofactors of certain network. The contribution of topological analysis is the establishment of relationships of the determinant and cofactors with the network topology.

3.

Topological Formulas

In this section, we give the formulas for the determinant and cofactors of some node admittance matrix from a topological point of view.

165

Topological Analysis of Passive Networks

3.1

Topological Formula for Determinant

Theorem 8.1. If C and D are two matrices of orders and if then

and

respectively,

where call a major of C, is a determinant of a matrix of order obtained from C by deleting some columns; and called the corresponding major of C to is a determinant of the matrix of order obtained from D by deleting the corresponding rows. We now illustrate the ideas in this theorem by means of the following example. Example 8.5. Let C and D be the following matrices:

Then

On the other hand, the majors of C and D are:

Thus, which agrees with the value of

computed directly from the product CD.

Theorem 8.2. Suppose that N is a linear network with nodes and branches. Its incidence matrix is denoted by A, and a major of A, is the determinant of a matrix of order obtained from A by deleting some rows. The sufficient condition for is that the columns in constitute a tree structure in N. Furthermore, if then Proof. Elementary graph theory tells us that, for a loop in N, the column of any branch in the incidence matrix is a linear combination of the columns of other branches in the loop. The constants of the linear combination are either +1 or –1, depending on the directions of the branches.

166

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Indeed, when is not zero, has a value of ±1. If we are able to arrange a row-based expansion2 sequence in determining the determinant of such that each row in the expansion has exactly one nonzero, either 1 or – 1, then is either 1 or –1. We guarantee the existence of such a sequence under the assumption that the columns in constitute a tree of network N, by 3 noticing the fact that leaf nodes of the tree have only one nonzero entry in the corresponding rows in Therefore, we can always start from any of those rows. And the resultant minor matrix obtained by crossing out the row and column corresponds to the subgraph after removing the node and the incident branch from the tree. Then we can again pick any of the leaf nodes in the subgraph. Therefore,

The following example shows the continuous process of a row-based expansion. The four determinants in the middle of

has an one-to-one mapping to the graphs in Fig. 8.9. For example, the second minor matrix after crossing out the first row and column in the first matrix corresponds to graph (b) with and removed from (a). Theorem 8.3. Let N be a passive network without mutual inductances. Let be the number of nodes, be the number of branches, be the number 2 The determinant of a 1 × 1 matrix is its sole entry. Let and assume that determinants of order less than have been defi ned. Let be an matrix. The cofactor of in A is

where is the minor matrix of A obtained by crossing out the determinant of A is

row and

column of A. The

The definition uses mathematical induction, and is called row-based expansion. It is free to choose of any integer from 1 to 3 Leaves of a tree are the vertices whose degree is 1.

Topological Analysis of Passive Networks

167

Figure 8.9. Removing leaf node one at a time corresponds to expanding the row of the node in and its minor matrices.

of all possible trees in N. The determinant is given by

of the node admittance matrix Y

where namely the tree admittance product, is the product of the admittances of all the branches of the tree Proof. From (1.7), we know that the node admittance matrix Y can be decomposed in the form of where theorem,

is of order

and

of order

In the light of the previous

Our aim is to proof that there is a one-to-one mapping between nonzero products in (3.4) and tree admittance products of network N. First we claim that a nonzero major of A results in a nonzero major of Because is a diagonal matrix, is obtained from A multiplying the columns of A by their corresponding branch admittances. Due to the linearity of determinant, where are the diagonal entries in Particularly, a major of obtained by removing some columns is equal to the corresponding major4 4

The major is obtained by removing the

columns with the same indices from A as those removed from

168

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

of A multiplied by the corresponding branch admittances of the remaining columns, i. e.,

Since branch admittances are not zero, a nonzero major of A results in a nonzero major of Secondly, since the determinant of a matrix is equal to the determinant of its transpose, a major, say of A, is equal to the corresponding major of to Finally, with the first and second claims, a condition that makes would be sufficient for Theorem 8.2 tells that the sufficient condition for is that the columns in constitute a tree structure in N. Therefore, all the nonzero correspond to all the trees in N. Example 8.6. A resistive one-port network with one driving current source is depicted in Fig. 8.10. Applying the topological formula in (3.2) to the network, we enumerate all the possible trees with resistive branches only in Fig. 8.11.

Figure 8.10. An illustrative one-port example.

Notice that current source is excluded from the tree enumeration, because it is not involved in the node admittance matrix. The determinant of the matrix is given by

3.2

Topological Formula for

Given a node admittance matrix Y, is defined as the determinant of a matrix, called minor matrix of Y, obtained by crossing out the row and column of Y. The minor matrix is the portion shown in shading in the matrix

169

Topological Analysis of Passive Networks

Figure 8.11. All the possible trees of the one-port with resistive branches only.

Figure 8.12. Minor matrix

Since Y is a product of a matrix and a matrix the minor matrix of Y is the product of the two matrices and column from and obtained by removing the row and the respectively (Fig. 8.13). Before we proceed to establish the relationship between the determinant of minor matrices and circuit topologies, let us interpret the physical meaning of the two component matrices of and is a diagonal matrix, where is a matrix obtained from A by removing the matrix theory tells us that

row. Elementary

170

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 8.13.

Computing minor matrix

from

and

Therefore, our question focuses on the physical meaning of and For the given network N, we use to represent the network deduced from N by merging node and the ground. Due to the merging, some node may have multiple branches connected to the ground5. Essentially, matrix with the row removed from the incidence matrix A of N is the incidence matrix of has the same result. Example 8.7. Consider the network N shown in Fig. 8.4. If we remove the 2nd row from A, then the resultant matrix

is the incidence matrix of the following network, deduced from N by merging with the ground. Definition 8.3. A 2-tree of a connected graph G is a subgraph of a tree T of G obtained by removing any one of the branches from T. Example 8.8. Fig. 8.15 illustrates the definition of 2-trees. A 2-tree is actually a forest with 2 trees, derived from a given tree. Notice that one tree can have many 2-trees. Theorem 8.4. A major of say is the determinant of a matrix of order obtained from by deleting some columns. If the columns in constitute a 2-tree with node in one part and the ground in the other, then Proof. Consider the graph if it represents a tree structure 5

In the light of Theorem 8.2, in The tree branches in

This is an important fact that leads to the concept of 2-trees of network N.

must

171

Topological Analysis of Passive Networks

Figure 8.14. Network

deduced from N from Fig. 8.4 by merging

and the ground.

Figure 8.15. A 2-tree example used in Example 8.15.

constitute a 2-tree

with node

in one part, and the ground in the other.

In other words, can not be together with the ground in 2-tree if it were, then there must be a loop in due to the merging of ground, which violates the definition of a tree.

Because and the

Theorem 8.5. The cofactor, of is equal to the sum of all the 2-tree admittance products, of N, each of which contains nodes and in one part and the ground in the other. That is,

Proof. Since

from Fig. 8.13,

172

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Therefore, in the light of Theorem 8.1,

Theorem columns and becomes

8.5 tells that, in order for and to be nonzero, in the two matrices have to constitute a 2-tree of N. Furthermore, have to be separate from the ground in the 2-tree. Thus, (3.8) (3.7).

Example 8.9. We illustrate how to use the topological formulas to solve for open-circuit transfer impedance from port gnd) to in the network N depicted in Fig. 8.16.

Figure 8.16. Using topological formulas to solve for open-circuit transfer impedance of a 2-port.

Consider (2.13) in solving for the open-circuit transfer impedance from port gnd) to Since

we need to evaluate the determinant and the cofactors respectively. In order to compute the determinant Theorem 8.2 states that one has to enumerate all the (resistive) trees in N (Fig. 8.16), i. e.,

Next, we enumerate all the 2-trees that isolate the ground, respectively. Therefore,

and

and

and

from

Topological Analysis of Passive Networks

173

Figure 8.17. Using topological formulas to solve for open-circuit transfer impedance of a 2-port.

Figure 8.18. Counter-example showing invalid 2-trees in the computation of cofactors

As an counter-example, Fig. 8.18 shows some invalid 2-trees in the computation of and For instance, the 2-tree in (a) is not valid because and the ground are in one part of the 2-tree. Corollary 8.1. The cofactor, of is equal to the sum of all the 2-tree admittance products, of N, each of which contains node in one part and the ground in the other. That is,

3.3

Time Complexity

Theorem 8.6. The total number of trees of a connected network N is equal to the value of the determinant of the product of its incidence matrix A and its transpose i. e.,

Proof. The proof of this important theorem is rather simple. We recall that

174

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

If we set every branch of N by an resistor, then each branch has an admittance of unity and the branch admittance matrix becomes a unit matrix. Thus (3.10) is reduced to We note that each term in (3.10) must be unity since it is a tree admittance product, and each branch of the tree has a unit admittance value. Consequently, V(Y) is equal to the total number of trees of N. This completes the proof. Example 8.10. For a complete graph with 3 nodes, apparently it has 3 different trees. The incidence matrix is given by

Therefore,

and

Generally, a complete graph with

nodes would have

One can use mathematical induction to prove (3.11).

4.

Flow-Graph Technique

As an extension of the topological formulas, flow-graph technique [14] establishes relationships between a system of linear algebraic equations with a graph, called signal-flow graph, as defined by Mason and then solves the system topologically using the properties of this specially defined graph. The idea of solving a system of linear algebraic equations by the use of graphs was first introduced by Mason [58, 59]. Although signal-flow graphs have proved to be very useful for the analysis of engineering problems because they display intuitively the causal relationships between the variables of a system under study, the expansion of Mason’s gain formula6 from signal-flow graphs is very complicated. Later on, Coates introduced a modified version of signalflow graph, called the flow graph, and gave a rigorous derivation of a simpler gain formula. Our discussion mainly focuses on the Coates’ flow graph. 6

A gain formula of a given linear algebraic system is the solution of an unknown in terms of inputs

represented

175

Topological Analysis of Passive Networks

Definition 8.4 (Flow Graph A flow graph, is a graph with weighted and directed branches interconnected at points called nodes, A flow graph uniquely defines a system of linear algebraic equations. The flow graph corresponding to a system of linear algebraic equations with unknowns,

has nodes (representing the unknowns in (4.1)) plus a source node 1. If in the system of (4.1), then there is a branch directed from node to node with branch gain if then there is a branch directed from the source node 1 to node with branch gain Example 8.11. For the case that assuming that all the are (4.1) becomes

and the

and the flow graph representing (4.2) is shown in Fig. 8.19.

Figure 8.19. The fbw graph of (4.2).

Let us recall Cramer’s rule for solving a system of linear algebraic equations with unknowns written in the matrix form, AX = B;

176

If the determinant rule states that

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

of the coefficient matrix A is different from zero, Cramer’s

where is the cofactor of the element of Relating the quantities in (4.4) topologically to the subgraphs of the flow graphs, Coates was able to derive his gain formula based on the modification he made on the Mason graph. But, before discussing Coates’ gain formula and its derivation, it is necessary to introduce the following definitions: Definition 8.5 (Subgraph The subgraph of the flow graph subgraph of by deleting the source node 1 and all its branches.

is the

Definition 8.6 (Connection). A connection of the flow graph is a subgraph of such that (a) each node of is included; (b) each node has only one incoming branch and one outgoing branch. Definition 8.7 (Connection Gain). The connection gain of a connection is the product of the branch weights of all the branches of that connection. It is denoted as Definition 8.8 (Directed Path and Directed Loop). A directed path from to is a path in which each directed branch is taken toward in the proper direction. Particularly, a directed path becomes a directed loop, if the directed branch in the path forms a circuit, i. e., Definition 8.9 (One-Connection). An one-connection from node to node of graph is a subgraph of containing all the nodes of such that (a) has only one outgoing branch and no incoming ones; (b) has only one incoming branch and no outgoing ones; (c) all other nodes have exactly one incoming and one outgoing branch. Definition 8.10 (One-Connection Gain). The one-connection gain of a oneconnection is similarly defined as is the connection gain of a connection. Therefore, an one-connection is a forward path together with, possibly, some directed loops. Example 8.12. Consider the flow graph of Fig. 8.19. The corresponding subgraph is shown in Fig. 8.20; the two connections of are given in Fig. 8.21; and the four one-connections of are depicted in Fig. 8.22. The connection gains of the two connections in Fig. 8.21 are and Similarly, the one-connection gains of the two-connections of Fig. 8.22 are and

177

Topological Analysis of Passive Networks

Figure 8.20. The subgraph of

in (4.2).

Figure 8.21. The two connections of

Lemma 8.1. The determinant of the system of (4.3) can be evaluated topologically from of its flow graph by the formula

where is the number of directed loops in the connection; is the connection gain of the connection of and the summation is taken over all connections of Proof. From the theory of determinants, it is known that

where the summation is taken over all the

permutations of the form

178

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 8.22. The four one-connections of (c)(d) The two one-connections from 1 to

(a)(b) The two one-connections from 1 to

and (sgn P) of a permutation is ±1, depending on whether the permutation P is even or odd7. Now, consider a particular product in the sum given in (4.7). Let be the set of all branches whose gains appear in the product Since is a product of factors with running from 1 to there is exactly one branch of that terminates at each of the nodes of Since is a permutation of there is exactly one branch of originating from each node of 7A

permutation is in the form of

A transposition is just an interchange of the two objects

and of (4.8), i. e.,

Every permutation of can be represented by a product of transpositions, and an even (odd) permutation must be decomposed of an even (odd) number of transpositions.

Topological Analysis of Passive Networks

179

Conversely, given an arbitrary connection of since, by definition, it contains one branch terminating at each of the nodes of and one branch leaving each of the same nodes, then its connection gain can be written as

where is a permutation of Hence, it will appear as one of the products in (4.7). Therefore, by simply listing all the connections of and finding all the connection gains—that is, obtains all the terms of the sum in (4.7). As for the sign of each term (sgn P), consider again a particular product of the sum given in (4.7) and its associated connection of the graph G. Clearly, is a collection of directed loops. For the sake of simplicity, let us assume that consists of three non-touching directed loops having nodes, respectively. Then, since, by definition, all nodes of are included in a connection. Now we relabel8 the nodes of so that, when we traverse along the first loop of in the positive direction, the nodes will be touched in the natural order, and similarly for the other two loops. The branch-gain product of the first loop is then

Note that the factors of this product are ordered so that their row subscripts occur in their natural order as required by (4.7). Hence the sign assigned to is that assigned to the permutation defined by

To rearrange this permutation in the natural order,

transpositions are required. Hence the sign of the permutation (sgn P) is Note that there are three directed loops in the product It is clear, 8

Suppose the permutation after the relabeling is then where A is a transformation (permutation) that maps old node indices to new node indices, and is to map the indices back. Since A and has the same parity property, is always an even permutation. Therefore, node relabeling has no impact of the parity of P, i. e., (sgn P).

180

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

then, that if the connection Therefore,

has L loops, the sign would have been

Lemma 8.2. The expression

in (4.4 can be evaluated topologically from the flow graph (4.3) by the formula

of the system of

where is the one-connection gain of the one-connection from node 1 to node of is the number of directed loops in the one-connection, and the summation on is over all one-connections of Proof. Let us first begin our proof by considering one let us evaluate

in particular; that is,

by assuming that there is only one branch with gain connecting the source node 1 to the rest of the graph. Note that is equal to the determinant obtained by replacing the column of by a column of zeros, except for the element of the row which is that is

This determinant will not change its value, if all the elements of the row, except are replaced by zero. The result is denoted by the determinant

Topological Analysis of Passive Networks

181

Thus,

Now let us investigate what effect the above operation has on the original graph Obviously, replacing the column of by a column of zeros means the deletion of all the outgoing branches from node replacing the row of by a row of zeros means the deletion of all the incoming branches to node of graph putting in the position means adding a branch from node to node with branch gain Let us call this modified graph Then, if graph is shown in Fig. 8.23, graph will be the graph depicted in Fig. 8.24.

Figure 8.23. Graph

of the proof of Lemma 8.1.

Figure 8.24. Graph

of the proof of Lemma 8.2.

Thus, on the basis of Lemma 8.1,

where is the connection gain of the connection of is the number of directed loops of the connection; and the summation is taken over all connections of

182

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

In order to interpret this result in terms of graph let us examine the graph as shown in Fig.8.24. Each one of the connections of includes the branch because it is the only branch leaving node In each one of these connections, let us disconnect branch at node and identify the “hanging” node of as node 1(as it was originally in graph Furthermore, let us change the branch gain from to Then, in each case, the resulting configuration causes any connection in equal to an one-connection from 1 to of Since, by definition, in each connection of there is no other incoming branch for or outgoing branch for besides Therefore, after the displacement, the “opened” directed loop becomes a forward path. Together with other directed loops in constitutes an one-connection. Plus, by displacing the branch one directed loop has been “opened”, the number of directed loops in the one-connection of is one less than that of the original connection of This will result in a change of sign, which will cancel the one caused by the change of sign of the branch gain Consequently,

It is evident that if there is more than one asserted by the lemma.

in the system, (4.12) will result, as

Theorem 8.7. In a system of linear algebraic equations with

The value of

unknowns,

is given by

where from 1 to

is the one-connection gain of the one-connection of is the number of directed loops in the one-connection, is the connection gain of the connection. is the number of directed loops in the connection. The summations are over all oneconnections of on and all connections of on Example 8.13. For a given linear system of 2 equations with 2 unknowns,

183

Topological Analysis of Passive Networks

we use the connections and one-connections given in Fig. 8.21 and Fig. 8.22, (4.14) becomes

On the other hand, using Cramer’s rule, gain

of (4.15) is given by

which is the same as the result from topological formulas in (4.16).

5.

Summary

In this chapter, we have presented topological analysis methods in two flavors: one is circuit-graph based, the other is flow-graph based. The common concept of the two methods is that, they both utilize graph theory to derive determinants and their cofactors topologically. The principal difference of them is that circuit-graph based method uses circuits themselves as graphs, while the flow-graph based method generates graphs from linear systems formulated from circuits. An evident advantage of topological analysis methods over matrix-based ones, is that the former intuitively provides the physical meaning of circuits analyzed/reduced. But a big disadvantage of the methods is their high time complexity. In the next chapter, we will introduce more efficient symbolic analysis method based on determinant decision diagrams.

This page intentionally left blank

Chapter 9 EXACT SYMBOLIC ANALYSIS USING DETERMINANT DECISION DIAGRAMS

In this chapter, we present a graph-based approach to exact symbolic analysis, which is capable of analyzing analog integrated circuits substantially larger than those previously handled.

1.

Combination Set Systems and Zero-Suppressed Binary Decision Diagrams

We first introduce combination set notation before we introduce the concept of determinant decision diagrams. Let V be a set of elements. The number of elements in V is called the cardinality of V, denoted by The set of all combination sets of V is called the power set of V, denoted by A combination set X of the power set, written as is called a combination set system of V. A combination set system X of V can be decomposed with respect to an element in V into two unique combination set systems, and where is the set of combination sets of V belonging to X that contain from which has been removed, and is the set of combination sets of V belonging to X that do not contain For instance, let Then we have and This decomposition can be represented graphically by a decision vertex. It is labeled by and represents the combination set system X. As illustrated in Fig. 9.1 (a), the vertex has two outgoing edges: one points to (called 1-edge), and the other to (called 0-edge ). We say that the edges are originated from the vertex. If X is recursively decomposed with respect to all the elements of V, one obtains a binary decision tree whose leaves are {{}} and {}, respectively. For convenience, we denote leaf {{}} by the 1-terminal, and {} by the 0-terminal.

186

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 9.1. (a) A ZBDD example, (b) An illustration of the zero-suppression rule.

When a combination set system X is decomposed with respect to an element that does not appear in X, then its 1-edge points to the 0-terminal. This is illustrated in Fig. 9.1(b) for decomposing with respect to To make the diagram compact, Minato suggested the following zerosuppression rule for representing sets of sparse combination sets: eliminate all the vertices whose 1-edges point to the 0-terminal vertex and use the subgraphs of the 0-edges, as shown in Fig. 9.1 (b) [61]. A Zero-suppressed Binary Decision

Exact Symbolic Analysis Using Determinant Decision Diagrams

187

Diagram (ZBDD) is such a zero-suppressed graph with the following two rules due to Bryant [4]: ordered—all elements of V, if one appears, will appear in a fixed order in all the paths of the graph, and shared—all equivalent subgraphs are shared. ZBDD is a canonical representation of a combination set system, i.e., every combination set system has a unique ZBDD representation under a given vertex ordering. For example, Fig. 9.1 (a) is a unique ZBDD representation for the combination set system with respect to ordering and For convenience, every non-terminal vertex is indexed by an integer number greater than those of its descendant vertices [61]. How all the non-terminal vertices are indexed is called vertex ordering. A path from a non-terminal vertex to the 1-terminal is called 1 -path. It defines a combination set of V. The combination set consists of all the elements of V from which the 1-edges in the 1-path originate. The number of vertices in a ZBDD is called its size.

2.

DDD Representation of Symbolic Matrix Determinant

In this section, we formally introduce the concept of determinant decision diagrams (DDDs) for representing matrix determinant. A DDD actually is a signed ZBDD. It has all the properties that a ZBDD has. The most significant is that DDDs lead to a canonical representation for matrix determinants, and are different from BDDs for representing binary functions and ZBDDs for representing combination set systems. DDDs exploit the fact that the circuit matrix is sparse, and many times, a symbolic expression may share many sub-expressions. For example, consider the following determinant

We note that subterms ad, gj, and hi appear in several product terms, and each product term involves a combination set (four) out of ten symbolic parameters. Therefore, we view each symbolic product term as a combination set, and use a ZBDD to represent the combination set system composed of all the combination sets each corresponding to a product term. Figure 9.2 illustrates the corresponding ZBDD representing all the combination sets involved in det(M) under ordering It can be seen that subterms ad, gj, and ih have been shared in the ZBDD representation. Following directly from the properties of ZBDDs, we have the following observations. First, given a fixed order of symbolic parameters, all the combination sets in a symbolic determinant can be represented uniquely by a ZBDD. Second, every 1-path in the ZBDD corresponds to a product term, and the num-

188

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 9.2. A ZBDD representing {adgi, adhi, a f ej, cbgj, cbih} under ordering

ber of 1-edges in any 1-path is The total number of 1-paths is equal to the number of product terms in a symbolic determinant. We can view the resulting ZBDD as a graphical representation of recursive application of determinant expansion formula (4.8) with the expansion order Each vertex is labeled with the matrix entry with respect to which the determinant is expanded, and it represents all the combination sets contained in the corresponding submatrix determinant. The 1-edge points to the vertex representing all the combination sets contained in the cofactor of the current expansion, and 0-edge points to the vertex representing all the combination sets contained in the remainder. To embed the signs of the product terms of a symbolic determinant into its corresponding ZBDD, we consider one step of matrix expansion with respect to as defined by (4.8). The sign is Note that and are, respectively, the row and column indices of the element in the submatrix before this step of expansion, say Let the absolute row and column indices of the element in the original matrix A before any expansion be and respectively. Then, we observe that is equal to the number of rows in with absolute indices less than plus the number of columns in with absolute indices less than We also note that all the rows and columns in except that of are represented in the subgraph rooted at the vertex

Exact Symbolic Analysis Using Determinant Decision Diagrams

189

pointed to by the 1-edge of vertex Therefore, the sign of a non-terminal vertex denoted by can be defined recursively as follows: 1. Let be the set of ZBDD vertices that originate the 1 -edges in any 1 -path rooted at Then

where and refer to the absolute row and column indices of vertex in the original matrix, and is an integer so that

2. If has an edge pointing to the 1-terminal vertex, then This is called the sign rule. For example, in Fig. 9.3, shown aside by each vertex are the row and column indices of that vertex in the original matrix, as well as the sign of that vertex obtained by using the sign rule above.

Figure 9.3. A signed ZBDD for representing symbolic terms.

For the sign rule, we have following result: Theorem 9.1. The sign of a DDD vertex is uniquely determined by (2.2), and the product of all the signs in a path is exactly the sign of the corresponding product term.

190

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Proof. We first consider one step of matrix expansion with respect to as defined by (4.8). The sign in the cofactor with respect to is Note that and are, respectively, the row and column indices of the element in the submatrix before this step of expansion, say Let the absolute row and column indices of the element in the original matrix A before any expansion be and respectively. Then, we observe that is equal to the number of rows in with absolute indices less than plus the number of columns in with absolute indices less than We also note that all the rows and columns in except that of are covered exactly once by any 1-path in the subgraph rooted at the vertex pointed to by the 1-edge of vertex This is because the subgraph, rooted at the DDD vertex corresponding to essentially represents i.e. all the product terms in Hence, is equal to the defined in equation (2.2) by selecting any 1-path in the subgraph rooted at As a result, the product of all the signs in a path is all the signs we will meet when we expand A by (4.8) to obtain the product term that the path corresponds to. For example, consider the 1-path acbgih in Figure 9.3. The vertices that originate all the 1-edges are their corresponding signs are –, +, – and +, respectively. Their product is +. This is the sign of the symbolic product term cbih. With ZBDD and the sign rule as two foundations, we are now ready to introduce formally our representation of a symbolic determinant. Let A be an sparse matrix with a set of distinct symbolic parameters where Each symbolic parameter is associated with a unique pair and which denote, respectively, the row index and column index of Definition 9.1. Formally, a determinant decision diagram is a signed, rooted, ordered, acyclic graph with two terminal vertices, namely the 0-terminal vertex and the 1-terminal vertex. Each non-terminal vertex is associated with a sign, determined by the sign rule defined by (2.2). It has two outgoing edges, called 1-edge and 0-edge, pointing, respectively, to and A determinant decision graph having root vertex denotes a matrix determinant D defined recursively as 1. If is the 1-terminal vertex, then D = 1. 2. If is the 0-terminal vertex, then D = 0. 3. If is a non-terminal vertex, then Here is the cofactor of D with respect to is the minor of D with respect to is the remainder of D with respect to and operations are algebraic multiplications and additions. For example, Figure 9.4 shows the DDD representation of det(M) under ordering

Exact Symbolic Analysis Using Determinant Decision Diagrams

191

Figure 9.4. A determinant decision diagram for matrix M.

To enforce the uniqueness and compactness of the DDD representation, the three rules of ZBDDs, namely, zero-suppression, ordered, and shared, described in section 1 are adopted. This leads to DDDs having the following properties: Every 1-path from the root corresponds to a product term in the fully expanded symbolic expression. It contains exactly 1-edges. The number of 1-paths is equal to the number of product terms. For any determinant D, there is a unique DDD representation under a given vertex ordering. We typically use to denote the size of a DDD, i.e., the number of vertices in the DDD.

3.

An Effective Vertex Ordering Heuristic

A key problem in many decision diagram applications is how to select a vertex ordering, since the size of the resulting decision diagram strongly depends on the chosen ordering. For example, if we choose vertex order for det(M) in Section 2, then the resulting DDD is shown in Fig. 9.5. It has 13 vertices, in comparison to 10 in Fig. 9.4, although they represent the same determinant. In this section, we describe an efficient heuristic for selecting a good vertex ordering, and show that it is optimal for a class of circuit matrices.

192

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 9.5. DDD representing det(M) under ordering

We propose to select the vertex ordering for a DDD by examining the structure of the original matrix. Suppose that A is an matrix with non-zero elements (entries, or symbols). The vertex ordering problem is how to label all the nonzero elements in A using integers 1 to so that the resulting DDD constructed with the chosen order has a small size. As stated in Section 1, those elements labeled by smaller integers will appear close to the leaves, or the bottom, of the DDD, and the root is labeled by We propose a vertex ordering heuristic, based on the refinement of a wellknown strategy for Laplace expansion of a sparse matrix [37]. The basic idea is to label those columns or rows with fewer nonzero elements with larger indices. Elements in those dense rows and columns will be labeled using small indices. Intuitively, this strategy increases the possibility of DDD subgraph sharing. Figure 9.6 describes the heuristic for labeling all the elements in matrix In the algorithm, denotes the matrix obtained from by removing row and column We keep a global counter Initially is set to 1, and As an example, consider how to apply MATRIX_GREEDY_LABELING to label the matrix M defined in Section 2. The complete process is illustrated in Fig. 9.7. First, columns 1 and 4 of M, as well as rows 1 and 4, have the least number of nonzero elements (2). We arbitrarily select column 1. Then the set of rows that have a nonzero element at column 1 are 1 and 2, i.e., Since

Exact Symbolic Analysis Using Determinant Decision Diagrams

193

Figure 9.6. A DDD vertex ordering heuristic.

Figure 9.7. An illustration of DDD vertex ordering heuristic.

row 1 has one nonzero element, and row 2 has two nonzero elements, lines 3-5 invoke first MATRIX_GREEDY_LABELING on matrix M after removing row 1 and column 1, then on matrix M after removing row 2 and column 1. The process is applied recursively on the resulting submatrices, and is illustrated in Fig. 9.7 from the top to the bottom. Then, elements are labeled in the Fig. 9.7 from the bottom to the top in the reverse order of expansion. These labels are marked in Fig. 9.7 at the top right corner of each element. If we summarize all the labels assigned to the matrix elements using the original matrix structure, we have

194

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

The heuristic leads to compact DDDs for a large class of circuit matrices, as observed in our experiments described in Section 7. In the rest of this section, we show that the heuristic is optimal for a class of circuit matrices, called band matrices. Band matrices are matrices that have only non-zero elements at positions and They have the following structure:

The number of non-zero elements in following result:

is

Then, we have the

Theorem 9.2. The DDD representation under the vertex ordering given by MATRIX_GREEDY_LABELING for a band matrix is optimal. Proof. We note that the lower bound on the number of DDD vertices is equal to the number of matrix entries, i.e., each vertex appears once in the final DDD. We will show that, for band matrices, the ordering given by M A TRIX_ GREEDY_ LABELING results in a DDD with the number of vertices equal to the number of nonzero matrix elements. This is proved by induction. It is easy to see that the result is true for 1 × 1 and 2 × 2 matrices. Now we assume that it is true for i.e., the number of DDD vertices is We prove that it is also true for the number of DDD vertices is Let vertex represent the DDD of and represent the DDD of Matrix has an extra row and column with three nonzero elements and Algorithm MATRIX_GREEDY_LABELING assigns integer labels and to elements and respectively. This gives ordering We thus first create a DDD vertex labeled by Its 1-edge points to vertex and its 0-edge points to next vertex, which corresponds to The 0-edge of vertex points to the 0-terminal. Its 1-edge points to the vertex that represents the determinant of matrix after removing the first column and the second row. Since the first row in the resulting matrix contains only one nonzero element we can create a DDD vertex for with its 1-edge pointing to and its 0-edge pointing to the 0-terminal. This is illustrated in Figure 9.8. Only three vertices are added for representing The total number of DDD vertices for is thus We have proved that for band matrix the number of DDD vertices is As a comparison, the number of expanded product terms in

Exact Symbolic Analysis Using Determinant Decision Diagrams

195

Figure 9.8. An illustration of DDD construction for band matrices.

is

where

is the

Fibonacci number defined by

Each product term involves symbols. To store all the product terms without considering sharing, the memory requirement is proportional to Further, any symbolic manipulation using the expended form would have time complexity at best proportional to In Fig. 9.9, the number of DDD vertices is plotted against the number of product terms. The practical relevance of band matrices is that they correspond to the circuit matrices for ladder networks—an important class of structures in analog design. A three-section ladder network is shown in Fig. 9.10. The system of equations can be formulated as follows:

If we view each entry as a distinct symbolic parameter, the resulting circuit matrix is a band matrix. We note that many practical circuits have the structure of ladders or close to ladders. We emphasize that just like the BDD representation for Boolean functions, in the worst case, the number of DDD vertices can grow exponentially with

196

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 9.9. A comparison of DDD sizes verse numbers of product terms for band matrices.

Figure 9.10. A three-section ladder network.

the size of a circuit. Nevertheless, as we have observed that with the proposed vertex ordering, the numbers of DDD vertices are manageable for practical analog circuits.

4.

Manipulation and Construction of DDD Graphs

In this section, we show that, using determinant decision diagrams, algorithms needed for symbolic analysis and its applications can be performed with the time complexity proportional to the size of the diagrams being manipulated, not the number of 1-paths in the diagrams, i.e., product terms in the symbolic expressions. Hence, as long as the determinants of interest can be represented by reasonably small graphs, our algorithms are quite efficient.

Exact Symbolic Analysis Using Determinant Decision Diagrams

197

A basic set of operations on matrix determinants is summarized in Table 9.1. Most operations are simple extensions of combination set operations introduced by Minato on ZBDDs [61]. These few basic operations can be used directly and/or combined to perform a wide variety of operations needed for symbolic analysis. In this section, we first describe these operations, and then use an example to illustrate the main ideas of these operations and how they can be applied to compute network function sensitivities—a key operation needed in optimization and testability analysis.

4.1

Implementation of Basic Operations

We illustrate these operations in Fig. 9.11. For the clarity of the description, the steps for computing the signs associated with DDD vertices, using the sign rule defined in section 2, are not shown. Fig. 9.11 illustrates the basic DDD graph operations summarized in the Table 9.1. As the basis of implementation, we employ two techniques originally developed by Brace, Rudell and Bryant for implementing efficiently decision diagrams [45]. First, a basic procedure is to generate (or copy) a vertex for a symbol top and two subgraphs and In the procedure, a hash table is used to keep each vertex unique, and vertex elimination and sharing are managed mainly by GETVERTEX. With GETVERTEX, all the operations for DDDs we need are described below.

198

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 9.11. Illustrations of DDD graph operations.

Exact Symbolic Analysis Using Determinant Decision Diagrams

199

Second, similar to conventional BDDs, we use a cache to remember the results of recent operations, and refer to the cache for every recursive call. In

200

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

this way, we can avoid duplicate executions for equivalent subgraphs. This enables us to execute these operations in a time that is linearly proportional to the size of a graph. Evaluation: Given a determinant decision diagram pointed to by D and a set of numerical values for all the symbolic parameters, EVALUATE(D) computes the numerical value of the corresponding matrix determinant. E VALUATE (D) naturally exploits sub-expression sharing in a symbolic expression, and has time complexity linear in the size of the diagram. Construction: Let be an symbolic matrix, where is a set of integers from 1 to constructs a determinant decision diagram of a submatrix of A with row set and column set such that for a given ordering of symbolic parameters. It can be viewed as a generalized Laplace expansion procedure of matrix determinants. In line 3 of the procedure DDD_OF_MATRIX, a non-zero element is selected, and the determinant is expanded. Due to the canonical property of DDD, can be any non-zero matrix element, and the resulting DDD is always the same. However, the best expansion order is the DDD vertex ordering. That is to use the element with the largest integer label in line 3 of the procedure DDD_OF_MATRIX. Cofactor and Derivative: is to compute the cofactor of a symbolic determinant D represented by a DDD with respect to symbolic parameter It is exactly the derivative of D with respect to COFACTOR is perhaps the most important operation in symbolic analysis of analog circuits. For example, the network functions can be obtained by first computing some cofactors, and then combining these cofactors according to some rules (Cramer’s rule).

4.2

Illustration of Basic Operations and its Use in Circuit Sensitivity

In this subsection, we use an example to show how the network function sensitivity can be computed using DDD-based COFACTOR. We also use COFACTOR to exemplify the main ideas of a typical DDD-based operation. Consider the ladder circuit shown in Fig. 9.10. Its system of equations has been formulated in (3.1). The input impedance is defined as

If each matrix entry is viewed as a distinct symbol, the determinant of the circuit matrix can be rewritten as (2.1). We redraw its DDD in Fig. 9.12(a), where the 0-terminal and all the 0-edges pointing to the 0-terminal are suppressed. In the figure, for each vertex labeled by a lower-case letter, we use the corresponding upper-case letter to denote the determinant represented by that vertex. The root

Exact Symbolic Analysis Using Determinant Decision Diagrams

201

of the DDD represents the determinant, denoted by A, of the circuit matrix. Note that and From Cramer’s rule,

Thus

We consider the normalized sensitivity of the input impedance to resistor

Note that

with respect

and

we have

The three cofactors

and in the expression above can be computed elegantly using algorithm COFACTOR in Table 9.1 on the DDD shown in Fig. 9.12(a). Recall that the vertex ordering in Fig. 9.12(a) is First, consider how to compute is returned.

Since points to D. Similarly, points to G. They are shown in Fig. 9.12(b). Next consider Since line 3 of the algorithm is executed with and i.e., Then the procedure is invoked recursively, respectively, for and This process is shown in Fig. 9.13, where top-down solid arrows illustrate the recursive invocation of the procedure COFACTOR, bottom-up dashed arrows show how the final result is synthesized, and each step is labeled by a number that indicates its order of execution. Note that returns the 0-terminal based on the zero-suppression rule. Eventually, returns Since no vertex exists with label the 0-edge pointing to 0, and the 1-edge pointing to will create such a new vertex, as shown in Fig. 9.12(b). In the process, C OFACTOR (0,d) is first calculated at steps 3 and 4. Later on at step 6, its return value has

202

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 9.12. DDD-based derivation of cofactors.

Figure 9.13. Illustration of DDD-based cofactoring.

Exact Symbolic Analysis Using Determinant Decision Diagrams

203

been cached and will be used directly. This avoids the duplicate execution of COFACTOR on the same subgraph. All three cofactors and the original determinant are compactly represented in a single four-root DDD shown in Fig. 9.12(b). From this DDD, the sumof-product expressions of cofactors and determinants can be generated efficiently by enumerating all its corresponding 1-paths. For this example, we have and The DDD representation enables efficient computation of exact sum-of-product symbolic expressions and their sensitivities. We can also generate the sequence-of-expression representations by introducing one intermediate symbolic symbol for each vertex. In comparison, sensitivity computation using directly the sequence-of-expressions approach requires grammar-driven compilation [54].

5.

DDD-based Exact Symbolic Analysis Flow

After all the important aspects of DDD graphs are presented, we now show the whole DDD-based exact symbolic analysis flow in Fig. 9.14 We start with the general nonlinear analog circuits. DC analysis is first performed using SPICE, and the resulting small-signal models from the outputs of SPICE are used in further symbolic analysis. Then modified nodal formulation is used to set up circuit equations for the symbolic analysis, which can be written as Since we perform the analysis in the frequency domain, the input independent current and voltage sources are mainly used for deriving the desired transfer functions. After the MNA equation is set up, each nonzero element will be assigned a unique index by using the proposed variable ordering algorithm in Section 3, which essentially is the Markowitz’s ordering algorithm when the circuit matrix is symmetric. After this, the DDD of the circuit matrix det(A) is constructed by Laplace expansion of matrix A. Also the minor caching technique is employed for speeding up the construction process. After the DDD representation of det(A) is obtained, the symbolic expressions like transfer functions are generated in terms of cofactors of det(A). All the cofactors of det(A) are obtained by the either Laplace expansion as we did for obtaining det(A) or by DDD Cofactor operations shown in Table 9.1 After symbolic expressions have been built, we can perform the numerical evaluation, symbolic pole/zero extraction, noise spectrum analysis. Also with the DDD representation, s-expanded DDD, which will be discussed in the next chapter, can be easily constructed. Symbolic approximation like dominant term generation [86], hierarchical model order reduction [83] can also be performed.

204

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 9.14. DDD-based exact symbolic analysis flow

6.

Related to Other Decision Diagram Concepts

The notion of DDDs comes from the application of ZBDDs to represent the sum-of-product symbolic expressions. Each vertex in the DDD represents a symbolic determinant and is defined by the determinant expansion and mul-

Exact Symbolic Analysis Using Determinant Decision Diagrams

205

tiplication in normal algebra. We note that in the area of formal verification of digital circuits, several algebraic forms of decision diagrams have been introduced; for example, Algebraic Decision Diagrams [3], Binary Moment Diagrams [6], Multi-Terminal Binary Decision Diagrams and Hybrid Decision Diagrams [13], and several others as described in the book edited by Sasao and Fujita [70]. Among them, DDDs are closely connected to BMDs. BMD provides a canonical representation for multivariate linear function. It is a variation of BDDs where the expansion rule is the following decomposition rule of function where terms (respectively, denotes the positive (respectively, negative) cofactor of with respect to i.e., the function resulting when constant 1 (respectively, 0) is substituted for Note that the determinants are multivariate linear functions in its entries. Recall the DDD expansion rule (4.8):

Here is the remainder of det(A), which is equal to i.e., the value of det(A) by substituting by 0. In other words, a DDD vertex pointed by 0-edge, which comes from vertex represents a determinant obtained by setting and is denoted as The corresponding portion of the DDD graph for one-step determinant expansion of Eq. (6.1) is shown in Fig. 9.15.

Figure 9.15. A determinant expansion and its DDD representation.

It can be verified that

Therefore, the DDD representation can be viewed as a special case of BMDs. However, the matrix determinants as a special form of multivariate linear functions have several special properties. For example, the sign can be determined nicely with the sign rule (Section 2) and be attached as part of a vertex,

206

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

where in BMDs, signs are encoded as edge weights. The BMDs’ objective is for formal verification of arithmetic digital circuits, where matrix operations such as multiplication are emphasized, whereas in our application, solving a system of symbolic equations is the objective and the representation and manipulation of symbolic determinants and cofactors are of primary interest. Nevertheless, rich techniques such as how to represent polynomials [62] and how to represent numeric coefficients using multi-terminals and attributed edges developed in the area of decision diagrams can be adapted to enhance the power of DDDs.

7.

Application to Symbolic Analysis of Analog Circuits

In this section, we show how the DDD graphs can be used to perform the exact symbolic analysis on some real analog circuits. Specifically, we look at cascodeOpamp circuit, which is a CMOS cascode opamp containing 22 transistors with the schematic in Fig. 9.19 and opamp circuit, which is a bipolar opamp containing 26 transistors and 11 resistors, with the schematic in Fig. 9.18. For the completeness, the small-signal models used for bipolar and MOS transistors are described in Figs. 9.16 and 9.17, respectively. The modified nodal analysis (MNA) approach is used to formulate the circuit equations. Exact symbolic expressions for network transfer functions (voltage gains) are computed using Cramer’s rule and shared DDD representations of symbolic determinants and cofactors. The transfer function is in the form of the ratio of two DDDs, which are represented compactly using a single shared DDD with two roots; this is referred to as the DDD representation of the transfer function.

Figure 9.16. The MOSFET small-signal model.

For CascodeOpam circuit, the vertices in the DDD representation of the transfer function without and with the use of the ordering heuristic described in Fig. 9.6 are 119395. For each circuit, the number of DDD vertices without ordering is the average of that of ten randomly generated orderings. For the CascodeOpam, the DDD size is 150868.1 without the vertex ordering. For

Exact Symbolic Analysis Using Determinant Decision Diagrams

207

Figure 9.17. The Bipolar transistor model.

Figure 9.18. The circuit schematic of bipolar

the different become more significant as the DDD size with vertex ordering is 119011 and no DDD graphs can be constructed without vertex ordering. So vetex ordering is critical for DDD constructions. One important application for symbolic analysis is to do what-if analysis to see how circuit characteristics change with circuit parameter values. Such what-if analysis can guide designers to quickly fix design problems and meet design specifications. The what-if analysis can be done very efficiently once symbolic expressions are generated as we can obtain the new responses by simply plugging in new parameter values and evaluating the symbolic expressions. As an example, we look at the frequency responses of circuit in Fig. 9.18. One important parameter of this circuit is the compensating capacitor COMP, which determines the unit-gain frequency of The nominal value of COMP is 30pf. If we sweep COMP value from 10pf to 60pf, we

208

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 9.19. The circuit schematic of MOS cascode Opamp.

obtain a host of waveforms as shown in Fig. 9.20, which clearly shows how COMP changes the unit-gain frequency of circuit. It is also shown in [77] that for ladder networks, the numbers of DDD vertices are exactly the numbers of non-zero matrix elements, which show the optimal representation of DDD graphs. DDD representations compare favorably with other symbolic analyzers like SCAPP [89], ISAAC [37] and Maple-V [10] for generating the complete sum-of-product expressions of the transfer functions.

8.

Summary

In this chapter, we have briefly reviewed the symbolic analysis techniques and pointed out the major challenge for symbolic analysis. We then presented a new graph representation, called determinant decision diagrams (DDDs), for symbolic matrix determinants and DDD-based symbolic analysis algorithms for analog circuits. Unlike previous approaches based on either the expanded form or the nested form representations of symbolic expressions, DDD-based symbolic analysis exploits the sparsity and sharing in a canonical manner. We described an efficient vertex ordering heuristic. We proved theoretically the heuristic yields an optimum ordering for ladder-structured circuits, and observed experimentally that for practical circuits, the numbers of DDD vertices are quite small—usually several orders of magnitude smaller than the number of product terms in the expanded form. In contrast to the existing nested form representations, the DDD representation is more amenable to efficient symbolic manipulation. As shown in this chapter and following chapters, symbolic analysis algorithms such as driving

Exact Symbolic Analysis Using Determinant Decision Diagrams

Figure 9.20.

209

frequency responses versus COMP values

cofactor computation, network function construction, sensitivity calculation, and generating significant terms, can be performed in time almost linear in the number of DDD vertices. Generating the complete sum-of-product symbolic expressions from the DDD representation offers orders of magnitude improvement in both CPU time and memory usages over symbolic analyzers ISAAC and Maple-V for large analog circuits. It enables the exact analysis of such large analog circuits as for the first time.

9.

Historical Notes on Symbolic Analysis Techniques

Research on symbolic analysis can be dated back to last century. Developments in this field gained real momentum in the 1950’s when electric computers were introduced and used in circuit analysis. Methods developed from the 1950’s to the 1980’s can be basically categorized as: (1) Tree Enumeration methods, (2) Signal Flow Graph methods, (3) Parameter Extraction methods, (4) Numerical Interpolation methods and (5) Matrix-Determinant methods. The details of these method can be found in [38, 53]. In the late 1980’s, symbolic

210

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

analysis gains renewed interests as industrial demands for analog design automation increased. Despite of its advantages, symbolic analysis had not been mainstream analysis tools by analog designers. The root of the difficulty is apparently: the number of product terms in a symbolic expression may increase exponentially with the size of a circuit. For example, for a BiCMOS amplifier that has about 15 node and 25 devices (transistors, diodes, resistors and capacitors), the determinant of the matrix contains more than product terms [99]. Any manipulation and evaluation of sum-of-product-based symbolic expressions will require CPU time at best linear in the number of terms, and therefore have both the time and space complexities exponential in the size of a circuit. To cope with large analog circuits, modern symbolic Analyzers 1 rely on two techniques—hierarchical decomposition and symbolic simplification— developed mainly in the past decade. Hierarchical decomposition is to generate symbolic expressions in the nested instead of expanded form [40,41,81]. Symbolic simplification is to discard those insignificant terms based on the relative magnitudes of symbolic parameters and the frequency defined at some nominal design points or over some ranges. It can be performed before/during the generation of symbolic terms [8, 42, 73, 107] or after the generation [27, 37, 98]. Exploitation of these techniques has enabled the use of symbolic simulators in several university research projects [7, 28, 37, 105]. However, both techniques have some major deficiencies. Manipulation (other than evaluation) of a nested expression usually requires complicated and time-consuming procedures; e.g., sensitivity calculation in [54] and lazy approximation in [73]. On the other hand, simplified expressions only have a sufficient accuracy at some points or frequency ranges. Even worse, simplification often loses certain information, such as sensitivity with respect to parasitics, which is crucial for circuit optimization and testability analysis.

1 Some are surveyed in a paper by F. V. Fernández and A. Rodríguez-Vázquez [28].

Chapter 10 S-EXPANDED DETERMINANT DECISION DIAGRAMS FOR SYMBOLIC ANALYSIS

In Chapter 9, we have introduced determinant decision diagrams for representing all those determinants and cofactors. In this chapter, we introduce the concept of s-expanded determinant decision diagrams for symbolically representing s-expanded polynomials from a determinant.

1.

Introduction

For many symbolic analysis applications, however, such a representation is still inadequate. These applications commonly require symbolic expressions to be represented in the so-called fully expanded form in or in the s-expanded form. For an circuit matrix with its entries being the linear function in the complex frequency its determinant, can be written into an s-expanded polynomial of degree

As a result, the same linear(ized) circuit transfer function in the s-expanded form in Eq.(1.2).

can be written

where and are symbolic polynomials that do not contain the complex variable Despite the usefulness of s-expanded symbolic expressions, no efficient derivation method exists. The difficulty is still rooted in the huge number of s-expanded product terms that are far beyond the capabilities of symbolic analyzers using traditional methods. Although the numerical interpolation method [96] can generate s-expanded expressions,

212

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

only complex frequency is kept as a symbol. This method also suffers the numerical problem due to the ill-conditioned equations for solving for numerical coefficients, and thus has limited applications. Various simplification schemes can be used to find approximate symbolic expressions [28, 38]; yet it is well known that approximate expressions may not be adequate for such circuit characterizations as symbolic pole-zero derivations [38]. Arbitrarily nested hierarchical expressions or sequences of expressions can be useful for circuit simulation [41], but no method exists to derive the s-expanded expressions from these representations. It turns out that s-expanded polynomial expressions can be easily computed using determinant decision diagrams and the related graph-based operations. The key idea still lies in the exploration of the DDD structure. The result is a slightly different DDD, called an s-expanded determinant decision diagram (s-expanded DDD), where each root represents a symbolic coefficient of a particular power of s-Expanded DDDs share all the properties of DDDs, but greatly extend the capabilities of DDDs in representing symbolic expressions. We present an efficient algorithm of constructing an s-expanded DDD from an original DDD. If the maximum number of admittance parameters in an entry of a circuit matrix is bounded (true for most practical analog circuits), we prove that both the size of the resulting s-expanded DDD and the time complexity of the construction algorithm is where is the highest power of in the s-expanded polynomial of the determinant of the circuit matrix and is the size of the original DDD D representing the determinant. Experimental results indicate that the number of DDD vertices used can be many orders-ofmagnitudes less than that of product terms represented by the DDDs. With s-expanded expressions, approximation on symbolic transfer functions can be performed very efficiently (see Chapter 11) by finding shortest paths or by the dynamic programming based method. In addition, symbolic poles and zeros can also be approximated using the pole-splitting method [31] (also see Chapter 11). With some or all circuit parameters substituted with numerical values, frequency response calculation using s-expanded representation can be performed much faster than SPICE-like methods [53]. In the sequel, we will first present DDD (sDDD) graph concept for deriving s-expanded polynomials in Sections 1 and how to efficiently construct sDDD from complex DDD graphs in Section 2 and Section 3.

2.

s-Expanded Symbolic Representations

In this section, we introduce the concept of s-expanded determinant decision diagrams. Instead of presenting the concept in a formal way, we illustrate it through a circuit example.

s-expanded Determinant Decision Diagrams For Symbolic Analysis

213

Figure 10.1. An example circuit

Consider a simple circuit given in Figure 10.1. By using the nodal formulation, its circuit matrix can be written as

In modified nodal analysis formulation, the admittance of each circuit or lumped circuit parameter, arrives in the circuit matrix in one of three and the admittance of resistances and capacitances and inductances, respectively. To construct DDDs, we need to associate a label with each entry of a circuit matrix. We call this procedure labeling scheme. Instead of labeling one symbol for each matrix entry, we label each admittance parameter in the entries of the circuit matrix when deriving the s-expanded DDDs. Specifically, we label each admittance element of circuit parameters by a unique symbol. By using the labeling scheme, we can rewrite the circuit matrix of the circuit matrix can be rewritten as follows:

where We first consider the original DDD representation shown in Figure 10.2 of the circuit matrix. Each DDD vertex is labeled using the first labeling scheme. By the definition of DDDs, each 1-path in a DDD corresponds to a product term in the determinant that the DDD represents. In this example, there are three 1-paths, and thus three product terms:

214

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 10.2. A complex DDD for a matrix determinant

We now consider how to expand a symbolic expression into an s-expanded one and represent the expanded product terms by a new DDD structure. Expanding the three product terms, the same three product terms in the complex DDD of the example circuit will be expanded into 23 product terms in different powers of

The resulting s-expanded DDD is depicted in Figure 10.3 We can easily represent these product terms using a multi-rooted DDD structure as shown in Figure 10.3. The new DDD has four roots and each DDD root represents a symbolic expression of a coefficient of a particular power of Each DDD seen from a root is called a coefficient DDD, and the resulting multi-rooted DDD is called an s-expanded DDD. The original DDD is referred to as the com-

s-expanded Determinant Decision Diagrams For Symbolic Analysis

215

plex DDD as complex frequency variable appears in some vertices throughout the rest of the dissertation. Such a representation exploits the sharing among different coefficients in a polynomial in addition to that explored by complex DDDs. In Figure 10.3, 18 non-terminal vertices are used. In comparison, without exploiting the sharing and the sparsity, 108 (= 12 × 9, #product-terms × #symbols) vertices would be used. The s-expanded DDD will be more suited for the DDD-based approximation to be presented in Chapter 11. Note that each vertex in a complex DDD may be mapped into several vertices, in the resulting s-expanded DDD. We say that a contains and denote this relationship by As a result, a product term, in a complex DDD will generate a number of product terms, in the resulting s-expanded DDD. Similarly, we say contains and denotes this relationship by If we further define the row and the column indices of a vertex in a coefficient DDD as that of respectively, we have the following result: Theorem 10.1. A coefficient DDD represents the sum of all s-expanded product terms of particular power of in the s-expanded polynomial of a determinant. Proof. We note that for a vertex in a coefficient DDD, there is one and only one vertex in the complex DDD such that Because vertex has the same row and column indices as so has the same sign as using the sign rule defined in Section 1. Hence the sign of each product term in a coefficient DDD will be identical to that of product term where Hence all the product terms have the same sign as This agrees with the arithmetic operation of transforming an expression in a product-of-sum form into the one in a sum-of-product form. Theorem 10.1 implies that an s-expanded DDD shares the same properties as a complex DDD, although it does not represent a determinant, instead only those terms that have the same powers of in a determinant. All the manipulations of complex DDDs mentioned in the Section 2 therefore can be applied to sexpanded DDDs. Under a fixed vertex ordering of all vertices representing admittance parameter in a circuit matrix, the representation of the circuit-matrix determinant by an s-expanded DDD is also canonical. The canonical property in an s-expanded DDD ensures that the maximum sharing among all its coefficients is attained, and the size of the resulting s-expanded DDD is a minimum under a vertex ordering.

3.

Vertex Ordering for s-Expanded DDDs

Vertex ordering in determinant decision diagrams crucially determines the size of the resulting DDDs. We therefore need to find a good vertex ordering for an s-expanded DDD as to minimize its size.

216

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 10.3. An s-expanded DDD by using the labeling scheme

Because an s-expanded DDD is derived from an existing complex DDD, we can take the advantage of the vertex ordering, found by the heuristic described in Section 2, in the complex DDD. We will show in Section 4 that the new vertexordering scheme is also vital to the efficient s-expanded-DDD construction algorithm. Let and are two vertices in an s-expanded DDD; and are two vertices in the corresponding complex DDD such that and Let denote the label of vertex in a complex DDD and denote the label of vertex in an s-expanded DDD. The basic idea is to order the vertices such that if then Such an ordering scheme will ensure that the sharing in a complex DDD is still explored in the resulting s-expanded DDD. The relative order of the vertices contained by one complex DDD vertex can be arbitrarily selected since it makes no impact on the size of the resulting s-expanded DDDs as shown in Section 4. In particular, we use a simple mapping function to compute the label of a vertex in an s-expanded DDD from the label of its containing vertex. We consider an admittance parameter to be represented by a vertex, in an sexpanded DDD and its containing vertex

s-expanded Determinant Decision Diagrams For Symbolic Analysis

217

The mapping function is defined as

where is the maximum number of circuit admittance parameters in a complex DDD vertex. Function gives the unique index of in and Similarly, from the label of a vertex in an s-expanded DDD, one can easily compute the label of its containing vertex and its unique index in its containing vertex. The s-expanded DDDs in Figure 10.3 and are constructed using and respectively. In the following section, we show that with the new vertexordering scheme the size of the resulting s-expanded DDD constructed from a complex DDD is only proportional to the size of the complex DDD, the highest power of in the s-expanded expression and

4. Construction of s-Expanded DDDs 4.1 The Construction Algorithm An s-expanded DDD can be constructed from a complex DDD by one depthfirst search of the complex DDD. The procedure is very efficient with the time complexity linear in the number of the resulting s-expanded DDD. In the second labeling scheme, we use to represent the admittance parameter in a complex DDD vertex D. can be a resistive admittance, a capacitive admittance or an inductive admittance. The function will return res, cap and ind for the three admittance types, respectively. The COEFFCONST is expressed in Figure 4.1. An s-expanded DDD, P, is list of coefficient DDDs with denoting the coefficient DDD of power and Then, we introduce the following four basic operations: computes the union of two s-expanded DDDs, and

computes the product of s-expanded DDD P and coefficient DDD vertex increments the power of in s-expanded DDD P. decrements the powers of in s-expanded DDD P. Algorithm COEFFCONST described in Figure 4.1 takes a complex DDD vertex and creates its corresponding coefficient DDDs. The implementations of COEFFUNION and COEFFMULPLTY are also shown in Figure 10.4 in terms of the basic DDD operations MULTIPLY and UNION, whose implementations can be found in the Subsection 4.1 in Section 2. As in all other DDD operations [76], we cache the result of COEFFCONST(D), and in case D is encountered again, and its result will be used directly.

218

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 10.4. The s-expanded DDD construction with the second labeling scheme

Figure 10.5. The basic s-expanded DDD construction algorithms

4.2

Time and Space Complexity Analysis

Consider a circuit matrix. A complex DDD with its size denoted by is used to represent the determinant of the circuit matrix. Let be the size of the determinant represents. The maximum number of the circuit admittance parameters in an entry of a circuit matrix is Then, we have the following result for the s-expanded DDD derived from by COEFFCONST for both labeling schemes:

Theorem 10.2. The time complexity of vertices (size) of the resulting s-expanded DDD are

and the number of

Proof. Function performs a depth-first search on so it will visit each DDD vertex just once, and COEFFCONST will be called just times.

s-expanded Determinant Decision Diagrams For Symbolic Analysis

219

At each vertex D in the complex DDD, we visit all the admittance parameters according to their unique indices (from the smallest one to the largest one). For each admittance parameter COEFFCONST calls COEFFMULPLTY no more than once and COEFFUNION just once. In function COEFFMULPLTY, we claim that the DDD operation MULTIPLY can complete in a constant time, where To see this, we note that is always larger than the labels of any coefficient DDD vertices in as the labels of all the coefficient DDD vertices in are mapped from the complex DDDs whose labels are less than L(D) according to the new vertex-ordering scheme. So the resulting coefficient DDD from can be readily constructed in a constant time as shown in Figure 10.6. Hence function COEFFMULPLTY takes to finish for no more than coefficient DDDs.

Figure 10.6.

operation

In the function COEFFUNION, we first consider its uses in steps 9, 12 and 15 in Figure 4.1. DDD operation in COEFFUNION will also take a constant time to complete, where and are two coefficient DDDs. To see this, we take a close look at how and are constructed. We note that is the result of a operation where is the root vertex in where if is an admittance of resistance; if is an admittance of capacitance and if is an admittance of inductance. We also observe that is the result of the previous operation. Because is always larger than where is the admittance visited before in D. So will be larger than the labels of all the vertices in As a result, the resulting coefficient DDD from can be readily constructed in a constant time as shown in Figure 10.7 for all admittance types. So function COEFFUNION also takes to finish for no more than coefficient DDDs.

220

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 10.7.

operation

Both COEFFMULPLTY and COEFFUNION will be called at most times for each admittance parameter. So it will take to finish all the tasks before the last COEFFUNION call. Finally we consider the calls of at line 16 in Figure 4.1. We claim that this operation also takes to complete. This is can be verified by observing that the coefficient DDD of from the result of the last COEFFUNION operation consists of four types of coefficient DDDs: The coefficient DDD from the multiplication of an admittance of resistance— and The coefficient DDD from the multiplication of an admittance of capacitance— and The coefficient DDD from the multiplication of an admittance of inductance— and

s-expanded Determinant Decision Diagrams For Symbolic Analysis

221

The final coefficient of from the last COEFFUNION operation is the UNION of all the coefficient DDDs of the four types. Note that the UNION of the coefficient DDDs of the first three types is actually in the operation. As a result, the 0-edge of the vertex, in which has the smallest label among all the admittance parameters in D, must point to 0-terminal because is the first admittance parameter visited in D, and in fact is 0-terminal when operation is carried out for With this, the UNION operations in the last COEFFUNION operation can be readily performed by redirecting the 0-edge of to Such an operation also takes a constant time. In summary, the total time complexity and also the final size of the s-expanded DDD is To conclude this section, we make the following observations: 1 From the previous analysis, one can easily see that a tighter bound of time complexity of function COEFFCONST is the final size of the resulting sexpanded DDD. In addition, in the function COEFFMULPLTY and COEFFUNION, we only need to visit all the nonzero coefficient DDDs. So a more precise size bound of the resulting s-expanded DDD should be where is the highest power of in the s-expanded polynomial of the determinant which represents. 2 For a practical analog circuits, actually is bounded by a constant and is independent of the size of the circuit.

Considering all the observations, we have the following conclusion: Corollary 10.1. Let be the highest power of in the s-expanded polynomial of the determinant of a circuit matrix. If the maximum number of the admittance parameters in each entry of the matrix is bounded by a constant, the time complexity of and the size of the resulting s-expanded DDD is

5.

Applications of Deriving Transfer Functions

In this section, we show some experimental results for some analog circuits. Specifically, we illustrate how to construct the s-expanded polynomials in the transfer function of a bipolar opamp circuit, shown in Fig. 9.18. Still, the small-signal models used for bipolar and MOS transistors are described in Figs. 9.16 and 9.17, respectively. We observe that for large circuits, product terms grow dramatically with the size of a circuit for both complex DDDs and DDDs, while the DDD sizes grow modestly. So expanding complex products terms into an polynomial can lead to an exponential number of product terms. For example, the denominator of the transfer function for has 108032

222

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

complex product terms. Expansion of these terms leads to product terms. This is shown in Fig. 10.8 with the distribution of the number of product terms over the power of for the denominator of the transfer function under full symbolic representation.

Figure 10.8. Product term distribution of

by the second labeling scheme.

Despite rapid growth of product terms, the sizes of DDDs and the CPU time in constructing these DDDs grow very modestly. For the transfer function with product terms in the numerator and product terms in the denominator can be compactly represented by a DDD with only 99846 vertices. Even if for full symbol representation, where the number of product terms grows by 9 orders of magnitude, the number of DDD vertices increases only to 297117 (about 3 times of 99846). The construction of DDDs takes only a few CPU seconds on a Ultra-SPARC-I workstation. This demonstrates the superior expressive power of DDDs and the efficiency of based algorithms for symbolic analysis. Figure 10.9 shows that the actual size of an DDD is clearly bounded by where under the MNA formulation on various analog circuits, and is the size of a complex DDD. It also supports the theoretical claim in Theorem 10.2.

6.

Summary

In this chapter, we have shown how to derive network functions for small-signal characterization of analog integrated circuits based on multi-

s-expanded Determinant Decision Diagrams For Symbolic Analysis

Figure 10.9. Sizes of

223

DDDs vs sizes of the complex DDDs.

root determinant decision diagrams (DDDs). Experimental results have shown that the exact symbolic transfer functions for analog integrated circuits such as operational amplifiers can be generated in a few CPU seconds on modern computer workstations. The expressive power of multi-root DDDs is so remarkable that, for the first time, over product terms have been successfully represented by a multi-root DDD with less than 0.2M vertices. Such a representation compactness is achieved by exploring the expression sharing among both the numerator and the denominator coefficients of symbolic network functions. It is made possible by a vertex ordering heuristic and an implicit construction algorithm for DDDs developed in this paper. We proved theoretically, as well as validated experimentally, both the space and time complexities of multi-root DDDs. We demonstrated the advantages of applying DDDs to frequency-domain simulation.

This page intentionally left blank

Chapter 11 DDD BASED APPROXIMATION FOR ANALOG BEHAVIORAL MODELING

In this chapter, we present several efficient algorithms for obtaining approximate symbolic expressions based on DDD presentations of symbolic expressions. We show that a dominant term of a determinant can be found by searching shortest paths in the DDD graphs. An incremental shortest paths search scheme has been developed, which can efficiently find dominant product terms from DDD graphs presenting a determinant.

1.

Introduction

One of the challenging problems in analog design is that analog circuits typically have many characteristics, and they depend in a very complicated way on circuit, layout process and environment parameters. In this chapter, we consider the problem of generating simple yet accurate symbolic representation of circuit transfer function and characteristics in terms of circuit parameters for linear(ized) analog integrated circuits. It is well known that circuit transfer function and characteristics are dominated by a small number of product terms called significant or dominant. For instance, Fig. 11.1 shows a CMOS two-stage opamp circuit. The simplified MOS small-signal model is shown in Fig. 9.16. If we ignore and (as they are typically small compared to other parameters) in the MOS model and treat the as an ideal current source and as a resistor, the exact transfer function from input to is shunted to ground), as shown in Appendix 8, contains 16 product terms in the numerator and 60 terms in the denominator. We can see that each coefficient expression of is dominated by a few product terms. For example, for the coefficient of in the denominator, the first product term amounts to 86% of the total magnitude of the coefficient and the first two terms amount to 97% of the total magnitude. If these errors are acceptable, the re-

226

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

maining terms can be neglected. With 5% error, the transfer function can be simplified as shown in Eq. (1.1).

Figure 11.1. A simplified two-stage CMOS opamp.

In this chapter, we present efficient algorithms of generating dominant terms for deriving interpretable symbolic expressions based on a compact DDD representation of circuit transfer functions [77,78]. We show that dominant term generation can be performed elegantly by DDD graph manipulations. Since we start with the exact symbolic expressions in DDD representations, the approximation methods feature both the reliability in the approximation-after-generation methods and the capability in approximation-before/during-generation for analyzing large analog circuits. Experimental results show that the DDD-based algorithms outperform the dynamic programming based dominant term generation method reported [86, 93, 95].

2.

Symbolic Cancellation and De-cancellation

Before we generate the dominant terms, one problem we need to consider is symbolic cancellation. Symbolic canceling terms arise from the use of the MNA formulation in analog circuits. For instance, consider the s-expanded DDD in Fig. 10.3. Since and term cancels term in the coefficient DDD of Our experiments show that 70-90%

DDD Based Approximation for Analog Behavioral Modeling

227

terms are canceling terms. Clearly it is inefficient to generate the 70%-90% terms that will not show up in the final expressions. It will be shown in Chpater 12 that fundamentally symbolic cancellation is caused by the submatrix reduction or variable/node reduction. MNA formulation is obtained by reducing all the branch current and branch voltage variables from the sparse tableau formulation, which is cancellation-free [96]. Such a reduction will lead to the symbolic cancellation [82]. More detailed treatment of this issue will be covered in Chpater 12. In this chapter, we only focus on the symbolic term cancellation, where the sum of two symbolic terms is zero (cancels), in the MNA formulation. Symbolic canceling terms can be detected by considering several MNA matrix patterns shown in Fig. 11.2,

Figure 11.2. Matrix patterns causing term cancellation.

where matrix element and can be stamped from device resistor and capacitor respectively in MNA formulation. Notice that case 1 may come from the rectangular stamps of a floating resistor in the nodal admittance formulation (in this case, and and case 2 may come from stamps of a voltage controlled current source. Canceling terms can be removed more efficiently during the construction of DDDs from original complex DDDs [78]. To build cancellationfree DDDs from DDDs, we build a canceling label list for each label such that With this, we first loop through all the devices and build the CL for each unique symbol. Then we call function COEFFCONST to construct the DDDs. The pseudo code for cancellation-free C OEFFM ULTIPLY in C OEFFC ONST is shown in Fig. 11.3, where lines 2 to 3 are used not to generate canceling terms. For this example the resulting cancellation-free DDD shown in Fig. 11.4 is smaller than the original DDD in Fig. 10.3. Our experimental results, however, show that the cancellation-free DDDs can be larger than the normal DDDs [90].

228

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 11.3. Cancellation-free COEFFMULTIPLY.

Figure 11.4. Cancellation-free multi-root DDD.

3.

Dynamic Programming based Generation of Dominant Terms

In this section, we present a dynamic programming (DP) based algorithm for generating dominant terms using DDDs. The original idea of using dynamic programming was proposed by Verhaegen and Gielen [93, 95], but was implemented based on non-canonical DDD graphs with node duplication. Our implementation is based on canonical DDD graphs without dynamic removal of canceling terms, and therefore is faster than the one in [93, 95]. To derive the DP algorithm, we characterize here some theoretical properties of DDDs. First, we note that the vertex ordering heuristic used to construct DDDs is based on Laplace expansion of a circuit matrix along the row or column [77]. We also know from the canonical property of DDD that the

DDD Based Approximation for Analog Behavioral Modeling

229

structure of a DDD is unique under a fixed vertex order, i.e., independent of how it is constructed. We thus have the following lemma. Lemma 11.1. All 0-edge linked vertices come from either the same row or the same column of the original circuit matrix. The proof of the lemma can be found in [86]. With Lemma 11.1 as the basis, we can show the following main result. Theorem 11.1. The incoming edges of a non-terminal vertex in a complex DDD or native DDD are either all 0-edges or all 1-edges. The proof of the lemma can be found in [86]. Theory 11.1 is important for the DP-based dominant term generation algorithm shown below. It also holds for native DDDs by noticing that 0-edges between DDD vertices may also represent the relationship among the different symbolic circuit parameters in a non-zero element in a determinant. Native here means that the DDDs are obtained from complex DDDs without any structure modification. Now we are ready to describe a DDD-based DP algorithm for generating dominant terms. From Lemma 11.1 and Theorem 11.1, we know that we only need to calculate dominant terms for 1-edge pointed DDD vertices as 1-edge represent multiplication relationship among two DDD vertices. The fundamental idea of the DP-based dominant term generation algorithm is based on the fact that we can generate the partial dominant terms seen at each 1-edge pointed vertex and the partial dominant terms consist of the partial dominant terms from the downstream vertices seen from the vertex. In this way we can generate the dominant terms when the vertex is the root of the whole DDD tree in a recursive way. Let D be a 1-edge pointed vertex. We use D. counter to keep track of the number of dominant terms generated for the vertex D (D is included in the terms). We use an ordered array, denoted as D. term-list, to keep track of those generated dominant terms in the minor represented by D, where D.term-list[1], D.term-list[2],... represents the largest term (first dominant term), the second largest term (second dominant term). D. counter is initially set to 1 for all 1-edge pointed vertices, and can be increased up to As shown in pseudo code in Fig. 11.5, to find the dominant terms at a 1 -edge pointed vertex D, we first check if such terms already exist in the term-list in GETKDOMITERMS (D, If they do not exist, they will be generated by invoking COMPUTEKDOMINANTTERM(D, In COMPUTEKDOMINANTTERM(D, the largest term is computed and stored in the term-list of D by visiting all the 0-edge linked DDD vertices. Each time a dominant term is computed, the corresponding vertex V.counter will be increased by 1. UPDATETERM() adds a vertex (its symbol) into a term represented by a DDD tree. COMPUTETERMVALUE() computes the numerical value of a given term. We

230

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 11.5. Dynamic programming based dominant term generation.

algorithm.

use V.child1 to represent the vertex pointed to by the 1-edge originating from vertex V. Let be the number of vertices in a path from 1-terminal to the root vertex, i.e. the depth of the DDD graph. Let each circuit node be connected by at most devices. Then each matrix entry can be a sum of at most individual elements. The algorithm takes linear time in terms of the size of a DDD, if UPDATETERM() and COMPUTETERMVALUE() are implemented to use constant time each time when a vertex is added to a term. This can be accomplished by using memory caching. After obtaining the first dominant term, the next dominant can be found in time assuming the UPDATETERM() and COMPUTETERMVALUE() take constant time and the number of 0-edge linked vertices is bounded by and (due to line 04 in Fig. 11.5).

DDD Based Approximation for Analog Behavioral Modeling

231

But depends on the circuit topologies and may become comparable to for some strongly connected circuit structures and the time complexity of the DP algorithm will become in this case. We note that cancellation-free DDDs do not satisfy Theorem 11.1. For example, Fig. 11.4 shows the cancellation-free DDD of the DDD in Fig. 10.3, vertex in the coefficient of has both incoming 1-edge and incoming 0-edge. Verhaegen and Gielen [93, 95] resolved this problem by duplicating vertex Their approach, however, would destroy the DDD canonical property, a property that enables many efficient DDD-based graph manipulations. In this paper, we apply the proposed DP based term generation approach on the DDDs before de-cancellation.

Figure 11.6. Implementation of SUBTRACT() for symbolic analysis and applications.

4.

Incremental k-Shortest Path Algorithm

In this section, we present an efficient algorithm for finding dominant terms in [90]. The algorithm does not require DDDs to be native or to satisfy aforementioned graph theoretical property (Theorem 11.1), and thus can be applicable to any DDD graph. The SP algorithm is based on the observation that the most significant term in coefficient DDDs can be transformed into the shortest path in edge-weighted DDD graphs by introducing the following edge weight in a DDD: 0-edge costs 0 1-edge costs and denotes the numerical value of the DDD vertex that originates the corresponding 1-edge. The weight of a path in a coefficient DDD is defined to be the total weights of the edges along the path from the root to the 1-terminal. As a result, given a path, say abcdef, their path weight is

232

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

If is the value of the largest term, value of will be the smallest, which actually is (4.1). The shortest (weighted) path in a coefficient DDD, which is a DAG (direct acyclic graph), can be found by depth-first search in time O(V + E), where V is the number of DDD vertices and E is number of edges [17]. So it is O(V) in DDDs. Once we find the shortest path from a DDD, we can subtract it from the DDD using SUBTRACT() operation [77], and then we can find the next shortest path in the resulting DDD. But instead of applying the shortest path search algorithm to the DDD graph directly, which requires to visit every vertex in a DDD graph to find the dominant term as required by the shortest path search algorithm [17] after every vertex has been visited once (i.e. after the first dominant term is found). The the new algorithm is based on the observation that not all the vertices are needed to be visited, after the DDD graph is modified due to the subtraction of a dominant term from the graph. We show that only the newly added DDD vertices are needed to be relaxed and the number of newly added DDD vertices is bounded by the depth of a DDD graph. In the sequel, we first introduce the concept of reverse DDD graphs. As shown in Fig. 10.2, a DDD graph is a direct graph with two terminal vertices and one root vertex. Remember that the 1-path in a DDD graph is defined from the root vertex to the 1-terminal. Now we define a new type of DDD graphs, called reverse DDD graphs where all the edges have their directions reversed and the root of the new graph are 1-terminal and 0-terminal vertices and new terminal vertex becomes the root vertex of the original DDD graph. The reverse DDD graph for the DDD graph in Fig. 10.2 is shown in Fig. 11.7. For the clarification, the root vertex and terminal vertices are still referred to as those in the original DDD graphs. With the concept of the reverse DDD graph, we further define 1 -path and path weight in a reverse DDD graph. Definition 11.1. A 1-path in a reverse DDD is defined as a path from the 1terminal to root vertex (A in our example) including all symbolic symbols and signs of the vertices that the 1-edges point to along the 1-path. Definition 11.2. The weight of a path in a DDD is defined to be the total weights of the edges along the path where each 0-edge costs 0 and each 1-edge costs and denotes the numerical value of the DDD vertex that the corresponding 1-edge points to. We then have the following result. Lemma 11.2. The most significant product (dominant) term in a symbolic determinant D corresponds to the minimum cost (shortest) path in the corresponding reverse DDD between the 1-terminal and the root vertex.

DDD Based Approximation for Analog Behavioral Modeling

233

Figure 11.7. A reverse DDD.

The shortest path in a reverse DDD, which is still a DAG and thus, can be found in time as the normal DDD graph does. Following the same strategy in [90], after we find the shortest path from a DDD, we can subtract it from the DDD using SUBTRACT() DDD operation, and then we can find the next shortest path in the resulting DDD. We have the following result: Lemma 11.3. In a reverse DDD graph, after all the vertices have been visited (after finding the first shortest path), the next shortest path can be found by only visiting newly added vertices created by the subtraction operation. Proof: The proof of Lemma 11.3 lies in the canonical nature of DDD graphs. A new DDD vertex is generated if and only if the subgraph rooted at the new vertex is a new and unique subgraph for the existing DDD graph. In other words, there do not exist two identical subgraphs in a DDD graph due to the canonical nature of DDD graphs. On the other hand, if an existing DDD vertex becomes part of the new DDD graph, its corresponding subgraphs will remain the same. As a result, the shortest path from 1-terminal to all vertices in the subgraph will remain the same. Hence, it is sufficient to visit the newly added vertices to find the shortest paths from 1-terminal to those vertices. The root vertex of the new DDD graph is one of those newly added vertices. Fig. 11.8 illustrates the incremental k-shortest path algorithm. The figure in the left-hand side shows consecutive k-shortest path algorithm to find the shortest path. Every time when a new DDD graph is created which is rooted at we have to visit the whole graph to find the shortest path. The figure shown in the right-hand side is the new incremental k-shortest path algorithm

234

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

where we only need to visit all the newly created DDD nodes (in the upper left triangle) to be able to find the shortest path. As shortest paths are found from the source to all the nodes in a graph, the shortest paths, shown in dashed lines, in the existing subgraphs can be reused in the new DDD graph.

Figure 11.8. Incremental k-shortest path algorithm.

It turns out that finding the shortest path from 1-terminal to the new vertices can be done very efficiently when those new vertices get created. The shortest path searching can virtually take no time during the subtraction operation. Suppose that every vertex in reverse DDD graph D has a shortest path from 1-terminal to it (be visited once). Then the new algorithm for searching the next dominant term is given in Fig. 11.9. In G ETN EXTS HORTESTP ATH(D), E XTRACTP ATH(D) obtains the found shortest path from D and returns the path in a single DDD graph form. This is done by simply traversing from the root vertex to 1-terminal. Each vertex will remember its immediate parent who is on the shortest path to the vertex in a fully relaxed graph (relaxation concept will be explained soon). Once the shortest path is found, we subtract it from the existing DDD graph and relax the newly created DDD vertices (line 15-17) at same time to find the shortest paths from 1-terminal to those vertices, which is performed in the modified function S UBTRACT(D, P), now called S UBTRACTA NDR ELAX(D, P). In function SUBTRACTANDRELAX(D, P), RELAX(P, Q) performs the relaxation operation, an operation that checks if a path from a vertex’s parent is the shortest path seen so far and remember the parent if it is, for vertices P and Q where P is the immediate parent of Q in the reverse DDD graph. The relaxation operation is shown in Fig. 11.10. Here, is the shortest path value see so far for vertex is the weight of the edge from P to Q, which actually is the circuit parameter value that Q represents in the reverse DDD graph. Line parent(Q) = P remembers the parent of Q in the shortest path from the

DDD Based Approximation for Analog Behavioral Modeling

235

Figure 11.9. Incremental k-shortest path based dominant term generation

algorithm.

Figure 11.10. THE RELAX() operation.

1-terminal to Q. In the reverse DDD graph, each vertex has only two incoming edges (from its two children in the normal DDD graph), so the relaxation with its two parents in lines 16 and 17 are sufficient for the relaxation of vertex V. Moreover, the relaxation for V happens after all its parents have been relaxed due to the DFS-type traversal in SuBTRACTANDRELAX(). This is consistent with the ordering requirement of the shortest path search algorithm. Therefore by repeatedly invoking function GETNEXTSHORTESTPATH(D), we can find all the dominant terms in a decreasing order.

236

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Let be the number of vertices in a path from 1-terminal to the root vertex, i.e. the depth of the DDD graph, given the fact that D is a DDD graph and P is a path in the DDD form, then we have the following theorem: Theorem 11.2. The number of new DDD vertices created in function SUBTRACTANDRELAX(D, P) is bounded by and the time complexity of the function is Proof: As we know that DDD graph D contains path P. As P is a singlepath DDD graph, P.child0 is always 0-terminal. So lines 9-10 and line 13 will immediately return D and D.child0 respectively (actually, line 10 will never be reached if D contains path P). As a result, we will descend one level down in graph D each time depending on which line we choose to go for lines 7 and 14. In fact, function SUBTRACTANDRELAx(D, P) actually will traverse the embedded path P in D until it hits a common subgraph in both D and P as indicated in line 5. After this, new vertices will be created on its way back to the new root vertex, is the number of vertices visited in D in the whole operation and If the common subgraph is 1-terminal, then We then have the following result for incremental k-SP based algorithm: Theorem 11.3. The time complexity of the incremental k-SP algorithm for finding k shortest paths is

where

is the depth of the DDD graph.

Proof: The RELAX() operation shown in Fig. 11.10 takes constant time to finish. As a result, the time complexity of the operation SUBTRACTANDRELAX() will still be according to Theorem 11.2. After finding the first shortest path, which takes to finish, the algorithm will take to find each shortest path. Therefore, it takes to find the rest of shortest paths and the total time complexity of finding the shortest paths becomes Notice that both DP based algorithm and incremental k-SP based algorithm have time complexity to find a dominant term, where is the size of a DDD graph. After the first dominant term, however, both algorithms show better time complexities for generating next dominant terms, that is But in contrast to DP based algorithm, the actual running time of the incremental k-SP based algorithm does not depend on the topology of a circuit. Notice that the new incremental k-shortest path generation algorithm can be performed on any DDD graph, including cancellation-free DDD. We note that the variant of DDD used by Verhaegen and Gielen in [93,95] does not satisfy the canonical property due to vertex duplication. As a result, except for the first shortest path, remaining dominant paths cannot easily be generated

DDD Based Approximation for Analog Behavioral Modeling

237

by using the shortest path algorithm as the found shortest path is hard to be subtracted (if possible at all) as most DDD graph operations are not valid for a non-canonical DDD graph. Following the same strategy in [98], our approach also handles numerical cancellation. Since numerical canceling terms are extracted one after another, they can be eliminated by examining two consecutive terms.

4.1

DDD-based Approximation Flow

In this subsection, we give the overall flow of the DDD-based symbolic approximation algorithm as shown in Fig. 11.11. The input of the algorithm is user specified parameter which specifies how many errors are allowed for the approximation for each coefficient of the transfer function. Also let represent a coefficient of an and represent the numerical value of the coefficient at frequent The checking for error will be carried out over the entire frequency range as shown in Fig. 11.11.

Figure 11.11. DDD-based symbolic approximation fbw

238

5.

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Application to AC Characterization of Analog Circuits

In this section, we show how to generate the dominant terms for some real analog circuits. We apply the proposed dominant term generation algorithms to derive interpretable symbolic expressions for transfer functions and poles from simple [two-stage CMOS Opamp circuit shown in Fig. 11.1. The exact transfer function generated by our program is shown in Appendix 8. In the approximation process, we monitor both the magnitude and phase of the simplified expressions to control the accumulated error within a given frequency range. Before we generate dominant terms, we first simplify DDD graphs by device removal and node contraction on the complex DDD representation [90, 88], which will remove many insignificant terms and result in smaller complex DDDs. For TwoStage, the simplified voltage gain for TwoStage given by our program is shown in Eq. (1.1). Table 11.1 shows the exact values of three zeros and three poles.

Since three poles are far away from each other, the pole splitting method can be used to find their symbolic expressions. For instance, the resulting expression of the first pole based on DDD manipulations is as follows:

This agrees with the exact first pole described in Table 11.1. It is shown in [86] that the incremental k-SP based algorithm consistently outperforms the DP based algorithm for different analog the circuits in both CPU time and memory usage. Fig. 11.12 shows the CPU time for different ladder circuits. The CPU time increases almost linearly with the size of a ladder circuit for all three algorithms. The “shortest path” algorithm refers to SP algorithm which does not perform the incremental path search. Both the SP-based algorithms consistently outperforms DP based algorithm in terms of CPU time. The reason is that sizes of DDDs for representing ladder circuits grow linearly with the sizes of the ladder circuits, that is so the time complexities of all three algorithms, become But the DP based algorithm needs to take extra efforts to loop through all 0-linked vertices to compute the dominant terms and restore them at each 1-edged pointed vertex.

DDD Based Approximation for Analog Behavioral Modeling

239

Those extra efforts will become significantly when the graph becomes very deep as with the higher order ladder circuits.

Figure 11.12. CPU time vs number of ladder sections.

Figure 11.13. Memory use vs number of ladder sections.

Fig. 11.13 shows the memory usage for different ladder circuits. The memory usage of DP based method increases linearly with the sizes of ladder circuits, while the non-incremental k-SP and the incremental k-SP algorithms take much smaller amount of memory for the same set of ladder circuits. The DP based

240

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

method will use more memory when more terms are generated as more memory will be used for caching the generated terms at each 1-edge pointed DDD vertex.

6.

Summary

In chapter, we have presented efficient algorithms to generate dominant terms for ac characteristics of large linear analog circuits. The new algorithms are based on a DDD graph-based compact and canonical representation of symbolic expressions. We formulated the dominant term generation problem as the one of searching for the shortest paths in DDD graphs. Theoretically we showed that dynamic programming based dominant term generation method is restricted to certain DDD graphs. Practically, we presented a incremental search algorithm, which can be applied to any DDD graphs, based on the canonical property of DDD graphs. Experimental results indicate that the proposed incremental path algorithm outperform the best known algorithm based on the dynamic programming [93, 95] in terms of CPU time and memory usage.

7.

Historical Notes on Symbolic Approximation

Notice that the symbolic approximation are typically carried out around some nominal numerical values (points) of the devices involved, the generated model will approximate actual devices well when the sized device parameters are close to the nominal values used for model generation. However, when using a staged optimization approach, the nominal points will move and model will be updated adaptively. As a result, the optimized devices will be very close to the nominal points of the model generated in the final stage (as the model is re-centered after every stage). Such nominal point approximation strategy used in this work is also adopted by most of symbolic approximation methods [19, 30, 48, 93, 98, 99, 107]. During the approximation, we monitor both magnitudes and phases of the transfer functions until errors are within the user-specified error bounds for the frequency range. As illustrated in [37], simple yet accurate symbolic expressions can be interpretable by analog designers to gain insight into the circuit behavior, performance and stability, and are important for many applications in circuit design such as transistor sizing and optimization, topology selection, sensitivity analysis, behavioral modeling, fault simulation, testability analysis and yield enhancement [38]. Efficient symbolic techniques for linear(ized) analog circuit analysis are the basis of distortion analysis of weakly nonlinear circuits [94, 100], symbolic modeling of time-varying systems such as mixers [92]. Previous attempts to generate interpretable expressions use various symbolic analysis methods to generate sum-of-product representations for network func-

DDD Based Approximation for Analog Behavioral Modeling

241

tions. This area has been studied extensively in 1960s-1980s [53]. The resulting approaches, however, are only feasible for very small circuits, since the number of expanded product terms grows exponentially with the size of a circuit, and the resulting expressions are no longer interpretable by analog designers. Recently, various approximation schemes have been developed. Approximation after generation is reliable but it requires the expansion of product terms first [37, 72, 99]. Some improvements based on nested expressions have been proposed [27, 73]. But they generally suffer symbolic term-cancellation and align-term problems. Approximation during generation extracts only significant product terms [30, 98, 107]. It is very fast, but has two major deficiencies: First, if accurate expressions are needed, the complexity of the approach becomes exponential. Second, it works only for transfer functions. Other smallsignal characteristics such as sensitivities, symbolic poles and zeros, cannot be extracted in general. At the same time, several approximation before generation techniques [42, 107] were proposed in which the complexity of a circuit is simplified before symbolic analysis methods are applied. Recently, a signalflow graph based approximation before generation method was proposed [18] and demonstrated successfully to symbolic pole and zero generation. Symbolic analysis based on the concept of signal paths in control theory was employed for pole and zero location analysis [48, 49].

8.

Appendix

Exact transfer function of two-stage CMOS opamp in Fig. 11.1 The numerical value at the end of each line is the magnitude of the coefficient of if the line starts with or the magnitude of the product term in the same line otherwise. All the products in each coefficient are sorted with respect to their numerical magnitudes. For instance, in the numerator, means that the numerical value for the coefficient of is The line below is which shows that term gm2 gm2 gm6 has numerical value and is the first dominant term for

242

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

DDD Based Approximation for Analog Behavioral Modeling

243

This page intentionally left blank

Chapter 12 HIERARCHICAL SYMBOLIC ANALYSIS AND HIERARCHICAL MODEL ORDER REDUCTION

In this chapter, we present a general s-domain modeling and simulation technique via hierarchical symbolic analysis technique, which is a generalized version of transformation algorithm presented in Chapter 4 and Chapter 6. The algorithm can reduce the circuit complexities by applying general symbolic subcircuit reduction and keeping the generated admittances in the reduced circuit matrices in the exact or approximate rational function forms. The method performs the node reduction directly on the circuit matrices and hence it is general enough to reduce any linear circuits formulated by more general modified nodal analysis (MNA) method. Furthermore, instead of reducing one node at a time as done in transformation [68], the method allows elimination of multiple nodes simultaneously. This leads to a general hierarchical s-domain analysis technique as we can suppress subcircuits, which consist of a number of nodes, one at a time in a hierarchical and an independent way. The method thus is able to exploit the naturally hierarchical structures inherent in many linear circuits. Such a hierarchical node reduction is made possible by means of a DDD graph-based hierarchical symbolic analysis technique for computing the newly created admittances and removing the canceling terms and common factors (de-cancellation) in determinants [77, 78] – the key operations in the hierarchical modeling and simulation algorithm. The resulting algorithm can perform efficient s-domain and time-domain analysis on any linear active or passive network with very high accuracy. The major differences and similarities between the proposed method and the transformation are listed below: Reduction Methodology: Both methods essentially are based on the Gaussian elimination process to perform the node reduction. The hierarchical method is a more general version of the reduction method as we can

246

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

reduce multiple nodes at a time, which is shown to be more efficient than reducing one node at a time. Circuits Can Be Reduced: The hierarchical reduction method can be applied to any linear circuit with any controlled and independent source. While method can only solve certain circuits with limited independence sources (like current sources). Circuit elements whose stamps can not be written in the admittance form can’t be used in the method due to the nodal formulation requirement. Circuit Formulation: The hierarchical method is based on more general MNA formulation and works directly on circuit matrix. The method is based on nodal formulation (NA) and works on the circuit topology directly, which limits its applications. Implementations: The hierarchical method is a general version of the method. It uses a special graph-based (DDD graphs) technique to compute the rational function of a determinant. It also allows the symbolic term de-cancellation to improve the accuracy of the reduction process during the computation process. In contrast, the method does not have to deal with determinant and can thus be implemented more easily. But all the cancellations have to be done numerically in the method. The major implementation overhead of the hierarchical method over the method is the DDD graph related data structures and general subcircuit related data structures and corresponding operations.

1. DDD-based Hierarchical Decomposition 1.1 Subcircuit Reduction In this section, we briefly review how nodes in a subcircuit can be suppressed in matrix form. Consider a subcircuit with some internal structures and terminals, as illustrated in Figure 12.1. The circuit unknowns—the node-voltage variables and branch-current variables—can be partitioned into three disjoint groups and where the superscripts I, B, R stand for, respectively, internal variables, boundary variables and the remaining of variables. Internal variables are those local to the subcircuit, boundary variables are those related to both the subcircuit and the rest of the circuit. Note that boundary variables include those variables required as the circuit inputs and outputs. With this, the system-equation set can be rewritten in the following form:

Hierarchical Symbolic Analysis and Hierarchical Model Order Reduction

247

Figure 12.1. A hierarchical circuit

The matrix, is the internal matrix associated with internal variable vector Assume the row indices for are from 1 to row indices for are from to and row indices for are from to where and are the sizes of the submatrices and respectively. Subcircuit suppression (also called Schur Decomposition) is used to eliminate all the variables in and to transform Eq.(1. 1) into the following reduced set of equations:

where

where is called the adjoint matrix of A, is the first-order cofactor of det(A) with respect to and is defined as and matrix is the obtained from matrix A by deleting row and column is also called Schur complement [34]. We also have

248

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Subcircuit suppression can be performed for all the subcircuits by visiting the circuit hierarchy in a bottom-up fashion. Since the number of internal variables is and the number of boundary variables is Eq.( 1.4) and (1.6) can be written in the following expanded forms:

where

and

where From Eq.(1.7) and (1.8), we can observe that admittance and input stimuli at boundary nodes will become rational functions of once the subcircuit is suppressed. The term

are called composite admittances as they are the admittances generated during subcircuit reduction. In order to obtain the rational functions for and we need to compute the rational function for a determinant whose elements may again be rational functions of This task can be achieved via determinant decision diagrams (DDDs), which were proposed originally for symbolic analysis of large analog circuits [77, 91]. We will show how the DDD graphs can be modified to compute the rational function for a determinant in the later sections. An important issue is that if the symbolic expressions are kept ( s-expressions are special symbolic expressions), the final expressions of the generated rational admittances are not free from cancellation as common factors between the numerator and denominator of the resulting rational admittances in and will be generated (common-factor cancellation) or sum of two symbolic terms equals to zero (). Such symbolic cancellation problem has been observed and discussed in Section 1 of Chapter 5 in the context of transformation. The cancellation dues to common factors may lead to exponential growth of the magnitude of coefficients in the numerators and denominators. As we can see in the later sections of this chapter, cancellation-free rational admittances are directly related to the exact admittance expressions computed from the flattened circuit matrix and are also very important to the new de-cancellation method. Fundamentally, we will show in section 3 that all the cancellations are caused by subcircuit reductions. The conditions for common-factor cancellations and term cancellations will be explained in more details in Theorem 12.2 and Theorem 12.3.

Hierarchical Symbolic Analysis and Hierarchical Model Order Reduction

249

To be more precise on cancellation-free expressions, we define admittance order, which is the number of the basic admittances of circuit devices (like etc.) in any product term in the denominators of those newly generated admittance terms and in the reduced matrix. Actually according to the definition of a determinant, it can be seen that the number of device admittances equals the dimension of the determinant But if all the nodes internal to the submatrix are reduced by different subcircuits at different circuit hierarchical levels, the resulting admittance order in each new term or will be larger than the real admittance order if common-factors are not removed. Therefore how to remove those common factors (de-cancellation) in the rational functions of and in general becomes a key issue for the subcircuit reduction process. An efficient algorithm has been proposed for de-cancellation during the generalized transformation in Section 2 of Chapter 5. In the sequel, we show how cancellation-free rational functions can obtained by efficient DDD graph operations during the general hierarchical circuit reduction process.

1.2

Overview of The Simulation and Reduction Algorithm

In this section, we give the overview of the general s-domain circuit modeling and simulation algorithm based on the DDD-based hierarchical decomposition framework and the de-cancellation algorithm given in later sections. The basic idea is to reduce subcircuits and the right-hand side vector in a hierarchical and cancellation-free way. The new admittances coming from subcircuit suppressions shown in Eq.(2.1) and Eq.(2.2) are kept as rational functions of in the exact or order-reduced form (with fixed order of Such a reduction can be repeated until we reach the top level circuit, which is typically small enough to be solved exactly and symbolically is still the only symbol). The resulting circuit unknown variables are rational functions of which can be converted to time domain for waveform evaluation [66], From a simulation perspective, once the parent circuit variables .. are known, we can obtain the internal variables of subcircuit by solving

In this way, we can obtain all the unknown variables in the rational form. From a modeling perspective, we can easily obtain the network functions of the given circuits to compute other small-signal characteristics of analog circuits and second or higher order effects as nonlinearity (especial weakly nonlinear characteristics like distortions) can be estimated based on network functions of linearized circuits [101]. We assume that the circuit hierarchy has been constructed using the multiple minimum degree (MMD) algorithm. The modeling algorithm is shown below:

250

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

The General Hierarchical Network Modeling Algorithm 1. Build the complex DDDs for each subcircuit matrix and all the required cofactors/determinants for each newly created admittances in a bottom up way. 2. If the present circuit has subcircuits, perform the reduction on each subcircuit first. 3. Derive the YDDDs from complex DDDs for each new composite admittance shown in Eq.(2.1) and Eq.(2.2) 4. Construct the cancellation-free rational admittances for each YDDD using C OMP R AFUNC (). 5. If truncation is carried out and stability is required, perform Routh-Hurwitz approximation on the reduced transfer functions.

The general hierarchical reduction algorithm is also illustrated in Fig. 12.2. It was shown that YDDD representation is more compact than sequence of expressions [41,91], whose complexity essentially represents the complexity of symbolic node-by-nodeGaussian elimination process. Hence time complexity of the general hierarchical reduction algorithm is better than reduction algorithm [68], which is based on Gaussian elimination. Another advantage of the general reduction algorithm over the existing transformation algorithm is that we need to remember fewer number of common-factors, which are the determinants of the reduced subcircuit matrices. If we reduce one node at a time, each node becomes a subcircuit, we end up with more commonfactors to deal with. Also there are more independent subcircuit hierarchies as each subcircuit is the smallest (consists of one node). As a result, we have to remember all the common-factors of the reduced circuits (nodes) that are connected to nodes yet to be reduced, which in turn leads to more memory usage compared to the general reduction method. Our experimental results confirm those observations. For large RLC interconnect circuits, truncations have to be carried out to keep limited orders of in each rational admittance. The resulting admittances or transfer functions may not be stable. Routh-Hurwitz approximation can be carried out to enforce stability [102, 68, 82].

2.

DDD-based Hierarchical Decomposition

The idea of DDD-based hierarchical decomposition [91 ] is to represent all the determinants and cofactors in Eq (1.7) and (1.8), as well as those determinants and cofactors in the final transfer functions of the desired circuit characteristics. Due to the compactness of DDD graphs, DDD-based hierarchical circuit decomposition was shown to be superior to the previous methods [41, 81]. For our problem, some elements (in admittance forms) of a circuit matrix will become a rational function of during the hierarchical subcircuit reduction

Hierarchical Symbolic Analysis and Hierarchical Model Order Reduction

251

Figure 12.2. The general hierarchical network reduction algorithm flow

process. As a result, the construction of the rational function for such a determinant will be different from the method used for DDDs [78]. A new DDD graph, called Y-expanded DDD (YDDD) is introduced for this task, which will be explained soon. First we introduce the following theorem: [84]

252

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 12.3. Illustration of Theorem 12.1

Theorem 12.1. Eq.(1.7) can be written in the following form:

where form:

and Eq.(1.8) can be written in the following

where, which actually is

is the submatrix that consists of matrix plus row and column of matrix A; is the submatrix that consists of matrix plus row of matrix A and the right hand side column The and are illustrated in Fig. 12.3. The proof of the theorem can be found in [83]. Submatrix notation

can be illustrated using Eq(3.1). The submatrix A[1, 2, 3|1, 2, 3] of the matrix in Eq(3.1) is

With Theorem 12.1, we only need to compute the rational function for the numerator, which is a determinant (as shared by all the newly created matrix elements for each subcircuit) for each boundary-variable related element in the reduced circuit matrix instead of representing each individual first-order cofactor of explicitly [91]. This leads to the efficient DDD-based hierarchical decomposition method. Such determinant-only DDD representation for all the involved matrix elements is more compact than the previous

Hierarchical Symbolic Analysis and Hierarchical Model Order Reduction

253

method [91] as first-order cofactors are not explicitly represented. Therefore, more sharing of common terms becomes possible among those cofactors and elements in row columns and More importantly, such DDD-only representation of new admittances is more amenable to removing cancellation during subcircuit reduction process as shown in the next section.

3.

Cancellation Analysis for Subcircuit Reduction

In this section, we explain how cancellation happens due to circuit device and due to subcircuit reduction as well as their relationship in MNA formulation. Some theoretical results will be presented.

3.1

Cancellation Due to Circuit Devices

The common factors will be introduced when the same circuit parameter will appear more than once in a circuit matrix in MNA formulation for a subcircuit. Two cancellation patterns are shown in Fig. 12.4.

Figure 12.4. Matrix patterns causing term cancellation.

Case 1 comes from the rectangular appearance of a floating resistor/conductor and case 2 reflects the pattern from a voltage controlled current source (VCCS) in MNA formulation [96]. As a result, all the product terms consisting of elements at and at will cancel all the terms consisting of elements at and at for case 1. The same is true for Case 2. Such cancellation can lead to numerical errors if they are carried out numerically in general. But those errors may only affect very high order terms based on our observations. In our algorithm, we have an better approach to this problem as term cancellations due to case 1 and case 2 in Fig. 12.4 and other general cases due to circuit reduction shown later can be symbolically removed during YDDD construction for a determinant [85]. A detailed description of the algorithm for general term de-cancellation is given in subsection 4.3.1. As we can see later that the device-level cancellations coming from the NA or MNA formulation are essentially caused by subcircuit reduction discussed in the next subsection.

254

3.2

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Cancellation Due to Subcircuit Reduction

Once a subcircuit has been suppressed, new cancellation patterns are created. Let’s illustrate this concept through a simple RC circuit shown in Fig.12.5. Assume all the R and C devices have unit value, then the circuit matrix of the circuit is shown in Eq.(3.1).

Figure 12.5. A simple RC circuit.

Let’s suppress node 1

first, the resulting circuit matrix becomes

It can be seen that the product term of and will cancel the product term of and This is the term cancellation during the subcircuit reduction process in this chapter. If we further reduce the node 2 the resulting circuit matrix will become:

First, we notice that the denominator in the composite admittances actually is which is the determinant of the subcircuit matrix consisting of node 1 and 2 only (first two

Hierarchical Symbolic Analysis and Hierarchical Model Order Reduction

255

rows and columns in the Eq.(3.1)). Also all the numerators in those composite admittances agree with Eq.(1.7). As a result, we can rewrite Eq.(3.2) as follows:

Eq.(3.3) tells us that the resulting admittances in the reduced circuit are the same regardless of how nodes are reduced (one-by-one or subcircuit-bysubcircuit). For this reduced matrix, cancellation becomes more complicated and both term cancellation and common-factor cancellation exists. For instance, if we look at the four composite admittances at rows and and columns and in Eq.(3.2), we will have

So becomes the common factor of the resulting rational admittance. This is the common-factor cancellation in the chapter. In general, after subcircuit is reduced both term cancellation and commonfactor cancellation will be generated. For common-factor cancellation, it can be more clearly explained graphically in Fig. 12.6. Nodes at and at are the internal nodes in a subcircuit to be suppressed. Nodes at and at are boundary nodes. Their connections with the two internal nodes are shown in the right-hand side of Fig. 12.6. As a result, admittances and are not zero. According to Eq.(1.7) we have,

256

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 12.6. Cancellation pattern due to subcircuit reduction

where, is the new admittance at is the internal determinant of the subcircuit suppressed and is the first-order cofactor of with respect to element Since the four new composite admittances appear in two rows and two columns, they will cause new cancellation when node and are suppressed as the internal nodes in the upper level subcircuits. Specifically, we will have the following product terms in the internal determinant of the upper-level subcircuit according to the definition of a determinant (if those two nodes are suppressed at the same time).

where is the rest of other terms when the products of the new admittances are expanded. We have two scenarios to consider. First, if nodes and are the same node, i.e. the last two terms in (3.9) will cancel each other as This is the term cancellation. Second, if those two nodes are different internal nodes, we will show that the combined last two terms in (3.9) has a common factor between the numerator and the denominator. Specifically,

As a result, we know that is a common factor in the combined last two terms in (3.9), which will become

Hierarchical Symbolic Analysis and Hierarchical Model Order Reduction

257

after the common factor in the numerator and the denominator cancels. This actually is the common-factor cancellation. Going back to the example in Eq.(3.4), we have where which validates Eq.(3.10).

3.3

Theoretical Analysis of Cancellation Conditions

In general, if the composite admittances from the suppression of one subcircuit populate more than two rows and columns, their corresponding first-order cofactors may also appear in more than two rows and columns in the submatrix We then have the following general theorem regarding the common-factor cancellation [82]. Theorem 12.2. Given a matrix A and its and columns as shown in (3.11),

elements at rows

we then have

where

is order cofactor with rows removed from det(A) and is defined as

and columns

When all the rows and columns are removed from A, we have Theorem 12.2 actually is the classic Jacobi matrix identity [34]. In the sequel, we show how Jacobi matrix identity is linked to the common-factor cancellation issue encountered in the general hierarchical node circuit reduction algorithm. After the subcircuit reduction, there are many composite elements in the reduced matrix (1.2) and each of them contains one first-order cofactor of the

258

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

suppressed sub-matrix Theorem 12.2 basically says that if all those firstorder cofactors form a matrix whose associated matrix elements are coming from rows and columns in the reduced submatrix shown in Eq.(3.11), will become the common factor between the numerator and the denominator of the sum-of-product term, which consists of all the product terms with first-order cofactors in each product term when the determinant of the reduced matrix is computed. Note that if the common-factor is not removed, the denominator of each product term is as is the denominator for every composite admittance. But does such first-order cofactor matrix always exist in the reduced matrix? We have the following corollary answering this question [83]. Let be the submatrix in Eq.(1.1). Assume there exists a product term in the determinant of the reduced matrix in Eq.(1.2) and the product term consists of first-order cofactors of Corollary 12.1. If all the first-order cofactors have unique row and column indices, there exists a full first-order cofactor matrix as shown in Eq. (3.12) embedded in the reduced matrix where the product term is one of the terms in the determinant of the matrix. Also will be the common factor between the numerator and the denominator of the sum-of-product rational expression of those product terms whose first-order cofactors form the matrix. The corollary essentially tells us that if there exists a term whose first-order cofactors come from different rows and columns in the sub-matrix there exist similar product terms and common-factor cancellation will always happen when those terms are added together. On the other hand, if there is a product term from a determinant of the reduced matrix with first-order cofactor and whose row or column indices are not unique, this product term will eventually cancel out due to term cancellation. Following theorem gives the condition on the term cancellation in the reduction process [84, 83]. Theorem 12.3. For a given product term from a determinant, which consists of first-order cofactor of a subcircuit, if there are two first-order cofactors that share the same row index or column index, then there exists another product term that will cancel with this product term. As a result, we can see that any higher admittance-order term coming from multiplications of composite admittances will eventually merge (to generate common cofactors) or cancel out with other same-order terms so that the resulting terms will have the correct admittance order. This is also consistent with the observation that no matter how internal nodes are reduced, the admittances in the reduced circuit should have the same admittance order given the same set of reduced nodes.

Hierarchical Symbolic Analysis and Hierarchical Model Order Reduction

259

If we look at the example in Fig. 12.5 again, we notice that in Eq.(3.2), all the terms containing three first-order cofactors will cancel out eventually as some first-order cofactors will always share the same row or column indices for every product term. This also reflects the fact that the determinant consisting of all the first-order cofactors of all the composite admittances is a singular matrix as shown below:

As a result, we have the following result regarding the cancellation-free denominator of the rational admittance computed from the determinant of a reduced circuit matrix [83]. Corollary 12.2. The is the denominator of the cancellation-free rational admittances computed from a determinant of a reduced circuit matrix with being the internal matrix of the reduced subcircuit. Note that if the circuit has more than one immediate subcircuit (say circuits), it can be easily shown that

will be the denominator of the resulting rational admittance, where internal matrix of subcircuit

3.4

sub-

is the

Device-Level Cancellation From Subcircuit Reduction’s Perspective

Device-level cancellation is actually caused by the subcircuit reduction. Circuit matrices formulated by MNA and NA methods can be obtained by reducing the branch current variables and branch voltage variables from circuit matrices formulated by using sparse tableau analysis (STA) method, which is cancellation-free as each device parameter appears only once in STA matrices. To see this, Fig. 12.7 shows the stamps for an impedance (like a self-inductor) and the reduced matrix where the current variable I is reduced. So the cancellation for an admittance device can be viewed as the cancellation due to the reduction of the current variable for an impedance element.

3.5

Cancellation at Different Hierarchical Circuit Levels

If the nodes and in Fig.12.6 are reduced in different subcircuits at different circuit hierarchical levels, cancellation will happen when those composite admittances from different subcircuits are merged. To see this,

260

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 12.7. An impedance stamp and the stamp in the reduced matrix.

suppose that only node is selected to be suppressed in subcircuit III. As a result, the new element value at node which is not suppressed, becomes

We also notice that

As a result, we have

Notice that is just Eq.(3.9). Therefore we know that is the common factor in the numerator and the denominator of the resulting rational function. After the common factor is removed, will become cancellation-free. The cancellation at different circuit hierarchical levels essentially can be viewed as the cancellation inside a determinant in one circuit level as discussed in Subsection 3.2. Based on Theorem 12.1, we know that the numerator expression in Eq.(3.17) eventually forms a determinant if all the composite and non-composite admittance terms are added together. So the cancellation problems in the numerator are the cancellation problems in a determinant. More precisely, Eq.(3.17) only presents a specific common-factor cancellation when the numerator (which is a determinant is expanded along the row and column sequentially. If all the cancellations are carried out numerically, no special consideration for cancellation at different circuit hierarchical levels is required in the general hierarchical decomposition scheme. If we remove the term cancellations symbolically, we have to represent each composite admittance explicitly instead implicitly. The composite

Hierarchical Symbolic Analysis and Hierarchical Model Order Reduction

261

admittances from the reduction of different subcircuits will be added together in a cancellation-free manner.

4.

General s-Domain Hierarchical Network Modeling and Simulation Algorithm

In this section, we detail the general network modeling and simulation algorithm based on cancellation rules discussed in the previous section.

4.1

Cancellation-Free Rational Admittance

First we show that if we can manage to obtain symbolic of the determinant of a reduced circuit matrix during the hierarchical decomposition, those cancellation-free rational admittances can lead to the exact symbolic expressions obtained from the determinant of original (flattened) circuit matrices. Such cancellation-free expressions can significantly simplify the reduction process. To simplify the discussion, we first assume that for every circuit or subcircuit at a particular circuit hierarchical level, it has only one subcircuit. We can easily extend the result to multiple subcircuit case. Let be the internal matrix of subcircuit at level when all its subcircuit matrices are reduced, with subcircuit being its immediate children circuit and subcircuit being its immediate parent circuit. Also let be the internal matrix of the flattened subcircuit that includes all the internal nodes in subcircuit as well as in its direct or indirect subcircuits in all the downstream hierarchical levels in one level. In other words, represents the flattened subcircuit that includes all the suppressed internal nodes at subcircuit level. Then we have the following result [83]: Theorem 12.4. Let be the matrix of the subcircuit at level and are the matrices of the flattened circuits at circuit level and

and Then

Note that if current circuit has more than one immediate subcircuit, Eq.(4.1) can be modified as

where N is number of subcircuits of the current circuit. Before we proceed, we define some terms used in the following theoretical results.

262

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Definition 12.1. Exact symbolic expressions are the expressions obtained directly from the expansion of a determinant without any approximation. Definition 12.2. Cancellation-free expressions are the expressions that are free of symbolic cancellations. The symbolic cancellations can be term cancellation or common-factor cancellation and they come from the hierarchical Schur decomposition only. The significance of Theorem 12.4 is twofold. First by combining with Corollary 12.2, we can immediately have the following corollary: Corollary 12.3. The numerator of a cancellation-free symbolic rational expression of a determinant of a reduced circuit matrix is the exact symbolic expression obtained from the determinant of the flattened circuit matrix. As a result, we can obtain the exact symbolic expressions of the flattened matrix by obtaining the cancellation-free symbolic expressions during the hierarchical decomposition. Second the reduction process is independent of reduction sequences if the symbolic rational expressions are kept cancellation-free all the time. In other words, we will arrive at the same cancellation-free symbolic expressions for each newly created rational admittance regardless of how internal nodes are suppressed (node-by-node or subcircuit by subcircuit). The reason is obvious: the cancellation-free rational expressions at a particular circuit level are identical to those obtained by reducing all the internal nodes all together in one subcircuit. As a result, we only need to worry about the cancellation between current circuit and its immediate subcircuits at any circuit hierarchical level. This will significantly simplify the de-cancellation process during the hierarchical decomposition process.

4.2

Y-expanded DDDs

In order to efficiently compute the rational function for a determinant and handle cancellations, an different DDD graph called Y (parameter) expanded DDDs (YDDD) is first introduced. Y-expanded DDDs are also DDD graphs where each DDD node represents a device admittance or a composite admittance as shown in Fig. 12.8. Note that some circuit parameter admittances are functions of the complex frequency variable This is different from the DDD graphs where is explicitly extracted and represented [78]. The main purpose of the introduction of YDDDs is that we can easily handle both term cancellation and common-factor cancellation as cancellation patterns can be easily detected by examining those device admittances or composite admittances. Similar to DDDs [78], the YDDDs can be constructed from a complex DDD in linear time in the size of the original complex DDDs. The time complexity

Hierarchical Symbolic Analysis and Hierarchical Model Order Reduction

263

Figure 12.8. A determinant and its YDDD.

for constructing complex DDD depends on the circuit topology. Given the best vertex ordering, if the underlying circuit is a ladder or tree circuit, is a linear function of the size of the circuit. For general circuits, the size of DDD graph may grow exponentially in the worse case. But like BDDs, with proper vertex ordering, the DDD representations are very compact for many real circuits [77, 78]. In Fig. 12.9, we present a version of the algorithm called YDDDC ONST( ).

Figure 12.9. Y-expanded DDD construction.

Function YDDDCONST( ) takes a complex DDD rooted at D and returns the resulting YDDD tree. D.1 and D.0 denote, respectively, the vertices pointed to by the 1-edge and 0-edge of vertex D. is the number of devices admittance or composite admittances connected to a node and each is denoted by computes the union of two YDDDs, and computes the product of YDDD P and YDDD vertex

264

4.3

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Computation of Cancellation-Free Rational Admittances

To construct a cancellation-free rational admittance (rational function of from a determinant represented by a DDD graph, whose elements are rational admittances too, we need to take care of both term cancellation and commonfactor cancellation. The computation can be done in a bottom up fashion. Specifically, at each YDDD node P, we compute the rational function from the YDDD tree rooted at P recursively. Let denote the rational admittance that the YDDD node P itself represents. and represent the rational admittances for the YDDD subtrees rooted at nodes pointed by the 1 -edge and 0-edge of P respectively. The rational admittance of the DDD tree rooted at P will become [77]

With Eq.(4.3), the rational function (admittance) at the root of the whole YDDD can be computed recursively. Since both multiplication and addition are involved, de-cancellation measures have to been taken for both operations as shown below. 4.3.1 De-cancellation for term cancellation Term cancellation happens when two identical symbolic product terms with opposite signs are added together. The cancellation can come from device admittances or from subcircuit reduction as shown in Subsections 3.1 and 3.2. For canceling terms generated by subcircuit reduction, we may have as their denominators, the efficient constant-admittance-order de-cancellation strategy (will be discussed below) will lead to unnecessary polynomial divisions, which add unnecessary computational costs at best and adversely introduce some numerical noises at worst. In our method, term cancellation can be removed during the construction of YDDDs for a determinant. The idea is to remove all those canceling terms via DDD operations. We first introduce concept of a canceling pair for two admittances (represented by two DDD nodes). For instance, composite terms and in Eq.(3.1) is a canceling pair. If those two terms are in a product term, this term will cancel out with another term eventually. Since each DDD node has an index, we say the DDD index is a canceling index of the other for a canceling pair. Before the construction of a YDDD for a determinant, we build a canceling list for each YDDD index, whose corresponding admittance is a composite admittance or device admittance. The use of a list is due to the fact that one DDD index can have more than one canceling DDD index. The criteria

Hierarchical Symbolic Analysis and Hierarchical Model Order Reduction

265

Figure 12.10. Term-Cancellation Free YDDDMULTIPLY.

for two indices to a canceling pair are based on Theorem 12.3 for composite admittances and the cancellation patterns in Fig. 12.4 for device admittances. To avoid duplication we require that and Once we have the canceling list for each DDD index, it will be used in YDDDMULTIPLY( ) shown in Fig. 12.9. The pseudo code for the term-cancellation-free YDDDMULTIPLY() in YDDDCONST() is shown in Fig.12.10, where lines 2 to 3 are used to remove canceling terms for each canceling pair. DDD operations and are operations to find all terms which do not contain symbol in P and to add symbol to every term in P respectively. is the number of the devices or composite admittances in the complex DDD vertex. We notice that the algorithm can’t remove the term cancellation symbolically. This is another significant advantage of the general hierarchical reduction algorithm over the algorithm. 4.3.2 De-cancellation for Common-Factor Cancellation Common-factors are more difficult to remove symbolically. Instead, we remove them numerically. We need to look at two situations where the common factors are introduced into the numerators and denominators of the resulting rational functions. The first one comes from the multiplication of and according to Corollary 12.2. The second one is due to the addition of two rational functions in Eq.(4.3), with common factors in their denominators. For instance, let’s consider the addition of two rational functions If there is a common term in both and will become a common factor in both the numerator and the denominator of the resulting rational function. Those two situations are handled separately in the presented method.

1. Cancellation due to multiplication. According to Corollary 12.2, only will be present in the denominator of the final rational admittances for each subcircuit from a circuit hierarchy. This leads to a very simple cancellation strategy: whenever we see admittance order is increased due to multiplication of two terms that both have in their denominators, we divide the resulting numerator by In this way, the

266

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

resulting admittance terms always have the correct admittance order and the cancellation-free numerators in the resulting expressions will be formed implicitly and numerically when all the resulting terms are added together. 2. Cancellation due to addition. Since common-factor cancellations are only caused by subcircuit reduction based on MNA formulation, we only need to consider the common factor for each subcircuit. The idea is that when addition of two rational admittances takes place, we explicitly watch for the admittances such that will not appear twice in the resulting new admittance. Specifically, this rule requires that only one for each subcircuit from a circuit hierarchy exists in the denominator of the resulting rational admittance. Now we are ready to present the whole rational admittance computation method for a determinant represented by its YDDD tree based on the decancellation aforementioned strategy. For each YDDD node P, we keep two things: the numerator polynomial of the computed rational admittance for the subtree rooted at P – denoted by N(P) and a set of YDDD indexes whose denominators are not trivial and unique – denoted by In this way we do not need to keep the denominator polynomial for each YDDD node explicitly and it is also easy to watch the cancellation situations. P(D) denotes the rational admittance for the DDD subtree rooted at D. D.index is the index of the DDD node D. Following the convention of DDD operations, we use D.1 and D.0 to represent the DDD subtrees pointed by 1-edge and 0-edge of DDD vertex D respectively. The resulting algorithm is shown Fig. 12.11.

Figure 12.11. Computation of the cancellation-free rational function from a YDDD.

Hierarchical Symbolic Analysis and Hierarchical Model Order Reduction

267

The algorithm basically visits every YDDD node once in a bottom-up fashion and computes the new rational admittance for each subtree rooted at the YDDD node visited and performs the de-cancellation for both multiplication and addition operations. So the time complexity of the algorithm is where is the number of YDDD nodes and is the highest order of all the rational admittances.

4.4

Clustering Algorithm

To construct the circuit hierarchy and minimize the computation costs, efficient clustering algorithm is required. Since the hierarchical reduction process is equivalent to the block Gaussian elimination process, the reduction order should follow the minimum fill-in or minimum degree ordering. Our clustering algorithm consists of two steps: (1) finding a good node reduction ordering; (2) performing the connectivity-based clustering based on the given node ordering subject to node size constraint and other user-specified constraints. For the node ordering algorithm, the multiple minimum degree algorithm (MMD) [55] is employed to find the node reduction ordering. The basic idea of MMD is to delay the updates of changing connectivity information (represented by the so-called elimination graphs to find the nodes with minimum degree) during the simulated Gaussian reduction process to speed up the ordering process. Once the node order is found, clustering is performed based on the connectivity information and the given node ordering subject to a given node count limit, which specifies the maximum internal node count, to control the size of the internal matrix for each subcircuit. Also nodes as inputs and outputs will be put into the top level circuit during the clustering process.

5.

Hierarchical Analysis of Analog Circuits – Examples

Here we present the exact transfer function for a second order linear filter shown in Fig.12.12 obtained from the new reduction program. In this circuit, we have and is an Opamp circuit and is represented by a linear model of 741 Opamp circuit shown in Fig. 12.13 which contains two voltage controlled current sources and The transfer function obtained by the new program is shown in the following:

Note that both the numerator and the denominator become rational functions of due to suppression of subcircuit But they share a common denominator

268

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 12.12. A second-order active filter.

Figure 12.13. A linear model of an Opamp circuit.

which is actually the determinant of the internal matrix of the subcircuit After the common denominator is removed, the transfer function is exactly the same one as we obtain from the flattened filter circuit. We also notice that the highest order of the transfer function of the second order filter becomes 3. But if Opamp is a ideal voltage controlled current source with infinite gain, the highest order will be 2. Next, we derive the exact transfer function for a more complicated active low pass filter shown in Fig. 12.14, which also contain controlled current sources. It has four identical subcircuits, named X1 to X4. Fig.12.15 shows the detailed structure of the subcircuit. Each subcircuit contains two Opamp subcircuits, which are also represented by the Opamp circuit shown in Fig. 12.13. The exact transfer function, computed by the new method, is shown as the follows:

Hierarchical Symbolic Analysis and Hierarchical Model Order Reduction

269

Figure 12.14. An active low-pass fi lter.

Figure 12.15. An FDNR subcircuit.

The flattened circuit of this low pass filter has 41 nodes, which can not be analyzed by DDD symbolic analysis directly due to circuit-limitation problem. If we set the maximum order to 8, we will obtain the exact coefficients up to 8th order of the exact transfer function. The exact, 8th-order, 10th-order and 16th-order approximate responses of the active filter are shown in Fig.12.16. We also notice that the numerator and the denominator do not share the same

270

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

Figure 12.16. The frequency response of the active fi lters (exact vs 8th, 10th, 16th order approximation).

denominator in this case. But it should agree with the exact transfer function after the transfer function is transformed into a rational form.

6.

Summary

In this chapter, we have presented a general hierarchical linear network simulation and modeling technique in s-domain. This hierarchical reduction method can be viewed as generalized transformation discussed in the previous chapters. The simulation and modeling are done by subcircuit suppression in a hierarchical way and by rational function approximation, which generates exact or order-reduced cancellation-free admittances in the reduced network matrices. The presented method works on circuit matrices formulated by MNA formulation and can be applied to any linear circuit. On the theoretical side, we studied how common factors are generated in the general subcircuit reduction process and presented some theoretical results. On the practical side, we presented a novel de-cancellation strategy based on determinant decision diagrams to derive the cancellation-free rational functions for determinants generated from subcircuit reduction. The resulting method can be used for modeling of both linear(ized) analog circuits, which typically are active circuits with controlled sources, and passive interconnect circuits. Experimental results have validated the proposed method on some linear analog circuits and large RLC interconnect circuits.

Hierarchical Symbolic Analysis and Hierarchical Model Order Reduction

7.

271

Historical Notes on the Model Order Reduction

Modeling and simulation of linear analog circuits in both frequency (sdomain) and time domain are critical for top-down constraint-driven design methodology for mixed-signal system-on-a-chip (SoC) designs[36] and interconnect centered physical design and optimizations [16, 52]. Due to the importance of on-chip global interconnects like power /ground grids, global signal nets and clock trees, a number of projection-based modelorder reduction based techniques have been introduced [23, 24, 25, 64, 66, 80, 79] to analyze the transient behavior of interconnects. Asymptotic Waveform Evaluation (AWE) algorithm was first proposed [66, 67] where explicit moment matching was used to compute the dominant poles at low frequencies. But AWE method is numerically unstable for higher order approximation. Thereafter a number of other projection-based model-order reduction methods based on implicit moment matching (via Krylov subspace projection) were developed. Examples are Pade via Lanczos (PVL) [23], Matrix PVL [24], Arnoldi method [80], Arnoldi Transformation method [79], PRIMA [64] and SyPVL algorithm [25]. Those projection-based algorithms mainly work for passive linear networks as the computation of moments and Krylov space base vectors requires a special partitioning of circuit matrices and solving of the partitioned circuit matrices iteratively, which may not be possible for general active networks with controlled sources seen in many analog circuits. Also projectionbased methods are not efficient for circuits with many independent sources as its time complexity is dependent on the number of independent sources or external ports. Another approach to circuit complexity reduction is by means of local node reduction. The main idea is to reduce the number of nodes in the circuits and approximate the newly added elements in the circuit matrix in reduced rational forms. The major advantage of those methods over projection-based methods is that the reduction can be done in a local manner and no overall solutions of the whole circuit are required (with some circuit realization/synthesis techniques), which makes those methods very amenable to attacking large linear networks. This idea has been explored by approximate Gaussian elimination for RC circuits [22], by the TICER program [74], which is also based on Gaussian elimination but it only keeps first two moments, and by the extension of TICER method into RLC circuits [2]. The rational approximation is also explored by the direct truncation of the transfer function algorithm (DTT) [43] for tree-structured RLC circuits and by an extended DTT method for non-tree structured RLC circuits [87]. Recently a more general topology based node-reduction method was proposed [68, 69], in which nodes are reduced one at a time (topologically it is called transformation) and the generated admittance in the reduced network is represented as an order-reduced rational function of This method

272

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

is equivalent to symbolic Gaussian elimination ( is the only symbol) but the reduction is done on circuit topologies only, which is equivalent to the nodal analysis (NA) formulation of a circuit only. The stability is enforced by RouthHurwitz polynomial approximation. But this method only works for linear circuits with limited element types (RCLK-VJ) and cannot be applied to reduce general linear circuits due to NA formulation. The details of transformation are discussed in Part II of this book. For both existing projection-based and node reduction based algorithms, the major problem is that they mainly work for interconnect circuits modeled as passive RLC circuits with limited capacity for mutual inductors. For active linear analog circuits with controlled sources, those reduction methods can not be applied in general. More importantly, as mutual inductive effects become more and more pronounced, more effective mutual inductance models, like vector potential equivalent circuit (VPEC) model [65], the improved VPEC model [106] and wire duplication models [108], begin to emerge. Those new mutual inductor models contain controlled sources which makes them difficult for reduction by existing model-order reduction techniques.

References

[1] S. B. Akers, “Binary decision diagrams,”IEEE Trans. on Computers, vol. 27, no. 6, pp. 509–516, 1976. [2] C. S. Amin, M. H. Chowdhury, and Y. I. Ismail, “Realizable rlck circuit crunching,” in Proc. Design Automation Conf. (DAC), 2003, pp. 226–231. [3] R. I. Bahar, E. A. Frohm, C. M. Gaona, G. A. Hachtel, E. Macii, A. Pardo, and F. Somenzi, “Algebraic decision diagrams and their applications,” in Proc. Int. Conf. on Computer Aided Design (ICCAD), Nov. 1993, pp. 188–191. [4] R. E. Bryant, “Graph-based algorithms for Boolean function manipulation,”IEEE Trans, on Computers, pp. 677–691, 1986. [5]

“Binary decision diagrams and beyond: enabling technologies for formal verifi cation,” in Proc. Int. Conf. on Computer Aided Design (ICCAD), 1995.

[6] R. E. Bryant and Y. A. Chen, “Verifi cation of arithmetic functions with binary moment diagrams,” in Proc. Design Automation Conf. (DAC), 1995, pp. 535–541. [7] R. Carmassi, M. Catelani, G. Iuculano, A. Liberatore, S. Manetti, and M. Marini, “Analog network testability measurement: a symbolic formulation approach,” IEEE Trans. Instrumentation and Measurement, vol. 40, pp. 930–935, Dec. 1991. [8] S.-M. Chang, J.-F. MacKey, and G. M. Wierzba, “Matrix reduction and numerical approximation during computation techniques for symbolic analog circuit analysis,” in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), 1992, pp. 1153–1156.

[9] H. Chapellat, M. Mansour, and S. P. Bhattacharyya, “Elementary proofs of some classical stability criteria,”IEEE transations on education, vol. 33, pp. 232–239, 1990.

[10] B. W. Char and et al, Maple V: Language Reference Manual. Springer-Verlag, 1991. [11] W. K. Chen, “Topological analysis for active networks,” IEEE Trans. Circuit Theory, vol. CT-12, pp. 85–91, Mar 1965. [12]

Applied Graph Theory: Graphs and Electrical Networks. Elsevier, 1976.

New York: American

274

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

[13] E. M. Clarke, M. Fujita, and X. Zhao, Multi-terminal binary decision diagrams and hybrid decision diagrams. Kluwer Academic Publishers, 1996, ch. 4 in book “Representations of Discrete Functions”, pp. 93–108. [14] C. L. Coates, “Flow-graph solutions of linear algebraic equations,” IRE transactions on circuit theory, vol. CT-6, pp. 170–187, 1959. [15] C. P. Coelho, J. R. Phillips, and L. M. Silveira, “A new proof of the Routh-Hurwitz stability criterion using the second method of Lyapunov,” in Proceedings of Cambridge philosophy society meeting, vol. 58, Nov. 1962, pp. 694–702. [16] J. Cong, L. He, C.-K. Koh, and P. Padden, “Performance optimization of VLSI interconnect layout,” Integration, the VLSI Journal, vol. 21, no. 1&2, pp. 1–94, Nov 1996. [17] T. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction to Algorithms. Cambridge, Massachusetts: The MIT Press, 1990. [18] W. Daems, G. Gielen, and W. Sansen, “Circuit simplifi cation for the symbolic analysis of analog integrated circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 4, pp. 395–407, April 2002. [19] W. Daems, W. Verhaegen, P. Wambacq, G. Gielen, and W. Sansen, “Evaluation of errorcontrol strategies for the linear symbolic analysis of analog integrated circuits,” IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol. 46, no. 5, pp. 594–606, May 1999. [20] A. Devgan, H. Ji, and W. Dai, “How to effi ciently capture on-chip inductance effects: introducing a new circuit element K,” in Proc. Int. Conf. on Computer Aided Design (ICCAD), 2000, pp. 150–155. [21] R. J. Duffi n, E. L. Peterson, and C. Zener, Geometric programming —theory and application. New York: John Wiley & Sons, Inc., 1967. [22] P. Elias and N. van der Meijs, “Including higher-order moments of RC interconnections in layout-to-circuit extraction,” in Proc. European Design and Test Conf. (DATE), 1996, pp. 362–366. [23] P. Feldmann and R. W. Freund, “Effi cient linear circuit analysis by pade approximation via the lanczos process,”IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 5, pp. 639–649, May 1995. [24]

“Reduced-order modeling of large linear subcircuits via block lanczos algorithm,” in Proc. Design Automation Conf. (DAC), 1995, pp. 376–380.

[25]

“Reduced-order modeling of large linear subcircuits by means of the sypvl algorithm,” in Proc. Int. Conf. on Computer Aided Design (ICCAD), 1996, pp. 280–287.

[26] A. Feliachi, “Control systems curriculum national survey,”IEEE Transactions on education, pp. 257–263, Aug. 1994. [27] F. V. Fernández, J. Martín, A. Rodríguez-Vázquez, and J. L. Huertas, “On simplifi cation techniques for symbolic analysis of analog integrated circuits,” in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), 1992, pp. 1149–1152.

REFERENCES

275

[28] F. V. Fernández and A. Rodríguez-Vázquez, “Symbolic analysis tools—the state of the art,” in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), 1996, pp. 798–801. [29] F. V. Fernández, A. Rodríguez-Vázquez, J. L. Hertas, and G. Gielen, Symbolic Analysis Techniques: Application to Analog Design Automation. IEEE Press, 1998. [30] F. V. Fernández, P. Wambacq, G. Gielen, A. Rodríguez-Vázquez, and W. Sansen, “Symbolic analysis of large analog integrated circuits by approximation during expression generation,” in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), 1994, pp. 25– 28. [31] H. Floberg, Symbolic Analysis in Analog Integrated Circuit Design. Massachusetts: Kluwer Academic Publisher, 1997. [32] G. E. Forsythe, M. A. Malcolm, and C. B. Moller, Computer methods for mathematical computations. Prentice-Hall, 1977. [33] F. R. Gantmacher, The theory of matrices. New York: Chelsea Pub. Co., 1959, vol. II. [34]

The Theory of Matrices, Vol.1. New York : Chelsea Pub. Co., 1977.

[35] A. George and J. W. Liu, Computer solution of large sparse positive defi nite systems. Englewood Cliffs, NJ: Prentice-Hall, 1981. [36] G. Gielen and R. Rutenbar, “Computer-aided design of analog and mixed-signal integrated circuits,” Proc. of IEEE, vol. 88, no. 12, pp. 703–717, Dec. 2000. [37] G. Gielen and W. Sansen, Symbolic Analysis for Automated Design of Analog Integrated Circuits. Kluwer Academic Publishers, 1991. [38] G. Gielen, P. Wambacq, and W. Sansen, “Symbolic analysis methods and applications for analog circuits: A tutorial overview,” Proc. of IEEE, vol. 82, no. 2, pp. 287–304, Feb. 1994. [39] E. A. Guillemin, The mathematics of circuit analysis; extensions to the mathematical training of electrical engineers, Principles of electrical engineering series. New York: J. Wiley, 1949. [40] M. M. Hassoun and P. M. Lin, “A new network approach to symbolic simulation of large-scale network,” in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), 1989, pp. 806–809. [41]

“A hierarchical network approach to symbolic analysis of large scale networks,” IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol. 42, no. 4, pp. 201–211, April 1995.

[42] J.-J. Hsu and C. Sechen, “DC small signal symbolic analysis of large analog integrated circuits,” IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol. 41, no. 12, pp. 817–828, Dec. 1994. [43] Y. Ismail and E. G. Friedman, “DTT: direct truncation of the transfer function – an alternative to moment matching for tree structured interconnect,”IEEE Trans. on ComputerAided Design of Integrated Circuits and Systems, vol. 21, no. 2, pp. 131–144, Feb. 2003.

276

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

[44] H. Ji, A. Devgan, and W. Dai, “Ksim: A stable and effi cient RKC simulator for capturing on-chip inductance effect,” in Proc. Asia South Pacific Design Automation Conf. (ASPDAC), 2001, pp. 379–384. [45] R. L. R. K. S. Brace and R. E. Byrant, “Effi cient implementation of a bdd package,” in Proc. Design Automation Conf. (DAC), 1990, pp. 40–45. [46] N. Kazarinoff, Geometric inequalities. New York: Random House, 1961. [47] E. Kuh and D. Pederson, Principles of Circuit Synthesis. 1959.

New York: McGraw-Hill,

[48] F. Leyn, G. Gielen, and W. Sansen, “Analog small-signal modeling - part I: behavioral signal path modeling for analog integrated circuits,”IEEE Trans. on Circuits and Systems II: analog and digital signal processing, vol. 48, no. 7, pp. 701–711, July 2001. [49]

“Analog small-signal modeling - part II: elementary transistor stages analyzed with behavioral signal path modeling,”IEEE Trans. on Circuits and Systems II: analog and digital signal processing, vol. 48, no. 7, pp. 701–711, July 2001.

[50] H. Liao and W. Dai, “Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels,” in Proc. Int. Conf. on Computer Aided Design (ICCAD), 1995, pp. 704–711. [51] H. Liao, R. Wang, R. Chandra, and W. Dai, “S-parameter based macro model of distributed-lumped networks using Padé approximation,” in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), 1993, pp. 2319–22. [52] J. Lillis, C. Cheng, S. Lin, and N. Chang, Interconnect analysis and synthesis. John Wiley, 1999. [53] P. M. Lin, Symbolic Network Analysis. Elsevier Science Publishers B.V., 1991. [54]

“Sensitivity analysis of large linear networks using symbolic program,” in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), 1992, pp. 1145–1148.

[55] J. W. Liu, “Modifi cation of the minimum degree algorithm by multiple elimination,” ACM Trans. Math. Software, vol. 11, pp. 141–153, 1985. [56] A. Manthe, L. Zhao, and C.-J. R. Shi, “Symbolic analysis of analog circuits with hard nonlinearity,” in Proc. Design Automation Conf. (DAC), 2003, pp. 542–545. [57] A. Manthe, L. Zhao, C.-J. R. Shi, and K. Mayaram, “Symbolic analysis of nonlinear analog circuits,”in Proc. European Design and Test Conf. (DATE), 2003, pp. 1108–1109. [58] S. J. Mason, “Feedback theory – some properties of signal flow graphs,” Proc. IRE, vol. 45, pp. 829–838, 1953. [59]

“Feedback theory —further properties of signal flow graphs,” Proceedings of IRE, vol. 44, pp. 920–926, July 1956.

[60] W. Mayeda and S. Seshu, “Topological formulas for networks,”in Engineering Experimentation Station Bulletin 446, 1957, university of Illinois, Urbana.

REFERENCES

277

[61] S. Minato, “Zero-suppressed bdds for set manipulation in combinatorial problems,” in Proc. Design Automation Conf. (DAC), 1993, pp. 272–277. [62]

Binary Decision Diagrams and Application for VLSI CAD. Boston: Kluwer Academic Publishers, 1996.

[63] L. W. Nagel, “SPICE2: A computer program to simulate semiconductor circuits,” Ph.D. dissertation, University of California, Berkeley, Berkeley CA, May 1975. [64] A. Odabasioglu, M. Celik, and L. Pileggi, “PRIMA: Passive reduced-order interconnect macromodeling algorithm,”IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 645–654, 1998. [65] A. Pacelli, “A local circuit topology for inductive parasitics,” in Proc. Int. Conf. on Computer Aided Design (ICCAD), 2002, pp. 208–214. [66] L. T. Pillage and R. A. Rohrer, “Asymptotic waveform evaluation for timing analysis,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 352– 366, April 1990. [67] L. T. Pillage, R. A. Rohrer, and C. Visweswariah, Electronic Circuit and System Simulation Methods. New York: McGraw-Hill, 1994. [68] Z. Qin and C.-K. Cheng, “RCLK-VJ network reduction with hurwitz polynomial approximation,” in Proc. Asia South Pacific Design Automation Conf. (ASPDAC), Jan. 2003, pp. 283–291. [69] Z. Qin and C. Cheng, “Realizable parasitic reduction using generalized Y — formation,” in Proc. Design Automation Conf. (DAC), 2003, pp. 220–225.

trans-

[70] T. Sasao and M. Fujita, Representations of Discrete Functions. Kluwer Academic Publishers, 1996. [71] M. Schetzen, The Volterra and Wiener Theory of Nonlinear Systems. New York: Wiley, 1981. [72] S. J. Seda, M. G. R. Degrauwe, and W. Fichtner, “A symbolic analysis tool for analog circuit design automation,” in Proc. Int. Conf. on Computer Aided Design (ICCAD), Nov. 1988, pp. 488–491. [73]

“Lazy-expansion symbolic expression approximation in synap,” in Proc. Int. Conf. on Computer Aided Design (ICCAD), Nov. 1992, pp. 310–317.

[74] B. N. Sheehan, “TICER: Realizable reduction of extracted RC circuits,” in Proc. Int. Conf. on Computer Aided Design (ICCAD), 1999, pp. 200–203. [75]

“Branch merge reduction of RLCM networks,” in Proc. Int. Conf. on Computer Aided Design (ICCAD), 2003, pp. 658–664.

[76] C.-J. Shi and X.-D. Tan, “Symbolic analysis of large analog circuits with determinant decision diagrams,”in Proc. Int. Conf. on Computer Aided Design (ICCAD), Nov. 1997, pp. 366–373.

278

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

[77]

“Canonical symbolic analysis of large analog circuits with determinant decision diagrams,”IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 1, pp. 1–18, Jan. 2000.

[78]

“Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 7, pp. 813–827, April 2001.

[79] M. Silveira, M. K. andI. Elfadel, and J. White, “A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits,” in Proc. Int. Conf. on Computer Aided Design (ICCAD), 1996, pp. 288–294. [80] M. Silveira, M. Kamon, and J. White, “Effi cient reduced-order modeling of frequencydependent coupling inductances associated with 3-D interconnect structures,” in Proc. Design Automation Conf. (DAC), June 1995, pp. 376–380. [81] J. A. Starzky and A. Konczykowska, “Flowgraph analysis of large electronic networks,” IEEE Trans. on Circuits and Systems, vol. 33, no. 3, pp. 302–315, March 1986. [82] S. X.-D. Tan, “A general s-domain hierarchical network reduction algorithm,” in Proc. Int. Conf. on Computer Aided Design (ICCAD), 2003, pp. 650–657. [83]

“A general hierarchical circuit modeling and simulation algorithm,”IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2005, (in press).

[84] S. X.-D. Tan, Z. Qi, and H. Li, “Hierarchical modeling and simulation of large analog circuits,” in Proc. European Design and Test Conf. (DATE), Feb. 2004, pp. 740–741. [85] S. X.-D. Tan and C.-J. Shi, “Effi cient DDD-based interpretable symbolic characterization of large analog circuits,” IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E86-A, no. 12, pp. 3112–3118, Dec. 2003. [86]

“Effi cient approximation of symbolic expressions for analog behavioral modeling and analysis,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 6, pp. 907–918, June 2004.

[87] S. X.-D. Tan and J. Yang, “Hurwitz stable model reduction for non-tree structured RLCK circuits,” in IEEE Int. System-on-Chip Conf. (SOC), 2003, pp. 239–242. [88] S. X.-D. Tan and C.-J. Shi, “Parametric analog behavioral modeling based on cancellation-free ddds,” in Proc. IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), Oct. 2002. [89] X. Tan and C.-J. Shi, “Hierarchical symbolic analysis of large analog circuits with determinant decision diagrams,” in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), vol. VI, 1998, pp. 318–321. [90] X.-D. Tan and C.-J. Shi, “Interpretable symbolic small-signal characterization of large analog circuits using determinant decision diagrams,” in Proc. European Design and Test Conf. (DATE), 1999, pp. 448–453. [91]

“Hierarchical symbolic analysis of large analog circuits via determinant decision diagrams,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 4, pp. 401–412, April 2000.

REFERENCES

279

[92] P. Vanassche, G. Gielen, and W. Sansen, “Symbolic modeling of periodically timevarying systems using harmonic transfer functions,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 9, pp. 1011–1024, Sept. 2002. [93] W. Verhaegen and G. Gielen, “Effi cient ddd-based symbolic analysis of large linear analog circuits,” in Proc. Design Automation Conf. (DAC), June 2001, pp. 139–144. [94]

“Symbolic distortion analysis of analog integrated circuits,” in Proc. European Conference on Circuit Theory and Design, Aug. 2001, pp. I.21–I.24.

[95]

“Symbolic determinant decision diagrams and their use for symbolic modeling of linear analog integrated circuits,”Kluwer International Journal on Analog Integrated Circuits and Signal Processing, vol. 31, no. 2, pp. 119–130, May 2002.

[96] J. Vlach and K. Singhal, Computer Methods for Circuit Analysis and Design. York, NY: Van Nostrand Reinhold, 1995.

New

[97] P. Wambacq, G. Gielen, and W. Sansen, “Symbolic simulation of harmonic distortion in analog integrated circuits with weak nonlinearities,”in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), May 1990, pp. 536–539. [98]

“A cancellation-free algorithm for the symbolic simulation of large analog circuits,” in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), May 1992, pp. 1157– 1160.

[99]

“A new reliable approximation method for expanded symbolic network functions,” in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), 1996, pp. 584–587.

[100] P. Wambacq and W. Sansen, Distortion Analysis of Analog Integrated Circuits. Kluwer Academic Publishers, 1998. [101] J. Yang and S. X.-D. Tan, “An effi cient algorithm for transient and distortion analysis of mildly nonlinear analog circuits,” in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2004, (to appear). [102] X. Yang, C.-K. Cheng, W. Ku, and R. Carragher, “Hurwitz stable reduced order modeling for RLC interconnect trees,” in Proc. Int. Conf. on Computer Aided Design (ICCAD), Nov. 2000, pp. 222–228. [103] M. Yannakakis, “Computing the minimum fill-in is np-complete,” SIAM Journal on discrete mathematics, pp. 77–79, 1981. [104] W. C. Yengst, Procedures of modern network synthesis. New York: Macmillan, 1964. [105] Z. You, E. Sánchez-Sinencio, and J. P. de Gyvez, “Analog system-level fault diagnosis based on a symbolic method in the frequency domain,” IEEE Trans. Instrumentation and Measurement, vol. 44, no. 1, pp. 28–35, Feb. 1995. [106] H. Yu and L. He, “Vector potential equivalent circuit based on PEEC inversion,”in Proc. Design Automation Conf. (DAC), 2003, pp. 781–723. [107] Q. Yu and C. Sechen, “A unifi ed approach to the approximate symbolic analysis of large analog integrated circuits,”IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol. 43, no. 8, pp. 656–669, Aug. 1996.

280

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

[108] G. Zhong, C. Koh, and K. Roy, “On-chip interconnect modeling by wire duplication,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 11, pp. 1521–1532, 2003.

Index

2-tree, 170 Absolute truncation error, 26 Adjoined merging, 58 Adjoint matrix, 247 Admittance matrix, 42 Admittance order, 249 Algebraic Decision Diagrams, 205 Align-term, 241 Approximation-after-generation, 226 Approximation-before-generation, 226 Approximation-during-generation, 226 Arnoldi method, 271 Arnoldi Transformation method, 271 Asymptotic Waveform Evaluation, 271 AWE, 271 Backward-solving, 85 BDD, 9 Behavioral modeling, 225 Binary decision diagram, 9 Binary Moment Diagrams, 205 Block transformation, 7 BMD, 205 Boundary variables, 246 Branch constitutive equation, 16 Branch constitutive relations, 155 Cancellation analysis, 253 circuit devices, 253 subcircuit reduction, 254 Cancellation due to addition, 266 Cancellation due to multiplication, 265 Cancellation-free, 227 Cancellation-free expressions, 249 Cancellation-free expressions, 262 Cancellation-free rational admittances, 261 Canonical, 187 Canonical property, 10, 200 Circuit realization, 13 Circuit’s impulse responses, 36 CMOS two-stage opamp circuit, 225 Coates’ fbw graph, 174

definition, 175 Coates’ gain formula, 176 CoeffConst, 217 Coefficient DDD, 214 CoeffMulplty, 218, 228 CoeffUnion, 218 Cofactor, 5, 29 Cofactor, 197 Cofactor Schur decomposition, 247 Combination set operations, 197 Combination sets, 185 Combination set system, 185 Common-factor cancellation, 248 conditions, 258 theoretical study, 257 Common-factor explanation of the effect, 77 hierarchical reduction, 248 recursive existence, 81 type-I, 78 type-Il, 79 Companion network, 46 Complementary linear program, 12 Complex frequency, 5 Composite admittance, 248 CompRafunc, 266 ComputeKDominantTerms, 230 Connection, 176 Connection gain, 176 Constant-admittance-order, 264 Convolution, 28 Cramer’s rule, 5 definition, 30 DDD, 10 1-edge, 190 cofactoring, 200 complex DDD, 215 construction, 200

282

SYMBOLIC ANALYSIS AND REDUCTION OF VLSI CIRCUITS

d0-edge, 190 definition, 190 evaluation, 200 related to other decision diagrams, 204 De-cancellation, 227 common-factor cancellation, 265 constant-admittance-order, 264 term cancellation, 264 recovery, 85 Determinant, 29 Directed loop, 176 Directed path, 176 Dominant term, 226 Driving-point impedance, 161 DTT,271 Dual function, 145 Dynamic programming, 228 Eigenvalue, 28 Elmore delay, 37 Evaluate, 197 Exact symbolic expressions, 261 First order realization, 141 Floating current source, 67 Flow-graph technique, 174 Fully expanded form, 211 Gauss elimination, 66 Gaussian elimination, 250 Geometric programming, 144 constraints, 146 GetKDomiTerms, 230 GetNextShortestPath, 235 Hierarchical model order reduction, 245 Hierarchical Network Modeling Algorithm, 250 High-order truncation, 72 Hurwitz polynomial, 117, 127 Hybrid Decision Diagrams, 205 Impedance, 6 Incidence matrix, 155 directed graph, 157 Incremental k-shortest path algorithm, 233 Internal matrix, 247 Internal variables, 246 Intersec, 197 ISAAC, 208 Jacobi matrix identity, 257 Kirchhoff’s current law, 16 Krylov space, 271 Laplace expansion, 192 Local node reduction, 271 Major, 170 Maple-V, 208 Mason’s gain formula, 174 Matrix, 29 Matrix-Determinant, 209 Matrix PVL, 271 MMD, 267 Model-order reduction, 6

Modifi ed nodal analysis, 21 Moment-matching, 46 Moments concept, 35 Moments: impulse response, 36 Moments MNA formulation, 41 RLC tree, 41 Multiple minimum degree, 267 Multiply, 197 Multi-rooted DDD, 214 Multi-Terminal Binary Decision Diagrams, 205 Native DDD, 229 Network transfer functions, 164 transfer impedance, 164 voltage-ratio transfer function, 164 Nodal analysis formulation, 10, 16 Node admittance matrix, 155 Node ordering, 73 Numerical Interpolation, 209 One-connection, 176 One-connection gain, 176 Open-Circuit Impedance, 162 Orthogonality condition, 146 Padé approximation, 38 Pade via Lanczos, 271 Parallel topology, 53 Parameter Extraction, 209 Partial fraction decomposition, 28, 40 Permutation, 178 definition, 178 Piecewise linear functions, 12 Positive real, 48 PRIMA, 271 Primal function, 145 Projection-based model-order reduction, 271 PVL, 271 RC circuit formulation, 16 Realizability of impedance, 47 Realizable circuit template, 143 Realizable reduction, 47 Relax, 235 Remainder, 197 Resistance shielding effect, 37 Reverse DDD, 232 RLC circuit formulation general RLC circuits, 20 special RLC circuits, 18 RLC 51 Roundoff error, 89, 91 Routh-Hurwitz stability criterion, 118 necessary and sufficient condition, 119 necessary condition, 118 proof, 123 Row-based expansion, 166 SCAPP, 208 Scattering parameter, 54

INDEX Schur complement, 247 Schur decomposition, 247 SDDD, 212 S domain analysis, 27 Self merging, 59 Sequence of expressions, 250 Series topology, 52 S-expanded DDD, 212 construction, 217 de-cancellation, 227 definition, 212 example, 212 vertex ordering, 215 S-expanded determinant decision diagram, 13 S-expanded form, 211 S-expanded polynomial, 211 Shortest path, 231 Signal-fbw diagram, 8 Signal-fbw graph, 174 Signal Flow Graph, 209 Sign rule, 189 Singular matrix, 17 S-Plane, 124 Stable polynomial, 117 Stable transfer function, 117, 138–139 Storage element, 6 Subcircuit suppression, 247 SubtractAndRelax, 235 Symbolic analysis, 3 Symbolic approximation, 240 Symbolic cancellation, 227 Symbolic Gaussian elimination, 272 Symbolic simplifi cation, 210 SyPVL, 271 Term cancellation, 227 definition, 248 Term generation, 226 TermSubtract, 197 Time domain analysis, 16 Time domain circuit response, 24 Taylor expansion, 24 Topological analysis, 8, 155

283 Topological formulas, 164 168 determinant, 165 Transfer function, 4 definition, 27 transfer function matrix, 27 Tree enumeration, 8 Tree Enumeration, 209 Two-stage CMOS Opamp, 238 UA741,207 Union, 197 Unrealizability of admittance, 142 Vector potential equivalent circuit, 272 VertexOne, 197 Vertex ordering, 187, 191 VertexZero, 197 Volerra functional series, 12 Volterra kernel, 12 VPEC, 272 YDDD, 251 YDDDConst, 263 YDDDMultiply, 265 Transformation, 7 transformation: classical, 65 transformation fidelity, 72 invariance, 74 multiport, 85 simplest form, 111 Y-expanded DDD, 251 construction, 263 definition, 262 Y-parameter, 56 ZBDD 0-edge, 185 0-terminal, 185 ZBDD, 187 1-edge, 185 1-path, 187 1-terminal, 185 Zero-suppressed Binary Decision Diagram, 186