Electrothermal Analysis Of Vlsi Systems

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

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ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Yi-Kan Cheng Motorola, Inc.

Ching-Han Tsai University of Illinois at Urbana-Champaign

Chin-Chi Teng Silicon Perspective Corporation

Sung-Mo (Steve) Kang University of Illinois at Urbana- Champaign

KLUWER ACADEMIC PUBLISHERS New York / Boston / Dordrecht / London / Moscow

eBook ISBN: Print ISBN:

0-306-47024-1 0-792-37861-X

©2002 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: and Kluwer's eBookstore at:

http://www.kluweronline.com http://www.ebooks.kluweronline.com

Contents

List of Figures List of Tables Preface Acknowledgments Part I

ix xv xvii xxi

THE BUILDING BLOCKS

1. INTRODUCTION 1.1. Electrothermal Phenomena in VLSI Systems 1.2. Introduction to Electrothermal Simulation 1.2.1 Overview of Electrothermal Simulation for ICs 1.3. ILLIADS-T: An Electrothermal Simulator for VLSI Systems 1.4. Overview of this Book

3 4 5 6 12 15

2. POWER ANALYSIS FOR CMOS CIRCUITS 2.1. Introduction 2.2. Sources of Power Consumption in CMOS Technology 2.2.1 Dynamic Power 2.2.2 Internal Power 2.2.3 Short-circuit Power 2.2.4 Leakage Power 2.3. Power Analysis Overview 2.4. Introduction to Power Analysis Techniques 2.4.1 Deterministic Power Analysis 2.4.2 Probabilistic Power Analysis 2.4.3 Statistical Power Analysis 2.4.4 Power Analysis for Sequential Circuits 2.5. Summary

21 21 21 22 23 24 25 28 29 29 30 33 37 39

3. TEMPERATURE-DEPENDENT MOS DEVICE MODELING 3.1. Introduction 3.2. Temperature-dependent Device Physics and Modeling

45 45 46

vi

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS 3.2.1 Temperature-dependent Threshold Voltage 3.2.2 Temperature-dependent Carrier Mobility 3.3. Temperature-dependent BSIM Model for SPICE Simulation 3.4. Regionwise Quadratic (RWQ) Model 3.4.1 Temperature-dependent Mobility Modeling 3.4.2 Extraction for RWQ Modeling 3.4.3 Mobility and RWQ Fitting Examples 3.5. Summary

46 47 48 51 53 54 54 57

4. THERMAL SIMULATION FOR VLSI SYSTEMS 4. 1. Introduction 4.2. Substrate/Package Modeling: An Overview 4.3. Formulation of Thermal Analysis 4.3. I Fast Thermal Analysis 4.3.2 Numerical Approach 4.3.3 Analytical Approach 4.3.4 Discussion 4.4. Package Simulation 4.4.1 Modeling of the Convective Boundaries 4.4.2 Modeling of Heat Flow Paths 4.5. Summary

61 61 64 65 65 72 79 82 83 83 84 88

5. FAST-TIMING ELECTROTHERMAL SIMULATION 5.1. Introduction 5.2. ILLIADS: A Fast Timing Simulator 5.2.1 Primitive Formation and Solutions 5.2.2 Simulation Strategies 5.2.3 Power Estimation using ILLIADS 5.3. Incremental Electrothermal Simulation in ILLIADS-T 5.4. Tester Chip Design and Calibration 5.5. Verification of ILLIADS-T 5.6. ILLIADS-T Simulation Examples 5.7. Summary

95

Part II

95 96 96 98 101 101 103 105 112 116

THE APPLICATIONS

6. TEMPERATURE-DEPENDENT ELECTROMIGRATION RELIABILITY 6.I . Motivation 6.2. Electromigration (EM) Physics 6.2.1 EM Lifetime Dependence on Current Density 6.2.2 EM Lifetime Dependence on Current Waveforms 6.2.3 EM Lifetime Dependence on Interconnect Width and Length 6.2.4 EM Model Used in the Book 6.3. EM Simulation: An Overview

121 121 122 123 124 127 129 129

Contents 6.4. ITEM: A Temperature-dependent EM Diagnosis Tool 6.4.1 Interconnect Temperature Estimation 6.4.2 Analytical Model of Interconnect Thermal System 6.4.3 Lumped Model of Interconnect Thermal System 6.4.4 iTEM Simulation Examples 6.5. Summary

vii 133 133 135 136 143 148

7. TEMPERATURE-DRIVEN CELL PLACEMENT 7.1. Introduction 7.2. Overview 7.3. Substrate Temperature Calculation 7.4. Compact Substrate Thermal Modeling 7.4.1 Transfer Thermal Resistance Matrix 7.4.2 Admittance Matrix Reduction 7.4.3 Runtime Efficiency of Compact Thermal Modeling 7.5. Thermal Placement Algorithms 7.5.1 Standard Cell Thermal Placement 7.5.2 Macrocell Thermal Placement 7.6. Simulation Examples 7.7. Summary

157 157 157 160 161 161 163 164 165 165 168 169 172

8. TEMPERATURE-DRIVEN POWER AND TIMING ANALYSIS 8.1. Introduction 8.2. Timing Analysis Overview 8.2.1 Dynamic Timing Analysis 8.2.2 Static Timing Analysis 8.2.3 Delay Modeling 8.3. Statistical Power Density Estimation 8.4. Monte-Carlo Power-Temperature Iteration Scheme 8.5. Temperature-dependent Gate and RC Delays 8.6. Simulation Examples 8.7. Summary

181 181 182 182 183 190 191 192 I94 194 199

Index

205

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List of Figures

1.1 1.2 1.3 1.4

1.5 1.6 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 3.1 3.2 3.3 3.4 3.5

Applications of electrothermal CAD tools. Elements of electrothermal simulations. Electrothermal simulation procedure in [I]. (a) An RC circuit example, (b) the dc circuit for the firstmoment generation, and (c) the dc circuit for finding the second moment. The integrator circuit used to implement the solution of the 3-D heat diffusion equation. Flowchart of ILLIADS-T electrothermal simulation. Illustration of dynamic power consumption in a CMOS inverter. Charging and discharging of an internal node of 2-input NOR gate. Short-circuit power for inverter with large load. Short-circuit power for inverter with small load. Leakage current at reversed-biased diode junction. Subthreshold leakage current. (a) Logic circuit without reconvergent fan-out, and (b) Logic circuit with reconvergent fan-out. A standard statistical power estimation flow. Relationship between F , a , and the confidence level. A generic sequential circuit. BSIM sensitive parameter subset approach. BSIM parameter value update using temperature coefficients. Regionwise partition of the (V DS , VGS E) plane. Fitted vs. extracted and (b) NMOSFET: (a) RWQ fitting result at 27 RWQ fitting result at 100 with mobility optimization.

5 6 7

10

11 13 22 23 25 26 26 27 32 34 35 37 50 52 53 55

55

I

x

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS 3.6 3.7 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.1 1 4.12

4.13 4. I4 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 5.1 5.2

5.3 5.4

PMOSFET: (a) RWQ fitting result at 27 oC, and (b) RWQ fitting result at 100 oC with mobility optimization. Figure A thermal simulation framework [2]. Illustration of effective heat transfer macromodeling. Method of images. Error function approximation. Transformation 1: Constrain the observation point to the first quadrant. Transformation 2: Constrain ta1 to be larger than tb1An FTA example. Chip structure and heat source locations. (a) Top view of the solid containing heat sources, and (b) 3-D view of grid point (i, j , k ). (a) Analogous thermal circuit to Fig. 4.9(a), and (b) thermal conductances from (i, j, k ) to adjacent grids. Analogy between thermal and electrical circuits. (a) Top view of a part of the chip comprised of composite materials, and (b) 3-D view of grid point (i, j, k). (a) Analogous thermal circuit to Fig. 4.12(a), and (b) thermal conductances from (i, j, k) to adjacent grids. Equivalent thermal circuit at the convective boundary. Speedup of FTA over numerical method. Layout of the solid containing three heat sources. Temperature profiles along the x direction at y = 500 pm for three different he values. Unit-level layout of a high-performance chip. Cross-sectional view of a flip-chip package. Equivalent thermal circuit of the flip-chip package. Method to determine the thermal resistances for heat flowing through the carrier aside to the lids. On-chip temperature contour for the first experiment. On-chip temperature contour for the second experiment. On-chip temperature contour for the third experiment. General MOS circuit primitive used in ILLIADS. Illustrations of SCC formation and topological sort: (a) the original circuit. (b) the digraph representation, and ( c ) the condensed digraph after topological sort. Example of transistor merging and internal node elimination. Primitive mapping for the circuit shown in Fig. 5.3 after the transistor merging process.

56 56 63 64 66 67 68 69 70 71 74 74 75

76 77 78 83 84 85 85 86 87 87 88 89 89 97

99 100

100

List of Figures

5.5 5.6 5.7

5.8 5.9 5.10 5.1 1 5.12 5.13 5.14

5.15 5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23 6.1 6.2 6.3

6.4 6.5 6.6 6.7 6.8 6.9 6.10

DCCB power calculation using ILLIADS. Convergence plot for power and temperature. Illustration of incremental latency: the nominal waveforms are shown in solid lines, while the perturbed waveforms are in dashed lines. Microphotograph of the tester chip; long blocks are Rosc 149s and short blocks are Rosc3s. Four-terminal configuration for diode measurement. Diode calibration example (D1). Simulated temperature profile for Expt. 2. Simulated temperature profile for Expt. 1. Comparison between simulated and measured temperatures for D1. Comparison between simulated and measured temperatures for D2. Comparison between simulated and measured temperatures for D3. (a) Measured and (b) simulated waveforms for Expt. 8. (a) Measured and (b) simulated waveforms for Expt. 7. (a) Measured and (b) simulated waveforms for Expt. 5 (a) Measured and (b) simulated waveforms for Expt. 1. Layout of the I0-bit negative adder. Layout of the simulated chip. Packaging structure used in the simulation example. Output waveforms of the I0-bit negative adder. The temperature effect on electromigration reliability. An example of a bidirectional pulsed current density waveform. Electromigration MTF as a function of interconnect width [ 14]. Microstructure of the interconnects. Electromigration MTF as a function of interconnect length. SPIDER [ 19] for the simulation of interconnect reliability. CURRANT representation of a 2-input NAND gate. A hierarchical environment for interconnect EM reliability diagnosis. Simulation flowchart of iTEM. The interconnect on insulator structure.

xi 101 102

103 104 105 106 107 107

108

108 109 109 110 110 111 112 113 1I 4 115 122 127 127 128 129 130 131 132 134 135

xii

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS 6.1 1

A T is a function of metal current density. The fol-

lowing parameters values are used to generate the data: ti = 2 pm, t = 0.5 pm, w = 2 pm, po = 3.6 x 10– 6 cm, ß = 4.04 x 10= ³ K=¹, Ki = 1.835 W/(K.m), and Ts = 300 K. 137 (a) Interconnect with contacts to substrate, and (b) the 6.12 corresponding temperature distribution from 3-D thermal simulation. Note that the interconnect temperature is reduced near the contacts and bond pads. 138 A lumped model of the interconnect thermal system. 139 6.13 A right-angle bend conductor. 140 6.14 A lumped model of the interconnect thermal system 6.15 near a via. 141 (a) Simulated interconnect structure with four contacts 6.1 6 to substrate. (b) Comparison of the thermal simulation 142 results using lumped thermal model and 3-D simulation. 6.17 (a) Simulated multi-layered interconnect structure. (b) Comparison of thermal simulation results using lumped thermal model and 3-D simulation. 143 6.18 Procedure of the interconnect temperature estimator. 144 6.19 Example of partitioning the interconnect layout in the interconnect temperature estimator. 144 6.20 The lumped thermal model for a transistor with multiple contacts . 145 6.21 Strategies for grouping contacts that are close to each other. 145 6.22 Simulation results of multiple contacts which are close to each other. 146 6.23 A layout of 10-bit negative adder. 146 147 6.24 The power/ground bus layout of 10-bit negative adder. iTEM simulation result of the 10-bit negative adder. 6.25 The number marked is the predicted electromigration MTF in hours. 147 The power and ground bus layouts of the 2-D discrete 6.26 cosine transformation chip. 148 iTEM simulation result of the 2-D discrete cosine trans6.27 formation chip. The number marked is the predicted electromigration MTF in hours. 149 7.l(a) Optimal heat distribution for a design with a core size 12mm x 12mm. The power density of the fixed cell near the lower-right corner of the layout is lower than the chip average. 158

List of Figures 7.1(b) Optimal temperature distribution resulting from the heat distribution in Fig. 7.1(a). 7.2 Block diagram of the thermal placement algorithm. 7.3 Revised simulated annealing algorithm for standard cell thermal placement. 7.4 Revised simulated annealing algorithm for macrocell thermal placement. 7.5(a) Temperature profiles of benchmark ami49 without thermal placement. The ambient temperature is assumed to be zero. 7.5(b) Temperature profiles of benchmark ami49 with thermal placement. The ambient temperature is assumed to be zero. 7.6 Histograms of on-chip temperatures of ami33 (a) before and (b) after thermal placement. 7.7 Histograms of on-chip temperatures of ami49 (a) before and (b) after thermal placement. 7.8 Histograms of on-chip temperatures of biomed (a) before and (b) after thermal placement. 7.9 Histograms of on-chip temperatures of primary 1 (a) before and (b) after thermal placement. 7.10 Histograms of on-chip temperatures of primary2 (a) before and (b) after thermal placement. 7.11 Histograms of on-chip temperatures of sp1 (a) before and (b) after thermal placement. 7.12 Histograms of on-chip temperatures of struct (a) before and (b) after thermal placement. 7.13 Histograms of on-chip temperatures of industry1 (a) before and (b) after thermal placement. 8.1 Relations between power, temperature, and timing. 8.2 Block diagram of static timing analysis. 8.3 An example circuit diagram. 8.4 Arrival time propagation in block-oriented analysis. 8.5 Required arrival time propagation in block-oriented analysis. 8.6 Slack calculation in block-oriented analysis. 8.7 A false path example. 8.8 Monte-Carlo power and temperature iteration scheme. 8.9 Example of a distributed RC tree. 8.10 Example of an equivalent model. 8.11 Thermal boundary conditions for temperature-dependent timing simulation.

xiii 159 165 167 169

172 173 174 174 175 175 176 176 177 177 182 184 185 186 188 189 189 193 195 195 196

xiv

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

8.12

The simulated temperature profile and the gate distribution of the longest path in C6288: The solid lines are the isothermal temperature contour and the small diamonds are the on-chip locations of gates in the longest path.

198

List of Tables

1.1

3.1 4.1 4.2 4.3 4.4 5.1 5.2 5.3 5.4 5.5 6.1 7.1 7.2 8.1 8.2 8.3

Trends of future microprocessor characteristics (ref: 1997 NTRS). Here the on-chip temperature is calculated assuming an ambient temperature of 75 oC. BSIM sensitive parameters Error function approximations. Eight cases under six constraints. Violation rate by using the FTA method. Definition of the symbols in Fig. 4.20. Activation status of Rosc3s. ILLIADS-T simulation results of the tester chip. ILLIADS-T simulation results. Packaging parameters for thermal simulation. ILLIADS-T simulation results. Simulation results of iTEM. Standard cell thermal placement simulation results. Macrocell thermal placement simulation results. The ISCAS85 benchmark circuits. Simulation results with dynamic timing analysis. Simulation results with static timing analysis.

4 50 68 69 71 86 106 111 113 114 115 150 170 170 196 197 198

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Preface

With increasing complexity of VLSI chips, the task of developing state of-the-art VLSI systems has become a highly challenging multidisciplinary task. Although in early days of MOS technology, silicon compilation looked promising, it has become difficult to fully automate the entire design flow from high-level design to mask generation due to many difficult physical design problems, including timing closure, power constraint, crosstalk, signal integrity, testability and reliability issues. In particular, the conventional practice of treating reliability qualification as a backend process has become no longer acceptable in view of excessive cost for design iterations. Attempts are under way to include reliability verification in the design flow so that expensive design iterations due to reliability problems can be avoided. With foresight Semiconductor Research Corporation has provided strong support on our research of “design for reliability” at the University of Illinois at Urbana-Champaign for over a decade. New models and CAD capabilities have been developed and transferred to industry to address some of the serious reliability problems such as electromigration (EM) in metallic interconnect electrostatic discharge (ESD) damages to I/O pads. With increasing concerns for on-chip power dissipation due to high packing density and high-frequency operation, electrothermal analysis has become critically important for accurate assessment of thermally activated device and circuit failures, and for timing analys i s . In this book we have attempted to provide in-depth coverage of important subjectsrequired for electrothermal analy of MOS VLSI circuits in an orderly manner. The underlying principles of circuit models and simulation algorithms in reliability CAD tools such as ILLIADS-T and iTEM are described in detail. For verification of design tool capability, chip design and bench test results are presented for electrothermal analysis of ring oscillators operating under digitally controlled thermal environment. We also present a "thermally skewed timing failure” phenomenon w i th det ailed simulation result. This subject has

xviii

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

not been discussed in any literature to our best knowledge, but such failures have been noticed by practicing VLSl design engineers. It is our sincere desire that readers will find the contents of this book useful for practice and also for furtherance of research in this challenging field. YI-KAN CHENG CHING-HAN TSAI CHIN-CHI TENG SUNG-MO (STEVE) KANG

To ECE and CSL of the University of Illinois at Urbana-Champaign, and to Semiconductor Research Corporation

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Acknowledgments

The authors wish to thank program managers of Semiconductor Research Corporation (SRC) and colleagues in semiconductor industry for their support, in particular Dr. Ralph Cavin, Dr. William Joyner, Dr. Justin Harlow of SRC, Dr. Charvaka Duvvury, Dr. P. B. Ghate of Texas Instruments, Dr. Ping Yang of Taiwan Semiconductor Manufacturing Company (TSMC), formerly of Texas Instruments, Dr. Shiuh-Wuu Lee of Intel Corporation. Authors also wish to acknowledge helpful discussions and encouragement from Profs. Elyse Rosenbaum, Timothy Trick, Ibrahim Hajj, Karl Hess, Ravi Iyer, Janak Patel of the University of Illinois at Urbana-Champaign, Profs. Chenming Hu, Ernest Kuh, Robert Brayton of the University of California at Berkeley. Prof. Ron Rohrer formerly of Carnegie-Mellon University, Prof. Stephen Director of the University of Michigan at Ann Arbor, and Dr. Herman Gummel of Lucent Technologies Ball Labs at Murray Hill have encouraged research on reliability-driven CAD. The Coordinated Science Laboratory under the directorship of Prof. W. Ken Jenkins and the Department of Electrical and Computer Engineering of the University of Illinois at Urbana-Champaign have provided excellent supports for research and preparation of this book. Finally, the authors would like to thank their parents - Dong-Pyng and ShiawChen Cheng, Hsiao-Lang and Mei-Hua Tsai, Yuan-Sun and Mei-Chu Teng their wives - Hui-Chun (Angie) Cheng, Pei-Tzu Teng, and Myoung A (Mia) Kang - Ching-Han’s friend - Kathy Chang - and their children - Jennifer and Jeffrey Kang - for their understanding and support during the writing of this book. Their love, patience and encouragement made this project possible. The authors express the deepest gratitude to them.

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Foreword

Continuing increases in the levels of circuit integration and concomitant increases in performance are sustaining the trend of increasing power dissipation in VLSI systems. A consequence is that the impact of temperature on the successful operation and reliability of devices must be comprehended during the design process. For the past decade, the authors have led an effort to provide a framework, accompanied by tools, for the electrothermal analysis and design of integrated circuits and systems. This is a challenging field driven by the enormous complexity of integrated circuits and by the need for tractable, predictive, and executable models of electrical and thermal interaction physics. This text provides a comprehensive formulation of the electrothermal analysis problem beginning with a summary of the sources of power dissipation i n CMOS circuits and followed by a formulation of the effect of temperature on MOS devices. A general framework for thermal simulation of integrated circuits and packages is presented and then the fast timing electrothermal simulator, ILLIADS-T, is described. Applications include the study of temperature dependent electromigration reliability, captured in the simulator iTEM, and the placement of cells so as to mitigate temperature effects. The text concludes with the description of a methodology to predict the effects of temperature on the timing of integrated circuits. The tools and methods described herein are finding widespread use in industrial applications by SRC members. We at the SRC are pleased to acknowledge the important contributions that have been made by the authors and expect that readers who are involved in electrothermal modeling will find the integrated perspective of this text to be very useful. Dr. Ralph K. Cavin, Vice President Semiconductor Research Corporation February 2000

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I

THE BUILDING BLOCKS

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Chapter 1

INTRODUCTION

When the chip integration level increases and the device feature size decreases, the die yield goes down in most cases. Furthermore, the overall chip performance degradation can be significant due to parasitic effects and the associated reliability problems. Consequently, the chip reliability and chip performance have become equally important in high-performance very-large scale-integrated (VLSI) system design. The commonly considered reliability issues in a VLSI system are: hot carrier induced degradation, oxide breakdown, electrostatic discharge (ESD), electrical overstress (EOS), and electromigration (EM). Most of these issues have been discussed in detail in many introductory or advanced books. This book is intended to address another emerging and important reliability problem in VLSI systems: electrothermal analysis of reliability and circuit performance.. The electrothermal problem has long been a major concern in analog circuit design because the bipolar circuits consume a large amount of power and have the potential thermal runaway problem. Since current VLSI systems mainly consist of MOS devices, the power consumption is comparatively low and the electrothermal problem is seemingly not a threat. Unfortunately, it is not true when the technology scaling continues to be the trend of VLSI system design.

In the following, the electrothermal phenomena in a VLSI system are described. An overview of the generic electrothermal analysis flow is presented. The existing electrothermal analysis methods are also reviewed. Finally, the organization of this book is given.

4

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Table I . I . Trends of future microprocessor characteristics (ref: I997 NTRS). Here the on-chip temperature is calculated assuming an ambient temperature of 75 oC.

1.1.

ELECTROTHERMAL PHENOMENA IN VLSI SYSTEMS

Due to the increasing packing density, higher operating speed, and larger scale of integration, the power density and on-chip temperature in integrated circuits continue to increase. For instance, the trend of future microprocessor characteristics is depicted in Table 1.1, which is extracted from the 1997 National Technology Roadmap for Semiconductors (NTRS). Table 1.1 shows the projection of the maximum power and the size of the chip. The operating temperatures are estimated by using the following formula:

(1.1)

where Ti is the internal average chip temperature, Ta is the ambient temperature, Ptotal is the total power consumption of the design, and R t h is the equivalent thermal resistance of the packaging components (oC/W) . The on-chip temperature of the packaged VLSI circuit not only can reach as high as 100 oC on average, but also can vary by as much as a few tens of degrees from one location to another. Because the failure rate of microelectronic devices depends heavily on the localized operating temperature, hot spots due to high local-power dissipation have become a long-term integrated-circuit (IC) reliability concern i n diverse applications such as high-performance microprocessors and digital signal-processing chips. Because of the complexity of a VLSI chip, the verification of chip performance at various operating temperatures relies heavily on computer simulations. Once the temperature profile is determined, several important issues shown in Fig. 1.1 can be addressed. It is clear that the thermal engineering can be used not only for reliability checking, but also as an additional degree of freedom for enhancing the circuit performance.

INTRODUCTION

Figure 1.1.

1.2.

5

Applications of electrothermal CAD tools.

INTRODUCTION TO ELECTROTHERMAL SIMULATION

Electrothermal simulation consists of electrical and thermal simulations. The purpose of electrical simulation is to obtain the information on power dissipation and the performance of devices or circuits. On the other hand, the thermal simulation is used to find the temperature profile and to update all the temperature-dependent physical parameters of the the device or circuit model. This is illustrated in Fig. 1.2. The loop in Fig. 1.2 forms the basic mechanism of electrothermal simulation. The electrical and thermal relationships must b e self-consistent for the system to remain stable. Otherwise the thermal runaway effects may occur.

6

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 1 . 2 .

1.2.1

Elements of electrothermal simulations.

OVERVIEW OF ELECTROTHERMAL SIMULATION FOR ICS

Fukahori and Gray [ I ] comprehensively addressed the simulation of ICs in the presence of electrothermal interaction. Their focus was on the analog circuits where thermal feedback can severely degrade the circuit performance and distort the voltage transfer characteristics. The electrothermal simulation procedure in [I] is illustrated in Fig. 1.3. A coupled set of nonlinear electrothermal equations is first generated. Next, those equations are represented by a matrix form and then linearized and solved by using the Newton-Raphson method. The linearized circuit matrix contains three parts:

1. Elements corresponding to the electrical circuit (Yv)

INTRODUCTION

7

Solution at t Figure 1.3.

Electrothermal simulation procedure in [1 ].

2. Elements corresponding to the thermal circuit (Yth )

3 . Elements corresponding to the coupling between the two circuits The thermal circuit was generated by using the finite-difference method (FDM) for the simplified die-header structure. Elements corresponding to the coupling between the two circuits are the thermally controlled current sources corresponding to the temperature effects on the electrical physical parameters, and the electrically controlled power sources corresponding to the power dependence of the node voltages.

8

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Once the matrix is solved and the dc solution is found at time t , as illustrated in Fig. 1.3, the transient solution of the temperature and the node voltage can be found by utilizing the preferred integration formula. In [ I ] , the trapezoidal integration technique was employed. The above procedures are similar to those used in the circuit simulation programs such as SPICE [2]. The electrothermal simulator in [ I ] was applied to several analog circuits for the prediction of electrothermal interactions, both in dc transfer characteristics and in transient response. It was also pointed out that the simulation time was typically a factor of ten greater than the case when only the electrical effects were considered. In 1982, a transistor-level electrothermal simulator was developed by Latif et al. [3]. It aimed at finding the temperature-dependent behaviors of power bipolar transistors. Each simulated device was partitioned into n x m (in 2-D case) sections connected in parallel by appropriate base resistors, where each section operated at its own temperature. A temperature-dependent EbersMoll model was used for each section. This model included the effects of avalanche multiplication, basewidth modulation, and current gain variations. The thermal network of the device was generated by using the 3-D finitedifference approach. Two numerical techniques were proposed in [3] to solve the coupled electrothermal circuits. The first one was called the direct method, which is similar to the method proposed earlier in [l]. The second technique was called the relaxation method. This method divided the original problem into electrical and thermal systems. They were solved separately and the solutions were obtained by applying successive relaxation between the two systems. Both techniques have their own advantages and disadvantages. The direct method is more general and powerful for analyzing different problems such as dc, transient, and dc transfer characteristics. However, it is computationally more expensive and may not be able to handle all nonlinearities of the system. The relaxation method is more efficient, but convergence problems can occur under some biasing conditions. Lee et al. developed a coupled electrothermal simulator for ICs in 1993 [4]. Its purpose was similar to that of [ l], but with the focus on improving the simulation efficiency while preserving the accuracy. For dc analysis, the incomplete Cholesky conjugate gradient (ICCG) method[5] was used. For the transient analysis, the macromodeling method based on asymptotic waveform evaluation (AWE) [6] was employed. The ICCG method is one of the relaxation methods that does not require the expensive LU factorization process to solve the network matrix as in the direct method. Combining incomplete Cholesky decomposition and conjugate gradient optimization, the ICCG method is known to be very efficient in solving symmetric and diagonally dominant systems such as 3-D interconnect structures or 3-D thermal networks. Simulation results for a 741 operational

INTRODUCTION

9

amplifier showed that the CPU time saved was 93% by using the ICCG method compared to the direct method [4]. More CPU and memory savings are expected for larger circuits. AWE is a technique to find the time-domain response of a linear system by utilizing a reduced set of approximate poles and residues in the frequencydomain transfer function. These poles and residues are determined by applying a moment-matching method such as the Pade approximation [7]. The manner in which moments for a linear system are calculated is to successively perform the dc analysis of the system. For example, consider the RC circuit in Fig. 1.4(a). The first set of moments of the circuit is found by transforming the circuit in Fig. 1.4(a) into Fig. I .4(b), replacing capacitors with zero-valued constantcurrent sources, and calculating the voltages across the current sources. The voltages m c1, mC2 , and mC 3 in Fig. 1.4(b) are the resulting first set of moments. The successive generations of higher-order moments are accomplished by setting the driver to zero and replacing each current source with the product of its previous moment and capacitance value. For illustration, the second set of moments for the circuit in Fig. 1.4(a) is found as shown in Fig. 1.4(c). Once the poles and residues are found by moment matching, transient response of the system can be subsequently calculated. A linear thermal system can always be described in terms of the state equations in Eq. (1.2),

(1.2) where x is the state vector, u is the input vector, y is the output vector, and D is the vector related to the electrothermal coupling. Therefore, the AWE technique can be directly applied to this system to obtain the transient temperature response, which is computationally much more efficient when compared to a conventional time-domain integration method such as in SPICE. The transient electrothermal simulation was performed on the 741 operational amplifier, and the CPU time saved by using the AWE technique was about 85% in comparison to the trapezoidal integration method [4]. Transient simulations were done by Lee et al. for both bulk silicon and silicon-on-insulator (SOI) technologies, and the comparison of thermal effects between the two technologies was made. A new circuit-level electrothermal simulator, iETSIM, was introduced by Diaz et al. in 1994 [8]. It simulates the transient electrothermal effects, with an emphasis on the electrical overstress (EOS) and electrostatic discharge (ESD) applications. ESD is one of the most prevalent causes for IC failures due to the short-duration high-current stress. Under such a stress, the breakdown of a device can occur. Because the second breakdown is thermally originated, electrothermal simulation is essential for an accurate ESD-induced failure analysis. iETSIM is a coupled transient electrothermal simulator. To find the node voltages and circuit temperatures, a set of coupled electrothermal equations

10

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

(c) Figure 1.4. (a) An RC circuit example, (b) the dc circuit for the first-moment generation, and (c) the dc circuit for finding the second moment.

INTRODUCTION

Figure 1.5 equation

11

The integrator circuit used to implement the solution of the 3-D heat diffusion

is formed and solved by using the standard modified nodal analysis (MNA) technique as shown in Fig. 1.3. For the electrical part, a new model and algorithm for avalanche breakdown were developed for accurate ESD/EOS simulation. This new algorithm was shown to be much simpler, more robust and more efficient than the algorithms introduced earlier in [9]. For the thermal part, a novel temperature model based on an electrical analog implementation of the time-dependent 3-D heat-diffusion equation was developed. It employed the solution of the 3-D heat-diffusion equation derived by Dwyer et al. [10]. For a heat source with dimensions a x b x c and a constant power value P 0 , the transient temperature distribution due to this source can be written as [10]

(1.3) In Eq. (1.3 ), the location of the observation point with respect to the center of the heat source, T0 is the ambient temperature, p is the mass density, Cp is the specific heat, and G (x ,a ,T ) , G ( y , b , T), and G (z, c, T ) are the Green’s functions. In IETSIM, the integral over time in Eq. (1.3) is evaluated by using an electrical equivalent integrator circuit shown in Fig. 1.5. In this circuit, a power monitor (P 0) and a time-dependent resistor (R) are provided to convert power to the temperature rise above the ambient temperature T0 .The time-dependent resistor can be obtained from Eq. (1.3) and is given as

(1.4) where C is chosen so that the matrix entries become more even, and its typical value is 1 pF.

12

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

With the implementation in Fig. 1.5, iETSIM is more efficient than the relaxation method in [3] , especially when the circuit contains more than one device or when the temperature gradient is steep under ESD stress. In order to simulate the complete coupling between various heat sources in an ESD protection circuit, the current summation property of the integrator can be used as suggested by the superposition principle [8]. Recently iETSIM has been extended to handle the temperature calculation of devices with time-varying power dissipation values. In this case, the device temperature is given by the following convolution equation:

Numerically computing the convolution equation in Eq. (1.5) is expensive. For the sake of efficiency, regionwise exponential (RWE) approximation is applied to the Green's functions in Eq. (1.5), in order to perform the convolution recursively for temperature calculation. Readers may refer to [11] for further details.

1.3.

ILLIADS-T: AN ELECTROTHERMAL SIMULATOR FOR VLSI SYSTEMS

A fast-timing simulation based electrothermal simulator, called ILLIADS-T, was developed [12]. ILLIADS-T was designed to simulate the digital VLSI circuits. The flowchart of ILLIADS-T simulation procedure is shown in Fig. 1.6. The main features of ILLIADS-T are listed below.

1. To achieve the computational time efficiency required by large circuits, ILLIADS-T uses a fast-timing simulator, ILLIADS (ILLInois Analogous Digital Simulator) [13], to calculate the power dissipated by each logic gate. Each gate is then viewed as a heat source in thermal simulation. ILLIADS has the following advantages: The speedup of ILLIADS over SPICE-like programs increases linearly with the circuit size as measured in terms of the transistor count The speedup can be further enhanced by introducing the incremental electrothermal simulation technique [14 ] an accurate temperature-dependent modeling method for the MOS device was developed based on the regionwise quadratic (RWQ) modeling technique [15]. With this method, the accuracy of delay and power values estimated by ILLIADS is comparable to SPICE for a wide range of temperatures (27 oC - 12 0 oC.

2. The coupled electrothermal simulation methods such as those introduced earlier are time consuming. The total simulation time is first divided into

INTRODUCTION

Figure 1.6.

13

Flowchart of ILLIADS-T electrothermal simulation.

many small time intervals, then the power and temperature values are updated and coupled for each time interval. This kind of approach is ideal only for transient simulation on small circuits. ILLIADS-T, which is designed to find the chip-level steady-state temperature distribution and the resulting circuit performance, uses a much more feasible approach for VLSI circuits. It starts with an initial guess of the average chip temperature and then calculates the average power for each gate based on the current waveform drawn from the power supply. Next, the gate power values are fed to the thermal simulator to estimate the temperature profile. The temperature profile is then used to update the device model parameters for the second round of power calculation. This process continues until convergence is obtained and the steady-state temperature profile is found. The above approach decouples the power and temperature calculation. The decoupling strategy is justified by the fact that the time required for the onchip temperature to reach steady state (i.e., thermal time constant) is several orders of magnitude longer than the clock signal period (i.e., electrical time constant) in digital circuits [16]. In other words, the chip temperature does not immediately follow the instantaneous power dissipation, and thus the

14

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS average power instead of the instantaneous power is used in the steady-state temperature calculation in ILLIADS-T.

3. Previous electrothermal simulators were developed mainly for the temperature profile estimation of SSI or MSI circuits [ l , 4, 8], therefore the thermal boundary conditions were simplified. Moreover, the 1-D/2-D thermal simulations were usually adopted. For VLSI/ULSI chips with complex packaging structures, the simplified boundary conditions and 1-D/2-D approaches may not be valid. To handle this problem, a thermal simulation framework, iTEMP, has been built in ILLIADS-T to solve the 3-D heat equations for the chip substrate and to model the packages and heat sinks as effective thermal resistances. iTEMP can handle various thermal boundary conditions at any side of the chip with no limitations. A hierarchical approach was also developed in this thermal simulation framework in order to quickly identify the on-chip hot spots and to subsequently pinpoint the hot-spot temperatures.

4. The chip temperature can be found with full top-down automation. Once the chip dimensions, packaging materials, device I-V data and thermal parameters are specified by the user, ILLIADS-T requires only the layout description file (e.g., CIF or GDSII format) to find the steady-state temperature profile and the corresponding circuit performance and reliability.

5. By using the RWQ modeling technique instead of the complex MOS models as in [17], temperature-dependent power and delay estimation can be done in ILLIADS-T even when only measured data are available and the MOS models have not been fully developed or characterized. This makes ILLIADS-T device-model-independent, and thus applicable to the advanced CMOS technologies. Referring back to Fig. 1.6, the primary input to ILLIADS-T is the layout description file of the target VLSI chip. A layout extractor has been developed to obtain the electrical circuit that the layout represents. as well as to identify the location of each device. A standard device specification in the netlist generated by the layout extractor in ILLIADS-T is shown below: MOS-name ND NG NS NB MODEL-name (L=VAL) (W=VAL) (AD=VAL) (AS=VAL) (PD=VAL) (PS=VAL) XMIN YMIN XMAX YMAX where XMIN, YMIN, XMAX, and YMAX define the bounding box of a MOS device layout, and MODEL-name specifies a particular RWQ model for a MOS device. ILLIADS-T then calculates the bounds of each logic gate according to the coordinates of the bounding boxes of MOS devices within this gate. Next, the

INTRODUCTION

15

average power dissipation from each gate at the initial temperature is calculated by ILLIADS. iTEMP will take as input the power values and the coordinates of heat sources to calculate the on-chip temperature profile by solving the heat equations. In particular, the average temperature of each gate is found. At this stage, each gate has its updated local temperature and ILLIADS must be rerun to find the new average power values under the new temperature distribution. This iterative procedure stops when the updated temperature of each gate no longer has any significant change from the previous value. Empirical results shown in [12] indicate that this process is efficient and usually converges within two or three iterations. Note that in CMOS circuits, the short-circuit power can account for approximately 25% of the total IC power consumption [ 18]. The temperature-induced variations of the short-circuit power and/or the switching activity are what necessitate a few iterations during ILLIADS-T simulation.

1.4.

OVERVIEW OF THIS BOOK

This book addresses the issues related to electrothermal problems in modem VLSI designs from the modeling and simulation perspectives. It is intended to cover the most important electrothermal reliability and performance issues that can be encountered in VLSI system design. Solid-state transistors, interconnects, logic gates, macros, chips, and packages, are all temperature-sensitive VLSI design objects that will be covered in this book. The first few chapters are designed to present the fundamental building blocks in an electrothermal simulation environment. Chapter 2 discusses the power analysis methods. As shown in Fig. 1.2, power analysis is used to determine the amount of power dissipation to be used in thermal analysis. Therefore, it is the very first building blockin electrothermal analysis. Chapter 2 starts with the introduction of sources of power consumption in a CMOS circuit, followed by three different power analysis techniques. These three techniques have their own advantages and disadvantages, which will be addressed and compared in detail. In Chapter 3 , the temperature-dependent MOS device modeling is presented. The temperature-dependent modeling of the threshold voltage and the channel carrier mobility of a MOS transistor is given. The three scattering mechanisms that determine the carrier mobility in the solid are also described. Two temperature-dependent MOS device models are presented. The first one is the BSIM model, which is based on the sensitivity analysis of the sensitive parameters in the original BSIM model. The second one is the RWQ model, which is based on the regionwise fitting to the experimental data and the inclusion of the scattering mechanisms in mobility modeling. Chapter 4 concentrates on thermal analysis for VLSI systems. This chapter begins with the introduction of the heat equation and the common thermal boundary conditions. A complete thermal simulation framework is presented.

16

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

This framework includes a fast thermal simulator, a numerical thermal simulator, an analytical thermal simulator, and a package thermal simulator. The mathematical formulations of the solutions to these thermal simulation methods are discussed. Examples of simulating the VLSI system using these methods are also given. Chapter 5 focuses on the discussion of the fast-timing electrothermal simulation. A fast timing simulator developed at the University of Illinois at Urbana-Champaign, ILLIADS, is first presented. A fast-timing electrothermal simulator, ILLIADS-T, was developed by combining ILLIADS with the thermal simulation framework discussed in Chapter 4. An incremental simulation strategy used in ILLIADS-T is illustrated in this chapter. A tester chip was designed for verifying the accuracy of ILLIADS-T. The details of the tester chip design, experimental setup, tester chip calibration, and chip temperature measurement, are presented. The experimental results are compared with the ILLIADS-T simulation results. Finally, a number of circuits are simulated, and the impact of the thermal effect on the circuit performance is examined. The last three chapters in this book address three important applications of the electrothermal analysis, based upon the building blocks discussed in previous chapters. In Chapter 6, the temperature-dependent electromigration diagnosis method is presented. The chapter first illustrates how significantly the interconnect temperature affects its electromigration mean time to failure, followed by the introduction of the electromigration phenomena. The dependence of the electromigration lifetime on the current density, current waveforms, and the metal length and width, is described. Based one the dependence, a electromigration model suitable for circuit simulation is presented. Next, the overview of existing electromigration analysis methods is given. Finally, a temperature-dependent electromigration diagnosis tool developed at the University of Illinois at Urbana-Champaign, called iTEM, is discussed. A lumped thermal model used to find the temperatures of the multilayered interconnect system is developed and discussed. Finally, a number of circuits are simulated using iTEM. The electromigration mean time to failure is predicted by iTEM, and the importance of including interconnect temperature in the analysis is demonstrated. Chapter 7 addresses the issues related to temperature-driven cell placement for uniform substrate thermal distribution. Two approaches for deriving the compact substrate thermal model are illustrated. The first approach employs the superposition principle to construct a transfer thermal resistance matrix, and the second approach involves the direct manipulation of the nodal matrix equation. The comparison of runtime efficiency of these two approaches is given. Two thermal placement algorithms, one suitable for the standard-cell placement and the other suitable for the macrocell placement, are presented and discussed. The algorithms have been tested on many benchmark circuits.

References

17

The thermal placement results show that, in general, the temperature profile is improved at the cost of longer simulation time. The total wire length and area after thermal placement are also compared with those generated by the conventional placement algorithm (i.e., no temperature is considered). In Chapter 8, an integrated framework for temperature-driven power and timing analysis is presented. Since power and timing are closely related, they are treated together in this chapter. The relationship between power, temperature, and timing will be explained. An overview of timing analysis is given in order to show its importance to VLSI system design. Two timing analysis methods are introduced: dynamic method and static method. Dynamic timing analysis uses user-specified input patterns to simulate the circuit delay. It is the most accurate way of predicting path timing. Static timing analysis is conceptually very different from the dynamic analysis in that no input patterns are required. The false-path problem associated with the static timing analysis is examined and different solutions are provided. Two distinct approaches in static timing analysis, path-oriented approach and block-oriented approach, are presented. Because the block-oriented approach is extremely efficient and widely used in high-performance VLSI design, it will be the focus of our discussion. The step-by-step illustration of how to calculate the arrival times, the required times, and the slacks in the block-oriented approach is given. All of the above timing analysis methods will be compared. Next, the delay modeling for timing analysis is discussed. The temperature dependence of the gate and interconnect delay will also be addressed. A statistical technique for estimating average power of each logic gate in the circuit is presented. The estimated average power are used to find the nominal on-chip temperature distribution by utilizing a power-temperature iteration scheme. This two-level iteration scheme will be described. Finally, the experimental results are demonstrated. The nominal temperatures are statistically estimated and the timings of the benchmark circuits are found by using both dynamic and static timing analysis methods. It will be shown that the on-chip temperature rise and temperature gradient can cause different critical path and critical timing in comparison to the case where a uniform temperature distribution is assumed.

References [l] K. Fukahori and P. R. Gray, “Computer simulation of integrated circuits in the presence of electrothermal interaction,” IEEE Journal of Solid-State Circuits, vol. 11, pp. 834-846, Dec. 1976.

[2] L. W. Nagel, SPICE2: A Computer Program to Simulate Semiconductor Circuits. PhD thesis, Dept. of Electrical Engineering, Univ. of California at Berkeley, 1975.

18

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

[3] M. Latif and P. R. Bryant, “Network analysis approach to multidimensional modeling of transistors including thermal effects,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 94-101, Apr. 1982. [4] S. S. Lee and D. J. Allstot. “Electrothermal simulation of integrated circuits,” IEEE Journal of Solid-State Circuits, vol. 28, pp. 1283-1293, Dec. 1993. [5] J. A. Meijerink and H. A. van der Vorst, Mathematics of Computation, vol. 31, pp. 148-162, 1977. [6] L. T. Pillage and R. A. Rohrer, “Asymptotic waveform evaluation for timing analysis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, pp. 352-366, Apr. 1990. [7] G. A. Baker Jr., Essentials of Pade Approximants. New York, N Y Academic Press, 1975. [8] C. H. Diaz, S. M. Kang, and C. Duvvury, “Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, pp. 482-493, Apr. 1994. [9] C. H. Diaz and S. M . Kang, “New algorithms for circuit simulation of device breakdown,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, pp. 1344-1354, Nov. 1992. [10] V. Dwyer, A. Franklin, and D. Campbell, “Thermal failure in semiconductor devices,” Solid-State Electronics, vol. 33 , pp. 553-560, May 1990. [11] T. Li, C. H. Tsai, and S. M. Kang, “Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstress,” in Proceedings of the ACM/IEEE International Conference on Computer-Aided Design, pp. 6-11, NOV. 1998. [12] Y. K. Cheng, P. Raha., C. C. Teng, E. Rosenbaum, and S. M. Kang, “ILLIADS-T: An electrothermal timing simulator for temperaturesensitive reliability diagnosis of CMOS VLSI chips,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, pp. 668-681, Aug. 1998.

[13] Y. H. Shih, Y. Leblebici, and S. M. Kang, “ILLIADS: A fast timing and reliability simulator for digital MOS circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, pp. 1387-1402, Sept. 1993.

References

19

[14] Y. K. Cheng and S. M. Kang, “Improvement on Chip-Level Electrothermal Simulator - ILLIADS-T,” in Proceedings of the IEEE International Symposium on Circuits and Systems, May 1996. [l5] A. Dharehoudhury, S. M. Kang, K. H. Kim, and S. H. Lee, “Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics,” in Proceedings of the ACM/IEEE International Conference on Computer-Aided Design, pp. 208-211, Nov. 1994. [I6] R. Darveaux, I. Turlik, L. T. Hwang, and A. Reisman, “Thermal stress analysis of a multichip package design,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 12, pp. 663-672, Dec. 1989. [17] C. P. Wan and B. J. Sheu, “Temperature dependence modeling for MOS VLSI circuit simulation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8 , pp. 1065-1 073, Oct. 1989.

[18] A. M. Hill, Switching Density Analysis for Power and Reliability in VLSI Circuits. PhD thesis, Dept. of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, 1996.

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Chapter 2 POWER ANALYSIS FOR CMOS CIRCUITS

2.1.

INTRODUCTION

To calculate the on-chip temperature profile, according to Fig. 1.2, the power distribution must be calculated first. Because of the increasing use of portable electronic applications such as cellular phone, laptop computers and personal digital assistant (PDA) devices, low power is the trend for modem processor design in order to reduce the chip temperature and to prolong the operation time between two battery charge-ups. Without proper thermal engineering, the overheating in VLSI chips can degrade the circuit performance and reduce the chip life time. For those high-power chips, temperature control must be done by using costly packaging materials and efficient heat-dissipating structures. Because power management is important, power analysis has become indispensable for VLSI design and is one of fields that is currently under extensive investigation. A common goal of power analysis is to accurately and efficiently calculate the power consumption of the system under analysis. In this chapter, several power analysis methods will be described. First, the definition of power dissipation in CMOS circuits and the common sources of power consumption will be discussed in the following section.

2.2.

SOURCES OF POWER CONSUMPTION IN CMOS TECHNOLOGY

A CMOS digital circuit always consumes power whether its logic state undergoes dynamic transitions or remains unchanged. Its power consumption is comprised of the following four components: dynamic (switching) power internal power

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

22

Figure 2.1.

Illustration of dynamic power consumption in a CMOS inverter.

short-circuit power leakage power The cause of each component and the significance of its contribution to the total power consumption will be explained as follows.

2.2.1

DYNAMIC POWER

Dynamic power occurs when the output of the CMOS logic gate switches. During the switch, the output parasitic capacitances are either charged up to the supply voltage level or discharged to the ground level (See Fig. 2.1). During the charge-up phase, half of the energy supplied by the power source is stored in the output loading capacitance. The other half has been dissipated by the PMOS transistor. During the discharge phase, the remaining charge is removed from the capacitor and its energy is dissipated by the NMOS transistor. The average dynamic power consumption of a logic gate can be expressed as (2.1) where VD D is the power supply voltage, f clk is the global clock frequency, E(transitions) is the expected number of transitions per clock cycle at the gate output, and (2.2)

POWER ANALYSIS FOR CMOS CIRCUITS

Figure 2.2.

Charging and discharging of an internal node of 2-input NOR gate.

i Here, C G is the gate capacitance of the ith fanout and C wire is the interconnect capacitance of the driven net. Dynamic power is used for the logic evaluation by propagating the output states of logic gates. Therefore the dynamic power must be consumed in order to realize the functionality of a circuit. Given a processing technology and a functional description, there exists a theoretical lower bound of the power that must be consumed. This lower bound is determined by the amount of computation and is independent of the implementation [l, 2, 3, 4]. In a reasonably designed circuit, dynamic switching power usually accounts for the major portion of the total power consumption [ 5 ] .

2.2.2

INTERNAL POWER

When the inputs of a logic gate are switching, it is possible that certain internal capacitances are charged or discharged without changing the output logic states. When this occurs, the internal power is consumed. One example is shown in Fig. 2.2 [6], where a two-input NOR gate is considered. If the inputs V 1 and V2 are changing from 01 at t 1 to 10 at t 2 , the output remains unchanged at state 0. However, after t2 ,the capacitance at node i is discharged. The internal power consumption happens at the internal nodes of the logic gate, therefore it cannot be captured by the dynamic switching power model in

23

24

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Eq. (2.1). The internal power of a logic gate can be calculated as

(2.3) where N i n is the number of internal nodes, C Si D is the source/drain capacitance of the internal node i, and Ei (transitions) is the expected number of transitions at node i . Note that Eq. (2.3) is very similar to Eq. (2.1) except that the power consumption is measured at the internal nodes instead of the output node. From Eq. (2.3) it can be seen that when the source/drain capacitance is large or when the number of internal nodes in a circuit is big, the internal power consumption can be considerable. A recent study [6] showed that the internal power is on average ~16% of the power consumption due to the gate capacitances. However, in the deep-submicron technologies, the internal power usually accounts for less than 5% of the total power consumption [ 5 ]. This is because the interconnect capacitance becomes dominant in the parasitic loading in comparison with the transistor capacitance.

2.2.3

SHORT- CIRCUIT POWER

Another source of power dissipation in a CMOS circuit is the direct flow of current from power source to ground. It is called the short-circuit power, which occurs when both the NMOS and PMOS transistors are conducting simultaneously. Such a path should never exist in a dynamic circuit because the precharge and evaluate transistors should never be on at the same time, or malfunction will occur. Ideally, if a CMOS logic gate is driven by step input signals, either PMOS or NMOS transistors (but not both) will be conducting at a time. Unfortunately, input signals always have nonzero transition time because o f the nonzero loading of the previous logic stage. Let us consider a CMOS inverter containing an NMOS transistor with threshold voltage VT,n and a PMOS transistor with threshold voltage VT ,p. During transition, when the voltage of the input signal V I N satisfies (2.4) both transistors are on and the short-circuit power is consumed. The total amount of short-circuit power dissipation is a function of the on-time of the transistors and the operating modes of the devices. Short-circuit power estimation has attracted many research interests in recent years [7, 8, 9, 10, 11]. Although it is difficult to derive an exact formula that is valid for all operating conditions in a circuit, simple expressions have been derived for some special cases. For instance, considering an unloaded inverter

POWER ANALYSIS FOR CMOS CIRCUITS

Figure 2 .3.

25

Short-circuit power for invecter with large load.

with V T ,n = VT , p = VT , the short-circuit power can be calculated as [7]:

(2.5) where p is the MOS transistor gain factor and T I S the input transition time. Note that the input transition time determines the length of the period during which Eq. (2.4) holds. The longer T is, the more the short-circuit power is consumed. Now let us qualitatively consider the impact of the loading capacitance on short-circuit current. In Fig. 2.3, the large output loading causes the output transition to be slow. Under such circumstances, the input signal moves through the transient period before the output starts to change. As a result, the PMOS is off and only a small amount of short-circuit current is carried. The opposite case is given in Fig. 2.4, where the small output loading causes immediate output transition. A considerable amount of short-circuit current will flow since the drain-source voltage of the PMOS transistor equals V DD for most of the transition period. From the above discussion, it can be concluded that the short-circuit power of a gate is minimized if the output rise/fall time is larger than the input rise/fall time. A common practice to minimize the short-circuit power of a circuit in a global way, however, is to match the rise/fall times of the input and output signals for every logic gate [7].

2.2.4

LEAKAGE POWER

All of the power components described above manifest themselves when a circuit is switching. Ideally there should be no power consumption if the circuit i s in steady state. However, there is always a leakage current flowing

26

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 2.4.

Figure 2.5.

Short-circuit power for inverter with small load.

Leakage current at reversed-biased diode junction.

through the reverse-biased diode junctions of the transistors located between the source or drain and the substrate, as depicted in Fig. 2.5. The resulting power consumption is called the diode leakage power. The magnitude of the diode leakage current can be expressed as

(2.6) where AD is the drain diffusion area and Js is the leakage current density. Since the leakage current saturates at relatively small reverse bias potential, it is

POWER ANALYSIS FOR CMOS CIRCUITS

Figure 2.6.

27

Subthreshold leakage current.

roughly independent of the supply voltage. Moreover, the diode leakage current is caused by the thermally generated carriers. Therefore, its value increases exponentially with the increasing junction temperature. Since the diode leakage current is generally small compared with other power components, it is often ignored in power estimation. A more important source of leakage current is the subthreshold leakage current, and the resulting power consumption is called the subthreshold leakage power . An MOS transistor can experience a drain-source current even when the gate-source voltage is smaller than the threshold voltage, as shown in Fig. 2.6. The closer the threshold voltage is to zero volts, the greater the leakage current. In the subthreshold regime, an MOS transistor behave similarly to a bipolar transistor, and its I - V characteristics can be described by [12]:

(2.7) where K is a function of the technology, V t is the thermal voltage ( K T / q ) , VT is the threshold voltage and n = 1 where t ox is the gate oxide thickness, D is the channel depletion width, and = E s i/E o x . It can be seen that as VT decreases, the magnitude of the subthreshold leakage current grows exponentially. In order to offset this effect, the threshold voltage of the MOS transistors is generally kept above a certain level (e.g., 0.5 V). Technology s caling tends to lower the power supply voltage. I n order to maintain or even increase the driving capability of the transistor current and thus the circuit speed, the threshold voltage needs to be scaled down as

+

28

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

well. However, doing so increases the subthreshold leakage power, which is undesirable in the low power design. To solve the above dilemma, the dual-VT technology is widely employed for the high-performance processor design. In such a design, the high-VT devices are generally used for low power. For devices on the timing critical paths, however, the low-V T technology is used. For both sources of leakage (i.e., diode leakage and subthreshold leakage), their power dissipation can be expressed by

Pleakage = Ileakage x V DD

(2.8)

where IIeakage is denotes either I d l in Eq. (2.6) or I st in Eq. (2.7). Since the leakage power could contribute significantly to the total power consumption, several CAD tools have been developed for analyzing [13] and optimizing [ 14] the leakage power.

2.3.

POWER ANALYSIS OVERVIEW

In general, a power analysis tool can be classified based on one of the following criteria: Analysis Levels: architectural level, register transfer level (RTL), gate level, and transistor level, etc. Analysis Engines: SPICE, fast-timing, switch-level, etc. Analysis Techniques: deterministic, probabilistic, statistical, etc. For the analysis levels, the tradeoff between the efficiency and the accuracy needs to be considered. The models with a higher level provide a design space with more degree of freedom for the reduction of power consumption [15]. As a result, a high-level model should be employed at the early design stage for its larger potential for power saving. On the other hand, due to its lack of design details, the accuracy of power estimation from high-level models is limited. Therefore, a good power management strategy should be: (1) Perform the power analysis at high level first in order to reduce the power consumption aggressively for the low-power design; (2) Perform low-level analysis next in order to enable further power reduction with high accuracy. The choice of analysis engines in power analysis is again mainly determined by the tradeoffs between the simulation speed and the simulation accuracy. The SPICE-like simulators, although relatively slow in comparison with other general-purpose circuit simulators, offer the highest accuracy by directly solving the circuit nodal equations at the transistor level. Since there is no model simplification or approximation, exact transient simulation is done and thus the timing is well monitored. The importance of the timing information to power analysis is twofold. Firstly, the switching power is proportional to the running

POWER ANALYSIS FOR CMOS CIRCUITS

29

frequency (timing) of the chip. Secondly, the toggle power (due to the transient behaviors of signals before they are stable) are transient in nature, therefore the signal timing needs to be closely captured. A novel power estimation method using SPICE as the analysis engine is the power meter technique [16], where the transient current drawn from the power supply is obtained by adding extra circuit elements to the original netlist. In order to improve computational efficiency, several other analysis engines such as fast timing simulator [17] and gate-level (logic) simulator [18] were used in power analysis. Because those simulators use groups of transistors as the basic simulation units, approximations must be made and certain loss of accuracy cannot be avoided. The development of the power analysis techniques for improving the accuracy and efficiency of power estimation is still an important research area. In the rest of this chapter, the three distinct techniques, i.e., deterministic, probabilistic, and statistical techniques, will be described and discussed. The focus of the discussion will be on the statistical technique because of its accuracy, efficiency and simplicity.

2.4. 2.4.1

INTRODUCTION TO POWER ANALYSIS TECHNIQUES DETERMINISTIC POWER ANALYSIS

The deterministic technique, being strongly input pattern dependent, takes the user-specified primary input vectors and performs analysis at the specific level with the preferred analysis engine. This technique is clearly accurate because the inputs are known a priori. How the input vectors are collected and how many input sequences are needed to be representative are beyond the concerns of the deterministic technique. However, the input patterns can be generated exhaustively for all combination of possible input logic transitions when the total number of inputs is small, or are gathered for specific applications that are described by a sequence of architectural instructions. For the latter, it is often of great interest to provide the instructions that cause the maximum power (worst case). To generate such instructions in a processor design environment, for instance, the following constraints need to be considered: Number of instructions that can be dispatched per cycle Availability of various buffers and queues Execution time of various instructions Post dispatch serialization The deterministic technique is exact as long as the design details are available. Unfortunately, it may not always be the case. Often the power analysis

30

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

needs to be done for one block in early design phase before any other blocks in a chip are defined or completely specified. Therefore, usually the exact input specification is not available. In addition, when a chip needs to be qualified with its power rating, one may want to ensure that certain requirements are always met irrespective of the applications. For those cases, weakly input pattern dependent techniques, such as the probabilistic and statistical techniques, are preferred.

2.4.2

PROBABILISTIC POWER ANALYSIS

The probabilistic power analysis technique, simply put, is a way of calculating power by propagating the probability of logic transitions starting at the primary inputs. Because there are no exact input patterns required (i.e., only probabilities are required), it requires only one simulation run. Since no repeated simulation runs are necessary, it is computationally very efficient. One common limitation of the probabilistic techniques, however, is that they all require special delay models. The special delay models prohibit the use of existing simulation tools and libraries. Moreover, those models can significantly hinder the simulation accuracy. To describe the concept of probabilistic techniques, we start with the following definitions:

Spatial Independence. Signals at the primary inputs or internal nodes in a circuit may be correlated. For instance, they may never be simultaneously high or low due to the logic topology. If the signal correlation is ignored in simulation, we call that the spatial independence is assumed. Temporal Independence. Signal x at clock cycle T may be correlated to signal X at clock cycle (T +1). For instance, the oscillator circuits expect to change state for every clock cycle. If the temporal correlation is ignored in simulation, we call that the temporal independence is assumed. Signal Probability. The signal probability Ps ( x ) at node x is the average fraction of clock cycles in which the stable logic value of x is high.

a

Transition Probability. The transition probability a—b(x) at node x is the average fraction of clock cycles in which the logic value of x transitions from a to b. For instance, a o +l stands for the probability of the logic transition from 0 to 1. Formally, a0 +1 is defined as

(2.9)

POWER ANALYSIS FOR CMOS CIRCUITS where n ( N ) is the number of 0

31

1 transitions in N clock cycles.

The probabilistic power analysis technique was first proposed in [19]. Both spatial and temporal independence was assumed in this original work. Consider a logic AND gate with the following boolean expression: z = (a . b ) where . represents the AND operation. From the basic probability theory, if signals at input a and b are spatially independent, then Ps ( z ) = Ps (a) . Ps ( b ) , where Ps (.) is the signal probability defined above. Similarly for a logic OR operation with the boolean expression z = (a + b), the signal probability of z is (2.10) To calculate the average power consumption in a circuit, the following formula can be used: (2.11) where fc l k is the clock frequency, C L ( x i ) is the load capacitance at node xi , and n is the total number of output nodes (of the logic gates) in the circuit. It is assumed that the dynamic switching power is dominant when using Eq. (2.11) to estimate the total power. Given the temporal independence assumption, a 0 1 can be computed in the following way. Consider a static 2-input NOR gate with the Boolean expression z = a + b. Its transition probability is given by

(2.12) where (2.13) Assuming Ps (a) = Ps (b) = 0.5, the transition probability at the output of the NOR gate is 3/16. Note that the transition probability a 0 1 depends on the logic styles (e.g., static logic, dynamic logic, etc). Equations (2.12) and (2.13) are valid only for the static NOR gate. For the dynamic logic, power is only dissipated when the output is switching from 1 to 0 during evaluation. As a result, the transition probability at the output of the dynamic NOR gate is 3/4. The above analysis technique propagates the probability values from the primary inputs forward to the primary outputs. It is extremely fast because it takes advantage of the assumption of the signal spatial independence. Unfortunately, this assumption is rarely valid in real circuits, where the reconvergent

32

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

(a)

(b)

Figure 2.7. (a) Logic circuit without reconvergent fan-out, and (b) Logic circuit with reconvergent fan-out.

fan-out exists. Figure 2.7 illustrates this situation. In Fig. 2.7(a), signals at nodes C and B are independent, therefore the above probabilistic technique can be directly applied to find the signal and transition probabilities at node Z. In Fig. 2.7(b), however, the reconvergent fan-out exists. Signals at nodes B and C are inter-dependent because they all depend on the signal at node A. To analyze such a circuit, the described probabilistic technique needs to be extended by considering the conditional probabilities. Since the signal interdependence substantially complicates the correlation between signals, CAD tools are required for such analysis. After the advent of the first probability-based power analysis tool, many other probabilistic approaches have been developed that aimed to improve the simulation accuracy. In [20], probability waveforms are specified at the primary input instead of fixed probability values. A probability waveform indicates the time period at which the signal logic is high, and the probability of signal transition from low to high at specific time points. With probability waveforms, the assumption of temporal independence is removed, and hence the accuracy is improved. Similarly, the equilibrium probability and transition density are specified at the primary inputs in [21] to eliminate the temporal independence assumption. Both techniques in [20] and [21] still assume the spatial independence among signals. The technique proposed in [22], which is based on the Binary Decision Diagram (BDD), attempts to handle both spatial and temporal correlations without the independence assumptions. As a result, it is very accurate compared to the previously developed probabilistic techniques. However, since BDD grows very rapidly and may even break down with increasing circuit size, its usefulness is mainly limited to moderate sized circuits.

POWER ANALYSIS FOR CMOS CIRCUITS

2.4.3

33

STATISTICAL POWER ANALYSIS

The statistical technique for power analysis is an attractive choice among others because of its efficiency, accuracy, and simplicity. Its efficiency, although not as good as the probabilistic techniques, makes simulation of big circuits possible. It can be easily implemented in existing simulators. The idea behind the statistical technique is to repeatedly simulate the circuit while monitoring the power being consumed. To proceed with our discussion, the following definition and statistical law are given first:

Sample Mean. Let . . . , x n be a random sample of size n from some distribution with mean and variance The sample mean, denoted is defined as the random variable obtained as the following arithmetic average: (2.14)

Law of Large Numbers. As the number of random sample n increases, the gets tightened around its distribution mean distribution of the sample mean In the limit, it can be expressed as (2.15) The Law of Large Numbers is the fundamental principle behind the statistical technique. It illustrates how the repeated simulation can estimate the average value mean) of a random variable, as long as the number of samples is large enough. In order to obtain the statistical measure of the transition activities (power) in a circuit, the statistical characteristics of the primary inputs must be specified. An input pattern generator is then used to generate the input vectors for the statistical simulation based on the given input characteristics. The next outstanding question is, how many input vectors are enough. Or, how many random samples do we need at least so that the Law of Large Numbers holds. A statistical power analysis tool addresses the above question. A standard statistical power estimation flow is shown in Fig. Detailed implementation of each component in this flow varies among different analysis tools. For the circuit simulation part, one can choose from any of the analysis engines described earlier in this chapter. For the input pattern generation part, if the statistical characteristics of the input is unknown at the time of power estimation or the input stream does not contain signal correlations, it is usually sufficient to use a random number generator. Alternatively, the input vectors can be directly drawn from the input stream pool if provided. The statistical measurement block in Fig. 2.8 is needed in order to collect and update the statistical data. Next, the stopping criterion is used to determine

34

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 2.8.

A standard statistical power estimation flow.

whether the average power estimated thus far is close enough (converged) to the real value. If it is, the repeated simulation is terminated and the average power value is reported. Otherwise, another input pattern will be generated for the next round of circuit simulation. For simulation efficiency, it is crucial that the stopping criterion will result in the sample size as small as possible, while the required accuracy is achieved. To derive a stopping criterion, the central limit theorem and the concept of confidence level are often used [23]:

POWER ANALYSIS FOR CMOS CIRCUITS

Figure 2.9.

Relationship between F , a , and the confidence level.

Central Limit Theorem. If , form a random sample from an arbitrary distribution, with mean p and variance and if is their sample mean, then (2.16) where P is the probability and I(x ) is the cumulative distribution function (cdf) of the standard normal distribution. In other words, the random variable has the standard normal distribution for large n..

Confidence Level. If a random variable x has cdf F (. ), and 0 <_ a <_ 1, then the of F ( . ) ,denoted F a , is a real number such that:

P{x _ < Fa } = a.

(2.17)

It then follows that (2. I8) (2.19) and

(2.20) The above equation can be interpreted as follows: With (1 - a )confidence, the inequality F a / 2 < x <_ F 1 - a / 2 is valid (See also Fig. 2.9). Given that has the standard normal distribution for large n (central limit theorem) and from Eq. (2.20) ,it follows that (2.21)

35

36 Since

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS =

(See Fig. 2.9), Eq. (2.21) can be recast to

(2.22)

where is the user specified error tolerance. Equation (2.22) can be readily used as a stopping criterion for the statistical power estimation: Once users specify and the the confidence level (1 a) ,the minimally required number of repeated simulations (i.e., n) can be calculated according to Eq. (2.20). Note that for the standard normal distribution, is well tabulated and can be easily calculated. McPower [24] was developed to statistically estimate the total average power of a circuit by using the Monte-Carlo simulation. It is assumed in this approach that the power consumed by a circuit over time has a distribution close to normal. Based on this assumption, a set of stopping criterion similar to Eq. (2.22) is derived for the given confidence level and percentage error. This approach assumes no spatial and temporal independence for internal nodes. It only requires that the primary inputs be independent and do not change with time in statistical characteristics. Another statistical technique, called MED [25], wasdeveloped for estimating the average power of each gate in a circuit. It is an attractive technique because it provides a very useful piece of information: power density i.e., power consumption per unit area. This localized information is essential for electrothermal simulation to find the hot spots caused by the gates (or macros) with high power density. The MED approach is conceptually similar to McPower, except for its stopping criteria. Two stopping criteria are needed in MED for good convergence rate, one for the normal gates and the other for gates with very few logic transitions. The details of the MED approach and its application to the electrothermal simulation environment will be presented in Chapter 8 for the temperature-driven power and timing analysis. The McPower-like approaches assume that the average power follows the normal distribution based on the central limit theorem. Such approaches are called the parametric approaches because they are designed by employing the properties of certain statistical distribution function. Another approach, called the nonparametric approach, was proposed in [26] for estimating the average power of a circuit. It is a reliable alternative for average power analysis because no up-front statistical distribution function of the average power is assumed. It was shown that the nonparametric approach can generate more accurate and robust average estimates with higher simulation costs. –

POWER ANALYSIS FOR CMOS CIRCUITS

Figure 2.10.

2.4.4

37

A generic sequential circuit.

POWER ANALYSIS FOR SEQUENTIAL CIRCUITS

All of the above power analysis techniques either assume certain input statistics, or at minimum assume that the inputs are independent. Those are reasonable assumptions for combinational circuits because unless exact input vectors are specified as in the deterministic approach, the circuit’s input patterns are unknown by nature. For sequential circuits, however, none of the above approaches can be directly applied. In order to implement a finite-state machine (FSM), a sequential circuit contains latches and feedback loops, thus introducing spatio-temporal correlations among the latch output signals. It is shown in Fig. 2.10, where the present state lines form the secondary inputs to the combinational circuit. Because the present state lines are the outputs of latches, they are not necessarily independent and must be characterized. Power and switching activity estimation for sequential circuits are significantly more difficult than for combinational circuits because the number of states in an FSM increases exponentially with the number of latches. To reduce the complexity of power analysis for sequential circuits to a manageable level, it is convenient to partition the circuits and perform power analysis for the

38

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

latches and the combinational blocks separately. Most existing probabilistic or statistical power analysis techniques for combinational circuits introduced earlier can be directly utilized, and the only extra information needed is the transition probability or statistics of the latch outputs (secondary inputs). This information can be gathered by either solving the state equations or by logic simulation. In the following, a brief overview of some distinct techniques is presented. In [27], a n exact probabilistic method for estimating the sequential circuit power with the given state transition graph (STG) of the FSM, is presented. The state probabilities (i.e., probability for an FSM being in a particular state) are first calculated by iteratively solving the Chapman-Kolmogorov equations [28]. Using these probabilities, the exact signal probabilities (i.e., probability of a signal being logic high) and transition probabilities (i.e., probability of a signal that will switch) are calculated by an implicit state enumeration procedure. The average power can then be directly found from the transition probabilities. Although this exact method is computational very expensive and thus its usefulness is severely limited by the circuit size, many subsequent approximation approaches are based on its formulation. In [27] , a n approximation method is presented, which solves the nonlinear system equations to find the present state line probabilities. This nonlinear system is represented by P ns = F( P p s) , where Pps and Pns are vectors of the state line probabilities for present state and next state, respectively. The function F ( . ) is a nonlinear function determined by the Boolean equation of the combinational logic shown in Fig. 2.10; F ( . ) can be obtained from a BDD. From Fig. 2.10 it can be seen that the present state lines are the outputs of latches, therefore = Pns = P, and the nonlinear equation can be reduced to P = F ( P ) . This system is then solved by applying the Picard-Peano iteration method. In order to correct the assumption that the presented state lines are independent, the authors in [27] proposed a method to unroll and cascade the combinational logic k times such that the effect of the independence assumption becomes mild. A totally new approach for power analysis in sequential circuits is described in [29], which is based on a statistical estimation technique. By applying randomly generated input sequences to the circuit, statistics on the latch outputs are collected by logic simulation. Like statistical techniques developed for the combinational circuits, a set of stopping criteria determining how many random samples are needed and how long (in terms of clock cycles) the FSM needs to be simulated for each sample, are derived for the sequential circuits. After the statistics of the latch outputs are collected, it is then possible to use any of the existing combinational circuit techniques to compute the total circuit power. One important advantage of this approach is that the desired accuracy of the simulation results can be specified upfront by users.

POWER ANALYSIS FOR CMOS CIRCUITS

39

In [30], another statistical technique was proposed for sequential circuit power estimation. An initial transient problem was investigated and a solution was provided. In an FSM, a set of states is said to be closed if no state outside can be reached from any state in it. If such a closed set does exist and if the randomly generated initial state of the FSM is in this set, the estimated power can be severely biased. In other words, the estimated power with the initial state in closed set S1 may be very different from the one with he initial state in closed set S 2 . The above is called the initial transient problem. A concept of warm-up period is given in [30] to address the initial transient problem. In theory, the state of an FSM at time k becomes independent of its initial state at time 0 as k assuming that all logic signals are non-periodic. The warm-up period is the period of time that the FSM has to be simulated before its power values is independent of the initial state. Therefore, the power data should be collected only after the warm-up period for each sample. In [3 1], a nonparametric statistical approach for sequential circuit power analysis is presented. The concept of warm-up period is also visited and the length of warm-up period is determined by the hypothesis test for randomness. A hypothesis test determines whether or not a power sequence is a random sample by the statistical measure of that sequence. Given a specified significance level, if the hypothesis is accepted at a trial independence interval, the sequence can be viewed as a random sample. Otherwise the trial interval is increased to reduce the temporal correlation. These steps are repeated in an iterative manner until the randomness hypothesis is accepted and the selected interval is used hereafter to generate random power samples. Next, the stopping criterion based on the order-statistics is used to analyze the sample data and control the sample size until the desired accuracy is achieved. In addition to high accuracy by considering all signal correlations, the simulation efficiency is also greatly improved by choosing the independence interval dynamically.

2. 5.

SUMMARY

This chapter provides an overview of various power analysis techniques for CMOS circuits. The estimated power values can be used by thermal analysis to calculate the temperature distribution. Sources of power consumption in CMOS technology are described:

-

Dynamic (switching) power Internal power Short-circuit power Leakage power

Three different criteria based on which a power analysis tool can be classified are introduced:

40

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

-

Analysis level

-

Analysis engine

-

Analysis technique

The deterministic power analysis technique is first presented. A number of constraints that need to be considered when generating a good set of input vectors are given. The limitation of this technique due to its input pattern dependence is described. The probabilistic power analysis technique is presented. Some assumptions that are commonly used in this technique are provided. The definition of signal probability and transition probability is also given. Examples of calculating the signal probability and transition probability for simple logic gates are provided. Reconvergent fan-outs in a circuit is considered for finding the (conditional) probabilities. Finally, different probabilistic power analysis tools are compared. The statistical power analysis technique is presented. Some commonly used statistical terms and theorems are provided. A standard statistical power analysis flow is shown. Based on the central limit theorem, the stopping (convergence) criterion is derived so that the repeated simulation is terminated while the specified accuracy level is reached. Two branches of statistical power analysis techniques are also described: parametric and nonparametric techniques. Different statistical power analysis tools are presented. The above power analysis techniques are revisited for analyzing the sequential circuits. Because the sequential circuit contains memory elements and feedbacks, the inputs to the circuits can no longer be assumed independent. A number of approaches used to take into account such spatio-temporal correlations are illustrated.

References [l] N. R . Shanbhag, “Lower bounds on power-dissipation for dsp algorithms,” in Proceedings of the International Symposium on Low Power Electronics and Design, pp. 43-48, 1996.

[2] A. Tyagi, “Entropic bounds on fsm switching,” in Proceedings of the International Symposium on Low Power Electronics and Design, pp. 323-328, 1996.

References

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[3] S. Ramprasad, N. R . Shanbhag, and I. N. Hajj, “Achievable bounds on signal transition activity,” in Proceedings of the ACM/IEEE International Conference on Computer-Aided Design, pp. 126-129, 1997. [4] D. Marculescu, R. Marculescu, and M. Pedram, “Theoretical bounds for switching activity analysis in finite-state machines,” in Proceedings of the International Symposium on Low Power Electronics and Design, pp. 3641, 1998. [ 5 ] L . P. Yuan, Power and voltage drop analyses in VLSI circuits. PhD thesis, Dept. of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, 1999.

[6] C. Y. Tsui, M. Pedram, and A. M. Despain, “Power efficient technology decomposition and mapping under an extended power consumption model,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 9, pp. 1110-1122, 1985. [7] H. J. M. Veendrick, “Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits,” IEEE Journal of Solid-State circuits, vol. 19, no. 8, pp. 468-473, 1984. [8] N. Hedenstierna and K. O. Jeppson, “CMOS circuit speed and buffer optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 6 , no. 2, pp. 270-28 I, 1987. [9] T. Sakurai and A. R. Newton, “Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas,” IEEE Journal of Solid-State Circuits, vol. 25, no. 2, pp. 584-594, 1990.

[10] S. R. Vemuru and N. Scheinberg, “Short-circuit power dissipation estimation for CMOS logic gates,” IEEE Transactions on Circuits and Systems, vol. 41, no. 1 1 , pp. 762-765, 1994.

[ I I] A. Alvandpour, P. Larsson-Edefors, and C. Svensson, “Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits,” in Proceedings of the International Symposium on Low Power Electronics and Design, pp. 245-258, 1998. [12 ] A. Chandrakasan, I. Yang, C. Vieri, and D. Antoniadis, “Design consideration and tools for low-voltage digital system design,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 1 13-1 18, 1996. [I3] Z. Chen, M. Johnson, L. Wei, and K. Roy, “Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor

42

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS stacks,” in Proceedings of the International Symposium on Low Power Electronics and Design, pp. 239-244, 1998.

[14] J. P. Halter and E Najm, “A gate-level leakage power reduction method for ultra-low-power CMOS circuits,” in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 475-478, 1997. [15] M. Nemani and F. Najm, “High-level area and power estimation for VLSI

circuits,” IEEE Transactions on Computer-Aided Design of Integrated Cir cuits and Systems, vol. 18, no. 6, pp. 697-713, 1999. [16] S. M. Kang, “Accurate simulation of power dissipation in VLSI circuits,”

IEEE Journal of Solid-State Circuits, vol. 21, pp. 889-891, Oct. 1986.

[17] Y. K. Cheng, P. Raha., C. C. Teng, E. Rosenbaum, and S . M. Kang, “ILLIADS-T: An electrothermal timing simulator for temperaturesensitive reliability diagnosis of CMOS VLSI chips,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, pp. 668-681, Aug. 1998. [18] F. Dresig, P. Lanches, O. Rettig, and U. G. Baitinger, “Simulation and reduction of CMOS power dissipation at logic level,” in Proceedings of the European Design Automation Conference, pp. 341-346, 1993. [19] M. A. Cirit, “Estimating dynamic power consumption of CMOS circuits,” in Proceedings of the ACM/IEEE International Conference on Computer Aided Design, pp. 534-537, 1987. [20] F. Najm, R. Burch, P. Yang, and I. Hajj, “CREST: A current estimator for CMOS circuits,” in Proceedings of the ACM/IEEE International Conference on Computer-Aided Design, pp. 204-207, 1988.

[21] F. Najm, “Transition density: a new measure of activity in digital circuits,” IEEE Transactions on Computer-Aided Design of lntegrated Circuits and Systems, vol. 12, no. 2, pp. 310-323, 1993. [22] R. E. Bryant, “Graph-based algorithms for Boolean function manipulation,” IEEE Transactions on Computers, vol. 35, pp. 677-691, Aug. 1986. [23] P. L. Meyer, Introductory Probability and Statistical Applications. Addison-Wesley, 1970.

[24] R. Burch, F. Najm, P. Yang. and T. Trick, “McPOWER: A Monte Carlo approach to power estimation,” in Proceedings of the ACM/IEEE Interna tional Conference on Computer-Aided Design, pp. 90-97, 1992.

References

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[25] M. G. Xakellis and F. N. Najm, “Statistical estimation of the switching activity in digital circuits,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 728-733, June 1994. [26] L. P. Yuan, C. C. Teng, and S . M. Kang, “Nonparametric estimation of average power dissipation in CMOS VLSI circuits,” in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 225-228, 1996. [27] C. Y. Tsui, M. Pedram, and A. M. Despain, “Exact and approximate methods for calculating signal and transition probabilities in FSMs,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 18-23, 1994. [28] A. Papoulis, Probability, Random Variables and Stochastic Processes. New York: McGraw-Hill. 1984. [29] F. Najm, S. Goel, and I. Hajj, “Power estimation in sequential circuits,”in Proceedings of the ACM/IEEE Design Automation Conference, pp. 635– 640, 1995.

[30] T. L. Chou and K. Roy, “Statistical estimation of sequential circuit activity,” in Proceedings of the ACM/IEEE International Conference on Computer-Aided Design, pp. 34-37, 1995. [31] L . P. Yuan, C. C . Teng, and S. M. Kang, “Statistical estimation of average power dissipation in sequential circuits,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 377-382, 1997.

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Chapter 3

TEMPERATURE-DEPENDENT MOS DEVICE MODELING

3.1.

INTRODUCTION

A circuit can be represented by a set of node equations describing the circuit network comprised of semiconductor devices. To accurately model the thermal effect in a circuit, the device model must take into account the device temperature as one of its modeling parameters. Due to the rapid advance in semiconductor fabrication technologies, the device feature size has been drastically reduced to the very deep submicron regime. The short channel effects in devices often necessitate the use of 3D device modeling or sometimes quantum physics for device analysis. One of the device simulation techniques, namely the Monte-Carlo simulation, investigates the electron scattering mechanisms in the crystal from the probability view point. With the increasing speed and capacity of computers today, one can accurately model the semiconductor device characteristics, such as electronic current, using this technique. Monte-Carlo simulation for semiconductor devices requires solving the Boltzmann equation coupled with the Poisson equation. It is often very complicated, and assumptions are made so that simple forms of modeling equations can be derived. Once the simplified device equations and models are found, their physical or fitting parameters can be determined on the basis of physical properties of the devices, measured data, or combination of the two. They can then be readily applied to the large-scale circuit simulation and analysis with sufficient accuracy. In the following, an overview of the temperature-dependent device physics and device modeling will be presented. The temperature-dependent models of the threshold voltage and carrier mobility of the MOS transistors are de-

46

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

rived. Two device models that are suitable for the temperature-sensitive circuit simulation will be visited as case studies.

3.2.

TEMPERATURE-DEPENDENT DEVICE PHYSICS AND MODELING

The popular Shichman-Hodges model [ I ] (also known as the SPICE Level 1 model) for the MOS transistor defines the MOS current in two operating regions in terms of the gate-source voltage V G S and the drain-source voltage V D S as follows:

(3.1) W In the above equation, /3 is the MOS device transconductance given by u and VGSE = VG S V T , where / 0 is the carrier mobility, Co x is the gate oxide capacitance per unit area, VT is the threshold voltage, W and L are the device channel width and length respectively. The channel-length modulation parameter /\ is ignored in Eq. (3.1) for simplicity. Equation (3.1) contains two temperature-dependent physical parameters, /u0 and V T.

3.2.1

TEMPERATURE-DEPENDENT THRESHOLD VOLTAGE

The threshold voltage VT can be expressed as the summation of the zerobias threshold voltage VT 0 and another term related to the body effect. The temperature dependence in VT0 is contributed by several material-related physical parameters and can be derived by applying MOS device physics. In the SPICE Level 1 MOS model, for instance, VT0 ( T ) of an NMOSFET with n+ - polysilicon gate at temperature T can be formulated as (3.2)

(3.3) where

(3.4) (3.5) In the above equations, ni is the intrinsic carrier concentration of silicon, E g is the energy band gap of silicon, N a and Na are the doping concentration,

TEMPERATURE-DEPENDENT MOS DEVICE MODELING

47

k is the Boltzmann constant, and E s i is the permittivity of silicon. The total charge density Qtot includes the surface state charge density ( Q S S ) , fixed charge density (QF), and the threshold voltage-adjustment implant density ( Q i mp ).

3.2.2

TEMPERATURE-DEPENDENT CARRIER MOBILITY

The carrier mobility in semiconductors is related directly to the mean-free time between collisions, which in turn is determined by various scattering mechanisms. The three most important mechanisms are Coulomb, lattice, and surface-roughness scatterings.

COULOMB (IMPURITY) SCATTERING. Coulomb scattering results when a charge carrier travels past an ionized impurity. The effect of Coulomb scattering at high temperature is small because the carriers are moving faster and, therefore, scatter less. However, this cannot be neglected because the oxide charges contribute to the Coulomb scattering at room temperature or higher [2] . In [ 2 ] ,it is proven that the Coulomb-scattering-limited mobility /uc follows

(3.6) where T is temperature and NI is the charge density at the Si-SiO2 interface.

LATTICE (PHONON) SCATTERING. Lattice scattering results from thermal vibrations of the lattice atoms at any temperature above zero. These vibrations disturb lattice periodic potential and allow energy to be transferred between the carriers and the lattice. For intermediate inversion-layer concentrations ( Q N / q = 0.5 ~ 5 x 1012/cm2), the channel mobility has been observed to have the following relationships with the effective transverse electric field E e f f and T [ 3 ] :

(3.7) where

(3.8) The QD term is the depletion charge density, y = 3 ~ 6 , and n = 1 ~ 1.5, depending on the crystallographic orientation and the strength of intervalley and intersubband scattering.

SURFACE-ROUGHNESS SCATTERING. Surface-roughness scattering results from the asperities at the Si-Si02 interface at high electron concentrations. The dependence of the surface-roughness scattering-limited mobility

48

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

/u S R on E e f f is given by [4]

(3.9) Because the probability of a collision (1/Tc ) taking place in unit time is the sum of the probabilities of collisions due to various scattering mechanisms, it follows that

Or equivalently:

(3.10) The simple temperature-dependent mobility formula used in the SPICE Level 1 model is

(3.1 1 ) where lattice scattering is assumed to be the only factor that determines the carrier mobility, and n in Eq. (3.7) is chosen to be 1.5.

3.3.

TEMPERATURE-DEPENDENT BSIM MODEL FOR SPICE SIMULATION

In [ 5 ] , an accurate temperature-dependent device modeling technique for MOS VLSI circuit simulation was proposed. This technique has been incorporated into the Berkeley Short-Channel IGFET Model (BSIM, also called the Level-4 model) to predict the temperature-dependent characteristics of devices in the submicron regime. Each electrical parameter Pi in BSIM is described by the following formula [6]: (3.12) where P0i, PLi and Pwi are the process parameters associated with the electrical parameter Pi. The effective channel length (Le f f ) and channel width (We f f ) are used in the formula. The parameters Poi , P Li and P w i are generated by fitting the parameter file with different device dimensions to Eq. (3.12). Once P0i , P Li and PW i are known, the electrical parameters for a device with any channel length and width can be calculated from Eq. (3.12) by replacing L e f f and W e f f with the desired dimensions. Because each electrical parameter is calculated from several process parameters, the BSIM contains sixty-seven process parameters in total. Furthermore,

TEMPERATURE-DEPENDENT MOS DEVICE MODELING

49

the BSIM drain current equation is considerably more complicated than the simple formula in Eq. (3.1). In the triode (linear) region, for instance, the BSIM drain current can be written as: (3.13)

Cox , V T, a, U0 ,and U1 can all be expressed in terms of the In this equation, BSIM electrical parameters. Totally eighteen different electrical parameters are needed in calculating the drain current expressed in Eq. (3.13). If the temperature dependence needs to be considered, even more complexity will be added to Eq. (3.13). One straightforward way to model the temperature-dependent BSIM drain current is to characterize each electrical parameter used in Eq. (3.13) over a certain range of temperatures. In other words, Pi becomes P i (T) in Eq. (3.12) and I D S (T) can be found accordingly by Eq. (3.13). Unfortunately, this approach is computationally expensive. One attractive alternative proposed by [ 5 ] utilizes the concept of sensitivity. It first determines a sensitive SPICE parameter subset that has large effects on the device output characteristics, and only the parameters in this subset need to be updated as temperature changes. To find the sensitive subset, a sensitivity function is used. A basic sensitivity function of a variable Q with respect to an electrical parameter Pi is defined as [ 7]: (3.14) For digital ICs, the variable Q could be the drain current of the MOS transistor. A modified sensitivity function for the drain current over a biasing space A (e.g., linear, saturation) can be expressed as: (3.15) where I D S , Pi is the simulated drain current with P i being perturbed and m is the number of data points. The user-specified input I D S O is used to determine whether an absolute or relative error is preferred. After the sensitivity analysis, there are eight out of eighteen BSIM electrical parameters left in the sensitivity subset. It means that if the BSIM drain current needs to be updated due to any environmental perturbation, including temperature change, only eight parameters need to be recalculated. Table 3.1 lists these eight electrical parameters, most of which are related to the carrier mobilityand the threshold voltage. The above procedure for finding the sensitive parameter subset corresponds to the sensitivity analysis box in Fig. 3.1, which illustrates the whole BSIM sensitive parameter subset approach.

50

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS Table 3.I .

BSIM sensitive parameters

Parameter Names

Physical Meaning

VF B

Flat- band voltage Surface inversion potential Body effect coefficient Drain/source depletion charge sharing coefficient Zero-bias mobility Zero-bias transverse-field mobility degradation coefficient Zero-bias velocity saturation coefficient Mobility at zero substrate bias and at V D s = V D D

K1 K2

U0z U1Z s

Figure 3.1.

BSIM sensitive parameter subset approach.

TEMPERATURE-DEPENDENT MOS DEVICE MODELING

51

Next, in order to determine how sensitive those eight parameters are to the temperature variation, their temperature coefficients need to be found. The temperature coefficients can be obtained from one of the following two sources: the measured experimental data or the analytically derived formula. In the first case, the values of process parameters are extracted automatically from the device I-V data using the BSIM Extract program at different temperatures. The parameter-temperature relationship can thus be found and fitted by an appropriate fitting function. For instance, values of the parameters K1, K2, U 0 z , V F B, and ø s are fitted by a linear function of temperature,while values of the parameters µ z and µ s are fitted by functions of T -1 . 5 and values of U1z are fitted by T -2.5 [ 5 ] . The temperature coefficients can also be analytically derived, as will be illustrated by taking ø s as an example. The surface inversion potential (ø s ) is given by (3.16) where n z is also temperature dependent as shown in Eq. (3.4). Its temperature coefficient can be derived and represented by a simple analytical formula [8]:

(3.17) By using Eq. (3.17), parameter ø s can be easily updated under any temperature perturbation during the SPICE simulation. Consequently, the drain current can be recalculated efficiently. This can be done for all other sensitive parameters as long as simple yet accurate analytical formula can be obtained. Figure 3.2 demonstrates the procedure for incorporating the temperature coefficient values into the BSIM parameter update, where P0 i , PL i and Pwi are the process parameters used in Eq. (3.12).

3.4.

REGIONWISE QUADRATIC (RWQ) MODEL

The fast-timing simulation technique was originally proposed to bridge the gap between full timing simulation and switch-level timing simulation. It is computationally very efficient compared to SPICE-like simulation method. The description of the general fast-timing simulation technique and the introduction of the fast timing simulator developed at the University of Illinois, named ILLIADS, will be given in Chapter 5 . In this section, the device modeling technique employed by ILLIADS, called the regionwise-quadratic (RWQ) model [9], is discussed. The extension of the RWQ model to take into account the temperature dependence is also addressed in detail. The RWQ model was developed for submicron device modeling i n order to improve the accuracy of fast timing simulation. Its modeling procedure takes as input a set of data points (V D S , VGS E , ID S ) that have been obtained either from

52

ELECTROTHERMAL ANALYSIS O F VLSI SYSTEMS

BSIM parameter tile at

BSIM parameter file at room temperature

Figure 3.2.

specified temperature

BSIM parameter value update using temperature coefficients.

measured data of a test device or by exercising (using SPICE, forexample) a VT0 particular analytical or empirical MOS I-V model. Here VG S E = V G S and VT 0 is the zero-bias threshold voltage of a MOS device. Next, the ( V D S, VG SE) plane is optimally partitioned into a number of regions and a quadratic model of I D S is numerically fitted in terms of V D S and VG S E in each region using the data points in that region. One example of the partitioned (V D S , VG SE) plane is shown in Fig. 3.3. For a given regionwise partition , the following quadratic model of I D S is fitted to the data in the K th region, —

(3.18) where ß is the MOS device transconductance as in Eq. (3.1), n r is the number of regions chosen for best fitting, and a’s are fitting parameters in the k t h region. Again, the carrier mobility (µ0 ) and the zero-bias threshold voltage (VT O) are the two physical parameters that are temperature dependent in the RWQ drain current equation Eq. (3.18). In [10] , the temperature-dependence is incorporated into the RWQ model. It was observed in [10] that the threshold voltage is much less temperature sensitive than the carrier mobility. Therefore, the temperature-dependent VT 0 model in [10 ] follows the simple MOS Level 1 model given in Eq. (3.2) and Eq. (3.3). However, a new temperature-dependent

TEMPERATURE-DEPENDENT MOS DEVICE MODELlNG

Figure 3.3.

Regionwise partition of the ( VD S ,

53

VG S E) plane.

µ 0 model that accurately take into account different scattering mechanisms has been developed in [l0], which will be presented in the following.

3.4.1

TEMPERATURE-DEPENDENT MOBILITY MODELING

Because the on-chip temperature could be as high as 120 oC and the device feature size keeps shrinking in state-of-the-art VLSI technologies, the simple mobility model in Eq. (3.11) may not be sufficient to cover a wide range of temperatures. However, it is rather difficult to devise an analytical formula to accurately calculate the channel carrier mobility because of the complex quantum effects [ 1 1]. Although some empirical models such as SPICE BSIM use as many as eight fitting parameters to obtain a fairly good fit for the mobility of a fixed technology, the technology dependence and scaling properties are not well understood. Owing to above reasons, a physically based, semiempirical mobility model has been developed [10] for the temperature range of 300 - 400 K, which is the normal temperature range for most circuits. Because this model is intended to be used in the fast-timing simulator, it must be accurate yet simple. In addition, this model should be scaled only with temperature and not with the transverse electric field Eef f, although the physical channel mobility indeed depends on both temperature and transverse electric field. This is because the transverse field dependence is already taken into account by VG S E in Eq. (3.18) at the RWQ fitting stage, i.e., E e f f V GS E [12].

54

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Based on Eq. (3.6), Eq. (3.7) , Eq. (3.9) and Eq. (3.10), the following temperature-dependent mobility model was proposed [10]:

(3.19) The symbol U ( T ) , defined as the inverse of the mobility /u 0 ( T ), is used for convenience. The A1, A2, A3 and A4 terms are fitting parameters, which are determined by using the nonlinear least-square fitting technique to match the extracted /u 0 ( T ) . Method used to extract /u0 ( T ) will be given in the next section. The Ee f f dependence in Eq. (3.7 ) and (3.9) is merged into A 2 and A4 in Eq. (3.19).

3.4.2

µ0 (T ) EXTRACTION

FOR RWQ MODELING

Let and be the experimental and RWQ-fitted drain currents in the k-th region, respectively. Here x denotes the data point vector ( VDS ,VG S E). The optimized mobility that produces the best fit can be extracted by minimizing the following objective function

(3.20) where nr is the number of regions and N k is the number of data points in region k.. The minimization process provides us with a best overall RWQ fit to ID S (X) from which µ0 (T) is extracted to be [10] (3.21) Once µ0 (T ) values are extracted at several temperatures, Eq. (3.19) is used to find the optimized A1, A2, A3 and A 4.

3.4.3

MOBILITY AND RWQ FITTING EXAMPLES

To evaluate the mobility modeling procedure described by Eq. (3.19) Eq. (3.21), the values of /u 0 (T ) for an NMOSFET with specific dimensions, in this case, L = 0.8 µm and W = 1.6 µm, are extracted. Nonlinear least-square fitting of the A1, A2, A3, and A4 parameters is accomplished by using the Levenberg-Marquart algorithm [13]. The results are shown in Fig. 3.4 and the extracted parameters are given in the inset. The RWQ modeling result at 27 o C is compared with the measured data in Fig. 3.5(a). The mobility model in Eq. (3.19) was used to predict /u 0 (T =

TEMPERATURE-DEPENDENT MOS DEVICE MODELING

Figure 3.4.

(a)

55

Fitted µ0 (T) vs. extracted µ0 (T).

(b)

Figure 3.5. NMOSFET: (a) RWQ fitting result at 27 o C, and (b) RWQ fitting result at 100 o C with mobility optimization.

100 o C) as 464.2 cm²/ (V.s), which is very close to 466.3cm2 / (V.s) obtained by extraction. The I D S - V DS curves at T =100 o C were constructed by using the RWQ fitting parameters a 0 - a5 obtained at room temperature and the value of µ0 (T = 100 oC). The results are compared with the measured data in Fig. 3.5(b). Similarly, the RWQ fitting results for a PMOSFET with the same dimensions are shown in Fig. 3.6.

56

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

(b)

(a)

o

o Figure 3.6. PMOSFET: (a) RWQ fitting result at 27 C, and (b) RWQ fitting rcsult at 100 C with mobility optimization.

Time (n Sec.)

Figure 3.7. chain .

Waveform comparison between SPICE and ILLIADS-T for a 9-stage inverter

Finally, to demonstrate the simulation accuracy of the fast-timing electrothermal simulator (ILLIADS-T) [10] in which the temperature-dependent RWQ model is implemented, a nine-stage inverter chain was simulated using both ILLIADS-T and SPICE with BSIM MOSFET models. The output waveforms at different temperatures are compared in Fig. 3.7.

References

3.5. .

57

SUMMARY

This chapter provides the temperature-dependent MOS device modeling techniques for circuit simulation. The temperature-dependent models of the threshold voltage and mobility of the MOS device are derived. To derive the temperature-dependent mobility model, the temperature dependence of three scattering mechanisms that determine the carrier mobility in semiconductors are introduced. The three scattering mechanisms are:

–

Coulomb (impurity) scattering

–

Lattice (phonon) scattering

–

Surface-roughness scattering

Because the probability of a collision taking place in unit time is the sum of the probabilities of collision due to the scattering mechanisms, the carrier mobility can be expressed as the summation of the scattering-mechanismlimited mobilities. The temperature-dependent BSIM model for SPICE simulation is presented.

–

The general formula for describing the electrical parameters in BSIM is provided.

–

Since the number of electrical parameters in BSIM is large, the sensitivity analysis approach is used so that only sensitive parameters are analyzed when temperature changes.

–

In order to determine how sensitive the sensitive parameters are to the temperature variation, the temperature coefficients are determined by either measured experimental data or by analytically derived formula.

The temperature-dependent regionwise-quadratic (RWQ) model for fast timing simulation is presented.

–

The working principles of the RWQ model are described.

–

The temperature-dependent mobility formula used in the RWQ model is developed. It is based on three scattering mechanisms and a number of fitting parameters. The fitting parameters are determined by the experimental data and the nonlinear least-square fit.

–

The simulation results are provided and compared to the measured data.

58

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

References [1] H. Shichman and D. A. Hodges, “Modeling and simulation of insulated gate field effect transistor switching circuits.” IEEE Journal of Solid-State Circuits, vol. 3, pp. 245-259, Sept. 1968. [2] C. T. Sah, T. H. Ning, and L. L. Tschopp, “The scattering of electrons by surface oxide charges and by the lattice vibrations at the Si-SiO2 interface,” Surface Science, vol. 32, pp. 561-575, 1972. [3] H. Ezawa, S. Kawaji, and K. Nakamura, “Surfons and the electron mobility in silicon inversion layers,” Japanese Journal of Applied Physics , vol. 13, pp. 126-155, Sept. 1974.

[4] A. Hartstein, T. H. Ning, and A. B. Fowler, “Electron scattering in silicon inversion layers by oxide and surface roughness,” Surface Science, vol. 58, pp. 181-190, 1976. [5] C. P. Wan and B. J. Sheu, “Temperature dependence modeling for MOS VLSI circuit simulation,” IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems , vol. 8, pp. 1065- 1073, Oct. 1989. [6] M . C . Hsu and B . J. Sheu, “Inverse-geometry dependence of MOS transistor electrical parameters,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 6, pp. 582-585, July 1987. [7] P. Tomovic, Sensitivity Analysis of Dynamic Systems. New York, NY: McGraw-Hill, 1963.

[8] S. M. Sze, Physics of Semiconductor Devices. New York, N Y : 2nd ed. John Wiley & Sons, 198 1. [9] A. Dharchoudhury, S. M. Kang, K. H. Kim, and S. H. Lee, “Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics,” in Proceedings of the ACM/IEEE International Conference on Computer - Aided Design, pp. 208-21 1, Nov. 1994. [10] Y. K. Cheng, P. Raha., C. C. Teng, E. Rosenbaum, and S. M. Kang, “ILLIADS-T: An electrothermal timing simulator for temperaturesensitive reliability diagnosis of CMOS VLSI chips,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, pp. 668-681, Aug. 1998. [11] M. S. Lin, “A better understanding of the channel mobility of Si MOSFET’s based on the physics of quantized subbands,” lEEE Transactions on Electron Devices, vol. 35, pp. 2406-241 I, 1988.

References

59

[12] M. S . Liang, J. Y. Choi, P. K . Ko, and C. Hu, “Inversion-layer capacitance and mobility of very thin gate-oxide MOSFET’s,” IEEE Transactions on Electron Devices, vol. 33, pp. 409-412, 1986. [13] D. W. Marquart Journal of the Society f o r Industrial and Applied Math., voI. 11, pp. 431-441, 1963.

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Chapter 4

THERMAL SIMULATION FOR VLSI SYSTEMS

4.1.

INTRODUCTION

A thermal simulator finds the temperature distribution of a system containing heat sources during the electrothermal simulation, as depicted in Fig. 1.2. A heat source in a VLSI system may be a chip in a multi-chip module (MCM), or may simply be a heat dissipating device (e.g., transistor, resistor). Because the number of heat sources in a VLSI system can be large, the thermal simulation method for such a system must take into account the tradeoff between efficiency and accuracy. The heat diffusion equation is the governing equation for describing the heat conduction and for calculating the temperature. The general equation is given in the following form [ 1] (4.1) subject to the general thermal boundary condition (4.2) and the initial temperature condition (4.3) In Eq. (4.1) and Eq. (4.2), T is the temperature (°C), g is the power density of the heat source(s) (W/m³), k is the thermal conductivity (W/(m°C)), p is the density of material (Kg/m³), cp is the specific heat (J/(Kg°C)), hi is the heat transfer coefficient (W/(m² °C) ), ƒi (x, y, z ) is an arbitrary function, and n i is the outward direction normal to the surface i. For the steady-state case, the term in Eq. (4.1) is zero.

62

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

If the thermal conductivity k is uniform (i.e., independent of position and temperature), Eq. (4.1) can be reduced to

(4.4) and Eq. (4.2) can be reduced to

(4.5) where a is called the thermal diffusivity of the medium defined as (4.6) The following three types of thermal boundary conditions derived from Eq. (4.5) can be applied to the object boundaries, depending on the packaging materials and the surrounding environment: Isothermal (Dirichlet):

(4.7)

Insulated (Neumann):

(4.8)

Convective (Robin):

(4.9)

where Ta is the ambient temperature. To solve the above boundary value problem of heat conduction, many existing analytical or numerical approaches are available. However, due to the large problem size in VLSI systems, some modification, simplification, or enhancement on those approaches are necessary. In Fig. 4.1, a mixed use of different thermal simulation methods that is particularly useful for a VLSI chip is illustrated [2] . This framework is comprised of three simulation engines: a fast thermal simulator, a numerical thermal simulator, and an analytical thermal simulator. The simulated on-chip substrate temperature profile is further utilized for interconnect temperature estimation as shown in Fig. 4.1. The interconnect temperature plays an important role in the RC delay calculation and electromigration reliability diagnosis, which will be discussed in Chapter 6 and Chapter 8. The fast thermal simulator in the framework is designed to quickly identify the on-chip hot spots. It is very fast and provides a qualitative temperature description of the heat sources. The numerical thermal simulator is designed for the full-chip temperature profiling, while the analytical thermal simulator is used for accurately pinpointing the temperatures of the hot spots. Both numerical and analytical thermal simulation approaches take into account the

THERMAL SIMULATION FOR VLSI SYSTEMS

Figure 4. I.

63

A thermal simulation framework [2].

packaging effect. Note that although the framework in Fig. 4.1 was originally developed to solve the electrothermal problem for a chip, it can be well applied to other VLSI systems. In the following, a general description of the simulation strategy for a simple substrate/package structure of a chip will be given. Concepts such as the thermal resistance and the effective heat transfer will also be introduced. The fast thermal analysis, the numerical thermal simulation method, and the analytical

64

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 4.2.

Illustration of effective heat transfer macromodeling.

thermal simulation method will be presented and compared. Finally, the details of the package simulation technique will be presented.

4.2.

SUBSTRATE/PACKAGEMODELING: AN OVERVIEW

A chip can be viewed as a combination of the substrate (bulk) and the package. A package consists of the heat sink, the pins, and many other heat removal devices. An exact approach to model a chip for thermal simulation is to directly model the whole structure. Because of its complexity, however, a chip is often modeled and simulated by the following mixed 3-D/I -D strategies: (1) 3-D simulation is performed for the chip substrate to achieve a higher degree of accuracy, and (2) packaging elements are modeled as 1-D thermal resistances to reduce the computation cost. The strategy (2) is henceforth referred to as the effective heat transfer macromodeling. Specifically, as shown in Fig. 4.2, the thermal resistance of the package ( R k ) and the thermal resistance from package to ambient (R h) are serially combined to calculate the effective heat transfer coefficient h e given by (4.10) In Eq. (4.10), Rk = Rh = L and k p are the thickness and the thermal conductivity of the package respectively, h p is the heat transfer coefficient from package to ambient, and A c is the chip area normal to the direction of heat flow. From Eq. (4.10) it can be seen that the package effects are merged into the hi term in Eq. (4.2) and an effective h e is formed. The advantage of the effective heat transfer macromodeling is threefold. First, it improves the overall simulation efficiency. Second, it decouples the thermal simulation problem between the substrate and the package, so that Eq. (4.2) remains valid with the exception that hi is replaced by h e. Also the substrate and the package can be characterized and simulated independently. Third, it allows the complicated chip structures to be easily handled. For instance, if

THERMAL SIMULATION FOR VLSI SYSTEMS

65

there are pins existing in Fig. 4.2, they can be taken into account by replacing kp in Rk with (4.1 1 ) where kp i n is the thermal conductivity of the pins and

X =

4.3.

(Area of pins) (Total package area)

(4.12)

FORMULATION OF THERMAL ANALYSIS

The different thermal simulation methods in the framework shown in Fig. 4.1 can be utilized to generate the temperature profile, identify the hot spots, and pinpoint the hot-spot temperatures for the VLSI systems. In the following, the formulation of each thermal simulation technique in the framework will be presented. The advantages and disadvantages of each technique will be also discussed.

4.3.1

FAST THERMAL ANALYSIS

For a VLSI system containing a large number of heat sources, the exact numerical and analytical methods are computationally inefficient. In the early design phase when no specific package information is given or the thermal boundary condition is not fully characterized, a fast thermal analysis method that emphasizes the hot-spot identification is highly desirable. It can be used for the iterative temperature-sensitive module placement in order to achieve a more uniform temperature distribution for better reliability and reduced delay. In this section, a fast thermal analysis method, called FTA [3], is introduced. This method has been shown to quickly identify the on-chip hot spots. Several assumptions were made in [3] specifically for a VLSI chip, therefore the presented formulation may need to be modified to suit certain needs for other environment. However, the basic concept remains the same. The FTA approach utilizes the fact that the dimensions of the gate-level or subcircuit-level heat sources in a VLSI chip are small compared with the chip size. Therefore, all heat sources can be viewed as located in a virtually infinite body. Consider a point source in a chip as shown in Fig. 4.3(a). Since ICs have a passivation layer, the top of the chip is insulated. We therefore have a boundary value problem with infinite dimension in the x-y plane while with semi-infinite dimension in the z direction. Moreover, the boundary condition at t) z = 0 is = 0. To find the temperature subject to this specific geometry and boundary conditions, the method of images is used [ 3 ] : an identical heat source that is symmetric with respect to z = 0 is added and the insulating boundary is removed. Now, the problem in Fig. 4.3(a) is transformed to that in Fig. 4.3(b).

66

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 4.3.

Method of images.

The Green's function solution G ( r , of the heat diffusion equation Eq. (4.4) for the point source in Fig. 4.3 can be derived as = Gx . Gy . Gz , where

(4.13) where a is the thermal diffusivity. The resulting temperature rise above the ambient at observation point r due to the parallelepiped heat source with dimensions a x b x c can be formulated as (4.14) where the coordinate origin has been set to be at the center of the source and P0 is the source power. By utilizing the error function, Eq. (4.14) can be simplified to:

where

THERMAL SIMULATION FOR VLSI SYSTEMS

Figure 4.4.

67

Error function approximation.

(4.16) In Eq. (4.15), the observation point is set to be on the chip surface by replacing r with ( x , y , 0 ) . D efinin g A 1 = 2 (a/2+X ),A2 =2(a/2-x), B1=2(b/2+y), B 2 = 2 ( b / 2 y ), and C = 2c, along with the change of variables, Eq. (4.15) can be rewritten as –

In order to perform the integration in Eq. (4.17) analytically, the error function is piecewise linearized according to (referring to Fig. 4.4) [4] (4.18) Table 4.1 demonstrates the approximation results by using Eq. (4.18) and defining t al = ta2 = tbl = tb2 = In Table 4.1, m = 0 if A2 > 0, otherwise m = 1. and tc = Similarly, n = 0 if B2 > 0, otherwise n = 1. To obtain the analytical solution of Eq. (4.17), the number of possible permutations (i.e., 120) of t a l , ta2, tb1, t b 2 and tc needs to be reduced to a manageable level. To do this, the following constraints are asserted according to [3]:

68

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS Table 4.1 .

Figure 4.5.

Error function approximations.

Transformation 1: Constrain the observation point to the first quadrant.

Constraints (2) and (3) are straightforward algebraically. Constraints (4) and ( 5 ) are valid because the thickness of the heat sources (i.e., c) is much smaller than the physical dimensions (i.e., a and b) of a logic gate. Constraint (1) is equivalent to transforming all the observation points to the first quadrant by using the symmetric property as graphically shown in Fig. 4.5. To satisfy Constraint (6), the coordinate transformation shown in Fig. 4.6 is used. With the above specified constraints, Eq. (4.17) now becomes tractable. In other words, the order of ta1, ta2, tb1, tb2 and t c must belong to one of the eight cases shown in Fig. 4.2. The analytical solutions are derived for all cases. Proper solutions will be used during the simulation, depending on the geometry and

THERMAL SIMULATION FOR VLSI SYSTEMS

Figure 4.6 .

69

Transformation 2: Constrain t a l to be larger than tb l .

Table 4.2.

Eight cases under six constraints.

the size of the heat sources, as well as the relative locations between the heat source and the observation point. For a VLSI chip with n heat sources, the temperature rise at the center of source i is obtained by considering the heat diffusion from i itself, plus that from other n — 1 sources using superposition:

(4.19) where is the temperature rise at the center of source i, is the temperature rise due to i itself, and t ) is the temperature rise due to source k . Here, t ) and t ) can both be found by combining Eq. (4.17) with one of the eight cases in Fig. 4.2. Let us consider Fig. 4.7 as an example, where one source with power P1 is located at (0,0) and the other one with power P I I is at (3,2). The temperature t ) in Eq. (4.19)) rise at the center of source II due to source I (i.e., can be found by recognizing that this condition satisfies Case 1 above, where tal t bl t b2 ta 2 tc. Thus the integration in Eq. (4.17) can be explicitly performed. Specifically, at steady state (t

70

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 4.7.

An FTA example.

(4.20) if m = 1 and n = 1 where ( x , y ) = ( 3 , 2 ) . Similarly. the temperature rise at t ) in Eq. (4.19)) can be the center of source II due to self heating (i.e., t c ) of Case 3: t b1 tb2 found since it is a special case (ta1 = t a 2 (4.21) Finally, the steady-state temperature rise at the center of source II can be obtained, according to Eq. (4.19), as (4.22) The mathematical formulation of the FTA method is based on the closedform Green’s function with the assumption of semi-infinite boundary condition. In practice, this assumption is not valid due to the existence of package and heat sink in a chip. Therefore, the temperature rise predicted by Eq. (4.19) represents the relative value instead of the absolute value. However, the FTA method provides a quick estimate of the temperature distribution. This is particularly useful when the number of heat sources is large or when a large number of repeated thermal simulations are needed. It is also useful when the chip package specification is not known in the early design phase. In order to take into account the effects of package and heat sink, detailed thermal simulation using a numerical or analytical approach is needed. Among different thermal simulation methods, the FTA method is primarily used for fast hot-spot identification. In order to observe how accurately the

THERMAL SIMULATION FOR VLSI SYSTEMS

Figure 4.8.

Chip structure and heat source locations.

Table 4.3.

Violation rate by using the FTA method.

71

FTA method can identify the hot spots, the following experiment is performed. Consider a chip containing 10 heat sources, all with dimensions of 50 µm x 50 µm. The sources are confined within the area (source area) with dimensions of 500µm x 500µm, and the distance between the boundary of the source area and the chip’s bonding pad is 500µm as shown in Fig. 4.8. The heat sources are randomly placed and the power values from 10 m W to 100 mW are randomly assigned to the sources. The heat source with the highest temperature is found by using both the FTA method and the exact numerical thermal simulation method. The above process is repeated for 50 times (i.e., 50 tests). A violation happens in a test if the hot spot identified by the FTA method is different from the one identified by the exact method. The number of violation and the violation rate among 50 tests are shown in the second and third rows of Table 4.3 for different h (heat transfer coefficient in Eq. (4.2)) values. Note that the exact method needs the h value in order to take the boundary conditions into account. In Table 4.3, is defined

72

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS 4.3 (continued).

Violation rate by using the FTA method.

as

(4.23) Here, T ie xact is the actual temperature of th e hot spot that is identified by the exact method, and is the actual temperature of the hot spot that is identified by the FTA method. It shows that a violation occurs only when the two hot spots have very close temperature values, which is insignificant for reliability concerns. Therefore, the FTA method proposed in [3] is generally accurate in finding the hot spots i n the VLSI chip. The efficiency of the FTA method will be presented later in the chapter, after the exact numerical and analytical simulation methods are introduced.

4.3.2

NUMERICAL APPROACH

The heat conduction problem can be solved numerically by using the finitedifference method (FDM) [ 5 , 6 , 7] , the finite-element method (FEM) [8, 9, 10], or the boundary-element method (BEM) [11] among others. In this section, the FDM will be discussed and it will remain to be the main numerical method used for illustration throughout this book. The basic concept of the finite-difference approach is to approximate the partial derivative of a given point by a derivative taken over a finite interval across that point. Let ƒ(x) be a function which is finite, continuous and single valued. The derivative of f (x) at point xi can be approximated by the following difference equation:

(4.24) where ( xi + h ) and ( x i - h ) are the two neighboring points. Similarly, the finite-difference approximation of the second derivative of f (x) can be given as (4.25) The above finite-difference expressions of the first and second derivatives can be applied to Eq. (4.1) or Eq. (4.4) with respect to the time domain and the

THERMAL SIMULATION FOR VLSI SYSTEMS

73

space domain. The object under simulation is first discretized into many space grid points x i , and the algebraic difference equations are obtained for each x i . The resulting set of equations that represent all grid points can be solved for the successive time points provided that the temperature distribution at t = 0 is given. The number of grids and the distance between two grid points determine the accuracy and sirnulation speed of the FDM. Furthermore, the distance between the grid points (x i+,xi +2) can be different from the distance between the grid points (xi +1,xi +2). To account for both accuracy and speed, an adaptive meshing technique is often employed in the FDM to optimally generate the variable grid system [6]. The grid lines are first uniformly deployed according to the user-specified initial number of grids. After an initial estimate of the temperature distribution is obtained, the grids are refined or redistributed by sensing the temperature gradient. Extra grids are added to the regions with larger gradient based on the following weight function (Eq. (4.26)) and equidistribution criterion (Eq. (4.27)) [12]: (4.26) (4.27) where is the user-specified tuning parameter and r denotes the x or y axis. It can be seen that for a larger gradient, a smaller grid spacing is needed. Temperature solutions of the grids in the previous grid system are compared to those in the refined grid system. If the percentage difference is less than a prescribed threshold, then the grid refinement process is terminated. The stopping criterion can also be the user-specified maximum number of grids. To start deriving the finite-difference equations similar to Eq. (4.24) and Eq. (4.25) for the 3-D Cartesian coordinate system, the schematic representation of a solid containing several heat Sources along with the variable grid system is given in Fig. 4.9. After the coordinates of each heat source are identified, the corresponding grid points into which the heat flows and the proportionate power values in the analogous thermal circuit are found as shown in Fig. 4.10. Symbol Pi in Fig. 4.10 (a) denotes the heat flow from source i . The solid lines in Fig. 4.9(a) and Fig.4.10 (a) represent the chosen grid lines and dashed ones are in the middle of two adjacent grid lines. A e f f is the effective area of a grid point. Every heat source that overlaps the effective area of a grid point serves as a power source feeding into that grid, and the corresponding power value is calculated based on the ratio of the source area within A e f f to the total area of the source. In Fig. 4.9 (b), h x+, hx - , hy+ , h y - , h z + and h z- are

74

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS I. 11, I l l : Heat sources

(a)

(b)

Figure 4.9. (a) Top view of the solid containing heat sources, and (b) 3-D view of grid point (i, j, k).

(a)

(b)

Figure 4.10. (a) Analogous thermal circuit to Fig. 4.9(a), and (b) thermal conductances from (i, j, k) to adjacent grids.

halves of the distances from grid (i j , k ) to grids ( i + 1, j , k ) , ( i 1, j , k ) , (i, j +1 , k ), (i , j 1, k ) , ( i , j , k+ l ), and ( i ,j ,k - l) , respectively. The thermal conductances G1, G2, G3 and the thermal capacitance C in Fig. 4.10(b) can be —

–

THERMAL SIMULATION FOR VLSI SYSTEMS

Figure 4.11.

75

Analogy between thermal and electrical circuits.

found by applying the first law of thermodynamics (i.e., energy conservation in a thermodynamic system) on the grid point (i, j , k ) :

(4.28) where is the time increment and Tn is the temperature at time n . From Eq. (4.28), it can be seen that the heat conduction in a thermal circuit is similar to the current conduction i n an electrical circuit with the analogy shown in Fig. 4.1 1. Therefore, a finite-difference heat conduction problem can be mapped into an electrical RC network problem. In fact, Eq. (4.28) is analogous to the Kirchhoff's current law (KCL) used in the electrical circuit. The thermal conductances and capacitance connected to the grid ( i, j ,k ) can thus be found as

76

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

(a)

(b)

Figure 4.12. (a) Top view of a part of the chip comprised of composite materials, and (b) 3-D view of grid point (i, j , k).

(4.29) Similar expressions for G4 ,G 5 and G 6 can be derived. For a composite material system, as shown in Figs. 4.12 and 4.13, G1, G 2 , and G3 are found to be

(4.30) The thermal circuit is represented by a large set of nodal equations like Eq. (4.28), and a system matrix is created. This matrix can be solved by either the sparse-matrix technique or the successive-over-relaxation (SOR) technique in order to obtain the temperature distribution of the object under simulation. The matrix is solved successively for each time increment based on the temperature values of the grids at the previous time point. In the electrothermal simulation flow for the VLSI chip, once the on-chip temperature profile is found, the gate temperature is calculated by averaging the temperature values of the grids that the gate covers.

THERMAL SIMULATION FOR VLSI SYSTEMS

(a)

77

(b)

Figure 4.13. (a) Analogous thermal circuit to Fig. 4.12(a), and (b) thermal conductances from (i, j, k) to adjacent grids.

The previous discussion describes the finite-difference temperature calculation for the interior grids. However, special care must be taken for the boundary grids. In the following, the 3-D steady-state case is illustrated without loss of generality. Figure 4.14 shows the steady-state thermal circuit used to model the top of a solid with the convective boundary condition, where Ta is the ambient temperature. To find the equivalent thermal conductances for this system, the first law of thermodynamics is again applied on the grid point (i, j ,k ) :

(4.31) where h e is the effective heat transfer coefficient defined in Eq. (4. 10). Using the analogy in Fig. 4.1 1, the thermal conductances G1, G2 and G3 in Fig. 4.14(a) are found as

(4.32)

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ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

(a)

(b)

Figure 4.14.

Equivalent thermal circuit at the convective boundary.

(4.33) (4.34) Defining A e f f = ( h x+ + h x- ) ( hy + + hy-) as the effective area of the grid e ( i , j ,k ) , the thermal resistance associated with the convective heat transfer R h in Fig. 4.14(a)) is (4.35)

THERMAL SIMULATION FOR VLSI SYSTEMS

79

This boundary value problem can be solved as follows. First, the circuit in Fig. 4.14(a) is transformed to the equivalent circuit in Fig. 4.14(b), and a 3-D network containing only resistive elements and independent current sources is obtained (i.e., capacitive elements are open-circuited in the steady state). Next, a nodal analysis of this network is performed, and the system admittance matrix is constructed and solved. For the boundary condition other than the convective condition, a similar procedure follows by replacing he in Eq. (4.35) with for the isothermal condition, or with 0 for the insulated condition.

4.3.3

ANALYTICAL APPROACH

If both the heat diffusion equation Eq. (4.4) and the boundary condition Eq. (4.5) are homogeneous, the heat conduction problem can be conveniently solved by using the method of separation of variables. For nonhomogeneous problems, a general method such as the multiple integral transform (i.e., Fourier transform) and the associated multiple inversion technique [ 13] is required. The integral transform technique removes the space variables from the partial differential equation. It treats all space variables in the same manner with no inversion difficulties because all the integral transform and the inversion formula are well defined at the onset of the problem. Consider a general 3-D problem in the finite ranges of 0 x a , 0 y b and 0 z c , where a, b , c are the dimensions of a solid. The triple-integral and inversion formulae are defined as

(4.36)

(4.37) where K(ßm, x), K (vn , y ) , K ( ni p , z ) are z the eigenfunctions and ß m, v n , ni p are the eigenvalues. The eigenfunctions and eigenvalues can be derived by simply solving the auxiliary homogeneous problem called the Sturm - Liouville problem [14]. The integral transform of the heat equation Eq. (4.4) can be taken by applying Eq. (4.36):

(4.38)

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ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

where t ) is the integral transform of g(x. y , z , t ) . By using the Green’s theorem, Eq. (4.38) can be transformed into the following expression which takes the boundary conditions into account:

(4.39) where

(4.40) where ƒ1 - ƒ6 correspond to f i (x ,y, z , t ) in Eq. (4.5) for the six sides of the solid. The solution of the first-order differential equation Eq. (4.39) subject to the transformed initial condition (4.41) is straightforward and can be found in most differential equation texts [14]. Once_T( iB m,Vn, t ) is solved, T(x,y , z , t ) can be found by using the inver sion formula Eq. (4.37). For the steady-state case, Eq. (4.39) reduces to (4.42) where

THERMAL SIMULATION FOR VLSI SYSTEMS

81

(4.43) Similar to the transient case, once_T( B i m, V n , is solved, T (x,y, z ) can be found subsequently. As an example, now we present the solution of the steady-state case where all four sides and the top surface of the chip are insulated, while the bottom surface is convective. In this case, the eigenfunctions are

where h ez is the effective heat transfer coefficient of the bottom surface. Note that when ß m in K( ßm, x) is zero, the coefficient of K(ßm, x ) has to be replaced by in order to retain the eigenfunction normalities. Same i m , Vn, , nip in Eq. (4.43) argument also applies to vn in K (v n,y ). NowA ( B becomes

A ( ßm , Vn

,

=

Vn ,

z)

+

K(vn,y)dxdy . (4.44)

if m 0 and n 0, where (xic , yic , zic ), (xid , yid , Z i d ) and g i are the center coordinates, dimensions, and the power density of heat source i , respectively,

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ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

and nr is the number of heat sources. If m = 0 and/or n = 0, a similar expres sion for can be derived. Note that the number of terms used in the infinite series expansion in Eq. (4.37) is actually finite in practical implementation. For instance, when the additional term does not change the temperature value by more than a small specified amount (e.g., 0.01 º C) or percentage, the series summation is terminated.

4.3.4

DISCUSSION

So far the above three different thermal analysis methods have been introduced. In general, the numerical method is more powerful and can be more easily applied to various kinds of heat conduction problems (e.g., linear, nonlinear, homogeneous, nonhomogeneous). The analytical method, on the other hand, is more restrictive in solving complex problems. For instance, if the thermal conductivity k is temperature dependent, some variable transformation technique such as the Boltzmann's transformation or the Kirchhoff's transformation [15] may need to be used in order to simplify the original problem to an analytically tractable level. Moreover, for systems containing composite material or multiple layers, special treatment is necessary in deriving the analytical solutions. From the viewpoint of computational efficiency, the nonclosed form of the analytical triple series summation in Eq. (4.37) is more expensive than the numerical method [2], and this is aggravated when the number of points for which the temperature needs to be calculated is large (e.g., full-chip temperature profile estimation). For instance, the chip shown in Fig. 4.8 was simulated by both methods, and the temperatures of 400 mesh points on the chip were calculated. The numerical method required 26.09 seconds and the analytical one required 448 seconds of CPU time on SUN SPARC 10. The analytical method, however, has a clear advantage. Because it provides an explicit expression for the temperature of a point (x,y, z), it is very useful if one only needs to calculate the temperatures of some specified points (e.g., hot spots identified by the FTA method) rather than solving the temperature profile of the whole chip. The FTA method can efficiently identify the hot spots. To demonstrate its speed advantage, both the FTA method and the numerical finite-difference method are used to identify the hot spot among the heat sources in Fig. 4.8. The speedup factor of FTA over the numerical method with increasing number of heat sources is plotted in Fig. 4.15. In the numerical simulation, one grid line is assigned for each heat source in both x and y directions. The mixed use of the above thermal simulation methods are commonly seen for solving the temperature of complex systems. For instance, the FTA method was used in conjunction with the numerical method for mesh generation [3]. Areas with larger temperature gradient often require more grids for better accuracy. The FTA routine can be incorporated into the numerical thermal

THERMAL SIMULATION FOR VLSI SYSTEMS

83

simulator as a preprocessor to estimate the temperature gradient, which helps to determine a better initial guess of the grid distribution and therefore facilitate a more accurate and efficient thermal simulation. Moreover, in [16], a semianalytical method to predict the printed circuit board package temperatures was proposed. In this approach, the analytical solution is derived to represent the temperature of each package layer, while the numerical iteration is needed to take into account the heat flow between layers and the final package temperature. In [17], a combination of the numerical and analytical methods to solve the temperature of the multilayered structure was also developed.

4.4.

PACKAGE SIMULATION

Section 2 in the chapter presents the basic concept of the package modeling: The package related thermal resistances are first found, and then later incorporated into the 3-D bulk simulation in order to find the temperature distribution of the bulk. In the following. the packaging effects, the heat-flow paths through the package, and the calculation of the thermal resistance, will be explained in more detail.

4.4.1

MODELING OF THE CONVECTIVE BOUNDARIES

The effective heat transfer coefficient h e in Eq . (4.10) describes how significantly heat transfers between the object and the ambient. Its value is determined by both the package structure and the efficiency of the heat removal process. Consider a solid with the dimensions of 1000 µm x 1000 µm x 250 µm. It

84

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 4.16.

Layout of the solid containing three heat sources.

contains three heat sources with power values shown i n Fig. 4.16. The heat transfer coefficient of the bottom sink is given to be 10,000 (W/m² º C) . Let us assume that the top and the four sides of the solid have the same h e values of 0 (perfect insulation), 8.0 (natural convection), and 5,000. The simulated temperature profiles along the x direction at y = 500 µm are shown in Fig. 4.17 for these different h e values. For a packaged solid under the natural convective condition, the boundaries of the top and all four sides are often approximated as perfectly insulated in the thermal simulation. It is verified by the results shown in Fig. 4.17, where the temperature difference under the two conditions is very small. However, if a solid is under a forced-convective condition (e.g., h e = 5,000) , its boundaries can no longer be modeled as perfectly insulated. As can be seen from Fig. 4.17, the forced convection greatly reduces the overall temperature. The packaging effect, therefore, plays an important role in temperature calculation and must be modeled correctly.

4.4.2

MODELING OF HEAT FLOW PATHS

Figure 4.18 shows a unit-level layout of a prototype ULSI high-performance chip in its initial design phase with the flip-chip packaging technology. Each unit contains several functional unit blocks (FUBs), and the estimated power values of all FUBs are given. There are in total more than three hundred FUBs in the chip. A cross-sectional view of the flip-chip package is shown in Fig. 4.19. The flip-chip bonding technology offers a better packaging solution, but also brings challenges for heat removal from the chip to the package (through the

THERMAL SIMULATION FOR VLSI SYSTEMS

Figure 4.17. values.

85

Temperature profiles along the x direction at y = 500 µm for three different h e

Figure 4.18.

Unit-level layout of a high-performance chip

bumps in Fig. 4.19). Furthermore, the heat sink (i.e., heat pipe) must be efficient enough to serve as the major heat removal path. From measurements, the temperature at the surface of the heat pipe is estimated to be 45 ºC. The

86

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 4.19.

Table 4.4.

Ta 27 Ta 45 Tam R car- d own Rcar-side Rbump Runder R lid 1 Rlid 2 Rtp Rh 1 Rh 2 Rhs Rhm

Cross-sectional view of a flip-chip package. Definition of the symbols in Fig. 4.20.

Ambient temperature (27°C) Ambient temperature(45°C) Ambient temperature near mother board Thermal resistance for heat flowing through carrier down to the mother board Thermal resistance for heat flowing through carrier aside to the lids Thermal resistance for heat flowing through bumps Thermal resistance for heat flowing through underfills Thermal resistance for heat flowing through lids to air Thermal resistance for heat flowing through lids to the heat pipe Thermal resistance for heat flowing through the thermal paste Thermal resistance for heat transfer between lid surface and Ta 27 Thermal resistance for heat transfer between lid surface and Ta45 Thermal resistance for heat transfer between the thermal paste and Ta45 Thermal resistance for heat transfer between the carrier and mother board

equivalent thermal circuit of Fig. 4.19 is shown in Fig. 4.20, and the symbol definitions are listed in Table 4.4. To formulate the effective heat transfer macromodel, the thermal resistances of the carrier ( R c a r - d o w n , Rcar-side) and lids (Rlid1, Rlid2) among others need to be determined. To find the lumped value of R c a r - s i d e , for instance, the boundaries at four sides of the carrier is set to be in constant temperature

THERMAL SIMULATION FOR VLSI SYSTEMS

Figure 4.20.

87

Equivalent thermal circuit of the flip-chip package.

Figure 4.21. Method to determine the thermal resistances for heat flowing through the carrier aside to the lids.

Ta , and the top (except for the chip-carrier interface) and bottom surfaces of the carrier to be insulated. The lumped thermal resistance of the carrier can ), where I is the chip power, and Ta v g therefore be calculated as R = ( is the average temperature at the chip-carrier interface which is precharacterized by performing numerical or analytical thermal simulation on the carrier. This procedure is graphically shown in Fig. 4.21. To determine the values of the thermal resistances accounting for the heat transfer between package surfaces

88

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 4.22.

On-chip temperature contour for the first experiment.

and ambient (e.g., Rh1, R h 2 , R h s ), formula R = is used, where hp is the heat transfer coefficient from package to ambient and A is the surface area. Having discussed the package modeling, we now refer back to Fig. 4.20 and start the thermal simulation. In order to see how important the packaging effect is to the overall on-chip temperature, three different experiments are performed. In the first experiment, the contact resistance between the thermal paste and the heat pipe 0.15 ºC/W) is ignored. Figure. 4.22 shows a simulated temperature contour. In the second experiment, the contact resistance is taken into account, but it is assumed that no heat is flowing through the carrier (i.e., Rcar- side = Rcar-d o w n = The simulation result is shown in Fig. 4.23. In the last experiment, both the contact resistance and the finite carrier thermal resistance are considered, and the result is shown in Fig. 4.24. It is clear that different packaging structures and materials have significant impact on the bulk temperature distribution. An electrothermal simulator can thus beused to guide the thermally reliable package design and improve the chip performance.

4.5.

SUMMARY

This chapter deals with the topics related to the thermal simulation for VLSI systems.

THERMAL SIMULATION FOR VLSI SYSTEMS

Figure 4.23.

Figure 4.24.

On-chip temperature contour for the second experiment.

On-chip temperature contour for the third experiment.

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ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

90

The heat diffusion equation for describing heat conduction in solids is provided. In addition, the thermal boundary conditions and the initial temperature condition are given. The three thermal boundary conditions are:

–

Isothermal (Dirichlet) condition

–

Insulated (Neumann) condition

–

Convective (Robin) condition

A general description of the thermal simulation strategy for a simple chip substrate/package structure is given, and the effective heat transfer macromodel is described.

A thermal simulation framework that is developed mainly for the VLSI systems is presented. This framework consists of fast thermal analysis (FTA), numerical/analytical thermal simulation, package thermal simulation, and interconnect thermal simulation (discussed in Chapter 6). The FTA method is developed for efficiently identifying the on-chip hot spots.

–

It is based on the formulation and approximation of the Green’s functions.

–

The error function is approximated by a piecewise linear function

–

Six constraints are specified so that the original problem is simplified to a tractable level.

–

Experimental results show that the FTA method can quickly pinpoint the hot spots.

The finite-difference method (FDM) is chosen in this book as the numerical thermal simulation method.

–

The basic concept of the finite-difference approach is provided.

–

The adaptive meshing technique for distributing the grid lines with variable grid space in the FDM method is introduced.

–

The analogy between the thermal circuit and electrical circuit is provided.

–

The formulae of thermal conductance and capacitance in the 3 D grid system are derived. Similar expressions are derived for the system containing composite materials. Special care must be taken to model the boundary grids.

References

91

The analytical thermal simulation method is presented.

–

It is based on the integral transform (Fourier transform) and the associated multiple inversion techniques

–

The derivation of the analytical formula for a general 3D problem is presented.

–

The eigenfunctions and the analytical solutions of the steady-state problem with special thermal boundary conditions are provided as an example.

The above thermal simulation methods are compared. In general, the FTA method is the fastest, the numerical method is the most general, and the analytical method has the advantage when calculating the temperatures of a small number of spots. The package simulation method is presented. The importance of accurate package modeling is demonstrated. A prototype chip with the flip-chip package is used as a walk-through example:

–

Different heat flow paths in this structure are identified and modeled

–

The lumped thermal resistances of the packages are calculated

–

Three different experiments are performed. From the experimental results it can be seen that different packaging structure and materials can have significant impact on the bulk temperature distribution. An electrothermal simulator can be used to guide the thermally reliable package design.

References [1] M. N. Qzisik, Boundary Value Problems of Heat Conduction. New York, NY: Dover, 1968. [2] Y. K. Cheng, Electrothermal Simulation and Temperature-sensitive Relia bility Diagnosis for CMOS VLSI Circuits. PhD thesis, Dept.of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, 1997. [3] Y. K. Cheng and S. M. Kang, “An efficient method for hot-spot identification in ULSI circuits,” in Proceedings of the ACM/IEEE International Conference on Computer-Aided Design, pp. 124-127, Nov. 1999.

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[4] V. Dwyer, A. Franklin, and D. Campbell, “Thermal failure in semiconductor devices,” Solid-State Electronics, vol. 33 , pp. 553-560, May 1990. [5] K. Fukahori and P. R. Gray, “Computer simulation of integrated circuits in the presence of electrothermal interaction,” IEEE Journal of Solid-State Circuits, vol. 1 I , pp. 834-846, Dec. 1976. [6] Y. K. Cheng, P. Raha., C . C. Teng, E. Rosenbaum, and S. M. Kang, “ILLIADS-T: An electrothermal timing simulator for temperaturesensitive reliability diagnosis of CMOS VLSI chips,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, pp. 668-681, Aug. 1998. [7] G. Digele, S. Lindenkreuz, and E. Kasper, “Fully coupled dynamic electrothermal simulation.” IEEE Transactions on VLSI Systems, vol. 5, pp. 250– 257, Sept. 1997. [8] W. K. Chu and W. H. Kao, “A three-dimensional transient electrothermal simulation system for IC’s,” in Proceedings of the THERMINIC Workshop, pp. 201-207, Sept. 1995. [9] V. A. M. N. Sabry, A. Bontemps and R. Vahrmann, “Realistic and efficient simulation of electro-thermal effects in VLSI circuits,” IEEE Transactions on VLSI Systems, vol. 5 , pp. 283-289, Sept. 1997. [10] C. C. S. Wunsche and P. Schwarz, “Electro-thermal circuit simulation using simulator coupling,” IEEE Transactions on VLSI Systems, vol. 5, pp. 277-282, Sept. 1997. [11] B. D. J. P. Fradin. “Automatic computation of conductive conductances intervening in the thermal chain,” in Proceedings of the International Conference on Environmental Systems, July 1995.

[12] J. F. Thompson, Z. Warsi, and C. W. Mastin, Numerical Grid Generation. New York, NY: North-Holland, 1985. [I3] J. W. Brown and R. V. Churchill, Fourier Series and Boundary Value Problems. New York, NY: McGraw-Hill, 1993.

[14] D. G. Zill, Differential Equations with Boundary-Value Problems. Prindle, Weber & Schmidt, 1986. [15] W. F Ames, Nonlinear Partial Differential Equations in Engineering. Academic Press, New York, 1965. [16] J. N. Funk, M. P. Menguc, K. A. Tagavi, and C. J. Cremers, “A semianalytical method to predict printed circuit board package temperatures,”

References

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IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. 15, pp. 675-684, Oct. 1992. [17] V. Koval, I. W. Farmaga, A. J. Strojwas, and S. W. Director, “MONSTR: A complete thermal simulator of electronic systems,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 570-575, June 1994.

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Chapter 5

FAST-TIMING ELECTROTHERMAL SIMULATION

5.1.

INTRODUCTION

The electrical simulator in the electrothermal simulation framework calculates the power and the timing of a circuit. It must generate accurate results so that the electrothermal behaviors are well predicted. It also needs to be computationally efficient in order to simulate VLSI circuits with acceptable run time. Existing electrical simulators can be classified into the following classes: the circuit level, the timing level, the fast-timing level, the switch-level, and the logic level. The circuit-level simulators such as SPICE provide the most accurate voltage and current information for the circuit nodes. They are indispensable in modem digital and analog circuit design. However, they are computationally very expensive. The timing-level simulators [ 1, 2] are less costly than the circuit-level simulators but less accurate. In order to obtain orders of magnitude speedup over SPICE, techniques such as the table lookup and the event-driven simulation are employed in the timing-level simulators. The switch-level simulators [3, 4] model the MOS transistor as a switch controlled by the gate voltage. If the transistor is conducting, then the switch is closed; otherwise the switch is open. To provide the timing information at the switch level, simple delay models are often used. The fast timing simulators [ 5 , 6 ] were originally proposed to bridge the gap between the timing-level simulator and the switch-level simulator. They have the efficiency close to the switch-level simulators and the accuracy comparable to the timing-level simulators. The fast timing simulators generally possess the following features: the event-driven simulation is used the subcircuits are mapped into the macromodels or primitives

I

96

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS the node equations are solved by the analytical solution.

The fast timing simulators are not only computationally efficient, but can also be built with the accurate device model for submicron technology. Therefore, they are capable of simulating modern VLSI circuits. The electrothermal simulator, ILLIADS-T [7], was developed mainly for simulating the VLSI systems. It uses a fast timing simulator as its electrical simulation engine because of the advantages described above. ILLIADS-T was described in Chapter 1. In this chapter, it will be revisited with the focus on its simulation of a tester chip and other benchmark circuits. In the following, the underlying principles of the fast timing simulator used in ILLIADS-T will be described. The approach used to speed up the iteration process between the power and temperature calculation in ILLIADS-T will also be presented. The details of the tester chip design and the experiment setup for verifying the ILLIADS-T simulation result will be given. From the experimental results, it will be shown that the thermal effect can significantly impact the overall chip/circuit performance, even causing functional failures.

5.2.

ILLIADS: A FAST TIMING SIMULATOR

The major shortcoming of typical fast-timing simulation approaches lies in the lack of simulation accuracy. A major source of inaccuracy is due to the use of overly simplified MOS transistor models for the submicron devices with various short-channel effects. The other source is due to the inadequate mapping of gates or subcircuits to the circuit macromodels. To address the first inaccuracy problem, the regionwise quadratic (RWQ) device model [9] was developed for the accurate device modeling and circuit simulation. The details of the temperature-dependent RWQ model were described in Chapter 3. To solve the second inaccuracy problem, a fast timing simulator, ILLIADS, was developed [8]. A new circuit primitive is used in ILLIADS to reduce the mapping error. The resulting node equations for the primitive are then solved for the node voltages. The overview of the primitive formation and solutions in ILLIADS will be given next, followed by its simulation strategy.

5.2.1

PRIMITIVE FORMATION AND SOLUTIONS

The generic circuit primitive of MOS digital circuits used in ILLIADS is shown in Fig. 5.1. This primitive contains multiple branches of NMOS and PMOS transistors, linear coupling capacitances C (.), and linear conductances g(.). The output node voltage and the loading capacitance are denoted as and C L , respectively. The applied terminal voltages are represented by D ( . ) and G ( .).

FAST- TIMING ELECTROTHERMAL SIMULATION

Figure 5.1.

97

General MOS circuit primitive used in ILLIADS.

When the drain current i k of MOS transistor k is modeled by a quadratic function of its terminal voltages, it can be expressed as

(5.1) where p , q, r are integers that satisfy 0 p , q, r 2, and VT is the threshold voltage. The Shichman-Hodges model (see Eq. (3.1)) is a special case of Eq. (5.1). The current equations for the linear capacitors and conductors are given by (5.2) and (5.3) respectively, where c is the number of capacitors in the primitive and n is the total number of parallel branches in the primitive. When the waveforms of the applied terminal voltages D k and G k are piecewise linearized, the state equation of the output node of the primitive in Fig. 5.1 can be written as (5.4) with the initial condition V ( 0 )= V0. Substituting Eq. (5.1), Eq. (5.2) and Eq. (5.3) into Eq. (5.4), Eq. (5.4 ) can be recast to

(5.5) The coefficients k , p1, P0 , q 2 , q1, and q 0 are written in terms of the MOS transistor model parameters, capacitances, conductances, and input signals.

98

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Equation ( 5 . 5 ) belongs to the class of Riccati differential equations [11]. In the most general case, the analytical solutions for the Riccati differential equations can be found by using the hypergeometric functions [12]. An alternative approach is to use the power series method as done in ILLIADS. Detailed solutions of Eq. (5.5) and its degenerate forms are given in [10].

5.2.2

SIMULATION STRATEGIES

Given a circuit netlist, ILLIADS first partitions the circuit and groups the dc-connected blocks (DCCBs) using the breadth-first or depth-first search. A DCCB consists of a set of circuit nodes and elements that are connected through dc paths. Next, a directed graph (digraph) is constructed based on the connectivity of each DCCB. In order to detect the feedback loops, the vertices of the digraph are further partitioned into strongly connected components (SCCs). Each SCC contains DCCBs which can traverse to one another in the digraph. After the SCC partitioning, the circuit graph consists of condensed vertices which are either DCCBs or SCCs. The topological sort is then performed to obtain their temporal order. The SCC partitioning and the topological sort can be done simultaneously using the modified Tarjan’s algorithm [ 13]. The procedures for SCC formation and topological sort are illustrated by the example in Fig. 5.2. In ILLIADS, internal nodes (nodes that connect the dc paths of only one type of transistor, either NMOS or PMOS) are usually eliminated by merging serial or parallel transistors and forming the equivalent transistor. When necessary, however, internal nodes can also be simulated with the tradeoff of execution time. For serial merging of two transistors with transconductances ß1 and ß 2, the transconductance of the equivalent transistor is given by ßeq = ß 1 ß 2 / ( ß 1 + ß2 ).. The equivalent gate signal is taken to be the weaker segment of the two gate signals (i.e., lower voltage for NMOS transistors and higher voltage for PMOS transistors). For parallel transistor merging, the equivalent transconductance is given by ßeq = ß1 + ß2 , and the equivalent gate signal is the stronger segment of the two gate signals. Figure 5.3 illustrates the transistor merging and the internal node elimination process. After internal node elimination, the remaining circuit is mapped into a primitive with the generic structure shown in Fig. 5.1. For example, the circuit after node elimination in Fig. 5.3 is mapped into the primitive given in Fig. 5.4. Next, the state equation is formed and the corresponding Riccati differential equation is solved analytically. The analogous output waveform can thus be obtained and used as the input to the next DCCB after piecewise linearization. For the circuit containing SCCs, the DCCBs inside the SCC are first ordered by a greedy algorithm where the DCCBs with the most external inputs and the least feedbacks are put in front of the queue. The waveform-relaxation method [14] is used to simulate the SCCs. The waveform-relaxation algorithm

FAST-TIMING ELECTROTHERMAL SIMULATION

99

(a)

(b)

(c)

Figure 5.2. Illustrations of SCC formation and topological sort: (a) the original circuit, (b) the digraph representation, and (c) the condensed digraph after topological sort.

implemented in ILLIADS uses the partial waveform and time convergence and the dynamic windowing technique [8]. Note that the ILLIADS simulation efficiency is mostly contributed from the use of the analytical solutions of the Riccati differential equation. To formulate this equation, the drain current of the MOS transistor is assumed to follow the quadratic dependence on its terminal voltages. One such transistor model is the well-known Shichman-Hodges model. However, this model is not accurate enough for modeling the submicron devices. Therefore, a new quadraticcurrent model must be sought for in oder to improve the simulation accuracy

I00

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 5.3.

Figure 5.4. process.

Example of transistor merging and internal node elimination.

Primitive mapping for the circuit shown in Fig. 5.3 after the transistor merging

FAST-TIMING ELECTROTHERMAL SIMULATION

101

Algorithm DCCB POWER CALCULATION for (all DCCBs in the circuit) for (all simulated nodes in the DCCB) find voltage waveforms by solving the Riccati equation from the state equation of the node; for (all elements in DCCB connected to VDD) find the current waveform drawn from VDD; Iavg average the current waveform over the simulation period; Pavg Iavg X VDD; End DCCB POWER CALCULATION Figure 5.5.

DCCB power calculation using ILLIADS.

in ILLIADS. The RWQ modeling technique [9] introduced in Chapter 3 was developed mainly for this purpose.

5.2.3

POWER ESTIMATION USING ILLIADS

Given the input patterns, the average power of each DCCB (or gate) in the circuit can be calculated by using ILLIADS. In the ILLIADS-T electrothermal simulation flow, each DCCB is treated as a heat source and its power value is input to the thermal simulator. The procedure for the power calculation in ILLIADS is shown in Fig. 5.5. It is similar to the power-meter method proposed in [15]. However, instead of building the power-meter circuitry, ILLIADS directly solves the Riccati differential equation for each DCCB primitive and finds the current waveform drawn from the power supply for all branches that are connected to it. Like the power-meter method, ILLIADS can accurately calculate both dynamic and short-circuit power.

5.3.

INCREMENTAL ELECTROTHERMAL SIMULATION IN ILLIADS-T

The temperature-induced variations of the short-circuit power and the switching activity can affect the average power consumption of the logic gates. On the other hand, the changing power values can significantly perturb the original temperature distribution. As described in Chapter 1, because the power consumption and the temperature distribution are strongly dependent on each other, the decoupled electrothermal sirnulation flow in ILLIADS-T requires several iterations between the power and temperature calculation. When temperature and power converge to the values in the previous stimulation run, the final steady-state solution is found.

102

ELECTROTHERMAL ANALYSIS OF VLSl SYSTEMS Temperature and Power Variations

Figure 5.6.

Convergence plot for power and temperature.

The above observation is shown in Fig. 5.6, where a nine-stage ring oscillator is simulated by ILLIADS-T . The power and temperature values are recorded during the iteration process. In Fig. 5.6, the temperature difference between two successive simulation runs becomes smaller as the number of iterations increases. This trend indicates the feasibility of incremental simulation [16], in which the circuit parameters vary by small amounts compared to their previous values. Consider a circuit containing blocks that are ordered for simulation based on the fanin-fanout relationship. In ILLIADS-T, if the temperature difference in a block between current (perturbed) and previous (nominal) runs exceeds a prescribed threshold T-THRLD, then this block is considered to have local temperature variation and will be marked with T-VAR. If a block is marked with T-VAR, it is not considered to be incrementally latent and it needs to be simulated. The resimulated waveforms then serve as the nominal waveforms for the next simulation run. However, if a block is not marked with T-VAR, then the nominal and perturbed waveforms for all of the inputs to the block are compared. If the difference between them is less than a user-specified threshold, the block is marked as being incrementally latent and is not simulated (i.e., its perturbed solution will be the same as its nominal solution). On the other hand, if the difference in any of the inputs is larger than the threshold, the block is not considered to be latent and is simulated.

FAST-TIMING ELECTROTHERMAL SIMULATION

1 03

Figure 5.7. Illustration of incremental latency; the nominal waveforms are shown in solid lines, while the perturbed waveforms arc in dashed lines.

This procedure is illustrated in Fig. 5.7, where Block 1 and Block 4 have local temperature variations and are incrementally resimulated. For Block 2, there is no local temperature variation, but the difference between its nominal and perturbed input signals is large and it, too, is resimulated. However, Block 3 is considered to be latent because besides having no temperature variation, the difference between its nominal and perturbed inputs is very small. Thus, for Block 3, the incremental simulation is skipped and its perturbed solution is assumed to be the same as its nominal results. Note that ILLIADS-T identifies the blocks having local temperature variations dynamically in each new simulation run. In other words, a block can be marked with T-VAR in one run, but is not marked in another. As the number of iterations increases in the ILLIADS-T simulation, the advantage of the incremental approach will appear even greater because it is expected that a large number of latent cases will be detected. For larger circuits, it is also expected that the computational savings of latency will be more pronounced, because a larger number of blocks will be latent. Furthermore, for circuits with a larger temperature gradient (e.g., due to either a large power density variation or a special kind of boundary condition), the incremental technique will be even more effective. The simulation speedup due to the incremental approach will be presented later in this chapter.

5.4.

TESTER CHIP DESIGN AND CALIBRATION

A tester chip was designed for the verification of ILLIADS-T simulation accuracy [7]. It was fabricated using 0.8 µm CMOS technology and packaged by MOSIS. Figure 5.8 shows the microphotograph of the chip, where the blocks I. III and V are high-frequency 3-stage ring oscillators designed in a standard

104

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 5.8. Rosc3s.

Microphotograph of the tester chip; long blocks are Rosc149s and short blocks are

super-buffer configuration. Blocks II and IV are 149-stage ring oscillators, and the three small dots (D1, D2, D3) are temperature-monitoring diodes. Henceforth, the 3-stage and 149-stage oscillators are denoted as Rosc3s and Rosc149s, respectively. Each ring oscillator has an enable signal which is used to activate or deactivate the oscillator. In this design, the power is mainly dissipated by the Rosc3s. The onchip temperature can be determined by measuring the voltage drop across the forward-biased diodes according to VF = ( k T / q ) I n ( l F / I s ( T ) + 1), where I F is the forward-bias current provided by a constant current source. The reason why the diode is measured in the forward-biased mode is that in the reverse-biased mode, in addition to the thermal generation of carriers. other generation-recombination mechanisms are also present to affect the accuracy of the measurement.

FAST- TIMING ELECTROTHERMAL SIMULATION

Figure 5.9.

105

Four-terminal configuration for diode measurement

Figure 5.9 shows the diode circuit designed for the temperature measurement. Because the voltage drop across the lead resistance of the diode is also a function of the temperature, a four-terminal configuration is used to cancel out the voltage drop i n the test leads. The diodes were calibrated individually by measuring V F at different temperatures. The diode temperature was controlled by placing the chip upside-down on a hot plate after the chip lid had been removed. The temperatures on the surface of the hot plate were accurately determined by placing a thermistor on the plate and measuring its resistance values. These values were then translated to the temperatures of the thermistor, namely, the temperatures of the hot plate. The I F values were forced small (15 - 20 µA) to ensure that there is no self heating from the diode. An example of the calibration data is shown in Fig. 5.10, where both the stepwise I-V data and the glitch at 45 º C were caused by the measuring resolution. When the tester chip was operating, the local temperature near the diode was determined by using the calibration data. The package thermal parameters are also calibrated based on the MOSIS handbook for the DIP40 package. The effective heat transfer coefficient of the chip bottom (h e in Eq. (4. IO)) was determined to be 8,689 (W/(m² ºC)) with all other sides insulated.

5.5.

VERIFICATION OF ILLIADS-T

During the tester chip experiments, Rosc149s were always activated while the chip power consumption was varied by activating different Rosc3s. Depending on the on/off status of the Rosc3s, eight unique experiments can be performed as shown in Table 5.1. For instance, the ILLIADS-T-simulated

106

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 5.10.

Table 5.1. Expt. # Block 1 III V 1: on

1 111

2 110

Diode calibration example (D1).

Activation status of Rosc3s.

3 101

4 100

5 011

6 010

7

00 1

8 000

0: off.

temperature profiles for Expt. 2 (block I and III on, block V off) and Expt. 1 (all blocks on) are shown in Figs. 5.1 1 and 5.12, respectively. Note that the power dissipation from the output buffers of blocks I, III and V (O I , O1 II, and OV in Fig. 5.8) was also taken into account. The simulated and measured diode temperatures for all eight experiments are compared in Figs. 5.13 - 5.15. In these figures, the error bars show the spread of the measured data. Good agreement between measured and simulated temperatures was found. ILLIADS-T was also used to predict the frequency shift of Rosc149s due to the local temperature rise. The mobility-temperature relationship was extracted from frequency measurements on block II, and the mobility model Eq. (3.19) was employed to obtain the optimized fitting parameters A1 - A 4 Next, the mobility model was used in ILLIADS-T to predict the frequency shift of block IV for different cases. The results were compared with the measured data, and the measured and simulated waveforms of block IV are shown in Fig. 5.16 Fig. 5.19.

FAST-TIMING ELECTROTHERMAL SIMULATION

Figure 5.11.

Simulated temperature profile for Expt. 2.

Figure 5.12.

Simulated temperature profile for Expt. 1.

107

108

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 5.13

Comparison between simulated and measured temperatures for D1.

Figure 5.14.

Comparison between simulated and measured temperatures for D2.

FAST- TIMING ELECTROTHERMAL SIMULA TION

Figure 5.15.

109

Comparison between simulated and measured temperatures for D3.

Figure 5.16.

(a) Measured and (b) simulated waveforms for Expt. 8.

1 10

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 5.17.

(a) Measured and (b) simulated waveforms for Expt. 7.

Figure 5.18.

(a) Measured and (b) simulated waveforms for Expt. 5.

FAST-TIMING ELECTROTHERMAL SIMULATION

Figure 5.19.

11I

(a) Measured and (b) simulated waveforms for Expt. 1.

Table 5.2. Tester chip

P a v g [Watt]

Expt. 7 Expt. 5 Expt. 1

0.350 0.636 0.882

ILLIADS-T simulation results of the tester chip.

Tb l k4

[ o C]

44.17 56.03 63.43

Freq. shift [MHz] 14.07 14.07 14.07

11.53 10.35 9.62

CPU t i m e1 [sec] 422 650 822

¹ On SUN SPARC station 10 (numerical thermal simulation used) .

Additional simulation results are presented in Table 5.2, where Pavg is the average power consumption of the chip (including output buffers), and T b l k 4 is the average temperature of block IV. The oscillation frequencies of block IV before and after electrothermal simulation are shown in the fourth column of Table 5.2. Note that as the temperature increases, the oscillation frequency is significantly lowered and, consequently, so is the power. Therefore, the power values listed in Table 5.2 were calculated at the simulated operating temperature. The total CPU time for the electrothermal simulation (i.e., numerical thermal simulation was used) is shown in the last column i n Table 5.2 .

112

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS ROW- BASED FLEXIBLE-CELL LAYOUT

Figure 5.20.

5.6.

Layout of' the I0-bit negative adder.

ILLIADS-T SIMULATION EXAMPLES

In the following, the ILLIADS-T simulation results for a number of circuits are demonstrated. The top and the four sides of the circuits are assumed insulated, while the effective heat transfer coefficient of the bottom surface is assumed to be 3,000 (W/(m²K)) for all test circuits. A 10-bit negative adder is first considered with the layout shown in Fig. 5.20. The layout was generated by a synthesis tool iCGEN [17]. Simulation results are listed in Table 5.3, where n tra n and nhsrc are the numbers of transistors and heat sources in the circuit, respectively, P a v g is the average total power consumed in the circuit, Ta v g is the average circuit temperature, and n run is the number of repeated simulation runs before convergence. The symbol Sfac denotes the speedup factor of the electrothermal timing simulation, which is computed as the ratio of the total (i.e., including all simulation runs) transient analysis time without the incremental simulation to the transient analysis time with the incremental simulation. Table 5.3 also presents the ILLIADS-T simulation results for several other circuits such as HIGHWAY [18], ALU and control, and a 16-bit multiplier. Another simulation example is shown in Fig. 5.21. This chip contains two ISCAS85 benchmark circuits, C3540 and C6288, one negative adder, and two three-stage ring oscillators identical to Rosc3 in Fig. 5.8. The packaging structure for the chip is shown in Fig. 5.22 and the corresponding thermal parameters are given in Table 5.4. The heat transfer coefficient between the heat sink and the ambient is assumed to be 12,000 (W/(m²K)). Simulation results are presented in Table 5.5. Here, T m a x and T m in are the maximum and minimum temperatures of individual circuits; they were pinpointed by the

FAST-TIMING ELECTROTHERMAL SIMULATION

Table 5.3.

1Under

ILLIADS-T simulation results.

steady-state temperature distribution.

Table 5.3 (continued).

ILLIADS-T simulation results.

2 Convergence criterion < %1. for interation: ³ On SUN SPARCstation 10 (numerical thermal simulation used).

Figure 5.21.

Layout of the simulated chip.

1 13

114

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Reff = Rsolder + Rpolymer + Rsub +Rgel + Rsink + R h

Figure 5.22.

Table 5.4.

Packaging structure used in the simulation example.

Packaging parameters for thermal simulation.

Table 5.4 (continued).

Packaging parameters for thermal simulation.

FTA thermal analysis method and their temperatures were calculated by the analytical method. To demonstrate the importance of performing the temperature-dependent simulation, the output waveforms at bit ten of the negative adder with and without electrothermal simulation are compared in Fig. 5.23. The output was generated by asserting an input pulse at the first bit with the pulse width 2.5 ns. A logic fault was identified via the electrothermal simulation. This fault was caused by the combination of temperature rise and unbalanced circuit design. It can be observed that the pulse width of the output waveform, even at room temperature, is narrower than the input pulse width (2.5 ns) due to the

FAST-TIMING ELECTROTHERMAL SIMULATION Table 5.5.

Figure 5.23.

1 15

ILLIADS-T simulation results.

Output waveforms of the I0-bit negative adder.

unbalanced rise and fall path delays. This unbalance is aggregated at higher temperature and, finally at around 47 o C , the fault occurs before the output waveform can fully switch to ground. The average temperature of the whole layout in Fig. 5.21 was calculated to be 35 º C using ILLIADS -T. Note that when the temperature of the negative adder was assigned to 35 o C as would be used in conventional simulations, the logic fault still could not be detected as shown in Fig. 5.23. Simulation results suggest that the on-chip temperature variation must be considered in timing verification, and ILLIADS-T is one of the useful tools to ensure that the specified timing constraints are met.

116

5.7.

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

SUMMARY

This chapter presents a fast-timing electrothermal simulator - ILLIADS - T, which is developed for predicting the temperature distribution and the temperaturesensitive reliability of the VLSI systems. The fast-timing simulator used in ILLIADS-T, called ILLIADS, is presented: –

A generic circuit primitive used in ILLIADS is described.

–

The formation of the state equation and the solutions of the resulting Riccati differential equation are given.

–

The simulation strategy of ILLIADS, including the transistor grouping and merging, is described.

–

The ILLIADS power estimation method for calculating the power of the logic gates is illustrated.

An incremental strategy for the fast-timing electrothermal simulation is given. The details of the tester chip design, calibration and measurement for verifying the accuracy of ILLIADS-T simulation results are provided. A number of ILLIADS-T simulation examples are provided. It can be seen that, a logic fault can happen in a circuit and be inadvertently ignored in circuit analysis if the temperature rise or temperature gradient is not considered.

References [1] B . Chawla, H. Gummel, and P. Kozak, “MOTIS an MOS timing simulator,” IEEE Transactions on Circuits and Systems, vol. 22, pp. 90 1-909, Dec. 1994. –

[2] R. Saleh, J. Kleckner, and A. Newton, “Iterated timing analysis and SPLICE1 ,” in Proceedings of the ACM/IEEE International Conference on Computer-Aided Design, pp. 139-140, 1983.

[3] J. Ousterhout, “A switch-level timing verifier for digital MOS VLSI,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 4, no. July, pp. 336-349, 1985.

References

117

[4] V. B. Rao, Switch-level timing simulation of MOS VLSI circuits. PhD thesis, Dept. of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, 1985.

[ 5 ] D. Overhauser. Fast timing simulation of MOS VLSI circuits. PhD thesis, Dept. of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, 1989. [6] Y. H. Shih, Computationally efficient methods for accurate timing and reliability simulation of ultra-large MOS circuits. PhD thesis, Dept. of Electrical and Computer Engineering, University of Illinois at UrbanaChampaign, 1991. [7] Y. K. Cheng, P. Raha., C. C. Teng, E. Rosenbaum, and S. M. Kang. “ILLIADS-T: An electrothermal timing simulator for temperaturesensitive reliability diagnosis of CMOS VLSI chips,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, pp. 668-68 1,Aug. 1998. [8] Y. H. Shih, Y. Leblebici, and S. M. Kang, “ILLIADS: A fast timing and reliability simulator for digital MOS circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12. pp. 1387-1402, Sept. 1993.

[9] A. Dharchoudhury, S. M. Kang, K. H. Kim, and S. H. Lee, “Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics,” in Proceedings of the ACM/IEEE International Conference on Computer-Aided Design, pp. 208-21 I , Nov. 1994. [10]

Y. H. Shih and S. M. Kang, “Analytic transient solution of general MOS circuit primitives,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. l l, pp. 719-73 1, June 1992.

[11] W. T. Reid, Riccati Differential Equations. New York, NY: Academic Press, 1972. [12] H. Buchholz, The Confluent Hypergeometric Function. New York, NY:

Springer Verlag, 1969. [ 13] R. E. Tarjan, “Depth first search and linear graph algorithms,” SIAM J.

Comput., vol. 1, pp. 146-160, June 1972. [14] J. K. White and A. Sangiovanni-Vincentelli, Relaxation Techniques for the Simulation of VLSI Circuits. Norwell, MA: Kluwer, 1987.

[15] S. M. Kang, “Accurate simulation of power dissipation in VLSI circuits,”

IEEE Journal of Solid-State Circuits, vol. 21, pp. 889-891, Oct. 1986.

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II

THE APPLICATIONS

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Chapter 6

TEMPERATURE-DEPENDENT ELECTROMIGRATION RELIABILITY

6.1.

MOTIVATION

The device packing density in modern VLSI chips increases steadily. Therefore, the temperature rise in a packaged chip can be dramatic. Because many known IC failure mechanisms are either thermally activated or related, on-chip temperature profile must be predicted prior to any reliability diagnosis and performance analysis. In addition, temperature profile plays an important role in the application of thermal stress evaluation and package design at the chip or the printed-circuit-board (PCB) level. Note that due to large temperature variations across a packaged chip, the assumption of the uniform on-chip temperature usually is not acceptable. In this chapter, one major application of the electrothermal simulation will be presented: temperature-dependent electromigration reliability diagnosis. Other applications such as the cell-based thermal placement and the temperature-driven power/timing analysis will be addressed in subsequent chapters. In a state-of-the-art chip, the interconnect temperature can rise by as much as 100 º C above the ambient temperature attributed to different heat flow mechanisms. These mechanisms include heat conduction from the substrate, from the nearby interconnects, and heat generated in interconnect itself (Joule heating). The temperature affects the diffusion rate of the metal ions because the diffusivity of the ions is exponentially dependent on the temperature. This means that the ions diffuse more rapidly in areas where the temperature is elevated. If there is a temperature gradient i n the direction of current flow, an ion flux divergence will be created. Therefore for the locations with higher temperatures, vacancies are likely to form.

122

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 6.1.

The temperature effect on electromigration reliability.

The above temperature-dependent mass transport of metal ions, called electromigration (EM), can be described by the well-known Black’s equation [1]:

(6.1) In Eq. (6. 1), MTF stands for the EM-induced mean time to failure, A is a proportionality constant, J is the current density, Ea is the activation energy, k: is the Boltzmann’s constant, and T is the temperature in degree Kelvin. The physical meaning of the Black’s equation Eq. (6.1) will be discussed later. According to Eq. (6.1), the ratio of MTF(T = 300K) over MTF(T = 300K + AT) as a function of A T is shown in Fig. 6.1. From Fig. 6.1 it can be seen that if a metal line has a temperature equal to 340 K, its MTF will be twenty times shorter than the MTF when it is subject to the room temperature. It also suggests that neglecting the temperature effect in electromigration failure analysis can substantially overestimate the metal lifetime and lead to unacceptable prediction error.

6.2.

ELECTROMIGRATION (EM) PHYSICS

When a metal line is stressed at high current density, mass transport of metal ions driven by the electron wind will appear. This mass transport in metal is known as electromigration (EM). In the range of the device operating temperature, since metal ion flux due to the lattice diffusion inside the grain is much smaller than that due to the grain-boundary diffusion, the dominating

TEMPERATURE-DEPENDENT ELECTROMIGRATION RELIABILITY

123

modes of mass transport are along the grain boundary. The ion flux equation along the grain boundary can be expressed as

(6.2) where Z* is the effective charge of the ion at the grain boundary, p is the resistivity, n g b is the ion density in the grain boundary, uu is the average grain boundary width, d is the average grain size, D gb is the ion diffusion coefficient along the grain boundary, and J is the current density. Due to the structural inhomogeneities, temperature gradient, or stress gradient, the ion flux divergence will occur, i.e.,

(6.3) The flux divergence can induce damages in the forms of voiding and hillocks. Electromigration-induced voiding can grow and lead to resistance increase or even a catastrophic open of the interconnects. Electromigration-induced hillocks can cause both intralevel and interlevel metal shorts. The times and the locations of void-opens or extrusion-shorts are basically of statistical nature, depending on the spatial distribution of the flux divergence sites. The failure time, of course, is also determined by the magnitude of the flux divergence.

6.2.1

EM LIFETIME DEPENDENCE ON CURRENT DENSITY

The electromigration lifetime dependence on the current density under dc stress was first established by Black [ 1]. Basically a thermally activated metal ion is acted on by two forces in a metal line: (i) the force created by an electrical field applied to the conductor, and (ii) the rate of momentum exchange between conducting electrons colliding with the activated metal ion. Shielding effects reduce the electrical field effect so that the mass transport of metal ion is mainly driven by the momentum exchange. The rate of mass transport R can be expressed as

R

(electron momentum P)

x (number of electrons passing through a unit volume per second N ) x (effective target cross section) x (metal activated ion density)

(6.4)

where both the electron momentum P and the number of electrons passing through a unit volume per second N are linearly proportional to the metal current density J . The number of activated ions per unit volume follows the Arrhenius equation as a function of temperature: metal activated ion density

exp (-Ea / kT ) .

(6.5)

124

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Since metal MTF is inversely proportional to the rate of mass transport, Eq. (6.4) can be written as (6.6) which is the Black’s equation Eq. (6. I ). In Black’s equation, the inverse-current-square relationship of MTF is suggested. Hinode et al. [2] also found the same result based on both experiments and computer simulation. However, several experimental results have been reported for the values of the current density exponent from 1 to 16 ,which do not seem to have any agreement on the current density exponent, especially at the high current density range. Sakimoto et al. [3] indicated that the disagreement stems from the lack of accurate temperature data. In the hight current density regime, the self Joule heating increases the metal temperature significantly. If the measurement for the electromigration lifetime is carried out with accurate measurement of the metal temperature, then the current exponent in Black’s equation, which is equal to two, is valid at both low and high current density ranges.

6.2.2

EM LIFETIME DEPENDENCE ON CURRENT WAVEFORMS

In the digital circuit environment, the interconnect experiences unidirectional or bidirectional ac current stressing. Many models have been proposed to estimate the EM-induced failure lifetime under such current stress.

UNIDIRECTIONAL AC CURRENT STRESS Suppose that a metal line is subject to a repetitive pulsed current with a peak value. Intuitively, the MTF of this metal will be longer than the case when it is under the constant dc current stress of this peak value. In the early stage of electromigration research, Towner et al. [4] and Brooke [ 5 ] proposed an empirical electromigration failure model for the unidirectional pulsed current stress using experimental results:

(6.7) where MTF pulse is the EM-induced MTF under unidirectional pulsed current stress, and Ja vg is the average current density defined as

(6.8) Equation (6.7) is usually referred to as the average current model. Later, Maiz [6] applied the kinetics of material accumulation/depletion to approximate the electromigration failure model under pulsed current stress. In

TEMPERATURE-DEPENDENT ELECTROMIGRATION RELIABILITY

125

addition, other models have been proposed such as the vacancy supersaturation model by Clement [7] and the defect relaxation model by Tao et al. [8]. Al though different theoretical models were proposed, they all arrived at the same conclusion and validated the average current model for unidirectional pulsed current stress. Here, the defect relaxation model [8] will be used to explain the average current model. Assume that represents the volume of voiding in the interconnects. The increase of in the unit time is proportional to the product of vacancy concentration n and current density J . Hence,

(6.9) The proportionality constant R is a function of .. Suppose that at time MTF, the reaches some critical value and causes the failure of the interconnect. The above relation can be written as (6.10) where K is a constant. Assuming that the vacancy relaxation time is then rate of vacancy generation is proportional to

and the

(6.1 1)

If J is a dc current, by solving Eq. (6.1 1), the vacancy concentration can be obtained as follows (6.12) Substituting Eq. (6.12) into Eq. (6.10), then the MTFdc is (6.13)

If we set (6.14)

the MTF under dc stress can have a simple form: (6.15)

The above equation exactly matches the Black’s equation. Now considering a unidirectional pulsed current where the peak value is J and the duty factor is

126

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

D , solve Eq. (6.11) to obtain the vacancy concentration and apply the solution to Eq. (6.10) again. The MTF pulse can be obtained as (6.16) and ƒ is the frequency of the dc pulse. The vacancy where a = relaxation time is approximately equal to 1 ms. When the operating frequency 1 KHz, then Eq. (6.16) can be approximated is much higher than i.e., ƒ as (6.17) For an arbitrary unidirectional ac current waveform in the high frequency region, Eq. (6.7) is still valid [8, 9].

BIDIRECTIONAL AC CURRENT STRESS The signal lines between logic gates carry bidirectional current in the CMOS circuits. It is thus essential to assess the reliability of a metalization system under bidirectional current stress. It has been observed that the electromigration damage incurred by the positive (forward) current stress can be partially healed by the following negative (reverse) current stress [8 , 10, 11, 12, 13]. Ting et al. [ 12] have empirically shown that (6.18] This model is called the average current recovery model. The effective current density J e f f is defined as (6.19) where and are the average current density including only the positive and the negative current, respectively. In Eq. (6.19), is assumed. Considering the bidirectional pulse waveform shown in Fig. 6.2, for instance, we have (6.20)

(6.21) In Eq. (6.19), represents the degree of damage recovery due to the current with opposite polarity. It has to be in the range [0,1]. In the extreme cases, if = 0 , there is no healing effect in ac stressing, whereas if = 1, there is perfect healing during the negative pulse. Usually the value of is around 0.9. The validity of the average current model has been shown in [ 12].

TEMPERATURE-DEPENDENT ELECTROMIGRATION RELIABILITY

6.2.3

Figure 6.2.

An example of a bidirectional pulsed current density waveform.

Figure 6.3.

Electromigration MTF as a function of interconnect width [14].

127

EM LIFETIME DEPENDENCE ON INTERCONNECT WIDTH AND LENGTH

The electromigration lifetime as a function of the interconnect width is shown in Fig. 6.3. For interconnects with the width larger than the metal grain size (Figure 6.4(a)), the major mechanism of electromigration is the grain-boundary diffusion occurring in the triple points . Since the EM-induced open-circuit failure in the metal line is along its width, an increase of lifetime

128

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

(a) width larger than average grain size

(b) width smaller than average grain size. Figure 6.4.

Microstructure of' the interconnects.

with increasing line width is expected because the probability of making a wider interconnect open is smaller. However, as the width is reduced to comparable to or smaller than the mean grain size, the metal line becomes more or less a bamboo structure (Figure 6.4(b)). The lifetime is found to either level off or increase because the number of the triple points in the line with bamboo structure is much less. Thus, the mass transport of the metal ion is more difficult to occur. The electromigration lifetime dependence on the metal line length has been investigated in many papers [14, 15, 16, 17]. The simplest analysis method is to use the series model [ 17, 18]. The series model treats an interconnect of length L as a series connection of L unit lines. Assuming that the electromigration failure model follows the Weibull distribution, the MTF of an interconnect of length L can be derived as

(6.22) where m is the shape parameter of the Weibull distribution, and MTFu nit is the MTF of the interconnect of unit length. From the series model it can be seen that the MTF approaches zero as the metal line is long enough. The typical results of the electromigration lifetime dependence on the interconnect length are shown in Fig. 6.5 [15, 16]. The MTF decreases rapidly with increasing line length and then reaches a saturation value beyond a critical length. It clearly contradicts the series model prediction. Note that the series model treats every unit of interconnects as independent random variables, which is not true in the physical mechanism behind electromigration. In thin-film interconnects, the EM-induced damage due to flux divergence can occur at any intrinsic defects (e.g., dislocations of grain boundary) or extrinsic defects (e.g., process-induced defects [16]). In essence, the EMinduced failure lifetime is dependent on the most severe defect in the whole

TEMPERATURE-DEPENDENT ELECTROMIGRATION RELIABILITY

Figure 6.5 .

129

Electromigration MTF as a function of interconnect length.

interconnect, rather than on the number of the defects with the severity beyond a certain level. The possibility of finding more severe defects increases with the interconnect length, so that the lifetime of longer interconnects is shorter. However, because of the stability of processing and the characteristics of the material structure, the severity of extrinsic and intrinsic defects has an upper bound. Therefore, the EM-induced lifetime levels off when the interconnect length is greater than the critical length.

6.2.4

EM MODEL USED IN THE BOOK

There is still no consensus on the theory of the electromigration phenomenon. The analytical failure model for electromigration used in this book mainly adopts the average current recovery model in Eq. (6.1 8), which is derived from the theoretical and experimental works and is believed to be correct. A more general form of the average current recovery model describing the MTF of an interconnect can be expressed as: (6.23) where MTF l , w is the MTF of the interconnect with length l and width w. The proportionality constant A is now a function of l and w.

6.3.

EM SIMULATION: AN OVERVIEW

In a VLSI system, the development of computer programs that are capable of simulating a large number of interconnects and accurately predicting the

130

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 6.6.

SPIDER [19 ] for the simulation of interconnect reliability.

electromigration lifetime has been a constant challenge. SPIDER [9] was one of the first tools developed for the simulation of interconnect reliability. In SPIDER, users select a portion of the metal bus and specify the current sources to load the metal bus at specified contact points, as shown in Fig. 6.6. Then SPIDER extracts an equivalent RC network for the metal bus and simulates the network using SPICE [20]. The current waveforms of every segment of interconnects can be obtained and used for the design and analysis of the metal system. Another electromigration reliability CAD tool, called RELIANT [21], was developed in 1989. RELIANT extracts the interconnect network and the transistors from the circuit layout. A switch-level simulator, CURRANT [22], is then employed to calculate the current waveform of each interconnect. In CURRANT, each transistor is substituted by a resistor that represents the sourceto-drain resistance. An example demonstrating the substitution for a 2-input logic NAND gate is shown in Fig. 6.7. The value of the resistance depends on whether the transistor is on or off. Interconnects are represented by resistors and capacitors. Next, CURRANT analyzes the mapped RC network to determine the delay and the transient current waveform of each interconnect.

TEMPERATURE-DEPENDENTELECTROMIGRATION RELIABILITY

CMOS gate Figure 6.7.

131

CURRANT RC representation

CURRANT representation of a 2-input NAND gate.

RELIANT can handle large circuits, but the inaccurate switch-level simulator may cause significant errors, especially for the deep submicron technology. The Berkeley reliability tool (BERT) [23] is an integrated reliability tool. It can simulate the. circuit reliability of the hot-carrier effect, the time-dependent dielectric breakdown, and the electromigration. There are two modes of operation in BERT electromigration simulation. In the first mode, users provide a SPICE input file without any layout information. Then BERT generates a layout advisory based on the current flowing in the circuit and the user-specified reliability requirements. This advisory can be used for the design of an electromigration reliable interconnect system. The second mode is to simulate the electromigration failure rate for the given circuit layout. In this mode, BERT first extracts the circuit netlist from the target layout and generates a SPICE input deck. At the same time, it produces a geometry description file for all interconnects, vias, and metal-to-diffusion contacts. Next, BERT runs SPICE circuit simulation to obtain the current waveform of the transistors. The postprocessor of BERT calculates the failure rate as a function of the data in the geometry description file and the SPICE simulation result. Compared with RELIANT, BERT is much more accurate. However, it is computationally expensive due to the amount of CPU time that SPICE requires. Two other reliability simulators, RELIC [24] and RELY [25] , employ the approach similar to BERT for the electromigration simulation. All of the above electromigration CAD tools require users to provide either the input current load of the interconnects or the input vectors of the circuit. Their simulation results are strongly dependent on the specified input patterns. An alternative approach is to use the probabilistic simulation [26,27, 28] to

132

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 6.8.

A hierarchical environment for interconnect EM reliability diagnosis.

get the average current stress in interconnections without knowing the input patterns. However, the signal correlations between internal nodes in the probabilistic simulation need to be properly handled for accuracy. Since handling the signal correlation is difficult and expensive, the accuracy is usually traded for speed. Moreover, the average-case analysis is not able to predict the worst-case scenario, which is important in the design-for-reliability paradigm. A hierarchical electromigration reliability diagnosis tool [29] was developed to resolve the speed and accuracy problems in above approaches. Two levels of diagnosis hierarchy are used as shown in Fig. 6.8. The top hierarchy is the input pattern-independent electromigration diagnosis. It can quickly identify the critical interconnects with potential electromigration reliability problems. The corresponding input patterns which cause the worst-case current stress to each critical interconnect are also found. The problem size of the worst-case electromigration reliability analysis is thus significantly reduced and becomes tractable. Designers can focus on those critical interconnects and feed the corresponding critical input patterns into the second hierarchy: the input

TEMPERATURE-DEPENDENT ELECTROMIGRATION RELIABILITY

133

pattern-dependent electromigration reliability simulation. The simulation tool is called iTEM [30]. The acronym iTEM stands for the Illinois Temperature-dependent ElectroMigration diagnosis tool. It accurately computes the EM-induced failure of the interconnect system. One important feature of iTEM is that, in addition to the current density and the interconnect geometry, it takes into account the steady-state temperature of every interconnect under the given operating conditions. As mentioned earlier, the temperature effect is critical to the accuracy of the electromigration MTF estimation. In the following of the chapter, the temperature-dependent electromigration reliability diagnosis flow in iTEM will be examined in detail.

6.4.

ITEM: A TEMPERATURE-DEPENDENT EM DIAGNOSIS TOOL

In order to estimate the interconnect temperature, the first step is to find the substrate temperature distribution based on which the individual interconnect temperature can be calculated subsequently. Different approaches for finding the substrate temperature were presented and discussed in Chapter 4. Among all approaches, the fast timing electrothermal simulator ILLIADS-T [31] was mainly designed for the VLSI systems. Since iTEM also aims to predict the electromigration problems at the VLSI level, ILLIADS-T is employed as its simulation engine for substrate temperature calculation. The iTEM simulation flow is shown in Fig. 6.9. After the ILLIADS-T electrothermal simulation, iTEM extracts the power and ground buses from the layout and identifies the transistors i n contact with the ground/power buses. The correspondence between the bus and the transistors that are connected to it is also identified concurrently. The extraction procedures are similar to those used in [32 ]. Next, iTEM extracts the resistive networks from the buses and builds the admittance matrices for the networks. The currents drawn from the transistors connected to the buses serve as the current sources of the networks, and the admittance matrices of the network are solved. At this stage, the current waveform of each metal rectangle, via and metaldiffusion contact is found for the ground and power buses.

6.4.1

INTERCONNECT TEMPERATURE ESTIMATION

The previous discussion described the procedures for finding the substrate temperature profile and the interconnect current waveform for the ground and power buses. The next step is to estimate the interconnect temperature in order to accurately predict the EM-induced MTF. The following assumptions for interconnect temperature estimation are made in iTEM:

1 35

TEMPERATURE-DEPENDENT ELECTROMIGRATION RELIABILITY

6.4.2

ANALYTICAL MODEL OF INTERCONNECT THERMAL SYSTEM

To estimate the interconnect temperature, the following case shown in Fig. 6.10 is first examined. This structure consists of a long metal wire and an insulator on the substrate. The width and thickness of the metal line is w and t respectively, and the thickness of the insulator is ti . The resistivity p of the metal line is a function of temperature T as follows: (6.24) where is the resistivity at 0 ºC and is the temperature coefficient of resistivity. The Joule heating P j generated by a segment of interconnect with length A x is

(6.25) The heat Pi conducted to the substrate is

(6.26) where Rth is the thermal resistance between the interconnect and the silicon, T s is the substrate temperature, Tm is the metal temperature, and T m = T m – T s . In Eq. (6.26), K i,e f f is the effective thermal conductivity of the insulator taking into consideration the deviation from one-dimensional heat flow. Given that the thermal conductivity in the bulk of the insulator is Ki , the ratio of (Ki,eff / Ki ) is larger than I and increases when (ti /w) decreases, because the heat fringing effect increases. By using the Schwarz-Christoffel conformal transformation [33 , 34], the ratio of (Ki,eff / Ki ) can be approximated by

(6.27)

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ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

within 3% of error if w > 0.4ti. The heat diffusion equation along the x-axis in Fig. 6.10 is (6.28) where Km is the thermal conductivity of the metal. Substituting Eqs. (6.25) and (6.26) into Eq. (6.28) results in (6.29) The resistivity of the interconnect is temperature dependent as described in Eq. (6.24). When the temperature dependence of the resistivity is included, we have (6.30)

= 0 at steady state. Hence, the metal If the metal length is long enough, temperature Tm can be presented as [33, 35]: (6.31) where J = I / (w. . t ) is the current density. A 3-D numerical thermal simulator was used to verify the above equation. Two cases were simulated, In the first case, K i,e f f in Eq. (6.31) was replaced by Ki (i.e., the l-D model). In the second case, Eq. (6.27) was used for K i , e f f in Eq. (6.31). The results are shown in Fig. 6.1 1, where it can be seen that (i) the error resulting from the I-D model is not acceptable, and (ii) Eq. (6.31) matches quite well with the 3-D simulation if Eq. (6.27) is used for K i,e f f.

6.4.3

LUMPED MODEL OF INTERCONNECT THERMAL SYSTEM

A 3-D interconnect structure (Fig. 6.12(a)) carrying 9 MA/cm² current was simulated by a 3-D numerical thermal simulator with the substrate maintained at 350 K and the bond pads at 300 K. The result is given in Fig. 6.12(b). It shows that for the locations in the interconnect that are at least one thermal diffusion length away from the metal-diffusion contacts or pads, their temperatures are well-modeled by Eq. (6.3 1). However, the interconnect temperature of the points close to the contacts and pads does not follow Eq. (6.31) since the contacts and pads are good heat sinks.

TEMPERATURE-DEPENDENT ELECTROMIGRATION RELIABILITY

137

Figure 6.11 AT is a function of metal current density. The following parameters values are = 3.6 x 10- 6 cm, used to generate the data: t i = 2 µm, t = 0.5 µm, w = 2 µm , = 4.04 x 10-³ K-¹, Ki, = 1.835 W/(K.m), and Ts=300 K.

From the above observation, it is clear that Eq. (6.3) can overestimate the interconnect temperature in many situations. On the other hand, the boundary conditions of the full-chip interconnect thermal system are so complicated that it is impossible to solve the heat diffusion equation analytically like the methods used in [33, 35]. Instead, a lumped model to estimate the interconnect temperature was proposed in ITEM. Consider the structure of a metal interconnect on an insulator as shown in Fig. 6.13. The width and thickness of the metal line is w and t respectively, the insulator thickness is ti , and the current flowing through the metal is I. For a segment of interconnect with length the local thermal system can be mapped into the equivalent electrical network shown in Fig. 6.13 by using the thermal-electrical analogy described in Chapter 4. In Fig. 6.13, Vs and V m are the substrate and metal temperatures respectively. The Joule heating of the metal comprises two elements: I R and The first element is the constant current source in Fig. 6.13, which is the primary contributor of Joule heating and is calculated as (6.32)

As mentioned before, the metal resistivity increases with temperature (Eq. (6.24)). Therefore the second element of Joule heating can be represented by a voltage-

138

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

(a) Cross-sectional view

(b) Temperature distribution Figure 6.12. (a) Interconnect with contacts to substrate, and (b) the corresponding temperature distribution from 3-D thermal simulation. Note that the interconnect temperature is reduced near the contacts and bond pads.

dependent current source that is due to the resistivity increase caused by the interconnect temperature rise: (6.33)

In Fig. 6.13, Rm is the thermal resistor of the metal given by (6.34) where Km is the thermal conductivity of the metal. The thermal conduction path between the interconnect and the chip substrate is described by Ri. If

TEMPERATURE-DEPENDENT ELECTROMIGRA TION RELIABILITY

Figure 6.13.

139

A lumped model of the interconnect thermal system.

the material between the metal and the substrate (i.e., Area 2 in Fig. 6.13) is insulator, then (6.35) If the material is metal, i.e, contacts, then

(6.36) Based on the lumped model, let us again examine the long metal line structure the interconnect temperature shown in Fig. 6.10. Since Rm Vm is

(6.37)

After substituting Eqs. (6.32), (6.33) , and (6.35) into the above equation, an expression for Vm (i.e., Tm ) will be obtained, which is the same as Eq. (6.31). An important shape of the interconnect that needs to be taken into account is the right-angle bend (L-shape), as shown in Fig. 6.14. A two-dimensional analytical formula is used to approximate the thermal resistance of the corner

140

ELECTROTHERMAL ANALYSIS O F VLSI SYSTEMS

Figure 6.14.

A right-angle bend conductor.

rectangle [37]: (6.38)

where a is the ratio of wide-to-narrow widths of the corner rectangle. (In Fig. 6.14 , a = W1 / W2 with the assumption that w 1 w 2 .) A similar equation can be derived for the T-shape. For those irregularly shaped conductors requiring the high accuracy of the heat resistance calculation, the finite-difference or finite-element method can be used [37]. For the heat interaction between the interconnects in different layers, iTEM only considers the heat path through the vias. An example of the lumped model for the interconnect thermal system near a via is shown in Fig. 6.15. The above lumped thermal models were verified by the accurate 3-D numerical thermal simulation. The first structure tested is a long interconnect with four contacts to the substrate as shown in Fig. 6.16(a). The simulation parameters are the same as in Fig. 6.1 1. The substrate temperature is maintained at 300 K. Figure 6.16(b) shows the simulated interconnect temperature distribution along the x-axis when the interconnect current densities are 2 MA/cm² and 3 MA/cm² . The second structure is a two-layer metal structure. Metal 1 has two contacts to the substrate, and Metal 2 has one via to Metal 1 as shown in Fig. 6.17(a). The thickness between different layers is 1 µm. The substrate temperature is maintained at 300 K and the current density at both metal layers is 3 MA/cm². The simulation results are shown Fig. 6.17(b). In both examples, the temperature difference between the simulation results using the lumped model and the 3-D simulation is at most 1 K. This difference is mostly due to the inherent error of K i,e f f . (See Fig. 6.11.) Using the lumped thermal model, the procedure of interconnect temperature estimation in iTEM is shown in Fig. 6.18. The first step is to partition the interconnect layout according to the geometry . An example is given in Fig. 6.19. The partitioning rule is almost the same as that used in the parasitic resistance extraction [38]. After partitioning, every segment of the intercon-

I 41

TEMPERATURE-DEPENDENT ELECTROMIGRATION RELIABILITY

Figure 6.15.

A lumped model of the interconnect thermal system near a via.

nects is mapped into a thermal resistor as shown in Fig. 6.13. Thus, a thermal resistive network describing the interconnect thermal system is obtained. Next, the admittance matrix of the thermal network is formed and the interconnect temperatures are solved. Note that the contacts in one source/drain area are usually very close to each other. To reduce the number of nodes in the interconnect thermal resistive network without loss of accuracy, the contacts that belong to one diffusion region can be heuristically grouped into one segment. For instance, the entire segment A X with four contacts in Fig. 6.20 will be mapped into one lumped thermal resistive network since the four contacts locate in the same diffusion area. The materials below the interconnect with multiple contacts are not homogeneous. The equivalent thermal resistance method [39] can be applied to describe the non-homogeneous heat path between the metal and the substrate. For example, in Fig. 6.20:

(6.39)

142

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

(a) A simulated structure

(b) Simulation results Figure 6.16. (a) Simulated interconnect structure with four contacts to substrate. (b) Comparison of the thermal simulation results using lumped thermal model and 3-D simulation.

where

(6.40)

The same structure shown in Fig. 6. I6(a) is again simulated, but the distance between contacts is reduced to 2 µm. The current density is assumed 3 MA/cm². Two partitioning strategies are compared. One is to partition the four contacts into different segments as in Fig. 6.21(a). The other is to lump the contacts together and use the concept of equivalent thermal resistance as in Fig. 6.21(b). The result in Fig. 6.22 indicates that lumping the close contacts together is a proper approximation, which substantially reduces the complexity of the thermal resistive network.

TEMPERATURE-DEPENDENT ELECTROMIGRATION RELIABILITY

I43

(a) A simulated structure

(b) Simulation results Figure 6.17. (a) Simulated multi-layered interconnect structure. (b) Comparison of thermal simulation results using lumped thermal model and 3-D simulation.

6.4.4

ITEM SIMULATION EXAMPLES

Figure 6.23 is the layout of the 10-bit negative adder used as a test circuit with the input signal frequency of 300 MHz. Its power/ground bus layout is shown in Fig. 6.24. Based on the iTEM simulation, the electromigration diagnosis result is shown in Fig. 6.25 for the region within the box in Fig. 6.23. The number marked in each metal rectangle and contact is the predicted MTF in hours. Several metal lines have an “Inf” MTF since there exist transistors not switching during the simulation period.

144

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 6.18.

Figure 6.19. estimator.

Procedure of the interconnect temperature estimator.

Example of partitioning the interconnect layout in the interconnect temperature

Next, a large circuit containing about 110k transistors is simulated. It is an 8 x 8 2-D discrete cosine transformation (DCT) chip [40] and its power bus

TEMPERATURE-DEPENDENT ELECTROMIGRATION RELIABILITY

Figure 6.20.

Figure 6.21.

145

The lumped thermal model for a transistor with multiple contacts.

Strategies for grouping contacts that are close to each other.

layout is shown in Fig. 6.26. The electromigration diagnosis result for a small region of the layout is shown in Fig. 6.27. Finally, the detailed iTEM simulation results for four different circuits are shown in Table 6.1. Twenty input vectors are input into each testing circuit. The MTF shown in the table is the shortest MTF among all interconnects in the circuit. Note that the predicted MTF may decrease as much as 17 times if

146

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 6.22.

Simulation results of multiple contacts which are close to each other.

Figure 6.23.

A layout of I0-bit negative adder.

the heating effects are considered. Therefore, the electrothermal analysis must be done prior to the electromigration diagnosis in order to pinpoint the true locations that are susceptible to electromigration problems.

TEMPERATURE-DEPENDENT ELECTROMIGRATION RELIABILITY

Figure 6.24.

147

The power/ground bus layout of 10-bit negative adder.

Figure 6.25 . iTEM simulation result of the I0-bit negative adder. The number marked is the predicted electromigration MTF in hours.

148

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 6.26.

6.5.

The power and ground bus layouts of the 2-D discrete cosine transformation chip.

SUMMARY

In this chapter, the temperature-dependent electromigration (EM) reliability diagnosis is discussed. Because the EM-induced mean time to failure is inversely proportional to the interconnect temperature, the temperature effect

TEMPERATURE-DEPENDENT ELECTROMIGRATION RELIABILITY

149

Figure 6.27. iTEM simulation result of the 2-D discrete cosine transformation chip. The number marked is the predicted electromigration MTF in hours.

is significant and must be taken into account in electromigration diagnosis in order to accurately predict the interconnect lifetime. The cause of electromigration phenomena is described. In addition to temperature, the electromigration lifetime is dependent on:

–

interconnect current density

–

interconnect current waveform

–

interconnect width

–

interconnect length

150

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS Table 6.1.

Simulation results of i TEM.

For the current density, the inverse-current-square relationship is commonly observed. For the current waveform, the mean times to failure resulting from the unidirectional and bidirectional current stress modes are derived and compared. An average current model is used in both modes, while the healing effect is considered in the bidirectional mode. The interconnect lifetime dependence on its width is examined for the metal with the triple-point structure and the bamboo structure. The interconnect lifetime dependence on its length is modeled based on the series model with slight modification. The electromigration model for circuit simulation used in this book is given. An overview of existing electromigration diagnosis tools is provided. The temperature-dependent electromigration diagnosis tool, called iTEM, is introduced. This tool takes into account the interconnect temperature as one of its modeling parameters.

–

The interconnect temperature is estimated based on the substrate temperature, which can be found by thermal simulation introduced in Chapter 4.

–

Three assumptions are made in iTEM electromigration analysis.

–

An analytical model for estimating the interconnect temperature is derived. Although this model is simple and general accurate, it cannot accurately estimate the temperature near the heat sinks such as the metal contact (via) and the bond pad.

References

151

–

To remedy the above accuracy problem, a lumped thermal model is derived for estimating the temperatures of the interconnect system. This model utilizes the thermal-electrical analogy, and the interconnect temperatures can be found by solving the node voltages of the thermal circuit. The thermal circuit is comprised of a constant current source to model the Joule heating, a voltage-dependent current source to model the resistivity increase caused by rising temperature, and thermal resistances. The analytical formulae for finding the thermal resistance of the L-shaped and T-shaped metals are provided.

–

The layout partitioning and contact grouping strategies in the iTEM analysis flow are presented.

–

Finally, iTEM simulation examples are given. It is shown that the mean time to failure of the interconnect is significantly reduced if the temperature effect is considered.

References [ 1] J. R. Black, “Electromigration failure modes i n aluminum metalization for semiconductor devices,” P roceedings of the IEEE , vol. 57, pp. 1587-1594, Sept. 1969.

[2] K. Hinode, T. Furusawa, and Y. Homma, “Dependence of electromigration lifetime on the square of current density,” in Proceedings of the IEEE International Reliability Physics Symposium, pp. 317-326, 1993. [3] M . Sakimoto, T. Itoo, T. Fujii, H. Yamaguchi, and K. Eguchi, “Temperature measurement of AI metallization and the study of Black’s model in high current density,” in Proceedings of the IEEE International Reliability Physics Symposium , pp. 333-341, 1995. [4] J. M . Towner and E. P. van de Ven, “Aluminum electromigration under pulsed DC conditions,” in Proceedings of the IEEE International Reliability Physics Symposium, pp. 36-39, 1983. [ 5 ] L. Brooke, “Pulsed current electromigration failure model,” in Proceedings of the IEEE International Reliability Physics Symposium, pp. 136 -139, 1987.

[6] J. A. Maiz, “Characterization of electromigration under bidirectional (BC) and pulsed unidirectional (PDC) currents,” in Proceedings of the IEEE International Reliability Physics Symposium, pp. 220-228, 1988.

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[7] J. J. Clement, “Vacancy supersaturation model for electromigration failure under DC and pulsed DC stress,” Journal of Applied Physics, vol. 91, pp. 4264-4268, May 1992.

[8] J. Tao, N. Cheung, and C. Hu, “An electromigration failure model for interconnects under pulsed and bidirectional current stressing,” IEEE Transactions on Electron Devices, vol. 41, pp. 539-545, Apr. 1994. [9] B. K. Liew, N. Cheung, and C. Hu, “Projecting interconnect electromigration lifetime for arbitrary current waveforms,” IEEE Transactions on Electron Devices , vol. 37, pp. 1343-1351, May 1990. [I0] J. Tao, K. Young, C. A. Pico, N. Cheung, and C. Hu, “Electromigration characteristics of AI/W via contact under unidirectional and bidirectional current conditions,” in Proceedings of the IEEE VLSI Multilevel Interconnection Conference, pp. 390-392, 1991. [11] J. Tao, N. Cheung, and C. Hu, “Metal electromigration damage healing under bidirectional current stress,” IEEE Electron Device Letters, vol. 14, pp. 554-556, Dec. 1993.

[I2] L. M. Ting, J. S. May, W. R. Hunter, and J. W. McPherson, “AC electromigration characterization and modeling of multilayered interconnects,” in Proceedings of the IEEE International Reliability Physics Symposium, pp. 31 1-316, 1993. [I3] J. Tao, N. W. Cheung, and C. Hu, “Modeling electromigration lifetime under bidirectional current stress,” IEEE Electron Device Letters, pp. 476478, Nov. 1995. [14] T. Kwok, “Effect of metal line geometry on electromigration lifetime in

A1-Cu submicron interconnects,” in Proceedings of the IEEE International Reliability Physics Symposium, pp. 185-191. 1988. [15] B. N. Agarwala, M. J. Attardo, and A. P. Ingraham, “Dependence of electromigration-induced failure time on length and width of aluminum thin-film conductors,” Journal of Applied Physics, vol. 41, pp. 3954-3960, Oct. 1970.

[16] T. Kwok, J. Finnegan, and D. Johnson, “Effect of linelength and bend structure on electromigration lifetime in AI-Cu submicron interconnects,” in Proceedings of the IEEE VLSI Multilevel Interconnection Conference, pp. 436-445, 1988. [17] T. Nogami, S. Oka, K. Naganuma, T. Nakata, C. Maeda, and 0. Haida, “Electromigration lifetime as a function of line length or step number,”

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system for modeling VLSI metallization patterns,” IEEE Transactions on Computer-Aided Design of I ntegrated Circuits and Systems , vol. CAD-36, pp. 1023-103 1, Nov. 1987. [20] L. W. Nagel, SPICE2: A Computer Program to Simulate Semiconduc tor Circuits. PhD thesis, Dept.of Electrical Engineering, University of California at Berkeley, 1975. [21] D. F. Frost and K. F. Poole, “RELIANT: A reliability analysis tool for VLSI interconnects,” IEEE Journal of Solid-State Circuits, vol. 24, pp. 458- 462, Apr. 1989.

[22] D. A. Haeussler and K. F. Poole, “CURRANT: A current prediction software tool using a switch-level simulator,” in IEEE Southeastern ’89 Proceedings, pp. 946-948, 1989. [23]

R. H. Tu, E. Rosenbaum, W. Y. Chan, C. C. Li, E. Minami, K. Quader, P. K. Ko, and C. Hu , “Berkeley reliability tools-BERT,’’IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, pp. 1524–1534, Oct. 1993.

[24] T. S. Hohol and L. A. Glasser, “RELIC: A reliability simulator for integrated circuits,” in Proceedings of the ACM/IEEE International Conference on Computer-Aided Design , pp. 5 17- 520, Nov. 1986.

[25] B. J. Sheu, W.-J. Hsu, and B. W. Lee, “An integrated circuit reliability simulator-RELY,” IEEE Journal of Solid -State Circuits, vol. 24.pp. 473477, Apr. 1989.

[26] F. N. Najm, R. Burch, P. Yang, and I. N. Hajj, “CREST - a current estimation for CMOS circuits,” in Proceedings of the ACM/IEEE International Conference on Computer - Aided Design , pp. 204-207, 1988.

[27] F. N. Najm, R. Burch, P. Yang, and I. N. Hajj, “Probabilistic simulation for reliability analysis of CMOS VLSI circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, pp. 439450, Apr. 1990.

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[28] F. N. Najm, I. N. Hajj, and P. Yang, “An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits,” IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, vol.10 , pp. 1372-1381, Nov. 1991. [29] C. C. Teng, Y. K. Cheng, E. Rosenbaum, and S. M. Kang, “Hierarchical electromigration reliability diagnosis for VLSI interconnects,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 752-757, June 1996. [30] C. C. Teng, Y. K. Cheng, E. Rosenbaum, and S. M. Kang, “ITEM: A new electromigration (EM) reliability diagnosis tool using electrothermal timing simulation,” in Proceedings of the IEEE International Reliability Physics Symposium, pp. 172-179, 1996.

[31] Y. K. Cheng, P. Raha., C. C. Teng, E. Rosenbaum, and S. M. Kang, “ILLIADS-T: An electrothermal timing simulator for temperaturesensitive reliability diagnosis of CMOS VLSI chips,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, pp. 668-68 1, Aug. 1998. [32] R. M. Iimura, “iCHARM: Hierarchical CMOS circuit extraction with power bus extraction,” Master’s thesis, Dept. of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, 1990.

[33] H. A. Schafft, “Thermal analysis of electromigration test structures,” IEEE Transactions on Electron Devices, pp. 664–672, Mar. 1987. [34] A. A. Bilotti, “Static temperature distribution in IC chips with isothermal heat source,” IEEE Transactions on Electron Devices, pp. 217-226. Mar. 1974. [35] H. Katto, M. Harada, and Y. Higuchi, “Wafer-level JRAMP and JCONSTANT electromigration testing of conventional and SWEAT patterns assisted by a thermal and electrical simulator,” in Proceedings of the IEEE International Reliability Physics Symposium, pp. 85-88, 1991. [36] THUNDER User’s Manual. SILVACO Data Systems, 1993. [37] S. L. Su , Extraction of MOS VLSI Circuits Models Including Critical Interconnect Parasities. PhD thesis, Dept. of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, 1987.

[38] S. L. Su, V. B. Rao, and T. N. Trick, “HPEX: A hierarchical parasitic circuit extractor,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 566-569, 1987.

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Chapter 7

TEMPERATURE-DRIVEN CELL PLACEMENT

7.1.

INTRODUCTION

The smaller feature size, higher packing density and rising power consumption have led to dramatic temperature increase in modem VLSI circuits. Moreover, the cross-chip temperature differential larger than tens of degrees has been commonly observed. Because the circuit delay and many IC reliability problems are strongly temperature dependent, the hot spots often become the performance and reliability bottlenecks and create serious design constraints as illustrated in previous chapters. Consequently, the capability to assess and optimize the thermal quality throughout the VLSI design process is critically important. Since the thermal (temperature) distribution profile of a design is largely determined by the cell locations, cell placement is the natural starting point of a temperature-aware design flow. In this chapter, it will be shown that careful cell placement at the physical design stage can help improve the thermal distribution of the design, adding little or only minor overhead to conventional design objectives such as area and delay.

7.2.

OVERVIEW

The majority of the previous studies on the thermal placement problem were mostly conducted in the context of placing chips for printed circuit boards (PCBs) and multi-chip modules (MCMs) [1]-[4]. Due to the differences in boundary conditions and problem granularity, these results are not directly applicable at the cell level. A more relevant study can be found in [ 5 ] ,where the authors proposed a generic force-directed placement algorithm that can potentially incorporate the power distribution of a placement as one of the placement considerations. In [6] the authors modeled the thermal placement problem as a matrix synthesis

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ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

O ptimal_Power_Density_Distribution

Figure 7.1(a). Optimal heat distribution for a design with a core size 12mm x 12mm. The power density of the fixed cell near the lower-right corner of the layout is lower than the chip average.

problem where the temperature distribution is optimized by uniform distribution of heat sources (gates) on the chip. There is one common issue that the above two papers did not address: Due to the finite thermal conductivity of the packaging components and the presence of the hard-placed cells, uniform heat distribution does not lead to uniform temperature profile. Therefore, if the thermal placement problem is formulated as to optimally distribute the heat sources, then the optimal heat distribution under the given thermal boundary conditions and design specifications (i.e. the location and power dissipation of any hard-placed cell) must be found first. Figures 7.l(a) and 7.l(b) illustrates this concept. A particular design with one fixed cell and with a total power of 30 Watts is used in this example. Figure 7.l(a) shows the optimal heat distribution of the design in order to produce the temperature profile in Fig. 7. I (b) that is uniformly flat outside the fixed cell. It can be seen that the optimal heat distribution is not uniform due to the effects of boundary conditions and the existence of hard-placed cells. Another limiting factor of the approach taken in [6] is the assumption of constant gate power dissipation. The power dissipated by individual cells is affected by the load capacitances, which do not remain constant during the placement as the locations of other cells change. As a result, the cell power dissipation in the final placement may be significantly different from the cell power

TEMPERATURE-DRIVEN CELL PLACEMENT

159

Even Temp Dist

Figure 7.l(b). Optimal temperature distribution resulting from the heat distribution in Fig. 7.l(a).

calculated before placement. It is not clear how the matrix synthesis algorithm can adapt to on-the-fly power estimation required for thermal placement at the gate level. In [7], the above limiting factors are addressed: The authors proposed a method for standard cell placement that aims to reduce the number of hot spots while optimizing traditional design metrics such as area and wire length. By using the superposition principle and the concept of transfer thermal resistance, the temperature distribution constraint is converted to its corresponding power distribution constraint under arbitrary boundary conditions. The power distribution constraint is then gradually tightened during the placement process by simulated annealing to produce improved temperature profile. Later in [8], an approach similar to [7] was proposed for macrocell thermal placement. A new thermal penalty term is added to the overall cost function during the modified simulated annealing process. The thermal simulator in [7] and [8] calculates the steady-state substrate temperature based on the finite-difference method as described in chapter 4. Enhancement is made in their work to reduce the matrix size during numerical simulation by deriving a compact substrate thermal model. The remainder of this chapter will begin with the discussion of this model. Two thermal placement algorithms proposed in [7] and [8] will also be examined.

160

7.3.

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

SUBSTRATE TEMPERATURE CALCULATION

The heat diffusion equation and its discretized form used in the numerical finite-difference formulation were discussed in Chapter 4. If the thermal conductivity k is uniform (i.e., independent of position and temperature), the heat diffusion equation at steady state can be expressed as

(7.1) which is a linear equation. By combining Eq. (4.28), Eq. (4.29), and Eq. (7. 1), we have

(7.2) where y,z) is the discretized heat source, and all of the time-dependent terms are omitted for steady state. Equivalently, Eq. (7.2) can be written as

(7.3) By exploiting the thermal-electrical analogy, T N can be shown to be the node voltage (temperature) at node N = ( i ,j , k ) , gi,j be the (thermal) conductance between node i and node j , and be the injection current at node Equation (7.3) is in fact the KCL equation for node N . Writing the same equation for every node i in the substrate mesh and compiling these equations into a matrix form, we have

(7.4)

with v denoting the node temperature, and i the power dissipation at each node. These notations will be followed henceforth. Note that the matrix G in Eq. (7.4) is symmetric and positive definite. The computational cost associated with solving the nodal matrix equation in Eq. (7.4) is too expensive to be used directly in an iterative placement algorithm for temperature calculation and optimization. Consequently, for temperatureaware physical design, either a more efficient temperature calculation method or an alternative approach is needed. In the following section it will be shown that this can be achieved by using a more compact substrate thermal model.

TEMPERATURE-DRIVEN CELL PLACEMENT

7.4.

16I

COMPACT SUBSTRATE THERMAL MODELING

In this section, two methods are discussed to derive the compact substrate thermal model for thermal placement. The first method employs the superposition principle to construct a transfer thermal resistance matrix, and is independent of the methods used to obtain the substrate temperature values. The superposition principle applies here because Eq. (7.1) is linear. The second method involves only direct manipulation of the nodal matrix equation, and is applicable when the user chooses a numerical method such as the finitedifference method that uses such a matrix equation for temperature calculation.

7.4.1

TRANSFER THERMAL RESISTANCE MATRIX

Assume that the substrate surface is discretized into a collection of m points where movable cells can reside. These points also act as the temperature monitor points. The temperature values at these m locations can be found by using a numerical method, or by experiments. By the superposition principle, the temperature values at these points are simply the sum of the separate temperature profiles created by individual heat sources in the system:

Ttotal

+

T fixed-cells + Tambient

=

Tmovable- cells

=

Tmovable-cells + T B C

(7.5)

where T m o v a b l e - c e l l s , Tƒixed-cells and Tambient are the temperature profiles at the m monitor points caused by movable cells, hard-placed cells and the ambient individually. Here, TBC stands for the temperature set by the ambient and fixed cells. Note that vectors such as T B C are shown in bold type. Applying the superposition principle further to the monitor points on the substrate surface that are to be covered by movable cells, we have:

(7.6) where Ti is the temperature profile caused by the power located at monitor point i alone. of point i with respect to Let us define the transfer thermal resistance point j as the rise in temperature at point i due to one unit of power dissipated at point j :

(7.7)

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ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

We can define a for every grid point pair (i, j ) among the m surface monitor points, and represent these resistances in the matrix form

(7.8)

The matrix R t is the transfer thermal resistance matrix. For any cell power distribution P = [P1, P2, . . . , Pm] on the monitor grid points, Tm o v a b l e_ c e l l s can be calculated by direct matrix multiplication:

(7.9)

Thej t h column in the transfer thermal resistance matrix, ..., is simply the temperature at points 1 , 2 , . . . , m of the monitored grid points due to one Watt of power dissipated at point j , and can be calculated by using any temperature calculation method or measured experimentally. Combining Eq. (7.5) and Eq . (7.9), we have

(7.10)

where T BC can also be found by using any computational or experimental method. Once R t and T BC are obtained, the temperature profile due to any power distribution can be calculated by direct matrix multiplication. Alternatively, for any desired thermal distribution, one can determine the corresponding power distribution by treating [P1, P2,. . . , Pm as unknowns and solving for Eq. (7.10). As an example, let us define the optimal substrate temperature profile as one that is perfectly uniform, and the optimal power distribution as one that creates such an optimal temperature profile. Then for the given set of boundary conditions and total power dissipation, the optimal power distribution

TEMPERATURE-DRIVEN CELL PLACEMENT

163

and the corresponding uniform substrate temperature can be obtained by solving the following matrix equation:

(7.1 1 )

where T BC = . .., P total is the sum of the power dissipated by all movable cells, P = [P1, P2, . . . , Pm] is the optimal power distribution with Pi = Ptotal, and Ts is the optimal temperature under the given total power and boundary conditions. This is how the optimal power distribution map was generated in Fig. 7.l(a).

7.4.2

ADMITTANCE MATRIX REDUCTION

The transfer thermal resistance matrix can also be obtained through direct reduction of the admittance matrix that is constructed by numerical methods such as the finite-difference method for temperature calculation. Assuming the 3-D substrate mesh has m + 1port nodes (including the thermal ground) and n internal nodes, the thermal conductance matrix G in Eq. (7.4) has m n,rows and columns. If the nodes are reordered such that the first m rows correspond to the port nodes and the final n rows to the internal nodes, Eq. (7.4) can be rewritten as

+

(7.12) where vp and V I represent the m port temperatures and n internal node temperatures, respectively, and ip denotes the power dissipation at the port nodes. The dimensions of the submatrices in Eq. (7.12) are m x m for G p , n x m for G c , and n, x n for G I . Note that the internal node part of i is zero. It is because there is no heat dissipated at these nodes in a chip (i.e., heat sources are normally distributed on the top surface). If the multiport admittance is defined as Y ip/vp. and V I is eliminated in Eq. (7.12), we have (7.13) The power dissipations at the port nodes and their temperatures are thus related by a simple matrix equation: (7.14) All internal nodes in Eq. (7.14) have been entirely eliminated, which results in a much smaller admittance matrix Y of dimension m x m, compared with the

164

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

+

+

original G of size ( m n) x ( m n).The reduced network has exactly the same input/output characteristics as the original network; no additional error is introduced by the reduction. Because G I is symmetric and positive definite, the Cholesky factorization can be applied to compute the inverse of G I , which is more efficient than the LU factorization. The matrix Y is in fact the inverse of the transfer thermal resistance matrix derived i n the previous section: (7.15) The resulting Y is usually very dense, meaning that the reduced thermal resistive network is strongly connected.

7.4.3

RUNTIME EFFICIENCY OF COMPACT THERMAL MODELING

The following complexity analysis is based on the assumption that, the same network admittance matrix constructed by the numerical method (such as the finite-difference method) is used for both compact model derivation methods described in Sections 7.4.1 and 7.4.2. Again, assuming there are m 1 port nodes (including the thermal ground) and n internal nodes in the original thermal network. The first method, described in Section 7.4.1, involves decomposing the admittance matrix of size ( m n)x (m n)once, whose runtime complexity is O ( ( m n)³) if LU or Cholesky factorization is used. In addition, it requires forward/backward substitutions m. times, whose complexity is O(m(m n)²). Therefore the total complexity of the first method is O (( m n)³) O(m(m

+

+

n)²)

+

+

+

O ( ( m+ n)³).

+

+

+

The runtime complexity of the second method, introduced in Section 7.4.2, can be obtained by analyzing the complexity of Eq. (7.14). Eq. (7.14) includes inverting the matrix G I of dimension n x n,two matrix multiplications, and a matrix subtraction. The complexity of inverting G I is O(n³); the complexity of the multiplications is O(mn²); and the complexity of the subtraction is O(m²). The total complexity of the second method is thus O(n³)+O(mn²)+O(m²) 0(n³) if m n,or O(n³) O(mn²) otherwise. Since m < n almost always holds in practice, it can be easily seen that the second method is more efficient. The first method should be used only when experimental results are readily available and can be used to construct the transfer thermal resistance matrix R t without further computation, or if the temperature calculation tools at hand do not utilize the mesh network as the substrate thermal model (such as those based on the Green’s function solutions). It is important to point out that the simple discussion carried out above does not consider the performance improvement of employing advanced sparse

+

TEMPERATURE-DRIVEN CELL PLACEMENT

165

matrix solving techniques. More careful and complicated analysis is required if such techniques are to be used.

7.5.

THERMAL PLACEMENT ALGORITHMS

The block diagram of the thermal placement algorithm based on the compact thermal modeling is shown in Fig. 7.2. The whole process consists of three main steps:

Figure 7.2.

Block diagram of the thermal placement algorithm.

1. substrate thermal model derivation 2. thermal objective construction

3 . placement with thermal objective optimization For reasons that will become clear, standard cell and macro cell designs require different thermal objectives and strategies for thermal distribution optimization. In the following these steps will be discussed in detail for both design styles.

7.5.1

STANDARD CELL THERMAL PLACEMENT

The first step in standard cell thermal placement is to construct the matrix Y . As described in Section. 7.4.2, the matrix Y is reduced from the network admittance matrix G that is built by using the finite-difference method. Next, the matrix Y is used to convert the user specified thermal (temperature) distribution objective into the corresponding power distribution objective. The specified

166

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

thermal distribution objective can be either a uniform or a non-uniform thermal distribution, which is based upon the locations of the temperature-sensitive components such as the analog or the clock generation modules. In the following discussion, it is assumed that a uniform thermal distribution is used as the objective, and this objective is determined from the average substrate temperature. With the estimated total chip power, the average substrate temperature is first calculated by using (7.16) where Ta is the ambient temperature, Pchip is the total chip power, and Rth is the equivalent thermal resistance of the packaging components. Then a user-adjustable temperature slack is added to Tavg to form the temperature objective. This temperature objective is converted into the corresponding power distribution by using Eq. (7.14). The calculated power constraint Pabj = [P1,P2 . . . , Pm]T becomes the final power budget at the m port grid points. Finally, Pobj is multiplied by a user-specified factor to get the starting power budget. Power budgets are used to prune the cell movements during the simulated annealing process. Specifically, a cell movement changes the lengths of the nets that the cell is connected to, thereby changing the power dissipation on the cells directly connected to the moving cell. For any proposed cell movement, the power dissipation changes at all m, monitor grid points are first recalculated. If the proposed cell movement only increases the power at those grid points where the power dissipations do not exceed the current budget, then the movement passes the budget test. Conversely, for the grid points where the power already exceed the budget. if the proposed movement further increases their power dissipation, then this movement is immediately rejected. The power budget is gradually tightened from the starting value to the final value Pobj during the placement process according to the cooling schedule. The revised simulated annealing algorithm is shown in Fig. 7.3. There are a few issues worth further discussion: 1. The estimated total power in Eq. (7.16), from which the average substrate temperature is estimated, can be provided by the user. Or alternatively, a few number of random placements can be generated in order to obtain a quick estimate of the total power dissipation by using the following equation:

(7.17) where fclk is the clock frequency, V DD is the power supply voltage, C l o a d (i) is the load capacitance of cell i, and Srate (i) is the rate of switching activity at the output pin of cell i .

TEMPERATURE-DRIVEN CELL PLACEMENT

167

Algorithm SIMULATED ANNEALING do do GenerateMovement ( ) ; () ;

reject=Check_Power_Budget ( ) ; if (reject) continue; = Compute-Cost-Change ( ) ; Accept T ); until in equilibrium; Reduce ( T ); Reduce_Budget ( T ); until cost cannot be further reduced; End SIMULATED ANNEALING Figure 7.3. Revised simulated annealing algorithm for standard cell thermal placement.

2. Given the final power budget Pobj, one might be tempted to adopt a penaltybased approach for thermal optimization by adding an additional thermal penalty term to the cost function for the simulated annealing engine to optimize. However, unlike typical penalties such as cell overlaps or timing violations, thermal penalty usually cannot be completely eliminated by placement alone. Thus the presence of thermal penalty usually results in suboptimal placements. Depending on the weightings of different objectives, it can be shown from experiments that the penalty-based approach could result in up to 50% increase in total wirelength and up to 20% increase in area [ 7 ] , which underperforms the above constraint-based method. Tradeoffs between the traditional and the thermal objectives will be demonstrated later in the simulation results section.

3. It is not necessary to add an equal amount of temperature slack to the average substrate temperature to form the thermal distribution constraint. For instance, if the design contains certain temperature sensitive subcircuits, it is beneficial to enforce a more rigid temperature constraint locally, while relaxing the constraint in non-critical regions.

4. The thermal distribution calculation is only as accurate as the power estimation. Accurate power estimation is a research topic that is being actively studied, and a general overview has been given in Chapter 2. The thermal placement algorithm introduced above is quite general and can be used with any power estimation technique. For instance, Eq. (7.17) can be replaced with a more accurate power measure.

168

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

5. The above constraint-based placement method can also be applied to circuits with multiple power dissipation patterns, such as the sequential circuits or the microprocessors with gated clocks. One only needs to apply the power budget test (i.e. Check_Power_Budget ( ) )in the algorithm to all possible power dissipation scenarios.

7.5.2

MACROCELL THERMAL PLACEMENT

The reasons why the macrocell thermal placement demands a different implementation strategy from the standard cell thermal placement can be best understood by considering the sources of hot spots in a design. There are basically two such sources: One is the fast-switching, high power-consumption cells and the other is the thermal coupling between nearby hot cells. Although the power dissipation of standard cells are affected by their wire load and thus their relative cell locations, it is safe to assume that for macrocells the power remain relatively constant regardless of the placement. As a result, a flatter power distribution cannot be enforced simply by moving cells around, as what is done in the case of standard cell design. The only way to improve the thermal distribution quality is by reducing the degree of thermal coupling between cells. Thus it is important for the thermal placement objective to capture the coupling effect. The most straightforward way to do so is to use the actual substrate surface temperature. To avoid the pitfall of lengthy simulation during placement, the compact substrate thermal model can be used to calculate the temperature efficiently. Again the placement process begins with the construction of the Y matrix. It is then inverted to form the transfer thermal resistance matrix R t . Any desired thermal distribution can still be specified as the objective. During simulated annealing, the thermal profile is updated incrementally as follows. Suppose at a particular iteration the annealer moves cell a with heat dissipation Pa from grid point i to point j . The following new vector can be formed:

with the entry -Pa at location i and Pa at location j , respectively. The incremental temperature profile change is then calculated by T’ = R t x P¹. The vector T’ can subsequently be added back to the original temperature profile to obtain the final profile. Thermal penalty is calculated according to the degree of discrepancy between the new profile and the desired one. It is important for the thermal penalty to discourage uneven temperature profile, as well as to reduce the maximum on-chip temperature. Inadequately constructed thermal penalty might in some cases result in very hot spots within very small areas. For the implementation in [8], the following formula is used

TEMPERATURE-DRIVEN CELL PLACEMENT

169

Algorithm SIMULATED ANNEALING do do GenerateMovement ( ) ; Update_Temp_Dist () ; = Compute-Cost-Change ( ) ; Accept T ); until in equilibrium; Reduce(?'); until cost cannot be further reduced; End SIMULATED ANNEALING Figure 7.4. Revised simulated annealing algorithm for macrocell thermal placement.

for calculating the thermal penalty: (7.18) where m is the number of surface nodes, T[.] is the temperature profile of the current placement, Top is the optimal surface temperature, Tmax is the maximum surface temperature, and and ß are user controllable scaling factors. The algorithm for macrocell thermal placement is given in Fig. 7.4. It is virtually the same as the placement algorithm in [9], except that the cost function now contains the extra thermal penalty term shown in Eq. (7.18) in addition to the original terms for area and wirelength. The algorithm can still handle designs with multiple power dissipation patterns; one only needs to calculate the temperature and insert an additional thermal penalty term for every power dissipation pattern individually.

7.6.

SIMULATION EXAMPLES

The thermal placement tool based on the above algorithms can be used effectively. The programs were implemented in the C language. The cooling schedule for simulated annealing is adopted from [10]. The tool was applied to six standard cell (biomed,primary1, primary2, s p l , struct and industry1) and two macrocell benchmark circuits (ami33 and ami49), and the simulation results on a machine with Intel Pentium 233MMX CPU and 64MB physical memory are listed in Tables 7.1 and 7.2. For the standard cell circuits, the cell power dissipation is estimated according to Eq. (7.17), with the rate of switching activities randomly generated between 0 1 for each net. The input pin capacitance of each gate is assumed to be 0.1 pF, and the wire capacitance is assumed 242 pF/m. The clock frequency is assumed to be ˜

170

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS Table 7.1.

Standard cell thermal

Table 7.1 (continued).

Table 7.2.

placement

simulation results

Standard cell thermal placement simulation results.

Macrocell thermal placement simulation results.

800 MHz. For the macrocell circuits, the cell power dissipation is randomly generated by assigning cells power densities ranging from 2.2 x 10* (W/m²) to 2.4 x 106 (W/m²), which are the typical values in modem high performance circuits such as microprocessors. Thermal conductivity of the package is assumed to be 7 (W/mºC) for the sides, 2000 (W/mºC) for the top, and 8800 (W/m°C) for the bottom for all cases. The finite-difference mesh used for the substrate thermal modeling has 20 ˜ 40 grid lines in the X and Y directions, and 6 i n the Z direction. The runtime of the pre-characterization phase (including substrate thermal model reduction,

Table 7.2 (continued).

Macrocell thermal placement simulation results.

TEMPERATURE-DRIVEN CELL PLACEMENT

171

thermal/power objectives construction, etc) varies between 1 ~ 5 minutes. In Tables 7.1 and 7.2, Tmax is the maximum on-chip temperature, Ltotal is the estimated total wire length, and CPU is the execution time of the placement tool. The net length is estimated by using the half-perimeter bounding box model. The numbers in parentheses are the thermal placement results in percentage term of the traditional placement results, in which only the total wirelength and area are used as the optimization objectives. Overall, the thermal placement algorithms provide noticeable improvements in thermal distribution in the final layouts. An execution time overheads of 30% ~ 50% were observed for the case of standard cell thermal placement. This runtime overhead primarily stems from the increased cell movement attempts due to rejecting cell movements that will worsen the thermal constraint violations. For standard cell thermal placement, no area increase was observed for all circuits, and on average the thermal placement algorithm yields approximately the same or slightly smaller total wire lengths than using the traditional placement approach. One possible explanation of the slightly better wire length results is that rejecting thermal constraint violating cell movements effectively results in a slower annealing schedule, which tends to produce better results if the original annealing process is not absolutely optimal. In view of wirelength and area, the results for macrocell thermal placement are showing more overhead in comparison with the case of standard cell placement. The runtime overheads range between 140% ~ 170%, which come primarily from the matrix multiplications in estimating the incremental temperature profile change, and also from the evaluation of Eq. (7.18). Final areas increase only slightly (< 5%), but the wirelength increases are between 5% ~ 10% even after extensive tweaking of Eq. (7.18). Without tweaking, the wirelength and final area could easily increase up to 30%. It is obvious that the tradeoff does exist between the traditional and thermal objectives after the addition of the thermal penalty term in the simulated annealing cost function. Currently no reported implementation strategy that is based on power distribution can capture the thermal coupling effects, without wirelength or area degradation when taking the thermal profile quality into placement consideration. This is a subject worth further investigation. To illustrate the thermal distribution improvement, the temperature profiles of ami49 before and after thermal placement are shown in Fig. 7.5(a) and Fig. 7.5(b). The histograms of the temperature values at the surface grid points for all benchmarks are given in Fig. 7.6 - Fig. 7.13. Note that in all simulations the ambient temperature is assumed to be zero, therefore all the temperature values shown in the figures are caused by cell power dissipation alone.

172

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Original Temperature Profile of ami49 Tmax = 79.74, Tmin = 19.13

Figure 7.5(a). Temperature profiles of benchmark ami49 without thermal placement ambient temperature is assumed to be zero.

7.7.

The

SUMMARY

This chapter describes two cell placement tools for improving the substrate thermal distribution of both standard cell and macro cell designs. An brief overview of existing thermal placement studies are given. –

–

It is pointed out that the uniform power distribution does not guarantee uniform temperature distribution. A limiting factor of most existing thermal placement tools is the assumption of constant power dissipation, which is not true when the loading capacitance changes during placement.

The substrate temperature calculation that was introduced in Chapter 4 is revisited in this chapter. The finite-difference equations for all nodes in the thermal system are represented in a matrix form. This matrix form serves as the basis for later compact substrate thermal modeling. The concept of the compact substrate thermal modeling is presented. –

The compact substrate thermal model significantly improves the efficiency of the temperature profile estimation and optimization.

TEMPERATURE-DRIVEN CELL PLACEMENT

173

Optimized Temperature Profile of ami49 Tmax = 50 29 Tmin = 24 84

Figure 7.5(b). Temperature profiles of benchmark ami49 with thermal placement. The ambient temperature is assumed to be zero.

–

Two approaches for deriving the compact thermal models are described and their runtime efficiencies are compared. The first approach uses the superposition principle to construct the transfer thermal resistance matrix. The second approach directly manipulates the nodal admittance matrix.

Two thermal placement algorithms that utilize the compact substrate thermal modeling are discussed; one is for the standard cell placement and the other is for the macrocell placement. –

–

For the standard cell thermal placement, a new simulated annealing algorithm is developed and presented. During the annealing process, the power budget that constrains the cell movement is gradually tightened according to the cooling schedule. For the macrocell thermal placement, it is pointed out that the thermal coupling effect between macrocells is dominant. A thermal penalty term is added to the cost function during placement to discourage uneven temperature distribution.

The above thermal placement algorithms can be applied to the designs with multiple power dissipation patterns, such as sequential circuits or

174

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

(a)

(b)

Figure 7.6. Histograms of on-chip temperatures of ami33 (a) before and (b) after thermal placement.

(a)

(b)

Figure 7.7. Histograms of on-chip temperatures of ami49 (a) before and (b) after thermal placement.

TEMPERATURE-DRIVEN CELL PLACEMENT

(a) Figure 7.8. placement.

175

(b)

Histograms of on-chip temperatures of biomed (a) before and (b) after thermal

(a)

(b)

Figure 7.9. Histograms of on-chip temperatures of primary 1 (a) before and (b) after thermal placement.

176

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

(a)

(a)

Figure 7.10. Histograms of on-chip temperatures of primary 2 (a) before and (b) after thermal placement.

(a)

(b)

Figure 7.11. Histograms of on-chip temperatures of spl (a) before and (b) after thermal placement.

TEMPERATURE-DRIVEN CELL PLACEMENT

(a) Figure 7.12. placement.

177

(b)

Histograms of on-chip temperatures of struct (a) before and (b) after thermal

(a)

( b)

Figure 7.13. Histograms of on-chip temperatures of industry I (a) before and (b) after thermal placement.

178

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

microprocessors. It is useful in controlling the local operating temperatures at temperature sensitive subcircuits for mixed-signal or system-on-a-chip designs. Simulation examples are provided for both standard cell and macrocell placement. By applying the thermal placement algorithms, the temperature distribution becomes more uniform with little impact on area and wire length. The possibility of extending the thermal placement algorithms to other physical design processes such as floorplanning and netlist partition ing/routing is addressed.

References [1] M. D. Osterman and M. Pecht, “Component placement for reliability on conductively cooled printed wiring boards,” ASME Journal of Packaging, 111(3):149-156, 1989. [2] R. Darveaux, I. Turlik, L. T. Hwang, and A. Reisman, “Thermal stress analysis of a multichip package design,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, pp. 663-672, Dec. 1989. [3] M. D. Osterman and M. Pecht, “Placement for reliability and routability of convectively cooled PWBs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 9(7):734-744, Jul. 1990. [4] K. Y. Chao and D. F. Wong, “Thermal placement for high performance multi-chip modules,” i n Proceedings of the IEEE International Conference on Computer Design, pp. 218-223, Oct. 1995

[ 5 ] H. Eisenmann and F. M. Johannes, “Generic global placement and floorplanning,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 269-274, June 1998. [6] C. N. Chu and D. F. Wong, “ A matrix synthesis approach to thermal placement,” in Proceedings of the 1997 International Symposium on Physical Design, pp. 163-168, 1997. [7] C. H. Tsai and S. M. Kang, “Standard cell placement for even on-chip thermal distribution,” in Proceedings of the International Symposium on Physical Design, pp. 179- 1 82, April 1999. [8] C. H. Tsai and S. M. Kang, “Macrocell placement with temperature profile optimization,” in Proceedings of the International Symposium on Circuits and Systems, pp. 390-393, 1999.

References

179

[9] C . Sechen and A. Sangiovanni-Vincentelli, “The TimberWolf placement and routing package,” IEEE Journal of Solid - S tate Circuits, Vol. SC- 20, NO. 2, April 1985, pp. 510-522.

[10] M. Huang, F. Romeo and A. Sangiovani-Vincentelli, “An efficient general cooling schedule for simulated annealing,” in Proceedings of the Interna tional Conference on Computer-Aided Design, pp. 381-384, Nov. 1986.

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Chapter 8

TEMPERATURE-DRIVENPOWER AND TIMING ANALYSIS

8.1.

INTRODUCTION

It has been shown in Chapter 3 that the MOS transistors are sensitive to their local temperatures. The carrier mobility and the driving capability of the source-drain current are reduced at higher temperatures. As a result, the circuit performance can be considerably degraded if the on-chip temperature is not well controlled. This was also evidenced by the experiments shown in Chapter 5 . Indeed, the avoidance of hot spots is exactly the reason why the thermal placement concept introduced in Chapter 7 is important. Given the fact that the circuit delay is strongly dependent on temperature, one may want to know how the on-chip temperature gradient affects the overall chip timing. To be more specific, one may ask, “Does a critical path become less critical, or a non-critical path become critical because of the on-chip temperature gradient?" This chapter addresses the above question. To find the steady-state temperature distribution for temperature-dependent timing analysis, the statistical power and temperature estimation techniques are used. As described in Chapter 2, the statistical power analysis is an efficient and accurate way for the average power estimation. Moreover, it is more meaningful to handle the environmental variables such as temperature in a statistical manner when the system timing is concerned. Figure 8.1 shows the relationship between power, temperature, and timing in a VLSI system. The temperature variation directly impacts the power consumption (i.e., short-circuit power and leakage power) and delay. On the other hand, different power distribution can generate very different temperature profile. In order to accommodate the degraded timing due to temperature rise, the clock frequency must be adjusted, which in turn changes the power con-

181

182

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 8.1.

Relations between power, temperature, and timing.

sumption. Since the power, temperature, and timing are mutually related, this chapter discusses the temperature-driven power and timing analysis as a single subject. In the following, the general overview of timing analysis techniques will be given first. The base methodology used in the statistical power and temperature estimation will be discussed next. Finally, the temperature-dependent timing analysis, including the delay modeling and the analysis results, will be presented.

8.2.

TIMING ANALYSIS OVERVIEW

Timing analysis is one of the most critical tasks in high-performance ULSI system design. Over the last decade, designers have increasingly resorted to timing analysis tools to check whether a given circuit meets the performance goal (i.e., clock speed). Timing analysis of the ULSI design consists ofchecking for short and long path (critical path) problems. Traditional timing analysis methods consist of two branches: dynamic and static methods. Not only are the underlying concepts of the two methods distinct, the delay models used can also be totally different. In the following, both methods will be discussed with the comparison of their pros and cons.

8.2.1

DYNAMIC TIMING ANALYSIS

Dynamic timing analysis is also called the delay simulation. It simulates a design with input patterns and collects the timing (delay) information. The simulation engines used in the dynamic timing analysis are similar to those used in the power analysis, which were discussed in Chapter 2. Dynamic timing analysis approaches have been widely used for studying the timing of a design. After the simulation, the waveforms at primary outputs are inspected and the timing violations will be reported. The timing relationships such as setup and hold among the internal signals are also verified. Moreover, the dynamic timing analysis can be used for functional verification as well.

TEMPERATURE-DRIVEN POWER AND TIMING ANALYSIS

183

Normally in dynamic timing analysis, the input pattern that triggers the critical path can be easily identified with no extra computational cost. It is because the input patterns are exercised one at a time and the circuit timing is monitored for each pattern. Since it is always good to know which input pattern causes the timing to fail, the dynamic timing analysis can produce such information as its by-product. Another advantage of the dynamic timing analysis is that it avoids the false path problem. The definition of a false path will be given later when static timing analysis is discussed. Because it is necessary to identify all possible timing errors in timing analysis, a complete set of input patterns need to be generated in this dynamic approach. Unfortunately, the generation of the complete set or the set that covers all possibilities can be difficult. Even if such a set is generated, it is impractical to simulate all input patterns in this set in an exhaustive way if the design is large or complex. Therefore, the dynamic timing analysis is primarily used for small circuits. It can also be used to accurately compute the delay of the paths that are known to be critical.

8.2.2

STATIC TIMING ANALYSIS

The static timing analysis identifies timing violations without the knowledge of input patterns, therefore it is much faster than the dynamic timing analysis. The late mode analysis (sometimes called “long path” analysis) propagates the latest arrival times for each logic block, which in turn finds the largest cumulative path delays. This mode identifies paths that will prevent the hardware from being able to operate at desired clock cycle time. The early mode analysis (sometimes called “short path” analysis) propagates the earliest arrival times for each block, which in turn finds the smallest cumulative path delays. This mode identifies paths that will cause the hardware to incorrectly store data into the previous clock cycle. In the rest of this chapter, the late mode analysis will be assumed for the convenience of discussion, unless otherwise indicated. In general. a static timing tool requires the following information as its inputs: the points in the logic model where the timing is of interest (e.g., inputs, outputs, logic gates) the timing relationship between those points of interest (e.g., delays, setup, hold) arrival times asserted at the logic inputs required arrival times asserted at the logic outputs clock definition (if sequential logic is present)

184

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 8.2.

Block diagram of static timing analysis.

The block diagram of the general static timing analysis procedure is shown in Fig. 8.2. There are two different approaches in static timing analysis. The first one is the path-oriented approach, also called the path enumeration approach. The other one is the block-oriented approach. The path-oriented approach handles the timing problem for each unique path, while the block-oriented one does the same thing for each unique block (gate). In the following, these two approaches will be described. Because the block-oriented approach is faster and requires less memory, it is ideal for the VLSI systems, and will be the focus of the discussion.

TEMPERATURE-DRIVEN POWER AND TIMING ANALYSIS

Figure 8.3.

185

An example circuit diagram.

PATH-ORIENTED APPROACH The path-oriented approach has been employed in many static timing analysis tools [1, 2, 3]. Consider the circuit diagram in Fig. 8.3 borrowed from [4]. The block delays are shown at the bottom of the blocks marked from A to P. The rising and falling delays are asumed to be identical for simplicity. To perform the path-oriented timing analysis, the most straightforward way is to enumerate all paths in the circuit from the primary inputs (PI1 P14) to the primary outputs (PO1 P04). For this small circuit, there are a total of 32 paths. Next, the path delays are found by adding up the delays of individual blocks. For instance, the delay of the path PI1-A-B-C-H-PO2 is 12. The above approach that enumerates all paths is clearly expensive. It is impractical for circuits with larger size or more complex structure. An alternative is to extract the k-most critical paths. One example is to find only the most critical path [ 5 ] ,in which the depth-first search with pruning was used. The above algorithm is efficient, but extracting only one critical path often fails to provide enough information for correcting the timing violations. In 1989, Yen et al. developed an algorithm which traces the k-most critical paths [6] and the ˜

˜

186

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Propagating Latest Arrival Times Forward

Figure 8.4.

Arrival time propagation in block-oriented analysis.

sorted path delays were reported. A more efficient algorithm using the idea of branch slacks was later proposed to extract the k-most critical paths [7].

BLOCK-ORIENTED APPROACH The above path-oriented approach finds timing problems one path at a time. For some logic blocks, like block K in Fig 8.3, there are many different paths passing through. In other words, these blocks are analyzed several times by the path-oriented approach. A more efficient approach is to analyze all paths simultaneously. The blocks are analyzed in order and the worst timing caused by the paths passing through the block is recorded. It is therefore called the block-oriented approach. Consider a simple circuit in Fig 8.4, where three blocks (AND gate, OR gate, inverter) are shown. In Fig 8.4, ATR and ATF denote the rise and fall arrival times; DRR and DFF denote the the rise and fall block delays of the non-

TEMPERATURE-DRIVEN POWER AND TIMING ANALYSIS

187

inverting logic; DRF and DFR denote that rise-to-fall and fall-to-rise block delays of the inverting logic. In block-oriented timing analysis, the arrival times at the primary inputs are asserted as given. The arrival times of the rest of the circuit are then concurrently propagated forward to the primary outputs. During the propagation, the latest arrival times are recorded. For instance, the rise arrival times at the output of the AND gate is computed as max(54 2,50 4) = 56. Similarly, the fall arrival times is max(52 3,56 5) = 61. In order to see whether the arrival times at the primary outputs are late, the required arrival times must be specified (asserted) at the primary outputs. If the arrival time is greater than the required arrival time at some primary output, there is at least one timing problem. Next, the required arrival times of internal nets are calculated by propagating the asserted required times backward to the primary inputs. During the propagation, the worst case must be considered and thus the earliest required arrival times are chosen for the late-mode analysis. Figure 8.5 illustrates the backward propagation. where RATR and RATF denote the rise and fall required arrival times. Finally, to find out exactly which blocks are causing the timing problems, the concept of slack is used for convenience. The late-mode slack is defined as

+

+

+

slack = (Required arrival time

+

–

Arrival time).

(8.1)

If a net has negative slack, the signal is late. A slack calculation example for the sample circuit is given in Fig. 8.6, where SLKR and SLKF are the rise and fall slacks. Note that the slack value is constant (= -3) along the worst path through the logic. The block-oriented approach is fast. Moreover, the critical gates can be easily identified. It is well suited for integration with the logic synthesis program that requires values of the gate slack. However, this approach produces less information about the design timing than the path-oriented approach. The block-oriented analysis only records the worst slack for a given point of the logic. Therefore, unlike the path-oriented approach, it is difficult to handle the problem of finding the k-most critical paths.

DETECTION AND REMOVAL OF FALSE PATHS The static timing analysis approaches need no knowledge of the input pattern and the functionality of the blocks (i.e., only need to know whether the blocks are inverting or non-inverting). Although computationally very efficient, they often lead to serious overestimation of the critical path delay due to the false path problem. A false path is not a true path along which signals can actually propagate. One example of a false path problem is shown in Fig. 8.7 (from [8]. Path P =< b, d, e , x, y> is considered a false path because in order for

1 88

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Propagating Latest Required Times Backward Figure 8.5.

Required arrival time propagation in block-oriented analysis.

signals to propagate from gate d through gate e, c has to be 1 which blocks signals from x through gate y. Several approaches have been developed to resolve the false path problem, and the most primitive one is called the static sensitization. A statically sensitizable path is the one that can be activated in isolation from other paths, with all of its side-inputs held at constant noncontrolling values (e.g., 1 for AND gates and 0 for OR gates). In [9], efficient algorithms and a backtracking technique have been utilized to find the statically sensitizable paths. A new idea that totally eliminates the backtracking process, which is usually very costly, has been proposed by Ju et al. [7]. It transforms the sensitization problem into a satisfiability problem and applies the binary decision diagram (BDD) [ 10, 11] to construct the output functions of the paths. Although the use of BDD package is often limited to small circuits, the satisfying sets for all of the internal nodes of the slowest primary output function can be constructed in a very short

TEMPERATURE-DRIVEN POWER AND TIMING ANALYSIS

Figure 8.6.

189

Slack calculation in block-oriented analysis.

Figure 8.7.

A false path example.

time. Other approaches for solving the false path problem, such as those based on the dynamic sensitization [12], the viability condition [13], and the Du's criterion [8], have also been proposed.

STATIC TIMING ANALYSIS FOR SEQUENTIAL CIRCUITS The preceding examples and discussion focus on the static timing analysis of combinational logic. The theory directly applies to the analysis of synchronous sequential logic by breaking it into several combinational logics. The storage elements (latch, flip-flop) are usually chosen to be the break points. Because now the starting and/or ending points of the combinational paths are the storage elements, the timing assertions and constraints will come from the clocks that control the storage elements.

190

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

For systems with multiple clocks, the problem becomes much more complex. The timing analysis program needs to have a smart way of knowing which clocks launch and capture which data, and when to launch and capture them. The data may contain a clock phase tag besides their delay values for that purpose. One other factor that makes the sequential timing analysis difficult is the loop. A loop exists in a sequential circuit when the signal goes through a series of transparent latches and feeds back to itself. A static timer must have the capability of automatically breaking such a loop, otherwise the propagation of arrival times and required arrival times will create infinite loops. A loop must be broken without hiding the potential timing problem, and the slack stealing effect also needs to be taken into account [14, 15, 16].

8.2.3

DELAY MODELING

The circuit delay must be accurately modeled in both dynamic and static timing analysis. For dynamic analysis, the delay accuracy is determined primarily by the simulation engine used. Chapter 2 and Chapter 5 have briefly introduced different kinds of simulation engines. For static analysis, the base simulation unit is a block (gate). Therefore, the delay model of the gate must be carefully characterized before timing analysis is performed. The gate delay modeling with a single switching input has been addressed by many research works [17, 18, 19]. The case of multiple-input switching has also received much attention [20, 21, 221]. One general and powerful approach to model the gate delay is to numerically fit the SPICEgenerated delay data by an empirical formula. This empirical formula is a function of the input slew, output loading, and a set of fitting parameters. For instance,

Delay = K0

+ K1 x Cload + K2 x Tinput-slew + . . . .

(8.2)

This model is accurate, yet the lengthy and repetitive SPICE simulation is avoided in static timing analysis. The gate delay is not only a function of the input slew and output loading, it is also affected by the temperature and voltage fluctuation, as well as the silicon process variation. The silicon process variation is difficult to capture and is often statistically modeled. The voltage fluctuation can be estimated by the IRdrop analysis tools. Traditionally the temperature effect is taken into account by assuming that a worst possible temperature value is uniformly distributed across the chip. It is a pessimistic assumption. It not only overestimates the gate delay and thus constrains the design space, but may also lead to timing problems by ignoring the on-chip temperature gradient. This issue will be addressed further later in this chapter.

TEMPERATURE-DRIVEN POWER AND TIMING ANALYSIS

8.3.

191

STATISTICAL POWER DENSITY ESTIMATION

As described in Chapter 2, the power estimation method can be either input pattern dependent or independent. The pattern-dependent method is used when the input sequence is known for certain applications, and it produces a deterministic power value. However, input patterns are often unknown during the design phase. It is also impractical to estimate the average power by exercising all possible input patterns. As a result, in order to estimate the nominal on-chip steady-state temperature profile, it is more meaningful to calculate the average power in a statistical manner. This nominal temperature profile will later be used for the temperature-driven timing analysis. A brief overview of the underlying theory of the statistical (Monte-Carlo) power analysis methods has been presented in Chapter 2. Interested readers may refer to it for more detail. In this chapter, a unique technique for the Monte-Carlo average power estimation, called the Mean Estimator of Density (MED) [ 2 3 ] , is employed. The MED technique is a good mix of accuracy, speed, and ease of implementation. More importantly, it captures the transition statistics of each logic gate instead of the whole circuit. Therefore, it directly suits the purpose of temperature profile calculation. Suppose a circuit is simulated n times, and for each time the number of logic transitions of a gate is xi. According to the central limit theorem [24], the average ¯ x = xi/n has a distribution which is close to normal for large n. If µ is the true expected number of transitions of this gate, with (1 x 100% confidence it follows that –

(8.3) where is the standard deviation, and z1-a/2 is defined so that the area to its right under the standard normal distribution curve is equal to a/2. Here we define as the sample mean of the power density of a given gate in the circuit. Power density is defined as the power value per unit area, which is a direct measure of the local temperature rise. For sufficiently large number of n (i.e., n 30), can be approximated by the sample standard deviation s. By using Eq. (8.3), one can show that the number of samples required is

(8.4) such that we have (1 satisfied:

–

x 100% confidence that the following condition is

(8.5) where is the user-specified error tolerance. Equation (8.4) provides a stopping criterion to yield the power estimation accuracy specified in Eq. (8.5) with confidence (1 x 100%. –

192

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

It is clear from Eq. (8.4) that for a small value of the number of samples required can be very large to meet the specified accuracy level. In MED-like approaches, the stopping criterion Eq. (8.4) is used for gates that have larger than the user-specified threshold value. µmin. These gates are referred to as the regular-density gates. A different stopping criterion is used for gates that have less than µmin:

–

(8.6) These gates are referred to as the low-density gates. Equation (8.6) controls the number of samples by providing an absolute error bound for the low-density gates. Although the estimated power values of those gates are less accurate, they have the least effect on temperature rise.

8.4.

MONTE-CARLO POWER-TEMPERATURE ITERATION SCHEME

To determine the nominal steady-state temperature profile of the chip substrate, the power values of the gates obtained from the above statistical simulation need to be input to a 3-D thermal simulator. Since power and temperature are functions of each other as described at the beginning of this chapter, an iteration scheme is invoked between the power density and temperature calculations [25]. The iteration scheme is graphically shown in Fig. 8.8. There are two levels of iteration. The first level is related to the Monte-Carlo power estimation, and the second level is related to the mutual dependence between power and temperature. In Fig. 8.8, the convergence rates of the first and second levels of iteration are determined by the quantities circled by the dashed lines. The quantities in <.> are non-constants, which are calculated and updated at run time. The stopping (convergence) criterion of the first level of iteration is described by Eq. (8.4) and Eq. (8.6). The stopping criterion of the second level of iteration is based on two factors: the temperature difference between two consecutive iterations and the power estimation error inherited from the MonteCarlo simulation. Suppose the confidence level (1 x 100% and the percentage error are used in the Monte-Carlo power estimation for the regular-density gates. After the power estimation is complete in (second-level) iteration k , the power of each regular-density gate is compared with the one calculated in iteration k 1. The number of regular-density gates that have percentage power difference less than between iterations k 1 and k is counted and denoted nrs If the ratio of nrs to the total number of regular-density gates in the circuit is larger than (1 the iteration process is stopped. Otherwise the thermal simulation is performed based on the power distribution in iteration k , and the –

–

–

–

–

TEMPERATURE-DRIVEN POWER AND TIMING ANALYSIS

Figure 8.8.

193

Monte-Carlo power and temperature iteration scheme.

updated temperature profile is found. The resulting temperature of each gate is then compared with the one in iteration k 1 in order to determine whether or not the iteration process can be stopped according to the user-specified accuracy level of temperature. The above 1 term accounts for the possible overestimation and under-estimation of the power values inherited from using the places an upper bound for the Monte-Carlo approach. The value (1 temperature effect to be considered important during iterations. The above two-level iteration scheme was adopted in [25].In this work, the external spatial correlation of the input signal vector is not considered in MonteCarlo power estimation. The circuit is given a sequence of two input vectors for one logic simulation run. All possible input patterns (high, low, high-to-low, low-to-high) are assumed to have an equal probability of occurrence. Moreover, the logic simulator used in [25]takes as inputs the load capacitances, the input signal slope, and the temperature-dependent MOS device and interconnect parameters of each gate, as will be described in the following section. The state equations of the gates are formulated as the Riccati differential equations and solved analytically [26]. The above process is fast enough to make the temperature-sensitive statistical power estimation both accurate and feasible. –

–

–

194

8.5.

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

TEMPERATURE-DEPENDENT GATE AND RC DELAYS

From the experimental results presented in Chapter 5 , it can be seen that the on-chip temperature gradient and temperature rise substantially affect the circuit delay. The critical path timing, affected by the delays of logic gates and interconnects, is therefore strongly temperature-dependent. Temperaturesensitive timing analysis is important to the high-performance VLSI design, and the assumption of uniform temperature across the chip may not be appropriate. In [25],the temperature-dependent gate delay is calculated by using the regionwise quadratic (RWQ) model with the mobility model introduced in Chapter 3. As for the interconnects at given temperatures, the following equation is used in order to find the resistance value for temperature-dependent RC delay estimation: (8.7)

In Eq. (8.7), R ( T )is the resistance at temperature T , R0 is the resistance at is the temperature coefficient of resistivity (e.g., room temperature T0, and 0.004 º C - ¹ for Aluminum). As a general rule of thumb, the RC delay increases about 5% for 10 "C of interconnect temperature rise. To find the signal-line interconnect temperature, the coordinates of each y) metal are first extracted. Next, the localized substrate temperature at (x, is used as the temperature of the interconnects located near (x, y). It implies that the temperature difference between the substrate and the multi-layered signal-line metals is ignored. Note that, however, the Joule heating effect may also need to be taken into account separately for calculating the temperature of the multi-layered interconnects. Details of the interconnect temperature calculation considering Joule heating was described in Chapter 6. To facilitate the RC delay calculation, the layout extractor developed in [25] extracts the signal-line interconnect resistance in the form of a distributed RC tree, as shown in Fig 8.9. Each signal-line interconnect tree is transformed into an equivalent and is lumped to the corresponding driving gate. This is shown in Fig. 8.10, where Tg is the gate temperature, and Ri(Ti) is the temperature-dependent resistance calculated by using Eq. (8.7).

8.6.

SIMULATION EXAMPLES

Finding the path timing requires either dynamic or static timing analysis. In this section, the dynamic analysis will be used first to investigate how temperature can affect the timing and change the criticality of a path. To dynamically find the critical (longest) path, it is assumed that the pool of all possible input patterns is provided. Therefore, the input pattern that triggers the critical path, i.e., critical pattern, must also be in this pool.

TEMPERATURE-DRIVEN POWER AND TIMING ANALYSIS

Figure 8.9.

Figure 8.10.

Example of a distributed RC tree.

Example of an equivalent

model.

195

196

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS Table 8.1.

Figure 8.I I .

The ISCAS85 benchmark circuits.

Thermal boundary conditions for temperature-dependent timing simulation.

In [25], it is assumed that the input-pattern pool is composed of the input patterns that are generated earlier for Monte-Carlo power estimation. During the Monte-Carlo power estimation phase, the longest path delay and its associated input pattern are concurrently found. If the number of samples needed in Monte-Carlo simulation is n, the longest delay and its triggering pattern will be found out of the n input patterns. This pattern thus obtained is the critical pattern, which will be used to identify and report the gates along the critical path. In the remainder of this section, six ISCAS85 benchmark circuits will be used as examples to demonstrate the simulation results. Table 8.1 shows these circuits and their functions. Figure 8.1 1 shows the thermal boundary conditions used for all circuits under simulation [25]:The four sides are set to be in the isothermal condition, i.e., constant temperatures, the top is perfectly insulated, and the bottom is convective to room temperature with the heat transfer coefficient 5,000 (W/m² "C). Simulation results of the temperaturedependent Monte-Carlo power estimation and critical path delay calculation are demonstrated in Table 8.2. In Monte-Carlo power simulation, 95% confidence = 0.05) and 5% error tolerance = 0.05) were used. The µmin value was dynamically determined in the following way. Circuits were first simulated using an initial large µmin. This provided a rough estimation of the power density distribution of the gates.

TEMPERATURE-DRIVEN POWER AND TIMING ANALYSIS Table 8.2.

197

Simulation results with dynamic timing analysis.

Table 8.2 (continued),

Simulation results with dynamic timing analysis.

The new µmin value was then chosen such that 10% of the gates were classified as low-density gates (i.e., with power density less than µmin. The simulation was then rerun based on the new µmin value. The estimated circuit powers are shown in the second column in Table 8.2. Here. Tdccb-max and Tdccb-min are the simulated maximum and minimum temperatures of the gates on the longest path, respectively. The longest path delays without considering the temperature effect are shown in the fifth column. The estimated temperaturedependent longest path delays (i.e., Delay(T)) are listed in the sixth column for comparison. For a given critical input pattern, the critical path may be different for a circuit subject to a uniform room temperature and subject to a non-uniform temperature distribution. The circuits under simulation with changing critical path due to the thermal effect are marked with in the seventh column. The CPU times (on SUN SPARCstation 10) used for the Monte-Carlo power and thermal simulations are given in the last two columns of Table 8.2. Finally, the temperature profile of C6288 is demonstrated in Fig. 8.12. The gates on the longest path of C6288 are shown as small diamonds. The static timing analysis is also performed on the same circuits and the results are given in Table. 8.3. In the static timing analysis, each gate has four

198

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Figure 8.12. The simulated temperature profile and the gate distribution of the longest path in C6288: The solid lines are the isothermal temperature contour and the small diamonds are the on-chip locations of gates in the longest path.

Table 8.3.

Simulation results with static timing analysis.

delay values: t-rise(27 ºC),t-fall(27 ºC), t-rise(Tg), t-fall(Tg), where T g is the gate temperature obtained directly from previous thermal simulation. It is assumed that each gate is subject to constant input slope and output loading. The four delay values of each gate are precharacterized and tabulated before timing analysis starts. When a gate is precharacterized, its loading interconnects are lumped to the output node of this gate and their temperatures-dependent resistances are used (See also Fig. 8.10).

TEMPERATURE-DRIVEN POWER AND TIMING ANALYSIS

199

The delay values in Table 8.3 are different from those in Table 8.2. The difference comes from two sources. Firstly, the delay models used in the dynamic and static timing analysis are different. Secondly, the input patterns used in the dynamic timing analysis are not complete, therefore the critical path found may not be the true critical path. The static timing analysis used for this example eliminates the false paths by using the backtracking technique [9]. Note that the temperature-induced critical path change also occurs in static timing analysis. In Table 8.3, one more circuit (C1355) changes its critical path because of the on-chip temperature gradient. The simulation results again confirm that the path delay must be accurately determined based on its local temperature, and the traditional assumption of the uniform temperature distribution may lead to false prediction of the timing problems.

8.7.

SUMMARY

This chapter discusses the importance of the thermal effect on circuit timing. Because temperature distribution is determined by power distribution, a statistical power analysis approach is used for finding the nominal on-chip temperature profile. Both temperature-dependent power and timing analyses are addressed in this chapter. The relationships between power, temperature, and timing are illustrated. The dynamic timing analysis method (also called delay simulation) is described. –

It simulates a design with given input vector patterns.

–

It is accurate yet expensive, which is ideal for analyzing small designs.

The static timing analysis method is described. –

–

–

–

–

It finds the critical path timing without requiring the input patterns. Two different approaches are in the static timing analysis method: pathoriented approach and block-oriented approach. The path-oriented approach enumerates the k-most critical paths one at a time. The block-oriented approach propagates the timings through each block and only the worst timing is recorded. In this approach, the details of how to propagating the arrival times, the required arrival times, and the slacks are described. The false path problem in static timing analysis is defined and examined. Methods used to remove the false paths are presented.

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ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

The delay models generally used in timing analysis are introduced. A statistical power analysis method, based on MED, is presented. It estimates the power density in a design so that the local temperature rise can be accurately determined. A statistical power-temperature iteration scheme for finding the average power and the nominal steady-state power is developed and described.

The temperature-dependent gate and RC delay models used in timing analysis are described. Simulation example are provided. The results show that the on-chip temperature rise and temperature gradient not only can change the circuit timing, but also can change the criticality of a path.

References [1] D. J. Pilling, and H. B. Sun, “Computer-aided prediction of delays in LSI logic systems,” in Proceedings of the ACM/IEEE Design Automation Workshop, pp. 182-186, 1973.

[2] M. A. Wold, “Design verification and performance analysis,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 264-270, 1978. [3] R. Kamikawai, M. Yamada, T. Chiba, K. Furumaya, and Y. Tsuchiya, “A critical path delay check system,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 118-123, 1981. [4] R. B. Hitchcock, G. L. Smith, and D. D. Cheng, “Timing analysis of computer hardware,” IBM Journal of Research and Development, vol. 26, pp. 100-105, Jan. 1982. [5] J. Ousterhout, “A switch-level timing verifier for digital MOS VLSI,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 4, pp. 336-349, July 1985. [6] H. C. Yen, D. H. Du, and S. Ghanta, “Efficient algorithms for extracting the k-most critical paths in timing analysis,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 649-654, June 1989.

[7] Y. C. Ju and R. A. Saleh, “Incremental techniques for the identification of statically sensitizable critical paths,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 54 1-546, June 1991.

References

20 I

[8] D. H. Du, S. H. Yen, and S. Ghanta, “On the general false path problem in timing analysis,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 555-560, June 1989. [9] J. Benkoski, E. V. Meersch, L. J. Claesen, and H. DeMan, “Timing verification using statically sensitizable paths,” IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, vol. 9, pp. 1073-1084, Oct. 1990. [IO] R. E. Bryant, “Graph-based algorithms for Boolean function manipulation,” IEEE Transactions on Computers, vol. 35, pp. 677-691, Aug. 1986. [113 K. S. Brace, R. L. Rudell, and R. E. Bryant, “Efficient implementation of a BDD package,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 40-45, June 1990.

[12] P. C. McGeer and R. K. Brayton, Integrating Functional arid Temporal Domains in Logic Design. Kluwer Academic, New York, 1991. [13] P. C. McGeer and R. K. Brayton, “Efficient algorithms for computing the longest viable path in a combinational network,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 56 1-567, June 1989. [ 14] T. G. Szymanski, “Computing optimal clock schedules,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 399-404, 1990.

[15] T. M. Burks, K. A. Sakallah, and T. N. Mudge, “Identification of critical paths in circuits with level-sensitive latches,” in Proceedings of the ACM/IEEE International Conference on Computer-Aided Design, pp. 137141, 1992. [16] T. M. Burks and K. A. Sakallah, “Optimization of critical paths in circuits with level-sensitive latches,” in Proceedings of the ACM/IEEE International Conference on Computer-Aided Design, pp. 468-473, 1994. [17] H. Y. Chen and S. Dutta, “A timing model for static CMOS gates,” in Proceedings of the ACM/IEEE International Conference on ComputerAided Design, 1989. [ 18] T. Sakurai and A. R. Newton, “Delay analysis of series connected MOS-

FETs,” IEEE Journal of Solid-state Circuits, vol. 26, pp. 122-131, Feb. 1991.

[ 19] J. T. Kong and D. Overhauser, “Methods to improve digital MOS macro-

model accuracy,” IEEE Transactions on Computer-Aided Design of Integrated Circuits arid Systems, vol. 14, pp. 868-88l , July 1995.

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[20] A. Nabavi-Lishi and N. C. Rumin, “Inverter models of CMOS gates for supply current and delay evaluation,” IEEE Transactions on ComputerAided Design of Integrated Circuits arid Systems, pp. 1271-1279, 1994. [21] S. Z. Sun, D. H. Du, and H. C. Chen, “Efficient timing analysis for CMOS circuits considering data dependent delays,” in Proceedings of the IEEE International Conference on Computer Design, 1994.

[22] V. Chandramouli and K. A. Sakallah, “Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 617-622, 1996. [23] M. G. Xakellis and F. N. Najm, “Statistical estimation of the switching activity in digital circuits,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 728-733, June 1994.

[24] P. L. Meyer, Introductory Probability and Statistical Applications. Addison-Wesley, 1970. [25] Y. K. Cheng and S. M. Kang, “Temperature-driven power and timing analysis for CMOS VLSI circuits,” in Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 6, pp. 214-217, May 1999. [26] Y. H. Shih and S. M. Kang, “Analytic transient solution of general MOS circuit primitives,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. l l , pp. 7 19-73l , June 1992.

About the Authors

Dr. Yi-Kan Cheng received the B.S. degree from the National Chiao-Tung University, Taiwan in 1991, the M.S. degree from the University of Southem California in 1993, and the Ph.D degree from the University of Illinois at Urbana-Champaign in 1997, all in electrical engineering. In the summer of 1996, he was with the Technology Computer-Aided Design (TCAD) Department of Intel Corporation, Santa Clara, CA, working in the area of electrothermal reliability simulation and modeling. Currently he is with the Motorola Somerset Design Center, Austin, TX, as a Development Staff Member for the PowerPC microprocessor design. His present research interests include IC design, IC reliability analysis, timing optimization and analysis, and power analysis. Dr. Ching-Han Tsai received the B.S. degree i n electrical engineering from National Taiwan University in 1992, and M.S. and Ph.D. degree in electrical and Computer engineering from the University of Illinois at Urbana-Champaign in 1997 and 2000, respectively. He was with Intel Corp. in the summer of 1997, and Cadence Design Systems Inc. in the summer of 1998. His research interests include electrothermal circuit simulation, substrate modeling for noise/latchup/thermal analysis, and reliability-driven physical design. Dr. Chin-Chi Teng received the B.S. Eng. degree in electrical engineering from the National Taiwan University, Taiwan, and the M.S. and Ph.D. degrees in electrical and computer engineering in 1993 and 1996, respectively, from the University of Illinois at Urbana-Champaign. Since 1996, he was with the Analysis Product Division, Avant! Corporation, Fremont, CA. Currently he is a senior member of technical staff at Silicon Perspective Corporation, Santa Clara, CA. His research interests are in the areas of computer-aided design on VLSI circuits and systems, with emphasis on circuit simulation, power estimation, interconnect reliability assessment, and post-layout performance optimization for deep-submicron circuits.

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ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Dr. Sung-Mo (Steve) Kang received the Ph.D. degree i n electrical engineering from the University of California at Berkeley in 1975. Until 1985 he was with AT&T Bell Laboratories at Murray Hill and Holmdel, and also served as a faculty member of Rutgers University. In 1985, he joined the University of Illinois at Urbana-Champaign where he is Professor and Department Head of Electrical and Computer Engineering, and Research Professor of Coordinated Science Laboratory and Beckman Institute for Advanced Science and Technology. He was the Founding Editor-in-Chief of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Dr. Kang is Fellow of IEEE and AAAS, a Foreign Member of National Academy of Engineering of Korea. He is recipient of the IEEE Millennium Medal (2000), SRC Technical Excellence Award (1999), KBS Award in Science and Technology (1 998), IEEE CAS Society Technical Achievement Award (1997), Humboldt Research Award for Senior US Scientists (1 996), IEEE Graduate Teaching Technical Field Award (1 996), IEEE Circuits and Systems Society Meritorious Service Award (1 994), SRC Inventor Recognition Awards (1993, 1996), IEEE CAS Darlington Prize Paper Award (1993), ICCD Best Paper Award (1986) and Myril B. Reed Best Paper Award (1979). He was an IEEE CAS Distinguished Lecturer (1994-1997) and holds six patents, published over 250 papers and co-authored six books, Design Automation For Timing-Driven Layout Synthesis ( I 992), Hot-Carrier Reliability of MOS VLSI Circuits (1993, Physical Design for Multichip Modules (1994), and Modeling of Electrical Overstress in Integrated Circuits (1 994) from Kluwer Academic Publishers, CMOS Digital Circuits: Analysis and Design (1995, 2nd ed. 1998) from McGraw-Hill, and Computer-Aided Design of Optoelectronic Integrated Circuits and Systems (1996) from Prentice Hall.

Index

Adaptive mesh generation, 73, 82 Admittance matrix, 164-165 reduction. 163 system, 79 Alpha percentile, 35 Ambient temperature, 4, 1 I , 62 Analytical thermal simulation, 16, 62, 82 Architectural instructions, 29 Arrhenius equation, 123 Arrival time, 183, 186-187 Asymptotic waveform evaluation (AWE), 8-9 Auxiliary homogeneous problem, 79 Avalanche breakdown, 8, 11 Average current model, 124-125 Average current recovery model, 126, 129 AWE, 8-9 Backtracking technique, for false path, 188, 199 Bamboo structure of metal, 128 Band gap of silicon, 46 Basewidth modulation, 8 Berkeley reliability tool (BERT), 131 Berkeley Short-Channel IGFET Model (BSIM) (see MOS device model) Bidirectional current stress, 126 Binary decision diagram (BDD), 32, 38, 188 Black's equation, 122, 124 Body effect, 46 coefficient, 50 Boltzmann constant, 47 Boltzmann equation, 45 Boltzmann's transformation, 82 Boundary condition, 14-15, 61, 65, 71, 80, 103, 157-159, 196 convective (Robin), 62, 77 forced, 84 natural, 84 homogeneous, 79 insulated (Neumann), 62,79 isothermal (Dirichlet), 62, 79

Boundary value problem, 62, 65, 79 Boundary-element method (BEM), 72 BSIM (see MOS device model) Cell placement, 157 Central limit theorem, 34-36, 191 Channel-length modulation parameter, 46 Chapman-Kolmogorov equation, 38 Cholesky factorization, 164 Circuit primitive, 95-96, 98 internal node, 98 Circuit-level simulation, 95 Closed state i n FSM. 39 Compact substrate thermal model, 16, 159, 161, 164, 168 Condensed vertex, 98 Conditional probability, 32 Confidence level, 34-36, 191-192 Constraint-based thermal optimization, 167 Critical path, 181-182, 194, 197, 199 k-most, 185 , 187 Critical pattern, 194, 196 Cumulative distribution function (cdf), 35

Cumulative path delay, 183 Current density, 122-123, 136

average, 124, 126 effective, 126 Current gain, 8

Dc-connected block (DCCB), 98, 101 Defect relaxation model, 125 Delay model, 17. 30, 182 in dynamic timing analysis, 190 in static timing analysis, 190 temperature-dependent, 194 Delay simulation, 182 Deterministic power analysis (see Power analysis) Dielectric breakdown, 131 Difference equation, 72-73 Diffusion rate, of metal ions, 121 Diffusivity, I2 1

206

ELECTROTHERMAL ANALYSIS OF VLSl SYSTEMS

Distributed RC tree, 194 Drain/source depletion charge sharing coefficient, 50 Du's criterion, I89 Dual-VT technology, 28 Dual-in-line package (DIP), 105 Dynamic power, 21-23, 31 Effective heat transfer, 63 coefficient, 64. 77, 81, 83, 105, 112 macromodeling, 64, 86 Eigenfunction, 79, 81 Eigenvalue, 79 Electrical overstress (EOS), 3, 9 Electrical simulation, 5, 95 Electrical time constant, 13 Electromigration (EM), 3 analysis, 16, 129 BERT, 131 hierarchical, 132 iTEM (see ITEM) pattern-independent, 132 probabilistic, I3 1 RELIANT. 130 RELIC, 131 RELY, I3 I SPIDER, 130 temperature-dependent, 16, 121, 133 cause of, 122 lifetime, 16, 122, 149 current density, 16, 123 current waveform, 16, 124 metal length, 16, 128 metal width, 16, 127 mean time to failure (MTF), 16, 122, 124-126, 128-129, 143, 145 temperature-dependent, 16, 62, 122, 133 Electron wind, 122 Electrostatic discharge (ESD), 3, 9, 12 Electrothermal analysis, 3 application, 16 Electrothermal simulator, 8 chip-level, 13 fast timing, 12 transistor-level, 8 Electrothermal reliability, 3, 15 simulation, 5, 36, 61, 76, 95, 114 analog circuit, 6 coupled, 6, 8-9, 12 decoupled, 13, 101 digital VLSI circuit, 12 direct technique, 8-9 fast-timing, 16, 101, 133 ILLIADS-T (see ILLIADS-T) incremental technique, 12, 16, 102-103, 112 relaxation technique, 8 transient, 13

Equidistribution criterion, 73 Equilibrium probability, 32 Equivalent 194 Equivalent thermal resistance method, 141 Error function, 66 piecewise linear, 67 Error tolerance, 36 Event-driven simulation, 95 Failure rate, 4, 131 False path, 17, 183, 187, 199 Fast thermal analysis (FTA), 16, 62, 65, 82, I14 constraints, 67 Fast timing simulation, 12, 29, 51, 95-96 Finite-difference method (FDM), 7-8, 72-73, 75, 82, 140, 159, 161, 163, 165 boundary grid, 77 interior grid. 77 Finite-element method (FEM), 72, 140 Finite-state machine (FSM), 37-38 First law of thermodynamics, 75, 77 Fixed charge density, 47 Flat-band voltage, 50 Flip-chip package, 84 Flux divergence, of metal ions, 121, 123, 128 Forward-bias current in diode, 104 Forward/backward substitution. 164 Fourier transform, 79 Full timing simulation. 51, 95 Functional unit block (FUB), 84 Gate delay. 17, 190, 194, 200

Generation-recombination mechanism, I04 Grain-boundary diffusion, of metal ions, 122, 127 Green's function, 11, 66, 70, 164 Green's theorem, 80 Half-perimeter bounding box model, 171 Hard-placed cell, 158 Healing effect, 126 Heat conduction, 61-62. 72, 75, 79, 121, 134 Heat diffusion equation, 15, 61, 136 homogeneous, 79 steady-state, 160 Heat fringing effect, 135 Heat pipe, 85 Heat sink, 64, 70 Heat transfer coefficient, 61, 64 ,71, 84, 88, 112 Hillock, 123 Hold time. 182 Hot carrier induced degradation, 3 Hot carriers, 131 Hot spot, 4. 14,62, 65, 70, 82, 157, 159, 168 Hypergeometric function, 98 Hypothesis test, 39 ICCG, 8 ICGEN, a layout synthesis tool, 112 IETSIM, 9, 11

Index ILLIADS. 12, 16,51,96,98, 101 ILLIADS-T, 12, 14-16,56,96, 101, 112, 115, 133 tester chip, 103, 105 Implicit state enumeration, 38 Incomplete Cholesky conjugate gradient (ICCG) method, 8 Incremental simulation, 12, 16, 102-103, I12 Independence interval, 39 Initial temperature condition, 61 Initial transient problem, 39 Input pattern generator, 33 Integral transform, 79 triple-integral, 79 Integration formula, 8 trapezoidal, 8-9 Integrator circuit, 11 Interconnect defect, 128 Interconnect delay, 17, 62, 194, 200 Interconnect temperature (see Temperature) Internal power, 2 I , 23-24 Intrinsic carrier concentration, 46 Ion diffusion coefficient, 123 Ion flux equation, 123 IR voltage drop, 190 ITEM, 16, 133 contact grouping, 141 interconnect partitioning, 140, 142 interconnect temperature, 133 lumped thermal model for interconnects, 137, 139-140 simulation flow, 133 ITEMP. I4-15 Joule heating, 121, 124, 134-135, 137, 194 Kirchhoff’s current law (KCL), 75 Kirchhoff’s transformation, 82 Latent block, 102 Lattice diffusion, of metal ions, 122 Law of Large Numbers, 33 Leakage current, 25 Leakage current density, 26 Leakage power, 22,25, 181 diode. 16-28 Sub threshold, 27-28 Levenberg-Marquart algorithm, 54 Logic fault, I14 Logic simulation, 29, 38, 95 Logic style. 31 Loop, in static timing analysis, 190 LU factorization, 8, 164 Lumped thermal model, 16 Macrocell placement (see Placement) Macromodel, 8, 64,86, 95-96 Mass transport, in metal, 122 McPower, 36 Mean Estimator of Density (MED), 36, 191

207

error tolerance, 191 low-density gate, 192, 197 regular-density gate, 192 stopping criterion, 191-192 Mean time to failure (MTF), 16, 122, 124-126, 128-129, 143, 145 Mean value of a random variable, 33.35 Method of images, 65 Method of separation of variables, 79 Mobility, 46-47,49,52, 181 temperature-dependent. 15, 45, 52, 106 in RWQ model, 54, 194 SPlCE Level-1 model, 48 Modified nodal analysis (MNA), 1 1 Moment matching, 9 Monte-Carlo simulation, 36, 45 MOS device model BSIM, 15,48,53 BSIM drain current, 49 electrical parameter, 48-49 parameter file, 48 process parameter, 48 sensitive parameter, 49 sensitivity analysis, 49 sensitivity function, 49 temperature coefficient, 5 1 effective channel length, 48 effective channel width, 48 RWQ, 12, 14-15,51,53-54.56,96, 101, 194 drain current, 52,97 Shichman-Hodges model, 46, 97, 99 temperature-dependent, 15, 45.48, 51, 56, 96. I94 MOS device transconductance, 46, 52, 98 MOS transistor gain factor, 25 Multi-chip module (MCM), 6 1, I57 Multiple power dissipation pattern, 168-169 Node equation. 45, 76, 96 Nonhomogeneous heat conduction problem, 79 Nonlinear least-square fitting, 54 Nonlinear system equation, 38 Nonparametric analysis, 36, 39 Normal distribution. 35-36, 191 Numerical thermal simulation, 16, 62, 72, 82, 136 Order-statistics, 39 Oxide breakdown. 3 Package design, 88 Package modeling, 64, 83, 88 Package thermal simulation, 16, 83 Packaging effect, 63, 70, 83. 88 Padé approximation, 9 Parametric analysis, 36 Path enurneration approach, 184 Penalty-based thermal optimization, 167, 169 Pi model, 194

208

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Picard-Peano iteration method, 38 Placement, 16. 157 force-directed algorithm, 157 matrix synthesis algorithm, 158-159 temperature-driven, 16, 157, 165. 181 constraint-based, 167 macrocell placement, 159, 168-169 penalty-based, 167, 169 standard cell placement, 159, 165, 169 Poisson equation, 45 Pole, 9 Post dispatch serialization, 29 Power analysis, 15, 21 deterministic, 28-29, 37, 191 engine, 28 in ILLIADS, 101 level, 28 nonparametric, 36, 39 parametric, 36 probabilistic, 28-32, 38 sequential circuit, 37-39 statistical (Monte-Carlo). 17. 28-29, 33, 36. 38-39, 181, 191-192. 196 strongly input-pattern dependent, 29 temperature-driven, 17, 36, 181 , 196 weakly input-pattern dependent, 30 Power budget, 166-167 Power consumption, 3 average, 13-15,31, 34.36, 38, 101, 111, 181 dynamic power. 21-23, 3 1 instantaneous, 13 internal power, 2 1,23-24 leakage power, 22,25-28, 18 1 lower bound, 23 maximum, 4, 29 monitor, I 1 short-circuit power, 15, 22, 24-25, 181 switching power (see Dynamic power) toggle power, 29 Powerdensity, 4, 36, 81, 103, 170, 191 Power estimation (See also Power analysis) biased, 39 Power meter, 29, 101 Power series method, 98 Power-temperature iteration scheme, 17 Probabilistic power analysis (see Power analysis) Probability waveform, 32 Quantum effect, 53 Random number generator, 33 Randomness hypothesis, 39 RC delay. 62. 194, 200 Reconvergent fan-out, 32 Regionwise quadratic (RWQ) model (see MOS device model) Reliability, 3, 72, 121, 157 RELIANT, 130 RELIC, 131

RELY, 131 Required arrival time, 183, 187 Residue, 9 Resistivity. of metal line, 135-137, 194 Riccati differential equation (RDE), 98, I93

Sample mean, 33. 35, 191 Sample size, 34 Scattering mechanism, 15,45, 47, 53 surface-roughness, 47 Coulomb, 47 lattice, 47-48 Schwarz-Christoffel conformal transformation, 135 Secondary input, 37 Self heating, 70, 105, 121, 124, 134 Semi-analytical thermal simulation, 83 Sensitivity analysis, 15, 49 Sensitization dynamic, 189 static, 188 Series model, 128 Setup time, 182 Shichman-Hodges model, 46, 97, 99 Short-channel effects, 96 Short-circuit current, 25 Short-circuit power, 15, 22, 24-25, I 8 1 Signal correlation, 30, 39, 132, 193 Signal inter-dependence, 32 Signal probability, 30, 32, 38 Significance level of hypothesis test, 39 Silicon-on-insulator (SOD, 9 Simulated annealing, 159, 166-168 cooling schedule, 166, 169 Slack stealing. 190 Slack, of timing, 187 Sparse-matrix technique, 76, 165 Spatial independence. 30-32, 36 Spatio-temporal correlation, 37 Specific heat, 11, 61 SPICE, 8-9 level-4 model, 48 SPIDER, 130 Standard deviation, 191 Standard-cell placement (see Placement) State equation, 9, 38, 98, 193 State line probability, 38 State probability, 38 State transition graph (STG), 38 Statistical (Monte-Carlo) power analysis (see Power analysis) Statistical power-temperature iteration, 192 convergence rate, 192 stopping criterion, 192 Steady-state temperature, 13-14, 61, 69, 81. 101, 159, 181, 192 Stopping criterion in statistical power analysis, 33-34, 36, 38-39

Index in statistical power-temperature iteration. I92 Stress gradient. 123 Strongly connected component (SCC), 98 Sturm-Liouville problem, 79 Successive-over-relaxation (SOR) technique, 76 Superposition, 12, 16, 69, 159, 161 Surface inversion potential, 50-5 1 Surface state charge density, 47 Switch-level timing simulation, 5 1, 95 Switching activity, 37 Switching power (see Dynamic power) Table lookup, 95 Tarjan’s algorithm, 98 Temperature coefficient of resistivity, 135 Temperature objective, 166 Temperature ambient, 4, 11, 62, 121 average, 15, 87, 166 constraint, 159, 167 gradient, 12, 73, 103, 121, 123, 134, 181, 190, 199 interconnect, 16, 62, 121, 133, 135, 194 analytical model, 136 lumped model, 137, 139-140 maximum, minimum, 112, 168, 171, 197 nominal, 17, 191-192 on-chip, 4, 13, 62, 76, 88, 104 optimal, 162, 169 slack, 166-167 steady-state, 13-14,61, 69, 81, 101, 159, 181, 192 substrate, 62, 133, 159, 161-162, 166-168, 194 transient, 8-9, 11 uniform distribution, 121, 158, 162, 190, 199 Temporal correlation, 30, 39 Temporal independence, 30-32, 36 Tester chip, 103, 105 Thermal analysis, 15 Thermal boundary condition (see Boundary condition) Thermal capacitance, 74-75 Thermal circuit, 7, 73, 75-76. 86 steady-state, 77 Thermal conductance, 74-75,77 matrix, 163 Thermal conductivity, 61,64–65, 114, 134, 160, 170 effective, 135 uniform, 62 Thermal constraint, 167 Thermal coupling, 168, 171 Thermal diffusion length, 136 Thermal diffusivity, 62, 66 Thermal ground, 163-164 Thermal network, 8, 141 linear, 9 Thermal objective, 165-166

209

Thermal penalty, 167-169, 171 Thermal placement, 16-17, 157-159. 161, 165, 167-169, 171, 181 (See also Placement) Thermal resistance, 63-64, 78, 83, 86-87, 135 contact, 88 effective, 14 equivalent, 4, 166 L-shape, 140 lumped, 87 T-shape, 140 Thermal runaway, 3 , 5 Thermal simulation, 5 , 61, 88 ID/2D, 14 1 D/3D, 64 analytical, 16, 62, 82 fast analysis, 16, 62, 65, 82, 114 constraints, 67 for composite material, 76, 82 multilayered, 82-83 numerical, 16,62,72, 82, 136 package, 16, 83 semi-analytical, 83 Thermal stress, 121 Thermal time constant, 13 Thermal-electrical analogy, 137, 160 Thermistor, 105 Threshold voltage, 27, 46, 49, 97 temperature-dependent, 15, 45, 52 Threshold voltage-adjustment implant density, 47 Timing analysis, 182 dynamic method, 17, 182-183, 194 simulation engine, 182 early-mode, 183 late-mode, 183 static method, 17, 182-183, 197 block-oriented approach, 17, 184, 186-187 path enumeration, 184 path-oriented approach, 17, 184-185 sequential circuit, 189 temperature-driven, 17, 36, 18 1, 191, 196 Toggle power, 29 Transfer thermal resistance, 159, 161 matrix, 16, 161-164, 168 Transient temperature, 8-9, 1 1 Transistor merging, 98 Transition activity, 33 Transition density, 32 Transition probability, 30-32, 38 dynamic logic, 31 static logic, 3 1 Transverse electric field, 47, 53 Triple point in metal line, 127

Unidirectional current stress, 124 arbitrary, 126 dc, 125 pulsed, 126

2 10

ELECTROTHERMAL ANALYSIS OF VLSI SYSTEMS

Uniform thermal (temperature) distribution (see Temperature) Vacancy relaxation time, 125-126 Vacancy supersaturation model, 125 Variance of a random variable, 33,35 Viability condition, 189 Voiding, 123, 125 Warm-up period, 39 Waveform-relaxation method, 98

dynamic windowing technique, 99 partial waveform and time convergence technique, 99 Weibull distribution, 128 Weight function, 73 Zero-bias mobility, 50 Zero-bias threshold voltage, 46,52 Zero-bias transverse-field mobility degradation coefficient, 50 Zero-bias velocity saturation coefficient, 50