Post-Processing Techniques for Integrated MEMS

Post-Processing Techniques for Integrated MEMS

For a complete listing of the Artech House Microelectromechanical Systems Series, turn to the back of this book.

Post-Processing Techniques for Integrated MEMS Sherif Sedky

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Library of Congress Cataloging-in-Publication Data Sedky, Sherif. Post-processing techniques for integrated MEMS / Sherif Sedky. p. cm. — (Artech House microelectromechanical systems series) Includes bibliographical references and index. ISBN 1-58053-901-7 (alk. paper) 1. Microelectromechanical systems. I. Title. TK7875.S43 2005 621.381—dc22 2005050833

British Library Cataloguing in Publication Data Sedky, Sherif Post-processing techniques for intergated MEMS. — (Artech House MEMS series) 1. Microelectromechanical systems I. Title 621.3’81 ISBN-10: 1-58053-901-7 Cover design by Igor Valdman

© 2006 ARTECH HOUSE, INC. 685 Canton Street Norwood, MA 02062

All rights reserved. Printed and bound in the United States of America. No part of this book may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording, or by any information storage and retrieval system, without permission in writing from the publisher. All terms mentioned in this book that are known to be trademarks or service marks have been appropriately capitalized. Artech House cannot attest to the accuracy of this information. Use of a term in this book should not be regarded as affecting the validity of any trademark or service mark. International Standard Book Number: 1-58053-901-7 Library of Congress Catalog Card Number: 2005050833 10 9 8 7 6 5 4 3 2 1

To Mostafa, Ahmed, and Laila

Contents Preface

xi

Acknowledgments

xiii

1

MEMS Monolithic Integration Techniques

1

1.1

Introduction

1

1.2 1.2.1

MEMS Fabrication Technologies Bulk Micromachining

5 6

1.2.2 1.2.3

Surface Micromachining LIGA

8

1.2.4 1.2.5

Deep Reactive Ion Etching Soft Lithography

11 12

1.2.6

Laser Micromachining

13

1.3 1.3.1

MEMS Monolithic Integration Technology Interleaved Processing

14 15

1.3.2

Post-Processing

18

1.4

Summary and Conclusion References

22 22

2

Maximum Post-Processing Temperature

31

2.1

Introduction

31

vii

9

viii

Post-Processing Techniques for Integrated MEMS

2.2

CMOS Technology

32

2.2.1 2.2.2

Front-End Description Backend Description

32 34

2.2.3

Measurement Setup

36

2.3 2.3.1

Impact of Annealing on Backend Impact of Annealing Temperature

37 37

2.3.2

Impact of Annealing Period

40

2.4

Impact of Annealing Temperature on the Front-End

45

2.5

Summary and Conclusion

47

References

48

3

MEMS Materials

51

3.1

Introduction

51

3.2

Stress and Stress Gradient in Thin Films

52

3.3

Metals as a MEMS Structural Layer

53

3.3.1 3.3.2

Tantalum as an Attractive MEMS Material Nickel for MEMS Applications

54 61

3.3.3 3.3.4 3.3.5

Platinum as a MEMS Material Gold as a MEMS Material Electroplated Copper

63 66 67

3.4 3.4.1

Semiconductor and Dielectric Materials Polycrystalline Silicon

69 70

3.4.2 3.4.3 3.4.4

Polycrystalline Germanium Silicon Nitride Silicon Dioxide

72 73 76

3.4.5

Porous Silicon

78

3.4.6

Silicon Carbide

79

3.5

Summary and Conclusion References

80 83

4

Silicon Germanium as an Attractive MEMS Material

91

4.1

Introduction

91

4.2

Actual Wafer Temperature

93

Contents

ix

4.3

Growth Kinetics of Silicon Germanium

94

4.4

Conduction Mechanism in Polycrystalline Silicon Germanium

99

4.5 4.5.1 4.5.2

Electrical Properties of Polycrystalline Silicon Germanium Characteristics of Ion-Implanted Polycrystalline Silicon Germanium

101 102

Characteristics of In Situ Doped Polycrystalline Silicon Germanium

107

4.6

Electrical Noise in Polycrystalline Silicon Germanium

110

4.7

Thermal Properties of Silicon Germanium

114

4.8 4.8.1

116

4.8.2 4.8.3

Stress in Polycrystalline Silicon Germanium Effect of Deposition Conditions and Annealing Temperature Impact of Reducing the Deposition Temperature Stress in PECVD Silicon Germanium

117 118 120

4.9

Stress Gradient in Silicon Germanium

121

4.9.1

Effect of Thermal Treatment and Doping Type on Stress Gradient Effect of Deposition Conditions and Ge Content

122

on Stress Gradient

124

4.10

Summary and Conclusion References

128 130

5

Low Thermal Budget Techniques for Enhancing Crystallization

135

5.1

Introduction

135

5.2 5.2.1

Metal Induced Crystallization of SiGe MIC for MEMS Application

136 138

5.3 5.3.1 5.3.2

Laser Induced Crystallization Laser Setup Effect of Laser Annealing on Grain Microstructure, Electrical Conductivity, and Surface Roughness Film Melt Depth

144 145

4.9.2

5.3.3

145 149

x

Post-Processing Techniques for Integrated MEMS

5.3.4

Effect of Laser Annealing on Mean Stress and Stress Gradient

153

Summary and Conclusion

157

References

159

6

Post-Processed MEMS Devices

163

6.1

Introduction

163

6.2

Monolithically Integrated Surface Micromachined Structures

164

5.4

6.2.1 6.2.2 6.3 6.4

Monolithic Integration of DMDs Monolithic Integration of Surface Micromachined Accelerometers

164 168

Monolithic Integration Using Bulk Micromachining and DRIE

186

Summary and Conclusion

189

References

190

List of Acronyms

197

About the Author

201

Index

203

Preface Recent developments in integrated circuit fabrication technology have given rise to a new generation of devices that are not purely electronic in character. In such devices, the dimensions of conventional mechanical systems are reduced to a few microns or down to a few tens of nanometers and are combined with electrical components to form microelectromechanical systems (MEMS) or nano- electromechanical systems (NEMS). The reduction in dimension of the mechanical systems results in a dramatic decrease of power consumption and cost, as well as a significant improvement in yield and reliability. MEMS/NEMS are currently used in a broad range of applications including the automotive industry, digital projection displays, imaging, space applications, wireless communication, data storage, DNA analysis, and medical applications. The increased demand to implement MEMS in a wide variety of systems requires the monolithic integration of these devices together with the driving and control electronic circuitry on the same chip. This improves yield and reliability, especially for commercial devices used in sensitive applications such as airbag deployment systems or in applications that require high-density integration, as is the case for digital projection displays. Ideally, MEMS monolithic integration should be simple and cost-effective while enabling the optimization of the physical properties of the MEMS structural layers in order to yield high-performance devices. Thus, the process of merging MEMS and electronics should be modular and should not introduce any modifications to the standard electronics fabrication process. Furthermore, there should be no limits imposed on the MEMS structural layer thickness, electrical conductivity, and mechanical properties.

xi

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Post-Processing Techniques for Integrated MEMS

Currently, there are many MEMS monolithic integration approaches developed by several companies as well as by academia. Each approach has its own pros and cons. In general, optimizing the performance of MEMS involves using a complicated process. This is mainly due to the fact that most of the materials commonly used as a MEMS structural layer for high-performance devices are processed at relatively high temperatures (> 800°C), and accordingly, MEMS cannot be post-processed on top of the driving electronics. As a result, the integration process becomes more complicated and more expensive. The main purpose of this book is to investigate the possibility of developing high-quality MEMS structural layers at temperatures compatible with the standard CMOS backend. First the MEMS fabrication technologies are reviewed. This is followed by defining the maximum thermal budget that can be accommodated by prefabricated standard electronics. Then, the attractive features of the different materials suitable for MEMS are highlighted. The effect of the deposition conditions and the type of substrate on the physical properties of the different materials is then discussed. Recently, silicon germanium has gained a lot of attention as a MEMS structural layer that can be processed at a CMOS backend temperature and preserve attractive properties for a wide variety of MEMS application. This material is investigated in detail, as it seems to give promise for a simple modular integration process for MEMS on top of standard preprocessed electronics. In addition, low thermal budget techniques that can locally modify the physical properties of the MEMS material without affecting the underlying layers are introduced. Finally, an overview of the recent developments in the field of MEMS monolithic integration with the driving electronics is given. The advantages and disadvantages of the different approaches implemented either commercially or in academia are highlighted. Finally, the milestones on the road to the formation of a generic modular monolithic integration of MEMS with the driving electronics are defined.

Acknowledgments It is with great pleasure that I express my deepest thanks and gratitude to all those who contributed to this work. First, I would like to thank Professor Robert Mertens, IMEC senior vice president, who introduced me to the fascinating field of MEMS in 1995. I am also greatly indebted to Professor Paolo Fiorini who introduced me to the use of silicon germanium as a MEMS structural material. It was a great pleasure to collaborate with Professor Fiorini over the last 10 years during the course of which so many new ideas for reducing the MEMS thermal budget were developed. Without the valuable feedback and critical comments of Professor Fiorini, this book would never have been in its current shape. I acknowledge my gratitude to Dr. Chris Van Hoof, Dr. Kris Baert, Dr. Ann Witvrouw, and Dr. Matty Caymax, for many interesting discussions, for suggesting new approaches and techniques for MEMS monolithic integration, for instructive feedback, and for supporting my research on MEMS at IMEC during the last decade. I express my appreciation to Agnes Verbist, Bert Du Bois, and Ann De Caussemaeker for their outstanding and professional technical support, and also to Dr. Hugo Bender, Dr. Olivier Richard, Christel Drijbooms, Bert Brijs, and Luc Geenen for performing the advanced material characterization techniques reported in the different sections of this book. A special word of thanks is due to Ingrid Debusschere, Nicolas Lietaer, David Maes, and Brice De Jaeger for interesting discussions and for providing state-of-the-art CMOS wafers that were used for testing the maximum allowable CMOS backend thermal budget. Words are insufficient for expressing my gratitude and appreciation to Professor Roger Howe. Working with Professor Howe increased the depth of my understanding and appreciation of the field of MEMS. During my visit to

xiii

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Post-Processing Techniques for Integrated MEMS

the University of California, Berkeley, Professor Howe encouraged me to expand my interest in new interdisciplinary areas and he facilitated my interactions with various research groups at U.C. Berkeley. Also, I thank Professor Howe for his valuable feedback and advice concerning the different chapters of this book. I greatly enjoyed collaboration with Professor Tsu-Jae King, who introduced me to novel research ideas for merging MEMS with electronics. Furthermore, I express my gratitude to Professor Tim Sands for the breadth of his vision and his valuable advice during the implementation of laser-annealing techniques. I am indebted to Dr. Jeremy Schroeder for his support while executing excimer laser experiments at U.C. Berkeley. I would also like to acknowledge the technical support of Dr. Sunil Behave, Dr. Hideki Takeuchi, Kataline Voros, Sia Parsa, Jimmy Chang, Robert Hamilton, and Roger Loo for their technical support at the Berkeley Microfabrication laboratory. A special word of appreciation is due to Professor Fadel Assabghy, Dean of the School of Science and Engineering, for giving me the opportunity to start MEMS research at the Science and Technology Research Center of the American University in Cairo. Also, I express my gratitude to Dr. Ashraf El Figi, Vice President, Professor Tim Sullivan, Provost, Professor Mahmoud Farag, Vice Provost, and Professor Hosney Omar, Chair of the Physics Department, for supporting my research at the American University in Cairo. I am greatly indebted to Dr. Amr Shaarawi for the instructive discussions and precious feedback for the different chapters of this book. An acknowledgment is also due to Ms. Hoda El Ridi, head of Document Delivery at the American University Library, for the outstanding library service and support that I have enjoyed. Special thanks for Miss Amal Khalil for her enormous effort in providing me, promptly, with the required publications to complete this book. Ibrahim El Deftar and Nevine El Labban are thanked for the careful and precise review of the final manuscript. I would like to acknowledge the different institutes, publishers, and authors that granted permissions for reusing figures from their earlier publications: the Institute of Electrical and Electronics Engineers (IEEE), European Physical Journal, the Institute of Electrical Engineers of Japan (IEEJ), Elsevier, the American Institute of Physics, the International Society for Optical Engineering (SPIE), the Materials Research Society, the Electrochemical Society, PennWell Publishing, the Institute of Physics, the Taylor & Francis Group, Professor Steven M. Yalisove, Professor Euijoon Yoon, and Dr. Chen-Kuei Chung. Finally, I thank Julie Lancashire, and Tiina Ruonamaa, Katherine Nolan, and Kate Remelt of Artech House for the huge effort they put forth during the different publication phases of this book. Also, a special acknowledgment is due to the reviewer of the final manuscript whose comments and feedback greatly improved the quality of this book.

1 MEMS Monolithic Integration Techniques 1.1 Introduction Microelectromechanical systems (MEMS) is an enabling technology that implements techniques similar to traditional integrated circuit fabrication processes to realize highly miniaturized devices that can ultimately integrate a number of functions including mechanics, electronics, optics, and fluidics on a single silicon chip [1–7]. MEMS merge sensing, actuating, and computing into miniature systems that enable enhanced levels of perception, control, and performance. The major attraction of MEMS technology is the order of magnitude reduction of power and thermal requirements over existing electronic components. Recent advances in MEMS technology have made it possible to produce pressure, acceleration, humidity, and temperature sensors having masses in the milligram range or even lighter (excluding the package). The tremendous evolution of MEMS has had a direct impact on wireless communication as it enabled the realization of a new generation of high-performance radio frequency MEMS (RF-MEMS) to replace off-chip passives such as high-Q inductors, ceramic and surface acoustic wave (SAW) filters, varactor diodes and discrete PIN diode switches [8–11]. The integration of MEMS into traditional RF circuits will result in systems with superior performance levels and lower manufacturing costs. The incorporation of MEMS-based fabrication technologies into micro and millimeter wave systems offers viable routes to integrated circuits (ICs) with MEMS actuators, antennas, switches, and transmission lines. The resultant systems are expected to operate with an increased bandwidth and increased radiation efficiency and have considerable scope for 1

2

Post-Processing Techniques for Integrated MEMS

implementation within the expanding area of wireless personal communication devices. From a future prospective, the integration of sensors and RF signal processing functions would expand the application space for MEMS tremendously. It will be harder and harder to figure out how much MEMS will account for when it is merged into systems such as cell phone transceivers. In the near future, MEMS switch, MEMS resonator oscillator, and MEMS filters, like the FBAR, are expected to be used by millions per year. Recently, there has been a huge evolution in optical systems for telecommunications to meet the needs for increased bandwidth, for optical networks with terabit capacities per fiber link, and for local area networks. Some applications require precise features for optical alignment while others involve the precise movement of small optical parts to achieve advanced functionality. Using MEMS, low-loss, optical connections are made between different guided wave optical components including fibers, waveguides, and lasers. Applications for MEMS in telecommunications were inspired by the emergence of the digital micromirror projection display (DMD), which are the world’s largest MEMS device with chips ranging from hundreds of thousands to a few million electrostatically actuated torsion mirrors [12–14]. DMDs are considered mature MEMS devices that demonstrates the commercial impact of MEMS. Currently, more than 50% of the projectors and 18% of large screen TVs have a MEMS DMD chip inside. Microfluidics is now rapidly emerging as one of the most enabling technologies, which can give a strong impact on biochemical analysis on chip. Recently, there has been a large demand for the applications of microfluidics, which range from ink-jet printers to lab-on-a-chip. In microfluidics, MEMS offers potential for increased performance and better functional integration, at lower cost and size, as well as increased reliability [14, 15]. Furthermore, MEMS technology allowed the development of novel devices and microinstruments, especially in the area of deoxyribose nucleic acid (DNA) sequencing and analysis [16–20]. The DNA extractor, having nanometer entropic barriers and micropillar array, is fabricated by micromachining processes. In medical applications, MEMS is used to design surgical instruments that incorporate various kinds of sensors such as chemo sensors, which can detect the pH, oxygen, and carbon dioxide levels in tissue, as well as other chemical entities of clinical importance [21–29]. MEMS pressure sensors are also used in vital signs monitors; to remove fluid from the eye during surgery, for blood analysis, in inhalers, for blood and fluid pressure measurement during kidney dialysis, in drug delivery systems, and in pacemakers. An attractive feature for MEMS-based devices is that they are resistant to radiation damage and operate comfortably in high-radiation environments. Aerospace MEMS development leads to constellations of cheap satellites, which enhances communications and remote sensing. MEMS technology has obvious

MEMS Monolithic Integration Techniques

3

advantages for space applications, since it offers the promise of highly capable devices with ultra low mass, size, and power consumption [30–33]. For many portable applications such as laptop computers and video camcorders, MEMS-based storage devices provide a more robust and lower-power solution [34–36]. They are much more immune to gyroscopic effects and can absorb much greater external forces. Furthermore, such devices can add huge databases to single-chip continuous speech recognition systems and can be integrated into low-cost consumer or mobile devices. Single chip throw-away MEMS storage devices are widely used for modest-capacity applications in the 1- to 10-GB range such as civil infrastructure monitoring (e.g., bridges, walls, roadways), weather or seismic tracking, and medical applications. Fuel cells are electrochemical energy conversion devices that convert hydrogen and oxygen into electricity and heat. Like a battery, a fuel cell can be recharged while power is being drawn from it, but instead of recharging using electricity, a fuel cell uses hydrogen and oxygen. MEMS technology provides lighter-weight, smaller, cheaper and longer-lasting fuel cells [37–40]. Such a MEMS-based power source is expected to replace rechargeable batteries, such as lithium-ion and lithium-ion polymer in devices like cell phones, laptops, and handheld devices. Moreover, they can be integrated with MEMS-based biomedical implantable devices. The miniaturization capability of MEMS technology enabled the emergence of a new generation of thermal infrared (IR) sensors operated at ambient temperature [41–45]. These detectors created the opportunity for achieving low-cost infrared imaging systems for both military and commercial applications. Uncooled MEMS infrared focal plane arrays (FPAs) are used for a wide variety of applications including, but not limited to, attitude control of microsatellites, contactless measurements of human body temperature, night vision, search tracks, fire fighting, and the detection of earth resources. Over the last decade, the automotive industry has been using millions of MEMS sensors to control engine performance, enhance driving safety in foggy environments, monitor tire pressure, as well as for collision avoidance radar systems and for satellite accelerometer systems [46–49]. MEMS inertial sensors [50–54] are widely used for air bag control, for vehicle dynamic control (VDC) systems, which enable the driver to regain control of the automobile when it starts to skid, for roll-over detection, for antitheft systems incorporating tilt detection systems where low-g MEMS sensors are ideal, for electronic parking brake systems, and for vehicle navigation systems. Furthermore, MEMS-based infrared thermal imaging allows an early and reliable detection of road obstacles in front of the car, providing an effective nighttime viewing system that could mitigate the inefficiency of the usual sensors and fulfill night driving safety requirements.

4

Post-Processing Techniques for Integrated MEMS

The increased demand on implementing MEMS in various systems mandates their integration with the driving controlling and signal processing electronics. This can be achieved by hybrid integration [55–59] or by monolithic integration [46, 60–63]. In general, there is a strong debate whether to use monolithic or hybrid integration, as each approach has its own advantages and limitations. In the hybrid approach, the MEMS structures are fabricated on a substrate different than that of the driving electronics, which is then connected to the electronics by flip chip, wire bonding or self assembly. Accordingly, there are no strict limits on the MEMS thermal budget or contamination. The main limitation of this approach is pronounced in high-density integration, as the fill factor is low due to the relatively large area occupied by the bonding pads. Furthermore, the parasitic capacitance is relatively high, which has a negative impact on the device functionality, specifically for RF-MEMS. On the other hand, monolithic integration combines MEMS and the driving electronics on the same chip, and hence, eliminates parasitic capacitance, improves performance, yield, and reliability, and lowers the manufacturing, packaging, and instrumentation costs. It should be noted also that monolithic integration is economical if the process yield is 100%, otherwise hybrid would be much more economical. In general, most of the commercially available driving electronics are based on complementary metal oxide semiconductor (CMOS) technology. Accordingly, it is worthwhile considering merging MEMS with this type of technology. Adding the transducer-specific process steps and modules to a CMOS process can be done in three different ways: as preprocessing [64, 65] [Figure 1.1(a)], as interleaved processing, or as post-metal processing steps [Figure 1.1(b)]. In the preprocessing approach, MEMS are completely fabricated prior to the CMOS process. Accordingly, to allow the wafers to enter a microelectronics fabrication line, there are lots of constrains on contamination introduced by the MEMS process. Furthermore, both preprocessing and interleaved processing introduce significant changes to the standard CMOS process flow, and hence, the integration process becomes expensive. If possible, the post-processing route is preferred as it enables integrating MEMS without introducing any changes to the standard CMOS fabrication processes. Hence, the manufacturing process becomes simpler, modular, cost-effective, and independent of the type of technology used to fabricate the driving electronics. The main constraint imposed by post-processing is that the maximum fabrication temperature of MEMS is limited to the temperature that does not introduce any damage or degradation in the performance of the existing electronics or interconnects. This temperature constraint is quite strict for post-processing surface micromachined MEMS, as it might affect relevant physical properties such as polycrystallinity, growth rate, mechanical properties, dopant activation, and electrical resistivity. The main objective of this book is to investigate the possibility of integrating MEMS monolithically with the driving electronics without introducing any

MEMS Monolithic Integration Techniques Driving electronics

5

MEMS

(a)

MEMS

Driving electronics

(b)

Figure 1.1 Possible approaches for monolithic integration of MEMS with the driving electronics: (a) preprocessing; and (b) post-processing.

changes into the standard electronics fabrication process, and at the same time the physical properties of the different MEMS structural layers can be optimized to maximize the device performance. To realize this objective, we first must specify the appropriate MEMS fabrication technology which is best suitable for this approach: either surface micromachining or bulk micromachining. A general process flow for integrating MEMS with CMOS electronics using an interleaved or post-processing approach is defined. This is followed by presenting a methodology for specifying the maximum post-processing temperature and duration on top of standard prefabricated electronics. Then, the MEMS materials that are compatible with standard CMOS backend are reviewed. Silicon germanium is introduced as an attractive material for MEMS, which can be processed at a CMOS backend temperature and at the same time has attractive properties suitable for a wide variety of MEMS applications. Techniques for enhancing crystallization at low temperatures such as metal-induced crystallization and laser-induced crystallization are presented. Finally, the state-of-the-art MEMS monolithically integrated devices are presented in the last chapter.

1.2 MEMS Fabrication Technologies Currently there are several technologies for fabricating MEMS. Bulk micromachining was the first technology used for realizing MEMS devices. In 1967

6

Post-Processing Techniques for Integrated MEMS

Nathanson et al. [66] introduced for the first time surface micromachining technology, which is currently considered the optimal route for integrating MEMS with the driving electronics [67]. In addition to bulk micromachining and surface micromachining, X-ray lithography is used to realize micromolds characterized by high aspect ratio (> 50) and a smooth surface. Such technology is referred to as LIGA and it will be introduced in the following subsections. Deep reactive ion etching is also widely used to realize MEMS structures having deep trenches with high aspect ratio (~ 20). Furthermore, there are new technologies that have been recently introduced such as soft lithography and laser micromachining. The following subsections give an overview of the different MEMS technologies. 1.2.1

Bulk Micromachining

Bulk micromachining is widely used for applications that might need a large proof mass such as accelerometers [68–72], gyroscopes [73–76], optical communication systems [77–79], or applications that require a high piezoresistive coefficient such as pressure sensors [80–82]. This technology is considered the simplest and least demanding micromachining technology from the point of view of capital equipment. The main concept of this technology is based on sculpting features in the bulk of the material by orientation-independent (isotropic) or orientation-dependent (anisotropic) wet or dry etchants. The advantage of using wet etching compared to dry etching is that it provides a higher degree of selectivity and it is much faster. Etch rate can reach few tens of microns for isotropic etching, and is reduced down to 1 µm/min for anisotropic etching. The main drawback of wet etching is that any modification of the wet etchant type, concentration, and/or temperature can change selectivity towards silicon dopant concentration and crystal orientation. Materials commonly used for bulk micromachining are silicon (Si), quartz, silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), germanium (Ge), and glass. To get a deeper insight of a typical isotropic and anisotropic bulk micromachining process flow, it is instructive to refer to Figures 1.2 and 1.3. The process starts by depositing and patterning a mask layer as shown in Figures 1.2(a) and 1.3(a). The mask material depends on the etching depth. Thick layers of SiO2 are used as a mask during isotropic shallow etching as it is easy to form and pattern. For deeper etching, a nonetching gold (Au) or silicon nitride (Si3N4) mask is required. After patterning the mask, the wafer is placed in the etching solution. Isotropic etchants etch in all crystallographic directions at the same rate and they are usually acidic such as hydrofluoric acid (HF), nitric acid (HNO3), and acetic acid (CH3COOH). Isotropic etchants move downwards and outwards from an opening in the mask and enlarge the etch pit while deepening, as can be seen in

MEMS Monolithic Integration Techniques

7

Mask

Si substrate

(a)

Si substrate (b)

Si substrate (c)

Figure 1.2 (a–c) Process flow for a typical MEMS bulk micromachining technology using isotropic etching. (Based on discussion presented in [1].)

Si substrate

Mask

(a)

(b)

(c)

Figure 1.3 (a–c) Process flow for a typical MEMS bulk micromachining technology using anisotropic etching. (Based on discussion presented in [1].)

8

Post-Processing Techniques for Integrated MEMS

Figure 1.2(b). The main disadvantage of isotropic etching is that the etch rate is temperature dependent and hence it is difficult to control lateral as well as vertical geometries. On the other hand, anisotropic etchants “machine” geometric shapes bounded by perfectly defined crystallographic planes [see Figure 1.3(b)]. In crystalline Si, {111} orientation has the highest atomic packing density and hence these planes are nonetching compared to other planes. Anisotropic etchants are usually alkaline aqueous solutions of KOH, NaOH, LiOH, CsOH, NH4OH, and quaternary ammonium hydroxides, with the possible addition of alcohol. After completing the etching, the mask layer is removed, as shown in Figures 1.2(c) and 1.3(c). In general, for bulk micromachining no driving electronics can exist underneath the micromachined structures. 1.2.2

Surface Micromachining

In surface micromachining technology structures are built up layer by layer on the surface of a substrate. Shapes in X-Y plane are defined by lithography followed by dry etching. A typical surface micromachining technology is displayed in Figure 1.4. First, a sacrificial layer is deposited. Then the anchoring points of the device are defined as illustrated in Figure 1.4(a). This is followed by depositing and patterning the MEMS structural layer. Finally, the sacrificial layer is etched away resulting in a suspended structure. This is the most critical step as Sacrificial layer (spacer)

Anchoring points

Substrate (a) Structural material

Substrate (b) Gap

Substrate (c)

Figure 1.4 (a–c) Process flow for a typical MEMS surface micromachining technology.

MEMS Monolithic Integration Techniques

9

the surface tension force might pull the suspended structure resulting in permanent stiction. To avoid this problem, surface tension force can be eliminated by coating the surface to reverse the shape of water meniscus underneath the structure to make the contact angle larger than 90° [83], performing etching in vapor HF [84], freeze drying of water/methanol mixture [85], using super critical drying techniques [86], or by deflecting the released structures out of the substrate by magnetic force during the drying process [87]. Furthermore, the sacrificial layer etchant should be highly selective with respect to the structural layer. There is a wide variety of sacrificial layers that can be used including, but not limited to, phosphorus silicon glass (PSG), silicon dioxide (SiO2) deposited by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), LPCVD & PECVD silicon nitride (Si3N4,), LPCVD polycrystalline silicon (poly Si), LPCVD polycrystalline germanium (Poly Ge), aluminum (Al), and gold (Au). Whereas, the MEMS structural layer can be Poly Si, Poly Si1−xGex, LPCVD & PECVD Si3N4, Polyimide, Ti, SiO2, and CVD Tungsten. It is clear that the surface micromachining technology is much more complicated than bulk micromachining as it implies the deposition of several layers. Moreover, depending on the deposition technique used for the different layers, the layer thickness can vary between a few tens of nanometers up to a few microns. Furthermore, the MEMS structural layer should be flat and suspended after being released, which means that it should have low mean stress and stress gradient. In general, a high temperature treatment is required to relief the internal stresses, as will be discussed in Chapters 3, 4, and 5. In spite of the drawbacks of the surface micromachining technology, it is the optimal route for post-processing MEMS on top of standard prefabricated electronics as it allows having the driving electronics directly underneath the device, which means a significant improvement in the fill factor and hence a higher integration density. Furthermore, the minimum feature realized by surface micromachining technology can be fractions of a micron, which is not the case for bulk micromachining. On the other hand, surface micromachining implies the deposition of polycrystalline films, which has a lower piezoresistance as compared to crystalline silicon. Moreover, Young’s modulus of the structural layer might vary from one device to the other. 1.2.3

LIGA

LIGA is the German acronym for X-ray Lithographie, Galvanoformung, and Abformtechnik, which means X-ray lithography, electrodeposition, and molding [1]. It is widely used for realizing three-dimensional structures having high aspect ratio (> 50) such as coupled-cavity traveling-wave tube (TWT) used as a millimeter wave source [88], MEMS variable capacitors having a quality factor

10

Post-Processing Techniques for Integrated MEMS

as high as 435 [89], massive parallel micromirrors [90], single mode waveguides [91], and electrostatic wobble motors [92]. Furthermore, LIGA technology has been successfully used to realize cylindrical lenses with spherical contours having an optical surface roughness below 50 nm [93]. Figure 1.5 gives a general overview of a typical LIGA process. This process involves a thick X-ray resist layer (from microns to centimeters) [Figure 1.5(a)] and a high energy X-ray exposure and development resulting in a three-dimensional resist structure [Figure 1.5(c, d)]. Electrodeposition is used to fill the resist mold with metal [Figure 1.5(e)]. After resist removal a freestanding structure results [Figure 1.5(f)]. The X-ray photoresist should have high sensitivity to X rays, high resolution, resistance to dry and wet etching, and thermal stability greater than 140°C. The unexposed resist must be absolutely insoluble during development, must exhibit very good adhesion to the substrate, should be compatible with the electroforming process, and must have low residual stress to avoid mechanical damage to the microstructures induced by stress during development. PolyMethylmMethAcrytale (PMMA) is the preferred resist for deep X-ray resist

Substrate (a)

Substrate (d)

X-ray mask Membrane

X-ray absorber

Substrate (b)

Substrate (e)

High energy X-ray radiation

Free-standing metal structure

Substrate (c)

Substrate (f)

Figure 1.5 Illustrative diagram for a typical LIGA process: (a) X-ray resist deposition; (b) X-ray mask; (c) exposure to high energy X ray; (d) developing the X-ray resist; (e) electrodeposition; and (f) resist removal. (Based on discussion presented in [1].)

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synchrotron etching [1]. The X-ray mask is composed of an absorber deposited on a membrane. The absorber is usually realized by materials having high atomic number to absorb X rays (e.g., Au) and produce high attenuation (> 10 dB). Also, the absorber layer should be stable under radiation over extended periods, easily patterned, and have negligible distortion and a low defect density. The mask membrane is realized by a material having low atomic number to transmit wavelengths from 0.2 to 0.6 nm with a transparency of at least 80%. Residual stress in the membrane should be less than 10 MPa. Typical membrane materials are Si, SiNx, SiC, diamond, beryllium (Be), and Ti [1]. To enhance the electroforming process, the substrate should be a conductor or an insulator coated by a conducting material. Typical substrates are: Austenite steel plate, Si covered by a thin Ti or Au/Cr top layer, and Cu plated with Au, Ti, or Ni [1]. Also, other metal substrates such as metal plated ceramic, plastic, and glass plates have been employed. Sometimes the metallic surface is mechanically roughened to have good adhesion between the X-ray resist and the metal layer. Electroplated Ni is widely used for defining LIGA structures [94, 95]. Typical depth of LIGA features is 20 to 500 µm, minimum lateral dimensions are 1 to 2 µm, and surface roughness is 0.03 to 0.05 µm (maximum peak to valley). The maximum lateral dimensions are 20 × 60 mm [1]. The main limitation for the LIGA technology is its using X-ray lithography, which is not used by the mainstream integrated circuit technology. This in return makes such technology extremely expensive and not popularly used. Furthermore, the fabrication of X-ray masks is much more difficult and expensive than the conventional IC masks. In 1989 IBM introduced a new photo resist: SU-8 [96], which can be spin coated in thick layers (∼500 µm) and will maintain high aspect ratio, high resolution, high sensitivity, low optical absorption, and good thermal and chemical stability. Accordingly, X-ray lithography has been replaced by conventional UV lithography [97–102], and a wide variety of devices has been realized by this technology. This includes electromagnetic power relays [98], arrays of microcavities [100], and gear reducers [101]. 1.2.4

Deep Reactive Ion Etching

The development of high-density plasma sources (> 1011/cm3) enhanced the etch rate of silicon and at the same time enabled the realization of high aspect ratio structures in crystalline silicon, which was not possible with conventional dry etching techniques. Using this etching technology, which is referred to as deep reactive ion etching (DRIE), micromolds can be realized at a much lower cost as compared to LIGA. DRIE is currently used in a wide variety of MEMS applications including ink jet heads [103], realization of the proof mass of post-CMOS gyroscopes [104], ultra small resonators [105], and tensional actuators to turn vertical mirrors with small angles [106].

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Post-Processing Techniques for Integrated MEMS

To enhance the etch rate of silicon, DRIE uses fluorine-based gases as this increases the etch rate of silicon to 6 µm/min with a Si:SiO2 selectivity better than 150:1 [1]. To protect the sidewalls from etching, the wafer is cooled to cryogenic temperature, as this results in gas condensation of the reactant gases and accordingly the etching process is more anisotropic and the sidewalls are vertical after etching. There are few drawbacks to DRIE such as the generation of micro grass or black silicon structures at the bottom of the deep silicon trenches, which is due to any contamination on the silicon surface, redeposition of the mask material, or due to sharpening of the ion angular distribution with the increasing aspect ratio of the trench during etching [1]. Furthermore, etch rates of silicon show a dependence on the aspect ratio and this is because etching is diffusion limited and the etching rate decreases with increasing the aspect ratio. 1.2.5

Soft Lithography

Soft lithography is an attractive technique that can be used for nonplaner substrates, unusual materials, and large areas. Moreover, it enables the fabrication of nanostructures having a minimum dimension of 30 nm. This technology has been recently implemented to realize MEMS devices such as plastic microcantilevers for force sensors [107], and arrays of ceramic gas sensors [108]. Soft lithographic techniques are also used to generate complex ceramic features without resorting to etching procedures [109]. Using a combination of soft molds and dry etching enables the realization of environmentally sensitive free-standing micromirrors based on hydrogels that can be integrated monolithically with the driving electronics [110]. Soft lithography uses a patterned elastomer as a stamp, mold, or mask to generate micropatterns or microstructures instead of using a rigid photomask. The elastomer stamp is generated by patterning a photoresist layer using conventional UV lithography as shown in Figure 1.6(a–c). Then the elastomer is cast into the patterned photoresist [Figure 1.6(d)]. Then the cast elastomer is removed, as seen in Figure 1.6(e). Polydimethylsiloxane (PDMS) is a good candidate for a stamp material as it is chemically inert, does not swallow with humidity, passes gases easily, has good thermal stability, and is optically transparent for wavelengths down to 300 nm. In addition, it is durable, which means that the stamp can be used several times. Using soft lithography, micropatterns are generated by microcontact printing, by microtransfer molding, or by micromolding in capillaries. In microcontact printing, the elastomer is immersed in the ink to be printed in selected areas of the substrate. In this case only the raised part of the elastomer will be coated by the ink molecules. When stamped on the substrate, self-assembled monolayers of the ink will be printed on the substrate in areas of good

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13

Photoresist

Substrate (a) UV exposure

Mask

Substrate (b)

Substrate (c)

Elastomer

Substrate (d)

(e)

Figure 1.6 Schematic cross sections for generating a soft lithography stamp: (a) spinning photoresist; (b) exposing the photoresist to UV through a mask; (c) developing the photoresist; (d) casting the elastomer; (e) removing the cast elastomer. (From: [1]. © 2002 CRC Press. Reprinted with permission.)

contact between the elastomer and the substrate. Microtransfer molding implies filling the grooves in the elastomer with polymer precursors, and then the elastomer stamp is pushed against the substrate. After curing the polymer, it is transferred to the substrate and the stamp is peeled off. Soft lithography based on micromolding in capillaries is used to realize plastic field effect transistors [111] and Pt-Si Schottky diodes [112]. In this case, the elastomer stamp is pushed against the substrate, then a liquid polymer is applied which wicks into the cavities of the elastomer. After curing, the elastomer is removed, and the patterned polymer remains on the substrate. 1.2.6

Laser Micromachining

Pulsed laser is an efficient, multipurpose technology that can be used for MEMS processing. The short pulse duration together with the high energy make laser annealing an attractive technique to locally modify the physical properties of the

14

Post-Processing Techniques for Integrated MEMS

MEMS layers without having any thermal impact on the under laying layers [113]. This issue is discussed in detail in Chapter 5. In addition, excimer laser annealing has been used to deposit a wide variety of thin films including metals and semiconductors [114–116]. A broad range of lasers can be implemented for micromachining; this includes microsecond infrared carbon dioxide lasers having wavelength between 9.3 and 11 µm [117, 118], nanosecond pulsed excimer lasers (157 to 353 nm) [119, 120], and femtosecond pulsed solid state lasers (266 to 1,060 nm) [121, 122]. In general, optimal laser micromachining is achieved when photons are absorbed in submicron depth. Moreover, the short pulse duration creates localized ablation in the irradiated surface without having any lateral thermal impact on the surrounding area. Thus, depending on the beam spot size, micromachining can be localized to a few microns area. As most materials absorb short wavelengths, ultra violet lasers are much more suited for micromachining applications as compared to infrared lasers. Furthermore, short wavelengths are less diffracted, and accordingly, the beam can be controlled to be localized in smaller lateral areas, hence reducing the dimensions of micromachined features [123]. Short wavelength (157 to 193 nm) UV excimer lasers have proven ideal for processing difficult materials such as borosilicate glass, quartz, and fused silica, exhibiting the ability to machine complex features with large area and characteristic smooth cuts, which is attractive for applications such as precise drilling of microscopic apertures [124]. The use of high energy femtosecond laser micromachining enabled the realization of submicron features, which allowed the fabrication of several types of MEMS and optoelectronic devices for sensors and other applications using direct laser writing process [125]. Using this type of laser, three-dimensional structures with high aspect ratio can be realized without the need for masks [126].

1.3 MEMS Monolithic Integration Technology In general, integrating MEMS on the same chip containing the driving electronics depends on the technology used for realizing the MEMS device. For bulk micromachined MEMS, or surface micromachined MEMS realized by high temperature materials such as silicon carbide or poly Si deposited at high temperature, the MEMS structures are processed prior to the CMOS process. This technique is referred to as the preprocessing approach, and in most cases surface micromachined structures are processed in a deep trench. After finishing the MEMS process the trench is filled with oxide and then the wafer is planarized with Chemical Mechanical Polishing (CMP). Hence the CMOS process starts with a planarized wafer. The main advantage of this integration technique is that it does not impose any thermal limit on the MEMS fabrication process and

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accordingly it is commercially implemented by lots of companies as explained in detail in Chapter 6. The following sections give deeper insight of merging MEMS with the driving electronics using interleaved process or by post-processing. It should be noted that the CMOS process considered in the following subsections is a simple process with one or two metallization levels as the main objective is to give the reader a general overview of each approach. A more comprehensive discussion is presented in Chapter 6, with a focus on the technologies developed by academia and various companies. 1.3.1

Interleaved Processing

The main concept of this approach is based on matching the high processing temperature steps of MEMS to that of the CMOS process. The process flow defined in Figure 1.7 demonstrates how this could be realized. It should be noted that depending on the actual CMOS fabrication technology, the actual CMOS process might deviate slightly from that displayed in Figure 1.7, but the methodology presented in this section should not be conceptually affected. The CMOS process flow proceeds normally until depositing the intermetal dielectric layer as demonstrated in Figure 1.8(a). At this point, the MEMS process starts by etching the spin on glass (SOG) and phosphorus silicon glass (PSG) from the position of the MEMS [see Figure 1.8(b)]. The field oxide together with the tetra ethyl ortho silicate (TEOS) layer will be used as the sacrificial layer, where the anchoring points are patterned as shown in Figure 1.8(c). This is followed by depositing and patterning the MEMS structural layer, which is in general a high temperature step [Figure 1.9(a)]. After thermally tuning the physical properties of the MEMS structural layer, the CMOS process is continued in the standard way as shown schematically in Figure 1.9(b,c). Before etching the sacrificial layer, the oxide of the CMOS circuits should be isolated from that of the MEMS, to avoid damaging the driving electronics. This can be done by pattering the TEOS and field oxide surrounding the MEMS device, then depositing and patterning 2 µm of silicon nitride (Si3N4), as illustrated in Figure 1.10(a). The thickness of the Si3N4 layer is selected to stand the etchant of the oxide sacrificial layer. It should be noted that the distance, x, between the MEMS structural layer and the intermetal dielectric layer [Figure 1.9(a)] should be large enough to accommodate the deposition and patterning of the protection layer. Finally, the MEMS structure is released by etching the sacrificial layer. At this point, it is instructive to note that the MEMS structural layer should stand the etchant of the intermetal dielectric layer (which is used as the sacrificial layer). This fact narrows the choice of the MEMS active material. The main disadvantage of this approach of integration is that it interferes strongly with the CMOS process flow, and accordingly, special developments for different steps of the CMOS process flow might be required, which means

16

Post-Processing Techniques for Integrated MEMS

start p-type <100> wafers or p/p+ <100> EPI wafers

N-well Pad oxidation. Photostep N well. N well implantation. N well drive. Etch the oxide.

Active Pad oxidation. Nitride deposition. Photostep active + etch. Photostep N field. N implantation. Field oxidation.

Junctions Back side etch. Photostep Nplus. Nplus implantation. Photostep Pplus Pplus implantation. Anneal. Rapid thermal anneal.

Contacts and metal 1 TEOS deposition. SOG coat. PSG deposition. Anneal.

Photostep MEMS. Etching PSG and SOG. Photostep anchoring points

Plasma oxide deposition. SOG coat and cure. Plasma oxide deposition. Photostep via. Etch the via, this will include etching the layers on top of the MEMS structure. Metal 2 sputtering. Photostep Metal 2. Dry etch Metal 2.

Isolating the field oxide of CMOS circuits from that of the MEMS structure. Plasma nitride deposition. Photostep, dry etch plasma nitride on top of the MEMS.

of the MEMS structure. Channel Etch nitride + oxide. White ribbon oxidation. Photostep N field. Anti-punch through implantation.

Gate 1 Etch oxide. Gate 1 oxidation. VT-adjust implantation. Poly1 deposition. Poly1 implantation. Anneal. Photostep poly1 + etch.

Etch field oxide. Passivation. Deposit MEMS structural layer and tunning its physical properties

Photostep, etch MEMS structural layer

Photostep. Dry etch passivation windows. Sintering.

Etch the sacrificial layer Underneath the MEMS structure.

Contacts and metal 1 photostep contacts. Etch contacts. Metal 1 Sputtering. Photostep Metal 1. Etch Metal 1.

Figure 1.7 Process flow for integrating MEMS with driving electronics using interleaved processing.

that the integration process is expensive and time consuming. Furthermore, the proposed flow might be changed depending on the type of intermetal dielectric layer used for the specific CMOS processes. For low-k dielectrics, which do not stand high processing temperatures, the MEMS process should start prior to the CMOS process, which in turn results in high initial topography and makes the

MEMS Monolithic Integration Techniques

17

(a)

(b)

(c)

Figure 1.8 (a) CMOS process completed up to the intermetal dielectric layer. (b) Patterning TEOS, SOG, and PSG in the places where the MEMS structures are processed. (c) Etching the anchoring points of the MEMS structural material.

MEMS structural layer x µm

(a)

(b)

(c)

Figure 1.9 (a) Depositing and patterning the MEMS structural layer. (b) Opening metal contacts. (c) Depositing and patterning metal one.

18

Post-Processing Techniques for Integrated MEMS

(a)

(b)

Figure 1.10 (a) Patterning TEOS and field oxide in the region surrounding the MEMS device. Depositing and patterning 2 µm of LPCVD Si3N4. (b) Etching the sacrificial layer.

CMOS process much more complicated. In general, the fill factor of this process is low as the driving electronics are always processed beside the MEMS devices. In addition, the driving electronics should be encapsulated by a material that can stand the sacrificial layer etchant (to avoid attacking the field oxide), and thus we lose more space. The following section presents an integration approach that alleviates most of the drawbacks of interleaved post-processing. 1.3.2

Post-Processing

The monolithic integration cost can be reduced significantly if the MEMS device is processed on top of standard prefabricated CMOS circuits, as this does not introduce any modifications to the standard process flow. In addition to cost reduction, post-processing noticeably improves the fill factor as the driving electronics can be positioned directly underneath the MEMS devices. Furthermore, this approach broadens the choice of the MEMS sacrificial layer and structural material. The only constraint imposed by this technique is that the MEMS processing temperature should not introduce any damage or modifications to the standard characteristics of the driving electronics. To have a general idea about post-processing, it is instructive to refer to the process flow displayed in Figure 1.11. The CMOS process is completed to the end of metallization and passivation [see Figure 1.12(a)] and without opening the metal contacts, as this will be done at the end of the MEMS process. Before starting the MEMS process, it is recommended to protect the different CMOS layers with a thin film that can stand the etchants of the different MEMS layers[Figure 1.12(b)]. Accordingly, the type of this film might differ from one MEMS device to the other. The different MEMS layers are deposited and patterned according to the device under consideration

MEMS Monolithic Integration Techniques

19

start p-type <100> wafers or p/p+ <100> EPI wafers

Junctions Back side etch. Photostep Nplus.

Deposit MEMS sacrificial layer

Nplus implantation. N-well Pad oxidation. Photostep N well. N well implantation. N Well drive. Etch the oxide.

Photostep Pplus Pplus implantation. Anneal. Rapid thermal anneal.

Contacts and metal 1 TEOS deposition.

Active Pad oxidation. Nitride deposition. Photostep active + etch. Photostep N field. N implantation. Field oxidation.

Photostep anchoring points of the MEMS structure. Etch sacrificial layer.

Deposit MEMS structural layer and tune its physical properties

SOG coat. PSG deposition. Anneal. Photostep contacts.

Photostep, etch MEMS structural layer

Etch contacts. Metal 1 sputtering.

Metal contacts:

Photostep metal 1.

Photostep,

Etch metal 1.

Pattern the contacts. Sputter contact metal, Pattern metal.

Channel Etch nitride + oxide.

Plasma oxide deposition.

White ribbon oxidation.

SOG coat and cure.

Photostep N field.

Plasma oxide deposition.

Anti-punch through implantation.

Photostep via. Etch the via, Metal 2 Sputtering.

Passivation. Photostep. Dry etch passivation windows. Sintering.

Photostep metal 2. Gate 1

Dry Etch metal 2.

Etch oxide. Gate 1 oxidation. VT-adjust implantation.

Plasma nitride deposition

Etch the sacrificial layer underneath the MEMS structure.

Poly1 deposition. Poly1 implantation. Anneal. Photostep poly1 + etch.

Deposit a protective layer for the different CMOS layers.

Figure 1.11 Process flow for post-processing MEMS on top of standard prefabricated CMOS driving electronics.

20

Post-Processing Techniques for Integrated MEMS CMOS passivation layer

(a)

Protective layer

(b)

Figure 1.12 Schematic cross sections for MEMS post-processing on top of standard prefabricated driving electronics: (a) standard CMOS process with metallization and passivation; and (b) depositing a thin protective layer for the different CMOS layers.

(a)

(b)

Figure 1.13 Schematic cross section for MEMS process on top of standard prefabricated driving electronics: (a) depositing and patterning the sacrificial layer; and (b) depositing and patterning the MEMS structural layer.

MEMS Monolithic Integration Techniques

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(see Figure 1.13). Then the MEMS device is connected to the driving electronics by opening a via through the stack formed by the MEMS structural layer, the insulating layer, and the CMOS passivation layer as illustrated in Figure 1.14(a). This is followed by depositing and patterning the interconnect layers [Figure 1.14(b)]. Finally, the sacrificial layer is etched [Figure 1.14(c)]. At this point it should be noted that the maximum MEMS processing thermal budget is determined by the actual CMOS process flow, the type of interconnects, and intermetal dielectric layers. In Chapter 2, it is demonstrated that the maximum post-processing temperature on top of standard 0.35-µm CMOS technology with aluminum interconnects is 520°C for a duration of 90 minutes. Thus, if the MEMS processing temperature cannot be reduced below

(a)

(b)

(c)

Figure 1.14 Schematic cross section for connecting MEMS device to the driving electronics: (a) opening the windows of metal contacts; (b) depositing and patterning metal; and (c) etching the sacrificial layer.

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Post-Processing Techniques for Integrated MEMS

650°C, then a special CMOS process is required where the interconnects are made of tungsten or copper, and the intermetal dielectric layers should stand high temperatures.

1.4 Summary and Conclusion This chapter gives an overview of the wide variety of MEMS applications. The principle micromachining technologies—namely, bulk micromachining, surface micromachining, LIGA, DRIE, soft lithography, and laser micromachining—are introduced. Integration of MEMS with the driving electronics can be realized by preprocessing, interleaved processing, or by post-processing. The first two approaches are suitable for the different types of micromachining technologies, but they require many modifications to the standard process flow and the integration density is not optimized, as the driving electronics cannot lie below the MEMS structure. On the other hand, postprocessing can significantly reduce the integration cost as it results in a modular process that does not introduce any modifications to the standard process. This approach imposes a limit on the thermal processing temperature of MEMS. Chapter 2 sets guidelines for determining the maximum MEMS post-processing temperature. Later chapters give an overview of the different MEMS materials and sacrificial layers that can be processed at a CMOS backend compatible temperature.

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[92] Samper, V. D., et al., “Multistator LIGA-Fabricated Electrostatic Wobble Motors with Integrated Synchronous Control,” Journal of Microelectromechanical Systems, Vol. 7, No. 2, June 1998, pp. 214–223. [93] Gerner, M., et al., “Micro-Optical Structures Realized by LIGA Technology,” Conference on Lasers and Electro-Optics Europe—Technical Digest, 1994, p. 218. [94] Borca-Tasciuc, D., et al., “Thermophysical Properties of Ni Films for LIGA Microsystems,” Materials Research Society Symposium—Proceedings, Vol. 782, Micro- and Nanosystems, 2003, pp. 371–376. [95] Cho, H. S., et al., “Measured Mechanical Properties of LIGA Ni Structures,” Sensors and Actuators, A: Physical, Vol. 103, No. 1–2, January 15, 2003, pp. 59–63. [96] Gelorme, J., R. Cox, and S. Gutierrez, “Photoresist Composition and Printed Circuit Boards and Packages Made Therewith,” U.S. Patent No. 4,882,245, November 21, 1989. [97] Li, B., and Q. C. Quanfang, “Low Stressed High-Aspect-Ratio Ultra-Thick SU-8 UV-LIGA Process for the Fabrication of a Micro Heat Exchanger,” Proceedings of SPIE— The International Society for Optical Engineering, Vol. 5344, 2004, pp. 147–154. [98] Williams, J., and W. Wang, “Microfabrication of an Electromagnetic Power Relay Using SU-8 Based UV-LIGA Technology,” Microsystem Technologies, Vol. 10, No. 10, December 2004, pp. 699–705. [99] Ho, C.-H., et al., “Ultrathick SU-8 Mold Formation and Removal, and Its Application to the Fabrication of LIGA-Like Micromotors with Embedded Roots,” Sensors and Actuators, A: Physical, Vol. 102, No. 1–2, December 1, 2002, pp. 130–138. [100] Roberts, K., et al., “Fabrication of an Array of Microcavities Utilizing SU-8 Photoresist as an Alternative ‘LIGA’ Technology,” Biennial University/Government/Industry Microelectronics Symposium—Proceedings, 1999, pp. 139–141. [101] Zhang, W., et al., “The Modeling and Fabrication of Micro 3K-2 Type Planetary Gear Reducer Utilizing SU-8 Photoresist as Alternative ‘LIGA’ Technology,” Proceedings of SPIE - The International Society for Optical Engineering, Vol. 4601, 2001, pp. 271–277. [102] Ho, C.-H., and W. Hsu, “Experimental Investigation of an Embedded Root Method for Stripping SU-8 Photoresist in the UV-LIGA Process,” Journal of Micromechanics and Microengineering, Vol. 14, No. 3, March 2004, pp. 356–364. [103] Hopkins, J., “DRIE of Silicon for MEMS Inkjet Heads,” Semiconductor International, Vol. 27, No. 12, November 2004, pp. 83–84. [104] Xie, H., and G. Fedder, “Fabrication, Characterization, and Analysis of a DRIE CMOSMEMS Gyroscope,” IEEE Sensors Journal, Vol. 3, No. 5, October 2003, pp. 622–631. [105] Chang, D., et al., “Optimized DRIE Etching of Ultra-Small Quartz Resonators,” Proceedings of the Annual IEEE International Frequency Control Symposium, 2003, pp. 829–832. [106] Yang, Y., et al., “Novel MEMS Torsional Mirror Optical Switch,”Proceedings of SPIE— The International Society for Optical Engineering, Vol. 5281, APOC 2003: Asia-Pacific Optical and Wireless Communications: Optical Transmission, Switching and Subsystems, 2003, pp. 718–726. [107] Ferrell, N., J. Woodard, and D. Hansford, “Design and Fabrication of a Polymer MEMS Cell Force Sensor for Measuring Single Cell Biomechanics,” Proceedings of the Second IASTED International Conference on Biomechanics, Proceedings of the Second IASTED International Conference on Biomechanics, 2004, pp. 146–149.

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[108] Heule, M., and L. Gauckler, “Micromachined Nanoparticulate Ceramic Gas Sensor Array on MEMS Substrates,” Materials Research Society Symposium—Proceedings, Vol. 687, 2002, pp. 69–74. [109] Yang, H., et al., “Fabrication of High Performance Ceramic Microstructures from a Polymeric Precursor Using Soft Lithography,” Advanced Materials, Vol. 13, No. 1, January 2001, pp. 54–58. [110] Lei, M., et al., “Soft Mold-Dry Etch: A Novel Hydrogel Patterning Technique for Biomedical Applications,” Conference Proceedings of the 26th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2004, 2004, pp. 1983–1986. [111] Rogers, J., and V. Raju, “Nonphotolithographic Fabrication of Organic Transistors with Micron Features Size,” Applied Physics Letters, Vol. 72, 1998, pp. 2716–2718. [112] Erhardt, K., and R. Nuzzo, “Fabrication of Pt-Si Schottky Diodes Using Soft Lithography Patterning and Selective Chemical Vapor Deposition,” Langmuir, Vol. 15, 1999, pp. 2188–2193. [113] Sedky, S., and A. Witvrouw, “Micromachining of Pulses Laser Annealed PECVD SixGe1-x Deposited at Temperatures 370°C,” 18th IEEE Conference on Micro Electro Mechanical Systems, MEMS 2005, Miami, Florida, 2005, pp. 487–490. [114] Puretzky, A., “Amorphous Diamond-Like Carbon Film Growth by KrF- and ArF-Excimer Laser PLD: Correlation with Plume Properties,” Materials Research Society Symposium—Proceedings, Vol. 388, Film Synthesis and Growth Using Energetic Beams, 1995, pp. 145–150. [115] Dhote, A., and S. Ogale, “Deposition of Tungsten Films by Pulsed Excimer Laser Ablation Technique,” Applied Physics Letters, Vol. 64, No. 21, May 23, 1994, pp. 2809–2811. [116] Fu, G., et al., “Preparation of Nanocrystalline Silicon Films by Excimer Laser-Induced Crystallization,” Proceedings of SPIE—The International Society for Optical Engineering, Vol. 4905, 2002, pp. 438–441. [117] Baker, H., et al., “Precision Laser Processing of Optical Microstructures with Slab Waveguide CO2 Lasers,” Proceedings of SPIE—The International Society for Optical Engineering, Vol. 3888, 2000, pp. 625–634. [118] Yoshida, Y., et al., “Hole Drilling of Glass-Foam Substrates with Laser,” Proceedings of SPIE —The International Society for Optical Engineering, Vol. 4426, 2002, pp. 154–157. [119] Choi, K., et al., “Excimer Laser Micromachining for 3D Microstructure,” Journal of Materials Processing Technology, Vol. 149, No. 1–3, June 10, 2004, pp. 561–566. [120] Jolic, K. I., et al., “Fabrication of Three-Dimensional Inductor Coil Using Excimer Laser Micromachining,” Journal of Micromechanics and Microengineering, Vol. 13, No. 5, September 2003, pp. 782–789. [121] Gupta, M., and M. El-Bandrawy, “Femtosecond Laser Micromachining of Silicon for MEMS,” Proceedings of SPIE—The International Society for Optical Engineering, Vol. 4977, 2003, pp. 219–225. [122] Sanner, N., et al., “100-kHz Diffraction-Limited Femtosecond Laser Micromachining,” Applied Physics B: Lasers and Optics, Vol. 80, No. 1, January 2005, pp. 27–30. [123] Gower, M., “Laser Micromachining for Manufacturing MEMS Devices,” Proceedings of SPIE—The International Society for Optical Engineering, Vol. 4559, 2001, pp. 53–59

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2 Maximum Post-Processing Temperature 2.1 Introduction The use of MEMS in such applications as infrared detectors [1, 2], accelerometers [3], gyroscopes [4], and RF-MEMS [5, 6] is continuously increasing. Monolithic integration of MEMS with the driving, controlling, and signal processing electronics on the same standard CMOS substrate can be advantageous as it improves performance, yield, and reliability and also lowers the cost of manufacturing, packaging, and instrumentation. As previously discussed in Chapter 1, the post-processing route is preferred because it enables integrating MEMS without introducing any changes to the standard CMOS fabrication processes. Hence, the manufacturing process becomes simpler, modular, cost-effective, and independent of the type of technology used to fabricate the driving electronics. The main constraint imposed by post-processing is that the maximum fabrication temperature of MEMS is limited to the temperature that does not introduce any damage or degradation in the performance of the existing electronics or interconnects. In general, the maximum post-processing temperature on CMOS wafers with Al interconnects is considered to be 450°C [7]. This temperature constraint is quite strict for post-processing surface micromachined MEMS, as it might affect relevant physical properties such as polycrystallinity, growth rate, mechanical properties, dopant activation, and electrical resistivity. Consequently, post-processing surface micromachined MEMS will be limited to materials having low deposition and annealing temperature such as metals or semiconductor material having low crystallization temperature such as germanium. To broaden the material choice and to have more freedom to optimize the performance of the post-processed devices, it is

31

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Post-Processing Techniques for Integrated MEMS

essential to investigate the possibility of exceeding the 450°C limit and to determine precisely the maximum post-processing temperature. This chapter sets guidelines for the experimental determination of the maximum post-processing temperature on top of standard CMOS wafers with aluminum-based interconnects and tungsten plugs. We consider as an example 0.35-µm CMOS technology for demonstrating the critical parameters that are significantly affected by the annealing temperature. It should be noted that the temperature limits deduced might not be valid for 0.13-µm CMOS technology (or later), but the methodology presented in this chapter can be implemented on the state-of-the-art CMOS technologies to determine the maximum post-processing thermal budget that can be tolerated. Section 2.2 gives a detailed description of 0.35-µm CMOS technologies with different interconnect aluminum-based alloys (either Al-1wt%Si-0.5wt%Cu [AlSiCu] or Al-0.5wt%Cu [AlCu]) and different back-end structures. As some MEMS applications require the deposition of thick structural layers, it is instructive to study the impact of both the temperature and period on the CMOS characteristics. Sections 2.3 and 2.4 present a detailed analysis of the consequences of the gradual increase of the annealing temperature from 425°C to 575°C, for periods varying between 30 to 90 minutes on the CMOS backend and front-end characteristics. It is shown that the maximum annealing temperature is a function of the structure and composition of the interconnect layers and their maximum allowable resistance increase. It is also demonstrated that the transistor characteristics, the silicide quality, and the leakage currents are as good as unaffected by annealing for 90 minutes at temperatures up to 525°C.

2.2 CMOS Technology In general, it is expected that the impact of annealing on the characteristics of a CMOS technology is determined by the type of the aluminum alloy used as interconnect layer (either AlSiCu or AlCu), the presence of titanium (Ti) or titanium nitride (TiN) below or on top of the interconnect lines, the number of interconnect levels, and the type of pre- and intermetal dielectric layers. To analyze the effect of these parameters, we consider two different 0.35-µm CMOS technologies, having the schematic cross sections displayed in Figure 2.1 [8]. The front-end of these technologies is similar; the backend differs significantly as highlighted in the following sections. 2.2.1

Front-End Description

For both technologies, N-wells are formed by ion implantation with a phosphorous dose of 8 × 1012, 2.5 × 1012, and 7 × 1012 cm–2P. On the other hand,

Maximum Post-Processing Temperature

33

Pre-metal dielectric Inter-metal dielectric HDP USG

PECVD oxide

HDP PSG

TEOS

Interconnection stack

HDP oxide Tungsten plugs (CMP)

Ti/TiN

500 nm field oxide Low doped drain (LDD)

P-well

N+ doped drain

Gate oxide (7 nm)

TiSi 2

N+ doped source

P+ doped source

P+ doped drain

N-well

Gate (a-Si, 250 nm) (a)

Inter-metal dielectric

Pre-metal dielectric

TEOS

USG

LPCVD PSG

PECVD oxide

PECVD oxide

Interconnection stack

SOG FOX Tungsten plugs (etch back) Ti/TiN

500 nm field oxide P-well

Low doped drain (LDD)

N+ doped drain

TiSi 2 N+ doped source

P+ doped drain

Gate oxide (7 nm) P+ doped source N-well

Gate (a-Si, 250 nm) (b)

Figure 2.1 Schematic cross sections of the 0.35-µm CMOS technologies under consideration: (a) technology A and B from Table 2.1; and (b) technology C from Table 2.1. (From: [8]. © 2001 IEEE. Reprinted with permission.)

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P-wells are formed by ion implantation with boron doses of 1013, 5 × 1012, and 4 × 1012 cm–2B. NMOS and PMOS sources and drains are made by ion implantation of a low doping dose of phosphorus and boron of 5 × 1013 cm–2, followed by arsenic and boron high ion implantation dose of 4 × 1015 cm–2As and 3 × 1015 cm–2B, respectively. Titanium silicide (TiSi2) is formed by sputtering 55 nm of titanium on top of the drain, gate, and source, followed by a rapid thermal anneal for 30 seconds at 730°C, removal of excess titanium (Ti) and then another rapid thermal anneal for 30 seconds at 850°C. The field oxide thickness is 500 nm and the gate oxide is 7 nm thick. 2.2.2

Backend Description

The main differences between the technologies under consideration are in the pre- and intermetal dielectric layers and in the structure, composition, and number of interconnect levels. Table 2.1 gives an overview of the different technologies. CMOS technologies A and B are schematically displayed in Figure 2.1(a). The premetal dielectric layer is composed of 100 nm of tetra ethyl ortho silicate (TEOS), 350 nm of high-density plasma (HDP) undoped silicon glass (USG), and 1,140 nm of HDP PSG. This stack is annealed for 30 minutes at 750°C and then planarized by chemical mechanical polishing (CMP) to a total thickness of 1450 nm (including the field oxide). The intermetal dielectric layer is composed of 1500 nm of HDP oxide and 750 nm of plasma enhanced chemical vapor deposited (PECVD) oxide. After CMP the total thickness is reduced to 1,100 nm. Tungsten (W) plugs are deposited on top of a 15-nm Ti/45-nm TiN barrier. Excess tungsten is removed by CMP. The composition, thickness, and number of interconnect levels are listed in Table 2.1. Technology A has two interconnection levels. A schematic cross section of each level is displayed in Figure 2.2(a). AlCu lines, 690 nm thick, are sandwiched between 20 nm of bottom Ti and 20nm Ti/60nm TiN top antireflective coating. Technology B has four interconnection levels. The first three are identical. Each level consists of 15nm Ti/45nm TiN/690nm AlCu/20nm Ti/60nm TiN [Figure 2.2(b)]. The fourth interconnection level has no Ti on top of AlCu, only 80 nm of TiN [Figure 2.2(c)]. In technology C [fourth row in Table 2.1 and Figure 2.1(b)], the premetal dielectric layer is composed of 150-nm TEOS densified at 750°C for 30 minutes, 150 nm of USG cured at 750°C for 30 minutes, and 1,000 nm of LPCVD PSG annealed for 30 minutes at 750°C. This stack is planarized by CMP to a total thickness of 1,100 nm, including the field oxide. The intermetal dielectric layer consists of 250 nm of PECVD oxide, 400 nm of spin-on glass (SOG) flowable oxide (FOX) cured at 450°C for 30 minutes and 1,300 nm of PECVD oxide. After CMP the total thickness is reduced to 1,100 nm. Tungsten plugs are deposited on top of 20 nm Ti/60 nm TiN and then etched back. Three

Maximum Post-Processing Temperature TiN

35

60 nm 20 nm

Ti AlCu

690 nm

Ti TiN

20 nm Ti/AlCu/Ti/TiN (a) 60 nm 20 nm

Ti AlCu

690 nm 45 nm 15 nm

TiN Ti

Ti/TiN/AlCu/Ti/TiN (b)

TiN

80 nm

AlCu

690 nm 45 nm 15 nm

TiN Ti TiN

Ti/TiN/AlCu/TiN (c) 60 nm 20 nm

Ti

500 nm

AlSiCu TiN Ti

80 nm 30 nm Ti/TiN/AlSiCu/Ti/TiN (d)

TiN

80 nm 500 nm

AlSiCu TiN Ti

80 nm Ti/TiN/AlSiCu/TiN (e)

20 nm

Figure 2.2 Schematic cross sections of different interconnection stacks under investigation: (a) 20 nm Ti/690 nm AlCu/20 nm Ti/60 nm TiN; (b) 15 nm Ti/45 nm TiN/690 nm AlCu/20 nm Ti/60 nm TiN; (c) 15 nm Ti/45 nm TiN/690 nm AlCu/80 nm TiN; (d) 30 nm Ti/80 nm TiN/500 nm AlSiCu/20 nm Ti/60 nm TiN; and (e) 20 nm Ti/80 nm TiN/500 nm AlSiCu/80 nm TiN. (From: [8]. © 2001 IEEE. Reprinted with permission.)

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Table 2.1 Different 0.35-µm CMOS Technologies Considered for Analyzing the Effect of the Annealing Temperature and Period # of CMOS Metal Tech. Layers Metal Type

Metal Thickness

Premetal Dielectric (PMD)

Intermetal Dielectric (IMD)

A

Two

Ti/AlCu/Ti/TiN

20/690/20/60 nm

B

Four

M1, M2, and M3: Ti/TiN/AlCu/Ti/TiN

15/45/690/20/60 nm 100-nm TEOS, 1,500-nm HDP 350-nm HDP USG, oxide, 750-nm 1140-nm HDP PSG PECVD oxide

M4:

15/45/690/80 nm

100-nm TEOS, 1,500-nm HDP 350-nm HDP USG, oxide, 750-nm 1140-nm HDP PSG PECVD oxide

Ti/TiN/AlCu/TiN

C

Three

M1 and M2:

30/80/500/20/60 nm 150-nm TEOS, 150-nm USG, Ti/TiN/AlSiCu/Ti/TiN 1,000-nm LPCVD PSG M3:

250-nm PECVD oxide, 400-nm SOG FOX, 1,300-nm PECVD oxide

20/80/500/80 nm

Ti/TiN/AlSiCu/TiN (Source: [8].)

interconnect levels are used. The first two are similar and are composed of 30 nm Ti/80 nm TiN/500 nm AlSiCu/20 nm Ti/60 nm TiN [Figure 2.2(d)]. The third interconnection level consists of 20 nm Ti/80 nm TiN/500 nm AlSiCu/ 80 nm TiN (no Ti on top [Figure 2.2(e)]). 2.2.3

Measurement Setup

To eliminate the effect of process variation from one wafer to another, it is recommended to use the same wafer for studying the effect of annealing temperature. This can be done by dicing the wafer into four quarters. Keep one quarter as a reference and treat the rest at different temperatures. The annealing period is selected to be representative of an actual MEMS process flow [1], taking into consideration a longer deposition time, to compensate for the lower growth rate associated with the low deposition temperature [9]. After annealing, it is advisable to sinter all the treated samples at 420°C in forming gas to retain hydrogen bonds at the Si-SiO2 interface. A complete analysis of the treated wafers can be

Maximum Post-Processing Temperature

37

done using a data acquisition system, which automatically analyzes all the transistor characteristics. Metal sheet resistance can be measured using a semiconductor parameter analyzer. An impedance/gain-phase analyzer is suitable for measuring accumulation and inversion gate capacitance. To have a better insight of the changes introduced to interconnects by the thermal treatment; it is instructive to inspect a cross section done by focused ion beam (FIB). On the other hand, auger electron spectroscopy (AES) and elemental mapping are useful techniques to determine the diffusion of Al into silicon. As indicated in Section 2.2.1, the front-end is already exposed to relatively high temperatures. Consequently, its characteristics are not expected to change significantly by the annealing temperatures under investigation. On the other hand, the low melting point of Al and the spiking of junctions limit the thermal budget of the backend, and hence, it is expected to define the upper limit for the maximum annealing temperature. Thus, it is convenient to start our analysis by studying the impact of annealing on the backend and then to proceed to the front-end.

2.3 Impact of Annealing on Backend 2.3.1

Impact of Annealing Temperature

To study the effect of the annealing temperature, we start by considering a wafer from CMOS technology A [Table 2.1 and Figure 2.1(a)]. For this technology the two metal layers are identical and have the structure shown schematically in Figure 2.2(a). The effect of varying the annealing temperature from 420°C to 575°C can be investigated by monitoring the changes introduced to 0.8-µm-wide and 300-µm-long lines, as such dimensions are representative for a typical interconnect. By investigating Figure 2.3, it is clear that in general, for all annealing temperatures, the mean sheet resistance of metal one is always higher than that of metal two. Furthermore, for the same metal layer, increasing the annealing temperature is accompanied by an increase in the sheet resistance. To explain these observations, it is instructive to analyze the FIB cross sections displayed in Figure 2.4. For the different annealing temperatures there is a uniform dark layer at the bottom and top parts of the AlCu lines, which does not show any channeling contrast as in the case of Al. This layer represents the reaction between the top and bottom Ti layers and AlCu that results in the formation of TiAl3 [10, 11]. Increasing the annealing temperature enhances this reaction and accordingly, the thickness of the TiAl3 layer is increased, as seen in Figure 2.4(b, c). As AlCu is much more conductive than TiAl3 [12], the net conductive cross section is reduced and accordingly the resistance is increased. The initial higher resistance of metal one can be explained by the fact that it is exposed to higher temperatures during processing the intermetal dielectric layer resulting in more

38

Post-Processing Techniques for Integrated MEMS

Sheet resistance (m Ω /sq )

55

Metal 1

50

45

40 Metal 2 35 400

420

440 460 480 500 Annealing temperature (°C)

520

540

Figure 2.3 Mean sheet resistance of 20 nm Ti/690 nm AlCu/20 nm Ti/60 nm TiN interconnects. Diamonds: metal one; circles: metal two. Horizontal bars indicate the standard deviation. (From: [8]. © 2001 IEEE. Reprinted with permission.)

TiAl3 formation as compared to metal two. Actually, the FIB cross sections can be used to estimate the change in resistance as a function of annealing temperature, by neglecting conduction through TiAl3, TiN, and Ti [12] and considering only the net thickness of the AlCu layer (Figure 2.4). To clarify this point, let us consider the relative change in the conductive cross section of metal two after annealing at 520°C for 30 minutes. In this case, the FIB cross sections in Figure 2.4(a, c) show that the net thickness of AlCu is reduced from 595 nm to 455 nm. This corresponds to a relative change in the resistance of ∆R =

( ρl / (W × 455nm )) − ( ρl / (W × 595nm )) = 31% ( ρl / (W × 595nm ))

where is the resistivity of AlCu, l and W are the length and width, respectively, of the interconnect line. On the other hand, the sheet resistance measurements reported in Figure 2.3 (circles) shows that the relative change in the resistance of metal two after annealing at 520°C is ∆R =

49.7 Ω / Sq .−37 Ω / Sq . = 34% 37 Ω / Sq .

which is close to that estimated from the FIB cross sections, confirming that the formation of TiAl3 is the main phenomena affecting the characteristics of interconnects for annealing temperatures up to 525°C.

Maximum Post-Processing Temperature

500 nm TiAl 3

39

Al grains

595 nm

(a)

500 nm

TiAl 3

540 nm

(b) 500 nm

TiAl 3

455 nm

(c)

Figure 2.4 FIB cross sections of Ti/AlCu/Ti/TiN interconnects [shown schematically in Figure 2.2(a)]: (a) reference lines annealed at 420°C for 20 minutes; and (b, c) lines annealed for 30 minutes at 475°C and 525°C, respectively. (From: [8]. © 2001 IEEE. Reprinted with permission.)

However, if the annealing temperature is further increased—for example, to 575°C—more drastic changes in the interconnects are visible. Figure 2.5 demonstrates the consequences of annealing AlCu bonding pads at 575°C for 30 minutes. By investigating the FIB cross sections in Figure 2.5(a), unusual dark shaped grains are observed, in addition to an irregular layer underneath the pads. The dark spots are identified by AES, and they are found to contain Ti, Si, and less Al [Figure 2.5(b)]. This indicates that significant diffusion of Ti took place from the upper and lower Ti layers and that Si diffused from the intermetal dielectric layer into the interconnection stack. The irregular layer under the bonding pad is an Al-rich region, reflecting significant diffusion of Al

40

Post-Processing Techniques for Integrated MEMS

500 nm Al-Si-Ti Al rich region

Ti/TiN

AlCu

Inter-metal dielectric

Ti (a)

AlCu

Ti/TiN

Ti (b)

Figure 2.5 (a) FIB cross sections of Ti/AlCu/Ti/TiN bonding pads annealed at 575°C for 30 minutes. (b) Distribution of Al, Ti, and Si atoms as determined by AES. (From: [8]. © 2001 IEEE. Reprinted with permission.)

into the intermetal dielectric layer. The reactions, observed at 575°C, might also occur at lower annealing temperatures if the annealing period is increased. This is explained in more detail in the next section. 2.3.2

Impact of Annealing Period

CMOS technologies B and C described in Table 2.1 can be considered as a representative 0.35-µm CMOS process to study the consequences of increasing the annealing period for a fixed annealing temperature. For both technologies, the interconnect stack is one of those displayed in Figure 2.2(b–e). Such stacks give a comprehensive understanding for the effect of the annealing period on the formation of the TiAl3 layer in either AlCu or AlSiCu having Ti or TiN deposited directly on top of them. As the impact of the thermal treatment depends on the line width, it is reasonable to analyze the effect of annealing on lines that are

Maximum Post-Processing Temperature

41

0.7 µm wide and 300 µm long as such dimensions are typical values for interconnects. We start by analyzing the impact of annealing at 475°C for 90 minutes and then the effect of higher temperatures is investigated. The relative change in sheet resistance for different interconnect stacks is reported in Table 2.2. From this table it is clear that for the same annealing period and temperature, the relative change in sheet resistance depends noticeably on the type of interconnect. To better understand such observations, it is instructive to refer to the FIB cross sections displayed in Figure 2.6. Annealing an interconnect stack composed of Ti/TiN/AlCu/Ti/TiN [similar to that in Figure 2.2(b)] at 475°C for 90 minutes, results in a reaction between AlCu and the upper and lower Ti/TiN layers forming TiAl3 with an average thickness of 190 nm [Figure 2.6(a)]. Comparing Figures 2.4(b) and 2.6(a) shows that the total thickness of TiAl3 increased by increasing the annealing period (notice that the net thickness of AlCu is reduced from 540 nm [Figure 2.4(b)] to 500 nm [Figure 2.6(a)] in spite of removing the Ti layer underneath AlCu [Figure 2.6(a)]. Also, it is clear that for longer annealing periods, the TiAl3 layer extends deeper into the interconnect layer due to the increased diffusivity. The increased thickness of TiAl3 agrees with the higher relative change in resistance associated with increasing the annealing period observed in Table 2.2. On the other hand, changing the Al-based interconnect layer from AlCu [Figure 2.6(a)] to AlSiCu [Figure 2.6(b)], reduces the total thickness of TiAl3 from 190 nm to 140 nm, for the same annealing conditions. This can be explained by the retardation in the formation of TiAl3 in AlSiCu by the presence of silicon [13]. Moreover, the reaction with the lower TiN layer is more pronounced in AlCu compared to AlSiCu [14, 15]. It should be noted that the higher relative change in sheet resistance reported for AlSiCu (third row in Table 2.2), as compared to AlCu (second row in Table 2.2), is due to its thinner cross section (500 nm instead of 690 nm). Thus, for the same thickness, the relative change in resistance of AlSiCu is expected to be at least 10% lower than that of AlCu. Table 2.2 Effect of Aluminum Composition, Thickness of Aluminum Layers and Type of Layers on Top and Underneath the Metal Lines on the Measured Relative Change in the Sheet Resistance Type of Interconnection

Thickness of Metal Layers

Relative Change in Sheet Resistance

Ti/TiN/AlCu/Ti/TiN

15/45/690/20/60 nm

16%

Ti/TiN/AlSiCu/Ti/TiN

30/80/500/20/60 nm

18.4%

Ti/TiN/AlSiCu/TiN

20/80/500/80 nm

5%

Ti/TiN/AlCu/TiN

15/45/690/80 nm

10.4%

Note: Annealing temperature is fixed at 475°C for 90 minutes. ( Source: [8].)

42

Post-Processing Techniques for Integrated MEMS

500 nm

Ti/TiN/AlCu/Ti/TiN

500 nm

TiAl 3 (a) 500 nm

Ti/TiN/AlSiCu/Ti/TiN

360 nm

TiAl 3 (b)

500 nm Ti/TiN/AlCu/TiN

615 nm

TiAl 3

(c)

Figure 2.6 FIB cross sections of interconnections annealed at 475°C for 90 minutes: (a) 15 nm Ti/45 nm TiN/690 nm AlCu/20 nm Ti/60 nm TiN; (b) 30 nm Ti/80 nm TiN/500 nm AlSiCu/20 nm Ti/60 nm TiN; and (c) 15 nm Ti/45 nm TiN/690 nm AlCu/80 nm TiN. (From: [8]. © 2001 IEEE. Reprinted with permission.)

It is also interesting to note that removing the upper Ti layer noticeably reduces the relative change in sheet resistance as demonstrated by the last two rows in Table 2.2. The slight increase in the resistance of AlSiCu-based interconnect lines is probably due to the diffusion of Ti through TiN into the AlSiCu resulting in the formation of a ternary compound of Al-Si-Ti during annealing [16]. Alternatively, the resistance increase could be due to diffused-in Ti, as one atomic percent of Ti results in an increase in the resistivity of AlSiCu

Maximum Post-Processing Temperature

43

by 5.1 µΩ.cm [17]. Thus, an increase in resistivity from 3.3 µΩ.cm (before annealing) to 3.5 µΩ.cm (after annealing at 475°C for 90 minutes) corresponds to a diffusion of 0.03 atomic percent of Ti. On the other hand, the higher relative change in sheet resistance of the Ti/TiN/AlCu/TiN interconnect is due to the reaction of AlCu with the lower TiN layer [Figure 2.6(c)]. Notice also from Figure 2.6(c) that there is no visible reaction layer between AlCu and the upper TiN layer. Based on the above discussion, it is clear that using AlSiCu is more favored than using AlCu, as the formation of TiAl3 is much slower, and accordingly, it can stand higher annealing temperatures. Thus, to determine the maximum annealing temperature that can be applied for 90 minutes, it is recommended to consider a CMOS technology having a flow similar to that of Technology C described in Table 2.1 as the interconnect stacks are AlSiCu. The effect of different annealing temperature on the interconnect stacks is demonstrated in Figure 2.7. From this figure it is clear that avoiding direct contact between Ti and AlSiCu significantly reduces the relative change in resistance, even for annealing temperatures up to 525°C (circles in Figure 2.7). On the other hand, annealing Ti/TiN/AlSiCu/Ti/TiN for 90 minutes at 525°C results in a 50% relative change in sheet resistance (diamonds in Figure 2.7). This high resistance increase is caused by the formation of TiAl3 along certain grain boundaries and thus narrowing the effective cross section of the Al lines. This phenomenon is more pronounced at 525°C or 550°C as clear from the FIB cross sections in 120

Sheet resistance (mΩ/sq )

110 Ti/TiN/AlSiCu/Ti/TiN 100 90 80 70 Ti/TiN/AlSiCu/TiN 60 400

420

440 460 480 500 Annealing temperature (°C)

520

540

Figure 2.7 Effect of annealing temperature on sheet resistance of 30 nm Ti/80 nm TiN/500 nm AlSiCu/20 nm Ti/60 nm TiN (diamonds) or 20 nm Ti/80 nm TiN/500 nm AlSiCu/80 nm TiN (circles). Annealing period has been fixed to 90 minutes. Horizontal bars indicate the standard deviation. (From: [8]. © 2001 IEEE. Reprinted with permission.)

44

Post-Processing Techniques for Integrated MEMS

Figure 2.8. It is possible that the texture of Al has an effect on the amount of TiAl3 reacting along the grain boundaries. Consequently, the amount of resistance increase is expected to depend on processing. The impact of annealing temperature on tungsten plugs resistance can be checked by measuring the contact resistance of Kelvin structures [18] using four-point probe. Figure 2.9 displays the measured mean value of the contact resistance, as a function of annealing temperature for 90 minutes. From the figure, it can be seen that the contact resistance is nearly unaffected by annealing temperatures up to 500°C for 90 minutes. Increasing the annealing temperature to 525°C increases the contact resistance by nearly 5%. At this point, we would like to note that the impact of the annealing temperature on interconnect reliability should be addressed as well. It is found that the electromigration lifetime of Al alloy conductors can be significantly increased by rapid thermal annealing for 5 to 30 seconds at a peak temperature between 520°C and 580°C [19]. Moreover, it is demonstrated that improved electromigration behavior can be achieved by annealing Al and a transition metal (such as Ti) at 500°C for a long time (∼6 hours) to form an intermetallic compound (such as TiAl3) [20]. This indicates that the interconnection reliability most likely will not be the limiting factor for increasing the CMOS post-processing temperature. However, as with all process changes, it is necessary to evaluate the effect of post-processing on the interconnect reliability for the 500 nm

TiAl

Ti/TiN/AlSiCu/Ti/TiN

3

Al Grains (a) 500 nm

TiAl 3

Al Grains

Ti/TiN/AlSiCu/Ti/TiN (b)

Figure 2.8 FIB cross sections of Ti/TiN/AlSiCu/Ti/TiN, annealed for 90 minutes at (a) 525°C and (b) 550°C. (From: [8]. © 2001 IEEE. Reprinted with permission.)

Maximum Post-Processing Temperature

45

2.6

Contact resistance (Ω)

2.4 2.2 2 1.8 1.6 1.4 400

420

440 460 480 500 Annealing temperature (°C)

520

540

Figure 2.9 Effect of annealing temperature on mean value of contact resistance between metal lines and N+ active (diamonds), P+ active (circles), N+ doped poly Si (squares), and P+ doped poly Si (stars). Horizontal bars indicate the standard deviation. (From: [8]. © 2001 IEEE. Reprinted with permission.)

technology of choice. For an overview of the different techniques for interconnect reliability evaluation and appropriate test structures, the reader is referred to [21, 22]. Based on the above analysis, it is proven that the main impact of annealing temperature on the backend is an increase in interconnection resistance due to the reaction between Al and the Ti/TiN barrier. Consequently, if the estimated resistance increase is accepted by the circuit designer, annealing at 500°C or 525°C, for 90 minutes, is possible from the backend point of view. In the next section, we investigate the effect of annealing on the front-end.

2.4 Impact of Annealing Temperature on the Front-End It can be inferred from the analysis presented in the previous section that the backend of a typical 0.35-µm CMOS technology can withstand temperatures as high as 520°C for 90 minutes. The main objective of this section is to check the impact of such thermal budget on the front-end characteristics. The consequences of the thermal treatment can be investigated by inspecting the transistor characteristics, silicide quality, and leakage currents. Table 2.3 shows the effect of annealing for 90 minutes at different temperatures on relevant transistor parameters. The nominal channel length for the investigated technology is 0.35 µm. The threshold voltages of the 0.35-µm devices in the linear and saturation region are reported in the first two rows of Table 2.3, and they are measured at a drain to source voltage of 0.1V and 3.3V, respectively. It is clear that the

46

Post-Processing Techniques for Integrated MEMS

Table 2.3 Effect of the Annealing Temperature on the Front End of CMOS Technology C (Table 2.1)

Annealing Temperature Standard

475°C

500°C

525°C

Threshold voltage (linear)

0.681V ± 8.7 mV

0.672V ± 4.3 mV

0.677V ± 6.8 mV

0.662V ± 6 mV

Threshold voltage (saturation)

0.58V ± 14.7 mV

0.58V ± 4 mV

0.59V ± 5 mV

0.57V ± 12.8 mV

% gate depletion 11.86% of PMOST

12.9%

12.72%

11.52%

% gate depletion 14.32% of NMOST

13.44%

12.79%

14.12%

< 1 pA

< 1 pA

< 1 pA

3.75 mA ± 60 µA

3.89 mA ± 71 µA

Transistor leakage current

< 1 pA

Drive current

3.77 mA ± 110 µA 3.84 mA ± 30 µA

Channel conductivity (A/V2)

±

±

±

±

Subthreshold slope

78.58 mV ± 0.65 mV

78.65 mV ± 0.21 mV

79.03 mV ± 0.24 mV

78.8 mV ± 0.39 mV

Maximum bulk current

13 mA ± 1.2 µA

13 mA ± 0.68 µA

12 mA ± 0.59 µA

14 mA ± 1.2 µA

Multiplication factor

0.01002 ±

0.01044 ±

0.00964 ±

0.01035 ±

51.8 V ± 0.9 V

53.8 V ± 1.9 V

55.8 V ± 2.5 V

2.18543 Ω ± 0.033 Ω

2.16695 Ω ± 0.01 Ω

2.17413 Ω ± 0.033 Ω

1.27 kΩ ± 19.8 Ω

1.27 kΩ ± 34.4 Ω

1.31 kΩ ± 63.8 Ω

∼1 pA

∼1 pA

∼1 pA

Threshold 40.17 V ± 2.2 V voltage of NFLDT Resistance of N+ doped Van der Pauw structure [15]

2.185 Ω ± 0.03986 Ω

Line resistance 1.34 kΩ ± 65.8 Ω of N+ doped poly Si silicided lines Diode leakage current

∼1 pA

Note: The annealing period has been fixed to 90 minutes. ( Source: [8].)

maximum relative change in the threshold voltage for the highest annealing temperature is less than 3%. Percentage gate depletion is an important

Maximum Post-Processing Temperature

47

parameter as it indicates the impact of annealing temperature on dopant deactivation [23]. This parameter is reported in the third and fourth rows of Table 2.3 for PMOS and NMOS transistors. We notice that there is no clear effect for the annealing temperature on gate depletion. The variation in the measured values is within the normal spread over the wafer. Transistor leakage current measured at a drain to source voltage of 3.63V seems not to be affected by annealing temperatures up to 500°C. A slight increase is observed at 525°C, but still the measured values are acceptable. The values reported for drive current, channel conductivity, subthreshold slope, maximum bulk current, and multiplication factor, measured at a drain to source voltage of 3.3V and zero bulk voltage, shows that these parameters are nearly independent of annealing temperatures up to 525°C. The threshold voltage of N type field transistors can be used as an indicator for the impact of annealing on the quality of the premetal dielectric layer [24]. The N+ active areas of these transistors are spaced by 0.7 µm and the width of the transistor is 1 mm. The threshold voltage is defined as the gate voltage required to increase the drain current up to 100 pA per µm width. The fourth row from the bottom of Table 2.3 shows that the threshold voltage is increased with increasing the annealing temperatures, which is favorable. The impact of annealing temperature on the quality of titanium silicide can be checked by measuring the resistance of N+ doped Van der Pauw structures [18], and 250-µm-long, 0.35-µm-wide N+ doped silicided silicon and poly Si lines. Some representative measurements are shown in Table 2.3, and no effect of annealing can be observed (notice also that the standard deviation in the measured data is less than 5%). Finally, the last row of Table 2.3 shows that the diode leakage current of N+ doped active regions having an area of 12 × 104 µm2 and a perimeter of 1,400 is almost unaffected by annealing. In addition to the presented results, all other CMOS parameters, for different channel length, do not show any significant change confirming that the front-end is almost unaffected by temperatures as high as 520°C for 90 minutes.

2.5 Summary and Conclusions This chapter investigates the impact of increasing the post-processing temperature on standard 0.35-µm CMOS wafers with Al-based interconnections and tungsten plugs. It is demonstrated that it is possible to increase the temperature up to 525°C without introducing significant changes in the standard characteristics. The front-end is nearly unaffected, whereas for the backend, an increase in the interconnect resistance was observed. This increase depends on the type of Al alloy and the presence of Ti/TiN layers on top or below the Al layer. For the same layer thickness and interconnect stack structure, the relative change in

48

Post-Processing Techniques for Integrated MEMS

resistance is expected to increase when AlCu is used instead of AlSiCu, as Si retards the reaction with Ti and TiN. As a rule of thumb, annealing at 525°C for 90 minutes results in a relative change in sheet resistance between 50% and 60% for Ti/TiN/AlSiCu/Ti/TiN or Ti/TiN/AlCu/Ti/TiN interconnects. Removing the top Ti layer reduces the relative change in resistance to 25% or lower depending on the type of Al alloy. It should be noted that the exact changes depend on the type of technology and thus might differ from one foundry to another. Recent research at UC Berkeley showed that, for a 0.25-µm CMOS process, the limiting factor is the increase in the via resistance, which is the contact between different metal layers. In this case the maximum post-processing temperature would be 475°C for 30 minutes [25]. In conclusion, it is possible to post-process MEMS on top of standard 0.35-µm CMOS wafers at temperatures up to 525°C for periods up to 90 minutes if circuit design is still possible with the increased sheet resistance (which depends on the specific type of Al alloy and interconnection stack used by the CMOS technology) and if the reliability is found to be good enough. The next step would be to measure the impact of annealing on hot carrier degradation and gate oxide reliability. This issue is beyond the scope of this book as it is expected to depend on the type of post-processed device, and optimization of these parameters is expected to be device dependent.

References [1]

Sedky, S., et al., “IR Bolometers Made of Polycrystalline Silicon Germanium,” Sensors and Actuators A, Vol. 66, No. 1–3, 1998, pp. 193–199.

[2]

Sedky, S., et al., “Characterization and Optimization of Infra Red Poly SiGe Bolometers,” IEEE Transactions on Electron Devices, Vol. 46, No. 4, 1999, pp. 675–682.

[3]

Huikai, X., et al., “Design and Fabrication of an Integrated CMOS-MEMS 3-Axis Accelerometer,” 2003 Nanotechnology Conference and Trade Show, Vol. 1, 2003, pp. 292–295.

[4]

Huikai, X., and G. Fedder, “Vertical Comb-Finger Capacitive Actuation and Sensing for CMOS-MEMS,” Sensors and Actuators, A: Physical, Vol. 95, No. 2–3, 2002, pp. 212–221.

[5]

Jahnes, C., et al., “Simultaneous Fabrication of RF MEMS Switches and Resonators Using Copper-Based CMOS Interconnect Manufacturing Methods,” Proceedings of the 17th IEEE International Conference on Micro Electro Mechanical Systems (MEMS), 2004, pp. 789–792.

[6]

Franke, A., et al., “Polycrystalline Silicon Germanium Films for Integrated Microsystems,” Journal of Microelectromechanical Systems, Vol. 12, No. 2, 2003, pp. 160–171.

[7]

Franke, A., et al., “Post-CMOS Integration of Germanium Microstructures,” 12th IEEE International Conference on Micro Electro Mechanical Systems, MEMS’99, Orlando, FL, 1999, pp. 630–637.

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49

[8] Sedky, S., et al., “Experimental Determination of the Maximum Post Process Annealing Temperature for Standard CMOS Wafers,” IEEE Transactions on Electron Devices, Vol. 48, No. 2, 2001, pp. 377–385. [9] Sedky, S., et al., “Effect of In-Situ Boron Doping on Properties of Silicon Germanium Films Deposited by CVD at 400°C,” Journal of Materials Research, Vol. 16, No. 9, 2001, pp. 2607–2612. [10] Nahar, R., N. Devashrayee, and W. S. Khokle, “Diffusivity of Al in Ti and the Effect of Si Doping for Very Large Scale Integrated Circuit Interconnect Metallization,” Journal of Vacuum Science Technology, Vol. B6, 1988, p. 880. [11] Zhao, X., F. C. T. So, and M. A. Nicolet, “TiAl3 Formation by Furnace Annealing of Ti/Al Bilayers and the Effect of Impurities,” Journal of Applied Physics, Vol. 63, No. 8, 1988, pp. 2800–2807. [12] Wondergem, H., A. Heger, and J. J. Van den Broek, “Determination of W-Tl/Al Thin-Film Interaction by Sheet Resistance Measurement,” Thin Solid Films, Vol. 249, No. 1, 1994, p. 6. [13] Koubuchi, Y., et al., “Effects of Si on Electromigration of Al-Cu-Si/TiN Layered Metallization,” Journal of Vacuum Science Technology, Vol. B (10), No. 1, 1992, pp. 143–148. [14] Sobue, S., et al., “Dependence of Diffusion Barrier Properties in Microstructure of Reactively Sputtered TiN Films in Al Alloy/TiN/Ti/Si System,” Applied Surface Science, Vols. 117–118, June 2, 1997, pp. 308–311. [15] Lee, W., et al., “Texture and Sheet Resistance of Al Alloy Thin Films on Ti and TiN Thin Films,” Journal of Materials Science: Materials in Electronics, Vol. 15, No. 1, January 2004, pp. 9–13. [16] Mandl, M., H. Hoffmann, and P. Kucher, “Diffusion Barrier Properties of Ti/TiN Investigated by Transmission Electron Microscopy,” Journal of Applied Physics, Vol. 68, No. 5, 1990, pp. 212–217. [17] Hatch, J., Aluminum Properties and Physical Metallurgy, Metal Parks, OH: American Society for Metals, 1984, p. 29. [18] El-Kareh, B., and R. J. Bombard, Introduction to VLSI Silicon Devices, Physics, Technology, and Characterization, Chapter 1, Boston: Kluwer Academic Publishers, 1986. [19] Janet, T., and Van de Ven Everhardus, “Formation of Electromigration Resistant Aluminum Alloy Conductors,” European Patent # EP 0161026 A2 19851113. [20] James, H., and P. Ho, “Intermetallic Compound Layer in Thin Films for Improved Electromigration Resistance,” U.S. Patent # US 4017890. [21] Foley, S., J. Molyneaux, and A. Mathewson, “An Evaluation of Test Methods for the Detection and Control of Interconnect Reliability,” IEEE Transactions on Semiconductor Manufacturing, Vol. 13, No. 2, May 2000, pp. 127–135. [22] Runnels, S. R., et al., “Advanced Experimental and Computational Tools for Robust Evaluation of On-Chip Interconnect Reliability,” IEEE Transactions on Semiconductor Manufacturing, Vol. 15, No. 3, August 2002, pp. 355–365. [23] Kamins, T., Polycrystalline Silicon for Integrated Circuit Applications, Boston: Kluwer Academic Publications, 1988.

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[24] Laker, K. R., and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems, New York: McGraw-Hill, 1994. [25] Takeuchi, H., et al., “Thermal Budget Limits of Quarter-Micrometer Foundry CMOS for Post-Processing MEMS Devices,” IEEE Transactions on Electron Devices, Vol. 52, No. 9, 2005, pp. 2081–2086

3 MEMS Materials 3.1 Introduction As previously discussed in Chapter 1, MEMS is used in a broad range of applications. Accordingly, the selection criteria of the MEMS structural layer depend strongly on the function performed by each device and the operating environment. If we consider thermal infrared imagers, the structural layers should have high thermal insulation and should possess a physical property that is highly sensitive to the absorbed radiation. Furthermore, the structural material should provide good electrical contact to the substrate. On the other hand, if we consider MEMS mechanical resonators and switches, the structural layer should have high quality factor and low electrical resistivity to reduce insertion loses. For micromirrors, the structural layer should have high reflectivity to optimize the device functionality. Other applications might require that the electrical conductivity of the material vary by orders of magnitude from one part of the device to another, and in this case the use of a semiconductor material is mandatory. In some cases, the material is required to have good magnetic, piezoresistive or piezoelectric properties. Furthermore, the optical properties of the material might be a critical issue for specific applications. In addition to the requirements of each specific application, there are common properties that should be always satisfied for most MEMS materials, such as the constraints imposed on mean stress and stress gradient. As the majority of MEMS devices consist of a suspended structure, the structural layer should ideally have zero stress and stress gradient or practically low tensile stress with the upper layers more tensile than the bottom ones to avoid bending towards the substrate and consequently stiction.

51

52

Post-Processing Techniques for Integrated MEMS

In general, there is a wide variety of materials having physical properties suitable for MEMS devices. The most popular materials are those compatible with CMOS technology such as polycrystalline silicon [1], polycrystalline silicon germanium [2–4], aluminum [5, 6], copper [7, 8], tantalum [9], silicon dioxide [10, 11], silicon carbide [12], silicon nitride [13], and porous silicon [14, 15]. In addition, there are new materials used for optical MEMS such as sol-gel [16], superplastic alloys such as Al-78ZN [17], amorphous LaAlNi [18], and ZrAlCu [19]. Since the main objective of this book is to focus on MEMS post-processing on top of standard prefabricated driving electronics, the discussion in this chapter will be limited to materials commonly used for MEMS and that can be processed at temperatures compatible with the standard CMOS backend. In the previous chapter, it was demonstrated that the maximum post-processing temperature for standard CMOS wafers varies between 370°C and 520°C depending on the type of metallization and fabrication technology. Accordingly, it is instructive to consider materials prepared by low thermal budget techniques that provide conformal depositions and good step coverage. Sputtering yields good step coverage at relatively low temperatures (< 200°C), but in general the deposition rate is relatively low, and hence, the thickness of the MEMS structure is limited to few microns. Furthermore, it is demonstrated in the following sections that the mechanical and electrical properties of the deposited films depend strongly on the sputtering pressure and power. To deposit thicker films (> 10 µm) and to define devices having high aspect ratio (> 50:1), electroplating and electroless plating would be the optimal choice. On the other hand, for semiconductor and dielectric thin films, the deposition thermal budget is significantly reduced by using plasma enhanced chemical vapor desposition (PECVD), as it increases the deposition rate by one order of magnitude compared to the conventional low pressure chemical vapor deposition (LPCVD). The main drawback of this deposition technique is that the deposited layers are in general amorphous, and also the step coverage is relatively poor. This chapter starts by giving an overview of the factors affecting mean stress and stress gradient in thin films. The effect of the deposition conditions on the physical properties of thin metal films is discussed in Section 3.3. Section 3.4 highlights the limitations of using semiconductor materials for MEMS post-processing.

3.2 Stress and Stress Gradient in Thin Films Surface micromachined MEMS require the deposition of thin films on top of the substrate. The mechanical properties of such films depend strongly on the deposition techniques (either sputtering or evaporation or chemical vapor

MEMS Materials

53

deposition), and in general they deviate noticeably from the bulk properties as they depend on the grain microstructure and defect density. In general, stress in thin films is the sum of thermal and intrinsic stress. Thermal stress is caused by a difference in the expansion coefficient of the substrate and of the thin film. Intrinsic stress has two components. The first originates from volume contraction associated with crystallization and is tensile. The second component is compressive, and it is due to the existence of a preferred growth orientation [20], disorder at the grain boundary [21], effects related to different deposition rates [22], or the incorporation of impurity atoms [23]. It is verified that the dominant stress component is the intrinsic one [24]. Accordingly, stress depends on the deposition conditions and the annealing temperature. For surface micromachined structures a high compressive mean stress results in buckling; high tensile stress might cause cracks or fractures in the suspended structures. Ideally, the MEMS structural material is desired to have zero mean stress, or practically low tensile mean stress. Stress can be measured by determining the bow of the wafer before and after depositing the film, or by implementing special structures on the substrate [25, 26]. Stress gradient originates from the variation of stress normal to the growth surface, which is mainly due to the variation of grain microstructure and defect density with thickness. This results in an out-of-plane deflection, which dramatically affects the functionality of surface micromachined structures. Stress gradient can be determined qualitatively by investigating the profile of surface micromachined cantilevers by scanning electron microscopy. If the cantilevers are bending upwards, this means that the upper layers are more tensile than the lower ones. On the other hand, if the upper layers are more compressive than the bottom ones, the cantilevers will bend downwards. To have a quantitative estimate for stress gradient, the bending profile of surface micromachined cantilevers can be determined by scanning the surface of the cantilevers by optical, noncontact techniques having a reasonable vertical resolution (∼5 nm) and intermediate lateral resolution (∼1 µm).

3.3 Metals as a MEMS Structural Layer Metals are commonly used as a MEMS structural material for a wide variety of applications due to their high electrical conductivity, ferromagnetic properties, optical reflectivity, hardness, low electrical noise, low deposition temperature, and relatively simple deposition techniques. The main objective of this section is to highlight the attractive properties of some metals such as tantalum, aluminum, gold, platinum, nickel, and copper for micromachining applications. The effect of the deposition technique on the mechanical and electrical properties of thin metal films is reviewed.

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3.3.1

Post-Processing Techniques for Integrated MEMS

Tantalum as an Attractive MEMS Material

RF-MEMS devices are an emerging class of MEMS devices used for RF signal processing in telecommunication applications. For example, metal surface micromachined switches are a promising alternative for current solid-state switches or mechanical reed relays due to their potential for miniaturization, integration, and improved performance. RF-MEMS switches normally consist of a metal bridge or cantilever electrode, which can be pulled in towards a bottom electrode by electrostatic forces [27]. The bridge material is often chosen to be Al or an Al-alloy because of its low resistivity [28]. During each switch cycle the metal top electrode goes through a mechanical stress cycle. These successive stress cycles might lead to reliability problems such as fatigue and/or creep. This is certainly the case for Al, which is known to have a low creep resistance [29]. Several alternatives have been investigated such as alloying Al with other materials [30], or replacing Al with metals having better mechanical properties, specifically low creep, such as tungsten (W) or tantalum (Ta). Especially high melting point materials are interesting alternatives as the creep resistance is expected to increase with the melting point [31]. If we consider surface micromachined RF switches, the pull in voltage and sheet resistance are two important parameters that should be taken into consideration while selecting the switch material. In general, the pull in voltage depends on mean stress, lateral dimensions, layer thickness, and Young’s modulus. In case of stress-free films, a material having a low Young’s modulus is preferred for low pull-in voltage. As W is known to have high intrinsic stress [32] and a higher Young’s modulus compared to Ta [33], it is instructive to consider Ta as a structural material for surface micromachining applications. In general, stress and resistivity in sputtered metals can be tuned by adjusting sputtering power, pressure, and target-to-substrate distance. Figure 3.1 gives an overview of the dependence of stress in sputtered tantalum on the sputtering pressure. By investigating this figure we notice that increasing the sputtering pressure from 0.8 Pa to 1 Pa, at a sputtering power of 300W, changes the mean stress from highly compressive to relatively low tensile. However, the resistivity is slightly increased. Further increase in the sputtering pressure results in an increase in resistivity and a huge nonuniformity across the wafer (as clear from the horizontal bars). Thus, the optimal sputtering pressure would be 1 Pa. It is interesting to note that the abrupt change in stress as a function of sputtering pressure corresponds to a phase transition of the film structure from cubic alpha to tetragonal beta [34]. The corresponding resistivity and stress is 170 µΩ.cm and 120 MPa tensile, respectively, in agreement with values reported for tetragonal beta phase. The effect of sputtering power, at a sputtering pressure of 1 Pa, is illustrated in Figure 3.2. For low sputtering powers, the uniformity across the wafer is poor (as clear from the variance in measured resistivity). Increasing the sputtering power results in a slight increase in resistivity

55

400

3

200

2.5 2

0 –200

1.5

–400

1

–600

0.5

–800 0.5

1

1.5 2 2.5 Sputtering pressure (Pa)

3

3.5

Resistivity (mΩ.cm)

Mean stress (MPa)

MEMS Materials

0

Figure 3.1 Effect of sputtering pressure on stress (diamonds) and resistivity (squares) of Ta sputtered on oxidized silicon wafers at 300W and 80-mm spacing between target and substrate. Horizontal bars indicate the standard deviation. (From: [9].)

1200 0.24 1000

Mean stress (MPa)

0.2

600

0.18

400 200

0.16

0

0.14

–200

0.12

–400 50

Resistivity (mΩ.cm)

0.22

800

0.1 100

150

200 250 300 Sputtering power (W)

350

400

450

Figure 3.2 Effect of sputtering power on stress (diamonds) and resistivity (squares) of Ta sputtered on oxidized silicon wafers at 1 Pa and 80-mm spacing between target and substrate. Horizontal bars indicate the standard deviation. (Data is based on experiments performed at IMEC, Belgium.)

coupled with improved uniformity. As we are interested in low tensile stress, it would be convenient to fix the sputtering power at 300W. 3.3.1.1 Mean Stress and Stress Gradient in Tantalum

In the previous section it was demonstrated that minimum mean tensile stress, coupled with relatively low resistivity, can be realized by sputtering Ta at 300W and 1 Pa. In this section we investigate the possibility of further reducing the

56

Post-Processing Techniques for Integrated MEMS 200 150 Ta

Stress (MPa)

100 50

AlSi 0

–50 –100

0

50

100

150

200

250

300

350

Annealing temperature (°C)

Figure 3.3

Effect of annealing temperature on mean stress of Ta (diamonds) sputtered at 300W or AlSi (squares) sputtered at 1,500W. Annealing period has been fixed to 12 hours. (From: [9].)

mean stress by annealing. Figure 3.3 shows that the mean stress of Ta slightly decreases by annealing for 12 hours at 100°C or 200°C. Increasing the annealing temperature to 300°C results in a dramatic change in stress (stress changes from tensile to compressive). For comparison, stress data of AlSi layers sputtered at 1,500W, and 0.8 Pa are displayed (squares in Figure 3.3 [9]). Such conditions yield a low tensile stress of +60 MPa for a 1−µm-thick AlSi film. It is interesting to note that the stress in AlSi has a different dependence on annealing temperature compared to Ta, especially at low temperatures (compare squares and diamonds in Figure 3.3). The tensile stress increase of AlSi is probably caused by the relaxation of stress at the annealing temperature, followed by a tensile stress build-up during cool-down due to the difference in thermal expansion coefficient between the Al film and the substrate. On the other hand, Figure 3.4 shows that the electrical resistivity of Ta is almost a factor of 50 higher than that of AlSi, and in general annealing temperatures as high as 300°C do not have a noticeable influence on electrical conductivity even for long time intervals. To have an idea about stress gradient, it is instructive to investigate the bending profile of surface micromachined cantilevers realized by 1-µm-thick Ta. Figure 3.5 shows that these cantilevers are bending upwards, indicating that the upper layers are more tensile than the lower ones. At this point it should be noted that the advantage of using Ta as compared to AlSi is that the stress is not sensitive to temperature variations. As we are considering low temperature processing, photoresist can be used as a sacrificial layer. In this case releasing the structures is done in oxygen plasma, which might imply heating to 200°C for a relatively long period (up to 90 minutes). Such a release process results in a

MEMS Materials

57

500

Resistivity (µΩ.cm)

200 100 Ta

50 20 AlSi

10 5 2

0

50

100 150 200 250 Annealing temperature (°C)

300

350

Figure 3.4 Effect of annealing temperature on resistivity of Ta (diamonds) sputtered at 300W or AlSi (squares) sputtered at 1,500W. Annealing period has been fixed to 12 hours. (Data is based on experiments performed at IMEC, Belgium.)

Figure 3.5 Surface micromachined cantilevers having a length varying from 1 mm to 100 µm, realized by 1-µm-thick Ta sputtered at 600W and 1.4 Pa. (From: [9].)

noticeable change in the AlSi mean stress, as it was observed that stress increases to 180 MPa after the release process. Stress in Ta is almost unaffected. This confirms that Ta is less sensitive to thermal processing (see also Figure 3.3). AlSi also has a larger stress gradient after release compared to Ta. This is reflected in

58

Post-Processing Techniques for Integrated MEMS

the sharper bending of surface micromachined AlSi cantilevers compared to Ta cantilevers, as shown in Figure 3.6. In general, a wide variety of surface micromachining applications require flat suspended membranes, and thus it is interesting to check the stability of such structures realized by sputtered Ta. Figure 3.7 shows that 1-µm-thick Ta clamped-clamped beams, 50 or 100 µm wide and 200 µm long are completely flat and suspended. As Ta seems to be a good structural MEMS material, the only drawback of using Ta compared to Al is its high resistivity, which is, for example, not suitable for RF-MEMS switches. To overcome this problem, it might be convenient to combine the good electrical properties of Al with the good mechanical properties of Ta by building a stack of the two materials. The SEM image displayed in Figure 3.8 shows that the central part of bridges, 50 µm wide and 200 µm long, realized by 1-µm Ta/1-µm AlSi stack is bending downwards. This is due to the differences in stress between AlSi and Ta, leading to a stress gradient across the thickness. Such bending can be completely eliminated if the Ta/AlSi stack is sputtered on top of AlSi as shown in Figure 3.9. In this case, the sheet resistance of this stack is 27 mΩ/sq., whereas its mean stress, measured before etching the sacrificial layer, is 180 MPa tensile [9]. This stress increases to 350 MPa due to the release process. It should be noted that the stack thickness together with its relatively high mean stress is expected to result in a significant increase of the RF-switch actuation voltage. Thus, it is instructive to investigate the possibility of reducing the total stack thickness to 1 µm. In this case, the mean stress of a 0.3-µm AlSi/0.3-µm Ta/0.3-µm AlSi stack is 380 MPa

Figure 3.6 Surface micromachined cantilevers having a length varying from 1 mm to 100 µm, realized by 1-µm-thick AlSi sputtered at 1,500W and 0.8 Pa. (From: [9].)

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59

Figure 3.7 Surface micromachined bridges, 200 µm long and 50 or 100 µm wide, realized by 1-µm-thick Ta sputtered at 600W and 1.4 Pa. (From: [9].)

Figure 3.8 Surface micromachined bridges realized by a stack of 1-µm Ta/1-µm AlSi. (From: [9].)

tensile and its sheet resistance is 50 mΩ/sq. Wide bridges (> 50 µm) realized by this stack bend downwards at the sides as illustrated in Figure 3.10. This is due to the increased stress gradient associated with decreasing thickness. This phenomenon is less pronounced in narrow beams [∼10 µm wide (Figure 3.10)] as they are stiffer along the width direction.

60

Post-Processing Techniques for Integrated MEMS

Figure 3.9 Surface micromachined bridges, 100 µm long realized by a 1-µm AlSi/1-µm Ta/1-µm AlSi stack. (From: [9].)

Narrow beams

Figure 3.10 Surface micromachined bridges realized by a 0.3-µm AlSi/0.3-µm Ta/0.3-µm AlSi stack. (From: [9].)

MEMS Materials 3.3.2

61

Nickel for MEMS Applications

Nickel is used in a wide variety of MEMS applications such as hearing aids [35], active catheters [36], microfluidic devices [37], and microlenses [38]. Compared to silicon, nickel is less brittle and more flexible, and it has good electrical conductivity. Its good optical properties enable the realization of smooth mirrors used in optical applications. In addition, its magnetic properties make it a suitable media for magnetic recording [39] or as magnetoresistive heads [40]. Furthermore, it can be easily prepared at a CMOS backend compatible temperature. Nickel is a ferromagnetic material with face centered cubic (FCC) crystalline structure that can be deposited by evaporation [41], electrodeposition [42], or sputtering [43]. In general, the grain microstructure and accordingly, the electrical and magnetic properties of Ni thin films depend on the sputtering pressure and temperature, substrate type, and orientation. Reducing the sputtering pressure and increasing the sputtering temperature result in a dense microstructure [44, 45] having low density intergranular voiding, which is resistant to oxidation effects. Figure 3.11 shows that such high-density structure has high saturation magnetism [43], whereas, the resistivity is low, as shown in Figure 3.12. Increasing the sputtering power also increases the film density as can be inferred from the reduced resistivity, and accordingly, saturation magnetism is also increased. At this point, we would like to highlight the effect of the substrate type on the structural properties of sputtered nickel. It was found that sputtering thin nickel films (< 110 nm) on glass substrates almost has no texture. Increasing the 550

3

Magnetization (emu/cm )

500 2,000W

450 400 350

500W 300 250

3

5

10 Argon pressure (mTorr)

20

30

Figure 3.11 Dependence of nickel saturation magnetization on sputtering pressure. Squares: films sputtered at 2,000W; diamonds: films sputtered at 500W. (From: [43]. © 1994 American Institute of Physics. Reprinted with permission.)

62

Post-Processing Techniques for Integrated MEMS 80

Resistivity (µΩ.cm)

70 60

500W

50 40 30 2,000W 20 10

3

5

10 Argon pressure (mTorr)

20

30

Figure 3.12 Dependence of nickel resistivity on sputtering pressure. Squares: films sputtered at 2,000W; diamonds: films sputtered at 500W. (From: [43]. © 1994 American Institute of Physics. Reprinted with permission.)

film thickness over 140 nm results in textured film, which increases with thickness. Using Si (100) or Si (111) as a sputtering substrate, the sputtered nickel films always have <111> preferred orientation for all thicknesses larger than 40 nm. Furthermore, it was found that the lattice constant for nickel sputtered on glass is smaller than that of the bulk film [46], indicating a compressive stress, which might be due to the amorphous nature of the substrate, or due to differences in thermal expansion coefficients between the film and the substrate. On the other hand, nickel sputtered on Si (100) or Si (111) has almost the lattice constant as that of the bulk film, indicating low residual stress. It is interesting to note that the grain size of sputtered nickel depends strongly on the substrate type and layer thickness. Figure 3.13 clarifies this issue, where it can be observed that in general the grain size of nickel on Si (100) or on glass increases with increasing thickness with much smaller grains for Ni/glass, which might be due to the amorphous state of the substrate [46]. However, Ni/Si (111) has a constant grain size independent of the layer thickness. In spite of the larger grains of Ni on Si (100) compared to Ni on glass, the resistivity of the later is lower, as shown in Figure 3.14 [46]. This might be due to the diffusion of electrons by the semiconductor layer under the nickel layer, which is not the case for an insulator underlayer [47]. Thus it can be concluded that, if we need highly conductive nickel films, it is recommended to sputter these films on an insulator, but stress will be relatively highly compressive. If we can accommodate relatively high resistances, then mean stress can be reduced by depositing Ni films on a Si (100) or Si (111) substrates.

MEMS Materials

63

80 70

Ni/Si (100)

Grain size (nm)

60 50 40

Ni/Si (111)

30 20 Ni/Glass

10 0 30

50

100 200 Thickness (nm)

300

500

Figure 3.13 Effect of Ni film thickness and substrate type on the grain size of sputtered nickel. (From: [46].) 1600 Ni/Si (111)

1400

Resistivity (µΩ.cm)

1200 1000 800

Ni/Si (100)

600 400 200 Ni/Glass 0 30

50

100 200 Thickness (nm)

300

500

Figure 3.14 Dependence of electrical resistivity of sputtered Ni films on thickness and substrate type. (From: [46].)

3.3.3

Platinum as a MEMS Material

Platinum is considered an attractive MEMS material due to its hardness and resistance to corrosion. In addition, it is a nonferromagnetic material and hence it is suitable for applications that are exposed to high magnetic fields where nickel, cobalt, and copper cannot be used. Moreover, platinum has been considered a good candidate for uncooled infrared detector applications due to its

64

Post-Processing Techniques for Integrated MEMS

relatively high temperature coefficient of resistance [48]. Furthermore, it is clear from Figure 3.15 that stress can be tuned to a low tensile value at a sputtering pressure around 4.8 mTorr [49]. The resistivity of platinum thin films depends strongly on the deposition technique and the oxygen content. For focused ion beam induced deposition, it is clear from Figure 3.16 that the resistivity of platinum depends strongly on the ion beam current, which can be tuned to 3 mΩ.cm [50], which is more than 500 times higher than that of the bulk material (10.6 µΩ.cm). In general, platinum has poor adhesion to oxide substrates, and accordingly, it is sputtered in an oxygen/argon gas mixture, as this results in platinum 400 Tensile stress 200

Stress (MPa)

0 –200 –400 –600 –800 Compressive stress

–1000 1.5

2

2.5

3 3.5 4 4.5 Sputtering pressure (mTorr)

5

5.5

Figure 3.15 Dependence of stress on sputtering pressure of platinum alloyed with 15% Rh and 6% Ru. (From: [49]. © 2003 IEEE. Reprinted with permission.) 7

Resistivity (mΩ.cm)

6 5 4 3 2

0

1

2

3 4 5 Ion beam current (nA)

6

7

Figure 3.16 Dependence of resistivity of platinum on ion beam current. (From: [50]. © 2001 IEEE. Reprinted with permission.)

MEMS Materials

65

oxides that improve adhesion by forming a thin oxide layer at the interface between platinum and the oxide substrate [51–53]. On the other hand, introducing oxygen during sputtering results in severe changes in electrical resistivity. It is clear from Figure 3.17 that increasing the oxygen content results in an increase in resistivity, which is due to the formation of a platinum oxide layer. Decreasing the sputtering pressure is accompanied by a decrease in resistivity, which is due to changes in the film microstructure [54]. It was observed that, irrespective of the deposition conditions, annealing platinum films at 800°C reduces the resistivity of the films to around 13 µΩ.cm, which is close to that of the bulk material [54]. This is believed to be due to the removal of all incorporated oxygen in platinum. At this point it is interesting to investigate the dependence of mean stress on the oxygen content. Since resistivity indicates the oxygen content in platinum thin films [55, 56], stress can be related to resistivity. Figure 3.18 shows that for platinum films sputtered at 5 mTorr and room temperature, the lower the resistivity (i.e., the lower the oxygen content), the higher the mean stress. As the oxygen content is increased, the mean tensile stress is decreased, which might be due to the formation of oxides with large lattice parameters or the oxide atoms reside in interstitial sites [57]. By increasing the deposition pressure to 9.4 mTorr, stress is decreased, which is due to the higher oxygen content, and this results in the formation of an amorphous oxide in most of the platinum film [54]. Thus, it can be concluded that for MEMS applications there is a compromise between electrical resistivity, mean stress, and adhesion to silicon dioxide 10000 3000

RT, 9.4 mTorr RT, 5 mTorr

Resistivity (µΩ.cm)

1000 300

400°C, 5 mTorr

100 30 10 3

0

10

20 30 PO2 / Pt (%)

40

50

Figure 3.17 Effect of fractional oxygen content on resistivity of 400-nm platinum films deposited under different conditions on top of 300 nm of silicon dioxide. (From: [54]. Reprinted with permission.)

66

Post-Processing Techniques for Integrated MEMS 0.7 0.6

Stress (GPa)

0.5

RT, 5 mTorr

0.4 0.3 0.2

RT, 9.4 mTorr

0.1 0 50

100

200

500 1000 Resistivity (µΩ.cm)

2000

5000

Figure 3.18 Variation of stress as a function of resistivity of sputtered platinum thin films. (From: [54]. Reprinted with permission)

sacrificial layers. To have flat suspended structures having good adhesion to oxide substrates, the resistivity will be almost two orders of magnitude higher than that of the bulk material. Temperature coefficient of resistance (TCR) of platinum is an important issue. It enables the use of this material for infrared detectors and the fabrication of resistance thermometers. It has been found that TCR is affected by the sputtering gas being either argon or nitrogen [58]. For platinum films sputtered under nitrogen, the average TCR, obtained after two successive recrystallization heat treatments at temperatures higher than 1,000°C, is around 3,850 ppm/°C [58]. It should be noted that such TCR is lower than that of bulk platinum (3,928.9 ppm/°C [59]); this is mainly due to the fact that TCR is very sensitive to impurities, grain size, grain boundaries, grain shape regularity, small holes along the grain boundaries, dislocations within the polycrystalline grains, sputtering gas atoms entrapped during deposition, film thickness, continuity, and surface roughness. 3.3.4

Gold as a MEMS Material

Gold is an attractive candidate for applications that require high reflective coatings as micromirrors [60, 61] as it minimizes thermal absorption and can compensate the residual stress in the MEMS structural layer to obtain flat suspended structures. Furthermore, contacts in RF microswitches [62] and microrelays [63] are fabricated of gold. It is also used for wafer level packaging [64]. To have an idea about mean stress in sputtered gold, it is instructive to refer to Figure 3.19, where it is clear that mean stress can be tuned to a low tensile value if the layer thickness is around 1,000 Å [65]. In spite of such low

MEMS Materials 2.5

67

Tensile stress

2

Stress (GPa)

1.5 Chromium 1 Gold

0.5 0 –0.5 –1

Titanium 0

500

1000 1500 Film thickness (Å)

Compressive stress 2000

2500

Figure 3.19 Dependence of stress on thin metal film thickness. Circles: titanium; diamonds: gold; squares: chromium. All metals are sputtered at 10 mTorr. (From: [65]. Reprinted with permission.)

mean stress, adhesion of gold to silicon is poor, and accordingly, a thin adhesive layer of either titanium or chromium is necessary. The selection of one of these two materials is based on their mean stress. By inspecting the squares and circles in Figure 3.19, it is evident that the mean stress in thin Ti layers (thinner than 500 Å) is highly compressive and it is noticeably reduced if the layer thickness is increased to 1,000 Å or more. On the other hand, chromium has a high mean tensile stress which does not drop significantly even for thick layers (∼1,500 Å). At this point, it is interesting to note that the mean stress in thin Ti layers (∼100 Å) can be reduced by more than a factor of five if the sputtering pressure is increased to 30 mTorr (cf. squares in Figure 3.20). On the other hand, stress in chromium is less sensitive to the sputtering pressure as clear from the diamonds in Figure 3.20. As we are interested in the mean stress of a stack composed of Au and Ti, it might be instructive to investigate the dependence of mean stress on sputtering pressure for such a stack. The data displayed in Figure 3.21 shows that sputtering 1,500 Å of Au on top of 100 Å of Ti, at a sputtering pressure slightly higher than 30 mTorr, eliminates completely the mean stress; whereas sputtering Au on top of Cr, at the same pressure, has a tensile stress of 60 MPa, which can still be acceptable for surface micromachining applications. 3.3.5

Electroplated Copper

Electroplating enables the realization of thick structures (>20 µm) having a high aspect ratio (>50:1) that cannot be realized by conventional deposition techniques such as sputtering, evaporation, or chemical vapor deposition. In general, the electroforming process is characterized by low residual stress [42]. The

68

Post-Processing Techniques for Integrated MEMS 2 Tensile stress

Stress (GPa)

1.5 1

Chromium

0.5 0

–0.5 Titanium –1

0

10

Compressive stress

20 30 Sputtering pressure (mTorr)

40

50

Figure 3.20 Dependence of stress on sputtering pressure of chromium and titanium. Layer thickness is 10 nm. (From: [65]. Reprinted with permission.)

80 Tensile stress 60

Stress (MPa)

40

1,500 Å Au / 100 Å Cr

20 0 –20 –40

1,500 Å Au / 100 Å Ti

–60 Compressive stress –80

10

20 30 40 Sputtering pressure (mTorr)

50

Figure 3.21 Dependence of stress on sputtering pressure for a stack of 1,500 Å of Au on top of 100 Å of Ti (squares), or 1,500 Å of Au on top of 100 Å of Cr (diamonds). (From: [65]. Reprinted with permission.)

process uses thick spin coated polymers (SU-8, or PMMA) [42, 66]. The polymer layer is patterned by UV exposure, e-beam or X-ray radiation, followed by development. Then an adhesive layer is sputtered; this is followed by the deposition of an electrically continuous seed layer for the electroplating process. Typically 50 to 100 Å of titanium or chromium [42] are used as adhesion layers, whereas 150 to 300 Å of Au, Cu, Pt, Ni, or NiFe is used as a seed layer for electroplating [42, 66]. In general, electroplating is done in an electrolytic cell. The

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69

reactions depend on the imposed current density, temperature, solution composition, agitation, and pH. For more details about this process, the reader is referred to [42]. At this point it should be noted that the electroplating process depends on dissolution of the substrate, and accordingly, the process is self-limiting [42], which means that the thickness will saturate at a certain value. Electroless plating alleviates this problem [67]. In this case, no current is required and deposition depends on the reduction of a metal from its salt using electrons supplied by a simultaneous oxidation reaction. Electroless plating results in conformal metal deposition, which is suitable for coating MEMS structures having high aspect ratio. The advantage of this technique is that it allows self-aligned electrical isolation [67]. The low preparation temperature of electroplated copper, coupled with its low residual stress, makes this material suitable for post-processing MEMS on top of standard prefabricated CMOS electronics [68]. In addition, the high mass density of copper as compared to Al enables the realization of high mass inertial systems. Copper has been used for RF-MEMS switches because of its low resistivity compared to Al and gold [69]. Electroformed copper has been an attractive candidate for the fabrication of high aspect ratio microstructures realized by deep X-ray lithography on graphite substrates [70]. The advantage of using electroplated copper is that it absorbs scattered X-rays and the electroforming process is low cost and has low toxicity. Electroplated copper has enabled the realization of three-dimensional inductive components [71] having low resistance and relatively high inductance, which can be used as actuators for MEMS-based applications such as microvalves, micropumps, and biomagnetic particle separators [71]. Furthermore, electroplated copper is used to fabricate low-voltage comb-drive actuators for tunable capacitors to reduce the tuning voltage in MEMS structures to less than 5V and simultaneously increase the capacitance in between the electrode fingers [72].

3.4 Semiconductor and Dielectric Materials In spite of the fact that metals are used in a wide variety of MEMS applications, there is an increasing demand for using semiconductor materials as a MEMS structural material due to its high temperature coefficient of resistance, which is essential for thermal detectors, and its low thermal conductivity, which is an order of magnitude lower than that of metal [73]. In addition, the quality factor of semiconductor materials is much higher than that of metals [74]. The following sections review the different semiconductor materials used as a structural MEMS material and highlights the limitations for each one.

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3.4.1

Post-Processing Techniques for Integrated MEMS

Polycrystalline Silicon

Polycrystalline silicon (poly Si) has been widely used to conduct electrical signals for actuating or sensing. Its Young’s modulus-to-density ratio, E/ρ = 170 GPa / 2,320 kg/m3 = 73 × 106 m2/s2, indicates that it is a suitable material for elastic suspensions. Its fracture strength σmax = 2.5 GPa provides more-than-adequate safety margins for the mechanical designer, especially since poly Si exhibits negligible hystereses for stresses up to σmax at normal operating temperatures. Finally, internal energy dissipation in poly Si is extremely low, which is an important issue for resonator applications such as sensing and RF communication. Silicon resonators with mechanical quality factors as high as 80,000 have been reported [74]. In general, the transition temperature of silicon from amorphous to polycrystalline depends strongly on the deposition pressure and the type of deposition gases; it is typically 550°C or higher [75]. Such relatively high transition temperature limits the use of polycrystalline silicon for MEMS post-processing on top of standard prefabricated electronics. In addition, Figure 3.22 shows that stress in as-grown poly Si deposited at different temperatures is relatively high for MEMS applications [26, 76]. By comparing the squares and diamonds in Figure 3.22, it is clear that reducing the deposition temperature of LPCVD poly Si from 620°C to 590°C reverts stress from being highly compressive to highly tensile. This might be due to the fact that the films deposited at 590°C are amorphous as deposited and then crystallize in the furnace. 400

Poly Si deposited at 590°C Tensile stress

300

Stress (MPa)

200 100 0 –100 –200

Poly Si deposited at 850°C

–300 –400 –500 500

Poly Si deposited at 620°C 600

Compressive stress

700 800 900 Annealing temperature (°C)

1000

1100

Figure 3.22 Dependence of stress on annealing temperature of polycrystalline silicon. Squares: LPCVD poly Si deposited at 590°C and 0.1 Torr; stars: LPCVD poly Si deposited at 620°C and 0.1 Torr; and diamonds: APCVD poly Si deposited at 850°C and atmospheric pressure. (Data from: [26, 76].)

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Crystallization results in contraction against the boundary constraints, inducing a tensile stress, which can be approximated as the radial traction, applied at the edge of the imaginary unconstrained crystallized film, required to restore it to its original amorphous diameter. On the other hand, the high compressive stress reported poly Si deposited at 620°C might be due to high defect density or highly disordered grain boundaries [77]. Increasing both the deposition temperature and pressure to 850°C and 760 Torr, respectively, reduces the stress in the as-grown film relatively, as can be seen from the diamonds in Figure 3.22. In general, stress can be reduced by increasing the annealing temperature due to the motion of dislocations in the direction of the stress gradient [78]. Mean stress can be completely eliminated at temperatures around 950°C, as clear from Figure 3.22. Thus, it can be concluded that stress in poly Si cannot be controlled at a CMOS backend compatible temperature. Amorphous silicon has been used as a MEMS structural or sacrificial layer [79]. The advantage of using amorphous silicon as a sacrificial layer is that it can be easily wet etched in KOH or TMAH or dry etched using XeF2 or SF6. Furthermore, this material can be prepared at relatively low temperatures (~ 300°C) as it can be deposited using physical vapor deposition (PVD), sputtering, or PECVD. PECVD is preferred as it provides a good adhesion to silicon dioxide and the film does not peel off. Stress in PECVD Si depends strongly on the RF power and mode as demonstrated in Figure 3.23 [79], which shows that reducing the deposition power and increasing the RF frequency to 13.56 MHz reduces mean stress to around 150 MPa compressive. At this point it should be noted that crystallization of amorphous silicon films could be enhanced at a CMOS backend compatible temperature by –150 –200 Stress (MPa)

–250

RF mode: 13.56 MHz

–300 RF mode: 380 KHz

–350 –400 –450 –500 50

100

150

200 250 RF power (W)

300

350

Figure 3.23 Dependence of stress in amorphous silicon on RF power and mode. (From: [79]. Reprinted with permission.)

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Post-Processing Techniques for Integrated MEMS

depositing PECVD silicon on top of a thin metal film and annealing for long time. This technique is known as metal induced crystallization [80, 81]. It is demonstrated in Chapter 5 that this approach results in films having high compressive stress and a significant stress gradient. Furthermore, the electrical conductivity of the films is mainly dominated by the metal, and accordingly, resistivity cannot be controlled by doping. Pulsed laser annealing is also another technique widely used to enhance the crystallization of silicon at relatively low temperatures for thin film transistors deposited on top of glass substrates [82]. The main limitation of this approach is that the crystallization depth is limited to fraction of a micron. Moreover, there is no published data on stress gradient in laser annealed silicon films for MEMS applications. Alloying silicon with germanium reduces the crystallization temperature to 400°C (for a Ge content around 69% [83]). It is demonstrated that stress in silicon germanium can be tuned to low tensile values at a CMOS compatible backend temperature [3]. In addition, there are many attractive features of silicon germanium that make it superior to silicon. For example, the thermal conductivity of Si70Ge30 is a factor of six lower than that of poly Si [4]. Furthermore, for the same doping concentration the resistivity of p-type SixGe1-x is lower than that of poly Si. Thus, it is interesting to consider this material as a structural layer for MEMS devices that are post-processed on top of standard prefabricated electronics. The next chapter is devoted to the discussion of the physical properties of silicon germanium from the point of view of MEMS, focusing on low thermal budget techniques for controlling stress and electrical conductivity. 3.4.2

Polycrystalline Germanium

Recently, polycrystalline germanium has been considered as a MEMS structural material and sacrificial layer due to its low crystallization temperature (∼300°C) [84]. Furthermore, germanium can be easily etched in hydrogen peroxide (H2O2) [85], which makes this material etched selectively with respect to a wide variety of materials. Germanium can be deposited by LPCVD or PECVD [86, 87], using germane in hydrogen as the germanium gas source. At this point it might be instructive to highlight the main differences between these two techniques. For LPCVD, the growth rate decreases significantly with reducing the deposition temperature. For films deposited at 400°C the growth rate is 4 nm/min. Furthermore, the surface roughness is higher than that of the PECVD films (cf. Figure 3.24 [87]). The main advantage of LPCVD is that the step coverage is good. Figure 3.24(a) clarifies this issue: a 2-µm thick LPCVD Ge film fills completely a 12-µm-deep and 2-µm-wide trench. Figure 3.24(b) shows that for the same thickness and deposition temperature, PECVD Ge films have poor step coverage, but the growth rate is much higher than that of the LPCVD films (~70

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(a)

73

(b)

Figure 3.24 SEM image of 12-µm-deep and 2-µm-wide trenches covered with (a) 2-µm-thick LPCVD Ge deposited at 400°C, and (b) 2-µm-thick PECVD Ge deposited at 400°C, and 20 W. (From: [87]. Reprinted with permission.)

nm/min). Thus, PECVD is preferred for applications that require thick films, having a smooth surface, and step coverage is not an issue. Franke et al. [86] studied the effect of rapid thermal annealing temperature and period on mean stress of n-type LPCVD poly Ge deposited at 400°C under different pressures. From Figure 3.25(a) it is clear that the mean stress in poly Ge deposited under 300 mTorr, is almost unaffected by the annealing period at 450°C, whereas increasing the annealing temperature to 550°C [Figure 3.25(a)] results in a steep change in stress from compressive to tensile, which indicates significant textural changes. As we are interested in as-grown tensile films, it is instructive to investigate the effect of the deposition pressure and phosphine flow rate on the mean stress of as-grown poly Ge films deposited at 400°C. Figure 3.25(b) shows that increasing the deposition pressure to 600 mTorr results in an as-grown tensile film. For a deposition pressure of 300 mTorr, reducing the phosphine flow rate converts stress from compressive to tensile, as seen in Figure 3.25(c). As stress gradient is an important issue, it might be also interesting to investigate the effect of phosphorus in situ doping on stress variation across the film thickness. The data displayed in Figure 3.26 shows that adding phosphine during the deposition of poly Ge has a significant impact on stress gradient [86]. Reducing the phosphine gas flow rate during deposition results in a noticeable decrease in stress gradient, which is eliminated by annealing at 550°C. But such thermal treatment is no longer compatible with standard CMOS backend, as previously discussed in Chapter 2. Thus, it might be difficult to use poly Ge for applications that have strict constraints on stress gradient as inertial sensors. 3.4.3

Silicon Nitride

Silicon nitride is widely used in MEMS either as a supporting membrane [88] or as an insulating layer [89], due to its low thermal conductivity (∼2.2 W/mK [73]), which is two orders of magnitude lower than that of metals. Also, the high

74

Post-Processing Techniques for Integrated MEMS 300

Mean stress (MPa)

200 550°C

100 0 –100 450°C –200

0

50

100 150 200 250 Annealing time (sec) (a)

220

350

300

350

650°C

200 Mean stress (MPa)

300

550°C

180 160 140 120 100

450°C

80

0

50

100 150 200 250 Annealing time (sec) (b)

300 650°C

Mean stress (MPa)

250 550°C 200 150

450°C

100 50

0

50

100 150 200 250 Annealing time (sec) (c)

300

350

Figure 3.25 Effect of rapid thermal annealing temperature on mean stress in n-poly Ge deposited under different conditions: (a) 400°C, 300 mTorr, 100 sccm GeH4, 10 sccm PH3/SiH4 2 µm thick; (b) 400°C, 600 mTorr, 219 sccm GeH4, 10 sccm PH3/SiH4 5 µm thick; and (c) 400°C, 300 mTorr, 219 sccm GeH4, 5 sccm PH3/SiH4 5.1 µm thick. (From: [86]. © 1999 Institute of Electrical Engineers of Japan. Reprinted with permission.)

MEMS Materials 120

75

450°C

Cantilever deflection (µm)

100 80 60 40 550°C 650°C

20 0

0

50

100

150 200 250 Annealing time (sec) (a)

300

350

80 Cantilever deflection (µm)

450°C 60

40

20

0

550°C

0

50

100

650°C

150 200 Annealing time (sec) (b)

250

300

350

Figure 3.26 Effect of phosphine flow rate and deposition pressure on the deflection of 1–mm-long cantilever realized by n-type poly Ge deposited at 400°C and different pressures and gas flow rates: (a) 600 mTorr, 219 sccm GeH4, 10 sccm PH3/SiH4 5 µm thick; (b) 300 mTorr, 100 sccm GeH4, 10 sccm PH3/SiH4 2 µm thick. (From: [86]. © 1994 Institute of Electrical Engineers of Japan. Reprinted with permission.)

quality factor of this material makes it suitable for fabricating force sensors in atomic force microscopy [74]. The development of high-quality low-stress PECVD silicon nitride has enabled the realization of self-supporting membranes capable of performing large displacements, which are used for monolithic integration of inductors with RF driving electronics [88]. Such application implied that the silicon nitride supporting membrane should have low tensile stress (< 10 MPa) to avoid significant distortion of the spiral. Adjusting the deposition conditions of PECVD silicon nitride films enabled the realization of the required stress at 200°C [88]. Furthermore, the mechanical properties of

76

Post-Processing Techniques for Integrated MEMS 600

Stress (MPa)

400 200 0 –200 –400

0

50

100 150 RF power (W)

200

250

Figure 3.27 Dependence of mean stress of PECVD Si3N4 deposited at 350°C and 850 mTorr on RF deposition power. (From: [87]. Reprinted with permission.)

Si3N4 do not vary significantly at cryogenic temperatures (∼30 K), which makes this material suitable for space applications [90]. At this point it is important to provide more insight about the deposition of PECVD Si3N4, as it is attractive for post-processed MEMS. In general, ammonia is used as the nitrogen gas source, whereas the silicon gas source is silane [87]. Stress in PECVD Si3N4 is affected by the deposition power and pressure. Figure 3.27 shows that for low deposition powers, the mean stress in the films deposited at 350°C and 850 mTorr, is relatively high tensile. Around 50W, the mean stress is almost zero, and any further increase in deposition power converts stress to compressive. On the other hand, for the same deposition power, Figure 3.28 shows that increasing the deposition pressure reduces the compressive stress until it is converted to tensile for pressures higher than 850 mTorr. Accordingly, for low stress layers it is recommended to deposit the films at around 50W and 850 mTorr. This corresponds to a deposition rate of 21 nm/min and a refractive index of 2.038 [87].

3.4.4

Silicon Dioxide

Silicon dioxide is commonly used as a MEMS sacrificial layer [91, 92], as it can be etched selectively with respect to the silicon, silicon nitride, and aluminum. Etching can be done wet in hydrofluoric acid or buffer hydrofluoric acid and glycol (to avoid attacking aluminum). Vapor HF is demonstrated to be an efficient technique for etching of SiO2 and at the same time eliminate surface tension to yield flat suspended structures, even for thin films (< 0.5 µm) [3].

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77

300 200

RF power: 50 W

Stress (MPa)

100 0 –100 –200

RF power: 100 W

–300 –400 –500 400

600

800

1000

1200 1400 1600 Pressure (mTorr)

1800

2000

2200

Figure 3.28 Dependence of mean stress in PECVD Si3N4 deposited at 350°C on deposition pressure. Deposition power is either 50W (diamonds) or 100W (squares). (From: [87]. Reprinted with permission.)

Also, SiO2 is used in wafer bonding [93] and for electrical isolation of MEMS structures [94, 95]. Furthermore, the low thermal conductivity of this material (∼1 W/mK [73]) enables the realization of high thermal isolation. In general, silicon dioxide can be grown by oxidizing silicon wafers by a stream of wet or dry oxygen/nitrogen mixture at temperatures varying between 600°C and 1,250°C [42]. Such oxidation process results in compressive films due to the molecular volume mismatch and thermal expansion differences. The deposition temperature of silicon dioxide can be significantly reduced by using plasma enhanced chemical vapor deposition (PECVD) [87, 96]. In this case the silicon gas source can be pure silane, whereas nitrous oxide (N2O) can be used as the oxygen gas source. Mean stress in PECVD SiO2 can be controlled to a low tensile value (∼+15 MPa at a deposition temperature of 500°C [87]) by adjusting the ratio of the low frequency and high frequency modes of the RF generator, as well as the deposition power and pressure. It is interesting to note that the refractive index and growth rate of PECVD SiO2 films depend strongly on the ratio between nitrous oxide and silane. Growth rate increases linearly with the silane flow rate (Figure 3.29). Whereas it is clear from Figure 3.29 that as the ratio of N2O/SiH4 exceeds 40 the sharp change in the refractive index starts to level off [96]. For a ratio of 44, the refractive index is close to that of thermal oxide. For lower ratios, the film is silicon rich or oxygen deficient. It should be noted that mean stress is also significantly affected by the ratio of N2O:SiH4, as shown in Table 3.1 [96]. This is due to the differences in microstructure and impurity corporation level [97].

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Post-Processing Techniques for Integrated MEMS 500

1.48

400 Refractive index

1.47 1.465

300

1.46

200

1.455 100

Deposition rate (nm/min)

1.475

1.45 1.445

0

20

40 60 80 N2O/SiH4 flow rate ratio

100

0 120

Figure 3.29 Dependence of silicon dioxide growth rate and refractive index on the ratio of N2O:SiH4. (From: [96]. Reprinted with permission.) Table 3.1 Dependence of Stress on N2O:SiH4 Ratio for Silicon Dioxide Deposited at 380°C N2O:SiH4

Stress

20:1

60 MPa compressive

44:1

210 MPa compressive

80:1

325 MPa compressive

Source: [96].

3.4.5

Porous Silicon

Porous silicon is used as a sacrificial layer for MEMS [98, 99]. In this case, the depth of the sacrificial layer can extend to hundreds of microns underneath the MEMS structure. Also, it can be easily dissolved in hydroxyl solutions such as KOH. The development of the technology for pore initiation and formation has enabled the use of this material as an active MEMS material for a wide variety of applications such as the tunable optical interference filter [100], which uses density modulated porous silicon. Controlling the current during the electrochemical formation of silicon adjusts the porosity and the refractive index of silicon layer by layer, thus creating an interference filter, capacitors, or photonic bandgap materials in the infrared regime. Depending on the pore size and density, yield strength can vary between 83 GPa for 20% porosity to 0.87 GPa for 90% porosity [101]. The thermal conductivity of porous silicon is low (∼1 W/mK), which is attractive for applications that require high thermal isolation.

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Porous silicon is formed by anodization of silicon substrate in a mixture of hydrofluoric acid, methanol, and water in a cell with electrolytical backside contact, and illumination with visible light [102]. Pore dimensions are mainly determined by the doping type and concentration, current density, and the illumination conditions used during anodization. Table 3.2 gives guidelines for the relation between doping level and pore size. Micropores show photo luminescence [14], which is not relevant for MEMS applications. Macropore silicon is more interesting for MEMS as there are some devices realized by this material such as tunable optical filters [100], miniaturized microphones [103], microheaters [104], and humidity sensors [105]. In general, macropore formation is dominated by space charge effects [106]. Under anodic bias, a space charge region of significant extension is only present in n-type semiconductors. Accordingly, macropore formation in aqueous electrolyte solution is only observed for n-type silicon electrodes [14]. To enhance the generation of electron-hole pair, required to promote dissolution, the n-type material must be illuminated during the anodization process. Furthermore, the diameter of macropores depends strongly on the substrate resistivity and it increases proportionally to the substrate resistance. As a rule, the substrate resistivity in Ω.cm is the square of the pore diameter in microns [14]. The shape of the pores cross section can be determined by the surface treatments preceding the electrochemical pore formation process as oxidation (for circular pores) or anisotropic chemical etching, which makes square shaped pores. Rinsing after pore formation is the most critical step as surface tension force might damage the formed layers. This can be avoided by rinsing in solvents such as penthane or ethanol [100]. 3.4.6

Silicon Carbide

Silicon carbide is an attractive material due to its hardness, chemical inertness, high thermal conductivity, electrical stability at temperatures well above 300°C, and radiation resistance. Accordingly, it is suitable for high temperature MEMS applications such as micropropulsion, automotive, turbomachinery, oil Table 3.2 Dependence of Pore Size on Substrate Type and Doping Level Substrate Doping

Doping Level

Pore Size

N-type

Moderately doped

< 2 nm (micropores)

P- or N-type

Degenerately doped

2 to 50 nm (mesopores)

N-type

Nondegenerate and illumination

> 50 nm (macropores)

Source: [14].

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Post-Processing Techniques for Integrated MEMS

well/logging equipment, industrial process control, and nuclear power, where Si cannot be used, as it cannot stand temperatures higher than 250°C electronically and 650°C mechanically. Hence, it will require special packaging for such applications. Since silicon carbide is not etched, except in KOH at high temperature (∼600°C), a wide variety of materials can be used as a sacrificial layer including silicon. The electrical properties of SiC depend on the crystalline nature of this material, which is determined from the staking sequence of identical planes of Si and C atoms. For cubic poly type silicon carbide (3C-SiC), the energy bandgap between the valence band and the conduction band is 2.3 eV, whereas for hexagonal 2H-SiC the bandgap is 3.4 eV [12]. Doping of SiC is typically done in the gas phase, as activating ion-implanted dopants is not straightforward and doping by diffusion is impractical as SiC is a diffusion barrier [12]. Single crystal 3C-SiC and 6H-SiC are typically deposited at temperatures varying between 1,150°C and 1,360°C [12, 107]. Using PECVD, the deposition temperature can be varied between 200°C and 1,000°C, but the deposited materials are amorphous. Poly SiC is prepared by LPCVD and atmospheric pressure chemical vapor deposition (APCVD) [108–110]. Recently, UC Berkeley developed a new LPCVD process for depositing in situ doped polycrystalline SiC at 800°C [111, 112]. The as grown films have a resistivity as low as 28 mΩcm. Furthermore, it is demonstrated that the SiC films can be etched selectively with respect to low temperature oxide [111]. This is considered an important step towards surface micromachining silicon carbide MEMS devices. The main limitation for using such material for MEMS post-processing is that the processing temperature should be higher than 800°C; thus, it might be suitable for interleaved processing.

3.5 Summary and Conclusion This chapter gives an overview of the different MEMS materials that can be processed at a CMOS-compatible backend. Table 3.3 provides a summary for the attractive material properties, potential applications, and deposition techniques compatible with standard CMOS backend. Sputtered tantalum is a new MEMS material that can improve reliability of MEMS suspended structures. It is demonstrated that sandwiching Ta between two AlSi layers results in a stable surface micromachined structure having a sheet resistance of 27 mΩ/sq, suitable for RF switches. This stack is expected to have less creep than that of pure AlSi, at the expense of higher actuation voltage. The actuation voltage can be reduced by using thinner multilayer stacks (∼1 µm total thickness) coupled with narrow beams (∼10 µm wide).

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Table 3.3 Summary of the MEMS Material Properties

Material

Attractive Physical Properties

Potential Application

Deposition Technique Compatible with CMOS Post-Processing

Nickel

Ferromagnetic material Less brittle and more flexible than silicon Good electrical conductivity (200–1,600 mW.cm depending on layer thickness and substrate type).

Microlenses, microfuidics, for the realization of smooth mirrors, magnetic recording media, magneto resistive heads, and medical applications such as hearing aids and active catheters.

Evaporation, electroplating, and sputtering

Tantalum

Resistivity: 170 mW.cm Mean stress: 175 MPa tensile Compared to aluminum, it is less affected by creep.

Expected to improve reliability of RF switches.

Sputtering

Platinum

Hard and resistant to corrosion. Nonferromagnetic material. Relatively high temperature coefficient of resistance: 3,850 ppm/°C. Low mean stress (but resistivity will increase by one oreder of magnitude~200 mW.cm).

Suitable for applications that are exposed to high magnetic fields where nickel, cobalt and copper cannot be used. For temperature measurements.

Sputtering

Gold

High reflectivity. Low tensile stress (∼+100 MPa). Low electrical resistivity.

Contacts in RF microswitches and micro-relays. Wafer level packaging. Reflective coating for micro-mirrors.

Evaporation and sputtering

Copper

Low electrical resistivity. Low residual stress. High mass density of copper as compared to A1.

High aspect ratio microstructures. High mass inertial systems. RF MEMS switches. 3-D inductive components, low voltage comb-drive actuators for tunable capacitors.

Electrplating and sputtering

Poly Silicon

E/ρ = 170 GPa/2320 kg/m =73 × 106 m2/s2. Fracture strength σmax=2.5 GPa. Negligible hystereses for stresses up to σmax energy dissipation in poly Si is extremely low.

Suitable for applications that require elastic suspensions. PECVD silicon can be used as a sacrificial layer.

PECVD, but the material is amorphous

Poly Ge

Low crystallization temeperature (~300°C) Can be easily etched in hydrogen peroxide (H2O2)

Sacrificial layer, and structural layer for high quality resonators.

LPCVD and PECVD

Silicon Dioxide

Can be etched selectively with respect to the silicon, silicon nitride and aluminum. Low thermal conductivity of this material (~1 W/mK) PECVD SiO2 has Low mean tensile stress (~+15 MPa).

Sacrificial layer. Wafer bonding. Electrical isolation of MEMS structures. For applications that require high thermal isolation.

PECVD

3

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Post-Processing Techniques for Integrated MEMS

Table 3.3 (continued) Deposition Technique Compatible with CMOS Post-Processing

Attractive Physical Properties

Potential Application

Silicon Nitride

Low thermal conductivity (∼2.2 W/mK) High quality factor PECVD silicon nitride has low tensile stress (∼10 MPa).

Supporting membrane. Insulating layer. For resonators that require high quality factor such as force sensors.

PECVD

Porous Silicon

Depth of the sacrificial layer can extend to hundreds of microns underneath the MEMS structure. Ca be easily dissolved in hydroxyl solutions such as KOH.

Sacrificial layer. Tunable optical interference filter.

Anodization of silicon

Silicon Carbide

Hard, Chemically inert. High thermal conductivity. electrically stable at temperatures well above 300°C. Radiation resistance. Etches only in KOH at high temperature (∼600°C)

Micropropulsion, automotive, turbomachinery, oil well/logging equipment, industrial process control, nuclear power.

PECVD, but the material is amorphous

Material

In general, the electrical and mechanical properties of sputtered thin metal films depend on the sputtering pressure and the type of seeding layer required to enhance the adhesion of the metal film to the substrate. Sputtering Ni on an insulating substrate (e.g., glass) results in high conductivity, but stress is highly compressive. Stress can be reduced by using Si (100) or Si (111) substrates, but this will be at the cost of higher resistivity. On the other hand, stress and electrical conductivity in sputtered platinum are very sensitive to the oxygen content. The low sputtering temperature allows using photoresist as a sacrificial layer, which can be easily etched in oxygen plasma. It is demonstrated that the physical properties of poly Si can be tuned at temperatures higher than 600°C, and accordingly, this material cannot be used for MEMS post-processing on top of standard prefabricated electronics. In general, the deposition temperature can be reduced significantly by PECVD, but the films are amorphous and their physical properties are not suitable for a wide variety of MEMS applications. Thus, it is instructive to investigate the possibility of alloying silicon with germanium to reduce the crystallization temperature and to control the material physical properties at a CMOS backend temperature. This issue is discussed in depth in Chapters 4 and 5. Poly Ge and porous silicon are good candidates for low temperature sacrificial layers that can be prepared at a CMOS backend-compatible temperature and at the same time can be etched selectively with a wide variety of materials. In spite of the superior properties of SiC, its relatively high deposition temperature

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83

limits the monolithic integration of MEMS with the driving electronics to preprocessing or interleaved integration. In addition to the materials discussed in this chapter, there are new emerging materials such as aluminum nitride, which is rapidly becoming an important MEMS material that can be deposited at a CMOS backend temperature. This material has been recently implemented in high quality piezoelectric resonators that span a frequency range from 223 MHz to 656 MHz [113], thin-film bulk acoustic resonators [114, 115], and piezoelectric microactuator array that is considered to be the key component of a remotely controlled, wireless, solar powered microsystem which should be capable of locomotion [116].

References [1] Mingching, W., S. Shy, and W. Fang, “Integrating SOI and Poly-Si Surface Structures Using a Monolithic Process,” American Society of Mechanical Engineers, Micro-Electromechanical Systems Division Publication (MEMS), Vol. 5, 2003, p 63–68. [2] Busquere, J., et al., “MEMS SiGe Technologies for Advanced Wireless Communications,” 2004 IEEE Radio Frequency Integrated Circuits Symposium, 2004, pp. 247–250. [3] Sedky, S., A. Witvrouw, and K. Baert, “Poly SiGe, a Promising Material for MEMS Monolithic Integration with the Driving Electronics,” Sensors and Actuators A, Physical, Vol. 97-98C, 2002, pp. 503–511. [4] Sedky, S., et al., “Characterization and Optimization of Infra Red Poly SiGe Bolometers,” IEEE Transactions on Electron Devices, Vol. 46, No. 4, 1999, pp. 675–682. [5] Fritschi, R., et al., “High Tuning Range AlSi RF MEMS Capacitors Fabricated with Sacrificial Amorphous Silicon Surface Micromachining,” Microelectronic Engineering, Vols. 73–74, June 2004, pp. 447–451. [6] Ganguly, U., and P. Krusius, “Fabrication of Ultraplanar Aluminum Mirror Array by Novel Encapsulation CMP for Microoptics and MEMS Applications,” Journal of the Electrochemical Society, Vol. 151, No. 11, 2004, pp. H232–H238. [7] Saidani, M., A. Meyer, and M. Gijs, “Hybrid MEMS Inductor for Miniaturized Autonomous Power Converter,” Proceedings of the IEEE Microelectromechanical Systems (MEMS), 2003, pp. 586–589. [8] Fritschi, R., et al., “A Novel RF MEMS Technological Platform,” IECON Proceedings (Industrial Electronics Conference), Vol. 4, 2002, pp. 3052–3056. [9] Sedky, S., et al., “Sputtered Tantalum as a Structural Material for Surface Micromachined RF Switches,” Material Research Society Symposium Proceedings, Vol. 729, 2002, pp. 89–94. [10] Zhang, X., K. Chen, and M. Spearing, “Thermo-Mechanical Behavior of Thick PECVD Oxide Films for Power MEMS Applications,” Sensors and Actuators, A: Physical, Vol. 103, No. 1–2, January 15, 2003, pp. 263–270. [11] Charavel, R., et al., “Stress Release of PECVD Oxide by RTA,” Proceedings of SPIE—The International Society for Optical Engineering, Vol. 5116 II, 2003, pp. 596–606.

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[12] Mehregany, M., et al., “Silicon Carbide MEMS for Harsh Environment,” Proceedings of the IEEE, Vol. 86, No. 8, August 1998, pp. 1594–1610. [13] Chang, C. H., et al., “RF MEMS Capacitive Switches Fabricated with HDICP CVD SiNx,” IEEE MTT-S International Microwave Symposium Digest, Vol. 1, 2002, pp. 231–234. [14] Lehmann, V., “Porous Silicon – A New Material for MEMS,” 9th Annual International Workshop on Micro Electro Mechanical Systems, 1996, MEMS ’96, Proceedings, An Investigation of Micro Structures, Sensors, Actuators, Machines and Systems, IEEE, February 11–15, 1996, pp. 1–6. [15] Mescheder, U., et al., “Porous Silicon as Multifunctional Material in MEMS,” IEEE-Nano-2001, Nanoelectromechanical Systems, 2001, pp. 483–488. [16] Obi, S., et al., “Replication of Optical MEMS Structures in Sol-Gel Materials,” Microelectronic Engineering, Vols. 73–74, June 2004, pp. 157–160. [17] Saotome, Y., “Superplastic Nano/microforming of Bulk Metallic Glasses and the Application to Micromachines,” 2003 International Symposium on Micromechatronics and Human Science, pp. 11–16. [18] Saotome, Y., and H. Iwazaki, “Superplastic Backward Microextrusion of Microparts for Micro-Electro-Mechanical Systems,” Journal of Materials Processing Technology, Vol. 119, No. 1–3, December 20, 2001, pp. 307–311. [19] Saotome, Y., and A. Inoue, “Superplastic Micro-Forming of Microstructures,” Proceedings of the IEEE Microelectromechanical Systems, An Investigation of Micro Structures, Sensors, Actuators, Machines and Robotic Systems, 1994, pp. 343–348. [20] Fan, L. S., and R. S. Muller, “As-Deposited Low-Strain LPCVD Polysilicon,” Solid State Sensors and Actuators Workshop, 1988, p. 55. [21] Kamins, T. I., “Design Properties of Polycrystalline Silicon,” Sensors and Actuators A, Vol. 21–23, 1990, pp. 817–824. [22] Krulevitch, P., et al., “Stress in Undoped Polycrystalline Silicon,” 6th International Conference on Solid State Sensors and Actuators, 1991, pp. 949–952. [23] Benitez, A., et al., “Stress in Low Pressure Chemical Vapor Deposition Poly Crystalline Silicon Thin Films Deposited Below 0.1 Torr,” Sensors and Actuators A, Vol. 37–38, 1993, pp. 723–726. [24] Koleshko, V. M., V. F. Belitsky, and I. V. Kiryshin, “Stress in Thin Polycrystalline Silicon Films,” Thin Solid Films, Vol. 162, 1988, pp. 365–374. [25] Roy, S., et al., “In Situ Measurements of Young’s Modulus and Residual Stress of Thin Electroless Nickel Films for MEMS Applications,” Materials Research Symposium, Vol. 356, 1995, pp. 573–578. [26] Sedky, S., et al., “Structural and Mechanical Properties of Polycrystalline Silicon Germanium for Micromachining Applications,” Journal of Microelectromechanical Systems, Vol. 7, No. 4, 1998, pp. 365–372. [27] Tilmans, H., et al., “Wafer-Level Packaged RF-MEMS Switches Fabricated in a CMOS Fab,” Proceedings of IEDM 2001, Washington, D.C., December 3–5, 2001, pp. 921–924.

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[28] Seok-Whan-Chung and Yong-Kweon-Kim, “Design and Fabrication of 10*10 Micro-Spatial Light Modulator Array for Phase and Amplitude Modulation,” Sensors and Actuators A (Physical), Vol. A78, No. 1, November 23, 1999, pp.63–70. [29] Zolochevsky, A., and Y. Obataya, “Tension-Compression Asymmetry of Creep and Unilateral Creep Damage in Aluminum for Isothermal and Nonisothermal Processes,” JSME International Journal, Series A (Solid Mechanics and Material Engineering), Vol. 44, No.1, January 2001, pp.100–108. [30] Logsdon, W., and P. Liaw, “Tensile, Fracture Toughness and Fatigue Crack Growth Rate Properties of Silicon Carbide Whisker and Particulate Reinforced Aluminum Metal Matrix Composites,” Engineering–Fracture–Mechanics, Vol. 24, No. 5, 1986, pp.737–751. [31] Kelly, A., and N. Macmillan, Strong Solids, Oxford: Oxford University Press, 1986, p. 176. [32] Vink, T., et al., “Stress, Strain and Microstructure in Thin Tungsten Films Deposited by DC Magnetron Sputtering,” Journal of Applied Physics, Vol. 74, No. 2, 1993, pp. 988–995. [33] http://www.webelements.com. [34] Clevenger, L., et al., “The Relationship Between Deposition Conditions, the Beta to Alpha Phase Transformation, and Stress Relaxation in Tantalum Thin Films,” Journal of Applied Physics, Vol. 72, No. 10, 1992, pp. 4918–4924. [35] Cherowbrier, N., “Emerging Micro-Technology Finds Favor with Wafer Producers,” Advanced Packaging, Vol. 12, No. 10, October 2003, pp. 35–36. [36] Haga, Y., M. Esashi, and S. Maeda, “Bending, Torsional and Extending Active Catheter Assembled Using Electroplating,” Proceedings of the IEEE Microelectromechanical Systems (MEMS), 2000, pp. 181–186. [37] Macia, N., “Construction of a Microfluidic, Bi-Stable, Fluid Amplifier Using the Nickel Electroforming Method,” Proceedings of SPIE—The International Society for Optical Engineering, Vol. 4560, 2001, pp. 28–38. [38] Brug, J., T. Anthony, and J. Nickel, “Magnetic Recording Head Materials,” MRS Bulletin, Vol. 21, No. 9, September 1996, pp. 23–27. [39] Liao, S., and S. Anderson, “Domain Characteristics and Conformal Deposition of NiFe Thin Films,” Journal of the Electrochemical Society, Vol. 140, No. 1, January 1993, pp. 208–211. [40] Pan, L.-W., L. Lin, and J. Ni, “Cylindrical Plastic Lens Array Fabricated by a Micro Intrusion Process,” Proceedings of the IEEE Micro Electro Mechanical Systems (MEMS), 1999, pp. 217–221. [41] Boukhi, M., A. Bruson, and P. Guilmin, “X-Ray Diffraction Study Of Amorphization Along Interfaces in Polycrystalline Ni/Ti Multilayers,” Solid State Communications, Vol. 83, 1992, p. 5. [42] Madu, M., Fundamentals of Microfabrication, The Science of Miniaturization, Boca Raton, FL: CRC Press, 2002. [43] Miller, M. S., et al., “Influence of RF Magnetron Sputtering Conditions on the Magnetic, Crystalline, and Electrical Properties of Thin Nickel Films,” Journal of Applied Physics, Vol. 75, No. 10, Pt. 2A, May 15, 1994, pp. 5779–5781.

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[44] Movchan, B., and A. Demchishin, “Study of the Structure and Properties of Thick Vacuum Condensates of Nickel, Titanium, Tungsten, Aluminum Oxide and Zirconium Dioxide,” Phys. Met. Metallogr. (USSR), Vol. 28, No. 4, 1969, pp. 83–90. [45] Thornoton, J., “Influence of Apparatus Geometry and Deposition Conditions on the Structure and Topography of Thick Sputtered Coatings,” Journal of Vacuum Science and Technology, Vol. 11, 1974, p. 666. [46] Ghebouli, B., A. Layadi, and L. Kerkache, “Effect of the Substrate on the Structural and Electrical Properties of dc Sputtered Ni Thin Films,” EPJ Applied Physics, Vol. 3, No. 1, 1998, pp. 35–39. [47] Chopra, K. L., Thin Film Phenomena, New York: McGraw-Hill, 1970. [48] Shie, J.-Sh., et al., “Characterization and Modeling of Metal-Film Microbolometer,” Journal of Microelectromechanical Systems, Vol. 5, No. 4, December 1996, pp. 298–306. [49] Brazzle, J., et al., “A Hysteresis-Free Platinum Alloy Flexure Material for Improved Performance and Reliability of MEMS Devices,” 12th International Conference on Solid State Sensors, Actuators and Microsystems, Boston, MA, June 8–12, 2003, pp. 1152–1155. [50] Li-Jian, L., and J. Wang, “Investigation of Deposited Pt Films Induced by Focused Ion Beam,” Proceedings of the 6th International Conference on Solid-State and Integrated-Circuit Technology, Vol. 2, 2001, pp. 1087–1090. [51] McBride, J., “Growth and Characterization of Reactively Sputtered Thin-Film Platinum Oxides,” Journal of Applied Physics, Vol. 69, 1991, p. 1596. [52] Hecq, M., A. Hacq, and M. Liemans, “Some Experimental Aspects of dc Reactive Sputtering,” Journal of Applied Physics, Vol. 49, 1978, p. 6176. [53] Buhdani, R., et al., “Summary Abstract: Oxygen Enhanced Adhesion of Platinum Films Deposited on Thermally Grown Alumina Surfaces,” Journal of Vacuum Science Technology, Vol. 4, No. 6, 1986, p. 3023. [54] Kim, M., et al., “Stress of Platinum Thin Films Deposited by DC Magnetron Sputtering Using Argon/Oxygen Gas Mixture,” Materials Research Society Symposium, Vol. 441, 1997, pp. 427–432. [55] Bennewitz, C., W. Westwood, and J. Brown, “Structural and Electrical Properties of Films Sputtered from a Pt Cathode in Argon-Oxygen Mixtures,” Journal of Applied Physics, Vol. 46, 1975, p. 558. [56] Neff, N., et al., “Structural, Optical, and Electronic Properties of Magnetron-Sputtered Platinum Oxide Films,” Journal of Applied Physics, Vol. 79, 1996, p. 7672. [57] Alexander, P., and R. Hoffman, “Effect of Impurities on Intrinsic Stress in Thin Ni Films,” Journal of Vacuum Science, Vol. 13, 1975, pp. 96–98. [58] Zhang, J., et al., “Microstructure and Temperature Coefficient of Resistance of Platinum Films,” Journal of Applied Physics, Vol. 36, 1997, pp. 834–839. [59] Curtis, D., “Temperature, Its Measurement and Control in Science and Industry,” Instrument Society of America, Pittsburg, Vol. 5, 1982, p. 803. [60] Luo, Y., et al., “Gold Layer of MEMS Micro-Mirror,” Proceedings of the Second International Symposium on Instrumentation Science and Technology, Vol. 2, 2002, pp. 2/161–2/165

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[61] Min, Y., and Y. Kim, “Modeling, Design, Fabrication and Measurement of a Single Layer Polysilicon Micromirror with Initial Curvature Compensation,” Sensors and Actuators A: Physical, Vol. 78, No. 1, November 1999, pp. 8–17. [62] Lafontan, X., et al., “Concepts, Characterization and Modeling of MEMS Micro-Switches with Gold Contacts in MUMPs,” Proceedings of SPIE—The International Society for Optical Engineering, Vol. 4408, 2001, pp. 381–390. [63] Lafontan, X., et al., “Physical and Reliability Issues in MEMS Micro-Relays with Gold Contacts,” Proceedings of SPIE—The International Society for Optical Engineering, Vol. 4558, 2001, pp. 11–21. [64] Chen, S., et al., “Wafer-Level MEMS Package by Gold-Tin Bonding Method,” American Society of Mechanical Engineers, Micro-Electromechanical Systems Division Publication (MEMS), Vol. 5, 2003, pp. 169–172. [65] Picard, Y., et al., “Low Stress, High Reflectivity Thin Film for MEMS Mirrors,” Materials Research Society Symposium, Vol. 729, 2002, pp. 113–118. [66] Roberts, K., et al., “The Fabrication of an Array of Microcavities Utilizing SU-8 Photoresist as an Alternative ‘LIGA’ Technology,” Proceedings of the Thirteenth Biennial Microelectronics Symposium, June 20-23, 1999, pp. 139-141. [67] Neves, H., et al., “Conformal Electroless Copper and Nickel Deposition on MEMS Structures,” Materials Research Society Symposium Proceedings, Vol. 546, 1999, pp. 139–144. [68] Luo, H., et al., “A Copper CMOS-MEMS Z-Axis Gyroscope,” Proceedings of the IEEE Micro Electro Mechanical Systems (MEMS), 2002, pp. 631–634. [69] Balaraman, D., et al., “Low-Cost Low Actuation Voltage Copper RF MEMS Switches,” Microwave Symposium Digest, 2002 IEEE MTT-S International, Vol. 2, June 2–7, 2002, pp. 1225–1228. [70] Makarova, O., et al., “Microfabrication of Freestanding Metal Structures Released from Graphite Substrates,” 15th IEEE International Conference on Micro Electro Mechanical Systems, 2002, pp. 400 –402. [71] Sadler, D. J., et al., “Micromachined Semi-Encapsulated Spiral Inductors for Microelectromechanical Systems (MEMS) Applications,” IEEE Transactions on Magnetics, Vol. 33, No. 5, September 1997, pp. 3319–3321. [72] Aggarwal, A., et al., “MEMS Composite Structures for Tunable Capacitors and IC-Package Nano Interconnects,” IEEE 2004 Electronic Components and Technology Conference, 2004, pp. 835–842. [73] Von Arx, M., O. Paul, and H. Baltes, “Process-Dependent Thin Film Thermal Conductivities for Thermal CMOS MEMS,” Journal of Electromechanical Systems, Vol. 9, No. 1, 2000, pp. 136–145. [74] Yasumura, K., et al., “Quality Factor in Micron- and Submicron-Thick Cantilevers,” Journal of Microelectromechanical Systems, Vol. 9, No. 1, 2000, pp. 117–125. [75] Lin, H, et al., “Deposition and Device Application of In Situ Boron-Doped Polycrystalline SiGe Films Grown at Low Temperatures,” Journal of Applied Physics, Vol. 74, No. 9, 1993, pp. 5395–5401.

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[76] Sedky, S., and P. Fiorini, “Poly SiGe Bolometers,” in Handbook of Computer Vision Application, Jähne B., H. Hauβecker, and P. Geiβler, (eds.), New York: Academic Press, 1999, pp. 274–308. [77] Fan, L., and R. S. Muller, “As-Deposited Low-Strain LPCVD Polysilicon,” Solid State Sensors and Actuators Work Shop, 1998, p. 55. [78] Maier-Schneider, et al., “Variation in Young’s Modulus and Intrinsic Stress of LPCVD-Polysilicon Due to High Temperature Annealing,” Journal of Micromechanics and Microengineering, Vol. 5, 1995, p. 131. [79] Chung, C., et al., “Fabrication and Characterization of Amorphous Si Films by PECVD for MEMS,” Journal of Micromechanics Microengineering, Vol. 15, 2005, pp. 136–142. [80] Yoon, S. Y., et al., “Low Temperature Solid Phase Crystallization of Amorphous Silicon at 380°C,” Journal of Applied Physics, Vol. 84, 1998, p. 6463. [81] Yoon, S. Y., et al., “Low Temperature Metal Induced Crystallization of Amorphous Silicon Using a Ni Solution,” Journal of Applied Physics, Vol. 82, 1997, p. 5865. [82] Ikeda, H., “Evaluation of Grain Boundary Trap States in Polycrystalline Silicon Thin-Film Transistors by Mobility and Capacitance Measurements,” Journal of Applied Physics, Vol. 91, 2002, p. 4637. [83] Sedky, S., et al., “Effect of In Situ Boron Doping on Properties of Silicon Germanium Films Deposited by CVD at 400°C,” Journal of Materials Research, Vol. 16, No. 9, 2001, pp. 2607–2612. [84] Franke, A., et al., “Polycrystalline Silicon Germanium Films for Integrated Microsystems,” Journal of MicroElectroMechanical Systems, Vol. 12, No. 2, 2003, pp. 160–171. [85] Franke, A., et al., “Post-CMOS Modular Integration of Poly-SiGe Microstructures Using Poly Ge Sacrificial Layers,” Solid State Sensor and Actuator Workshop, Hilton Head Island, S C, June 4–8, 2000, pp. 18–21. [86] Franke, A. E., et al., “Optimization of Poly-Silicon-Germanium as a Microstructural Material,” Proceedings of the 1999 International Conference on Solid-State Sensors and Actuators, Transducers’99 Sendai, Japan, 1999, pp. 530–533. [87] Rusu, C., et al., “Planarization of Deep Trenches,” Proceedings of SPIE Micromachining and Microfabrication Process Technology VII, October 22–24, 2001, San Fransisco, CA, pp. 49–57. [88] Dell, J. M., et al., “Variable MEMS-Based Inductors Fabricated from PECVD Silicon Nitride,” Proceedings of the IEEE International Conference on Optoelectronic and Microelectronic Materials and Devices, 2002, pp. 567–570. [89] Anderson, R.C., R. Muller, and C. Tobias, “Porous Polycrystalline Silicon: A New Material for MEMS,” Journal of Microelectromechanical Systems, Vol. 3, No. 1, March 1994, pp. 10–18. [90] Chuang, W., et al., “Characterization of Mechanical Properties of Silicon Nitride Thin Films for Space Applications,” Materials Research Society Proceedings, Vol. 782, 2004, pp. A.5.21.1–AA5.21.6. [91] Sedky, S., et al., “IR Bolometers Made of Polycrystalline Silicon Germanium,” Sensors and Actuators A, Vol. 66 (1–3), 1998, pp. 193–199. [92] Plaza, J. A., et al., “Piezoresistive Accelerometers for MCM Package,” Journal of Microelectromechanical Systems, Vol. 11, No. 6, 2002, pp. 794–801.

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[93] Tan, C., et al., “Low-Temperature Direct CVD Oxides to Thermal Oxide Wafer Bonding in Silicon Layer Transfer,” Electrochemical and Solid-State Letters, Vol. 8, No. 1, 2005, pp. G1–G4. [94] Lee, S., et al., “Surface/Bulk Micromachining (SBM) Process and Deep Trench Oxide Isolation Method for MEMS,” Technical Digest—International Electron Devices Meeting, 1999, pp. 701–704. [95] Du, X., D. Zhang, and T. Lee, “Chip Level Packaging for MEMS Using Silicon Cap,” Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium, Vol. 29, 2004, pp. 342–344. [96] Choi, D., et al., “Optical and Thermo-Mechanical Properties of Plasma Enhanced CVD Silicon Dioxide Films upon Annealing,” Proceedings of SPIE—The International Society for Optical Engineering, Vol. 5355, Integrated Optics: Devices, Materials, and Technologies VIII, 2004, pp. 40–51. [97] Leplan, H., et al., “Residual Stresses in Evaporated Silicon Dioxide Thin Films: Correlation with Deposition Temperature and Aging Behavior,” Journal of Applied Physics, Vol. 78, No. 2, 1995, pp. 962–968. [98] Yong, D., et al., “Preparation and Etching of Porous Silicon as a Sacrificial Layer Used in RF MEMS Devices,” Proceedings of the 6th International Conference on Solid-State and Integrated-Circuit Technology, 2001, Vol. 2, October 22–25, 2001, pp. 816–819. [99] Bell, T., and K. Wise, “A Dissolved Wafer Process Using a Porous Silicon Sacrificial Layer and a Lightly-Doped Bulk Silicon Etch-Stop,” Proceedings of the 11th Annual International Workshop on Microelectromechanical systems, MEMS 1998, January 25–29, 1998, pp. 251–256. [100] Lammel, G., et al., “Tunable Optical Filter of Porous Silicon as Key Component for a MEMS Spectrometer,” Journal of Microelectromechanical Systems, Vol. 11, No. 6, 2002, pp. 815–827. [101] Mescheder, M., et al., “Porous Silicon as Multifunctional Material in MEMS,” Nanoelectromechanical Systems (NEMS), IEEE-NANO, 2001, pp. 483–488. [102] Lang, W., et al., “Current Induced Light Emission from Nanocrystalline Silicon Structures,” Proceedings of the International Conference on Micro Electro Mechanical Systems, 1992, MEMS ‘92, An Investigation of Micro Structures, Sensors, Actuators, Machines and Robot, IEEE, February 4–7, 1992, pp. 99–103. [103] Kronast, W., et al., “Single Chip Condenser Microphone Using Porous Silicon as Sacrificial Layer for the Air Gap,” Sensors and Actuators A, Vol. 87, 2001, pp. 188–193. [104] Ducso, C., et al., “Porous Silicon Bulk Micromachining for Thermally Isolated Membrane Formation,” Sensors and Actuators A, Vol. 60, 1997, pp. 235–239. [105] Rittersma, Z., and W. Benecke, “A Novel Capacitive Porous Silicon Humidity Sensor with Integrated Thermo and Refresh Resistors,” Proceedings of the Eurosensors XIII, The 13th European Conference on Solid State Transducers, 1999, pp. 371–374. [106] Theunissen, M., “Etch Channel Formation During Anodic Dissolution of N-Type Silicon in Aqueous Hydrofluoric Acid,” Journal of Electrochemical Society, Vol. 119, 1972, p. 351. [107] Gourbeyre, C., et al., “Control of Stress with Growth Conditions and Mechanical Parameters Determination of 3C-SiC Heteroepitaxial Thin Films,” Proceedings of the Materials Research Society, Vol. 657, 2001, pp. EE5.20.1–EE5.20.6.

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[108] Derst, G., et al., “Preparation of Crystalline SiC Thin Films by Plasma-Enhanced Chemical Vapor Deposition and by Ion Beam Modification of Silicon,” Mater. Sci. Eng., Vol. B11, 1992, pp. 79–82. [109] Kobayashi, J., et al., “Preparation of Polycrystalline SiC Thin Films by RF Magnetron Sputtering Using Multi-Target,” in Silicon Carbide and Related Materials, Vol. 142, S. Nakashima, et al., (Eds.) Bristol, UK: IOP Publishing, 1995, pp. 229–232. [110] Onuma, Y., et al., “Thin Film Transistors Using Polycrystalline SiC,” in Amorphous and Crystalline Silicon Carbide II, Vol. 43, M. M. Rahman, C.Y. Yang, and G. L. Harris (Eds.), Berlin: Springer, 1989, pp. 212–216. [111] Gao, D., et al., “Recent Progress Toward a Manufacturable Polycrystalline SiC Surface Micromachining Technology,” IEEE Sensors Journal, Vol. 4, 2004, pp. 441–448. [112] D. Gao, R. T. Howe, and R. Maboudian, “High-selectivity etching of polycrystalline 3C-SiC films using HBr-based transformer coupled plasma,” Applied Physics Letters, 82, 2003, pp. 1742–1744. [113] Piazzo, G., et al., “Low motional resistance ring-shaped contour-mode aluminum nitride piezoelectric micromechanical resonators for UHF applications,” 18th International Conference on Micro Electro Mechanical Systems, MEMS’05, pp. 20-23. [114] Kun-Wook K., et al., “Resonator size effects on the TFBAR ladder filter performance,” IEEE Microwave and Wireless Components Letters, Volume 13, Issue 8, August, 2003 pp. 335–337. [115] Hara, M., “MEMS Based Thin Film 2 GHz Resonator for CMOS Integration,” 2003 IEEE MTT-S International Microwave Symposium Digest, Volume 3, June 2003, pp. 1797–1800. [116] Ruffieux, D., M. Dubois, and N. de Rooij, “An AlN piezoelectric microactuator array,” The 13th Annual International Conference on Microelectromechanical Systems, 2000. MEMS 2000. Jan. 2000, pp. 662–667.

4 Silicon Germanium as an Attractive MEMS Material 4.1 Introduction In spite of the fact that metals [1], amorphous silicon [2], vanadium oxide [3], and sputtered silicon [4] are used as structural materials for MEMS devices that are post-processed on top of prefabricated electronics, the use of each of these materials has limitations. Metals with a tendency to creep, such as Al, might result in reliability problems, specifically for RF switches [5]. In addition, the resistivity of metals is a slowly varying function of temperature, making them unsuitable for temperature sensitive applications such as high performance infrared focal plane arrays. Amorphous semiconductors have large low frequency (1/f ) noise and high compressive stress that dramatically limit the performance of MEMS devices. Vanadium oxide is not a standard material in IC technology, and it requires special process optimization to obtain the desired activation energy, resistivity, and noise [3]. Using a bilayer of a metal and a dielectric [6] can improve reliability, but this will be at the cost of process complexity. In general, the performance of a wide variety of MEMS devices can be optimized using either polycrystalline silicon (poly Si) or polycrystalline silicon-germanium (poly Si1-xGex) as a structural layer due to their superior mechanical and thermal properties [7, 8], high quality factor [9], and compatibility with standard fabrication processes. Poly Si1-xGex is considered an attractive alternative to poly Si, especially for low-temperature applications due to its lower transition temperature from amorphous to polycrystalline [10, 11] and its lower electrical resistivity [12]. Furthermore, the thermal conductivity of 91

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Si1-xGex is lower than that of poly Si, as the phonon scattering is mainly affected by the Ge atoms. The minimum value for thermal conductivity is obtained for a Ge content around 30% [13], and it is a factor of six lower than that of Si [14]. The deposition and crystallization behavior of Si1-xGex alloys prepared by LPCVD, PECVD, and rapid thermal chemical vapor deposition (RTCVD) is widely investigated by many groups [10, 15–23]. The early motivation for these studies was to develop a tunable-work-function gate-electrode material for CMOS transistors. The incorporation of Ge into heavily doped p-type poly Si causes the gate work function to be noticeably reduced, allowing both PMOS and NMOS surface channels to be realized [24, 25]. Silicon germanium was attractive for the low-temperature fabrication of high-performance thin-film transistors on glass substrates for flat-panel display applications, where the processing temperature should be limited below 550°C, thereby avoiding problems associated with glass shrinkage and warpage [26, 27]. Moreover, the capability of Si1−xGex to absorb solar radiation falling in the near infrared improves the efficiency of solar cells [28]. For all these applications the processing temperature is 500°C or higher, and the main objective is to optimize the electrical properties at this temperature, or to tune the energy band gap by either varying the germanium content, or controlling the value of strain in case of heterojunctions. Recently, the application of LPCVD and PECVD poly Si1-xGex films as structural and sacrificial layers for surface micromachining was investigated [29–35]. For these studies, the deposition temperature was reduced to 400°C to achieve compatibility with standard CMOS backend and at the same time minimize the mean stress and stress gradient to realize flat suspended structures at such low temperature. The mechanical properties of poly Si1-xGex films were found to be broadly similar to those of poly Si films. For poly Ge, the ratio of Young’s modulus, E, to the material density, , is E / = 130 GPa / 5330 kg/m3 = 24 × 106 m2/s2, which is about one-third that of silicon. In addition, poly Ge has low internal dissipation and high fracture strength, making it more than adequate as a mechanical material for many MEMS applications [36]. Thus, alloying silicon and germanium yields a material combining the superior properties of both materials. This chapter starts by providing practical guidelines for determining the actual wafer temperature during the deposition of the different MEMS layers on top of prefabricated electronics. Section 4.3 investigates the consequences of reducing the deposition temperature to a CMOS backend compatible limit and how the different deposition parameters can be optimized to maximize the growth rate. The electrical conduction mechanism in poly Si1-xGex is discussed in Section 4.4. The electrical conductivity depends on the doping type, method of introducing dopants (either ion implantation or in situ doping), and the doping activation temperature. This issue is discussed in Section 4.5. The dependence of electrical noise on Ge content, deposition conditions, and doping type is

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investigated Section 4.6. For MEMS applications such as thermal infrared detectors and thermocouples, the active element should be thermally isolated from the substrate, and accordingly, the thermal conductivity of the active element is an important issue that might dramatically affect the functionality of the device. An attractive feature of silicon germanium is its low thermal conductivity compared to silicon. Section 4.7 gives an overview of the different factors affecting the thermal conductivity and the experimental determination of this physical quantity for Si1-xGex. Finally, Sections 4.8 and 4.9 present the effect of deposition conditions, annealing temperature, and Ge content on mean stress and stress gradient.

4.2 Actual Wafer Temperature It is important when post-processing MEMS on top of standard prefabricated electronics to determine the exact wafer temperature while depositing the different MEMS layers in order to avoid damaging the devices or interconnects that might exist on the wafer. In general, for single wafer systems, there is a difference between the reactor temperature set point and the actual wafer temperature. Such temperature difference depends on the type of reactor and the location of heaters with respect to the chuck. A simple method to determine the exact wafer temperature makes use of the strong dependence of the sheet resistance of phosphorus ion-implanted silicon on temperature. In this case phosphorus ionimplanted p-type Si wafers can be placed in the deposition system, at the required deposition pressure, for the necessary deposition period. Then the sheet resistance of these wafers is compared to that of similar wafers placed in a conventional furnace for the same time interval. The reason for using a conventional furnace as a reference is mainly because the actual wafer temperature can be accurately estimated, and hence, we can know to which temperature the measured sheet resistance corresponds. The diamonds in Figure 4.1 represent typical measurements for the average measured sheet resistance of a phosphorus ion-implanted Si wafer after being annealed in a conventional furnace for 30 minutes in nitrogen atmosphere at temperatures varying between 500°C and 650°C [32]. For a better sense of the difference between the exact wafer temperature and the reactor set temperature, it is instructive to refer to the squares in Figure 4.1, which represent the sheet resistance of phosphorus-implanted wafers placed in a single wafer CVD reactor for 30 minutes in a hydrogen flow at a pressure of 40 Torr and a temperature of 550°C or 600°C. It is clear that the difference between the reactor temperature and the wafer temperature increases by decreasing the reactor temperature. Depending on the type of reactor and the location of heaters with respect to the chuck, the temperature difference can vary between 25°C and 100°C.

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Post-Processing Techniques for Integrated MEMS 90 Reactor operated at 550°C

Sheet resistance (Ω/sq.)

88 86

Reactor operated at 600°C

84 82 80 78 76 74 450

500

550 600 Annealing temperature (°C)

650

700

Figure 4.1 Determination of the exact wafer temperature in a single wafer CVD reactor. Diamonds: sheet resistance of wafers placed in conventional furnace; squares: sheet resistance of wafers placed in CVD reactor. (From: [32].)

It should be noted that the above method is suitable for determining wafer temperatures as low as 500°C. For lower wafer temperatures it is better to use silicon wafers with integrated thermopiles to determine the exact wafer temperature, but this will require external connections out of the reactor to measure the voltage across the thermopiles, which might not be always feasible.

4.3 Growth Kinetics of Silicon Germanium In general, silicon germanium (Si1-xGex) thin films can be prepared by LPCVD or PECVD. The silicon gas source can be silane (SiH4), disilane (Si2H6), or dichlorosilane (SiH2Cl2), whereas germane in hydrogen (GeH4) is commonly used as the germanium gas source. The deposition rate and the germanium content depend mainly on the gas type and flow rate, deposition temperature, and pressure. In a typical MEMS process, the structural layer is deposited on top of a sacrificial layer, which is etched selectively at the end of the process. The high wet etch selectivity of silicon dioxide (SiO2) with respect to Si1-xGex makes this material a suitable sacrificial layer. Hence, it is instructive to study the growth kinetics of Si1-xGex on top of SiO2. To enhance nucleation and to improve adhesion of Si1-xGex to silicon dioxide, a thin Si layer (∼2 nm) is deposited prior to the silicon germanium deposition. This layer is deposited at the same temperature of Si1-xGex for a maximum period of 5 minutes. Accordingly, it should not have any impact on process economy or complication. Kamins et al. [16] investigated the effect of gas type, at atmospheric pressure, on the Ge content and growth rate. In this study 2% silane in H2, 2%

Silicon Germanium as an Attractive MEMS Material

95

disilane in hydrogen or dichlorosilane is used as the silicon gas source. The germanium gas source is 1% GeH4 in H2. For all depositions the silicon gas source flow rate is 20 sccm, whereas the GeH4 flow rate is varied. The deposition temperature is either 625°C or 700°C. Even though Figure 4.2 shows that, for the same Ge content and deposition temperature, the growth rate is significantly increased if disilane is used as the silicon gas source, it is much more expensive than silane, and so the latter is considered for low-temperature applications. Further inspection of Figure 4.2 shows that for the same gas type and Ge content, by decreasing the deposition temperature from 700°C to 625°C, the growth rate is reduced by one order of magnitude. As these temperatures are still too high for MEMS post-processing on top of standard CMOS wafers, it is instructive to refer to Figure 4.3, which demonstrates the impact of reducing the deposition temperature down to 470°C [32]. In this case the silicon gas source is pure SiH4, and 1% GeH4 in hydrogen is used as the Ge gas source. For all depositions the GeH4 flow rate is fixed to 200 sccm, whereas the SiH4 flow rate is varied. In general, reducing the deposition temperature from 600°C to 470°C reduces the growth rate of poly Si1-xGex (x < 1) by one order of magnitude. It is interesting to note that the growth kinetics of pure Ge are completely different than that of the Si1-xGex alloy. This is clear from the circles in Figure 4.3, which show that the growth rate of poly Ge is much lower than that of poly Si1-xGex and is slightly affected by reducing the deposition temperature. This is because the deposition of germanium is reaction-rate-limited for this temperature range [37, 38]. The higher growth rate measured for poly Si1-xGex can be explained by considering the total growth rate as the superposition of the silicon and germanium growth rate, while taking into consideration the catalytic effect the Si 2 H 6

700°C

Growth rate (nm/min)

40 SiH 4

30

SiH 2Cl

2

20

SiH 4

10

0

625°C Si 2 H 6

0

10

20 Ge content (%)

SiH2 Cl 2

30

40

Figure 4.2 Effect of Ge content and type of silicon gas source on the deposition rate of poly silicon germanium deposited at 625°C, or 700°C. (From: [16]).

96

Post-Processing Techniques for Integrated MEMS 140

Growth rate (Å/min)

120

Poly Si 0.67 Ge 0.33

100 Poly Si0.57 Ge0.43 80 60 40 20 Poly Ge 0 460

480

500 520 540 560 580 600 Average wafer temperature (°C)

620

Figure 4.3 Dependence of growth rate on wafer temperature and germanium content for a deposition pressure of 40 Torr. Circles: 100% Ge; stars: 43% Ge; diamonds: 33% Ge. (From: [32].)

germanium has on the silicon deposition. Germanium atoms present on the growth surface lower the hydrogen desorption energy and hence enhance the decomposition and adsorption of Si atoms [10, 23]. As the deposition temperature exceeds 580°C, Figure 4.3 shows that, in spite of the lower Ge content in poly Si0.67Ge0.33, its growth rate starts to be higher than that of poly Si0.57Ge0.43. As the reduction in the Ge content is achieved in this case by increasing the silane flow rate for a fixed germane flow rate, the increased growth rate is due to a shift in growth rate control from reaction rate limitation to mass transport limitation. The data displayed in Figure 4.3 shows that for deposition temperatures compatible with standard CMOS backend (≤ 500°C) the growth rate is lower than 1 nm/min. This fact imposes a constraint on the thickness of the MEMS structural layer. Hence, it is instructive to investigate the possibility of enhancing the growth rate. This can be achieved by increasing the deposition pressure, increasing the Ge content in the film, adding diborane to the deposition gases, or using PECVD. The effect of the deposition pressure is demonstrated in Figure 4.4, where it is clear that the growth rate is increased by almost one order of magnitude if the deposition pressure changes from 10 Torr to 760 Torr [32]. Reducing the deposition pressure, for the same gas flow rate, decreases the time for which the gas precursors are inside the deposition chamber, hence decreasing the growth rate. The decreased Ge content accompanying the pressure reduction is explained by the fact that reducing the deposition pressure enhances desorption of adsorbed hydrogen from the deposition surface and consequently there are more free sites for decomposition and adsorption of silicon atoms, and hence, the Ge content is decreased.

Silicon Germanium as an Attractive MEMS Material

80

50

60

48

40

46

20

44

0

5

10

20

50 100 200 Total pressure (Torr)

500

Germanium concentration (%)

52

Growth rate (Å/min)

100

97

42 1,000

Figure 4.4 Dependence of growth rate (squares) and germanium concentration (diamonds) on total pressure for a wafer temperature of 520°C. (From: [32].)

At this point, it should be noted that the major drawback of increasing the deposition pressure is the degradation of film uniformity over the wafer. This can be improved by increasing the hydrogen flow. However, this reduces the partial gas pressure of silane and germane, and consequently, the growth rate becomes slightly lower than the values reported in Figure 4.4. To assure compatibility with a broad range of standard CMOS backend, it is interesting to investigate the consequences of further reducing the deposition temperature to 400°C or even lower. At this temperature, the deposition rate is reaction-rate-limited and increasing the germanium content is expected to improve the growth rate. This can be explained by the fact that the presence of germanium atoms on the growth surface lowers the hydrogen desorption energy and consequently enhances the decomposition and adsorption of silicon atoms [10]. Figure 4.5 demonstrates the impact of varying the silane flow on both the germanium content and the growth rate of boron in situ doped Si1-xGex films deposited at 400°C [31]. The impact of adding diborane to the deposition gas sources is widely investigated [17, 27, 39, 40]. It is demonstrated that it enhances direct deposition of silicon germanium on top of silicon dioxide [27, 39], due to the preferential adsorption of boron on silicon dioxide, which ultimately facilitates the nucleation of both silicon and germanium. Also, it is demonstrated that the addition of diborane enhances the growth of fine-grained poly Si1-xGex with a carrier concentration of 8 × 1020 cm–3 at a deposition temperature of 500°C [17]. Furthermore, it is shown in [7, 36] that boron in situ doped poly Si1-xGex deposited at 450°C is suitable for fabricating MEMS on top of standard CMOS wafers due to its low as-deposited stress (10 MPa compressive) and good electrical conductivity (resistivity is as low as 1.8 mΩ.cm).

Post-Processing Techniques for Integrated MEMS 50

100

40

90

30

80

20

70

10

60

0

0

20

40

60 80 Silane flow (sccm)

100

Ge content (%)

Growth rate (Å/min)

98

50 120

Figure 4.5 Dependence of growth rate (diamonds) and Ge content (squares) on silane flow rate for boron in situ doped Si1-xGex deposited at 400°C and 2 Torr. (From: [31].)

By studying Figure 4.6, we notice that the introduction of diborane initially decreases the growth rate of Si0.11Ge0.89. This is due to the decrease in the partial pressure of germane, which decreases the probability that a germanium atom sticks to the substrate [38]. Further increase in the diborane flow enhances the growth rate as the boron atoms act as adsorption sites for both silicon and germanium atoms [18]. It is interesting to note that for 40 sccm of diborane, the growth rate of Si0.11Ge0.89 is almost doubled, as compared to the undoped film. On the other hand, for the same deposition temperature a significant increase in the growth rate can be achieved by PECVD. Comparing the diamonds and stars in Figure 4.7, it can be noticed that PECVD Si1-xGex (x > 40%), deposited at 400°C, has higher deposition rate than LPCVD Si1-xGex 35

Growth rate (Å/min)

30 25 20 15 10

0

10

20 30 1% Diborane flow (sccm)

40

50

Figure 4.6 Dependence of growth rate on 1% diborane flow rate for Si0.11Ge0.89 deposited at 400°C and 2 Torr. (From: [31].)

Silicon Germanium as an Attractive MEMS Material

99

80 450°C PECVD

500°C PECVD

70 Growth rate (Å/min)

60 50 40

400°C PECVD 600°C LPCVD

30

500°C LPCVD

20 10 0

0

10

20 30 Ge content (%)

40

50

Figure 4.7 Effect of deposition temperature and germanium content on the growth rate of LPCVD and PECVD Si1-xGex. (From: [41]. © 1995 American Institute of Physics. Reprinted with permission.)

deposited at 600°C [41]. For the same deposition conditions, plasma enhanced deposition yields smaller grains than thermal growth. This is because plasma deposition generates a high density of initial nucleation sites, which makes growing nuclei impinge upon each other at a faster rate, resulting in a smaller grain size. Furthermore, the hydrogen content in the PECVD films is high, which may result in voids when the film is exposed to temperatures higher than the deposition temperature. Another disadvantage of PECVD films is that the mean stress is much higher than the LPCVD ones, especially for p-type films deposited at 400°C [35]. This point will be discussed further in Section 4.8.

4.4 Conduction Mechanism in Polycrystalline Silicon Germanium The electrical properties of the MEMS active material are an important issue that dramatically affects the performance of the realized devices. Due to the similarity between poly Si1-xGex and poly Si, we can apply the models derived for poly Si to explain the conduction mechanism in poly Si1-xGex [42–49]. Accordingly, conduction in poly Si1-xGex can be considered as a thermally activated process with an activation energy that depends on the doping concentration, N, and the defect density, NT, at the grain boundaries. For low doping concentration the total number of carriers per unit area, N , in a grain of length ᐉ is much less than the number of traps, NT, per unit area at the grain boundary. If the energy levels of the traps are low enough, most of the carriers, provided by the active dopants, are trapped at the grain boundaries. Hence, a charge-depleted region will extend nearly over the entire grain and consequently no neutral region will exist. This will generate a barrier against charge transportation

Post-Processing Techniques for Integrated MEMS

Resistivity

100

Low doping

High doping Moderate doping

Critical doping (NT / l ) Doping concentration

Figure 4.8 Dependence of resistivity on doping concentration for polycrystalline materials. (After: [49].)

between different grains. Increasing the doping concentration (for doping levels < NT / ᐉ) will increase the barrier height, resulting in a relative increase in the resistivity, as shown schematically in Figure 4.8. This mechanism will continue until all the trapping levels are completely filled. This condition is realized for a doping concentration Ncritical = NT / ᐉ. For N > Ncritical, the number of trapped carries per unit area at the grain boundaries will remain constant and equal to NT. The added carriers will start to form a neutral region within the grain, thus reducing the barrier height and consequently the resistivity will start to decrease. This range of doping is referred to as moderate doping level (see Figure 4.8). At high doping levels, the barrier height is greatly reduced and the conductivity is similar to that of the crystalline material (about a factor of two lower because of reduced mobility). At very high doping dose, the resistivity levels off due to the solubility limit of the dopants. In general, the resistivity, , can be related to the activation energy across the barrier, Ea, by ρ = ρo e E a /kT

(4.1)

where o is the resistivity of the crystalline material, k is Boltzman’s constant, and T is the temperature in Kelvin. For some MEMS applications the temperature coefficient of resistance (TCR) of the active material is an important figure of merit that determines the

Silicon Germanium as an Attractive MEMS Material

101

performance of any temperature-sensitive device such as thermal infrared detectors and temperature sensors. It is interesting to relate this parameter to the material properties. The TCR is defined as the change in resistance per unit temperature and is expressed as TCR =

1 dR 1 dρ = R dT ρ dT

(4.2)

Ea kT 2

(4.3)

Substituting (4.1) into (4.2) yields TCR =

Thus, the TCR is directly proportional to the activation energy. Accordingly, if we need to have a material having high sensitivity towards temperature changes, it is recommended to use moderate doping (N ≅ Ncritical) as this corresponds to the maximum activation energy.

4.5 Electrical Properties of Polycrystalline Silicon Germanium The main objective of this section is to determine the consequences of reducing the processing temperature on doping activation and the electrical resistivity of p- and n-type silicon germanium thin films. In general, the electrical conductivity of poly SiGe can be controlled by adding donor atoms (phosphorus is commonly used) or acceptor atoms (usually boron) either by ion implantation or from gas phase during deposition (in situ doping). In spite of the fact that ion implantation is not the optimal choice for MEMS post-processing on top of standard prefabricated electronics, it is relevant for applications where different doping levels are required in the active material. Surface micromachined uncooled IR detectors are a good example that clarifies this issue (see Figure 4.9). In this case the active part of the device needs to be lightly doped in order to have high sensitivity for the incident radiation. The supports connecting the detector to the driving electronics, however, which are realized by the same material, need to be highly doped. This can be only achieved by combining ion implantation and in situ doping. Section 4.5.1 provides an overview of the characteristics of ion-implanted Si1-xGex under a wide range of thermal treatments and it specifies the minimum activation temperature that can be practically realized. The advantage of in situ doping is presented in Section 4.5.2. It is demonstrated that combining boron in situ doping with a high Ge content (∼65%) can reduce the processing temperature of the active MEMS material to 400°C or even lower.

102

Post-Processing Techniques for Integrated MEMS Active element (moderately doped) Supports (highly doped)

Substrate

Figure 4.9 Schematic diagram for surface micromachined MEMS device that requires several doping concentrations.

4.5.1

Characteristics of Ion-Implanted Polycrystalline Silicon Germanium

The electrical properties of heavily doped, ion-implanted, p- and n-poly Si1-xGex, with Ge content up to 56%, have been widely investigated [12, 50–53]. Figure 4.10 shows that the resistivity of boron ion-implanted Si1-xGex decreases with increasing the Ge content [50]. For low Ge contents (< 50%) the resistivity of phosphorus doped Si1-xGex decreases proportionally to the Ge content, and then it increases abruptly. For a better understanding of the behavior of the resistance for boron and phosphorus ion-implanted samples, it is instructive to refer to the dependence of carrier mobility and concentration on the Ge content, presented in Figure 4.11 [12]. By studying this figure, we conclude that the decreased resistance observed with the increased Ge content (for 20 Phosphorus doped film

10 Resistivity (mΩ.cm)

Boron doped film 5 2 1 0.5 0.2

0

10

20

30 40 Ge content (%)

50

60

Figure 4.10 Dependence of resistivity on Ge content for phosphorus and boron ionimplanted, 0.3-µm-thick Si1-xGex films deposited at 620°C and 0.2 Torr. Implantation dose is 4 × 1015 cm–2. Films were annealed at 900°C for 40 minutes. (From: [50], © 1994 IEEE. Reprinted with permission.)

Normalized carrier concentration (cm–3)

Silicon Germanium as an Attractive MEMS Material

103

1 Hole concentration

0.8

0.6

0.4 Electron concentration 0.2

0

0

0.1

0.2

0.3 0.4 Ge content (%) (a)

0.5

0.6

50

60

16 Hole mobility (cm2 .v–1 .s–1)

Hole mobility 14 12 Electron mobility

10 8 6

0

10

20

30 40 Ge content (%) (b)

Figure 4.11 (a) Normalized active carrier concentration, and (b) hole mobility of boron and phosphorus doped polycrystalline Si1-xGex films versus Ge content. Annealing temperature is 650°C and annealing time is 1.0 minute (From: [12].)

boron-doped samples) is due to the increase of both the hole mobility and the active carrier concentration. On the other hand, the increased resistance of the phosphorus-doped Si1-xGex films (x > 50%) is mainly due to the decreased carrier concentration with increasing the Ge content [Figure 4.11(a)], which is due to phosphorus segregation at the grain boundaries. Figure 4.12 gives an overview of the effect of annealing temperature on activating ion-implanted boron in poly Si1-xGex films deposited at 600°C [50]. At this temperature all the films are polycrystalline as-deposited. For the same annealing temperature, the resistivity decreases with increasing the Ge content, which is in agreement with the previous observation in Figure 4.10. In general,

104

Post-Processing Techniques for Integrated MEMS 50 Si

Resistivity (mΩ.cm)

30

Si 0.86 Ge 0.14

20

Si 0.74 Ge0.26 10 Si 0.48 Ge0.52 5

400

500

600 700 800 900 Annealing temperature (°C)

1000

1100

Figure 4.12 Effect of rapid thermal annealing on activating ion-implanted boron (dose 1015 cm–2) in 0.25-µm-thick Si1-xGex films deposited at 620°C and 0.2 Torr and annealed for 30 seconds. (From: [50]. © 1994 IEEE. Reprinted with permission.)

there is a noticeable dependence of resistivity on the annealing temperature, which decreases with increasing the Ge content. For a Ge concentration higher than 50%, the resistivity is almost independent of the annealing temperature, which indicates that all the dopants are activated at temperatures as low as 500°C. Another important consequence of increasing the Ge content is the enhancement of boron diffusion as illustrated in Figure 4.13 [53]. In addition, the solid solubility limit of boron in silicon germanium is shown to decrease exponentially with increasing Ge content up to 70%; it then drops rapidly by one order of magnitude by increasing the Ge content from 78% to 100%, as illustrated in Figure 4.14 [53]. It should be noted that the values reported for the solid solubility of boron in polycrystalline Si and polycrystalline Ge are close to that reported for single crystalline Si and Ge, respectively, which indicates that the grain boundaries do not have any effect on the solid solubility limit. The previous discussion was mainly devoted to heavily doped poly Si1-xGex, which is of great importance for MOS transistors, thin film transistors (TFTs), and bipolar junction transistors (BJTs). The recent developments of sensors and the evolution of the MEMS technology required moderate doping levels (∼1013 cm–2) [54]. Sedky et al. [17] investigated the dependence of sheet resistance and TCR on boron ion-implantation dose for poly Si0.74Ge0.26 deposited at 650°C and atmospheric pressure (AP). For this study, Si0.74Ge0.26 samples are boron implanted at a fixed energy of 75 KeV by a dose varying from 1011 to 1015 boron/cm2 and annealed at 850°C for 1 hour. The behavior of sheet resistance and TCR versus the implant dose is reported in Figure 4.15. The general

Silicon Germanium as an Attractive MEMS Material

Chemical concentration (cm–3)

1E+22

105

Ge

1E+21 Si 0.52 Ge 0.48

1E+20

Si0.22 Ge 0.78

1E+19 1E+18 Si

1E+17 1E+16

Si 0.73 Ge0.27 0

100

200 300 Depth (nm) (a)

400

500

Chemical concentration (cm–3)

1E+21 Si

3E+20

Si 0.73 Ge 0.27

1E+20 3E+19 1E+19

Ge

Si0.52 Ge0.48

3E+18 1E+18 3E+17

0

100

200 300 Depth (nm) (b)

400

500

Figure 4.13 Dependence of boron diffusion on the Ge content: (a) samples annealed at 800°C; (b) samples annealed at 900°C. (From: [53]. Reproduced by permission of The Electrochemical Society, Inc.)

trend is similar to the one observed in poly Si [49]. We can distinguish a low doping region where the sheet resistance is doping independent, a transition region where sheet resistance sharply decreases with the increase of doping, and a third region where low values of sheet resistance are obtained. We note that the sheet resistance starts to decrease steeply when the doping exceeds 1013 boron/cm2. In poly Si also, the decrease of resistivity starts at these doping levels, which indicates that grain size and grain defect density are similar in the two materials. At this point, it is instructive to compare the sheet resistance of poly Si1-xGex to that of poly Si, for the same boron ion-implantation dose (Table 4.1). The high sheet resistance observed for poly Si deposited at AP, 850°C, and ion

106

Post-Processing Techniques for Integrated MEMS 3E+20

Solid solubility limit (cm–3)

1E+20

900°C

3E+19 1E+19

800°C

3E+18 1E+18

3E+17

0

20

40 60 Ge content (%)

80

100

Figure 4.14 Solid solubility limit of boron in Si1-xGex at different annealing temperatures. (From: [53]. Reproduced by permission of The Electrochemical Society, Inc.)

5 1E+4 1E+3

1

1E+2 0.2

1E+1 1E+0 1E-1 0.1

TCR (%)

Sheet resistance (KΩ/square)

1E+5

0.05 1

10 100 Dose (×1012 boron/cm2)

1000

0.02

Figure 4.15 Dependence of sheet resistance and TCR on boron ion-implantation dose for AP Si0.74Ge0.26 deposited at 650°C and annealed at 850°C for 1 hour. (From: [14]. © 1999 Institue of Electrical Engineers of Japan. Reprinted with permission.)

implanted by 1.5 × 1013 boron/cm2 (third column in Table 4.1), indicates that it is still in the low level doping region. Meanwhile, for the same doping dose, AP poly Si0.74Ge0.26 is in the moderate doping region, where the TCR varies strongly with doping concentration (cf. Figure 4.15). Increasing the boron doping dose to 3 × 1013 boron/cm2 results in the data reported in Table 4.1, which shows that the resistivity of AP poly Si0.74Ge0.26 becomes more than a factor of three lower than that of AP poly Si, whereas, the TCR of both materials is almost the same.

Silicon Germanium as an Attractive MEMS Material

107

Table 4.1 Dependence of Sheet Resistance and TCR on Boron Doping Doses for Poly Si0.74Ge0.26 Deposited at 650°C and 760 Torr, and Poly Si Deposited at 850°C and 760 Torr Sheet Resistance

TCR

Poly Si74Ge26

Poly Si

Poly Si74Ge26

Poly Si

cm

350 KΩ/Sq.

4.3 MΩ/Sq.

−2.54%

−3.29%

cm−2

173 KΩ/Sq.

585 KΩ/Sq.

−2.1%

−2.2%

19.5 KΩ/Sq.

24.7 KΩ/Sq.

−0.96%

−1.1%

Doping Dose −2

−2

cm

Source: [14].

4.5.2

Characteristics of In Situ Doped Polycrystalline Silicon Germanium

Up until now, we have considered the characteristics of ion-implanted Si1-xGex films deposited at 550°C or higher, which are of great interest for thin film transistors and NMOS and PMOS. The demand for integrating MEMS on top of standard prefabricated driving electronics raised the need for decreasing the dopant activation temperature to a limit compatible with the CMOS backend. Based on the discussion presented in Chapter 2, this limit is defined to be 520°C, for a maximum period of 90 minutes, for a standard 0.35-µm CMOS with Al interconnects and tungsten plugs. For more advanced CMOS technologies with low K dielectrics, this limit is expected to be reduced to 400°C or lower. To meet this requirement, dopants should be added from the gas phase while depositing the film, as ion implantation always requires post-annealing to activate the implanted dopants and to recover the damage caused by implantation. The resistivity of boron and phosphorus in situ doped poly Si0.57Ge0.43 deposited at 40 Torr and a wafer temperature of 520°C and annealed at 520°C or 650°C for 30 minutes in nitrogen atmosphere is displayed in Figure 4.16 [55]. By investigating this figure, we notice that the resistivity of boron in situ doped poly Si0.57Ge0.43 is almost independent of the annealing temperature, which means that boron dopants can be activated at 520°C for a Ge content as low as 43%. On the other hand, the stars and circles in Figure 4.16 show that there is a noticeable change in the resistivity of phosphorus in situ doped poly Si0.57Ge0.43 with the annealing temperature. The observed increase in resistivity might be due to doping segregation at the grain boundaries [56, 57]. Also, it can be noticed that for the same doping concentration, the resistivity of boron in situ doped poly Si0.57Ge0.43 is one order of magnitude lower than that of phosphorus doped samples.

108

Post-Processing Techniques for Integrated MEMS 1E+4

Phosphorus 650°C

Resistivity (Ω.cm)

1E+3

520°C

1E+2 1E+1 1E+0

520°C Boron 650°C

1E–1 0.3

1

3 10 30 100 300 Doping concentration (×1017 cm–3)

1,000

Figure 4.16 Dependence of resistivity on in situ doping concentration of RPCVD poly Si0.43Ge0.57 deposited at 520°C. Squares: boron in situ doping annealed at 520°C; diamonds: boron in situ doping annealed at 650°C; stars: phosphorus in situ doping annealed at 520°C; circles: phosphorus in situ doping annealed at 650°C. (From: [55].)

Figure 4.17 demonstrates the possibility of activating boron in situ doping, at a CMOS backend compatible temperature for different germanium concentrations of poly Si1-xGex deposited at 400°C and 2 Torr [55]. It is clear from the figure that for Ge concentrations higher than 70%, the resistivity is constant independent of the annealing temperature. The minimum resistivity is 0.5 mΩ.cm, which corresponds to a Ge content of 90% (circles in Figure 4.17). Decreasing the Ge content below 70% creates a significant increase in the resistivity of the as-grown material, which decreases by increasing the annealing

100 10 Resistivity (Ω.cm)

Poly Si 0.44 Ge 0.56 1 Poly Si 0.35 Ge0.65 0.1 0.01

Poly Si 0.11 Ge0.89

Poly Si0.25 Ge 0.75

0.001 0.0001 350

400

450 500 550 600 Annealing temperature (°C)

650

700

Figure 4.17 Effect of annealing temperature on resistivity of boron in situ doped LPCVD Si1-xGex deposited at 400°C and 2 Torr. (From: [55].)

Silicon Germanium as an Attractive MEMS Material

109

temperature (squares and diamonds in Figure 4.17). This increase is due to the presence of an amorphous phase, which increases by decreasing the Ge content [31]. Annealing results in crystallization and this explains the decrease in resistivity. For Ge concentrations lower than 60%, the crystallization temperature is higher than 550°C (as inferred from the data reported in Figure 4.17). Thus, for low-temperature applications (∼400°C), it is recommended to keep the Ge content higher than 65%. The effect of phosphorus in situ doping on poly Si0.6Ge0.4 deposited at 400°C is presented in Figure 4.18 [7]. The high sheet resistance measured for the as-grown material indicates that this material is amorphous. Annealing this film at 550°C is not enough to crystallize this film; we need to go as high as 650°C to do so, as clear from the drop in resistivity observed in Figure 4.18. In spite of the low resistivity reported for LPCVD Si1-xGex deposited at 400°C, the growth rate is extremely low, as was discussed in the previous section. Hence, it is instructive to investigate the electrical resistivity of PECVD Si1-xGex deposited at relatively low temperatures (∼400°C). By analyzing Figure 4.19 we notice that for the same boron concentration, the resistivity of as-grown, boron in situ doped PECVD Si0.31Ge0.69 is two orders of magnitude higher than that of LPCVD Si0.35Ge0.69 having the same boron concentration [35]. This indicates that the PECVD films are amorphous whereas the LPCVD ones are polycrystalline. The PECVD films become fully polycrystalline at temperatures as high as 600°C. Thus, in spite of the economical growth rate of the PECVD films, the doping activation thermal budget is not compatible with the CMOS backend. In the next chapter we investigate different techniques that can locally activate the dopants without having any thermal impact on the underlying layers. 1E+7

Sheet resistance (Ω/Sq.)

1E+6 1E+5

650°C 550°C

1E+4 1E+3

750°C

1E+2 1E+1 1E+0

0

50

100

150 200 250 Annealing time (sec)

300

350

Figure 4.18 Effect of rapid thermal annealing temperature and duration on sheet resistance of phosphorus in situ doped LPCVD poly Si0.6Ge0.4 deposited at 400°C. (From: [7].)

110

Post-Processing Techniques for Integrated MEMS 1,000

Resistivity (Ω.cm)

100

PECVD Si 0.31Ge 0.69 (30 W)

10 1 PECVD Si 0.31 Ge 0.69 (50 W)

0.1 0.01 0.001

0.0001 350

LPCVD Si 0.35 Ge0.65 400

450 500 550 Annealing temperature (°C)

600

650

Figure 4.19 Effect of annealing temperature on the electrical resistivity of boron in situ doped PECVD and Si1-xGex deposited at 400°C and 2 Torr. (From: [35]. © 2003 IEEE. Reprinted with permission.)

4.6 Electrical Noise in Polycrystalline Silicon Germanium Random noise plays an important role in the performance of MEMS. Noise sources might arise from the material, physical phenomena to be detected (in case of a sensor) or from the driving electronics. In this section, we discuss only the major noise sources associated with the material, namely, the Johnson noise and the low frequency (1/f ) noise. The Johnson noise arises from the random motion of free carriers within any resistive material. The RMS of the voltage fluctuation associated with the Johnson noise, VJ, is [58] V j = A 4 kTρ∆f e

(4.4)

where A is a constant which depends on the device geometry, k is Boltzman’s constant, T is the temperature in Kelvin, is the material resistivity, and ∆fe is the electric bandwidth. In any resistor it is possible to measure a noise component that decreases as 1/f γ(where 0 < γ < 0.5) and which adds up to the Johnson noise. Although its origin is still a matter of debate, it is well described by an empirical expression by Hooge [59]: V 1/ f = KV b

ρ wLtf

(4.5)

Silicon Germanium as an Attractive MEMS Material

111

where K, is a constant that depends on the type of material, Vb, is the bias voltage, is the material resistivity, w, L, and t are the width, length, and thickness, respectively, of the active material. The total noise, Vn, is the RMS of these two dominate noise components and it is given by V n = V j2 + V 12/f

(4.6)

In general, the low frequency (1/f ) noise depends on the material structural properties, doping type, and germanium concentration. The dependence of noise on structural properties is studied for poly Si0.74Ge0.26 deposited at 650°C and atmospheric pressure (referred to as AP Si0.74Ge0.26) or 625°C and a reduced pressure of 40 Torr (RP Si0.78Ge0.22) [60]. Electrical noise can be measured by connecting a load resistor, having the same resistance of the poly SiGe sample, in series with the sample under test. The circuit can be biased by a dc source having a voltage between 1.5V and 8V. Then, the voltage across the load resistor is sent to the input of a dynamic signal parameter analyzer, which is used to measure the noise power spectrum. To study the influence of the surrounding media on the measured noise, it is interesting to perform the measurements once under atmospheric conditions and then repeat the same measurements under vacuum. It is also recommended to check the reliability of measurements by verifying that the expected value of the Johnson noise is obtained if the poly Si1-xGex sample is replaced by another standard resistor. This shows if there is any threshold in the measurements. Figure 4.20 displays the dependence of noise on frequency for 1-µm-thick poly Si1-xGex samples having lateral dimensions of 50 µm × 50 µm. The samples are deposited at 40 Torr and 625°C (RP Si0.78Ge0.22) or 760 Torr and 650°C (AP Si0.74Ge0.26) [60] and then ion implanted by different boron doses and annealed at 650°C for 1 hour. It is clear from this figure that there is a significant 1/f noise component, which levels down to the Johnson noise. Also, for the same material it can be noticed that the 1/f noise scales with the square root of the resistivity [compare, for instance, the diamonds and circles in Figure 4.20(a)]. The comparison of Figure 4.20(a) and 4.20(b) shows that the noise is larger for RP Si0.78Ge0.22. As the 1/f noise depends on generation and recombination of carriers in surface energy states and density of surface states [61], the higher noise measured for RP poly Si0.78Ge0.22 indicates that the surface defect density in this material is higher than that of AP poly Si0.74Ge0.26, which is probably due to the different arrangement of nonsaturated bonds on the surface. To understand the effect of the Ge content on the 1/f noise, it is instructive to refer to the noise measurements displayed in Figure 4.21, which

112

Post-Processing Techniques for Integrated MEMS 5 2

Noise voltage (µV/ Hz)

Noise voltage (µV/ Hz)

ρ = 4.43 Ω. cm ρ = 0.9 Ω. cm

1

ρ = 0.45 Ω. cm 0.2

0.05

ρ = 1.9 Ω. cm 0.5

ρ = 0.97 Ω. cm

0.2

0.05

RP SiGe 0.01

ρ = 8.64 Ω. cm

AP SiGe 1 Frequency (kHz) (a)

100

0.01

1 Frequency (kHz) (b)

100

Figure 4.20 Dependence of total noise on frequency for Si1-xGex films having different resistivity: (a) RP poly Si0.78Ge0.22 (circles: ρ = 4.43 Ω.cm; diamonds: ρ = 0.9 Ω.cm; stars: ρ = 0.45 Ω.cm); (b) AP poly Si0.74Ge0.26 (circles: ρ = 8.64 Ω.cm; diamonds: ρ = 1.9 Ω.cm, stars: ρ = 0.97 Ω.cm). (From: [60]. © 1999 Elsevier. Reprinted with permission.)

Noise voltage (µV/ Hz)

2 AP Poly Si

1 0.5

0.2 AP Poly Si0.26 Ge 0.74 0.1 1

5

20 Frequency (Hz)

200

Figure 4.21 Dependence of noise voltage on frequency for AP poly Si0.74Ge0.26 deposited at 650°C (diamonds), and AP poly Si deposited at 850°C (stars). (From: [14].)

compares noise in AP poly Si0.74Ge0.26 deposited at 650°C to that of AP poly Si deposited at 850°C and 760 Torr [14]. In this case poly Si films are prepared in the same reactor used for the SiGe depositions. The deposition temperature and pressure of poly Si are selected to yield the same grain microstructure of AP poly Si0.74Ge0.26 to eliminate the effect of structural properties on noise measurements [29]. Furthermore, both films are ion implanted with the same boron

Silicon Germanium as an Attractive MEMS Material

113

dose (9 × 1013 boron/cm2). Thus, the difference in noise spectrum observed in Figure 4.21 is mainly due to the presence of the germanium atoms. The 1/f noise in AP poly Si is a factor of two higher than that of AP poly Si0.74Ge0.26, which indicates that the presence of Ge reduces the surface defect density. Now, it is interesting to investigate the effect of the doping type on noise. To achieve this goal we consider boron and phosphorus in situ doped RP poly Si0.57Ge0.43 deposited at 520°C and 40 Torr [55]. Figure 4.22 shows that in spite of the lower resistivity of the phosphorus doped samples, the noise measured for these samples is higher than that of boron doped ones. This is in agreement with what was reported for lowly doped poly Si [62]. Furthermore, the noise voltage varies inversely with the square root of frequency, which indicates a dominant 1/f noise. To have a clearer idea about the origin of noise, the dependence of noise (measured at 1 Hz) on resistivity is fitted, as demonstrated in Figure 4.23, and it is found to vary proportionally to the square root of resistivity for both phosphorus and boron in situ doped samples. It is also noticed that the noise voltage (measured at 1 Hz) varies inversely with the square root of the spacing between contacts. All these observations confirm that the measured noise is a 1/f noise. Based on the experimental data displayed in Figure 4.23, it is concluded that noise in phosphorus and boron doped poly Si0.57Ge0.43 samples can be expressed respectively by (4.7) and (4.8) [55]: V n = 12 . × 10 −3

ρ WLtf

( µV

/ Hz

)

(4.7)

P, ρ = 0.65 Ω.cm

10

1/2

Noise spectrum (µV/Hz )

30

P, ρ = 4.65 Ω.cm

3 1 0.3

B, ρ = 27.3 Ω.cm

0.1 0.03 0.01 1E+0

B, ρ = 9.6 Ω.cm

1E+1

1E+2

1E+3 1E+4 Frequency (Hz)

1E+5

1E+6

Figure 4.22 Dependence of noise voltage on frequency for boron and phosphorus in situ doped poly Si0.57Ge0.43 deposited at 520°C. Resistivity is indicated on the different graphs. Measurements have been performed on 500-µm-wide, 50-µm-long, and 400-nm-thick sheets. (From: [55].)

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Post-Processing Techniques for Integrated MEMS 140

Noise spectrum (µV/Hz 1/2)

120 100

Phosphorus in situ doped

80 60 Boron in situ doped

40 20 0

0

2

4

6 8 ρ1/2 (Ω.cm) 1/2

10

12

Figure 4.23 Dependence of noise (measured at 1 Hz) on the square root of resistivity of phosphorus (diamonds) and boron (squares) in situ doped poly Si0.57Ge0.43 films deposited at 520°C. Measurements have been performed on 500-µm-wide, 50-µm-long, and 400-nm-thick sheets. (From: [55].)

V n = 10 −4

ρ WLtf

( µV

/ Hz

)

(4.8)

where W, L, and t are the width, length, and thickness of the structure measured in centimeters.

4.7 Thermal Properties of Silicon Germanium The thermal conductivity of the MEMS active material is an important parameter especially for applications where the active element should be thermally isolated from the substrate. The most attractive feature in using poly Si1-xGex is that its thermal conductivity is at least a factor of five lower than that of poly Si [63]. To clarify this issue, we consider the heat transport mechanism in lowly doped semiconductors, which is mainly due to phonons, as the electronic contribution is negligible. The observation of a finite thermal conductivity is due to the existence of different process of phonon scattering, the most important of which are: 1. Phonon-phonon scattering (two phonons interact to give a third phonon, the total momentum is either conserved or changed by a reciprocal lattice vector) [64]; 2. Phonon scattering due to interaction with electrons (or holes) [64];

Silicon Germanium as an Attractive MEMS Material

115

3. Point defect scattering [65]; 4. Grain boundary scattering [66]. Mechanisms (1) and (2) are always present and their discussion is not relevant for our purposes. Mechanism (3) is very important. This kind of scattering is due to the presence of foreign atoms in substitutional positions in the lattice. They are capable of hindering the propagation of elastic waves in the solid. As an example, this mechanism is responsible for the decrease of thermal conductivity when dopants are added (notice that at high doping levels, the thermal conductivity increases again due to the increase of the electronic contribution). Moreover, this mechanism reduces the thermal conductivity of alloys, which is the case for silicon germanium (germanium atoms can be considered as point defects in the silicon lattice). The minimum thermal conductivity of poly Si1-xGex is obtained at a germanium content of 30% [45]. Mechanism (4) is also very important; it is thought to be responsible for the lower thermal conductivity of poly Si with respect to c-Si [67]. The thermal conductivity of poly Si0.74Ge0.26 can be measured in terms of the thermal time constant and thermal capacity of surface micromachined infrared detectors [68], which are basically thermally isolated suspended structures connected to the substrate by thin long supports. To determine the thermal time constant, , of the device, the detectors are mounted in a vacuum chamber (to eliminate heat lost by convection) and exposed to the radiation of a black body through a filter that limits the wavelength of the incident radiation between 8 and 16 µm. The radiation of the black body is chopped and the signal generated by the incident IR power is measured as a function of the chopper frequency, f, and plotted in Figure 4.24 for different devices [54]. The thermal 1

τ=1.5 ms

Normalized signal

0.5 τ=23 ms 0.2

τ=10 ms τ=8 ms

0.1

τ=5 ms 0.05

0.02

τ=3 ms 10

100 Chopper frequency (Hz)

1,000

Figure 4.24 Dependence of detected signal on chopper frequency for devices having different thermal time constants. (From: [54]. © 1999 IEEE. Reprinted with permission.)

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time constant is obtained by fitting the detected signal using V ( f ) = V DC / 1 + ( 2 πf τ) 2 . The thermal conductance, G, is related to the thermal capacity, C, of the device, and the thermal time constant, , by G = C/ . Finite element analysis can be used to relate the thermal conductance of the device to the thermal conductivity of the material (g). To simplify the analysis, we can assume uniform heat generation all over the active area of the IR detector. Figure 4.25 displays the simulation results for structures having different support dimensions. It is clear from Figure 4.25(a) that for wide (5 µm) and short (5 µm) supports, there is a large temperature drop on the active area. When the supports become thinner and longer, the thermal gradient appears only along the supports, as clear from Figure 4.25(b, c), and the thermal conductance can be related to the thermal conductivity, g, by G = gA/l, where A and l are respectively the cross sectional area and the length of the supports. The thermal conductivity of poly Si74Ge26 is computed by fitting the measured thermal conductance using finite element analysis. The average thermal conductivity of poly Si0.74Ge0.26 is 2.9 W/mK. Van Gerwen et al. [69] confirmed this value for high boron doping doses. This value is a factor of six lower than that reported for poly Si (18 W/mK [67]). Thus, for the same device geometry the performance of poly Si0.74Ge0.26 device is at least a factor of six higher than that realized by poly Si.

4.8 Stress in Polycrystalline Silicon Germanium As previously discussed in Chapter 3, mean stress and stress gradient are two important parameters that dramatically affect the functionality of surface micromachined structures. The main objective of the following subsections is to give an overview of the dependence of stress on deposition conditions, annealing temperature, and Ge content.

(a)

(b)

(c)

Figure 4.25 (a–c) Finite element analysis results for 50 × 50 µm surface micromachined infrared detectors having different support geometry. (From: [14]. © 1999 Institute of Electrical Engineers of Japan. Reprinted with permission.)

Silicon Germanium as an Attractive MEMS Material 4.8.1

117

Effect of Deposition Conditions and Annealing Temperature

The structural properties of thin films are significantly affected by the deposition temperature and pressure. For the same deposition temperature, the deposition pressure can be tuned to control the mean stress of the MEMS structural layer to the desired value. To clarify this issue, let us consider AP poly Si0.74Ge0.26 deposited at 650°C and 760 Torr. Figure 4.26 shows that the stress in the as-grown material is compressive (∼ −145 MPa). This compressive stress is almost a factor of three lower than that of typical LPCVD poly Si deposited at a pressure of 0.1 Torr and at a temperature of 620°C [70]. Reducing the deposition pressure of poly Si0.78Ge0.22 to 40 Torr, converts the mean stress from compressive to a relatively low tensile value of 60 MPa (as clear from the squares in Figure 4.26). The compressive stress reported for as-grown AP poly Si0.74Ge0.26 might be due to highly disordered grain boundaries, which are typically associated with the dominant {220} texture observed for this material [71]. The low mean stress measured for RP poly Si0.78Ge0.22 is due to the presence of both randomly oriented and columnar grains. The tensile stress indicates that the layer is deposited in the amorphous state and then crystallizes in the furnace. Crystallization results in contraction against the boundary constraints, inducing a tensile stress, which can be approximated as the radial traction (applied at the edge of the imaginary unconstrained crystallized film) required to restore it to its original amorphous diameter. To have an idea of the effect of Ge on stress, it would be interesting to compare mean stress of Si1-xGex to that of Si having the same grain microstructure. It is found that depositing Si at 850°C and 760 Torr has the 200 RP Poly Si 0.78 Ge 0.22

Tensile stress

Stress (MPa)

100

0 AP Poly Si 0.74 Ge 0.26

–100 Compressive stress –200 500

600

700 800 900 Annealing temperature (°C)

AP Poly Si 1000

1100

Figure 4.26 Dependence of mean stress in poly Si1-xGex on the deposition conditions and annealing temperature. (From: [29]. © 1998 IEEE. Reprinted with permission.)

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same microstructure as that of Si0.74Ge0.26 deposited at 650°C and 760 Torr [29]. The diamonds in Figure 4.26 show that stress in as-grown poly Si is similar to that of as-grown AP poly Si0.74Ge0.26 confirming that the structural properties of the two materials are the same. Thus, in this case the presence of 26% Ge reduced the thermal budget by 200°C. It is shown later that further increase in the Ge content can dramatically reduce the thermal budget. As for the dependence of mean stress on the annealing temperature, it is clear that the stress of RP poly Si0.78Ge0.22 is nearly independent of this parameter. This is consistent with the fact that only slight changes are brought about to the structure of the film, by annealing, as determined from X-ray diffraction (XRD) patterns and transmission electron microscopes (TEM) cross-sections [29]. Meanwhile, the stress of AP poly Si0.74Ge0.26 strongly depends on annealing. By increasing the annealing temperature, it starts to decrease due to the motion of dislocations in the direction of the stress gradient [72]. At temperatures close to 950°C, the stress becomes tensile; this is due to recrystallization, which, as we have already discussed, increases the tensile stress. As for AP poly Si, the decrease in stress due to the motion of dislocations is observed, but the stress does not become tensile as poly Si recrystallization occurs only above 1,050°C [49]. 4.8.2

Impact of Reducing the Deposition Temperature

The main objective of the previous discussion was to highlight the major differences between poly Si1-xGex and poly Si and to demonstrate the effect of the deposition pressure and that of introducing Ge on reducing the thermal budget. As our aim is to develop a material compatible with standard CMOS backend, it is instructive to investigate the consequences of reducing the processing temperature of poly Si1-xGex on mean stress. As we are interested in polycrystalline MEMS structural layers, reducing the deposition temperature implies increasing the Ge content to preserve a polycrystalline structure. Accordingly, if it is desired to keep the Ge content lower than 50%, the deposition temperature cannot be dropped below 470°C. In this case the mean stress depends strongly on the deposition temperature, as clear from Figure 4.27. By analyzing this figure we notice that mean stress in as-grown poly Si1-xGex, deposited at 40 Torr, is always tensile [32]. Mean stress increases with increasing the deposition temperature [notice that for the deposition temperature range under consideration Rutherford back scattering (RBS) did not show any significant change in the Ge content for the same silane and germane flow rates]. As stress could be related to texture [70], the reported increase in stress might be explained by the significant textural changes observed by XRD [32]. It is interesting to note that for poly Si0.57Ge0.43, deposited at an actual wafer temperature of 520°C, the stress is 120 MPa tensile. This stress is low enough to use the as-grown material for realizing

Silicon Germanium as an Attractive MEMS Material 300

119

Poly Si 0.67 Ge 0.33 Poly Ge

Stress (MPa)

250

200 Poly Si 0.57 Ge 0.43 150

100 540

560

580 600 Deposition temperature (°C)

620

640

Figure 4.27 Effect of varying the Ge content and the deposition temperature on mean stress of poly Si1-xGex. (From: [32].)

surface micromachined structures, as demonstrated in Figure 4.28 [32]. Thus, this material, with a Ge content below 50%, can be used for post-processing MEMS on top of CMOS and might not introduce any damage to the driving electronics as predicted by the analysis presented in Chapter 2. At this point we would like to note that the stars in Figure 4.27 show that stress in pure Ge behaves differently as a function of the deposition temperature. As the deposition temperature is increased, stress in pure germanium decreases, which is believed to be due to annealing out of defects and/or motion of dislocations as XRD analysis showed almost no changes in texture.

20 µm

Figure 4.28 Surface micromachined infrared detectors realized by 370-nm-thick poly Si0.57Ge0.43 deposited at 520°C and 40 Torr. Device lateral dimensions are 60 × 60 µm. (From: [32].)

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On the other hand, the optimal Ge concentration, which yields the minimal tensile stress in poly Si1-xGex deposited at 400°C, can be determined by comparing the squares and diamonds in Figure 4.29 [8]. For Ge contents lower than 60%, stress does not change with annealing temperature up to 520°C. As the Ge content increases, annealing at 520°C results in structural changes as inferred from the change in stress. Also, it is clear that the stress in the material deposited at 400°C decreases for high Ge contents (> 70%). This is mainly due to the development of the polycrystalline structure: the grains tend to be V-shaped, and this explains the shift of the stress towards compressive for Ge contents higher than 80%. As we are interested in low tensile stress achieved directly from the as-grown material, then we can consider films having a concentration either around 50% or around 70%. But, since Figure 4.17 showed that as-grown or annealed Si1-xGex films with ∼50% Ge have high resistivity, these films are amorphous and will be excluded. Poly Si1-xGex with ∼70% Ge seems to be a more suitable candidate. In the next section we investigate the stress gradient in this material and how it can be eliminated. 4.8.3

Stress in PECVD Silicon Germanium

It was demonstrated in Section 4.3 that depositing Si1-xGex films by PECVD increases the growth rate dramatically, especially at low temperatures (∼400°C). Accordingly, it is interesting to have an idea about mean stress in thin films 300

Mean stress (MPa)

200 RP poly SiGe deposited at 520°C

100 0 –100 Poly SiGe annealed at 520°C

–200 –300 20

40

Poly SiGe deposited at 400°C

60 80 Ge content (%)

100

120

Figure 4.29 Dependence of mean stress on Ge content. Stars: as-grown RP poly Si1-xGex deposited at 520°C; squares: as-grown, boron in situ doped, poly Si1-xGex deposited at 400°C; diamonds: boron in situ doped poly Si1-xGex deposited at 400°C and annealed at 520°C for 30 minutes. (From: [8]. © 2002 Elsevier. Reprinted with permission.)

Silicon Germanium as an Attractive MEMS Material

121

deposited by this technique. The dependence of stress on annealing temperature and plasma power of boron in situ doped PECVD Si0.31Ge0.69 deposited at 400°C is demonstrated in Figure 4.30 [35]. The as-deposited layers have a low mean stress (compressive –100 MPa and –50 MPa for 30W and 50W, respectively). Based on the resistivity measurements displayed in Figure 4.19, the as-grown films are amorphous and an annealing step is necessary for crystallization. When these layers are annealed at low temperature (450°C and 520°C), the stress changes to tensile and remains low. High stress is obtained if the layers are annealed at high temperatures: at 600°C stress values of +587 MPa and +337 MPa are measured for 30W and 50W, respectively. At this temperature, however, cracks and/or pinholes were formed and could be seen with the naked eye. This can probably be explained by the crystallization of the films with associated hydrogen release. We can conclude that PECVD layers deposited at 400°C and annealed at low temperature (450°C to 520°C) have a low stress but a high resistivity (Figure 4.19). Low resistivity but high stress and cracks and/or pinholes are obtained for PECVD layers annealed at high temperature (600°C). These observations can be explained by the fact that the as-deposited amorphous films crystallizes during the 600°C annealing step. If one wants to obtain in situ polycrystalline layers with low tensile stress and low resistivity, a higher deposition temperature is necessary.

4.9 Stress Gradient in Silicon Germanium Stress gradient originates from the variation of stress normal to the growth surface, which is mainly due to the variation of grain size with thickness. This 800

Stress (MPa)

600 30W 400 200 50W

0 –200 350

400

450 500 550 Annealing temperature (°C)

600

650

Figure 4.30 Dependence of stress on annealing temperature of PECVD Si0.31Ge0.69 deposited at 400°C and 2 Torr. (From: [35]. © 2003 IEEE. Reprinted with permission.)

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results in an out of plane deflection, which dramatically affects the functionality of surface micromachined structures. Stress gradient can be determined qualitatively by investigating the profile of surface micromachined cantilevers by scanning electron microscopy. If the cantilevers are bending upwards, this means that, before releasing the film, the upper layers have higher tensile stress than the lower ones. On the other hand, if the upper layers are more compressive than the bottom ones, the cantilevers will bend downwards. To have a quantitative estimate for stress gradient, the surface of the micromachined cantilevers can be optically scanned by a technique having a reasonable vertical resolution (∼5 nm) and intermediate lateral resolution (∼1 µm). As we are interested in post-processing MEMS on top of standard prefabricated electronics, it is instructive to focus on the material deposited between 400°C and 520°C and study the dependence of stress gradient on thermal treatments, type of dopants added from the gas phase, deposition pressure and temperature, and Ge content. Such issues are discussed in the following sections. 4.9.1

Effect of Thermal Treatment and Doping Type on Stress Gradient

It was shown in the previous section that for films deposited at 400°C, the minimum tensile mean stress is obtained for boron in situ doped poly Si0.31Ge0.69 deposited at 2 Torr (cf. squares in Figure 4.29). To have an idea about stress gradient in this film, it is instructive to refer to the SEM images of the surface micromachined cantilevers displayed in Figure 4.31 [8]. The curling profile of the cantilevers realized by the as-grown material [Figure 4.31(a)] indicates a severe stress gradient (the upper layers have much higher tensile stress than the lower ones). Annealing at 450°C for 30 minutes significantly reduces the stress gradient, as evident from the flat profile of the cantilevers displayed in Figure 4.31(b). Further increase of the annealing temperature to 520°C makes the upper layers more compressed than the lower ones, as evident from the bending profile of the cantilevers in Figure 4.31(c). To have a better understanding of the dependence of stress gradient on grain microstructure and annealing temperature, it is interesting to refer to the TEM cross sections in Figure 4.32 [8]. By investigating Figure 4.32(a), we notice that as-grown poly Si0.31Ge0.69 has V-shaped grains and there is an amorphous portion in between the grains. Based on the cantilever profile of the as-grown film [Figure 4.31(a)], it can be concluded that the lower amorphous layer has a high compressive stress whereas the crystalline portion is less compressive. TEM cross sections did not show a significant change in grain microstructure by increasing the annealing temperature to 450°C. Accordingly, the noticeable change in cantilever profile [Figure 4.31(b)] may indicate that there are changes in the amorphous structure, which result in a more uniform stress distribution along the film thickness. The TEM cross

Silicon Germanium as an Attractive MEMS Material

(a)

123

(b)

(c)

Figure 4.31 Surface micromachined cantilevers realized by 330 nm thick, poly Si0.31Ge0.69, deposited at 2 Torr: (a) as-grown (400°C); (b) annealed for 30 minutes at 450°C; and (c) annealed for 30 minutes at 520°C. (From: [8]. © 2002 Elsevier. Reprinted with permission.)

section displayed in Figure 4.32(b) shows that annealing poly Si0.31Ge0.69 at 520°C for 30 minutes results in crystallization of the amorphous portion. This, together with the cantilever profile displayed in Figure 4.31(c), shows that crystallization results in high tensile stress for the lower layers (due to volume reduction). Because the upper layers did not undergo this stress change, since they were already crystalline as-deposited, the stress gradient is reversed after annealing at 520°C. To visualize the impact of stress gradient and mean stress on the stability of surface micromachined structures, it is instructive to refer to the SEM images in Figure 4.33, which represent a linear array of 50 × 50 µm surface micromachined structures [8]. A detailed inspection of this figure shows that structures realized by the material deposited at 400°C and annealed at 450°C for 30 minutes are completely flat and suspended. Whereas, the as-grown structures and those annealed at 520°C have an out-of-plane deflection corresponding to the stress gradient observed in Figure 4.31.

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Post-Processing Techniques for Integrated MEMS 0.45 mm

Amorphous portion (a) Portion crystalized by annealing

(b)

Figure 4.32 TEM cross section of boron in situ doped poly Si0.31Ge0.69 deposited at 400°C: (a) as-grown; and (b) annealed for 30 minutes at 520°C. (From: [8.] © 2002 Elsevier. Reprinted with permission.)

4.9.2

Effect of Deposition Conditions and Ge Content on Stress Gradient

In Section 4.9.1 it was demonstrated that as-grown Si1-xGex deposited at 400°C has a severe stress gradient [Figure 4.31(a)], which can be eliminated after annealing at 450°C for 30 minutes. As there are many process parameters that might influence the stress gradient (such as varying the Ge content, layer thickness, deposition pressure and temperature), it is interesting to investigate the possibility of tuning these parameters to minimize the stress gradient in the as-grown material. The advantage of such tuning is to avoid additional annealing steps and consequently reduce the process thermal budget. The effect of Ge content, layer thickness, and deposition pressure and temperature on stress gradient can be investigated by observing the tip deflection of surface micromachined cantilevers having a length varying from 25 µm to 1 mm and realized by LPCVD Si1-xGex thin films deposited at temperatures varying between 400°C and 450°C. It is clear from Figure 4.34 [74] that for a fixed deposition temperature and pressure of 400°C and 650 mTorr, respectively, increasing the Ge content from 40% to 60% decreases the stress gradient by a factor of 2.5. Further increase of the Ge content from 60% to 90% decreases the stress gradient by 20%. In spite of the fact that increasing the Ge content decreases the stress gradient, it should be noted that Ge contents higher than 70% are not fully compatible with standard VLSI processes [10]. Moreover, it might affect device

Silicon Germanium as an Attractive MEMS Material

125

(b)

(a)

(c)

Figure 4.33 SEM image of linear array of 50 × 50 µm surface micromachined structures realized by 0.3-µm Si0.31Ge0.69 deposited at 400°C: (a) as-grown; (b) annealed at 450°C for 30 minutes; and (c) annealed at 520°C for 30 minutes. (From: [8]. © 2002 Elsevier. Reprinted with permission.) 50 Si0.4 Ge0.6,1 µm Cantilever deflection (µm)

40 Si0.58 Ge0.42,1 µm 30

20

10

Si0.12 Ge0.88,1 µm

0 0

100

200 300 Cantilever length (mm)

400

500

Figure 4.34 Effect of Ge concentration on stress gradient of SixGe1-x deposited at 400°C and 650 mTorr. Diamonds: Si0.58Ge0.48 1.02 µm thick; squares: Si40Ge60 1.12 µm thick; circles: Si0.12Ge0.88 1.7 µm thick. (Displayed data has been approximately scaled to 1-µm thick films using the dependence of stress gradient on layer thickness determined from Figure 4.35). (From: [74]. © 2004 IEEE. Reprinted with permission.)

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reliability as Ge is more affected by humidity compared to silicon [75, 76]. Also, some applications, such as uncooled surface micromachined IR detectors [53], might require a low Ge content to reduce thermal conductivity (which is minimized at around 30% Ge [13]). Another drawback of using a high Ge content is that, for the same deposition temperature, surface roughness is increased [77], which is not desirable for some applications like optical MEMS [78] where a smooth surface is essential. Thus, it can be concluded that the optimal stress gradient can be achieved at a Ge content around 60%. On the other hand, Figure 4.35 shows that, for almost the same Ge content, the stress gradient varies inversely with layer thickness (according to Figure 4.34, the slight difference in Ge content will have a negligible influence on stress gradient). Whereas, for the same layer thickness and Ge content, the cantilever deflection varies, as expected, proportional to the square of the cantilever length. At this point it should be noted that stress gradient is not sensitive to slight changes in deposition pressure, as clear from the data displayed in Figure 4.36. Thus, it is recommended to deposit Si1-xGex films at the highest possible pressure (determined by film uniformity across the wafer), as this enhances the growth rate (deposition rate increases from 2.5 nm/min at 650 mTorr to 5 nm/min at 800 mTorr). On the other hand, a severe change in deposition pressure (by one order of magnitude or more) might have an influence on stress gradient as reported in [29]. The effect of deposition temperature on stress gradient is demonstrated in Figure 4.37. In this figure, despite the lower Ge content in the film deposited at 425°C (which is expected to yield a higher stress gradient as demonstrated in Figure 4.34), the cantilever deflection is a factor of seven lower than that

Cantilever deflection (µm)

25 20

Si 0.12 Ge0.88 , 650mT, 400°C, 1.7 µm

15 10 5 0

Si 0.08 Ge0.92, 650mT, 400°C, 5 µm 0

100

200 300 Cantilever length (µm)

400

500

Figure 4.35 Effect of layer thickness on stress gradient of Si1-xGex deposited at 400°C and 650 mTorr. Squares: Si0.12Ge0.88 1.7 µm thick; diamonds: Si0.08Ge0.92 5 µm thick. (From: [74]. © 2004 IEEE. Reprinted with permission.)

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25

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20 Si 0.4Ge0.6 , 800mT, 400°C, 1 µm

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Si 0.4Ge0.6 , 650mT, 400°C, 1 µm

0 0

50

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150 200 Cantilever length (µm)

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Figure 4.36 Effect of deposition pressure on stress gradient in Si0.4Ge0.6 deposited at 400°C. Diamonds: film deposited at 800 mTorr and 0.53 µm thick; squares: film deposited at 650 mTorr and 1.12 µm thick. (Displayed data has been approximately scaled to 1-µm-thick films using the dependence of stress gradient on layer thickness determined from Figure 4.35). (From: [74]. © 2004 IEEE. Reprinted with permission.) 35

Cantilever deflection (µm)

30 25 20

Si 0.58 Ge0.42 , 650mT, 400°C, 1 µm

15

Si0.71Ge 0.29 , 800mT, 425°C, 1 µm

10 5 0

0

50

100 150 Cantilever length (µm)

200

250

Figure 4.37 Effect of deposition temperature on stress gradient. Diamonds: Si0.58Ge0.42 deposited at 400°C, 650 mTorr, and 1.02 µm thick; squares: Si0.71Ge0.29 deposited at 425°C, 800 mTorr, and 0.45 µm thick. (Displayed data has been approximately scaled to 1 µm thick films using the dependence of stress gradient on layer thickness determined from Figure 4.35). (From: [74]. © 2004 IEEE. Reprinted with permission.)

deposited at 400°C with much higher Ge content. In the meantime, if we extrapolate the data in Figure 4.34 for Si0.4Ge0.6 deposited at 400°C and 650 mTorr to 1-mm-long cantilever, we get a deflection of 118 µm, which is one

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order of magnitude higher than that reported for the same Ge content and deposition pressure at 450°C [79]. Thus, it can be concluded that the deposition temperature has a dominant effect on controlling the stress gradient. As the type of CMOS technology determines the maximum deposition temperature [73], the optimal, as-deposited stress gradient is expected to be achieved at a Ge content around 60%. For some applications, such as surface micromachined accelerometers, thick structural layers (∼10 µm) are required, as this determines the strength of the capacitive signal [80]. Such layers cannot be deposited by conventional LPCVD techniques due to their low growth rate. Mehta et al. [81] developed a process for combining LPCVD and PECVD depositions to benefit from the high growth rate of the PECVD process and enhance crystallization at low temperature (∼450°C) by using the LPCVD process. To begin with, a thin PECVD Si0.35Ge0.65 layer is deposited (∼94 nm) to avoid the large incubation time for the growth of Si1-xGex on SiO2, as normally seen in thermal LPCVD Si0.38Ge0.65 processes [4]. This layer is amorphous and acts as a seed layer for the LPCVD layer on the top. The LPCVD layer serves as a crystallization seed layer for the PECVD layer, thus making it possible to obtain a polycrystalline film at low temperatures. The mean stress in these films is 71 MPa tensile, and the strain gradient of 3.6 × 10–5 µm–1 with the upper layers more tensile than the lower ones. To reduce this stress gradient, a top compressive LPCVD Si0.38Ge0.62 layer is deposited, which reduces the strain gradient to 1.2 × 10–5 µm–1 as clear from the cantilever profile displayed in Figure 4.38 [81]. It should be noted that in general the minimum stress gradient obtained in the as-grown film is not suitable for a wide variety of MEMS applications such as surface micromachined accelerometers and optical mirrors, where the stress gradient must be completely eliminated. As we are considering MEMS processing temperatures compatible with the state-of-the-art CMOS backend, the physical properties of the film should be locally modified without affecting the underlying layers. This goal can be realized by pulsed laser annealing, which is discussed in the next chapter.

4.10 Summary and Conclusion The main objective of this chapter is to introduce silicon germanium as a material with attractive physical properties that can be tuned at a CMOS backend compatible temperature and at the same time meet the requirements of a broad range of MEMS applications. First, the growth kinetics of silicon germanium are reviewed and it is demonstrated that using silane as the active silicon gas source and diborane as the doping gas is an economical method to enhance the crystallization and growth rate for LPCVD films deposited at CMOS backend

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Figure 4.38 SEM image for surface micromachined cantilevers realized by 10-µm-thick poly Si1-xGex deposited by combining PECVD and LPCVD depositions. (From: [81]. © 2004 IEEE. Reprinted with permission.)

compatible temperatures (∼400°C). In addition, it is shown that boron in situ doping can be activated at temperatures as low as 400°C for a Ge content of 65% or higher; phosphorus doping needs higher activation temperatures. Moreover, electrical noise in boron-doped samples is one order of magnitude lower than the phosphorus doped ones. Recently, using boron tetrachloride (BCI 3 ) as the boron gas source for the p-type in situ doped Si1-x Gex is investigated [82]. Preliminary results show that using BCI3 greatly improves uniformity and repeatability as compared to diborane. Furthermore, stress can be turned to relatively low compressive values (∼50 MPa) and strain gradient can be as low as 4 × 10−4µm−1. There is a strong correlation between mean stress, the Ge content, and deposition temperature and pressure. For applications that require Ge contents lower than 50%, the deposition temperature cannot be dropped below 470°C and still preserve a polycrystalline structure. In this case, by adjusting the deposition pressure, a low tensile stress can be achieved at such low temperature. On the other hand, if the deposition temperature is reduced to 400°C, the optimal Ge content is around 70%. The minimum as-grown strain gradient is achieved at a deposition pressure of 650 mTorr and at the highest permissible deposition temperature, which is determined by the CMOS backend thermal budget. For

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thick layers (∼10 µm), combining LPCVD ad PECVD depositions can reduce the strain gradient to 1.2 × 10–5 µm–1. In the next chapter we explore low thermal budget techniques that can completely eliminate stress gradient at 400°C.

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[31] Sedky, S., et al., “Effect of In-Situ Boron Doping on Properties of Silicon Germanium Films Deposited by CVD at 400°C,” Journal of Materials Research, Vol. 16, No. 9, 2001, pp. 2607–2612. [32] Sedky, S., et al., “Characterization of RPCVD Polycrystalline Silicon Germanium Deposited at Temperatures ≤ 550°C,” Journal of Materials Research, Vol. 17, No. 7, 2002, pp. 1580–1586. [33] Fiorini, P., et al., “Preparation and Residual Stress Characterization of Poly-Silicon Germanium Films Prepared by Atmospheric Pressure Chemical Vapor Deposition,” Proceedings of Material Research Society Symposium, Vol. 474, 1997, pp. 227–231. [34] Sedky, S., et al., “Pulsed Laser Annealing of Silicon-Germanium Films,” Material Research Society Symposium Proceedings, Vol. 741, Fall 2002, pp. J4.1.2–J4.1.6. [35] Rusu, C., et al., “New Low-Stress PECVD Poly-SiGe Layers For MEMS,” Journal of Microelectromechanical Systems, Vol. 12, No. 6, 2003, pp. 816–825. [36] Franke, A., et al., “Polycrystalline Silicon Germanium Films for Integrated Microsystems,” Journal of Microelectromechanical Systems, Vol. 12, No. 2, 2003, pp. 160–171. [37] Kamins, T., and D. Meyer, “Kinetics of Silicon-Germanium Deposition by Atmospheric-Pressure Chemical Vapor Deposition,” Applied Physics Letters, Vol. 59, No. 2, 1991, pp. 178–180. [38] Cao, M., A. W. Wang, and K. C. Saraswat, “Low Pressure Chemical Vapor Deposition of Si1-xGex Films,” Proceedings of the Electrochemical Society, Vol. 93, No. 6, 1993, pp. 350–356. [39] Li, V. Z., et al., “Rapid Thermal Chemical Vapor Deposition of In Situ Boron-Doped Polycrystalline Silicon-Germanium Films on Silicon Dioxide for ComplementaryMetal-Oxide-Semiconductor Applications,” Applied Physics Letters, Vol. 71, No. 23, 1997, pp. 3388–3390. [40] Edelman, F., et al., “Stability and Transport Properties of Microcrystalline Si1-xGex Films,” Thin Solid Films, Vol. 337, 1999, pp. 152–157. [41] Tsai, J., and R. Reif, “Polycrystalline Silicon-Germanium Films on Oxide Using Plasma-Enhanced Very-Low Pressure Chemical Vapor Deposition,” Applied Physics Letters, Vol. 66, No. 14, 1995, pp. 1809–1811. [42] Fripp, A. L., “Dependence of Resistivity on the Doping Level of Polycrystalline Silicon,” Journal of Applied Physics, Vol. 46, 1975, pp. 1240–1244. [43] Kamins, T. L., “Hall Mobility in Chemically Deposited Polycrystalline Silicon,” Journal of Applied Physics, Vol. 42, 1971, pp. 4357–4365. [44] Seto, J. Y. W., “The Electrical Properties of Polycrystalline Silicon Films,” Journal of Applied Physics, Vol. 46, 1975, pp. 5247–5254. [45] Baccarani, G., B. Ricco, and G. Spadini, “Transport Properties of Polycrystalline Silicon Films,” Journal of Applied Physics, Vol. 49, 1978, pp. 5565–5570. [46] Rai-Choudhury, P., and P. L. Hower, “Growth and Characterization of Polycrystalline Silicon,” Journal of Electrochemical Society, Vol. 120, 1973, pp. 1761–1766. [47] Colinge, J. P., et al., “Grain Size and Resistivity of LPCVD Polycrystalline Silicon Films,” Journal of Electrochemical Society, Vol. 128, 1981, pp. 2009–2014. [48] Korsh, G. J., and R. S. Muller, “Conduction Properties of Lightly Doped Polycrystalline Silicon,” Solid State Electrons, Vol. 21, 1978, pp. 1045–1051.

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[49] Kamins, T., Polycrystalline Silicon for Integrated Circuit Applications, Boston: Kluwer Academic Publications, 1988. [50] King, T., et al., “Electrical Properties of Heavily Doped Poly Crystalline Silicon-Germanium Films,” IEEE Transactions on Electron Devices, Vol. 41, No. 2, 1994, pp. 228–232. [51] Noguchi, T., et al., “Resistivity Study of P-, B- and BF2-Implanted Polycrystalline Si1-xGex Films with Subsequent Annealing,” Japanese Journal of Applied Physics, Vol. 33, No. 12B, 1994, pp. 1748–1750. [52] Jin, Z., et al., “Low-Temperature Annealing of Polycrystalline Si1-xGex After Dopant Implantation,” IEEE Transactions on Electron Devices, Vol. 44, No. 11, 1997, pp. 1958–1964. [53] Hellberg, P., et al., “Boron Doped Polycrystalline SixGe1-x Films, Dopant Activation and Solid Solubility,” Journal of Electrochemical Society, Vol. 144, No. 11, 1997, pp. 3968–3973. [54] Sedky, S., et al., “Characterization and Optimization of Infra Red Poly SiGe Bolometers,” IEEE Transactions on Electron Devices, Vol. 46, No. 4, 1999, pp. 675–682. [55] Sedky, S., “Electrical Properties and Noise of Poly SiGe Deposited at Temperatures Compatible with MEMS Integration on Top of Standard CMOS,” Material Research Society Symposium Proceedings, Vol. 729, April 2002, pp. 89–94. [56] Giles, M. D., and S. M. Sze, VLSI Technology, Second Edition, New York: McGraw-Hill, 1988, p.235. [57] Mandurah, M. M., K. C. Saraswat, and C. R. Helms, “Dopant Segregation in Polycrystalline Silicon,” Journal of Applied Physics, Vol. 51, 1980, pp. 5755–5763. [58] Laker, K. R., and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems, New York: McGraw-Hill, 1994. [59] Hooge, F. N., “1/f Noise Is No Surface Effect,” Physics Letters, Vol. 29A, No. 3, 1969, p. 139. [60] Sedky, S., and P. Fiorini, “Poly SiGe Bolometers” in Handbook of Computer Vision Application, B. Jähne, H. Hauβecker, and P. Geiβler, (eds), London: Academic Press, 1999, pp. 274–308. [61] Motchenbacker, C. D., and F. C. Fitchen, Low-Noise Electronic Design, New York: John Willey and Sons, 1973, Chapter 1. [62] Brederlow, R., et al., “A Physically Based Model for Low Frequency Noise of Poly-Silicon Resistors,” International Electron Devices Meeting, 1998, pp. 89–92. [63] Sedky, S., et al., “Thermally Insulated Structures for IR Bolometers, Made of Polycrystalline Silicon Germanium Alloys,” 9th International Conference on Solid State Sensors and Actuators, 1997, pp. 237–240. [64] Vining, C. B., “A Model for the High Temperature Transport Properties of Heavily Doped N-Type Silicon-Germanium Alloys,” Journal Applied Physics, Vol. 69, 1991, pp. 331–341. [65] Steigmeier, E. F., and B. Abeles, “Scattering of Phonons by Electrons in Germanium-Silicon Alloys,” Physical Review, Vol. 136, No. 4A, 1964, p. A1149. [66] Slack, G. A., and M. A. Hussain, “The Maximum Possible Conversion Efficiency of Silicon Germanium Thermoelectric Generators,” Journal of Applied Physics, Vol. 70, 1991, pp. 2694–2718.

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[67] Paul, O. M., J. Korviet, and H. Boltes, “Determination of the Thermal Conductivity of CMOS IC Polysilicon,” Sensors and Actuators A, Vol. 41–42, 1994, pp. 161–164. [68] Sedky, S., et al., “IR Bolometers Made of Polycrystalline Silicon Germanium,” Sensors and Actuators A, Vol. 66, No. 1–3, 1998, pp. 193–199. [69] Van Gerwen, P., et al., “Thin Film Boron Doped Polycrystalline Silicon70%-Germanium30% for Thermopiles,” 8th Conference on Solid State Sensors and Actuators, Stockholm, Sweden, June 25–29, 1995, pp. 210–213. [70] Maier-Schneider, et al., “Variation in Young’s Modulus and Intrinsic Stress of LPCVDPolysilicon Due to High Temperature Annealing,” Journal of Micromechanics and Microengineering, Vol. 5, 1995, p. 131. [71] Fan, L. S., and R. S. Muller, “As-Deposited Low-Strain LPCVD Polysilicon,” Solid State Sensors and Actuators Workshop, 1988, p. 55. [72] Koleshko, V. M., V. F. Belitsky, and I. V. Kiryshin, “Stress in Thin Polycrystalline Silicon Films,” Thin Solid Films, Vol. 162, 1988, pp. 365–374. [73] Sedky, S., et al., “Experimental Determination of the Maximum Post Process Annealing Temperature for Standard CMOS Wafers,” IEEE Transactions on Electron Devices, Vol. 48, No. 2, 2001, pp. 377–385. [74] Sedky, S., R. Howe, and T. King, “Pulsed Laser Annealing, A Low Thermal Budget Technique for Eliminating Stress Gradient in Poly-SiGe MEMS Structures,” Journal of Microelectromechanical Systems, Vol. 13, No. 4, 2004, pp. 669–675. [75] Wee, A., et al., “A Comparative Study of the Initial Oxygen and Water Reactions on Germanium and Silicon Using SIMS,” Corrosion Science, Vol. 36, No. 1, 1994, pp. 9–22. [76] Plaksina, Y., V. Kobyakov, and L. Chelnokova, “Atmospheric Oxidation of Germanium, Tin, and Lead Telluride Powders,” Soviet Powder Metallurgy and Metal Ceramics, Vol. 12, No. 3, 1973, pp. 218–22. [77] Hall, L., “Preparation and Properties of Antireflection Coatings by Chemical Vapor Deposition,” Journal of Applied Physics, Vol. 43, No. 11, 1972, pp. 4615–4621. [78] Youngjoo, Y., et al., “Integrated Multi-Wavelength Laser Source Module with Micromachined Mirrors,” Proceedings of the SPIE, The International Society for Optical Engineering, Vol. 3878, 1999, pp. 398–406. [79] King, T. J., et al., “Recent Progress in Modularly Integrated MEMS Technologies,” International Electron Device Meeting Technical Digest, IEEE, Piscataway, NJ, 2002, pp. 199–202. [80] Furtsch, M. W., Mechanical Properties of Thick Polycrystalline Silicon Films Suitable for Surface Micromachining, Duisburg University, Germany, Doctoral Dissertation, 1999. [81] Mehta, A., et al., “Novel High Growth Rate Processes for Depositing Poly-SiGe Structural Layers at CMOS Compatible Temperatures,” Proceedings of MEMS, 2004, pp. 721–724. [82] Low, C. et al., “In Situ Doped Poly-SiGe LPCVD Process Using BCL3 for PostCMOS Integration of MEMS Devices,” Electromechanical Society Proceedings: SiGe: Materials, Processing, and Devices—Proceedings of the First Symposium, Vol 7, 2004, pp. 1021–1032.

5 Low Thermal Budget Techniques for Enhancing Crystallization 5.1 Introduction It was demonstrated in the previous chapters that the processing temperature of polycrystalline semiconductor materials is always higher than the CMOS backend thermal budget, and this is mainly due to the relatively high transition temperature from amorphous to polycrystalline. In Chapter 4, the possibility of reducing the transition temperature by alloying silicon and germanium was investigated. The main drawback of this approach is that the Ge content should be higher than 65%, which is not fully compatible with standard VLSI processes [1], and which might affect device reliability since Ge is more affected by humidity compared to silicon [2, 3], and surface roughness is also increased [4]. The crystallization temperature of silicon can be significantly reduced to 500°C or lower by using metal induced crystallization (MIC), and the realized devices have outstanding performance compared to those employing conventional solid-phase crystallization [5, 6]. The crystallization thermal budget can be further reduced by using laser induced chemical vapor deposition (LICVD) and/or laser induced crystallization (LIC), which was proposed for low thermal budget applications such as TFTs [7], solar cells fabricated on glass substrates [8], and for monolithic integration of MEMS devices on top of standard driving electronics using SiGe as an structural material [9]. The following sections give an overview of the effect of metal induced crystallization and pulsed laser annealing on the morphology of silicon germanium.

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5.2 Metal Induced Crystallization of SiGe The main concept of metal induced crystallization is based on reducing the solid phase crystallization temperature of silicon due to the interaction between the silicon covalent bond and the free electrons of certain metals such as aluminum [6], copper [10], gold [11], silver [12], or nickel [13]. The crystallization temperature of silicon depends on the type of metal and varies between 350°C for Ag [12] and 485°C for Cu [10]. The main disadvantage of this technique is the metal contamination into the crystallized film, which might imply a significant reduction in the electrical conductivity especially for semiconductor materials. Thus, this technique might not be suitable for applications that require high electrical resistivity or a wide range of conductivity by controlling the doping level. Furthermore, the presence of the metal atoms inside the crystallized film might affect the internal dissipation, thus reducing the quality factor, which means that this technique might not be appropriate for the realization of high quality resonators. Zhang et al. [14] investigated the effect of Ni seeding on the structural properties of Si1-xGex deposited at 450°C for TFTs. Compared to excimer laser annealing and solid phase crystallization, this approach is expected to give better uniformity over large areas and to be more cost effective. Figure 5.1 shows that increasing the thickness of the Ni layer to 0.2 nm results in a sharp increase in the grain size. Further increase of the thickness of the Ni film results in a decrease in the grain size till it reaches a minimum at 0.5 nm. Increasing the thickness of the Ni layer from 0.5 to 1 nm is accompanied by a gradual increase in the grain size. For Ni layers thicker than 1 nm, the grain size is almost independent of the thickness of the Ni layer. This behavior is mainly due to the increase in density of Ni nuclei with thickness. For very thin layers (~ 0.05 nm), the Ni nuclei density is 7.5 × 108/cm2 [14]. The deposition of a thin Ni layer 140

Grain size (nm)

120 100 80 60 40

0

0.5

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2

Figure 5.1 Poly Si1-xGex grain size as a function of the Ni seed layer thickness. (From: [14].)

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directly on clean c-Si results in NiSi2 [15], which has a cubic structure and a lattice constant closely matched to that of silicon, thus enhancing the preferential growth rate of silicon as confirmed by the Raman spectrum displayed in Figure 5.2. This explains the steep increase in the grain size observed in Figure 5.1. The increase in the Si peak observed in the Raman spectrum displayed in Figure 5.2 (see peak located at 500m–1) shows that this process proceeds until the Ni thickness reaches 0.2 nm. The decreased grain size accompanying the increase in the thickness of the Ni film more than 0.2 nm is due to the preferential crystallite growth of Si1-xGex induced by the seeding effect of the Ni nuclei rather than the spontaneous formation of Si1-xGex nuclei on the surface [14]. As the Ni thickness exceeds 1 nm, the Ni nuclei coalesce to form a continuous film, and accordingly, the nuclei formation of Si1-xGex on Ni starts to be the decisive factor for grain growth. Hence, the grain size is independent of the thickness of the Ni seed layer, as clear from Figure 5.1. It is also interesting to note that the changes in the intensity of the Si and Ge peaks observed in the Raman spectrum displayed in Figure 5.2 shows that the thickness of the Ni layer not only affects the grain size but also affects the film composition. Chen et al. [16] investigated the possibility of using Au to enhance the crystallization of amorphous Si1-xGex deposited on glass substrates for pin infrared detectors. This technique allows maximizing optical gain and response speed. Figure 5.3 shows the effect of the annealing temperature and period on the induced lateral crystallization (ILC). This figure shows that the lower the hydrogen content in the film, the larger the induced crystallization. This is mainly due to the higher density of dangling bonds which captures the gold atoms, encouraging the formation of meta stable Au-SiGe compound, which enhances Si diffusion and causes dendritic growth of SiGe crystals. 1,400

Ramen intensity (rel. u.)

1,200 1,000

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800

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600

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400

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200 0 200

Ni 0 nm 300

400 500 Ramen shift (cm–1)

600

Figure 5.2 Raman spectra of poly Si1-xGex films deposited on Ni-seeding layers with different thickness. (From: [14]. © 2003 American Institute of Physics.)

Post-Processing Techniques for Integrated MEMS Au lateral induced crystallization (µm)

138

200 350°C 150

100 300°C

250°C

200°C

50

0

0

50

100 150 200 250 Hydrogen flow rate (sccm)

300

350

Figure 5.3 Effect of annealing temperature and hydrogen flow rate on lateral induced crystallization of α-SiGe. (From: [16]. © 2003 IEEE. Reprinted with permission.)

5.2.1

MIC for MEMS Application

The previous section gave an overview of the concept of metal induced crystallization. At this point it is instructive to investigate the impact of the metal seed layer on grain microstructure, mean stress, and stress gradient of the MEMS structural layer. It is recommended to select a seed layer that is compatible with standard CMOS fabrication tools, as this allows using advanced facilities for depositing and patterning the MEMS structural layer. Hence, a reasonable choice for the seed layer would be either aluminum or titanium. Due to the attractive physical properties of silicon germanium, it might be interesting to consider this material as the MEMS structural material. To enhance crystallization, the structural layer can be deposited directly on top of the metal seed layer or the seed layer can be inserted in the middle of the structural layer as shown schematically in Figure 5.4. For the same seed layer type and the same Si1-xGex deposition temperature, crystallization enhancement depends strongly on the deposition technique being either LPCVD or PECVD. By investigating the TEM cross sections in Figure 5.5 [17], it is clear that LPCVD Si0.37Ge0.63 deposited at 370°C on top of Al is fully polycrystalline with a columnar grain microstructure. This might be due to the low growth rate, which enables better mixing and diffusion of Al with Si1-xGex to form an alloy having lower crystallization temperature. On the other hand, PECVD Si0.29Ge0.71 deposited at the same temperature has a few columnar grains embedded in an amorphous matrix as inferred from the TEM cross section displayed in Figure 5.5(b). Depositing PECVD Si0.29Ge0.71 on top of Ti reduces significantly the grain size of the columnar crystals, and the amorphous phase dominates, as demonstrated in Figure 5.5(c). Finally, the TEM cross section displayed in Figure 5.5(d) illustrates the effect of a long anneal at a

Low Thermal Budget Techniques for Enhancing Crystallization

139

Si 0.29Ge0.71 50 nm Al Si-substrate (a)

250 nm SiO 2 Si 0.29Ge0.71 50 nm Ti

Si-substrate

250 nm SiO 2

(b) Si 0.29Ge0.71 50 nm Al Si 0.29Ge0.71 50 nm Al Si-substrate 250 nm SiO 2 (c) Si 0.29Ge0.71 50 nm Al Si 0.29Ge0.71 50 nm Ti Si-substrate

250 nm SiO 2

(d)

Figure 5.4 Schematic cross section for the different structures under consideration. (From: [17].)

temperature close to the deposition temperature for PECVD Si0.29Ge0.71 deposited on top of a thin Al layer. Annealing results in the generation of small crystals (∼10 nm) embedded inside the amorphous matrix. Thus, it can be concluded that for low thermal budget applications, it is recommended to use Al as this enhances crystallization at lower temperatures. It is important now to have an idea about the mean stress and the sheet resistance in the different layers under consideration. The data displayed in Table 5.1 shows that in general metal induced crystallization results in a compressive stress. The minimum stress is obtained by LPCVD depositions; while depositing PECVD Si1-xGex on top of Ti results in the highest mean compressive stress. On the other hand, the measured sheet resistances of the different Si1-xGex layers deposited on top of Al are close to each other in spite of the significant differences in the grain microstructure. This might indicate that the conductivity is dominated by the bottom Al layer, or it might be due to the diffusion of Al throughout the Si1-xGex layer. To discriminate between the two effects, it might be instructive to check the Al distribution throughout the film using secondary ion mass spectroscopy (SIMS). Figure 5.6 shows that for the LPCVD Si0.37Ge0.63

140

Post-Processing Techniques for Integrated MEMS

LPCVD Si 0.37 Ge0.63

500 nm Al SiO2 (a) PECVD Si0.29Ge0.71 1 µm Al (b)

PECVD Si0.29Ge0.71

Ti 250 nm

SiO2 (c)

PECVD Si0.29Ge0.71 Al 500 nm

SiO2 (d)

Figure 5.5 TEM cross section of Si1-xGex deposited at 370°C: (a) LPCVD Si0.37Ge0.63 deposited on Al; (b) PECVD Si0.29Ge0.71 deposited on Al; (c) PECVD Si0.29Ge0.71 deposited on Ti; and (d) PECVD Si0.29Ge0.71 deposited on Al and annealed for 21 hours at 370°C. (From: [17].)

Concentration (atom/cc)

Low Thermal Budget Techniques for Enhancing Crystallization 1E+9

3.2E+5

1E+8

3E+5 2.8E+5

1E+7

2.6E+5

1E+6

2.4E+5

Si 1E+5

2.2E+5

Al 1E+4

2E+5

1E+3

Concentration (atom/cc)

1E+2

1.8E+5 0

0.2

0.4

0.6

0.8 1 Depth (µm) (a)

1.2

1.6E+5 1.6

1.4

1E+9

2.6E+5

1E+8

2.4E+5 2.2E+5

1E+7

2E+5

1E+6

Si

1E+5

1.4E+5

1E+3

1.2E+5 0

0.1

0.2

1E+9

0.3 0.4 Depth (µm) (b)

1E+5 0.6

0.5

3.5E+5

1E+8

Concentration (atom/cc)

1.8E+5 1.6E+5

Al 1E+4

1E+2

141

3E+5

1E+7

2.5E+5

Al

1E+6

Si

2E+5

1E+5 1.5E+5

1E+4

1E+5

1E+3 1E+2

0

0.2

0.4

0.6

0.8 1 Depth (µm) (c)

1.2

1.4

5E+4 1.6

Figure 5.6 Al profile in Si1-xGex deposited at 370°C as determined by SIMS: (a) LPCVD Si0.38Ge0.62; (b) PECVD Si0.29Ge0.71; and (c) PECVD Si0.29Ge0.71 annealed for 21 hours at 370°C. (From: [17].)

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Post-Processing Techniques for Integrated MEMS

Table 5.1 Stress and Sheet Resistance in Different Stacks of Si1-xGex Deposited at 370°C (From: [17].) Stack (defined from bottom to top)

Stress

Sheet Resistance

SiO2/Al/LPCVD Si0.37Ge0.63

−97 MPa

0.45 ± 0.0123 Ω/Sq

SiO2/Al/PECVD Si0.29Ge0.71

−196 MPa

0.524 ± 0.0156 Ω/Sq

SiO2/Ti/PECVD Si0.29Ge0.71

−307 MPa

8.98 ± 0.331 Ω/Sq

SiO2/Al/PECVD Si0.29Ge0.71 (annealed for 21 hours)

−197 MPa

0.55 ± 0.035 Ω/Sq

layer, Al diffused significantly throughout the total film thickness. This large amount of diffusion can be explained by the long deposition period (4 hours) [17]. On the other hand, for the as-grown PECVD films, there is a significant amount of Al in the top 50 nm of the film [Figure 5.6(b)]. This might explain the relatively low sheet resistance, in spite of the significant amorphous phase observed in the TEM cross sections [Figure 5.5(b)]. Annealing a stack of 50-nm Al /1.4-µm Si0.29Ge0.71 for 21 hours at 370°C resulted in a significant increase in the Al concentration in the Si1-xGex layer up to a depth of 1 µm from the Al/SiGe interface, as clear from the SIMS profile displayed in Figure 5.6(c). Thus, the low sheet resistance observed for the different stacks is mainly due to the significant diffusion of Al or Ti into the Si1-xGex film. For MEMS applications we are interested in having layers with low mean tensile stress. Hence, it is instructive to investigate the possibility of reducing mean stress by sandwiching the metal layer in between two structural layers [Figure 5.4(c, d)]. Such structure is characterized by a stronger texture even for the plasma enhanced deposited films, as clear from the TEM cross section displayed in Figure 5.7. Accordingly, the stress tends to be more tensile. The mean

PECVD SiGe Al PECVD SiGe

Ti

Figure 5.7 TEM cross section for a stack of Ti/PECVD Si29Ge71/Al/PECVD Si0.29Ge0.71. (TEM cross section has been done by Hugo Bender and Oliver Richard IMEC, Belgium.)

Low Thermal Budget Techniques for Enhancing Crystallization

143

stress reported for a stack of either Ti/Si0.29Ge0.71/Al/Si0.29Ge0.71 or Al/ Si0.29Ge0.71/Al/Si0.29Ge0.71 is 66 MPa or 90 MPa tensile, respectively [17]. In addition to mean stress, stress gradient is also an important issue, as it might dramatically affect the functionality of surface micromachined structures. By inspecting the deflection profile of the surface micromachined cantilevers displayed in Figure 5.8, it is clear that a stack of Ti/PECVD Si1-xGex is always bending upwards, indicating that the bottom layers are much more compressive than the upper ones. On the other hand, the profiles of cantilevers realized by stacks of Ti/ Si0.29Ge0.71/Al/Si0.29Ge0.71 or Al/ Si0.29Ge0.71/Al/Si0.29Ge0.71 indicate that the upper layers are more compressive than the lower ones. This is most probably due to the fact that the middle Si0.29Ge0.71 layer is more crystalline than the upper one (as inferred from TEM cross sections). Further reduction of the stress gradient might be possible by fine-tuning the thickness of the individual layers of the stack. It is also interesting to note that the minimum bending profile is obtained for a stack of Al/PECVD Si0.29Ge0.71, in spite of the fact that the mean stress is highly compressive. King et al. [9] investigated the effect of using Ni as a seed layer for enhancing the crystallization of Si1-xGex having a Ge content between 25% and 30%. To study the effect of Ni, a thin Ni layer has been deposited on top of α-Si0.7Ge0.3 film. After annealing at 425°C for a long time, the structure is completely crystalline, as clear from the TEM cross section displayed in Figure 5.9. The mean stress of the crystallized film has been found to be compressive (~ 135 MPa). Whereas, the strain gradient is 3 ×10–4 µm–1 [9], which is rather high for applications requiring large suspended structures such as inertial sensors. 200 Ti/Si 0.35Ge 0.65 at 300°C

Cantilever deflection (µm)

Ti/Si 0.42 Ge 0.58 at 300°C 150 Ti/Si 0.29 Ge 0.71 at 370°C Al/Si 0.29 Ge0.71 /Al/Si0.29 Ge0.71 at 370°C

100

Ti/Si 0.29 Ge0.71 /Al/Si 0.29 Ge 0.71 at 370°C Al/Si 0.29 Ge0.71 at 370°C 50

0

0

200

400

600 800 Cantilever length (µm)

1000

1200

Figure 5.8 Bending profile of surface micromachined cantilevers realized by different stacks of thin metal films and PECVD Si1-xGex. (From: [17].)

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Post-Processing Techniques for Integrated MEMS

SiGe

SiO 2

Figure 5.9 TEM cross section for metal induced crystallization of Si0.7Ge0.3 using Ni seed layer. (From: [9]. © 2002 IEEE. Reprinted with permission).

5.3 Laser Induced Crystallization Over the last two decades excimer laser annealing was considered an efficient low thermal budget technique for locally modifying the physical properties of thin films without introducing any damage or modifications to the underlying layers. Early motivation for using pulsed laser annealing was to control the grain size and crystallinity of amorphous silicon [18, 19], which was attractive for the fabrication of thin film transistors having high field effect mobility on glass substrates [20, 21]. Also, it was commonly used to tune the electrical properties of implanted semiconductors [22–24] especially for devices that require shallow doped regions. Furthermore, it was demonstrated that pulsed laser annealing can noticeably improve the efficiency of solar cells as it enhances the minority carrier diffusion length [25, 26]. The fact that pulsed laser annealing reduces the defect density due to the melting and recrystallization mechanism widened the application of this technique to improve the electrical properties of metal induced crystallized amorphous silicon thin films [27]. Microsecond and nanosecond lasers are now used for low temperature deposition of a wide variety of materials like bismuth telluride [28], aluminum nitride [29], vanadium oxide [30], and ferromagnetic materials [31]. Many studies have been performed to understand the effect of laser annealing on the average grain size and stress of silicon films deposited by LPCVD [18] or RF sputtering [32]. The effects of pulsed laser annealing in locally tuning the electrical and structural properties of silicon [33–35] and Si1-xGex [36–39] are widely investigated. A novel application for pulsed laser annealing is to control stress and stress gradient in surface micromachined MEMS that are integrated on top of standard prefabricated driving electronics [40]. This application is much more challenging as MEMS implies using rather

Low Thermal Budget Techniques for Enhancing Crystallization

145

thick layers and requires the optimization of mechanical and electrical properties, and accordingly, the laser annealing conditions are completely different from those conventionally implemented for TFTs or pulsed laser deposition. 5.3.1

Laser Setup

The most important criteria for selecting the laser source are the wavelength, pulse fluence, repetition rate, and the intensity profile along the beam cross section. The type of the MEMS structural material determines the wavelength, as it should be efficiently absorbed by the material. The combination of the pulse fluence and rate determines the grain microstructure, electrical conductivity, surface roughness, mean stress, and stress gradient. To guarantee a uniform treatment all over the wafer, the beam should have a uniform intensity across its wave front, which can be realized by using a set of lenses for beam reshaping and homogenization as explained in [41]. 5.3.2

Effect of Laser Annealing on Grain Microstructure, Electrical Conductivity, and Surface Roughness

One of the attractive features of pulsed laser annealing is that it enables a broader range of Ge contents, and hence, the required physical properties of the MEMS structural layer can be tailored according to the application without being limited to high Ge contents as in the case of conventional thermal treatments discussed in Chapter 4. To study the interaction between laser pulse and the MEMS structural layer, we consider Si1-xGex films, having low Ge content (∼25%), and deposited at 400°C on top of thermal oxide. The as-grown films are amorphous, as clear from the TEM cross section displayed in Figure 5.10 [42]. Exposing this film to a single, 440 mJ/cm2 laser pulse, having a wavelength of 248 nm and duration of 24 ns, crystallizes the film, resulting in a grain microstructure characterized by two distinct regions: an upper low defect density region having blocky grains and a bottom region having high defect density fine grains. Thus, this fluence lies in the near complete melting regime [43]. Increasing the pulse fluence is accompanied by an increase in the maximum temperature, and accordingly, the melt depth is increased. This results in the generation of blocky coarse grains close to the surface and fine bottom grains. The depth of the blocky grain region significantly increases by increasing the pulse fluence, where as the fine grain zone diminishes, as clear from the TEM cross sections in Figure 5.11(b, c). Increasing the number of pulses to 100, at an average pulse energy density varying between 400 and 600 mJ/cm2, the thickness of the columnar layer is slightly increased [Figure 5.11(d, e)] and the defect density is somewhat lower than for single pulse. On the other hand, applying 100 pulses at a fluence of 790 mJ/cm2

146

Post-Processing Techniques for Integrated MEMS

Si0.75Ge0.25 deposited at 400°C

0.4 µm

SiO2 (0.1 µm)

Si Substrate

Figure 5.10 TEM cross section of as-grown Si0.75Ge0.25 deposited at 400°C and 800 mTorr. (From: [42].)

converts the grain microstructure from equiaxed to columnar [Figure 5.11(f)]. The XRD patterns displayed in Figure 5.12 show that after laser crystallization, the film always has a dominant {111} texture regardless of the average laser energy density.

(a)

(d)

(b)

(e)

(c)

(f)

Figure 5.11 TEM cross sections demonstrating the effect of average laser energy and number of pulses on grain microstructure of Si0.75Ge0.25 films deposited at 400°C: (a) single pulse at 440 mJ/cm2; (b) single pulse at 616 mJ/cm2; (c) single pulse at 790 mJ/cm2; (d) 100 pulses at 440 mJ/cm2; (e) 100 pulses at 616 mJ/cm2; and (f) 100 pulses at 790 mJ/cm2. (From: [42].)

Intensity (a.u.)

400 300

c

200

b

222

311

d

500

220

200 (Si-substrate)

111

600

147

400 (Si-substrate)

Low Thermal Budget Techniques for Enhancing Crystallization

100 a 0

20

30

40

50

60

70

80

2 Θ degrees (Cu Kα)

Figure 5.12 XRD diffraction analyses of laser-annealed poly-Si0.75Ge0.25 deposited at 400°C: 2 2 (a) single laser pulse at 760 mJ/cm ; (b) single laser pulse at 440 mJ/cm ; (c) 100 2 laser pulses at 10 Hz and 760 mJ/cm ; and (d) 100 laser pulses at 10 Hz and 440 2 mJ/cm . (From: [42].)

It is also interesting to correlate structural changes associated with laser annealing to changes in electrical conductivity. Figure 5.13 shows that for a single laser pulse, the resistivity tends to increase with the laser fluence. The noticeable increase at 790 mJ/cm2 is likely due to the formation of an equiaxed grain microstructure [see Figure 5.11(c)]. On the other hand, the squares in 1

Resistivity (mΩ.cm)

0.8 Single pulse 0.6 0.4

100 pulses

0.2 0

0

200

400 600 Laser energy (mJ/cm 2 )

800

1000

Figure 5.13 Dependence of resistivity of Si0.75Ge0.25 deposited at 400°C on pulse fluence for single pulse (diamonds) and 100 laser pulses at 10 Hz (squares). (From: [42].)

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Post-Processing Techniques for Integrated MEMS

Figure 5.13 show that the resistivity drops significantly with multiple pulses. This is more pronounced at the lowest and highest energy densities. The low resistivity at high energies may be due to the combined effects of the transformation from equiaxed to columnar grain structure and a noticeable increase in average grain size [see Figure 5.11(d)]. The low resistivity at low energies may be due to the reduced defect density, as inferred from the TEM cross sections displayed in Figure 5.11. It is interesting to note that similar results are reported for laser-crystallized silicon [44]. For MEMS, surface roughness is a critical issue that might affect the functionality of the realized devices. Hence, it is instructive to investigate how it is affected by laser fluence and pulse rate. Figure 5.14 provides quantitative data on the effect of laser energy density on surface roughness of a Si0.12Ge0.88 film deposited at 400°C. Exposing this film to a single laser pulse at 792 mJ/cm2 decreases the root-mean-square (rms) surface roughness from 160 to 80 nm. The TEM cross sections displayed in Figure 5.15 show the effect of the number of pulses on surface roughness. In this case the Ge content is much higher than the film considered in Figure 5.10. This high Ge content enhances the crystallization of the as-grown material deposited at 400°C, as clear from the TEM cross section displayed in Figure 5.15(a), where the surface roughness is also evident. Comparing Figure 5.15(b) and Figure 5.15(c), it can be concluded that surface roughness is reduced by increasing the number of pulses from 1 to 10. Similar behavior is reported for laser-annealed PECVD amorphous-Si deposited at temperatures between 310°C and 360°C [6]. It should be noted that a large number of laser pulses (100) results in a dramatic increase in surface roughness, as is shown in Figure 5.15(d). 180

Surface roughness (nm)

160 140 120 100 80 60

0

200

400 2 Laser energy (mJ/cm )

600

800

Figure 5.14 Effect of single-pulse excimer-laser annealing on rms surface roughness, for poly-Si0.12Ge0.88 deposited at 400°C and 650 mTorr. The film thickness is 1.6 µm. (From: [42].)

Low Thermal Budget Techniques for Enhancing Crystallization

(a)

(b)

(c)

(d)

149

Figure 5.15 TEM cross sections demonstrating the effect of number of laser pulses for a 2 fixed laser energy of 796 mJ/cm on 5-µm-thick poly Si0.08Ge0.92 deposited at 400°C and 650 mTorr: (a) as-grown; (b) after a single laser pulse; (c) after 10 pulses at 1 Hz; and (d) after 100 pulses at 1 Hz. (From: [42].)

In addition to the changes introduced by the laser pulse to the grain microstructure and surface roughness, it is essential to check if the laser treatment has any influence on doping or germanium segregation. By investigating the SIMS profile displayed in Figure 5.16 we notice that exposing a 5 µm thick Si0.08Ge0.92 film to a single laser pulse having a fluence of 728 mJ/cm2 increased the boron concentration close to the surface by almost a factor of five. Furthermore, there is a noticeable increase in the oxygen content, which extends for 1 µm below the film surface. On the other hand, after laser treatment, the Ge profile seems to be more uniform over the first 100 nm of the film. 5.3.3

Film Melt Depth

In order for the pulsed laser annealing technique to be suitable for MEMS monolithic integration on top of standard prefabricated electronics, the absorbed energy must be retained within the Si1-xGex film. The penetration depth of the laser-generated heat into the absorbing layer is characterized by the

150

Post-Processing Techniques for Integrated MEMS 1E+22

0.9

1E+21

Oxygen 0.8

1E+20 0.7 Boron

1E+19

0.6 1E+18

1E+17

Ge content

Concentration (atom/cc)

1

Germanium

0.5

0

1

2

3 Depth (µm) (a)

4

1E+22

5

6

0.4

1

Germanium

0.9

1E+21

0.8 1E+20

Boron 0.7

1E+19 0.6 1E+18

1E+17

Ge content

Concentration (atom/cc)

Oxygen

0.5

0

1

2

3 Depth (µm) (b)

4

5

0.4

Figure 5.16 SIMS profile of germanium, boron, and oxygen in 5 µm thick Si8Ge92 film: (a) as-grown; and (b) after a single laser pulse having a fluence of 782 mJ/cm2. (From: [42].)

larger of the optical absorption length and the thermal diffusion length determined at the end of the laser pulse. In general, for the 248-nm wavelength, the thermal absorption length dominates over the optical absorption for Si1-xGex and it will depend mainly on the initial microstructure of the SiGe film (being either amorphous or polycrystalline) as well as any phase transformations that occur during the laser pulse. The TEM cross sections displayed in Figure 5.17 provide some evidence for the depth over which the laser pulse altered the film microstructure. By investigating this figure, we notice that a 1-µm-thick Si0.4Ge0.6 film deposited at 400°C and 650 mTorr exhibits polycrystalline regions that nucleated during growth, presumably at the growth surface. Exposing this film to a single laser pulse [Figure 5.17(b)] or 10 laser pulses at 1 Hz

Low Thermal Budget Techniques for Enhancing Crystallization

Si0.4 Ge0.6 (1 µm) SiO2 (1.2 µm)

Si0.4 Ge0.6 (1 µm)

151

Si0.4 Ge0.6 (1 µm)

SiO2 (1.2 µm) SiO 2 (1.2 µm)

(a)

(b)

(c)

Figure 5.17 TEM cross-sections showing the penetration depth of excimer laser pulses in Si0.40Ge0.60 deposited at 400°C and 650 mTorr: (a) as-grown film; (b) film exposed to single laser pulse at 728 mJ/cm2; (c) film exposed to 10 pulses at 1 Hz and 728 mJ/cm2. (From: [42].)

[Figure 5.17(c)] at an average energy density of 728 mJ/cm2 results in crystallization of the amorphous material and recrystallization of the regions that were originally crystalline. The crystallization depth is limited to approximately 0.8 µm, as inferred from the thickness of the bottom amorphous layer in Figure 5.17(b, c). It should be noted that the crystallization temperature for a 60% Ge film is ~450oC [45]. Therefore, if the Si1-xGex film thickness is greater than 1 µm, there should be no significant thermal impact on the underlying layers (which can withstand exposure to temperatures at or below 450°C). If the film thickness is less than 1 µm, then the thermal penetration depth can be reduced by lowering the pulse fluence. Figure 5.18 demonstrates this for a 160-nm-thick Si0.82Ge0.18 film deposited at 400°C: a 616-mJ/cm2 pulse completely penetrates the film [Figure 5.18(a)]; by reducing the laser fluence to 120 mJ/cm2, the melt depth is noticeably reduced [Figure 5.18(b)]. At this point it is interesting to note that the effective penetration depth of the laser pulse (i.e., the depth through which microstructural changes are evident) depends strongly on the grain microstructure of the as-grown film. If the film is initially polycrystalline, the activation energy required for grain growth is much higher than that required for crystallization of an amorphous film, as previously reported for silicon [46], and hence, for the same pulse fluence, the molten depth is significantly reduced as compared to the amorphous film. Figure 5.19(a) clarifies this issue where it can be noticed that the changes in the grain microstructure of poly Si44Ge56 after being exposed to a single laser pulse at 320 mJ/cm2 are limited to a depth of 100 nm, most likely indicative of a shallow molten depth and a limited diffusion of the self-propagating silicon germanium liquid. For an amorphous film, this same effective penetration depth is achieved

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Si0.82Ge0.18 laser annealed at 616 mJ/cm2 160 nm

SiO2

(a) Si0.82Ge0.18 laser annealed at 120 mJ/cm2 0.1 µm

SiO2

(b) Figure 5.18 TEM cross section of 180-nm-thick Si0.82Ge0.18 deposited at 400°C and 1 Torr and exposed to a single laser pulse: (a) 616 mJ/cm2; and (b) 120 mJ/cm2. (From: [42].)

by a pulse having energy 2.5 times lower than this value [see Figure 5.18(b)] due to the lower melting temperature of the amorphous phase and the longer diffusion length of the molten. Finally, it is interesting to compare pulsed laser annealing to rapid thermal annealing (RTA), which is also a low-thermal-budget crystallization technique. For this comparison, we consider amorphous Si0.75Ge0.25 films deposited at 400°C and 650 mTorr (Figure 5.10). After annealing at 500°C for 3 minutes, the film is composed of randomly oriented tiny crystals [Figure 5.20(a)]; in contrast, if the film is exposed to a single laser pulse at 760 mJ/cm2, the grains are columnar and much larger [Figure 5.20(b)]. The differences in grain size and microstructure are more evident in the higher sheet resistance of the RTA film, as inferred from the data displayed in Figure 5.21. It is clear that even if the

Low Thermal Budget Techniques for Enhancing Crystallization

153

Laser annealed surface

0.1 µm

(a)

(b)

Figure 5.19 TEM cross section showing the effect of pulsed laser annealing on as-grown poly-Si0.44Ge0.56, 1.4 µm thick, deposited at 425°C and 650 mTorr: (a) exposed to a single laser pulse at 320 mJ/cm2; and (b) as-grown. (From: [42].)

RTA temperature is increased to 900°C, the sheet resistance is still more than a factor of 2.5 higher than that of the laser-annealed film. 5.3.4

Effect of Laser Annealing on Mean Stress and Stress Gradient

For an understanding about the effect of pulsed laser annealing on mean stress and stress gradient, we start by considering as-grown, 5-µm-thick, poly Si0.08Ge0.92 film deposited at 400°C and 650 mTorr. TEM cross sections show that the as-grown film is polycrystalline with a V-shaped, columnar texture [Figure 5.15(a)]. The stress gradient of the as-grown film is relatively low, as clear from the bending profile of the surface micromachined cantilevers displayed in Figure 5.22(a). Exposing this film to a single laser pulse having an energy density varying from 244 to 568 mJ/cm2, at atmospheric pressure, results in an increase in both the stress gradient and in the mean tensile stress, as clear from

154

Post-Processing Techniques for Integrated MEMS

(a)

(b)

Figure 5.20 TEM cross section of 0.4-µm-thick Si0.75Ge0.25 deposited at 400°C and 0.65 Torr: (a) after rapid thermal annealing at 500°C for 3 minutes; (b) after being exposed to 100 laser pulses at 760 mJ/cm2. (From: [42].) 1,000

900

2

Laser energy (mJ/cm )

800

800 600 700 400 600 200 0 10

500

20 30 50 Sheet resistance (Ω/sq.)

100

Rapid thermal annealing (°C)

1,000

400

Figure 5.21 Dependence of sheet resistance of 0.4-µm-thick Si0.75Ge0.25 deposited at 400°C and 0.65 Torr on laser pulse fluence (stars) or rapid thermal annealing at 500°C for 3 minutes (diamonds). (From: [42].)

the deflection of the surface micromachined cantilevers and the rotating pointer [47] displayed in Figure 5.22(b–d). The increased tensile stress, especially for the top layers of the film, is mainly due to the recrystallization of the film by the laser pulse, which results in contractions against the grain boundaries. This effect decreases gradually below the film surface due to the limited penetration of the laser pulse, and accordingly, the stress gradient is increased.

Low Thermal Budget Techniques for Enhancing Crystallization

(a)

(b)

(c)

(d)

155

Figure 5.22 Effect of single laser pulse on stress gradient and mean stress of 5-µm-thick poly Si8Ge92 film deposited at 400°C and 650 mTorr: (a) as-grown; (b) laser annealed with a single pulse at 244 mJ/cm2; (c) laser annealed with a single pulse at 408 mJ/cm2; and (d) laser annealed with a single pulse at 568 mJ/cm2. (From: [40]. © 2004 IEEE. Reprinted with permission.)

Thus, to control stress gradient using pulsed laser annealing, we should start with an as-grown material having upper layers more compressed than the lower ones. This can be achieved either by tuning the deposition conditions (which is not always feasible) or by depositing Si1-xGex bilayers having different mean stresses and tuning the energy of the laser pulse impinging the surface of the top or bottom film (or perhaps both) until the stress gradient is completely eliminated. Figure 5.23 gives more insight about how this concept can be

156

Post-Processing Techniques for Integrated MEMS

(a)

(b)

(c)

(d)

(e)

(f)

Figure 5.23 Surface micromachined cantilevers, 5 µm wide, and having a length varying from 25 µm to 1 mm, realized by Si1-xGex bilayer: (a–c) films deposited at 400°C, bottom film: 1.4-µm Si0.6Ge0.4, top film: 1.4-µm Si0.44Ge0.56; (d–f) films deposited at 425°C, bottom film: 0.9-µm Si0.44Ge0.56, top film: 0.6-µm Si0.57Ge0.43. (a) As-grown films; (b) bottom film exposed to a single laser pulse at 320 mJ/cm2; (c) bottom film exposed to single laser pulse at 380 mJ/cm2; (d) as-grown; (e) bottom film exposed to a single laser pulse at 320 mJ/cm2; and (f) bottom film exposed to a single laser pulse at 400 mJ/cm2. (From: [40]. © 2004 IEEE. Reprinted with permission.)

implemented. In this case, we consider the effect of single laser pulse on two different SixGe1-x stacks deposited at 400°C [Figure 5.23(a–c)] or at 425°C [Figure 5.23(d–f)]. For the first stack, the as-grown bottom film is amorphous, whereas the top film is polycrystalline and the bilayer bends upwards [Figure 5.23(a)]. To study the effect of pulsed laser annealing on eliminating the stress gradient, first the bottom Si0.6Ge0.4 layer is deposited, and then the sample is removed from the LPCVD furnace and exposed to a single laser pulse at 320 mJ/cm2 under normal atmospheric conditions. Then the sample is cleaned in hydrofluoric acid for 1 minute to eliminate the native oxide. Immediately after

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that, the sample is placed in the LPCVD furnace to deposit the top Si0.44Ge0.56 film. By investigating the cantilever profile displayed in Figure 5.23(b), it is clear that the stress gradient is significantly reduced. This is mainly due to the increased tensile stress in the bottom Si60Ge40 film after laser annealing. If the laser energy is tuned in such a way that makes the tensile stress balance the bending moments around the interface of the two films, the stress gradient is almost eliminated. A slight increase in the laser energy results in an undesired out-of-plane deflection as demonstrated in Figure 5.23(c). Now, if we consider the as-grown Si1-xGex stack deposited at 425°C [Figure 5.23(d)], it would be logical to expose the top film, only, to a single laser pulse to eliminate the out-of-plane downward bending. But Figure 5.23(e) shows that stress gradient is completely eliminated if the bottom film is exposed to a single laser pulse at 320 mJ/cm2 and the top film is not laser treated. Further increase in the energy of the laser pulse, impinging the surface of the bottom film, results in an upward bending rather than an expected downward bend. For a better understanding of this behavior, it is instructive to refer to the TEM cross sections of the as-grown and laser annealed films displayed in Figure 5.24. These cross sections show that the single laser pulse affected not only the microstructure of the bottom film, but also the microstructure of the top film. Figure 5.24(b) shows that the texture of the top film is more columnar when deposited on a laser-annealed lower film. Thus, we can classify the effect of laser annealing according to the type of the as-grown film being either amorphous or polycrystalline. If the bottom film is amorphous, which is the case at 400°C deposition temperature, the single laser pulse results in crystallization and a huge tensile stress. This stress has a dominant effect in determining the bending moments of the composite film, rather than the effect of the changes in the microstructure of the top film. If the bottom film is initially polycrystalline, the changes in the grain microstructure of the top film play the major role in determining the stress gradient. Finally, it should be noted that in addition to eliminating stress gradient, the single laser pulse significantly reduces average stress. The average stress of the bottom layer of the bilayer deposited at 425°C is reduced from 120 MPa compressive to 20 MPa compressive. An SEM image of surface micromachined interdigitated structure realized by a Si1-xGex bilayer is displayed in Figure 5.25. It is clear form the figure that the low mean stress results in perfect alignment of the stationery and movable comb fingers.

5.4 Summary and Conclusion This chapter explores the possibility of enhancing crystallization of the MEMS structural layer by either metal induced crystallization or pulsed laser annealing. The grain microstructure and texture of PECVD Si1-xGex deposited at 370°C on

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(a) Laser annealed surface

(b)

Figure 5.24 TEM cross section for Si1-xG-x bi layers deposited at 425°C and 800 mTorr: (a) bottom film: 0.9-µm Si0.44Ge0.56, top film: 0.6-µm Si0.57Ge0.43; and (b) bottom film: 0.9-µm Si0.44Ge0.56 exposed to a single laser pulse at 320 mJ/cm2, top film: 0.6-µm Si0.57Ge0.43. (From: [40]. © 2004 IEEE. Reprinted with permission.)

Figure 5.25 SEM image for surface micromachined interdigitated structure realized by a Si1-xGex bilayer similar to that displayed in Figure 5.24(b). (From: [9]. © 2002 IEEE. Reprinted with permission.)

top of thin Al or Ti metal films is investigated. In general, Al enhances the crystallization of as-grown Si1-xGex, but the mean stress is highly compressive. The electrical conductivity is close to that of Al and this is mainly due to the

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significant diffusion of Al into the Si1-xGex films. Stacking Ti/Si1-xGex/Al/Si1-xGex noticeably strengthens texture and results in a relatively low mean tensile stress. The stress gradient needs further reduction. The effect of pulsed excimer laser annealing (ELA) on the microstructure, texture, electrical conductivity, and surface roughness of Si1-xGex films is investigated. ELA is a useful technique for locally modifying the physical properties of Si1-xGex films, and it is suitable for annealing films deposited on top of completed CMOS electronics. Laser-annealed in situ–doped p-type Si1-xGex films are characterized by a dominant {111} texture, an average grain size of 300 nm, and an average resistivity of 0.7 mΩ.cm. The maximum depth to which the microstructure can be significantly modified is 0.8 µm in SixGe1-x that is amorphous as deposited. This effective penetration depth can be reduced by either decreasing the laser pulse fluence or by using polycrystalline films. Finally, the surface roughness can be reduced with a moderate number of laser pulses (∼10 pulses). Stress gradient can be completely eliminated by pulsed laser annealing of Si1-xGex bilayers. Finally, it is worthwhile to mention that hydrogenated microcrystalline silicon germanium deposited at temperatures varying between 300°C and 400°C is currently investigated as a material suitable for low thermal budget MEMS applications [48, 49]. Preliminary results on boron in situ doped as grown material shows that electrical resistivity, mean stress and strain gradient can be tuned respectively to an optimal value of 7 mΩcm, 34 MPa tensile and 1.5 × 10−4 µm−1 [49]. This approach might be attractive as you can realize the required MEMS physical properties in situ without any additional steps. The main drawback for such approach is after depositing the microcrystalline film, the wafer temperature cannot exceed the deposition temperature otherwise there are voids due to hydrogen evolution.

References [1]

King, T. J., and K. C. Saraswat, “Deposition and Properties of Low-Pressure ChemicalVapor Deposited Polycrystalline Silicon-Germanium Films,” Journal of Electrochemical Society, Vol. 141, 1994, pp. 2235–2241.

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Plaksina, Y., V. Kobyakov, and L. Chelnokova, “Atmospheric Oxidation of Germanium, Tin, and Lead Telluride Powders,” Soviet Powder Metallurgy and Metal Ceramics, Vol. 12, No. 3, 1973, pp. 218–22.

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[5] Lee, S., and S. Joo, “Low Temperature Poly Si Thin Film Transistor Fabricated by Metal Induced Lateral Crystallization,” IEEE Electron Device Letters, Vol. 17, 1996, pp. 160–162. [6] Radnoczi, G., et al., “Al Induced Crystallization of a-Si,” Journal of Applied Physics, Vol. 69, No. 9, 1991, pp. 6394–6399. [7] Toet, D., P. Smith, and T. Sigmon, “Laser Crystallization of Hydrogenated Amorphous Silicon Thin Films,” Journal of Applied Physics, Vol. 85, No. 11, 1999, pp. 7914–7918. [8] Andra, G., et al., “In Situ Diagnostics for Preparation of Laser Crystallized Silicon Films on Glass for Solar Cells,” Thin Solid Films, Vol. 337, 1999, pp. 98–100. [9] King, T., et al., “Recent Progress in Modularly Integrated MEMS Technologies,” International Electronics Device Meeting, 2002, pp. 199–202. [10] Russel, S., J. Li, and J. W. Mayer, “In Situ Observation of Fractal Growth During a-Si Crystallization in a Cu3Si Matrix,” Journal of Applied Physics, Vol. 70, 1991, pp. 5153–5155. [11] Hultman, L., et al., “Crystallization of Amorphous Silicon During Thin-Film Gold Reaction,” Journal of Applied Physics, Vol. 62, 1987, pp. 3647–3655. [12] Bian, B., et al., “Fractal Formation in a-Si:H/Ag/a-Si:H Films After Annealing,” Journal of Applied Physics, Vol. 73, 1993, pp. 7402–7406. [13] Kawazu, Y., et al., “Initial Stage of the Interfacial Reaction between Nickel and Hydrogenated Amorphous Silicon,” Japanese Journal of Applied Physics, Part 1, Vol. 29, 1990, p. 729. [14] Zhang, J., K. Shimizu, and J. Hanna, “Ni-Seeding Effects on the Properties of Polycrystalline Silicon-Germanium Grown at Low Temperature,” Applied Physics Letters, Vol. 82, No. 11, 2003, pp. 1745–1747. [15] Tung, R., and F. Schery, “Growth of Epitaxial NiSi2 on Si(111) at Room Temperature,” Applied Physics Letters, Vol. 55, 1989, pp. 256–258. [16] Chen, C., and J. Jier Ho, “Low Temperature Poly-SiGe Alloy Growth of High Gain/Speed Pin Infrared Photosensor with Gold-Induced Lateral Crystallization (Au-ILC),” IEEE Transactions on Electron Devices, Vol. 50, No. 8, 2003, pp. 1807–1812. [17] Sedky, S., et al., “Metal Induced Crystallization of SiGe Deposited at 370°C for Monolithically Integrated MEMS Applications,” Material Research Society Symposium Proceedings, Vol. 808, Spring 2004, pp. A4.19–A4.24. [18] Watanabe, H., et al., “Crystallization Process of Polycrystalline Silicon by KrF Excimer Laser Annealing,” Japanese Journal of Applied Physics, Vol. 33, No. 8, Part 1, 1994, pp. 4491–4498. [19] Bhattacharyya, A., B. Streetman, and K. Hess, “Theoretical and Experimental Investigation of the Synamics of Pulsed Laser Annealing of Amorphous Silicon,” Journal of Applied Physics, Vol. 52, No. 5, 1981, pp. 3611–3617. [20] Zhang, H., et al., “KrF Excimer Laser Annealed TFT with Very High Field-Effect Mobility of 329 cm2/V.s,” IEEE Electron Device Letters, Vol. 13, No. 5, 1992, pp. 297–299. [21] Koho, A., et al., “High Performance Poly-Si TFTs Fabricated Using Pulsed Laser Annealing and Remote Plasma CVD with Low Temperature Processing,” IEEE Transactions on Electron Devices, Vol. 42, No. 2, 1995, pp. 251–257.

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[22] Bhattacharyya, A., et al., “Electrical Activation and Impurity Redistribution During Pulsed Laser Annealing of BF2+ Implanted Amorphous Silicon,” IEEE Transactions on Component, Hybrid, and Manufacturing Technology, Vol. CHMT-4, No. 4, 1981, pp. 425–428. [23] Kim, D., and D. Kwong, “Pulsed Laser Annealing of Single-Crystal and Ion Implanted Semiconductors,” IEEE Journal of Quantum Electronics, Vol. QE 18, No. 2, 1982, pp. 224–232. [24] Narayan, J., et al., “Rapid Thermal and Pulsed Laser Annealing of Boron Fluoride-Implanted Silicon,” Journal of Applied Physics, Vol. 57, No. 8, 1985, pp. 2709–2716. [25] Young, R., and R. Wood, “Laser Processing for High-Efficiency Si Solar Cells,” Journal of Applied Physics, Vol. 53, No. 2, 1982, pp. 1178–1189. [26] Ostoja, P., S. Solmi, and A. Zani, “Optical and Electrical Characterization of High-Dose Ion Implanted, Laser-Annealed Silicon Solar Cells,” Journal of Applied Physics, Vol. 52, No. 10, 1981, pp. 6208–6213. [27] Park, K., et al., “Excimer Laser Annealing Effect on Nickel-Induced Crystallized Polycrystalline Silicon Film,” Journal of the Electrochemical Society, Vol. 148, No. 10, 2001, pp. G563–G565. [28] Makala, R., K. Jagannadham, and B. Sales, “Pulsed Laser Deposition of Bi2Te3-Based Thermoelectric Thin Films,” Journal of Applied Physics, Vol. 94, No. 6, 2003, pp. 3907–3918. [29] Hirayama, Y., H. Yabe, and M. Obara, “Selective Ablation of AlN Ceramic Using Femtosecond, Nanosecond and Microsecond Pulsed Laser,” Journal of Applied Physics, Vol. 89, No. 5, 2001, pp. 2943–2949. [30] Suh, J., et al., “Semiconductor to Metal Phase Transition in the Nucleation and Growth of VO2 Nanoparticles and Thin Films,” Journal of Applied Physics, Vol. 96, No. 2, 2004, pp. 1209–1213. [31] Postma, F., et al., “Epitaxial Diodes of a Half-Metallic Ferromagnet on an Oxide Semiconductor,” Journal of Applied Physics, Vol. 95, No. 11, 2004, pp. 7324–7326. [32] Fogarassy, E., et al., “Pulsed Laser Annealing of RF Sputtered Amorphous Si-H Films Doped with Arsenic,” Journal of Applied Physics, Vol. 53, No. 4, 1982, pp. 3261–3266. [33] Donnelly, D., et al., “Athermal Annealing of Ion-Implanted Silicon,” 9th International Conference on Advanced Thermal Processing of Semiconductors-RTR, 2001, pp. 133–144. [34] Prussin, S., and W. Van der Ohe, “Laser Annealing of Low-Fluence Ion-Implanted Silicon,” Journal of Applied Physics, Vol. 51, No. 7, 1980, pp. 3853–3859. [35] Kim, D., and D. Kwong, “Pulsed Laser Annealing of Single-Crystal and Ion-Implanted Semiconductors,” IEEE Journal of Quantum Electronics, Vol. QE 18, No. 2, 1982, pp. 224–232. [36] Chiussi, S., et al., “Laser-Induced Integrated Processing for Heteroepitaxial SixGe(1-x) Alloys,” Applied Surface Science, Vol. 102, 1996, pp. 42–46. [37] Chiussi, S., et al., “Laser Crystallization of Poly-SiGe for Microbolometers,” Applied Surface Science, Vol. 186, 2002, pp. 166–172. [38] Chang, T., et al., “A Novel Germanium Doping Method for Fabrication of High-Performance P-Channel Poly-Si1-xGex TFT by Excimer Laser Crystallization,” IEEE Electron Device Letters, Vol. 24, 2003, pp. 233–235.

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[39] Yu, G., “Characterization of Excimer Laser Annealed Polycrystalline Si1-xGex Alloy Thin Films by X-Ray Diffraction and Spectroscopic Ellipsometry,” Journal of Applied Physics, Vol. 83, 1998, pp. 174–180. [40] Sedky, S., R. Howe, and T. J. King, “Pulsed Laser Annealing, a Low Thermal Budget Technique for Eliminating Stress Gradient in Poly-SiGe MEMS Structures,” Journal of Microelectromechanical Systems, Vol. 13, No. 4, 2004, pp. 669–675. [41] Sedky, S., and A. Witvrouw, “Micromachining of Pulses Laser Annealed PECVD SixGe1-x Deposited at Temperatures 370°C,” 18th IEEE Conference on Micro Electro Mechanical Systems, MEMS 2005, 2005, pp. 487–490. [42] Sedky, S., et al., “Effect of Excimer Laser Annealing on the Structural Properties of Silicon Germanium Deposited at 400°C,” Journal of Materials Research, Vol. 19, No. 12, 2004, pp. 3503–3511. [43] Hatano, M., et al., “Excimer Laser-Induced Temperature Filed in Melting and Resolidification of Silicon Thin Films,” Journal of Applied Physics, Vol. 87, No. 1, 2000, pp. 36–43. [44] Anderson, G., et al., “Critical Laser Fluence Observed in (111) Texture, Grain Size and Mobility of Laser Crystallized Amorphous Silicon,” Materials Research Society Symposium Proceedings, V297, Amorphous Silicon Technology, 1993, pp. 533–538. [45] Sedky, S., et al., “Effect of In-Situ Boron Doping on Properties of Silicon Germanium Films Deposited by CVD at 400°C,” Journal of Materials Research, Vol. 16, No. 9, 2001, pp. 2607–2612. [46] Thompson, M., G. Galvin, and J. Mayer, “Melting Temperature and Explosive Crystallization of Amorphous Silicon During Pulsed Laser Irradiation,” Physics Review Letters, 1984, pp. 2360–2363. [47] Sedky, S., et al., “Structural and Mechanical Properties of Polycrystalline Silicon Germanium for Micromachining Applications,” Journal of Microelectromechanical Systems Vol. 7, No. 4, 1998, pp. 365–372. [48] Gromova, M., Et al., “The Novel Use of Low Temperature Hydrogenated Microcrystalline Silicon Germanium (µCSiGe:H) for MEMS Applications,” Microelectronics Engineering, Vol. 76, 2004, pp. 266–271. [49] Menta, A., et al., “Optimisation of PECVD Poly-SiGe Layers for MEMS Post-Processing on Top of CMOS,” 13th International Conference on Solid-State Sensors, Actuators, and Microsystems, Seoul, Korea, June 5–9, 2005, pp. 1326–1329.

6 Post-Processed MEMS Devices 6.1 Introduction Over the last two decades there has been an increased demand for low-cost, reliable systems, especially for the automotive industry, which is considered the driving force for the monolithic integration of MEMS with the driving electronics. Currently, there is a broad range of monolithically integrated systems, including digital mirror displays (DMDs) used for projection display systems [1–7] and accelerometers and gyroscopes which are widely used in the automotive industry for airbag deployment, navigation, and vehicle stabilization systems [8–10]. Other applications include the development of pressure sensors [11–13], infrared imagers [14, 15], high-quality film bulk acoustic resonators used for wireless communication [16], low-loss transmission lines operated in the gigahertz range [17], intermediate frequency (IF) filters having low power consumption and low cross coupling [18], high Q tunable capacitors integrated on the same chip with voltage controlled oscillators [19, 20], and micromotors for intelligent microsystems [21]. The conceptual approach for integrating MEMS monolithically with the driving electronics was highlighted in Chapter 1. The main objective of this chapter is to give deeper insight into the monolithic integration techniques implemented by different research institutes and companies and to pinpoint the pros and cons of each technique. Furthermore, this chapter outlines the future developments required for broadening the choice of surface micromachined devices that can be monolithically integrated on top of standard CMOS driving electronics without introducing any changes to the standard electronics fabrication process and at the same time optimizing the performance of the MEMS device. 163

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For a better understanding of the different integration approaches, it might be instructive to focus on devices that have been considered extensively by different companies, especially those for which many developments have been completed to improve their integration efficiency. Digital micromirrors and accelerometers are two attractive devices that have gained wide attention, and accordingly, they will be considered in detail throughout the following sections. It should be noted that the approaches explained for these devices can be generalized for the monolithic integration of most MEMS devices.

6.2 Monolithically Integrated Surface Micromachined Structures In general, monolithic integration of surface micromachined structures can be divided into two main categories. The first is a process that is inserted on top of standard prefabricated electronics without introducing any changes to the electronics fabrication process, including the digital micromirror displays developed by Texas instruments [1–7], electroplated gyroscopes developed by the University of Michigan and Delphi Automotive industry [22, 23], electroplated accelerometers developed by Infineon [24], and Honeywell’s thermal imagers [14]. Devices realized by this approach use mainly low temperature structural materials such as metals or vanadium oxide. The other approach uses high thermal budget structural materials (poly Si in most cases), which implies many changes into the standard CMOS process. Examples of this approach are the monolithic integration technologies developed by Sandia National Laboratories [25], U.C. Berkeley [26–31], and Analog Devices [26, 32]. The following sections give an overview of the various monolithic integration technologies developed by academia and industry, highlighting the pros and cons for each approach. 6.2.1

Monolithic Integration of DMDs

The first monolithically integrated commercial device was the digital micromirror displays developed by Texas Instruments in mid-1990s. Conventional electronic projection displays are based on CRT-addressed displays, active-matrix liquid crystal displays (LCDs), liquid crystal light valves (LCLV), or electron beam–addressed oil films. The development of MEMS technology enabled the realization of a new generation of projection systems based on digital light processing (DLP) [1–7]. The major component of a DLP is the digital micromirror, which is a MEMS array of fast reflective digital switches that precisely control the path of light emitted from a source to a projection screen using binary pulse width modulation [1]. In this case, light is reflected in one of two directions by 16-µm square aluminum mirrors. The mirror tilt angle can be

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either plus 10° or minus 10° depending on the state of the underlying CMOS memory cells—either high or low. That is why these mirrors are called digital mirrors as they have only two predetermined inclinations. The mirror rotation is done by electrostatic actuation produced by the potential difference between the underlying CMOS memory cell and the mirror [7]. Each mirror is composed of alternating layers of aluminum and air gaps. A schematic cross section of the different layers is displayed in Figure 6.1(a) [7]. The mirror is rigidly connected to an underlying yoke by support posts at its center. Figure 6.1(b) shows the details of the yoke. It is connected to support posts by mechanically compliant torsion hinges. The support posts are attached to the underlying substrate and also provide bias-rest signals to the mirror. Spring tips located at the yoke tip provide more efficient release of the yoke from the landing mirror as it moves from one state to the other. Finally, the address electrodes for the mirror and the yoke are connected, through the bottom metal plate, to the complementary sides of the underlying synchronous dynamic random access memory (SDRAM). The mirrors are post-processed on top of standard prefabricated electronics, using a low temperature surface micromachining technology, which allows high integration density up to 1.3 million mirrors [7]. The mirrors are arranged Mirror

Support post

Bias-reset bus

Torsion Yoke Support posts hinge Bottom metal plate (a)

Mirror address electrode

Yoke Support posts

Torsion hinge

Bias-reset

(b)

Spring tip

Figure 6.1 Schematic diagram for the different components of the DMD: (a) cross section of the DMD clarifying the different layers; and (b) top view of the yoke and hinge. (After: [7].)

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at a pitch of 17 µm, and accordingly, the fill factor of this integration approach is ∼90%, thus allowing high optical efficiency. The schematic cross sections shown in Figures 6.2 and 6.3 give an overview of the process flow for the monolithic integration of the DMDs. The driving electronics are fabricated using a 0.8-µm CMOS technology. After completing the CMOS process, a thick oxide layer is deposited and planarized using CMP [see Figure 6.2(a)]. This planarization step is important as it provides a flat substrate for fabricating the DMD, and hence ensuring that brightness uniformity and contrast ratio is not degraded over the DMD array. The DMD fabrication process involves depositing four different metal layers. The bottom metal layer is for addressing the yoke and provides bias/rest signals. The second metal layer is for the torsion hinge and it is separated from the bottom metal layer by a photoresist sacrificial layer as shown schematically in Figure 6.2(b). The third metal represents the yoke, mirror address electrodes, and the hinge support posts [Figures 6.2(c) and 6.3(a)]. The last metal layer is that of the mirror, which is separated from the underlying layer by a thick photoresist layer as shown in Figure 6.3(b). Bottom metal

Resist sacrificial layer

CMP oxide

Substrate with CMOS address circuitry (a)

Oxide hinge mask

Hinge metal

Substrate with CMOS address circuitry (b) Oxide yoke mask

Yoke metal

Substrate with CMOS address circuitry (c)

Figure 6.2 Process flow for fabricating DMDs. (a) Oxide deposition, planarization and patterning, depositing and patterning the bottom metal plate, depositing and patterning the resist sacrificial layer; (b) depositing hinge metal, depositing and patterning hinge oxide mask; and (c) depositing yoke metal, depositing and patterning yoke oxide mask. (From: [7]. © 1998 IEEE. Reprinted with permission.)

Post-Processed MEMS Devices Hinge support post

Yoke

167

Hinge

Substrate with CMOS address circuitry (a)

Mirror

Mirror support post

Oxide mirror mask

Substrate with CMOS address circuitry (b)

Mirror

Mirror support post

Oxide mirror mask

Substrate with CMOS address circuitry (c)

Figure 6.3 (a) Etching yoke metal and stripping yoke oxide mask; (b) depositing and patterning the second sacrificial layer, depositing mirror metal, depositing and patterning mirror oxide mask; (c) etching mirror metal, stripping mirror oxide mask, and releasing the structure. (From: [7]. © 1998 IEEE. Reprinted with permission.)

Sputtered aluminum is used typically for different metal layers [7], and it is plasma etched using a PECVD silicon dioxide etch mask layer as illustrated in Figures 6.2(c) and 6.3(b). The oxide masks are plasma stripped and the photoresist sacrificial layer is removed in oxygen plasma to yield a suspended structure as shown in Figure 6.3(c). The main attractive feature of this process is that it does not introduce any changes to the standard CMOS fabrication process and the fill factor together with the integration density is very high. Furthermore, using a photoresist as a sacrificial layer makes the release process simple and does not require any additional layers to protect the underlying CMOS layers. The main limitation in this process is that the structural layers are metal, which suffers from fatigue and creep. Fatigue results in hinge damage [7]; and creep occurs in mirrors that are

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landed in one of the two states for a long time. In this case there is a residual tilt that builds up over time, and accordingly, the mirror is difficult to control dynamically [7]. 6.2.2

Monolithic Integration of Surface Micromachined Accelerometers

Microaccelerometers are used in a broad range of applications. The automotive industry uses this type of sensor for airbags, in vehicle stability systems, and in electronic suspension [33, 34]. In addition, accelerometers are used in medical applications [35, 36], activity monitoring systems [37, 38], head-mounted displays [39, 40], padless mouse [41], virtual reality applications [42], robotics [43], and navigation systems [8, 9]. The huge demand for implementing accelerometers in a wide variety of systems is the driving force for improving the reliability of such type of sensors, and accordingly, the monolithic integration of this device with the driving and controlling electronics. In general, an accelerometer is composed of a proof mass, suspension beams, and a damper. To improve the static sensitivity and quality factor, and to reduce the total acceleration noise of the accelerometer, the proof mass should be as large as possible and the spring constant as small as possible [44]. There are different techniques for detecting the vibrations of the proof mass, either using a piezoresistive material or a variable capacitor. Piezoresistive detection has been used for the first micromachined accelerometer [45] and the first commercialized microaccelerometer [46]. The main advantage of a piezoresistive accelerometer is that it is simple to fabricate, and it is easily interfaced to the readout electronics. On the other hand, this detection mechanism is sensitive to temperature changes, and also the minimum detectable acceleration is higher than that of capacitive detection [44]. For this type of microaccelerometer, a large proof mass is required, which is realized by bulk micromachining [47, 48]. Using capacitive detection instead of piezoresistive detection significantly improves sensitivity, dc response, and noise performance. In addition, this detection mechanism is characterized by low drift, low power dissipation, and low temperature sensitivity [44]. Thus, this type of accelerometers has been attractive for the automotive industry [49] and for high precision inertial grade microgravity devices [50]. The main limitation for this technique is that it is sensitive to electromagnetic interference, and accordingly, the device should be well shielded. There are two basic configurations for capacitive detection, either lateral or vertical schemes. In vertical detection (Figure 6.4), the proof mass moves perpendicular to the substrate and the change in capacitance between the proof mass and a bottom conductive plate is detected. For lateral detection, the proof mass moves parallel to the plane of the substrate and the capacitor is formed between fingers in the proof mass and fixed electrodes on the substrate, as demonstrated schematically in Figure 6.5.

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Supporting beam Anchor point

Proof mass

(a) Proof mass Anchor point Direction of acceleration

Substrate

Conducting plate (b)

Figure 6.4 Schematic cross section for vertical capacitive detection: (a) top view; and (b) cross section. (Based on discussion presented in [44].)

Acceleration Anchor point

Fixed electrode

Movable electrode

Figure 6.5 Schematic cross section for lateral capacitive detection: (a) top view; and (b) cross section. (Based on discussion presented in [44].)

In 1982, Howe and Muller demonstrated for the first time the possibility of using poly Si to realize surface micromachined cantilevers [51]. Two years later, Howe demonstrated the possibility of merging a MEMS vapor sensor with driving electronics realized by NMOS transistors using an interleaved approach [28–30]. In this case, the spacer oxide and PSG are used as a sacrificial layer, and the MEMS structural layer was poly Si. Later, Analog Devices developed a

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commercial accelerometer based on an interleaved process to integrate surface micromachined poly Si structures with the driving electronics using a BiCMOS process [32]. The reason for selecting BiCMOS technology for fabricating the electronics is that it is mature and it provides 24V for bias voltage, which makes the circuit design much more flexible. The detailed process flow is displayed in Figures 6.6 to 6.8. The integration process in this approach is interleaved, which means that the MEMS process is inserted within the standard BiCMOS process flow. First, the BiCMOS process is executed until the deposition of borophosphosilicate glass (BPSG) [see Figure 6.6(a)]. At this point the MEMS process starts by depositing a thin layer of low temperature oxide (LTO) to passivate the n+ junctions. Then an LPCVD nitride layer is deposited, which acts as an etch stop for the sacrificial layer during releasing the structures [Figure 6.6(b)]. This is followed by depositing a sacrificial layer composed of 1.6-µm densified, undoped LTO. Small depressions are defined in the LTO oxide as shown schematically in Figure 6.6(c). Such depressions minimize the contact area between the MEMS structural layer and the substrate, and hence reduce the stiction probability. After that the anchor points of the structural layer into the substrate are etched in the sacrificial layer as illustrated in Figure 6.6(c). These Circuit area

THOX

MEMS area

BPSG n+ runner

p

p

p– LPCVD nitride

THOX

(a) LTO

BPSG n+ runner

p

p

p– (b)

Anchor opening

Spacer oxide

THOX

p

BPSG n+ runner

Depression in space oxide

p

p– (c)

Figure 6.6 Process flow for interleaved MEMS monolithic integration: (a) sensor area, post-BPSG planarization and moat mask; (b) sensor area after deposition of thin oxide and thin nitride; (c) sensor region following deposition of spacer oxide, bumps, and anchor masks. (From: [32]. © 1993 PennWell.)

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Sensor poly Si

Spacer LTO THOX

BPSG n+ runner

p

p

p– (a)

LTO

Contact opening

THOX

BPSG n+ runner

p

p

p– (b)

Plasma oxide Metal

THOX

p

BPSG n+ runner p–

p

(c)

Figure 6.7 (a) Cross sectional view after sensor polysilicon deposition, implant, anneal, and patterning; (b) sensor area after removal of dielectrics from circuit area, contact mask, and Pt silicide; (c) post-metallization and plasma oxide passivation and patterning. (From: [32]. © 1993 PennWell. Reprinted with permission.)

points will also provide electrical contact between the MEMS device and the electrical circuitry through the n+ runner. At this stage, the relatively deep junctions of the BiCMOS process allow the high thermal budget for processing the MEMS structural layer, together with any dielectric densification steps without introducing any parametric shifts in the standard characteristics of the BiCMOS electronics. Two microns of poly Si are used as MEMS structural layer [Figure 6.7(a)]. After implanting, annealing, and patterning the structural layer, the sacrificial oxide is etched from the circuitry region. This is followed by defining contact openings and forming platinum silicide as illustrated in Figure 6.7(b). The BiCMOS process is completed by sputtering and patterning a TiW barrier and Al/Cu interconnect [Figure 6.7(c)]. At this point, the circuit region should be protected during the HF release process of the MEMS structure. Silicon nitride would be the optimal choice, as it can stand the long HF etch. During patterning the silicon nitride protective layer, the underlying layers might be attacked. Accordingly, an etch stop, plasma oxide layer, should be deposited prior to the

172

Post-Processing Techniques for Integrated MEMS Plasma nitride

THOX

BPSG n+ runner

p

p– (a)

Photoresist

THOX

p

BPSG n+ runner

p

p–

p

(b)

THOX

p

Air

BPSG n+ runner

p

p– (c)

Figure 6.8 (a) Post-plasma nitride passivation and patterning; (b) sensor area at final beam release etch (pre-etch); and (c) sensor area after final beam release etch (after resist removal). (From: [32]. © 1993 PennWell. Reprinted with permission.)

nitride protective layer. The stack of the oxide/nitride acts as a passivation layer for the BiCMOS circuit as shown schematically in Figure 6.8(a). After passivation, the MEMS area is cleared by etching all the layers on top of the structural layer [Figure 6.8(b)]. Before performing the HF release, the circuitry is protected by a photoresist layer as demonstrated in Figure 6.8(b). Finally, the structures are released and the photoresist is removed in oxygen plasma, resulting in a final cross section similar to that displayed in Figure 6.8(c). It is evident from the above process that such an interleaved approach allows a high thermal budget for the MEMS process, which is favored from the point of view of optimizing the physical properties of the different MEMS layers and achieving high growth rate for the structural films. This was at the cost, however, of a strong interference with the electronics fabrication process. Such interference results in introducing topography to the standard process flow, depositing extra protective layers, and exposing the electronics to high temperatures, which are not taken into consideration in the standard process flow. These modifications imply much development to guarantee a high process yield, especially for commercial products. This means that the development cost for the final device could be extremely high. Furthermore, it might require direct access to the electronics foundry, which is not always possible. In addition, the

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thickness of the structural layer is limited to few microns, due to topography, and hence, the performance of the MEMS device is not optimized for applications such as inertial sensors, which imply using thick films. Accordingly, this process cannot be considered as the optimal approach for low-cost, monolithically integrated MEMS that can be used for any application. To partially overcome the drawbacks of the above process, Yun et al. demonstrated a modular integration approach for post-processing polycrystalline silicon MEMS on top of driving electronics realized by 3-µm CMOS technology [27]. The main motivation for this process is to minimize changes introduced to the standard CMOS process flow and at the same time use poly Si, which is a standard IC material as a MEMS structural layer. To achieve this goal, and to accommodate the high thermal budget required for processing poly Si on top of prefabricated CMOS electronics, aluminum interconnects are replaced by tungsten (W), which is selected due to its low electrical resistivity and its high melting point. Furthermore, the thermal expansion coefficient of W matches closely that of silicon. As tungsten starts to react with silicon around 600°C, TiN/TiSi2 is used as a diffusion barrier at the metal silicon contacts. It is demonstrated that using W metallization and a TiN/TiSi2 barrier causes no noticeable changes to the standard characteristics of the MOS circuitry for temperatures as high as 850°C [52]. After completing the CMOS process, the wafers are coated by 300 nm of low temperature oxide followed by 200 nm of LPCVD nitride as shown in the schematic cross section in Figure 6.9(a). These layers act as a protection for the CMOS circuitry against subsequent etching during the MEMS process. At this stage the MEMS process starts by etching openings in the oxide nitride stack. Then the bottom electrode of the MEMS device is deposited and patterned. This layer is 350 nm of in situ doped poly Si, and it also connects the MEMS device to the CMOS circuitry through the poly capacitor, as shown in Figure 6.9(b). The advantage of using the poly capacitor as a bridge between the bottom electrode and the CMOS circuitry is that it prevents any contamination in the poly Si tube due to the out-diffusion of the mobile ions in the sputtered tungsten film. After depositing the bottom electrode, a 1-µm-thick PSG sacrificial layer is deposited and patterned. This is followed by depositing a 2 µm thick poly Si film, which acts as the proof mass, suspension, and the levitation comb fingers of the MEMS device. To relieve stress and minimize the stress gradient in this film, 0.5 µm PSG is deposited prior to etching the poly Si film and then the wafer is rapid thermally annealed at 1,000°C for 1 minute. It should be noted that stress and stress gradient can be further reduced by annealing at higher temperatures (∼1,050°C [27]), but this might result in blistering of the nitride layer. After annealing, the poly Si layer is patterned and then the sacrificial layer is removed in buffered HF. The nitride passivation layer acts as a protection cap for the CMOS circuitry during the release process.

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Post-Processing Techniques for Integrated MEMS

Tungesten metallization

Gate poly

Poly-poly capacitor

PSG TiN/TiSi 2

p+

n+

p+

N-Substrate

Low temperature oxide

Nitride passivation

n+

P Well (a)

Poly 2 Bottom electrode (poly Si) Poly capacitor p+

p+

N-substrate

n+

n+

P well (b)

Figure 6.9 Schematic cross section for MEMS post-processing on top of standard 3-µm CMOS wafers with tungsten metallization: (a) CMOS wafers after being coated with low temperature oxide and LPCVD nitride; and (b) MEMS module added on top of the CMOS circuitry. (From: [27]. © 1992 IEEE. Reprinted with permission.)

By comparing this process to the interleaved process developed by Analog Devices [32], it is evident that this approach is much simpler and more modular. The only drawback is that it requires special metallization and metal diffusion barriers to withstand the high thermal budget of MEMS. To avoid introducing any changes to the standard CMOS process flow, and to preserve the modularity of the integration process, Sandia National Laboratories developed a preprocessing monolithic integration technology [25]. The main objective of this approach is to eliminate the topography introduced by MEMS, and at the same time allow a high thermal budget for depositing and relieving stress in poly Si, which is used as a MEMS structural layer. To achieve this goal, MEMS are processed in a trench. The depth of the trench is adjusted in such a way that after processing the MEMS structure the wafer can be planarized by CMP, and hence, the CMOS process starts with no topography. Figure 6.10 gives an overview of the process flow for this integration approach. The process starts by defining alignment marks on the silicon surface, which are used as a reference for subsequent processing. Then, a shallow trench (∼6 µm deep) is defined in the Si substrate using KOH anisotropic etching [Figure 6.10(a)]. The advantage of using anisotropic etching is to produce a slope in the trench sidewalls, which simplifies photolithography on the MEMS

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175

6 mm deep trench (a)

Silicon (100) substrate Silicon nitride

(b)

Silicon (100) substrate Poly Si bottom electrode

Contact stud Sacrificial oxide

Strucutral layer

(c)

Silicon (100) substrate

Silicon nitride cap

(d)

Silicon (100) substrate Silicon nitride

Interconnect metal

(e)

Silicon (100) substrate Silicon nitride

Interconnect metal

(f)

Silicon (100) substrate

Figure 6.10 Process flow of Sandia National Labs for integrating MEMS monolithically with CMOS circuitry using preprocessing approach: (a) defining trench for MEMS; (b) depositing silicon nitride at the bottom of the trench; (c) depositing and patterning ground plane, sacrificial layer, and the MEMS structural layer; (d) filling the trench with oxide, CMP, and depositing a silicon nitride cap layer; (e) standard CMOS process and opening the nitride on top of the MEMS structure at the end of the CMOS process; and (f) releasing the MEMS structure. (From: [25]. © 1995 IEEE. Reprinted with permission.)

structures deposited inside the trench. To improve the resolution inside the trench, alignment marks are defined at the bottom of the trench. Using this technique, 1 µm features can be realized at the bottom of the trench. A dielectric

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Post-Processing Techniques for Integrated MEMS

silicon nitride thin film is deposited at the bottom of the trench as shown in Figure 6.10(b). This is followed by processing the MEMS structure, which includes depositing the bottom poly Si electrode, an oxide sacrificial layer and the poly Si structural layer as demonstrated in Figure 6.10(c). The depth of the trench is adjusted so that the height of the contact stud is just below the planarized trench. After that the shallow trench is filled with oxides. It should be noted that this is a critical step, as this oxide layer should not produce any voids in high aspect ratio structures. Then the wafer is planarized using CMP. High temperature annealing is used to relieve stress in the poly Si film. Finally, the MEMS region is caped by a silicon nitride layer as shown schematically in Figure 6.10(d). At this stage, the CMOS process starts on a planner wafer. The standard CMOS process flow is executed normally. The only modification to the backend is that the nitride mask on top of the MEMS region should be opened prior to releasing the structures. During the release process, the CMOS circuitry is protected by a photoresist. This step also represents a critical part of the process, as the field oxide should not be attacked and the photoresist must have good adhesion to the passivation layer. It is clear that this preprocessing approach is modular, but it requires many processing steps, a few of which are critical such as lithography at the bottom of the trench, high quality oxides to avoid out-gassing during the CMOS process, and planarization. The main limitation for this approach is that the thickness of the MEMS structural layer cannot exceed few microns, otherwise the resolution of lithography will be dramatically reduced especially for structures defined at the bottom of the trench. Recently, Analog Devices developed a new modular MEMS process to monolithically integrate thick poly Si (5 to 10 µm) multilayers with submicron CMOS processes [26]. The main objective of this process is to use the area efficiently and to allow stress relief in poly Si by annealing at high temperatures (1100°C or higher). In this approach, the MEMS devices are processed completely prior to the CMOS, thus allowing high temperature steps for poly Si deposition and stress relief. CMP has been used to provide good surface planarity for CMOS processing. The cross sections displayed in Figures 6.11 to 6.14 give an overview of the process flow. The process starts by growing 600 nm of silicon dioxide using a typical LOCOS process. Then a silicon nitride layer is deposited as an etch stop for the sacrificial layer. This is followed by the deposition of the ground plane of the MEMS device, which is composed of 250 nm of poly Si. Then, 1.6-µm sacrificial dioxide is deposited and patterned. After that, 6 µm of phosphorus in situ doped poly Si layer is deposited, which represents the device structural layer [Figure 6.11(a)]. Such a thick layer is one of the challenges of this process due to high stress and risk of cracks, in addition to the high surface roughness. Films are annealed at 1,100°C to relief stress and stress gradient. After the thermal treatment, the mean stress is 2 MPa tensile and the out-of-plane deflection of 500 µm long cantilevers is

Post-Processed MEMS Devices

177 Poly Si deposition to fill the trench

CMOS electronics

6 µm in situ doped Poly Si Sensor region 1.6 µ of silicon oxide Poly Si Silicon nitride

Anchor Si-substrate (a)

600 nm of silicon oxide

Contact stud

TEOS for trench isolation

Area for CMOS electronics

Sensor region

Si-substrate (b)

Area for CMOS electronics

Sensor region

Si-substrate (c) Silicon nitride as an oxidation barrier

Area for CMOS electronics

2 µm TEOS Cap

Sensor Region

Si-substrate (d)

Figure 6.11 Schematic cross section for the CMOS preprocessing process developed by Analog Devices, U.C. Berkeley, and Bosch: (a) depositing the MEMS sacrificial layer and structural layer; (b) defining contact studs and isolating parts with different potential; (c) filling trenches with poly Si; and (d) depositing a 2-µm TEOS cap and a thin silicon nitride layer. (From: [26]. © 2003 SPIE. Reprinted with permission.)

0.1 µm or less. The sheet resistance of the poly Si film is 15 Ω/sq. The surface roughness of the poly Si layer is high (∼800 nm over the total range), and accordingly, a CMP step is required to reduce the surface roughness to a RMS of less than 1 nm [26]. To electrically isolate the different MEMS regions at different potentials, a trench is defined at the place of the contact stud, as shown in Figure 6.11(b). This is one of the most challenging steps in this process. To insure good electrical isolation, poly Si should be overetched to ensure complete poly removal from the 6 µm trench. The good etch selectivity for poly against the bottom oxide enables the success of this process. Then conformal TEOS deposition is used to electrically isolate the sidewalls of the trench [Figure 6.11(b)]. After that the trenches are filled with poly Si as shown in Figure 6.11(c). This is followed by poly etch back to remove the poly trench fill from the surrounding oxide. To

178

Post-Processing Techniques for Integrated MEMS

CMOS Sensor region

Si-substrate (a)

CMOS Side wall spacer

Sensor region

Si-substrate (b)

Figure 6.12 Isolating the MEMS region from the CMOS electronics: (a) etching all the layers in the CMOS area; and (b) thermal oxidation to isolate the MEMS structure. (From: [26]. © 2003 SPIE. Reprinted with permission.)

isolate the MEMS device from the CMOS process, a 2-µm TEOS cap layer is deposited followed by a thin silicon nitride layer which acts as an oxidation barrier [Figure 6.11(d)]. At this point, the area of the CMOS electronics is prepared by protecting the MEMS by a photoresist and then all the layers in the CMOS region are etched down to the bottom poly Si plate as shown in Figure 6.12(a). The sidewalls of the MEMS region are isolated by thermal oxidation as demonstrated in Figure 6.12(b). Then the bottom poly Si plate and the oxide layers underneath that plate are etched [Figure 6.12(b)]. To eliminate the topography introduced by the thick MEMS structures and to enable integration with submicron CMOS process, epitaxial silicon is grown selectively in the area of the CMOS. This process is challenging as the epitaxial process should be uniform all over the wafer. The ground poly is close enough to the surrounding silicon substrate, and accordingly, the epitaxial substrate over grew this area and good epitaxial layer is obtained against the MEMS block side. Due to the slow crystal growth in the vicinity of the MEMS region, a 1.5 µm deep facet is formed, as shown in Figure 6.13(a). This results in a 12 µm

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179

wide exclusive zone [Figure 6.13(a)] which is not planner and where no CMOS electronics can exist. Outside the exclusive region, the variation in the epi thickness is less than 0.25 µm, which is acceptable for submicron lithography. The 1.5-µm facet is filled with oxide/nitride/oxide. Then the surface is planarized by CMP, as shown in Figure 6.13(b). The nitride layer acts as a polish stop for CMP. After polishing, the nitride layer is removed from the epi region. Then a shallowly sloped contact is wet etched down to the 6-µm poly Si structure [Figure 6.14(a)]. The MEMS structure is protected from the CMOS process by a seal layer composed of a stack of oxide and nitride [Figure 6.14(a)]. Such a stack is designed to be a sufficient protection for the MEMS structure against the standard CMOS clean steps, initial oxidations, wet etches, and the LOCOS Epitaxial silicon

1.5 µm deep facet

12 µm CMOS exclusive Electronics zone

Sensor region

Si-substrate (a) 12 µm exclusive zone

Epitaxial silicon (CMOS circuit area)

Sensor region

Si-substrate (b)

Figure 6.13 (a) Epitaxial silicon growth; and (b) filling the facet and planarization using CMP. (From: [26]. © 2003 SPIE. Reprinted with permission.)

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Post-Processing Techniques for Integrated MEMS

Contact to MEMS

Sealing layer

CMOS Epitaxial silicon Electronics (CMOS circuit area)

Sensor region

Si-substrate (a) Passivation layer

Epitaxial silicon (CMOS circuit area)

Sensor region

Si-substrate (b)

Released beam

Epitaxial silicon (CMOS circuit area)

Si-substrate (c)

Figure 6.14 (a) Shallowly slope contact wet etch, and coating the MEMS structure with a protection seal layer; (b) standard CMOS process flow; and (c) release of the MEMS structure. (From: [26]. © 2003 SPIE. Reprinted with permission.)

field oxide process sequence used at the beginning of a typical CMOS process. This step is also one of the critical steps in this process, as the thickness and the

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deposition technique of the seal layer should be tailored in such a way to with stand the subsequent steps. Then the standard CMOS process flow is executed normally as shown in Figure 6.14(b). Metallization is the last critical step in this process, as a good electrical contact should be achieved between the standard metal lines and the MEMS structure. For this process, it was found that the large contact area, defined prior to the CMOS process, did not introduce significant changes to standard CMOS process flow. After completing the CMOS process and depositing the passivation layer, the layers deposited on top of the MEMS structure are etched, and then beams are defined in the 6-µm-thick poly Si structure. Finally the MEMS structures are released [Figure 6.14(c)]. This step also requires a lot of development, as the CMOS circuitry should be protected during the release process. This is done by using a photoresist protective layer, which is removed in oxygen plasma after releasing the structures. In conclusion, the above process enables the monolithic integration of surface micromachined thick layers (∼6 µm) with standard CMOS process using a preprocessing approach. The advantage of this process is that it enables high temperature processing for the MEMS structural layer, and at the same time eliminates topography, enabling the use of a submicron CMOS fabrication process. This approach requires many critical integration steps. First, the isolation of the MEMS structure from the driving electronics needs lots of development to guarantee proper electrical isolation. Next, the epitaxial growth requires special tuning for the process to achieve high uniformity for the selective epitaxial process, and also it should provide good coverage at the sidewalls of the MEMS structural layer. Then the protection of the MEMS device during the CMOS process is another challenge, as the protective layers should withstand all the different CMOS processing steps without being attacked. The opening of the electrical contact should be etched in a special way to guarantee good electrical contact between the CMOS circuitry and MEMS, and at the same time it should not introduce significant modifications to the standard CMOS metallization process. Finally, the release process is another critical step that should be carefully developed to avoid any damage of the CMOS structures during the HF release of the MEMS sacrificial layer. The adhesion of the photoresist to the different layers should be perfect to avoid any peeling off and consequent under etching of the CMOS field oxides. Furthermore, this integration approach does not allow the use of low-cost state-of-the art CMOS fabrication processes, as such processes do not allow any change in their standard process. The integration technologies presented up until now fall into two main categories: processes that require introducing major interaction with the standard CMOS process (as in the interleaved process of Analog Devices), or processes that require developing many critical steps in the MEMS process to avoid major modifications to the CMOS process. This is the case for the preprocessing

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Post-Processing Techniques for Integrated MEMS

technology presented by both Sandia Labs and Analog Devices, which implies developing either planarization steps, or growing the epitaxial layer selectively and depositing special buffering layers between the MEMS region and the CMOS circuitry. The modular post-processing approach presented by U.C. Berkeley would be more promising if the MEMS thermal budget could be reduced to avoid replacing aluminum with tungsten. In this case, using pure germanium or silicon germanium as the MEMS structural layer is expected to resolve this issue. It was demonstrated in Chapters 4 and 5 that the mechanical and electrical properties of Si1-xGex can be tuned to the desired values at a CMOS backend compatible temperature by either adjusting the germanium content (~ 65%) or by pulsed laser annealing, which allows a significant reduction in the germanium content. Recently, Franke et al. demonstrated the possibility of integrating an n-type poly Ge MEMS resonator on top of prefabricated CMOS electronics [31]. The driving electronics have been realized using a 3-µm CMOS process with Al_2% Si interconnects. A schematic cross section of the completed CMOS process before starting the MEMS process is displayed in Figure 6.15(a). In this case the CMOS is passivated by LTO, which is used as a sacrificial layer for the poly Ge structure. Furthermore, the low thermal budget of this process together with the fact that the fabrication technology is not advanced, eliminates the need for adding a diffusion barrier between the interconnect metal and the silicon surface. It should be noted that for more advanced technologies or for shallower drain/source junctions, spiking might be activated by the MEMS processing temperature, and accordingly, the presence of a barrier layer might be mandatory. After completing the CMOS process, the wafer is protected by 675 nm of LTO on top of which there is 59 nm of amorphous silicon [Figure 6.15(b)]. The LTO layer is grown at 400°C for 1 hour. The top amorphous silicon layer protects the CMOS oxide layers during the HF release etch for the MEMS structure. Accordingly, this film should have a low pinhole density to avoid HF penetration to the buried oxide. This is realized by depositing the α-Si layer on two steps. The first step is at 450°C for 6 minutes, and the second is at 410°C for 40 minutes. Before starting the MEMS process, an LTO thin film (∼350 nm) is deposited which acts as an etch stop for the poly Ge ground plane. The MEMS process starts by etching vias in the LTO, α-Si and LTO stopping on the bottom n+ poly Si layer, which is used to connect the MEMS layer to the interconnect metal [Figure 6.15(c)]. Actually, a direct contact between the MEMS layer and the interconnect would reduce the contact resistance, but using the poly Si bridge avoids having exposed metal inside the deposition furnace as this might result in metal contamination for the SiGe deposition system. After that 310 nm of poly Ge is deposited at 400°C, followed by a 2.1 µm layer of LTO, which acts as the sacrificial layer. In this case it should be noted that cleaning the wafers before the LTO deposition is a critical step as poly Ge is

Post-Processed MEMS Devices Silicon oxide passivation

CMOS

p+

p+

Al

183

MEMS

n+

n+ P well

N-substrate

(a)

α-Si

p+

LTO

CMOS

p+

N-substrate

n+

n+ P well

(b) n+ poly Si

p+

p+

N-substrate

MEMS

n+

n+ poly Ge (ground plane)

n+

P well (c)

n+ poly Ge

p+

p+

N-substrate

n+

n+

P well (d)

Figure 6.15 Schematic cross sections for MEMS post-process on top of CMOS electronics using n poly Ge as a MEMS structural material: (a) completed CMOS process; (b) protection layers for the CMOS circuitry from HF release etch process; (c) opening contact via between MEMS and the driving electronics, depositing and patterning poly Ge ground plane; (d) depositing and patterning the sacrificial layer and the MEMS structural layer, releasing the structure. (From: [31]. © 2003 IEEE. Reprinted with permission.)

etched in piranha, and hence, wafers should be cleaned in solvents to remove organics, followed by an HF dip and rinsing in DI water [31]. Finally, the anchor points of the top poly Ge plane are defined in the LTO sacrificial layer,

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Post-Processing Techniques for Integrated MEMS

and 2.2 µm of poly Ge are deposited at 400°C. It is worthwhile to note that growing this film takes around 4 hours and 45 minutes. To lower the resistivity of poly Ge, a rapid thermal annealing step at 550°C for 30 seconds is required [31]. Figure 6.15(d) shows a final cross section of the device after being released. It is interesting to note that adding the MEMS process on top of the CMOS electronics resulted in a change in the dependence of the drain current on gate voltage, as clear from Figure 6.16 [31]. The drive current above threshold voltage increased, whereas, the leakage current decreased. These changes are typical after the 400°C step and the sintering step at 550°C for 30 seconds, which in principle improves the performance of the transistor. In spite of the low processing temperature of poly Ge, it is not a favored MEMS structural material especially for critical applications where reliability is an important issue. This is mainly due to the fact that Ge is affected by humidity much more than silicon is [53, 54]. To overcome this drawback, U.C. Berkeley developed another post-processing technology where p-type Si0.35Ge0.65 is used as the structural material and poly Ge is the sacrificial layer [31]. The attractive feature of this approach is that the MEMS structure is integrated directly on top of the electronics, thus demonstrating the efficiency of post-processing in saving area. Furthermore, poly Ge can be etched in hydrogen peroxide (H2O2), and accordingly, no protection layer is required, which makes the integration process much simpler. A schematic cross section for the MEMS and CMOS circuits is displayed in Figure 6.17. Poly Si0.35Ge0.65 is deposited at 450°C. The deposition conditions are adjusted to grow the poly Si0.35Ge0.65 ground plane in 30 minutes, 1E+3

After MEMS

1E+2

Drain current (µA)

1E+1 1E+0 1E–1

Before MEMS

1E–2 1E–3 1E–4 1E–5 1E–6

0

1

2

3 4 Gate voltage (V)

5

6

Figure 6.16 Dependence of drive current on gate voltage before (squares) and after (diamonds) the MEMS process. (From: [31]. © 2003 IEEE. Reprinted with permission.)

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185 p+ poly SiGe

p+ poly SiGe Silicon dioxide

Al

p+ N-substrate

p+

n+ P well

n+ p+ poly Si

Figure 6.17 Cross sectional diagram of the p-type poly Si0.35Ge0.65 modularly integrated after completion of CMOS transistors with Al interconnects. (From: [31]. © 2003 IEEE. Reprinted with permission.)

which corresponds to a 410-nm-thick layer. The Ge sacrificial layer is deposited at 375°C, and it takes 2 hours and 45 minutes to grow 2-µm-thick film. At this point it should be noted that etching the anchor points of the top electrode is critical, as it implies dry etching the Ge sacrificial selectively with respect to the bottom poly Si0.35Ge0.65 electrode. Due to the low etch selectivity, a thin LTO layer should be deposited on top of the bottom poly Si0.35Ge0.65 electrode. After dry etching the Ge sacrificial layer from the location of the anchor points, the LTO layer is removed by wet etching in buffered HF. Finally, the structural layer is deposited at 450°C for 3 hours to yield a 2.5-µm-thick layer. By investigating the above process, it is clear that using poly Ge or poly Si1-xGex allowed MEMS post-processing on top of standard CMOS electronics. The main limitation of this process is the low growth rate of the MEMS structural layers, which increases the time for which the CMOS wafers are exposed to 400°C or 450°C, which might have an impact on the characteristics of the CMOS circuits or interconnects as previously discussed in Chapter 2. Furthermore, the thickness of the MEMS structural layer is limited to a few microns, which might have a negative impact on the performance of inertial sensors that requires a large proof mass and hence a much thicker layer. To reduce the thermal budget and increase the thickness of the active layer, it is worthwhile considering PECVD Si1-xGex rather than LPCVD Si1-xGex. In a joint collaboration between the Interuniveristy Microelectronics Center (IMEC), Phillips, ASM, and Bosch, the possibility of integrating MEMS on top of standard 0.35-µm CMOS technology having five metal layers [55, 56] is investigated. The MEMS structural material is 10-µm-thick poly Si1-xGex deposited at 450°C. To reduce mean stress and strain gradient, and at the same time to enhance the growth rate, Si1-xGex films are deposited by a process that combines LPCVD and PECVD depositions [57] (this is outlined in Chapter 4). The mean stress of the as-grown films is 57 MPa tensile, strain gradient is 1.2 × 10–5 µm–1, resistivity is

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Post-Processing Techniques for Integrated MEMS

0.9 mΩ.cm, and the growth rate is 100 nm/min. The sacrificial layer used in this case is silicon dioxide.

6.3 Monolithic Integration Using Bulk Micromachining and DRIE Historically, bulk micromachining is an attractive technology for fabricating sensors due to the superior mechanical properties of silicon; and the first generation of commercial accelerometers has been realized by this technology [10]. Bulk micromachining is used for the monolithic integration of a wide variety of devices including tire pressure monitoring systems [58], barometric pressure sensors [59], optical switches [60], bulk acoustic resonators [61], two-dimensional microscanners [62], microvalves [63], low-cost uncooled infrared detectors [64], magnetic field sensors [65], tactile finger print sensors [66], and chemical gas sensors [67, 68]. There are many bulk micromachining technologies that have developed at different research centers for post-processing MEMS after the completion of the CMOS process [48, 69–71]. The Physics Electronics Laboratory, ETH Zurich, realized a wide variety of devices by machining CMOS wafers. This included gas sensors [67, 68, 72], infrared detectors [73–75], pressure sensors [76], and gas flow sensors [77]. This approach relies on making use of the different layers deposited during the CMOS process to realize the required function of the device. This can be achieved by anisotropic etching of the silicon wafer either from the backside or from the front side. Etching the silicon wafer completely from the backside, and using the CMOS thermal oxide as an etch-stop, the resulting membranes will be composed mainly of the CMOS dielectric layers, which is suitable for sensors that require high thermal isolation such as infrared detectors or calorimetric chemical sensors. On the other hand, poly Si and metal structures sandwiched between the dielectric layers can be used to create thermopiles and heating resistors [69]. For applications that require silicon membranes and suspended n-well islands, the pn junction between the p-type silicon substrate and the n-well is used as an etch-stop for the electrochemical process used to release the structures [78]. Figure 6.18 shows a schematic cross section for a monolithically integrated piezoresistive bulk micromachined accelerometer developed by Daimler-Benz and Dialog Semiconductors [48]. This process introduces minimum modifications to the CMOS process, as implanting the piezoresistor and depositing LPCVD layers for stress compensation. The CMOS circuits are protected by a standard LOCOS technology, whereas, poly gate and metal are protected by BPSG. N-well is used for the electrochemical etch-stop of the sensor. Carnegie Mellon developed a monolithic integration process for three-axis gyroscopes and accelerometers that enables simultaneous detection of lateral

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187

Piezoresistor

n Well P-substrate

N-well

Figure 6.18 Schematic cross section for a monolithically integrated bulk micromachined piezoresistive accelerometer. (From: [48]. © 1995 IEEE. Reprinted with permission.)

vibrations (parallel to the substrate plane) as well as vertical vibrations (perpendicular to the substrate plane) on the same chip without any need for wafer-to-wafer bonding or using silicon on insulator (SOI) wafers [79, 80]. This is realized by combining surface micromachining and DRIE. The advantage of this approach is that it uses single crystal silicon microstructures and is fully compatible with the standard CMOS process. This process is pure CMOS post-processing, as it uses prefabricated CMOS wafers realized by 0.8 µm CMOS technology. The MEMS process starts by etching the wafer backside by DRIE, as shown in Figure 6.19(a). This step reduces the thickness of the silicon wafer to 50 to 80 µm. Then the CMOS intermetal dielectric layers are etched by reactive ion etching using the top metal layers as a mask [Figure 6.19(b)] [81]. The advantage of using such maskless etching is that no lithography is required; in addition, the minimum beam width and gaps are set by the CMOS process and scale down with the technology. The structural layer is defined by etching through the silicon wafer by DRIE, as shown schematically in Figure 6.19(c). Finally, a short isotropic timed etch of silicon is performed [Figure 6.19(d)]. The main objective of this step is to electrically isolate bulk silicon structures. The advantage of this process is that it is fully compatible with CMOS backend and combined large proof masses, typically realized by bulk micromachining, with thin films. Furthermore, the maskless etching of the dielectric layer makes this process simple and cost effective. The main limitation for such process is that the mechanical properties of the thin film laminated structure depends strongly on the CMOS vendor. As via and interconnect in any foundry are tailored for planarized interconnect and not for suspended structures, the residual stress, stress gradient, and Young’s modulus might vary from one foundry to another, and a good control of these parameters is essential for the appropriate functionality of the device. Recently, Takahashi et al. [82] demonstrated the possibility of post-processing MEMS electrostatic actuators using DRIE. In this case 8-µm-thick silicon on insulator (SOI) is used, and MEMS is processed next to the driving electronics. Before starting the MEMS process, the prefabricated electronics are

188

Post-Processing Techniques for Integrated MEMS Dielectric CMOS circuitry

MEMS region

Poly Si

Metal_3 Metal_2 Metal_1

Silicon Membrane

Silicon substrate (a)

(b)

(c)

(d)

Figure 6.19 Schematic cross section for the MEMS post-processing technology developed at Carnegie Mellon: (a) backside deep silicon etch; (b) anisotropic oxide etch; (c) deep Si etch for release; and (d) Si undercut. (From: [79]. © 2003 IEEE. Reprinted with permission.)

protected by a silicon dioxide layer. Then the oxide in the MEMS area is cleared using masked buffered HF etching. After that metal contacts between MEMS and the driving electronics are deposited and patterned (this is done prior to defining the MEMS structure to avoid large topography introduced by the

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189

MEMS process). The MEMS structure is defined by DRIE in the SOI layer. Finally, the sacrificial layer is removed in buffered HF. The advantage of this approach is that it alleviates the dependence of stress on process parameters as in the case of the process developed by Carnegie Mellon. Furthermore, it makes use of the superior properties of crystalline silicon. The main limitation is that MEMS is processed next to the driving electronics, which might have a negative impact on fill factor, especially for high-density integration

6.4 Summary and Conclusion This chapter gives an overview of the different MEMS monolithic integration processes. Each process described has it own attractions and limitations. Metals have been used successfully as a structural material for post-processing surface micromachined structures, without introducing any changes to the standard CMOS process flow, and there are commercial devices based on this structural material. The main limitation for metals is that they suffer from creep and fatigue, which might affect long-term reliability of surface micromachined devices. Furthermore, the physical properties of metals are not suitable for a wide variety of high performance MEMS applications. To clarify this issue, we note that the high thermal conductivity and the low temperature coefficient of resistance make metals unsuitable for applications that require high thermal isolation and high sensitivity for thermal radiation, such as thermal imagers. Furthermore, the internal dissipation of metals is higher than that of semiconductors, and so this will affect the quality factor of mechanical resonators. In spite of the attractive physical properties of poly Si, monolithic integration of this material implies introducing significant changes to the standard CMOS process flow. If post-processed, tungsten interconnects should be used instead of Al. Also, diffusion barriers should be deposited at the metal silicon contact points. Pre-processing, however, makes the MEMS process complicated and involves many additional processes such as defining trenches, which have a negative impact on the minimum features that can be realized; and also the thickness of the structural layer is limited to few microns, which might reduce the performance of some devices such as inertial sensors. Interleaved processing makes the integration process very expensive and not modular. The low thermal budget for depositing Si1-xGex together with its attractive physical properties (discussed in detail in Chapter 4), makes this material suitable for post-processing MEMS on top of standard prefabricated electronics. U.C. Berkeley demonstrated the monolithic integration of this material on top of standard CMOS electronics. Using Ge as a sacrificial layer is attractive since it can be etched in hydrogen peroxide, which means that no protective layer is

190

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needed for the CMOS electronics during the MEMS release process. Furthermore, the deposition temperature of germanium is fully compatible with the state-of-the-art CMOS electronics. The main limitation for using LPCVD poly Si1-xGex as a structural material is its relatively high deposition temperature (∼ 450°C), as well as its low deposition rate and high germanium content. The PECVD SixGe1-x process recently demonstrated by IMEC [55] resolved the low growth rate, and accordingly, the thickness of the structural material can be increased to 10 µm. To make MEMS post-processing compatible with the state-of-the art CMOS fabrication technologies and to improve the reliability of the devices, the MEMS processing temperature should be decreased below 400°C and the germanium content must be reduced to 50% or lower. Pulsed laser annealing seems to be a promising route to realize this objective. It is demonstrated in Chapter 5 that by using this technique, high quality LPCVD films can be realized at temperatures as low as 400°C with a Ge content of 25%. Future research in this direction should investigate the possibility of combing PECVD deposition with pulsed laser annealing technology, and tuning the laser annealing process to produce high-quality films at relatively low temperatures (~ 370°C or lower). This approach will not only give a high growth rate and superior material properties, but it will also allow a broad range of Ge content, varying from pure silicon to pure Ge. Preliminary research in this direction seems to be promising [82]. Bulk micromachining and deep reactive ion etching, however, is fully compatible with the thermal budget allowed by the state-of-the-art CMOS technologies, but this approach relies on defining the different structural layers of the MEMS device from CMOS metal and dielectrics layers, which might again limit the performance of the device. Also, stress in the CMOS process is not optimized for realizing suspended structures. In bulk micromachining it is very difficult to build the device on top of the driving electronics and so the fill factor is relatively low.

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List of Acronyms AES

Auger electron spectroscopy

Al

aluminum

AlCu

Al-0.5wt%Cu

AlSiCu

Al-1wt%Si-0.5wt%Cu

AP

atmospheric pressure

APCVD

atmospheric pressure chemical vapor deposition

Au

gold

BCl3

Boron tetrachloride

Be

beryllium

BiCMOS bipolar complementary metal oxide semiconductor BJT

bipolar junction transistor

BPSG

borophosphosilicate glass

Cr

chromium

CMP

chemical mechanical polishing

CMOS

complementary metal oxide semiconductor

CVD

chemical vapor deposition

Cu

copper 197

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Post-Processing Techniques for Integrated MEMS

DLP

digital light processing

DMD

digital micromirror display

DNA

deoxyribose nucleic acid

DRIE

deep reactive ion etching

Epi

epitaxial

FIB

focused ion beam

FOX

flowable oxide

FPA

focal plane arrays

Ge

germanium

GeH4

germane

H2O2

hydrogen peroxide

HDP

high density plasma

HF

hydrofluoric acid

HNO3

nitric acid

IC

integrated circuit

IF

intermediate frequency

ILC

induced lateral crystalization

IR

infrared

KOH

potassium hydroxide

LCD

liquid crystal display

LCLV

liquid crystal light valves

LIC

laser induced crystallization

LICVD

laser induced chemical vapor deposition

LIGA

X-ray lithography, electro-deposition and molding

LPCVD

low pressure chemical vapor deposition

LTO

low temperature oxide

MEMS

microelectromechanical systems

List of Acronyms

MIC

metal induced crystallization

Ni

nickel

NiSi2

nickel silicide

NEMS

nanoelectromechanical systems

PDMS

polydimethylsiloxane

PECVD

plasma enhanced chemical vapor deposition

PMMA

polymethylmmethacrytale

PSG

phosphorus silicon glass

Pt

platinum

PVD

physical vapor deposition

Q-Factor

quality factor

RBS

Rutherford backscattering

RF

radio frequency

RP

reduced pressure

RTA

rapid thermal annealing

RPCVD

reduced pressure chemical vapor deposition

RTCVD

rapid thermal chemical vapor deposition

SDRAM

synchronous dynamic random access memory

SEM

scanning electron microscopy

Si

silicon

SiC

silicon carbide

SiGe

silicon germanium

SiH4

silane

Si2H6

disilane

SiH2Cl2

dichlorosilane

SIMS

secondary ion mass spectroscopy

Si3N4

silicon nitride

199

200

Post-Processing Techniques for Integrated MEMS

SiO2

silicon dioxide

SOI

Silicon on insulator

SOG

spin on glass

Ta

tantalum

TCR

temperature coefficient of resistance

TEM

transmission electron microscopy

TEOS

tetra ethyl ortho silicate

TFT

thin film transistors

Ti

titanium

TiN

titanium nitride

TiSi2

titanium silicide

TWT

traveling-wave tube

UV

ultra violet

USG

undoped silicon glass

VDC

vehicle dynamic control

VLSI

very large scale integration

W

tungsten

XRD

X-ray diffraction

About the Author

Sherif Sedky received a B.Sc. with honors, in electronics engineering in 1992, and a M.Sc. in engineering physics in 1995, both from the Faculty of Engineering at Cairo University, and a Ph.D. in microelectronics in 1998 from the Katholieke Universiteit Leuven, Belgium. In 1995 he joined the MEMS group of the Interuniversity Microelectronics Center (IMEC) in Leuven, Belgium. From 1999 to 2002 he was an assistant professor at Cairo University. During the academic year 1999–2000, he was a postdoctoral fellow at the Katholieke Universiteit Leuven and a visiting professor at the same university during the summers of 2001 through 2005. In 2002 he was a visiting researcher at the University of California, Berkeley. In September 2002, Dr. Sedky joined the Physics Department at the American University in Cairo, where he is currently an associate professor. He is a member in the Institute of Electrical and Electronic Engineers (IEEE). He holds four patents and authored and coauthored more than 40 international publications and a book chapter in the field of design, fabrication, and monolithic integration of MEMS with the driving electronics using polycrystalline silicon germanium as a structural material. Currently, he is establishing a MEMS fabrication facility at the Science and Technology Research Center at the American University in Cairo. He was a recipient of the prestigious Egyptian National Award in Advanced Technological Sciences in 2002 and the Graduate Studies Award from Cairo University in 1996. He has served on committees of several international conferences.

201

Index Auger electron spectroscopy, 37, 40

Accelerometers Capacitive, 168–169 Monolithic integration Interleaved, 169–172 Pre-process, 174–181 Post-processing, 173, 174, 182–185 Aluminum CMOS interconnects, 34–36 Aluminum copper CMOS interconnects, 37–40 Aluminum silicon CMOS interconnects, 40–45 Focused ion beam (FIB) cross sections of, AlCu, 39, 40, 42, AlSiCu, 44, Metal induced crystallization using Al, seed layer, 138–144 Nitride, 83 Reaction between AlCu and Ti, 37, 38 AlCu and TiN, 41, 43 AlSiCu and Ti, 43, 44 Resistivity of AlSi, 57 SIMS profile of Al in Si1-xGex, 141 Sheet resistance of AlCu, 38, 41 AlSiCu, 41, 43 Stress in AlSi, 56 Stress gradient in AlSi, 58 Amorphous silicon, 71–72

Boron tetrachloride, 129 Bulk micromachining anisotropic etchants, 8 anisotropic etching, 6, 7,8 applications, 6 CMOS integration, 186–189 materials commonly used, 6 monolithic integration, 186–189 isotropic etchants, 6 isotropic etching, 6, 7 process flow, 7 Chemical mechanical polishing (CMP), 14, 34, 174, 175, 177, 179 CMOS Backend, 34–36 Contact resistance, 45 Frontend, 32–34, 45–47 Maximum processing temperature, 47–48 MEMS integration, Interleaved processing, 15–18, 169–172, Post-processing, 4–5, 18–21, 173–174, 182–185, 189–190. Pre-processing, 5, 14, 174–181 Copper Electroplated copper, 67–69 adhesion, 68 MEMS applications, 81

203

204

Resource Allocation in Hierarchical Cellular Systems

Deep reactive ion etching, 11–12 CMOS integration using, 187 Digital micromirror display, (DMD) structure, 165 Monolithic integration, 166, 167 Doping Boron in situ doping, 97, 98, 101, 107, 108, 110, 129 Boron ion-implantation, 102, 104–107 Phosphorus ion implantation, 92, 93, 102 Phosphorus in situ doping, 109,

strain gradient, 155–157 surface micromachining, 158 surface roughness, 148, 149 penetration depth, 150–152 Micromachining, 13–14 Lithography Soft lithography, 12–13 X-Ray lithography, 9–11 LIGA Applications, 9 Typical process, 10

Germanium Attractive features for MEMS, 81 Growth kinetics, 95, 96 Sacrificial layer, 184–185 Stress gradient in n-type, 73, 75 Stress in n-type, 73–74 Step coverage, 72 Post-processing, 182–184 Gold Adhesion to silicon, 67 Attractive features for MEMS, 81 Enhancing crystallization of α-SiGe, 137 MEMS applications, 66 Sputtering, 67, 68 Stress, 67, 68 Grain size of nickel, 63 Grain microstructure of laser annealed LPCVD Si1-xGex, 146, 149, 151, 152, 153, 154 LPCVD Si1-xGex deposited on Al, 140 PECVD Si1-xGex deposited on Al, 140 PECVD Si1-xGex deposited on Ti, 140 rapid thermal annealed (RTP) LPCVD Si1-xGex, 154

MEMS Applications, 1–4 Fabrication processes Bulk micromachining, 6–8 DRIE, 11–12 Laser micromachining, 13–14 LIGA, 9–11 Soft lithography, 12–13 Surface micromachining, 8–9 Materials, 51–52 Metals as MEMS material, 53–69, 91 Semiconductors as MEMS material, 69–80 Structural layers, 9 Metal induced crystallization of Si1-xGex using Al Seed layer, 138–143 Ni Seed layer, 136–137, 143–144 Ti Seed layer, 139–140, 142 Microcrystalline SiGe, 159 Mobility of Electrons in Si1-xGex, 103 Holes in Si1-xGex, 103 Monolithic integration techniques, 4 Analog device process, 169–173, 176–181 Berkeley process, 173, 174, 182–185 Carnegie Mellon, 186–189 Daimler-Benz and Dialog semiconductors, 186, 187 Interleaved processing, 15–18, 169–172, Physics electronics laboratory ETH Zurich, 186 Post-processing, 4–5, 18–21, 173–174, 182–185, 189–190. Pre-processing, 4, 5, 14, 174–181 Sandia National Labs Process, 174–176

Hybrid integration, 4 Laser Crystallization of Si1-xGex, 145-147 Excimer laser effect on boron distribution, 150 electrical conductivity, 147 germanium profile, 150 grain microstructure, 145, 146, 151, 152, 153 oxygen profile, 150 texture, 146, 147

Index Nickel Attractive features for MEMS, 81 Deposition techniques, 61 Effect of substrate on texture, 62 Grain size, 62–63 Magnetization, 61 MEMS applications, 61 Metal induced crystallization using Ni seed layer, 136–137, 143–144 Resistivity, 62–63 Sputtering, 61 Noise Dependence of noise in Si1-xGex on deposition conditions, 111, 112 doping type, 114 germanium, 112 resistivity, 112 in silicon, 112 Johnson noise, 110 Low frequency noise, 110–114 PECVD Germanium, 72, 73 Silicon, 71, 72 Silicon germanium, 98, 99, 110, 185 Silicon nitride, 75, 76, 77 Silicon oxide, 77 Platinum Advantages for MEMS, 63, 81 Adhesion to oxide, 64–65 MEMS applications, 81 Resistivity, 64–65 Stress 64, 65–66 Sputtering, 64 Temperature coefficient of resistance (TCR), 66 Poly Si Crystallization temperature, 70 Mechanical properties, 70 Noise, 112 Post-processing, 173 Pre-processing, 174–176 Sheet resistance, 107 Stress, 70–71 Temperature coefficient of resistance, 105–107. Porous silicon Formation, 78–79 pore size, 79 Thermal conductivity, 78

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Yield strength, 78 Post processing SiGe resonators, 184–185 Process flow for Bulk micromachining, 7 DMD post processing, 166–167 Interleaved MEMS monolithic integration, 16, 17–18, 170–172 LIGA, 10 MEMS pre-processing, 175, 177–180 MEMS post-processing, 19, 20–21, 183, 188 Surface micromachining, 8, 9 Rapid thermal annealing, 44, 73, 74, 103, 109, 152, 154 Resistivity of laser annealed LPCVD Si1-xGex, 147, 148 Nickel, 62–63 n-type Si1-xGex, 102, 109 PECVD Si1-xGex, 110 Platinum, 64–65 p-type Si1-xGex, 102, 104, 106–110 rapid thermal annealed LPCVD Si1-xGex, 103–104, 109, 152, 154 Tantalum, 54–57 Sacrificial layer Amorphous silicon, 71 Germanium, 72, 184–185 Pores silicon, 78 Resist, 56, 167 Silicon Dioxide, 76, 94 Secondary ion mass spectroscopy (SIMS) profile of Al in LPCVD Si1-xGex, 141 Al in PECVD Si1-xGex, 141 boron in Si1-xGex, 150 germanium in Si1-xGex, 150 oxygen in Si1-xGex, 150 Silicon carbide, 79–80 Attractive features for MEMS, 82 Energy bandgap, 80 Doping, 80 Silicon nitride MEMS applications, 73, 75 Refractive index, 76 Stress, 76-77 Thermal conductivity, 73 Silicon dioxide Etching, 76

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Silicon dioxide (continued) MEMS applications, 81 Refractive index, 77, 78 Stress, 77, 78 Thermal conductivity, 77 Silicon germanium Applications, 92 Boron diffusion, 105 Crystallization, 109, 136 Doping, 101–110 Enhancing crystallization using Al seed layer, 138-142 Ni seed layer, 136–137, 143–144 excimer laser annealing, 144–152 Ge content dependence on deposition pressure, 97 silane flow rate, 98 Grain microstructure, 124, 140, 142, 144, 146, 149, 151, 152, 153, 154, 158 Growth rate dependence on deposition pressure, 96–97 deposition technique, 98–99 diborane flow rate, 98 Ge content, 95, 99 silane flow rate, 97–98 type of silicon gas source, 95 Wafer temperature, 96 Mechanical properties, 92 Noise dependence on deposition pressure, 112 doping type, 113, 114 frequency, 112 resistivity, 112 Nucleation on oxide 94 PECVD Si1-xGex, 99, 120–121, 129, 138–143 Post-processing, 184–185 Resistivity dependence on annealing temperature, 104, 108, 109, 110 annealing time, 109 boron ion implantation dose, 106 doping concentration, 100, 108 Ge content, 102, 104, 108, 110 Laser annealing conditions, 147 Silicon gas source silane, 95, 98 disilane, 95 dichlorosilane, 95 Solid solubility of boron, 104, 106

Stress dependence on annealing temperature, 117, 119 deposition pressure, 117 deposition technique, 117, 121 deposition temperature, 120 Ge content, 117, 119, 120 Stress gradient dependence on annealing temperature, 123 deposition pressure, 127 Ge content, 125 laser annealing, 155–157 layer thickness, 126 of Al/Si1-xGex, 143 of Ti/Si1-xGex, 143 of Ti/Si1-xGex/Al/Si1-xGex, 143 Surface micromachined structures, 119, 125 Surface roughness, 148 Temperature coefficient of resistance (TCR), 101, 106, 107 Texture, 147 Thermal conductivity factors affecting, 114–115 measurement, 115–116 Soft lithography, 12, 13 Sputtering Gold, 67 Nickel, 61 Platinum, 64 Tantalum, 54 Step Coverage of PECVD Ge, 72, 73 LPCVD Ge, 73 Stiction of surface micromachined structures, 9 Stress in thin films, 52–53 Stress in AlSi, 56 AlSi/Si1-xGex, 142 Amorphous silicon, 71 APCVD Poly Si, 117 APCVD Poly Si1-xGex, 117 Chromium, 67, 68 Gold, 67, 68 LPCVD Poly Si, 70–71 N-type Poly Ge, 73–74 PECVD Si3N4, 76–77 Platinum, 64, 65–66 PECVD Si1-xGex, 120, 121, 142 RPCVD Si1-xGex, 117, 119

Index Silicon dioxide, 77, 78 Tantalum, 55–56, 58–60 Titanium, 67, 68 Ti/Si1-xGex, 142 Stress gradient, 53 Stress gradient in AlSi, 58 n-type Poly Ge, 73, 75 laser annealed LPCVD Si1-xGex, 155–157 PECVD Si1-xGex, 128, 129 Si1-xGex, 123, 125–128 Si1-xGex on top of Al, 143 Si1-xGex on top of Ti, 143 Tantalum, 56, 57 SU-8 photoresist, 11 Surface micromachining process flow, 8, 9 sacrificial layer, 9 structural layer, 9 Surface Roughness effect of excimer laser annealing on, 148

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Tantalum attractive features for MEMS, 81 resistivity, 54–57 sputtering, 54 stress, 55–56 stress in Ta/AlSi stack, 58–60 stress gradient, 56–57 Temperature coefficient of resistance, 66, 100, 101, 106 Texture of laser annealed Si1-xGex, 147 Thermal conduction mechanism in Si1-xGex, 114–115 Thermal conductivity of Porous silicon, 78 Silicon dioxide, 77 Silicon germanium, 92, 115–116 Silicon nitride, 73 TiAl3, 37, 38, 40, 41 Titanium, 67, 68, 143 Tungsten plugs, 34, 44 Tungsten interconnects for post processing, 173 Wafer temperature during deposition, 93–94