Advanced MEMS packaging

Advanced MEMS Packaging

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Advanced MEMS Packaging John H. Lau Chengkuo Lee C. S. Premachandran Yu Aibin

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Copyright © 2010 by The McGraw-Hill Companies, Inc. All rights reserved. Except as permitted under the United States Copyright Act of 1976, no part of this publication may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system, without the prior written permission of the publisher. ISBN: 978-0-07-162792-4 MHID: 0-07-162792-8 The material in this eBook also appears in the print version of this title: ISBN: 978-0-07-162623-1, MHID: 0-07-162623-9. All trademarks are trademarks of their respective owners. Rather than put a trademark symbol after every occurrence of a trademarked name, we use names in an editorial fashion only, and to the benefit of the trademark owner, with no intention of infringement of the trademark. Where such designations appear in this book, they have been printed with initial caps. McGraw-Hill eBooks are available at special quantity discounts to use as premiums and sales promotions, or for use in corporate training programs. To contact a representative please e-mail us at [email protected]. Information contained in this work has been obtained by The McGraw-Hill Companies, Inc. (“McGraw-Hill”) from sources believed to be reliable. However, neither McGraw-Hill nor its authors guarantee the accuracy or completeness of any information published herein, and neither McGraw-Hill nor its authors shall be responsible for any errors, omissions, or damages arising out of use of this information. This work is published with the understanding that McGraw-Hill and its authors are supplying information but are not attempting to render engineering or other professional services. If such services are required, the assistance of an appropriate professional should be sought. TERMS OF USE This is a copyrighted work and The McGraw-Hill Companies, Inc. (“McGraw-Hill”) and its licensors reserve all rights in and to the work. Use of this work is subject to these terms. Except as permitted under the Copyright Act of 1976 and the right to store and retrieve one copy of the work, you may not decompile, disassemble, reverse engineer, reproduce, modify, create derivative works based upon, transmit, distribute, disseminate, sell, publish or sublicense the work or any part of it without McGraw-Hill’s prior consent. You may use the work for your own noncommercial and personal use; any other use of the work is strictly prohibited. Your right to use the work may be terminated if you fail to comply with these terms. THE WORK IS PROVIDED “AS IS.” McGRAW-HILL AND ITS LICENSORS MAKE NO GUARANTEES OR WARRANTIES AS TO THE ACCURACY, ADEQUACY OR COMPLETENESS OF OR RESULTS TO BE OBTAINED FROM USING THE WORK, INCLUDING ANY INFORMATION THAT CAN BE ACCESSED THROUGH THE WORK VIA HYPERLINK OR OTHERWISE, AND EXPRESSLY DISCLAIM ANY WARRANTY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. McGraw-Hill and its licensors do not warrant or guarantee that the functions contained in the work will meet your requirements or that its operation will be uninterrupted or error free. Neither McGraw-Hill nor its licensors shall be liable to you or anyone else for any inaccuracy, error or omission, regardless of cause, in the work or for any damages resulting therefrom. McGraw-Hill has no responsibility for the content of any information accessed through the work. Under no circumstances shall McGraw-Hill and/or its licensors be liable for any indirect, incidental, special, punitive, consequential or similar damages that result from the use of or inability to use the work, even if any of them has been advised of the possibility of such damages. This limitation of liability shall apply to any claim or cause whatsoever whether such claim or cause arises in contract, tort or otherwise.

About the Authors John H. Lau earned a Ph.D. in theoretical and applied mechanics from the University of Illinois. He has also earned three master’s degrees. He currently is a visiting professor at the Hong Kong University of Science & Technology (HKUST). His research interests cover a broad range of enabling technologies for 3D IC and system-in-package integration for RoHS-compliant electronics, optoelectronics, photonics, and MEMS packaging. Prior to joining HKUST, Dr. Lau was the director of the Microsystems, Modules, and Components Laboratory at the Institute of Microelectronics in Singapore for 2 years and a Senior Scientist/MTS at Agilent/Hewlett-Packard in California for more than 25 years. With more than 35 years of R&D and manufacturing experience, he has authored or co-authored more than 400 peer-reviewed technical publications, books, book chapters, and papers. Dr. Lau has received awards from ASME and IEEE, and is a Fellow of both organizations. Chengkuo Lee received a Ph.D. in precision engineering from the University of Tokyo, and has also earned two master’s degrees. He worked as a researcher in several labs and then managed the MEMS device division at the Metrodyne Microsystem Corporation in Taiwan. Dr. Lee co-founded Asia Pacific Microsystems, Inc., in Taiwan, and served as vice president. He is now an assistant professor in the Department of Electrical and Computer Engineering at National University of Singapore and a senior member of the technical staff at the Institute of Microelectronics in Singapore. He has authored or co-authored about 200 conference papers, extended abstracts, and peer-reviewed journal articles, and holds eight U.S. patents in the MEMS and nanotechnology fields. C. S. Premachandran earned a master of technology degree in solid state technology from the Indian Institute of Technology, Madras. He has held managerial/ executive positions at Indian Telephone Industries, Sun Fiber Optics, and Delphi Automotive Systems. Since 1998 he has worked as a member of the technical staff in

the Microsystems, Modules, and Components Laboratory at the Institute of Microelectronics, Singapore. He has authored or co-authored more than 50 conference papers and journal articles and holds 10 U.S. patents. He is a Senior Member of IEEE. His research interests are in MEMS and biosensor, optical, and advanced packaging. Yu Aibin received a Ph.D. in electrical and electronic engineering from Nanyang Technological University in Singapore. He is a senior research engineer in the Microsystems, Modules, and Components Laboratory at the Institute of Microelectronics in Singapore. His research interests include advanced packaging and MEMS design, fabrication, and packaging. Dr. Yu has authored or co-authored more than 60 technical publications.

Contents Foreword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi 1

2

3

Introduction to MEMS . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Commercial Applications of MEMS . . . . . . . . 1.3 MEMS Markets . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Top 30 MEMS Suppliers . . . . . . . . . . . . . . . . . . 1.5 Introduction to MEMS Packaging . . . . . . . . . . 1.6 MEMS Packaging Patents since 2001 . . . . . . . 1.6.1 U.S. MEMS Packaging Patents . . . . . 1.6.2 Japanese MEMS Packaging Patents . . . 1.6.3 Worldwide MEMS Packaging Patents . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 1 2 2 5 5 6 6 21

Advanced MEMS Packaging . . . . . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Advanced IC Packaging . . . . . . . . . . . . . . . . . . 2.2.1 Moore’s Law versus More Than Moore (MTM) . . . . . . . . . . . . . . . . . . . 2.2.2 3D IC Integration with WLP . . . . . . . 2.2.3 Low-Cost Solder Microbumps for 3D IC SiP . . . . . . . . . . . . . . . . . . . . 2.2.4 Thermal Management of 3D IC SiP with TSV ....................... 2.3 Advanced MEMS Packaging . . . . . . . . . . . . . . 2.3.1 3D MEMS WLP: Designs and Materials . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 3D MEMS WLP: Processes . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

47 47 47

Enabling Technologies for Advanced MEMS Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 TSVs for MEMS Packaging . . . . . . . . . . . . . . . 3.2.1 Via Formation . . . . . . . . . . . . . . . . . . . 3.2.2 Dielectric Isolation Layer (SiO2) Deposition . . . . . . . . . . . . . . . . . . . . . .

27 43

47 49 52 58 67 68 72 76 81 81 81 82 86

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Contents 3.2.3

3.3

3.4

3.5

3.6

3.7

Barrier/Adhesion and Seed Metal Layer Deposition . . . . . . . . . . . . . . . . . 3.2.4 Via Filling . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 Cu Polishing by Chemical/ Mechanical Polish (CMP) . . . . . . . . . 3.2.6 Fabrication of an ASIC Wafer with TSVs ...................... 3.2.7 Fabrication of Cap Wafer with TSVs and Cavity . . . . . . . . . . . . . . . . . Piezoresistive Stress Sensors for MEMS Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Design and Fabrication of Piezoresistive Stress Sensors . . . . . . . 3.3.2 Calibration of Stress Sensors . . . . . . . 3.3.3 Stresses in Wafers after Mounting on a Dicing Tape . . . . . . . . . . . . . . . . . 3.3.4 Stresses in Wafers after Thinning (Back-Grinding) . . . . . . . . . . . . . . . . . . Wafer Thinning and Thin-Wafer Handling . . . . 3.4.1 3M Wafer Support System . . . . . . . . . 3.4.2 EVG’s Temporary Bonding and Debonding System . . . . . . . . . . . . . . . 3.4.3 A Simple Support-Wafer Method for Thin-Wafer Handling . . . . . . . . . . . . . Low-Temperature Bonding for MEMS Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 How Does Low-Temperature Bonding with Solders Work? . . . . . . . . . . . . . . . 3.5.2 Low-Temperature C2C Bonding . . . . 3.5.3 Low-Temperature C2W Bonding . . . 3.5.4 Low-Temperature W2W Bonding . . . . MEMS Wafer Dicing . . . . . . . . . . . . . . . . . . . . . 3.6.1 Fundamentals of SD Technology . . . 3.6.2 Dicing of SOI Wafers . . . . . . . . . . . . . 3.6.3 Dicing of Silicon-on-Silicon Wafers . . . 3.6.4 Dicing of Silicon-on-Glass Wafers . . . RoHS-Compliant MEMS Packaging . . . . . . . . 3.7.1 EU RoHS . . . . . . . . . . . . . . . . . . . . . . . . 3.7.2 What Is the Definition of X-Free (e.g., Pb-Free)? .................. 3.7.3 What Is a Homogeneous Material? . . . . . . . . . . . . . . . . . . . . . . . . 3.7.4 What Is the TAC? . . . . . . . . . . . . . . . . 3.7.5 How Is a Law Published in the EU RoHS Directive? . . . . . . . . . . . . . . . . .

87 89 91 92 93 93 93 95 98 101 104 104 105 108 111 112 113 122 124 126 126 129 130 130 133 133 134 134 135 135

Contents 3.7.6 3.7.7 3.7.8 References 4

5

EU RoHS Exemptions . . . . . . . . . . . . Current Status of RoHS Compliance in the Electronics Industry . . . . . . . . . Lead-Free Solder-Joint Reliability of MEMS Packages . . . . . . . . . . . . . . . . . ..................................

Advanced MEMS Wafer-Level Packaging . . . . . . . 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Micromachining, Wafer-Bonding Technologies, and Interconnects . . . . . . . . . . . 4.2.1 Thin-Film Technologies . . . . . . . . . . . 4.2.2 Bulk Micromachining Technologies . . . . . . . . . . . . . . . . . . . . 4.2.3 Conventional Wafer-Bonding Technologies for Packaging . . . . . . . . 4.2.4 Plasma-Assisted Wafer-Bonding Technologies . . . . . . . . . . . . . . . . . . . . 4.2.5 Electrical Interconnects . . . . . . . . . . . 4.2.6 Solder-Based Intermediate-Layer Bonding . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Wafer-Level Encapsulation . . . . . . . . . . . . . . . 4.3.1 High-Temperature Encapsulation Process . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Low-Temperature Encapsulation Process . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Wafer-Level Chip Capping and MCM Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Wafer-Level MEMS Packaging Based on Low-Temperature Solders: Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.1 Case Study: In/Ag System of Noneutectic Composition . . . . . . . . . 4.5.2 Case Study: Eutectic InSn Solder for Cu-Based Metallization . . . . . . . . . . . 4.6 Summary and Future Outlook . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optical MEMS Packaging: Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Actuation Mechanisms and Integrated Micromachining Processes . . . . . . . . . . . . . . . . 5.2.1 Electrostatic Actuation . . . . . . . . . . . . 5.2.2 Thermal Actuation . . . . . . . . . . . . . . . 5.2.3 Magnetic Actuation . . . . . . . . . . . . . .

135 138 138 149 157 157 158 158 159 168 172 172 175 176 177 178 180

182 183 193 202 203 209 209 211 212 215 219

ix

x

Contents 5.2.4 5.2.5

Piezoelectric Actuation . . . . . . . . . . . . Integrated Micromachining Processes . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Optical Switches . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Small-Scale Optical Switches . . . . . . . 5.3.2 Large-Scale Optical Switches . . . . . . 5.4 Variable Optical Attenuators . . . . . . . . . . . . . . 5.4.1 Early Development Work . . . . . . . . . 5.4.2 Surface-Micromachined VOAs . . . . . 5.4.3 DRIE-Derived Planar VOAs Using Electrostatic Actuators . . . . . . . . . . . . 5.4.4 DRIE-Derived Planar VOAs Using Electrothermal (Thermal) Actuators . . . . . . . . . . . . . . . . . . . . . . . 5.4.5 3D VOAs . . . . . . . . . . . . . . . . . . . . . . . 5.4.6 VOAs Using Various Mechanisms . . . . . . . . . . . . . . . . . . . . . 5.5 Packaging, Testing, and Reliability Issues . . . . 5.5.1 Manufacturability and Self-Assembly . . . . . . . . . . . . . . . . . . . 5.5.2 Case Study: VOAs . . . . . . . . . . . . . . . . 5.5.3 Case Study: Optical Switches . . . . . . 5.6 Summary and Future Outlook . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Optical MEMS Packaging: Bubble Switch . . . . . . . 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 3D Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Boundary-Value Problem . . . . . . . . . . . . . . . . . 6.3.1 Geometry . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Materials . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 Boundary Conditions . . . . . . . . . . . . . 6.4 Nonlinear Analyses of the 3D Photonic Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 Creep Hysteresis Loops . . . . . . . . . . . 6.4.2 Deflections . . . . . . . . . . . . . . . . . . . . . . 6.4.3 Shear-Stress Time-History . . . . . . . . . 6.4.4 Shear-Creep-Strain Time-History . . . 6.4.5 Creep-Strain Energy-Density Range . . . . 6.5 Isothermal Fatigue Tests and Results . . . . . . . 6.5.1 Sample Preparation . . . . . . . . . . . . . . 6.5.2 Test Setup and Procedures . . . . . . . . . 6.5.3 Test Results . . . . . . . . . . . . . . . . . . . . . 6.6 Thermal Fatigue Life Prediction of the Sealing Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . .

219 221 224 225 233 237 238 240 242

252 254 258 261 264 269 275 285 286 297 297 297 302 302 302 305 306 306 307 307 307 308 309 309 309 312 314

Contents 6.7 Appendix A: Package Deflection by Twyman-Green Interferometry Method . . . . 6.7.1 Sample Preparation . . . . . . . . . . . . . . 6.7.2 Test Setup and Procedure . . . . . . . . . 6.7.3 Temperature Conditions . . . . . . . . . . 6.7.4 Measurement Results . . . . . . . . . . . . . 6.8 Appendix B: Package Deflection by Finite-Element Method . . . . . . . . . . . . . . . . . . . 6.9 Appendix C: Finite-Element Modeling of the Bolt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.1 Description of the Bolted Model . . . . 6.9.2 Responses of the Bolted Photonic Switch . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

8

Optical MEMS: Microbolometer Packaging ..... 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Bolometer Chip . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Thermal Optimization . . . . . . . . . . . . . . . . . . . 7.3.1 Final Temperature Stability Testing . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Structural Optimization of the Package .... 7.5 Vacuum Packaging of Bolometer . . . . . . . . . . 7.5.1 Ge Window . . . . . . . . . . . . . . . . . . . . . 7.6 Getter Attachment and Activation . . . . . . . . . 7.7 Outgassing Study in a Vacuum Package . . . . 7.8 Testing Setup for Bolometer . . . . . . . . . . . . . . . 7.8.1 Package Testing . . . . . . . . . . . . . . . . . . 7.8.2 Image Testing . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bio-MEMS Packaging . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Bio-MEMS Chip ........................ 8.3 Microfluidic Components . . . . . . . . . . . . . . . . 8.3.1 Microfluidic Cartridge . . . . . . . . . . . . 8.3.2 Biocompatible Polymeric Materials . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Microfluidic Packaging .................. 8.4.1 Polymer Microfabrication Techniques . . . . . . . . . . . . . . . . . . . . . . 8.4.2 Replication Technologies . . . . . . . . . . 8.4.3 Overview of Existing DNA and RNA Extractor Biocartridges . . . . . . . 8.5 Fabrication of PDMS Layers . . . . . . . . . . . . . . 8.6 Assembly of PDMS Microfluidic Packages . . .

314 315 316 317 317 317 320 320 322 325 327 327 329 330 334 335 340 342 344 346 347 347 350 352 353 353 355 357 357 359 362 362 362 363 364 364

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Contents 8.6.1

Microfluidic Package without Reservoirs . . . . . . . . . . . . . . . . . . . . . . . 8.6.2 Development of Reservoir and Valve . . . . . . . . . . . . . . . . . . . . . . . 8.7 Self-Contained Microfluidic Cartridge ..... 8.7.1 Microfluidic Package with Self-Contained Reservoirs . . . . . . . . . 8.7.2 Pin-Valve Design . . . . . . . . . . . . . . . . . 8.7.3 Fluid Flow-Control Mechanism . . . . 8.8 Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8.1 Substrate Fabrication . . . . . . . . . . . . . 8.8.2 Material Selection for the Reservoir Membrane . . . . . . . . . . . . . . . . . . . . . . 8.9 Permeability of Material . . . . . . . . . . . . . . . . . . 8.10 Thermocompression Bonding . . . . . . . . . . . . . 8.10.1 Bonding of PMMA to PMMA for the Channel Layer . . . . . . . . . . . . . . . . . . . 8.10.2 Polypropylene to PMMA for Reservoir and Channel Layer . . . . . . 8.10.3 Tensile Test . . . . . . . . . . . . . . . . . . . . . . 8.11 Microfluidic Package Testing . . . . . . . . . . . . . . 8.11.1 Fluid Testing . . . . . . . . . . . . . . . . . . . . 8.11.2 Biologic Testing on a Biosample . . . . 8.12 Sample Preparation and Setup . . . . . . . . . . . . 8.12.1 Pretreatment of the Cartridge ..... 8.12.2 PCR Amplification . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Biosensor Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.1 Review of Optical Coherence Tomography (OCT) . . . . . . . . . . . . . . 9.2 Biosensor Packaging .................... 9.2.1 Micromirror . . . . . . . . . . . . . . . . . . . . . 9.2.2 Single-Mode Optical Fiber and GRIN Lens . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.3 Upper Substrate . . . . . . . . . . . . . . . . . 9.2.4 Lower Substrate . . . . . . . . . . . . . . . . . 9.3 The Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.1 Configuration of the Probe . . . . . . . . 9.3.2 Optical Properties and Theories ... 9.3.3 Evaluations of Parameters . . . . . . . . . 9.4 Optical Simulation . . . . . . . . . . . . . . . . . . . . . . . 9.4.1 Optical Model of the Probe . . . . . . . . 9.4.2 Effect of Mirror Curvature on Coupling Efficiency . . . . . . . . . . . . . .

366 370 371 371 374 375 377 377 381 381 384 385 387 390 391 391 392 394 394 394 395 397 397 398 401 401 401 403 404 404 404 406 410 412 412 415

Contents 9.4.3 Effect of Lateral Tilt of a Flat Micromirror on a Curved Sample . . . . 9.4.4 Effect of Vertical Tilt of a Flat Micromirror on a Curved Sample . . . 9.4.5 Effect of Vertical Tilt of a Flat Micromirror on a Flat Sample . . . . . . 9.5 Assembly of the Optical Probe . . . . . . . . . . . . 9.5.1 Fabrication of SiOB . . . . . . . . . . . . . . . 9.5.2 Probe Assembly . . . . . . . . . . . . . . . . . . 9.5.3 Probe Housing .................. 9.6 Testing of the Probe ..................... 9.6.1 Optical Alignment . . . . . . . . . . . . . . . 9.6.2 Axial Scanning Test Result . . . . . . . . . 9.6.3 Probe Imaging .................. 9.6.4 Optical Efficiency Testing . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

11

Accelerometer Packaging . . . . . . . . . . . . . . . . . . . . . . 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Wafer-Level Package Requirements ....... 10.2.1 Electrical Modeling . . . . . . . . . . . . . . . 10.2.2 Package Structure . . . . . . . . . . . . . . . . 10.2.3 Extraction Methodology of the Interconnection Characteristics . . . . . 10.3 Wafer-Level Packaging Process . . . . . . . . . . . . 10.3.1 Method 1: TSV with Sacrificial Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 Method 2: TSV without Sacrificial Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.3 Method 3: TSV with MEMS Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 Wafer Separation Process . . . . . . . . . . . . . . . . . 10.4.1 Process Integration . . . . . . . . . . . . . . . 10.5 Sacrificial Wafer Removal . . . . . . . . . . . . . . . . 10.6 Wafer-Level Vacuum Sealing ............. 10.7 Vacuum Measurement Using a MEMS Motion Analyzer ....................... 10.8 Reliability Testing: Vacuum Maintenance ... 10.9 Wafer-Level 3D Package for an Accelerometer . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Radiofrequency MEMS Switches . . . . . . . . . . . . . . 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Design of RF MEMS Switches . . . . . . . . . . . . . 11.2.1 Design of Capacitive Switches . . . . .

417 419 420 421 421 422 425 427 427 427 429 431 433 435 435 437 438 438 442 448 450 450 452 458 460 462 464 467 469 471 473 475 475 475 475

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Contents 11.2.2 Design of Metal-Contact Switches . . . . 11.2.3 Mechanical Design of RF MEMS Switches . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Fabrication of RF MEMS Switches . . . . . . . . . 11.3.1 Surface Micromachining of RF MEMS Switches . . . . . . . . . . . . . . . . . . 11.3.2 Bulk Micromachining of RF MEMS Switches . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Characterization of RF MEMS Switches . . . . 11.4.1 RF Performance . . . . . . . . . . . . . . . . . . 11.4.2 Mechanical Performance . . . . . . . . . . 11.5 Reliability of RF MEMS Switches . . . . . . . . . . 11.5.1 Reliability of Capacitive Switches . . . . . . . . . . . . . . . . . . . . . . . . 11.5.2 Reliability of Metal-Contact Switches . . . . . . . . . . . . . . . . . . . . . . . . 11.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

13

RF MEMS Tunable Capacitors and Tunable Band-Pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 RF MEMS Tunable Capacitors . . . . . . . . . . . . 12.2.1 Analog Tuning of RF MEMS Capacitors . . . . . . . . . . . . . . . . . . . . . . 12.2.2 Digital Tuning of RF MEMS Capacitors . . . . . . . . . . . . . . . . . . . . . . 12.3 RF MEMS Tunable Band-Pass Filters . . . . . . . 12.3.1 Analog Tuning of a MEMS Band-Pass Filter . . . . . . . . . . . . . . . . . . 12.3.2 Digital Tuning of an RF MEMS Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

479 479 484 484 488 489 489 489 492 492 492 492 493 495 495 495 496 503 504 505 506 512 513

Advanced Packaging of RF MEMS Devices . . . . . 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 Zero-Level Packaging . . . . . . . . . . . . . . . . . . . . 13.2.1 Chip Capping . . . . . . . . . . . . . . . . . . . 13.2.2 Thin-Film Capping . . . . . . . . . . . . . . . 13.3 One-Level Packaging . . . . . . . . . . . . . . . . . . . . 13.4 Reliability of Packaged RF MEMS Devices . . . 13.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

515 515 515 516 523 525 526 528 528

Index

531

.......................................

Foreword

T

he invention of the bipolar junction transistor and the junction field-effect transistor by Bardeen, Brattain, and Shockley in 1956 foreshadowed the development of generations of smart phones and computers yet to come. The invention of the silicon integrated circuit (IC) by Jack Kilby of Texas Instruments in 1958 and 6 months later by Robert Noyce of Fairchild Semiconductor excited the development of generations of integrations. The proposal of doubling the number of transistors on an IC every 24 months by Gordon Moore in 1965 (also called Moore’s law) has been the most powerful driver for the development of the microelectronic industry in the past 44 years. This law emphasizes lithography scaling and integration (in two dimensions) of all functions on a single chip, through system-on-chip (SoC). Apart from SoC, integration of all these functions can be achieved through system-in-package (SiP) or, ultimately, three-dimensional IC integration, which can be called “more than Moore.” Based on siliconplatform technology, anything that involves the integration of electronics, photonics, mechanics, chemistry, heat, magnetics, biology, etc., for functionality and system performance when interacting with people and the environment is known as more than Moore. Microelectromechanical systems (MEMS) is a part of it. Yole Development forecasted the MEMS market to be $14 billion by 2012. The packaging cost of MEMS products in general is about 70 percent. Thus MEMS packaging could be a $10 billion market by 2012. Unlike electronics IC packaging, MEMS packaging is custombuilt and difficult due to the moving structural elements. For some MEMS devices, such as resonators, infrared bolometers, and gyroscopes, vacuum packaging is required. For most researchers and engineers, advanced MEMS packaging is the least understood of all. Thus, there is an urgent need to generate a comprehensive book on the current state of knowledge in the design, materials, process, manufacturing, and reliability of advanced MEMS packaging technology. Institute of Microelectronics (IME), Singapore, one of the research institutes of the Agency for Science, Technology and Research (A∗STAR), has been publishing MEMS papers extensively in a wide spectrum

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Foreword of journals, conference proceedings, symposia, and workshops. However, there is no single comprehensive compilation of information devoted to state-of-the-art advanced MEMS packaging. This book is written for everyone who can quickly learn about the basics and problem-solving methods, understand the trade-offs, and make system-level decisions. John Lau, Chengkuo Lee, C. S. Premachandran, and Yu Aibin of IME have taken the time and made the effort to complete this book on this timely topic of advanced MEMS packaging. This book will help focus the attention of practicing engineers and research scientists, as well as faculty and students, on the complex MEMS packaging challenges that must be overcome. I wish that this book will serve future generations of engineers, scientists, and students who will continue to advance the science and engineering of MEMS packaging. With their predecessors’ knowledge and their creativity, there is no doubt this wish will come true. Professor Dim-Lee Kwong Executive Director Institute of Microelectronics Singapore

Preface

T

he last decade witnessed an explosive growth in research and development efforts devoted to advanced microelectromechanical systems (MEMS) packaging as a direct result of higher requirements for package footprint, density, and performance and cost advantages over conventional MEMS packages. For the next decade, MEMS devices and packaging will penetrate into IT, telecommunications, automotive, life sciences, medical, and implantable applications. However, like many other new technologies, advanced MEMS packaging still has many critical issues that need to be addressed. In the development of advanced MEMS packaging, the following must be noted and understood: The infrastructure of MEMS devices and MEMS packaging is not well established; MEMS packaging expertise is not commonly available; MEMS packaging is unique and custom-built; MEMS general packaging platform technology is not available; hermetic sealing of the MEMS device is necessary; vacuum packaging is even required for some MEMS devices; vertical electrical feed-through with through-silicon vias (TSVs) is still too costly; bare ASIC die/wafers are not commonly available for three-dimensional (3D) integration; bare thin die/wafer handling is not easy; pick and place is more difficult; low-temperature bonding is not mature enough for high-volume production; rework is more difficult; micro solder bumping, assembly, and reliability are more critical; inspection is more difficult; MEMS assembly testability is not well established; dies shrink and expand; known-good-die; thermal management; wafer dicing; and device/chip cracking during bonding. In the past few years, some of these critical issues have been studied by experts in the field. Their results have been disclosed in diverse journals and in the proceedings of many conferences, symposia, and workshops whose primary emphases are electrical designs, materials science, manufacturing engineering, or electronic packaging and interconnection. Consequently, there is no single source of information devoted to the state of the art of advanced MEMS packaging technologies for, e.g., inertial, optical, RF, BioMEMS, and medical MEMS devices. This book aims to remedy this deficiency

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Preface by presenting in one complete and concise volume a summary of the progress in this fascinating field that has occurred within the past few years. This book is written for everyone so that they can quickly learn the basics, grasp problem-solving methods, understand the tradeoffs, and make system-level decisions with advanced MEMS packaging technologies. This book is organized into five parts. Chapter 1, the first part, briefly discusses MEMS devices, commercial applications, and markets. MEMS packaging is also briefly mentioned, and some of the MEMS packaging patents from the United States, Japan, and the world since 2001 are provided. Chapter 2, the second part, briefly discusses the state of the art and future trends of advanced integrated-circuit (IC) electronics packaging. It is followed by advanced MEMS packaging, where 10 different designs of 3D MEMS packaging and their assembly processes are presented. There are two chapters in the third part, where some important enabling technologies for advanced MEMS packaging are presented. In Chapter 3, TSVs, stress sensors, wafer thinning and thin-wafer handling, low-temperature C2C, C2W, and W2W bonding, wafer dicing, and the reliability of RoHS-compliant MEMS packaging are discussed. Chapter 4 focuses on wafer-level packaging, where micromachining, wafer-level encapsulation, wafer-level chip capping, and a couple of case studies on wafer bonding based on low-temperature solder for MEMS packaging are presented. The fourth part has six chapters, and its focus is on the applications of advanced packaging on some MEMS devices. Chapter 5 presents an overview of microfabrication technology and major actuation mechanisms in enabling optical MEMS, followed by two well-studied optical MEMS devices in communications: optical switches and variable optical attenuators (VOAs). All aspects of MEMS design, manufacturability, packaging, and reliability are discussed. Chapter 6 presents the packaging and thermal reliability of the solder sealing ring of an RoHS-compliant 3D bubble-actuated photonic crossconnect switch. Emphasis is placed on determination of the thermal fatigue life of the lead-free solder sealing ring under shipping, storing, and handling conditions. Chapter 7 outlines the design, process, packaging, and testing of a bolometer vacuum package. The challenge of vacuum packaging and maintaining the temperature within ±0.1°C, packaging material and getter selections, and testing are presented. Chapter 8 presents the design, materials, process, and testing of bio-MEMS packaging. Emphasis is placed on the process developments of the microfluidics package and its application to extracting dengue virus from the samples. Chapter 9 presents the design, materials, process, and testing of MEMS packaging of a biosensor (micromirror) in an optical probe, which can take images from body tissues. Chapter 10 presents a wafer-level package with

Preface TSV interconnects and a wafer-level vacuum package with lateral electrical feed-through interconnects for accelerometer devices. For TSV interconnects, the die shear and hermeticity tests are used to characterize the package, and their results are discussed. For waferlevel vacuum packages, the C-V curves subjected to reliability tests and the Q-factor measurement of the vacuum inside the package are presented. The fifth part of this book covers radio frequency (RF) MEMS and packaging. Chapter 11 presents the design, fabrication, and characterization of RF MEMS switches. Emphasis is placed on mechanical and electrical design for performance, the micromachining and bulk micromachining processes, and maintaining an insertion loss of the MEMS switch that is lower than 0.5 dB up to 40 GHz and an isolation higher than 15 dB at 10 GHz. Chapter 12 presents different RF MEMS circuits, including tunable capacitors and tunable band-pass filters, which consist of different MEMS switches and can be tuned analogically or digitally. Usually the digital tuning approach has a larger tuning range and has more flexibility for constructing different tuning circuits. Chapter 13 presents the zero-level and first-level packaging of RF MEMS switches, which must be packaged in a nitrogen or dryair atmosphere (for high reliability) owing to hermeticity, temperature, and outgassing constraints. In zero-level packaging, capping of RF MEMS devices can be categorized as chip capping and thin-film capping. In first-level packaging, plastic packaging is the most common solution applicable for frequencies below several gigahertz, and ceramic packages exhibit the potential for good performance into the millimeter-wave region. For whom is this book intended? Undoubtedly, it will be of interest to three groups of specialists: (1) those who are active or intend to become active in research and development of MEMS devices and packaging, (2) those who have encountered practical MEMS packaging problems and wish to understand and learn more methods for solving such problems, and (3) those who have to choose a reliable, creative, high-performance, robust, and cost-effective packaging technique for their MEMS devices. This book also can be used as a text for undergraduate and graduate students who have the potential to become our future leaders, scientists, and engineers in the electronics, optoelectronics, and photonics industries. We hope that this book will serve as a valuable reference source for all those faced with the challenging problems created by the everincreasing interest in MEMS devices and packaging. We also hope that it will aid in stimulating further research and development on optical, electrical, thermal, and mechanical designs, materials, processes, manufacturing, testing, and reliability and more sound applications of advanced packaging technologies in MEMS products. The organizations that learn how to design advanced MEMS packaging in their interconnect systems have the potential to make

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Preface major advances in the electronics industry and to gain great benefits in cost, performance, quality, size, and weight. It is our hope that the information presented in this book may assist in removing road blocks, avoiding unnecessary false starts, and accelerating design, materials, and process development of MEMS packaging. We are strongly against the notion that packaging is the bottleneck of advanced MEMS applications. Rather, we would like to consider this as a golden opportunity to make a major contribution to the MEMS industry by developing innovative, high-performance, cost-effective, and reliable packaging for MEMS products. It is an exciting time for advanced (especially 3D) MEMS packaging! John H. Lau Chengkuo Lee C. S. Premachandran Yu Aibin

Acknowledgments

D

evelopment and preparation of Advanced MEMS Packaging was facilitated by the efforts of a number of dedicated people. We would like to thank them all, with special mention to Michael Mulcahy of McGraw-Hill and Somya Rustagi of Glyph International for their unswerving support and advocacy. Our special thanks go to Taisuke Soda and Steve Chapman of McGraw-Hill, who made our dream of this book come true by effectively sponsoring the project, patiently listening to our excuses for delay, and solving many problems that arose during the book’s preparation. It has been a great pleasure and fruitful experience to work with all of them in transferring our messy manuscripts into a very attractive printed book. The material in this book clearly has been derived from many sources, including individuals, companies, and organizations, and we have attempted to acknowledge by citations, in the appropriate parts of the book, the assistance that we have been given. It would be quite impossible for us to express our thanks to everyone concerned for their cooperation in producing this book, but we would like to extend due gratitude. Also, we want to thank several professional societies and publishers for permitting us to reproduce some of their illustrations and information in this book, including the American Society of Mechanical Engineers (ASME) Conference Proceedings (e.g., International Intersociety Electronic Packaging Conference) and Transactions (e.g., Journal of Electronic Packaging), the Institute of Electrical and Electronic Engineers (IEEE) Conference Proceedings (e.g., Electronic Components & Technology Conference) and Transactions (e.g., Advanced Packaging, Components and Packaging Technologies, and Manufacturing Technology), the International Microelectronics and Packaging Society (IMAPS) Conference Proceedings (e.g., International Symposium on Microelectronics) and Transactions (e.g., International Journal of Microcircuits & Electronic Packaging), the IBM Journal of Research and Development, Electronic Packaging & Production, Advanced Packaging, Circuits Assembly, Surface Mount Technology, Connection Technology, Solid State Technology, Circuit World, Microelectronics International, and Soldering and Surface Mount Technology.

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Acknowledgments John Lau would like to thank his former employers, the Institute of Microelectronics (IME), Agilent, and HP, for providing him excellent working environments that have nurtured him as a human being, fulfilled his need for job satisfaction, and enhanced his professional reputation. He also would like to thank Professor Dim-Lee Kwong for his trust, respect, and support of his work at IME, Agency for Science, Technology and Research (A∗STAR), Singapore. Furthermore, he would like to thank Dr. Lim Thiam Beng for helping to bring him into IME and all the members of the Microsystems, Modules, and Components Laboratory for their stimulating discussions, teamwork, and friendship. With respect to this book, Dr. Lau would like to single out the significant contributions of Zhang Xiaowu, Tang Gongyue, Cheryl Selvanayagam, Aditya Kumar, Yan Li Ling, Choi Won Kyoung, Kelvin Chen, Ahmad Kharyanto Bin Ratmin, Navas Khan, Chai Tai Chong, Yu Da Quan, N. Ranganathan, Ebin Liao, Li Hong Yu, Qing Xin Zhang, Seung Yoon, Feng Hanhua, Xie Ling, Ong Yue Ying, Wai Yin Hnin, Eva Wai, Damaruganath Pinjala, Vaidyanathan Kripesh, and Joanne Tan. Finally, he would like to thank his eminent colleagues (the enumeration of whom would not be practical here) at HKUST, IME, HP, and Agilent and throughout the electronics industry for their useful help, strong support, and stimulating discussions. Working and socializing with them has been a privilege and an adventure. He learned a lot about life and advanced packaging and interconnection technologies from them. Chengkuo Lee would like to thank his colleagues at Asia Pacific Microsystems, Inc., in Hsinchu, Taiwan, for their excellent work in MEMS packaging technology development. In particular, Mr. Ming Hung Tasi, Mr. Chia-Yu Wu, Mr. Chihchung Chen, Dr. Yen-Jyh Lai, Mr. Yu-Shen Lin, Mr. Shih-Yun Hung, Mr. Wen-Chih Chen, Dr. ShihChin Gong, and Professor Ruey-Shing Huang are specially acknowledged. Dr. Lee also appreciates his colleagues at the Institute of Microelectronics, A∗STAR, Singapore, for their research work in MEMS wafer-level packaging technology. To name a few, Dr. Daquan Yu, Dr. Li Ling Yan, Dr. Won Kyoung Choi, Dr. Johnny H. He, Dr. Qing Xin Zhang, Dr. Seung-Uk Yoon, and Dr. Hanhua Feng are appreciated most. Dr. Lee extends thanks to Mr. Riko I Made and Professor Chee Lip Gan from the School of Materials Science and Engineering, Nanyang Technological University, for their work in InAg solder bonding. He is further indebted to Professor J. Andrew Yeh at National Tsing Hua University, Hsinchu, Taiwan; Professor T. Suga, Professor H. Toshiyoshi, and Professor H. Fujita at the University of Tokyo, Tokyo, Japan; Dr. R. Maeda, Dr. T. Itoh, and Dr. T. Kobayashi of AIST, Tsukuba, Japan; Professor R. Sawada at Kyushu University, Fukuoka, Japan; Professor R. R. A. Syms at Imperial College, London, United Kingdom; and Professor Lih Y. Lin at the University of Washington, Seattle, Washington, for information on their research results and their continuous support. Dr. Lee also

Acknowledgments acknowledges Professor C.-C. Chen at the National Central University, Jhong-Li, Taiwan, and Professor John T. L. Thong, Professor W. K. Choi, Professor G. Pastorin, and Dr. Fu-Li Hsiao at the National University of Singapore for their continuous support and encouragement. C. S. Premachandran would like to acknowledge and thank his colleagues Ling Xie and Michelle Chew for their contribution on bioMEMS packaging; Dr. Pavel Neuzil, Chong Ser Choong, Navas Khan, Damaruganath Pinjala, Chai Tai Chong, and Dr. Zhang Xiao Wu for their contribution on optical MEMS—bolometer packaging; Dr. Janak Singh, Xu Yingshun, Kelvin Chen, Ahmad Khairyanto, Pamidighantam Ramana, Chuah Tong Kuan, and Jaya Krishnan Chandrappan for their contribution on biosensor packaging; and Dr. Mahadevan K. Iyer, Rangnathan Nagarajan, Choong Ser Chong, Mihai D. Rotaru, Dr. Chen Yu, and Dr. Vaidyanathan Kripesh for their contribution on accelerometer packaging. Finally, he would like to thank Dr. Lim Thiam Beng, who has inspired him in the MEMS packaging research area. Yu Aibin would like to thank all the authors cited in the reference lists for sharing their important and useful knowledge. He also would like to thank Professor AiQun Liu from Nanyang Technological University, Singapore, and Dr. Zhang Qingxin from the Institute of Microelectronics, Singapore, for invaluable support. Lastly, John Lau wants to thank his daughter Judy and his wife Teresa for their love, consideration, and patience by allowing him to work peacefully on this book. Their simple belief that he is making a small contribution to the electronics industry was a strong motivation for him. Knowing that Judy has earned her Ph.D. degree in physics from Princeton University and is working for Stanford University and that Teresa and he are in good health, he wants to thank God for his generous blessings. Chengkuo Lee shares the same feelings about his family. For a certain period of time, he slept only 4 hours a day on average while working on this book. Without the spiritual support of his family, he could never have struggled through those exhausting nights! C. S. Premachandran would like to thank his wife, Asha Venugopal, and their loving children, Karthik and Swetha, for their continuous support, love, and understanding while he worked on this book. Yu Aibin wishes to express his gratitude to his parents for all their support through the years; to his wife, Zhu Suli, for her understanding and loving support; and to his lovely daughter, Yu Wanxin, for her joyful time.

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CHAPTER

1

Introduction to MEMS 1.1

Introduction MEMS stand for microelectromechanical systems, which are the integration of mechanical elements such as sensors and actuators and electronics on a common silicon substrate through the use of microfabrication technology.1–41 The same basic technology and process steps such as the etching, patterning, doping, and connecting employed for making conventional electronic integrated circuits (ICs) such as complementary metal-oxide-semiconductors (CMOS) can be used to fabricate (micromachining) micromechanical elements by selectively etching away parts of a silicon wafer or adding new structural layers to form MEMS devices. However, there is a fundamental difference between MEMS and ICs devices—namely, MEMS devices must remain physically movable. MEMS devices use electronics to move their mechanical elements (parts)! MEMS are made up of elements between 1 and 100 μm (0.001 and 0.1 mm) in size, and MEMS devices generally range in size from 20 to 1000 μm.42 Nanoelectromechanical systems (NEMS) are similar to MEMS but much smaller, and they hold the promise of improving the ability to measure infinitesimal displacements and forces on the molecular scale but will not be discussed in this book. Micro-opto-electromechanical systems (MOEMS) are a special class of MEMS that use electronics to move mechanical parts that can sense and control light and manipulate optical signals. Their fabrication technology and process are similar to those of MEMS except that in addition to silicon materials, they also use, for example, gallium arsenide.

1

2 1.2

Chapter One

Commercial Applications of MEMS MEMS provide a combination of mechanical functions (e.g., sensing, moving, and heating) and electrical functions (e.g., switching and deciding). Some commercial applications42 of MEMS today are as follows: • Inkjet printers, which use piezoelectric or thermal bubble ejection to deposit ink on paper • Accelerometers in modern cars for a large number of purposes, including airbag deployment in collisions • Accelerometers in consumer electronic devices such as game controllers (Nintendo Wii), personal media players/cell phones (Apple iPhone), and a number of digital cameras (various Canon Digital IXUS models), as well as in PCs to park the hard-disk head when free fall is detected to prevent damage and data loss • MEMS gyroscopes used in modern cars and other applications to detect yaw (e.g., to deploy a roll-over bar or trigger dynamic stability control) • Silicon pressure sensors such as car tire-pressure sensors and disposable blood pressure sensors • Displays in projectors (e.g., the DMD chip) based on DLP technology, which has on its surface several hundred thousand micromirors • Optical switching technology such as that used for switching and aligning data communications • Bio-MEMS applications in medical and health related technologies from Lab-On-a-Chip to MicroTotalAnalysis (e.g., biosensors and chemosensors) • Interferometric modulator displays (IMOD) in consumer electronics (primarily displays for mobile devices), which are used to create interferometric modulation (i.e., reflective display technology as found in Mirasol displays)

1.3

MEMS Markets The MEMS market forecast by Yole Development calls for $10 billion by 2010 and $14 billion by 2012. [For 2008, Jean Christophe Eloy, CEO of Yole, expects the market to be $7.8 billion. This represents a combined annual growth rate (CAGR) of 14 percent for the 2007–2012 period. The 2007–2010 growth, however, will be quite modest (11 percent), but strong growth is expected after 2010.] The packaging cost of a MEMS product

Introduction to MEMS in general is between 60 and 80 percent. Thus MEMS packaging could be a $7 billion market by 2010 and $10 billion by 2012. The MEMS devices that make up the market forecast are, for example, inkjet (IJ) heads, pressure sensors, silicon microphones, accelerometers, gyroscopes, MOEMS devices, microbolometers, microdisplays, microfluidics, radiofrequency (RF) MEMS, microtips, microfuel cells, and emerging MEMS. These MEMS devices can be applied to the automotive, aeronautics, consumer, defense, industrial, medical, life science, and telecommunication industries. Their units and market values have been provided by Yole Development and are shown in Figs. 1-1 and 1-2, which also include the forecasts up to 2012. It can be seen that the value of MEMS production is expected to double in 2012 (from 2007) and that the total units of MEMS production are expected to quadruple in 2012 (from 2007). According to Jean Christophe Eloy, whose company tracks 150 MEMS applications, RF MEMS is expected to have the highest growth (50 percent) (Figs. 1-3 and 1-4), followed by microfluidic chips for drug delivery (42 percent), silicon microphones (32 percent), microfluidic chips for diagnostics (23 percent), microtips and microprobes (22 percent), and microbolometers (20 percent). Eloy also said that the most promising MEMS devices include accelerometers for humanmachine interfaces, with a CAGR exceeding 120 percent, followed by RF-MEMS devices for automatic test equipment (81 percent).

16,000.0 Defense

14,000.0

Aeronautics

Million, $ US

12,000.0

Industrial

10,000.0

Telecom

8,000.0

Life science

6,000.0

Medical 4,000.0 Automotive 2,000.0

Consumer

0.0 2006 Consumer Automotive Medical Lifescience Telecom Industrial Aeronautics Defense

2007

2008

2009

2010

2011

2012

2006

2007

2008

2009

2010

2011

2012

854.4 375.6 49.6 154.5 257.8 23.7 0.3 0.8

997.9 422.7 58.1 173.4 386.2 25.2 0.3 1.1

1,231.0 480.5 70.8 199.2 539.9 27.9 0.4 1.4

1,531.9 510.7 85.5 228.8 799.2 36.3 0.5 1.8

1,999.3 541.1 112.0 274.7 1,274.4 49.5 0.5 2.1

2,689.8 571.4 132.1 367.7 2,005.9 64.2 0.6 2.4

3,504.4 615.3 139.5 494.4 3,214.7 154.9 0.6 3.2

FIGURE 1-1 MEMS value market forecast for 2006–2012 ($ US millions).

3

Chapter One

Million, units

9,000.0 8,000.0

Defense

7,000.0

Aeronautics

6,000.0

Industrial

5,000.0

Telecom

4,000.0

Life science

3,000.0

Medical

2,000.0

Automotive

1,000.0 Consumer 0.0 2006 Consumer Automotive Medical Life science Telecom Industrial Aeronautics Defense

2007

2008

2009

2010

2011

2012

2006

2007

2008

2009

2010

2011

2012

2,825.2 1,277.7 336.0 432.6 380.4 853.9 30.0 258.1

2,919.4 1,362.2 381.3 494.6 556.3 912.0 37.8 343.2

3,322.3 1,421.8 422.8 573.4 650.2 991.4 45.4 415.3

3,639.7 1,464.7 457.7 664.3 791.4 1,107.2 52.6 489.3

4,129.2 1,464.0 495.2 788.6 1,002.5 1,244.9 59.8 558.9

4,608.6 1,485.9 535.7 1,254.6 1,325.2 1,439.8 66.0 628.9

5,415.3 1,572.4 560.1 1,645.6 1,827.7 1,945.3 78.5 824.8

FIGURE 1-2 MEMS volume market forecast for 2006–2012 (millions of units).

1,600.0 1,400.0

Million, $ US

4

1,200.0 1,000.0 800.0

RF-MEMS for consumer RF-MEMS for defense RF-MEMS for aeronautics RF-MEMS for industrial RF-MEMS for telecom

600.0 400.0 200.0 0.0 2006 2007 2008 2009 2010 2011 2012

RF-MEMS for telecom RF-MEMS for industrial RF-MEMS for aeronautics RF-MEMS for defense RF-MEMS for consumer

2006

2007

2008

2009

2010

2011

2012

179.0

321.1

385.5

467.9

632.4

888.2

1,284.9

1.0

4.5

9.4

17.6

36.1

56.9

95.8

0.0

0.0

0.0

0.0

0.1

0.1

0.2

0.2

0.8

2.1

4.3

9.0

14.1

22.9

0.0

0.5

2.0

5.0

10.0

20.0

25.0

FIGURE 1-3 RF-MEMS value market forecast for 2006–2012 ($US millions).

Introduction to MEMS 2,500.0

Million, units

2,000.0 1,500.0

RF-MEMS for consumer RF-MEMS for defense RF-MEMS for aeronautics RF-MEMS for industrial RF-MEMS for telecom

1,000.0 500.0 0.0 2006 2007 2008 2009 2010 2011 2012

RF-MEMS for telecom RF-MEMS for industrial RF-MEMS for aeronautics RF-MEMS for defense RF-MEMS for consumer

2006

2007

2008

2009

2010

2011

2012

3.0

5.0

8.3

96.4

371.0

894.7

1,826.2

0.0

0.2

0.4

0.9

2.6

5.3

11.7

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.1

0.1

0.0

5.0

20.0

50.0

100.0

200.0

250.0

FIGURE 1-4 RF-MEMS volume market forecast for 2006–2012 (millions of units).

1.4 Top 30 MEMS Suppliers The top 30 MEMS suppliers ranked by Yole Development 43 are Hewlett-Packard (HP), Texas Instruments (TI), Robert Bosch, Lexmark, Seiko Epson, STMicroelectronics, Freescale Semiconductor, Canon, Analog Devices, Systron Donner, Denso, Avago Technologies, GE Sensing, Honeywell, Infineon Technology, Delphi, Olivettii-Jet, Boehringer Ingelheim Microparts, VTI Technologies, Panasonic, Formfactor, Knowles Electronics, Murata, Continental Automotive, Measurement Specialties, Inc., Flir Systems, Ulis, Omron, Silicon Sensing Systems, and Colibrys. These 30 companies’ global sales totaled approximately $6 billion in 2007, representing approximately 80 percent of the global MEMS market. HP is the largest supplier, mainly supplying inkjet printheads, followed by TI, which mainly provides the digital light processor. For more information about these companies and many others, please see ref. 43.

1.5

Introduction to MEMS Packaging The MEMS device is not an isolated island. It must communicate with other integrated circuit (IC) chips in a circuit through an input/ output (I/O) system of interconnects. Furthermore, the MEMS device needs to be powered up, and its embedded circuitry and elements are

5

6

Chapter One delicate, requiring the package to both carry and protect the device. Consequently, the major functions of MEMS packaging are (1) to provide a path for the electrical current that powers the circuit and moves the moving elements, (2) to distribute the signals onto and off the MEMS device, (3) to remove the heat generated by the circuit, and (4) to support and protect the MEMS device from hostile environments. Unlike electronics IC packaging,44–56 MEMS packaging is not trivial, is expensive (60 to 80 percent of the product total cost), and is custom-built. Electronics IC packaging is a well-developed technology (e.g., wire bonding, tape automated bonding, and the flip chip). However, MEMS packaging is a specially designed packaging process that is difficult owing to moving structural elements, and it is the most expensive process in micromachining. Unlike electronics IC packaging,44–56 MEMS packaging needs a cap. In order for the moving elements of a MEMS device to move effectively (e.g., with minimum damping and stiction) in a well-controlled atmosphere, hermetic sealing of the MEMS device in a cap is necessary. For some MEMS devices (e.g., resonators, infrared bolometers, and gyroscopes), vacuum packaging is even required. Usually, the cap is processed at the wafer level, and thus MEMS packaging is truly a waferlevel packaging. The design, materials, process, testing, and reliability of MEMS wafer-level packaging will be presented, discussed, and examined throughout this book.

1.6

MEMS Packaging Patents since 2001 In the past few years, many patents have been granted for MEMS packaging. In this section, some of the patents (since 2001) from the United States, Japan, and the world have been selected and listed for convenient practice.

1.6.1

U.S. MEMS Packaging Patents

Some of the U.S. MEMS packaging patents selected from the U.S. Patent and Trademark Office (USPTO) since 2001 are as follows: Patent No. 7,508,063

7,491,567

7,479,516

Owner(s)/Title/Date Duboc, Robert M. (Menlo Park, CA), Tarn, Terry (San Diego, CA), “Low cost hermetically sealed package,” March 24, 2009. D’Camp, Jon B. (Savage, MN), Curtis, Harlan L. (Champlin, MN), “MEMS device packaging methods,” February 17, 2009. Chen, Jian (Richardson, TX), Rajagopal, Ramasubramaniam (Richardson, TX), “Nanocomposites and methods thereto,” January 20, 2009.

Introduction to MEMS 7,465,600

7,463,404

7,456,497

7,452,800

7,449,784

7,449,358

7,449,356

7,443,563

7,436,054

7,425,749

Michael, Don (Monmoth, OR), Rossman, Mari J. (Corvallis, OR), Bower, Bradley (Junction City, OR), Haluzak, Charles Craig (Corvallis, OR), Stemer, John R. (Albany, OR), Qi, Quan (Corvallis, OR), Kane, John (Corvallis, OR), “Package for a micro-electro-mechanical device,” December 16, 2008. Chen, Dongmin (Saratoga, CA), Xiong, Fulin (San Jose, CA), “Method of using a preferentially deposited lubricant to prevent anti-stiction in micromechanical systems,” December 9, 2008. Higashi, Mitsutoshi (Nagano, JP), “Electronic devices and its production methods,” November 25, 2008. Sosnowchik, Brian D. (Walnut Creek, CA), Lin, Liwei (Castro Valley, CA), Pisano, Albert P. (Danville, CA), “Bonding a non-metal body to a metal surface using inductive heating,” November 18, 2008. Sherrer, David W. (Radford, VA), Rasnake, Larry J. (Blacksburg, VA), Fisher, John J. (Blacksburg, VA), “Device package and methods for the fabrication and testing thereof,” November 11, 2008. Patel, Satyadev R. (Sunnyvale, CA), Huibers, Andrew G. (Palo Alto, CA), Chiang, Steve S. (Saratoga, CA), “Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates,” November 11, 2008. Weigold, Jason W. (Somerville, MA), “Process of forming a microphone using support member,” November 11, 2008. Palmateer, Lauren (San Francisco, CA), Gally, Brian J. (Los Gatos, CA), Cummings, William J. (Millbrae, CA), Kothari, Manish (Cupertino, CA), Chui, Clarence (San Jose, CA), “Packaging for an interferometric modulator,” October 28, 2008. Zhe, Wang (Singapore, SG), “MEMS microphone with a stacked PCB package and method of producing the same,” October 14, 2008. Hartzell, John Walter (Camas, WA), Zhan, Changqing (Vancouver, WA), Wolfson, Michael Barrett (Somerville, MA), “MEMS pixel sensor,” September 16, 2008.

7

8

Chapter One 7,424,198

7,422,962

7,416,938

7,415,870

7,414,310

7,408,250

7,405,860

7,405,466

7,405,100

7,402,878

Palmateer, Lauren (San Francisco, CA), Cummings, William J. (San Francisco, CA), Gally, Brian (San Rafael, CA), Miles, Mark (San Francisco, CA), Sampsell, Jeffrey B. (San Jose, CA), Chui, Clarence (San Mateo, CA), Kothari, Manish (Cupertino, CA), “Method and device for packaging a substrate,” September 9, 2008. Chen, Chien-Hua (Corvallis, OR), Chen, Zhizhang (Corvallis, OR), Geissler, Steven R (Albany, OR), “Method of singulating electronic devices,” September 9, 2008. Seh, Huankiat (Phoenix, AZ), Min, Yongki (Phoenix, AZ), “Inkjet patterning for thin-film capacitor fabrication, thin-film capacitors fabricated thereby, and systems containing same,” August 26, 2008. Mancosu, Federico (Milan, IT), Brusarosco, Massimo (Cesano Boscone, IT), Fioravanti, Anna Paola (Monza, IT), Romeo, Fabio (Monza, IT), “Movable unit and system for sensing at least one characteristic parameter of a tyre,” August 26, 2008. Do, Byung Tai (Singapore, SG), Yang, Sung Uk (Singapore, SG), “Waferscale package system,” August 19, 2008. Doan, Jonathan (Mountain View, CA), Tarn, Terry (San Diego, CA), “Micromirror array device with compliant adhesive, August 5, 2008. Huibers, Andrew G. (Mountain View, CA), Patel, Satyadev R. (Elk Grove, CA), “Spatial light modulators with light blocking/absorbing areas,” July 29, 2008. Wei, Jun (Singapore, SG), Wong, Stephen Chee Khuen (Singapore, SG), Wu, Yongling (Singapore, SG), Ng, Fern Lan (Singapore, SG), “Method of fabricating microelectromechanical system structures,” July 29, 2008. Mostafazadeh, Shahram (San Jose, CA), Smith, Joseph O. (Morgan Hill, CA), “Packaging of a semiconductor device with a non-opaque cover,” July 29, 2008. Tarn, Terry (San Diego, CA), “Packaging method for microstructure and semiconductor devices,” July 22, 2008.

Introduction to MEMS 7,393,758

7,393,712

7,381,629

7,381,583

7,378,734

7,373,026

7,368,808

7,368,311

7,361,581

7,358,106

Sridhar, Uppili (Dallas, TX), Zou, Quanbo (Plano, TX), “Wafer level packaging process,” July 1, 2008. Smith, Mark A. (Corvallis, OR), Boucher, William R (Corvallis, OR), Haluzak, Charles C (Corvallis, OR), “Fluidic MEMS device,” July 1, 2008. Sankarapillai, Chirayarikathuveedu Premachandran (Singapore, SG), Nagarajan, Ranganathan (Singapore, SG), Soundarapandian, Mohanraj (Singapore, SG), “Method of forming through-wafer interconnects for vertical wafer level packaging,” June 3, 2008. Ebel, John L. (Beavercreek, OH), Cortez, Rebecca (Xenia, OH), Strawser, Richard E. (Greenville, OH), Leedy, Kevin D. (Centerville, OH), “MEMS RF switch integrated process,” June 3, 2008. Yabuki, Richard (Garden Grove, CA), Tea, Nim (Orange, CA), “Stacked contact bump,” May 27, 2008. Chui, Clarence (San Mateo, CA), “MEMS device fabricated on a pre-patterned substrate,” May 13, 2008. Heck, John (Palo Alto, CA), Hayden, III, Joseph S. (Sunnyvale, CA), Greathouse, Steve W. (Chandler, AZ), Wong, Daniel M. (Fremont, CA), “MEMS packaging using a non-silicon substrate for encapsulation and interconnection,” May 6, 2008. Tilmans, Hendrikus (Maastricht, NL), Beyne, Eric (Leuven, BE), Jansen, Henri (Leuven, BE), De Raedt, Walter (Edegem, BE), “Method and system for fabrication of integrated tunable/ switchable passive microwave and millimeter wave modules,” May 6, 2008. Adkisson, James W. (Jericho, VT), Gambino, Jeffrey P. (Westford, VT), Jaffe, Mark D. (Shelburne, VT), Rassel, Richard J. (Colchester, VT), Sprogis, Edmund J. (Underhill, VT), “High surface area aluminum bond pad for through-wafer connections to an electronic package,” April 22, 2008. Potter, Curtis Nathan (Austin, TX), “Hermetic MEMS package and method of manufacture,” April 15, 2008.

9

10

Chapter One 7,357,017

7,324,716

7,314,777

7,309,902

7,307,775

7,302,829

7,297,573

7,288,464

7,286,278

Felton, Lawrence E. (Hopkinton, MA), Harney, Kieran P. (Andover, MA), Roberts, Carl M. (Topsfield, MA), “Wafer level capped sensor,” April 15, 2008. Epitaux, Marc (Sunnyvale, CA), “Silicon packaging for opto-electronic modules,” January 29, 2008. D’Camp, Jon B. (Savage, MN), Curtis, Harlan L. (Champlin, MN), Dunaway, Lori A. (New Hope, MN), Glenn, Max C. (Chanhassen, MN), “Chip packaging systems and methods,” January 1, 2008. Reboa, Paul F. (Corvallis, OR), “Microelectronic device with anti-stiction coating,” December 18, 2007. Patel, Satayadev R. (Sunnyvale, CA), Huibers, Andrew G. (Palo Alto, CA), Chiang, Steve (Saratoga, CA), Duboc, Robert M. (Menlo Park, CA), Grobelny, Thomas J. (Snohomish, WA), Chen, Hung Nan (Kaohsiung, TW), Dehlinger, Dietrich (Sebastopol, CA), Richards, Peter W. (Palo Alto, CA), Shi, Hongqin (San Jose, CA), Sun, Anthony (San Jose, CA), “Methods for depositing, releasing and packaging microelectromechanical devices on wafer substrates,” December 11, 2007. Zribi, Anis (Rexford, NY), “Contactless humidity/chemical vapor sensor device and associated method of fabrication,” December 4, 2007. D’Camp, Jon B. (Savage, MN), Curtis, Harlan L. (Champlin, MN), Dunaway, Lori A. (New Hope, MN), Glenn, Max C. (Chanhassen, MN), “Methods and apparatus for particle reduction in MEMS devices,” November 20, 2007. Haluzak, Charles C. (Corvallis, OR), Pollard, Jeffrey R. (Corvallis, OR), “MEMS packaging structure and methods,” October 30, 2007. Patel, Satyadev R. (Sunnyvale, CA), Huibers, Andrew G. (Palo Alto, CA), Chiang, Steve S. (Saratoga, CA), “Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates,” October 23, 2007.

Introduction to MEMS 7,282,329

7,276,789

7,276,398

7,275,424

7,262,622 7,259,449

7,243,533

7,238,999

7,238,546

7,233,048

7,218,742

7,217,588

7,203,394

Manalis, Scott (Cambridge, MA), Burg, Thomas (Cambridge, MA), “Suspended microchannel detectors,” October 16, 2007. Cohn, Michael B. (Berkeley, CA), Kung, Joseph T. (Santa Clara, CA), “Microelectromechanical systems using thermocompression bonding,” October 2, 2007. Michael, Don (Monmoth, OR), Rossman, Mari J. (Corvallis, OR), “System and method for hermetically sealing a package,” October 2, 2007. Felton, Lawrence E. (Hopkinton, MA), Harncy, Kieran P. (Andover, MA), Roberts, Carl M. (Topsfield, MA), “Wafer level capped sensor,” October 2, 2007. Zhao, Yang (Andover, MA), “Wafer-level package for integrated circuits,” August 28, 2007. Floyd, Philip D. (Redwood City, CA), “Method and system for sealing a substrate,” August 21, 2007. Mancosu, Federico (Milan, IT), Romeo, Fabio (Monza, IT), Brusarosco, Massimo (Cesano Boscone, IT), Fioravanti, Anna Paolo (Monza, IT), “Movable unit and system for sensing at least one characteristic parameter of a tyre,” July 17, 2007. LaFond, Peter H. (Redmond, WA), Yu, Lianzhong (Redmond, WA), “High performance MEMS packaging architecture,” July 3, 2007. Stark, David H. (Evergreen, CO), “Hermetically sealed micro-device package with window,” July 3, 2007. Rybnicek, Kimon (Santa Barbara, CA), “MEMS device trench plating process and apparatus for through hole vias,” June 19, 2007. Kay, Kelly Q. (Chicago, IL), Gilbert, Mark W. (Park Ridge, IL), “Condenser microphone assembly,” May 15, 2007. Hartzell, John W. (Camas, WA), Walton, Harry Garth (Beckley, GB), Brownlow, Michael James (Drayton, GB), “Integrated MEMS packaging,” May 15, 2007. Wiegele, Thomas (Apple Valley, MN), Apanius, Christopher (Moreland Hills, OH), Goldman, Kenneth G. (Olmsted Township, OH), Guo,

11

12

Chapter One

7,202,553

7,202,552

7,198,982

7,183,176

7,176,106

7,166,488

7,164,199

7,160,637

7,153,759

Shuwen (Lakeville, MN), St. Clair, Loren E. (Apple Valley, MN), O’Meara, Timothy R. (Burnsville, MN), Pohl, James J. (Apple Valley, MN), “Micro mirror arrays and microstructures with solderable connection sites,” April 10, 2007. Snyder, Tanya Jegeris (Edina, MN), Yi, Robert H. (Palo Alto, CA), Wilson, Robert Edward (Palo Alto, CA), “Wafer bonding using reactive foils for massively parallel micro-electromechanical systems packaging,” April 10, 2007. Zhe, Wang (Singapore, SG), Yubo, Miao (Singapore, SG), “MEMS package using flexible substrates, and method thereof,” April 10, 2007. Patel, Satyadev R. (Sunnyvale, CA), Huibers, Andrew G. (Palo Alto, CA), Chiang, Steve S. (Saratoga, CA), “Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates,” April 3, 2007. Sankarapillai, Chirayarikathuveedu Premachandran (Singapore, SG), Nagarajan, Ranganathan (Singapore, SG), Soundarapandian, Mohanraj (Singapore, SG), “Method of forming through-wafer interconnects for vertical wafer level packaging,” April 3, 2007. Snyder, Tanya Jegeris (Edina, MN), Yi, Robert H. (Palo Alto, CA), Wilson, Robert Edward (Palo Alto, CA), “Wafer bonding using reactive foils for massively parallel micro-electromechanical systems packaging,” February 13, 2007. MacDonald, Noel C. (Santa Barbara, CA), Aimi, Marco F. (Goleta, CA), “Metal MEMS devices and methods of making same,” January 23, 2007. Tarn, Terry (San Diego, CA), “Device packages with low stress assembly process,” January 16, 2007. Chiao, Mu (Beaverton, OR), Lin, Liwei (Castro Valley, CA), Lam, Kien-Bang (Albany, CA), “Implantable, miniaturized microbial fuel cell,” January 9, 2007. Wei, Jun (Singapore, SG), Wong, Stephen Chee Khuen (Singapore, SG), Wu, Yongling (Singapore, SG), Ng, Fern Lan (Singapore, SG), “Method of fabricating microelectromechanical system structures,” December 26, 2006.

Introduction to MEMS 7,145,213

7,132,721

7,129,163

7,115,182

7,112,525

7,112,463

7,101,789

7,094,967

7,084,073

7,071,594

Ebel, John L. (Beavercreek, OH), Cortez, Rebecca (Xenia, OH), Strawser, Richard E. (Greenville, OH), Leedy, Kevin D. (Centerville, OH), “MEMS RF switch integrated process,” December 5, 2006. Platt, William P. (Columbia Heights, MN), Ford, Carol M. (Columbia Heights, MN), “Bonding for a micro-electro-mechanical system (MEMS) and MEMS based devices,” November 7, 2006. Sherrer, David W. (Radford, VA), Rasnake, Larry J. (Blacksburg, VA), Fisher, John J. (Blacksburg, VA), “Device package and method for the fabrication and testing thereof,” October 31, 2006. Wei, Jun (Singapore, SG), Wong, Stephen Chee Khuen (Singapore, SG), Nai, Sharon Mui Ling (Singapore, SG), “Anodic bonding process for ceramics,” October 3, 2006. Bhansali, Shekhar (Tampa, FL), Aravamudhan, Shyam (Tampa, FL), Luongo, Kevin (St. Petersburg, FL), Kedia, Sunny (Tampa, FL), “Method for the assembly of nanowire interconnects,” September 26, 2006. Horning, Robert (Savage, MN), Ohnstein, Thomas (Roseville, MN), Youngner, Daniel (Maple Grove, MN), “Method for making devices using ink jet printing,” September 26, 2006. Subramanian, Kanakasabapathi (Clifton Park, NY), Fortin, Jeffrey Bernard (Niskayuna, NY), Tian, Wei-Cheng (Clifton Park, NY), “Method of wet etching vias and articles formed thereby,” September 5, 2006. Evans, Cliff (Newtown, CT), Dalton, Mark William (Danbury, CT), “Electrical feedthru,” August 22, 2006. Lee, Moon-chul (Sungnam, KR), Choi, Hyung (Sungnam, KR), Jung, Kyu-dong (Suwon, KR), Jang, Mi (Suwon, KR), Hong, Seog-woo (Busan, KR), Chung, Seok-whan (Suwon, KR), Jun, Chan-bong (Seoul, KR), Kang, Seok-jin (Suwon, KR), “Method of forming a via hole through a glass wafer,” August 1, 2006. Yan, Jun (Cincinnati, OH), Casasanta, III, Vincenzo (Woodinville, WA), Luanava, Selso H. (Woodinville, WA), Urey, Hakan (Istanbul, TR),

13

14

Chapter One

7,030,432

7,029,829

7,011,793

7,008,193

7,004,015

7,002,436

7,002,241

7,002,215

6,995,040

DeWitt, IV, Frank A. (Bloomfield, NY), Tegreene, Clarence T. (Bellevue, WA), Wiklof, Christopher A. (Everett, WA), “MEMS scanner with dual magnetic and capacitive drive,” July 4, 2006. Ma, Qing (San Jose, CA), “Method of fabricating an integrated circuit that seals a MEMS device within a cavity,” April 18, 2006. Stark, Brian H. (Ann Arbor, MI), Najafi, Khalil (Ann Arbor, MI), “Low temperature method for forming a microcavity on a substrate and article having same,” April 18, 2006. Zhou, Peng (Newtown, PA), Young, Lincoln (Ithaca, NY), “Reconfigurable modular microfluidic system and method of fabrication,” March 14, 2006. Najafi, Khalil (Ann Arbor, MI), Kim, Hanseup S. (Ann Arbor, MI), Bernal, Luis P. (Ann Arbor, MI), Astle, Aaron A. (Ann Arbor, MI), Washabaugh, Peter D. (Ann Arbor, MI), “Micropump assembly for a microgas chromatograph and the like,” March 7, 2006. Chang-Chien, Patty P. L. (Hermosa Beach, CA), Wise, Kensall D. (Ann Arbor, MI), “Method and system for locally sealing a vacuum microcavity, methods and systems for monitoring and controlling pressure and method and system for trimming resonant frequency of a microstructure therein,” February 28, 2006. Ma, Qing (San Jose, CA), Cheng, Peng (Campbell, CA), Rao, Valluri (Saratoga, CA), “Vacuum-cavity MEMS resonator,” February 21, 2006. Mostafazadeh, Shahram (San Jose, CA), Smith, Joseph O. (Morgan Hill, CA), “Packaging of semiconductor device with a non-opaque cover,” February 21, 2006. Miller, David (Louisville, CO), “Floating entrance guard for preventing electrical short circuits,” February 21, 2006. Patel, Satyadev R. (Sunnyvale, CA), Huibers, Andrew G. (Palo Alto, CA), Chiang, Steve S. (Saratoga, CA), “Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates,” February 7, 2006.

Introduction to MEMS 6,995,034

6,987,304

6,987,258

6,984,866

6,982,491

6,972,955

6,969,635

6,965,721

6,962,834

6,958,846

Patel, Satyadev R. (Sunnyvale, CA), Huibers, Andrew G. (Palo Alto, CA), Chiang, Steve S. (Saratoga, CA), “Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates,” February 7, 2006. D’Camp, Jon B. (Savage, MN), Curtis, Harlan L. (Champlin, MN), Dunaway, Lori A. (New Hope, MN), Glenn, Max C. (Chanhassen, MN), “Methods and apparatus for particle reduction in MEMS devices,” January 17, 2006. Mates, John W. (Portland, OR), “Integrated circuit-based compound eye image sensor using a light pipe bundle,” January 17, 2006. Mostafazadeh, Shahram (San Jose, CA), Smith, Joseph O. (Morgan Hill, CA), Penry, Matthew D. (Morgan Hill, CA), “Flip chip optical semiconductor on a PCB,” January 10, 2006. Fan, Chun Ho (Sham Tseng, HK), Labeeb, Sadak Thamby (Tsuen Wan, HK), Chow, Lap Keung (Kowloon, HK), “Sensor semiconductor package and method of manufacturing the same,” January 3, 2006. Pleskach, Michael David (Orlando, FL), Koeneman, Paul Bryant (Palm Bay, FL), Smith, Brian Ronald (Pittsburgh, PA), Newton, Charles Michael (Palm Bay, FL), Gamlen, Carol Ann (Melbourne, FL), “Electro-fluidic device and interconnect and related methods,” December 6, 2005. Patel, Satyadev R. (Sunnyvale, CA), Huibers, Andrew G. (Palo Alto, CA), Chiang, Steven S. (Saratoga, CA), “Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates,” November 29, 2005. Tullis, Barclay J. (Palo Alto, CA), Prince, John H. (Los Altos, CA), “Integrated manufacture of sidepolished fiber optics,” November 15, 2005. Stark, David H. (Evergreen, CO), “Wafer-level hermetic micro-device packages,” November 8, 2005. Huibers, Andrew G. (Mountain View, CA), Richards, Peter W. (Palo Alto, CA), “Spatial light modulators with light absorbing areas,” October 25, 2005.

15

16

Chapter One 6,956,283

6,953,985

6,952,301

6,949,398

6,936,918

6,936,494

6,924,974

6,917,099

6,906,847

6,902,656

Peterson, Kenneth A. (Albuquerque, NM), “Encapsulants for protecting MEMS devices during post-packaging release etch,” October 18, 2005. Lin, Jong-Kai (Chandler, AZ), Lytle, William H. (Chandler, AZ), Fay, Owen (Gilbert, AZ), Markgraf, Steven (Chandler, AZ), Hughes, Henry G. (Scottsdale, AZ), Amrine, Craig (Tempe, AZ), De Silva, Ananda P. (Chandler, AZ), “Wafer level MEMS packaging,” October 11, 2005. Huibers, Andrew G. (Palo Alto, CA), “Spatial light modulators with light blocking and absorbing areas,” October 4, 2005. Lytle, William H. (Chandler, AZ), Fay, Owen (Gilbert, AZ), Markgraf, Steven (Plymouth, MN), Springer, Stephen B. (Mesa, AZ), “Low cost fabrication and assembly of lid for semiconductor devices,” September 27, 2005. Harney, Kieran P. (Andover, MA), Felton, Lawrence E. (Hopkinton, MA), Nunan, Thomas Kieran (Carlisle, MA), Alie, Susan A. (Stoneham, MA), Wachtmann, Bruce (Concord, MA), “MEMS device with conductive path through substrate,” August 30, 2005. Cheung, Kin P. (Hoboken, NJ), “Processes for hermetically packaging wafer level microscopic structures,” August 30, 2005. Stark, David H. (Evergreen, CO), “Hermetically sealed micro-device package using cold-gas dynamic spray material deposition,” August 2, 2005. Hellekson, Ronald A. (Eugene, OR), Chen, Chien-Hua (Corvallis, OR), Boucher, William R (Corvallis, OR), Smith, Joshua W. (Corvallis, OR), Craig, David M (Albany, OR), Watts, Gary J. (Albany, OR), “Die carrier with fluid chamber,” July 12, 2005. Huibers, Andrew G. (Mountain View, CA), Patel, Satyadev R. (Elk Grove, CA), “Spatial light modulators with light blocking/absorbing areas,” June 14, 2005. Ouellet, Luc (Granby, CA), Antaki, Robert (St-Luc, CA), Tremblay, Yves (Brigham, CA), “Fabrication of microstructures with vacuumsealed cavity,” June 7, 2005.

Introduction to MEMS 6,900,072

6,894,383

6,876,056

6,858,466

6,853,067

6,846,725

6,844,959

6,844,623

6,838,047

6,835,594

Patel, Satyadev R. (Elk Grove, CA), Huibers, Andrew G. (Mountain View, CA), “Method for making a micromechanical device by using a sacrificial substrate,” May 31, 2005. Bar-Sadeh, Eyal (Jerusalem, IL), Talalyevsky, Alexander (Jerusalem, IL), Ginsburg, Eyal (Tel Aviv, IL), “Reduced substrate micro-electromechanical systems (MEMS) device and system for producing the same,” May 17, 2005. Tilmans, Hendrikus (Maastricht, NL), Beyne, Eric (Leuven, BE), Jansen, Henri (Leuven, BE), De Raedt, Walter (Edegem, BE), “Method and system for fabrication of integrated tunable/ switchable passive microwave and millimeter wave modules,” April 5, 2005. Bower, Bradley (Junction City, OR), Qi, Quan (Corvallis, OR), Sand, Kirby (Corvallis, OR), “System and a method for fluid filling wafer level packages,” February 22, 2005. Cohn, Michael B. (Berkeley, CA), Kung, Joseph T. (Santa Clara, CA), “Microelectromechanical systems using thermocompression bonding,” February 8, 2005. Nagarajan, Ranganathan (Singapore, SG), Premachandran, Chirayarikathuveedu Sankarapillai (Singapore, SG), Chen, Yu (Singapore, SG), Kripesh, Vaidyanathan (Singapore, SG), “Wafer-level package for microelectro-mechanical systems,” January 25, 2005. Huibers, Andrew G. (Mountain View, CA), Patel, Satyadev R. (Elk Grove, CA), Duboc, Jr., Robert M. (Menlo Park, CA), “Spatial light modulators with light absorbing areas,” January 18, 2005. Peterson, Kenneth A. (Albuquerque, NM), Conley, William R. (Tijeras, NM), “Temporary coatings for protection of microelectronic devices during packaging,” January 18, 2005. Billiet, Romain Louis (Penang, MY), Nguyen, Hanh Thi (Penang, MY), “MEMS and MEMS components from silicon kerf,” January 4, 2005. Shong, Ci-moo (Sungnam-si, KR), Kang, Seok-jin (Suwon-si, KR), Chung, Seok-whan (Suwon-si, KR), Lee, Moon-chul (Sungnam-si, KR), Jung, Kyu-dong (Suwon-si, KR), Kim, Jong-seok (Gyeonggi-do, KR), Jun, Chan-bong (Seoul, KR),

17

18

Chapter One

6,834,154

6,825,744

6,809,412

6,808,955

6,808,954

6,798,954

6,793,829

6,788,840

6,780,672

6,775,068

6,773,962

Hong, Seog-woo (Busan, KR), Kang, Jung-ho (Suwon-si, KR), “Metal wiring method for an undercut,” December 28, 2004. Carpenter, Barry S. (Oakdale, MN), “Tooling fixture for packaged optical micro-mechanical devices,” December 21, 2004. Harney, Kieran Patrick (Andover, MA), “Active alignment as an integral part of optical package design,” November 30, 2004. Tourino, Cory G. (Georgetown, TX), Rice, Janet L. (Austin, TX), Flynn, Gregory (Austin, TX), “Packaging of MEMS devices using a thermoplastic,” October 26, 2004. Ma, Qing (San Jose, CA), “Method of fabricating an integrated circuit that seals a MEMS device within a cavity,” October 26, 2004. Ma, Qing (San Jose, CA), Cheng, Peng (Campbell, CA), Rao, Valluri (Saratoga, CA), “Vacuum-cavity MEMS resonator,” October 26, 2004. Carpenter, Barry S. (Oakdale, MN), Hagen, Kathy L. (Stillwater, MN), Smith, Robert G. (Vadnais Heights, MN), “Packaged optical micro-mechanical device,” September 28, 2004. Platt, William P. (Columbia Heights, MN), Ford, Carol M. (Columbia Heights, MN), “Bonding for a micro-electro-mechanical system (MEMS) and MEMS based devices,” September 21, 2004. Stewart, Robert E. (Woodland Hills, CA), Cherbettchian, Agop H. (Santa Monica, CA), Fersht, Samuel (Studio City, CA), Hall, David B. (La Crescenta, CA), “Bi-stable micro-actuator and optical switch,” September 7, 2004. Steele, Daniel W. (Clay, NY), Chovan, Joseph L. (North Syracuse, NY), “Micro eletro-mechanical component and system architecture,” August 24, 2004. Lomas, Stuart John (Edmonton, CA), McLaughlin, Dean Edward (Baltimore, MD), “Integrated optical channel,” August 10, 2004. Saia, Richard Joseph (Niskayuna, NY), Durocher, Kevin Matthew (Waterford, NY), Kapusta, Christopher James (Duanesburg, NY),

Introduction to MEMS

6,771,859

6,767,764

6,760,500 6,759,590

6,723,379

6,716,767

6,696,645

6,696,343

6,661,069

Nielsen, Matthew Christian (Schenectady, NY), “Microelectromechanical system device packaging method,” August 10, 2004. Carpenter, Barry S. (Oakdale, MN), “Selfaligning optical micro-mechanical device package,” August 3, 2004. Saia, Richard Joseph (Niskayuna, NY), Durocher, Kevin Matthew (Waterford, NY), Kapusta, Christopher James (Duanesburg, NY), Nielsen, Matthew Christian (Schenectady, NY), “Microelectromechanical system device packaging method,” July 27, 2004. Furuyama, Hideto (Kanagawa-ken, JP), “Optical wiring device,” July 6, 2004. Stark, David H. (Evergreen, CO), “Hermetically sealed micro-device package with window,” July 6, 2004. Stark, David H. (Evergreen, CO), “Hermetically sealed micro-device package using cold-gas dynamic spray material deposition,” April 20, 2004. Shih, Wu-Sheng (Rolla, MO), Lamb, III, James E. (Rolla, MO), Daffron, Mark (Rolla, MO), “Contact planarization materials that generate no volatile byproducts or residue during curing,” April 6, 2004. Margomenos, Alexandros (Ann Arbor, MI), Herrick, Katherine J. (Westford, MA), Becker, James P. (Bozeman, MT), Katehi, Linda P. B. (Northville, MI), “On-wafer packaging for RFMEMS,” February 24, 2004. Chinthakindi, Anil K. (Fishkill, NY), Groves, Robert A. (Highland, NY), Stein, Kenneth J. (Sandy Hook, CT), Subbanna, Seshadri (Brewster, NY), Volant, Richard P. (New Fairfield, CT), “Microelectromechanical varactor with enhanced tuning range,” February 24, 2004. Chinthakindi, Anil K. (Poughkeepsie, NY), Groves, Robert A. (Highland, NY), Stein, Kenneth J. (Sandy Hook, CT), Subbanna, Seshadri (Brewster, NY), Volant, Richard P. (New Fairfield, CT), “Micro-electromechanical varactor with enhanced tuning range,” December 9, 2003.

19

20

Chapter One 6,643,065

6,639,313

6,635,509 6,627,814

6,624,003

6,580,858

6,535,685

6,516,131

6,516,104 6,481,570

6,455,878

6,400,009

6,379,988

Silberman, Donn Michael (Aliso Viejo, CA), “Variable spacing diffraction grating,” November 4, 2003. Martin, John R. (Foxborough, MA), Harney, Kieran H. (Andover, MA), “Hermetic seals for large optical packages and the like,” October 28, 2003. Ouellet, Luc (Granby, CA), “Wafer-level MEMS packaging,” October 21, 2003. Stark, David H. (Evergreen, CO), “Hermetically sealed micro-device package with window,” September 30, 2003. Rice, Janet L. (Round Rock, TX), “Integrated MEMS device and package,” September 23, 2003. Chen, Jingkuang (Rochester, NY), Kubby, Joel A. (Rochester, NY), Sun, Decai (Los Altos, CA), “Micro-opto-electro-mechanical system (MOEMS),” June 17, 2003. Tullis, Barclay J. (Palo Alto, CA), “Arcuate fiber routing using stepped grooves,” March 18, 2003. Tullis, Barclay J. (Palo Alto, CA), “Structures and methods for aligning fibers,” February 4, 2003. Furuyama, Hideto (Kanagawa-ken, JP), “Optical wiring device,” February 4, 2003. Henshall, Gordon D (Harlow, GB), Rolt, Stephen (Herts, GB), “Packaging atmosphere and method of packaging a MEMS device,” November 19, 2002. Bhat, Jerome Chandra (San Francisco, CA), Ludowise, Michael Joseph (San Jose, CA), Steigerwald, Daniel Alexander (Cupertino, CA), “Semiconductor LED flip-chip having low refractive index underfill,” September 24, 2002. Bishop, David John (Summit, NJ), Gates, II, John VanAtta (New Providence, NJ), Kim, Jungsang (Basking Ridge, NJ), “Hermatic firewall for MEMS packaging in flip-chip bonded geometry,” June 4, 2002. Peterson, Kenneth A. (Albuquerque, NM), Conley, William R. (Tijeras, NM), “Pre-release plastic packaging of MEMS and IMEMS devices,” April 30, 2002.

Introduction to MEMS 6,335,224

6,297,072

1.6.2

Peterson, Kenneth A. (Albuquerque, NM), Conley, William R. (Tijeras, NM), “Protection of microelectronic devices during packaging,” January 1, 2002. Tilmans, Hendrikus A. C. (Maastricht, NL), Beyne, Eric (Leuven, BE), Van de Peer, Myriam (Brussel, BE), “Method of fabrication of a microstructure having an internal cavity,” October 2, 2001.

Japanese MEMS Packaging Patents

Some of the Japanese MEMS packaging patents selected from the Japan Patent Office (JPO) since 2001 are as follows: Patent No. 2008-298950 2008-244442

2008-229823 2008-221450

2008-211124 2008-209616

2008-198607

2008-193544

2008-185723 2008-185621

Owner(s)/Title/Date Yokoi, Junichi, “Optical scanning apparatus,” 11.12.2008. Seppala, Bryan R., Curtis, Harlan L., DCamp, Jon B., Spielberger, Richard K., “System and method for sealing MEMS device,” 09.10.2008. Aoki, Toshihiko, “Manufacturing method of MEMS device,” 02.10.2008. Fujii, Yoshio, Ogawa, Shinpei, Yokoyama, Yoshinori, Endo, Kazuyo, “MEMS package and manufacturing method therefor,” 25.09.2008. Chino, Mitsuru, “Semiconductor device storing package,” 11.09.2008. Kato, Seiichi, Nanjo, Takeshi, Otaka, Koichi, “Optical deflector and method of manufacturing the same,” 11.09.2008. Arthur, Stephen D., Elasser, Ahmed, Wright, Joshua Isaac, Subramanian, Kanakasabapathi, Keimel, Christopher Fred, Gowda, Arun Virupaksha, “Power overlay structure for MEM device, and method for producing power overlay structure for MEM device,” 28.08.2008. Aoki, Nobuhisa, Takano, Takeshi, Miyashita, Takumi, “Amplifier which takes internal matching according to signal characteristic,” 21.08.2008. Yokoi, Junichi, Sakai, Toshio, “Optical scanner,” 14.08.2008. Fujino, Hitoshi, Sakai, Toshio, “Optical deflector,” 14.08.2008.

21

22

Chapter One 2008-182103 2008-132587

2008-105162 2008-091334

2008-047955

2007-331099

2007-331098

2007-281292 2007-245339

2007-221105 2007-218902 2007-214440 2007-214439 2007-203451 2007-155714 2007-144617 2007-136668

Hatakeyama, Tomoyuki, “Airtight seal package,” 07.08.2008. Eskridge, Mark H., Jafri, Ijaz H., “Method of manufacturing wafer-level vacuum packaged device,” 12.06.2008. Hata, Shohei, Sakamoto, Eiji, Matsushima, Naoki, “Functional element,” 08.05.2008. Manuel, Carmona Flores, Kihara, Tatsuji, Jaume, Esteve Tinto, “MEMS package, and manufacturing method therefore, as well as integrated circuit including MEMS package,” 17.04.2008. Tenmyo, Hiroyuki, Isada, Naoya, Matsumoto, Kunio, Watanabe, Kazushi, Nagashima, Shiro, “Packaging structure having three-dimensional wiring,” 28.02.2008. Pyo, Sung-gyu, Kim, Dong-joon, “Package for MEMS element, and method for manufacturing the same,” 27.12.2007. Kim, Dong-joon, Pyo, Sung-gyu, “Package of MEMS device and method for manufacturing the same,” 27.12.2007. Ohara, Satoshi, “Semiconductor device mounting structure,” 25.10.2007. Robert, Philippe, “Microelectronic composite, especially packaging structure in sealing cavity of MEMS,” 27.09.2007. Eskridge, Mark H., “Sealing of MEMS device using liquid crystal polymer,” 30.08.2007. Eskridge, Mark H., “Discrete stress isolator,” 30.08.2007. Kuramochi, Satoru, Fukuoka, Yoshitaka, “Electronic device,” 23.08.2007. Satoru, Kuramochi and Yoshitaka, Fukuoka, “Composite sensor package,” 23.08.2007. MacGugan, Douglas C., “Integrated MEMS package,” 16.08.2007. MacGugan, Douglas C., “Compact package for moving sensor sensing axis,” 21.06.2007. D’Camp, Jon B., Curtis, Harlan L., “MEMS device packaging method,” 14.06.2007. D’Camp, Jon B., Curtis, Harlan L., “MEMS flipchip packaging,” 07.06.2007.

Introduction to MEMS 2007-132687 2007-124500

2007-108753

2007-088189

2007-082233 2007-060661

2007-042786 2007-017199

2006-321016 2006-286794 2006-270045

2006-247833

2006-202909

Taniguchi, Hajime, “Package for sensor, and detector using the same,” 31.05.2007. Yoshida, Koichi, Yamada, Toru, Kojima, Hideki, Makihata, Katsuhiro, “Acoustic sensor and method for manufacturing acoustic sensor,” 17.05.2007. Park, Heung-woo, Lee, Yeong-gyu, Boku, Shoshu, Lim, Ohk-kun, Park, Dong-hyun, “MEMS package and optical modulator module package,” 26.04.2007. Tenmyo, Hiroyuki, Isada, Naoya, Isobe, Atsushi, Terano, Akihisa, Matsumoto, Kunio, Ite, Mayumi, “MEMS (micro electronic mechanical system) package and its manufacturing method,” 05.04.2007. So, Seitan, “Silicon capacitor microphone and method for packaging same,” 29.03.2007. So, Seitan, “Silicon based condenser microphone and packaging method for the same,” 08.03.2007. Oya, Yoichi, “Micro device and its packaging method,” 15.02.2007. Tokushige, Nobuaki, Naka, Toshio, “Chip scale package and its manufacturing method,” 25.01.2007. Yoshikawa, Yasuhiro, Tajiri, Hiroyuki, “MEMS package,” 30.11.2006. Takahashi, Norio, “Semiconductor chip package and its manufacturing method,” 19.10.2006. Lim, Chang Hyun, Hwang, Woong Lin, Choi, Seog Moon, Park, Ho Joon, Lee, Sung Jun, Choi, Sang Hyun, “Light emitting diode package having electrostatic discharge protection functionality,” 05.10.2006. Kim, Jong-seok, Kim, Duck-hwan, Nam, Kuang-woo, Park, Yun-kwon, Yun, Seok-chul, Choa, Sung-hoon, So, Inso, “MEMS element package and its manufacturing method,” 21.09.2006. Ikeuchi, Naoki, Hashimoto, Hiroyuki, “Semiconductor device having minute structure and method of manufacturing minute structure,” 03.08.2006.

23

24

Chapter One 2006-190804

2006-186376

2006-186362

2006-173599

2006-173598

2006-147995

2006-123160

2006-121052

2006-121043

2006-119603

2006-099107

2006-099096

Kodate, Junichi, Machida, Katsuyuki, Urano, Masami, “Semiconductor device and its manufacturing method,” 20.07.2006. Kim, Jong-seok, Park, Yun-kwon, So, Inso, Kim, Duck-hwan, Nam, Kuang-woo, Yun, Seok-chul, “MEMS element and its manufacturing method,” 13.07.2006. Kim, Jong-seok, Park, Yun-kwon, So, Inso, Nam, Kuang-woo, Yun, Seok-chul, “MEMS element package and its manufacturing method,” 13.07.2006. Fazzio, Ronald S., Dungan, Thomas E., “Integrated wafer package of micro electrical machine and active device circuit,” 29.06.2006. Dungan, Thomas E., Fazzio, Ronald S., “Single integrated wafer package and assembling method of wafer package,” 29.06.2006. Kodate, Junichi, Machida, Katsuyuki, Urano, Masami, Kuwabara, Hiroshi, Terada, Jun, “Variable capacitance element and manufacturing method thereof,” 08.06.2006. Palmateer, Lauren, Gally, Brian J., Cummings, William J., “Method and device for providing MEMS device package having secondary seal,” 18.05.2006. Palmateer, Lauren, Cummings, William J., Gally, Brian J., Chui, Clarence, Kothari, Manish, “Method and system for packaging MEMS device together with incorporated getter,” 11.05.2006. Palmateer, Lauren, Cummings, William J., Gally, Brian J., Sampsell, Jeffrey B., “System and method for display provided with activated desiccant,” 11.05.2006. Gally, Brian J., Palmateer, Lauren, Cummings, William J., “System and method for protecting microelectromechanical system using backplate with non-flat portion,” 11.05.2006. Palmateer, Lauren, “System and method for display device with end-of-life phenomenon,” 13.04.2006. Floyd, Philip D., Arbuckle, Brian W., “Device having patterned spacer for backplate and method of making the same,” 13.04.2006.

Introduction to MEMS 2006-091849

2006-003277

2005-332957 2005-329532

2005-276816

2005-250307 2005-166909 2005-109221

2005-040940

2005-034987 2005-019966

2005-018015

2004-322157

2004-235465 2004-160654

Miles, Mark W., Sampsell, Jeffrey B., Palmateer, Lauren, Arbuckle, Brian W., Floyd, Philip D., “Method and system to package MEMS device,” 06.04.2006. Kanno, Yoshinori, “Semiconductor acceleration sensor system and its manufacturing method,” 05.01.2006. Okamoto, Kazuhisa, “Package manufacturing method,” 02.12.2005. Hong, Suk-kee, Lee, Yeong-gyu, Park, Heungwoo, “MEMS package having side seal member and its manufacturing method,” 02.12.2005. Tsui, Kenneth, Geisberger, Aaron, Skidmore, George, “Micro connector and non-powered microassembly with micro connector,” 06.10.2005. Hara, Koichi, “Optical deflector,” 15.09.2005. Yamamoto, Satoshi, Suemasu, Tatsuo, “Package and its manufacturing method,” 23.06.2005. Kawakubo, Takashi, Yasumoto, Yasuaki, Itaya, Kazuhiko, “Wafer-level package and its manufacturing method,” 21.04.2005. Snyder, Tanya Jegeris, Yi, Robert H., Wilson, Robert Edward, “Wafer bonding method using reactive foils for massively parallel micro-electromechanical systems packaging,” 17.02.2005. Smith, Mark A., Boucher, William R., Haluzak, Charles C., “Fluidic MEMS device,” 10.02.2005. Ikeda, Osamu, Okoda, Toshiyuki, “Semiconductor device and method of manufacturing the same,” 20.01.2005. Lee, Hyun Kee, Jung, Sung Cheon, Hong, Yoon Shik, “Optical switch and manufacturing method thereof,” 20.01.2005. Hino, Atsushi, Matsumura, Takeshi, “Working method for work and tacky adhesive sheet used for the same,” 18.11.2004. Yuasa, Mitsuhiro, “Bonding method, bonding device and sealant,” 19.08.2004. Lee, Eun-sung, Koh, Byeong-cheon, Moon, Chang-youl, Chun, Kuk Jin, “Side-bonding method for flip chip system in semiconductor device, MEMS device package and package method using the same,” 10.06.2004.

25

26

Chapter One 2004-160649

2004-158665

2004-136435

2003-347357 2003-297876

2003-243550

2003-075741

2002-246489

2002-236266

2002-043463

2002-043449

2001-196484

2001-185635

Lee, Moon-chul, Jun, Chan-bong, Choi, Hyung, Jung, Kyu-dong, Jang, Mi, Hong, Seog-woo, Kang, Seok-jin, Chung, Seok-whan, “Forming method of via hole of glass wafer,” 10.06.2004. Usami, Akira, Ohashi, Hidemasa, Nishino, Tamotsu, Owada, Satoru, Maeda, Chisako, Yoshida, Yukihisa, “Substrate for package and its manufacturing method,” 03.06.2004. Song, Ci-moo, Kang, Seok-jin, Chung, Seokwhan, Lee, Moon-chul, Jung, Kyu-dong, Kim, Jong-seok, Jun, Chan-bong, Hong, Seog-woo, Kang, Jung-ho, “Method of metal wiring for undercut,” 13.05.2004. Kawaguchi, Hitoshi, “Manufacturing method of semiconductor package,” 05.12.2003. Kawaguchi, Hitoshi, Takahashi, Toyomasa, “Manufacturing method for semiconductor package,” 17.10.2003. Kim, Woon-bae, Shin, Keisai, Cho, Soko, Kang, Seung-goo, “Hermetic sealing method for oxidation prevention at low temperature,” 29.08.2003. Boie, Robert Albert, Kim, Yunsang, Soh, Hyongsok, “Constitution of MEMS driver circuit,” 12.03.2003. Cho, Chang-ho, Shin, Hyung-jae, Kim, Woonbae, “Wafer level hermetic sealing method,” 30.08.2002. Jin, Sungho, Soh, Hyongsok, “Magnetically packaged optical MEMS device and method for making the same,” 23.08.2002. Kang, Seok-jin, “Surface mounting type chip scale packaging method of electronic and MEMS element,” 08.02.2002. Degani, Yinon, Dudderar, Thomas D., Tai, King L., “Micro mechanical packaging apparatus,” 08.02.2002. Ha, Byeoung Ju, Baek, Seog-soon, Kim, Hyunchul, Song, Hoon, Oh, Yong-soo, “Manufacturing method of MEMS structure enabling wafer level vacuum packaging,” 19.07.2001. Bishop, David John, Gates, John Vanatta, Kim, Jungsang, “Package having cavity for housing MEMS,” 06.07.2001.

Introduction to MEMS 2001-144117

Oakatto, John W., Downa, Andrew Steven, Rin, Tsuen Fwan, “Improved MEMS wafer-level package,” 25.05.2001.

1.6.3 Worldwide MEMS Packaging Patents Some of the MEMS packaging patents selected from European Patent Office (EPO) since 2002 are as follows: Title/Owner(s)/Patent No./Date 1. “Wafer level chip size package for MEMS devices and method for fabricating the same,” Wang, Zhiqi (CN), Yu, Guoqing (CN) (+2), US2009057868 (A1)—2009-03-05. 2. “Method for packaging an optical MEMS device,” Khonsari, Nassim (US), Chui, Clarence (US), EP2029473 (A2)—200903-04. 3. “Patterned contact sheet to protect critical surfaces in manufacturing processes,” Ya, Michael Wang Qing (US), Zhang, Junhong (US), CN101323428 (A)—2008-12-17. 4. “Vertically integrated 3-axis MEMS accelerometer with electronics,” Nasiri, Steven S. (US), Seeger, Joseph (US) (+1), US2008314147 (A1)—2008-12-25. 5. “Mirror and mirror layer for optical modulator and method,” Chui, Clarence (US), Sampsell, Jeffrey B. (US), US2008314866 (A1)—2008-12-25. 6. “System and method of fabricating micro cavities,” Wan, Chang-Feng (US), US2008308920 (A1)—2008-12-18. 7. “Electronic device comprising a MEMS element,” Dekker, Ronald (NL), Polhmann, Hauke (NL) (+1), CN101309854 (A)—2008-11-19. 8. “Apparatus for downhole fluids analysis utilizing micro electro mechanical systems (MEMS) or other sensors,” Terabayashi, Toru (VG), Sugimoto, Tsutomu (VG) (+3), CN101309853 (A)— 2008-11-19. 9. “MEMS device vacuum encapsulation method,” Jin, Yufeng (CN), Zhang, Yangfei (CN) (+2), CN101301993 (A)—2008-11-12. 10. “Packaging body and packaging component for microphone of micro electro-mechanical systems,” Huang, Zhaoda (CN), Jian, Xintang (CN), CN101316462 (A)—2008-12-03. 11. “Packaging body and packaging component for microphone of micro electro-mechanical systems,” Huang, Zhaoda (CN), Jian, Xintang (CN), CN101316461 (A)—2008-12-03. 12. “Packaging of Mems devices,” Johnson, Donald W. (US), Nagale, Milind P. (US), EP1997128 (A2)—2008-12-03.

27

28

Chapter One 13. “Silicon microphone with improved structure,” Wang, Xianbin (CN), Dang, Maoqiang (CN) (+2), CN201138866 (Y)—2008-10-22. 14. “Package and packaging assembly of microelectromechanical sysyem microphone,” Huang, Chao-Ta (TW), Chien, Hsin-Tang (TW), US2008283988 (A1)—2008-11-20. 15. “Package and packaging assembly of microelectromechanical sysyem microphone,” Huang, Chao-Ta (TW), Chien, Hsin-Tang (TW), US2008283942 (A1)—2008-11-20. 16. “Capacitance type micro-accelerometer,” Liu, Minjie (CN), Liu, Yunfeng (CN) (+2), CN101271125 (A)—2008-09-24. 17. “Silicon piezoresistance type pressure transducer encapsulation structure based on substrates,” Wang, Yuelin (CN), Wu, Yanhong (CN) (+2), CN101271029 (A)—2008-09-24. 18. “MEMS device support structure for sensor packaging,” Ahmad, Nazir (US), US2008277747 (A1)—2008-11-13. 19. “MEMS device with integral packaging,” Cohn, Michael B. (US), Xu, Ji-Hai (US), US2008272867 (A1)—2008-11-06. 20. “Packaged MEMS device assembly,” Haluzak, Charles C. (US), Pollard, Jeffrey R. (US) (+5), US2008272446 (A1)—2008-11-06. 21. “MEMS device airtightness packaging method,” Chen, Jing (CN), Wu, Yexian (CN) (+1), CN101234745 (A)—2008-08-06. 22. “Orientation-dependent etching of deposited AIN for structural use and sacrificial layers in MEMS,” Bouche, Guillaume (US), Wall, Ralph N. (US), US2008268575 (A1)—2008-10-30. 23. “Packaging a MEMS device using a frame,” Natarajan, Bangalore R. (US), EP1979268 (A2)—2008-10-15. 24. “Microelectromechanical systems, and methods for encapsualting and fabricating same,” Partridge, Aaron (US), Lutz, Markus (US) (+1), US2008237756 (A1)—2008-10-02. 25. “Functional device,” Hata, Shohei (JP), Sakamoto, Eiji (JP) (+1), US2008233349 (A1)—2008-09-25. 26. “Power overlay structure for MEM device, and method for producing power overlay structure for MEM device,” Arthur, Stephen D., Elasser, Ahmed (+4), JP2008198607 (A)—200808-28. 27. “MEMS fiber optic microphone,” Chin, Ken K. (US), Feng, Guanhua (US) (+1), WO2008100266 (A2)—2008-08-21. 28. “Apparatus for driving micromechanical devices,” Miles, Mark W. (US), US2008191978 (A1)—2008-08-14.

Introduction to MEMS 29. “Method for manufacturing a semiconductor package structure having micro-electro-mechanical systems,” Wang, MengJen (TW), Yang, Hsueh-An (TW), US2008188026 (A1)—200808-07. 30. “Package and method for making the same,” Wang, MengJen (TW), US2008185706 (A1)—2008-08-07. 31. “Methods and systems for wafer level packaging of MEMS structures,” Yang, Xiao (US), Payne, Justin (US) (+3), WO2008085779 (A1)—2008-07-17. 32. “Design of MEMS packaging,” Kvisteroy, Terje (NO), Westby, Eskild (NO), US2008164546 (A1)—2008-07-10. 33. “Packaging structure and method of a MEMS microphone,” Hsiao, Wei-Min (TW), US2008166000 (A1)—2008-07-10. 34. “MEMS packaging with reduced mechanical strain,” Kvisteroy, Terje (NO), Westby, Eskild (NO), EP1944266 (A1)—2008-07-16. 35. “Packaging of Micro Devices,” O’Mahony, Conor (IE), Hill, Martin (IE), US2008145976 (A1)—2008-06-19. 36. “High-aspect-ratio metal-polymer composite structures for nano interconnects,” Aggarwal, Ankur (US), Raj, Pulugurtha Markondeya (US) (+1), US2008136035 (A1)—2008-06-12. 37. “MEMS package and packaging method thereof,” Jung, Sung-Hae (KR), Lee, Myung-Lae (KR) (+4), WO2008069394 (A1)—2008-06-12. 38. “Integrated thermal systems,” Henderson, H. Thurman (US), Shuja, Ahmed (US) (+3), US2008128898 (A1)—2008-06-05. 39. “Microelectromechanical devices and fabrication methods,” Metz, Matthias (US), Pan, Zhiyu (CN) (+3), WO2008067097 (A2)—2008-06-05. 40. “Hermetically sealed wafer level packaging for optical MEMS devices,” Yang, Xiao (US), CN101183675 (A)—2008-05-21. 41. “Polymer object optical fabrication process,” Cregger, Robert Brian (US), WO2008063433 (A2)—2008-05-29. 42. “X-Y axis dual-mass tuning fork gyroscope with vertically integrated electronics and wafer-scale hermetic packaging,” Seeger, Joseph (US), Nasiri, Steven S. (US) (+1), US2008115579 (A1)—2008-05-22. 43. “MEMS package, and manufacturing method therefore, as well as integrated circuit including MEMS package,” Manuel, Carmona Flores, Kihara, Tatsuji (+1), JP2008091334 (A)— 2008-04-17.

29

30

Chapter One 44. “Microelectronic flow sensor packaging method and system,” Ricks, Lamar F. (US), WO2008057911 (A2)—2008-05-15. 45. “Hermetically sealed wafer level packaging for optical MEMS devices,” Yang, Xiao (US), GB2443352 (A)—2008-04-30. 46. “Methods for depositing, releasing and packaging microelectromechanical devices on wafer substrates,” Patel, Satayadev R. (US), Huibers, Andrew G. (US) (+8), US2008096313 (A1)—2008-04-24. 47. “Package structure and packaging method of MEMS microphone,” Chen, Jung-Tai (TW), Chu, Chun-Hsun (TW), US2008083960 (A1)—2008-04-10. 48. “Laser assisted system and method for bonding of surfaces,” Wang, Changhai (GB), Hand, Duncan (GB) (+1), EP1907160 (A1)—2008-04-09. 49. “Method for preparing spherical glass micro-cavity used for MEMS disc type packaging,” Shang, Jintang (CN), Huang, Qingan (CN) (+2), CN101143702 (A)—2008-03-19. 50. “Chip packaging systems and methods,” D’Camp, Jon B. (US), Curtis, Harlan L. (US) (+2), US2008063505 (A1)—2008-03-13. 51. “Micro electro-mechanical system module package,” Yen, Tzu-Yin (TW), Yeh, Cung-Mao (TW), US2008061409 (A1)— 2008-03-13. 52. “Integrated MEMS packaging,” Lu, Jun (CA), Menard, Stephane (CA), WO2008034233 (A1)—2008-03-27. 53. “Packaging structure having three-dimensional wiring,” Tenmyo, Hiroyuki, Isada, Naoya (+3), JP2008047955 (A)— 2008-02-28. 54. “MEMS fiber optic microphone,” Chin, Ken K. (US), Feng, Guanhua (US) (+1), US2008049230 (A1)—2008-02-28. 55. “MEMS packaging with improved reaction to temperature changes,” Strei, David (US), CN101098825 (A)—2008-01-02. 56. “Method and system for sealing packages for optics,” Yang, Xiao (US), Chen, Dongmin (US), US2008014682 (A1)—200801-17. 57. “MEMS microphone packaging structure,” Pan, Zhengmin (CN), CN200994191 (Y)—2007-12-19. 58. “Multiple internal seal ring micro-electro-mechanical system vacuum packaging method,” Hayworth, Ken J. (US), Yee, Karl Y. (US) (+5), US2007298542 (A1)—2007-12-27. 59. “Method for forming a hermetically sealed cavity,” Witvrouw, Ann (BE), Rico, Raquel H. (ES) (+1), US2007298238 (A1)—200712-27.

Introduction to MEMS 60. “Stacked die package for MEMS resonator system,” Gupta, Pavan (US), Razda, Eric (US), US2007290364 (A1)—2007-12-20. 61. “Hermetically sealed wafer level packaging for optical MEMS devices,” Yang, Xiao (US), GB2439403 (A)—2007-12-27. 62. “Method for manufacturing plastic packaging of MEMS devices and structure thereof,” Chen, Jung Tai (TW), Chang, Wen Yang (TW) (+2), KR20070095756 (A)—2007-10-01. 63. “MEMS device packaging methods,” D’Camp, Jon B., Curtis, Harlan L., SG132639 (A1)—2007-06-28. 64. “MEMS flip-chip packaging,” D’Camp, Jon B. (US), Curtis, Harlan L. (US), SG132638 (A1)—2007-06-28. 65. “Condenser microphone and packaging method for the same,” Song, Chung-Dam, SG131039 (A1)—2007-04-26. 66. “Silicon based condenser microphone and packaging method for the same,” Song, Chung-Dam, SG130158 (A1)—2007-03-20. 67. “Desiccant in a MEMS device,” Palmateer, Lauren (US), WO2007136706 (A1)—2007-11-29. 68. “Semiconductor device having microstructure and method of manufacturing microstructure,” Ikeuchi, Naoki (JP), Hashimoto, Hiroyuki (JP), US2007262306 (A1)—2007-11-15. 69. “High performance MEMS packaging archetecture,” Lafond, Peter H. (US), Yu, Lianzhong (US), EP1853928 (A1)—2007-11-14. 70. “Contact planarization materials that generate no volatile byproducts or residue during curing,” Shih, Wu-Sheng (TW), Lamb, James E. III (US) (+1), TW278488 (B)—2007-04-11. 71. “Packaging structure of MEMS microphone,” Park, Peter (KR), Choo, Yun-Jai (KR) (+1), WO2007123300 (A1)—2007-11-01. 72. “Packaging structure of MEMS microphone,” Choo, Yunjai (KR), Park, Peter (KR), WO2007123293 (A1)—2007-11-01. 73. “Method and system for packaging a MEMS device,” Miles, Mark W. (US), Sampsell, Jeffrey B. (US), US2007247693 (A1)— 2007-10-25. 74. “Packaging a MEMS device using a frame,” Natarajan, Bangalore R. (US), Palmateer, Lauren (US), US2007242345 (A1)— 2007-10-18. 75. “MEMS devices and processes for packaging such devices,” Natarajan, Bangalore R. (US), Ganti, Surya (US), US2007242341 (A1)—2007-10-18. 76. “Microelectronic composite, especially packaging structure in sealing cavity of MEMS,” Robert, Philippe, JP2007245339 (A)—2007-09-27.

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Chapter One 77. “Surface coating for electronic systems,” Cho, Junghyun (US), Oliver, Scott (US) (+2), US7282254 (B1)—2007-10-16. 78. “Self-packaging MEMS device,” Heck, John (US), US2007235501 (A1)—2007-10-11. 79. “Multi-unit planar lightwave circuit wavelength dispersive device,” Colbourne, Paul (CA), CA2584147 (A1)—2007-10-06. 80. “Packaging structure of MEMS microphone,” Park, Sung Ho (KR), Lim, Jun (KR) (+1), KR100737726 (B1)—2007-07-04. 81. “Packaging structure of MEMS microphone and construction method thereof,” Choo, Yun Jai (KR), Park, Peter (KR) (+1), KR100737728 (B1)—2007-07-04. 82. “Method of packaging of MEMS device at the vacuum state using a silicide bonding,” Lee, Ho Young (KR), Cho, Sung Woo (KR), KR20070078239 (A)—2007-07-31. 83. “Method of packaging of MEMS device at the vacuum state using a silicide bonding and vacuum packaged MEMS device using the same,” Lee, Ho Young (KR), Cho, Sung Woo (KR), KR20070078233 (A)—2007-07-31. 84. “Microstructure sealing tool and methods of using the same,” Schaadt, Gregory P. (US), US2007172991 (A1)—2007-07-26. 85. “Systems and methods of controlling micro-electromechanical devices,” Miles, Mark W. (US), US2007146376 (A1)—200706-28. 86. “Method for singulating a released microelectromechanical system wafer,” Loeppert, Peter V. (US), WO2007081346 (A1)— 2007-07-19. 87. “Micro-electro-mechanical systems (MEMS) device and system and method of producing the same,” Bar-Sadeh, Eyal (IL), Talalaevski, Alexander (IL) (+1), TW267490 (B)—2006-12-01. 88. “MEMS module package and packaging method,” Lee, Yeong Gyu (KR), KR20070042244 (A)—2007-04-23. 89. “MEMS device package and packaging method,” Kim, Dae Jun (KR), Lee, Yeong Gyu (KR) (+1), KR20070040472 (A)— 2007-04-17. 90. “MEMS device package and packaging method,” Kim, Dae Jun (KR), Lee, Yeong Gyu (KR) (+1), KR20070040471 (A)— 2007-04-17. 91. “MEMS module and packaging method,” Lee, Yeong Gyu (KR), KR20070040033 (A)—2007-04-16. 92. “Method for adjusting the frequency of a MEMS resonator,” Lutz, Aaron, Partridge, Markus (DE), CN1977448 (A)—200706-06.

Introduction to MEMS 93. “Micro electro-mechanical system packaging and interconnect,” Chen, Chien-Hua (US), Bamber, John (US) (+1), US2007128828 (A1)—2007-06-07. 94. “Wafer level packaging process,” Sridhar, Uppili (US), Zou, Quanbo (US), WO2007055924 (A2)—2007-05-18. 95. “Miniature package for translation of sensor sense axis,” MacGugan, Douglas C. (US), EP1785392 (A2)—2007-05-16. 96. “Method for integrated MEMS packaging,” Hartzell, John W. (US), Walton, Harry G. (GB) (+1), US2007099327 (A1)—200705-03. 97. “Systems and methods of testing micro-electromechanical devices,” Miles, Mark W. (US), US2007097134 (A1)—2007-05-03. 98. “Microphone and manufacturing method thereof,” Jang, Jau-Jr (TW), Tsai, Tzuen-Yi (TW) (+1), TW262735 (B)—2006-09-21. 99. “MEMS (micro electronic mechanical system) package and its manufacturing method,” Tenmyo, Hiroyuki, Isada, Naoya (+4), JP2007088189 (A)—2007-04-05. 100. “Micro electromechanical system chip size airtight packaging vertical interconnecting structure and its manufacturing method,” Wang, Yuchuan Luo (CN), CN1935630 (A)—200703-28. 101. “MEMS package and method of forming the same,” McBean, Ronald V. (US), WO2007027380 (A2)—2007-03-08. 102. “Micro device and its packaging method,” Oya, Yoichi, JP2007042786 (A)—2007-02-15. 103. “Microelectromechanical devices and fabrication methods,” Yama, Gary (US), US2007042521 (A1)—2007-02-22. 104. “Chip scale package and its manufacturing method,” Tokushige, Nobuaki, Naka, Toshio, JP2007017199 (A)—2007-01-25. 105. “MEMS micro high sensitivity magnetic field sensor and manufacturing method,” Liu, Wu Yaming (CN), CN1912646 (A)—2007-02-14. 106. “Silicon based condenser microphone and packaging method for the same,” Song, Chung-Dam (KR), WO2007015593 (A1)— 2007-02-08. 107. “MEMS packaging method for enhanced EMI immunity using flexible substrates,” Wang, Zhe (SG), Miao, Yubo (SG), US2007013052 (A1)—2007-01-18. 108. “Method of making an X-Y axis dual-mass tuning fork gyroscope with vertically integrated electronics and wafer-scale hermetic packaging,” Nasiri, Steven S. (US), Flannery, Anthony F., Jr. (US), US2007012653 (A1)—2007-01-18.

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Chapter One 109. “Method and system for packaging MEMS devices with incorporated getter,” Palmateer, Lauren (US), Cummings, William J. (US) (+3), KR20060092914 (A)—2006-08-23. 110. “Methods for depositing, releasing and packaging microelectromechanical devices on wafer substrates,” Patel, Satyadev R. (US), Huibers, Andrew G. (US) (+1), US2007001247 (A1)—2007-01-04. 111. “Two-freedom air-floated precisely locating platform for IC packaging,” Zhang, Dawei (CN), CN1887686 (A)—2007-01-03. 112. “MEMS package,” Yoshikawa, Yasuhiro, Tajiri, Hiroyuki, JP2006321016 (A)—2006-11-30. 113. “Encapsulation process for microelectromechanical structures,” Dudley, Bruce W., Wood, Robert L., KR20010051498 (A)—200106-25. 114. “Method of packaging MEMS,” Ouellet, Luc (CA), Chowdhury, Mamur (CA), EP1734001 (A2)—2006-12-20. 115. “Display device having a movable structure for modulating light and method thereof,” Miles, Mark W. (US), US2006274074 (A1)—2006-12-07. 116. “Production method of glass penetrating wiring board, glass penetrating wiring board, and probe card and packaging element using glass penetrating wiring board,” Fujimoto, Satoshi (JP), WO2006129848 (A1)—2006-12-07. 117. “X-Y axis dual-mass tuning fork gyroscope with vertically integrated electronics and wafer-scale hermetic packaging,” Nasiri, Steve S. (US), Seeger, Joseph (US), TW247896 (B)— 2006-01-21. 118. “Packaging method for rf mems switch to minimize short of switch connection,” Lee, Gyu Bok, KR20040093807 (A)—200411-09. 119. “Bonding method of flip-chip manner for semiconductor apparatus in lateral bonded type, MEMS package using the same, and packaging method,” Jin, Jun Guk, Cheon, Ko Byeong (+2), KR20040042924 (A)—2004-05-22. 120. “Method for forming via hole of glass wafer,” Choi, Hyeong, Hong, Seok U. (+6), KR20040042003 (A)—2004-05-20. 121. “Metal line method even though it has undercut,” Hong, Seok U., Jun, Chan Bong (+7), KR20040034949 (A)—200404-29. 122. “MEMS switch and method for packaging the same,” Lee, Dae Sung (KR), Sung, Woo Kyung (KR) (+3), KR20050113340 (A)—2005-12-02.

Introduction to MEMS 123. “Method of packaging of MEMS device at the vacuum state and vacuum packaged MEMS device using the same,” Lee, Ho Young (KR), Kim, Yong Hyup (KR) (+3), KR20050100039 (A)—2005-10-18. 124. “Electronic parts packaging structure and method of manufacturing the same,” Sunohara, Masahiro (JP), Higashi, Mitsutoshi (JP), US2006246630 (A1)—2006-11-02. 125. “Apparatus for packaging MEMS element and method thereof,” Jang, Hyuk Kyoo (KR), Noh, Seung Jeong (KR) (+3), KR20060061044 (A)—2006-06-07. 126. “Pizoelectric rf MEMS switch using wafer unit packaging and microfabrication technology and fabrication method thereof,” Park, Jae Hyoung (KR), Lee, Hee Chul (KR) (+1), KR20060022561 (A)—2006-03-10. 127. “Method for manufacturing structure of micro electromechanical system capable of wafer-level vacuum packaging,” Baek, Seok Sun (KR), Ha, Byeong Ju (KR) (+3), KR20010045332 (A)—2001-06-05. 128. “Variable display,” Jensen, Thomas (US), Lawler, Casimer E., Jr. (US), US2006227002 (A1)—2006-10-12. 129. “MEMS packaging structure and methods,” Haluzak, Charles C. (US), Pollard, Jeffrey R. (US), US2006228869 (A1)—200610-12. 130. “Reactive nano-layer material for MEMS packaging,” Lu, Daoqiang (US), Heck, John (US), US2006220223 (A1)—200610-05. 131. “Method of fabrication of AI/GE bonding in a wafer packaging environment and a product produced therefrom,” Nasiri, Steven S. (US), Flannery, Anthony Francis, Jr. (US), WO2006101769 (A2)—2006-09-28. 132. “Structure and process for packaging RF MEMS and other devices,” Schaper, Leonard W. (US), Malshe, Ajay P. (US) (+1), US2006211177 (A1)—2006-09-21. 133. “Passive devices and modules for transceiver and manufacturing method thereof,” Song, In Sang (KR), KR20020095728 (A)—2002-12-28. 134. “MEMS device for wafer level packaging and method for fabricating the same,” Jin, Jang Seok (KR), KR20020058223 (A)— 2002-07-12. 135. “MEMS packaging using a non-silicon substrate for encapsulation and interconnection,” Heck, John (US), Hayden, Joseph S., III (US) (+2), US2006194361 (A1)—2006-08-31.

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Chapter One 136. “Optical fiber MEMS pressure sensor packaging structure,” Li, Wang Ming (CN), CN2811965 (Y)—2006-08-30. 137. “Low temperature airtightness packaging method for wafer level micro machinery device and photoelectric device,” Wu, Liu Yufei (CN), CN1821052 (A)—2006-08-23. 138. “Heating device for automatic anode linkage of MEMS hightemperature pressure sensor,” Rong, Xie Hui (CN), CN1815705 (A)—2006-08-09. 139. “Packaging of micro devices,” O’Mahony, Conor (IE), Hill, Martin (IE), IE20060046 (A1)—2006-07-26. 140. “Ultra-small profile, low cost chip scale accelerometers of two and three axes based on wafer level packaging,” Liu, Sheng (CN), Chen, Bin (US) (+3), US2006179940 (A1)—200608-17. 141. “Laser assisted chemical etching method for release of microscale and nanoscale devices,” Abraham, Margaret H. (US), Helvajian, Henry (US) (+1), US2006183330 (A1)—200608-17. 142. “Dimesize attitude measurement system in magnetic infrared ray,” Liu, Ye Xiongying (CN), CN1796932 (A)—2006-07-05. 143. “A packaging method for MEMS devices, and MEMS packages produced using the method,” Wang, Zhe (SG), WO2006085825 (A1)—2006-08-17. 144. “Monolithically integrated switchable circuits with MEMS,” Yang, Jeffrey M. (US), Nishimoto, Matt (US) (+3), WO2006083432 (A1)—2006-08-10. 145. “Method and system for packaging MEMS devices with incorporated getter,” Cummings, Manish, Gall, William J. (US), CN1773358 (A)—2006-05-17. 146. “Method and system for packaging a MEMS device,” Miles, Mark W., Sampsell, Jeffrey (US), CN1755473 (A)—2006-04-05. 147. “Apparatus and method for wafer level packaging,” Chen, Jen-Yi (TW), Chiou, Jing-Hung (TW) (+1), TW236111 (B)— 2005-07-11. 148. “Silicon packaging for opto-electronic modules,” Epitaux, Marc (US), WO2006074048 (A2)—2006-07-13. 149. “Integrated MEMS packaging,” Hartzell, John W. (US), Walton, Harry G. (GB) (+1), US2006148137 (A1)—2006-07-06. 150. “System and method for display device with activated desiccant,” Cummings, William J. (US), MXPA05009407 (A)—200603-29.

Introduction to MEMS 151. “Device having patterned spacers for backplates and method of making the same,” Arbuckle, Brian W. (US), MXPA05009402 (A)—2006-03-29. 152. “Injection-molded package for MEMS inertial sensor,” D’Camp, Jon B. (US), Curtis, Harlan L. (US), WO2006068907 (A1)—2006-06-29. 153. “System and method for protecting microelectromechanical system using back-plate with non-flat portion,” Gally, Brian J., Palmateer, Lauren (+1), JP2006119603 (A)—2006-05-11. 154. “Micro-electromechanical varactor with enhanced tuning range,” Chinthakindi, Anil K. (IN), Groves, Robert A. (US) (+3), TW232500 (B)—2005-05-11. 155. “System and method for display device with end-of-life phenomena,” Palmateer, Lauren (US), US2006077524 (A1)—200604-13. 156. “Package for MEMS devices,” D’Camp, Jon B. (US), Curtis, Harlan L. (US), US2006042382 (A1)—2006-03-02. 157. “Micro-fluidic interconnect,” Okandan, Murat (US), Galambos, Paul C. (US) (+2), US7004198 (B1)—2006-02-28. 158. “Semiconductor acceleration sensor system and its manufacturing method,” Kanno, Yoshinori, JP2006003277 (A)—200601-05. 159. “Embedded integrated circuit packaging structure,” Park, Heung-Woo (KR), Song, Jong-Hyeong (KR), US2005275113 (A1)—2005-12-15. 160. “Lead-free bonding systems,” Aggarwal, Ankur (US), Abothu, Isaac R. (US) (+2), US2005274227 (A1)—2005-12-15. 161. “Micro electrical mechanical system (MEMS) tuning using focused ion beams,” Kubena, Randall L. (US), Joyce, Richard J. (US), US2005269901 (A1)—2005-12-08. 162. “Processes for hermetically packaging wafer level microscopic structures,” Cheung, Kin P. (US), US2005189621 (A1)— 2005-09-01. 163. “MEMS device with integral packaging,” Cohn, Michael B. (US), Xu, Ji-Hai (US), US2005168306 (A1)—2005-08-04. 164. “Microelectromechanical systems having trench isolated contacts, and methods for fabricating same,” Partridge, Aaron (US), Lutz, Markus (US) (+1), US2005156260 (A1)—2005-07-21. 165. “Micro connector and non-powered microassembly with micro connector,” Tsui, Kenneth, Geisberger, Aaron (+1), JP2005276816 (A)—2005-10-06.

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Chapter One 166. “Hermetic wafer-level packaging for MEMS devices with low-temperature metallurgy,” Ouellet, Luc (CA), Turcotte, Karine (CA), EP1544164 (A2)—2005-06-22. 167. “Hermetic wafer-level packaging for MEMS devices with low-temperature metallurgy,” Ouellet, Luc (CA), Turcotte, Karine (CA), US2005142685 (A1)—2005-06-30. 168. “Microelectromechanical system and method for determning temperature and moisture profiles within pharmaceutical packaging,” Walker, Dwight S. (US), US2005223827 (A1)— 2005-10-13. 169. “Packaging microelectromechanical structures,” Ma, Qing (US), Rao, Valluri (US) (+3), US2005062120 (A1)—2005-03-24. 170. “Method of making an X-Y axis dual-mass tuning fork gyroscope with vertically integrated electronics and wafer-scale hermetic packaging,” Nasiri, Steven S., Flannery, Anthony Francis, Jr., WO2005043078 (A2)—2005-05-12. 171. “Methods for depositing, releasing and packaging microelectromechanical devices on wafer substrates,” Patel, Satyadev R. (US), Huibers, Andrew G. (US) (+1), US2005048688 (A1)—2005-03-03. 172. “A biological micro spray array dot sample device and method for making same,” Zhao, Jianlong (CN), Xu, Baojian (CN) (+1), CN1629319 (A)—2005-06-22. 173. “Bonding for a micro-electro-mechanical system (MEMS) and MEMS based devices,” Platt, William P. (US), Ford, Carol M. (US), US2004266048 (A1)—2004-12-30. 174. “Micro electro-mechanical variable capacitor,” Chinthakindi, Anil K. (US), US6906905 (B1)—2005-06-14. 175. “Wafer bonding method using reactive foils for massively parallel micro-electromechanical systems packaging,” Snyder, Tanya Jegeris, Yi, Robert H. (+1), JP2005040940 (A)—2005-02-17. 176. “Ultra-miniature accelerometers,” Kenny, Thomas W., Park, Woo-Tae, WO2004092746 (A1)—2004-10-28. 177. “Ultra-miniature accelerometers,” Kenny, Thomas W. (US), Park, Woo-Tae (US), US2004200281 (A1)—2004-10-14. 178. “Magneic switch for use in a system that includes an in-vivo device, and method of use thereof,” Iddan, Gavriel J. (IL), US2004254455 (A1)—2004-12-16. 179. “Magnetic switch for use in a system that includes an in-vivo device, and a method of use thereof,” Iddan, Gavriel J. (IL), WO2004086434 (A2)—2004-10-07.

Introduction to MEMS 180. “Electromechanical system having a controlled atmosphere, and method of fabricating same,” Kronmueller, Silvia (DE), Lutz, Markus (US) (+1), EP1460038 (A2)—2004-09-22. 181. “Optical deflector,” Hara, Koichi, JP2005250307 (A)—200509-15. 182. “Method for fabricating a lid for a wafer level packaged optical MEMS device,” Ehmke, John C. (US), Lopes, Vincent C. (US) (+1), US6856014 (B1)—2005-02-15. 183. “MEMS package,” Brady, Frederick T. (US), US2004099921 (A1)—2004-05-27. 184. “Micro dynamic piezoresistance pressure sensor and manufacturing method thereof,” Wang, Wenxiang (CN), Li, Shuixia (CN) (+1), CN1544901 (A)—2004-11-10. 185. “Processes for hermetically packaging wafer level microscopic structures,” Cheung, Kin P, WO2004037711 (A2)— 2004-05-06. 186. “Processes for hermetically packaging wafer level microscopic structures,” Cheung, Kin P. (US), US2004126953 (A1)— 2004-07-01. 187. “Optical switch and method of producing the same,” Lee, Hyun Kee (KR), Jung, Sung Cheon (KR) (+1), US2004264848 (A1)—2004-12-30. 188. “Method of fabricating an integrated circuit and its precursor assembly,” Ouellet, Luc (CA), Poisson, Jules (CA), EP1405821 (A2)—2004-04-07. 189. “Method of air tight packaging micro computer electric system device using capillary tube method,” Wang, Lichun (CN), Luo, Le (CN) (+1), CN1513751 (A)—2004-07-21. 190. “Latching micro magnetic relay packages and methods of packaging,” Stafford, John (US), Tam, Gordon (US) (+1), US2004027218 (A1)—2004-02-12. 191. “MEMS control chip integration,” Kuo, Shun-Meen, Foerstner, Juergen A (+7), WO2004051744 (A2)—2004-06-17. 192. “Whole wafer MEMS release process,” Dewa, Andrew S. (US), US2004002215 (A1)—2004-01-01. 193. “Encapsulants for protecting MEMS devices during postpackaging release etch,” Peterson, Kenneth A. (US), US6956283 (B1)—2005-10-18. 194. “Method of trimming micro-machined electromechanical sensors (MEMS) devices,” Dwyer, Paul W. (US), US2003196489 (A1)—2003-10-23.

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Chapter One 195. “Methods for depositing, releasing and packaging microelectromechanical devices on wafer substrates,” Patel, Satyadev (US), Huibers, Andrew (US) (+8), WO03105198 (A1)— 2003-12-18. 196. “Microelectromechanical system and method for determining temperature and moisture profiles within pharmaceutical packaging,” Walker, Dwight Sherod (US), WO03107397 (A2)—2003-12-24. 197. “Post-package technology for microelectromechinical system,” Liu, Sheng (CN), Zhang, Honghai (CN) (+1), CN1449990 (A)— 2003-10-22. 198. “On-wafer packaging for rf-MEMS,” Margomenos, Alexandros (US), Herrick, Katherine J. (US) (+2), WO03095357 (A2)—200311-20. 199. “Wafer-level MEMS packaging,” Ouellet, Luc (CA), EP1352877 (A2)—2003-10-15. 200. “Bonding method, bonding device and sealant,” Yuasa, Mitsuhiro, JP2004235465 (A)—2004-08-19. 201. “CMOS compatible microswitches,” Huang, Jung-Tang (TW), Li, Sheng-Hung (TW) (+2), TW565530 (B)—2003-12-11. 202. “Structure and process for packaging rf MEMS and other devices,” Schaper, Leonard W. (US), Malshe, Ajay P. (US) (+1), WO03054927 (A2)—2003-07-03. 203. “Package structure and method for making the same,” Lee, Chenkuo (TW), Yi-Mou, Huang (TW), US2004087043 (A1)— 2004-05-06. 204. “MEMS device sealing packaging method and the fabrication method of metal cap thereof,” Pan, Jeng-Tang (TW), Lin, Kuen-Lung (TW), TW560028 (B)—2003-11-01. 205. “MEMS direct chip attach packaging methodologies and apparatuses for harsh environments,” Okojie, Robert S. (US), US6845664 (B1)—2005-01-25. 206. “Latching micro magnetic relay packages and methods of packaging,” Stafford, John (US), Tam, Gordon (US) (+1), WO03026369 (A1)—2003-03-27. 207. “Electromagnetic actuation optical switch and the fabrication method thereof,” Lu, Hui-Chuan (TW), Lee, Hsin-Li (TW) (+2), TW562951 (B)—2003-11-21. 208. “MEMS wafer level package,” Orcutt, John W. (US), Dewa, Andrew Steven (US) (+1), US2002179986 (A1)—2002-12-05. 209. “A low-cost HDMI-D packaging technique for integrating an efficient reconfigurable antenna array with rf MEMS switches

Introduction to MEMS and a high impedance surface,” Sievenpiper, Daniel F. (US), Schmitz, Adele E. (US) (+3), TW583789 (B)—2004-04-11. 210. “Packaging of MEMS devices using a thermoplastic,” Tourino, Cory G. (US), Rice, Janet L. (US) (+1), US6809412 (B1)—200410-26. 211. “Wafer level MEMS packaging,” Lin, Jong-Kai (US), Lytle, William H. (US) (+5), US2003230798 (A1)—2003-12-18. 212. “Microelectromechanical system device package and packaging method,” Saia, Richard Joseph (US), Durocher, Kevin Matthew (US) (+2), US2002173080 (A1)—2002-11-21. 213. “Surface excited device package including a substrate having a vibration-permitted cavity,” Youl, Min Byoung (KR), Lee, Choon Heung (KR) (+1), US2004164384 (A1)—2004-08-26. 214. “Electrostatically actuated micro-electro-mechanical devices and method of manufacture,” Kudrle, Thomas David (US), Mastrangelo, Carlos Horacio (US) (+6), WO02079853 (A1)— 2002-10-10. 215. “Electrostatically actuated micro-electro-mechanical devices and method of manufacture,” Kudrle, Thomas David (US), Mastrangelo, Carlos Horacio (US) (+6), US2002146200 (A1)— 2002-10-10. 216. “Packaging micromechanical devices,” Low, Yee Leng (US), Ramsey, David Andrew (US), US6603182 (B1)—2003-08-05. 217. “Micromachined fiber optic sensors,” Boyd, Joseph T. (US), Abeysinghe, Don C. (US) (+2), US2002159671 (A1)—200210-31. 218. “Micro-electro-mechanical systems packaging,” West, Glenn S. (SG), Alai, Aijay Babulal (SG) (+1), WO03085732 (A1)—200310-16. 219. “Multilayered microelectronic device package with an integral window,” Peterson, Kenneth A. (US), Watson, Robert D. (US), US6538312 (B1)—2003-03-25. 220. “Photonic component package and method of packaging,” Vaganov, Vladlmin (US), US2003138220 (A1)—2003-07-24. 221. “Method for calibrating a MEMS device,” Gates, John V. (US), Holland, William R. (US) (+2), US2003133644 (A1)— 2003-07-17. 222. “Flex circuit interconnect subassembly and electronic device packaging utilizing same,” Simmons, Richard L. (US), TW548233 (B)—2003-08-21. 223. “Microbar and method of its making,” Kemeny, Zoltan A. (US), US6515346 (B1)—2003-02-04.

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Chapter One 224. “Method of packaging a photonic component and package,” Kohlstadt, Michael (US), Vaganov, Vladmir (US) (+1), US2003113074 (A1)—2003-06-19. 225. “Magnetically packaged optical MEMS device and method for making the same,” Jin, Sungho, Soh, Hyongsok, JP2002236266 (A)—2002-08-23. 226. “Packaging atmosphere and method of packaging a MEMS device,” Henshall, Gordon (GB), Rolt, Stephen (GB), WO0227381 (A2)—2002-04-04. 227. “Method of trimming micro-machined electromechanical sensor (MEMS) devices,” Dwyer, Paul, WO0228766 (A2)— 2002-04-11. 228. “Temporary coatings for protection of microelectronic devices during packaging,” Peterson, Kenneth A. (US), Conley, William R. (US), US6844623 (B1)—2005-01-18. 229. “Wafer level hermetic sealing method,” Cho, Chang-Ho, Shin, Hyung-Jae (+1), JP2002246489 (A)—2002-08-30. 230. “Vacuum package fabrication of integrated circuit components,” Gooch, Roland W. (US), Schimert, Thomas R. (US), US2002000646 (A1)—2002-01-03. 231. “Chip scale surface-mountable packaging method for electronic and MEMS devices,” Kang, Seok-Jin (KR), US2002001873 (A1)—2002-01-03. 232. “Protective fullerene (C60) packaging system for microelectromechanical systems applications,” Olivas, John D. (US), US6791108 (B1)—2004-09-14. 233. “Micro mechanical packaging apparatus,” Degani, Yinon, Dudderar, Thomas D. (+1), JP2002043449 (A)—2002-02-08. 234. “Vacuum package fabrication of microelectromechanical system devices with integrated circuit components,” Gooch, Roland W., Schimert, Thomas R., WO0156921 (A2)—200108-09. 235. “Module with bumps for connection and support,” Pace, Benedict G (US), US6614110 (B1)—2003-09-02. 236. “Guided bullet,” Lipeles, Jay (US), Brosch, R Glenn (US), US2002190155 (A1)—2002-12-19. 237. “Package having cavity for housing MEMS,” Bishop, David John, Gates, John Vanatta (+1), JP2001185635 (A)—2001-07-06. 238. “Improved MEMS wafer-level package,” Oakatto, John W., Dowa, Andrew Steven (+1), JP2001144117 (A)—2001-05-25. 239. “Low-temp MEMS vacuum sealing technique for metals,” Jin, Yufeng (CN), Wu, Guoying (CN) (+1), CN1289659 (A)— 2001-04-04.

Introduction to MEMS 240. “Pre-release plastic packaging of MEMS and IMEMS devices,” Peterson, Kenneth A. (US), Conley, William R. (US), US6379988 (B1)—2002-04-30. 241. “Vacuum package fabrication of microelectromechanical system devices with integrated circuit components,” Gooch, Roland W. (US), US6479320 (B1)—2002-11-12. 242. “Hermetic chip scale packaging means and method including self test,” Bartlett, James L. (US), Wooldridge, James R. (US) (+1), US2003073292 (A1)—2003-04-17. 243. “Cover cap for semiconductor wafer devices,” Karpman, Maurice S. (US), Sengupta, Dipak (US), US6534340 (B1)— 2003-03-18. 244. “Microjoinery methods and devices,” Collins, Scott D. (US), US6393685 (B1)—2002-05-28.

References 1. Madou, M. J. Fundamentals of Microfabrication: The Science of Miniaturization. Boca Raton, FL: CRC Press, 2002. 2. Nguyen, C. “MEMS technology for timing and frequency control.” IEEE Trans. Ultrason. Ferroelect. Freq. Contr. 54:251–270, 2007. 3. Gad-el-Hak, M. The Mems Handbook. Boca Raton, FL: CRC Press, 2002. 4. Hacker, J. B., Mihailovich, R. E., Kim, M., and DeNatale, J. F. “A Ka-band 3-bit rf MEMS true-time-delay network.” IEEE Trans. Microwave Theory Tech. 51: 305–308, 2003. 5. Menz, W., Mohr, J., and Paul, O. Microsystem Technology. Hoboken, NJ: WileyVCH, 2001. 6. Goldsmith, C. L., Yao, Z., Eshelman, S., and Denniston, D. “Performance of low-loss rf MEMS capacitive switches.” IEEE Microwave Wireless Compon. Lett. 8:269–271, 1998. 7. Senturia, S. D. Microsystem Design. New York: Springer, 2000. 8. Rebeiz, G. M. RF MEMS: Theory, Design and Technology. Hoboken, NJ: Wiley, 2003. 9. Anagnostou, D. E., Christodoulou, C. G., Tzeremes, G., Liao, T. S., and Yu, P. K. L. “Fractal antennas with rf-MEMS switches for multiple frequency applications.” In Proceedings of the IEEE APS/URSI International Symposium, Vol. 2, San Antonio, TX, June 2002, pp. 22–25. 10. Yano, M., Yamagishi, F., and Tsuda, T. “Optical MEMS for photonic switchingcompact and stable optical crossconnect switches for simple, fast, and flexible wavelength applications in recent photonic networks.” J. Selected Topics Quantum Elect. 11:383–394, 2005. 11. Anagnostou, D. E., Zheng, G., Chryssomallis, M., Lyke, J. C., Ponchak, G. E., Papapolymerou, J., and Christodoulou, C. G. “Design, fabrication and measurements of a self-similar re-configurable antenna with rf-MEMS switches.” IEEE Trans. Antennas Propagat. 54:422–432, 2006. 12. Liu, A. Q., and Zhang, X. M. “A review of MEMS external-cavity tunable lasers.” J. Micromech. Microeng. 17:R1–R13, 2007. 13. Huff, G. H., and Bernhard, J. T. “Integration of packaged rf MEMS switches with radiation pattern reconfigurable square spiral microstrip antennas.” IEEE Trans. Antennas Propagat. 54:464–469, 2006. 14. Kingsley, N., Anagnostou, D. E., Tentzeris, M., and Papapolymerou, J. “Rf MEMS sequentially reconfigurable Sierpinski antenna on a flexible organic substrate with novel dc-biasing technique.” IEEE/ASME J. Microelectromech. Syst. 16:1185–1192, 2007.

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Chapter One 15. Van Caekenberghe, K., and Sarabandi, K. “A 2-bit Ka-band rf MEMS frequency tunable slot antenna.” IEEE Antennas Wireless Propagat. Lett. 7:179–182, 2008. 16. Nguyen, C. “MEMS technology for timing and frequency control.” IEEE Trans. Ultrason. Ferroelect. Freq. Contr. 54:251–270, 2007. 17. Young, R. M., Adam, J. D., Vale, C. R., Braggins, T. T., Krishnaswamy, S. V., Milton, C. E., Bever, D. W., Chorosinski, L. G., Li-Shu Chen, Crockett, D. E., Freidhoff, C. B., Talisa, S. H., Capelle, E., Tranchini, R., Fende, J. R., Lorthioir, J. M., and Tories, A. R. “Low-loss bandpass rf filter using MEMS capacitance switches to achieve a one-octave tuning range and independently variable bandwidth.” IEEE MTT-S Int. Microwave Symp. Digest 3:1781–1784, 2003. 18. Tan, G. L., Mihailovich, R. E., Hacker, J. B., DeNatale, J. F., and Rebeiz, G. M. “Low-loss 2- and 4-bit TTD MEMS phase shifters based on SP4T switches.” IEEE Trans. Microwave Theory Tech. 51:297–304, 2003. 19. Hacker, J. B., Mihailovich, R. E., Kim, M., and DeNatale, J. F. “A Ka-band 3-bit rf MEMS true-time-delay network.” IEEE Trans. Microwave Theory Tech. 51: 305–308, 2003. 20. Ford, J. E., Goossen, K. W., Walker, J. A., Neilson, D. T., Tennant, D. M., Park, S. Y., and Sulhoff, J. W. “Interference-based micromechanical spectral equalizers.” IEEE J. Selected Topics Quantum Elect. 10:579–587, 2004. 21. Nordquist, C. D., Dyck, C. W., Kraus, G. M., Reines, I. C., Goldsmith, L., Cowan, D., Plut, T.A., Austin, F., IV, Finnegan, P. S., Ballance, M. H., and Sullivan, T. “A dc to 10 GHz 6-bit rf MEMS time delay circuit.” IEEE Microwave Wireless Compon. Lett. 16:305–307, 2006. 22. Perruisseau-Carrier, J., Fritschi, R., Crespo-Valero, P., and Skrivervik, A. K. “Modeling of periodic distributed MEMS application to the design of variable true-time-delay lines.” IEEE Trans. Microwave Theory Tech. 54:383–392, 2006. 23. Kim, C.-H., Park, N., and Kim, Y.-K. “MEMS reflective type variable optical attenuator using off-axis misalignment.” Proc. IEEE/LEOS Int. Conf. Opt. MEMS, Lugano, Switzerland, 2002, pp. 55–56. 24. Lakshminarayanan, B., and Weller, T. M. “Design and modeling of 4-bit slowwave MEMS phase shifters.” IEEE Trans. Microwave Theory Tech. 54:120–127, 2006. 25. Lakshminarayanan, B., and Weller, T. M. “Optimization and implementation of impedance-matched true-time-delay phase shifters on quartz substrate.” IEEE Trans. Microwave Theory Tech. 55:335–342, 2007. 26. Van Caekenberghe, K., and Vaha-Heikkila, T. “An analog rf MEMS slotline true-time-delay phase shifter.” IEEE Trans. Microwave Theory Tech. 56:2151–2159, 2008. 27. Maciel, J. J., Slocum, J. F., Smith, J. K., and Turtle, J. “MEMS electronically steerable antennas for fire control radars.” IEEE Aerosp. Electron. Syst. Mag. Nov. 2007, pp. 17–20. 28. Yeow, T.-W., Law, K. L. E., and Goldenberg, A. “MEMS optical switches.” IEEE Commun. Mag. 39:158–163, 2001. 29. Herrick, K. J., Jerinic, G., Molfino, R. P., Lardizabal, S. M., and Pillans, B. “S-Ku band intelligent amplifier microsystem.” Proc. SPIE 6232, May 2006. 30. Neukermans, A., and Ramaswami, R. “MEMS technology for optical networking.” IEEE Commun. Mag. 39:62–69, 2001. 31. Pranonsatit, S., Holmes, A. S., Robertson, I. D., and Lucyszyn, S. “Single-pole eight-throw rf MEMS rotary switch.” IEEE/ASME J. Microelectromech. Syst. 15:1735–1744, 2006. 32. Lin, L. Y., and Goldstein, E. L. “Opportunities and challenges for MEMS in lightwave communications.” IEEE J. Selected Topics Quantum Elect. 8:163–172, 2002. 33. Vaha-Heikkila, T., Van Caekenberghe, K., Varis, J., Tuovinen, J., and Rebeiz, G. M. “Rf MEMS impedance tuners for 6–24 GHz applications.” Wiley Int. J. RF Microwave Computer-Aided Eng. 17: 265–278, 2007. 34. Syms, R. A., and Moore, D. F. “Optical MEMS for telecoms.” Materials Today 5:26–35, 2002.

Introduction to MEMS 35. Schoebel, J., Buck, T., Reimann, M., Ulm, M., Schneider, M., Jourdain, A., Carchon, G., and Tilmans, H., “Design considerations and technology assessment of phased array antenna systems with rf MEMS for automotive radar applications.” IEEE Trans. Microwave Theory Tech. 53:1968–1975, 2005. 36. Wu, M. C., Solgaard, O., and Ford, J. E. “Optical MEMS for lightwave communication.” J. Lightwave Technol. 24:4433–4454, 2006. 37. Mailloux, R. J. Phased Array Antenna Handbook. New York: Artech House, 2005. 38. Hoffmann. M., and Voges, E. “Bulk silicon micromachining for MEMS in optical communication systems.” J. Micromech. Microeng. 12:349–360, 2002. 39. Jung, C., Lee, M., Li, G. P., and Flaviis, F. D. “Reconfigurable scan-beam singlearm spiral antenna integrated with rf MEMS switches.” IEEE Trans. Antennas Propagat. 54:455–463, 2006. 40. Chang-Hasnain, C. J. “Tunable VCSEL.” J. Selected Topics Quantum Elect. 6: 978–987, 2000. 41. Lijie, J. Z., and Uttamchandani, D. “Integrated self-assembling and holding technique applied to a 3-D MEMS variable optical attenuator.” IEEE J. Microelectromech. Syst. 13:83–90, 2004. 42. Wikipedia. “Microelectromechanical systems:” available at http://en.wikipedia .org/wiki/MEMS, last accessed on April 1, 2008. 43. Yole Development. “World MEMS Markets: The 2006–2012 MEMS Market Database,” 2008. 44. Lau, J. H., Wong, C. P., Lee, N. C., and Lee, R. Electronics Manufacturing with Lead-Free, Halogen-Free, and Adhesive Materials. New York: McGraw-Hill, 2003. 45. Lau, J. H., and Lee, R. Microvias for Low Cost, High Density Interconnects. New York: McGraw-Hill, 2001. 46. Lau, J. H. Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies. New York: McGraw-Hill, 2000. 47. Lau, J. H., and Lee, R. Chip Scale Package Design: Materials, Process, Reliability, and Applications. New York: McGraw-Hill, 1999. 48. Lau, J. H., Wong, C. P., Prince, J., and Nakayama, W. Electronic Packaging: Design, Materials, Process, and Reliability. New York: McGraw-Hill, 1998. 49. Lau, J. H., and Pao, Y. Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies. New York: McGraw-Hill, 1997. 50. Lau, J. H. Flip Chip Technologies. New York: McGraw-Hill, 1996. 51. Lau, J. H. Ball Grid Array Technology. New York: McGraw Hill, 1995. 52. Lau, J. H. Chip on Board Technologies for Multichip Modules. New York: Van Nostrand Reinhold, 1994. 53. Lau, J. H. Handbook of Fine Pitch Surface Mount Technology. New York: Van Nostrand Reinhold, 1994. 54. Lau, J. H. Thermal Stress and Strain in Microelectronics Packaging. New York: Van Nostrand Reinhold, 1993. 55. Lau, J. H. Handbook of Tape Automated Bonding. New York: Van Nostrand Reinhold, 1992. 56. Lau, J. H. Solder Joint Reliability: Theory and Applications. New York: Van Nostrand Reinhold, 1991.

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CHAPTER

2

Advanced MEMS Packaging 2.1

Introduction This chapter briefly discusses the state of the art and future trends in advanced integrated circuit (IC) electronics packaging, followed by a discussion of advanced microelectromechanical systems (MEMS) packaging, where 10 different designs of three-dimensional (3D) MEMS packaging will be presented.

2.2 Advanced IC Packaging 3D IC integration with wafer-level packaging (WLP) has been the hottest packaging technology in the past few years and will be the trend in the future. The supply chain of 3D IC integration and WLP includes semiconductor device designers, foundries, packaging and testing houses, electronic design automation (EDA) vendors, processing equipment suppliers, materials suppliers, universities and research institutes, and industry analysts. In this section, the Moore’s law versus more than Moore (MTM) will be discussed briefly first. Next, some of the critical issues of 3D IC integration will be presented. Finally, a couple of enabling technologies (e.g., microbumps and thermal management) for 3D IC integration with WLP will be provided.

2.2.1

Moore’s Law versus More Than Moore (MTM)

In April 1965, Moore published a paper in Electronics with the title, “Cramming More Components onto Integrated Circuits.” Based on a few data points (Figs. 2-1 and 2-2), Moore proposed to put more transistors on an IC by reducing the feature sizes. Further, he suggested that the number of transistors on an IC (for minimum cost) doubles every 24 months. In the past 40+ years, Moore’s observation (law) about silicon integration (i.e., cost, yield, and reliability) has been the most powerful driver for development of the microelectronics industry. This law places emphasis on lithography scaling and integration

47

Chapter Two 16 15 Log2 of the number of components per integrated function

14 13 12 11 10 9 8 7 6 5 4 3 2 1975

1974

1973

1972

1971

1970

1969

1968

1967

1966

1965

1964

1963

1962

1961

1960

1959

1

Year

FIGURE 2-1 The empirical observation made by Moore in 1965 that the number of transistors on an IC for minimum component cost doubles every 24 months. 105 1962 Relative manufacturing cost/component

48

104

1965 103

102

1970

10

1 1

10

102

103

104

105

Number of components per integrated circuit

FIGURE 2-2 Moore’s observation about silicon integration (i.e., cost, yield, and reliability) has fueled the worldwide technology revolution: (1) IC miniaturization down to the nanoscale and (2) SoC-based system integration.

Advanced MEMS Packaging

MEMS ASIC

Seal ring

FIGURE 2-3 The accelerometer MEMS device is integrated into the ASIC chip by Analog Devices. On the other hand, the same functions can be achieved by stacking the MEMS device on the ASIC chip, resulting in 3D MEMS packaging.

[in two dimensions (2D)] of all functions on a single chip, perhaps through system-on-chip (SoC) capabilities. Today, 32-nm ICs are in volume production, and production of 28-nm ICs is planned to begin in the second half of 2010. In the meantime, 22-nm technology has been working/performing very well in research institutions and laboratories. On the other hand, integration of all these functions can be achieved through system-in-package (SiP) or, ultimately, 3D IC integration and WLP, which is called more than Moore (MTM).1–54 Figure 2-3 shows an example of Moore’s law (2D) versus MTM (3D). It can be seen from the left side of the figure that the accelerometer MEMS device is integrated into the ASIC chip by Analog Devices. On the other hand, the same functions can be achieved by stacking the MEMS device on the ASIC chip,52–54 resulting in 3D MEMS packaging (or 3D MEMS SiP or 3D MEMS WLP), which is the focus of this book. It should be pointed out that MTM is much more than just SiP. Based on the silicon-platform technology, anything that involves the integration of electronics, photonics, mechanics, chemistry, heat, magnetics, biology, etc., for functionality and system performance when interacting with people and the environment can be called MTM. One of the reasons why MEMS is called MTM is because the microelectronic ICs are thought of as the “brains” of a system, and MEMS augments this decision-making capability with “eyes” and “arms” to allow microsystems to sense and control the environment.

2.2.2

3D IC Integration with WLP

The Holy Grail of 3D IC integration (heterogeneous integration) is shown in Fig. 2-4, where all the chips [e.g., microdisplay, MEMS, memory, microprocessor, multiple outputs dc-dc converter, digital signal processor, microbattery, and analog-to-digital (A/D) mixed signal]

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Chapter Two

DSP B A

Memory Display B

DSP

OPTO

Display

Processor Memory

MEMS

Long wiring (from A to B) in 2D SoC

OPTO

MEMS TSV

A

Micro bumps

Processor

Short wiring (from A to B) in 3D IC integration with TSV and microbumps

FIGURE 2-4 The Holy Grail of 3D IC integration (heterogeneous integration) with TSV, which provides shorter wiring than 2D SoC.

are stacking in three dimensions. Just as with many other new technologies, 3D IC integration still faces many critical issues. In the development of 3D IC integration, the following must be noted and understood:1–24 • Design guidelines and software are not available. • Test methods and equipment are lacking. • Known good dies (KGDs) are required. • Through-silicon vias (TSVs) with redistribution layers (RDLs) usually are required. • Microbumps usually are required. • Equipment accuracy is necessary for alignments. • Fast chips must be mixed with slow chips. • Large chips must be mixed with small chips. • Wafer thinning and thin-wafer handling during processing are necessary. • Thermal issues: • The heat flux generated by stacked multifunctional chips in miniature packages is extremely high. • 3D circuits increase total power generated per unit surface area. • Chips in the 3D stack may be overheated if proper and adequate cooling is not provided. • The space between the 3D stack may be too small for cooling channels (i.e., no gap for fluid flow).

Advanced MEMS Packaging • Thin chips may create extreme conditions for on-chip hot spots. • 3D IC stacking inspection methodology is needed. • 3D IC stacking expertise is lacking. • 3D IC stacking infrastructure is lacking. • 3D IC stacking standards are lacking. In the past few years, some of these critical issues have been studied by a number of experts. Their results have already been disclosed in diverse journals or, more specifically, in the proceedings of many conferences, symposia, and workshops whose primary emphases have been on electrical packaging and interconnection. Consequently, there is no single source of information devoted to the state of the art of 3D IC integration with WLP technology. This section briefly mentions only microbumps and thermal management of 3D IC integration. The other important enabling technology (e.g., TSV; wafer thinning and thin-wafer handling; thin-wafer strengthening; wafer dicing; underfilling; lead-free soldering; low-temperature bonding; chip-to-chip (C2C), chip-to-wafer (C2W), and wafer-to-wafer (W2W) bonding; and in situ stress measurement for MEMS applications) will be discussed throughout the remaining chapters of this book. Figure 2-5 shows a generic 3D IC packaging roadmap provided by IBM.1 It can be seen from the “Chip-to-chip/chip-to-wafer” line that microbumps are used for connecting the high-performance chips and the TSV silicon carrier (interposer) and the 3D TSV memory-chip stack. Figure 2-6 shows Intel’s proposed roadmap of package-architecture

Wafer to wafer

3D Si integration

Device layer 2 Vertical interconnect Device layer 2

Silicon

Chip to chip/chip to wafer Performance

Silicon carrier Chip 1 Chip 2

TSV for interposer

3D chip stack

Substrate

TSV for 3D chip stacking

Chip to package Caramic and organic packages Evolutionary improvements Printed circuit card 2000

2005

2010 Time

FIGURE 2-5 IBM’s generic 3D IC packaging roadmap.

2015

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Chapter Two 3D Stackeddie MCP Memory CPU

Substrateembeddeddie MCP 2D Planar MCP

BW > 1 TB/s

CPU Memory

BW = 200 GB/s–1 TB/s CPU

Memory

Off-pkg BW = 100–200 GB/s CPU

Memory

BW < 100 GB/s

FIGURE 2-6 Intel’s proposed roadmap of package-architecture transitions to address the memory-bandwidth challenge.

transitions to address the memory-bandwidth challenge.14 It can be seen that 3D stacked-die multiple-chip packaging is needed to meet the performance requirements and that microbumps are used to connect the memory chip to the central processor unit (CPU).

2.2.3

Low-Cost Solder Microbumps for 3D IC SiP

The material used for connecting high-pin-count, small-pad, and finepitch chips can be either high-cost metal bumps (e.g., copper and gold) or low-cost solder bumps (e.g., tin). In this section, only low-cost solder microbumps will be discussed. Figure 2-7 is a schematic of the 3D stacking of a memory chip and an Si carrier chip (could be the CPU) with TSV.21 There are more than 4000 solder microbumps between them, and their distribution is shown in Fig. 2-8. The functional bumps are concentrated in a

Si chip Solder microbumps

TSV

UBM pad 25 Si carrier μm

Ordinary solder bumps

FIGURE 2-7 Schematic of the 3D stacking of a memory chip and an Si carrier (could be a CPU) at 25 μm pitch.

Advanced MEMS Packaging

All the others are dummy bumps/UBM pads for stability assembly

Bumps/UBM pads for interconnection

FIGURE 2-8 Distribution of solder microbumps/under-bump-metallurgy (UBM) pads on an Si chip/Si carrier (not in scale).

very narrow strip with very fine pitches (≤25 μm) and small pads (≤15 μm), and the dummy bumps (to provide support during assembly and to absorb the stresses and strains of thermal-expansion mismatch between the Si chip and the copper-filled TSV chip) are around the edges. Figure 2-9 shows a schematic of the cross section of a solder microbump on an Si chip. It can be seen that it consists of the metal pad and a Ti (or Ta) adhesion layer, Cu seed layer, plated Cu layer, plated Sn layer, and passivation layer. Figure 2-10 shows a schematic of the cross section of an electroless Ni and immersion Au (ENIG) under-bump metallurgy (UBM) pad. It can be seen that it consists of the Al pad, Ni layer, Au layer, and two passivation layers.

a. Bump height

b

b. Bump width c. Ti adhesion

g

a

d. Cu seed layer e. Cu f. Sn g. Passivation: SiO2

f e d

c Metal pad Si chip

FIGURE 2-9 Schematic of the cross section of a solder microbump on an Si chip.

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54

Chapter Two FIGURE 2-10 Schematic of the cross section of the electroless Ni and immersion Au (ENIG) UBM pad.

d

e

c b a f Si carrier

a. Passivation 1 (SiO2) b. Passivation 2 (SiO2) c. Al pad (daisy chain) d. Electroless Ni e. Immersion Au f. Al pad opening

Figure 2-11 shows scanning electron microscope (SEM) images of the electroplated Cu-Sn solder microbumps on an Si chip, and Fig. 2-12 shows the Cu-Sn solder microbumps on an Si chip after reflow at 265°C. Figure 2-13 shows a focused-ion-beam (FIB) image of the Cu-Sn solder microbumps on an Si chip. It can be seen that nice and smooth Cu-Sn solder microbumps on a 25-μm pitch and 15-μm pad have been achieved.

Plated Sn at 25-μm pitch

10 μm

FIGURE 2-11 SEM image of the electroplated Cu-Sn solder microbumps on an Si chip.

Advanced MEMS Packaging Reflowed Sn at 25-μm pitch

10 μm

FIGURE 2-12 SEM image of the Cu-Sn solder microbumps on an Si chip after reflow at 265°C.

Cu6Sn3

Cu3Sn

Sn

Cu

FIGURE 2-13 FIB image of the Cu-Sn solder microbumps on an Si chip.

55

56

Chapter Two Electroless Ni & lmmersion Au at 25-μm pitch

FIGURE 2-14 SEM image of ENIG UBM on an Si carrier.

Just as with ordinary solder bumps, there are two layers of intermetallic compounds (IMCs), the Cu3Sn and Cu6Sn5. Figures 2-14 and 2-15 show, respectively, SEM and FIB images of the ENIG UBM on an Si carrier. It can be seen that the Ni layer is about 4 μm thick and that there is no cracking around the edges of

FIGURE 2-15 FIB image of ENIG UBM on an Si carrier.

4 μm

Au Ni

Passivation

Advanced MEMS Packaging

Chip with solder bumps Cu Sn Ni

Chip with UBMs μm

μm

FIGURE 2-16 SEM images of the assembly cross section of an Si chip and Si carrier (15 μm pitch and 8 µm pad).

the passivations. A similar UBM has been made for a 15-μm pitch and 8-μm pad. In this case, the Ni layer is about 2 μm thick.22 Figure 2-16 shows the assembly of an Si chip and Si carrier with 15-μm pitch and 8-μm pad Cu-Sn solder microbumps. It can be seen from the cross section that the micro solder joints between these chips can be assembled properly and that the standoff is about 12 μm, which is preferred for 3D IC stacking and SiP. The effective thermal expansion coefficient of the Cu-filled TSV Si carrier (~10 × 10–6/°C) is larger than that (~2.5 × 10–6/°C) of the Si chip, and therefore, underfill may be necessary to ensure the reliability of the micro solder joint. Figure 2-17 shows an optical photograph of

Si chip

Si chip Underfill

Underfill in the assembly gap Si carrier Si carrier Si chip Si chip Underfill and microbumps in the assembly gap

Underfill

FIGURE 2-17 Optical photograph of a cross section of the underfill between an Si chip and Si carrier.

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Chapter Two a cross section of underfill between these two chips. For results of shearing and thermal cycling tests for these micro solder joint assemblies, please see refs. 21 and 22, which demonstrate that these solder microbumps are adequate for most operating conditions.

2.2.4 Thermal Management of 3D IC SiP with TSV As mentioned earlier, thermal management is one of the critical issues of 3D IC integration. Thus low-cost and effective thermal management design guidelines and solutions are desperately needed for widespread use of 3D IC integration. Based on the theory of heat transfer, this section examines the thermal performance of 3D stacking of up to eight copper-filled TSV chips. The results are plotted in useful design charts for engineering practice convenience, and design guidelines are also provided.20 In order to have a miniature product with low-profit and smallform-factor components, the chip thickness in a 3D stacked component must be very thin (e.g., 50 μm or less). Unfortunately, chip temperature and the hot-spot temperature in a chip increase with reductions in chip thickness, which poses significant thermal management challenges. This section also presents heat-transfer analysis of a (5 × 5 mm) chip with different thicknesses (from 10 to 200 μm) subjected to various heat sources. In addition, the thermal coupling effects of a (5 × 5 × 0.05 mm) chip subjected to heat sources at various locations are presented. Again, useful design charts and design guidelines relating the important parameters are provided. Even with the most effective software and advanced high-speed hardware, it is impossible to model all the TSVs in a 3D IC integration SiP. Therefore, this section develops empirical equations for the equivalent thermal conductivity of a copper-filled TSV chip with various TSV diameters, pitches, and aspect ratios through detailed 3D heat-transfer Computational Fluid Dynamic (CFD) analysis. These equations then are used (for each TSV chip as a lumped block) to perform all the simulations reported herein.

Equivalent Thermal Conductive of TSV Chips Figure 2-18 is a schematic of a 3D IC integration of eight copperfilled TSV chips. The top-layer chip does not (and does not need to) have a TSV. These chips are connected through microbumps, and the bottom TSV chip is also connected to the organic printed circuit board (PCB) by ordinary flip-chip solder bumps. Owing to the large thermal expansion mismatch between the silicon chip and the organic PCB, underfill is needed to cement the bottom chip (and the stack) to the PCB so that the solder joints are reliable. Underfill may not be necessary between all the TSV chips. As mentioned earlier, this section determines the equivalent thermal conductivity of the copper-filled TSV chips through detailed 3D

Advanced MEMS Packaging Copper-filled TSV (many)

TSV chip

TSV

z

y x

Micro bump

Chip q T

Solder bump

Adiabatic

Δz PCB

Underfill

Adiabatic

Δz q = –keq,z dT = k eq,z ΔT ⇒ k eq,z = q Δz dz ΔT ΔT Δx q = –keq,x dT = k eq,x ⇒ k eq,x = q dx Δx ΔT keq,y = keq,x

Isotherm (T1 = 25°C)

T q Adiabatic

Δx

FIGURE 2-18 Schematic of a 3D IC integration of eight copper-filled TSV chips along with the equivalent thermal conductive model and boundary conditions.

CFD analysis. One of the TSV chip is shown schematically in the upper right-hand corner of Fig. 2-18. It can be seen that unlike the thermal conductivity of an ordinary silicon chip [150 W/(m · °C)], which is isotropic, the thermal conductivity of a copper-filled TSV silicon chip is anisotropic; that is, the thermal conductivity in the xy-planar directions (keq,x = keq,y) is not equal to that in z-normal direction (keq,z). [The thermal conductivity of copper is 390 W/(m · °C).] The approaches for extracting keq,x = keq,y and keq,z are shown, respectively, in the center and bottom right-hand side of Fig. 2-18. First, construct the geometry of the copper-filled TSV chip with various diameters, pitches, and aspect ratios. Then input the thermal material properties [the thermal conductivity of silicon is 150 W/(m · °C) and that of copper is 390 W/(m · °C)]. Finally, apply the kinetic and kinematic boundary conditions, and calculate the temperature distributions. The equivalent thermal conductivity can be obtained with the equations shown in the lower left-hand corner of Fig. 2-18. For example, to extract the equivalent thermal conductivity in the z direction, the geometry of the TSV chip is constructed, then a uniform heat flux q is imposed on the top surface of the TSV chip, and the bottom surface is set as an isotherm boundary (i.e., 25°C), whereas the four surrounding boundaries are set as adiabatic boundaries. By using the Flowtherm software, the average temperature on the top surface of the TSV chip can be calculated, and consequently, keq,z can be obtained using the first equation in the figure.

59

Chapter Two 260 Equivalent conductivity, W/(m·K)

250

Pitch = 0.2 mm, Keq,z Pitch = 0.3 mm, Keq,z Pitch = 0.5 mm, Keq,z

240

Pitch = 0.25 mm, Keq,z Pitch = 0.4 mm, Keq,z Pitch = 0.6 mm, Keq,z

230 Keq, z

220 Pitch: 0.3 mm – correlation

210

D1

D1

200 0.3 mm

190

P

180

D2

D2

170 160 150 140 2

4

6

8

10

Aspect ratio, A keq,z = 150 + 188D 2P –2; D = (D1 + D2)/2; A = thickness/D

FIGURE 2-19 The equivalent thermal conductivity (in the vertical direction) for a copper-filled TSV chip with various diameters, pitches, and aspect ratios.

Figures 2-19 and 2-20, respectively, show the equivalent thermal conductivity for keq,z and keq,x = keq,y of a copper-filled TSV chip with various diameters, pitches, and aspect ratios. It can be seen that (1) the equivalent thermal conductivity in all directions of the TSV chip is 260 250 Equivalent conductivity, W/(m·K)

60

Pitch = 0.2 mm, Keq,x,y Pitch = 0.3 mm, Keq,x,y Pitch = 0.5 mm, Keq,x,y

240

Pitch = 0.25 mm, Keq,x,y Pitch = 0.4 mm, Keq,x,y Pitch = 0.6 mm, Keq,x,y

230 220 210 200

Pitch: 0.30 mm – correlation

190

Keq,x,y

D1 0.3 mm

D1 P

180

D2

170

D2

160 150 140 2

4

6 Aspect ratio, A

8

10

keq,x = keq,y = 150 + 105D 2P –2; D = (D1 + D2)/2; A = thickness/D

FIGURE 2-20 The equivalent thermal conductivity (in the horizontal direction) for a copper-filled TSV chip with various diameters, pitches, and aspect ratios.

Advanced MEMS Packaging larger than that of a pure silicon chip, (2) the equivalent thermal conductivity in all directions is larger for smaller pitches of the TSV chip, and (3) the equivalent thermal conductivity in all directions is larger for larger diameters of the TSV chip. For engineering convenience, the results in Figs. 2-19 and 2-20 have been curve-fitted into the following empirical equations for equivalent thermal conductivity: keq,z = 150 + 188D2P–2 keq,x = keq,y = 150 + 105D2P–2 where P is the pitch, D = (D1 + D2)/2 is the diameter, and D1 and D2 are the diameters of a tapered TSV chip. The accuracy of these equations has been demonstrated by showing the correlation between the empirical equations (for the case of P = 0.3 mm) with the detailed 3D CFD analyses, as shown in Figs. 2-19 and 2-20. Consequently, these empirical equations will be used for TSV chips as a lumped block without any vias for analysis of the 3D SiP. Table 2-1 shows the material properties for the simulations.

Thermal Performance of 3D Stacked TSV Chips with a Uniform Heat Source Figure 2-21 shows the maximum junction temperature of a stackedchip (varying with the number of the chips) package. In these simulations, all the chips have the same size (5 × 5 × 0.05 mm), and there are 225 (15 × 15) copper-filled TSVs with a 0.2-mm pitch on each chip. The power dissipated by each chip is 0.2 W, and it is assumed that the power is uniformly distributed on each chip. The ambient temperature is 25°C. It can be seen from the figure that the maximum junction temperature increases linearly with the number of the chips stacked. In addition, it can be seen that if the maximum allowable junction temperature is 85°C, then the maximum number of chips that can be stacked together is seven under the present conditions. Figure 2-22 shows the maximum junction temperature at each layer of the TSV chip stack. It can be seen that the maximum junction

Chip

TSV

Bumps

Underfill

PCB

Material

Si (TSV)

Cu

SnAg

Polymer

FR4

K [W/(m · °C)]

Empirical equation

390

57

0.5

// 0.8 ⊥ 0.3

Dimension (mm)

5×5

Ø = 0.05

Ø = 0.20 Height = 0.15

5×5× 0.15

76 × 114 × 1.6

Power (W)

0.2 W

NA

NA

NA

NA

TABLE 2-1

Material Properties and Dimensions of 3D IC Integration

61

62

Chapter Two

Max. junction temperature, Tj (°C)

95 85

Tj = 85°C

Uniform 75 heat source over the 65 whole TSV chip 55

TSV chip

45

Chip thickness = 50 μm Chip power = 0.2 W/chip Heat source area = 5 × 5 mm

35 25

0

2

4

6

8

10

Number of stacked TSV chips

Max. Temperature, °C

FIGURE 2-21 Maximum junction temperature of the eight stacked chips.

90

85

Chip thickness = 50 μm Chip power = 0.2 W/chip Heat source area = 5 × 5 mm

0

2

4

6

8

Layer of TSV chip (from the bottom)

FIGURE 2-22 Maximum junction temperature at each layer of the TSV chip stack.

temperature difference between each layer of the stack is negligible. This means that the temperature distribution for the different layer of chips is uniform because we assumed that the power dissipation is uniformly distributed in each chip. Figure 2-23 shows the variation in thermal resistance of the SiP with the number of the TSV chips stacked. The materials, geometry, boundary conditions, and assumptions are the same as those in Fig. 2-21. It can be seen that the thermal resistance of the stacked SiP decreases as the number of chip in the stack increases.

Advanced MEMS Packaging

Thermal resistance, Rja (°C/W)

45

Uniform heat source over the whole TSV chip

44 43 42 41

TSV chip

40 39 38

Chip thickness = 50 μm Chip power = 0.2 W/chip Heat source area = 5 × 5 mm

37 46 35

0

2

4 6 Number of stacked TSV chips

8

10

FIGURE 2-23 Variation in thermal resistance of the SiP with the number of TSV stacked chips.

Thermal Performance of 3D Stacked TSV Chips with a Nonuniform Heat Source The results presented in Figures 2-21, 2-22, and 2-23 are based on the assumption that the power is dissipated uniformly over the whole chip. However, in most applications, the power dissipated by each chip is basically nonuniform, and as such, it will induce quite different thermal behaviors of the 3D IC SiP with TSV chips. In addition, it is well known that ordinary silicon chips normally have large parallel conduction of heat (parallel to the chip surface) owing to the large thermal conductivity of the Si material. However, for 3D IC chip stacking, in order to have a low profile, the chip thickness of each layer of the 3D SiP must be ground down to 50 μm and less. Thus the parallel spreading effect is suppressed by the very thin chip, and the hot spot will be very intense. Compounding this with the nonuniform heat source, the hot spot becomes a challenge in 3D IC integration SiP. Figures 2-24, 2-25, and 2-26 show the thermal performance of a 3D integration of two copper-filled TSV chips stacking in an SiP, where a single copper-filled TSV chip is also included. All the chips are 5 × 5 mm, and their thicknesses vary from 10 to 200 μm. Each chip’s center is subjected to a distinct heat source (0.2 W) in a tiny area (0.2 × 02 mm). It can be seen from Figs. 2-24 and 2-25 that (for both one- and two-chip stacks) (1) for a nonuniform heat source, the effect of chip thickness on the thermal performance of 3D IC integrations is very important, (2) this thickness effect is even more significant in the application range (≤50 μm) of 3D IC integrations, and (3) the maximum junction temperature and thermal resistance decrease as chip thickness increases.

63

Chapter Two

Max. Junction temperature Tj (°C)

95 85 75

Two TSV chips

Heat source

65 One TSV chip

55

Chip

45 Chip power = 0.2 W/chip Chip heat source area = 0.2 × 0.2 mm

35 25

0

50

100 TSV chip thickness, μm

150

200

FIGURE 2-24 Maximum junction temperature of a 3D integration of two Cu-filled TSV chips.

250 Thermal resistance, Rja (°C/W)

64

200 Two TSV chips

150

Heat source One TSV chip

100

Chip

50

0

Chip power = 0.2 W/chip Chip heat source area = 0.2 × 0.2 mm 0

50

100 TSV chip thickness, μm

150

200

FIGURE 2-25 Thermal resistance of a 3D integration of two Cu-filled TSV chips.

Figure 2-26 shows the temperature maps on the chip for various chip thicknesses. It can be seen that the heat on the chip surface is well dissipated for typical chip thicknesses of 100 to 200 μm subjected to a generated power of 0.2 W. For the 200-μm-thick chip, the temperature distribution is almost uniform and equal to 35°C. However, the hot-spot temperature on the chip increases to 69°C (0.2-W power) if the chip thickness is reduced to 10 μm, and the hot-spot area is clearly shown.

Advanced MEMS Packaging t = 10 μm

t = 25 μm

t = 100 μm

t = 50 μm

t = 200 μm Temperature (°C) 68.9

49.5

Chip power: 0.2 W/chip Chip heat source area: 0.2 × 0.2 mm

30

FIGURE 2-26 Temperature maps on the chip for various chip thicknesses (hot spots).

In addition to one heat source per chip (5 × 5 mm), Figs. 2-27 and 2-28 show the effect of two heat sources at a distance apart (gap) on the thermal performance of 3D IC integrations of copper-filled TSV chips. There are two distinct heat sources (each with 0.1 W and on 0.2 × 0.2 mm area) on each chip (5 × 5 × 0.05 mm). It can be seen from the

Max. junction temperature, Tj (°C)

60

a

Chip power = 0.2 W/chip b

55

50

Heat source area = 0.2 × 0.2 mm

Two TSV chips

45 One TSV chip

40

35

0

0.2

0.4 0.6 Gap between heat sources, b/a

0.8

FIGURE 2-27 Maximum junction temperature of a 3D integration of two Cu-filled TSV chips subjected to two distinct heat sources.

1

65

Chapter Two 110 Thermal resistance, Rja (°C/W)

66

a

100

b

Chip power = 0.2 W/chip Heat source area = 0.2 × 0.2 mm

90 80

One TSV chip

70 Two TSV chips

60 50

0

0.2

0.4

0.6

0.8

1

Gap between heat sources, b/a

FIGURE 2-28 Thermal resistance of a 3D integration of two Cu-filled TSV chips subjected to two distinct heat sources.

figures that (1) the larger the gap (b/a ≤ 0.7) between the two heat sources, the better is the thermal performance (i.e., lower maximum junction temperature and thermal resistance), and (2) when the gap between the two heat sources is larger than 0.7 (i.e., the heat sources are too close to the edge of the chip), the thermal performance is weaker. This is due to suppressible spreading effects near the edges of the chips. In addition to the case of overlapping heat sources discussed in the preceding paragraph, finally, Figs. 2-29 and 2-30 show the orientation effect (staggered heat sources) of two stacked chips, each with two heat sources at a certain distance apart, on the thermal performance of a 3D SiP. It can be seen that (1) similar to case of overlapping heat sources, the larger the gap (b/a ≤ 0.7) between those two pairs of staggered heat sources, the lower are the maximum junction temperature and thermal resistance, (2) when the gap between the two pairs of staggered heat sources is larger than 0.7 (i.e., the heat sources are too close to the edge of the chip), the thermal performance is weaker, and (3) the maximum junction temperature and thermal resistance of the 3D SiP with two TSV chips subjected to two pairs of staggered heat sources are lower than those with two pairs of overlapping heat sources. This is so because the staggered heat sources avoid the superimposition of heat sources and thus lead to better thermal performance. This result is very useful for the design and layout 3D SiP because it permits relocation of the heat sources and/or rotation of the chip.

Advanced MEMS Packaging

Max. Junction temperature, Tj (°C)

55

a

Chip power = 0.2 W/chip Heat source area = 0.2 × 0.2 mm

a

54 b

53

b

52 51

Overlapped sources

50

2 TSV chips with over lapped heat sources

Staggered sources

49 48

2 TSV chips with staggered heat sources

47 46 45

0

0.2

0.4 0.6 Gap between heat sources, b/a

0.8

1

FIGURE 2-29 Maximum junction temperature of a 3D integration of two Cu-filled TSV chips subjected to two distinct staggered heat sources.

75

Thermal resistance, Rja (°C/W)

a b

70

65

Chip power = 0.2 W/chip Heat source area = 0.2 × 0.2 mm

a b

Overlapped sources

2 TSV chips with overlapped heat sources

Staggered sources

60 2 TSV chips with staggered heat sources

55

50

0

0.2

0.4

0.6

0.8

1

Gap between heat sources, b/a

FIGURE 2-30 Thermal resistance of a 3D integration of two Cu-filled TSV chips subjected to two distinct staggered heat sources.

2.3 Advanced MEMS Packaging Advanced MEMS packaging usually involves at least three wafers, namely, the MEMS device wafer, the ASIC wafer, and the cavity-cap wafer. This section examines the design and processing of 10 different configurations of 3D MEMS packaging.53 These packages are supposed to yield very low-cost, high-performance packaging with a small footprint.

67

68

Chapter Two Solder bump with TSV substrate

MEMS wafer

Note: Cases 1 to 6 should have the cap without TSV

Solder bump flip-chip without TSV Wire bond

ASIC wafer

5

6

2

3

4 1

With TSV

8

9

7

Without TSV

Note: Cases 7 to 9 should have the ASIC without TSV

Cap wafer TSV in cap

FIGURE 2-31 Nine different designs of 3D MEMS packaging for the MEMS wafer, ASIC wafer, and cavity-cap wafer.

2.3.1

3D MEMS WLP: Designs and Materials

Figure 2-31 shows nine different combinations (designs) of 3D MEMS packaging from the MEMS wafer (with either wire-bonding pads, solder-bumped TSV substrate, or solder-bumped flip-chip without TSV), the ASIC wafer (with or without TSV), and the cavity-cap wafer (with or without TSV).53 Case 1: The MEMS device is die attached and then wire bonded on the ASIC chip or wafer. The cavity-cap chip/wafer is attached to the ASIC chip/wafer with a sealing ring, as shown in Fig. 2-32. Cavity-cap

Wire bondIng

Sealing ring

MEMS device

ASIC chip Signal lines go through beneath sealing ring to wire-bonding pad on the chip periphery

Circuitry

MEMS chip (substrate)

Bonding pad on a substrate or PCB

FIGURE 2-32 All wire-bonding 3D MEMS packaging with lateral electrical feedthrough.

Advanced MEMS Packaging MEMS device and substrate with TSV

Cavity-cap Sealing ring

Wire bonding

ASIC chip Signal lines go through beneath sealing ring to wire-bonding pad on the chip periphery

Circuitry

Tiny solder bumps

Bonding pad on a substrate or PCB

FIGURE 2-33 Solder-bumped MEMS device with TSV substrate on an ASIC chip with lateral electrical feed-through.

The signal lines go through beneath the sealing ring to the wirebonding pad on the ASIC chip periphery. Another set of wirebonding pads connects the MEMS/ASIC 3D stack to either a substrate in a package or on a PCB. Case 2: The micro-solder-bumped MEMS device with a TSV substrate is first attached to the ASIC, as shown in Fig. 2-33. The rest is the same as in case 1. Case 3: The solder-bumped flip-chip MEMS device is first attached on the ASIC, as shown in Fig. 2-34. The rest is the same as in case 1. Case 4: The MEMS device is die attached and wire bonded on the ASIC chip with TSV and ordinary solder bumps, as shown in Fig. 2-35. A cavity cap is attached on the ASIC with a sealing ring. The MEMS/ASIC 3D stack is then attached (solder reflowed) to a substrate in a package or on a PCB.

MEMS device and substrate with solder bumps Cavity-cap Sealing ring Wire bonding

ASIC chip Signal lines go through beneath sealing ring to wire-bonding pad on the chip periphery

Circuitry Solder bumps

Bonding pad on a substrate or PCB

FIGURE 2-34 Solder-bumped flip-chip MEMS device on an ASIC chip with lateral electrical feed-through.

69

70

Chapter Two Wire bonding Sealing ring

Cavity-cap

MEMS device

ASIC chip

Ordinary solder bumps MEMS chip (substrate)

Through-silicon via (TSV)

FIGURE 2.35 MEMS device wire bonded on an ASIC chip with vertical electrical feed-through TSV.

MEMS substrate with TSV Cavity-cap Sealing ring

MEMS device

ASIC chip

Ordinary solder bumps Tiny solder bumps

Through-silicon via (TSV)

FIGURE 2.36 TSV MEMS device solder bonded on an ASIC chip with vertical electrical feed-through TSV.

Case 5: The micro-solder-bumped MEMS device with a TSV substrate is first attached to the ASIC chip with TSV and ordinary solder bumps, as shown in Fig. 2-36. The rest is the same as in case 4. Case 6: The solder-bumped MEMS device is first attached to the TSV ASIC with ordinary solder bumps, as shown in Fig. 2-37. The rest is the same as in case 5. Case 7: The MEMS device is die attached and then wire bonded on the ASIC. The cavity cap with TSV and ordinary solder bumps is attached to the ASIC with a sealing ring, as shown in Fig. 2-38. Then the whole 3D carrier is attached (solder reflowed) to a substrate in a package or on a PCB. Case 8: The micro-solder-bumped MEMS device with TSV substrate is first attached to the ASIC as shown in Fig. 2-39. The rest is the same as in case 7.

Advanced MEMS Packaging MEMS substrate with solder bumps Cavity-cap Solder bumps

Sealing ring

ASIC chip

Ordinary solder bumps

Through-silicon via (TSV)

MEMS device

FIGURE 2-37 Solder-bumped MEMS device flip-chip on an ASIC chip with vertical electrical feed-through TSV. Ordinary solder bumps Cavity-cap Through-silicon via (TSV)

Wire bonding Sealing ring

MEMS device

ASIC chip MEMS chip (substrate)

FIGURE 2-38 MEMS device wire bonded on an ASIC chip (vertical electrical feed-through TSV is in the package cap). Ordinary solder bumps Cavity-cap Sealing ring Through-silicon via (TSV)

MEMS device

ASIC chip MEMS substrate with TSV

Tiny solder bumps

FIGURE 2-39 TSV MEMS device solder bonded on an ASIC chip (vertical electrical feed-through TSV is in the package cap).

Case 9: The solder-bumped MEMS device is first attached to the ASIC as shown in Fig. 2-40. The rest is the same as in case 7. Case 10: The MEMS device is attached to the ordinary solderbumped TSV ASIC with a sealing ring, as shown in Fig. 2-41. Then the whole 3D stack is attached (solder reflowed) to a substrate in a package or on a PCB.

71

72

Chapter Two Ordinary solder bumps Cavity-cap Sealing ring Through-silicon via (TSV) ASIC chip MEMS device

Solder bumps

MEMS substrate with solder bumps

FIGURE 2-40 Solder-bumped MEMS device flip-chip on an ASIC chip (vertical electrical feed-through TSV is in the package cap). MEMS substrate

Sealing ring

ASIC chip

Ordinary solder bumps MEMS device

Through-silicon via (TSV)

FIGURE 2-41 MEMS device is bonded (with a sealing ring) on an ASIC chip with vertical electrical feed-through TSV.

2.3.2

3D MEMS WLP: Processes

There are many different processes to assemble these 10 MEMS SiPs. For example, the assembly process shown in Fig. 2-42 can be applied to cases 1 through 3; Fig. 2-43, to cases 4 to 6; and Fig. 2-44, to cases 7 to 9.53 Case 10 will be discussed later. As mentioned earlier, the MEMS wafer can be fabricated either with wire-bonding pads or TSV and solder bumps or a solder-bumped flip-chip, as shown in Figs. 2-42 through 2-44. These are followed by releasing (etching) the MEMS wafer and singulation. For 3D MEMS packaging with lateral electrical feed-through (cases 1, 2, and 3), there is no TSV in both the ASIC and cap wafers (see Fig. 2-42). In these cases, cavities should be formed in the cap wafer by either KOH etching or use of a laser. Then one performs the bonding of the MEMS device (chip) to the ASIC wafer (C2W). This

Advanced MEMS Packaging MEMS wafer

MEMS with wire-bonding pad

MEMS with TSV

MEMS with flip-chip

MEMS devices released

TSV formations and wafer bumping

Wafer bumping

Singulation

MEMS devices released

MEMS devices released

ASIC wafer without TSV

Singulation

C2W wire bonding

Singulation

C2W solder bonding

C2W solder bonding

Cap wafer without TSV

ASIC wafer to cap wafer bonding Cavity formation on cap wafer without TSV

Singulation

FIGURE 2-42 Assembly process for 3D MEMS packaging with lateral electrical feedthrough. MEMS wafer

ASIC wafer

MEMS with wire-bonding pad

MEMS with TSV

MEMS devices released

TSV formations and wafer bumping

Wafer bumping

Singulation

MEMS devices released

MEMS devices released

Singulation

Singulation

C2W solder bonding

C2W solder bonding

TSV formation on ASIC wafer C2W wire bonding

Cap wafer without TSV

ASIC wafer to cap wafer bonding Wafer bumping

Cavity formation on cap wafer

Singulation

FIGURE 2-43 Assembly process for 3D MEMS packaging with vertical electrical feed-through the TSV in an ASIC chip.

73

74

Chapter Two MEMS wafer

MEMS with wire-bonding pad

MEMS with TSV

MEMS with flip-chip

MEMS devices released

TSV formations and wafer bumping

Wafer bumping

Singulation

MEMS devices released

MEMS devices released

ASIC wafer without TSV

Singulation

C2W wire bonding

C2W solder bonding

Singulation

C2W solder bonding

Cap wafer without TSV

ASIC wafer to cap wafer bonding Cavity formation on cap wafer without TSV

Singulation

FIGURE 2-44 Assembly process for 3D MEMS packaging with vertical electrical feed-through the TSV in the package cap.

will be followed by bonding of the cavity-cap wafer to the ASIC wafer (W2W). Finally, the bonded wafers are singulated into individual units, which are ready to be wire bonded on the substrate of a package or on a PCB, as shown in Fig. 2-45. For both cases, encapsulant is recommended. For 3D MEMS packaging with vertical electrical feed-through in the ASIC chip (cases 4, 5, and 6), the TSV must be fabricated on the ASIC wafer before C2W bonding, as shown in Fig. 2-43. After the W2W (cap-to-ASIC) bonding, wafer bumping should be performed on the bottom side of the ASIC wafer. After singulations, the individual units can be soldered on the substrate of either a package or a PCB, as shown in Fig. 2-46. For the PCB case, underfill is necessary for the reliability of the solder joints. For the solder-bumped flip-chipin-package case, use of underfill depends on the substrate material. If it is made of ceramic, then underfill is optional. However, if it is an organic substrate, then underfill is a must. For 3D MEMS packaging with vertical electrical feed-through in the package cap (cases 7, 8, and 9), the TSV and cavity must be fabricated on the cap wafer before W2W bonding, as shown in Fig. 2-44. After W2W bonding, wafer bumping should be performed on the bottom side of the cap wafer. The rest is the same as in cases 4 through 6, and Fig. 2-47 shows an example of the complete 3D MEMS packaging with vertical electrical feed-through in the package cap.

Advanced MEMS Packaging Cavity-cap Sealing ring

Wire bonding MEMS device

ASIC chip Signal lines go through beneath sealing ring to wire-bonding pad on the chip periphery

Circuitry MEMS chip (substrate)

MEMS/ASIC module wire-bonding on the substrate of a package which is assembled on PCB

Bonding pad on a substrate or PCB

MEMS/ASIC module wire-bonding directly on PCB

Substrate

PCB

FIGURE 2-45 Complete 3D MEMS packaging with lateral electrical feed-through (encapsulants are recommended).

MEMS substrate with TSV Cavity-cap Sealing ring

MEMS device

ASIC chip

Ordinary solder bumps Tiny solder bumps

Through-silicon via (TSV)

MEMS/ASIC module attached on the substrate of a package which is assembled on PCB

MEMS/ASIC module flipchip attached on PCB

Substrate Solder balls PCB

FIGURE 2-46 Complete 3D MEMS packaging with vertical electrical feed-through in the TSV of a ASIC chip (underfills are recommended).

75

76

Chapter Two Ordinary solder bumps Cavity-cap

Sealing ring

Through-silicon via (TSV)

ASIC chip MEMS device

Solder bumps

MEMS substrate with solder bumps

MEMS/ASIC module attached on the substrate of a package which is assembled on PCB

MEMS/ASIC module flipchip attached on PCB

Substrate Solder balls PCB

FIGURE 2-47 Complete 3D MEMS packaging with vertical electrical feed-through the TSV of the package cap (underfills are recommended).

In the food chain of electronic products, packaging is a downstream process (i.e., the packaging people cannot be or are not in a proactive position and cannot say too much), and the packaging people just package whatever is given them by the semiconductor people (i.e., our job starts from the wafers). Case 10 (see Fig. 2-41) is a very low-cost, high-performance 3D MEMS package.53 However, in order to make it, the MEMS device (chip) must be much larger (to make space for the sealing ring) than that packages in cases 1 through 9 with a cavity cap. Thus, from a semiconductor points of view, this is a very bad idea because many fewer MEMS devices can be produced on the same size MEMS wafer.

References 1. Andry, P. S., Tsang, C. K., Webb, B. C., Sprogis, E. J., Wright, S. L., Bang, B., and Manzer, D. G. “Fabrication and characterization of robust through-silicon vias for silicon-carrier applications.” IBM Journal of Research and Development 52:571–581, 2008. 2. Knickerbocker, J. U., Andry, P.S., Dang, B., Horton, R. R., Patel, C. S., Polastre, R. J., Sakuma, K., Sprogis, E. S., Tsang, C. K., Webb, B. C., and Wright, S. L. “3-D silicon integration.” In IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL, May 2008, pp. 538–543. 3. Kumagai, K., Yoneda, Y., Izumino, H., Shimojo, H., Sunohara, M., and Kurihara, T. “A silicon interposer BGA package with Cu-filled TSV and multilayer Cu-plating

Advanced MEMS Packaging

4.

5.

6. 7.

8. 9.

10.

11.

12.

13.

14. 15.

16.

17.

interconnection.” In IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL, May 2008, pp. 571–576. Sunohara, M., Tokunaga, T., Kurihara, T., and Higashi, M., “Silicon interposer with TSVs (through-silicon vias) and fine multilayer wiring.” In IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL, May 2008, pp. 847–852. Lee, H. S., Choi, Y.-S., Song, E., Choi, K., Cho, T., and Kang, S. “Power delivery network design for 3D SIP integrated over silicon interposer platform.” In IEEE Proceedings of Electronic Components and Technology Conference, Reno, NV, May 2007, pp. 1193–1198. Matsuo, M., Hayasaka, N., and Okumura, K. “Silicon interposer technology for high-density package.” In IEEE Proceedings of Electronic Components and Technology Conference, Las Vegas, NV, May 2000, pp. 1455–1459. Selvanayagam, C., Lau, J. H., Zhang, X., Seah, S., Vaidyanathan, K., and Chai, T. “Nonlinear thermal stress/strain analysis of copper filled TSV (through silicon via) and their flip-chip microbumps.” In IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL, May 2008, pp. 1073–1081. Wong, E., Minz, J., and Lim, S. K. “Effective thermal via and decoupling capacitor insertion for 3D system-on-package.” In IEEE Proceedings of Electronic Components and Technology Conference, San Siego, CA, May 2006, pp. 1795–1801. Khan, N., Rao, V., Lim, S., Ho, S., Lee, V., Zhang, X., Yang, R., Liao, E., Ranganathan, N., Chai, T., Kripesh, V., and Lau, J. H. “Development of 3D silicon module with TSV for system in packaging.” In IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL, May 27–30, 2008, pp. 550–555. Ho, S., Yoon, S., Zhou, Q., Pasad, K., Kripesh, V., and Lau, J. H. “High rf performance TSV for silicon carrier for high frequency application.” In IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL, May 27–30, 2008, pp. 1956–1952. Premachandran, C., Rangnathan, N., Mohanraj, S., Chong Ser Choong, and Iyer, M. K. “A vertical wafer level packaging using through hole filled via interconnect by lift off polymer method for MEMS and 3D stacking applications.” In Proceedings of the Fifty-first Electronic Components and Technology Conference, Lake Buena Vista, FL, 2005, pp. 1094–1098. Chen, K. S., Ayon, A. A., Zhang, X., and Spearing, S. M. “Effect of process parameters on the surface morphology and mechanical performance of silicon surfaces after deep reactive ion etching (DRIE).” J. Microelectromech. Syst. 11:264–275, 2002. Zhang, X., Chai, T., Lau, J. H., Selvanayagam, C., Biswas, K., Liu, S., Pinjala, D., Tang, G., Ong, Y., Vempati, S., Wai, E., Li, H., Liao, B., Ranganathan, N., Kripesh, V., Sun, J., Doricko, J., and Vath, C. “Development of through silicon via (TSV) interposer technology for large die (21 × 21 mm) fine-pitch Cu/low-k FCBGA package.” IEEE Proceedings of Electronic Components and Technology Conference, San Diego, CA, May 2009, pp. 305–312. Hu, G., Kalyanam, H., Krishnamoorthy, S., and Polka, L. “Package technology to address the memory bandwidth challenge for tera-scale computing.” INTEL Technol. J. 11:197–206, 2007. Knickerbocker, J. U., Andry, P. S., Buchwalter, L. P., Deutsch, A., Horton, R. R., Jenkins, K. A., Kwark,Y. H., McVicker, G., Patel, C. S., Polastre, R. J., Schuster, C., Sharma, A., Sri-Jayantha, S. M., Surovic, C. W., Tsang, C. K., Webb, B. C., Wright, S. L., McKnight, S. R., Sprogis, E. J., and Dang, B. “Development of next-gereration system-on-package (SOP) technology based on silicon carriers with fine-pitch interconnection.” IBM J. Res. Dev. 49:725–754, 2005. Tomita, Y., Morifuji, T., Ando, T., Tago, M., Kajiwara, R., Nemoto, Y., Fujii, T., Kitayama, Y., and Takahashi, K. “Advanced packaging technologies on 3D stacked LSI utilizing the micro interconnections and the layered microthin encapsulation.” In Proceedings of the Fifty-first Electronic Components and Technology Conference, Orlando, FL, 2001, pp. 353–360. Choi, W. K., Premachandran, C., Ong, C., Ling, X., Liao, E., Khairyanto, A., Chne, K., Thaw, P., and Lau, J. H. “Development of novel intermetallic joints

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Chapter Two using thin film indium based solder by low temperature bonding technology for 3D IC stacking.” IEEE Proceedings of Electronic Components and Technology Conference, San Diego, CA, May 2009, pp. 333–338. 18. Takahashi, K., Umemoto, M., Tanaka, N., Tanida, K., Nemoto, Y., Tomita, Y., Tage, M., and Bonkohara, M. “Ultra-high-density interconnection technology of three-dimensional packaging.” Microelectronics Reliability 43:1267–1279, 2003. 19. Lau, J. H., Lim, Y., Lim, T., Tang, G., Khong, C., Zhang, X., Ramana, P., Zhang, J., Tani, C., Chandrappan, J., Chai, J., Li, J., Tangdiongga, G., and Kwong, D. “Design and analysis of 3D stacked optoelectronics on optical printed circuit boards.” In Proceedings of SPIE, Photonics Packaging, Integration, and Interconnects VIII, San Jose, CA, January 19–24, 2008, Vol. 6899, pp. 07.1–07.20. 20. Lau, J. H., and Tang, G. “Thermal management of 3D IC integration with TSV (through silicon via).” IEEE Proceedings of Electronic Components and Technology Conference, San Diego, CA, May 2009, pp. 635–640. 21. Yu, A., Kumar, A., Ho, S., Wai, H., Lau, J. H., Khong, C., Lim, S., Zhang, X., Yu , D., Su, N., Chew, M., Ching, J., Tan, T., Kripesh, V., Lee, C., Huang, J., Chiang, J., Chen, S., Chiu, C., Chan, C., Chang, C., Huang, C., and Hsiao, C., “Development of fine pitch solder microbumps for 3D chip stacking.” IEEE Proceedings of Electronic Packaging and Technology Conference, Singapore, December 2008, pp. 387–392. 22. Yu, A., Lau, J. H., Ho, S., Kumar, A., Wai, Y., Yu, D., Jong, M., Kripesh, V., Pinjala, D., Kwong, D., “Study of 15-μm-pitch solder microbumps for 3D IC integration.” IEEE Proceedings of Electronic Components and Technology Conference, San Diego, CA, May 2009, pp. 6 –10. 23. Yu, A., Lau, J. H., Ho, S., Kumar, A., Yin, H., Ching, J., Kripesh, V., Pinjala, D., Chen, S., Chan, C., Chao, C., Chiu, C., Huang, M., and Chen, C., “Three dimensional interconnects with high aspect ratio TSVs and fine pitch solder microbumps.” IEEE Proceedings of Electronic Components and Technology Conference, San Diego, CA, May 2009, pp. 350–354. 24. Yu, A., Khan, N., Archit, G., Pinjala1, D., Toh, K., Kripesh1, V., Yoon, S., and Lau, J. H. “Development of silicon carriers with embedded thermal solutions for high power 3D package.” IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL, May 27–30, 2008, pp. 24–28. 25. Rebeiz, G. M. RF MEMS: Theory, Design and Technology. New York: Wiley, 2003. 26. Nguyen, C. “MEMS technology for timing and frequency control.” IEEE Trans. Ultrason. Ferroelect. Freq. Contr. 54:251–270, 2007. 27. Mohamed Gad-el-Hak. The Mems Handbook. Boca Raton, FL: CRC Press, 2002. 28. Hacker, J. B., Mihailovich, R. E., Kim, M., and DeNatale, J. F. “A Ka-band 3-bit rf MEMS true-time-delay network.” IEEE Trans. Microw. Theory Tech. 51:305–308, 2003. 29. Anagnostou, D. E., Zheng, G., Chryssomallis, M., Lyke, J., Ponchak, G., Papapolymerou, J., and Christodoulou, C. G. “Design, fabrication and measurements of a self-similar re-configurable antenna with rf-MEMS switches.” IEEE Transactions on Antennas Propagat. 54:422–432, 2006. 30. Liu, A. Q., and Zhang, X. M. “A review of MEMS external-cavity tunable lasers.” J. Micromech. Microeng. 17:R1–R13, 2007. 31. Huff, G. H., and Bernhard, J. T. “Integration of packaged rf MEMS switches with radiation pattern reconfigurable square spiral microstrip antennas.” IEEE Trans. Antennas Propagat. 54:464–469, 2006. 32. Van Caekenberghe, K., and Sarabandi, K. “A 2-bit Ka-band rf MEMS frequency tunable slot antenna.” IEEE Antennas and Wireless Propagat. Lett. 7:179–182, 2008. 33. Nguyen, C. “MEMS technology for timing and frequency control,” IEEE Trans. Ultrason. Ferroelect. Freq. Contr. 54:251–270, 2007. 34. Tan, G. L., Mihailovich, R. E., Hacker, J. B., DeNatale, J. F., and Rebeiz, G. M. “Low-loss 2- and 4-bit TTD MEMS phase shifters based on SP4T switches.” IEEE Trans. Microwave Theory Tech. 51:297–304, 2003. 35. Hacker, J. B., Mihailovich, R. E., Kim, M., and DeNatale, J. F. “A Ka-band 3-bit rf MEMS true-time-delay network.” IEEE Trans. Microwave Theory Tech. 51:305–308, 2003.

Advanced MEMS Packaging 36. Ford, J. E., Goossen, K. W. , Walker, J. A., Neilson, D. T., Tennant, D. M., Park, S. Y., and Sulhoff, J. W. “Interference-based micromechanical spectral equalizers.” IEEE J. Select. Topics Quantum Elect. 10:579–587, 2004. 37. Nordquist, C. D., Dyck, C. W., Kraus, G. M., Reines, I. C., Goldsmith, C. L., Cowan, W. D., Plut, T. A., Austin, F., Finnegan, P. S., Ballance, M. H., and Sullivan, C. T. “A dc to 10 GHz 6-BIT RF MEMS time delay circuit.” IEEE Microwave Wireless Component Lett. 16:305–307, 2006. 38. Perruisseau-Carrier, J., Fritschi, R., Crespo-Valero, P., and Skrivervik, A. K. “Modeling of periodic distributed MEMS application to the design of variable true-time-delay lines.” In IEEE Trans. Microwave Theory Tech. 54:383–392, 2006. 39. Lakshminarayanan, B., and Weller, T. M., “Design and modeling of 4-bit slowwave MEMS phase shifters.” IEEE Trans. Microwave Theory Tech. 54:120–127, 2006. 40. Lakshminarayanan, B., and Weller, T. M. “Optimization and implementation of impedance-matched true-time-delay phase shifters on quartz substrate.” IEEE Trans. Microwave Theory Tech. 55:335–342, 2007. 41. Van Caekenberghe, K., and Vaha-Heikkila, T. “An analog rf MEMS slotline true-time-delay phase shifter.” IEEE Trans. Microwave Theory Tech. 56: 2008. 42. Maciel, J. J., Slocum, J. F., Smith, J. K., and Turtle, J. “MEMS electronically steerable antennas for fire control radars.” IEEE Aerosp. Electron. Syst. Mgnt., November 2007, pp. 17–20. 43. Pranonsatit, S., Holmes, A. S., Robertson, I. D., and Lucyszyn, S. “Single-pole eight-throw rf MEMS rotary switch.” IEEE/ASME J. Microelectromech. Syst. 15:1735–1744, 2006. 44. Lin, L. Y., and Goldstein, E. L. “Opportunities and challenges for MEMS in lightwave communications.” IEEE J. Select. Topics Quantum Electron. 8:163–172, 2002. 45. Vaha-Heikkila, T., Van Caekenberghe, K., Varis, J., Tuovinen, J., and Rebeiz, G. M. “Rf MEMS impedance tuners for 6–24 GHz applications.” Wiley Int. J. RF Microwave Computer-Aided Engineering 17:265–278, 2007. 46. Schoebel, J., Buck, T., Reimann, M., Ulm, M., Schneider, M., Jourdain, A., Carchon, G. J., and Tilmans, H. A. C. “Design considerations and technology assessment of phased array antenna systems with rf MEMS for automotive radar applications.” IEEE Trans. Microwave Theory Tech. 53:1968–1975, 2005. 47. Wu, M. C., Solgaard, O., and Ford, J. E. “Optical MEMS for lightwave communication.” J. Ligtwave Technol. 24:4433–4454, 2006. 48. Mailloux, R. J. Phased Array Antenna Handbook. London: Artech House, 2005. 49. Hoffmann, M., and Voges, E. “Bulk silicon micromachining for MEMS in optical communication systems.” J. Micromech. Microeng. 12:349–360, 2002. 50. Jung, C., Lee, M., Li, G. P., and Flaviis, F. D. “Reconfigurable scan-beam singlearm spiral antenna integrated with rf MEMS switches.” IEEE Trans. Antennas Propagat. 54:455–463, 2006. 51. Premachandran, C. S., Chew, M., Choi, W., Khairyanto, A., Chen, K., Singh, J., Wang, S., Xu, Y., Chen, N., Sheppard, C., Olivo, M., and Lau, J. H. “Influence of optical probe packaging on a 3D MEMS scanning micro mirror for optical coherence tomography (OCT) applications.” In IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL, May 27–30, 2008, pp. 829–833. 52. Premachandran, C. S., Lau, J. H., Ling, X., Khairyanto, A., Chen, K., and Myo Ei Pa Pa. “A novel, wafer-level stacking method for low-chip yield and non-uniform, chip-size wafers for MEMS and 3D SiP applications. In IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL, May 27–30, 2008, pp. 314–318. 53. Lau, J. H. “3D MEMS packaging.” In IMAPS Proceedings, San Jose, CA, November 2009. 54. Chen, K., Premachandran, C., Choi, K., Ong, C., Ling, X., Ratmin, A., Pa, M., and Lau, J. H. “C2W low temperature bonding method for MEMS applictions.” In IEEE Proceedings of Electronics Packaging Technology Conference, Singapore, December 2008, pp. 1–7.

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CHAPTER

3

Enabling Technologies for Advanced MEMS Packaging 3.1 Introduction As discussed in previous chapters, through-silicon vias (TSVs); wafer thinning; thin-wafer strength measurements; thin-wafer handling; chip-to-chip (C2C), chip-to-wafer (C2W), and wafer-to-wafer (W2W) bonding; and microelectromechanical systems (MEMS) wafer dicing are key enabling technologies for advanced MEMS packaging. This chapter presents TSVs, piezoresistive stress sensors, wafer thinning and thin-wafer handling, low temperature bonding, and MEMS wafer dicing. In order to make and ship green MEMS products everywhere in the world, these products must be compliant with the Restriction of the Use of Certain Hazardous Substances (RoHS) directive (e.g., lead free). Thus RoHS requirements, such as the fact that MEMS packaging must be lead-free and their lead-free solder joints must be reliable, will be discussed briefly.

3.2 TSVs for MEMS Packaging For three-dimensional (3D) MEMS packaging, TSVs are the most important enabling technology. TSVs provide advanced vertical interconnects and system-in-package (SiP) solutions such as C2C, C2W, and W2W stacking; wafer-level packaging and redistribution; interposer packaging; and the shortest electrical path (vertical electrical feedthrough) between two sides of a silicon “chip.” Just as with many other new technologies, TSVs still face many critical issues. In the development of TSVs, the following must be noted and understood.1–21

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Chapter Three • TSV cost is higher than that of wire bonding. • The only TSV volume product is CMOS image sensors. • Memory (e.g., Flash, DRAM, and SRAM) have just been talked about. • High-speed logic (e.g., processors and FPGAs) will come even later. • High-volume production tools are lacking and/or expensive. • TSV design guidelines are not commonly available. • TSV design software is lacking. • TSV technology usually requires redistribution layers (RDL). • TSV technology usually requires microbumps. • Test methods and software for TSVs are lacking. • Copper filling helps on thermal problems but increases thermal coefficient of expansion (TCE). • Copper filling takes a long time (low throughputs). • TSV wafer yields are high (>99.8 percent) owing to the large number of vias. • TSV wafer warpage is a problem owing to TCE mismatch. • Thin-wafer handling is necessary during all processes. • TSVs with high aspect ratios are difficult to make. • TSV inspection methodology is lacking. • TSV expertise is lacking. • TSV infrastructure is lacking. • TSV standards are lacking. Over the past few years, some of these critical issues have been studied by a number of experts. Their results have already been disclosed in various journals or, more incidentally, in the proceedings of a number of conferences, symposia, and workshops whose primary emphases are electrical packaging and interconnection.1–21 Consequently, there is no single source of information devoted to the state of the art of TSV technology. This chapter discusses only the five key TSV process steps, and they are demonstrated through the vias-first process.

3.2.1 Via Formation The vias in a silicon wafer can be formed either by etching (wet process) or by laser drilling (dry process). Reviewing the literatures, more than 80 percent of vias have been formed by deep reactive-ion etching (DRIE), which is a highly anisotropic etching process. However,

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g 10000 Laser-A Laser-B Laser-C Laser-D DRIE-A DRIE-B DRIE-C DRIE-D

Cost ($/w)

1000

100

10 10

100

1000

10000

# Vias/die

FIGURE 3-1 Sematech’s cost model for fabricating TSVs by laser and by DRIE.

based on Sematech’s cost model of DRIE versus laser (Fig. 3-1), it can be seen that for lower numbers of vias per die, laser drilling may be cheaper. In addition, vias made by laser are adequate for most of applications of MEMS packaging. For example, Fig. 3-2 shows the vias of a cap wafer made by laser.20 Furthermore, the cavity of a cap

TSV

Cross section of cap wafer by laser machining

Cross section of cap wafer by laser machining

Cross section of cap wafer by KOH (potassium hydroxide) wet etch

FIGURE 3-2 MEMS cap wafer with cavity and TSV fabricated by laser and by KOH etch methods.

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Chapter Three wafer can be made by laser machining, even though KOH etch yields a better (straight) wall condition. In this chapter, however, the threestep method developed14,16,18 based on the high-rate DRIE BOSCH technology will be discussed. The silicon vias are formed in an inductive-coupled plasma (ICP)–based deep reactive ion etching system from Surface Technology Systems (STS). Although the STS ICP system is designed mainly for performing deep reactive-ion etching of silicon by a specially designed switched etch and passivation process, also known as the BOSCH process, it also can be used in reactive-ion etch mode, referred as the non-BOSCH process.18 The system consists of ICP electronics, loadlock and carousel wafer-loading unit, and a process chamber. The plasma is generated by a coil assembly that is inductively coupled at 13.56 MHz via the matching unit in a ceramic plasma chamber. This provides high-density plasma capable of achieving high etch rates with little substrate damage. Independent biasing of the platen is made available by a separate 13.56-MHz radiofrequency (RF) biasing circuit on the bottom electrode that comes with automatic power control and impedance matching. Process gas is introduced to the chamber through the upper electrode assembly. Wafers are clamped by electrostatic chuck (ESC) on the lower electrode, which is powered at 13.56 MHz. The platen temperature is kept at 10°C by using recirculating deionizer (DI) water through a chiller system. The high-aspect-ratio tapered silicon vias are formed by three independently controlled process steps: (1) the straight via formation step by the BOSCH etch process, (2) the via tapering step by a controlled isotropic etch process, and (3) the corner-rounding step by a global isotropic etch process. The first etching step is designed mainly to achieve high etch rates with the BOSCH etch process. Typically, a high-etch-rate BOSCH process tends to give a vertical to slightly reentrant profile, as shown in Fig. 3-3 (left). The gases used in the BOSCH process are mainly sulfur hexafluoride (SF6) plus oxygen (O2) in the etch phase and C4F8 in the passivation phase. The recipes are shown in Table 3-1.18 It should be noted that as a consequence of the cyclic etch/passivation process, the sidewalls become scalloped or rough. In this step, the via is etched to approximately 50 to 60 percent of the final depth. This step defines the dimension of the via at the bottom and the depth. A non-BOSCH etch process consisting of a reactive-ion etching (RIE) process is used to produce the required tapered-sidewall profile. This is basically a controlled isotropic etch process that uses SF6 plus O2 plus Ar (argon) etch chemistry (see Table 3-1). The oxygen used helps in sidewall passivation and also controls excessive lateral etch rate. A proper balance between SF6 and O2 provides the desired taper angle to the via structure. As a consequence of this process, a sharp curvature is formed at the top of the via, as shown in Fig. 3-3 (center). At the end of step 1 (BOSCH process) and step 2 (non-BOSCH process),

108.1 µm

62.2 µm

137.82 µm 91.48 µm

96.5 17.05 µm

210µm

57.3 µm

After step 1 (BOSCH)

222µm

55.3 µm

220.45 µm

After step 2 (RIE)

55.11 µm

After step 3 (isotropic)

FIGURE 3-3 Step 1 shows the results achieved after 50-μm-diameter vias are etched to a depth in the range of 200 to 220 μm. Step 2 shows the evolution of a tapered profile after etch by a controlled-isotropic etch process and step 3 shows the final tapered via profile after the top corner is rounder by a global isotropic etch process.

Step 1: Straight (BOSCH) etch process

Etch cycle: APC: 77% (26 mt); 130 sccm SF6; 13 sccm O2; 600-W coil power; 20-W platen power; 6 seconds Passivation cycle: APC: 77% (17 mt); 85 sccm C4F8; 600-W coil; 5 seconds Platen temperature: 10°C Total process time: 60 minutes Etch rate: 3 to 3.5 μm/min on 15% to 20% exposed area

Step 2: Via tapering (RIE) process

APC: 78% (30 mt); 84 sccm SF6; 67 sccm O2; 59 sccm Ar; 600-W coil power; 30-W platen power Platen temperature: 10°C Process time: 60 minutes Etch rate: 3.5 to 4.0 μm/min on 15% to 20% exposed area

Step 3: Via corner rounding (isotropic etch) process

APC: 65% (12 to 13 mtorr); 180 sccm SF6; 18 sccm O2; 600-W coil power; 30-W platen power Platen temperature: 10°C Process time: 10 minutes Etch rate: 1.5 to 2.0 μm/min on blanket silicon wafer

TABLE 3-1

Summary of the Three-Step Via Tapering Process

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Chapter Three the required via depth and taper angle are almost achieved, except for the sharp curvature at the top of the via. After completing the earlier two etch steps, the etch mask is fully stripped and cleaned. The wafer then is subjected to a maskless global isotropic etch process. In this etch step, the etched via patterns are mainly subjected to an isotropic etch plasma that is rich in fluorine radical (see Table 3-1 for the recipes). Since the reaction in this step is mainly chemical in nature and mostly diffusion-limited, the reaction occurs more on the rough edges and sharp corners in the top region of the microstructure, resulting in well-rounded, smooth sidewalls inside the vias, as shown in Fig. 3-3 (right).

3.2.2

Dielectric Isolation Layer (SiO2) Deposition

The thermal oxidation (wet process) is used to deposit the isolation layer. The 1-μm SiO2 is grown in a Micro Fabrication Laboratory (MFL) furnace. Hydrogen and oxygen are mixed in the quartz bulb, where they react to create a flame and steam at 1050°C. The oxidation time of Si is 3-½ hours. Conformal SiO2 is shown in Fig. 3-4. The top, middle, and bottom of the via are covered by uniform SiO2. Uniformity of SiO2 is within ±5 percent. The sidewall roughness decreases from 200 to 250 nm to less than 100 nm because of silicon consumption in wet oxidation.18 The SiO2 also can be deposited by the dry process—plasma-enhanced chemical vapor deposition (PECVD), as shown in Fig. 3-5. It can be seen that the deposited oxide thickness is 1.9 to 2 μm on the top side of the via, 1.3 to 1.4 μm on the top sidewall, 0.7 to 0.8 μm on the middle sidewall, and 0.35 to 0.45 μm on the via bottom. Thus, the SiO2 thickness made by the dry process is not as uniform as that made by the wet process. In this case, the process temperature is less than 250°C.18 Top Top Middle

Middle

Bottom of via Bottom Bottom

FIGURE 3-4 Dielectric isolation layer (SiO2) deposited by wet thermal oxidation (1080°C).

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g Top

Middle

Bottom

FIGURE 3-5 Dielectric isolation layer (SiO2) created by plasma deposition

(<250°C).

3.2.3

Barrier/Adhesion and Seed Metal Layer Deposition

Figure 3-6 shows the Ti (3000-Å) barrier and Cu (2-μm) seed layer on the walls of the via. They are deposited by physical vapor deposition (PVD) with Tango System’s AXCECA chamber, and the key process parameters are shown in Table 3-2. It can be seen that very good coverage at via bottom and via sidewall has been achieved.14

143 nm

Bottom 2.jpg

Lower wall region showed thicker coverage than middle wall due to a higher flux of resputtered material being collected. The bottom shows finer grain structure, most likely from ion bombardment.

FIGURE 3-6 Ti barrier/adhesion layer and Cu seed layer created by Tango AXCECA physical vapor deposition.

87

88

Chapter Three Process

Ti

Cu

Thickness

3 kÅ

2 µm

Dc power

8 kW

8 kW

Coil power

600 W

600 W

Bias power

1000 W

1000 W

Ar flow/ch. pressure

10/1.5 mT

20/2 mT

Bias voltage

100 V

150 V

Target voltage

550 V

630 V

TABLE 3-2 Important Process Parameters for Fabricating the Ti Barrier and Cu Seed Layer

The Ti barrier and Cu seed layer also can be deposited by a wet process. Depositions of the insulation and barrier layers inside highaspect-ratio TSVs have been achieved by Alchimer’s electrografting (eG), which initiates chemical bond formation by means of a small electric current, followed by electroless chemical propagation. Figure 3-7 shows the results of wet deposition, and it can be seen that good coverage on via sidewalls and via bottom has been achieved. (Ti = 100 nm and Cu = 1 μm).

FIGURE 3-7 Ti barrier/adhesion layer and Cu seed layer deposited by Alchimer’s electrografting.

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g

3.2.4 Via Filling The via can be filled with Cu, Ti, Al, or solder by electroplating, W by sputtering, or polymers by printing with the help of vacuum. Based on the literatures, most of the vais are filled by electroplating the Cu, which will be discussed in this book. The Cu electroplating solution for deep and high-aspect-ratio viafilling application can be either copper sulfate or cyanide-based.14,16,18 Typical composition of an electrolyte includes CuSO4, H2SO4, Cl−, with additives including suppressor, accelerator, and leveler. The electroplating system used for deep via filling is a research system from Rena. Finally, void-free wafer-level Cu filling for 300-μm-deep vias has been achieved, as shown in Figs. 3-8 through 3-10. It should

FIGURE 3-8 Cu overburden owing to long plating time.

FIGURE 3-9 Chemical and mechanical polishing (CMP).

89

90

Chapter Three

(a) Cross-section of TSV with seams

3D x-ray image with the CT (computed tomography) reconstruction of the electroplated Cu (b)

Seams/voids

FIGURE 3-10 (a) 2D x-ray image of the electroplated Cu (wafer tilted at 70 degrees). (b) 3D x-ray image with the computed tomographic (CT) reconstruction of the electroplated Cu with seams/voids. (c) 3D x-ray image with the CT reconstruction of the Cu-filled void-free TSV (Ref. 14).

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g

SEM image showing void-free electroplated Cu vias 3D x-ray with CT (computed tomography) reconstruction for Cu-filled TSVs (c)

FIGURE 3-10 (Continued)

be noted that plating chemistry, low plating current, and pretreatment (i.e., wetting + DI rinsing + preabsorbing accelerator) are the key contributors to void-free Cu filling for deep and high-aspect-ratio tapered vias. The electroplating process uses pulsed reverse plating, which employs a two-component additive system consisting of brightener and leveler. TSV quality is inspected by the 2D and 3D x-ray nondestructive testing (NDT) at an earlier stage in the fabrication process. In other words, both 2D and 3D x-ray tests are used to monitor and check TSV quality during the fabrication process without resorting to physical cross-sectioning. Figure 3-10a shows a 2D x-ray image at a tilted angle of 70 degrees for through-view of the Cu-filled TSV array in the wafer. Figure 3-10b shows a 3D x-ray with computed tomographics (CT) reconstruction of the Cu-filled TSVs with seams/voids. After process improvements, Figure 3-10c shows a 3D x-ray with CT reconstruction of the Cu-filled void-free TSVs.14

3.2.5

Cu Polishing by Chemical/Mechanical Polish (CMP)

A thick layer (30 to 50 μm) of Cu overburden (see Fig. 3-8) is plated on the wafer surface because of the long plating time required to fill the 300-μm-deep vias. The wafer bows because of the thick Cu on the surface. Conventional chemical etching takes a long time to remove the thick Cu, and nonuniform etching has been observed. Okamoto GNX 200 is used for the higher-stress Cu CMP. A soft polishing pad and strong-removal-rate slurry from Rohms and Hass are applied for thicker copper removal. The load of polishing is 320 to 350 g/cm2. The speed of pad and chuck are 90 rev/min (rpm). The speed of slurry

91

92

Chapter Three feeding is 170 to 200 ml/min. Figure 3-9 shows a cross section of a polished wafer with Cu-filled vias.

3.2.6

Fabrication of an ASIC Wafer with TSVs

As mentioned in Chapter 2, for 3D MEMS packaging with vertical electrical feed-through, one option is to have the ASIC wafer fabricated with TSVs.14,16,18 Figure 3-11 illustrates the TSV ASIC wafer fabrication and integration flow. After the deep vias are etched, insulated, filled with Cu metal, and polished by CMP during the earliest stage of fabrication (see Secs. 3.2.1 through 3.2.5), the front-side metallization and Cu-Ni-Au under-bump metallurgy (UBM) are built on top of the wafer. Next, the wafer is attached to a supporting wafer using a temporary adhesive material from Brewer Science, followed back-grinding (thinning) and backside processing to expose the vias. The bonded wafers then are processed for back-end metallization/UBM/solder bumps. The backside UBM is electroplated copper. The solder-bump material is SnAgCu (SAC). After all these processes, the bonded wafers are debonded by sliding the wafers apart at higher temperature (200°C). Temporary bonding and debonding of wafers can be done with the EV Group equipment, which will be discussed in Sec. 3.4.2.

1. Via etch 6. Support wafer bonding

2. Oxide/barrier/seedlayer deposition

7. Via exposing by thinning

3. Cu via plating

8. Backside metallization/UBM

4. Cu CMP

TSV wafer 9. Solder bumping

5. Front-side metallization/UBM

Debonding

10. Debonding & cleaning

FIGURE 3-11 TSV wafer fabrication process and integration flow.

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g Now the TSV ASIC wafer, as shown in Fig. 3-11, is ready for the MEMS device (C2W) bonding or the MEMS wafer (W2W) bonding, which will be discussed in Sec. 3.5. After capping and dicing (which will be discussed in Sec. 3.6), the whole 3D MEMS SiP is ready to be mounted on the substrate of a package or a printed circuit board (PCB).

3.2.7

Fabrication of Cap Wafer with TSVs and Cavity

For vertical electrical feed-through MEMS packaging, the TSVs on the cap wafer could be fabricated more cheaply by laser drilling, as mentioned in Sec. 3.2.1, and this is shown in Fig. 3-2.20 The advantage of laser drilling is that it is a maskless and dry process, but the disadvantage is that it creates a rough surface that may affect TSV electrical performance. After via formation, the TSV is filled with conductive materials such as copper and conductive polymers. The cavity on the cap wafer also can be fabricated by laser drilling. However, most of the cavities fabricated today are done by the potassium hydroxide (KOH) wet etch process. It can be seen from Fig. 3-2 that this process provides a much smoother surface than laser drilling.20 The etch rate depends on the doping and crystallographic orientation of the silicon, as well as the concentration of KOH used. Usually the rate is 1 μm/min.

3.3

Piezoresistive Stress Sensors for MEMS Packaging Silicon piezoresistive stress sensors are powerful tools for in situ stress measurement.22–34 For advanced MEMS packaging, they can be used for measuring the strength of the MEMS wafer, the ASIC wafer, and the cavity-cap wafer during and after all the processes such as wafer thinning, SiO2 deposition, metallization, and electroplating. This section discusses the design, fabrication, calibration, and use of a piezoresistive stress sensor to measure the strength of wafers after mounting on a dicing tape and wafer thinning.

3.3.1 Design and Fabrication of Piezoresistive Stress Sensors The layout of a n-type stress-sensor design is shown in Figs. 3-12 and 3-13.32,34 The sensors R1, R2, R3, and R4 are fabricated along the [110], ⎡⎣100⎤⎦,⎡⎣110⎤⎦, and [010] directions of a p-type (100) silicon wafer. The resistance of the R1 and R3 sensors is about 0.625 kΩ, and that of the R2 and R4 resistors is about 0.932 kΩ. The sheet resistance of all the sensors is about 178 Ω/ . These n-type stress sensors are fabricated on the silicon wafer using the conventional process. First, a 4100-Å (100-Å thermal and then 4000-Å plasma-enhanced chemical vapor deposited) silicon dioxide is grown on the p-type silicon wafer. Then the oxide is etched from the area where the sensors are designed to be fabricated. After etching the

93

94

Chapter Three

y [100] '

y [110]

x '[010] x [110]

R1

R4

R3

R2

FIGURE 3-12 Piezoresistive stress-sensor rosette.

oxide, arsenic is implanted on the p-type silicon wafer to form the n-type resistor or sensor. The surface concentration of the dopant is around 1x10−3 cm. After forming the n-type resistor, 5000-Å plasma-enhanced chemical vapor deposition (PVCVD) oxide is deposited on the wafer, and then contact windows are opened in the oxide for resistors. Finally, TaN and Al metallizations are deposited to form metal contacts to the resistors, metallization lines, and probing pads. Figure 3-13 is a drawing of the sensor chip showing the metallization lines and probing pads. Four sensor rosettes are fabricated at different locations on a 5 × 5 mm chip.

FIGURE 3-13 Fabricated stress-sensor chip showing the metallization lines and probing pads.

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g

3.3.2

Calibration of Stress Sensors

The two basic requirements for piezoresistive stress sensors to perform stress measurements are (1) a measurable resistance change of sensors with the application of loads and (2) a sensor calibration to determine the piezoresistive coefficients.23 Sensor calibration involves measuring the resistance change of sensors with the application of a known stress and then determining the piezoresistive coefficients using the theory of piezoresistivity.23,25,26 Based on the theory of piezoresistivity, if an uniaxial stress σx is applied in the [110] direction of the sensor rosette shown in Fig. 3-12, then the piezoresistive coefficients are given by

∏ 11 + ∏ 12 =

∏ 44 =

1 ⎛ ΔR1 ΔR3 ⎞ + R30 ⎟⎠ σ x ⎜⎝ R10

1 ⎛ ΔR1 ΔR3 ⎞ − R30 ⎟⎠ σ x ⎜⎝ R10

(3-1)

(3-2)

where ΔRi and Ri0, respectively, are the stress-induced resistance change and the initial resistance of the ith sensor. Once the values of the piezoresistive coefficients are known (and assuming the case of plane stress, σz = 0), piezoresistive sensors can be used to determine the unknown in-plane stress components (σx and σy) by measuring the change in resistance of sensors ΔRi and Ri0.23,25,26 Thus

⎛ ΔR ⎛ ΔR R3 ⎞ Δ R3 ⎞ ΔR ∏ 44 ⎜ 1 + + (∏ 11 + ∏ 12 ⎜ 1 − R30 ⎟⎠ R30 ⎟⎠ ⎝ R10 ⎝ R10 σx = 2 ∏ 44 (∏ 11 + ∏ 12

) )

⎛ ΔR ⎛ ΔR R3 ⎞ Δ R3 ⎞ ΔR ∏ 44 ⎜ 1 + − (∏ 11 + ∏ 12 ⎜ 1 − ⎟ ⎟ R R R R ⎝ 10 ⎝ 10 30 ⎠ 30 ⎠ σy = 2 ∏ 44 (∏ 11 + ∏ 12

) )

(3-3)

(3-4)

Various methods, such as four-point bending (4PB) of a strip of sensor chips,24,26–30 4PB of a sensor chip,31 a wafer-level vacuum chuck,30 and a hydrostatic load,24 have been used to calibrate piezoresistive stress sensors. In this section, the 4PB method with a strip of sensor chips is used for the calibration owing to its simple setup and more literature data24,26–30 for reference. Figure 3-14 shows the strip of sensor chips for the calibration of the piezoresistive stress sensors. It can be seen that the size is 70 × 10 mm and that there are 28 sensor chips in two rows. However, only the sensor rosette that is located at the center of the strip is used for calibration.

95

96

Chapter Three Area of interest

2F Stresssensor strip

t d

L

FIGURE 3-14 Piezoresistive coefficients determined by the stress-sensor strip with 4PB and an Instron microtester.

In order to perform the 4PB of the strip of sensor chips, a 4PB fixture and a loading machine to apply the load on the strip, a microscope to visualize the probing pads, two microprobes to probe the sensor pads, and a multimeter to measure the sensor’s resistance, as shown in Fig. 3-14, are needed. Here, an Instron microtester with a 100-N load cell is used to apply a given force (2F) on the strip. The relationship between the stress (σ) and applied force (2F) is reported in ref. 26. Thus σ=

3 F (L − d) t2 h

(3-5)

This equation is derived from the classical strength of material (beam theory) assuming a uniform bending stress state for points within the supports of the specimen. In this equation, L is the loading span, d is the supporting span, h is the width of the strip, and t is the thickness of the strip (chip). This formula works well if the deflection of the strip owing to the load is small and the t and h are small compared with the d and L.29 Thus, in the present work, L, d, h, and t are chosen to be of 50, 20, 10, and 0.73 mm, respectively. In the calibration process, first the resistance of the stress sensors is measured without any applied load. Then a given load (with an increment of 4 N up to 24 N) is applied on the strip using the 4PB fixture and Instron microtester, and the corresponding resistances of the stress sensors are measured with the help of the microprobe and multimeter. Considering the variation in the readings, at least eight strips of sensors from two different wafers are taken to calculate the average values.

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g 1.2 R1 R2 R3 R4

Resistance, kohm

1.0

0.8

0.6

0.4 0

50 100 150 Applied stress, MPa

200

FIGURE 3-15 Resistances of stress sensors as a function of applied stress.

Figure 3-15 shows the resistances of sensors as a function of the applied stress. It can be seen that the resistance of n-type sensor decreases with an increase in applied stress. To determine the piezoresistive coefficients from the resistance versus applied stress data, according to Eqs. (3-1) and (3-2), slops of plots between normalized resistance changes (i.e., ΔR 1/R 10 ± ΔR 3/R 30) and applied stress, as shown in Fig. 3-16, are measured and tabulated in Table 3-3. The piezoresistive coefficients ∏11 + ∏12 and ∏44 of the n-type sensor are found to be –1.98 × 10−4 and –1.06 × 10−4 MPa−1, respectively.

Normalized resistance change

0.01 (ΔR1/R10 + ΔR3 /R30)

0.00

(ΔR1/R10 – ΔR3 /R30)

–0.01 –0.02 –0.03 –0.04 –0.05 –0.06 0

50

100

150

200

Applied stress, MPa

FIGURE 3-16 Normalized resistance change of stress sensors as a function of applied stress.

97

Chapter Three ∏11 + ∏12

−1.98 × 10−4 MPa−1

∏44

−1.06 × 10−4 MPa−1

TABLE 3-3 Piezoresistive Coefficients of n-Type Stress Sensor

These values of piezoresistive coefficients are in agreement with previously reported work.23 Once the piezoresistive coefficients ∏11 + ∏12 and ∏44 of the n-type stress sensor are determined, the stresses (σx and σy) can be calculated from Eqs. (3-3) and (3-4) with the measured change in resistance (ΔRi) and initial resistance (Ri0). In this chapter, the piezoresistive stress sensors will be used to evaluate the stresses in wafers after mounting of a dicing tape and thinning (back-grinding).

3.3.3

Stresses in Wafers after Mounting on a Dicing Tape

Figure 3-17 shows a 400-μm-thick sensor wafer mounted on a dicing tape with a dicing ring. It can be seen that a commercially available dicing tape is mounted or laminated on the backside of the wafer using a dicing ring and an automatic tape laminator (Dyna Tech).

FIGURE 3-17 Stresses in thinned sensor wafer after mounting on the dicing tape.

80

σx σy

60 Stress, MPa

98

40 20 0

–20 –40 400

300 200 Wafer thickness, μm

100

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g The parameters of the lamination process include a pressure of 0.3 MPa, a speed of 10 mm/s, a tape thickness of 70 mm, and lamination at room temperature (RT). After tape mounting, the wafer is baked at 70°C for 15 minutes to increase the adhesion between the dicing tape and the wafer. After baking, the dicing ring and any excess dicing tape are removed from the tape-mounted sensor wafer. The resistance measurement is performed at nine locations on a wafer, as shown in Fig. 3-18. The in-plane stress components (σx and σy) are determined by Eqs. (3-3) and (3-4), and their average values are shown in Fig. 3-17. It can be seen that the dicing-tape mounting increases the tensile stress at the surface of the sensor wafer. Owing to this increase in tensile stress, the stress in the 400-μm-thick wafer is in tension, whereas the stress in the 100-μm-thick wafer is still in compression, but its magnitude decreases significantly. The presence of these tensile and compressive stresses in the dicing-tape-mounted wafer is further confirmed with the wafer bending profile and bow values (by using 33-point measurements), as shown in Fig. 3-19 and Table 3-4, respectively. The transition in stress state in the sensor wafer after mounting with dicing tape can be explained through the dicing-tape mounting process. The dicing-tape mounting process is actually a lamination process, in which a polymer tape is stretched and laminated on the backside of the wafer. After that, the dicing tape tries to return to its

3

4

5

2

1

9

8

6

7

FIGURE 3-18 Stress-measurement locations on a stress-sensor wafer.

99

100

Chapter Three W

E

S

N

NW

SE

SW

NE

W

E

S

N

NW

SE

SW

NE

FIGURE 3-19 Bow data and bending profiles of a 400-μm-wafer (top) and a 100-μmwafer (bottom) after dicing-tape mounting.

Wafer Thickness (mm)

Bow (mm)

400

21.5

200

−20.8

100

−29.5

TABLE 3-4

Wafer Bow of Stress-Sensor Wafers of Different Thicknesses after Mounting with Dicing Tape

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g original shape owing to its viscoelastic behavior. Thus, after the lamination process, the shrinkage in dicing tape results in the development of a downward bending force on the sensor wafer, and therefore, the top surface of the wafer experiences a tensile stress.

3.3.4

Stresses in Wafers after Thinning (Back-Grinding)

In order to study the effects of wafer thinning on the strength of the wafer, three original sensor wafers (730 μm) were thinned down to three different thicknesses, namely, 400, 200, and 100 μm. A commercial back-grinding machine (Okamoto GNX 200) was used for the thinning process, which consisted of three major tasks: rough grinding, fine grinding, and polishing. The process parameters for the meshsize grinding wheel, spindle speed, chuck table speed, and feed rate are, respectively, No. 600, 3000 rpm, 230 rpm, and 180 to 190 mm/min for rough grinding and No. 2000, 3400 rpm, 230 rpm, and 12 to 16 mm/min for fine grinding. The final polishing is with a 200-ml/min slurry flow, 150-g/cm2 load, 230-rpm pad speed, and 210-rpm chuck speed. After thinning of the wafers, a resistance measurement is done at the same nine locations (as shown in Fig. 3-18) on the sensor wafer, and the stress components (σx and σy) are determined by Eqs. (3-3) and (3-4) and are shown in Table 3-5 for the case of a wafer thinned down to 100 μm. It can be seen that a large amount of compressive stress has been generated in the sensor wafer after thinning. Figure 3-20 shows the average stress as a function of wafer thickness, and it is apparent that the amount of in-plane stress (compressive) increases exponentially with a decrease in wafer thickness.

Location No.

Stress σx (MPa)

Stress sy (MPa)

1

−16

−23.6

2

−47.3

−24.6

3

−112

−89.2

4

−71.6

−48.8

5

−51.9

−44.3

6

−47.3

−24.6

7

−51.9

−44.3

8

−79.7

−56.9

9

−27.6

−20.0

Average

−56.1

−41.8

TABLE 3-5

Stress Components Measured at Different Locations on a Wafer after Thinning Down to 100 µm

101

Chapter Three

σx

20

σy 0 Stress, MPa

102

–20 –40 –60 –80 700

600

500

400

300

200

100

Wafer thickness, μm

FIGURE 3-20 Stress versus wafer thickness.

The degree of compressive stress on the sensor wafer is further confirmed by measuring the wafer bending profile and the bow of the original and back-ground wafers. The wafer bow was measured using the 33 point measurements and the results are shown in Fig. 3-21. The measured values are listed in Table 3-6. Transition of the wafer bow from positive to negative indicates that the stress state at sensor wafer plane changed from tensile to compressive. This transition in stress state can be understood with the help of sensor wafer processing materials. Basically, the sensor wafer consists of two layers of materials. The first layer (bottom layer) is a single-crystal silicon, and the second layer (top layer) is mainly 9000 Å of PECVD silicon dioxide. This PECVD silicon oxide is deposited on the silicon wafer at approximately 400°C. Thus, when the sensor wafer cools down to the RT, because of the thermal-expansion mismatch between the thin silicon dioxide [thermal expansion coefficient (TEC) = 0.54 ppm/K34] layer and the silicon substrate (TEC = 3.07 ppm/K34), it creates a bending (bowing upward) of the composite sensor wafer that generates tensile stress on top of the wafer. This is confirmed with the bow-measurement results shown in Fig. 3-21 (top). However, in order to define the reference point for stress measurement, the stress state on original wafer surface at RT is assumed as “stress free.” Thus, if the tensile stresses on the sensor-wafer surface decrease, then the stress sensor will detect an increase in compressive stress. The increase in compressive stress (decrease in tensile stress) in the thinned wafer can be attributed to the decrease in bending stiffness (which is to the cube of the thickness) of the silicon layer with the decrease in its thickness.

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g W

E

S

N

NW

SE

SW

NE

W

E

S

N

NW

SE

SW

NE

FIGURE 3-21 Bow data and bending profiles of original (730-μm) wafer (top) and 100-μm thinned wafer (bottom).

Wafer Thickness (mm)

Bow (mm)

730 (original)

8.1

400

9.9

200

−3.9

100

−9.2

TABLE 3-6 Bow of Stress-Sensor Wafer Showing a Transition from Positive Bow to Negative Bow with a Decrease in Wafer Thickness

103

104

Chapter Three Compounded with the thermomechanical stresses imposed during the wafer back-grinding process, subsurface damage could occur on the backside of the silicon layer.

3.4 Wafer Thinning and Thin-Wafer Handling In order to have low-profile products with 3D MEMS packaging, the thickness of the chips/wafers (e.g., MEMS device, ASIC chip, and cap) is usually very thin. Making the wafer thin is not a big problem. Most of the back-grinding machines (e.g., Disco) can do the job and grind the wafers to as thin as 5 μm. However, handling thin wafers through all the semiconductor fabrication and packaging assembly processes is difficult. Usually, the thin-device wafer is temporarily bonded on a support wafer. Then it goes through all the semiconductor fabrication processes, such as metallization, passivation, and UBM, and the packaging processes, such as backgrinding and solder bumping. After all these are done, removing the thin wafer from the support wafer poses another big challenge. This section discusses a few methods for handling thin wafers.

3.4.1

3M Wafer Support System

Figures 3-22 and 3-23 show the new 3M wafer support system,35 which enables conventional back-grinding equipment to be used to produce wafers with a final thickness as low as 20 μm. The key to the

FIGURE 3-22 3M wafer support system with a wafer.

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g

FIGURE 3-23 3M wafer support system with a glass supporting plate.

3M system is its ability to provide a rigid, uniform support surface to minimize stress on the wafer as the silicon is removed, resulting in less cracking and chipping. The system includes both the equipment and consumables [3M UV-Curable Liquid Adhesive LC-2201, glass support plate (typically recycled, can be reused many times), and 3M light-to-heat Conversion Solution] necessary for mounting, demounting, and removing adhesive from the wafer. In the 3M system, a glass plate (as shown in Fig. 3-23) is used to support the wafer through the back-grinding process. An ultraviolet (UV)–curable liquid adhesive is used as the bonding agent between the device wafer and the glass plate (support wafer). After the backgrinding process, as shown in Fig. 3-24, the thinned device wafer is transferred onto a dicing tape, and the support glass is removed by laser debonding of the adhesive-glass interface using a light-to-heat conversion (LTHC) layer. The adhesive then can be removed from the wafer, leaving behind fewer residues than seen with typical backgrinding tapes. This system also works for other semiconductor and packaging processes as long as the thermal-expansion mismatch between the device wafer and the glass plate is within the allowable tolerance.

3.4.2

EVG’s Temporary Bonding and Debonding System

EVG and Brewer Science have developed a solution that enables temporary bonding of a device wafer to a right carrier substrate (support wafer) and allows not only thinning but also a full range of subsequent

105

106

Chapter Three

Grinding stress to the wafer can be minimized because the UV-curable

Mount (spin coat UV resin on wafer; vacuum bond to support glass; UV irradiate)

adhesive flows into and supports the topography

Wafer

of the circuit patterns on

UV-cured liquid adhesive

the front side of the wafer.

LTHC layer

Support glass

The mounting process is

Because the wafer is fully

done under vacuum, ensuring that no bubbles

supported throughout

Back-grind

the back-grinding

are entrapped between

Grinding wheel

the wafer and the

process, less cracking is observed and higher

support glass.

yields can be obtained. Standard back-grinding

The laser debonding of

equipment is used; no

the adhesive-glass plate

significant back-grinding

interface is uniform, so

process changes are

no damage to the wafer

Laser irradiation

necessary. Laser

occurs when the glass plate is removed.

Dicing tape

Thinned wafer

Dicing

Remove support

Residue levels on the

Peel off UV resin layer

wafer surface after adhesive removal are lower than when using conventional back-grinding tapes.

FIGURE 3-24 3M wafer support system process flow (for wafer thinning).

processes, including high-temperature deposition, etching, lithography, dielectric application and curing, plating, and chemical cleaning, as shown in Fig. 3-25.36

Temporary Bonding The front side of the device wafer and the support wafer are coated with the WaferBOND, an HT Brewer Science adhesive material, by using the coating chamber (shown in Fig. 3-26) that includes spin and spray coat capability. Both wafers then are transferred to a bond

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g Device wafer: Front-end processing (lithography, etching, etc.) Flip wafer Device wafer Carrier wafer with intermediate layer

TEMPORARY BONDING Device wafer bonded on carrier wafer

Back-thinning and further processing Device wafer (thin) on carrier wafer

DEBONDING

Cleaning

Thin-wafer handling Unloading in output format

FIGURE 3-25 EVG temporary bonding and debonding (of wafers) process flow.

chamber (EVG850TB), where they are carefully centered and vacuum bonded at elevated temperatures. Once the device wafer is temporarily bonded to the support wafer, it is ready for backside processing, including back-grinding, etching, metallization, TSV formation, etc.

Debonding During the debonding process, the thin wafer is debonded first via a thermally activated slide lift-off approach from the support wafer, cleaned in a single-wafer cleaning chamber to remove the remaining adhesive residues, and then transferred to the appropriate output format, such as a film-frame carrier, a dedicated wafer cassette, or a coin-stack packing canister, as shown in Figs. 3-25 and 3-27.

107

108

Chapter Three

FIGURE 3-26 EVG wafer-coating chamber, including spin and spray-coat capability.

The carrier wafer is also cleaned and then can be reused immediately for another debonding process.

3.4.3 A Simple Support-Wafer Method for Thin-Wafer Handling This section presents a very simple support-wafer method for thinwafer (50-μm) handling.32 The support-wafer fabrication process flow is shown in Fig. 3-28. The major process steps are photoresist (PR), lithography, release-hole etching using deep reactive-ion etch (DRIE), stripping of PR, and back-grinding to 500 μm. The device-wafer and perforated support-wafer bonding process flow is shown in

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g

Thin-wafer cassette Megasonic

Processed device wafer

DI-water Solvent Diluted

Film frame

Chemistry Brush scrubber High pressure etc.

Carrier wafer

Coin stack

UV-exposure Single wafer carrier

DEBONDING

CLEANING

OUTPUT FORMAT

FIGURE 3-27 EVG debonding process flow, including debonding, cleaning, and outputting the thin wafer in various formats. Si wafer

Photoresist lithography

DRIE & stripping of PR

Back-grinding

Perforated support wafer

FIGURE 3-28 Support-wafer fabrication process flow.

Fig. 3-29 (left). The bonding adhesive used is the Waferbond from Brewer Science. The bonder used is the EVG bonder. The bonding parameters used are (1) 1.2 kN of applied force and (2) at 150ºC for 5 minutes. The wafer debonding process flow is shown in Fig. 3-29 (right). The major debonding steps are (1) soak in Waferbond remover solution at 90ºC and (2) remove wafer. The initial pitch between the two release holes on the perforated support wafer is 3.5 mm.

109

110

Chapter Three Wafer bonding

Wafer debonding

Device wafer Spin coating of adhesive Device wafer Support wafer

Wafer bonding

Device wafer Back-grinding to 50-μm

Stripping of adhesive Perforated support wafer (can be reused) + 50-μm-thick device wafer

FIGURE 3-29 Wafer bonding process flow (left) and wafer debonding process flow (right).

One of the key problems encountered in the support-wafer method is wafer debonding. The 50-μm-thick device wafer is easily broken during the wafer debonding process, as shown in Fig. 3-30. This key problem is resolved by optimizing the wafer debonding process to minimize residual stress. The first step is to reduce the pitch of the release hole on the perforated support wafer from 3.5 to 2 mm. The second step is to increase the number of perforations on the edge of the support wafer. These two optimized debonding methods allow more chemical solution to uniformly penetrate into the bonding adhesive and eventually debonded the wafers successfully, as shown in Fig. 3-31. Using the simple support-wafer method, thin-wafer transport and handling are possible. For example, the thin (50-μm) device wafer is attached to a support wafer and is handled and put in the PECVD FIGURE 3-30 Device wafer and perforated support wafer. 50-μm-thick device wafer

Perforated support wafer with 1-mm-diameter release holes

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g FIGURE 3-31 50-μm wafer after successful debonding.

50-μm-thick device wafer

Support wafer

50-μm-thick device wafer

FIGURE 3-32 The bonded perforated support wafer with the 50-μm device wafer in the plasma-therm chamber for the silicon dioxide PECVD process.

chamber for silicon dioxide deposition, as shown in Fig. 3-32. No wafer cracking is observed during wafer handling and after silicon oxide deposition. Thus thin-wafer handling using the support-wafer method is highly recommended. Some engineering and process development are required, though.

3.5

Low-Temperature Bonding for MEMS Packaging For 3D MEMS packaging, as mentioned in Chapter 2, the MEMS device/ wafer is bonded with the ASIC chip/wafer by either C2C or C2W bonding methods. Owing to chip yields and chip size differences, the W2W bonding method is seldom used. Most current bonding methods use temperatures higher than 300°C.37–39 During bonding, however, the

111

112

Chapter Three MEMS devices are already released (there are free-standing microstructures, e.g., membranes, beams, and cantilevers), and low-temperature bonding40–68 is desired to reduce damage to the microstructure owing to the thermal-expansion mismatch of the bonding structure (less bow). The bonding temperature for silicon C2C, C2W, and W2W bonding can be as low as RT40 (e.g., fusion bonding). However, for this kind of bonding, the bonding surfaces must be very flat and clean, which do not permit high-volume production, which is beyond the scope of this book. Low-melting solders such as In-Ag, In-Cu, In-Sn, In-Ni, and In-Sn-Cu, with bonding temperatures of less than 200°C, will be considered and presented in this and subsequent chapters.

3.5.1 How Does Low-Temperature Bonding with Solders Work? The basics of low-temperature bonding are shown in Figs. 3-33 and 3-34. It can be seen that the low-temperature solder (e.g., In-Ag, In-Cu, In-Sn, In-Ni, and In-Sn-Cu) is coated on the specially designed and Temperature, time, & pressure

Pick & place Micropads Micropads Low-melting solder

Micropads

Low-melting solder IMC

Low-melting solder Low-melting solder

Micropads

Micropads

Micropads

Aligning

Coating

Bond at 150–180°C, then all the interconnects become IMC with much higher remelt temperature

FIGURE 3-33 Fundamentals of low-temperature bonding. Wafer/Chip 2 Face UBM

Micropads

Face

Wafer/Chip 1

Transistor structure

Low-temperature solder

FIGURE 3-34 Face-to-face low-temperature bonding.

UBM

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g fabricated under-bump metallurgy (UBM). After aligning and bonding at a temperature of less than 200°C, all the solders will be reacted with the UBM (e.g., Cu, Cu/Au, and Cu/Ti/Au) of the pads (e.g., Al, Cu, Ni, Ag, and Au) on the chips/wafers and become an intermetallic compound (IMC) with a melting point that is (a couple of hundred degrees) higher than that of the solders. This feature is welcome by 3D MEMS packaging. For example, after the bonding of a MEMS device with an ASIC wafer with a lowmelting solder, all the bonding (solder-interconnect) areas become the IMC with a very high remelting temperature. When a cap wafer is bonded (with a low-temperature solder) to the ASIC wafer (already bonded with the MEMS device), the interconnect between the ASIC and the MEMS devices will not be reflowed. Furthermore, when the whole 3D MEMS package is attached to the PCB with surface-mounttechnology (SMT) lead-free solder (260°C), the solder interconnects between the ASIC and MEMS and cap and ASIC will not be reflowed.

3.5.2

Low-Temperature C2C Bonding

Figure 3-35 shows a schematic cross section of hermetic C2C lowtemperature bonding. The size of the bonding ring on the silicon base chip is 8 × 8 mm and the width of the bonding ring is 300 μm. The seed layers (SiO2, Si3N4, Ti, and Cu) and solder layers (In, Sn, and Au) are shown in the figure.42,43 The seed layers are fabricated by a sequential evaporation process along the bonding ring from a silicon wafer. This is followed by electroplating of the Cu and, finally, by E-beam

Cap Bonding ring

Base

SiO2 Si3N4

Silicon cap

Ti Cu

Au Sn

Silicon base

In Cu Ti Si3N4 SiO2

FIGURE 3-35 Schematic of a cap chip and a base chip with bonding ring (top) and their multilayer structures on the bonding ring.

113

114

Chapter Three sequential evaporation of the solder. The thickness of the Cu layer is 3 μm, the In layer is 1.6 μm, the Sn layer is 1.4 μm, and the Au layer is 50 nm. The very thin layer of Au is deposited on the Sn layer to inhibit oxygen penetration, which could happen when the samples are removed from the vacuum chamber and exposed to air. The silicon base-chip sizes are 10 × 10 mm. For the silicon cap chip, everything is the same except that there is no In, Sn, or Au. Figure 3-36 shows top and cross-sectional views of the as-received evaporated/electroplated bonding ring. It can be seen that the surface is very rough and has a granular structure with a grain size of 2 to 3 μm. In order to bond surfaces with such rough features, a molten solder layer and high pressure are necessary to fill the gaps between surfaces. Figure 3-37 shows the pull-test results (bond strength) of bonding couples under various bonding conditions (with the same bonding

In/Sn Cu Si

FIGURE 3-36 Scanning electron microscope (SEM) images of as-received evaporated composite coating surface (left) and its cross section (right). 8 5 minutes 20 minutes

Bonding strength, MPa

7 6 5 4 3 2 1 0

140

150

160 170 Temperature, °C

180

FIGURE 3-37 Effect of the bonding conditions on bonding strength.

190

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g

FIGURE 3-38 Cross section of a bonding ring bonded at 1.5 MPa and 180°C for 20 minutes.

pressure of 1.5 MPa). It can be seen that higher bonding temperatures with longer bonding times yield better bond-strength results. Figure 3-38 shows a cross section of bonding couples obtained at 1.5-MPa bonding pressure and 180°C for 20 minutes. The thickness of the interconnect is uniform throughout the whole contact area with a typical value of 6.2 ± 0.5 μm. The bond couples are in good contact, and no interface line is observed, which means that the solder intermediate layers have melted during the bonding process and leveled the trough between granules. Acoustic images of the bond interface for chips bonded at 1.5 MPa of bonding pressure and 180°C for 20 minutes are shown in Fig. 3-39. The whole bonding ring is a uniform gray color, indicating that the bonded couples have intimate contact and that no voids or delamination occurred. The helium-leak-rate test results show that the bonding couples are hermetically sealed with an average leak rate of 5.8 × 10−9 (atm · ml)/s (the average of five samples). The fracture surfaces after pull tests are studied by x-ray diffraction (XRD) to examine the IMCs evolved in the bonding reaction zone. The AuIn2, Cu6Sn5, and Cu11In9 phases are found in the XRD analyses shown in Fig. 3-40. No peak of Sn or In is detected. Since the IMC layers are relatively thin, the transmission electron microscope (TEM) technique is used because it provides local chemical analysis. Figures 3-41 and 3-42, respectively, show TEM images of the region close to the base material silicon and interfacial reaction region between the Cu and solder intermediate layers. Figure 3-41 shows that on top of the silicon, the first layer is silicon oxide, followed by silicon nitride, titanium, and copper. The interfaces between each layer are void-free and uniform. The silicon oxide and nitride layers provide good adhesion between the subsequent metal layer and silicon base. Figure 3-42 shows the reaction zone between the Cu and Sn-In solder interlayer. Small grains are clearly visible in the reaction zone. The elemental composition results of the selected points are summarized

115

Chapter Three FIGURE 3-39 Acoustic images of a well-bonded flat silicon chip (left) and well-bonded patterned chips bonded at 1.5 MPa and 180°C for 20 minutes.

(a)

Bonding ring

(b)

800 ⊕

700

Δ

Δ

600 Intensity

116

⊗

Cu6Sn5 Cu11In9 AuIn2

500 400

⊗

300

100

⊗

Δ

Δ

Δ ⊕

Δ

0 25

⊕

Δ

Δ ⊕

200

30

35

40

45

50

⊗ Δ ⊕

55

⊗ ⊕

60 2θ

⊕Δ

⊗ Δ

65

⊕

70

FIGURE 3-40 XRD results of interface after pull tests.

⊗

75

⊕

⊕

80

⊗

85

⊗

90

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g

Cu SiO2 & Si3N4

100 nm

Ti

Si

FIGURE 3-41 TEM image at the silicon region.

12 10 11 7 8 9 6 5 4

3

2 1 0.2 μm

FIGURE 3-42 TEM image at the interface region.

117

118

Chapter Three Composition (at percent) Point

Cu

In

Sn

Au

Phase

1

99.5

0.3

0.2

0

Cu

2

99

0.3

0.2

0.5

Cu

3

56.0

28.5

15.5

0

Cu11(In, Sn)9

4

54.6

31.3

13.7

0.4

Cu11(In, Sn)9

5

52.1

30.4

17.0

0.5

Cu11(In, Sn)9

6

51.4

28.3

19.6

0.7

Cu11(In, Sn)9

7

50.2

31.2

18.3

0.3

Cu11(In, Sn)9

8

48.1

21.0

30.4

0.5

η-Cu6(SnIn)5

9

49.8

23.4

26.6

0.2

η-Cu6(SnIn)5

10

50.3

20.7

29.0

0

η-Cu6(SnIn)5

11

5.9

59.0

1.1

34.0

Au(In, Sn)2

12

5.1

60.2

1.7

33.0

Au(In, Sn) 2

TABLE 3-7 Summary of Point EDX Analysis along the Interface Shown in the TEM Image

in Table 3-7. Two IMCs are identified along the main reaction zone, that is, Cu6(Sn, In)5 and Cu11(In, Sn)9. This result is very consistent with the XRD results, which confirmed the presence of these two IMCs in the bonding interface. The composition of Cu gradually reduces from 56 to 48 at percent from the near-Cu region to the near-In region. The energy dispersive x-ray (EDX) analysis suggests that there is still unreacted Cu that is not used for joint formation. At the edge of bonding interface, Cu composition drops dramatically, and only In and Au dominate, with the composition shown as points 11 and 12 in Table 3-7, that is, Cu5.9Au34In59.0Sn1.1 and Cu5.1Au33In60.2Sn1.7, which corresponds to an equilibrium-phase AuIn2. It is interesting to note that the overall composite solder is molten at 180°C, and the melting temperature of Sn is 230°C. This is so because the molten In layer is mixed with solid-state Sn layer and forms a thin, low-melting-temperature In-Sn layer at the interface. From the binary diagram, the eutectic In-Sn alloy has a lower melting point of 118°C, and at RT, the extent of Sn content in β phase ranges from 15 to 28 wt %, and the extent of In in γ phase can reach approximately 28 wt %. This means that In and Sn can easily diffuse into each other. Therefore, liquid In and solid Sn can interdiffuse into each other, and as a result, the eutectic In-Sn layer grows at the expense of the single In layer and Sn layer until both solder layers are completely consumed.

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g Notice that the initial overall composition of In and Sn present in the as-received base chip is the eutectic composition, that is, 48 wt % Sn. Although the In also reacts with Au, it consumes only a small portion of In, which leaves the overall In and Sn compositions slightly shifted to off-eutectic point, that is, with 50 wt % Sn. Thus, with such a near-eutectic liquid layer, the intrinsic roughness of the evaporated surface can be overcome, and a good joint interface is observed, as described earlier. During the soldering process, the subsequent interdiffusion of Cu and Sn or In takes place in the interface region and forms various IMCs. Because of the fully molten status of the intermediate layers at the temperature of 180°C, this may explain why the In atoms can interact with Au and form AuIn2 in the case where the Sn layer initially lies between the In layer and the Au. The composition analysis and XRD results also suggest that no unreacted In or Sn is present after bonding. The solder materials have completely transformed into IMCs by reacting with copper. This finding indicates that the bonding joint produced at low temperature can withstand high service temperatures owing to the presence of highmelting-point IMCs. From a consideration of the phase diagrams, the melting points of Cu6Sn5, Cu11In9, and AuIn2 are 430, 320, and 580°C, respectively. Therefore, the thermal stability of the joint is expected to be higher than 300°C. Figure 3-43 shows a slightly different solder system,50,51 where Cu/Au is used for the UBM, and the formation of mixed In-Cu and In-Au IMC phases are expected at the joint after bonding. The IMC phases and their melting temperatures could be checked in the phase diagrams (Fig. 3-44a and b). The structure and dimensions of various solder elements are shown in Fig. 3-43, where the bonding conditions, such as pressure (2.5 MPa), temperature (180°C), and time (20 minutes)

Si/SiO2 /Ti UBM (in μm)

Cu

Cu2Au0.03 Solder (in μm)

Sn

In

Sn

In

Au

Au

Sn0.5In2Sn0.5Au0.03

Bonding Parameters Temp Time Pressure (°C) (min) (MPa) 180

20

Cu Si/SiO2 /Ti

FIGURE 3-43 Schematic of the cap chip and base chip and their multilayer structures on the bonding ring.

2.5

119

Chapter Three 1200

1000 Liquid

Temperature, °C

800 FCC (Au) 600

Cu4In Cu7In3 Cu2In + Liquid

400

Cu11In9 + Liquid

Cu2In

200

Cu11In9

Cu11In9 + Tetragonal (In)

0 0

0.1

0.2

0.3

(a)

0.4 0.5 0.6 Mole fraction, In

0.7

0.8

0.9

1.0

1200

1000 Liquid 800

Temperature, °C

120

FCC (Au) 600 HCP_A3 400

AuIn_alpha1 AuIn3

AuIn2

Au7In2 200

Au3In

AuIn

Au7In3

AuIn2 + Tetragonal (In)

0 0 (b)

0.1

0.2

0.3

0.4 0.5 0.6 0.7 Weight fraction, In

0.8

0.9

FIGURE 3-44 (a) Phase diagram of Cu-In. (b) Phase diagram of Au-In.

1.0

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g Cross-sectional SEM images

Heat flow, w/g

DSC curve showing remelting temperature > 400°C

ηCu6(InSn)5

–10

–15 0

100

200 300 Temperature, °C

400

500

FIGURE 3-45 Cross section of a joint bonded at 1.5 MPa and 180°C for 20 minutes (left) and its DSC curve (right).

are given. Figure 3-45 shows a void-free cross section and the differential scanning calorimetry (DSC) curve indicting that the remelting temperature is higher than 400°C. Figure 3-46 shows the very good helium-leakage test results and shear-strength test results. The lowtemperature interconnects also pass some reliability assessments, such as the pressure cook test (PCT), the high-temperature-storage test (HTS), and the thermal cycling test (TCT).

As Sealed

PCT

HTS

TCT

He leakage (atm · cc/s)

<5 × 10–8

<5 × 10–8

<5 × 10–8

<5 × 10–8

Shear strength (MPa)

27

34

28

18

8 mm

PCT: 121°C, 100%RH, 2 atm, 300 h HTS: 125°C, 1000 h TCT: –40/+125°C 1000 cycles

Seal ring

8 mm

FIGURE 3-46 Reliability assessment of C2C bonding with He leakage and shear strength tests.

121

122

Chapter Three

3.5.3

Low-Temperature C2W Bonding

Usually the chip size between MEMS and ASIC is not the same. Thus W2W bonding of these two devices may not be a good idea, and the interconnections generally are performed by either C2C or C2W bonding. This section discusses a MEMS chip with only the UBM bonded to an ASIC wafer with the low-temperature solders discussed in the preceding section. The ASIC wafer is shown in Figs. 3-47 and 3-48.

Alignment keys

Low-temp solder seal ring

Low-temp solder bonding pads AuInSn Ti/Cu/Au

ASIC wafer

FIGURE 3-47 Top and side views of an ASIC wafer with low-temperature solders. ASIC chip

FIGUSE 3-48 The fabricated ASIC wafer.

Seal ring

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g Bonding and pickup tool MEMS chip

Low-temp solder

ASIC wafer

FIGURE 3-49 Pick and place the MEMS device on the ASIC wafer.

Both the bonding pads (for the MEMS device) and seal ring (for the cap wafer) are coated with low-temperature solders. Figures 3-49 and 3-50 show the MEMS chip being picked up and place on the ASIC wafer in an FC150 bonder. The bonding parameters are 6 MPa of bonding pressure at 200°C on the bonding tool (MEMS) and 90°C on the ASIC wafer, lasting for 40 seconds.50–53 The operation is performed in an enclosed N2 environment. Figure 3-51 shows a cross section of the bonding. There is no misalignment.

FIGURE 3-50 FC150 bonder (±1 μm) for C2W bonding.

123

124

Chapter Three

Shows good alignment

Bonding pad between MEMS device and ASIC wafer

FIGURE 3-51 Cross section of bonding between the MEMS device and the ASIC wafer.

3.5.4 Low-Temperature W2W Bonding An 8-in cap wafer is shown in Fig. 3-52. As mentioned earlier, its cavity is fabricated by the KOH etch process. The seal ring on the cap wafer is coated only with the UBM. Figure 3-53 shows a schematic of the cap wafer bonding to an ASIC wafer, which is accomplished in an EVG bonder with a pressure of 9 kN, temperature of 200°C, and bonding time of 20 minutes. 46–49 Figure 3-54 shows an x-ray

Cavity

Seal ring with UBM

FIGURE 3-52 The cap wafer with cavities and seal ring are coated with UBM only.

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g Cap wafer

ASIC wafer

FIGURE 3-53 Schematic of W2W bonding of a cap wafer and an ASIC wafer.

Bond pad (MEMS and ASIC)

Support wafer Seal ring

MEMS chip LT solder seal-ring bonding

X-ray picture of the bonded MEMS and ASIC wafers

LT solder bonding on 300-μm pads Bond pads between MEMS and ASIC (white arrows)

FIGURE 3-54 X-ray and SEM images indicate good alignment.

photograph and cross sections of the W2W bonding of the ASIC wafer and the cap wafer. It can be seen that (1) bond pads between the MEMS chip and the ASIC chip are in good alignment, and (2) there is no void in the solder sealing ring. Figure 3-55 shows the He leakage and shear strength test results. All the chips meet the specifications. After solder bumping and dicing, one of the individual packages is also shown in Fig. 3-55. It is ready to be put on a substrate in a package or on a PCB. It should be ensured that the bonding chamber for W2W bonding is free from debris. Because of the high vacuum during bonding, any particles present will cause the wafer to crack or form microcracks. Also, any significant misalignment between the ASIC wafer and the cap wafer could cause the entire wafer to be unusable. EVG’s SmartView Bond Aligner for face-to-face alignment can help. For more lowtemperature W2W bonding for 3D MEMS packaging, please see Chapter 4 and refs. 46 to 49.

125

126

Chapter Three Bond force

Temperature

Time

Shear strength (Cap-ASIC)

Shear strength (MEMS-ASIC)

Hermeticity (atmcc/sec)

9 kN

200°C

20 m

71.6 MPa

9.2 MPa

6 × 10–8

Completed package (face-to-face bonding) with solder ball attached

FIGURE 3-55 The completed package with solder ball attachment and reliability assessments.

3.6 MEMS Wafer Dicing Dicing of released MEMS wafers is not easy, especially for silicon-oninsulator (SOI) wafers and bonded wafers (e.g., silicon-on-silicon and silicon-on-glass) with etched patterns or circuitry. Compounded with very small MEMS die sizes and the requirement of very small street (kerf) widths (e.g., ≤100 μm) and chipping (e.g., ≤20 μm), dicing of MEMS wafers can be very challenging. Because of the exposed tiny/ thin, fragile, moving/pop-up structures (e.g., cantilevers, bridges, hinges, gears, and membranes), problems with stiction and debris are often encountered, thus decreasing manufacturing yields and increasing product costs. Use of the traditional diamond saw with water-jet cooling and cleaning is quite impossible without major modifications to the process steps. On the other hand, the stealth dicing (SD) technology uses a laser beam focused onto the MEMS silicon bulk and performs the internal transformation of silicon. The dies separate themselves by dicing-tape expansion, which effectively pulls the dies apart. This technology provides a dry, clean, nearly particle-free dicing process for sensitive MEMS devices. This section discusses dicing of SOI wafers and silicon-on-silicon bonded wafers using the SD method. Also, the dicing of silicon-on-glass bonded wafers is presented by the 2-step method developed by NEDO.

3.6.1

Fundamentals of SD Technology

Unlike the conventional laser dicing methods (i.e., laser ablation and laser breading),69–71 whose laser beam is focused on the wafer surface and the laser energy is absorbed on the wafer surface, the laser

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g FIGURE 3-56 Basic principles of SD technology.90–98

Laser

Focusing lens

SD layer

Si wafer

processing of SD method occurs only on the inside of the wafer; that is, the visible machining lines and the lines where cutting will be done remain hidden on the inside of the wafer, which is why the method is called stealth. There is little or no damage to the front and back sides of the wafer, as well as to the dicing tape on the backside of the wafer. The advantages of the SD method are (1) no chipping, (2) no debris contaminants, (3) a completely dry process, and (4) an environmentally friendly process. Figure 3-56 shows the basic principles of the SD technology72–77 developed by Hamamatsu Photonics. The laser beam is a 150-ns pulse Nd:YAG laser at a wavelength (>1000 nm, or 1064 nm) capable of transmitting through a silicon wafer that is condensed by an objective lens and focused onto a cleaving start point inside the wafer. By optimizing the laser and optical system to cause the absorption effect just in the vicinity of the focal point (also called the SD layer) inside the wafer, only localized points in the wafer can be selectively laser-machined without damaging the front and back surfaces of the wafer. The SD technology consists of two major processes. One is the laser process to form an SD layer (transformed area) on the interior of the wafer, and the other is the separation process to divide the wafer into small dies. Figure 3-57 (top) schematically shows the SD layer and the cracks that form on both sides of the SD layer, which extend toward (but do not reach) both surfaces of the wafer. Figure 3-57 (bottom) schematically shows wafer separation by tensile stresses induced by dicing-tape expansion. Figure 3-58 (top) shows the wafer before dicing-tape expansion, and Fig. 3-58 (bottom) shows the wafer after dicing-tape expansion, which is pushed up by a cylindrical stage. In this case, the 200-μm wafer is 50 μm thick, and individual die size is 10 × 10 mm.

127

128

Chapter Three

Cracks

Separated chip Tape expansion

Compression stress

Tensile stress

Tape expansion

FIGURE 3-57 SD technology: (top) laser transformation of silicon and (bottom) separation by tension.90–98

Chip

Wafer

Stage

Dicing tape Push up

FIGURE 3-58 Expansion process: (left) before expansion and (right) after tape expansion. When a cylindrical stage pushes up the dicing tape, the wafer on the dicing tape is separated into individual chips.90–98

For thicker silicon wafers, such as those with MEMS devices, in order to make it easier to separate the wafer into individual chips, the SD layers may have to be joined vertically while making multiple scans depth-wise in the wafer, as shown in Fig. 3-59. It can be seen in Fig. 3-59 (top) that the cracks have reached the laser irradiation surface, that is, the half-cut (HC), and Fig. 3-59 (middle) shows that the cracks have reached laser irradiation bottom surface, that is, the bottomside half-cut (BHC). Figure 3-59 (bottom) shows crack propagation of the BHC case under tape expansion. Owing to the stress concentration at the crack tip, the wafer is easily separated into individual dies.

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g Wafer

Crack extension Tensile stress

Tape expansion

Cracks

Wafer

Tape Tape expansion

BHC

Crack extension Tensile stress Tape Tape expansion

Tape expansion

Crack has reached upper surface Wafer

Cracks

Tensile stress

Tape expansion

Tape

Tape expansion

FIGURE 3-59 Fundamental principles of crack extension.90–98

Figure 3-60 shows SEM images of a MEMS sensor device (2 × 2 × 300 mm) with a membrane structure that has been diced by the SD method. A hollow with a depth of several microns is constructed in the center of the chip, and the actual sensor device is formed on the opposite side of the chip. It can be seen that (1) there is no chipping, (2) there are sharp and clean dicing lines, and (3) there is no trace of damage or debris. Figure 3-61 shows the sidewalls of a MEMS sensor chip (after SD laser processing and tape expansion) provided by the Fraunhofer Institute78 on the European Downscaled Assembly of Vertically Interconnected Devices (DAVID) project. Again, it can be seen that (1) no material abrasion or ablation has occurred; (2) the method minimizes the contamination risk on the die surface; and (3) the method completely avoids edge chipping.

3.6.2

Dicing of SOI Wafers

Figure 3-62 shows the results of dicing wafers with a SOI layer by the SD method.69–77 One of the unique features of today’s SOI wafers is that they have a buried silicon oxide (buried oxide or box) layer extending across the entire wafer. By optimizing the laser and optical system, SD layers can be formed in the SOI layer, box layer, and silicon layer, as shown in Fig. 3-62 for a MEMS sensor wafer. It can be seen from the SEM images that the wafer is (1) chip-free, (2) dust-particle-free, (3) with sharp surfaces, and (4) without damage to the fragile structure.

129

130

Chapter Three

1000 μm

100 μm

FIGURE 3-60 SEM images of chip cut with SD technology.90–98

3.6.3

Dicing of Silicon-on-Silicon Wafers

Figure 3-63 shows photographs and an SEM image of a diced silicon-onsilicon bonded wafer separated by the SD method. Similar results to those with SOI wafers have been achieved. DISCO has developed a new laser machine (DFL7340/7360) that uses the SD technology developed by Hamamatsu Photonics as a dicing solution for MEMS wafers and thin wafers.69–77

3.6.4

Dicing of Silicon-on-Glass Wafers

For silicon-on-glass wafers, it is very difficult to form the SD layer (internal transformation) inside the glass wafer with the laser. A new MEMS dicing method for glass wafers has been reported by the MEMS

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g

50 μm

500 × 20 mm 21.8.08 9:20:41 10 kV

FIGURE 3-61 SEM image of a MEMS chip after stealth dicing.99

SOl layer Box layer

Laser 50 μm

Box layer

Si layer

25 μm

SOl layer cross section

SOI layer

85 μm 3 μm

SOl layer surface quality

500 μm Tape expansion

Si layer 100 μm

No damage to sensor

50 μm

Wafer cross section

SEM image

FIGURE 3-62 SOI wafer diced by SD technology.90–98

131

132

Chapter Three SiO2

SiO2

.5 μm

Si layer SiO2

300 μm .5 μm 300 μm

Si layer

SiO2

50 μm SiO2 layer surface quality

FIGURE 3-63 Dicing of silicon-on-silicon wafers with the SD technology.90–98

project from the New Energy and Industrial Technology Development Organization (NEDO) of Japan.79 There are two process steps. The first is to form the international transformation, and the second is to separate the wafer by a CO2 laser–induced thermal stress. Unlike the SD method, whose internal transformation of silicon is based on the thermal effect of single-photon absorption, the new method’s internal transformation of glass is based on multiphoton absorption and thus a shorter-pulse-width (10 ns and 100 fs) laser with a high peak intensity. For separation of a glass wafer into individual chips, a 25-W CO2 laser with a wavelength of 10.6 μm is used, and the laser radiation is absorbed by the SiO2 and suitable for a local heat source in the glass. Figure 3-64a shows the dicing results of a silicon (300 μm) on Pyrex-glass

Glass/Si (3 mm × 3 mm)

Internal modification 100 μm

FIGURE 3-64 Dicing of a silicon-on-glass wafer.100

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g (300 μm) bonded wafer, and Fig. 3-64b shows a MEMS package consisting of a (100-μm-thick) silicon and (500-μm-thick) Pyrex-glass wafer. It can be seen that (1) the dicing lines follow the internal transformation, (2) the edges are sharp, (3) it is chip-free, and (4) neither debris nor damage is found. It should be pointed out that the contamination on the surface is formed during the MEMS processing and is not due to the dicing.

3.7

RoHS-Compliant MEMS Packaging In this section, the EU RoHS directive will be presented first. It should be emphasized that the information provided herein is intended to be of assistance to exporters who ship their products with MEMS devices and packages anywhere in the world, especially EU countries. While every effort has been taken to ensure the accuracy of the information presented here, given the dynamic nature of such information, special attention should be paid to the latest announcements/publications by the governments of the EU countries and especially the EU Commission. The impacts of RoHS, such as lead-free-solder joint reliability, on MEMS packaging will be presented later.

3.7.1 EU RoHS Since February 13, 2003, the Restriction of the Use of Certain Hazardous Substances (RoHS) directive has been law in the European Union (EU),80 and it was implemented on July 1, 2006. It bans lead (Pb), mercury (Hg), cadmium (Cd), hexavalent chromium (Cr6+), and two types of brominated flame retardants, polybrominated biphenyls (PBBs) and polybrominated diphenyl ethers (PBDEs). This means that all electrical and electronic equipment (EEE), except those with exemptions,80–88 cannot be put on the EU market if they contain any of those six banned materials. A list of products (the categories of EEE) that covered by the EU RoHS directive is shown in the Annex of Waste Electrical and Electronic Equipment (WEEE) directive.89 1. Large household appliances 2. Small household appliances 3. Information technology and telecommunications equipment 4. Consumer equipment 5. Lighting equipment 6. Electrical and electronic tools (with the exception of largescale stationary industrial tools) 7. Toys and leisure and sports equipment 10. Automatic dispensers It should be pointed out that as of today, category 8 (i.e., medical devices, with the exception of all implanted and infected products)

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Chapter Three and category 9 (i.e., monitoring and control instruments), which covered by the WEEE directive, are not covered by the RoHS directive.

3.7.2 What Is the Definition of X-Free (e.g., Pb-Free)? The maximum concentration value (MCV) of those six banned materials permitted in “homogeneous materials” of EEEs has been published in the Official Journal of the EU and become a law on August 18, 2005.90 The journal stated: “For the purposes of Article 5(1)(a), a MCV of 0.1 percent by weight in homogeneous materials for lead, mercury, hexavalent chromium, polybrominated biphenyls (PBBs), and polybrominated diphenyl ethers (PBDEs) and of 0.01 percent by weight in homogeneous materials for cadmium shall be tolerated.” In plain language, lead-free is defined as a content of lead in all (individual) homogeneous materials of an EEE that is less than 0.1 wt %.

3.7.3 What Is a Homogeneous Material? According to the EU Commission’s guidance, homogeneous materials are as follows.91 1. Homogeneous material means a material that cannot be mechanically disjointed into different materials. 2. The term homogeneous means “of uniform composition throughout.” Examples of homogeneous materials include individual types of plastics, ceramics, glass, metals, alloys, paper, board, resins, and coatings. 3. The term mechanically disjointed means that the materials can, in principle, be separated by mechanical actions such as unscrewing, cutting, crushing, grinding, and abrasive processes. Some EU Commission examples of the application of this guidance91 include 1. A plastic cover is a homogeneous material if it consisted exclusively of one type of plastic that was not coated with or has attached to it or inside it any other kinds of materials. In this case, the MCV of the RoHS directive would apply to the plastic. 2. An electrical cable that consisted of metal wires surrounded by nonmetallic insulation materials is an example of a nonhomogeneous material because the different materials could be separated by mechanical processes. In this case, the MCV of the RoHS directive would apply to each of the separated materials individually. 3. A semiconductor package contains many homogeneous materials, which include the plastic molding material, the tinelectroplating coatings on the lead frame, the lead-frame alloy, and the gold-bonding wires.

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g

3.7.4 What Is the TAC? There are 27 members of the Technical Adaptation Committee (TAC) of the EU. Each member represents her or his own member state (country). They have the utmost power because their role is to provide technical changes and exemptions, as well as interpretation of the EU RoHS directive. (Thus, if you are not clear about some specific MEMS packaging issue of a product to be shipped into a particular country, you can ask a TAC member, and the contact information for each is listed on his or her country’s Web site.) TAC members report to the EU Commissioner. All of them receive the same information from the Commissioner, but they don’t have the same voting power. The votes from some member states (e.g., the United Kingdom and Germany) will carry more weight than that of others (e.g., Greece and Ireland).

3.7.5

How Is a Law Published in the EU RoHS Directive?

After the TAC’s yes vote on an item (usually exemption), the EU Commissioner will consult with the Parliament and Council. If the Parliament agrees, then the Commissioner will sign the ruling and publish it in the Official Journal of the EU, and it becomes a law.

3.7.6

EU RoHS Exemptions

One of the key implementation methods of the EU RoHS directive is by exemptions,80–88 which many thousands of products have relied on (i.e., exemption from the RoHS directive). Companies from all over the world are entitled to apply for exemptions as long as they have enough supporting data. With the recommendations of consultants such as ERA Technology (in the United Kingdom) and the Oko Institute (in Germany), the TAC will vote on the exemptions and report the voting result to the EU Commissioner. At present, there are 32 exemptions, and they are as follows: 1. Mercury in compact fluorescent lamps not exceeding 5 mg per lamp 2. Mercury in straight fluorescent lamps for general purposes not exceeding halophosphate, 10 mg; triphosphate with normal lifetime, 5 mg; and triphosphate with long lifetime, 8 mg 3. Mercury in straight fluorescent lamps for special purposes 4. Mercury in other lamps not specifically mentioned in this Annex 5. Lead in glass of cathode-ray tubes, electronic components, and fluorescent tubes 6. Lead as an alloying element in steel containing up to 0.35 percent lead by weight, aluminium containing up to 0.4 percent lead by weight, and as a copper alloy containing up to 4 percent lead by weight

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Chapter Three 7. Lead in high-melting-temperature solders (i.e., lead-based alloys containing 85 percent by weight or more lead); lead in solders for servers; storage and storage array systems; and network infrastructure equipment for switching, signaling, transmission, and network management for telecommunications; lead in electronic ceramic parts (e.g., piezoelectronic devices) 8. Cadmium and its compounds in electrical contacts and cadmium plating, except for applications banned under Directive 91/338/EEC amending Directive 76/769/EEC relating to restrictions on the marketing and use of certain dangerous substances and preparations 9. Hexavalent chromium as an anticorrosion agent for carbon steel cooling systems in absorption refrigerators a. Deca-BDE in polymeric applications b. Lead in lead-bronze bearing shells and bushes 10. Within the procedure referred to in Article 7(2), the Commission shall evaluate the applications for: Deca-BDE; mercury in straight fluorescent lamps for special purposes; lead in solders for servers, storage and storage array systems, network infrastructure equipment for switching, signaling, transmission, and network management for telecommunications (with a view to setting a specific time limit for this exemption), and light bulbs as a matter of priority in order to establish as soon as possible whether these items are to be amended accordingly 11. Lead used in compliant pin connector systems 12. Lead as a coating material for a thermal conduction module C-ring 13. Lead and cadmium in optical and filter glass 14. Lead in solders consisting of more than two elements for connection between the pins and the package of microprocessors with a lead content of more than 80 percent and less than 85 percent by weight 15. Lead in solders to complete a viable electrical connection between semiconductor die and carrier within integratedcircuit flip-chip packages 16. Lead in linear incandescent lamps with silicate-coated tubes 17. Lead halide as radiant agent in high-density discharge (HID) lamps used for professional reprography applications 18. Lead as an activator in the fluorescent powder (1 percent lead by weight or less) of discharge lamps when used as tanning

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g lamps containing phosphors such as BaSi2O5:Pb (BSP), as well as when used as specialty lamps for diazoprinting reprography, lithography, insect traps, and photochemical and curing processes containing phosphors such as (Sr, Ba)2MgSi2O7: Pb (SMS) 19. Lead with PbBiSn-Hg and PbInSn-Hg in specific compositions as the main amalgam and with PbSn-Hg as an auxiliary amalgam in very compact energy saving lamps (ESLs) 20. Lead oxide in glass used for bonding front and rear substrates of flat fluorescent lamps used for liquid-crystal displays (LCDs) 21. Lead and cadmium in printing inks for the application of enamels on borosilicate glass 22. Lead as impurity in rare earth iron-garnet (RIG) Faraday rotators used for fiberoptic communications systems 23. Lead in finishes of fine-pitch components other than connectors with a pitch of 0.65 mm or less with NiFe lead frames and lead in finishes of fine-pitch components other than connectors with a pitch of 0.65 mm or less with copper lead frames 24. Lead in solders for the soldering of machined through-hole discoidal and planar array ceramic multilayer capacitors 25. Lead oxide in plasma display panels (PDPs) and surfaceconduction electron emitter displays (SEDs) used in structural elements, notably in the front and rear glass dielectric layer, the bus electrode, the black stripe, the address electrode, the barrier ribs, the seal frit and frit ring, and print pastes 26. Lead oxide in the glass envelope of black-light-blue (BLB) lamps 27. Lead alloys as solder for transducers used in high-powered (designated to operate for several hours at acoustic power levels of 125 dB SPL and above) loudspeakers 28. Hexavalent chromium in corrosion-preventive coatings of unpainted metal sheetings and fasteners used for corrosion protection and electromagnetic interface shielding in equipment falling under category 3 of Directive 2002/96/EC (IT and telecommunications equipment) (Exemption granted until 1 July 2007.) 29. Lead bound in crystal glass as defined in Annex I (categories 1, 2, 3, and 4) of Council Directive 69/493/EEC 30. Cadmium alloys as electrical/mechanical solder joints to electrical conductors located directly on the voice coil in transducers used in high-powered loudspeakers with sound pressure levels of 100 dB(A) and more

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Chapter Three 31. Lead in soldering materials in mercury-free flat fluorescent lamps (which, for example, are used for LCDs and design or industrial lighting) 32. Lead oxide in seal frits used for making window assemblies for argon and krypton laser tubes

3.7.7 Current Status of RoHS Compliance in the Electronics Industry Since 2000, the electronics industry has spent billions of dollars on compliance with the RoHS directive. More than 95 percent of the effort has been directed at eliminating lead (Pb), that is, creating lead-free materials, developing soldering process, performing characterization measurements, and reliability assessments, etc. The eutectic SnPb solder (63 wt % Sn and 37 wt % Pb), with a melting point of 183°C, has been the predominant choice for assembling electronics products for decades owing to its outstanding solderability and reliability. Unfortunately, because of the RoHS directive, Pb is banned in most electronics products that include MEMS components/modules. Not long ago, there were more than 100 lead-free solder alloys to be chosen from, as shown in Table 3.1 of ref. 92. However, because of the very tight regulatory deadlines, the industry has “rushed” to select SnAgCu solder alloys and is “in a great hurry” to build the infrastructure around the Sn(1 to 4 wt %)Ag(0.5 to 0.7 wt %)Cu lead-free solder family. The melting point of these solders is around 217°C, which is 34°C higher than that of SnPb solder. Thus, during assembly, the components (including MEMS) and PCBs will be subjected to higher soldering temperatures, and their cost, performance, and reliability are of great concern to manufacturers.92–129 Higher energy consumption is another concern.98 Owing to a lack of experimental and simulation data, one of the critical issues of lead-free soldering is solder-joint reliability, especially for high-reliability (>10 years of life) products. As discussed earlier, MEMS packaging consists of solder materials for sealing, die attachment, solder bumps, and/or solder balls. Thus the solder-joint reliability of MEMS packages is under scrutiny.

3.7.8

Lead-Free Solder-Joint Reliability of MEMS Packages

A number of environmental stress factors [e.g., temperature, voltage, humidity, corrosion, current density (electromigration), and mechanical loads) may lead to MEMS lead-free solder sealing-ring and/or solder-joint failure. The most commonly failure modes in practice are overload and fatigue.97,119 Overload failure occurs whenever the stress in a MEMS solder joint, brought about by the imposed stress factors, is greater than the capacity of the solder material. An example would be excessive bending and twisting of a PCB with a solder-bumped ASIC/MEMS chip

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g or PBGA package housing a MEMS device soldered to its surface. In this case, the bending and twisting stresses are larger than the strength or fracture toughness of the lead-free solder material. Fatigue failure takes place via the initiation and propagation of a crack until it becomes unstable. The stress factors that typically cause failure by fatigue are far below the overload failure levels. Examples of fatigue failure include the temperature cycling and/or vibration of a solder-bumped chip, chip scale package (CSP), or ball grid array (BGA) package that is soldered to the surface a PCB. This section will consider both the temperature and drop fatigue stress factors.

Definition of Reliability Reliability of a solder joint of a particular package (e.g., MEMS) in electronic products is defined as the probability that the solder joint will perform its intended function for a specified period of time under given operating conditions without failure.97,119 Numerically, reliability is the percent of survivors; that is, R(t) = 1 – F(t), where R(t) is the reliability (survival) function and F(t) is the cumulative distribution function (CDF). Life distribution is a theoretical population model used to describe the lifetime of a solder joint and is defined as the CDF, that is, F(t), for the solder-joint population. Thus the one and only way to determine solder-joint reliability is by reliability testing.

Objective of Reliability Tests The objective of reliability tests is to obtain failures (the more the better) and to best fit the failure data to (determine the parameters of) the CDF of a chosen probability distribution (e.g., Weibull). The number of items (i.e., sample size) to be tested should be such that the final data are statistically significant. The reliability test time is unknown but usually takes a while (e.g., a few months). It should be noted and emphasized that as soon as the life distribution F(t) of the lead-free solder joint of a particular package with a certain chip size is estimated by reliability testing, the reliability R(t), failure rate, cumulative failure rate, average failure rate, mean time to failure, etc. of the lead-free solder joints are readily determined.97 Most reliability tests are accelerated tests (with increased intensity of exposure to aggressive environmental conditions and realistic sample sizes and test times). Thus acceleration models are needed to transfer the failure probability, reliability function, failure rate, and mean time to failure from a test condition to an operating condition. In establishing the acceleration models for lead-free solder joints, their surrounding materials (e.g., solder, molding plastic, ceramic, copper, fiber-reinforced glass epoxy, and silicon), loadings (e.g., stress, strain, temperature, humidity, current density, and voltage), and failure mechanisms and modes (e.g., overload, fatigue, corrosion, and electromigration) must be considered.

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Reliability Test Methods Some common tests for solder joints include • Temperature cycling tests (e.g., –40 to 125°C) • Power cycling tests (depends on devices) • Functional cycling tests (depends on devices) • High/low-temperature storage tests (120°C/–20°C) • Biased 85/85 tests (e.g., 85°C/85 %RH, 1.8 V) • High-voltage extended-life tests (e.g., 100°C, 1.8 V) • Pressure-cook tests (autoclave tests) (e.g., 121°C, 2 atm) • Salt-atmosphere tests (MIL-STD-883D) • Moisture-sensitivity tests (e.g., IPC/JEDEC-020C) • Shock (drop) tests (e.g., 1.3- to 1.5-mm drops) • Vibration tests (e.g., random vibration) • Mechanical bending, shearing, and twisting tests (e.g., IPC/ JEDEC-9702) • Electromigration tests (e.g., see ref. 129) • Others For solder-joint reliability, most of these tests, in general, are very expensive and time-consuming. Thus, before and after reliability testing, design for reliability (DFR) and failure analysis (FA) have been very useful and important tools for solder-joint reliability.

Reliability Engineering of Solder joints Figure 3-65 shows the concept of reliability engineering of solder joints.97,119 It consists of three major tasks, namely, DFR, reliability testing and data analysis, and FA. Usually, the procedure starts with a design of the solder joints of a MEMS package with the given MEMS device size and package, the solder alloys, and the corresponding PCB and demonstrates that the design is electrically, thermally, and mechanically sound. As an example, the DFR activity is often performed with a finite-element simulation using the material properties of all the structural elements and the imposed boundary conditions. The next step in the process is for a certain number of samples of the sound or reliable design to be built and tested under certain conditions for a certain period of time. The test data (failures) then are analyzed and fitted into a life-distribution (or reliability) designation for the solder joints. Failure analysis (FA) then should be done on the failed samples to find out the root cause and understand the reason for their failure. This information is very useful for

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g

• Eliminate trial-anderror of reliability tests • Reduce cost • Reduce design/test/FA cycles

• Provide insight into the physical, chemical, electrical, mechanical, and thermal behaviors of the structure • Provide failure locations, failure modes, and failure mechanisms

Design for reliability

• Sample size

• Verify the reliability test data

• Test condition

Reliability engineering

• Test period • Obtain failures • Life distribution

Reliability test & data analysis

• Verify the DFR analysis results Failure analysis

• Reliability function • Failure rate • Mean time to failure

• Understand why it failed and how to fix it or do better for the next round of DRF and reliability test • Choose acceleration models to determine the acceleration factors

FIGURE 3-65 Reliability engineering.

1. Providing the failure locations, failure modes, and failure mechanisms 2. Verifying the reliability-test data 3. Verifying the DFR simulation results 4. Understanding why the sample failed and how to fix it (or to do better) 5. The next round of DFR and reliability testing 6. Choosing acceleration models to determine the acceleration factors because most of the reliability tests are naturally “accelerated” Some common methods for solder-joint FA are • Visual inspection • X-ray inspection • A-, B-, and C-mode scanning acoustic microscopy (SAM) • Dye and pry • Cross-sectioning • High-power microscopy • Scanning electron microscopy (SEM) • Focused ion beam (FIB) and SEM

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Chapter Three • X-ray diffraction (XRD) • Transmission electron microscopy (TEM) • Energy-dispersive x-ray spectrometry (EDX) • Tomographic acoustic microimaging (TAMI) • Others It should be noted and emphasized that the reliability obtained from DFR is not the same as the reliability (probability) obtained from reliability tests. For example, the life (number of cycles to failure) of a solder joint from reliability tests depends on the percent failed (or survived). Statistically, there are an infinite number of possible lives; for example, the characteristic life corresponds to 63.2 percent failed (or 36.8 percent survived). On the other hand, the best we can do from DFR is to predict a (one) life of the solder joint for a given boundary condition. As another example, the failure rate (i.e., the number of solder joints that failed in the first year, second, third, etc. year) can be determined from the reliability test. However, the DFR does not even know what failure rate means. In the past 2 decades, with the advancement of computers, DFR of solder joints has become as important as the reliability test. Even though it cannot predict solder-joint reliability, failure rate, mean time to failure, etc., DFR is usually performed by a mathematical modeling based on the material properties of the structure and laws of engineering and physics in order to 1. Eliminate trial-and-error reliability tests 2. Reduce cost 3. Reduce design/test/FA cycles 4. Reduce time to market 5. Provide insight into the physical, chemical, electrical, mechanical, and thermal behaviors of solder joints (e.g., the maximum stress/strain locations) to help test-board designs to capture the most likely (solder-joint) failure locations and to help FA to find these failures sites

Material Properties of Lead-Free Solders for MEMS Packaging In order to perform DFR and fully understand the engineering physics of solder-joint reliability, the material properties of solders must be known (through tests) and understood. Some important material properties of solders are • Phase-transition temperatures (i.e., solidus, liquidus, plastic, and eutectic) • Melting point

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g • Boiling point • Softening point • Hardness • Density • Dispensability • Glass-transition temperature • Coefficient of thermal expansion • Vapor pressure • Surface tension • Storage modulus • Loss modulus • Viscosity • Miscibility • Electrical conductivity • Thermal conductivity • Stress-strain curves • Shear strength • Tensile strength • Ultimate strength • Elongation • Yield strength • Young’s modulus • Poisson’s ratio • Creep curves • Stress-relaxation curves • Creep rates • Creep rupture • Fracture toughness • Viscoelasticity • Viscoplasticity • Fatigue strength • Isothermal fatigue curves • Fatigue crack-growth curves • Moisture absorption • Others

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Young’s modulus, GPa

Chapter Three 60 95.5Sn-3.9Ag-0.6Cu 40 SnPb

20

0 0

50

100

150

200

Temperature, °C

FIGURE 3-66 Young’s modulus of lead-free and tin-lead solders.

For example, the Young’s modulus of the lead-free (SAC) and tin-lead (Sn-Pb) solder alloys is shown in Fig. 3-66.109 The figure shows that the modulus of the lead-free solder alloy is larger than that of the Sn-Pb solder alloy. Therefore, for a given structural geometry and boundary condition, one should expect higher stresses in the leadfree solder joints compared with the Sn-Pb eutectic solder joints. For another example, the creep responses of SAC and Sn-Pb solders at 50°C are presented in Fig. 3-67.110 The figure shows that the Sn-Pb solder has a creep rate that is greater than that of the SAC solder. As a result, for a given structural geometry and boundary condition, the Sn-Pb solder joints should have both a faster creep response and higher creep strains. The cost, performance, quality, and reliability of solder joints will be affected by the preceding materials properties (>35) of the solder that forms the joints. However, it should be reemphasized that the reliability of solder joints cannot be determined by the materials properties of the solder but rather by reliability tests.

Tensile creep strain rate, 1/s

144

1.0E-04 1.0E-05 1.0E-06 1.0E-07 1.0E-08 1.0E-09 1.0E-10 1.0E-11 1.0E-12 1.0E-13

50°C

Sn-Pb SAC 1

10 Tensile stress, MPa

100

FIGURE 3-67 Tensile creep-strain rate for SAC and Sn-Pb solder alloys at 50°C.

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g 1200 1064.43

1000

Lower-melting point (217°C) eutectic Au90wt%Sn. Flux is needed unless use expansive process, e.g., pressure, plasma, …

Liquid 800 °C

600

Au

Fluxless Au20wt%Sn (280°C) eutectic

532

519

419.3

400 ζ

β

280°C

276 29 190

200

72

309 50.5

252

18.5

231.97 η

217

93.7 βSn

10

0

δ

ζ’

13 ε

αSn

–200 0 Au

10

20

30

40 50 60 Atomic percent, Sn

70

80

90

100 Sn

FIGURE 3-68 Au-Sn solder phase diagram.

AuSn for MEMS Packaging Au-Sn solders are especially suited for MEMS packaging. Most of the MEMS devices have to be soldered in a fluxless process, which is possible using Au-Sn solders, as shown in the phase diagram in Fig. 3-68. Also, most of the manufacturing processes for the cap wafer and the ASIC wafer already include Au plating, which makes the use of Au-Sn solders attractive. Furthermore, 80 wt % Au–20 wt % Sn solder is used widely because of its advantages, namely, high strength, high corrosion resistance, and high fatigue resistance. Thus the Au20Sn solder system is usually selected as the sealing material for MEMS (cap-waferto-ASIC-wafer bonding) applications.

Au-Sn Solder Lift-Off Process Au-Sn solder can be manufactured by various methods, such as evaporation, electrodeposition, paste and solder preform. Among these methods, evaporated solder allows more accurate control of dimensions and positions. Therefore, after under-bump metallurgy (UBM) patterning, a sequence of Sn-Au layers (in total, eight layers of Sn and eight layers of Au) is evaporated and simultaneously patterned by a lift-off process. The thickness of each Sn and Au layer is 0.2 and 0.24 μm, respectively. The evaporation is done in a Temescal E-Beam Evaporator (Model VES-2550) from Semicore Equipment, Inc. The evaporation rate is 5 Å/s. During the lift-off process, a 20-μm-thick dry film is used as a mold.

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W2W Au-Sn Solder Bonding After the formation of all the solder layers, wafer-level bonding is conducted to bond the cap wafer and the ASIC wafer. The bonding is carried out at 350°C with a 15-minute dwell at peak temperature and a compressive pressure of 4.7 MPa. After bonding, the W2W-bonded wafer is diced into individual stacks for shear testing, which shows that the shear strength of the bonding is higher than 27.2 MPa. (In this case, the spec is 6 MPa.) Of course, the W2W bonding also can be performed with low-temperature solders, as mentioned in Sec. 2.5.4.

Quality of Lead-Free Solder Joints During lead-free process development and manufacturing, the following tests usually are performed: • Wetting balance test • Solder-spreading test • Solderability test • Cleanability test • Printability test • Temperature-profiling test • Surface-insulation-resistance (SIR) test • Automated optical inspection (AOI) test • X-ray inspection test • In-circuit test (ICT) • Functional test • Shear test • Pull test • Bend tests • Others These tests are very useful for developing the assembly process and for improving manufacturing yield. Thus these tests will enhance and ensure the quality of the solder joints. However, these tests cannot determine solder-joint reliability, which has to be obtained by reliability tests.

Reliability Test of Lead-Free MEMS PBGA Solder Joints Figure 3-69 shows a very typical Weibull probability plot from the thermal-cycling reliability test results of Sn3Ag0.5Cu (SAC) lead-free solder joints. In this case, it is for a 256-pin plastic ball-grid array (PBGA) package as shown in Figs. 2-45, 2-46, and 2-47 in Chapter 2. It can be seen that for the test samples, at 2000 cycles (–25 to 125°C, one cycle per hour), 6 percent of the PBGA solder joints have failed, and 94 percent have survived, that is, the reliability is 0.94.

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g 90.00 Sample size = 20

50.00

Percent failed, F (x)

Median rank No. of failures = 16

10.00 5.00

Weibull slope β = 2.8 1.00 Characteristic life θ = 5466 cycles

0.50 β1 = 2.7750, η1 = 5465.7692, ρ = 0.9936

0.10 1500.00

John Lau Agilent

6000.00 Cycles to failure (x)

FIGURE 3-69 Thermal-cycling test of lead-free 256-pin PBGA package on a PCB (–25 to 125°C, one cycle per hour).

Figure 3-70 shows the life distribution of the lead-free PBGA at 90 percent confidence. At 90 percent confidence for a given 256-pin PBGA lead-free solder joint, that is, in 90 of 100 cases, the true characteristic life θt of the 256-pin PBGA lead-free solder joint will happen within the interval 4480 ≤ θt ≤ 6021 cycles. At the same time, it can be shown that the true mean life (which occurs at 51 percent failed) μ of the PBGA lead-free solder joints, in 90 of 100 cases (i.e., at 90 percent confidence), can be as low as 3822 cycles and as high as 4865 cycles, that is, 3822 ≤ μ ≤ 4865 cycles. The higher the required confidences, the wider are the life intervals. From solder-joint-uniformity points of view, for example, the true Weibull slope can be estimated from determination of the Weibull slope error E, which depends on the number of failures N and the required confidence C, as reported in refs. 100, 117, 119, 120, and 122. For example, in the present case, there are 16 failures (N = 16), and the required confidence is 90 percent (C = 0.9); then E = 30 percent.100,117,119,120,122 Thus the true Weibull slope βt of the 256-pin PBGA lead-free solder joint can be at least 1.95 but not more than 3.61, that is, 1.95 ≤ βt ≤ 3.61. Now you have done your reliability tests and data analysis properly and have obtained the life distribution, reliability function, failure rate, mean time to failure, etc., so what? How do you apply these test results to your products under operating conditions? What are the acceleration factors of lead-free solder joints under, for example, thermal, mechanical, shock and vibration, electromigration, and corrosion

147

Chapter Three 90.00 Sample size = 20

50.00 95% rank Percent failed, F (x)

148

No. of failures = 16

10.00 Sample weibull Slope β = 2.8

5.00 50% rank

5% rank Sample Characteristic life θ = 5466 cycles

1.00 0.50 β1 = 2.7750, η1 = 5465.7692, ρ = 0.9936 β2 = 4.1568, η2 = 6020.5530, ρ = 0.9908 β3 = 2.0446, η3 = 4480.3343, ρ = 0.9830

0.10 1500.00

John Lau Agilent

6000.00 Cycles to failure, (x)

FIGURE 3-70 Lead-free 256-pin PBGA with 90 percent confidence (–25 to 125°C, 1-hour thermal cycle).

conditions? What are the field failure data of lead-free solder joints to verify the acceleration models? The industry is still working very hard in these areas. In many situations, the qualities and uniformities of two products (e.g., two sets of solder joints) are to be compared based on knowledge of limited test data. One of the difficult tasks in reliability life testing is to draw conclusions about a population from a small sample size, as shown in preceding sections. It is even more difficult to compare the populations of two sets of solder joints (e.g., lead-free and tin-lead) based on knowledge of their limited test data. If one set of solder joints is found to be superior to another, how confident can one be that the same is true of their populations? (A simple equation reported in refs. 100, 117, 119, 120, and 122 can be used to determine this confidence, which is not the same as the required confidence discussed in preceding sections.) Now you have done the reliability tests of lead-free and tin-lead solder joints under the same test conditions and have determined that one is better than the other with very high confidence, so what? How do you know that it is also true at operating considerations such as thermal, mechanical, electromigration, corrosion, humidity, current density, shock, and vibration conditions? Again, the industry is still working very hard in these areas. Maybe another $5 billion of efforts will do it!

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Chapter Three 84. Commission Decision. “Amending for the Purposes of Adapting to the Technical Progress the Annex to Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of the Use of Certain Hazardous Substances (RoHS) in Electrical and Electronic Equipment (EEE).” Official J. European Union, April 28, 2006, pp. L 115/38–39. 85. Commission Decision. “Amending for the Purposes of Adapting to the Technical Progress the Annex to Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of the Use of Certain Hazardous Substances (RoHS) in Electrical and Electronic Equipment (EEE).” Official J. European Union, October 14, 2006, p. L 283/47. 86. Commission Decision. “Amending for the Purposes of Adapting to the Technical Progress the Annex to Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of the Use of Certain Hazardous Substances (RoHS) in Electrical and Electronic Equipment (EEE).” Official J. European Union, October 14, 2006, p. L 283/48. 87. Commission Decision. “Amending for the Purposes of Adapting to the Technical Progress the Annex to Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of the Use of Certain Hazardous Substances (RoHS) in Electrical and Electronic Equipment (EEE).” Official J. European Union, October 14, 2006, pp. L 283/50–51. 88. Commission Decision. “Amending for the Purposes of Adapting to the Technical Progress the Annex to Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of the Use of Certain Hazardous Substances (RoHS) in Electrical and Electronic Equipment (EEE).” Official J. European Union, May 24, 2008, pp. L 136/9–10. 89. European Parliament and Council of the European Union. “Directive 2002/96/EC on Waste Electrical and Electronic Equipment (WEEE).” Official J. European Union, February 13, 2003, pp. L 37/24–38. 90. Commission Decision. “Amending Directive 2002/95/EC of the European Parliament and of the Council for the Purpose of Establishing the Maximum Concentration Values for Certain Hazardous Substances in Electrical and Electronic Equipment (EEE).” Official J. European Union, August 19, 2005, p. L 214/65. 91. TAC Report. “RoHS Enforcement Guidance Document,” Version 1, UK, May 2006, pp. 13–14. 92. Lau, J. H. Low-Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies. New York: McGraw-Hill, 2000. 93. Lau, J. H., Wong, C. P., Prince, J. L., and Nakayama, W. Electronic Packaging: Design, Materials, Process, and Reliability. New York: McGraw-Hill, 1998. 94. Lau, J. H., and Lee, R. Chip Scale Package. New York: McGraw-Hill, 1999. 95. Lau, J. H., and Lee, R. Microvias for Low Cost, High Density Interconnects. New York: McGraw-Hill, 2001. 96. Lau, J. H., Wong, C. P., Lee, N. C., and Lee, R. Electronics Manufacturing with Lead-Free, Halogen-Free, and Conductive Adhesive Materials. New York: McGraw-Hill, 2003. 97. Lau, J. H., and Pao, Y. H. Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies. New York: McGraw-Hill, 1997. 98. Geiger, D., Shangguan, D., and Yi, S. “Thermal study of lead-free reflow soldering processes.” In Proceedings of the 3rd IPC/JEDEC Annual Conference on Lead-Free Electronic Assemblies and Components, San Jose, CA, 2003, pp. 95–98. 99. Lau, J. H., Harkins, G., Rice, D., Kral, J., and Wills, B. “Experimental and statistical analysis of surface-mount technology PLCC solder-joint reliability.” IEEE Transactions of Reliability 37:524–530, 1988. 100. Lau, J. H. “Reliability Testing and Data Analysis,” workshop at the NEPCON West, Anaheim, CA, February 1990. 101. Tu, K. N. “Recent advances on electromigration in very-large-scale-integration of interconnects.” J. Appl. Phys. 94:5451–5473, 2003.

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g 102. Lau, J. H., Mei, Z., Pang, S., Amsden, C., Rayner, J., and Pan, S. “Creep analysis and thermal-fatigue life prediction of the lead-free solder sealing ring of a photonic switch.” ASME Trans. J. Electron. Packag. 124:403–410, 2002. 103. Lau, J. H., and Lee, R. “Modeling and analysis of 96.5Sn-3.5Ag lead-free solder joints of wafer level chip scale package (WLCSP) on “build-up microvia printed circuit board.” IEEE Trans. Electron. Packag. Manufact. 25:51–58, 2002. 104. Lau, J., Dauksher, W., Smetana, J., Horsley, R., Shangguan, D, Castello, T., Menis, I., Love, D., and Sullivan, B. “Design for lead-free solder joint reliability of high-density packages.” J. Solder. Surface Mount Technol. 16:12–26, 2004. 105. Lau, J. H., and Dauksher, W. “Reliability of an 1657CCGA (ceramic column grid array) package with 96.5Sn3.9Ag0.6Cu lead-free solder paste on PCBs (printed circuit boards).” ASME Trans. Electron. Packag. 127:96–105, 2005. 106. Lau, J., Hoo, N., Horsley, R., Smetana, J., Shangguan, D., Dauksher, W., Love, D., Menis, I., and Sullivan, B. “Reliability testing and data analysis of leadfree solder joints for high-density packages.” J. Solder. Surface Mount Technol. 16:46–68, 2004. 107. Lau, J., Shangguan, D., Castello, T., Horsley, R., Smetana, J., Dauksher, W., Love, D., Menis, I., and Sullivan, B. “Failure analysis of lead-free solder joints for high-density packages.” J. Solder. Surface Mount Technol. 16:69–76, 2004. 108. Lau, J. H. “Impacts of RoHS (e.g., Pb-Free) on Electronic Products,” workshop at the IPC/JEDEC 9th International Conference on Lead-Free Electronic Components and Assemblies, Singapore, August 17, 2005. 109. Lau, J. H., Dauksher, W., and Vianco, P. “Acceleration models, constitutive equations and reliability of lead-free solders and joints.” In IEEE Electronic Components and Technology Conference Proceedings, New Orleans, LA, June 2003, pp. 229–236. 110. Lau, J. H., and Dauksher, W. “Creep constitutive equations of Sn(3.5–3.9)wt %Ag(0.5–0.8)wt %Cu.” In Micromaterials and Nanomaterials, edited by B. Michel, pp. 54–62. Berlin: Fraunhofer Institute IZM, 2004. 111. Lau, J. H., Lee, R., Dauksher, W., Shangguan, D., Song, F., and Lau, D. “A systematic approach for determining the thermal fatigue-life of plastic ball grid array (PBGA) lead-free solder joints.” ASME Paper No. IPACK200573364, New York, July 2005. 112. Lau, J. H., Goh, S., Tay, G., Erasmus, S., Sporon-Fiedler, F., and Pan, S. “Characterization of bump chip carrier (BCC++) package assembly and solder joint reliability for fiber-optic transceiver applications.” IEEE Trans. Components Packag. Technol. 2009. 113. Lau, J. H., Lo, J., Lam, J., Soon, E., Chow, W., and Lee, R. “Effects of underfills on the thermal-cycling tests of SnAgCu PBGA (plastic ball grid array) packages on ImAg PCB (printed circuit board).”IEEE Trans. Adv. Packag. (in press). 114. Lau, J. H. “Thermal stress analysis of a flip-chip parallel VCSEL (verticalcavity surface-emitting laser) package with low-temperature lead-free (48Sn-52In) solder joints.” IEEE Trans. Adv. Packag. (in press). 115. Lau, J. H., Pang, J., Lee, N., and Xu, L. “Material properties and intermetallic compounds of a new lead-free solder: Sn3wt %Ag0.5wt %Cu0.019wt %Ce (SACC).” IEEE Trans. Adv. Packag. (in press). 116. Lau, J. H., Gleason, J., Schroeder, V., Henshall, G., Dauksher, W., and Sullivan, B. “Design, materials, and assembly process of high-density packages with a low-temperature lead-free solder (SnBiAg).” Solder. Surface Mount Technol. 20:11–20, 2008. 117. Lau, J. H., Gleason, J., Schroeder, V., Henshall, G., Dauksher, W., and Sullivan, B. “Reliability test and failure analysis of high-density packages assembled with a low-temperature lead-free solder (SnBiAg).” Solder. Surface Mount Technol. 20:21–29, 2008. 118. Lau, J. H., Castello, T., Shangguan, D., Dauksher, W., Smetana, J., Horsley, R., Love, D., Menis, I., and Sullivan, R. “Failure analysis of lead-free solder joints of an 1657CCGA (ceramic column grid array) package.” J. Microelectron. Electron. Packag. 4:189–213, 2007.

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Chapter Three 119. Lau, J. H. “Reliability of lead-free solder joints.” ASME Trans. Electron. Packag. 128:297–301, 2006. 120. Lau, J., and Dauksher, W. “Reliability of an 1657CCGA (ceramic column grid array) package with 96.5Sn3.9Ag0.6Cu lead-free solder pasties on PCBs (printed circuit boards). ASME Trans. Electron. Packag. 127:96–105, 2005. 121. Lau, J., Dauksher, W., Smetana, J., Horsley, R., Shangguan, D., Castello, T., Menis, I., Love, D., and Sullivan, B. “Design for lead-free solder joint reliability of high-density packages.” J. Solder. Surface Mount Technol. 16:12–26, 2004. 122. Lau, J. H., Tse, P., Richard, E., Dauksher, W., Shangguan, D., Pang, J. “Reliability of Sn3wt %Ag0.5wt %Cu0.019wt %Ce (SACC) solder joints.” In IEEE Electronic Components and Technology Conference Proceedings, San Diego, CA, May 2009, pp. 415–422. 123. Lau, J. H., Pang, J., Lee, N.-C., and Xu, L. ”Material properties and intermetallic compounds of a new lead-free solder: Sn3wt %Ag0.5wt %Cu0.019wt %Ce (SACC).” In IEEE Proceedings of Electronic Components and Technology Conference, Reno, NV, May 29–June 1, 2007, pp. 211–218. 124. Lau, J. H., Liu, S., Shangguan, D., Song, Z., and Geiger, D. “Process development and solder joint reliability of a new lead-free solder: Sn3wt %Ag0.5wt %Cu0.019wt %Ce (SACC).” In IEEE Proceedings of Electronics Packaging Technology Conference, Singapore, December 10–12, 2007, pp. 546–552. 125. Lau, J. H., Shangguan, D., Lau, D., Kung, T., and Lee, R. “Thermal-Fatigue Equation for Wafer-Level Chip Scale Package (WLCSP) Lead-Free Solder on Lead-Free Printed Circuit Board (PCB).” In IEEE Proceedings of Electronic Components and Technology Conference, Las Vegas, NV, June 1–4, 2004, pp. 1563–1569. 126. Lau, J. H., and Dauksher, W. “Thermal stress analysis of a flip-chip parallel VCSEL (vertical-cavity surface-emitting laser) package with low-temperature lead-free (48Sn-52In) solder joints.” In IEEE Proceedings of Electronic Components and Technology Conference, San Diego, CA, May 30–June 2, 2006, pp. 1009–1017. 127. Lau, J. H., Lee, R., Song, F., Lau, D., and Shangguan, D. “Isothermal fatigue tests of plastic ball grid array (PBGA) SnAgCu lead-free solder joints at 60°C.” In IEEE Proceedings of Electronic Components and Technology Conference, San Diego, CA, May 30–June 2, 2006, pp. 1476–1483. 128. Lau, J. H., and Dauksher, W. “Effects of ramp-time on the thermal-fatigue life of SnAgCu lead-free solder joints.” In IEEE Proceedings of Electronic Components and Technology Conference, Lake Buena Vista, FL, May 31–June 3, 2005, pp. 1292–1298. 129. Yu, D., Chai, T., Thew, M., Ong, Y., Rao, V., Wai, L., and Lau, J. H. “Electromigration study of 50 μm pitch micro solder bumps using four-point kelvin structure.” In IEEE Proceedings of Electronic Components and Technology Conference, San Diego, CA, May 2009, pp. 930–935.

CHAPTER

4

Advanced MEMS Wafer-Level Packaging 4.1

Introduction Microelectromechanical systems (MEMS) technology has been investigated widely and vigorously by the research community for various applications over the past few years. Key factors for commercial success in MEMS devices include cost, yield, and reliability. Wafer-level packaging offers advantages and limitations that are substantially different from those of conventional packaging technology. Wafer bonding and wafer-level encapsulation enable a sealed and protected cavity for suspended MEMS structures. Planar and vertical electrical interconnects are selectively prepared by using micromachining technology. The greatest promise of wafer-level packaging appears to lie in the functional areas of various MEMS sensors, radio frequency (RF) MEMS, and optical MEMS. Owing to its unique nature, low-temperaturesolder-based wafer bonding technology continues to evolve toward a mature and reliable solution for enabling wafer-level hermetic packaging for MEMS. Indeed, wafer-level packaging technology is now poised to offer significant improvements and merits over conventional technology in MEMS packaging. The packaging of MEMS devices is one of the most challenging parts of MEMS commercialization. MEMS devices typically consist of cavities and free-standing or even out-of-plane microstructures, whereas integrated circuits (ICs) do not. Given this major difference between MEMS and IC devices, packaging for MEMS devices must allow space for actuator movement, permit the sensing element to interact with the surroundings via a pathway, or provide a suitable ambient inside the package to achieve higher sensitivity or better reliability. Each particular kind of MEMS device requires a more customized and dedicated solution than just a standard solution that aims at

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Chapter Four packaging for all MEMS devices.1,2 In addition to the aforementioned issues, the common requirements for developing a MEMS package include protection of fragile structures, formation of electrical interconnects, manufacturability, and reliability. The main consideration in MEMS packaging is that the free-standing and fragile MEMS structures either have to be protected properly before the chip singulation step (e.g., saw dicing) or must be strong enough to withstand the saw-dicing step. Generally speaking, suitable technologies for MEMS packages typically need to provide sealing or encapsulation of MEMS structures and electrical feed-throughs and pathways for the MEMS device to interact with the ambient so as either to sense the change or to introduce a change. The huge markets for mobile phones and handheld devices for computing and amusement applications generate new high-volume markets for MEMS microphones, inertial sensors, and RF MEMS devices. All these applications require thin and small packaged devices. Wafer-level packages and wafer-level chip-scale packages have been used widely in the IC-packaging industry. Vertical interconnects and stacking chips are deployed as cornerstone technologies for system-ina-package (SiP) solutions for mass production of some commercially available ICs. The concept of SiP solutions actually can help in the development of MEMS packaging.3,4 While most SiP solutions have relied on wafer-level approaches, wafer-level approaches for enabling MEMS packaging also show advantages in many respects. This chapter surveys the progress of wafer-level MEMS packaging. Some potential future research subjects also will be discussed. Basically, wafer-level MEMS packaging involves major technology challenges in terms of methods of wafer bonding and the formation of electrical interconnections, as well as requirements for hermeticity and/or vacuum. Wafer-level approaches are preferred for MEMS packages because approaches at this stage are considered to be batch-type processes, and they typically protect the microstructures from the potential damage during the die-separation step. Besides, the know-good-die testing, die marking, and die separation can be done at the wafer level. Most of packaging and assembly steps for MEMS devices after that can be realized by leveraging the existing techniques in IC packaging. Thus the cost of packaging MEMS device is drastically reduced, whereas the packaging yield is apparently increased.

4.2

Micromachining, Wafer-Bonding Technologies, and Interconnects 4.2.1 Thin-Film Technologies The evolution and maturity of MEMS in recent years have been driven by continuous progress in fabrication facilities and process development.

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g Traditionally, there have been two types of micromachining: bulk and surface micromachining. With strong demand for the development of complicated three-dimensional (3D) optical MEMS applications, enormous efforts have gone into integration of multiple and mixed process technologies. Unique integrated process technologies come from combining steps based on bulk and surface micromachining, wafer-bonding technology, and basic semiconductor fabrication techniques. These semiconductor fabrication techniques are (1) thin-film deposition, (2) lithography, and (3) etching. Thin films are deposited using various chemical or physical techniques and are used for masking, insulation, and structural purposes. Subsequent to thin-film deposition, the lithography step is performed such that the designed patterns are transferred from the mask to the substrate. Then substrate with photoresist patterns is etched using various wet-chemical and dry-plasma etching approaches. Finally, patterns of multiple thin layers on the substrate are fabricated after a number of steps including these three major techniques. To facilitate an understanding of the full range of MEMS fabrication technology, we start with the introduction of various micromachining technologies.

4.2.2

Bulk Micromachining Technologies

Bulk micromachining is deployed to selectively remove significant amounts of silicon from a silicon substrate. The geometries of etched features lie along a continuum between fully isotropic and anisotropic. Wet anisotropic etching is currently by far the most commercially successful method used to manufacture devices such as pressure sensors and ink-jet print heads. Wet anisotropic etch agents are ratelimited, whereas wet isotropic etch agents are diffusion-limited. Both involve oxidation of the Si followed by dissolution of the hydrated silicate. The most common wet isotropic silicon etch solution is HNA, which stands for a mixture of hydrofluoric acid (HF), nitric acid (HNO3), and acetic acid (CH3COOH). The HNO3 drives the oxidation of the silicon, and the acetic acid helps to prevent the dissociation of HNO3 into NO3– or NO2–. The etching chemistry is complex (owing to theautocatalytic ionization of HNO3), and etch rates also depend on the chemical mixture and doping concentration of silicon. The fluoride ions from HF react to form the soluble silicon compound H2SiF6. The overall reaction1 is given by 18HF + 4HNO3 + 3Si → 3H2SiF6 + 4NO(g) + 8H2O

(4-1)

Owing to equal etch rates in all directions, the HNA is used to round the sharp corners, to remove the roughness, and to perform the thinning. The main function of the isotropic wet etch in bulk micromachining is to remove the underlying silicon substrate or the silicon sacrificial layer. As a result, the free-standing structures are

159

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Chapter Four released from the substrate and remain on top of an isotropically etched cavity or a sacrificial gap. A useful formulation for HNA is 250-ml HF, 500-ml HNO3, and 800-ml CH3COOH.2 When HNA is used at room temperature, an etch rate of 4 to 20 μm/min is obtained, and this is increased with agitation. The HNA wet etch can be masked with silicon nitride or silicon dioxide (however, the silicon dioxide film is attacked rather quickly at a rate of 30 to 70 nm/min). It is also noteworthy that the HNA etch rate becomes slower by 150 times in the regions of light doping (<1017 cm–3 n- or p-type) than in more heavily doped regions. Second, the anisotropic etchants etch much faster in one direction than in the other, exposing the slowest-etching crystal planes over time. The slowest-etching crystal planes {111} lead to sloped sidewalls of 54.7 degrees, that is, the angle between the (111) plane and the wafer’s surface of the (100) plane of the {100} silicon wafer. To facilitate concept development in silicon crystal orientation, the four types of commercially available silicon wafers are illustrated in Fig. 4-1a, whereas various planes in a {100} n-type silicon wafer are sketched in Fig. 4.1b. Depending on the dimensions of the mask opening, a V-groove or trapezoidal basin is formed in the [100] wafer, as shown in Fig. 4-1c. A large enough opening will allow the silicon to be etched almost all the way through the wafer, leaving a thin dielectric membrane on the other side. Backside etching can be used to create free-standing structures such as beams, membranes, and plates. The three most important anisotropic silicon etchants are potassium hydroxide (KOH), ethylene diamine pyrochatechol (EDP), and tetramethyl ammonium hydroxide (TMAH). These etchants attack silicon along preferred crystallographic pathways. The crucial difference between these etchants is in the etch rates and hard-mask materials to be deposited on the substrate. Suitable hard-mask materials for KOH are silicon nitride and silicon carbide, which etch at negligible rates. In contrast, silicon dioxide is not an ideal mask materials for KOH owing to an etch rate that is typically 1/200 of the etch rate of {100} silicon plane. The KOH is corrosive to aluminum. Thus refractory metals (e.g., gold) are used as the metal surface to be exposed to KOH solution. However, silicon dioxide can be used as a hard mask when etching with TMAH because the etch rate is negligible. This is a clear advantage of TMAH anisotropic etching for releasing dielectric layers from a substrate made by the standard CMOS process. Another advantage of TMAH anisotropic etching is that it is possible to reduce the etch rate of aluminum to an acceptable level by adding silicon and/or polysilicic acid3 or by adding (NH4)2CO2 or (NH4)HPO4 to the etchant to lower the pH.4 The drawback to this TMAH etching condition is that hillocks and rough surfaces are generated in the {100} silicon planes. These can be alleviated to some extent by the addition of an oxidizer (e.g., ammonium peroxydisulfate).5

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g Secondary flat

No secondary flat (111) p-type

90° 45°

y

Primary flat

t fla

Primary flat

(111) n-type

(100) p-type

ar nd co Se

Secondary flat

(100) n-type

Primary flat

Primary flat

(a) (010) plane

(100) plane

(001) plane

tio n

z, [001] y, [010] x, [100]

(110) plane

[11 0] dir ec

45°

(110)

(b)

(111)

[001] [010] (111) [100]

(111)

Surface is (001)

(111)

Flat is along [110] direction

(c)

FIGURE 4-1

(a) Drawings showing the primary and secondary flats of {100} and {111} wafers for both n- and p-type doping. (b) Various planes in a wafer of {100} orientation (the wafer thickness is exaggerated). (c) Perspective view of a {100} wafer and a KOH-etched pit bounded by {111} planes. (Reprinted with permission from Maluf, N., and Williams, K., An introduction to microelectromechanical systems engineering, 2nd Edition, London: Artech House, 2004, ISBN 1-58053-590-9, Copyright 2004 Artech House.)

In the case of EDP anisotropic etching, both silicon dioxide and silicon nitride can be used as hard masks. In addition, many metals are not attacked by EDP, except aluminum, although the etch rate of aluminum for some formulations of the etchant can be reduced to useful proportions.6 It is also reported that the silicon etch rates versus temperature for the EDP formulation given above are 14 μm/h at 70°C, 20 μm/h at 80°C, 30 μm/h at 90°C, and 36 μm/h at 97°C.6 However, EDP is extremely hazardous, very corrosive, and carcinogenic, and it has to be used in a reflux condenser.

161

162

Chapter Four The silicon etching mechanism involved in these anisotropic etchants is suggested as the following reaction sequence.7,8 First, silicon atoms at the surface react with hydroxyl ions. The silicon is oxidized to form Si(OH)22+, and four electrons are generated as Si + 2OH– → Si(OH)22+ + 4e–

(4-2)

By taking these four electrons, water is reduced to form hydroxyl ions and hydrogen gas; that is, 4H2O + 4e– → 4OH– + 2H2

(4-3)

The Si(OH)22+ further reacts with hydroxyl ions to form a soluble SiO2(OH)22– and water; that is, Si(OH)22+ + 4OH– → SiO2(OH)22+ + 2H2O

(4-4)

The overall reaction is sum up as Si + 2OH– + 2H2O → Si(OH)22+ + 2H2

(4-5)

A thorough overview of alkaline etchants, their properties, and their mechanisms can be found in Seidel and colleagues.8 As a reference, the paper reports that the (100) silicon etch rate is derived as 1.4 μm/min for a 50 wt% KOH solution at 80°C.1 KOH wet etching solution concentrations below 20 wt% are not used because of the high surface roughness and the formation of potential insoluble precipitates. In addition, such solutions all show a marked reduction in etch rate in heavily doped (>5 × 1019 cm3) boron ( p++) regions that are formed by ion implantation and diffusion. This greatly simplifies the tooling required to perform the etch. However, the etch-rate selectivity is not quite as high as for passivating oxides. Besides, the p++ diaphragm shows residual tensile stress that might affect the performance of devices. Chemically reactive vapors and the reactive species in glowdischarge plasmas are highly effective etchants. These are known as dry-etching-process technologies and are classified into two groups: vapor etching and plasma-assisted etching. Plasma-assisted etching has been a key process in the semiconductor and optoelectronics industries for more than three decades. Given the well-established industrial infrastructure in terms of equipment makers and users and available technological knowledge and process recipes, plasmaassisted etching is the dominant process technology in the MEMS industry as well. Plasma-assisted etching has several advantages over the wet etching techniques. It normally offers smaller undercut (allowing smaller lines to be patterned) and higher anisotropicity (allowing high-aspect-ratio vertical structures) than wet etching, but the etchrate selectivity in some cases is not as good as that in wet etching.

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g There are three basic dry-etching techniques, namely, high-density plasma etching, reactive-ion etching (RIE), and ion milling (ionbombardment etching) in ref 9. The shape of a plasma-assisted etched feature is a strong function of the etching conditions. The least selective use of ions produced in a plasma is for the sputtering away of material. This is known as ion milling or ion-bombardment etching. When a blanket opening is exposed to plasma (e.g., argon plasma), the energetic argon ion ejects atom from the exposed surface owing to the ion-bombardment effect (or sputtering). Sputtering rate generally is low because the yield typically is like “one atom per incident ion,” and ion fluxes incident on surfaces in discharges are often small. Ion milling is a wellestablished technology and not a mainstream mass-production technology in the industry. Nevertheless, it is an effective approach for removing nonvolatile materials from substrate surfaces. In low-pressure glow-discharge plasmas, energetic ions are accelerated across the plasma sheath edge and strike the surface vertically with kinetic energy, resulting in directional etching (i.e., good anisotropy and poor selectivity). Thus the higher the base pressure in the plasma, the more isotropic is the etch profile owing to a much shorter mean free path of ions. In contrast, the etch rate generally is reduced in a plasma reactor chamber at lower pressure, whereas the etch becomes more directional because the ions that are accelerated through the dark space at the edge of the plasma strike the surface with a definite orientation. By leveraging the reactive chemical species (e.g., gas-phase etchant atoms or molecules such as the F atom in silicon etching) at the surface of the area to be etched, RIE leads to higher etch rate than the sum of the chemical etching rate and the sputter etching rate operated individually. In other words, RIE can remove surface material by direct ion bombardment and chemical-reaction effects, whereas the etched surface atoms are converted to volatile species that can be removed by the vacuum pump connected with the reactor chamber. Because of a lesser ion-bombardment effect in RIE, sidewalls are not etched significantly; that is, the ions do not strike sidewalls mainly. As a result, RIE provides much better directional etching. The tradeoff between anisotropy and selectivity is important in designing etch parameters in an RIE process. Given the significant effort made in silicon semiconductor manufacturing, there is a rich combination of plasma chemistries that can be used for etching all the microelectronic thin films: oxides, nitrides, metals, and silicon. A relevant selection to silicon micromachining is suggested in Table 4-1. To provide a better sense in process design, wet-etch alternatives are listed for a fair comparison. A much more complete database of etchants, including data on etch rates and selectivity, can be found in ref. 1. Most etch chemistries involve either fluorinated or chlorinated species. Recipes are developed to achieve the desired chemical selectivity, for example, etching oxide and stopping on nitride or etching silicon and stopping on oxide, whereas the etched profile is a main concern as well (i.e., the anisotropy).

163

164 Wet Etchants (Aqueous Solutions) Thermal silicon dioxide

LPCVD silicon nitride

Etch Rate (nm/min)

Dry Etching Gases (Plasma or Vapor Phase)

Etch Rate (nm/min)

HF

2,300

CHF3 + O2

50–150

5NH4F:1HF (buffered HF)

100

CHF3 + CF4 + He HF vapor (no plasma)

250–600

SF6

150–250

CHF3 + CF4 + He

200–600

Hot H3PO4

5

66

Warm H3PO4:HNO3:CH3COOH

530

Cl2 + SiCl4

100–150

HF

4

Cl2 + BCl3 + CHCl3

200–600

Gold

KI:I2

660

Titanium

HF:H2O2

110–880

SF6

100–150

Tungsten

Warm H2O2

150

SF6

300–400

K3Fe(CN)6:KOH:KH2PO4

34

Chromium

Ce(NH4)2(NO3)6:CH3COOH

93

Cl2

5

Photoresist

Hot H2SO4:H2O2

>100,000

O2

350

CH3COOH3 (acetone)

>100,000

Aluminum

(Reprinted with permission from Maluf, N., and Williams, K., An introduction to microelectromehcanical systems engineering, 2nd Edition, London: Artech House, 2004, ISBN 1-58053-590-9, Copyright 2004 Artech House)

TABLE 4-1

Wet and Dry Etchants of Thin Metal Films and Dielectric Insulators

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g Other than the dry-etching mechanisms introduced earlier (e.g., ion-bombard etching and RIE using capacitively coupled parallelplate electrodes), the last mechanism, and perhaps the most important dry-etching technique used in bulk micromachining, is high-density plasma etching. By using inductively coupled plasma (ICP) or an electroncyclotron resonance (ECR)–based power source, the high-density plasma reactor can independently control plasma parameters such as electron energy, ion energy, and plasma density. The high-density plasma reactor operates at lower process pressures and achieves a high ionization ratio such that the density of the plasma is higher than that of capacitively coupled plasma because the high-density plasma reactor can efficiently transfer energy to electrons so as to achieve a high ionization ratio. Furthermore, the longer mean free path of ions in the lowpressure process in a high-density plasma reactor enables significant improvements in directional etching. Therefore, high-density plasma etching is called deep reactive ion etching (DRIE). Starting in early 1990s, research attempts were focused on advanced DRIE in order to develop bulk micromachined structures with very high aspect ratios. One approach was for the glow discharge to supply the etchants, energetic ions, and inhibitor precursor molecules. Most plasma processes are a critical race between deposition of polymeric material from the plasma and removal of material from the surface. In well-designed plasma chemistries, removal (i.e., the etch process) dominates. By using a cryogenic cooling technique, when a wafer is maintained at liquid-nitrogen temperatures, the reactant gases condense onto the silicon surface, thus passivating the surface. For example, the inhibitor precursor molecules (e.g. CF2, CF3, CCl2, and CCl3), which are called unsaturates, deposit on the substrate surface to form fluoro- or chlorocarbon polymer films (i.e., a protective layer). In such DRIE equipment, the ion-bombardment effect is suppressed, but just enough for removal of the polymer layer on the bottom surfaces of etched trenches so as to perform the reactive ion etching continuously, whereas the polymer layer on the sidewalls of the trenches is retained owing to the directional ion etching effect (i.e., energetic ions move along the direction normal to the substrate). SF6 typically is used because of the high etch rates that can be achieved. The passivation can be enhanced by the addition of oxygen to the plasma, which results in an increased ratio of fluoro- to carbon, meaning more fluorounsaturates for polymer passivation. A potential problem with the cryogenic approach involves maintaining the cryogenic temperature of all the microstructures during the etch process. Some microstructures may become thermally isolated from the substrate when they are released from the substrate and become free-standing. The raised temperature in the local freestanding microstructures may lead to deterioration of polymer passivation. When polymer passivation on these microstructures is not sufficient, the etching mode dominates. As a result, notching and RIE

165

166

Chapter Four

C4F8

Photoresist

Scallop SF6

CF2 species for passivation

F species for etching

(a)

(b)

Photoresist

Silicon 10 μm (c)

1 μm (d)

FIGURE 4-2 Profile of a DRIE trench using the Bosch process: (a) passivation step of using CF2 species; (b) fluoroion-based etching step; (c) SEM microphotograph of cross-sectional view of DRIE trenches; (d ) SEM microphotograph of close-up view of scalloped sidewall. The process cycles between an etch step using SF6 gas and a polymer deposition step using C4F8. The polymer protects the sidewalls from etching by the reactive fluorine radicals.

lag effects are observed in this case such that the uniformity of etching results is not good. Scientists at Bosch have developed a revised process to further improve process control in DRIE.10 Instead of relying on the balance between plasma etching and polymer passivation, the Bosch process uses alternate etching and passivation steps, as shown in Fig. 4-2. The passivation is achieved by deposition of a polymer using CFx+, which is decomposed from C4F8 feedgas. The subsequent step is a reactiveion etching process using such species as F+ and SFx+, whereas the polymer on the bottom of the trench is removed owing to the directional etching effect of ion bombardment. The normal cycle time for each deposition or etch step is a few seconds. The resulting etch rate is 1 to 15 μm/min typically. An aspect ratio of etched trench of 30:1 can be achieved. A comparison of DRIE technology with other bulk micromachining technology is given in Table 4-2. The general issues

HF:HNO3: CH3COOH

KOH

EDP

N(CH3)4OH (TMAH)

SF6

SF6/C4F3 (DRIE)

XeF2

Etch type

Wet

Wet

Wet

Wet

Plasma

Plasma

Vapor

Typical formulation

250-ml HF, 500-ml HNO3, 800-ml CH3COOH

40 to 50 wt%

750-ml ethylenediamine, 120-g pyrochatechol, 100-ml water

20 to 25 wt%

Anisotropic

No

Yes

Yes

Yes

Varies

Yes

No

Temperature

25°C

70–90°C

115°C

90°C

0–100°C

20–80°C

20°C

Etch rate (μm/min)

1–20

0.5–3

0.75

0.5–1.5

0.1–0.5

1–15

0.1–10

[111]/[100] Selectivity

None

100:1

35:1

50:1

None

None

None

Nitride etch (nm/min)

Low

1

0.1

0.1

200

200

12

SiO2 etch (nm/min)

10–30

10

0.2

0.1

10

10

0

p + + etch stop

No

Yes

Yes

Yes

No

No

No

Roomtemp. vapor pressure

167

(Reprinted with permission from Maluf, N., and Williams, K., An Introduction to Microelectromehcanical Systems Engineering, 2nd Edition, London: Artech House, 2004, ISBN 1-58053-590-9, Copyright 2004 Artech House).

TABLE 4-2

Liquid, Plasma, and Gas Phase Etchants of Silicon

168

Chapter Four in both DRIE processes is that the etch rate is a function of the density of the opening area and trench width. Investigation of an etched dummy wafer is necessary for etch-rate calibration when users have a new lithography mask layout. Another dry bulk micromachining approach is vapor-phase etching. A reactive gas mixture that typically contains fluorine can etch silicon with very high selectivity to many masking layers, including Al, SiO2, Si3N4, photoresist (PR), and phosphosilicate glass (PSG). One of the most widely employed reactive gases is XeF2. As suggested by Chang and colleagues,11 the reaction with silicon is given by 2XeF2 + Si → 2Xe + SiF4

(4-6)

The gas xenon diflouride performs the non-plasma-based isotropic etch of the solid silicon surface and forms the volatile SiF4 product. This etch reaction completes with desorption of the volatile SiF4 product and residual xenon from the silicon surface. It is noteworthy that the etched surfaces shows granular structures of a few microns, making the etched surface unsuitable for situations where smooth surfaces are required (e.g., optical reflection surfaces). This reaction is exothermic. Thus the generated heat may adversely influence some microstructures. Pulse-mode operation of XeF2 etching is suggested. An important concern is that XeF2 reacts with water (even moisture in air) to form Xe and HF, whereas the generated HF will unintentionally etch silicon dioxide. A properly designed reaction chamber linked with a vacuum pump is still required for handling XeF2 vaporphase etching. The typical etch rate is a few micrometers per minute, as shown in Table 4-2. It is ideal for the dry release of CMOS MEMS devices (i.e., dielectric layers from a CMOS substrate) and surface micromachined structures in which polysilicon is used as the sacrificial layer.

4.2.3

Conventional Wafer-Bonding Technologies for Packaging

Wafer bonding is used widely in MEMS fabrication and packaging.12 It refers to approaches of firmly joining two wafers (or more) to create a stacked and bonded wafer. There are three main kinds of waferbonding processes: direct bonding, field-assisted bonding, and bonding with an intermediate layer. The choice of which is most suitable depends on the particular application and the materials involved. Silicon-to-silicon direct bonding, also called fusion bonding, is a direct silicon-to-silicon bonding technique without the assistance of significant pressure or any intermediate layers or fields.13 The process requires rather flat and clean surfaces as the bonding interface for the two wafers. The surfaces of silicon wafers are cleaned and rinsed first. Hydroxyl (–OH) groups form on the surfaces of the two wafers with

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g a thin native silicon oxide layer (i.e., hydrophilic surface). Two wafers can be joined together at room temperature, resulting in an immediate weak bond owing to van der Waals forces. Then the bonded wafers are heated to 800 to 1000°C to remove the water molecules and leave behind Si–O–Si bonds at the interface. Owing to perfectly matched thermal-expansion coefficients of the two wafers, silicon direct-bonded wafers have little or no residual stress owing to thermal mismatch. However, silicon direct bonding normally is used as the beginning step in an integrated process because of the rather high annealing temperature and high-quality requirement of the bonding interface in terms of cleanness and flatness. Another direct-bonding technology is restricted to bonding glass to a conductive substrate using electrical bias, that is, field-assisted bonding or anodic bonding.14 A glass wafer with a high concentration of sodium ions (e.g., Pyrex 7740 glass from Corning) is biased as the cathode, and the silicon wafer is the anode. The contacted wafers are heated to 300 to 400°C, and a voltage of about 200 to 1000 V is applied. The applied voltage produces a very high electrostatic attractive force that pulls the silicon and glass into intimate contact. The sodium ions in the glass wafer (i.e., the cathode side) diffuse toward the opposite side from the bonding interface, whereas the oxygen ions of negative charge are left behind and accumulate at the bonding interface. The available oxygen ions and silicon atoms at the interface will form strong Si–O bond, whereas a current of a few milliamperes per square centimeter flows between the two electrodes, signifying the movement of ions and completion of the process. When bonding is completed, this current drops to zero. Similar to the concern we have in silicon direct bonding, the anodic bonding is very susceptible to interference from particulate contaminants. To achieve an anodic bonded interface of good quality, there are several parameters, such as surface preparation, contact load, temperature, time of applied voltage, and magnitude of the applied voltage, that should be monitored during the bonding process. A number of glasses from different vendors can be used in anodic bonding. Basically, conductive glasses with a reasonably high content of sodium and boron have lower melting and softening temperatures. These glasses are more suitable for anodic bonding. When the glass is purer, its electrical conductivity decreases, which reduces the electric field strength and lowers the electrostatic attraction that exists between the two wafers. As a result, glass substrates of lower conductivity typically need a higher bonding temperature and a higher biased voltage to achieve a successful bond. A wide range of intermediate layers has been used for wafer-towafer bonding in microstructure fabrication. These intermediate-layer bonding approaches include eutectic bonding, glass-frit bonding, solder-based thermocompression bonding, and adhesive bonding. Eutectic bonding deploys a thin gold layer as an adhesive layer to

169

170

Chapter Four bond silicon wafers.15 The wafers, coated with a thin gold layer, are brought into contact at a temperature higher than Au-Si eutectic point (i.e., 363°C for 2.65% Si in Au). The common practice is bonding at 370°C for 15 minutes under 7 kN of applied force using a commercially available bonding tool. Wafer-level packaging based on a glassfrit-sealed interface between the MEMS wafer and a cap wafer has been a major technology for volume production of MEMS accelerometers in automotive airbag systems to realize hermetic sealing. This method is similar to the long-established approach of glass frits as seals in conventional hermetic ceramic packages.16 The cap wafer is stenciled with a mixture of glass and binder and patterned to form the walls of each device cavity. Another cap wafer is aligned and thermocompression bonded to the device wafer with glass-frit bonding rings. The bonding condition typically requires a temperature higher than 400°C and an applied pressure of 2 bars. However, reliable sealing using glass frits requires a relatively wider wall-sealing pattern. This implies fewer gross dies per bonded wafer. Eutectic Au-Sn solder has long been recognized as an approach offering superior high-temperature performance, high mechanical strength, and fluxless soldering because the melting temperature of its eutectic composition (Au 30 at% Sn) is 280°C.17,18 This approach has been used widely in the optoelectronics and microelectronics industries. It is a reliable solution for packages comprised of sealing of a Kovar case to a ceramic substrate. However, there is concern that a large residual stress will be introduced when two bonded wafers with a relatively large difference in coefficient of thermal expansion (CTE) undergo a process with a large temperature difference. In addition to the above-mentioned wafer-bonding technologies using the intermediate layer for hermetic bonding, the last group is polymer-based adhesive bonding. First, polymer-based adhesive bonding is used as temporary bonding of wafers, where the polymer just has to keep the wafers together during the micromachining process. Second, polymer-based adhesive bonding can be used to form waferbonded structures in nonhermetic and near-hermetic packages. Various kinds of adhesives, including epoxies, poly(methylmethacrylate) (PMMA), polyimides, silicone rubbers, and negative photoresists, are used. Generally, such polymer bonds can be achieved at temperatures lower than 150°C. Thus there is no serious concern about residual stress owing to the thermal-expansion mismatch between different types of wafers in the bonded wafers.19 Two polymer materials with major research interests are SU-8 and benzocyclobutene (BCB). SU-8 is an epoxy-based negative-resist material from Microchem, whereas BCB is from the Dow Chemical. BCB shows minimal outgassing, low moisture uptake, and excellent electrical properties. In one process, as shown in Fig. 4-3, BCB is spincoated onto the capping wafer and photopatterned to provide sealing

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g

Si Si

(a)

BCB intermediate bounding layer

(b) (e)

Spacing created by using dicing saw

(c) Si cap

(d)

PCB

(f)

FIGURE 4-3 Wafer-level packaging approach using polymer as the intermediate layer to form the sealing interface, ref. 21.

rings. After the cap wafer is bonded with the device wafer, multistep dicing is used to expose the bonding-pad area and separate each die from the bonded wafer (see Fig. 4-3b and c). For example, the capped die can be die-bonded and wire-bonded on a PCB. Thereafter, the whole packaging process is accomplished by a molding step (see Fig. 4-3d). The bonded wafer after dicing and a close-up view are shown in Fig. 4-3e and f, respectively. The reflow characteristic of BCB during the curing step allows the planar electrical signal feed-throughs passing through the bonding ring while maintaining a good seal. RF MEMS switches and film bulk acoustic resonator (FBAR) filters have been packaged by using the BCB capping process.20,21 On the other hand, we do not want residual BCB left inside deep cavities for wafers with high-aspect-ratio cavities; thus, we should not use a spin-on step to prepare the BCB coating layer. Besides, we could not use the spin-on process to prepare the BCB coating layer on a wafer with free-standing structures. A new process called contact printing provides better results than the spin-on technique. The contact printing method uses viscous BCB as “ink” and a soft-cured BCB pattern as a stamp to improve the bond strength of full-wafer adhesive bonding with patterned BCB as the intermediate bonding layer. This technology successfully demonstrated that the bond strength of samples has been improved by a factor of 2 over the conventional spin-on BCB bonding technique.22,23

171

172

Chapter Four

4.2.4

Plasma-Assisted Wafer-Bonding Technologies

Another low-temperature direct bonding approach is known as plasma-activated wafer bonding or surface-activation bonding. The plasmaactivation step modifies the surface chemistry in a similar manner to hydrophilic surface treatment. The substrates are pretreated with plasma and cleaned off, and then they are brought into contact with or without external pressure and high temperature to form an irreversible bond.24,25 Plasma may be generated from different feedgases, including oxygen, argon, nitrogen, and hydrogen. Oxygen plasma creates a thin oxide layer on the interface and is used for applications that require electrical isolation at the interface. On the other hand, hydrogen, nitrogen, and argon plasmas are used in applications where a bonded interface is preferred that does not have a residual oxide layer. Obviously, this process has to be carried out in a vacuum environment (i.e., a plasma chamber such as an RIE chamber or an ICP chamber). It is also possible to treat the surfaces chemically using a barrier-discharge method, where plasma is formed in the atmosphere. Plasma-activated bonding now has been applied to various materials, including silicon, compound semiconductors, oxides, and polymers.25 Normally, an annealing step at an elevated temperature of 100 to 400°C is needed depending on the required bond strength and the materials being bonded. When the wafer surface is cleaned using argon-beam sputtering in a high-vacuum environment, silicon wafers can be bonded at room temperature.26,27 The type of plasma used to activate the bonding surface, plasma power, and the annealing step all can have a significant influence on bond strength and void or defect density at the interface. Because wafers need to be aligned and then bonded in the plasma chamber without breaking vacuum, specialized alignment and bonding stages, as well as the substrate heater, need to be included in a single machine.

4.2.5

Electrical Interconnects

The most common electrical interconnects are the planar electrical leads. They are typically prepared on the same side of MEMS wafer. There are two major kinds of planar electrical leads: buried leads and surface leads. Buried leads can be heavily doped Si or metal silicide (e.g., AlSi) that forms a low-resistive path on the silicon substrate. For the surface lead line, the Al-alloy process used in microelelctronics is a common solution for MEMS (see Fig. 4-3). However, the Al may need to be substituted by other materials that can withstand the hightemperature process. Highly doped polysilicon is used commonly as a lead-line material in the surface micromachining technology, and it can sustain in all kinds of high-temperature wafer-bonding processes using the intermediate layer. Generally speaking, highly doped silicon or polysilicon is used widely as lead lines in electrostatic actuated

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g MEMS and capacitive sensors. It should be noted, though, that polysilicon leads typically exhibit higher 1/f noise than metal leads. Thus, in some resistive types of MEMS sensors, polysilicon leads may not be a good choice. Second, anisotropic wet-etched Si V-grooves could be used for through-wafer vertical electrical vias when metal leads are sputtered or electroplated on the V-groove sidewalls. Owing to the angle of the V-grooves, the footprint of through-wafer V-groove vias is relatively larger, as shown in Fig. 4-4a.28 Since the size of the through-wafer V-groove vias is determined simply by the thickness of wafer, by using a thin device layer of a silicon-on-insulator (SOI) wafer, the V-groove vias can be shrunk to a very small area (see Fig. 4-4b and c).18

(a) Electrical interconnects

μ-via

Solder ball (b)

V-groove μ-via SMD pad

Sealing ring

μ-via

(c)

FIGURE 4-4 V-groove type of vertical interconnects with small footprint for wafer-level MEMS packaging.

173

174

Chapter Four On the other hand, through-wafer vertical holes of silicon and glass substrates can be created by using DRIE or photo-assisted electrochemical etching. After forming the insulation layer based on thermal oxidation, chemical vapor deposition (CVD) dielectric-layer coating, or CVD parylene coating, the through-wafer vertical interconnects can be formed by heavily doped polysilicon conformal deposition, metal sputtering, metal plating, or vacuum metal sucking and refilling.29–32 Combining the vertical interconnects with cavities on the cap wafer allows the formation of a large number of interconnects and wafer-level packaging by means of a simple bonding step at the same time. In particular, wafer-level packaging using a solder intermediate layer with reflow is very suitable to this approach because the solderreflow step will enhance the connection between the vertical interconnects of the cap wafer and the planar electrical pads of MEMS wafer both mechanically and electrically. As shown in Fig. 4-5, this concept has been applied to the vacuum sealing of accelerometers (see Fig. 4-5a and b) and the hermetic sealing of RF MEMS switches (see Fig. 4-5c and d).33,34 Without using the high-temperature thermal oxidation process, a novel low-temperature process of creating a thick SU-8 dielectric isolation between Cu vertical interconnects and surrounding Si sidewalls has been reported.35 This approach allows one to create vertical interconnects on a wafer after MEMS devices

Transmission line Piezoelectric actuator

Via hole

Cap wafer

Vacuum Cap substrate

MEMS device Contact electrode

(a) Bottom substrate

Accelerometer device

(c) Via hole Electrode

Copper via

CPW line Bonding material Cap substrate

Cap wafer

Sealing rim

Solder ball Bottom substrate

Substrate (PCB)

(b)

Piezoelectric film

(d)

Contact electrode

Dielectric membrane

FIGURE 4-5 Through-wafer vertical interconnects with solder joints formed at the same wafer-bonding step for solder-based wafer-bonding MEMS packaging.

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g or Al planar electrical leads have been prepared on the same wafer. Additionally, the vertical interconnects are quite useful for SiP applications with high input-output (I/O) pin counts.

4.2.6

Solder-Based Intermediate-Layer Bonding

The choice of the intermediate bonding layer is made based on the types of substrates to be bonded, the thermal budget of the process temperature, and whether hermetic sealing is required or not. The well-known intermediate-layer bonding techniques include the use of polymer-based bonding at temperatures ranging from 100 to 150°C, Au/Sn solder–based eutectic bonding at 280°C,17,36 Au/Si eutectic bonding at 365°C,37 and glass-frit bonding at 400°C. Given that most of applications require hermetically sealed packages, polymer-based intermediate-layer bonding produces a gas-permeable interface and therefore does not meet the hermetic sealing requirements. Thus Au/Sn solder bonding and glass-frit bonding are the mainstream approaches in the MEMS industry nowadays. However, many MEMS devices contain different materials or need to bond substrates containing the electronic part of the device (e.g. CMOS wafers). Thus the difference in thermal-expansion coefficients of the dissimilar materials results in mechanical stress that is in proportion to the process temperature. Therefore, low-temperature wafer bonding is the key to avoiding such residual mechanical stress. To fulfill the requirements for hermetic sealing and low process temperatures, indium and indium-based alloy solders have been reported to be very attractive intermediate-layer materials. The batch-type techniques for preparing the solder pattern on wafers for bonding include stenciling, dip coating, electroplating, and evaporation/sputtering. The technical challenges of this process involve uniformity control of the solder pattern, thickness, and composition. Since the In-Sn material system has a eutectic point at 118°C and pure indium melts at 156.6°C, In-Sn (50/50) solder has been investigated as the bonding intermediate layer for packaging of thermal sensors and infrared imaging sensors.38 A helium-leakage rate less than 1 × 10–8 (torr · liter)/s and tensile strength of 200 kg/cm2 for the bonding interface can be obtained with a bonding temperature of 150°C.39 Au-In-Ni intermediatelayer material has been used for packaging thermal sensor arrays as well.40 The authors of this study suggested a thermocompression approach based on the cold-welding characteristics of indium. In a bonding chamber with a forming-gas environment (e.g., N2 90 percent and H2 10 percent), a shear strength of 72 MPa at the bonding interface can be obtained with a bonding temperature of 195°C for 10 minutes with an applied pressure of 8 MPa. This package shows postbonding temperature stability up to 473°C. On the other hand, In compression bonding has been reported for wafer bonding of vacuum-packaged microbolometers for infrared imaging applications.41–43 Extensive

175

176

Chapter Four studies on low-temperature bonding and the characteristics of the bonding interface on the chip-to-chip scale have been reported44–48 using various bonding-interface materials (e.g., In-Sn, In-Ag, In-Cu, and In-Au). Moreover, the industry also requires solder-bonded interfaces to be able to survive at temperature at least as high as 285°C, which is the peak temperature in the surface-mounting-technology (SMT) manufacturing line. This means that the resulting intermetallic compounds (IMCs) of the solder-bonded interfaces in any postbonding steps need to have a melting temperature (i.e., a remelting temperature) that is higher than the postbonding process temperature. Incorporating In and Sn as the solder layer to react at a high melting temperature to form stable IMCs is a new research direction in low-temperature solder-based wafer bonding that aims to create a materials evolution of the resulting IMCs at the bonded interfaces with respect to various postbonding heat-treatment process conditions. We will discuss this recent progress in Sec. 4.6.

4.3 Wafer-Level Encapsulation Wafer-level encapsulation is an approach that consists of using a sacrificial material to cover the MEMS device and a deposited thin film under tensile stress to encapsulate the MEMS device, followed by removal of the sacrificial layer by wet etching or vapor-phase etching through the opening and then encapsulation of the opening by deposition of a thin film. In the case of encapsulating the opening in a thinfilm reaction chamber under vacuum, the sealed cavity of the MEMS device can be preserved at low vacuum. This concept has been applied to achieve wafer-level packaging for capacitive- and piezoresistivesensing pressure sensors49–51 (Fig. 4-6a and b) based on low-pressure chemical vapor deposition (LPCVD) SiN film sealing and for resonators based on polysilicon-film sealing (Fig. 4-6c).52-53 This process is suitable for sealing surface-micromachined MEMS devices owing to its perfect process integration. To enhance the durability and mechanical robustness of the encapsulation, a 20-μm-thick epitaxial Si layer is prepared using dichlorosilane at 1080°C to seal the MEMS structure first, denoted as the cap layer in Fig. 4-6d. Then trenches are etched through the cap layer to allow the HF vapor etching to remove the refilled SiO2 and release the MEMS structure, thereby isolating the electrical conductive paths.54,55 Finally, a layer of LPCVD oxide is deposited on top of the cap layer to create a seal over the trenches. Since the oxide deposition furnace is under vacuum, the parts are also under vacuum when sealed. After the sealing oxide is deposited, metal layer is deposited and patterned to form the electrical leads and pads. Since SiO2 is permeable to the ambient gases, the silicon nitride film or metal layer on top of the oxide seal location can extend the vacuum life of package.

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g SiN diaphragm PolySi piezoresistors

Optional CMOS

Electrode contact

Epi layer

Sealed vacuum cavity

(a)

Poly layer

SOI layer

(e)

Handle wafer

Deflection electrode

Vibrating resonator

(b) Si epilayer

Shell of sealed vacuum cavity

SOI layer

(c)

Seal oxide Aluminum pads

Al contacts Sealing of vents Seal oxide Cap layer Refill oxide Device layer Sacrificial oxide

(d)

Handle wafer

(f)

PolySi

(g)

FIGURE 4-6 Wafer-level packaging approaches using high-temperature processes to form the wafer-level encapsulation.

4.3.1

High-Temperature Encapsulation Process

The last process described in previous section has been further developed by the Bosch Group and Stanford University and was commercialized recently by SiTime (www.sitime.com) for packaging of MEMS oscillators.56 As shown in Fig. 4-6e and f, this technology encapsulates silicon resonators in epitaxially sealed chambers buried under the wafer surface. Recently, an ultracompact encapsulated accelerometer with a die size of 387 × 387 × 230 μm has been demonstrated using this epitaxial Si encapsulation technology, as shown in Fig. 4-6g.57 The first step in the fabrication process is patterning the resonator structure from an SOI wafer with a 10- to 20-μm-thick device layer. An oxide layer is deposited and patterned to cover the resonator structure while providing via openings for electrical contacts. Then a thin epitaxial silicon layer is grown and patterned to get via openings through the oxide layer down to the silicon electrode part of the

177

178

Chapter Four device layer. Using the HF vapor-based etching, a portion of the oxide layer is removed to release the movable parts of the resonator structure. Thus the portion of this oxide layer that is the sacrificial layer, whereas the remaining portion is the insulating oxide layer (see Fig. 4-6e and f ). In the last step, a thick epitaxial silicon layer is grown on top to seal the trenches such that the cavity containing the movable parts of the resonator is sealed with the same degree of vacuum as the process-chamber pressure used in the epitaxial silicon deposition process. The epitaxial silicon grown on top of the oxide layer forms a polycrystalline silicon layer, whereas a single-crystal silicon layer is formed in the area where the oxide has been removed. After surface planarization and formation of contact isolation trenches, the wafer with encapsulated MEMS structures can be used as a starting wafer for further CMOS processing to create monolithically integrated circuits. The MEMS-first front-end wafer-level packaging process completely defines, releases, and seals the resonant microstructures in the front-end processing steps. Thus it provides reliable wafer-level vacuum packaging at low cost. One advantage of using a high-temperature sealing process (i.e., epitaxial Si deposition) to enable the Si oscillators to be embedded inside a sealed vacuum cavity is that the absorbed molecules inside the cavity will be removed during the high-temperature sealing step, just as in the hot baking treatment. Thus the newly released product exhibits excellent performance in terms of ultralow long-term drift of device features and good frequency stability against temperature variation.56

4.3.2

Low-Temperature Encapsulation Process

This high-temperature epitaxial Si sealing process limits material selection for MEMS devices. Some metals and low-temperature oxides cannot sustain their material characteristics under such high temperatures. As shown in Fig. 4-7, a three-mask low-temperature electroplating process has been proposed.58 An electroplated 40-μmthick nickel film is prepared on a sacrificial photoresist layer of several microns first (see Fig. 4-7a, 5). After the photoresist has been removed via access holes (see Fig. 4-7a, 8), the access holes can be sealed by sputtering a metal layer or melting Pb/Sn solder (see Fig. 4-7a, 9 and 10). If the final sealing step is handled inside a vacuum chamber, a sealed vacuum of about 1.5 torr can be obtained. Figure 4-7b and c show a schematic drawing of a sealed Pirani vacuum sensor and electroplated nickel thick-film cap, respectively. One drawback of this process is that the photoresist-removal step may take several hours. Recently, a novel encapsulation technique used a thermal decomposition step within the temperature range of 180 to 260°C to vaporize the sacrificial polymer via a permeable polymer overcoat, resulting in an encapsulated cap made of the suspended polymer overcoat,59 as shown

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g NI

Cr/Al Si 1. Pattern Cr/AI feed-throughs

PR

PR

Si

Si

PR Si

2. Pattern 3. Evaporate Cr/Au 4. Define plating sacrificial PR seed layer mold

NI

NI

PR

PR

Si 6. Strip PR and AU

PR Si 5. Plate Ni

NI

NI

NI

Si

Si

Si

Si

7. Strip Cr/Al

8. Strip PR

9. Sputter Cr/Au

10. Plate Au

(a) Dielectric membrane Package lid

Cr/Pt resistor

Rounded tethers Cr/Au contacts

Polysilicon Polysilicon anchor feed-throughs

(b)

AccW Spot magn WD Exp 500 μm 10.0 kV 3.0 70x 9.3 1 EMAL XL-50 FEG SEM

(c)

FIGURE 4-7 Wafer-level packaging approaches using low-temperature processes to form the wafer-level encapsulation, in ref. 58.

in Fig. 4-8b to d and f. The hermetic sealing can be realized by additional sputtered metal on top of the polymer overcoat (see Fig. 4-8e and g). Moreover, a sealed vacuum of around 1 torr or less can be achieved by conducting the metal hermetic sealing step inside a vacuum chamber. There are several advantages to this technology, such as 1. Low-temperature processing. The technology is suitable for packaging of MEMS devices that are sensitive to high temperatures and thermally induced residual stress. 2. Low cost and simple packaging. Both the sacrificial and the overcoat polymers can be made photosensitive. The process does not require cap-to-wafer alignment or a wafer-bonding step. 3. High-yield process. Thermal decomposition of the sacrificial polymer is used instead of etching, which is stictionless, structurally benign, and easily controlled. In summary, recent progress in wafer-level encapsulation technology has proven to be versatile and can be extended to any device that does not need direct physical contact with the ambient

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Chapter Four Embedded cavity Insulator

Si beam

(a) Unity

(b) Polymer overcoat (f) (c)

Gold coating Polymer overcoat Vacuum channel

(d) Metal t Ch

tC

1-μm gap (e)

(g)

Beam 50 μm

FIGURE 4-8 Wafer-level packaging approaches using low-temperature encapsulation steps involving polymer and metal coatings, ref. 59.

(e.g., accelerometers, gyroscope sensors, MEMS resonators, RF switches, varactors, and filters). The footprint of MEMS package using this technology is always smaller than that with the bondedcap approach because it does not require extra bonding area in the bonding ring region. Both planar and vertical interconnects can be realized with this technology.

4.4 Wafer-Level Chip Capping and MCM Technologies In addition to wafer-to-wafer bonding–based packaging solutions, a silicon chip with a V-groove cavity can be used as a cap chip to form a sealing cap on top of a MEMS structure on a wafer. This step can be implemented using the common flip-chip bonding technology. Discrete components such as IC chips and capacitors can be assembled on the wafer by the same flip-chip bonding approach. After chip separation, the diced MEMS chip is a carrier chip that hosts the other function chips that require different process technologies to fabricate. An epoxy-based molding step is used to finish the package for such devices. Module-like devices for such applications as RF MEMS, optical MEMS, and wireless sensor nodes can be created with this approach. This approach reflects the concept of a

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g system-in-a-packaging (SiP) solution. A similar approach uses ceramic substrates with cavities to host MEMS chips and other function chips inside the cavities. The standard high-density interconnect (HDI) process consists of embedding bare die into cavities milled into a base substrate and then fabricating a thin-film interconnect structure on top of the components. Each layer in the HDI overlay is constructed by bonding a sheet of dielectric film onto the substrate and forming via holes through a laser ablation process. The Ti/Cu/Ti metallization used for the die interconnects then is created through sputtering and photolithography.60 A device packaged in this manner is called a multiple-chip module (MCM), and it incorporates epoxy-mounted MEMS chips, ICs, surface-mount capacitors, and thick-film resistors. Combining MCM and HDI technology for optical MEMS packaging has been demonstrated.60 Moreover, electrical interconnects can be realized by wire bonds in an MCMpackaged MEMS pressure sensor.61 Another unique technology deploys localized heating to avoid the potential constraints owing to wafer-bonding temperatures because the wafer-bonding temperature must be compatible with all on-chip components, such as microstructures, metallization lines, and integrated circuitry, when the entire wafer is subjected to the same waferbonding temperature in a wafer-to-wafer bonding process. However, for reliable bonding and a hermetically sealed bonding interface, appropriate wafer-bonding technologies such as Au/Sn solder–based eutectic bonding at 280°C, Au/Si eutectic bonding at 365°C, and glassfrit bonding at 400°C normally are used. With this background as motivation, a microresistive heater is integrated into the bonding area either on the substrate or on the capping wafer. After the wafers are brought into contact, the bond is created by locally heating the bonding area via biasing the integrated microheater.62 Based on the reported simulation data,62 a thermal insulating layer (e.g., an SiO2 film) deposited on the thermally conductive substrate (e.g., silicon) can effectively prevent the temperature-sensitive MEMS components from being affected by the high bonding temperatures generated by the microheater during the heating step. With selection of the appropriate material combinations, Au-Si eutectic bonding, Si-glass fusion bonding, and indium solder bonding have been used for demonstrating this localized heating and bonding concept. Either in the wafer-based batch-type process or the chip-based approach, the techniques for preparing the solder pattern on wafers for bonding include stenciling, dip coating, electroplating, and evaporation/sputtering. The technical challenges of this process include uniformity control of the solder pattern, thickness, and composition. B. H. Stark and K. Najafi reported a molding and transferring technology that provides a way to solve these challenges. They reflowed the solder paste in cavities with accurate volume inside a vacuum chamber so as to convert the solder paste to a discrete solder

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Chapter Four ball in each cavity. Then this solder mold was aligned and bonded with the MEMS device wafer in a vacuum. By bonding at 260°C for 2 hours with Bi/Sn solder, a vacuum-packaged cavity that can withstand 1.5 torr can be achieved.63

4. 5 Wafer-Level MEMS Packaging Based on Low-Temperature Solders: Case Study As discussed in Sec. 4.2.6, formation of the bonding interface at low temperature with low-temperature solder (e.g., indium) has attracted a lot of research attention in the creation of hermetically sealed packaging. In order to withstand higher postbonding process temperatures, high-melting-temperature IMCs formed after low-temperaturesolder bonding are preferred. Stable and high-temperature resist bonding interfaces rely on the formation of IMCs of high melting temperature from a low-melting-point (LMP) component such as In or Sn and a high-melting-point (HMP) component such as Au, Ag, or Cu. Looking into the mechanisms of bonding-interface formation using low-temperature solder, two mechanisms are reported. Pure indium is melted at 156.6°C, as seen in the phase diagram in Fig. 4-9a. Reaction between the melted indium (LMP component) and Au, Ag, or Cu (HMP component) is the first mechanism.44–47

0

10

20

Atomic percent indium 30 40 50 60 70

80

90

100

1000 961.93°C 900

Temperature, °C

800 700

670°C

695°C β

L

680°C

600 500 ζ

(Ag)

400 300

187°C

100

α′

205°C 166°C AgIn2

200

γ

0 0 Ag (a)

10

20

30

40

50

60

166.634°C 144°C

70

80

(In)

90

Weight percent indium

FIGURE 4-9 (a) The In-Ag phase diagram. (b) The In-Sn phase diagram.

100 In

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g Weight percent tin 0

10

20

30

40

50

60

70

80

90

100

250 95.7 224°C 200

231.9681°C

L

Temperature, °C

156.634°C 14 10 12

150

120°C 44 48.3

100 β

(In)

γ

50 (βSn)

(αSn)

0 0 In

10

20

(b)

30

40

50

60

70

80

90

130°C

100 Sn

Atomic percent tin

FIGURE 4-9 (Continued )

In-Sn eutectic solder bonding without reaction to form the highmelting-point IMCs is the second approach38,39 (Fig. 4-9b). Considering the bonding temperatures and the formation of void-free joints and reliable IMCs, Sn/Au and In/Au systems have been studied extensively.64,65 Section 4.5.1 will report our recent results of investigations into the reliable high-melting-point IMCs in the In/Ag system for wafer-bonding-based MEMS packaging applications. More important, the use of Au would lead to a high cost for wafer bonding. Compared with Single-component solder of Sn or In, the In-Sn alloy is very attractive because of its low eutectic temperature (118°C) and good wettability with various common substrates. Since Cu is used widely in modern IC packaging technology and in 12-in CMOS process technology and is much cheaper than Au, Sec. 4.5.2 will report on the use of In-Sn of eutectic composition for Cu-based metallization.

4.5.1

Case Study: In/Ag System of Noneutectic Composition

In the In-Ag phase diagram (see Fig. 4-9a),66 the eutectic temperature is seen to be 144°C at 96.5 wt% In, whereas the melting temperatures of indium and silver are 156.7 and 961.9°C, respectively. Without using the eutectic composition, the HMP:LMP ratio of the overall

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Chapter Four Cap wafer UBM (Ti/Cu/Ni/Au)~1 μm Ag 4 μm In 2 μm Ag 0.1 μm Ag 0.1 μm In 2 μm Ag 4 μm UBM (Ti/Cu/Ni/Au)~1 μm Substrate wafer

FIGURE 4-10 The intermediate bonding layers on both sides of a bonding pair of wafers, where the schematic drawing shows the thin silver coating of both sides arranged face-to-face.

intermediate bonding layer (IBL) is selected to be high enough that the LMP component is essentially depleted into the HMP layer and reacted into high-melting-temperature IMCs. Figure 4-10 shows the IBL combination on both bonding surfaces of a pair of 8-in wafers. The IBLs include 2-μm In and 4-μm Ag layers, which are evaporated and patterned using the lift-off process on the top of the Si device wafer coated with a 300-Å Ti, 3000-Å Cu, 5000-Å Ni, and 1000-Å Au under-bump metallization (UBM) layer. Owing to the high interdiffusion rate within the layers of the IBL, some IMCs can be formed between the noble metals and indium even at room temperature. We take advantage of this and prepare a thin Ag layer of 1000 Å on top of the In layer to form a thin layer of AgIn2 at the surface. This will prevent oxidation of In layer below when these wafers are prepared and exposed to air after chamber opening. Thus we can avoid flux treatment of the wafer surface before the wafer-bonding step, so we say that it is a fluxless process. The weight percentage of the 2-μm In layer versus the 4-μm Ag layer is 25.4 percent. From the Fig. 4-9a, this 25.4 wt% In composition implies that the homogeneous phase of the bonded interface layer will be the solid solution of α′ phase and Ag. But the actual IMC phases of the bonded interface layer strongly depend on the layer sequence, interdiffusion process, and bonding conditions. In addition to the α′ phase, more IMC phases with In of 22 wt% up to 34 wt% are expected to be seen from our experimental results. Practically, the IMC phases containing In within this weight percentage range are the γ, ζ, and β phases, where these are the stable phases in each specific temperature range from ambient up to 695°C. Again, from Fig. 4-9a, we should notice that the melting point of IMCs increases with silver content, that is, eutectic composition (144°C) < AgIn2 (166°C) < γ (300°C) < ζ (670°C) < β (695°C).

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g Bonding ring of intermediate layer

Comb electrodes Comb electrodes

Torsion bar

Mirror

Mirror plate

Electrical isolation trench

Torsion bar

Comb electrodes

Posts of electrical feed-throughs

(a)

(b)

FIGURE 4-11 (a) Schematic top-view drawing of the micromirror device. (b) SEM photograph of the fabricated micromirror with two sets of vertical comb electrodes and a torsion bar.

In order to explore the feasibility of MEMS packages based on this concept, we developed an integrated process flow for making micromirror wafers and cap wafers. A silicon-on-insulator (SOI) wafer with a device layer of 30 μm, a buried oxide (BOX) layer of 2 μm, and a handle wafer of 690 μm was used for constructing the micromirror. Two steps of the DRIE process are carried out to pattern structures of the comb actuator and mirrors from the front side and to open the backside cavity for releasing the mirrors, respectively. Figure 4-11 shows a schematic drawing and scanning electron microscope (SEM) photograph of the micromirror device, respectively. The center white area represents the reflection mirror. After the backside cavity of the mirror wafer is sealed by bonding with another wafer on the backside, a dry film of photoresist is attached and lithographed on top of the mirror wafer. The In/Ag IBL is prepared by evaporation and lift-off steps. Finally, the whole mirror device is enclosed in an In/Ag IBL ring. The same In/Ag IBL ring is prepared separately on cap wafers containing a glass wafer on a silicon wafer with through-wafer holes. During the bonding process, these wafers are aligned and put into a bonding chamber under 6 mtorr of pressure first. Then the fluxless solder bonding is conducted at 180°C for 40 minutes under 8 kN of applied bonding force. Both the hermetically sealed ring and the electrical interconnects are formed at this bonding step. As shown in Fig. 4-11a, two metal posts on the mirror chip are separated electrically by a silicon trench. These two metal posts are connected electrically via a metal line on the cap-wafer side. The metal posts cross underneath the solder sealing ring with dielectriclayer passivation. Thus the hermetic sealing can be kept inside the sealed cavity. Figure 4-12a shows a top view of the bonded 8-in wafers. Figure 4-12b shows the wafer-bonding-packaged micromirror chip after dicing, whereas Fig. 4-12c shows an x-ray image of the bonded

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Chapter Four

(a)

(c)

(b)

(d)

FIGURE 4-12 (a) The bonded 8-in-diameter stack wafers. (b) Top-view photograph of separated micromirror chip with the reflective mirror at the center. (c) X-ray image of one chip area of cap wafer with bonding ring shown in dark square ring pattern. (d ) Photograph of diced micromirror chip after assembly on a DIP carrier.

wafer is taken from the cap-wafer side. The bright square in the center of micromirror chip in Fig. 4-12b is the reflective micromirror. Then the wafer-bonding-packaged micromirror chip is assembled on a dual in-line package (DIP) carrier for further device function testing, as shown in Fig. 4-12d.

Effect of Postbonding Annealing First, we conducted the postbonding annealing at 130°C for 24 hours for the wafer-bonding-packaged mirror chips after dicing in an N2filled furnace. Properly diced chips were mounted on epoxy resin and subsequently polished. The cross-sectional elemental composition of the bonded interface was characterized by energy dispersive x-ray spectroscopy (EDX). Samples were mounted on epoxy resin and subsequently polished. Figure 4-13 shows the weight percentage of all the components as a function of the depth along the bonded interface. Along the cross section of the bonded interface it is observed

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g 100 90

Weight percentage, %

80 70 Ag In Ti Ni cu

60 50 40 30 20 10 0

0

1

2

3

4

5 6 7 8 9 10 11 12 13 14 15 Interface thickness, μm

FIGURE 4-13 EDX analysis data along a cross section of the bonded interface.

that there is an intermediate layer of a homogeneous composition with a thickness of about 7.5 μm at the center zone. The composition ratio of this intermediate layer is referred to as the Ag9In4 IMC phase mainly, whereas the IMC phase at 7 μm is called the Ag2In phase because both Ag2In and Ag9In4 are the observed phases based on crystal structure analysis by XRD for the samples bonded at 180°C.67 It also should be noticed that there is a thin pure Ag layer of about 1 μm thickness on both sides of the IBL. These two pure Ag layers are referred to the remaining Ag on top of the UBM layers on the two bonding wafers. It also means that the current IBL design leads to IMCs with high remelting temperatures (e.g., γ of 300°C and ζ of 670°C). In other words, the HMP:LMP ratio of the IBL in Fig. 4-10 is an appropriate combination. The bonded interface of Ag9In4 and/or Ag2In IMC phases and pure Ag will guarantee a MEMS package with good high-temperature resistance to postbonding process temperatures (e.g., SMT peak temperature of 285°C).

Effect of Long-Term Room-Temperature Storage It has been reported that Ag2In and AgIn2 are the stable phases at temperatures above and below 100°C in an In-Ag diffusion-couple experiment using thick foils of pure In and Ag.68 When the diffusion couple with a dominant IMC of Ag2In was cooled down and maintained at room temperature for a long time, the Ag atoms diffused from some Ag2In grains into the adjacent pure Ag grains, and In atoms from adjacent pure In grains diffused into the Ag2In grains.

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Chapter Four Some of these Ag2In grains gradually became AgIn2 grains. In a later stage, the grain boundary of these AgIn2 grains expanded continuously by consuming adjacent Ag2In grains (i.e., the grain-growth process). Eventually, AgIn2 became the major IMC phase along the interface of the diffusion couple after room-temperature storage for a long time (e.g., 1 month).68 Because of this, we have kept diced chips in N2-filled containers at room temperature for 80 days (the chips were derived from bonded wafers that were bonded at 180°C for 40 minutes). We investigated the bonded interfaces of these chips via EDX analysis. Figure 4-14a shows a SEM photograph of the bonding-interface cross section denoted along with the phase composition, whereas the Fig. 4-14b shows the measured EDX results, which are plotted versus the position of bonding interface. In addition, the original positions of all layers except the UBM are marked on the left side of Fig. 4-14a. Figure 4-14c and d shows the results from another chip. First, no pure In phase is observed. We also concluded that both Ag2In and AgIn2 coexist in the bonding interface after room-temperature storage of 80 days. Some data points are derived with a weight percentage close to that of Ag9In4, as shown in Fig. 4-14c. For example, the composition at 3.3 μm in Fig. 4-14d is matched with Ag9In4. This observation is in agreement with previous bulk-based diffusion-couple results.68

Effect of Aging When we consider the postdicing chip-assembly process, such a process typically involves baking of the solvent and/or curing at low temperature. In the case of a packaged MEMS devices used in some high-temperature environment, the question becomes, What is the influence of such aging treatment? Thus we have kept diced chips in an N2-filled container at 70°C for 80 hours (where these chips have been stored at room temperature for 80 days and were derived from a bonded wafer that was bonded at 180°C for 40 minutes). The EDX results of a cross section of the bonded interface are shown in Fig. 4-15. We have conducted several line-scan analyses. Two of these line-scan data results are plotted in Fig. 4-15b and c. These data consistently show that the amount of AgIn2 phase is increasing when we compare these samples with long-term room-temperature storage samples and the as-bonded samples. However, the bonding interface does not convert into single IMC AgIn2 phase after this aging at 70°C for 80 hours. Given that the original weight ratio of Ag/In in the present IBL combination is 2.94, we strongly believe that the single IMC phase of AgIn2 will never happen at the bonding interface even after an extremely long period of low-temperature aging. The melting temperature of AgIn2 is 166°C. Thus the existing AgIn2 may be a concern in terms of long-term reliability.

Effect of Additional Postbonding Annealing In the last part of the experiment, we explored the influence of annealing. We have kept diced chips in an N2-filled container at 120°C for 80 hours

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g

Mixture of Ag2In and AgIn2

Ag

Mainly Ag2 In

In Ag In

Mainly AgIn2

Ag

(a) 100 In

Ag

Weight %

80 60 40 20 0

(b)

0

2

4

6

8

12

10

Position along cross section of the bonded interface (μm)

AgIn2 Mixture of AgIn2 and Ag2In Ag9In4 Mixture of AgIn2 and Ag2In

Ag In Ag In

Ag2In/Ag9In4

Ag AgIn2

(c) 100 Ag

In

Weight %

80 60 40 20 0

(d)

0

2

4

6

8

10

12

Position along cross section of the bonded interface (μm)

FIGURE 4-14 Study of the bonded interface after long-term room-temperature storage: (a) SEM photograph of first chip with the identified IMC phases denoted; (b) EDX data derived from the spots shown in part a; (c) SEM photograph of the second chip denoted with the identified IMC phases denoted; (d ) EDX data derived from the spots shown in part c.

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Chapter Four

A

B

Ag AgIn2

AgIn2 In Ag In

Mixture of Ag2In and AgIn2

Ag

Mixture of Ag2In and AgIn2 Ag

(a) 100

Weight %

Ag

A scan

80

In

60 40 20 0

0

2

4

6

8

10

12

Position along cross section of the bonded interface (μm)

(b) 100

B scan Weight %

80 Ag

In

60 40 20 0

(c)

0

2

4

6

8

10

12

Position along cross section of the bonded interface (μm)

FIGURE 4-15 Study of the bonded interface under low-temperature aging: (a) SEM photograph showing the identified IMC phases; (b) EDX data derived from scan-line A in part a; (c) EDX data derived from scan-line B in part a.

(and these chips have been stored at room temperature for 80 days and were derived from a bonded wafer that was bonded at 180°C for 40 minutes). The SEM photograph and line-scan-based EDX results of the cross section of the bonded interface are shown in Fig. 4-16. Interestingly, single-phase IMC of Ag2In has been observed and occupies the major portion of the bonding interface. Compared with the case in Fig. 4-13 (i.e., with existing pure Ag phase on both sides), Fig. 4-16 shows very limited thickness of the remaining phase other than Ag2In.

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g

A

B

Ag In Ag In

Ag2In

Ag

Ag2In

Mixture of Ag, In, Ti, and Ni

Mixture of Ag, In, Ti, and Ni

(a) 100 Ag

A scan

In

Weight %

80 60 40 20 0

0

(b)

2

4

6

8

10

12

Position along cross section of the bonded interface (μm) 100

Weight %

Ag

B scan

80

In

60 40 20 0

(c)

0

2

4

6

8

10

12

Position along cross section of the bonded interface (μm)

FIGURE 4-16 Study of bonded interface under additional annealing effect: (a) SEM photograph with identified IMC phases denoted; (b) EDX data derived from scan-line A shown in part a; (c) EDX data derived from scan-line B in part a.

This result points out that appropriate low-temperature annealing (e.g., at 120°C for 80 hours) can effectively get rid of low-meltingtemperature IMC phases, that is, AgIn2. In particular, the composition at the 2-μm position of the scan in Fig. 4-16a is quite close to Ag9In4. We can imagine that such annealing at 120°C for 80 hours could be well accepted by most packaged MEMS devices. Thus we can apply this annealing step to refine the microstructure of the sealing rings of packaged MEMS devices.

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Chapter Four

Ag wt%

In wt%

100.00

0

100.00

0

70.77

29.23

71.39

28.61

68.07

31.93

69.38

30.62

65.11

34.89

67.6

32.40

69.68

30.32

67.53

32.47

100.00

0

Cu Ti, Ni, and Cu Ag

Ag

In Ag In

Ag2In/Ag9In4

Ag Ag Ni, Ag, and Cu

10 μm

FIGURE 4-17 SEM photograph of the bonded interface after prolonged additional annealing. EDX results are shown on left side, and the suggested IMC phases are shown on right side.

On the other hand, some microcracks are observed at the bonding interface for the samples that underwent an even longer annealing step (i.e., 120 hours at 120°C). Figure 4-17 shows that the dominant phases are Ag2In and Ag9In4, whereas microcracks appear at the bonded interface. Both Ag2In and Ag9In4 are the high-melting-temperature phases and are desired to be the final IMCs at the interface. Moreover, to explore the reason behind such microcracks, we first calculate the density of AgIn2 as 8.43 g/cm3 and the density of Ag2In as 9.78 g/cm3. Then we determined the corresponding volume change of AgIn2 in unit mass to Ag2In in unit mass as an increment of 13.8 percent. The IBL ring structure is confined between two substrates and cannot absorb 13.8 percent volume expansion easily. Thus the residual stress eventually leads to the observed microcracks. A meander trace on the IBL ring and a narrow ring may be potential ways to release the residual stress so as to avoid microcrack generation. High-melting-temperature IMCs of Ag9In4 and Ag2In at the interface are derived after additional annealing at 120°C for 80 hours for samples after long-term room-temperature storage. The melting temperature of IMCs of Ag9In4 and Ag2In is higher than 400°C. This implies that appropriate annealing can get rid of low-melting-temperature IMC phases (e.g., AgIn2). However, prolonged annealing in this situation leads to the generation of microcracks because the IBL ring faces a significant volume change from phase transformation (i.e., from AgIn2 into Ag2In).

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g

4.5.2

Case Study: Eutectic InSn Solder for Cu-Based Metallization

In order to obtain a high yield of good bonded dies via wafer bonding, issues of wafer warpage and topography differences along the bonding rings across a wafer can be overcome by a solder-reflow step when sufficient solder is placed in the bonding rings. However, the LMP solder has to be fully consumed by reacting with HMP metals during the bonding and annealing steps to form reliable and hightemperature-resistant IMC phases at the bonding rings for hermetic sealing applications. This suggests that solder layers of reasonable thickness are an important case-sensitive parameter. We have studied the interface microstructure of Sn/In/Au/Cu metallization after solder deposition in detail. Since the diffusion rates between low-temperature solders and HMP metal substrates such as Cu and Au are very high, a portion of the as-deposited solders on the HMP metal would be consumed before the wafer-bonding step. As shown in Fig. 4-18, it is obvious that extensive interdiffusion between

InSn

AuIn2

Cu6(Sn,In)5

Cu

1 μm

1 μm

FIGURE 4-18 TEM analysis of thin Au0.03/(InSn)3/Au0.03/Cu2 metallization after deposition (thickness in microns). In order to accelerate the interdiffusion between Sn and In and to obtain an In-Sn alloy before bonding, 10 thin alternative In/Sn solder layers with each layer 0.3 µm thick were deposited by E-beam evaporation. The Au layers were deposited to protect the Cu and solder from getting oxidized.

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Chapter Four solder materials (i.e., Sn and In) and Au/Cu layers occurs. On the Cu substrate, Cu6(Sn, In)5 ternary phase was formed owing to interdiffusion. Additionally, Au diffused toward the solder side to from the AuIn phase, which was found inside the Cu6(Sn, In)5 phase. The residual low-temperature SnIn phase is located at the top of the interface, as shown by the dashed line in the figure. Based on preliminary 8-in wafer-bonding results using these SnIn/Au/Cu layers, complete depletion of the low-temperature solders in the as-deposited films would lead to a low yield of good bonded dies.69,70 Owing to the lack of reflow function provided by low-temperature solders, large voids and cracks were found inside the joint, and the hermeticity was quite poor. We screened the bonded dies after dicing by using cross-sectional scanning acoustic microscopy (C-SAM). A die was labeled as a “good die” if there were no detectable voids and/or cracks under C-SAM. The bonding yield was further defined as the percentage of “good dies” to the “bad dies” of a bonded wafer. As listed in Table 4-3, the bonding yield was 44 and 67 percent with a pressure of 3 and 5.5 MPa at 180°C for 20 minutes. Limited improvement was observed when the bonding pressure was increased.70 Therefore, prevention of interdiffusion between LMP and HMP components during the fabrication process and room-temperature storage is the key to obtaining high-yield wafer-to-wafer bonding. As described in Fig. 4-19, a thin buffer layer is introduced in between the Cu substrate and the solder layers such that interdiffusion is inhibited, whereas this thin buffer layer preferentially dissolves into the melted solder quickly at the beginning of soldering reaction (see Fig. 4-19b and c). Then the diffusion between the liquid solder and the Cu starts, and finally, all solder was converted into IMCs (see Fig. 4-19d). Since the buffer layer saves the low-temperature materials for a successful solder-reflow step during bonding, the production yield of wafer bonding is improved significantly. Ni is well known as a barrier layer for Sn-based solder and Cu substrate, and at the same time, it can easily diffuse into Cu-based IMCs.71 Thus a thin Ni buffer layer was chosen and investigated to control diffusion mechanism between In-Sn solder and Cu. For In/Sn/Cu systems after eutectic bonding, we hope that all low-temperature phase can be converted to high-temperature IMCs. According to the ternary-phase diagram of Cu-In-Sn, the calculated thickness ratio of Cu to In-Sn needs to be larger than 0.5 to form Cu6(Sn, In)5 compounds. To protect In-Sn from oxidization, a thin Au layer is deposited on top of the solder layers. Since In will form Au-In IMCs with Au, there will be two kinds of IMCs in the final seal joint: Cu6(Sn, In)5 and Au-In. To get a robust joint, the Au layer should be as thin as possible to reduce the volume of the Au-In IMC. To validate this new combination of materials for wafer bonding, we conducted a wafer-bonding experiment. First, 300-Å-thick SiO2 and 1500-Å-thick SiN were formed on a silicon wafer by thermal oxidation

Cap Wafer (Thickness in Micron) Wafer Pair 1 2

HMP Component Cu2/Au0.03 Cu2/Au0.03

Solder (Sn/In)3∗ (Sn/In)3∗

Bottom Wafer (Thickness in Micron) HMP Component Cu2/Au0.03 Cu2/Au0.03

Bonding Parameter Pressure (MPa)

Temperature (∞C)

Time (min)

Yield (%)

†

3.0

180

20

44

†

5.5

180

20

67

Solder (Sn/In)4

(Sn/In)4

∗Ten layers in turn, each layer was 0.3 μm. † Ten layers in turn, each layer 0.4 μm.

TABLE 4-3 Bonding Experiments of In-Sn Low-Temperature Solders versus Cu Bonding Rings

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Chapter Four • Buffer layer Copper Copper

Copper

Liquid solder

Liquid solder

Copper

Copper

Solder • Au Solder Copper (a)

(b)

(c)

IMCs

(d)

FIGURE 4-19 Schematic drawing of the role of a buffer layer during bonding: (a) before bonding; (b) liquid solder formed at the beginning of wafer bonding; (c) buffer layer dissolved into solder; (d ) high-temperature IMC joint finally formed during bonding.

and the LPCVD process. They acted as a photolithography mask for cavity etching. A cavity with a 6 × 6 mm2 area and 250-μm depth was formed using a KOH wet-etching process inside each bonding ring on both the cap wafer and the bottom wafer. By using photolithography to pattern dry film as a lift-off mask, Ti/Cu/Ni/Au metallization was sputtered on Si/SiO2/SiN substrate as the HMP component for diffusion bonding. The thickness of Ti/Cu/Ni/Au metallization was designed as 0.05, 2, 0.05, and 0.03 μm, respectively. The multilayered bonding-ring structure is shown in Fig. 4-20. The thin Ti layer acting as the adhesive layer is not shown in the figure, and the Ni is the buffer layer. We used the well-known Ti/Cu/Ni/Au under-bump metallization (UBM) process to prepare the HMP component while we increased the thickness of Cu layer up to 2 μm. Thus we called these HMP rings UBM rings. Then the solder layers and Au protection layer were deposited in turn in an E-beam evaporation chamber. After another dry-film-strip step, 300-μm-wide square bonding rings 11 mm long were finally fabricated on a wafer with

Au In Sn Ni Cu

FIGURE 4-20 Schematic depiction of the InSn solder versus Ti/Cu/Ni/Au UBM metallization.

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g cavities. After deposition and dry-film stripping, O2 plasma descum was conducted before the bonding process to remove the oxide layer and organic contaminants to produce a clean surface. In the waferbonding step, two wafers with cavities enclosed by bonding rings were aligned and brought into the vacuum chamber of a commercial wafer bonder. When the wafers were heated up to 180°C (i.e., bonding temperature), a bonding pressure of 5.5 MPa was applied to press the bonding-pair wafers into tight contact for 20 minutes. After the bonding step, the wafer was diced into chips of 13 × 13 mm2 in which each chip has a vacuum cavity sealed inside the bonded structure (Fig. 4-21). Scanning acoustic microscopy (SAM) was deployed for nondestructive study of the bonding interface. There were no detectable voids in any single seal ring. This meant that a 100 percent yield after bonding was achieved by this bonding method. A typical C-SAM graphs of dies is shown in Fig. 4-22.

FIGURE 4-21 Photo of a successfully bonded wafer with 100 percent yield.

FIGURE 4-22 SAM graph of bonded devices using Ti/Cu/Ni/Au UBM. The bonding temperature was 180°C.

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Chapter Four Each bonding ring was a uniform gray color, indicating the bonded joints have intimate contact. The hermeticity of the ring seals for pattered dies was evaluated by helium leak-rate testing (MIL-STD-883). A shear test was done with a shear tester (BT4000 Dage) using a speed of 50 μm/s. Reliability tests of the bonded devices was studied in detail. A pressure-cooker test was conducted at 121°C and 2 atm for 300 hours. High-humidity storage was done at 85°C and 85 percent relative humidity (RH) for 1000 hours. A high-temperature storage test at 125°C and a temperature cycling test (–45 to 125°C) for up to 1000 hours also were performed. For each item, 21 chips were tested. After the tests, these chips were examined by SAM and helium leak-rate and shear tests again.

Reliability Study The microstructure of the bonded interface is shown in Fig. 4-23 in the case of 180°C bonding. In the center region of the bonded interface, thick residual Cu and a thin IMC layer were found, as shown in the figure. Two kinds of IMCs were detected by EDX. One composition (atomic percent) is Cu:Ni:In:Sn = 56.17:4.63:12.37:26.84, which also corresponds to the η phase, that is, (Cu, Ni)6(Sn, In)5. Another is AuIn2 phases with white-particle morphology. According to the present materials design, the thickness of the seal joint should be around 10 μm. However, the actual thickness value achieved was about 7 μm. Under the present bonding temperature, solder materials melt fast and have good flowability. When bonding pressure was applied, a portion of the liquid alloy squeezed out. As shown in Fig. 4-23b, the length of the squeezed solder was about 80 μm. In order to know the kinetics of the bonding process involving the Ni buffer layer, TEM/EDX analysis was performed on the seal joint. The results are shown in Fig. 4-24 and Table 4-4. It was found that the

Au(In, Sn)2 Cu

Cu

Squeezed solder (Cu, Ni)6(Sn, In)5

(a)

(b)

FIGURE 4-23 Interfacial microstructure of the joint bonding at 180°C: (a) center region of the joint; (b) bonded joint of two wafers.

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g

0.5 μm

FIGURE 4-24 TEM/EDX analysis of the seal-ring joint after bonding. In order to find the trace of the Ni buffer layer, the analyzing position is near the residual Cu.

Element (at%) Position

Cu

1

88.1

2

47.4

3

32.6

8

4

36.5

11.7

5

5.7

6

11.6

7

42.6

TABLE 4-4

Ni 4.8

6

Sn

In

7.1

4.8

35.4

17.2

43.2

16.2

Au

45

6.8

6

55.1

33.3

13.2

47.6

27.7

41.8

9.6

Compositions of Selected Positions of TEM/EDX

Analysis

phase adjacent to the Cu substrate was Cu6(Sn, In)5, and next was (Cu,Ni)6(Sn, In)5. Island shape Au(In, Sn)2 phases embedded in the (Cu, Ni)6(Sn, In)5 phase also were identified. These results confirmed that the Ni buffer layer had been dissolved into a Cu6(Sn, In)5 IMC and formed a (Cu, Ni)6(Sn, In)5 phase in some regions. The content of Ni in this quaternary phase can reach 11.7 at%. The bonding process involving the buffer layer can be explained as follows: First, owing to the slow reaction between solder and Ni at room temperature, a major portion of the solder remains on top of the Ni

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Chapter Four buffer layer. When wafers are heated up to the bonding temperature, the solder melted and started to react with the thin Ni buffer layer. The Ni dissolved into the solder as Ni3Sn4 or NiInSn ternary phase72,73 according to studies of the interfacial reactions between liquid InSn solder and Ni. Since the Ni buffer layer is very thin, after a short time, InSn solder started to react with Cu to form Cu6(Sn, In)5 compounds. Since Ni has great solubility in the Cu6(Sn, In)5 compounds, a chemical potential gradient was generated, which led to dissolution of the Ni-containing compounds. Finally, all Ni atoms went into Cu6(Sn, In)5 solution to form the (Cu, Ni)6(Sn, In)5 phase. The testing results showed that the leak rates of all the samples bonded at 180°C were less than 5 × 10–8 (atm · cc)/s, which indicated that the dies obtained acceptable hermeticity based on the criteria of MIL-STD-883. The average shear strength of the joints was 32.13 MPa, which meant that robust bonding strength was achieved for these patterned dies. These results indicate that the Ni buffer layer plays an important role in achieving high-yield wafer-level hermetic bonding. The results of the reliability tests show that ratios of dies with a leak rate of less than 5 × 10–8 (atm · cc)/s after the pressure-cooker test, high-humidity storage, high-temperature storage, and temperature cycling were 71.4, 90.5, 76.2, and 81 percent, respectively. Meanwhile, the tested chips still maintain good mechanical properties. The shear test after pressure cooker test, high humidity storage, high temperature storage and temperature cycling were 27.08, 15.37, 12.32, 16.71 MPa, respectively. As shown in Fig. 4-25, the interfacial microstructures were analyzed after the reliability tests as well. The results show that embedded AuIn compounds congregated and that the size of the accumulation became larger at the interface. With further EDX analysis, the compositions of the bonding interface do not show any detectable change. Such results are reasonable because the temperatures for the reliability tests was not high enough to introduce phase changes at the IMC joints. However, based on the shear-test results, we believe that the adhesion between different IMCs decreased after reliability testing. Bonded chips with poor hermeticity were analyzed to know the failure mechanism of the bonding interface after reliability testing. As shown in Fig. 4-26, visible cracks throughout the bonding interface were found in these samples with poor leak-rate test results. It is clear that the crack expanded along the interface between AuInSn compounds and CuSnIn compounds. Stress generated at the interface between different IMCs when bonded chips were tested under thermal cycling and the pressure-cooker test. This is the reason why after these two tests, the leak-rate test revealed a relative poor hermeticity results compared with other tests. This implies that the adhesion between the two IMC phases is the key to determining the reliability of the bonded chips. Two ways are proposed to improve reliability further. The first is to reduce the amount of AuInSn compound

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g

(a)

(b)

(c)

(d)

FIGURE 4-25 Interfacial microstructure of the seal joints of good dies after reliability tests: (a) high-temperature storage; (b) temperature cycling; (c) high-humidity storage; (d ) pressure-cooker test.

(a)

(b)

FIGURE 4-26 Cracks along the interface after reliability tests: (a) temperature cycling; (b) pressure-cooker test.

by depositing a much thinner Au protection layer for fluxless bonding. The second approach is to increase the amount of low-temperature solder. As a result, the potential to form a continuous Au-rich IMC phase at the interface is reduced significantly. In this way, the reliability of the bonded interface can be improved.

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Chapter Four Low-cost and high-yield wafer-to-wafer bonding using In/Sn solder and a Cu/Ni/Au metallization system was investigated, and the process produced successful bonding at 180°C. Various tests were conducted to evaluate the reliability of the bonded devices. Cracks formed at the interface of the bonded chips after reliability testing are the main cause of deterioration of the bonded interface.

4.6

Summary and Future Outlook After a decade of research and commercialization, wafer-level packaging has proven to be a leading solution for MEMS packaging. In addition to the package size, cost, and performance advantages, wafer-level MEMS packaging provides a way for enabling a SiP-type of ultracompact and thin hybrid package that integrates MEMS, optoelectronics, signal-processing circuits, and even energy sources. In addition to the wafer-bonding type of MEMS packaging based on a BCB intermediate layer, a low-cost, near-hermetic package using a liquid-crystal polymer (LCP) substrate, cap, and sealing ring has been deployed widely for packaging CMOS image sensors nowadays. LCP is a thermoplastic polymer with barrier properties that are an order of magnitude greater than those of epoxy plastic materials. The permeability of LCP to water vapor and oxygen is close to that of glass. Without using wafers containing etched cavities, a thick LCP ring can be used as the necessary spacing layer between two bonded wafers that provides enough room for the motion of MEMS moving parts. A sealed LCP cavity can pass helium leak-rate testing (i.e., MILSTD-883E). However, this sort of testing may not be appropriate for polymer-type packages because it measures only fine and gross leaks without considering permeability and outgassing. Although LCPand BCB-based MEMS packages cannot be considered to be hermetic packages, they could be a cost-effective MEMS packaging solutions for consumer electronics applications. Some of MEMS devices require a controlled atmosphere in the cavity or even a vacuum-packaged cavity. Low-temperature-solderbased wafer bonding can be an effective and low-cost approach to enabling vacuum-packaged MEMS devices. The eutectic InSn solder versus Cu/Ni/Au UBM is characterized as a promising bonding-ring material combination. Wafer-level packaging of vacuum cavities brings the cost advantage of permitting simultaneous sealing of an entire wafer of cavities in a vacuum. This eliminates the manufacturing inefficiencies and costs involved in individual “pump down and pinch off” for archaic conventional metal or ceramic vacuum packages. Wafer-level packaging based on direct bonding, metal-intermediatelayer bonding, and metal-sealed encapsulation may provide the lowcost MEMS vacuum packaging solutions of the future. However, if we want to maintain the high vacuum over long lifetimes, the materials

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g and seals used must be leak-free, impermeable, and not sources of significant outgassing. The high surface-to-volume ratio of these microcavities makes the maintenance of packaged vacuum even more difficult in wafer-level MEMS packaging. These surfaces are reservoirs of adsorbed gases such as oxygen, carbon dioxide, and reactive gases. A plated metal surface is considered a major source of dissolved hydrogen, which is a potential device killer in some cases. Integrating getter film into the packaged cavities may be a good solution to overcome these concerns for enabling wafer-level MEMS vacuum packaging.33,74 On the other hand, the conventional standard of hermeticity based on MIL-STD-883E is invalid for cavity volumes of less than 1000 nl3. Currently, people measure wafer-level vacuumpackaged MEMS device characteristics and calibrate the measured data with data derived for devices tested in a well-controlled vacuum chamber with a known degree of vacuum. A MEMS resonator can allow us to discriminate the degree of vacuum from 0.1 torr to several tens of torrs.75 A Pirani sensor or a resistive type of thermal sensor with a suspended membrane structure on a V-groove may allow us to measure the degree of vacuum from ambient down to 0.1 torr,76 whereas a degree of vacuum of 4 mtorr can be detected using a bolometer or a resistive type of thermal sensor on the surfacemicromachined membrane with tight gap between the suspended membrane and substrate.77 It is also reported that Pirani sensors using proper readout circuits to counter the self-heating effect can allow us to measure the degree of vacuum down to 10–7 torr.78 However, more research effort is needed to establish the external wafer-level nondestructive characterization approaches for MEMS wafer-level vacuum packaging. Thus we may increase the testing speed and reduce cost.

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A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g 70. Yu, D.-Q., Lee, C., Yan, L. L., Choi, W.-K., Yu, A., and Lau, J. H. “The role of Ni buffer layer on high yield low temperature hermetic wafer bonding using In/Sn/Cu metallization.” Appl. Phys. Lett. 94:34105, 2009. 71. Li, J. F., Mannan, S. H., and Clode, M. P. “Lifetime of solid metals in contact with liquid solders for high temperature liquid solder assemblies.” Scr. Mater. 54:1773–1778, 2006. 72. Huang, C.-Y., and Chen, S. W. “Interfacial reactions in In-Sn/Ni couples and phase equilibria of the In-Sn-Ni system” J. Electron. Mater. 31:152, 2002. 73. Wang, S. S., Tseng, Y. H., and Chuang, T. H. “Intermetallic compounds formed during the interfacial reactions between liquid In-49Sn solder and Ni substrates” J. Electron. Mater. 35:165, 2006. 74. Lee, M. C., Kang, S. J., Jung, K. D., Choa, S.-H., and Cho, Y. C. “A high yield rate MEMS gyroscope with a packaged SiOG process.” J. Micromech. Microeng. 15:2003–2010, 2005. 75. Monajemi, P., Joseph, P. J., Kohl, P. A., and Ayazi, F. “Wafer-level MEMS packaging via thermally released metal-organic membranes.” J. Micromech. Microeng. 15:742–750, 2006. 76. Weng, P. K., and Shie, J.-S. “Micro-Pirani vacuum gauge.” Rev. Sci. Instrum. 65:492–499, 1994. 77. Gooch, R., and Schimert, T. “Low-cost wafer-level vacuum packaging for MEMS.” MRS Bull. 28:55–59, 2003. 78. Chou, B. C. S., Chen, Y.-M., Ou-Yang, M., and Shie, J.-S. “Sensitive Pirani vacuum sensor and electrothermal SPICE modelling.” Sensors & Actuators A, 53:273–277, 1996.

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CHAPTER

5

Optical MEMS Packaging: Communications 5.1 Introduction Optical microelectromechanical systems (MEMS) combine miniature optical components with elastic suspended springs and microactuators to perform unique and sophisticated functions such as beam steering, attenuation, and filtering in optical communications applications. This chapter discusses the development trends and state-ofthe-art technologies of optical switches and variable optical attenuators (VOAs) over the past few years. The tradeoffs among design, manufacturability, and reliability are explored and discussed in several cases. The technology evolution of optical MEMS in communications applications is scanned and explained in terms of optical configurations, actuator features, and packaging-technology progress. Although an electrostatic actuation mechanism is the mainstream approach in optical MEMS devices, other mechanisms show promising features in various application-specific situations. Both proof-ofconcept devices and commercialized products are introduced and discussed in this chapter. Quite a few reliability results prove that MEMS technology is a suitable solution in optical communications. Based on the indispensable features provided by optical MEMS devices, such as handling optical signals with protocol transparency, and data-rate and wavelength independence, optical MEMS technology finds a unique position in the telecommunications industry. Since the late 1990s, an optimistic telecommunications market forecast has stimulated enormous investment on optical MEMS technology because such technology has been recognized as indispensable in connecting other existing technologies to form an all-optical

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Chapter Five communications network. Telecommunication applications have become the new “killer applications” of optical MEMS.1 Many crucial MEMS-based components for telecommunications applications have been demonstrated and commercialized, such as optical switches, VOAs, tunable filters, tunable lasers, and reconfigurable optical add/drop multiplexers (ROADM). Comprehensive review articles can be found in refs. 2 through 6, whereas topical reviews on optical switches,7–9 VOAs,10 and tunable lasers11,12 also have been published. The requirements for optical communications components vary with the optical networks in which they are deployed. Optical network topologies typically are categorized as three major networks: long haul, metropolitan area, and access. Long-haul networks are the conventional long-distance point-to-point transport networks that can send signals across 1000 km before the need for regeneration. Metropolitan-area networks (MANs) refer to metropolitan-area corering networks that typically are hundreds of kilometers in length and do not use amplification. Access networks are the metropolitan-area access-ring networks, with stretches of a few to tens of kilometers (including the so-called last mile). Since the distance such a network covers is short, amplification is not necessary. Since the widespread deployment of wavelength-division-multiplexing (WDM)–based long-haul optical networks in late 1990s, WDM transmission systems have been evolving from point-to-point transmission to a nextgeneration reconfigurable add/drop mesh structure. In terms of signal-to-noise ratio, power equalization is extremely important in such a system. In addition, power equalization should be performed automatically to reduce operational expenditures. On the other hand, such a technology trend drives MANs to start evolving so as to have a transparent architecture. Regarding multiple service content in MANs, the ability to handle multiple protocols at varying speeds becomes critical to operational efficiency. Thus components with features that handle optical signals with protocol transparency and data-rate and wavelength independence are crucial to the practical implementation of this architecture. To enable an advanced optical network, optical MEMS technology provides free-space propagation of bounded beams among components such as mirrors, gratings, and lenses. These optical MEMS devices offer physical features such as transparency (bit-rate- and protocol-independent), tunability, scalability, low electrical operation power consumption, and small form factor. This chapter reviews the major micromechanisms for actuation. Representative optical MEMS devices are introduced thereafter. Consideration of optical MEMS packaging from the point of view of the optical communications and/or fiber telecommunications industry will occur at the end of this chapter.

Optical MEMS Packaging: Communications

5.2 Actuation Mechanisms and Integrated Micromachining Processes Recent developments in the rapidly emerging discipline of MEMS show special promise in sensors, actuators, and microoptical systems. In fact, optics is an ideal application domain for MEMS technology. Photons have no mass and are much easier to actuate than other micro-scale objects. In conjunction with properly designed mirrors, lenses, and gratings, various microoptical systems driven by microactuators can provide unique functions in light manipulation, such as reflection, beam steering, filtering, focusing, collimating, and diffracting. Although the force and displacement generated by the mciroactuators are normally quite small [e.g., displacement is on the order of a wavelength (a few microns)], these features make microoptical systems a promising application area for MEMS technology. The structures we discuss in the optical MEMS area range in dimension from a few microns to millimeters and are mostly fabricated on silicon substrates by micromachining techniques that came from standard semiconductor processing techniques. In other words, lithographic batch fabrication of MEMS devices, made possible and driven by the infrastructure of the integrated circuits (ICs) industry, is a relatively inexpensive fabrication method. As a result, MEMS devices offer the same potential benefits as advanced ICs in terms of low-cost, high-volume, and automated production. Another benefit that MEMS technology contributes to microoptical systems is assembly and packaging. The forms of light propagation in microoptical systems are categorized as free space and guided wave. Both schemes need to consider the light coupling loss and alignment accuracy between two elements in a microoptical system. In the case of optical MEMS-based approaches, the light path among various elements built on a silicon substrate can be defined precisely by the lithographic batch-fabrication technology. Alignment accuracy is guaranteed by the photolithographic resolution. Accuracy from the submicron level to 2 μm is normally achievable for lithographic processes using a stepper mask, whereas contact-mask lithographic processes provide an accuracy of 2 to 5 μm. On-chip active alignment with the aid of microactuators for position adjustment can give optical alignment accuracy as precise as 0.1 μm or less. In this way, an entire optical system can be integrated and realized monolithically on a single chip. Therefore, single-chip microoptical systems can be built by integrating multiple free-space microoptics that are cascaded along the optical axes on the same substrate.13 On the other hand, packaging of optical MEMS devices needs to comply with industrial reliability standards. Unlike the common solid-state lasers and discrete microoptics, the reliability issue of micromechanical movable elements involved in an optical MEMS system typically is imposed on the whole system as a

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Chapter Five reliability challenge. Reliability-proven designs have been reported in such applications as optical switches and VOAs. In principle, silicon is a qualified and appropriate material for realization of microoptics and microactuators in the optical MEMS area. With proper design, the reliability of optical MEMS is a manageable engineering task. First of all, the excellent mechanical properties of single-crystal silicon allow fabrication of fatigue-free devices. Since single-crystal silicon has no dislocations, it has virtually no fatigue and is a perfectly elastic material—a property that is extremely desirable for precision mechanics applications. Second, the silicon surface, when treated properly, can provide an optical surface of extremely high quality (i.e., flat and scatter-free), and an additional Au thin-film coating layer on top of silicon mirror surface enables perfect reflection on this silicon mirror. Third, the electrical properties of silicon allow for the integration of sensors and photodetectors with extraordinarily high precision, which is often required in optical networks for feedback-control purposes. In next few paragraphs we introduce the concepts of major actuation micromechaisms first. With the background knowledge of micromachining technology that we learned in Chapter 4, complicated and integrated micromachining processes used in optical MEMS applications will be discussed.

5.2.1 Electrostatic Actuation Let’s consider a parallel-plate capacitor with a fixed gap distance g between two plates with overlap area A. The energy stored in this capacitor subject to an applied direct-current (dc) bias V is given as W=

ε ε AV 2 1 CV 2 = 0 r 2 2g

(5-1)

and the attractive force generated between the two plates is

F=

dW ε 0ε r AV 2 = dg 2 g2

(5-2)

where the ε0 is the vacuum permittivity and εr is the relative permittivity or dielectric constant. The actual permittivity ε in a homogeneous material then is calculated by multiplying the relative permittivity εr by vacuum permittivity ε0. In the micromechanisms for electrostatic actuation, a movable electrode connected to suspended mechanical springs and a fixed electrode anchored onto substrate is the typical configuration. When a voltage is applied to the electrodes to form a capacitor, the electrostatic attractive force drives the movable electrode to the stationary electrode, and the capacitance between the two electrodes is increased accordingly. The spring suspending the movable electrode is deformed. Thus the displacement Δx of the movable electrode is determined by the force balance between the spring’s restoring force and the electrostatic force.

Optical MEMS Packaging: Communications There are two major types of electrodes in electrostatic actuators: parallel plate and interdigitated comb. To achieve long displacement, a laterally driven electrostatic comb actuator made of polycrystalline silicon was proposed by Tang and colleagues in 1989.14 The movablecomb electrode was suspended with folded-beam springs (each 100 μm long) and anchored to the substrate. Displacement of the movable comb of 5 to 20 μm was reported with a typical drive voltage ranging from 10 to 30 V. The geometry in such a surface-micromachined polycrystalline silicon substrate leads to the fact that the electrostatic attractive force between two comb electrodes is mainly due to the fringing fields rather than the parallel-plate fields because the thickness of the fingers is small compared with their lengths and widths. The maximum static displacement of a comb actuator is commonly smaller than the theoretical value, which is limited by the sidepulling effect of the comb fingers in the conventional design of comb actuators.15–17 Tiny deviations in comb finger thickness and gap width will lead to an unbalanced force between both sides of finger electrodes, and such a deviation is easily caused by the microfabrication process.18 The unbalanced force between both sides of a finger electrode is the major contributing factor to the side-instability effect. How to design and manufacture a comb-drive actuator that is more robust to process-induced deviation is key to successful industrial applications. As shown in Fig. 5-1a, looking into electrostatic actuators from a three-dimensional (3D) point of view, we normally design a micromechanism with a spring constant kx in the direction of movement (i.e., along the x axis) that is very small, and the spring constants ky and kz along the y and z axes (i.e., in a direction perpendicular to the moving axis) are much higher than kx. In doing so, the maximum static displacement Δx of the movable electrode in the direction of the x axis is derived from F = kxΔx, where the F is the spring restoring

Electrode Electrode finger of finger of fixed movable comb comb Central axis

g

loverlap + – V (a)

y ky

Thin folded spring x

kx Comb actuator

Reflective shutter

(b)

FIGURE 5-1 (a) Conceptual drawing of a small portion of a comb actuator with a pair of comb fingers, and the whole comb actuator contains a number of cascaded comb pairs. (b) Scanning electron microscope (SEM) photograph of an electrostatic comb actuator–driven 2 × 2 optical switch.

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Chapter Five force at this equilibrium position and equals the electrostatic attractive force. Thus the static actuated displacement Δx is given by

Δx =

Nε te 2 V kx g

(5-3)

where N = number of comb-electrode fingers te = comb-electrode thickness ε = actual permittivity of air g = gap between the comb fingers V = actuation voltage Figure 5-1b shows a 2 × 2 optical switch made from a silicon device layer on a silicon-on-insulator (SOI) substrate. By leveraging the high aspect ratio and fine gap of the comb fingers, a large output force from the comb actuator is achievable. On the other hand, Akiyama and colleagues20 reported a creative electrostatic actuator called a scratch-drive actuator (SDA). The SDA consists of a suspended polysilicon plate with a vertical bushing, as shown in Fig. 5-2a. This free-standing plate is linked with the major

Suspended poly-Si plate

Vertical bushing

Supporting beams

(a)

(b)

(c)

(d)

FIGURE 5-2 (a) SEM photograph of an SDA element. (b) SEM photograph of a rotary structure driven by an SDA array. (c) SEM photograph of an assembled polysilicon mirror driven by an SDA array. (d) SEM photograph of an assembled polysilicon shutter driven by an SDA array for a 2 × 2 optical cross-bar switch application.

Optical MEMS Packaging: Communications objects of a micromechanism via supporting beams that are connected at the junction edge of the main plate and the vertical bushing. When a voltage is applied between the free-standing polysilicon plate and the buried electrode layer on the substrate, the plate buckles down, causing the bushing to “scratch” along the insulator, thus resulting in a small forward movement. This means that a step of scratch enables the bushing to move from original contact point P1 to the new contact point P2 between the bushing and the substrate. The free-standing polysilicon plate returns to its original shape after the actuation voltage is removed. The deformed plate will bounce back to the original shape while the bushing maintains contact with the substrate at P2. When a pulse-wave-based actuation voltage is applied, the “scratch” step is repeated to form stepwise linear motion.19,20 An array of SDA devices has been used to drive various microstructures and optical MEMS devices (see Fig. 5-2). The fundamental design tradeoff in optical MEMS devices using electrostatic actuators is the choice between a suitable process technology and the actuation mechanism. Parallel-plate and comb actuators are the available designs for use in bulk micromachined optical MEMS devices, whereas polysilicon-based comb actuators and SDAs are often used in surface-micromachined structures. Such surface micromachining technology will be discussed in Sec. 5.2.5. Briefly, parallel-plate actuation can provide very high forces (~100 μN) with small displacements (~5 μm), but the force is highly nonlinear with instability within the displacement range. Interdigitated comb actuation provides a moderate level of force (~10 μN) with large displacements (~30 μm).

5.2.2 Thermal Actuation Thermal actuation uses the thermal expansion of materials to achieve mechanical actuation. The thermal expansion of a solid material is characterized by the coefficient of thermal expansion (CTE) αT. The CTE of a material generally is a function of temperature. With a small temperature change ΔT, the introduced mechanical strain is defined as the product αT ΔT. The CTE for a material has units of strain per change in temperature (1/°C). One of the basic micromechanisms for thermal actuation is a thermal bimorph, which consists of a cantilever with two or more layers.21 Relying on the difference in linear expansion coefficients between two materials, one layer expands as a result of ΔT by a different amount than the other, creating thermal stress at the interface between these two layers and leading to bending of the cantilever. The ΔT can be created by heating up the cantilever when a biasing current flows through an embedded resistor in the cantilever (i.e., Joule heating effect). Out-of-plane displacement is generated at the bent cantilever because of the volume-expansion difference in the two layers owing to ΔT. The thermal-bimorph actuator is used widely

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Chapter Five in both bulk and surface-micromachined devices in the optical MEMS field. Nevertheless, some applications demand in-plane displacement. By using a single material, a U-shaped thermal actuator consists of two arms of uneven widths suspended above the substrate with two anchor points at the ends of the two arms, as shown in Fig. 5-3.22,23 A U-shaped thermal actuator is made of metallic beams or conductive silicon beams. When an electric current is applied from one anchor to the other, the arm with the larger electrical resistance and resulting power generation achieves a higher temperature and a larger volume expansion (i.e., the so-called hot arm). The other arm is relatively cold and is referred to as the cold arm. The arm with the larger electrical resistance is the longer arm or the arm with the smaller cross-sectional area. These two arms are connected at one end opposite the anchors. The U-shaped thermal actuator will deflect laterally toward the cold arm owing to the asymmetric thermal expansion when the U-shaped thermal actuator is under a dc bias. Deflections of up to 16 μm and a force of 4.4 μN have been obtained for polysilicon

Anchor Hot arm

Dimple

Cold arm Direction of displacement (a)

Flexure

(c)

(b)

FIGURE 5-3 (a) Schematic drawing of a U-shaped thermal actuator. (b) SEM photograph of a suspended polysilicon U-shaped thermal actuator. (c) Closeup view of a U-shaped thermal actuator.

Optical MEMS Packaging: Communications thermal actuators at 10-mW driving power. The area (~20 × 200 μm2) is also very compact compared with comb-drive actuators.22 The polysilicon thermal actuator has been demonstrated to drive stepper motors and linear motors, as well as to assemble the 3D microstructures for optical switches and VOAs.24,25 Field and colleagues26 reported U-shaped thermal actuators with 25 to 50 μm thick electroplated nickel beam for moving optical fibers with static displacements as large as 150 μm for a 1 × 2 optical switch in 1997. The bent-beam thermal actuator consists of an arched beam extending between a pair of anchors, as shown in Fig. 5-4. This arched beam is a symmetric structure consisting of a long, thin beam canted at a small angle θ from the center line. Thus the arched beam is also called a V-shaped beam or V-beam. This V-beam structure was proposed as a strain sensor in the beginning27,28 but was proven to be a good thermal actuator later on.29,30 This arched beam will expand so as to further arch if electric current flows through the arched beams (see Fig. 5-4b). It is a mechanical amplifier of the small deflection produced by thermal expansion. V-beam thermal actuators may be cascaded by running in parallel as well as by using additional bent-beam structures for mechanical amplification.31,32 V-beam thermal actuators also can include a center post that connects the plurality of arched beams and serves to push against the work piece.33,34 V-beam actuators are promising in applications that require large stroke and high force outputs.

Arched direction θ

Suspended Canted beam Anchors

(a)

V Displacement direction

(b)

FIGURE 5-4 (a) Schematic drawings of V-shaped beam actuator of high-aspectratio structure. (b) V-shaped beam deformed in the arched direction owing to a dc bias.

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Chapter Five V-beam actuators are known to provide one-directional static displacement generated from a net volume expansion owing to the thermal-expansion difference distributed over the whole actuator structure. This net volume expansion always points in one direction. In applications such as bistable optical switches, planar micropositioners, and relays, the two-way motion and bidirectional static displacement are desired actuation mechanisms. By linking a set of two separately located V-beam actuators with opposite actuation directions in an H-shape,35 H-beam thermal actuators are reported to have bidirectional static displacement as high as 50 μm, as shown in Fig. 5-5. The design of thermal actuators is a multiphysics problem36 requiring thermal, structural, and electrical analyses. The heat transfer involved in a thermal analysis includes conduction and convection. Radiation heat transfer in a thermal actuator can be ignored because it is generally not significant. The upper practical limit for temperature in the polysilicon and single-crystal-silicon-based thermal actuator is approximately 600 and 800°C, above which material property changes, such as localized plastic yielding and material grain growth, become an issue. The alternating-current (ac) operation of thermal actuators generally is limited to a frequency response of less than 1000 Hz because of the time constants associated with heat transfer. For example, thermally driven scanning mirrors demonstrate scanning frequency in the range of 100 to 600 Hz.37 However, a

Anchor

Tilted angle

Width

Anchor

Tilted angle Actuator beam length (a)

(b)

(c)

(d)

Actuator beam length

FIGURE 5-5 Two types of single-crystal-silicon H-beam actuators are designed and fabricated by the micromachining process. (a) and (c) are a schematic drawing and SEM photograph of an H-beam actuator with outward arched shape, whereas (b) and (d) are a schematic drawing and SEM photograph of an H-beam actuator with inwardly arched shape, respectively.

Optical MEMS Packaging: Communications CMOS-MEMS-based scanning mirror operating at 2.6 kHz has been developed successfully because the thermal time response of the thermal actuator is less than 0.4 ms.38 This shows that a thermal actuator that operates at a few kilohertz is possible to achieve.

5.2.3 Magnetic Actuation A Lorentz force is generated when a current-carrying element is placed within a magnetic field. The Lorentz force FL is given by FL = iL × B

(5-4)

where the FL, i, and B refer to length of conductor, electric current, and a magnetic field, respectively. In addition, FL, i, and B are at right angles according to the right-hand rule implied by the cross-product. Lorentz force occurs in a direction perpendicular to the current and magnetic field. The magnitude of the force is proportional to the current i, length of the conductor L, and the magnetic field B. Although Lorentz-force actuation may be applied to MEMS devices in a number of ways, the prevailing mechanism is to have the metal coils integrated on a movable mirror and actuated by an ac current at resonance when this mirror is placed near a permanent magnet.39 A permanent magnet easily generates a magnetic induction of 0.5 to 1 T, whereas the magnetic induction of a simple planar electromagnetic coil with about 10 windings is in the millitesla range. Another approach is to integrate a permanent magnet (hard ferromagnet) or a soft ferromagnet (Permalloy) layer on a movable mirror, and the Lorentz force is generated by the interaction between the magnetic layer and the surrounding ac magnetic field owing to an external solenoid. Judy and colleagues40 demonstrated a device with an electroplated 7-μm-thick Permalloy layer on the free end of a polysilicon cantilever. Deflections at the cantilever end exceeding 90 degrees were achieved by applying an external magnetic field. The availability of permanent magnetic materials that are compatible with MEMS processing is limited and results in necessary process-development efforts. Thus it is common for the magnetic field to be generated externally, whereas the discrete and movable magnetic actuators often consist of metal coils.

5.2.4 Piezoelectric Actuation An applied dc voltage across the electrodes of a piezoelectric material will result in a net strain that is proportional to the magnitude of the voltage (strictly electric field), whereas a free-standing piezoelectric structure (e.g., a cantilever) will be excited at its mechanical resonant frequency under ac voltage of the same frequency. The piezoelectricity is attributed to charge asymmetry within the primitive unit cell, resulting in the formation of a net electric dipole. Adding up these individual dipoles over the entire crystal gives a net polarization and

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Chapter Five an effective electric field within the material. The popular piezoelectric materials include quartz, lithium niobate, lithium tantalite, AlN, ZnO, and lead zirconate titanate (PZT), whereas the most well-known polymer-based piezoelectric material is polyvinylidene fluoride (PVDF), which is a thermoplastic material. The poled PVDF exhibits piezoelectricity several times greater than quartz. Thin-film-based MEMS actuators using ZnO thin films for feedback control of a ZnOcoated cantilever have been applied to atomic force microscope applications.41,42 ZnO thin film can be prepared by sputtering relatively easily. Among the aforementioned piezoelectric materials, PZT is the most promising because it produces the highest piezoelectric response. PZT is a lead-zirconate-titanate ferroelectric ceramic. In the phase diagram of PZT, Pb(ZrxTi1–x)O3, there is a morphotropic phase boundary (MPB) that separates a rhomboidally distorted ferroelectric region at low Zr concentrations and a tetragonal region at high Ti concentrations. Pb(ZrxTi1–x)O3 exhibits outstanding piezoelectric characteristics at the MPB, where the x refers to 0.52 or 0.53. PZT of composition around this MPB shows the highest piezoelectric effect. The piezoelectric effect is described in terms of piezoelectric charge coefficients dij, which relate the static voltage or electric field in the i direction to displacement or applied force in the j direction. When we consider a PZT thin-film actuator prepared on top of an Si cantilever, we define axes 1 and 3 as longitudinal and normal directions regarding the cantilever. The piezoelectric charge coefficients are given as d33 for both voltage and force along the vertical axis (axis 3) and d31 for voltage along the vertical axis but force in the longitudinal direction (axis 1). The units of the piezoelectric charge coefficients are coulombs per newton (C/N) or meters per volt (m/V), depending on whether the electrical parameter of interest is voltage or charge. The induced strain along the vertical axis is actually very small when a voltage is applied along the vertical axis. The introduced stress, though, will bend the free end of the cantilever significantly. This displacement Δ at cantilever end is in proportion to the length of cantilever. Obviously, a piezoelectric thin-film-coated silicon cantilever is an efficient piezoelectric actuator for displacement amplification. The displacement Δ is given by43,44

Δ=

3 AB d L2V K 31

(

Si PZT PZT Si A = s11 s11 s11 tSi + s11 tPZT

B=

(5-5)

)

(5-6)

tSi (tSi + tPZT ) PZT Si s11 tSi + s11 tPZT

( )

(5-7)

2

Si Si PZT PZT K = s11 (hPZT )4 + 4s11 s11 tSi (tPZT )3 + 6s1Si1s11 (tSi )2 (tPZT )2

(

)

2

PZT Si PZT + 4s11 s11 (tSi )3 (tPZT ) + s11 (hSi )4

(5-8)

Optical MEMS Packaging: Communications Si and where L is the length of the cantilever, V is the applied voltage, s11 PZT −12 −1 s11 are the compliances of the silicon cantilever (5.9 × 10 GPa ) and PZT actuator (1.43 × 10−11 GPa−1), and tSi and tPZT are their respective thicknesses. The piezoelectric charge coefficients of d31 for various piezoelectric thin films of PZT, ZnO, and AlN are reported as –110, 5, and 2 to 3 pC/N, respectively. Several methods have been described for thin-film PZT deposition, for example, sputtering and sol-gel processes. High-temperature annealing (e.g., 600°C) is necessary to achieve a 100-percent perovskite phase of PZT film such that the PZT film exhibits its highest piezoelectric performance.45 The first research attempt to make piezoelectricdriven MEMS mirrors used PZT bimorph plates glued on a stainless steel frame in 1995.46 The first PZT thin-film-driven MEMS mirror was reported in 1996.47,48 One of the main challenges in making PZT thinfilm-driven MEMS mirrors is the residual-stress issue. Removing the PZT film from the silicon mirror area is necessary to keep the mirror flat. Recently, Yasuda and colleagues reported a large elliptical Si mirror (1 × 2 mm) driven by PZT actuators. This two-dimensional (2D) scanning mirror showed large optical scanning angles [e.g., 23 degrees (4.3 kHz for x scan) by 52 degrees (90.3 Hz for y scan] under 10 to 20 V ac with a 5-V dc offset.49 An overview of piezoelectric thin-film actuators has been provided by Maeda and colleagues.50

5.2.5

Integrated Micromachining Processes

We examined a number of thin-film and bulk-micromachining technologies in previous chapters. In contrast to bulk micromachining, surface micromachining refers the microfabrication technology for making MEMS devices entirely from released thin films that are deposited and patterned on top of substrates. Alternating layers of structural and sacrificial materials are deposited and patterned on the substrate first. Then the sacrificial materials are selectively removed by an etchant that attacks only the sacrificial materials. By leveraging the high selectivity of hydrofluoric acid–based sacrificial etching for silicon oxide with respect to polysilicon, a polysilicon-based surface micromachining process was reported by Howe and colleagues in 1983.51,52 With one gold electrode layer, two structural polysilicon layers, and two SiO2 sacrificial layers, complicated polysilicon-based micromechanical gears, springs, latches, micromotors, and sliders have been demonstrated. Polysilicon-based surface micromachining became the prevailing technology for making various optical MEMS devices in late 1990s because of the excellent mechanical properties of the polysilicon material and the availability of process service provided by foundries.5,13,53–56 Electrostatic actuators and thermal actuators are created by polysilicon-based surface micromachining, and additional optical components, such as mirrors, gratings, and lenses, may be integrated selectively in the same devices.53–56 In particular, the technique

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Chapter Five of surface micromachining is interesting in that it is a planar process that is capable of producing large-area, high-quality layered structures along the plane of the substrate, which then can be rotated out of the surface to form large optical surfaces angled to the surface of the substrate. Surface micromachined Au/poly-Si mirrors up to approximately 300 × 300 μm2 in size still can maintain reasonable flatness.57 However, a mirror of 1 mm2 or larger with high optical quality never can be created with polysilicon-based surface micromachining technology because of the deterioration of mirror flatness attributed to residual stress. In surface micromachining, movable structures generally are released by wet etching the sacrificial layer, followed by rinsing in water. After the rinse step, the capillary force generated by the water bridge formed in between the small sacrificial-layer gap leads to the stiction of suspended structures to the underlying substrate during the drying step. Many antistiction approaches have been developed. By dipping surface-micromachined devices in a hydrophobic liquid such as hexane or toluene in the last rinse step, formation of water bridge in the gap can be effectively avoided.58 The second approach relies on a sublimation process. Either by freezing or by heating the liquid to a supercritical state, one can avoid formation of the water bridge during the rinse and drying processes. t-Butyl alcohol is solid at room temperature (the freezing point is 25.6°C), so it is possible to perform freeze-drying without special cooling equipment and low vacuum pressures.59 In the supercritical drying method, the final rinse is done in a pressure vessel in liquid CO2, which is then raised to a supercritical state. The interface between the liquid and gas phases is indistinguishable, and there are no surface-tension forces in the supercritical state.60 Thereafter, the CO2 gas is vented without a surfacetension issue. The fourth method deploys HF vapor to conduct the vapor-phase sacrificial-layer etching. Since sacrificial-layer oxide is etched in vapor, there is no concern for surface-tension forces.61,62 Optical MEMS manufacturing processes require design tradeoffs among optical considerations, actuator performance, process yield, and reliability. Combining unique process steps from various process technologies, such as wet bulk micromachining, deep reactive-ion etching (DRIE), surface micromachining, chemical/mechanical polishing (CMP), and wafer bonding, can provide a wide range of process alternatives. For example, surface-micromachined polysilicon microstructures evidenced low stiffness owing to structures made from the thin-film polysilicon layer. Thus surface-micromachined mirrors with low stiffness could not tolerate the residual stresses. As a result, the size of a surface-micromachined polysilicon mirror typically is limited to 300 × 300 μm2. A creative molded surface-micromachining and bulk etch release (MOSBE) II process has been proposed by Wu and Fang63 to overcome this problem, as shown in Fig. 5-6. First, trenches with various depths are created down to silicon substrate by DRIE

Optical MEMS Packaging: Communications

(a)

(e)

(b)

(f)

(c)

(g) Stiff structure (e.g., mirror plate) Flexible structure Multidepth structure (e.g., torsional bar) (e.g., vertical combs)

(d)

(h)

PR

FIGURE 5-6

Oxide

Poly 1

Nitride

Poly 2

The process flow of a MOSBE II process.63

(Fig. 5-6a and b). The processes illustrated in Fig. 5-6c through g are the deposition, patterning, and stacking of thin films, in which these process steps are similar to surface-micromachining process steps. In Fig. 5-6f and g, low-stress nitride was deposited and patterned as the etching mask for bulk silicon etching, whereas the poly-Si film was fully protected by the thermal oxide and the SiN films. After the tetramethyl ammonium hydroxide (TMAH) bulk silicon etching and the HF oxide etching, the high-aspect-ratio polysilicon structures are released from the substrate (Fig. 5-6h). The DRIE-derived trenches are molds for high-aspect-ratio microstructures. The trench-refilled polysilicon film can form reinforced ribs so as to significantly enhance the stiffness of the mirrors, as shown in Fig. 5-7a and b. A mirror with 500-μm reinforced ribs shows a radius of curvature of 150 mm. By using this kind of mirror-fabrication technology, one can design a

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Chapter Five Reinforced ribs

(a)

(b) Supporting frame

Vertical comb actuator

Marks of the reinforced ribs

Mirror plate

Torsional sparing

(c)

FIGURE 5-7 SEM photographs of various mirrors made by the MOSBE II process: (a, b) Top and backside views of a torsional mirror with rib-reinforced structures; (c) optical scanning mirror with vertical comb actuators on two sides.63

scanning mirror of large size, large scanning angle, and high mechanical resonance frequency because the mass of mirror is reduced and the stiffness is increased. Another promising process technology is integration of polysilicon surface micromachining on top of an SOI substrate. By combining surface and bulk micromachining, a movable polymer lens can be released and assembled inside the space etched from the device layer of an SOI substrate.64 In short summary, various optical MEMS devices are derived by surface micromachining and SOI-based bulk micromachining. Through integration of different process technologies, more degrees of freedom in optimization of MEMS devices can be achieved.

5.3 Optical Switches Optical networks based on wavelength-division-multiplexing (WDM) systems have played a key role in increasing the capacity and flexibility of these networks. When the network architecture is evolving

Optical MEMS Packaging: Communications from point-to-point WDM transmission systems into ring-type networks, optical add/drop-multiplexing (OADM) systems and optical cross-connect (OXC) systems are required to enable more flexibility. Thus networks will evolve into a mesh-type architecture in the future. Based on free-space optics, various OADM and OXC devices have been demonstrated using MEMS technology. On the other hand, MEMS-based optical switches route the entire optical signal of various wavelengths from one fiber to another and scale in size from fundamental 1 × 2 and 2 × 2 switches to N × N switches, where N can be as large as 1000, because optical MEMS devices provide such key features as protocol and data-rate transparency, and wavelength independence. The basic 1 × 2 optical switch is often used for protection against equipment failure. For example, metropolitan-scale fiber rings often use fiber redundancy employing a bidirectional lineswitched ring topology. The 1 × 2 switch can route the signals from the main fiber to the backup fiber when a loss of signal occurs. A fundamental 2 × 2 switching element can be used as a stand-alone switch or within a multistage interconnection network for constructing larger switch fabrics. The 2 × 2 switch can be used for implementing OADM architecture on a per-channel basis. A 1 × N switch routes optical signals from one fiber to one of an array of N fibers. The 1 × N switch can be used for efficient equipment sharing, such as optical monitoring at an amplification site. Finally, large N × N switches, often referred to as optical cross-connects (OXCs), are used to establish a desired connectivity pattern across many fibers. An OXC performs as an automated patch panel whose connectivity can be changed without the need for a technician’s visit to the site of the patch panel. In addition, OXCs can be used to route individual WDM channels at a network node using opaque or transparent operating modes.

5.3.1

Small-Scale Optical Switches

An optical add/drop switch, the so-called 2 × 2 crossbar optical switch, is a critical element of OADM devices. It is desired for such a switch to be able to add or drop optical signals to or from current traffic directly without using an optical-electrical-optical (OEO) conversion. The common device configuration of a crossbar switch is that there is a tiny mirror sliding in and out of the intersection point of the light path. Thus light beams either cross unimpeded to the fiber opposite them or get diverted into the next fiber channel. This kind of movable mirror is used for gate switches (1 × 1 on/off switches) as well. Early gate switches and crossbar switches have been realized by using polysilicon-based surface-micromachining and bulkmicromachining technology. The first crossbar switch was created by surface micromachining and assembling of a polysilicon mirror.65 An electrostatic-actuated surface-micromachined polysilicon mirror

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Chapter Five Output fiber

Level arm

Pop-up poly-Si shutter

Pivot

Input fiber

Capacitor plate Spring Light beam

Moving direction

z

+ V

y

x

–

FIGURE 5-8 Schematic drawing of a surface-micromachined polysilicon pop-up shutter connected with a displacement amplification-level arm. The displacement generated by the parallel-plate actuator is amplified via the level arm to the pop-up shutter. This electrostatically actuated pop-up shutter can perform the functions of both a gate switch and a VOA.

has been created with a vertical sidewall electrode,66 a stress-bent parallel-plate electrode,67 and a displacement amplification-level arm.68 Figure 5-8 shows the pop-up mirror moving vertically in between two fibers for a gate-switch application.68 Based on bulk-micromachining technology, a crossbar switch has been created by using electromagnetic69,70 and electrostatic71–73 actuation schemes as well. Combining the comb-drive actuator with DRIEcreated trenches for holding optical fibers, a crossbar switch derived from an SOI substrate is shown in Fig. 5-9. Such an optical switch consists of a high-aspect-ratio micromirror with a vertical sidewall and an electrostatic comb-drive actuator for controlling the position of the micromirror (i.e., the shutter).71–73 The common comb-drive actuator includes a stationary-comb finger electrode and a movablecomb finger electrode connected to the micromirror via a suspended spring. This suspended spring is anchored onto the substrate at one end. Electrostatic force for moving the micromirror can be generated by applying voltage to the comb-drive actuator. The restoration force generated by the deformed spring will pull the actuated micromirror to its initial position. The optical fibers are assembled and aligned properly with respect to the micromirror inside the trenches. Thus the creation of DRIE-derived crossbar switches is much easier than that for the counterpart made by surface-micromachining technology. On the other hand, a similar comb actuator driven crossbar switch can be created from a normal silicon substrate based process combining the DRIE step with an oxide-refill step.74 To reduce the driving voltage, a two-step of DRIE process is reported to create a crossbar switch with two steps of height from an SOI substrate; this crossbar switch

Optical MEMS Packaging: Communications Si anchor

Suspended Si spring + V –

Stationary comb finger electrode Movable comb finger electrode

Input fiber In-plane moving Si shutter Output fiber

+ V –

Moving direction

Light beam

+ V –

FIGURE 5-9 Schematic drawing of a surface-micromachined silicon shutter connected with a lateral movable electrostatic comb actuator. This electrostatically actuated lateral movable shutter can perform the functions of both a gate switch and a VOA.

has thin folded springs and high comb-electrode fingers. Therefore, the stiffness of the spring along the moving axis (i.e., kx) is reduced significantly, whereas the stiffness of the spring along the other two axes is kept almost the same because the output electrostatic force versus the applied dc bias is the same as for conventional SOI-based crossbar switches. The switching voltage, however, is reduced significantly.75 Based on a revised structural concept,70 an electrostatic optical crossbar switch has been reported using a KOH-etched mirror on an electrostatically driven torsional plate.76 Regarding the application of an optical switch, the micromirror can be moved from the initial off-state (i.e., light-transmission state) to the actuated on-state (i.e., light-reflection state, or switching) by applying voltage to the comb-drive actuator. In general, the micromirror only needs to be capable of staying at two relative positions. A continuously applied electric bias on a MEMS actuator is necessary to hold the micromirror of the optical switch staying at the on-state because we need the force generated by the MEMS actuator to balance the restoring force from the spring. Therefore, the crossbar switch requires a latching function to allow devices to reliably maintain a known position without power consumption when the power is removed or lost. Bistable micromechanisms provide two relative positions that are both mechanically stable. A buckled-beam archshaped leaf-spring geometry driven by a bidirectional electrostatic comb actuator was the first demonstrated application of an optical switch with a latch function.77–79 The other kind of latch mechanism

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Chapter Five for optical switches uses a gripper to clamp the switch in one position80,81 and a deformed spring to pull the switch body back to the original rest position when the switch structure is released from the gripper. However, such contact-clamping latches may have repeatability and reliability issues because the unbalanced clamping force from both sides, residual electrostatic force, and variations in friction force at the interface between the gripper and the switch structure may lead to different light-reflection angles and different switching speeds. Using the buckled-beam spring (i.e., a buckle spring) to enable the latching function (i.e., bistable switching) is an appropriate alternative to avoid the above-mentioned potential problems. In order to move the buckle-spring-type bistable structure from one stable position to the other, a larger force output of the actuator is preferred. A thermal (denoted as electrothermal) actuator has been demonstrated as an alternative to provide a higher force output under lower applied voltage than an electrostatic comb actuator, although the thermal actuator consumes more power than the electrostatic actuator.34 A symmetric double-beam thermal actuator generating an in-plane bidirectional stroke has been used to perform the bistable function for a relay in association with the latch function provided by buckle springs.82 Obviously, conventional crossbar switches using electrostatic comb-drive actuators and buckle beams formed on SOI substrates have encountered the following problems: (1) The large displacement provided by the comb drive for gaining better optical performance in conjunction with optics will lead to the design limit of comb-drive actuators and a requirement of very high driving voltage for such comb-drive actuators, and (2) the necessary force output provided by the comb drive for moving the arch-shaped leaf spring from one stable state to the other will require the MEMS actuator to generate the needed force. According to the functional requirements for practical application of optical switches mentioned earlier, desirable device features of optical switches include large displacement regarding the mirror, large force output from the actuator, and a latch mechanism for the device itself. On the other hand, V-shaped thermal actuators are promising in applications that need large strokes and high force outputs, but these designs are not compatible with bidirectional movement, which is necessary for latch applications. Lee and Wu82 have reported a bistable crossbar optical switch consisting of two sets of movable V-beam actuators, a set of bucklebeam springs connected to a suspended movable shutter beam with a reflective mirror shutter, and a suspended movable translation link at the ends of the suspended movable shutter beam. Both ends of this set of buckle-beam springs are anchored to the substrate, whereas the center of the buckle beam is connected to the suspended movable shutter beam (Fig. 5-10a and b). The force generated by one of the two

Optical MEMS Packaging: Communications

V-beam actuator

V-beam actuator

Fiber

Fiber

Pushing arm

Buckle spring

Buckle spring

Movement translation link

Movement translation link (CH2)

Reflective shutter (CH3)

Reflective shutter

Pulling arm

(CH1) (CH4) (a)

(b)

Movement translation link

(c)

Buckle spring

Buckle spring

V-beam

V-beam

(d)

FIGURE 5-10 Schematic drawing of a bistable optical crossbar switch driven by two sets of V-beam thermal actuators: (a) transmission state; (b) switching state; (c) optical microscope photograph of thermal actuator and movement translation link in the transmission state; (d) optical microscope photograph of the thermal actuator and movement translation link in the switching state.

sets of V-beam thermal actuator on various values of the applied electrical load is against the restoration force from the buckle-beam springs. The buckle beam is deflected to a range where the force from the bent buckle-beam spring is balanced by the force generated by the V-beam actuator when it is under electrical load. The V-beam actuator can push or pull the suspended movable translation link to move the shutter beam when the buckle-beam spring is deflected in the opposite direction, with deflection equivalent to 133 percent of the initial buckle deflection owing to the generated electrothermal force against the existing buckle-beam spring force. Thereafter, the mirror and shutter beam will move from the initial position to another bistable position (Fig. 5-10c and d). On the other hand, the mirror and shutter beam will be moved by the suspended movable translation link back to the initial position of the bistable state when another one of the two sets of V-beam actuators is actuated to pull or push the suspended

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Chapter Five movable translation link. The measured 2- to 6-ms switching time is good enough for commercial applications. Thus an on/off switching operation with a latch function is realized such that this device can stay at bistable positions without demanding electric power. However, a V-beam-driven crossbar switch has a large footprint because it requires two separately controlled actuators to perform the bidirectional strokes. As discussed earlier, the bidirectional static displacement generated by an H-beam thermal actuator, as shown in Fig. 5-5, in an H-beam-driven crossbar switch is smaller than that of the V-beam crossbar switch. An H-beam-driven crossbar switch containing an H-beam actuator, movement link structure, reflective micromirror, and arched buckle spring has been reported.83 As shown in Fig. 5-11, when the electric load is applied to one beam of the H-beam actuator, the arched direction of the biased beam is the same as the direction of forward movement of the reflective shutter. Once the unbiased beam is deformed owing to the pulling force of the biased beam, the whole actuator structure will generate a net displacement in the direction of the biased beam. This side-beam structure will push the shutter and switch-body beam forward, moving it from the initial stable position (see Fig. 5-11a) to the other stable position. Thus the device will change its status from the transmission state (see Fig. 5-11a) to the reflection state (i.e., switching state; see Fig. 5-11b). The device can be changed from the second stable position (see Fig. 5-11b or c) back to its initial stable position (see Fig. 5-11a or d) by applying an electric load on the opposite side of the H-beam to pull the switch body back via movement of the link structure. A close-up view of the H-beam actuator, movement-link structure, and arched buckle spring is shown in Fig. 5-11e. The measured optical switching characteristics include a forward and backward switching time of 5 and 1 ms under a 25-V dc pulse (see Fig. 5-11f ), back-reflection loss of –52 dB, cross-talk of –60 dB, insertion loss of 0.8 dB, polarization-dependent loss of 0.03 dB, and wavelength-dependent loss of 0.11 dB. This H-beam actuator avoids the influence of rotational torque during its bidirectional dynamic and static movement because of its symmetric structural design. The next level of complexity is built using a 2D array of these mirrors to form a matrix switch, with rows of inputs and columns of outputs (or vice versa), as shown in Fig. 5-12a. Optical switches with 8 × 8 and 16 × 16 ports were demonstrated.84–86 Mirror control for these 2D switches is binary and thus straightforward, but the tradeoff for this simplicity is optical loss. The substantially different lengths of the optical paths through various switch configurations limit the scaling. Limits to the scaling also include the diameter of the mirrors and their maximum tilt angle. The mirrors are designed to be about 50 percent bigger than the optical beams to avoid excessive loss, and tilt is limited by both the method used to build the switch and the technique

Optical MEMS Packaging: Communications Applied voltage at one side of H-beam H-beam actuator Movement link structure

Direction of displacement

Fiber 1

Fiber 1 Fiber 4

Transmission state

Fiber 3

Fiber 2

Buckle springs Fiber 4 Switching state

Fiber 2 Fiber 3

(a)

(b) Applied voltage at one side of H-beam

Direction of displacement Fiber 1

Fiber 1

Fiber 4

Fiber 4 Fiber 2 Fiber 3

Transmission state

(c)

Fiber 2

(d) Switching characteristics of H-beam driven optical switch 4 Optical signal 30 Electrical signal 1 ms 5 ms

Switch body

25 Driving voltage, V

Movement link structure

Buckle springs

Fiber 3

3

20

Electrical bias signal Optical signal

15

2

10 1 5

H-beam actuator

0 –10

(e)

(f)

0

10

20

30 40 Time, ms

50

60

70

0 80

FIGURE 5-11 Schematic drawings of an H-beam-driven optical switch in the transmission state (a, d) and in the switching state (b, c). The reflective mirror connected with switch body stays either in the transmission or the switching position, and this behavior is controlled by the buckle springs and driven by the bidirectional movable H-beam thermal actuator. (e) A SEM photographic close-up of the switch body, buckle springs, and movement-link structure of an optical switch. (f ) Switching speeds between the two bistable positions of optical switches under different driving conditions.

O-E converter output voltage, V

Switching state

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Chapter Five

Light beam Free-rotating switch mirror Fiber-collimator array Fiber-collimator array (a) Fiber array

Lens array

Optical signal MEMS array Optical path

Mirror

MEMS array

Fiber array (b)

Lens array (c)

Torsional spring

FIGURE 5-12 (a) Conceptual drawing of a 2D optical switch. (b) Conceptual drawing of a 3D optical switch. (c) Conceptual drawing of beam steering using a dual-axis gimbaled mirror.93

used to actuate the mirror. While the path length grows linearly with N, the number of ports, the optical loss also grows rapidly owing to the Gaussian nature of light. Therefore, 2D architectures are found to be impractical beyond 32 input and 32 output ports. Two major micromirror actuation mechanisms have been reported. The first is based on rotation of the micromirror.84,85,87–89 The mirror is initially parallel to the substrate (OFF position). When actuated, it is rotated to the vertical position (ON). In these cases, control of the mirror is digital; that is, the mirror is swung between fixed stops, and tight control of its motion between the stops is not needed. However, precision manufacturing and packaging are required to ensure that the stops are positioned properly. The second mechanism moves the vertical micromirror in and out of the optical path without changing the mirror angle.67,69,79,90,91 The 2D switches have been created by both bulk-micromachining69,79 and surface-micromachining67,90,91

Optical MEMS Packaging: Communications technologies. Owing to process-integration considerations, these approaches use either electrostatic actuation or magnetic actuation. The aforementioned approach leads to a very cost-effective medium-scale matrix switch because all the packaging is planar. The optical paths between the individual mirrors can be through free space or via waveguides. A combination of MEMS and waveguides has been reported by De Dobbelaere and colleagues.92 This approach has advantages in terms of compact size, scalability, and integration of a few 2D switches into a 3D stacked switch.

5.3.2

Large-Scale Optical Switches

In contrast to the case of 2D optical switches (i.e., all the light beams reside on the surface plane of the MEMS substrate and this feature leads to unacceptably high loss for large port counts), 3D optical switches deploy an array of two-axis mirrors to steer the optical beams in 3D free space, as shown in Fig. 5-12b. These switches require extremely fine analog control to align their optical beams because the beams must be directed accurately along two angles and then stop at precise intermediate positions, not just fixed end points. Thus the two-axis mirror array is the key enabling device for the 3D switch. Key parameters of a two-axis mirror array include size, tilt angle, flatness, fill factor, and resonance frequency of the mirror. More important, the stability and repeatability of the actuated mirror under certain electric loads are critical to the complexity of control schemes. Early devices relied mainly on surface-micromachined two-axis mirrors.94,95 The residual stress limits the size of the mirror to approximately 1 mm, and the different thermal-expansion coefficients between the mirror and the metal coating also cause the mirror curvature to change with temperature. Bulk-micromachined single-crystal silicon micromirrors are used often in high-port-count 3D optical switches that demand larger mirror size.96–101 In the early 2000s, research effort focused on high-port-count 3D optical switches for OXC applications. For example, Kim and colleagues102 reported an OXC of 1100 × 1100 ports based on a surface-micromachined two-axis mirror array because of the explosion of Internet data transport demands in the telecommunications industry boom. They even reported that 3D optical switches with sizes as high as 4096 × 4096 are technically feasible, although their costly 3D packaging makes them too expensive to be implemented practically. Later on, the research effort shifted to applications in metropolitan-area networks (i.e., metro-access and metro-core networks). Such markets demand 3D optical switches with medium port counts (~100 × 100) and features of low cost, low power consumption, and small footprint.100,103 As shown in Fig. 5-12b, the design and optimization of two-axis mirrors require examination of three elements: the mirror, the torsional springs (i.e., the mechanical support), and the actuator—all of

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Chapter Five which determine the overall system parameters of 3D optical switches. Examples of these parameters include • Maximum port count. This depends on the mirror tilt angle. • Switch settling time. This depends on the mirror response time. • Insertion loss. This depends on mirror size, reflectivity, and maximum tilt angle. • Power dissipation. This depends on the power required for mirror actuation and control. For example, each mirror may require a diameter on the order of 1 mm and a mirror radius of curvature (ROC) that is greater than a few tens of centimeters in a 1000-port 3D optical switch. The reflectivity of each mirror should be above 97 percent. The tilt angle needs to be in the range of a few degrees to ±10 degrees depending on the optical-path design of the 3D optical switch. Moreover, there are different tradeoffs among the desired properties of two-axis mirrors. For example, the torsional springs of the mirrors must have sufficient stiffness to meet such requirements as mirror response time and vibration immunity. However, the upper bound of spring stiffness is also restricted by the desired maximum tilt angle and the maximum force or torque output of the actuators. Magnetic and electrostatic actuation are two viable solutions for two-axis mirror actuation in an analogue manner (i.e., positioning the mirror at a particular angle). Magnetic actuation offers the benefit of a large bidirectional (attractive and repulsive) linear force output but requires a relatively complicated fabrication process for making the metal coils or magnetic films and proper package design for electromagnetic shielding.104 Electrostatic actuation is used most commonly in 3D optical switches because of the relative ease of fabrication and its low power consumption and compact footprint in packaged devices. Early electrostatic devices based on parallel-plate actuators demanded high actuation voltages. In order to achieve a large tilt angle, one can use a stiff spring, and then the tradeoffs include high actuation voltages (e.g., 50 to 200 V) and nonlinear torque output. The second issue is that the scan angle is limited owing to pull-in instability and cannot reach the theoretical value.105 Although the pull-in effect can be mitigated by nonlinear controllers, this increases the complexity of the electronics.106 In 2001, Sawada and colleagues107 reported another unique design of electrostatic two-axis tilt mirrors, as shown in Fig. 5-13a through c. First, two wafers are processed independently by silicon bulk micromachining. Through the use of AuSn solder–based wafer bonding, a bonded structure of a mirror with a terraced electrode underneath forms a novel canted parallel electrode (see Fig. 5-13b and d). The 10-μm-thick mirror is supported by folded

Optical MEMS Packaging: Communications Base layer Torsion spring Mirror substrate

Silicon oxide Tilt mirror Pivot

Electrode substrate

(a)

(b)

Trench

Terraced electrode AuSn solder

Pivot

50 μm (c)

10 μm

100 μm (d)

(e)

FIGURE 5-13 (a) Optical microscope photograph of a two-axis tilt mirror with a wafer-bonded electrostatic actuator with a terraced electrode. (b) Schematic crosssectional view. (c) SEM photograph of a two-axis tilt mirror. (d) Photograph of the terraced electrode with a pivot. (e) Optical microscope photograph of high-aspectratio folded torsion spring.107–109

torsion springs on two orthogonal axes and is tilted two-dimensionally by electrostatic force (see Fig. 5-13c and e). The torsion spring has an aspect ratio of greater than 6, which gives it a strong bending stiffness relative to torsion and strong support for the mirror so as to achieve reliable switching operation. The mirror has a diameter of 600 μm and is integrated with the gimbal structures that provide freedom of tilt about two axes. The tilt angle of the mirror can be changed by controlling the applied voltage between the two substrates. In last step, a 10 × 10 two-axis mirror array with 1.3-mm spacing is assembled onto a conventional plastic grid array (PGA)-ceramic package.96,107–109 The packaged 3D optical switching module with 100 × 100 ports is approximately 80 × 60 × 35 mm3. This design can achieve large deflection angles without a severe pull-in effect. Another improved electrostatic actuation mechanism for mirrors is a vertical-comb actuator. The first micromirror with a vertical-comb actuator was reported in 2000.110 By leveraging vertical-comb actuators, tilt-mirror devices can have a much larger electrostatic-forceinduced torque such that one can reduce the operating voltage as well as increase the resonance frequency. Moreover, optical switches with 80 × 80 ports using vertical-comb-driven two-axis mirrors with the V-shaped torsion springs have been reported to show a stable rotation of 5 degrees at 50 V. This approach remedies the pull-in effect

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Chapter Five Au/Cr

SiO2

(a)

(d) Photoresist

(b)

(e) V-shaped torsion bar

Electrical connection bar (c)

(f)

FIGURE 5-14 Process flow for making a two-axis mirror driven by a vertical-comb actuator with step-height difference.111,112

and increases the stable tilt angles.100,111 Figure 5-14 shows the bulkmicromachining process for this vertical-comb-driven two-axis mirror. First, a SOI wafer with 100-μm-thick top and bottom Si layers sandwiched a 1-μm-thick buried oxide layer was oxidized to grow 0.5 μm of thermal oxide. A mirror, anchors, and movable comb fingers were patterned on both sides by a novel through-wafer DRIE process. Using the patterned resist and oxide film as an etching mask, the first DRIE was applied to obtain a 5-μm-deep trench (see Fig. 5-14c). The photoresist then was removed only from the top surface (see Fig. 5-14d). Next, both the top and bottom surfaces were etched with DRIE using the patterned oxide as an etching mask until the buried oxide was exposed (see Fig. 5-14e). Finally, the exposed oxide was removed by HF wet etching (see Fig. 5-14f ). This process flow produced a 5-μm-thick torsion bar. The movable and stationary comb fingers were patterned with DRIE on the top and bottom Si layers, respectively. Figure 5-15 includes a photograph of the resulting mirror array and SEM photographs of both sides of the mirror

Optical MEMS Packaging: Communications

11.4 mm

(a)

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FIGURE 5-15 (a) Microfabricated two-axis mirror array of 79 channels. (b) Top-view SEM photograph of a two-axis mirror. (c) Backside-view SEM photograph of a twoaxis mirror.111,112

with a vertical comb. The height of the vertical-comb finger is 100 μm. Moreover, optical switches with 80 × 80 ports using a vertical-combdriven two-axis mirror with V-shaped torsion springs have been reported to show stable rotation of 5 degrees at 50 V. This approach remedies the pull-in effect and increases the stable tilt angle. The average insertion loss is 2.6 dB, and the overall insertion loss is 4 dB. This 80 × 80 switch has a packaged size of 77 × 87 × 53 mm3.100,111 The total power consumption is only 8.5 W, attributed to the electrostatic actuation. In 2006, a 3D optical switch with 256 × 256 ports based on a 512-mirror array demonstrated a ±5-degree rotation of the two-axis stationary operation under a drive voltage of 160 V and a resonance frequency of 2 kHz.112 Mirror-based variations with parallel-plate and vertical-comb actuators have been reviewed.113 Among these approaches, angular vertical-comb actuators can be integrated easily with mirror structure by using single-side lithography process on common wafers.113 Thus the angular comb actuator, ref 114, provides a potentially improved solution for a new two-axis mirror for 3D optical switch applications.

5.4 Variable Optical Attenuators Among optical communication applications, VOAs and their arrays are crucial components for enabling advanced optical networks. Nowadays, single-port VOAs are used widely in such applications as attenuation control on individual line cards and total signal-level

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Chapter Five control of the optical input to erbium-doped fiber amplifiers (EDFAs). This section provides an extensive survey of MEMS VOA technology evolution in last decade. First, MEMS VOA devices offer such physical features as transparency (bit-rate- and protocol-independent), tunability, scalability, low power consumption, and small form factor. At nodes of MANs, the optical signals in traffic must be added into or dropped easily and cost-effectively from a particular optical fiber pipeline and switched from one channel to the other, whereas the optical signal power of certain channels may need to be attenuated at nodes as well. Currently, a dynamic gain equalizer (DGE)115,116 is provided in conjunction with wavelength-division multi/demultiplexers (MUXs/DEMUXs) to perform the attenuation function and the function of reconfigurable and transparent add/drop at nodes. The multichanneled VOA device can be the channel-power equalizer in WDM cross-connect nodes, as well as in transmission networks. Thus integrated multichannel VOAs with MUXs/DEMUXs will be an alternative to satisfy this market. In view of market requirements, such as small footprints and low power consumption, an array structure containing multiple MEMS attenuators in a single silicon chip is preferable for future dense wavelengthdivision-multiplexed (DWDM) applications, whereas single-port VOA is required in MAN applications.

5.4.1 Early Development Work The early development work on VOAs in late 1990s was contributed mainly by two groups at Lucent Technology and the group of Professor N. F. de Rooij at the University of Neuchâtel in Switzerland. In 1994, Walker and colleagues117 developed a mechanical antireflection switch (MARS) device. A MARS consists of a suspended membrane with an optical window at the center of membrane. By actuating the membrane with displacement of λ/4, light of particular wavelength can be either transmitted or reflected. The original idea was to use a MARS as an optical modulator for switching in fiber-to-the-home (FTTH) applications. In 1998, Ford and colleagues118 further revised the MARS structure and applied it to VOA applications. This MARS is a silicon nitride suspended membrane with λ/4 optical thickness above a silicon substrate with a fixed 3λ/4 spacing. Voltage applied to electrodes on top of the membrane creates an electrostatic force that pulls the membrane closer to the substrate, whereas membrane tension provides a linear restoring force. When the membrane gap is reduced to λ/2, the layer becomes an antireflection coating with close to zero reflectivity. It is basically a quarter-wave dielectric antireflection coating suspended above a silicon substrate. The membrane varies in size from 100 to 500 μm in diameter. The mechanical resonance frequency of such a MARS device is on the order of megahertz. Thus the response time is extremely fast (i.e., 3 μs). The dynamic range of

Optical MEMS Packaging: Communications attenuation is 25 dB. However, the insertion loss is 2 dB, and wavelength-dependent loss is relatively high for attenuations larger than 5 dB. Ford and Walker115 have further applied the concept of a MARS to a MEMS-based DGE filter. To form the DGE filter, the optical window of the attenuator was elongated to create a suspended rectangular membrane. An array of strip-electrode pairs along the length of the optical window was arranged. By applying independently controlled voltages to all the electrode pairs, a controllable reflectivity function was developed along the length of the device. The diffraction grating– based free-space optics system was used to spread the incoming light spatially along the length of the optical window. An input spectrum with more than 15 dB of dynamic range was flattened to less than a 0.25-dB ripple over a 42-nm-wide spectrum. In contrast to the suspended dielectric antireflection membrane used in the MARS, Bishop and colleagues119,120 at Lucent Technology in 1998 developed a MEMS VOA using a surface-micromachined polysilicon microshutter arranged between a transmission fiber and a reception fiber aligned and located on the same axis. In this fiber-tofiber in-line type of VOA, the shutter is connected with a movable capacitor plate via the pivoted rigid level arm, and this shutter can move upward and downward in an out-of-plane direction by adjusting the position of the capacitor plate owing to electrostatic force based on the applied voltage. Thus it can control the relative amount of attenuation by blocking part of the light beam. This surface-micromachined in-line type MEMS VOA can achieve a dynamic range as high as 50 dB and a less than 1-dB insertion loss, whereas the reported shutter displacement can reach 15 μm under a 25-V dc load. More details about the activities of Lucent Technology can be found in a review article by Walker.1 In addition to the surface-micromachined polysilicon-based approach, DRIE technology is another major alternative for making MEMS VOA structures from the device layers of an SOI wafer. The first demonstration was done by Professor N. F. de Rooji’s group at the University of Neuchâtel in Switzerland in 1998.121 This SOI-based VOA device consists of a movable comb-finger electrode connected with a microshutter via a suspended spring and a stationary combfinger electrode. The attenuation range is determined in terms of the in-plane position of the Si microshutter, where this in-plane position is controlled by force balance between the electrostatic force and the spring force. To reduce the return loss of the input light reflected back into the input fiber, the microshutter and the fiber-end faces are at an 82-degree angle with respect to the longitudinal direction of the fiber channels. This in-line type of VOA achieved an insertional loss and back-reflection loss of less than 1.5 and –37 dB, respectively, whereas it provided 57 dB of attenuation with respect to 32-V bias. Apparently, among these early demonstrations, the movable-microshutter-based

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Chapter Five approaches exhibit promising device features (e.g., larger dynamic range). DRIE-derived SOI MEMS VOAs have silicon trenches to accommodate optical fibers with the alignment accuracy regarding the microshutter determined by the photolithography process. This feature makes the tedious assembly and alignment easier.

5.4.2 Surface-Micromachined VOAs Polycrystalline silicon–based surface micromachining was developed initially for accelerometers in early 1990s. Surface-micromachined electrostatic parallel-plate actuators, electrostatic comb actuators, electrostatic scratch-drive actuators (SDAs), U-shaped thermal actuators, and microstructures such as hinges and latches were demonstrated in early 1990s as well. These actuators and micromechanical elements enabled realization of a monolithically integrated free-space microoptical bench.55,56 In essence, the photon mass is not a physical concern; thus the surface-micromachined actuator does not need to manipulate the small microoptics or micromirrors. The MARS devices of Lucent Technology relied on electrostatic parallel-plate actuation,117,118 whereas the first in-line type of MEMS VOA from Lucent Technology was deployed based on a revised micromechanism using electrostatic parallel-plate actuators.119,120 Demonstration of the first in-line type of MEMS VOA from Lucent Technology really showed the advantages provided by surface-micromachining technology (see Fig. 5-8). These merits include (1) forming 3D complicated structures based on patterned-planar-layer structure and (2) precise control of optical alignment owing to the accuracy granted by the lithographydetermined planar-layer structure. In 2002, another surface-micromachined MEMS in-line type of VOA using a pop-up microshutter based on electrostatic parallelplate actuation was reported by Liu and colleagues at Nanyang Technological University (NTU), Singapore.122–124 The pop-up microshutter uses the same design as that used by Lucent Technology, whereas this microshutter is fixed on a drawbridge plate and can be moved down to the substrate via an applied dc bias. It demonstrates 45 dB of attenuation under 8 V bias and 1.5 dB of insertional loss. Compared with the devices in refs. 119 and 120, the driving voltage has been reduced a lot by using this unique drawbridge structure. In 2003, a group at Asia Pacific Microsystems (APM), Inc., developed a new movement-translation micromechanism (MTM) to convert and amplify small in-plane displacements into large out-of-plane vertical displacements or large out-of-plane rotational angles. As shown in Figs. 5-16 and 5-17, the in-plane displacement is provided by an electrically controlled electrothermal actuator (ETA) array. Based on this MTM, we applied only 3-V dc to generate 3.1 μm of in-plane displacement, then a rotational angle of 26.4 degrees, and an equivalent out-of-plane vertical displacement of 92.7 μm for pop-up

Light transmission direction Lense fiber

Surface-micromachined poly-Si pop-up mirror Movement-translation mechanism

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FIGURE 5-16 Schematic drawings of a surface-micromachined MEMS VOA consisting of a pop-up micromirror and the input and output fibers. After a wet-etching release process, the lense fibers are aligned to achieve minimum insertion loss first. The attenuated light is reflected in the out-of-plane direction when a dc voltage is applied to the ETA array.

Staple and fixed hinge pin

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FIGURE 5-17 SEM photograph of the MEMS VOA shows that in-plane displacement from the ETA array under dc voltage load is converted into out-of-plane rotation. The upperright inset shows a close-up view of the pop-up micromirror, staple, and fixed-hinge pin, whereas the bottom-left inset shows a close-up view of the lifted-up MTM structure.

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Chapter Five micromirror.125,126 Using this MTM, the in-line type of VOA demonstrated a 37-dB attenuation range under a 3-V dc load, whereas return loss, polarization-dependent loss, and wavelength-dependent loss at an attenuation of 3 dB were measured as 45, 0.05, and 0.28 dB, respectively. This reveals the effort needed to reduce the driving voltage for surface-micromachined VOA devices. It shows the third benefit of surface micromachining to optical MEMS, which is that a small planar displacement can be amplified into a large 3D displacement (i.e., large rotational angle or significant displacement) of the micromirror.

5.4.3 DRIE-Derived Planar VOAs Using Electrostatic Actuators Shutter and Single-Reflection Mirror DRIE-derived VOAs from SOI substrates with fiber-alignment trenches make the testing, alignment, and assembly work easier.121 As shown in Fig. 5-9, a DRIE-derived VOA developed by Professor N. F. de Rooji’s group really opens a window for new research activities. Since MEMS VOAs attenuate light signals in free space, the relative wavelength-dependent loss, polarization-dependent loss, and insertion loss are lower than for other waveguide-based approaches, whereas return loss and response time can be as good as the data achieved by the other approaches (e.g., any waveguided format). However, the back-reflected light coupling into the input fiber was a concern for in-line MEMS VOAs. In order to have a smaller return loss, using fibers with 8-degree facet ends is a common solution for in-line VOAs. Kim and colleagues127 reported a new electrostatic comb– actuated VOA with an off-axis misalignment–based light-attenuation scheme (i.e., single-reflection type) in 2002, whereas a similar design was reported by Lee and colleagues at APM.128 The devices made by Kim and colleagues exhibited 2.5 dB of insertion loss and 50 dB of attenuation with respect to 14-μm displacement of the comb actuator at 5 V. Meanwhile, APM’s relevant results have been published elsewhere.129,130 The data show 35 and 50 dB of attenuation under 10 to 13 V and 13 to 15 V, respectively. Kim and colleagues reported their progress in VOA research, indicating that their VOA achieved 35 dB of attenuation at 10 V and that the maximum polarization-dependent loss was 0.24 dB within the 25-dB attenuation range. Their VOA also had a return loss of –38 dB, and the maximum wavelength-dependent loss was 0.7 dB at 25-dB attenuation.131 Furthermore, Lee and colleagues at APM improved the designs of the electrostatic comb actuator and the single-reflection VOA. Figures 5-18 and 5-19 show the equivalent polarization-dependent loss, wavelength-dependent loss, and similar attenuation versus dc bias characteristics. These data are about the same as the results reported by Kim and colleagues.131

Optical MEMS Packaging: Communications 1

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However, the return loss is kept smaller than –50 dB within the 50-dB dynamic range, which is much better than the data in ref. 131. Bashir and colleagues132 at MEMSCAP in Cairo, Egypt, also developed similar single-reflection-type VOA devices. Their work achieved 30 dB of attenuation at 32-V dc. Within the 30-dB dynamic range, the derived

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Chapter Five polarization-dependent loss was less than 0.1 dB, which was better than the data from the other groups. In terms of networking equipment configurations, we may need VOAs operating in a normally close scheme (i.e., dark type). With a dark-type VOA, all the incoming light is blocked out (i.e., 100 percent attenuation) in the beginning. All the previous reported data and the discussions in the reference are based on a normally open scheme (i.e., bright type). This means that the initial attenuation is zero (i.e., initial insertion loss only). In order to clearly illustrate the difference in operating mechanisms between bright and dark types of VOAs with respect to in-line and single-reflection types, we will explain the relationship between light paths and attenuation mechanisms first. As illustrated in the upper left of Fig. 5-20a showing an in-line VOA with an 8-degree slanted shutter, the insertion loss is maintained initially at its minimum level, and incoming light signals are fully transmitted (i.e., the upper left of Fig. 5-20b). The shutter is approaching the transmitted light owing to an applied electrical bias; then a portion of the incoming light is blocked by as a function of shutter position, as illustrated in the middle left of Fig. 5-20b. The dark circle represents the light beam, and the dotted circle represents the light-receiving area of the output port. This figure illustrates the partially attenuated state of an in-line VOA. Once the shutter approaches further, then all the light is fully blocked. This is the fully attenuated state, as illustrated in the bottom left of Fig. 5-20b. Second, the dark-type in-line VOA is kept at its rest state, that is, the zero-bias state (the upper right of Fig. 5-20b). In other words, the VOA maintains its maximal insertion loss in the initial state, and then a portion of light is allowed to transmit based on the shift in shutter position under a certain level of electrical bias (the middle right of Fig. 5-20b). When the applied electrical bias is larger enough to move the shutter away from the light-transmission path, all light is fully transmitted and coupled into the output port (the bottom right of Fig. 5-20b). Third, Fig. 5-20c illustrates the input and output fiber ports located in an orthogonally planar position, where the transmitted light falls on a reflective mirror and is reflected toward the output port. This is the so-called reflective-type or singlereflection VOA. The reflected light path is changed in accordance with different mirror positions that are determined by the comb-drive actuator based on various applied voltages. Therefore, the coupled light intensity of reflected light to the output port depends on the path of the reflected light. As shown in Fig. 5-20d, the reflected light is fully coupled into output port and fully attenuated at the beginning for bright- and dark-type operation, respectively. Whereas the partially attenuated state is considered as the operative state for both bright- and dark-type VOAs, the actuated position versus the initial rest position of the mirror are opposite each other, as shown in the middle drawings of Fig. 5-20d. Once the applied voltage is larger enough, the reflective mirror pulls back further, and then the reflected

Optical MEMS Packaging: Communications

Output fiber port Anchors of comb drive

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Attenuated light beam Fixed comb Moving direction drive electrode fingers In-line MEMS VOA (a)

Mirror Input light beam signals Input fiber port

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In-line MEMS VOA (b)

FIGURE 5-20 (a) Schematic drawing of an in-line MEMS VOA. (Inset) SEM photograph of a microshutter with a tilted mirror plane. (b) Schematic drawing of light-path configurations in an in-line attenuation scheme operating in bright- and dark-type VOAs. (c) Schematic drawing of a reflection-type MEMS VOA. (Inset) SEM photograph of a reflective micromirror with a 45-degree mirror plane. (d) Schematic drawing of light-path configurations in a reflection-type attenuation scheme operating in brightand dark-type VOAs.

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Reflection MEMS VOA (d)

FIGURE 5-20 (Continued)

Optical coupled light beam Input light beam signals

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FIGURE 5-21 Measured attenuation characteristic curves for dark operation, including insertion loss (IL), return loss (denoted as BR, i.e., back-reflection loss), polarizationdependent loss (PDL), and micromirror displacement versus the driving dc voltage.

light path is shifted far away from the initially optimized light path. In this way, a bright-type VOA reaches its full attenuation (bottom left in Fig. 5-20d), whereas a dark-type VOA reaches its full transmission state (bottom right in Fig. 5-20d). Figure 5-21 shows the measured attenuation characteristics for a reflective VOA operating in a dark-type manner. A dynamic range of 30 dB was achieved for dark-type operation under a driving voltage of 5.25 to 8.25-V dc. The zero-attenuation state (i.e., full transmission state) was reached by applying 8.25-V dc for dark-type operation. The return loss [i.e., back-reflection loss (BR)] was less than –50 dB over the full span for bright-type and –48 dB for dark-type operation, respectively. In addition, the polarization-dependent loss was derived as less than 0.15 dB within 10 dB of attenuation, less than 0.2 dB for attenuation between 10 and 20 dB, and less than 0.3 dB for attenuation between 20 and 30 dB, respectively. Briefly, VOAs using single reflection demonstrate extremely good polarization-dependent loss and better return loss than shutter-based VOAs. With proper design of the comb actuators, a well-optimized DRIE process, and appropriate selection of lense fibers, the reflective VOA is superior, except that there is concern that the package of a reflective VOA with 45 degrees between input and output optical fiber ports is not a common layout configuration in application markets.

Dual-Reflection Mirrors In addressing the layout-format concern mentioned in the preceding paragraph, Lee and colleagues came up with a new retroreflective type of VOA in 2003. Meanwhile, a similar-concept VOA was reported

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Chapter Five by Lim and colleagues as well. Lim and colleagues133 created a folded mirror with 45 degrees between the two reflective surfaces, and this folded mirror was connected with a set of comb actuators and suspended via a silicon beam. This VOA achieved 30 dB of attenuation at 34-V dc. In contrast to the work of Lim and colleagues, the retroreflective VOAs of Lee and colleagues consisted of two separately controlled reflective micromirrors that were allocated in front of the input and output fibers and then assembled in a planar coaxial layout (Fig. 5-22). This design exhibited an insertion loss of less than 0.9 dB, a return loss of less than –50 dB, and a wavelength-dependent loss of less than 0.35 and 0.57 dB at 20 and 30 dB of attenuation, respectively. A measured dynamic range of 50 dB under 7 V dc and a voltage span of 4.7 to 11 V dc was reported for bright- and dark-type operations, respectively. The relevant results were published in 2004.134,135 Basically, this retroreflective attenuation mechanism resulted in a lower operating voltage because the intensity adjustment depends on the light-path shift, which is doubled after retroreflection for the same actuator driving voltage as used in reflective VOAs. These two micromirrors are potentially capable of being feedback-controlled individually; thus the attenuation curve could behave more linearly with dedicated control design. Besides, users in the optical communications industry are familiar with the planar coaxial layout. Additionally, Kim and colleagues have integrated two 45-degree reflective mirrors to form a dual-reflection-based in-line VOA with a minute parallelshifted light-propagation axis between the input and output ports.136 They also reported a comprehensive comparison between a singlereflection VOA using lens fibers and a dual-reflection in-line VOA using common optical fibers.

Rotary-Comb Actuator Lim and colleagues further explored the possibility of driving a folded mirror with a rotary-comb actuator for VOA application. This VOA consisted of a folded mirror connected with a rotary comb via a suspended beam. The attenuation was reported to be 45 dB at a rotation angle of 2.4 degrees under 21-V dc, and response time was less than 5 ms.137 Yeh and colleagues138 reported on a reflective-type VOA. This new VOA attenuates the optical power using a planar rotational tilted mirror driven by novel rotary-comb actuators. Design considerations that are taken into account include linear spring response, smaller moment of inertia, lower rotational spring constants, and extra optical attenuation induced by displacement in addition to rotation. A centrally symmetric structure that occupies the entire circular area was employed, and meander springs were designed specifically for the desired spring responses. As shown in Fig. 5-23a and b, the micromachined rotary-comb actuator is connected with a tilted mirror, and the entire structure is suspended by four orthogonally cross-linked meander springs anchored at four corners. Four strips of comb-electrode

Optical MEMS Packaging: Communications

(a)

(b)

FIGURE 5-22 SEM photographs of retroreflective MEMS VOAs: (a) Two reflective micromirrors and two coaxially arranged fiber trenches to form a retrorefractive VOA; (b) close-up view of micromirrors created via DRIE of an SOI substrate.

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FIGURE 5-23 (a) SEM photograph of a MEMS VOA using a rotary-comb actuator. The VOA has four anchors at the ends of two orthogonally located meander springs. (b) Close-up SEM photograph of the 45-degree tilted rotational mirror driven by a beam linked via a rotary-comb actuator. (c) Measured attenuation curve versus driving voltage.

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FIGURE 5-23 (Continued)

pairs are packed in each quarter of the rotary-comb actuator. The meander springs were deployed to reduce the rotational spring constant Kφ and to maintain the sufficiently large ratio of radial spring constant Kr to Kφ. Hence stable rotations at low driving voltages can be achieved, along with high radial robustness in the device plane. The device was reported to have 50 dB of attenuation at a rotation angle of 2.5 degrees under 4.1-V dc, as shown in Fig. 5-23c. The response time from 0 to 40 dB of attenuation and backward switching time were measured as 3 and 0.5 ms, respectively. The measured insertion loss was 0.95 dB, and the polarization-dependent loss was 0.3 dB at 20 dB of attenuation with a wavelength of 1550 nm. The wavelength-dependent loss was measured to be 0.19, 0.25, 0.61, and 0.87 dB for attenuations of 0, 3, 10, and 20 dB, respectively.

Functional Shutter and Elliptical Mirror In 2003, a wedge-shaped silicon optical leaker (i.e., a revised shutter) was proposed as a new refractive-type VOA by Kim of the Korean Aerospace Research Institute, Yun and colleagues of the Gwang-Ju Institute of Science and Technology, Gwangju, Korea, and Lee and colleagues of the Samsung Electro-Mechanics Company, Suwon, Korea.139–141 With proper design of the wedge shape, this type of shutter allows multiple optical internal reflection to occur near the fiber core of the input and output fibers. Thus only a small portion of the incoming light leaks out with a tilted propagation angle. This device achieved a return loss of less than –39 dB and a wide attenuation range of 43 dB for 8-degree optical-fiber facet ends, whereas polarizationdependent loss also was less than 0.08, 0.43, 1.23, and 2.56 dB for attenuations of 0.6, 10, 20, and 30 dB, respectively. Without using a 45-degree reflection mirror, Liu and colleagues at NTU, Singapore, proposed a novel elliptical mirror driven by an axial movable-comb actuator in which the input and output fibers were

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Chapter Five arranged and aligned in an orthogonal layout regarding the elliptical mirror.142 In this unique design, the input and output fibers were allocated at the two focal centers of the reflective elliptical mirror. Since the ellipse can focus the light from one center to the other, the VOA enjoys low insertion loss while using common single-mode fibers. As the mirror is shifted in the axial direction of one fiber, the input beam is rapidly defocused, producing a wide attenuation range without requiring a large mirror displacement. A dynamic range of 44 dB was achieved at 10.7 V dc, whereas the response time was 0.22 ms. The insertion loss was 1 dB, and the polarization-dependent loss was 0.5 and 0.8 dB at 20 and 40 dB of attenuation, respectively. The measured wavelength-dependent loss was 1.3 dB at 20 dB of attenuation within 1520 to 1620 nm. Without using expensive optics (e.g., lensed fibers), this new designs provided very interesting results with promising application potential. In 2007, Liu and colleagues at NTU, Singapore, proposed an innovative design of a retroreflective VOA using a parabolic micromirror pair.143 They deployed a rotary mechanism to rotate this parabolic micromirror pair. The input and output fibers were arranged in parallel, and a rod lens was added in between the parabolic micromirror pair and the fiber pair. This device shows good linearity of attenuation versus rotation angle within the attenuation range of 60 dB, and the polarization-dependent loss and wavelength-dependent loss exhibit moderate values. As discussed earlier under the issue of the linearity of attenuation, we have two major nonlinear factors to be considered. First, the moving distance of the microshutter is proportional to square of the driving voltage of the electrostatic comb actuator. Second, the collimated optical beam shows a Gaussian distribution. Lee and colleagues at the Gwang-Ju Institute of Science and Technology, Gwangju, Korea, demonstrated an in-line shutter-type VOA with a linear attenuation curve by using a comb actuator with a curved comb finger shape.144 On the other hand, Liu and colleagues at NTU, Singapore, demonstrated another way to achieve the attenuation versus driving voltage with good linearity by using two curved shutters connected by a pair of individually controlled comb actuators.145 This device shows very good linearity within 25 dB of attenuation with 8-V dc of driving voltage. Recently, Glushko and colleagues146 reported a two-shutter VOA with advantage in reduced driving voltage and compensation of nonlinearity.

5.4.4 DRIE-Derived Planar VOAs Using Electrothermal (Thermal) Actuators All the devices discussed so far have relied on electrostatic actuation mechanisms. Since there is no current flowing between the electrodes of the electrostatic actuators, there is no power consumption within the actuator part during operation of electrostatic actuators. However,

Optical MEMS Packaging: Communications electrothermal actuators are known for their large displacements and high force output. These characteristics make electrothermal actuators a viable alternative for VOA devices. The size and weight of MEMS elements are relatively small, and only a small amount of energy is required to operate a MEMS-based VOA. In other words, the power consumption of an electrothermally driven MEMS VOA is expected to be low as well. Moreover, the nature of the electrothermal actuator structure means that an electrothermally driven MEMS VOA has a smaller footprint and a lighter weight than one with an electrostatic actuator. Chiou and colleagues147 deployed two pairs of U-shaped electrothermal actuators linked together to push two separate microshutters on opposite sides. Although these four U-shaped actuators have been symmetrically placed at the four corners of device, the robustness of this VOA is still constrained by the mechanical weakness of the flexure beam of the U-shaped actuator itself. The driving voltage was as low as 4.5 V dc with 45 dB of attenuation owing to the benefits of the two-shutter approach. The two-shutter concept was first implemented by Chiou and colleagues for reducing the needed moving distance for each shutter. Thus the device gained the advantage of a reduced driving voltage. As shown in Fig. 5-24, Lee148 has reported an H-shaped silicon beam structure consisting of two V-beam electrothermal actuators on both sides and a pair of reflective mirrors for VOA application, where a pair of mirrors is arranged at the center of a linked beam between two V-beam electrothermal actuators. When a dc bias is applied to the anchors of the V-beam, volume expansion owing to Joule heating will

H-Shaped electrothermal actuator of high-aspect-ratio structure along with the perpendicular directions to moving axis

Anchors onto substrate Moving direction Moving direction (arched direction of V-beam) Antishock stopper

Attenuated Original 0

0

(a)

(b) Movable reflective mirrors

Input fiber Output fiber

(d)

(c)

FIGURE 5-24 VOA device consisting of retroreflective mirrors driven by a linked electrothermal V-beam actuator pair, where four anchors of the V-beam actuators pair are arranged symmetrically on the four corners of device to form a robust VOA structure: (a) Schematic drawing; (b) SEM photograph of retroreflective mirrors and link beam; (c) close-up SEM photograph of mirror; (d) the retroreflective light path attenuation scheme.

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Chapter Five distort the beams on both sides of the H-beam in the arched direction (i.e., denoted as the moving direction in Fig. 5-24). The position of the retroreflective mirrors depends on the applied voltage. If we applied the same bias to both V-beams, the displacement generated of both sides would be the same. Optical attenuation happens when the retroreflective mirrors move from the initial location, where attenuation is optimized in terms of minimal insertion loss. The maximum dynamic range of attenuation was 50 dB under 9-V dc. The polarization-dependent loss was measured as 0.15 dB at 20 dB of attenuation. Lee149 also demonstrated a planar attenuation micromechanism consisting of a planar tilted mirror driven by a V-beam electrothermal actuator via a link beam, as shown in Fig. 5-25a and b. This electrothermally driven tilted mirror can be displaced statically with a motion trace that includes rotational and translational movement, as shown in Fig. 5-25c and d. The rotational and translational misalignment of the reflected light spot toward the core of the output port fiber will lead to light attenuation. Thus the attenuation is controlled by the position of tilted mirror, which depend on the driving dc voltage. This micromechanism provided a more efficient way to conduct the attenuation with respect to the other kinds of planar VOAs. The device achieved 30 dB of attenuation under a 7.5-V dc bias. The PDL was less than 0.1 dB, within the 30-dB attenuation region.

5.4.5 3D VOAs Combining optics and a tilt mirror or an array of mirrors to be assembled in a 3D configuration is also a key approach in making MEMS VOA devices. Andersen and colleagues150 in 2000 reported a surfacemicromachined tilted mirror using a 3D attenuation scheme, whereas Riza and colleagues151 reported a 3D VOA using the Digital Mirror Devices (DMD) micromirror array of Texas Instruments in 1999. Robinsen152 filed in a U.S. patent in 1998 on this sort of tilted mirror idea; that is, the attenuated light is controlled by changing the tilt angle of the mirror or a portion of a mirror array in a digital manner, as shown in Fig. 5-26a. However, early demonstrations show only moderate performance. In principle, we may prepare a large single-crystal silicon tilt mirror by using state-of-the-art DRIE micromachining technologies.153 When tilt mirrors are deployed for 3D VOAs in conjunction with large microoptics, such as the dual core collimator, the resulting VOA can show excellent return loss, PDL, and WDL under a reasonable driving voltage (i.e., a small rotational angle). Toshiyoshi and colleagues have demonstrated a 3D VOA that uses an electrostatic parallel-plate actuator in which the performance is very good in this sense; that is, only 4.5 V dc can achieve 0.3 degree of rotational angle and 40 dB of attenuation.154–156 Recently, Lee and colleagues157 developed a 3D VOA based on a pair of PZT actuators, as shown in Fig. 5-26b. In the operation of a

Optical MEMS Packaging: Communications Rotational axis Anchor

F

Electrothermal actuators

Spring

Plannar tilted mirror θ

Spring

Link beam

Plannar tilted mirror

(a)

(b)

Fiber trench

(c) Actuator

Translational displacement

B

∅ t

Spring

B′

Planar tilted mirror

D′

Original reflected light path C

A 2∅

(d)

D

Displacement

Rotational angle

BE // B′E′

E Reflected light path caused by rotational E′ effect only Reflected light path caused by overall actuation effect

FIGURE 5-25 VOA consisting of a planar tilted mirror driven by a V-beam electrothermal actuator: (a) Schematic drawing; (b) CCD image of the tilted mirror, spring, link beam, and electrothermal actuator of the VOA; (c) CCD image of the tilted mirror, spring, and trenches for accommodating fibers; (d) novel planar light attenuation scheme is realized by using this tilted mirror with rotational and translational displacement.

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Chapter Five FIGURE 5-26 (a) Schematic drawing of the optical path in a 3D VOA including a tilted mirror and optics. (b) Schematic drawing of a tilt mirror for a 3D VOA. The mirror rotates against the torsion spring owing to static displacements introduced by the lead-zirconatetitanate (PZT) actuator beams.

Collimating lens

Torsion spring

Rotation

MEMS tilt mirror (a) Torsion spring

PZT actuator B

Bending spring Mirror

PZT actuator A

(b)

PZT 3D VOA, various dc biases are applied to one or two of the actuators. Then the reflected light is deviated from the optimized light path in a manner that corresponds to the minimum insertion loss. Therefore, the insertion loss is increased as the increased dc bias because the coupled reflected light intensity toward output fiber is reduced (i.e., the attenuation operation). As shown in Fig. 5-27a, an SOI substrate with a 5-μm-thick Si device layer and a 1-μm-thick buried oxide (BOX) layer was used as the starting material. A thermal oxide layer of 0.37 μm was created from the Si device layer surface. A multilayer electrode of LaNiO3 (0.2 μm)/Pt (0.2 μm)/Ti (0.05 μm) was prepared by radiofrequency (for LaNiO3) and dc (for Pt/Ti) magnetron sputtering, respectively. Then a 3.1-μm-thick PZT thin film was formed by sol-gel deposition, as reported previously. The (100)-oriented PZT thin film prepared on the LaNiO3 buffer layers exhibited columnar structure, as shown in Fig. 5-28. This kind of (100)-oriented textured film exhibits a higher dielectric constant than the randomly oriented film and the (111)oriented film. The deposited films were pyrolyzed at 200 to 470°C for 5 minutes and then crystallized by rapid thermal annealing at 700°C for 2 minutes. Finally, a top electrode of Pt/LaNiO3 was sputtered on

Optical MEMS Packaging: Communications

(a)

(d)

(b)

(e) Mirror

Free-standing actuator beam (c)

(f) Si

SiO2

Electrode

PZT

FIGURE 5-27 Microfabrication process flow for making PZT actuators and mirror.

top of the PZT layer. The poling condition is 30 V for 10 minutes at room temperature. A Pt bottom electrode is used because it is a stable metal in this temperature range. The measured transverse piezoelectric constant d31 of –110 pm/V of the fabricated 3.1-μm PZT layer is rather good compared with published data, which show d31 ranging from –50 to –110 pm/V. Figure 5-27b shows how the top Pt thin film was etched by Ar ion etching and the top LaNiO3 thin film was subsequently etched by diluted HCl. Then the PZT thin film was etched by a mixture of HF, HNO3, and HCl. Finally, the bottom LaNiO3/Pt/Ti electrode layers were etched again, whereas the thermal oxide layer was etched by CHF3 reactive-ion etching to open the area of the mirror and springs shown in Fig. 5-27c. Thereafter, the mirror, springs, and frame of the actuators were patterned from the silicon device layer of the SOI substrate by DRIE, as shown in Fig. 5-27d. Then a 0.07-μm-thick Pt film

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Pt/LNO

PZT: 3.1 μm LNO/Pt/Ti/SiO2 Device layer Si: 4.8 μm

Box: 1 μm Handle wafer Si

5 μm

FIGURE 5-28 SEM micrograph in cross-sectional view of a PZT actuator thin film on an SOI substrate.

was deposited on the mirror as the reflective surface by a lift-off step, as shown in Fig. 5-27e. The lift-off method is chosen to avoid the difficulty of finding good etching stop materials for Pt in the Ar ion etching process. We used Pt as the mirror coating layer because we planned to conduct the postprocess annealing for the PZT layer initially. Only the Pt is very stable even in the annealing step with temperatures as high as 700°C. Using DRIE, the backside Si portion and BOX were etched from the substrate backside to release the mirror, springs, and actuators, as shown in Fig. 5-27f, whereas we used SF6 and CHF3 as the etching feedgas for Si and SiO2 etching, respectively. Figure 5-29 shows the attenuation curve measured when both actuators were under the same dc bias. Only 1 V dc can achieve 42 dB of dynamic range of attenuation, whereas 50 dB is obtained at 1.2 V dc. The optical deflection angle is measured as 0.18 degree at 1 V dc. Referring to most of the commercial applications, the 40-dB dynamic range is enough. This means that the PZT 3D VOA requires an operating voltage of only 1 V dc.157

5.4.6 VOAs Using Various Mechanisms Another type of 3D VOA relies on a grating structure (i.e., a diffractive type of mechanism).158 By modifying the original design of grating light valve (GLV) diffractive technology, Lightconnect has proposed a

Optical MEMS Packaging: Communications

Attenuation (dB)

60 50 40 30 20 10 0 1.2

1 0.8 0.6

Bias of actuator A (V)

0.4 0.2 0

0

0.2

0.4

0.8

0.6

1.2

1

Bias of actuator B (V)

FIGURE 5.29 Measured attenuation curve versus dc driving voltage equally applied to PZT actuators A and B, respectively.

revised design using a circularly symmetric membrane structure.159–161 This novel diffractive MEMS VOA is known as the first Telcordiaqualified MEMS VOA. As the SEM photograph in Fig. 5-30a shows, the microfabrication process of a diffractive MEMS VOA starts with patterning of the reference posts with a height of 2.32 μm. Then a thin (20 to 60 nm) layer of silicon dioxide is grown thermally. A layer of sacrificial polysilicon or amorphous silicon is deposited thereafter. This layer must remain optically smooth. If not, any defects on this

Reflecting membrane Release holes

Anchor to substrate

d=N Silicon substrate Array of fixed posts

(a)

Reflecting surface

λ0 2

Achromatic compensator

(b)

FIGURE 5-30 (a) SEM photograph of a diffractive MEMS VOA. (b) Schematic drawing of the diffractive MEMS VOA. The architecture incorporates achromatic compensation and cylindrical symmetry to ensure low dependence on polarization.159–161

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Chapter Five sacrificial layer will subsequently imprint the movable membrane. Holes are etched through the sacrificial layer to allow for the anchor points to the substrate. Silicon nitride film then is deposited and patterned as the movable membrane. Finally, xenon difluoride (XeF2) is used to etch away the sacrificial layer of silicon and to release the membrane. A subsequent gold coating across the entire surface is required to ensure high reflectivity in the infrared-wavelength range. The closely spaced suspended reflective membrane used for the GLV forms an adjustable-phase grating. When the reflective membrane and reflective post surface are coplanar, incident light is reflected back into the aperture without attenuation (Fig. 5-30b). When the reflective membrane is pulled down using electrostatic actuation by one quarter of a wavelength (λ/4) relative to its adjacent reflective post surface, the incident energy diffracts into higher orders that are directed outside the aperture, and the incident beam is completely attenuated. When the separation gap is less than λ/4, the incident beam is partially attenuated because some energy is shifted into the higher diffracted orders. Another unique feature of this diffractive MEMS VOA is the reduction in PDL provided by the design. Without using the ribbonlike microstructures in the GLV device, Lightconnect’s diffractive MEMS VOA deploys reference circular posts to replace the reference ribbon and a suspended reflective membrane to be the movable ribbon. Moreover, the achromatic compensating ribbons become annular rings around the reference posts. The suspended reflective membrane incorporates an array of air holes that assist in fast and uniform removal of the sacrificial layer during fabrication. The dimensions of the gaps remain the same as in the GLV device. In a typical design, N refers to 3 for the center wavelength of 1550 nm, corresponding to a height difference of 2.32 μm between the movable membrane and the compensating annuli. The periodicity of the repeating diffractive element is typically between 20 and 200 μm. The widths of the reference posts, as well as the gaps between the posts and membrane, are typically a few micrometers. This diffractive MEMS VOA has a dynamic range (attenuation range) of 30 dB, a WDL of 0.25 dB, and a PDL of 0.2 dB. The total insertion loss, which includes losses from fiber coupling, is 0.7 dB. The response time of the device is outstandingly fast (i.e., 40 μs) and is attributed to the small mass and short actuation distance (e.g., λ0/4 ≅ 400 nm). The actuation voltage is less than 8 V. We should also address the efforts in digital VOA development. By using an array of digital mirrors (i.e., maintained at either the rest position or the tilted position) with a fixed deflection angle, we may individually address bias to a column of mirrors or a single mirror of an array.162,163 The extended dynamic range of attenuation is up to 80 dB162 and an attenuation curve with good linearity is feasible. On the other hand, to avoid the requirement of on-hold voltage or power, a vernier-type latching mechanism for an in-line shutter-type

Optical MEMS Packaging: Communications VOA affords as small as 0.5-μm step resolution, as has been reported by Syms and colleagues.164,165 Moving-fiber mechanisms can lead to two aligned fibers being moved to misaligned positions from the optimized coupling position so as to perform the power attenuation. Thermal actuators have been proven to be good candidates for movingfiber optical switches.166–168 Such mechanisms can be used as VOAs as well because of analogue control capability. Approaches using a polymer waveguide or a MEMS polymer membrane structure have been investigated and show the potential advantages of a small footprint and low cost.169–172 Optofluidic technology has been applied to VOAs as well.173 Based on the preliminary results, rather good VOA characteristics, including a 38-dB dynamic range, 0.479 dB of insertion loss, and a PDL less than 0.4 dB have been reported.173 Electromagnetic actuation applied to a VOA has been reported to achieve 50 dB of attenuation under only 4 V.174 In order to achieve better optical characteristics, a pair of single-mode fiber collimators is deployed to integrate with a large shutter, a 500 × 1200 μm vertical micromirror, on top of an electromagnetic coil actuation flap. The micromirror was created by tetramethyl ammonium hydroxide (TMAH) anisotropic wet etching with a sharp edge and a smooth reflecting surface. The insertion loss of the VOA is 0.2 and 0.4 dB for normally-on and normally-off modes, respectively. The dynamic range of 40 dB is achieved at 0.5 V, and the driving power is less than 2 mW. A response time of 5 ms is achieved.175

5.5

Packaging, Testing, and Reliability Issues Optical MEMS devices involve either free-space propagation of bounded beams, wave guidance, or a mixture of the two. Optics design can be achieved by considering the properties of Gaussian beams, which propagate in free space and in cylindrically symmetric graded-index media.9 From these properties, we can determine layouts of a MEMS chip and its package. The typical arrangements are categorized into two approaches: (1) chip-level optical alignment and (2) package-level optical alignment. First of all, in the case of chiplevel optical alignment, a wet-etched V-groove can be used as a fiber holder, as shown in Fig 5-31a. A fiber can be aligned to a laser that is placed on top of the V-groove mirror at the end of the groove for holding the fiber. Thus the light coupling via a V-groove mirror can be optimized between the laser chip and the fiber end. This step eliminates all the degrees of freedom except axial motion. The fiber then may be butt-coupled and the assembly fixed by epoxy. An alternative method of alignment relies on a robust metal fixture to hold the components. As shown in Fig. 5-31b, a number of such fixures are soldered to a substrate and used to provide individual mounts for a set of components to form a free-space optical breadboard. This approach was pioneered by Axsun Technologies.176 When combined with

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Chapter Five

Laser chip Optic fiber

Probe tip

Shutter

Optical lense fiber (a)

(c) Tilt mirror Fixture

Rotary comb Optic component (b)

Optical lense fiber Optic fiber (d)

FIGURE 5-31 (a) SEM photograph of a typical optoelectronics hybrid package based on an Si optical bench showing passive optical alignment from laser to single-mode fiber to better than 1 μm of accuracy.5 (b) SEM photograph of a freespace optical breadboard using a micromachined metal fixture to clamp the fiber in a predetermined position aligned with the optoelectronic device.5 (c) Optical microscope photograph of a crossbar switch assembled with four optical fibers in DRIE trenches.75,82 (d) Optical microscope photograph of an electrostatic rotarycomb-driven VOA tilt mirror integrated with two optical fibers in DRIE trenches.138

MEMS device fabrication, the fiber trenches can be easily created on the silicon, especially for SOI substrate. For example, the fibers are aligned and assembled inside the trenches for a crossbar optical switch (Fig. 5-31c) and a tilt-mirror VOA (Fig. 5-31d). In the second approach, discrete components are assembled and aligned on a carrier substrate. The electrical interconnects of the assembled components are finished either by wire bonding or flipchip bonding. Then the substrate integrated with several discrete components is arranged in a metal case. In the last step, this metal case typically is hermetically sealed by a seam welder or a laser welder. For example, Fig. 5-32a shows a schematic drawing of a MEMS-based tunable external cavity laser based on a Littman-Metcalf geometry consisting of a diffraction grating illuminated at near-grazing incidence for angularly dispersing light and a mirror on a rotary-comb structure for retroreflecting finite spectral components. Continuous tunability is achieved by rotating the mirror and selecting the wavelength

Optical MEMS Packaging: Communications Lenses

Laser diode

PM fiber pigtail Grating

Wavelength locker

MEMS actuator (b)

Silicon mirror

Shutter/ VOA Beam splitter Isolator

(a)

FIGURE 5-32 (a) Conceptual drawing of a packaged MEMS-based tunable laser with an intracavity grating spectral filter. (b) Photograph of a vertical mirror driven by a rotary-comb actuator integrated with grating, lens, and laser to form the cavity.177,178

that satisfies retroreflection. The rotary comb rotates the attached mirror about a virtual pivot point that is at the intersection of the grating and mirror planes. The position of this pivot point is critical. Cavity length control is provided by a piezoelectric actuator that translates the diffraction grating in order to achieve a full communication-band tuning range. In this double reflection-diffraction arrangement, the light diffracts from the grating toward the mirror, reflects back to the grating, diffracts a second time from the grating, and then falls on the mirror, on which it is a retroreflection path for the center wavelength. By leveraging this design, the angular rotation-range requirement of mirror is reduced because it is directly related to the filter’s tuning range.177,178 From this case, translation and angular misalignment of the relative positions among these components are crucial to the performance of these optical MEMS devices in assembled packages. In fact, angular misalignment is the main concern in all kinds of MEMS devices for optical communications applications. 3D optical switch packaging will be discussed in Sec. 5.5.3. Generally speaking, the packaging of optical MEMS devices constitutes up to 80 percent of the final cost of the device. To highlight these key concerns in optical MEMS packages, we explore such issues from the points of view of manufacturability, yield, and reliability.

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5.5.1

Manufacturability and Self-Assembly

When we consider the manufacturability of an optical MEMS device, we have to look into all the facts related to yield. The yield loss could refer to front-end wafer process factors such as cross-wafer discrepancy of etch rate, residual stress, and film thickness, as well as backend packaging process factors such as damage and contamination introduced in the dicing process, optical loss owing to misalignment in assembly, failure in hermetic sealing owing to a leak in the housing, and the like. However, given the lack of a qualified tool for investigating 3D microstructures such as vertical mirrors in most of optical MEMS devices, we can only conduct final system-level testing. Although a general visual inspection and an actuator function test can be conducted at the wafer level, quite a few parameters can be measured only after fully complete or semicomplete packaging. Multichanneled optical MEMS devices have become indispensable in wavelength-division-multiplexed (WDM) telecommunication networks, such as optical cross-connects (OXCs), wavelength equalizers, and multichanneled variable optical attenuators (MVOAs). Using silicon DRIE to sculpt actuators and micromirrors from SOI substrates has been the most available micromachining process for realizing optical microsystems. A retroreflective MVOA with eight channels packaged in a metal case, as shown in Fig. 5-33, is the basis of our case study. To investigate its manufacturability, we characterized several MVOA devices in terms of insertion loss, PDL, back-reflection loss, and WDL. This eight-channel MVOA has monolithically integrated

FIGURE 5-33 Photograph of a packaged eight-channel MEMS VOA based on a retroreflective light-path arrangement.

Optical MEMS Packaging: Communications Percentage % 100 90 80 70 60 50 40 30 20 10 0 0.07 0.12 0.16 Polarization-dependent (a) loss (PDL; dB)

Percentage % 100 90 80 70 60 50 40 30 20 10 0 0.12 0.17 0.22 0.25 Polarization-dependent (b) loss (PDL; dB)

Percentage % 100 90 80 70 60 50 40 30 20 10 0 0.14 0.18 0.22 0.28 Polarization-dependent (c) loss (PDL; dB)

Percentage % 100 90 80 70 60 50 40 30 20 10 0 48.5 50.8 52.3 54.6 Back-reflection (d) loss (BR; dB)

Percentage % 100 90 80 70 60 50 40 30 20 10 0 47.7 50 52.1 55.5 Back-reflection (e) loss (BR; dB)

Percentage % 100 90 80 70 60 50 40 30 20 10 0 48.2 50.3 52.8 54.2 Back-reflection (f) loss (BR; dB)

57

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57

FIGURE 5-34 Histogram of mean-value distribution of measured data from each individual channel of a multichanneled VOA using a retrorefractive attenuation scheme showing PDL and back-reflection loss characteristics, where (a) and (d) represent measurement at 10 dB of attenuation; (b) and (e), at 20 dB of attenuation; and (c) and (f), at 30 dB of attenuation.

mirrors and optical fibers in a retroreflective type of light-path arrangement in an SOI substrate. A monolithically integrated VOA with multiple channels requires very good process control in microfabrication. As shown in Fig. 5-34, experimental study of such critical parameters as insertion loss, PDL, return loss, and WDL was done for several MVOA devices.179 In a well-controlled process, these MVOAs commonly provide excellent optical performance. These devices show a dynamic range of 50 dB, insertion loss of less than 0.8 dB, back-reflection loss of better than 50 dB, and PDL of less than 0.3 dB over the full span of attenuation. Each channel of an arrayed VOA device can be controlled individually. The channel number is potentially scaled up to 16 channels from 8 channels in current devices configurations. The correlation among measured data on PDL and back-reflection loss, design of the MEMS mirror, and surface quality of the MEMS mirror is not clear so far. The arrayed MEMS VOA using a retroreflection light attenuation scheme and planar layout configuration demonstrates competing optical characteristics and a cost-effective solution in terms of manufacturability, scalability, and compact footprint.179 On the other hand, fully automatic techniques are being developed for assembly of optical MEMS 3D structures. For example, the surface-micromachined shutter and structures are relatively fragile.

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Chapter Five

L-shaped curved beam for lifting up shutter plate

Planar latches Scratch-drive actuator (SDA)

(a)

(b) Pop-up shutter clamped by arm lockers

Pop-up shutter driven by SDA into fiber-end spacing

(c)

(d) Curved-flexure-beam electrostatic actuator

FIGURE 5-35 Schematic drawings of self-assembled VOA with pop-up shutter and stress-induced curved-beam electrostatic actuator: (a) device configuration before structure release; (b) device configuration after released and self-assembly; (c) microshutter driven by SDAs and moved into the space between fiber ends; (d) microshutter moved downward and performed the optical attenuation.

During the optical fiber alignment and assembly process, these microstructures are vulnerable to damage when the optical fiber touches the microstructures unexpectedly. Lee and colleagues180,181 reported a self-assembled VOA in 2003. As shown in Figs. 5-35a and b and 5-36, the self-assembly mechanism first allows the reflective shutter to be lifted up and fixed by two individually controlled stress-induced curved polysilicon beams. Second, this self-assembled reflective shutter is driven by a set of electrostatic SDAs that slide into the space between the input and output fiber ends (Fig. 5-35c and d). Then the attenuation is determined by the vertical position of the self-assembled pop-up polysilicon reflective shutter, which is controlled by an applied dc bias. In terms of the mass production of MEMS VOAs nowadays, we normally place and align the input/output fibers above the MEMS chip with the V-groove trench at the beginning. These elements and/ or optics will be fixed at relative positions by laser welding, soldering, or ultraviolet (UV) curing. Thereafter, the assembled components are accommodated into and fixed inside the product housing. As shown in Fig. 5-37, we proposed a new manufacturing flow based on this self-assembly technology to make surface-micromachined VOA devices. First, we could align and fix two fibers on a silicon carrier chip with V-grooved trenches to get an optimized coupling efficiency (i.e., the lowest insertion loss) (see Fig. 5-37a). In the meantime, the

Optical MEMS Packaging: Communications

Curved beam acted as electrostatic actuator

SDA Residual stressinduced curved beam for lift-up

Shutter plate

FIGURE 5-36 The SEM photograph of a MEMS VOA with the shutter being lifted by an L-shape stress-induced curved beam and clamped by the arrowhead locking element. (Inset) Close-up view of the bottom of the shutter plate, which is clamped by the arrowhead locking elements.

shutter plate is released first and lifted; then it is fixed on a curved polysilicon beam electrostatic actuator (see Fig. 5-37b). Thereafter, we could attach this self-assembled MEMS chip onto the fiber’s assembled carrier chip using flip-chip technology (see Fig. 5-37c) because the shutter and peripheral MEMS actuators and structures are designed to be allocated away from the area of fiber-to-fiber spacing. As a result, we could avoid damaging the fragile shutter and microstructures during flip-chip assembly. The fiber carrier chip is depicted as an opaque form in the schematic drawing to show the 3D geometric relationship of the relative elements. The V-groove through-wafer electrical feedthrough also is shown on top of the assembled device chip. In the step illustrated in Fig. 5-37c, we could apply an electrical load via the through-wafer electrical feed-through on a set of SDAs located in the area surrounding the shutter, which is hinged on a curved-beam electrostatic actuator. Since the relative positions of the fibers, actuators, and pop-up shutter are determined by photolithographic accuracy, this SDA set and connected polysilicon frame will move forward so as to drive the curved-beam electrostatic actuator and pop-up shutter concurrently toward the tiny space precisely between the two fiber ends. Furthermore, this VOA demonstrated continuous attenuation capability, a wide attenuation range of 60 dB, and an insertion loss of less than 1 dB under the 8 and 5 V dc for bright and dark operation, respectively. This self-assembly approach for creating a VOA reveals the potential solution of getting rid of tedious optical alignment and assembly efforts while drastically reducing or eliminating damage to the fragile surface-micromachined polysilicon shutter.

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Chapter Five FIGURE 5-37 Schematic drawings of the self-assembly mechanism: (a) the fiber-aligned carrier silicon chip; (b) flipchip bonding of the fiber carrier chip and chip with a self-assembled pop-up shutter; (c) final completed MEMS VOA, in which the pop-up shutter is driven by an SDA and moved into the space between the fiber ends.

(a)

(b)

(c)

On the other hand, Uttamchandani and colleagues182 at the University of Strathclyde has demonstrated a thermally controlled selfassembly mechanism for creating the pop-up microshutter, whereas the assembled microshutter is driven by an array of SDAs. In all, 45 dB of attenuation could be achieved at lateral displacement of the popup microshutter of about 20 μm with driving voltages of 60 to 290 V ac for various moving speeds of the microshutter.

Optical MEMS Packaging: Communications

5.5.2 Case Study: VOAs Now that we have a basic understanding of manufacturability in terms of yield in front-end and back-end processes, we can look into the factors that influence final product reliability. Generally speaking, the reliability of MEMS devices strongly depends on the detailed design of those structures, as well as the technologies used to fabricate them. These factors include materials failure, vibration tolerance, temperature dependence, and the stiction issue after long-term operation.

Electrostatic VOAs As illustrated in Fig. 5-26a, a MEMS tilt mirror is placed at the back focal plane of the lens to form a 3D VOA. In Sec. 5.4.5 we discussed a 30-μm-thick tilt mirror with a diameter of 600 μm driven by a parallelplate actuator, as shown in Fig. 5-38a.154–156 This VOA is made by using a double-sided DRIE process and HF vapor-phase etching62 to release the mirrors from the SOI substrate. A TO-Can-like package with a diameter of 5.6 mm and a length of 23 mm is demonstrated for a hermetically packaged 3D VOA. When the mirror is in the unactuated state, light from the input fiber is collimated by the lens onto the mirror, is reflected back, and subsequently is focused by the lens onto the output fiber. The PDL is minimized because the beam is almost normally incident onto the mirror. To perform the attenuation, a dc electrical bias is applied across the mirror plate and underneath the silicon substrate of the handle wafer portion of a SOI substrate, and the tilt mirror will bend toward the bottom electrode (i.e., underneath the silicon substrate). When the mirror is tilted, the focused beam is shifted from the optimized path in terms of the output fiber, and this results in increased coupling losses (i.e., the attenuation). To reduce the operating bias voltage, the most straightforward way is to deploy a soft torsion spring for the tilt mirror. However, if the soft spring is too soft, two issues may be introduced in operation. First, the soft springs need to be strong enough to be immune from ambient vibration shock. In the case of this tilt-mirror 3D VOA, two dimensions of the torsion spring have been investigated, namely, ls, hs, and ws = 200, 30, and 2 μm and 150, 30, and 1.6 μm. VOAs of both designs can survive a shock test up to 500g without mechanical failure. The way to avoid damage introduced by mechanical impact is to incorporate a mechanical stopper to limit the allowable spring deformation to within the elastic deformation region. Second, Fig. 5-38b shows the influence of 25g impact on the measured optical attenuation level at an attenuation of 10 dB (i.e., under a bias of 3 to 4 V). A measured fluctuation of more than 7 dB is shown for a VOA with a 200-μm-long spring. Coupling between the mirror angle and external vibration can be explained by the up-and-down motion of the actuator plate, which alters the mean electrostatic gap and thus the mirror angle. Since mechanical analysis tells that the

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Chapter Five suspension rigidity in the torsional motion is proportional to ws3 × ls, whereas that in the direction of bending (normal to substrate) is proportional to ws × ls3, the torsion spring rigidity in this direction can be almost doubled by shortening the length to 75 percent (from 200 to 150 μm) and thinning the width to 80 percent (2 to 1.6 μm) without stiffening rotational rigidity (or without increasing driving voltage). By using the shorter torsion spring (150 μm in length and 1.6 μm in width), the measured attenuation fluctuation is suppressed almost 50 percent and becomes 3 dB, as shown in Fig. 5-38b. Generally speaking, a stiff torsion spring can increase the dynamic stability of a VOA, but the tradeoff is a larger driving voltage. While the sizes of the mirror and springs are reduced, maintaining the necessary aspect ratio to produce the required stiffness is achieved. This is a good way to increase the mechanical stability of VOA mirrors significantly. On the other hand, the collimated optical beam size is another factor that needs to be considered. Optical fibers integrated with a microlens typically offer a focused-beam size of less than 50 μm,184 whereas optical fibers integrated with a collimated lens or GRIN lens normally provide a focused-beam size of 450 to 900 μm. In the 3D VOA configuration, an optics-provided focused-beam size of 450 to 900 μm normally is adopted. Thus the 600-μm-diameter mirror is designed for this reason.154–156 This also implies that reducing mirror size and mass and keeping the same aspect ratio of the torsion springs is a good approach to achieving the required mechanical stability of VOA mirrors, but the limit on the smallest mirror size is about 500 to 600 μm in 3D VOAs. However, the temperature dependence of attenuation characteristics must be explored. In order to apply open-loop control for VOA operation, good thermal stability of the VOA is necessary. Although we typically expect that the temperature dependence of the actuation characteristics of an electrostatically driven mirror is negligible, Isamoto and colleagues155 reported a measured fluctuation of 0.5 dB at 10 dB of attenuation in the temperature range of –5 to 70°C. As the conceptual curves of tilt angle versus voltage show in Fig. 5-38c, the mirror tilts more in the case of low ambient temperature under the same drive voltage but with a smaller contact angle (i.e., less maximum rotation angle). This deviation in rotation angle under the same voltage is attributed to the difference in thermal deformation of the mirror and the actuator plates at different temperatures. The gap between the mirror plate and the substrate is smaller at lower ambient temperatures. The origin of such variation is attributed mainly to the combination of built-in stress and thermal expansion owing to temperature change in the released device layer of the SOI wafer (i.e., the mirror layer). The built-in stress of the mirror after it is released leads to a 0.5-μm bulking-up deformation over a span of 2.6 mm, including the two sides of the torsion springs and center mirror.

Optical MEMS Packaging: Communications

Optical attenuation, dB

2.4 mm

0

Suspension length ls = 200 μm

–2

Width ws = 2.0 μm

–4

Suspension length ls = 150 μm > 7 dB

Fluctuation

–6

Width ws = 1.6 μm

–8

~ 3 dB Fluctuation

–10

(a)

0

2

(b) Low temperature

High temperature

Reference attenuation with bias voltage

Impulse 25g in x-direction

–12 –2

4 6 Time, ms

8

10

12

20.4 Without backside metallization

20.3

20.1 20.0

Contact angle Low temperature

Pull-in voltage

Mirror angle θ

20.2 Room temperature

High temperature

19.9 19.8 19.7 19.6

Drive voltage, V

(c)

With backside metallization 0

5

10

15

20 25 Time, s

30

35

40

(d)

FIGURE 5-38 (a) Optical microscope photograph of a 3D VOA showing the mirror, springs, and parallel-plate electrode. (b) Temporal fluctuation of attenuation at 10 dB under mechanical impact of 25g. (c) Temperature dependence of conceptual curves of tilt angle versus voltage. (d) Fluctuation of attenuation at 20 dB owing to electrostatic drift.154–156

To remedy this situation, a tensile Au/Cr metal layer coated on the mirror is suggested.155 On the other hand, the Fig. 5-38d shows the drift of the attenuation value in a short period of time after mirror is biased. Drift of ±0.2 dB at 20 dB of attenuation is observed in the figure. Isamoto and colleagues investigated various methods of die bonding and wire bonding. It was reported that a metallization process of the bottomsubstrate backside of the SOI mirror chip could effectively remove the accumulated charge at the bottom substrate.

VOA Using a Thermal Actuator VOAs were made using DRIE to pattern the H-shaped structures from the device layer of 82 μm of a 6-in SOI wafer. After the DRIE step, the H-shaped structure was released from the substrate after wet etched in HF-buffered solution. After chip separation and visual inspection, selected VOA chips were tested to confirm the function of the thermal actuator by applying bias to the electrode pads of the VOA chip on a probe station. The known-good-die characterization has been achieved by examining mirror displacement under various dc electrical biases

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Moving axis (x axis)

Tilt mirrors for retroreflection Lens fiber

(a)

Lens fiber

(b)

FIGURE 5-39 (a) Packaged VOA using an H-shaped beam actuator. (b) Optical microscope photograph of a pair of tilted mirrors and two coaxially arranged lens fibers.

via CCD camera. The selected good dies with qualified motion characteristics of their mirrors were moved to and fixed on a precision xyz stage. Two lens fibers were placed in the two parallel trenches and faced toward the tilted mirrors in front of them. The attenuation versus voltage curve, insertion loss, and PDL were measured as monitored parameters. The selected good dies were glued on ceramic carrier substrates and then placed in a metal case with metal pins on the backside, as shown in Fig. 5-39a. Then two lens fibers were placed in the DRIE-derived trenches, as shown in Fig. 5-39b. The fiber end faced the tilt mirror. The specifications of this lens fiber are discussed in ref. 184. Then the fibers were fixed in the trenches with UV glue after active alignment and a complete function test. Then this chip was finished with wire bonding, and the cover of the metal case was sealed and the fibers through the inlet tube of metal case were sealed with the tube wall. The finished metal package was 12 × 6.8 × 3.5 mm (length, width, and height). Moreover, the device characteristics in terms of the Telecordia GR1221 regulation are very interesting for practical applications. According to the Telecordia GR1221 regulation, the measured dynamic deviation in attenuation at 20 dB of attenuation should be less than ±0.5 dB under a vibration-testing condition of 20g periodic shocks with a frequency from 20 to 2 kHz along with x, y, and z axes, where four cycles of vibrations are required for each axis. In view of such a strict requirement, an H-shaped electrothermal actuation mechanism has been proposed to address this severe requirement, as shown in Fig. 5-24.148,185 By drastically reducing the mass and enhancing the stiffness of the structure, the mechanical resonance frequency of the H-shaped electrothermal VOA becomes much higher than that of its counterpart (i.e., the electrostatic comb-actuator-based design). As listed in Table 5-1, the measured dynamic attenuation fluctuation is less than ±0.03 and ±0.15 dB at 20 dB of attenuation over the full

Optical MEMS Packaging: Communications Moving-mirror axis

<±0.28 dB @ 100 Hz

<±0.30 dB @ 500 Hz

<±0.36 dB @ 1 kHz

<±0.10 dB @ 2 kHz

<±0.03 dB

>20 Hz to 2 kHz

Out-of-plane perpendicular axis <±0.15 dB

>20 Hz to 2 kHz

In-plane perpendicular axis

TABLE 5-1 Dynamic Attenuation Characteristics

x axis @ 100 Hz

0.00

0.01

Fluctuation of attenuation at 20 dB

(a) 21.0 20.8 20.6 20.4 20.2 20.0 19.8 19.6 19.4 19.2 19.0

0.02

0.03

0.04

0.05

0.02

0.03

Time, s

0.04

0.05

x axis @ 500 Hz

0.00

(b)

x axis @ 1000 Hz

0.01

21.0 20.8 20.6 20.4 20.2 20.0 19.8 19.6 19.4 19.2 19.0

0.06

Time, s

0.00

(c)

Fluctuation of attenuation at 20 dB

21.0 20.8 20.6 20.4 20.2 20.0 19.8 19.6 19.4 19.2 19.0

Fluctuation of attenuation at 20 dB

Fluctuation of attenuation at 20 dB

range of 20 to 2 kHz with respect to the axes of in-plane and out-ofplane perpendicular directions to the moving axis, where the moving axis (x axis) is considered to be the central beam with two refractive mirrors of H-shaped structure.185 Figure 5-40 shows that the measured dynamic attenuation deviation is less than ±0.28, ±0.30, ±0.36, and ±0.10 dB at vibration frequencies of 100 and 500 Hz and 1 and 2 kHz along the mirror moving axis, respectively, because the symmetric structure of the H-shaped VOA and high-aspect-ratio silicon beam, along with the out-of-plane perpendicular direction (i.e., the z direction), provide excellent mechanical stability against mechanical vibrations. The H-shaped beam-driven VOA is operated by controlling the displacement of retroreflective mirrors owing to Joule heating. It is

21.0 20.8 20.6 20.4 20.2 20.0 19.8 19.6 19.4 19.2 19.0

0.06

0.01

0.02

0.03

0.04

0.05

0.06

Time, s

x axis @ 2000 Hz

0.000 0.004 0.005 0.006 0.007 0.008 0.009

(d)

Time, s

FIGURE 5-40 Measured attenuation fluctuation at 20 dB of attenuation for a MEMS VOA using a linked pair of V-beam electrothermal actuators under mechanical vibration of 20g along the x axis (i.e., mirror-moving axis) at (a) 100 Hz, (b) 500 Hz, (c) 1 kHz, and (d) 2 kHz.

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1

2

6 7 3 4 5 Diving voltage, dc V

(c)

50 45 40 35 30 25 20 15 10 5 0

8

9

2.5 2 1.5 1 0.5 0 –0.5 –1 –1.5 –2 –2.5 10

50 45 40 35 30 25 20 15 10 5 0

Attenuation at 25.0°C Attenuation at 12.5°C

0

1

6 7 3 4 5 Diving voltage, dc V

2

(b)

Attenuation at 25°C Attenuation at 0°C

0

1

2

3 4 5 6 7 Diving voltage, dc V

8

9

2.5 2 1.5 1 0.5 0 –0.5 –1 –1.5 –2 –2.5 10

8

9

2.5 2 1.5 1 0.5 0 –0.5 –1 –1.5 –2 –2.5 10

Deviation of attenuation value, dB

0

Optical attenuation, dB

(a)

Attenuation at 25°C Attenuation at 75°C

Deviation of attenuation value, dB

50 45 40 35 30 25 20 15 10 5 0

Optical attenuation, dB

Chapter Five Deviation of attenuation value, dB

Optical attenuation, dB

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FIGURE 5-41 Attenuation curves measured at two temperatures and curve of deviation values of these two attenuation curves: (a) 25 versus 75°C; (b) 25 versus 12.5°C; and (c) 25 versus 0°C.

natural to doubt the temperature effect on the repeatability of attenuation characteristics. Thus Lee185 reported curves of attenuation versus applied bias at different temperatures. Figure 5-41a through c shows the temperature-dependent results of attenuation curves at 75, 12.5, and 0°C with respect to room temperature (25°C). The differences in the attenuation curves are 0.5, 0.6, and 1.3 dB for 75, 12.5, and 0°C, respectively. These results are attributed to the fact that the rate of heat dissipation from the actuated and heated H-shaped beam structure to the environment becomes larger owing to larger temperature difference in the case of a 0°C ambient temperature. Thus more driving voltage is required to reach the same attenuation value, where the driving electrical power is proportional to this driving voltage. Thus the attenuation curve measured at 0°C ambient temperature is shifted to right of the high-driving-voltage region. When we discuss the reliability results, we are normally looking into the measured results of packaged VOA devices. If we consider that the overall loss on any occasion is less than 1 dB, we may refer to the typical loss budget as an insertion loss of 0.5 dB, a PDL of 0.2 to 0.3 dB, and a package-related loss of less than 0.2 dB. The insertion loss is mainly attributed to the coupling loss between light and the output port and reflection loss of the MEMS mirror. PDL typically gets higher at larger attenuations (e.g., 30 dB of attenuation). Therefore, the allowable loss budget related to packaging and environment effects is limited to 0.2 dB. Once the device package is completed, proper selection of epoxy or soldering materials is crucial to maintaining the alignment accuracy of optical light path among the MEMS parts and optics.

Optical MEMS Packaging: Communications In other words, good matching of the thermal-expansion coefficients of the various materials among silicon MEMS chip, optics, and housing materials is necessary. In the case of temperature-dependent VOA devices, such as H-shaped electrothermal MEMS VOAs and polymerbased VOAs, we may deploy heat-sink structures to gain better temperature stability.183 A high-temperature, high-humidity (HTHH) aging test is one of the major tests in the Telecordia GR1209 and GR1221 regulations. The test requires storage of devices at 85°C and 85-percent relative humidity for 14 days (GR1209) and for 2500 hours (GR1221), respectively. Hermetic sealing of the housing and the interface of the inlet and outlet optical fibers is definitely necessary. Without properly packaging of MEMS VOA chips in hermetically sealed housing, electrostatic comb actuator–based VOA devices have failed after 100 to 300 hours of HTHH aging. We concluded that stiction of comb structures is the root cause for failure after we did a decap and checked the microstructures. In contrast to electrostatic comb actuator–based VOAs, H-shaped beam–driven VOAs show more robust results in HTHH aging tests. However, repeatable and reliable results are normally achieved when devices are packaged via metal welding and/or soldering. Some packaged-related reliability data for a waveguide-based silica VOA can be found at ref. 183. Owing to the limited availability of published MEMS VOA reliability data, we may refer to the published reliability data on dry thermal aging at 85°C for 5000 hours for MEMS 2D optical switch-array devices.186 Generally speaking, planar MEMS VOAs based on DRIE-derived single-crystal microstructures show the advantages of easy assembly and repeatable manufacturability; whereas 3D MEMS VOAs easily can show low return loss and low PDL with challenges in precise alignment and parts assembly. However, this kind of labor-intensive alignment, assembly, and packaging could be resolved by using precision automation equipment. Technology for enabling low-cost hermetic sealing of packaging for MOEMS mirrors for display applications at the wafer level is quite intriguing from the perspective of MEMS VOA packaging187 because we may perform the hermetic sealing of MEMS elements at the wafer level first. While we can achieve MEMS wafer-level packaging, accomplishment of fiberoptic assembly and interface hermetic sealing at the wafer level is the main challenge and needs to be explored.

5.5.3

Case Study: Optical Switches

Large-scale optical switch packages need to assemble and align hundreds (e.g., 2D switches) to thousands (e.g., 3D switches) of micromirrors, lenses, and fibers with each other with tolerances on the order of microns and hundreds of microradians. The packaged optical switches must endure thermal cycles, shock, and vibration during

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Chapter Five shipping and operation, which may lead to short- and long-term mechanical drift in packaging. Obviously, the tolerances of the various pointing errors and misalignment errors depend on the robustness of the optical architecture design. Additionally, these thousands of optical components must be packaged carefully and compactly with all the necessary control electronics in order to meet the additional space constraints and front-panel accessibility requirements of telecommunications equipment. A hermetically sealed housing normally is required to protect MEMS devices and optics from the outside environment because MEMS devices are sensitive to dust particles and humidity. Humidity can cause a number of failure mechanisms, such as anodic oxidation and condensation of moisture on the MEMS devices and optics. In this section we look into general considerations involved in packaging large-scale optical switches and reliability data. The package is mainly determined by the optical configuration, whereas the MEMS mirrors and actuators are designed to meet the specifications on the selected optics. To explain such design and optimization flow, 3D optical switches and their optical configurations are introduced accordingly. The early reported optical configuration of a packaged 112 × 112 ports of 3D optical switch from Lucent is shown in Fig. 5-42a.188 This 3D optical switch uses a single mirror-array chip that consists of surface-micromachined polysilicon mirrors, as shown in Fig. 5-42b. The reported typical connection switching time is less than 10 ms, including the drive-voltage rise time. Insertion loss of the optical fabric is 7.5 ± 2.5 dB in the minimum-loss region around 1550 nm. Another mainstream design, as shown in Fig. 5-42c, is the Z-configuration 3D optical switch reported in 2001. In the Z-configuration, two mirror-array chips are required to provide the necessary beam-steering function. Systems containing this 3D optical switch of 512 × 512 ports have been commercialized (Fig. 5-42d).189 The main technical concern in 3D optical switches is the coupling losses between the input and output ports. Component fabrication and packaging tolerances need to be estimated first. For example, ±1 percent of focal variation in a single port lens in a lens array could account for up to 1 dB of optical loss. Similarly, ±2 μm of relative position error in a fiber array can lead to losses. The packages also must be designed so that they can accommodate differences in thermal expansion between the different parts inside and reduce the influence of thermal excursions on optical performance. One method to facilitate packaging is to make use of large fiber array (fiber bundles), lens arrays, and monolithically integrated thousands of mirrors in one chip. By doing so, we can reduce the complexity of the system. However, fabrication and packaging of such large fiber bundles, lenslet arrays, and tilt-mirror array chips pose formidable challenges. To explain how these technologies are being implemented, we look into some reported examples of 3D optical switch housing. Figure 5-43a and b shows a

Optical MEMS Packaging: Communications

(a)

(b)

MEMS mirror array Fiber array Lens array

Optical path A single MEMS mirror (c)

(d)

FIGURE 5-42 (a) Simple configuration of a 3D optical switch using a single-mirror array (Microstar switch from Lucent).188 (b) A polysilicon surface-micromachined gimbaled mirror by Lucent.188 (c) A 3D optical switch based on the Z-configuration from Tellium. (Inset) SEM photograph of a tilt mirror.189 (d) Tellium’s Aurora Optical Switch of 512 × 512 ports and 1.28 Tbit/s switching capacity.189

3D optical switch with 100 × 100 ports based on the Z-configuration and its metal housing from NTT.108,109 Inside this metal housing, a switch module containing two mirror-array chips and two fiber-array bundles arranged in a Z-configuration are placed at the center. Photographs of the fiber array and packaged mirror array are shown in Fig. 5-43c and d, respectively. The details of the tilt mirror were illustrated in Fig. 5-13. The measured insertion loss is 4 dB. Lucent reported a 256 × 256 3D optical switch based on the revised Z-configuration with a Fourier lens at the center of the optical path in 2003 (see Fig. 5-43e).190 The housing of the optical-switch module is shown in Fig. 5-43f. This 3D optical switch shows mean and maximum insertion losses of 1.3 and 2.0 dB, respectively. The third example is the one from Fujitsu (see Fig. 5-43g and h). Without using the Z-configuration, it shows a new configuration containing retroreflector optics. The input and output fiber collimators face each other as in a mirror image, enabling size reduction through beam folding and angle reduction in MEMS mirror operations through a “parallel shift” effect. The mirror-array chips,

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Light beam

(a)

(e) Fiber array

Lens array

Mirror array Fourier MEMS lens mirror array

Fiber array

Mirror array (b)

In

Fiber array Lens array Fiber array 56 mm

Mirror array

(d)

Mirror array (h)

MEMS array

Fiber array

Fiber array

Out

72 mm

(f)

(c)

MEMS (g) mirror array Retroreflector

Fiber array

Fourier lens

Flexible print cables

FIGURE 5-43 (a) 3D optical switch based on the Z-configuration from NTT.108,109 (b) Photograph of prototype optical switch module having 100 × 100 ports with a size of 80 × 60 × 35 mm3 located at the center of the metal housing. (c) Photograph of fiber array of 100 ports.108,109 (d) Mirror array chips assembled on a multilayer ceramic substrate. (e) 3D optical switch based on the Z-configuration with a Fourier lens at the center of the optical path from Lucent.190 (f ) Hermetically sealed metal housing of a 256 × 256 port of 3D optical switch from Lucent showing the mirror array, the fiber array, and the Fourier lens mounted inside the housing.190 (g) Schematic drawing of a 3D optical switch from Fujitsu, (h) The optical housing with size of 77 mm × 87 mm × 53 mm.

Optical MEMS Packaging: Communications optics, and fiber bundles are actively aligned and assembled on a metal housing. Information on tilt mirrors is given in Figs. 5-14 and 5-15. The average insertion loss is reported to be 2.6 dB.100 The optical power-loss budget is required by the whole system such that optical communications system can reduce the cost of the transmitters and receivers in the network. Therefore, achieving a low insertion loss is a major task in 3D optical switch development. If the insertion loss is too large, then this may require the addition of amplifiers or regenerators. In order to obtain a low-loss 3D optical switch, it is necessary to have microlenses with very low aberrations, low wave-front errors across entire arrays, and high focal-length uniformity. The microlens array is aligned to ensure minimum double-pass insertion loss and beam registration of better than 50 μm, and then it is attached to the fiber arrays. A microlens array creates collimated beams that then land on the micromirrors, which can redirect the beams. The silicon microlens array is made by a reflow process and has excess losses from 0.1 to 0.3 dB, which is comparable with the best individual collimators available today. By adjusting the angles of the input and output mirrors, any input can be connected to any output. Fabrics built this way are data-rate-independent, can operate over the entire 1.3 to 1.6 μm of optical communications band, have negligible PMD and PDL, and have very low optical losses. Except for insertion loss, PDL is required to be low enough to minimize monitoring and dynamic compensation requirements. Other parameters, such as crosstalk and back-reflection, also have an impact on the signal integrity in the network. In addition to these housing-scale efforts, packaging of optical MEMS mirror arrays with a large footprint (>10 cm2) introduces new complexities that are more challenging than those in packaging of pressure sensors and accelerometers. The challenges of designing such a package are considerable given the simultaneous requirements of getting many electrical leads as well as light into and out of the package. To guarantee long-term operation of the MEMS mirror, the mirror-array chip must be hermetically sealed in a package with an antireflection (AR) material–coated optically clear window. Rigorous thermal management of MEMS die packages may be required because the mirror radius of curvature (ROC) can be a strong function of temperature. Signal routing and inputs/outputs (I/Os) to the die are also paramount considerations. Given the large number of die I/Os (1000 or more), a large die package with matching bonding pads and output pins is required. Figure 5-43d shows a mirror array hermetically packaged on a multilayer ceramic substrates for NTT’s 100 × 100 3D optical switch. The hermetic sealing is done using AuSn solder. True hermetic seals (preventing permeation of humidity) can be obtained only with perfect metallic seals. The latest land-grid array (LGA) and ball-grid array (BGA) with 0.5 to 1 mm of pitch can contribute to a 3D optical switch as an interconnect substrate to meet the signal-density

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Chapter Five requirements. Furthermore, Fig. 5-44a shows a conceptual schematic drawing of a packaged mirror-array chip based on multichip directmounting (MCDM) technology.191 First, Au bumps are formed on the Au pads of the chip-mounting area of the ceramic package. To provide redundancy as backup channels, eight chips of a 79-channel mirror array are mounted onto a ceramic package using MCDM technology to create a 512-mirror array module (see Fig. 5-44b). These bumps are subjected to a leveling process. Uniform pressure is applied to the bumps to make them level with each other. The warp of the package surface can be absorbed during the leveling process. Based on reported data, a warp not to exceed 40 μm can be absorbed during the bump-leveling process. Bump height is 70 μm after the leveling process, which provides space under the comb teeth for the two-axis tilt motion of the mirrors. The separately prepared 79-channel mirrorarray chips are aligned with the package and mounted onto the bumps. Finally, BGA connectors are mounted on the rear of the package, and the package is hermetically sealed with an AR window. The 512-mirror-array module constructed by the newly developed MCDM technology is shown in Fig. 5-44c. During operation, the MEMS mirrors also may experience stochastic perturbation from the environment, including vibration from equipment cooling fans, heavy truck deliveries, door slams, and earthquakes. Therefore, a closed-loop feedback control system is designed to guarantee timely and reliable port connections by the MEMS mirrors. Most important, a tilt mirror under a feedback servo can be immune to random external shock and vibration. Nevertheless, a 3D optical switch with closed-loop-controlled MEMS mirrors requires the development of a servo-control algorithm, the incorporation of sensing mechanisms for computing the proper control feedback signal, and the implementation of control electronics that offer sufficient computing power to control 1000 or more mirrors within the power and space budget of the switching device. Another practice that is worth looking into is the packaging of a 16 × 16 2D optical switch by OMM.86,192 Figure 5-45a shows the metal housing of the final finished product, and Fig. 5-45b and c provides a schematic drawing and a SEM photograph of the surfacemicromachined polysilicon vertical mirrors, respectively. As we explained in previous paragraphs, insertion loss and PDL are the two key parameters of optical switches and VOAs. Additionally, switch time and repeatability are parameters of specific interests for optical switches. Switch time is defined as the time period between the bias voltage that is applied to the switch and the moment the insertion loss of the switched path reaches more than 90 percent of its final value. Repeatability is defined as the difference between the maximum and minimum insertion loss of a path when the corresponding mirror goes through many consecutive switch cycles. Figure 5-45e to h shows the derived histogram data of 16 × 16 2D optical switches. The maximum

Optical MEMS Packaging: Communications Directly mounted small-scale mirror arrays Micromirror

Comb teeth

Au-resin bump Ceramic package

(a)

Solder-bump

BGA- connector

AR window

79-channel mirror chip

50 mm (b)

10 mm (c)

FIGURE 5-44 (a) Conceptual drawing of a hermetically sealed mirror-array package from Fujitsu. (b) A 512-mirror module constructed with the newly developed multichip-direct mounting (MCDM) technology. (c) Close-up of two mirror-array chips of 79 channels individually.191

insertion loss is measured as 3.1 dB, whereas most of the channels demonstrate insertion loss of less than 2 dB. The PDL is mainly less than 0.35 dB. Optical crosstalk and back-reflection are less than −50 dB. The repeatability is less than 0.1 dB. The typical switch time is about 7 to 8 ms.

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Chapter Five

(a) Up position

Mirror Actuator

Down position

(c)

(b)

80 70 60 50 40 30 20 10 0

Polarization dependent loss 80 Frequency

Frequency

(d) Insertion loss 16 × 16

20

200

(f)

Frequency

Frequency

40

0

0 0.5 1 1.5 2 2.5 3 3.5 4 (e) Insertion loss, dB Repeatability 16 × 16 250

150 100 50 0 0

(g)

60

0.1

0.2

0.3

0.4

Repeatability, dB

160 140 120 100 80 60 40 20 0

0.5 More

(h)

0

0.1

0.2 0.3 0.4 PDL, dB

0.5 More

Switch time 16 × 16

0 1 2 3 4 5 6 7 8 9 10 11 12 More Switch time, ms

FIGURE 5-45 (a) Hermetic metal housing of a 16 × 16 2D optical switch from OMM. (b) Drawing of the actuation mechanism for the vertical mirror. (c) SEM photograph of a MEMS chip with 256 vertical mirrors. (Inset) Drawing of actuation mechanism for the vertical mirror. (d) Image of the 16 × 16 2D optical switch in the metal housing. (e) Histograms of insertion loss over all 256 paths. (f ) Histograms of PDL over all 256 paths. (g) Histograms of repeatability over all 256 paths. (h) Histograms of switch time over all 256 paths.86,192

Optical MEMS Packaging: Communications Again, the key optical performance parameter of an optical switch is insertion loss. The most important optical-loss mechanisms for the 2D optical switch mirror array are • Path-length-dependent loss • Loss owing to angular mirror or collimator misalignment • Loss owing to clipping of light at the mirror boundaries The path lengths for beams propagating from input collimator to output collimator vary depending on which connection is established. This path-length variation leads to insertion loss because axial misalignment (i.e., longitudinal distance deviation) of Gaussian beams and is a function of the beam waist radius and the layout of the 2D switch chip; that is, for a 16 × 16 2D optical switch with a 1 mm2 area, the maximum path-length difference is 30 mm. An array of vertical mirrors may show a discrepancy in mirror angle of ±0.1 degree owing to manufacturing imperfections. This factor causes angular misalignment of the reflected beams. These losses attributed to angular misalignment of Gaussian beams are proportional to the squares of both the beam waist radius and the angular nonuniformity. The sum of both axial and angular misalignment losses can be minimized by selecting the optimal beam waist radius for the collimated beam for a given beam-angle nonuniformity. In order to avoid clipping losses, a mirror size needs to be selected with respect to this optimal beam waist size. Not only are the collimators designed with tightly specified optical beam parameters, but they also must meet other optical requirements such as low back-reflection, low polarization-dependent loss, and low wavelength-dependent loss as well. Static reliability of a 16 × 16 2D optical switch concerns the ability of the switch to alter states after it has remained for a longer time in the same state (e.g., a situation that may occur in optical protection switching). Because of the electrostatic actuation mechanism, the associated failure mode of this 16 × 16 2D optical switch is reported to be stiction mainly. On the other hand, the dynamic reliability (i.e., durability) of this 2D optical switch refers the ability of the switch to perform many switch cycles without wearout or degradation. Both static reliability and dynamic reliability depend strongly on detailed design of MEMS structures. In the case of electrostatic surface-micromachined polysilicon structures, failure during static operation (i.e., stiction) may occur because of the buildup of a parasitic adhesion force that prevents movement of the actuator. Several mechanisms may cause an adhesion force, including contamination, humidity, van der Waals forces, welding, and mechanical friction of parts. In this 16 × 16 2D optical MEMS switch, stiction can be eliminated by keeping the contact area to an absolute minimum (see Fig. 5-45b), ensuring strict process cleanliness during manufacturing, and using a hermetically

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Chapter Five Endurance tests Damp heat Thermal cycling Thermal aging Durability Low-temperature storage Thermal shock Robustness tests Fiber retention Fiber flex test Fiber twist test Mechanical shock Mechanical vibration Electrostatic discharge (a)

+75°C/90% RH, 1500 hours –40°C/+85°C, 100 cydes +85°C, 2000 hours 1,000,000 cydes –40°C, 2000 hours 0°C/100°C, 20 cydes 19.2 N,10 S, 3 cydes 4.8 N, 100 flex cydes 4.8 N,10 twist cydes 200g, 1.3 ms, 5 shocks per direction: ±x, +/y, ±z 10 to 55 Hz, amplitude 1.52 mm, 2 hours 500 V, human body model

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FIGURE 5-46 (a) Reliability test items and relevant conditions of 16 × 16 2D optical switches from OMM. (b) Reliability test results of damp heat exposure (11 devices, 1500 hours at +75°C and 90-percent relative humidity). (c) Reliability test results of durability (11 devices, up to 1 million switch cycles).192

Optical MEMS Packaging: Communications sealed housing. Static reliability of a 16 × 16 2D optical switch based on such an improved design has been verified for more than a year on over 4000 switch elements. No failures have been observed when the devices were altered in state; this leads to a verified estimate of less than 37 FIT (1 FIT = 1 failure over 1 billion operating hours) for the random failure rate of the switching element.192 One million failurefree switch cycles are often required for dynamic reliability (equivalent to cycling every 10 minutes over a period of 20 years). Elimination of mechanical contact during movement solved this problem; excellent performance in excess of 10 million cycles has been verified for this 16 × 16 optical switches. Following the Telcordia generic requirements,193 the test conditions and some of the test results are shown in Fig. 5-46. These reliability test results confirm that this 16 × 16 2D optical switch meets telecommunications requirements, and these results demonstrate the robustness of MEMS optical switches under operation, storage, and transport conditions.

5.6

Summary and Future Outlook Over the last few years, an amazing amount of interest has emerged for applications of optical MEMS devices in telecommunications. Various kinds of integrated micromachining processes have been developed for making optical MEMS devices. Actuation mechanisms are designed and optimized by considering the tradeoffs among processes, optics, displacement, and force output. Among the well-studied actuation schemes, such as electrostatic, thermal (electrothermal), magnetic (electromagnetic), and piezoelectric, the most popular actuator is electrostatic. Silicon-based materials and processes can be widely accessed (there are even a few foundry services), and various electrostatic actuators (e.g., parallel-plate actuators and comb actuators) are easily prepared in this way. As a result, optical MEMS devices have proven to be the technology of choice for low-cost and scalable photonic applications because they allow mass production of highly accurate miniaturized parts and use materials with excellent mechanical and electrical properties. Based on an in-depth study and literature survey of optical switch and VOA technologies, we discuss design considerations and guidelines, manufacturability, performance, packaging, and reliability of these optical MEMS devices. A number of common potential failure mechanisms from the point of view of reliability can be identified: mechanical wear, mechanical stress, dielectric breakdown, anodic oxidation, material migration, stress relaxation, contamination, and particles. According to the reported data, most of these failures can be avoided by proper design of the MEMS structure, packaging, or housing, whereas others, such as contamination and particles, can be solved by using better-controlled processes and manufacturing environment.

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Chapter Five Optical MEMS devices that handle optical signals with protocol transparency and are independent of data rate and wavelength are indispensable to the practical implementation of optical networks. MEMS technology offers the tantalizing possibility of advanced components for optical communication applications. It offers unique manufacturable, scalable, reliable, and low-cost solutions to industry. The next generation optical networks will benefit from the fast growing MEMS technology.

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wavelength applications in recent photonic networks.” IEEE J. Select. Topics Quantum Electron. 11:383–394, 2005. Kudrle, T. D., Wang, C. C., Bancu, M. G., Hsiao, J. C., Pareek, A., Waelti, M., Kirkos, G. A., Shone, T., Fung, C. D., and Mastrangelo, C. H. “Single-crystal silicon micromirror array with polysilicon flexures.” Sensors Actuators A 119: 559–566, 2005. Kim, J., Nuzman, C. J., Kumar, B., Lieuwen, D. F., Kraus, J. S., Weiss, A., Lichtenwalner, C. P., Papazian, A. R., Frahm, R. E., Basavanhally, N. R., Ramsey, D. A., Aksyuk, V. A., Pardo, F., Simon, M. E., Lifton, V., Chan, H. B., Haueis, M., Gasparyan, A., Shea, H. R., Arney, S., Bolle, C. A., Kolodner, P. R., Ryf, R., Neilson, D. T., and Gates, J. V. “1100 × 1100 port MEMS-based optical crossconnect with 4-dB maximum loss.” IEEE Photon. Technol. Lett. 15:1537–1539, 2003. Kozhevnikov, M., Basavanhally, N. R., Weld, J. D., Low, Y. L., Kolodner, P., Bolle, C. A., Ryf, R., Papazian, A. R., Olkhovets, A., Pardo, F., Kim, J., Neilson, D. T., Aksyuk, V. A., and Gates, J. V. “Compact 64 × 64 micromechanical optical cross connect.” IEEE Photon. Technol. Lett. 15:993–995, 2003. Taylor, W. P., Brazzle, J. D., Osenar, A. B., Corcoran, C. J., Jafri, I. H., Keating, D., Kirkos, G., Lockwood, M., Pareek, A., and Bernstein, J. J. “A high fill factor linear mirror array for a wavelength selective switch.” J. Micromech. Microeng. 14:147–152, 2004. Xiao, Z., Peng, W., Wu, X., and Farmer, K. R. “Pull-in study for round doublegimbaled electrostatic torsion actuators.” J. Micromech. Microeng. 12:77–81, 2002. Dadap, J. I., Chu, P. B., Brener, I., Pu, C.,Lee, C. D., Bergman, K., Bonadeo, N., Chau, T., Chou, M., Doran, R., Gibson, R., Harel, R.,Johnson, J. J., Lee, S. S., Park, S., Peale, D. R., Rodriguez, R., Tong, D., Tsai, M., Wu, C., Zhong, W., Goldstein, E., Lin, L., and Walker, J. A. “Modular MEMS-based optical cross-connect with large port count.” IEEE Photon. Technol. Lett. 15:1773–1775, 2003. Sawada, R., Higurashi, E., Shimizu, A., and Tohru Maruno, T. “Single crystalline mirror actuated electrostatically by terraced electrodes with high-aspect ratio torsion spring.” In Proceedings of Optical MEMS 2001, Okinawa, Japan, Sept. 25–28, 2001, pp. 23–24. Yamamoto, T., Yamaguchi, J., Takeuchi, N., Shimizu, A., Higurashi, E., Sawada, R., and Uenishi, Y. “A three-dimensional MEMS optical switching module having 100 input and 100 output ports.” IEEE Photon. Technol. Lett. 15:1360–1362, 2003. Yamamoto, T., Yamaguchi, J., Takeuchi, N., Shimizu, A., Sawada, R., Higurashi, E., and Uenishi, Y. “A three-dimensional micro-electro-mechanical system (MEMS) optical switch module using low-cost highly accurate polymer components.” Jpn. J. Appl. Phys. 43:5824–5827, 2004. Conant, R. A., Nee, J. T., Lau, K. Y., and Muller, R. S. “A flat high-frequency scanning micromirror.” In Proceedings of the Technical Digest Solid-State Sensor and Actuator Workshop, Cleveland, OH, 2000, pp. 6–9. Tsuboi, O., Mizuno, Y., Koma, N., Soneda, H., Okuda, H., Ueda, S., Sawaki, I., and Yamagishi, F. “A rotational comb-driven micromirror with a large deflection angleand low drive voltage.” In Proceedings of the IEEE International Conference on MEMS, Lugano, Switzerland, Aug. 20–23, 2002, pp. 532–535. Mi, X., Soneda, H., Okuda, H., Tsuboi, O., Kouma, N., Mizuno, Y., Ueda, S., and Sawaki, I. “A multi-chip directly mounted 512-MEMS-mirror array module with a hermetically sealed package for large optical cross-connects.” J. Opt. A: Pure Appl. Opt. 8:S341–S346, 2006. Wu, M. C., Solgaard, O., and Ford, J. E. “Optical MEMS for lightwave communication.” J. Lightwave Technol. 24:4433–4454, 2006. Piyawattanametha, W., Patterson, P. R., Hah, D., Toshiyoshi, H., and Wu, M. C. “Surface- and bulk-micromachined two-dimensional scanner driven by angular vertical comb actuators.” J. Microelectromech. Syst. 14:1329–1338, 2005.

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Optical MEMS Packaging: Communications 179. Lee, C. “Arrayed variable optical attenuator using retro-reflective MEMS mirrors.” IEEE Photon. Technol. Lett. 17:2640–2642, 2005. 180. Lee, C., Lai, Y.-J., Wu, C.-Y., Lin, Y.-S., Tsai, M. H., Huang, R.-S., and Lin, M.-S. “Scratch drive actuator driven self-assembled variable optical attenuator.” Jpn. J. Appl. Phys. 43:3906–3909, 2004. 181. Lee, C., Lai, Y.-J., Wu, C.-Y., Yeh, J. A., and Huang, R.-S. “Feasibility study of self-assembly mechanism for variable optical attenuator.” J. Micromech. Microeng. 15:55–62, 2005. 182. Lijie, J., Zawadzka, J., and Uttamchandani, D. “Integrated self-assembling and holding technique applied to a 3D MEMS variable optical attenuator.” IEEE J. MEMS, 13:83–90, 2004. 183. Ogawa, J., Doi, Y. Hashizume, Y., Kamei, S., Tamura, Y., Ishii, M., Kominato, T., Yamazaki, H., and Kaneko, A. “Packaging technology for ultra-small variable optical attenuator multiplexer (V-AWG) with multichip PLC integration structure using chip-scale-package PD array.” IEEE J. Select. Topics Quantum Electron. 12:1045–1053, 2006. 184. Wu, G., Mirza, A. R., Gamage, S. K., Ukrainczyk, L., Shashidhar, N., Wruck, G., and Ruda, M. “Design and use of compact lensed fibers for low cost packaging of optical MEMS components.” J. Micromech. Microeng. 14:1367–1375, 2004. 185. Lee, C. “A MEMS VOA using electrothermal actuators.” J. Lightwave Technol. 25:490–498, 2007. 186. De Dobbelaere, P., Falta, K., and Gloeckner, S. “Advances in integrated 2D MEMS-based solutions for optical network applications.” IEEE Commun. Mag. 41:S16–S23, 2003. 187. van Heeren, H., EI-Fatatry, A., Paschalidou, L., and Salomon, P. “Industrial packaging and assembly infrastructure for MOEMS.” J. Microlith. Microfab. Microsyst. 4:041701, 2005. 188. Neilson, D. T., Aksyuk, V. A., Arney, S., Basavanhally, N. R., Bhalla, K. S., Bishop, D. J., Boie, B. A., Bolle, C. A., Gates, J. V., Gottlieb, A. M., Hickey, J. P., Jackman, N. A., Kolodner, P. R., Korotky, S. K., Mikkelsen, B., Pardo, F., Raybon, G., Ruel, R., Scotti, R. E.’Van Blarcum, T. W., Zhang, L., and Giles, C. R. “Fully provisioned 112 × 112 micromechaincal optical cross-connect with 35.8 Tb/s demonstrated capacity.” In Proceedings of the Optical Fiber Communication Conference, Baltimore, MD, 2000, Vol. 12-1, p. 202. 189. Chu, P. B., Lee, S.-S., Park, S., Tsai, M.-J., Brener, I., Peale, D., R. A. Doran, D. R. A., and Pu, C. “MOEMS: enabling technologies for large optical crossconnects.” Proc. SPIE 4561:55–65, 2001. 190. Neilson, D. T., Frahm, R., Kolodner, P., Bolle, C. A., Ryf, R., Kim, J., Papazian, A. R., Nuzman, C. J., Gasparyan, A., Basavanhally, N. R., Aksyuk, V. A., and Gates, J. V. “256 × 256 port optical cross-connect subsystem.” J. Lightwave Technol. 22:1499–1509, 2004. 191. Mi, X., Soneda, H., Okuda, H., Tsuboi, O., Kouma, N., Mizuno, Y., Ueda, S., and Sawaki, J. V. “A multi-chip directly mounted 512-MEMS-mirror array module with a hermetically sealed package for large optical cross-connects.” J. Opt. A: Pure Appl. Opt. 8:S341–S346, 2006. 192. De Dobbelaere, P., Falta, K., Fan, L., Gloeckner, S., and Patra, S. “Digital MEMS for optical switching.” IEEE Commun. Mag. 40, 88–95, 2002. 193. Telcordia, “Generic Requirements for Single mode Fiber Optic Switches,” GR-1073-CORE, issue 1, Jan. 2001.

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CHAPTER

6

Optical MEMS Packaging: Bubble Switch 6.1 Introduction This chapter discusses the packaging and thermal reliability of the solder sealing ring of Restriction of the Use of Certain Hazardous Substances (RoHS) Directive–compliant three-dimensional (3D) bubbleactuated photonic cross-connect switches.1–10 Emphasis is placed on determination of the thermal fatigue life of the lead-free solder sealing ring under shipping, storing, and handling conditions.

6.2 3D Packaging The fundamental principles, design concepts, and engineering developments of the Agilent photonic switching platform have been reported in refs. 1 through 9. Figure 6-1 shows the fully assembled (fiber-attached) 32 × 32 all-optical device. Basically, Agilent Technologies’ approach to photonic cross-connect switching consists of a fused-silica planar lightwave circuit (PLC) chip and a silicon matrix controller chip (MCC). The silica chip contains intersecting arrays of rectangular waveguides with trenches etched into each crosspoint. The silicon chip consists of a matrix of matching patterns of electrically addressable resistive heating elements, each aligned to a waveguide crossing. These two chips are hermetically sealed together in 3D with a lead-free solder ring, as shown in Fig. 6-2. In the default state, the trenches, along with the rest of the sealed space between the silica and silicon chips, are filled with a liquid whose refractive index matches that of the waveguides and whose properties are suitable for bubble creation and control. Thermoelectric coolers (TECs) are used to control the liquid temperature to ensure accurate index matching. An external temperature-controlled liquid

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Chapter Six

FIGURE 6-1

Fully assembled (fiber-attached) 32 × 32 all-optical device.

Transparent planar lightwave circuit (PLC) chip on top Lead-free sealing ring

PLC

Resistors

Si

Silicon-based actuator chip with resistors on bottom

FIGURE 6-2 PLC chip stacked on a silicon chip with a sealing ring on Mo substrate bolted on an Al cooling plate.

Optical MEMS Packaging: Bubble Switch

No switching

Light

Light

Resistor on Si is not fired

(Not to scale) Trench on PLC to form bubble

Resistor on Si is fired PLC (SiO2) with waveguides

Resistor

Si substrate

Switching achieved Lead-free solder ring

Filled liquid with the same refractive index matches the PLC

FIGURE 6-3 When the resistor on the silicon chip is not fired, there is no switching. However, when the resistor on the silicon chip is fired, then switching is achieved.

reservoir regulates the liquid pressure inside the sealed lead-free solder ring. Optical signals passing along any guide on the silica chip simply pass on through. However, by activating a resistive element on the silicon chip, a bubble can be created at that crosspoint so that total internal reflection occurs at the sidewall of the corresponding trench, and switching is achieved,1–10 as shown in Figs. 6-3 and 6-4. Figure 6-4 shows a schematic of the structure of a single crosspoint (bubbleswitch element). When no bubble is present, signals in the form of guided lightwaves can transverse the trench from IN to DROP and ADD to OUT with little loss. However, once the electrically controlled resistive center heater generates a vapor bubble, total internal reflection is made possible at the vapor-silica interface of the trench sidewalls (i.e., IN to OUT and ADD to DROP). The sidewall metalizations drawn in Fig. 6-4 are optional. The key packaging elements of the photonic switch consist of the silica chip, 48 wt % Sn–52 wt % In solder sealing ring, silicon chip, 100 wt % In solder die attachment, and molybdenum substrate. This 3D stack of elements is bolted down onto a very large and thick aluminum cooling plate. Because of the very large thermal-expansion mismatch among the silica chip (0.5 × 10–6/°C), Sn-In solder (28 × 10–6/°C), silicon chip (2.5 × 10–6/°C), In solder (32.1 × 10–6/°C), molybdenum substrate (4.8 × 10–6/°C), and aluminum plate (23.2 × 10–6/°C), as shown in Table 6-1, the whole structure is subjected to a very complicated state of stresses and strains when it is under shipping, storing, and handling conditions.

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Chapter Six ADD signal

IN signal Fluid Trench

Center heater Optical waveguide Sidewall metalization

Bubble DROP signal

OUT signal

FIGURE 6-4 Top view of bubble-switch elements.

From a packaging point of view, the lead-free solder sealing ring is the most critical structural element. It not only connects the MCC and PLC chips together but also confines the liquid that fills the trenches and the gap between the MCC and PLC chips. Thus the reliability of the lead-free solder sealing ring bears great scrutiny. The objective of this investigation is to determine the thermal fatigue life of the solder sealing ring of the photonic switch under shipping, storing, and handling conditions. The 48 wt % Sn–52 wt % In and 100 wt % In solders are assumed to obey the Garofalo-Arrhenius creep constitutive law. Creep responses, such as creep strain energy density per cycle, are determined by a nonlinear time- and temperature-dependent finite-element method. In order to determine the thermal fatigue life of the solder sealing ring of the photonic switch, a relationship between the number of cycles-to-failure Nf and the strain energy density per cycle is needed. Thus isothermal fatigue tests of the solder sealing ring are performed. In order to increase the confidence of the finite-element analysis, material properties, and boundary conditions, some of the simulation results are compared with experimental results. Thus the thermalcycling deflections of the module are measured by the TwymanGreen interferometry method.

Material Molybdenum (Mb) Silicon (Si)

Coefficient of Thermal Yield Tensile Thermal Young’s Specific Modulus Poisson’s Expansion Strength Strength Elongation Conductivity Density Heat (ppm/°C) (MPa) (MPa) (%) (W/m ◊ K) (g/cm3) (cal/g ◊ K) Creep (GPa) Ratio 355a

0.3g

4.8a

552a

655a

a

a

a

a

a

163.3

0.28

34.5

185

—

b

7.3

—

Yes j

—

82d

7.3d

—

Yese

—

0.33c

2.2c

—

No

237c

2.7g

—

11i

0.45i

32.1f

—

—

Silica fused quartz (SiO2)

72.4c

0.14c

0.5c

66.9c

75.9c

Aluminum 6061-T6

70.3c

0.35g

23.2c

10.3g

45g

165.43

2.4

Lau, J., and Pao, Y.-H. Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine-Pitch SMT Assemblies. New York: McGraw-Hill, 1997. Harper, C. A. Electronic Packaging and Interconnection Handbook. New York: McGraw-Hill, 2000. c King, J. A. Materials Handbook for Microelectronics. Los Angeles, CA, Teledyne Microelectronics, 1998. d www.webelements.com, 2001. e Lau, J. Ball Grid Array Technology. New York: McGraw-Hill, 1995. f Lau, J., and Lee, R. Microvias for Low Cost and High Density Interconnects. New York: McGraw-Hill, 2001. g Mark’s Standard Handbook for Mechanical Engineers, 8th ed. New York: McGraw-Hill, 1978. h Average of Sn and In from note d. i Indium Corporation of America, Technical Bulletin of Pure Indium, 2001. j Mei, Z., and Morris, J. W. “Superplastic creep of low melting point solder joints.” J. Electron. Mater. 21:401–401, 1991. k Hwang, J. Solder Paste in Electronics Packaging. New York: Van Nostrandn Reinhold, 1989. b

301

TABLE 6-1 Material Properties of the Optical Package

No

—

—

a

a

0.06g

No

—

12g

10.24g

0.169

28

100In

139a

k

0.36

30.5

h

2.5

a

48Sn-52In

h

2.5c

0.211g

No

302

Chapter Six

6.3 Boundary-Value Problem The boundary-value problem of the photonic switch is defined by its geometry, materials, and loading (boundary) conditions.10

6.3.1 Geometry The geometry of the photonic switch is shown in Figs. 6-2, 6-5, and 6-6. It can be seen that (1) the silica chip is attached on top of the silicon chip with a solder sealing ring, (2) the solder sealing ring is made of 48 wt % Sn–52 wt % In solder, (3) the silicon chip is attached on top of the molybdenum substrate, (4) the die-attached material is 100 wt % In solder, (5) the molybdenum substrate is bolted onto a very large and thick aluminum cooling plate, and (6) the cooling plate is bolted on an FR-4 printed circuit board.

6.3.2 Materials Material properties such as the Young’s modulus, Poisson’s ratio, coefficient of thermal expansion, yield strength, and tensile strength of the molybdenum substrate, silicon chip, silica chip, aluminum cool plate,

ng oli co te l A pla

Sealing ring

C5

C3 50

10 2

C6

C

C4

78

26 25

Molybdenum substrate

PCB

FIGURE 6-5 The whole optical bubble switch [microelectromechanical systems (MEMS)] packaging.

R1

Optical MEMS Packaging: Bubble Switch

Silica chip

Bolt

Solder sealing ring

Silicon chip

Aluminum cooling plate

Molybdenum substrate

FIGURE 6-6

Finite-element model for one-quarter of the photonic package.

100 wt % In solder, and 48 wt % Sn–52 wt % In solder of the photonic switch are listed in Table 6-1. All the materials are considered to be linearly elastic except the solders, whose properties are considered to be time- and temperature-dependent (i.e., they undergo creep). The Garofalo-Arrhenius constitutive equation,11 as shown below, has been used frequently to model the creep behavior of solders:12 n

⎡ ⎛ Q⎞ ⎛ τ ⎞⎤ dγ = A ⎢sinh ⎜ ⎟ ⎥ exp ⎜ − ⎟ dt B ⎝ ⎠⎦ ⎝ kT ⎠ ⎣ where

(6-1)

γ = creep shear strain dγ/dt = creep shear-strain rate t = time A = temperature-dependent material constant B = temperature-dependent shear modulus T = absolute temperature (K) τ = shear stress n = stress exponent Q = activation energy for a specific diffusion mechanism (e.g., dislocation diffusion, solute diffusion, lattice selfdiffusion, and grain boundary diffusion) k = Boltzmann’s constant (8.617 × 10–5 eV/K)

303

304

Chapter Six For the 100 wt % In solder, we have13 A = 70, 400(593 − T )/T B = 158 − 0 . 27T n= 5 Q = 0 . 72

If the solder obeys the von Mises criterion,14 then Eq. (6-1) can be written as ⎛ C ⎞ dε = C1[sinh(C2 σ )]C3 exp ⎜ − 4 ⎟ dt ⎝ T⎠

(6-2)

where13 C1 = 40, 647(593 − T )/T C2 = 1/(274 − 0 . 47 T ) C3 = 5 C4 = 83 5 6

It should be pointed out that Eq. (6-2) is exactly the same form of material input as for the implicit creep model (TBOPT = 8) of ANSYS.15 In Eq. (6-2), σ is the uniaxial stress, and dε/dt is the uniaxial creep strain rate. The unit for σ and τ is in pounds per square inch (lb/in2 or psi). The creep behavior of 48 wt % Sn–52 wt % In solder has been determined experimentally in ref. 16 by the double shear specimens method.17 Each specimen contains 18 solder joints with dimensions of 1.27 × 2.03 × 0.18 mm sandwiched between three plates of fiberglassreinforced printed circuit board. The solder joints are formed by reflowing the solder paste in a furnace with a controlled temperature profile for 5 minutes at 110°C, followed by 3 minutes at 150°C. A creep rate at a certain shear stress and temperature is measured by submerging a specimen in a temperature-controlled oil bath, applying dead weight to stress, and measuring the shear displacement. The creep rates are measured at more than five stress levels at each of the three temperatures (20, 65, and 90°C) shown in Fig. 6-7. It can be seen that the strain rate of the solder is very sensitive to temperature; the higher the temperature, the higher is the strain rate. After curvefitting the 48 wt % Sn–52 wt % In data into Eqs. (6-1) and (6-2), then we have A = 4 . 392 × 1011(593 − T )/T B = 2964 . 6 − 4 . 9993T

Optical MEMS Packaging: Bubble Switch

Steady-state shear strain rate, 1/s

1.E-02 90°C 65°C 20°C fitted, 90°C fitted, 65°C fitted, 20°C

1.E-03

1.E-04

1.E-05

1.E-06

1.E-07

10

100

1000

10000

Shear stress, psi

FIGURE 6-7

Creep strain rate versus stress of 48 wt% Sn–52 wt% In solder.

Q/k = 9, 704 . 9 n = 3 . 1103

and C1 = 2 . 5357 × 1011(593 − T )/T C2 = 1/(5234 . 84 − 8 . 648T ) C3 = 3 . 1103 C4 = 9704 . 9

6.3.3 Boundary Conditions According to Bellcore’s specific reliability and quality criteria, all photonic products have to be subjected to the thermal cycling test (–40 to +70°C) to simulate the shipping, storing, and handling conditions. In this study, the temperature profile shown in Fig. 6-8 will be used as the input for the nonlinear temperature-dependent time-history analysis of the switch. It can be seen that for each cycle (60 minutes), the temperature is between –40 and +85°C, with 15 minutes of ramp-up another 15 minutes of ramp-down, 15 minutes of hold at hot, and 15 minutes of hold at cold. Five full cycles are executed.

305

306

Chapter Six 100 80

Temperature, °C

60 40 20 0 –20 –40 –60

0

3600

7200

10800

14400

18000

Time, s

FIGURE 6-8

6.4

Temperature cycling condition.

Nonlinear Analyses of the 3D Photonic Switch Owing to its double symmetry, only one-quarter of the switch is modeled, as shown in Fig. 6-6. It is a 3D model with many 20-node elements, each node with 3 degrees of freedom. The commercial finite-element code ANSYS is used to perform the time-history nonlinear analysis. Some important results are summarized in the following sections.

6.4.1

Creep Hysteresis Loops

Shear stress, MPa

For creep analysis, it is important to study the responses for multiple cycles until the hysteresis loops become stabilized. Figure 6-9 shows the shear stress and shear creep strain hysteresis loops for multiple

18 16 14 12 10 8 6 4 2 0 –2 –4 –0.08

FIGURE 6-9

–0.07

–0.06

–0.05 –0.04 –0.03 Shear creep strain

–0.02

–0.01

Creep hysteresis loops (shear stress versus shear creep strain).

0.00

Optical MEMS Packaging: Bubble Switch cycles at the sealing solder ring. It can be seen that (1) the creep shear strain is quite stable after the third cycle, (2) the creep responses converge in the fourth thermal cycle, (3) the stress range (see Fig. 6-9) in the solder ring is 17.5 MPa, and (4) the shear creep strain range in the sealing ring is 0.043.

6.4.2 Deflections Owing to the thermal-expansion mismatch among the silica chip, solder sealing ring, silicon chip, die attachment, molybdenum substrate, and aluminum cooling plate, the photonic switch is subjected to a very complicated state of stresses and strains when it is subjected to thermal loading. Figure 6-10 shows the time-history maximum (center) deflection of the silica and silicon chips. It can be seen that (1) they are in phase with the applied temperature profile, (2) the maximum deflection of the silicon chip is (∼2 μm) larger than that of the silica chip, and (3) the gap between the silica chip and the silicon chip is not closed because the original gap between these two chips was 5 μm.

6.4.3 Shear-Stress Time-History The shear-stress history at the solder sealing ring of the photonic switch is shown in Fig. 6-11. It can be seen that: (1) the shear stress is not in-phase of the temperature, (2) the shear stress decreases as the temperature increases, (3) the shear stress increases as the temperature decreases, and (4) the shear stress range is about 17.5 MPa when the creep is stabilized, which is acceptable.

6.4.4 Shear-Creep-Strain Time-History The shear-strain history at the solder sealing ring of the photonic switch is shown in Fig. 6-12. It can be seen that (1) the creep strain is 10

Displacement, micron

8 6 4 2 0 –2 SiO2 Si

–4 –6 0

3600

7200

10800

14400

18000

Time, s

FIGURE 6-10 Time-history deflection of the silica and silicon chips at the package center.

307

Chapter Six 18 16 14 12 10 8 6 4 2 0 –2 –4

100 80 60 40 20 0

Temperature, °C

Shear stress, MPa

308

–20 –40 0

3600

7200

10800

14400

–60 18000

Time, s

FIGURE 6-11

Time-history stress in the solder sealing ring.

0.00 –0.01 Shear strain

–0.02 –0.03 –0.04 –0.05 –0.06 –0.07 –0.08

0

3600

7200

10800

14400

18000

Time, s

FIGURE 6-12

Time-history creep strain in the solder sealing ring.

stabilized in the third thermal cycle, and (2) the shear-creep-strain range at the solder sealing ring in the third thermal cycle is 4.2%, which is acceptable.

6.4.5

Creep-Strain Energy-Density Range

The creep-strain energy-density history at the solder sealing ring is shown in Fig. 6-13. It can be seen that it is a monotonically increasing curve. The creep-strain energy-density range (or creep-strain energy density per unit cycle), approximately 0.5 MPa, can be determined from this curve by taking the difference between the creep-strain energy density at 14,400 seconds and at 10,800 seconds. This value also can be determined from the area of the fourth shear stress and shear creep strain hysteresis loop, as shown in Fig. 6-9.

Optical MEMS Packaging: Bubble Switch

Creep shear strain energy density, MPa

2.5

2.0

1.5

1.0

0.5

0.0

0

3600

7200

10800

14400

18000

Time, s

FIGURE 6-13

6.5

Time-history creep-strain energy density in the solder sealing ring.

Isothermal Fatigue Tests and Results As mentioned earlier, in order to predict the thermal fatigue life of the solder sealing ring, the relationship of the number of cycles-to-failure versus the strain energy density for the 48 wt % Sn–52 wt % In solder is needed. This relationship is determined by a set of isothermal fatigue tests.

6.5.1 Sample Preparation The test specimen consists of a stack of silica chip, 48 wt % Sn–52 wt % In solder sealing ring, silicon chip, 100 wt % In die-attached solder, and molybdenum substrate. The aluminum cooling plate is not included. The integrity of the 48 wt % Sn–52 wt % In solder seal is checked by connecting the specimen to a helium leakage detector and measuring the helium leak rate. If the leak rate is 10e–11 Pa · m3/s or less, then the specimen is further characterized by the C-mode scanning acoustic microscope (SAM), as shown in Fig. 6-14.

6.5.2 Test Setup and Procedures The isothermal fatigue tests are performed on a screw-driven Instron mechanical testing machine with a load cell of 450-lb capacity. The maximum loads applied in the fatigue tests are in the range of 25 to 100 lb, so the load-cell resolution is sufficient. Before testing, in order to reduce the sluggishness in the loading system during cyclic loading and unloading, a dummy specimen is mounted and loaded to 400 lb. All the screws for the loading pins, adapters, and pulling rods are turned tight in the 400-lb loading condition.

309

310

Chapter Six

B00408

FIGURE 6-14 C-mode SAM image of the solder sealing ring.

In order to apply a pure shear loading on the solder seal ring that is only 5 μm thick and minimize any bending and twisting, a set of specimen grip fixtures has been designed, and a specimen mounting procedure has been followed. A specimen is mounted by first attaching the back surface of the specimen (i.e., the backside of the molybdenum substrate) on the lower grip with an epoxy glue and four screws, which are evenly tightened with a 3 in-lb torque screwdriver. The lower grip then is mounted on the pulling rod of the Instron. Epoxy glue is painted onto the front surface of the specimen (i.e., the top side of the silica chip) and the upper grip. The lower grip, specimen, and upper grip are held together with a C-clamp. The upper grip then is mounted on the pulling rod before the epoxy is cured. Because the solder seal ring is only 5 μm thick, a displacement gauge with submicron resolution is needed for measuring the displacement in shear fatigue tests. A capacitance gauge with a sensitivity of 10 μm/V is used. The capacitance gauge is made of a probe, a flat plate, and a controller box that provides the excitation voltage for the probe and also amplifies the receiving signal. The basic principle of the capacitance gauge is to measure the capacitance between the probe and the flat plate, which is related to the distance between them. Before being used, the capacitance gauge is characterized by measuring its output voltage and the distance between the probe and the flat plate. The most linear range of the gauge, as shown in Fig. 6-15, between 5 and 10 V, is used.

Optical MEMS Packaging: Bubble Switch 16 14 12

Voltage, V

10 8 6 4 2 0 –50

–2 0

50

100

150

200

Displacement, μm

FIGURE 6-15

Capacitance-gauge calibration curve.

During a shear fatigue test, the probe and the flat plate of the capacitance gauge are fixed on the lower and upper grips, respectively. The measured displacement includes the deformations of the lower and upper grips and all the materials between the two grips—the epoxy and the specimen stack (silica chip, 48 wt % Sn–52 wt % In solder sealing ring, silicon chip, 100 wt % In die-attached solder, and molybdenum substrate). All these deformations are elastic and reversible except the deformations of the epoxy, the 48 wt % Sn–52 wt % In solder sealing ring, and the 100 wt % In die-attached solder. In a cyclic load versus displacement curve, the reversible displacements do not contribute to the width and area of the hysteresis curve; only irreversible displacements do. Therefore, inclusion of the reversible deformations in the displacement measured by the capacitance gauge does not affect the accuracy of the inelastic strain or inelastic strain-energy calculation (the area of the hysteresis loop). However, the irreversible deformations from the epoxy and 100 wt % In die-attached solder need to be excluded. In order to determine the irreversible deformations from the epoxy and 100 wt % In die-attached solder, a specimen made of a partial stack—the silicon chip, 100 wt % In die-attached solder, and molybdenum substrate—is glued with epoxy on the lower and upper grips. The cyclic load versus displacement curve of the partially stacked specimen is measured and is compared with the curve obtained from a fully stacked specimen—silica chip, 48 wt % Sn–52 wt % In solder sealing ring, silicon chip, 100 wt % In die-attached solder, and molybdenum substrate. The comparison shows that the

311

312

Chapter Six irreversible contributions from the epoxy and 100 wt % In dieattached solder are much less significant than that from the 48 wt % Sn–52 wt % In solder sealing ring for the same cyclic load range. This could be due to the very large amount of 100 wt % In solder die attachment compared with the 48 wt % Sn–52 wt % In solder sealing ring. All the isothermal fatigue tests are performed at room temperature and at 1 minute per cycle. The fatigue tests are displacementcontrolled; that is, the displacement amplitude is constant for each cycle. The cyclic-load amplitude is measured for each cycle. The number of the cycle after which the cyclic-load amplitude is reduced to 50 percent of that of the first cycle is defined as the fatigue life, or number of cycles to failure.

6.5.3 Test Results Figure 6-16 shows a typical load-drop curve versus time for one of the tested samples. In this case, it can be seen that the initial load was 36.2 lb, and the final load was 18.1 lb—and it occurs at about 80 cycles. A typical hysteresis loop (load versus displacement curve) for one of the tested samples is shown in Fig. 6-17. It can be seen that the initial load-displacement loops are kind of “skinny,” and then they become “fatter” as time goes by. As mentioned earlier, during the isothermal fatigue test, the sample is defined as failed when the initial load is reduced to half. The area under the hysteresis loop at this time (number of cycles to failure) is defined as the strain energy per cycle. When the strain energy per cycle is divided by the volume of the sealing ring, we have the strain energy density per cycle. The number of cycles to failure Nf is plotted against the strain energy density per cycle W on a log-log scale, as shown in Fig. 6-18. A least-squares-fit straight line is used to

Load over time 50 40 30 Load, lb

20 10 0 –10 0

20

40

60

–20 –30 –40 Time, cycles

FIGURE 6-16 Isothermal fatigue test load-drop curves.

80

100

120

Optical MEMS Packaging: Bubble Switch Hysteresis loop 50 40 30 Load, lb

20 10 0 –0.015

–0.01 0.01

–0.005 0.005

–10 0

0.005

0.01

0.015

10000

100000

–20 –30 30 –40 Displacement , mm

FIGURE 6-17 Isothermal fatigue test hysteresis loops.

Nf = 1468W –1.475

(W ) Strain energy density, MPa

100

10

1 1

0.1

10

100

1000

(Nf ) Number of cycles to failure

FIGURE 6-18 Isothermal fatigue test results.

determine the coefficients of the following thermal fatigue equation for the 48 wt % Sn–52 wt % In solder: N f = 1468W −1 . 475

(6-3)

Thus, once the strain energy density per cycle of the 48 wt % Sn–52 wt % In solder element in a structure under thermal-cycling conditions is determined, the average thermal fatigue life (number of cycles to failure) of the solder element can be estimated by Eq. (6-3).

313

314

Chapter Six

6.6 Thermal Fatigue Life Prediction of the Sealing Ring Based on the nonlinear temperature-dependent and time-history analysis of the photonic switch under shipping, storing, and handling condition, the strain energy density per cycle in the 48 wt % Sn–52 wt % In sealing ring is determined to be 0.5 MPa. Substituting this value into Eq. (6-3) or using Fig. 6-18, then the average thermal fatigue life of the solder ring is estimated to be 4000 cycles. This is more than adequate for shipping, storing, and handling the photonic package. It should be pointed out that in this study, (1) only a perfect structure is considered in the analysis, (2) the intermetallic compounds between the 48 wt % Sn–52 wt % In sealing ring and the silica chip and between the solder sealing ring and the silicon chip are not modeled, and (3) the isothermal fatigue data are very limited. Nevertheless, since the estimated thermal fatigue life (4000 cycles) is so many times larger than the required 300 to 500 cycles in general practice for shipping, storing, and handling, the photonic package should be considered reliable under these conditions.

6.7 Appendix A: Package Deflection by Twyman-Green Interferometry Method Twyman-Green interferometry offers a high-resolution and noncontacting measurement technique. Similar in design to a Michelson interferometer, the technique measures the relative path-length difference between a reference beam and an object beam. This instrument employs a division of amplitude using a 50:50 beamsplitter. A collimated beam is projected onto the beamsplitter at a 45-degree incidence. The reference beam travels through the beamsplitter and is projected onto a mirror set at normal incidence to the light’s direction. The object beam is reflected off the beamsplitter and travels to the sample. The two beams (reference and object) are then reflected back through the system and recombine at the beamsplitter. Because the light source is coherent, the recombined wave will create a constructive interference pattern at all points where the path-length difference is a multiple of the wavelength (n = 0, 1, 2, . . . ). Likewise, a destructive interference pattern occurs where the path-length difference is n + 1/2 the wavelength. The recombined wavefront with the interference pattern then is recorded. Taking the path-length difference, the resolution of the interferometer is given as

d=

nλ 2

(6-4)

where d = the displacement n = the fringe order (from constructive fringe to constructive fringe or destructive fringe to destructive fringe) λ = the wavelength of light used

Optical MEMS Packaging: Bubble Switch This technique gives us an out-of-plane displacement resolution of 0.316 μm per fringe order using an He-Ne laser. Twyman-Green interferometry, with a resolution of 0.316 μm per fringe, has been used as a tool for measuring the warpage of various electronic components. Previously, this full field technique has been applied only at room temperature.18–20 To extend the capabilities to elevated temperature measurements, a novel method for examining certain electronic packages at elevated temperatures using a TwymanGreen interferometer has been developed.21 This method is modified and adapted for the purposes of this experiment.

6.7.1 Sample Preparation The sample consists of the silica chip, the 48 wt % Sn–52 wt % In sealing ring, the silicon chip, the 100 wt % In die attachment, and the molybdenum substrate, as shown schematically in Fig. 6-19. (The aluminum cooling plate is not included.) A specular surface is required to use the Twyman-Green interferometer. To obtain a specular surface on the photonic package, 500 Å of chrome is deposited on the surface.

Free end

Symmetric

FIGURE 6-19 Finite-element model of half the test package.

Fixed end Thin Mo base, creep analysis, half model

315

316

Chapter Six

6.7.2 Test Setup and Procedure The test setup is shown in Fig. 6-20. The sample is mounted (fixed) upright on one end (very similar to the picture shown in Fig. 6-19 except with the whole module) in a small thermal cycling chamber located on the same optical table as the interferometer. The chamber is mounted on rubber bumpers on the table, and the sample is held directly to the table through a port on the side of the chamber to minimize vibration from the chamber. An He-Ne source with a wavelength of 0.632 μm is expanded, collimated, and projected to a beamsplitter. Through a window in the chamber wall, the top surface of the photonic package is hit with the object beam. The reflected object beam is combined with the reference beam (off a flat mirror at room temperature), producing an image of the interference pattern. Each fringe is a deviation from flat corresponding to half the wavelength of the light used (i.e., 0.316 μm). By counting the fringes, one can deduce the deviation of the surface from flat. A limitation of this technique is that the shape of the fringe pattern is unknown (i.e., either concave or convex). However, this shape often can be determined initially with other techniques. The initial shape of the package is determined using the Dektak, a surface profiler that runs a stylus across the silica chip.

Laser (not shown)

Beam steerer

Thermal cycling chamber

Beam collumator

Beamsplitter Digital camera Reference beam mirror

FIGURE 6-20

Test setup for Twyman-Green interferometry.

Optical MEMS Packaging: Bubble Switch 120

Temperature, °C

100 80 60 40 20 0

0

1000

2000

3000

4000

5000

Time, s FIGURE 6-21 Test temperature conditions.

6.7.3 Temperature Conditions The temperature of the convection chamber is controlled via a thermocouple that is adhered to the back of the sample. Computer proportional–integral–derivative (PID) control of the chamber allows for control of the temperature as a function of time. The temperature of the chamber is increased from room temperature to 100°C and back to room temperature, as shown in Fig. 6-21. Photographs of the fringe pattern are taken at increments along the way. With this information, the deformation of the sample as a function of temperature can be calculated by counting the fringes at each time interval.

6.7.4 Measurement Results An example of the data can be seen in Fig. 6-22 (30.03°C during the thermal cycle). The fringes are counted along the two axes of the diamond-shaped package. The long axis is referred to as the y axis, and the short axis is referred to as the x axis. Figure 6-23 shows the out-ofplane displacements as a function of temperature for the cycle. Because the package is larger in the y direction, more fringes (and therefore more displacement) are seen than for an equivalent amount of curvature in the x direction. Positive displacement indicates a convex surface; negative is concave. It is important to note that the concavity is inferred from the expansion coefficients of the components.

6.8 Appendix B: Package Deflection by Finite-Element Method The sample under the Twyman-Green interferometry test is modeled by the nonlinear finite-element analysis procedures used in this study with exactly the same geometry, material properties (see Table 6-1), and loading conditions (see Fig. 6-21). Since the structure is clamped at only one end, half the structure has to be modeled, as shown in Fig. 6-19.

317

318

Chapter Six Long axis - y 3 2 1

0

1

2 2.5

Short axis - x

FIGURE 6-22

Test results with fringe pattern.

2.5 Calculation (heating) Calculation (cooling) Test,

2 1.5 1 0.5 0 –0.5 –1 –1.5

0

20

40

60

80

100

Temperature, °C

FIGURE 6-23 Test and simulation results during heating and cooling.

120

Optical MEMS Packaging: Bubble Switch 0.0 –0.5 –1.0

Distance

1

–1.5

93.8°C 87.5°C 77.4°C 67.5°C 60.1°C thin Mo base, creep analysis, half model 50.2°C Temperature 39.8°C 100°C → 23°C 30.0°C 23.0°C → 27.8°C (4 days) 27.8°C, 4 days

–2.0 –2.5 –3.0 –3.5 –4.0 –4.5 –5.0

0

5

10

15 20 Distance, mm

25

30

35

FIGURE 6-24 Deflection of the package at various cooling temperatures.

Figure 6-24 shows the deflections along the longer centerline of the silica chip during cooling conditions. It can be seen that (1) the deflections are increasing as the temperature is cooling, (2) the deflection reaches a maximum when the temperature decreases to room temperature, and (3) the deflection reduces to almost zero 4 days later. This is so (1) because of the creep behavior of the 48 wt % Sn–52 wt % In solder, as shown in Fig. 6-23, (2) because the higher the temperatures, the larger is the creep strain rate, (3) because the larger the creep strain rate, the lesser is the bonding between the silica chip and the silicon chip and thus lesser is the deflection owing to the thermalexpansion mismatch between the silica chip and the silicon chip, and (4) because of the stress relaxation of the solder. In Figure 6-23, the deflection test results are measured from the center reference to the edge of the silica chip. In order to compare the finite-element results with the measurement results, Fig. 6-25 shows the method of calculation of the deflection from the finite-element results, that is, by connecting the end points (cord AB) of the deformed silica chip and calculating the distance from the midpoint of the Undeformed A E

Deformed

Midpoint of cord AB Deflection of silica chip = E

FIGURE 6-25 Calculation method of deflections for comparison purposes.

B

319

320

Chapter Six cord AB. The results are plotted in Fig. 6-23. It can be seen that the finite-element results compared very well with the measurement results, which enforces the confidence of the simulation results of the lead-free solder sealing ring.

6.9 Appendix C: Finite-Element Modeling of the Bolt As mentioned earlier, the silica chip, 48 wt % Sn–52 wt % In sealing ring, silicon chip, 100 wt % In die attachment, and molybdenum substrate are stacked up and bolted down onto the very large and thick aluminum cooling plate. Also, it has been pointed out that the thermalexpansion coefficient of the aluminum is many times larger than that of the silica, silicon, and molybdenum (see Table 6-1). Thus, when the package is subjected to temperature changes during shipping, storing, and handling, the effect of the thermal-expansion mismatch between the aluminum cool plate and the stacked structure above it depends on the bolted condition. For example, if the bolt is loose, then there is not any interaction between the aluminum cool plate and the stacked structure. On the other hand, if the bolt is infinitely rigid, then all the thermal-expansion mismatch between the aluminum cool plate and the stacked structure above it becomes 100 percent effective. Consequently, the bolted condition, including contact and friction near the bolt, plays a very important role in determining the final responses of the whole structure.

6.9.1

Description of the Bolted Model

Figure 6-26 shows the bolt configuration and the structural elements around it. Figure 6-27 shows the finite-element model of the bolt. Steel bolt

Seating surface

3.5 mm

1 mm

Bolt diameter = 2 mm 0.63 mm

Hole diameter = 2.1 mm

Thread binding

FIGURE 6-26

4 mm

Bolt configuration and surrounding materials.

Mo

Al

Optical MEMS Packaging: Bubble Switch

PRETS179 pretension element in ANSYS

FIGURE 6-27 Bolt finite-element model.

Pretension setting is allowed in this bolt model. An initial strain will be applied to a section of the bolt so that the resulting axial tensile load will be locked at a predetermined value at the initial step of the analysis. This is realized by implementation of the PRETS179 pretension element in ANSYS (Release 5.6 or later). Figure 6-28 shows a cut-away view of the assembled molybdenum substrate and aluminum cool plate by the steel bolt.

Note: Parts of the Al were cut away Steel bolt

Mo

Al

FIGURE 6-28 Finite-element model of the package with the bolt.

321

322

Chapter Six The bolt-up (pretension) load is calculated by the following formula:22 T=

where

2 πM l + fl sec b sec d csc b + 3πr f ′

(6-5)

l = pitch (0.4 mm) f = friction coefficient between the steel thread and Al hole, 0.61 f ′ = friction coefficient between the steel bolt head and Mo seat, 0.35 r = mean radius of the thread = 1/2 of pitch diameter = 0.87 mm b = angle of inclination of thread to a plane at right angles to the axis of screw tan b = l/2πr 2 sec d = sec c 1 − (sin b sin c) c = half the angle between the faces of a thread = 30° d = angle between a plane normal to the axis of the screw through the point of the resulting thread friction and a plane that is tangent to the surface of the thread at the same point

With a tightening torque M of 3 in-lb (339 N-mm), the resulting tension T in the bolt is calculated as 298 N. Contact and frictional effects between the steel bolt and the molybdenum substrate surfaces (i.e. the seating surfaces and the bolt-hole surfaces) are included in the finite-element analysis via surface-to-surface contact elements. However, the steel bolt and the aluminum cool plate are assumed to be perfectly connected, as shown in Figs. 6-26 and 6-28. Figure 6-29 shows the deformed shape of the bolt head after the initial bolt-up. It can be seen that the contact element functions as expected in the finite-element model.

6.9.2

Responses of the Bolted Photonic Switch

Figure 6-30 shows the time-history maximum (center) deflection of the molybdenum (Mo) substrate and the aluminum (Al) cooling plate at the center of the package when it is subjected to the thermal cycling loading shown in Fig. 6-6. Similarly, Fig. 6-31 shows the verticaldisplacement history of the silica and silicon chips at the center of the package. It is observed that there are irregular displacement changes (1) from temperature dwell to ramp-down and (2) from temperature dwell to ramp-up. These irregular responses are due to the contact and friction-condition changes near the bolt-head seating and between the molybdenum substrate and the aluminum plate. There are two contact conditions, namely, “contact and slip” and “contact and stick.”

Optical MEMS Packaging: Bubble Switch

FIGURE 6-29 Deformation of the bolt under pretension.

Irregular responses

Center displacement history

10 8 Displacement, μm

6 4 2 0 –2 –4

Mo Al

–6 –8 –10

0

3600

7200

10800

14400

18000

Time, s Note: 40°C <==> 85°C cycling of bolted switch

FIGURE 6-30 Time-history deflection of the Mo substrate and Al plate at the package center.

323

324

Chapter Six Spring-back force in Mo overcomes the friction, and “sliding” occurs. Mo starts to flatten out after sliding.

12 Mo Al

Displacement, μm

10

Start to cool from 85°C

8 6 Al shrinks more than Mo, and Mo center bulges up due to “sticking” at bolt head seating

4 2 0

0

200

400

600

800

1000

1200

Time, s

1400

1600

1800

Δt ≈ 5 s

Note: Data were recorded at every 20 time steps of solutions.

FIGURE 6-31 Time-history deflection of the Mo substrate and Al plate with smaller time steps.

To confirm and understand the cause of these irregular displacement changes, in a reanalysis, a finer time step of 5-second intervals was used during the first cycle, when the temperature starts to drop from 85°C (Fig. 6-31). More details of molybdenum displacement are captured, and the irregularity is more significant than that shown in Fig. 6-30. The interpretation of this irregularity is as follows: Since the stress-free temperature is set at 25°C, the aluminum tends to expand more than the molybdenum at 85°C. Friction force from the bolt head results in stretching of the molybdenum base. Initially, contact pairs on the bolt seating surface stick to each other. When the cooling down from 85°C starts, the aluminum plate shrinks faster than the molybdenum substrate. In the beginning, the friction force will change directions and starts to compress the molybdenum substrate inward. At this point, contact pairs are still sticking to each other, and the molybdenum substrate starts to bow up owing to compression. After the spring-back force in the molybdenum substrate overcomes the friction force, slip occurs in the contact pairs. The molybdenum substrate flattens out owing to a slip, and the contact pairs continue to slip during the cool-down phase. Figure 6-32 shows the corresponding contact conditions on the seating surface, which are extracted from ANSYS results. The stick or slip status matches the displacement change well. In reality, the actual bolt pretension level and the friction force may deviate from the assumed values in the analysis, and this certainly will affect the final displacement level.

Optical MEMS Packaging: Bubble Switch Load direction changed, but still sticking

Friction status

Start sliding

100 80

Sliding stopped after force balance adjustment to creep deformations in the solder ring and the 100In layer.

2

Slide

60 40

Slide

Start sliding

Stick

Stick

20 0

1

Temperature ,°C

3

–20

Friction status: 1 for stick, 2 for slide

–40

0 0

200

400

600

800 1000 Time, s

1200

1400

1600

–60 1800

Δt ≈ 5 s Note: Friction status is an output parameter of contact elements, recorded throughout the analysis

FIGURE 6-32 The time-history stick and slide friction status.

References 1. Fouquet, J. E., Venkatesh, S., Troll, M., Chen, D., Wong, H. F., and Barth, P. W. “A compact scalable cross-connect switch using total internal reflection and thermally generated bubbles.” In Proceedings of the IEEE/Lasers and Electro Optics Society Annual Meeting, San Francisco, CA, Vol. 2, December 1998, pp. 169–170. 2. Fouquet, J. E., Venkatesh, S., Troll, M., Chen, D., Schiaffmo, S., and Barth, P. “Compact, scalable fiber optic cross-connect switches.” In 1999 Digest of the LEOS Summer Topical Meetings, Nanostructures and Quantum Dots/WDM Components/VCSELs and Microcavaties/RF Photonics for CATV and HFC Systems, San Diego, CA, July 26–30, 1999, pp. 1159–1160. 3. Fouquet, J. E. “Compact optical cross-connect switch based on total internal reflection in a fluid-containing planar lightwave circuit.” In Proceedings of the Optical Fiber Communication Conference, Technical Digest, Baltimore, MD, 1:204–206, 2000. 4. Chen, D., Close, S., Fouquet, J., Haven, R., Reynolds, R., Schiaffino, S., Schroeder, D., Troll, M., and Venkatesh, S. “An optical cross-connect switch based on macro-bubbles.” Paper presented at the ASME Micro-Electro-Mechanical Systems (MEMS) Conference, Orlando, FL, November 2000. 5. Venkatesh, S., Haven, R., Chen, D., Reynolds, H., Harkins, G., Close, S., Troll, M., Fouquet, J., Schroeder, D., and McGuire, P. “Recent advances in bubble-actuated cross-connect switches.” In Proceedings of the 4th Pacific Rim Conference on Lasers and Electro-Optics (CLEO/Pacific Rim 2001), Chiba, Japan, Vol. 1, July 2001, pp. 1414–19. 6. Venkatesh, S., Son, J., Fouquet, J., Haven, R., Schroeder, D., Guo, H., Wang, W., Russell, P., Chow, A., and Hoffmann, P. “Recent advances in bubble-actuated photonic cross-connect switches.” In Proceedings of SPIE Photonics West, San Jose, CA, Jan 19–25, 2002, pp. 27–35.

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Chapter Six 7. Venkatesh, S., DePue, M., Okano, H., and Uetsuka, H. “Insertion loss reduction by optimization of waveguide perturbations.” In Proceedings of Optical Fiber Communication Conference, Postdeadline Papers, Anaheim, CA, March 17–22, 2002, pp. FA4-1 to FA4-3. 8. Venkatesh, S., Fouquet, J., Haven, R., DePue, M., Seekola, D., Okano, H., and Uetsuka, H. “Performance improvements in bubble-actuated photonic crossconnect switches.” In Proceedings of the IEEE Lasers and Electro-Optics Society (LEOS 2002), Vol. 1, Glasgow, Scotland, November 10–14, 2002, pp. 39–40. 9. Hengstler, S., Uebbing, J. J., and McGuire, P. “Laser-activated optical bubble switch element.” In Proceedings of the Optical MEMS, 2003 IEEE/LEOS International Conference, Waikoloa, Hawaii, August 18–21, 2003, pp. 117–118. 10. Lau, J. H., Mei, Z., Pang, S., Amsden, C., Rayner, J., and Pan, S. “Creep analysis and thermal-fatigue life prediction of the lead-free solder sealing ring of a photonic switch.” J. Electron. Packag., Trans. of ASME, 124:403–410, 2002. 11. Lau, J. H., and Pao, Y. H. Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies. New York: McGraw-Hill, 1997. 12. Lau, J. H. Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies. New York: McGraw-Hill, 2000. 13. Lau, J. H., and Lee R. Microvias for Low Cost High Density Interconnects. New York: McGraw-Hill, 2001, pp. 456–457. 14. Lau, J. H., Wong, C. P., Prince, and W. Nakayama. Electronic Packaging: Design, Materials, Process, and Reliability. New York: McGraw-Hill, 1998. 15. ANSYS Users’ Manual, Canonsburg, PA, 2002. 16. Mei, Z., and Morris, J. “Superplastic creep of low melting point solder joints.” Journal of Electronic Materials 21:401–407, 1992. 17. Lau, J. H. Solder Joint Reliability: Theory and Applications. New York: Van Nostrand Reinhold, 1991, pp. 225–265. 18. Han, B., Guo, Y., Lim, C., and Caletka, D. “Verification of numerical models used in microelectronics packaging design by interferometric displacement measurement methods.” Journal of Electronic Packaging 118:157–163, 1996. 19. Han, B., Guo, Y., and Lim, C. “Application of interferometric techniques to verification of numerical model for microelectronics packaging design.” In Proceedings of Advances in Electronic Packaging, Maui, Hawaii, March 26–30, 1995, pp. 1187–1194. 20. Lin, S., Han, B., Suhling, J., Johnson, R., and Evans, J. “Finite element and Moiré interferometry study of chip capacitor reliability.” In Proceedings of Advances in Electronic Packaging, Kohala Coast, Hawaii, June 15–19, 1997, pp. 1687–1964. 21. Rayner, J., and Pitarresi, J. “Warpage measurement of electronic packages using Twyman-Green interferometry.” In Proceedings of the SEM Annual Conference on Theoretical, Experimental, and Computational Mechanics, Cincinnati, OH, June 7–9, 1999, pp. 16–18. 22. Baumeister, T., Avallone, E., and Baumeister, T., III. Marks’ Handbook for Mechanical Engineers. New York: McGraw-Hill, 1978, pp. 3–30.

CHAPTER

7

Optical MEMS: Microbolometer Packaging 7.1

Introduction Vacuum is crucial to certain microelectromechanical systems (MEMS) devices; it helps in improving their performance and at the same time protects them from the environment. Thermal isolation inside the package also can be created by employing vacuum inside the package. An infrared (IR) bolometer works on the principle of change in resistance of the bolometer, generating a signal by absorption of incident IR radiation.1 Since an IR bolometer requires temperature stabilization, it is essential for the device to be thermally isolated from the package. Heat loss by conduction or convection requires a medium, and if the medium is a vacuum, the loss will be minimal. A vacuum package for an IR bolometer has been designed based on thermal and structural requirement and has been reported on by authors.2 Two critical elements for a good vacuum package are hermeticity and a low outgassing rate. Vacuum packages can be achieved with a component-level or die-level method based on the application.3 Different sealing methods, such as laser welding, solder sealing, seam sealing, and wafer bonding, have been attempted for vacuum sealing, and proper baking and selection of packaging materials reduce outgassing inside the package. In a vacuum package, real leaks can be solved by proper sealing of the packaging, whereas virtual leaks such as outgassing inside the package can be resolved by getters and proper baking of the package.4 Construction of a sealed vacuum package for 240 × 336 microbolometer arrays is showed in Fig. 7-1. Requiring a vacuum in a package will improve device performance for sure, but at a cost. New technologies are driving toward improved performance at lower cost, though. However, vacuum packaging still creates additional costs in packaging that will reduce the

327

328

Chapter Seven

Lower periphery metalized to permit soldering

Antireflected germanium window Silicon chip (HIDAD array)

Pads for Al bonds Thermistor Melalized for solder TE stabilizer (BeO plates)

–

+

TE power leads Pads tor Al bonds 88 pins Al2O3 frame

Mounting holes

Copper/tungsten baseplate

Kyocera custom package OFHC copper pumpout tube

Zr getter inside pumpout tube Crimp seal

FIGURE 7-1 Construction of a sealed vacuum package for 240 × 336 microbolometer arrays (Ref. 11).

market competitiveness. There is a tradeoff between performance and cost. Let us look into some of the applications for vacuum packaging. IR bolometers used for night vision in security applications work on the principle of IR irradiation of a MEMS membrane that is sensitive to heat. The absorption of incident IR irradiation changes the resistance of the bolometer structure and generates a pulse in the readout circuit. This output is processed by an additional electronic circuit, and an image is produced based on the temperature irradiation from the object. One of the important requirements in vacuum packaging is how to maintain the vacuum inside the package. Outgassing is the major issue in vacuum packaging, and it drops the vacuum inside the package. To maintain the vacuum inside the package, outgassing inside the package has to be reduced. There are two ways that outgassing can be controlled; one is by effective baking of the package and package materials prior to sealing, and the second is by incorporating getters. The baking of the package materials and package has to be done in under high-vacuum conditions at a temperature of 125°C to remove moisture. Additional gases outgassed by the package are absorbed by getters, which act as micropumps inside the package.5 The getters are activated at a particular temperature, and their surfaces will be exposed to absorb the gases. The challenges in vacuum packaging for MEMS devices are many. Maintenance of a high vacuum inside a package throughout its service life itself is a great challenge in packaging. Sealing of the package joints has to be done without any leakage. Meeting minimum hermeticity requirements (5 × 10–8 atm · cc/s) will not be sufficient to retain the vacuum for 5 years. The reliability of the package has to be

Optical MEMS: Microbolometer Packaging considered during the design stage, such as package geometry, hermeticity requirements, sealing technique, and plating material. The outgassing from the package and packaging materials must be understood before selecting the materials.4 Any additional materials will result in more outgassing into the package, and this will jeopardize the vacuum life of the package. Thus design of the package and selection of materials must be done with a view toward longterm reliability requirements. From a business point of view, the cost of vacuum packaging will be higher than that of normal packaging. The challenge with these devices is to keep the package cost as small as possible while maintaining the vacuum inside the package.

7.2

Bolometer Chip An IR bolometer used for night vision in security applications works on the principle of IR irradiation to a MEMS membrane that is sensitive to heat (Fig. 7-2). The absorption of incident IR irradiation changes the resistance of the bolometer structure and generates a pulse in the readout circuit. This output is processed by an additional electronic circuit, and an image is produced based on the temperature irradiation from the object. Temperature loss from the MEMS structure will result in incorrect data interpretation and produce uncorrelated results. In this case, the loss of heat from the structure by conduction and radiation/ convection should be reduced. Thermal isolation is required to avoid

128 µm × 128 µm pixel microbolometer focal plane array chip

FIGURE 7-2

A 128 × 128-array bolometer chip.

329

330

Chapter Seven 4 30

Heat capacitance, 10–9 J/K

Thermal conductance 3

20 2

10

1

0 10–5

FIGURE 7-3

Thermal conductance, 10–7 W/K

Heat capacitance

0 10–4

10–2 100 Pressure, torr

102

Sensitivity versus vacuum for a bolometer device.

further heat loss by conduction or convection. Vacuum provides a good thermal insulation between the device substrate and the MEMS membrane. The higher the vacuum inside the package, better is the efficiency of the bolometer device. However, the sensitivity saturates toward higher vacuum levels (Fig. 7-3).

7.3 Thermal Optimization The IR bolometer works on the principle of IR irradiation that changes the resistance of the bolometer structure and, in turn, generates a pulse in the readout circuit.1 Since it is difficult to control the temperature at the device level, controlling it at the package level is another option. The challenge in IR bolometer packaging is to control the chip/package temperature during operation. In this study, a thermally and structurally optimized package has been developed for a 128 × 128-array bolometer device. A cross-sectional view of the IR bolometer package is shown in Fig. 7-4. The package consists of a germanium (Ge) window that is transparent to IR light in the range of 8 to 14 μm. Bolometer sensitivity depends on the temperature stability of the package with respect to the ambient temperature.2 To meet this requirement, the design of the package should satisfy (1) minimized heat loss from the sensor area to the surroundings by conduction, convection, and radiation methods and (2) stable device temperature irrespective of ambient conditions. To minimize heat

Optical MEMS: Microbolometer Packaging FIGURE 7-4 Cross-sectional drawing of the bolometer package.

Bolometer chip

Ge window

TEC

loss through the medium, a vacuum is created between the bolometer array and package because the vacuum provides good thermal isolation from the ambient.3 The second part, chip temperature, can be controlled by using a thermoelectric cooler (TEC) to which the bolometer chip is attached. The vacuum requirement in the package poses additional loading/stress on the package structure.4 In addition, the performance of the TEC needs to be optimized to meet sustain temperature stabilization. Bolometer chip temperature stability is essential for the accuracy of IR sensing, and hence due consideration must be given to it in designing the package. The package design must accommodate two types of thermal loads, namely, (1) power consumed by the circuits on the chip and (2) heat transmitted to the chip from the surroundings. The power dissipation by the chip and the heat load together are estimated to be 1 W. However, the heat transmitted from the surroundings depends on the system’s operating environment. The bolometer system is expected to work in a wide range of environmental conditions (from –40 to 50°C), but the chip is always maintained around 22°C ± 0.2°C. The package has to transport the heat from the chip to the sink with the least amount of resistance. Thus the thermal conductivity of the material has to be high, and thermal diffusivity also has to be high to minimize energy storage during transient conditions. Considering other requirements, such as a low coefficient of thermal expansion (CTE), weight, and availability, copper tungsten (CuW) has been chosen as the package material. Thermal isolation of the chip from the package is essential for IR device sensitivity. Thus, by creating a vacuum inside the package, heat conduction and convection loss through air is avoided. However, heat gain or loss by radiation from the surroundings is minimized by the small area and temperature difference. Another requirement for the bolometer chip to function is to maintain a steady-state temperature during operation. Since the system operating environment ranges from subzero to high temperatures, a special device is required to heat or cool the chip.

331

332

Chapter Seven FIGURE 7-5 Bolometer package with TEC inside the package.

IR window

Die

Package body Heat sink

TEC

A TEC has been selected, considering the tight temperature tolerances required. The physical dimensions of the package are based on overall requirements and TEC size. The TEC needs to have good contact with the chip and the temperature gradient across the interface should be small for excellent temperature stability. A package with a TEC inside is shown in Fig. 7-5. However, the TEC will outgas over the time, and this may affect the vacuum level inside the package. Therefore, an alternate approach placing the TEC outside the package has been tested (Fig. 7-6). Two types of packages have been designed, one with a deep cavity to accommodate the chip and TEC and the other with a shallow cavity to house only the chip. The thermal behavior of both packages in a steady-state condition has been simulated using a Computational Fluidic Dynamic (CFD) tool.5 The temperature gradient between the chip and the cold side of the TEC is 0.1°C for the TEC inside the package and 1.8°C for the TEC outside the package. Solder has been used as a bonding material for the chip-to-TEC package. The steady-state condition of the package is not a big concern in terms of chip stability, but the dynamic behavior of the package with respect to ambient conditions is important. Thus an experimental method has been devised, and die temperature versus time has been measured.

FIGURE 7-6 Bolometer package with TEC outside the package.

Package body IR window

Die

Heat sink

TEC

Optical MEMS: Microbolometer Packaging Both packages have been built and tested. A standard thermal test die with a resistor and a temperature sensor has been used to represent the bolometer chip. Both packages were tested in similar environments and with similar power dissipation. The package was mounted on a heat sink, and the temperature stability of the chip was measured. Figure 7-7 shows the experimental setup. The TEC is controlled by a temperature controller with a maximum TEC current limit of 1.5 A. The test die is cooled or heated by the TEC to simulate extreme environmental conditions. A direct-current (dc) power source is used to heat the test die to emulate bolometer chip power dissipation. The test-die temperature is measured using a sensor implanted in the die. A custom-built data-acquisition tool is employed to log the die temperature approximately every 200 ms. Die temperature stability is observed for an hour and plotted. The die temperature stability is quite good with the TEC inside the package because the TEC controls a small thermal mass and is isolated from the ambient. With the TEC outside the package, though, the high thermal mass of the entire package is a deterrent to die temperature stability. Moreover, the cooling capacity of the TEC is not sufficient to meet the additional heat gained by the package surface area. Thus two TECs are connected in series, and the test is repeated. However, temperature stability was a major concern for a package with the TEC outside the package. Hence a package design with the TEC inside the package was recommended.

Die temperature measurement setup

Heating source

Thermal die

Sensor feedback to controller TEC

Temperature controller (LFI 3551 with PID controller from Wavelength Electronics)

FIGURE 7-7

Experimental setup for TEC temperature stability measurement.

333

334

Chapter Seven

7.3.1

Final Temperature Stability Testing

5 4.8 4.6 4.4 4.2 4 3.8 3.6 3.4 3.2 3 2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0

15:35:40

15:33:40

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14:45:40

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TEC inside ( 2 nos in series)

14:39:40

Die temperature, °C

A temperature sensor was calibrated in a temperature-controlled oven, and the sensitivity was found to be 7.9 Ω/°C. The package was evacuated and sealed. The temperature stability of the die was tested for two extreme conditions. Owing to practical difficulties, the package was not tested in an elevated/subzero ambient; instead, the temperature of the chip was cooled below the ambient and then heated above the ambient to represent the extreme environmental conditions. The following plots show the temperature stability of the die when the device was in a vacuum (Figs. 7-8 through 7-11).

Time

Die temperature stability with the TEC inside the package.

35 34.8 34.6 34.4 34.2 34 33.8 33.6 33.4 33.2 33 32.8 32.6 32.4 32.2 32 31.8 31.6 31.4 31.2 31 30.8 30.6 30.4 30.2 30

Time

FIGURE 7-9

Die temperature stability with the TEC outside the package.

11:41:49

11:39:39

11:37:29

11:35:19

11:33:09

11:30:59

11:28:49

11:26:39

11:24:29

11:22:19

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11:17:59

11:15:49

11:13:39

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11:07:09

11:04:59

11:02:49

11:00:39

10:58:29

10:56:19

10:54:09

10:51:59

10:49:49

10:45:41

TEC outside ( 2 nos in series)

10:43:31

Die temperature, °C

FIGURE 7-8

11:00:44

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10:41:34

10:37:44

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–5 –5.2 –5.4 –5.6 –5.8 –6 –6.2 –6.4 –6.6 –6.8 –7 –7.2 –7.4 –7.6 –7.8 –8 –8.2 –8.4 –8.6 –8.8 –9 –9.2 –9.4 –9.6 –9.8 –10

9:54:59

Die temperature, °C

Optical MEMS: Microbolometer Packaging

Time

11:25:07

11:22:07

11:19:07

11:16:07

11:13:07

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58 57.8 57.6 57.4 57.2 57 56.8 56.6 56.4 56.2 56 55.8 55.6 55.4 55.2 55 54.8 54.6 54.4 54.2 54 53.8 53.6 53.4 53.2 53 52.8 52.6 52.4 52.2 52

10:28:07

Die temperature, °C

FIGURE 7-10 Temperature stabilization during cooling of the package (above ambient).

Time

FIGURE 7-11 Temperature stabilization during heating of the package (below ambient).

7.4

Structural Optimization of the Package Design optimization of the IR package is necessary to meet new packaging requirements such as vacuum and chip temperature stabilization. Since the vacuum inside the package is on the order of 50 mtorr, an air-loading effect owing to changes in pressure with respect to atmospheric pressure will act on the germanium (Ge) window. This will deform the Ge window and can affect IR transmission as well as the reliability of joints of the package. A new window

335

336

Chapter Seven has been designed with optimized germanium thickness by structural modeling and found to be less deformed and more reliable. Finite-element simulations were performed to determine the warpage of four kinds of IR bolometer packages when they were subjected to thermal loading (80 to –55°C) owing to CTE mismatch and pressure loading owing to pressure differences in the cavity with respect to atmospheric pressure. The assumptions in the finiteelement model for three kinds of IR bolometer package designs are as follows: • Owing to the symmetry in geometry, only half the package is modeled. • The element used is a two-dimensional (2D) eight-node-plane strain element. • All materials are modeled as elastic materials and are listed in the Table 7-1. • The package is subjected to thermal loading (80 to –55°C) owing to CTE mismatch and pressure loading owing to pressure difference in the cavity with respect to atmospheric pressure.9 • The package is stress-free and not deformed at the curing temperature of 80°C. • Perfect adhesion is assumed at all material interfaces. ANSYS software is used to perform the finite-element modeling. The cross sections of the IR bolometer package designs I, II, and III are shown in Figs. 7-12 through 7-14, respectively. The material properties for all models are listed in Table 7-1. The typical finite-element mesh and boundary conditions for IR bolometer design III are shown in Fig. 7-15.

Material

CTE (ppp/∞C)

E (GPa)

n

Silicon die

2.6

131

0.25

TEC

6.936

160

0.3

Kovar

5.87

138

0.3

63Sn/37Pb

24

14.9

0.35

Ge window

6.1

102.7

0.3

CuW

5.0

324

0.3

AuSn

21.1

10

0.3

BiSn

15

11.9

0.3

TABLE 7-1 Material Properties Used in Structural Modeling

Ge window Die TEC

FIGURE 7-12 Design I: cross section of IR bolometer package (Ge window directly attached).

Ge window Die TEC Spacer

FIGURE 7-13 Design II: cross section of IR bolometer package (Ge window face down).

Ge window Die TEC Spacer

FIGURE 7-14 Design III: cross section of IR bolometer package (Ge window face up). Pressure loading

FIGURE 7-15 Finite-element mesh and boundary conditions for IR bolometer design III.

337

Chapter Seven

Warpage, µm

338

14 13 12 11 10 9 8 7 6 5 4 1.2

1.4

1.6

1.8

2

2.2

2.4

Ge window thickness, mm

FIGURE 7-16 package.

Effect of Ge window thickness on warpage for an IR bolometer

The effect of Ge window thickness on warpage for IR bolometer package design I is shown in Fig. 7-16. It can be seen that warpage at the top surface of the Ge window decreases as Ge window thickness increases. The target is to get minimum warpage provided by a thickness of Ge that can withstand the air loading owing to the pressure difference inside the package with respect to atmospheric pressure. Based on the process and package geometry, a Ge window thickness of 1 to 1.3 mm should be optimal for window attachment and future packaging-process conditions. A comparison of the three package designs in terms of warpage is shown in Table 7-2 with a Ge window thickness of 1.3 mm. It was found that the design with the Ge window facing up was better than the design with the Ge window facing down in terms of warpage. However, design I was found to have higher warpage for a Ge thickness of 1.3 mm and thus is not a suitable design. Since design III, with the Ge window face up, was found to be better in terms of warpage, another study was done for a Ge window thickness of 1 mm and is shown in Fig. 7-17. It can be seen that warpage has become saturated when the inside pressure is less than 0.01 torr. Different package materials have been studied in terms of deformation and stress on the package. A deformation study has been done with materials such as Kovar and CuW for design II (Fig. 7-18). It was found that warpage along the top surface of the Ge window for Kovar

Package Design

I

II

III

Warpage (μm)

13.2

3.18

1.5

TABLE 7-2 Comparison of Different Package Designs in Terms of Warpage with the Ge Window

Optical MEMS: Microbolometer Packaging

Warpage, µm

2 1.6 1.2 0.8 0.4 0 0.001

0.01

0.1

1

10

100

1000

Pressure inside, torr

FIGURE 7-17 Warpage versus vacuum when the Ge window thickness is 1 mm (design III).

Kovar

CuW (Copper Tungsten)

FIGURE 7-18 Deformation picture for IR-Bolometer package design II with Kovar/CuW as the base material.

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FIGURE 7-19 Package deformation for design I.

FIGURE 7-20 Package deformation for design III.

and CuW are 3.18 and 3.06 μm, respectively. There is no substantial difference in warpage when Kovar or CuW is used as the package base material. Two different designs, design I (Ge window directly attached) and design III (Ge window face up), have been compared for deformation and stress distribution in the package (Figs. 7-19 and 7-20). For a Ge window thickness of 1.3 mm, the deformation for design I was 13.2 μm, whereas for design III it was 1.5 μm. A substantial reduction in deformation can be seen in design III owing to structural optimization.

7.5 Vacuum Packaging of Bolometer Different package sealing techniques are used to achieve a vacuum package. The methods are

Optical MEMS: Microbolometer Packaging • Solder sealing • Laser welding • Seam welding • Wafer bonding Low- and high-temperature solders are used for hermetic sealing of the package. This method is an inexpensive one and does not depend on lid flatness and thickness tolerances. This method also allows the use of different cap materials with matching the CTE to that of the package. However, wetting of the solder depends on the surface quality and creates voids in the bonding that affect the yield and reliability of the package. Laser- and seam-welding methods are used to join the package body (Kovar) and the lid. The main advantage of these two techniques is that sealing of the package is done at a low temperature. In these methods, yield is better, and the process is clean. Both processes are expensive and require precision tooling in the package and the lid. However, high hermeticity of the package can be achieved with these methods, and both methods are suitable for metal-type packages. Ceramic/Kovar package options add to the total cost of the product (Fig. 7-21, Ref. 8). Wafer-level packaging offers a cost-effective packaging solution using wafer-to-wafer bonding (Fig. 7-22). Vacuum is applied during the wafer-bonding stage, and hermetic sealing is achieved. Since wafer-level packaging is a batch process, substantial cost reduction is possible (Fig. 7-23). High temperature during the process and difficulty in integrating getters into the package are the some of the disadvantages of this process. Two factors that are critical to a good vacuum package are hermeticity and a low outgassing rate. A vacuum package can be achieved with a component- or die-level method based on the application.3

Fab 20%

Design 5%

Packaging 75%

FIGURE 7-21

MEMS device cost with metal/ceramic packaging.

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Packaging 30%

Fab 60% Design 10%

FIGURE 7-22

MEMS device cost with wafer-level packaging.

Cap wafer Vacuum MEMS

Solder/eutectic/ anodic/frit glass bonding

FIGURE 7-23 Vacuum packaging at the wafer level with wafer-to-wafer bonding.

Different sealing methods such as laser welding, solder sealing, seam sealing, and wafer bonding have been tried for vacuum sealing. At the same time, outgassing inside the package can be reduced by proper baking and selection of packaging materials. In a vacuum package, real leaks can be solved by proper sealing of the packaging, whereas virtual leaks such as outgassing inside the package can be resolved by getters and proper baking of the package.4 In this study, a metallization development for Ge window solder sealing, an outgassing study of all packaging materials, and vacuum measurement of the package have been reported. A Ge window that transmits IR radiation in the range of 8 to 14 μm with antireflection coating on either side is used as the final sealing of the package. A vacuum package was developed using a single-element bolometer device and has been tested for vacuum consistency. This vacuum package is used for a 128 × 128-array bolometer and has been tested for functionality and image quality (Fig. 7-24).

7.5.1

Ge Window

A Ge window is used to transmit IR radiation to heat the bolometer elements. To ensure a complete transmission of IR light, antireflection coatings are provided on both sides of the window. In package development, the Ge window is attached to a Kovar frame. The Kovar

Optical MEMS: Microbolometer Packaging

Ge window

FIGURE 7-24

IR bolometer vacuum package.

frame with the Ge window is sealed to the package by a seam-sealing or laser-welding method. Since the Ge window is not a metal, sealing of the window can be done only by a solder-sealing method. For a solder seal, a wetting layer such as metallization is required on the Ge window. Metallization techniques available on Si surfaces were tried but found to have adhesion problems and failed in the peel-off test (Fig. 7-25). A process was developed to find a reliable metallization layer for good adhesion and solder wetting, and the results are shown in Table 7-3.

UBM peel-off

FIGURE 7-25

Metallization peel-off on Ge substrate.

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Sl No.

Metallization

Adhesion

1

Oxide + Ti/Ni/Au

NG

2

Ni + Au

NG

3

Au + anneal at 400°C for 1 h

NG

4

Cr/Au + anneal at 400°C for 1 h

NG

5

Cr/Ni/Au + anneal at 300°C for different times

NG

6

Cr/CrNi/Au

NG

7

Oxide + Ti/Ni/Au + anneal at 350°C

Good

Note: NG = not good.

TABLE 7-3 Different Metallizations Used on the Ge Substrate Window

Au Ni Ti Oxide Ge

FIGURE 7-26

UBM layer on Ge window.

In the different metallization combinations, oxide/Ti/Ni/Au has shown better results (Fig. 7-26). However, an additional annealing step improved the adhesion and was tested with the peel-off and dicing tests. No adhesion problems were seen after the peel-off and dicing tests. Solder preforms are used to attach the Ge window to the Kovar frame. Bonding quality was tested by the hermeticity test and has met the design criteria.

7.6

Getter Attachment and Activation A good hermetic package will not ensure a good vacuum package. This is so because of outgassing of the package materials, and this will increase the internal pressure of the package. Getters, which act as micropumps inside packages, have been used to absorb the outgassing gases before the final vacuum seal of the package. The target vacuum level inside the package was about 50 mtorr. Getter inside the package can be activated either by passing a current or heating the getter to the activation temperature. Heating the getter to the activation temperature is done by heating the whole package to the

Optical MEMS: Microbolometer Packaging

Getter

Leads

Getter

Pads

Solder

FIGURE 7-27

Getter lead attachment with solder.

activation temperature. Eutectic solder is used to connect getter and TEC leads to the package (Fig. 7-27). This can damage the bolometer device and TEC, which are sensitive to high temperatures. Activating the getter to the required temperature can be done by passing a current through the getter element. The current required to activate the getter to the required temperature was determined by measuring the temperature of the getter using a thermocouple attached to the getter (Fig. 7-28). Getters are attached to the package using soldering techniques. The getters are thoroughly cleaned in deionized (DI) water and dried before being used in the package. The influence of getter activation temperature on overall package temperature has been studied (Fig. 7-29). It was found that overall package temperature did not exceed the operating temperature of the device when activating the getter by the current-flow method. Getter temperature versus current Temperature, °C

600 500 400 Temperature, °C

300 200 100 0

0

FIGURE 7-28

1

2 3 Current, A

4

5

Characterization of getter with different currents.

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Temperature, °C

Package temperature versus current 80 T2

60

T1 — Package temperature T2 — Temperature at the getter contact to package

40 20 0

T1 0

FIGURE 7-29

1

2 Current, A

3

4

Measured temperature of the package during getter activation.

Thermal sensors

Getter

128 × 128 array bolometer chip

Kovar package

FIGURE 7-30

Fully assembled bolometer package.

In the final package, solder is used to attach the IR bolometer die, TEC, and thermal-sensor die. A Ge window with a Kovar frame is used to seal the IR bolometer package by the seam-welding method. The final package with a copper pipe connected at one end is use to pump down the package to a desired vacuum level. An external heating element is used at the bottom of the package to heat the package, so any residual gases from the package materials are removed during the pumping down of the package. The final vacuum sealing of the package is done by pinching the copper pipe with a customized tool (Fig. 7-30).

7.7

Outgassing Study in a Vacuum Package For vacuum packaging, outgassing is a reliability issue and needs to be known in advance to maintain the vacuum inside the package. To reduce the outgassing inside a package, package materials are baked

Optical MEMS: Microbolometer Packaging Sample ID

Unit

Kovar

TEC1

TEC2

Pressure

torr

0.5

2

0.5

Nitrogen

percent

0.9

8.81

12.6

Oxygen

ppm

ND

ND

ND

Argon

ppm

ND

ND

ND

CO2

percent

1.08

33.7

20.9

Moisture

percent

18.2

48.7

53.2

Hydrogen

percent

79.8

8.01

12.8

Helium

ppm

ND

ND

ND

Fluorocarbons

ppm

ND

ND

ND

Hydrocarbon

ppm

565

7319

4821

Note: ND = not detected.

TABLE 7-4 RGA Test on the TEC Used in Vacuum Sealing

before assembly into the package. The metal package and packaging parts, such as the TEC, are heated to a temperature of about 150°C in a vacuum oven to eliminate moisture and gases trapped in cavities of the package. Outgassing from packaging materials was studied with the residual gas analysis (RGA) test, and it was found that TECs outgass more than the other packaging materials or parts (Table 7-4). Outgassing of the vacuum-sealed package has been studied and found to have more with CO2 gas (Table 7-5). It is believed that the CO2 outgassing could be generated from the getter material Kovar/solder.

7.8 Testing Setup for Bolometer 7.8.1

Package Testing

Vacuum Measurement Technique Vacuum inside the package has been measured using a singleelement bolometer and is shown in Fig. 7-31. An IR bolometer package was used for packaging a single-element bolometer.10 The packaged device was connected to a Wheatstone bridge, and a dc bias was applied to the package for device warming (Fig. 7-32, Ref. 7). The package device was connected to a high-vacuum system, and the response of the device was monitored at different vacuum levels (Fig. 7-33). When the vacuum inside the package increases, the heat loss from the IR bolometer element decreases.6 The decrease in heat loss from the bolometer element increases the response of the bolometer

347

348

Chapter Seven Sample ID

Unit

1

2

Pressure

torr

247

474

Nitrogen

percent

77.5

76.8

Oxygen

percent

17.7

21.2

Argon

percent

0.9

1.01

CO2

ppm

8433

1051

Moisture

percent

288

0.82

Hydrogen

ppm

189

<100

Helium

ppm

ND

ND

Fluorocarbons

ppm

ND

ND

ISP_alcohol

ppm

348

ND

Hydrocarbon

ppm

180

ND

Acetone

ppm

1307

ND

Note: ND = not detected.

TABLE 7-5

FIGURE 7-31

RGA Test on Vacuum-Sealed Package

Single-element bolometer for vacuum-package development.

element. The change in the voltage (left y axis) is taken as the response at a particular vacuum level. Repeatability of the measurement has been tested with many packages and found to have correlation among the different samples (Table 7-6).

Optical MEMS: Microbolometer Packaging 2

Voltage, V

1

dc bias of 100 mV

0

No dc bias applied –1

–2

–20

0

20

40

60

80

Time, µs

FIGURE 7-32

Single-element bolometer time response with and without dc bias.

10.0

500

6 e-6 torr 7.5 5.0 0.37 torr

300

2.5 0.0

200

Slope, μVs

Voltage, mV

400

–2.5 100

–5.0

0

–7.5 –10.0 –20

0

20

40

60

80

Time, μs

FIGURE 7-33

Bolometer response under different vacuum conditions.

Using this method, the package can be calibrated for different vacuum levels. In subsequent vacuum packages, the vacuum inside can be determined by finding the y-value difference (voltage) and the corresponding vacuum level on the curve (Fig. 7-34).

349

350

Chapter Seven Package

Vacuum (torr)

y Value

1

–4

1.4 × 10 5.2 × 10–2 7.4 × 10–1

79.19 36.507 17.73

2

1.2 × 10–4 5.9 × 10–2 6.1 × 10–1

80.87 37.226 10.517

3

2.5 × 10–4 1.2 × 10–2 4 × 10–1

72.2 42 22

TABLE 7-6 y Values for Packages with Different Vacuum Conditions 2.50 2.25

Voltage, mV

2.00 1.75 1.50 1.25 1.00 0.75 0.50 10–5

FIGURE 7-34

7.8.2

10–4

10–3 10–2 Pressure, torr

10–1

100

Bolometer response for different air pressures.

Image Testing

A 128 × 128-array bolometer was vacuum packaged to test the IR camera system. Before vacuum packaging, this device was tested in the vacuum chamber of the camera. After vacuum packaging of the device, the quality of the image was tested. A test methodology was developed to test devices packaged in vacuum (Fig. 7-35). Two different IR sources were used in imaging application. Both sources were tried and found to have good image quality within the vacuum package. In the test setup, the bolometer package was attached to an IR camera system. The IR camera system was connected to both a monitor and a computer. An IR source was been targeted to the Ge window of the vacuum package. The Ge window transmits IR, and the radiation falls on the tiny pixels of the bolometer device. The pixels heat up based

Optical MEMS: Microbolometer Packaging Camera system

Monitor

Ge optics

Computer

Ge window IR array

d Blackbody

FIGURE 7-35

D

Vacuum chamber

Test setup for the bolometer image.

on the source, and a signal is sent through the CMOS part of the device for processing and image formation. The presence of vacuum inside the package improves image quality. An IR source was used for imaging, and the image quality was tested with the IR bolometer in a vacuum package. The image quality was compared with that of an IR bolometer inside a vacuum chamber. No degradation in image quality was seen after vacuum packaging of the device (Fig. 7-36).

Image of IR source

FIGURE 7-36

IR image taken by vacuum-packaged bolometer.

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Chapter Seven The quality of the image will not change once the vacuum inside the package reaches a value above 1 mtorr. The presence of vacuum improves image quality by not allowing heat loss through the medium. The importance of vacuum inside the bolometer package has been proven, and further studies are required to maintain it for a longer period (e.g., more than 5 years life).

References 1. He, X., Karunasiri, G., Mei, T., Zeng, W. J., Neuzil, P., and Sridhar, U. “Performance of microbolometer focal plane arrays under varying pressure.” IEEE Electron Device Lett. 21:233–235, 2000. 2. Premachandran, C. S., et al. “Design and development of new thermally stable high vacuum IR bolometer package.” 53rd Electronic components Technology conference, ECTC, New Orleans, LA, 27–30 May 2003. 3. Liwei Lin (position paper), “MEMS Packaging at the Wafer Level,” J. Materials Processing and Manufacturing Science, 8(4):347–349, 2000. 4. Gooch, R., Schimert, T., McCardel, W., Ritchey, B., Gilmour, D., and Koz, W. “Wafer-level vacuum packaging for MEMS” J. Vac. Sci. Technol. A, Vol. 17, No. 4, Jul/Aug 1999, pp. 2295–2299. 5. Tominetti, S., and Della Porta, A. “Moisture and impurities detection and removal in packaged MEMS.” Proc. SPIE Vol. 4558, pp. 215–225, Reliability, Testing, and Characterization of MEMS/MOEMS. 6. Neuzil, P., and Ting, M. “Evaluation of thermal parameters of bolometer devices.” Appl. Phys. Lett. 80, Isuue 10, 2002. 7. Radhakrishna, M. V. S., Karunasiri, G., Neuzil, P., Sridhar, U., and Zeng, W. J. “Highly sensitive infrared temperature sensor using self-heating compensated microbolometers.” Sensors & Actuators 79:122–127, 2000. 8. Premachandran, C. S. “MEMS vacuum packaging requirements and challenges.” Circuits & Assembly, April 2002. 9. Premachandran, C. S., Zhang, X., Chai, T. C., Samper, V., and Lim, T. B. “Study on packaging issues using FEA and experimental verification on Si-based microrelay.” Proceedings of SPIE Conference on Micromicromachining and Microfabrication, San Francisco, CA, 2001. 10. Neuzil, P., and Ting, M. “A method of suppressing self-heating signal of bolometers” IEEE Sensors Journal, Vol. 4, No. 2, April 2004, pp. 207–210. 11. Paul W. Kruse, David D. Skatrud “Uncooled Infrared Imaging Arrays and Systems” Semiconductors and semimetals, Vol. 47, San Diego, CA, Academic Press, 1997.

CHAPTER

8

Bio-MEMS Packaging 8.1

Introduction Miniaturization is the recent trend in analytical chemistry and life sciences. In the past two decades, miniaturization of fluid handling and fluid analysis has been emerging in the research field of microfluidics. Microfluidics can be interpreted as the manipulation of liquids and gases in channels having cross-sectional dimensions on the order of 10 to 100 μm. Microfluidics systems are now used widely in micro total analysis systems (μTAS) for DNA and protein analysis, cell sorting, high through-put screening, polymerase chain reaction (PCR) amplification, and capillary electrophoresis.1–7 Integration of microfluidics into analytical systems is advantageous because it decreases costs in manufacture, use, and disposal; decreases time of analysis; reduces consumption of reagents and analytes; reduces production of potentially harmful by-products; increases separation efficiency; and increases portability.8–12 The design and development of a functional microfluidic device must take into account the type of material used to fabricate the device. This material should be compatible with its applications and with sensitive methods of detection, should enable easy interfacing with the user, and should allow integration of other functional components. Furthermore, the material should be relatively inexpensive and compatible with micrometer-scale features and microfabrication methods, especially if the device intended for large-scale applications. The earliest microfluidic systems were fabricated by technology derived from microelectro-mechanical systems (MEMS), namely, photolithography and etching in silicon and glass, because these technologies were already available and highly developed.13–14 However, for the ongoing commercialization of this technology, these fabrication processes represent certain disadvantages. Silicon is a relatively expensive material and has the disadvantage that it is opaque in the visible-ultraviolet (UV) region of the electromagnetic spectrum, thus making it unsuitable for systems that employ optical detection. Although glass is transparent,

353

354

Chapter Eight it is amorphous, and hence vertical sidewalls are more difficult to etch than in silicon. The introduction of microelectronics into life science has fostered many developments in bioapplications. One of the main impacts on biosystems is the miniaturization that is clearly seen in microelectronics. Micro- and nanolevel interactions in biosystems have brought forth new fields of research and new applications. Microfluidics is one of the fast-emerging fields where fluids flow in microchannels and very few dead volumes are present, which eliminate contamination and mixing among the fluids.15 Convergence of microfluidics and microelectronics results in a new kind of device—the microfluidic chip. These chips require channels, reservoirs, and filters to process the fluid. Microfluidic structures are formed on silicon/polymer substrates by micromachining or microstamping. Microfluidic chips offer the ability to work with shorter reaction times and smaller fluid/reagent volumes and promise parallel processes. Major applications of microfluidics occur in clinical diagnostics, drug discovery, bioterrorism, and therapeutics devices. The fluidic components required for clinical diagnostics are different from those required for drug discovery. In most cases, though, a common platform can be used to combine basic modules to implement a microfluidic device for diagnostic application or drug discovery. The lab-on-a-chip (LOC) concept is to realize the functions of a biolaboratory on a silicon chip. These miniaturized biolaboratories are fabricated by a photolithographic process developed in the microelectronics industry to form circuits, chambers, valves, and channels in quartz or silicon substrate. Fluidic samples can be manipulated by placing valves and pumps in the chip, and fluid can be diluted, mixed with other reagents, or separated by other processes on the same chip. A microfluidic chip for DNA extraction and amplification shown in Fig. 8-1. Silicon substrate is used to form microfluidic components in the chip.

Detection unit (optical/electrical) PCB Electrical I/O + controller Microvalve Microfluidic chip Fluidic cartridge Cross section of disposable package

Fluidic controller External detect and control system

FIGURE 8-1 Schematic drawing of an integrated biomicrofluidic package for a DNA LOC application.

Bio-MEMS Packaging Packaging of the microfluidic chip is an important factor that completes the connection between the microfluidic chip and other systems, such as fluidic, electrical, optical, etc. applications. Since microfluidic chips interact with fluidic samples, the packaging of such chips also must meet the fluid flow requirements. In microfluidic packaging, polymers generally are used for encapsulation. Material compatibility based on biology and chemical stability based on the reagents are key parameters in package development.16 The challenge in microfluidic packaging is the integration of different systems into a common platform, and microfluidic system with multiple fluids or reagents must have a mechanism to control dispensing of each fluid or reagent so as to follow individual flow protocols. Microfluidic systems require fluidic dispensing control to realize specific protocols. Fluidic dispensing control includes control of flow sequence, flow duration, flow direction, and flow rate. At the same time, reagent cross-mixing resulting in contamination in the microfluidic system should be avoided. Certain other microfluidic systems require prestorage of reagents in integrated reservoirs. Besides storage functions, these reservoirs also need a dispensing mechanism that pushes the reagents into the microfluidic system during operation. After the reagents are fully dispensed, the dispenser should close to avoid flow of other reagents into the reservoir.

8.2

Bio-MEMS Chip In microfluidic chips, functions that are done in a laboratory, such as sample preparation, amplification, and detection, are shrunk onto a tiny silicon chip known as lab-on-a-chip (LOC). In LOC, the functions are integrated either into a single or multiple chips based on the application. A sample preparation chip is shown in Fig. 8-2, and it is

PCR

Filter Binder

FIGURE 8-2 Microfluidic chip for DNA/RNA extraction. (Courtesy: SiMEMS Bio Singapore)

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356

Chapter Eight used to extract DNA/RNA from the samples such as blood, saliva, and body tissues. The sample preparation chip is fabricated on a silicon wafer with a standard MEMS process. Chambers are formed on the silicon chip by bulk micromachining. The first chamber in the chip is a filter where the particles that are not of interest to the study are filtered. Tiny pillars are formed in the cavity of this chip, and the gaps between the pillars are determined based on the sizes of the particle that are to be filtered out. The advantage of having smaller chambers is that the sample volume used for extraction can be small compared with sample volumes used in the standard laboratory. The principle of this chip is to filter unwanted particles from the injected sample and bind the necessary particles such a virus or bacteria on the binder surface of the chip. After filtering the particles from the injected sample, the next chamber the filtered sample passes through is the binder, provided that the sample used for extraction has been made smaller. The chip consists of a filter, a binder, and a PCR unit. The DNA LOC is fabricated on a silicon substrate. The filter, binder, and PCR chamber are formed by bulk micromachining. The silicon DNA LOC wafer is bonded to a glass wafer by anodic bonding. The bonding process is conducted at the wafer level with a wafer bonder. A glass wafer is used so that an optical approach can be used for detection. A filter is used to filter the particles from the lysis sample which contains many components from the nucleus other than DNA/RNA, and a binder is used to bind the DNA onto the chip. The bound DNA particles are removed from the chip by a process called elution. The collected elution sample containing DNA particles is mixed with the primer and injected into the PCR chamber of the chip for amplification. Different reagents for this particular chip used in Fig. 8-2 are used for various steps in the DNA/RNA extraction process and are listed in the Table 8-1.

Reagents in Reservoir

Required Flow Rate (ml/min)

Lysed blood

12

Reagent1

50

Reagent2

50

Reagent3

100

Reagent4

2

TABLE 8-1 Reagent Protocol for the DNA/RNA Extraction

Bio-MEMS Packaging

8.3

Microfluidic Components 8.3.1

Microfluidic Cartridge

Packaging of microfluidic chips is an important factor that supports chip function by dispensing and controlling fluid flow to accomplish a particular bioprotocol. Fluid control includes controlling flow sequence, flow duration, flow direction, and flow rate. The package needs to have a mechanism to control each fluid/reagent in the order required by the protocol and, at the same time, to prevent reagents from cross-mixing. The package also completes the connection between the microfluidic chip and other systems, such as fluid source, electrical source, optical sensor, etc. (Fig. 8-3). In microfluidic packaging, polymers generally are used for encapsulation. Packaging material is based on biocompatibility and compatibility with the reagents used for extraction.17 A biomicrofluidic package with three PDMS substrate layers fabricated by casting from an acrylic mold is described . The lower substrate consists of the 500-μm-wide microchannels, whereas fluid inlets and outlets of the microchannels are fabricated on the upper substrate. The substrate designs are described in Figs. 8-4 and 8-5. The complete package includes a third PDMS substrate layer consisting of four reservoirs designed to contain four different types of chemical reagents required for biologic testing, and the entire package is sealed in a PDMS membrane. A cross-sectional view of the package is shown in Fig. 8-6. A vertical channel located at the bottom

Input reservoirs R1

R2

Inlet

R3

R4

Valve

Microfluidic chip

Switching valve PDMS/other material

FIGURE 8-3 valves.

R1′

R2′

Output reservoir

Schematic view of microfluidic package with reservoirs and

357

358

Chapter Eight Reservoirs

FIGURE 8-4 Design of lower PDMS substrate. Inlet port

Outlet ports

FIGURE 8-5 Design of upper PDMS substrate.

PCB

Reservoir Valve

Glass cap Microfluidic chip

FIGURE 8-6

Cross section of the package with fluidic chip.

Tape

Bio-MEMS Packaging From reservoir

FIGURE 8-7 Structure of a capillary-force passive valve. Microchannel

Meniscus

Valve gap To Microfluidic chip

Fluid flow Reagent 4 Reagent 3 Port

Reagent 1

Reagent 2

Chip

Sample Inject

FIGURE 8-8 Top view of the substrate with channels and port for injection of different reagents.

of the reservoir connects each reservoir to the microchannels. In addition, a passive valve is embedded in the vertical channel, and it functions via pressure activation (Fig. 8-7). During storing conditions, the valve is closed to prevent reagent flow from the reservoir to the cartridge channel. Fluid is injected into the reservoirs by external actuation, and during the process, membrane deformation is observed, and when the fluid pressure in the reservoirs increases and reaches the threshold pressure, the valve opens, and fluid passes through the valve and flows into the cartridge, as illustrated in Fig. 8-8.

8.3.2

Biocompatible Polymeric Materials

Currently, polymers are the most promising substrate materials for microsystem technology because they are applicable for massreplication technologies such as injection molding and hot embossing,

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360

Chapter Eight as well as for methods of rapid prototyping, such as casting and laser micromachining. They can be classified into three main categories based on their molding behavior. (1) Thermoplastic polymers consist of unlinked or weakly linked chain molecules. At temperatures above Tg, these materials become plastic and can be molded into specific shapes, which they will retain after cooling below Tg. (2) Elastomeric polymers are also very weakly cross-linked polymer chains. When an external force is applied, the molecular chains can be stretched, but they relax and return to their original state once the force is removed. In addition, elastomers do not melt before reaching their decomposition temperature. (3) The cross-linkages in duroplastic polymers are stronger; hence, they are more brittle and harder than thermoplastic polymers. Therefore, molecular movement is sufficient to cause a change in shape; thus, they have to be cast into their final shapes.

Polydimethylsiloxane (PDMS) PDMS belongs to a class of soft polymers also known as elastomers and is an excellent material for the fabrication of microchannel systems suitable for use with biologic samples in aqueous solution. The advantages of using PDMS for microfluidic applications include the following: (1) Features on a micron scale can be reproduced with high fidelity in PDMS by replica molding; (2) the material is optically transparent down to 280 nm, making it applicable for detection schemes; (3) the material has low curing temperatures; (4) it is biocompatible and nontoxic, which is important for devices implanted in vivo; (5) the material allows both reversible and irreversible sealing because it makes van der Waals contact with the surface or bonds covalently following exposure to air; and (6) its elastomeric properties allow it to conform to smooth, nonplanar surfaces and releases from delicate features of the mold without damage. Therefore, PDMS has been used traditionally in implantable drug-delivery devices, device coatings, gas-exchange membranes, ocular lenses, and orbital implants.

Polymethyl Methacrylate (PMMA) PMMA, commonly known as acrylic, is a thermoplastic produced by block polymerization of methyl methacrylate (PMMA) monomers through a free-radical mechanism. PMMA was seen originally as a replacement for glass in a variety of applications and is currently used extensively as bone cement and ocular lenses. PMMA demonstrates attractive characteristics for biomedical applications because of the following properties: PMMA is a glassy polymer with amorphous structure that exhibits low water absorption and possesses a low density of 1.19 g/cm3. PMMA also has high mechanical strength, good dimensional stability, with a high Young’s modulus and good hardness with low elongation at break. PMMA is resistant to aliphatic hydrocarbons, cycloaliphatic compounds, fats, and oils, as well as to

Bio-MEMS Packaging dilute acids at temperatures of up to 600°C. Chlorinated aliphatic hydrocarbons, ketones, alcohols, ethers, esters, aromatics, petrol, spirit, nitrocellulose varnishes, and certain plasticizers may cause PMMA to swell or produce stress cracks. Furthermore, PMMA displays excellent optical properties, with high light transmittance (~92 percent in the infrared region). In addition, PMMA can be injectionmolded at relatively good flow rates (~25 g/10 min). Current research shows that PMMA appears to be the most suitable polymer for laser ablation, particularly because of its high transparency and also because of its low heat capacity with a low heat conductance, which means that any absorbed heat will result in a rapidly rising temperature. During laser ablation, when PMMA heats up, it remains in the solid glassy state until it reaches its glass-transition temperature of about 1150°C. At temperatures higher than Tg, PMMA becomes easily moldable and rubbery. If more energy is added, then the thermal decomposition of PMMA begins, where long polymer chains are broken into smaller ones by a process known as depropagation, which is initiated by random chain breaking and end-chain scission. This spontaneous and random chain breaking finally leads to the development of monomers, which are volatile, thus resulting in the creation of microstructures in the polymer.

Cyclic Olefin Copolymer (COC) Cyclic olefin copolymers comprise a new class of polymers based on cyclic olefin monomers and ethene. Owing to the random or alternate attachment of the bulky cyclicolefin units to the polymer backbone, the copolymer becomes amorphous and displays properties of high glass-transition temperature, optical clarity, low shrinkage, low moisture absorption, and low birefringence. Currently, there are several types of commercial COCs on the market that are based on different cyclic monomers and polymerization methods. COCs can be produced either by chain copolymerization of cyclic monomers such as norbornene with ethene or by a ring-opening metathesis polymerization of various cyclic monomers followed by hydrogenation. COCs offer attractive properties that make them highly suitable for biomicrofluidic applications. COCs can be injection-molded at very high flow rates (~55 g/10 min) as compared with other polymeric materials. The lower viscosity of COCs at processing temperatures allows for lower injection pressures and better fills. COCs also exhibit extremely low water absorption (hydrophobic), typically lower than PC and PMMA. Most metallic films exhibit excellent adhesion to the COC substrate. Furthermore, COCs are resistant to most polar solvents such as acetone, methanol, and isopropyl alcohol, thus making them suitable for use with standard lithography techniques. In addition, COCs also possess excellent optical properties, which is advantageous for fluorescencebased biochemical analyses and biooptical applications.

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Chapter Eight

Microfluidic Packaging 8.4.1

Polymer Microfabrication Techniques

Polymeric microfabrication methods can be divided into two categories: replication technologies and direct techniques. In general, replication technologies (i.e., casting, injection molding, and hot embossing) represent the commercial pathways for the microfabrication of fluidic devices, providing the potential for high-volume production and realizing the possibility of disposable μTAS, because the principles behind these technologies are already well known in the macro world. Basically, the underlying principle is the replication of a microfabricated mold tool, which represents the inverse structure of the desired polymer structure. The expensive microfabrication step is therefore only necessary once for this master structure, which then can be used to replicate the polymeric substrates many times. Besides cost advantages, these replication techniques also allows the freedom to design various geometries using different microfabrication technologies. However, the interface chemistry between the tool material and the substrate polymer is a critical factor affecting the demolding step in the replication process and thus limiting the type of polymeric materials that can be used. In contrast to replication technologies that allow repetitive production of a polymer device from a single mold, direct techniques such as laser micromachining allow individual micromachining of each single device. While this technique permits rapid fabrication of single devices because no previous master fabrication step is involved, fabrication throughput is limited by the fabrication time of each individual device.

8.4.2

Replication Technologies

Casting Method Casting of silicone-base elastomers is a process that has found widespread use in the academic world. The earliest mention of a miniaturized separation device based on a polymer was made by Ekstrom and colleagues in 1990. Casting generally offers more flexibility and lower-cost access to planar microchannel structures, and the material involved, usually PDMS of the type SLYGARD 184, offers good optical properties with high transparency above 230 nm and little autofluorescence. During this process, a mixture of PDMS prepolymer and its curing agent is poured over molding templates. These templates are made by either silicon surface micromachining or lithography patterning using photoresist and can be surface modified for better mold release. After the curing process is completed, the soft elastomer copy can be easily peeled off the mold. These replicated

Bio-MEMS Packaging microstructures then can be placed against a planar surface such as a glass slide, a plastic sheet, or another elastomeric design to form closed channels.

Injection Molding Injection molding is a technique that has been well established in the macroscopic production of polymer parts for decades. This technique can be applied on a micro scale by employing a variotherm process The principal process steps include the following: (1) The mold cavity equipped with a microstructured tool (mold insert) is closed, evacuated, and heated above the glass-transition temperature of the polymer; (2) an injection unit heats the polymer up and presses the viscous polymer into the mold; and (3) the polymer is cooled down below its glass-transition temperature and demolded from the tool. This cyclic temperature control is known as a variotherm. Injection molding is used commonly for micromolding of thermoplastics such as COC and PMMA.

Hot Embossing Currently, hot embossing is the most widely used replication process to fabricate channel structures for microfluidic applications. The microfabrication process of hot embossing is as follows: (1) A thermoplastic film is inserted into the molding machine; (2) a microstructured tool (mold insert) in an evacuated chamber is pressed with high force into the film, which has been heated above its softening temperature (the mold insert is filled with the polymer material, which replicates the microstructures in detail); and (3) the setup is cooled, and the mold insert is withdrawn from the polymer. This technique is commonly applied for microchannel fabrication in PMMA.

8.4.3

Overview of Existing DNA and RNA Extractor Biocartridges

DNA is the chemical inside the cell nucleus that carries the genetic instructions for making living organisms. DNA is a linear molecule made up of nucleotides organized in two chains that form a twisting double helix. The order in which the four different nucleotides (i.e., adenine, thymine, guanine, and cytosine) occur in the DNA of a gene determines the protein formed, just like letters of the alphabet determine words and sentences. DNA is a vast chemical information database. RNA delivers DNA’s genetic message to the cytoplasm of a cell, where proteins are made. In certain viruses, RNA rather than DNA serves as the genetic material. With the rapid evolution of modern molecular biology, it is necessary for the concurrent development of specific bioanalytical tools to efficiently and rapidly analyze entities such as proteins, cells, nucleic acids, and bacteria. However, many biologic samples containing cells and spores are potentially dangerous

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Chapter Eight and require careful handling during laboratory analysis. Consequently, pretreatment of biologic samples prior to analysis within microfluidic systems is an area that attracts great interest.

8.5

Fabrication of PDMS Layers PDMS is fabricated by a casting process and is prepared using the SYLGARD 184 silicone elastomer kit manufactured by Dow Corning, which consists of the SYLGARD 184 silicone elastomer base and the SYLGARD 184 silicone elastomer curing agent. The elastomer base and curing agent are added precisely, with the aid of an electronic balance, based on a mass ratio 10:1 into a Styrofoam cup. The mixture is stirred continuously for about 1 minute to ensure uniform mixing. This mixture then is placed in a vacuum flask to degas for approximately 1-1/2 hours to get rid of the air bubbles introduced during the mixing process. Meanwhile, the acrylic molds are washed thoroughly with isopropyl alcohol and dried using a nitrogen-gas air gun. Subsequently, the PDMS mixture is poured carefully into acrylic molds of different designs that are negative replicas of the desired microstructures. Care must be taken to ensure that minimal air bubbles are introduced or trapped within the molds because they will interfere with the quality of the PDMS layers cast after the curing process. In addition, a flat surface such as a glass plate or a silicon wafer is used to check the surface levelness of the PDMS in the molds before placing them in the curing oven. The physical state of PDMS before curing is a viscous liquid. The process of curing modifies the physical properties of the two-part silicone elastomer, with a gradual increase in viscosity, followed by gelation, and eventually, the liquid mixture cures into a flexible solid elastomer. The curing conditions need to be preset before the curing process. For curing PDMS, the process follows a three-step program, including the temperature ramp-up, constant temperature, and temperature ramp-down. The curing conditions are 400 to 800°C for 1-1/2 hours for the first step, 800°C for 3 hours in the second step, and 800 to 400°C for 30 minutes in the final step. At the end of the curing process, step 3, the molds are taken out of the oven, and the cured PDMS layers are peeled out of the molds carefully with the aid of penknives and tweezers. The acrylic molds then are cleaned and are available for repetitive casting of identical PDMS layers.

8.6 Assembly of PDMS Microfluidic Packages After fabrication of the PDMS layers of different designs, those PDMS layers are cleaned thoroughly with isopropyl alcohol (IPA) and dried using an air gun. For samples that will be tested with biologic reagents, an additional step of rinsing the PDMS layers with distilled

Bio-MEMS Packaging water is necessary to remove any remaining IPA, which is an organic chemical that may interfere with the functionality and efficiency of the biocartridge during biologic testing. The cleaned PDMS layers then are examined under the microscope to ensure that the microstructures are completely fabricated and that no particles are embedded within the microchannels because any minute particles in the microchannels may impede fluid flow and result in a pressure buildup in the package and subsequent leakage. Any particle found is removed carefully using tweezers, after which the PDMS layers are cleaned again using the cleaning reagents mentioned earlier. Next, we will need to bond two or more PDMS layers together to assemble a package. However, unmodified PDMS presents a hydrophobic surface, so reversible or irreversible sealing must be done to bond the two layers together. Reversible sealing by weak van der Waals forces is watertight but is unable to withstand pressures greater than approximately 5 lb/in2 (psi). Silicone adhesive tape also provides reversible sealing with a stronger seal, and the seal is waterproof. On the other hand, irreversible sealing can be performed by exposing the PDMS layers to oxygen plasma. This treatment generates hydrophilic silanol groups (Si–OH) on the surface of the PDMS by oxidation of hydrophobic methyl (CH3) groups. While this sealing process is simple and reproducible, technical agility is essential because the two surfaces to be bonded must be brought into conformal contact within 1 minute of oxidation owing to the fact that the surface of the oxidized PDMS reconstructs quickly in air. On bonding, covalent bonds (–O–Si–O–) are formed, thus accounting for the irreversible sealing effect. Contact with water or polar organic solvents maintain the hydrophilic nature of the surface indefinitely. Empirical evidence has shown that oxidative sealing works best when the samples and the chamber are clean, the samples are dry, the surfaces are smooth on the micron scale, and the oxidized surfaces are not mechanically stressed. From experimental experience, it has been found that oxygen plasma treatment followed by adhesive bonding creates a stronger adhesion between the bonded PDMS layers. The operating parameters for the plasma machine are power in watts, type of plasma, plasma flow rate in standard cubic centimeters per minute, and plasma duration in seconds. The surfaces to be bonded are placed face up into the chamber. In addition, the glass face of the biochip is also oxidized in the same way. After plasma oxidation is completed, the two hydrophilic surfaces are bonded together with biocompatible silicone adhesive tape. These adhesive tapes has the same layout as the PDMS layers, where the holes on the adhesive tape align with the inlet/outlet holes of the biochip, as well as the entrance and exit ports of the microfluidic chambers. Subsequently, the biochip is attached to the package using the SRT Sierra chip-bonder machine. The method of operation of the SRT machine is as follows: The pickup tool picks up the biochip by means

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Chapter Eight of vacuum. The force and pickup height settings can be calibrated based on chip size and thickness. A CCD camera attached to the arm of the machine captures the chip image and displays it on the computer screen. The chip inlet and outlet then can be aligned with the inlet and outlet ports on the PDMS by adjusting the brightness, contrast, rotation, and xy directions controls. These assembly procedures are repeated for subsequent attachment of PDMS layers. After complete assembly of the package, the package is cured in the curing oven at a constant temperature of 80°C for about 1 hour to improve the adhesion between the different layers. The pin valves then are placed vertically into each reservoir, and biologic reagents or colored fluids are added in known volumes. The reservoirs then are sealed by a thin layer of PDMS membrane using adhesive tape, thus forming a closed micro-total-analysis system. The completely assembled biocartridge then is allowed to age overnight to further increase the adhesion strength so that the PDMS layers are securely bonded together.

8.6.1

Microfluidic Package without Reservoirs

Microfluidic structures are formed on the PDMS material by casting. By micromachining, a mold is made of acrylic material. Since the microfluidic package has three layers of substrate, three different acrylic molds are fabricated. PDMS material is mixed with a curing agent in a 10:1 ratio and placed in the mold for substrate formation. The mold with the PDMS material is kept in a vacuum oven at 80°C for 4 hours. After cooling, the substrate is removed from the mold. A closed fluidic channel is formed by bonding the lower PDMS substrate with a horizontal channel onto the upper PDMS substrate with vertical ports. A 500-μm channel is formed on the PDMS substrate and is connected to the chip inlet port (Fig. 8-9). In this package,

Fluidic ports

Microfluidic channel on PDMS

FIGURE 8-9

Lower and upper PDMS substrates with fluid channel.

Bio-MEMS Packaging

Ports for microfluidic chip

Through hole for ports

FIGURE 8-10 Double-sided tape with fluid ports for PDMS substrate bonding.

a medical-grade adhesive tape is used to bond the PDMS substrates together (Fig. 8-10). Different reagents are connected serially, and the device starts by injecting the biosample, blood, and subsequently dispensing reagents, from reagent 1 to reagent 4. Reagents 1 to 3 are used to remove the unwanted particles from the chip, keeping the bound DNA on the chip. The last reagent helps to unbind the DNA from the chip. Each reagent flows with a different rate to enhance the binding and unbinding processes of the DNA.18 In package design, the main points to be addressed are as follows: (1) The package should be disposable and biocompatible; (2) during actuation, the actuator should not come in contact with the reagents; (3) there needs to be an integrated valve to start/stop liquid dispensing; (4) no cross-mixing should be allowed before a reservoir dispenses liquid; (5) no backflow should be allowed to a reservoir after dispensing; and (6) the flow rate should be controllable during dispensing. The double-sided adhesive tape used here is cut only at the inlet and outlet ports and not at the channels. No cut made on the tape where the channels occur on the PDMS to eliminate any fluid leak owing to mismatch or tolerance error. The assembly process starts with cleaning of the substrate by the oxygen plasma treatment process. Plasma treatment enhances bonding of the PDMS substrates. Since PDMS is a hydrophobic substrate,

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Chapter Eight it is difficult to bond PDMS to another substrate. The oxygen plasma treatment process causes the PDMS substrate to become hydrophilic, and thus bonding can be achieved either by direct bonding or by using an intermediate layer. The tape used for substrate bonding should be biocompatible and PCR-compatible. The bonding strength of the PDMS substrates has been quantified by the pull test and the high-pressure fluid injection test to confirm that there is no leak. The DNA chip is also bonded to the PDMS substrate using this adhesive tape. The microfluidic chip is attached to the PDMS substrate using a pick-and-place machine (Fig. 8-11). The inlet and outlet holes are aligned with the PDMS substrate holes using a vision system. Doublesided adhesive tape is placed between the chip and the substrate, and a force is applied on the chip. Alignment of the channels with chip inlets and outlets is critical to avoid any leakage during the fluid test. PCR works on a temperature cycle. Heaters are provided around the PCR chamber to maintain a uniform temperature across the chamber. The heaters on the microfluidic chip are connected to the printedcircuit-board (PCB) pads by wire bonding. The pad traces are connected to the pins attached at the end of the PCB (Fig. 8-12). The challenges in developing a microfluidic package for a DNA LOC are low dead volume, no cross-mixing of reagents, and no fluid leakage during operation. Dead volume in the fluid package is

Pickup tool with microfluidic chip

Fluidic channel substrate

FIGURE 8-11

DNA chip is attached to PDMS substrate.

PDMS microfluidic substrate with microchannel

Sample inlets

Sample outlets

Microfluidic chip from SiMEMS Singapore

FIGURE 8-12

PCB substrate for electrical connection to PCR chamber

Microfluidic package with fluid and electric interconnections.

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Chapter Eight minimized by shortening fluid channel length, minimizing crossing of fluid channels, and proper design. Cross-mixing of fluids is avoided by proper placement of valves. Strong bonding between the substrates eliminates fluid leakage along the channels.

8.6.2

Development of Reservoir and Valve

To store reagents inside the package, reservoirs are fabricated on the package, and this is showed in Fig. 8-13. Reservoirs are design based on the volume required based on the DNA testing protocol. A thin membrane of PDMS is bonded on top to seal the reservoir and is shown in Fig. 8-14. A valve is created at the bottom of the reservoir to control fluid flow from the reservoir to the chip.

Piston depression on membrane

PDMS membrane Reservoir block

PDMS block Microvalve

FIGURE 8-13

Cross-sectional view of a reservoir and a valve.

Membrane Reservoir

FIGURE 8-14 Reservoir chamber with membrane attached.

Bio-MEMS Packaging

8.7

Self-Contained Microfluidic Cartridge 8.7.1

Microfluidic Package with Self-Contained Reservoirs

Packaging of microfluidic chips is an important factor that supports chip function by dispensing and controlling fluid flow in order to realize specific bioprotocols. A schematic view of the microfluidic package is shown in Fig. 8-15. Fluid control includes controlling flow sequence, flow duration, flow direction, and flow rate. The package needs to have a mechanism to control each fluid/reagent based on the protocol. At the same time, reagents must be protected from crossmixing and contamination. The package also completes the connection between the microfluidic chip and other systems, such as fluid source, electrical source, optical sensor, etc. In microfluidic packaging, polymers generally are used for encapsulation and shown in Fig. 8-16. Packaging material is based on biocompatibility and compatibility with the reagents used for the extraction of the key components such as DNA and RNA.19

Reservoir Design The reservoir has a conically shaped cavity covered with a thin layer of flexible film, as shown in Fig. 8-17. The actuator diameter is the same as the bottom diameter of the reservoir. The volume of dispensed liquid is equal to the volume of film deformation, as shown by the dashed line in the figure. Consider that the volume of liquid inside the reservoir is V, the top radius of the reservoir is R, the height

External actuator

2 1

3

4

Microfluidic chip PDMS/plastics substrate

FIGURE 8-15

Schematic view of an integrated biomicrofluidic package for DNA.

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Chapter Eight

Reservoirs filled with reagents

Pin valve

Microfluidic chip

Microfluidic channel

FIGURE 8-16 Microfluidic package with reservoirs for LOC applications.

Piston Thin PDMS membrane

r

R h r r

Pin valve

FIGURE 8-17 External actuator acting on reservoir.

of the reservoir is h, and radius of the actuator is r. Then the relation between flow rate and actuator speed can be written as21 V = (R2 + rR + r2) × h × π/3 dV/dt = [(R2 + rR + r2) × (π/3)] × dh/dt Since dV/dt = Q, the flow rate, and dh/dt = S, actuator speed, Flow rate Q = constant × actuator speed (s)

Bio-MEMS Packaging Therefore, the liquid flow rate is proportional to the actuator speed. The advantage of the conically shaped reservoir is that it allows a minimum dead volume and easy membrane deformation during actuation (Fig. 8-18) compared with other reservoir shapes (Figs. 8-19 and 8-20).

FIGURE 8-18 There is no dead volume after completing actuation.

FIGURE 8-19

Cylindrical reservoir with small piston → large dead volume.

FIGURE 8-20 membrane.

Cylindrical reservoir with big piston → large stress on

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Chapter Eight FIGURE 8-21 Differential volume with respect to time.

Flow rate Q (ul/min)

Q1 Q1 2

T1

FIGURE 8-22 Differential speed with respect to time.

T2

Time

Speed (mm/min)

S1

S1 2 T1

T2

Time

A differential flow of fluid can be created using an external actuation method on a conically shaped reservoir. During actuation of the fluid, the speed of actuation can be changed, and hence a different flow rate also can be achieved (Figs. 8-21 and 8-22).

8.7.2

Pin-Valve Design

A pin valve is the main control component of the microfluidic package, and it controls the flow into the DNA chip. It looks like a thumbtack with a round cap. The main body is a hollow needle with a sidehole and a slant tip. Liquid flows into the hollow needle from sidehole to the tip. The slant tip pierces the bottom of the reservoir during the initial stage of actuation (Fig. 8-23). As shown in Fig. 8-24, the reservoir bottom has a blind via to locate the pin valve. The blind via faces the port of the fluid channel. The blind via is not connected to the fluid channel during reagent storage. The blind via opens when the pin valve moves down and pokes through the reservoir bottom.

Bio-MEMS Packaging FIGURE 8-23 Pin valve with sidehole and slant tip.

Seal cap Inlet hole

Slant tip & exit hole

Fluidic flow direction

Blind via Fluidic channel

Reservoir Port layer

FIGURE 8-24 Pin valve closed.

The pin is tightly fitted to the bottom of the reservoir so that the pin tip is the only outlet of the reservoir. The length of the pin is calculated based on the distance traveled for pin to open the valve, close the valve, and dispense the required amount of reagent.

8.7.3

Fluid Flow-Control Mechanism

During the reagent storage period, the pin valve is located at the reservoir bottom and held firmly by the blind via hole in the reservoir. The reagent is filled into the reservoir, which is sealed with a thin rubber membrane. During this storage period, the valve is closed, and the fluid cannot flow into the channel layer, as showed in Fig. 8-24. The next step is that the actuator moves down to the reservoir and pushes the reservoir membrane down, at the same time pushing the pin valve down. The pin starts to move down and pokes through the reservoir bottom and blind via to open the port. The fluid starts to flow through the pin valve to the channel port and then to the chip (Fig. 8-25).

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Fluid start flowing through the inlet hole

FIGURE 8-25 Pin valve open.

As shown in Fig. 8-26, the fluid flows continuously through the channel. A constant flow rate is achieved by keeping a constant actuation speed. The actuator keeps pushing the pin until the pin tip is inserted into the bottom PDMS layer, and at this point, the valve is closed. The pin-valve bottom is blocked. The pin cap reaches the bottom point of the reservoir. The pin sidehole is sealed in the bottom of reservoir. The three levels of sealing are shown in circles in Fig. 8-26. After the valve closes completely, there is no path for the fluid to reenter the reservoir from the channel. When subsequent reagents are dispensed into the channel, this valve closure prevents cross-mixing of reagents between the reservoirs. A round-about channel design is implemented on the fluid channel to ease fluid flow when the pin valve is closed at the end of actuation (see Fig. 8-27). The valve and round-about port design can be used in multiple-reservoir structures (Fig. 8-28). It controls the fluid dispensing sequence of multiple reservoirs so that various types of reagents can be used.

Port layer

FIGURE 8-26

Pin valve closed by three levels of sealing.

Bio-MEMS Packaging

Airtight seal

No backflow

Substrate To chip

To chip

(No backflow, no dead volume, no cross-mixing)

FIGURE 8-27 Fluid flow in round about channel and with no backflow.

R1-1

R1-2

R1-3

R 2-1

R2-2

R2-3

Chip

R 3-1

R3-2

R3-3

FIGURE 8-28 Cartridge with multiple reservoirs.

8.8

Fabrication 8.8.1

Substrate Fabrication

Fabrication of the cartridge requires bonding of different layers of PDMS substrates. A mold is fabricated in acrylic material based on the reservoir and fluid channel design. The PDMS is mixed in a ratio of 10:1 and is poured into the acrylic mold. The filled mold is cured in

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Chapter Eight an inert oven. The cured PDMS is removed from the mold and is ready for assembly. The microfluidic cartridge consists of three substrates—reservoir substrate, vertical-port substrate, and channellayer substrate—and is shown in Fig. 8-29. The assembly process starts with cleaning of the substrate by the oxygen plasma treatment process.17 Since PDMS is a hydrophobic

Tape: membrane to reservoir

Membrane

∅12

∅16

∅12

∅14 (a)

(b) Tape: Reservoir to port layer Reservoir substrate

(c)

(d) Tape: chip to port layer substrate Vertical port substrate

(e)

(f) Fluidic channel substrate

Tape: port substrate to channel substrate

(g)

(h)

FIGURE 8-29 Substrates (fabricated in PDMS) and tape.

Bio-MEMS Packaging substrate, it is difficult to bond PDMS to another substrate. As a result of the oxygen plasma treatment process, the PDMS substrate becomes hydrophilic, and bonding can be achieved either by direct bonding or by using an intermediate layer. The tape used for substrate bonding should be biocompatible and PCR-compatible. The adhesive tape used in this study does not react with the fluids being used.17 The bonding strength of the PDMS substrate has been quantified by the pull test and the fluid injection test. Purified water at a pressure 100 kPa was injected into the fluid channel, and it was confirmed that there was no leak. The chip is attached to the PDMS substrate using a pick-andplace machine. The inlet and outlet holes are aligned with the PDMS substrate holes using a vision system with a tolerance of alignment of ±50 μm. Double-sided adhesive tape is placed between the chip and the substrate, and a force is applied on the chip. Alignment of channels with the chip inlets and outlets is critical to avoid any leakage during the fluid test. The pin valves are inserted into the reservoirs. The reagent volumes are measured using a pipet, and each reagent is placed in a reservoir. Finally, the reservoirs are covered with a thin, highly elastic membrane that is bonded using double-sided adhesive tape. The package is ready for microfluidic testing and is shown in (Fig. 8-30). The reservoir has a conically shaped cavity covered with a thin layer of flexible film, as shown in Fig. 8-31. The actuator diameter is same as the bottom diameter of the reservoir. The volume of liquid dispensed is equal to the amount of membrane deformation.

FIGURE 8-30 Microfluidic package filled with liquid.

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Blind via Fluidic channel

Reservoir Port layer

FIGURE 8-31 Original design of the reservoir membrane.

The reservoir design has been modified to reduce the valve opening time. The shape of the reservoir has been kept the same, whereas the pin-valve supporting part has been changed. An injection-molded rubber needle plug is used to secure the pin valve in the reservoir. Changing to a needle plug helps the pin valve to stay straight and keeps the valve opening time the same across the other reservoirs. A blind via hole is made in the needle plug to secure the pin valve. Final optimization of the valve opening is accomplished by inserting a piece of aluminum foil between the needle plug and the channel layer, and this is shown in Figs. 8-32 and 8-33. The force required to punch through the aluminum foil is small compared with that required for the thin PDMS membrane used in the first version of the reservoirs. The modifications finally reduced dispensing time by 50 percent, and this eventually reduced the cycle time of the protocol used for DNA extraction in the cartridge.20

Needle plug Al foil Through via Base layer

FIGURE 8-32 Design optimization of reservoir with aluminum foil and external actuator.

Bio-MEMS Packaging

FIGURE 8-33 Modified and optimized design of the reservoir.

8.8.2

Material Selection for the Reservoir Membrane

A good elongation membrane helps to minimize the push force required by the actuator so that actuator size can be reduced. Four biocompatible materials were selected for this study. They are made into 0.5-mm-thick membranes that are used to seal the reservoirs of the sample cartridges. Each sample cartridge has four reservoirs filled with a high salt solution, ethanol, air, and water, respectively. The sample cartridges are fixed on an Instron push-test machine by clamping on the bottom fixtures. The bottom load cell is nonmovable. A computer causes the top actuator to move downward and press on the membrane of each reservoir and dispense the fluid from reservoir. During the pushing action, the displacement of the top actuator and the load are transiently recorded. The membrane material is selected based on the smallest force in Tables 8-2 through 8-5. Different mixing ratios were tried for the PDMS-based membrane, and selected silicon rubber materials were tried as well. Based on this analysis, it is concluded that the lowest actuation force is desirable for the current package application. Thus silicon rubber is found to be suitable.

8.9

Permeability of Material Storing reagents inside the cartridge for a long time is difficult because it demands a minimum shelf life of 6 to 12 months. Since some of the reagents are highly volatile, any pinhole in the reservoir material can easily cause the reagent to evaporate or drain within a short time. A permeability study was done to understand how well the reservoir and membrane materials performed. The same thickness of both materials was used for permeability measurements. Polypropylene has better permeability than rubber

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Chapter Eight Ratio (PMDS:Curing Agent) = 10:1 Type of Fluid

High Salt

Ethanol

Air

Water

Speed (mm/min)

0.513

0.628

0.853

0.0251

Extension (mm)

Force (N)

0

0

0

0

0

1

1

0.31

1.31

1.15

2

3.24

1.21

1.6

3.85

3

6.09

2.91

3.4

7.35

4

8.99

4.81

5.6

11.15

5

12.15

6.76

7.25

15.3

6

16.2

8.86

10.4

20.59

7

21.69

11.47

13.2

27.35

8

28.14

15.7

16.65

35.05

9

35.95

22.6

22.06

40.1

TABLE 8-2 Actuation Force on Membrane 10:1 PMDS

Ratio (PMDS:Curing Agent) = 15:1 Type of Fluid

High Salt

Ethanol

Air

Water

Speed (mm/min)

0.513

0.628

0.853

0.0251

Extension (mm)

Force (N)

0

0

0

0

0

1

0.8

0.3

0.31

0.74

2

2.3

1

0.86

2.19

3

4.15

2.56

1.91

4.19

4

5.85

4.26

3.16

5.99

5

7.4

5.91

4.41

7.54

6

8.84

7.46

5.56

8.99

7

10.79

8.81

6.66

10.59

8

13.29

10.11

7.71

12.49

9

16.84

11.76

8.68

17.4

TABLE 8-3 Actuation Force on Membrane 15:1 PMDS

Bio-MEMS Packaging Ratio (PMDS:Curing Agent) = 20:1 Type of Fluid

High Salt

Ethanol

Air

Water

Speed (mm/min)

0.513

0.628

0.853

0.0251

Extension (mm)

Force (N)

0

0

0

0

0

1

0.7

0.37

0.3

1.7

2

1.85

1.22

0.8

2.8

3

3.25

2.47

1.7

4.5

4

4.65

3.87

2.85

6

5

5.85

5.28

4.05

7.3

6

6.9

6.43

5.2

8.65

7

8.2

7.53

6.3

10.6

8

10.3

8.88

7.3

11.2

9

13

10.68

8.3

16.47

TABLE 8-4 Actuation Force on Membrane 20:1 PMDS

Silicon Rubber Type of Fluid

High Salt

Ethanol

Air

Water

Speed (mm/min)

0.513

0.628

0.853

0.0251

Extension (mm)

Force (N) 0

0

0

0

0

1

2.05

1.40

1.43

1.38

2

2.66

2.58

1.83

2.98

3

3.66

3.25

2.38

4.43

4

4.58

4.10

3.33

5.18

5

5.68

5.00

4.03

6.10

6

6.59

5.85

4.78

7.22

7.52

7

8.92

6.03

9.04

8

11.95

10.2

7.00

11.38

9

13.02

11.99

8.53

13.74

TABLE 8-5

Actuation Force on Silicon Rubber

383

384

Chapter Eight

Material

Permeability (g/m2/day)

Rubber

0.63

Polypropylene

0.02

TABLE 8-6

Permeability of Membrane Material

Lab on a chip

PP reservoirs

FIGURE 8-34 Cartridge with rubber membrane and polypropylene reservoir material.

material for both membrane and reservoir applications. Since the material percent of elongation of polypropylene is less than that of rubber, rubber was chosen for the membrane, whereas polypropylene was used for the reservoir (Table 8-6). Combining both materials as a membrane and reservoir, the shelf life of the reagents has been improved more than 80 percent over PDMS containers, and the cartridge is shown in Fig. 8-34.

8.10 Thermocompression Bonding Bonding of biocompatible polymeric substrates is performed using thermocompression, where the bonding parameters are the arm and chuck temperature, the arm and chuck time, and the force applied. The bonding strength depends on these three bonding parameters and is investigated. The objective is to obtain the optimal bonding characteristics such that the microfluidic structures on the two substrates can be sealed without any physical distortion owing to melting of the material, which results in clogging of the microfluid channels.

Bio-MEMS Packaging

8.10.1

Bonding of PMMA to PMMA for the Channel Layer

Since PDMS is a porous material, it cannot be used for the storage reservoir. Thermoplastic materials that are injection-moldable are selected for the reservoir. Different thermoplastic materials such as COC, polypropylene, polycarbonate, and PMMA are fabricated. Bonding of these materials, both similar and dissimilar materials, must be optimized so that no fluid leaks during testing. Microchannels are fabricated on the thermoplastic material, and a roughness study must be done to understand fluid drag during fluid flow. The dimensions of the PMMA sample used for this study are 70 × 55 × 1 mm. The upper layer consists of all the fluid ports and through holes, whereas the lower layer consists of the microchannels. PMMA or acrylic is an amorphous thermoplastic that is optically transparent and has a high strength-to-weight ratio. The PMMA used in this investigation has a glass-transition temperature Tg of approximately 105°C. Above Tg, the secondary noncovalent bonds between the polymer chains become weak in comparison with thermal motion, and the polymer becomes rubbery and capable of elastic or plastic deformation without fracture. Since PMMA Tg is about 105°C, the initial bonding temperature was fixed within this range of 80 to 100°C. Although some signs of bonding are observed at 100°C, 60 kg, and 1500 s, the bonding result is not satisfactory. The bonding interface between the two substrates is not very smooth, and some air gaps are observed within the substrates, indicating that the bonding strength is still rather weak. Therefore, further steps were taken to increase the temperature up to Tg while varying the force applied and duration so as to ensure effective and efficient bonding. Some of the key results for bondability of PMMA can be found in Table 8-7. The optimized conditions for a piece of PMMA with the above-mentioned dimensions are 105°C, 50 kg, and 1200 s. The bonding result for two PMMA substrates is shown in Fig. 8-35. Since the microfluidic channels are already micromachined on the PMMA, it is possible to determine that thermal bonding under the preceding optimized conditions results in melting and flow in the substrate material that seal the microchannels. A simple experiment to determine this result was carried out using a syringe to inject colored water into one of the inlet ports located on the upper PMMA substrate. Since the microchannels are located on the lower PMMA layer, fluid is expected to flow into the inlet port, through the microchannel that connects to it, and exit from the outlet port. As observed earlier, a smooth and continuous fluid flow path is observed from the inlet to the outlet for both the inlet ports being tested, with no signs of leakage between the PMMA-bonded layers. A leakage test was conducted to determine the maximum pressure/ bonding strength the bonded PMMA layers can withstand before failure. This is achieved by continuously pumping liquid into channel.

385

386

Chapter Eight Sample

Temp. (∞C)

Force (kg)

Time (s)

Outcome

1

80

0.5

30

N

2

80

0.5

100

N

3

80

5

100

N

4

100

10

500

N

5

100

25

500

N

6

100

50

500

N

7

100

50

1000

N

8

100

60

1500

Weak

9

105

50

1500

Y

10

105

60

100

Y

11

105

50

1200

Y

TABLE 8-7 Process Optimization of Thermal Compress Bonding of PMMA

Upper PMMA substrate Lower PMMA substrate

FIGURE 8-35 Side view of PMMA-to-PMMA bonding.

The inlet pressure is measured with a pressure gauge. The fluid pressure within the microchannels built up before leakage occurs. The pressure before interface failure is the maximum pressure the bonding interface is able to withstand.

Bio-MEMS Packaging In the experiment, the inlet pressure was increased steadily over time up to a maximum of 176.44 kPa before the fluid started to leak. The pressure encountered in biologic testing is usually much lower than this pressure. Therefore, it can be concluded that thermal compression bonding of PMMA is effective and useful because it eliminates the need for adhesive and thus reduces cost and assembly time.

8.10.2

Polypropylene to PMMA for Reservoir and Channel Layer

Polypropylene and PMMA have different Tg values, and therefore, thermal bonding is not possible. Adhesive tape was used to bond these two layers in this study (Fig. 8-36). Aluminum foil is used to blind the reservoir openings. This makes the bonding interface less smooth and thus increases the difficulty of complete sealing. The challenge of bonding of two pieces of rigid plastic by adhesive tape is to achieve a secure and leakage-proof bonding.

Sample This sample was designed with a 80 × 60 × 10 mm polypropylene layer; on it there are 12 reservoirs, and each is the same configuration as the original reservoir (Fig. 8-37). Rubber stoppers are inserted. One aluminum foil with a diameter of 8 mm seals the outlet of a reservoir. The sample is similar to actual case. The PMMA layer was 3 mm thick without channels but with through holes for the fluid test. It was so designed because more than one reservoir would be tested, and since the reservoirs were at different locations—on the side, at the corner, and at the center—we were able to determine which location would be more susceptible to delamination.

Inlet port

FIGURE 8-36 Sample of polypropylene-to-PMMA bonding.

387

388

Chapter Eight

FIGURE 8-37 Microfluidic cartridge with 12 reservoirs.

Process Development: Adhesive Tape and Thermal Compress To bond the PMMA channel layer to the polypropylene reservoir, the Mini-Test Press machine was used to apply pressure to the sample interface and at the same time heat up the samples at a constant 80°C. Under this heating condition, the adhesive on both sides of the tape is softened and wets the interface better, thus maximize bonding effect. The process parameters are shown in Table 8-8. Process 7 was selected as the final bonding process. It contains three steps: 1. After assembly, the sample is heated to 80°C without pressure for 5 minutes. 2. Then 3 MPa of pressure is applied at 80°C. 3. Then the sample is cooled down without releasing the pressure. It was observed on bonded samples that certain parts of the interface showed clear and snowflake-like cracking lines owing to stretch and expansion of the tape. More lines appeared after the sample is fully cooled down to room temperature.

Bio-MEMS Packaging Reservoir

Maximum Pressure (kPa)

1

517

2

520

3

515

4

500

5

520

6

511

7

508

8

519

9

498

10

520

11

522

12

515

Average

513

TABLE 8-8

Process Optimization of Adhesive Bonding of Polypropylene to PMMA

Fluid Testing Theoretically, reservoirs at the corner and along the sides would be more susceptible to leakage than those at the center. Fluid testing was conducted on all the reservoirs by injecting liquid into the bonding interface through the rubber stopper. The entire reservoir could withstand an average pressure of 513 kPa without leakage, which is much higher than the requirements of the biopackage. For detailed data, please refer to Table 8-9.

Reservoir (dia/mm)

Required Flow Rate (ml/min)

Actuator Speed (mm/min)

Measured Flow Rate (ml/min)


50

0.528

47.0

R2 (12 mm)

50

0.972

46

R3 (16 mm)

100

0.912

96

R4 (12 mm)

2

0.024

TABLE 8-9 Interface

1.6

Fluid Testing on Maximum-Pressure Reservoir Bonding

389

390

Chapter Eight

8.10.3 Tensile Test The sample is assembled with a 20 × 20 × 10 mm piece of polypropylene and a 20 × 20 × 3 mm piece of PMMA with 8-mm-diameter aluminum foil in between. The dimensions are the same as a single reservoir. Four samples were tested on the MicroTesterTM . Samples were fixed on the tensile test machine by clamping to the ends of the fixtures. The bottom load cell is nonmovable. A computer moves the top fixture upward and pulls the specimen up. During the pulling action, displacement of top fixture and load are transiently recorded. The test setup is shown in Fig. 8-38. The recorded loads are shown in Fig. 8-39. The load is built up as the top fixture moves up. The load reaches its

Upper collet

Fixture

PP

PMMA

Lower collet

Load cell

FIGURE 8-38 Tensile test setup with bonding interface open.

Bio-MEMS Packaging 200 180

Specimen 1 Specimen 2 Specimen 3 Specimen 4

Stretching of the adhesive tape

160

Load, N

140 120 100 80 60

Stretching of the adhesive on A1 foil

40 20 0 0

1

2

3

5 4 Extension, mm

6

7

8

FIGURE 8-39 Graph of load versus extension for four samples.

maximum and suddenly drops when the bonding interface fails. It can be seen that after the interface fails, the tape and aluminum foil stay on the surface of the PMMA but not the polypropylene.

8.11

Microfluidic Package Testing

8.11.1

Fluid Testing

After assembly of the PDMS package, fluid testing is carried out to ensure that there is no leakage from the chip or between the PDMS layers. The procedures for fluid testing are as follows: Step 1: Fill a 1-ml syringe with colored water, ensuring that there are no air bubbles trapped within the syringe. Attach the syringe to a syringe pump, and close the latch. Step 2: Fix a filter to the syringe so as to eliminate any particles in the water that may cause blockage in the chip. Then connect the tubing from the syringe to the PDMS cartridge and a pressure meter via a three-way connector. Step 3: Insert a pin into each reservoir at the fluid inlet and outlet, respectively, to allow fluid to enter into the chip inlet and exit from the chip outlet. The inlet pin is connected to the pressure meter. Step 4: Set the constant-flow-rate value for the fluid on the syringe pump. In general, for leakage testing, two flow rates, 50 and 100 μl/ min, are tested. Press the “Start” button to start pumping the fluid through the cartridge.

391

392

Chapter Eight Step 5: Note the pressure value on the pressure meter when water is observed at the fluid outlet. This reading is equivalent to the inlet pressure. As fluid is continuously pumped into the cartridge, watch for any significant change in the inlet pressure. For normal cases, the pressure eventually will saturate at a constant value. Any sudden drop in pressure will indicate a leak, usually from the ports of the biochip. Step 6: At the end of the fluid testing, stop the syringe pump and remove the pins from the fluid inlet and outlet ports. An actuator that can control the speed and meet the required load is used to push the reagents stored in the reservoirs. Based on the linear function between actuator speed and flow rate, the speed of each reservoir is calculated, as shown in Table 8-9. The actual flow rate of each reservoir is also measured.21–23

8.11.2

Biologic Testing on a Biosample

The biosample and a lysis buffer are mixed in a certain ratio in a syringe. During the mixing process, cell membranes break down and DNA is released. The mixture is then injected into the text package via the sample port (Fig. 8-40). When the lysed biosample flows through microfluidic chip, the DNA attaches to the microchannel (Si surface). The rest flows out of the chip as waste. A computercontrolled actuator presses reservoirs in the sequence and speed

Injection ports

FIGURE 8-40 Reservoirs of thermoplastic material.

Reservoirs with reagents

Bio-MEMS Packaging Reservoir (dia/mm)

Required Flow Rate (ml/min)

Actuator Speed (mm/min)

Measured Flow Rate (ml/min)

R1 (14 mm)

50

0.528

47.0

R2 (12 mm)

50

0.972

46

R3 (16 mm)

100

0.912

96

R4 (12 mm)

2

0.024

TABLE 8-10

1.6

Flow Rate with Respect to Actuator Speed

determined by the protocol (Table 8-10). The last reagent is the lowsalt solution, which detaches the DNA from the Si surface and flushes it out. This process is called elution. The product of elution is collected into five PCR tubes, which are marked as elutions 0 to 4 (Table 8-11). All the elutions in this extraction showed a certain amount of DNA being eluted, and all were of sufficient quantity and quality to be amplified by PCR. The gel electrophoresis spectrum shows that elutions 0 to 4 all contain DNA and is shown in Fig. 8-41. The DNA is present in blood cells. In order to release DNA from blood cells, the blood sample should be lysed and the blood cell membranes broken. DNA then appears in the blood mixture. When the lysed blood flows through a silicon microfluidic chip in a highsalt environment, DNA tends to attach onto the Si pillars. The rest of the blood flows out of chip as waste. When a low-salt solvent flows through the Si chip, DNA detaches from the Si pillars, merges with the low-salt solvent, and flows out from chip.

DNA Extraction Average Amount of DNA (ng)

Total Amount of DNA Eluted (ng)

Amount of DNA Eluted per ml of Blood (ng)

351.88

3.3513

Sample ID

Volume of Elution (ml)

Elution 0

30

52.22

Elution 1

27

186.01

Elution 2

24

165.72

Elution 3

24

133.95

Elution 4

34

210.54

10-ng std

—

9

—

—

100-ng std

—

122

—

—

TABLE 8-11 Amount of DNA Eluted during Extraction

393

394

Chapter Eight

500 bp

300 bp 200 bp

Elutions 0 to 4 from fluidic testing ~251 bp

Lane: N: Negative PCR control M: 100 bp marker 1: Elution 0 2: Elution 1 3: Elution 2 4: Elution 3 5: Elution 4

FIGURE 8-41 All the elutions (0 to 4) were positively amplified in this experiment.

8.12

Sample Preparation and Setup In this study, DNA from human blood was extracted using a biocartridge. The cartridge has three main components: a silicon microfluidic chip, reservoirs and a microchannel as a link from the reservoirs to the chip. The chip has a chamber filled with microarrays of silicon pillars. The pillar surfaces are the areas for contacting of the blood sample. The cartridge self-contained reservoirs store a high-salt solution, a low-salt solution, a solvent, and other enzymes separately. During the biotesting, the solvents in the reservoirs are dispensed from reservoir to the silicon chip by the means of pushing the reservoirs’ membranes one by one. The pushing force and pushing distance are performed and controlled by an external actuator. The actuator has no contact with the solvent or sample throughout the testing.

8.12.1

Pretreatment of the Cartridge

Binding efficiency of DNA to the silicon chip is the key factor for success in separating DNA from blood. In order to enhance the bonding, pretreatment on the silicon chip surface is necessary. In this study, the package was treated with a solution of ammonium hydroxide, hydrogen peroxide, and water at room temperature. The treatment solution was pumped into the chip using a peristaltic pump. The chip in the package was washed with water before biotesting.

8.12.2

PCR Amplification

All the elutions in this extraction went through a PCR thermal cycler with following conditions: It showed a certain amount of DNA being eluted, and all were of sufficient quantity to be amplified by PCR. From all the elutions, the total amount of DNA eluted was about 351.8 ng, and this is more than sufficient for the Nornam requirement of 40 ng (Table 8-12). The gel fluorescence graph shows that elutions 0 to 4 have positive amplification and all contained DNA; this is shown in Fig. 8-41.

Bio-MEMS Packaging Step

Temp.

Duration

Cycle No.

Initial denaturation

98.0°C

1 min

1

Denaturation

98.0°C

8s

Annealing

61.5°C

20 s

Extension

72.0°C

7s

Final extension

72.0°C

8 min

}

28 cycles

1

TABLE 8-12 PCR Thermal Cycle Conditions

References 1. Chin, C. D., Linder, V., and Sia, S. K. “Lab-on-a-chip devices for global health: Past studies and future opportunities.” Lab on a Chip 7:41–57, 2007. 2. Vilkner, T., Janasek, D., and Manz, A. “Micro total analysis system: Recent developments.” Anal. Chem. 74:2637–2652, 2002. 3. Thorsen, T., Maerkli, S., and Quake, S. R. “Microfluidic large scale integration.” Science 298:580–584, 2002. 4. Erickson, D., and Li, D. “Integrated microfluidic devices.” Anal. Chem. 507:11–26, 2004. 5. Liu, R. H., Ngyuen, T., Schwarzk, K., Opf, H., Fuji, S., Petrova, A., Siuda, T., Peyvan, K., Bizak, M., Danley, D., and McShea, A. “Fully integrated miniaturized device for automated gene expression DNA microarray processing.” Anal. Chem. 78(6):980–1986, 2006. 6. Liu, R. H., Jlodes, M., Ngyuen, T., Siuda, T., Slota, M., Fuji, H. S., and McShea, A. “Validation of fully integrated microfluidic array device for influenza A type identification and sequencing.” Anal. Chem. 78:4184–4193, 2006. 7. Ducree, J., Haeberle, S., Lutz, S., Pausch, S., Von Stetten, F., and Zengerle, R. “The centrifugal microfluidic Bio-Disk platform.” J. Micromech. Microeng. 17: S103–S115, 2007. 8. Sia, S. K., and Whiteside, G. M. “Microfluidic devices fabricated in poly (dimethylsiloxane) for biological studies.” Electrophoresis 24:3563–3576, 2003. 9. Pan, T., McDonald, S. J., Kai, E. M., and Ziaie, B. “A magnetically driven PDMS micropump with ball check-valves.” J. Micromech. Microeng. 15:1021–1026, 2005. 10. Cho, Y.-K., Lee, J.-G., Park, J.-M., Lee, B.-S., Lee, Y., and Ko, C. “One step pathogen specific DNA extraction from whole blood on a centrifugal microfluidic device.” Lab on a Chip 7:565-673, 2007. 11. Ahn, C. H., Woo-choi, J., Beaucage, G., Nevin, J. H., Lee, J. B., Puntambekar, A., and Lee, J. “Disposable smart lab on a chip for point of care clinical diagnostics.” Proc. of IEEE 92:154–173, Jan. 2004. 12. Gray, B. L., Collins, S. D., and Smith, R. K. “Interlocking mechanical and fluidic interconnections for microfluidic circuit boards.” Sensors Actuators A 112:18–24, 2004. 13. Xie, L., Chong, S. C., Premachandran, C. S., Pinjala, D., and Iyer, M. K. “Disposable biomicrofluidic package with passive fluidic control.” In Proceedings of the 7th Electronics Packaging Technology Conference, Singapore, December 2005, pp. 93–97. 14. Pan, T., McDonald, s. J., Kai, E. M., and Ziaie, B. “A magnetically driven PDMS micropump with ball check valves,” J. Micromech. Microeng. 15:1021–1026, 2005. 15. Dittrich, P. S., and Manz, A. “Lab-on-a-chip: Microfluidics in drug discovery.” Nat. Rev. Drug Disc. 5:210–218, 2006. 16. Nguyen, N. T., and Wu, Z. “Micromixers: A review.” J. Micromech. Microeng. 15: R1–16, 2005.

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Chapter Eight 17. Linder, V., Sia, S. K., and Whitesides, G. M. “Reagent-loaded cartridges for valveless and automated fluid delivery in microfluidic devices.” Anal. Chem. 77:64–71, 2005. 18. Chong, S. C., Xie, L., Yobas, L., Ji, H. M., Li, J., Chen, Y., Pinjala, D., Hui, W., and Iyer, M. K. “Disposable polydimethylsiloxane package for microfluidic system.” In Proceedings of the 55th Electronic Components and Technology Conference, Miami, FL, June 2005, pp. 617–621. 19. Xie, L., Chong, S. C., Premachandran, C. S., Chew, M., and Raghavan, U. “Development of an integrated microfluidic package with microvalves and reservoirs for a DNA lab on a chip application.” In Proceedings of the 56th Electronic Components Technology Conference, San Francisco, CA, May 2006, pp. 693–698. 20. Xie, L., Premachandran, C. S., Chong, S. C., and Chew, M. “Design, integration and testing of a fluidic dispensing control valve into a DNA/RNA sample preparation microfluidic package for Lab On a Chip (LOC) applications.” In Proceedings of the 57th Electronic Components and Technology Conference, June 2007, pp. 1900–1904. 21. Yobas, L., et al. “A flowthrough shear type microfilter chip for separating plasma and virus particles from whole blood.” In Proceedings of Micros TAS 2004, 8th International Conference on Miniaturized Systems in Chemistry and Life Sciences, vol. 2, Sweden, September 2004, pp. 7–9. 22. Yobas, L., et al. “Microfluidic chips for viral RNA extraction and detection.” IEEE Sensors Oct 30–Nov 3, 2005, pp. 49–52. 23. Xie, L., Premachandran, C. S., Chong, S. C., and Chew, M. “Development of a disposable bio-microfluidic package with reagents self-contained reservoirs and micro-valves for a DNA lab on a chip (LOC) application.” IEEE Trans. Adv. Packag. (in press).

CHAPTER

9

Biosensor Packaging 9.1 Introduction Microelectromechanical systems (MEMS) devices are used as biosensors in many applications. Pressure sensors, accelerometers, microphones, micromirrors, and other types of MEMS devices are used for biosensor applications. Biosensors are categorized into different types based on the application: in vivo, implantable, and wearable types. Accelerometers are used in pacemakers, which are implantable devices, whereas pressure sensors measure blood pressure and are wearable types. MEMS devices used for endoscopy are in vivo applications. The endoscope is used inside the body for imaging internal parts. This chapter describes a MEMS micromirror used in a tiny endoscope for imaging applications. Optical coherence tomographic (OCT) bioimaging is an emerging technique for higher-resolution biopsies and other medical diagnostic applications.1 OCT imaging can achieve real-time cellular-scale resolution, which is important in producing high-resolution crosssectional images of the internal microstructure of living tissues.2,3 Higher resolution combined with real-time imaging makes opticalprobe OCT imaging an important tool for accurate cancer diagnosis and monitoring to avoid recurrence of cancer lesions. OCT with miniature probes can be used where excision biopsy is unsafe or not possible. It also can be used in delicate interventional procedures, such as neural investigations in the brain, and to reduce sampling errors owing to the fact that it is real-time. The optical probe is one of the critical elements in OCT imaging because it makes the OCT imaging real-time.2 The miniature optical probe helps to reduce patient trauma by eliminating the tissue removal required for biopsy. In its simplest implementation, the optical probe is a miniature assembly of fiberoptics that which can deliver a light beam (and also collect scattered light) and a scan in one dimension (lateral) of the

397

398

Chapter Nine target. This scanning can be achieved by actuating the mirror itself. Research also has shown that when the micromirror of the MEMS scanner is integrated into the outer tip of the probe, scan flexibility is added.1–10 Micromirror technology adds dynamism to the selected cross section (of tissue, lesion, etc.) by allowing real-time observation. The main challenge is in increasing dynamic flexibility while keeping the diameter small, which is essential to reduce patient trauma during real-time optical biopsy. A miniature package is required to allow the OCT probe to produce in situ real-time imaging of cells/tissues.10–20 The existence of OCT in biomedical imaging has enabled multiple cross-sectional imaging of biologic tissues both in vitro and in vivo. The image produced using is potentially useful in distinguishing pathologic from healthy tissue, especially when viewing epithelial tissues in the gastrointestinal tract. However, the size of current OCT probes has not permitted their use in the working channel of an endoscope, in which a probe has to be shorter than 15 mm and smaller than 3 mm in diameter.15

9.1.1

Review of Optical Coherence Tomography (OCT)

OCT is an imaging technique that uses a low-coherence light source to provide three-dimensional images with high spatial resolution. Regardless of whether time- or spectral-domain OCT is used, the probe that is designed for image acquisition has to be optimized for minimum size and maximum scan range. Currently, the best reported axial resolution of a side-imaging probe is 5 μm, whereas the best reported lateral resolution is 8 μm.23 Since invention of OCT system, it has been applied extensively in ophthalmologic settings. This is so because besides providing good spatial resolution, OCT offers high detection sensitivity, allowing low input power to be used. OCT is also capable of providing fast imaging speeds, although the imaging volume is small, typically smaller than 35 mm3. In addition to their use in ophthalmology, OCT systems also have been used extensively in cardiology.5,6 One of the advantages of OCT imaging is the possibility of in vivo applications.6–11 In conventional OCT, the probe is large, and thus imaging in vivo is quite difficult. The probe can be used as an endoscope so that internal tissue imaging can be performed. Both conventional and MEMSbased OCT probes are shown in Fig. 9-1. Morphologic changes in an internal organ can be identified based on changes in the images over time. Comparing an older image of healthy tissue with a newly taken image can ascertain whether there is any abnormality in that tissue. In commercial applications, there are two types of OCT systems: a swept-source OCT (SS OCT), where rapid scanning of narrow-band

Biosensor Packaging Optical fiber Outer sheath

Prism

Objective lens Optical fiber

Aluminum package Speedometer cable Silicone GRIN lens sealant Proximal actuation (a)

Collimator

MEMS scanner

(b)

FIGURE 9-1 OCT probes: (a) conventional OCT catheter; (b) MEMS scanning OCT endoscope.

source spectra is performed, and spectral-domain OCT (SD OCT), where a Fourier domain detection technique is used. An OCT test setup with probe is shown in Fig. 9-2. The scanning mechanism associated with the probe can be categorized as circumferential or lateral. Probes that use circumferential scanning incorporate a micromotor as an actuator that turns the mirror around so that the light source can be directed around a 360-degree range, and one such probe is shown in Fig. 9-3a and one without micro motor is shown in Fig. 9-3b.

Reference mirror Collimator

Source

Circulator Detector

Signal processor

Computer

Biocompatible housing

Sample

GRIN lens

25 mm Substrate 2–3 mm Probe

FIGURE 9-2 OCT setup with an optical probe.

399

400

Chapter Nine

Flexible part (57.5 cm)

Optical fiber

Optical glue

GRIN lens

Focused beam

MEMS motor Rigid part (2.5 cm)

Diameter (2.7 mm) Linear transversal stage

Motor wire Transparent FEP tube

Prism Medical glue

(a)

Detector

Beam splitter

RF component

Electrical connection Biocompatible GRIN lens

Sample

Substrate

(b)

3D MEMS mirror

FIGURE 9-3 Optical probe with MEMS micromirror.

Circumferential-scanning probes have one polar degree of freedom. Probes that use lateral scanning incorporate an actuator that is attached to the edge of the mirror, and the actuator controls the movement of the mirror in a limited angular range. Lateral-scanning probes have two rotational degrees of freedom. Some of the lateral-scanning probes have electrostatic actuators and electrothermal bimorph actuators. The actuation speed of an electrostatic actuator far exceeds that of a electrothermal bimorph actuator, which is an advantage. However, electrostatic actuators are more difficult to design.

Biosensor Packaging

9.2 Biosensor Packaging 9.2.1 Micromirror The micromirror is the most important part of the scanning mechanism. It is equipped by four bimorph thermal actuators controlled by five electrical connections. The micromirror is a nongimbal type in which the gold mirror is connected directly to four actuators. Each actuator is made of aluminum-silicon bimorph with a negligibly thin layer of silicon oxide sandwiched between the bimorph. The MEMS based micromirror chip used has a micromirror of about 0.5 mm diameter. An intact micromirror diced using a laser dicing machine and viewed under a scanning electron microscope (SEM) is shown in Fig. 9-4. The diameter of the micromirror is 0.5 mm. The bimorph actuator is powered by an external electric circuit connected to micromirror through solder pads. By applying voltage, the actuator is able to tilt the mirror by ±16 degrees about both x and y axes. There is a spring formed in the silicon between the mirror and each actuator, and it acts as a motion regulator and facilitates continuous motion of the tilting mirror. As seen in Fig. 9-5, the micromirror is connected to the chip only via thin silicon wires. Thus there is a process called release of the micromirror that removes the sacrificial layer holding the mirror structure onto the bulk silicon.

9.2.2

Single-Mode Optical Fiber and GRIN Lens

Standard single-mode fiber is used as the optical transmission medium for the probe. The core diameter of the index single-mode fiber is 8.2 μm, and it has a refractive index 1.4677 at a wavelength of

3D silicon micromirror Silicon spring Bimorph actuator

FIGURE 9-4 Silicon micromirror with thermal actuators.

401

402

Chapter Nine

y axis Middle substrate x axis

Fiber slot

Upper substrate

GRIN lens slot

Micromirror chip

z axis (optical axis)

Lower substrate

FIGURE 9-5 Upper and lower substrate assembly (cross-sectional view).

1310 nm, the center of the application wavelength of the endoscope probe. The index profile of the core is 0.36 percent higher than that of the cladding. The cladding is of standard outer diameter, which is 125 μm. In design of the endoscope probe, the length is 1 m. At the application wavelength, the numerical aperture∗ (NA) of the fiber at the 1 percent power level is 0.14, which is equivalent to 0.092 at 1/e2 power level (Sec. 9.3.2 discusses NA at different power levels of a Gaussian beam, namely, 1, 13.5, and 50 percent). The GRIN lens has the same function as a biconvex lens. It is fabricated by lithium ion exchange in glass,13 resulting in an index profile that decreases in the radial direction from the center to the edge. It is a rod lens having two flat and one curved surface. The flat surfaces are for input and output rays to go through surfaces (front surface for input rays and back surface for output rays), whereas the curved surface is just the edge of the lens. The advantages of using GRIN lens over a conventional spherical lens are that it provides easier assembly and alignment, and it has no spherical aberration. Moreover, for miniaturized application, spherical lenses are not readily available and thus are very expensive in terms of manufacturing time and cost compared with GRIN lens. For a certain index profile, the fabricated GRIN rod has a maximum NA and a fixed length of one (unity) pitch. Unity pitch is the length of the GRIN lens in which light completes one sinusoidal cycle of propagation and is shown in Fig. 9-6. A customized GRIN lens is designed so that the focal point will be at a certain working distance (WD) from the lens, and the pitch is usually a fraction of unity.14 The required WD is achieved by fixing an output NA that is smaller than the maximum NA. Once an NA is chosen, pitch is also fixed. Then the GRIN rod can be cut and polished at the determined length. ∗The numerical aperture of a fiber is a figure that represents its light-gathering capability.

Biosensor Packaging Edge surface

Back surface Front surface

1/4 Pitch

1/2 Pitch 1 Pitch

FIGURE 9-6 Ray traces within a GRIN focusing lens of different pitch lengths.

GRIN lens version 1 used in a probe has a working distance of 5.5 mm with an output NA of 0.042 at 1/e2 power level and a rod diameter of 1 mm. Version 2 has the same NA and a WD of 5 mm with a diameter of 0.5 mm.

9.2.3 Upper Substrate The upper substrate is a component for stabilizing the single-mode optical fiber and the graded-index (GRIN) lens. The substrate is made of single-crystal silicon. It is designed for holding the two important optical components in place. The design of this part has to be compatible with the trench of the lower substrate and the height of the mirror so that optical centers can be aligned. Widths of its fiber trench and its GRIN lens trench were designed so that they fit the components nicely with very small tolerance. Both trenches are made using deep reactive-ion etching (DRIE). The details of the upper and lower substrates are shown in Figs. 9-7 and 9-8.

Plan

Ferrule/GRIN lens trench

GRIN lens

Side Front

FIGURE 9-7 Upper substrate of an OCT endoscope probe.

403

404

Chapter Nine

GRIN lens assembly

Upper substrate

FIGURE 9-8 Upper substrate with GRIN lens assembly.

Plan Electrical connection

Trench for micromirror

Side Front

FIGURE 9-9 Lower substrate of an OCT endoscope probe.

9.2.4 Lower Substrate The lower substrate is also made of single-crystal silicon, with a trench for micromirror and integrated electrical connections. The trench is made using KOH wet etching. This silicon optical bench (SiOB) is used for holding the micromirror and providing solder connection between integrated gold traces and the solder pads on the micromirror chip. Top-view and cross-sectional drawings of the lower substrate are provided in Figs. 9-9 and 9-10.

9.3 The Package 9.3.1

Configuration of the Probe

With all the parts introduced in the preceding section, the assembled product is shown in Fig. 9-11. Probe assembly requires high precision for optical alignment up to the micron level to produce an optically

Biosensor Packaging

MEMS mirror Solder ball Trench

Metal traces for electrical connection to MEMS micromirror

FIGURE 9-10 Lower substrate of an OCT endoscope probe with mirror assembly.

MEMS mirror

Glass spacer Upper substrate Ferrule Single mode optical fiber

GRIN lens Lower substrate Electrical/optical connecting cap

FIGURE 9-11 Assembled substrates, side view without housing, GRIN lens, and fiber.

functional unit. The process can be controlled by translation stage and rotation stage. However, merely having the stages does not help. Instead, design of the fixtures (fixing on the translation stage) was done in such a way as to clamp the parts in place for proper assembly using the precision control stages. Moreover, assembly of the lower

405

406

Chapter Nine

y axis x axis

Center of the spot

Laser source

z axis Divergent beam Screen

FIGURE 9-12 A laser source detected by a screen.

substrate with the mirror requires high manual precision. The connection between the lower substrate and the micromirror chip is established by solder balls. Figure 9-12 also shows axis definitions that will be used in discussion of the probe throughout this chapter (unless otherwise specified). The z axis is defined to be the line along the center of the GRIN lens. The x axis points toward the direction of the light emitted from the GRIN lens to the micromirror and reflected outward (into this page, out from the probe). The y axis is defined as the vertical axis. The coordinate system is tilted 90 degrees about y axis once the light passes through the micromirror, which has an orientation of 45 degrees relative to the GRIN lens objective surface. Then the new z axis takes the direction of the old x axis, and the new x axis takes the direction of old negative z axis.

9.3.2

Optical Properties and Theories

System NA and Spot Size This section introduces theories and concepts that are important for the optical probe, such as system numerical aperture (NA), spot size, distribution of light intensity, depth of focus (DOF), axial resolution, and transverse resolution. In general, numerical aperture (NA) is used to characterize the angular spread of a beam in certain media. It is also used to characterize the acceptance angle of a fiber. The formula for numerical aperture is NA = n sin θ where n is the refractive index of the medium and θ is the half-angle of the cone of a converging/diverging beam. However, how to determine θ is not a trivial question. For a white-light beam that is generated by spontaneous emission and passes through an aperture, the value of θ can be obtained by geometric optics simply by drawing

Biosensor Packaging

(0, 1) Power density (power per area)

1

(1.1744, 0.5)

0.5

(2, 0.135)

0.135

(3.0349, 0.01) 0.01 –4

–3

1 2 –2 –1 0 x or y axis, in space (arbitrary length unit)

3

4

FIGURE 9-13 Standard Gaussian distribution of optical power in a laser spot.

and measuring the angle. However, in laser physics, an emitted beam usually has a Gaussian profile; thus, there is a need to define a boundary to characterize the spot size. For instance, in Fig. 9-12, a laser beam is profiled onto a screen from a certain distance away from the screen. If we plot the power density (of area) from the center of the spot (as y = 0 or as x = 0), we will get a Gaussian curve, as shown in Fig. 9-13. The center of the spot always has a largest power density, so it can be normalized to 1. According to the standard Gaussian distribution formula, 1

f(x) = σ 2 π e

−( x−μ )2 /2 σ 2

(9-1)

If the standard deviation σ is set to unity and the mean is set to 0, the standard Gaussian curve is f(x) =

1 2π

e−x

2 /2

(9-2)

Using Eq. (9-2), we can find out the peak, that is, f(x)max =

1 2π

which is at x = 0. If we substitute the value of 0.5f(x)max into Eq. (9-2), we can obtain the relative x value for spot radius at full-width

407

408

Chapter Nine half-maximum (FWHM) power level. If we substitute the value of 0.135f(x)max into Eq. (9-2), we can obtain the relative x value for spot radius at the 1/e2 power level (note that 0.135 is same as 1/e2). Similarly, if we substitute the value of 0.01f(x)max instead into Eq. (9-2), we can obtain the relative x value for spot radius at the 1-percent power level. These are the three different conventions used in various laser optics studies to define spot size. Most of the discussions herein, if not stated otherwise, will refer spot size as the spot size at the 1/e2 power level (all these relative x values are shown in Fig. 9-13). If, in any case, an FWHM spot diameter is obtained as dFWHM, the spot diameter at 1/e2 can be calculated using the relative x values as de–2 = dFWHM × (2/1.1744) Having introduced a general definition of NA and spot size for a laser source, now the system NA can be discussed. For the system being developed, the rays from the light source are directed into the GRIN lens and then focused into a point at a working distance (WD) from the objective surface (back surface) of the GRIN lens. As shown in Fig. 9-14 the system NA can be calculated by NA = n sin θ where θ is the angle between the outer ray (at 1.e2 power) and the optical axis, which is horizontal, and n is the refractive index of the medium, assumed to be unity because usually the medium at this ray segment is air. Thus, NA = sin θ Because the rays can be assumed to be paraxial,

sin θ ≈ tan θ =

d/2 WD

Working distance (WD)

Spot diameter at objective surface d

GRIN lens Source surface

Objective surface

FIGURE 9-14 GRIN lens with rays, definition of surfaces and length parameters.

Biosensor Packaging Thus, System NA = spot radius at objective surface/working distance (9-3)

Transverse Resolution (B-Scan and C-Scan), DOF, Axial Resolution (A-Scan, Optical Path Length) Transverse resolution refers to the smallest resolvable diameter on the sample that the optical device is capable of in the direction perpendicular to the optical axis. In our probe, the transverse resolution Δw can be defined as the spot diameter at the beam waist (focal point). Figure 9-15 shows a Gaussian beam at its beam waist. Transverse resolution can be obtained from the following formula:16 Δw =

2λ c p(NA)

(9-4)

where λc is the central wavelength of the light source, and NA is the 1/e2 numerical aperture of the system. A smaller value of Δw corresponds to better resolution. Transverse resolution affects image quality in B- and C-scans. B-scanning is scanning in which adjacent A-scan images are combined to form a two-dimensional (2D) image. C-scanning is scanning at a certain depth (certain radial distance from the center of the micromirror) in the sample that produces a 2D image. A-scanning is scanning performed by moving the referenced arm, thus changing the reference optical path length, which produces an image along the optical axis. Depth of focus (DOF) refers to the range in which spot size lies within 2 Δw along the optical axis. The DOF of a system increases with decreasing NA. This length gives the length in the sample that

DOF

√2 Δw

Δw

z Optical axis

FIGURE 9-15 Gaussian beam at its beam waist.

409

410

Chapter Nine is in focus at any given time. For our application, this length is the same as the depth of field because only one lens is used in the system. Its value is inversely proportional to the square of NA and can be calculated as follows:16 DOF =

2λ c p(NA)2

(9-5)

For a fixed light source, varying the DOF does not vary the axial resolution. Axial resolution refers to the smallest resolvable length inside the sample along the optical axis (z axis, depth axis). It is important in A-scan images. Its value is independent of NA but depends on the bandwidth of the light source. The light source used in time-domain OCT is a continuous wave with a broad bandwidth, around 110 nm at FWHM. The reason for choosing a broadband light source is to provide a low coherence length (in meters that characterize time coherence) of the source. A low coherence length, in turn, facilitates high axial resolution. A round-trip coherence length can be calculated from the following formula:17 lc =

2(ln 2)λ 2c p(BW)

(9-6)

where λc is the center wavelength of the light source, and BW is the bandwidth of the light source at FWHM. Referring to Fig. 9-2, the light source passes through the fiber and is split to reference arm and sample arm. In the reference arm, light is reflected, traveling an optical path length of L1 before reaching the coupler again; in the sample arm, light is scattered and recollected into the fiber coupler, traveling an optical path length L2 before reaching the coupler again. Both the back-traveling lights interfere at the coupler, producing interference fringes that are detected at the photo detector. For a high-coherence light source, the interference fringes can be produced at many points in the sample, making it difficult to tell which point is sampled. Conversely, for a low-coherence light source, interference fringes can be produced only when |(L1 – L2)| < lc; thus one fringe corresponds to one point in the sample. The smaller value of lc leads to better axial resolution. In other words, broader bandwidth results in better axial resolution, and lc is used to quantify the axial resolution.

9.3.3

Evaluations of Parameters

This section evaluates all the optical parameters in the probe explained in the preceding section. Only the optical parameters of the latest version of the probe are evaluated, and that probe has a GRIN-lens diameter of 0.5 mm.

Biosensor Packaging

Parameters Available Spot radius at objective surface = 209 μm Working distance = 5 mm Center wavelength of light source = 1310 nm Bandwidth of light source at FWHM = 110 nm Using Eq. (9-3), System NA = spot radius at objective surface/working distance = 209 μm/5mm = 0.0418 Using Eq. (9-4),

2λ c p(NA)

Transverse resolution =

=

2(1310 nm) (0.0418)

= 1.995 × 10−5 m = 19.95 μm Using Eq. (9-5), DOF = =

2λ c p(NA)2 2(1310 nm) (0.0418)2

= 4.77 × 10−4 m = 477 μm Using Eq. (9-6), Axial resolution = =

2(ln 2)λ 2c p(BW) 2(ln 2)(1310 nm)2 p(110 nm)

= 6.88 μm

411

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Chapter Nine

9.4 Optical Simulation 9.4.1

Optical Model of the Probe

This section discusses the purposes, implications, applications, and results of some optical simulations done to obtain a better understanding of how the optical components of the probe work as a system. The discussion will focus only on the system using a GRIN lens with a diameter of 0.5 mm. This is so because that batch of GRIN lens is believed to be working best for the assembled probe compared with all previously developed batches. The optical design is the most important part of probe design. The imaging quality of the probe depends on proper design of the optical path and the components associated with the optical path. In optical assembly, an important criterion of performance is optical loss, which has many sources. The main sources of optical loss are the coupling between the fiber and the GRIN lens, the working distance from the GRIN lens to the micromirror, micromirror roughness, micromirror flatness, housing transparency, and the radius of curvature of the housing. The microoptical components are required to collect the light and focus the beam on the mirror. Design of the package depends on the selection of microoptical components. The dimensions and shape of the optical components will determine the final package size. The optical components’ physical properties are determined based on the optical resolution and image-quality requirements. The axial resolution of the OCT system depends on the light source. The advantage in using an optical probe is to increase the lateral resolution of the system, which depends on such optical parameters as the size of the lens, the geometry and scan angle of the MEMS mirror, the beam diameter, and the focal length of the lens. An optical simulation was performed to study beam diameter and coupling efficiency after scattering from the sample. In the initial setup, a reflective surface was used to study the coupling efficiency, and subsequently, the reflective surface was made more rough to accommodate scattering. Optical design attempts to make sure that the light will be focused at the sample (tissue) side. A GRIN lens was selected to achieve a maximum working distance and at the same time use a smaller beam diameter (BD) at the mirror side (Fig. 9-16). Beam diameter at the mirror side should be at least 50 percent smaller than the mirror diameter so that most of the light falls into the mirror even though there is a small shift in the beam owing to misalignment of the optical components. The efficiency of light collection at the MEMS mirror after scattering from the sample was calculated in the simulation (Fig. 9-17). It was found that about 50 percent of the light could be collected at the

Biosensor Packaging Input fiber: SMF 28 NA 0.095 mode field diameter: 10.4 μm Spot radius: 80 μm Spot radius: 63 μm

Spot radius: 46 μm

4 mm 2 mm Spacer : 1.06 mm GRIN lens, 0.48 mm

Mirror plane

Object plane

FIGURE 9-16 Design of GRIN lens dimensions to meet the beam-diameter requirements.

Sample BD: 33 μm

Optical fiber

GRIN lens BD: 85 μm 3D micromirror

FIGURE 9-17 Optical simulation to study beam size and coupling efficiency.

mirror, provided that the sample was a reflective surface. The collection efficiency will be degraded if the sample is rough and scattering in nature. A simulation was performed to investigate the change in coupling efficiency when the micromirror takes on different tilt orientations. A curved sample mirror was used so that maximum coupling could be obtained for all tilt orientations of the micromirror and so that the sample was always at the focal point. An optical system was built in the simulation software Zemax, as shown in Fig. 9-18. The mirror surface was coated with Au layer for

413

414

Chapter Nine Sampling mirror/detector

b

Spacer

Single mode fiber

GRIN lens a

Micromirror

FIGURE 9-18 Optical model built in Zemax for various simulations of the optical properties of the probe.

good reflection. After deposition of the Au layer and release of the mirror, the mirror tends to warp; it can be either convex or concave depending on the stress during the process. Most of the mirrors produced were concave mirrors. This concave mirror shape results in a reduced working distance. To understand the effect of a curved mirror on the assembled optical system, a simulation was performed to find out the locations of the changed working distance and coupling efficiency at the original (produced by a flat mirror) working distance (WD). The light source was modeled as a divergent Gaussian beam having an NA and diameter given by the NA and diameter of the singlemode fiber. As shown in Fig. 9-19, the light source was located at the onset of the spacer and directed to point A. The light travels through B and C. Owing to the fact that the focal point is at the sampling mirror, the light is reflected and takes the exact opposite paths. Therefore, the light travels through the micromirror to point D, then to point E, and then into the fiber, eventually coming out of the fiber at point F. To test the power loss of the system, the light intensity of the light source was set at 1 W, and detectors were placed at different points.

C

A /D F

FIGURE 9-19 Light path in the optical model of the probe.

B/D

Biosensor Packaging Detector at Point

% Power Detected

A

96.2

B

95.0

C

85.8

D

82.5

E

82.5

F

72.3

TABLE 9-1 Power Detection along the Optical Path Inside the Probe

A detector detects the power in only one direction. The detected power values are reported as a percentage of the power source, shown in Table 9-1. In reality (not simulation), light is collimated into a curved fiber at point F, passing through the probe and back to point F. Thus the power obtained using the simulation can give a fair estimate (but often overestimate) of the actual power going back to point F. The percentage power going back to point F is called the coupling efficiency. The coupling efficiency of the probe from the simulation was 72.3 percent.

9.4.2

Effect of Mirror Curvature on Coupling Efficiency

The micromirror is designed to be flat. Unfortunately, owing to process complications during deposition of the wafer layers, uncharacterized internal stress is generated, causing the micromirror to have a certain curvature. Most of the mirrors produced are concave, and thus the problem corresponds to a reduced working distance. To understand the effect of a curved mirror on the assembled optical system, a simulation was done to find out the locations of the changed working distance and coupling efficiency at the original (produced by a flat mirror) working distance (WD). Simulation results are plotted in Figs. 9-20 through 9-22. Effect of curvature on coupling efficiency is plotted in Fig. 9-20. From the results, it is found that the coupling efficiency decreases with an increase in mirror curvature and drops exponentially when the radius of curvature of the mirror falls below 160 mm. From the plot, the curvature of the mirror has to be smaller than 0.66 × 10–2 mm–1 (radius of curvature has to be larger than 152 mm) to prevent the coupling efficiency from falling below 60 percent. Optimization of mirror design and processing is necessary to improve the curvature of the mirror. From the results shown in Fig. 9-21, the percent reduction in working distance is approximately linearly correlated with the curvature.

415

416

Chapter Nine

% Coupling efficiency

80.00 70.00 60.00 50.00 40.00 30.00 20.00 10.00 0.00 0.0 5.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 0E+ 0E– 0E– 0E– 0E– 0E– 0E– 0E– 0E– 0E– 0E– 0E– 0E– 0E– 0E– 0E– 0E– 0E– 0E– 00 03 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 Curvature (inverse of radius of curvature, mm)

% Reduction in working distance

FIGURE 9-20 Effect of curvature on coupling efficiency.

35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 0.0E+00 1.0E–02 2.0E–02 3.0E–02 4.0E–02 5.0E–02 6.0E–02 7.0E–02 8.0E–02 9.0E–02

Curvature (inverse of radius of curvature, mm)

FIGURE 9-21 Effect of curvature on working distance.

Negative-tilt focal line Positive-tilt focal line Curved sample mirror following focal line Radius of focal line = b

b

Tilt angle of mirror = 45° + 16°

FIGURE 9-22 Tilted fold mirror and curved sample mirror in the optical system.

Biosensor Packaging Radius of Curvature (mm)

Curvature (mm–1)

12

8.3 × 10–2

13

WD (mm)

% Change in WD

3.1

3.48

32.9

7.7 × 10

3.2

3.55

31.6

20

–2

5.0 × 10

3.7

3.92

24.5

22

4.5 × 10–2

4.1

3.99

23.1

28

3.6 × 10

5.2

4.18

19.5

35

2.9 × 10

7.4

4.33

16.6

40

2.5 × 10

9.2

4.43

14.6

50

–2

2.0 × 10

15.1

4.54

12.5

500

2.0 × 10–2

70.7

5.11

1.5

Infinity

0.0

72.3

5.19

0.0

–2

–2 –2 –2

% Efficiency at Original WD

TABLE 9-2 Effect of Micromirror Curvature on Coupling Efficiency and Working Distance

Estimating directly from the plot, to maintain the working distance within 5 percent, the curvature of the mirror has to be smaller than 0.75 × 10–2 mm–1 (radius of curvature has to be larger than 133 mm). It was concluded from this investigation that coupling efficiency is more sensitive to the curvature problem, and the results are listed in Table 9-2.

9.4.3 Effect of Lateral Tilt of a Flat Micromirror on a Curved Sample The micromirror has an initial position that is laterally tilted 45 degree relative to the GRIN lens objective surface. Defining zero tilt angle as when the micromirror is parallel with the GRIN lens objective surface, a positive tilt is one that directs the rays away from the probe. A simulation was done to investigate the change in coupling efficiency when the micromirror takes on different tilts. The sample used was a concave mirror having a radius of curvature equal to b in Fig. 9-22. A curved sample mirror was used so that maximum coupling could be obtained for all tilt orientations of the micromirror and so that the sampled point was always at the focal point. From the results it is clear that positive tilts result in more loss than negative tilts. The loss of optical power increases steadily as the angle of positive tilt is increased. On the negative half of the plot, there is no significant change in coupling efficiency when there is a change in tilt. An optical coupling study was done with angle of tilt of ±16 degrees and 45-degree mirror placement and found that there

417

Chapter Nine 72 70 Coupling, %

418

68 66

Positive tilt

64

Negative tilt

62 60 58 1

3

5

7 9 11 Tilt angle from 45°

13

15

FIGURE 9-23 Efficiencies at various lateral tilts.

is a 10 percent coupling loss with the positive tilt, whereas there is no significant drop with negative tilt (see Fig. 9-23). This means that image compensation in programming is required only when the mirror directs light away from the probe in positive tilt. The system consists of all optical elements in perfect condition; thus there is no scattering. In the diagram (Fig. 9-18), a + b = WD. Fresnel reflection from surface to surface is taken into account in calculation of the data obtained from the simulation. The single-mode fibers are adjusted to be very near to each other so that their distance is negligible. The spacer is a glass component with a single refractive index similar to that of BK7 glass. This component is considered to be closely attached to the GRIN lens, so the air gap and surface transition between them are neglected (although, in reality, there is a small gap that may be filled with transparent adhesive or air). In the exposed (objective) surface of the GRIN lens, the model, matching reality, includes an antireflection (AR) coating to prevent backreflection. The micromirror folds the light by 90 degrees to hit the sampling mirror. A detector was superimposed on the sampling mirror. Obtaining the change in coupling efficiency at different tilts serves as a check of the consistency of the optical functionality of the probe. This information can be used for programming in image construction so that the inherent inconsistency factor can be removed to produce a more accurate image. Table 9-3 presents the results obtained. From the results in Table 9-3 , it is clear that positive tilts result in more loss than negative tilts. The loss of optical power increases steadily as the angle of positive tilt is increased. On the negative half of the plot, there is no significant change in coupling efficiency when the tilt is changed. This means that only while the mirror directs light away from the probe is there a need for imaging compensation in programming.

Biosensor Packaging Positive Tilt from 45°

% Coupling

Negative Tilt from 45°

% Coupling

1

69.36

1

69.37

2

69.27

2

69.23

3

68.59

3

69.31

4

68.97

4

69.74

5

68.37

5

69.86

6

67.95

6

70.04

7

68.44

7

70.23

8

68.16

8

69.08

9

67.48

9

69.82

10

66.68

10

69.66

11

66.26

11

69.44

12

66.19

12

69.60

13

65.20

13

69.63

14

64.19

14

69.77

15

63.91

15

69.77

16

62.44

16

69.88

TABLE 9-3 Efficiencies at Various Lateral Tilts

For the same experiment, if a flat sampling mirror is used instead, after a small tilt (from the initial 45 degrees) of the micromirror, many points of the sample will be out of focus and thus will give very small coupling efficiencies. In such a case, only small-angle tilts need to be investigated because large tilts result in no coupling. The purpose of this investigation will be discussed in the next section. When investigating small-angle tilt, to avoid complications with lateral tilt, tilt in an axis perpendicular to the lateral tilt axis was used; we denote this as the vertical tilt axis. The lateral tilt axis is the y axis (tilting about the y axis that passes through the center of the mirror), whereas the vertical tilt axis is the x axis (tilting about the x axis) passing through the center of the mirror.

9.4.4 Effect of Vertical Tilt of a Flat Micromirror on a Curved Sample This section discusses the simulation done to the system as shown in Table 9-4 except that the micromirror is in its initial position laterally but is vertically tilted. The purpose of this investigation was the same

419

420

Chapter Nine Positive Tilt from 0°

% Coupling

Negative Tilt from 0°

% Coupling

1

69.51

1

69.72

2

69.44

2

69.20

3

69.64

3

69.56

4

69.01

4

69.52

5

69.40

5

69.24

6

68.80

6

69.56

7

68.77

7

69.23

8

69.72

8

69.44

9

69.21

9

69.76

10

69.13

10

69.88

11

69.29

11

69.59

12

69.13

12

68.96

13

69.70

13

69.41

14

69.42

14

69.25

15

69.40

15

68.91

16

68.86

16

69.35

TABLE 9-4 Efficiencies at Various Vertical Tilts

as the previous simulation but at another tilt axis. Referring to Fig. 9-22, positive tilt refers to tilt in which the mirror surface turns out from the diagram to face the reader. The results suggest that there is no large variation in coupling efficiency when the vertical tilt is changed. The coupling efficiency is consistent with a small fluctuation from 69.3 percent except at zero tilt, when the coupling efficiency is higher by 3 percent. It is not clear why there is higher coupling at zero tilt when the sample used is a perfect curved mirror. An experiment may have to be carried out to investigate the accuracy of the simulation and to determine the reason of the discrepancy.

9.4.5 Effect of Vertical Tilt of a Flat Micromirror on a Flat Sample The purpose of this simulation was to determine the angular accuracy that is acceptable for the system. Use of a flat micromirror and a flat sample is ideal in examining the change in efficiency. The results of the simulation are tabulated in Table 9-5.

Biosensor Packaging Positive Tilt from 0°

% Coupling

Negative Tilt from 0°

% Coupling

0.125

65.33

0.125

66.01

0.250

61.23

0.250

61.00

0.375

54.64

0.375

54.82

0.500

48.37

0.500

47.90

0.625

41.87

0.625

42.04

0.750

34.10

0.750

34.08

0.875

27.92

0.875

28.09

1.000

20.70

1.000

21.04

2.000

3.00

2.000

3.00

TABLE 9-5

Efficiencies at Various Small Vertical Tilts of a Flat Sample Mirror

From the results plotted, it can be seen that the effect is symmetric for positive tilt and negative tilt. The plot suggests that to preserve the coupling efficiency above 60 percent, the vertical tilt allowed during assembly is 0.25 degree. Therefore, the mirror chip has to be placed on the trench in the lower substrate with a tolerance as small as 0.25 degree. However, practically, this may not be possible. What has to be done practically is to adjust the relative position of the mirror with the GRIN lens by moving the GRIN lens using a precision alignment stage.

9.5 Assembly of the Optical Probe 9.5.1

Fabrication of SiOB

The driving factor in developing a probe is to miniaturize the overall dimensions. This is a challenge for probe packaging. The optical components and the mirror need to be packaged in a miniaturized format, and at the same time, the packaging material must be transparent to infrared (IR) light. In the current design, a wavelength of 1300 nm is used in shining the light on the sample.24–28 Selection of a substrate for packaging should meet both optical and miniaturization requirements. Silicon is a good material for micromachining to create smaller dimensions to meet the miniaturization requirement, and it is transparent to IR wavelengths. The targeted diameter of the probe is 4 mm. An 8-in wafer is used to fabricate the SiOB structures. Since KOH etching cannot make 45-degree trenches, the structures are made on a wafer with a 45-degree shift. The structure is rotated at 45 degrees, and

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Chapter Nine the trenches are made. While singulating the device, the wafer has to be mounted carefully to offset the 45-degree-angle trench. The Si wafer is micromachined to form a slot to attach the three-dimensional (3D) micromirror. The depth of the trench is calculated to make sure that the mirror pads are aligned with metal traces to form an interconnection. Cr + Au underbump metallizations (UBMs) are deposited on the silicon wafer by the sputtering method. The sputtered metal is patterned by lithographic technique. The pitch of the metal traces is about 150 μm with a width of 125 μm. The tight dimensions are required to meet the probe size of 4 mm in diameter. The metal traces are formed on the trenches and are extended to the end of the silicon optical bench to connect to the external world. The GRIN lens and fiber are attached to a silicon optical bench. Placement of the GRIN lens is such that the optical axis is in line with the center of the MEMS 3D micromirror.

9.5.2 Probe Assembly Assembly of the probe starts with attachment of the GRIN lens and fiber to the silicon optical bench (Fig. 9-24). In this development, an integrated GRIN lens with fiber is used, and hence there is no need to align the fiber and lens separately. An ultraviolet (UV)–cure epoxy is used to attach the GRIN lens and the fiber to the bench. The 3D micromirror is attached to another SiOB structure that has a 45-degree trench in which to place the mirror (Figs. 9-25 and 9-26). The lower

45 degree trench for mirror placement

Metal trace for electrical connection to micromirror

FIGURE 9-24 Silicon optical bench for 3D micromirror.

Biosensor Packaging

Metal pads for electrical connection

Spring

Actuator

FIGURE 9-25 Mirror device on the silicon substrate.

(a)

(b)

FIGURE 9-26 Electrical connection of mirror device with solder balls.

substrate with the micromirror is bonded to the upper substrate, which has the GRIN lens and fiber. The micromirror is attached vertically into the trench formed on the lower substrate. Solder balls are used to attach the micromirror to the trench, on whose sidewall are formed the trace lines for the power supply.1,2 The lower and upper substrates are optically aligned in an optical assembly stage before bonding together by the UV-cure method (Fig. 9-27). Solder balls are attached to the mirror device and are subjected to reflow (Fig. 9-28) A pick-and-place machine grasps the mirror and

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GRIN lens

Fiber

FIGURE 9-27 GRIN lens and fiber attached to the SiOB substrate.

3D MEMS mirror

Metal traces

Solder interconnect

FIGURE 9-28 3D micromirror interconnected to the SiOB substrate with solder balls.

attaches it to the silicon substrate. The solder balls on the mirror contact the metal traces on the bench. The solder-interconnected mirror with the silicon substrate is reflowed again to form the final interconnection to the external world. The lower substrate with the micromirror is bonded to the upper substrate with the GRIN lens and fiber (Fig. 9-29). The micromirror is attached vertically into the trench formed on the lower substrate. Solder balls are used to attach the micromirror to the trench, on whose sidewalls the trace lines for the power supply are formed.20,21 The lower and upper substrates are optically aligned in an optical assembly stage before bonding by the UV-cure method (Fig. 9-30).

Biosensor Packaging

Housing cap

Probe assembly

FIGURE 9-29 Probe assembly with mounting cap.

Applied voltage for mirror switching

Mirror aligned to GRIN lens

GRIN lens

ror

r

Mi

Sample

FIGURE 9-30 GRIN lens aligned with micromirror.

9.5.3 Probe Housing The housing of the probe is important for in vivo imaging applications. Since the wavelength used for illuminating the sample is 1300 nm, the material used for the housing should have 100 percent transparency at this wavelength. Also, the size demanded for this housing is less than 4 mm; normal manufacturing methods cannot

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Chapter Nine meet this requirement. A micro-injection-molding method is used to fabricate the probe housing. Probe size is a limiting factor for material selection, and in addition, the wall thickness of the housing needs to be controlled. A wall thickness of 0.2 mm is used in this probe development. The material used is a polycarbonate that has transparency of greater than 95 percent for 1300-nm light. Since the probe is about 25 mm long, a single micromold will provide additional stress to the probe, and this will generate bending or warpage of the probe. In view of this, two molds are used to fabricate the probe housing. The closedtip part where the mirror is located is separated from the main body. They are joined together after at final assembly of the probe housing. Assembly of the probe inside the housing is another important requirement in final probe housing development. Since the probe requires power for the mirror to rotate and the optical fiber is to illuminate the mirror with IR light, assembly of the probe in the housing

Alignment

Electrical/ optical interface

FIGURE 9-31 Optical probe in a biocompatible housing.

Optically transparent polycarbonate housing

SiOB substrate

MEMS 3D micromirror

FIGURE 9-32 Completed probe in a biocompatible housing.

Biosensor Packaging Electrical connection to MEMS mirror actuation

Optical probe in bio compatible plastic housing Optical fiber to light source

FIGURE 9-33 Probe with optical fiber and the electrical feed-through.

needs to meet these requirements without damaging the probe. Special microconnections are used to connect the traces on the lower substrate to the micromirror. The fiber is taken out from the probe housing using a special groove so that no big holes are left on the housing when the optical fiber and power supply lines are taken out (Fig. 9-31). Figures 9-32 and 9-33 show the probe with optical fiber and electrical feed-through. An injection-molding process was used to fabricate the housing.

9.6 Testing of the Probe 9.6.1 Optical Alignment Optical alignment is done in an optical bench. A three-axis optical stage is used to align the micromirror with the GRIN lens and fiber. The assembled upper substrate with GRIN lens and fiber is bonded with the lower substrate with the micromirror. Special fixtures are made to hold the bonded substrates. Before bonding the upper substrate with the lower substrate, the GRIN lens is aligned with the micromirror by adjusting the lateral movement of the upper substrate. The alignment is made by fine-tuning the three axes in the optical stage, and this is repeated until optimal coupling efficiency is obtained. The optical-alignment setup is shown in Fig. 9-34.

9.6.2 Axial Scanning Test Result This section presents the results obtained using the probe assembled as described in Sec. 9.4.1. Since the micromirror is not capable of tilting, only axial scanning is possible. External samples used were a flat mirror and a slab of glass. The simulated samples were chosen because of their high transmission of IR rays so that a greater depth can be scanned. As the external mirror in the reference arm is moved, the optical path length L1 is changed, and the depth scanned in the

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Jigs Mirror 1 rotated 45° of the optical path

Port 3

Port 2

Port 1

3.5 mm 1.5 mm Mirror 2 as full reflective sample

Circulator

GRIN lens

FIGURE 9-34 Optical testing setup for aligning the fiber with the mirror.

Interference signal, V

sample is also changed, corresponding to L2 within tolerance of lc [in other words, (L1 – lc) > L2 > (L1 + lc)]. Figure 9-35 shows the interference signal received in the time-domain OCT system by axial scanning of a simulated sample using a flat mirror.

0.1

0.05

0 0

1

2 3 Depth axis, mm

4

FIGURE 9-35 Interference signal obtained from a mirror package detecting a sample that is a flat mirror.

Biosensor Packaging

Interference signal, V

0.02 0.015 0.01 0.005 0

0

1

2 3 Depth axis, mm

4

FIGURE 9-36 Interference signal obtained from a mirror package detecting a sample that is a glass slab.

Results from Fig. 9-36 suggest that the reflective plane inside the sample mirror is 2.5 mm from the reference zero location (this location is the first to be sampled and imaged), resulting in a very strong signal interference at this point. This result can be used to estimate the signal-to-noise ratio (SNR) of the probe. The maximum magnitude of the interference signal is 0.1 V; the maximum magnitude of the background noise is about 0.01 V; thus the SNR is 10, or 10 dB. Results from Fig. 9-36 also suggest that the reflecting surfaces are at 1.4 and 3.7 mm. Thus we can infer the thickness of the glass slab to be the difference, that is, 2.3 mm. Note that the signal is lower at 3.7 mm than that at 1.4 mm. Assuming that the glass slab is nearly perfectly symmetric on both surfaces, this difference in signal magnitude can be accounted for by the absorption and scattering of light inside the glass slab.

9.6.3 Probe Imaging Imaging of the sample with the completed probe was investigated. It was found that image resolution was not as good as with the conventional OCT setup. The reason for the lower-resolution image is that not enough light was collected from the sample. The main factors contributing to this are the mirror curvature and the NA of the GRIN lens. The smaller the NA, the lower is the light-collection efficiency. Another factor is the aberration of light owing to the small curvature of the housing that slightly distorts the beam from the mirror to the sample and eventually reduces the intensity of the beam. Since the working distance of the beam is fixed, there is a change in the depth of the focus of the beam when the mirror starts scanning the beam into the tissue. The shift in the depth of the focus of the

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(a)

(b)

FIGURE 9-37 (a) En face image obtained by a conventional optical microscope. (b) OCT en face image.

beam affects the axial resolution of the image and, in turn, affects the image quality. Images have been acquired with the probe assembly, and the images obtained have been found to be comparable with those obtained with the commercial OCT setup. Both en face and 3D OCT images acquired by the two-axis MEMS scanning probe are shown in Fig. 9-37. An IR viewing card (VC-VIS/ IR, Thorlabs, United States) consisting of a transparent polymer surface and a photosensitive material beneath the surface was used as an imaging target. As a reference image, an en face image in the IR viewing card was obtained by a conventional optical microscope with a 0.75-NA objective lens and 1550-nm light for illumination, and this is shown in Fig. 9-37a. Figure 9-37b shows an en face OCT image of an arbitrary 2D plane in a relative small region of the IR viewing card with approximately 20-μm transverse resolutions and approximately 12-μm axial resolutions in air. The usual penetration depth of the OCT probe in a biologic sample is 2 to 3 mm because the biologic sample scatters the IR light extensively (thus large signal attenuation).29–34 However, from the results obtained, it can be seen that the OCT probe is able to scan 3 to 4 mm because the samples are not biologic tissues and possess high transmission and low attenuation to the light source. The orthogonal slices of OCT images acquired by the probe from IR viewing card are shown in Fig. 9-38.

Biosensor Packaging

Axial

Sagittal

Coronal

FIGURE 9-38 Orthogonal slices of OCT images acquired by the probe from an IR viewing card.

9.6.4 Optical Efficiency Testing This section introduces the procedures to evaluate actual optical efficiency in an assembled probe. The procedure is useful as a quality assurance process so that only probes that are actually useful will be sent out for testing on tissue samples. Tissue samples have high scatter, so probes with poor coupling efficiency cannot provide a good SNR testing. The procedures involved are listed as follows: 1. After completion of an assembled probe, additional materials to obtain for optical testing are an external mirror (a round or prismshaped mirror is equally acceptable), a rotation stage, and adjustment fixtures that can control the orientation of the mirror. 2. Remove the translation stage from the optical work desk. Place the rotation stage in the designed position on the optical work desk. 3. Fix the mirror onto the mirror post, followed by fixing the mirror post onto the post holder. Place the post holder onto the rotation stage, and tighten the rotation stage that holds the post holder. 4. Clip the probe using the left fixture support on the translation stage. Use the translation stage to move the probe toward the external mirror; no precision is required. 5. Construct the fiberoptic configuration as shown in Fig. 9-39. The laser source is adjusted to a 1310-nm wavelength for a GRIN lens of 0.5-mm diameter, with power calculated in step 6.

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Port 1/port A Optical circulator

Port 2/port B

Endoscopic probe

Port 3/port C Optical power meter Arrows indicate direction of light

FIGURE 9-39 Schematic diagram for configuration of the optical table.

6. To obtain a 0-dBm output displayed at the optical power meter, you can calculate the loss that is expected along the optical pathway and set the power of the laser source. The data available are that connector loss is 1 dB each, and probe efficiency is 0.723 (from Table 9-6). dB loss = –10 log(output power/input power ) dB loss of the probe = 1.4 dB Thus the power of laser source should be set to at least 5.8 dBm (3.8 mW) to get an output of 0 dBm. Note that a power reading obtained in the experiment that is lower than calculated is normal. 7. Move the translation stage so that the probe is placed the correct distance from the external mirror. As in Fig. 9-18 the distance from the center of the micromirror to the external mirror has to roughly equal b.

Direction

Component of Loss

dB Loss

Source to circulator

Connector

1.00

Circulator port 1 to 2

Circulator

0.65

Circulator to probe

Connector

1.00

Probe to sample mirror and back to probe

Probe

1.40

Circulator port 2 to 3

Circulator

0.75

Circulator to power meter

Connector

1.00

Total

5.80

TABLE 9-6 Calculation of Optical Power Loss in Optical Efficiency Testing

Biosensor Packaging 8. Adjust the tilt of the external mirror until the power reading shows an increment. Find the tilt orientation that results in largest power reading. 9. Fine-tune the distance between the micromirror and the external mirror again, until the maximum power reading is obtained. The maximum should be near 0 dBm.

References 1. Fujimoto, J. G. “Optical coherence tomography” C. R. Acad. Sci. Paris 2:1099–1111, 2001. 2. Aguirre, A. D., Herz, P, R., Chen, Y., Fujimoto, J. G., Piyawattanametha, W., Fan, L., Hsu, S.-T., Fujino, M., and Wu, M. C. “Ultrahigh resolution OCT imaging with a two-dimensional MEMS scanning endoscope.” In Photonics West 2005, Advanced Biomedical and Clinical Diagnostic Systems, Vol. III, Session 11, 5692–5649 Proc. SPIE, 5692:277, 2005. 3. Daoyin, Y., Wanhui, L., Yi, W., and Xiaodong, C. “Design of endoscopic optical coherence tomography system.” Proc. SPIE, 6026:60260N, 2006. 4. Su, J., Zhang, J., Yu, L., and Chen, Z. “In vivo three-dimensional microelectromechanical endoscopic swept source optical coherence tomography.” Opt. Exp., 15(16):10390–10396, August 2007. 5. Tran, P. H., Mukai, D. S., Brenner, M., and Chen, Z. “In vivo endoscopic optical coherence tomography by use of a rotational microelectromechanical system probe.” Opt. Lett. 29:1236–1238, 2004. 6. Tumlinson, A. R., Považay, B., Hariri, L. P., McNally, J., Unterhuber, A., Hermann, B., Sattmann, H., Drexler, W., and Barton, J. K. “In vivo ultrahighresolution optical coherence tomography of mouse colon with an achromatized endoscope.” J. Biomed. Opt. 11(6):064003, 2006. 7. Chamot, S. R., and Depeursinge, C. “MEMS for enhanced optical diagnostics in endoscopy.” Minimally Invas. Ther. 16:101–108, 2007. 8. Chong, C., Isamoto, K., and Toshiyoshi, H. “Optically modulated MEMS scanning endoscope.” IEEE Photon. Technol. Lett. 18(1):133–135, Jan. 1, 2006. 9. Bernsteina, J. J., Leea, T. W., Rogomenticha, F. J., Bancua Ki, M. G., Kimb, H., Magulurib, G., Boumab, B. E., and DeBoer, J. F. “Scanning OCT endoscope with 2-axis magnetic micromirror.” Proc. SPIE, 6432:64320L, 2007. 10. Bo’hringer, H. J., Boller, D., Leppert, J., Knopp, U., Lankenau, E., Reusche, E., Hu’ttmann, G., and Giese, A. “Time-domain and spectral-domain optical coherence tomography in the analysis of brain tumor tissue.” Lasers Surg. Med. 38:588–597, 2006. 11. McCormick, D. T., Jung, W., Ahn, Y.-C., Chen, Z., and Tien, N. C. “A three dimensional real-time MEMS based optical biopsy system for in-vivo clinical imaging.” Presented at the 14th International Conference on Solid-State Sensors, Actuators and Microsystems, Lyon, France, June 10–14, 2007. 12. Douglas, H. N., Kindred, S., and Moore, D. T. “Index profile control using Li+ for Na+ exchange in aluminosilicate glasses.” Appl. Opt. 29(28):4056–4060, 1990. 13. Grintech, “Introduction to gradient index optics;” available at www.grintech.de/; accessed on May 13, 2007. 14. Knittel, J., Schiender, L., Buess, G., et al. “Endoscope-compatible confocal microscope using a gradient index-lens system.” Opt. Commun. 188:267–273, 2001. 15. Lee, K. S., Wu, L., Xie, H., et al. “A 5-mm catheter for constant resolution probing in Fourier domain optical coherence endoscopy.” In Endoscopic Microscopy II. Edited by Tearney, Guillermo J.; Wang, Thomas D. Proc. SPIE, 6432:64320B, 2007. 16. Lexer, F., Hitzenberger, C. K., Drexler, W., et al. “Dynamic coherent focus OCT with depth-independent transversal resolution.” J. Mod. Opt. 46:541–553, 1999.

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Chapter Nine 17. Tran, P. H., Mukai, D. S., Brenner, M., et al. “In vivo endoscopic optical coherence tomography by use of a rotational microelectromechanical system probe.” Opt. Lett. 29:1236–1238, 2004. 18. Yaqoob, Z., Wu, J., McDowell, E. J., et al. “Methods and application areas of endoscopic optical coherence tomography.” J. Biomed. Opt. 11:06301, 2006. 19. Premachandran, C. S., Chen Wei Sheng, K., Singh, J., Teo, J., Xu Yingshun, Nanguang, C., Sheppard, C., Olivo, M. “Design, fabrication and assembly of an optical biosensor probe package for OCT (optical coherence tomography) application.” Electronic Components and Technology Conference, 2007 Proc. 7: 1556–1560, May 29 2007–June 1 2007. 20. Premachandran, C. S. Khairyanto, A., Chen, K., and Singh, J. “A biocompatible miniaturized package housing for a 3D micro mirror based optical bio-probe for OCT imaging application.” Photonics West, Proc. SPIE, 6887:688708 (2008J). 21. Zysk, A. M., Nguyen, F. T., Oldenburg, A. L., Marks, D. L., and Boppart, S. A. “Optical coherence tomography: A review of clinical development from bench to bedside.” J. Biomed. Opt. 12:051403, 2007. 22. Yaqoob, Z., Wu, J., McDowell, E. J., Heng, X., and Yang, C. “Methods and application areas of endoscopic optical coherence tomography.” J. Biomed. Opt. 11:063001, 2006. 23. Tearney, G. J., Brezinski, M. E., Bouma, B. E., Boppart, S. A., Pitris, C., Southern, J. F., and Fujimoto, J. G. “In vivo endoscopic optical biopsy with optical coherence tomography.” Science 276:2037, 1997. 24. Huang, D., Swanson, E. A., Lin, C. P., Schuman, J. S., Stinson, W. G., Chang, W., Hee, H. R., Flotte, T., Gregory, K., Puliafito, C. A., and Fujimoto, G. “Optical coherence tomography.” Science, 254:1178–1181, 1991. 25. Bouma, B. E., Yun, S. H., Oh, W. Y., Shishkov, M., de Boer, J. F., and Tearney, G. J. “Latest developments in optical coherence tomography” Lasers and Electro-Optics Society, 2004. LEOS 2004. The 17th Annual Meeting of the IEEE, 2:761–769. 26. McCormick, D. T., Jung, W., Chen, Z., and Tien, N. C. “3-D MEMS based minimally invasive optical coherence tomography.” In Proceedings of Transducers ’05, 13th International Conference on Solid State Sensors, Actuators and Microsystems— Digest of Technical Papers, 2:1644–1648, Seoul, Korea, 2005. 27. Xie, T., Xie, H., Fedder, G. K., and Pan, Y. “Endoscopic optical coherence tomography with new MEMS mirror.” Electron. Lett. 39(21):1535–1536, 16 Oct. 2003. 28. Jung, W., McCormick, D. T., Zhang, J., Wang, L., Tien, N. C., and Chen, Z. P. “Three-dimensional endoscopic optical coherence tomography by use of a two axis microelectromechanical scanning mirror.” Appl. Phys. Lett. 88:163901, 2006. 29. Aguirre, A. D., Herz, P. R., Chen, Y., Fujimoto, J. G., Piyawattanametha, W., Fan, L., and Wu, M. C. “Two-axis MEMS scanning catheter for ultrahigh resolution three-dimensional and en face imaging.” Opt. Exp. 15:2445, 2007. 30. Lee, K.-S., Koehler, C., Johnson, E. G., Teuma, E. V., Ilegbusi, O., Costa, M., Xie, H., and Rolland, J. P. “2-mm catheter design for endoscopic optical coherence tomography” Proc. SPIE-OSA 6342:63420F-1–63420F-9, 2006. 31. McCormick, D. T., Jung, W., Chen, Z., and Tien, N. C. “3-D MEMS based minimally invasive optixal coherence tomography” Presented at the 13th International Confcrence on Solid-State Sensors, Actuators and Microsystems, Seoul, Korea, June 5–9, 2005. 32. Jain, A., Kopa, A., Pan, Y., Fedder, G. K., and Xie, H. “A two-axis electrothermal micromirror for endoscopic optical coherence tomography.” IEEE J. Select. Topics Quantum Electron., 10(3): 636–642, May–June 2004. 33. Sharma, U., and Kang, J. U. “Common-path optical coherence tomography with side-viewing bare fiber probe for endoscopic optical coherence tomography.” Rev. Sci. Instrum. 78:113102, 2007. 34. Wang, Z. G., Adler, H., Chan, D., Jain, A., Xie, H. K., Wu, Z. L., and Pan, Y. T. “Cystoscopic optical coherence tomography for urinary bladder imaging in vivo.” Coherence Domain Optical Methods and Optical Coherence Tomography in Biomedicine X. Edited by Tuchin, Valery V.; Izatt, Joseph A.; Fujimoto, James G. Proc. SPIE, 6079:91–99, 2006.

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Accelerometer Packaging 10.1 Introduction Microelectromechanical systems (MEMS) technology is penetrating every part of the electronics market and replacing existing technology with its advantages of smaller size and higher sensitivity. When replacing the conventional products with MEMS devices, one major drawback is the cost of the device. Since MEMS devices can be made with silicon wafers that have considerable yield, the overall device cost requirement can be met but final packaging costs are high compared with conventional devices. The main contributor to the higher cost is the packaging. An examination of packaging requirements reveals that MEMS packaging is unique and has special requirements such as hermetic sealing and vacuum or gas inside the package. These requirements can be met only by expensive metal/ceramic packages and lead to the higher cost. Thus a new solution has to be found to meet MEMS packaging requirements while keeping the price competitive with that of conventional packaging. New package development always attempts to use the old standards and existing processes to reduce manufacturing costs. Standard packages, available in ceramic and plastic, are made with respect to packaging standards. Since MEMS devices are replacing existing products and providing performance advantages, the package format has to closely follow that of conventional products. It is well known that MEMS packages are very unique based on their applications. Thus a generic package needs to be developed that keeps assembly costs low. A ceramic/metal package is a readily available solution, but the cost to market is high. Looking into new packaging approaches, wafer-level packaging technology is promising as a lowcost option. Wafer-level packaging (WLP) has been explored and found to provide a batch process with high yield and fewer assembly processes.

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Chapter Ten Using a wafer-level packaging method, package size can be reduced to almost the same size as the chip, and the cost of the package can be lowered by batch process. When considering a MEMS package in wafer-level form, one additional requirement is to protect the sensing element of the device. An additional hermetic encapsulation is required to protect the MEMS moving/sensitive part. This additional cap requirement prevents us from using conventional waferlevel packaging methods. A new methodology has to be developed for wafer-level packaging of MEMS devices. Conventional wafer-level packaging is surface-mountable and can meet the standard requirements of the integrated circuit (IC) packaging industry. The advantages of standard surface-mount technology include reduced package footprint, thin profile, reduced weight, better electrical performance, and an area-array distribution of interconnections. Meeting these requirements with wafer-level packaging for MEMS devices will reduce the overall cost of those devices. This will be an added advantage in the competition between MEMS devices and conventional devices. Cost and size reductions are driving the packaging industry to new measures and approaches. Wafer-level packaging is one of the approaches the packaging industries are looking into for size and cost reduction. Since wafer-level packaging is a batch process and results in an almost a true chip-size package, cost and size can be reduced. A further reduction in size can be achieved by integrating different devices into a single package. This is done by stacking (1) different chips vertically at the chip level or (2) different device wafers.1 Stacking wafers vertically and making them into a final package by singulation can save many assembly process steps. Vertical stacking/ integration of wafers is based on thinning, bonding, and interconnecting the wafer by through-hole filled-via interconnects. Current packaging trends show that vertical interconnects are favored because of space efficiency, design simplicity, heterogeneous integration, and low parasitic capacitance and impedance. Through-wafer vias are essential for providing interconnects between both sides of wafers with microdevices. By forming through-hole via interconnects, a vertical wafer-level package has been realized, and the vias are essential for providing signal transmission. The package is shown in Fig.10-1.2 This chapter uses a bottom-up approach electroplating process for forming through-hole vias for MEMS wafers. In this electroplating method, a seed layer such as gold or copper is required at the bottom of the via, and this has been achieved by using another wafer known as a handler wafer. The required seed-layer metallization is formed on the handler wafer and is bonded to the through-hole-via wafer. Bonding of the wafer is done by thermocompression Au-Au bonding or Cu-Cu bonding. The bonded wafer is transferred to an

Accelerometer Packaging Solder interconnection

Solder ball

ASIC/cap wafer

Cavity

Copper filled through silicon via

MEMS device

FIGURE 10-1 device.

Cross-sectional view of a vertical wafer-level package for a MEMS

electroplating bath, and the vias are filled through. Once the via filling process is completed, the handler wafer is separated by grinding. During grinding, the sacrificial wafer sometimes breaks or is difficult to separate owing to poor wafer bonding or vias that are strongly rooted to the handler wafer. A wafer bonder is used to bond the through-hole via and handler, wafers and the bonding parameters must be optimized to achieve optimal bonding quality. The bonding between the handler and through-hole via wafers has to be good because the handler wafer will be separated later in the wafer-grinding process. The grinding process is done by lapping and chemical/mechanical polishing (CMP). Since it is a mechanical process, defects such as microcracks and chipping can occur during grinding. These microcracks can propagate further, leading to chip-outs as the grinding process advances in the handler wafer. When there is no uniformity on the handler wafer, the machine stops automatically, and further grinding/polishing process will cease. Instability in bond quality and defects during the grinding process present a bottleneck to separation of the handler wafer from the through-hole via wafer. Throughhole via preparation, wafer bonding, and wafer separation are described in subsequent sections.

10.2 Wafer-Level Package Requirements Wafer-level packaging is required when package size is a constraint for the final product. Two large-volume products that require waferlevel packages are accelerometers and radiofrequency (RF) MEMS devices are used in mobile and handheld applications (Fig. 10-2). Simulations are required to understand the stresses acting on MEMS structures during bonding and how wafer-level packages behave in high-frequency applications.

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Comb structure

FIGURE 10-2 An accelerometer.

10.2.1 Electrical Modeling Wafer-level packaging is essential to RF applications so that interconnect distance becomes small. The unprecedented development of wireless and mobile communications systems for commercial purposes has triggered the demand for high-performance, low-weight, and low-cost RF MEMS devices.1,2 The special needs of RF MEMS devices, such as environmental protection, hermetic/vacuum sealing, low interconnect resistance, and low insertion loss, make the packaging design process a complex procedure.3–6 Owing to the RF nature of the signal that has to be provided to MEMS devices, the packaging has to accommodate such effects as parasitic coupling and interference. Shorter paths for the signal are desirable so that parasitic effects are smaller. This is another reason for the renewed interest in wafer-level packaging with through-hole vias and bumps. The final package can be attached as a surface-mountable unit. A similar package structure has been reported and studied,3 but electrical characterization of the interconnect and the influence of different cap-wafer materials have not been studied. The proposed structure consists of a cap wafer that provides mechanical and environmental protection, as well as hermetic sealing, of the RF MEMS device. The internal environment in the enclosure formed by the cap and substrate can be controlled (i.e., vacuum, gas, etc.). The through-hole vias and bumps provide interconnection of the electrical path for the RF signals and power from the printed circuit board (PCB).

10.2.2 Package Structure A cross section of the proposed package structure is shown in Fig. 10-3. The cap wafer in the WLP has a highly resistive silicon substrate

Accelerometer Packaging (a) z

Solder bumps Cap wafer

Through-hole via RF MEMS device Cavity RF MEMS substrate

x

y

(b) Sealing

Signal Ground

x

FIGURE 10-3 Cross section of a wafer-level package.

(1000 Ω-cm) with a micromachined cavity to accommodate the MEMS device, as well as its movement. The structure is designed to package RF MEMS devices with center frequencies of 2.5 GHz at the wafer level. Copper plugs through the cap wafer and solder bumps are used as RF electrical interconnection between the device and the substrate PCB. The WLP offers mechanical protection as well as hermetic sealing for the sensitive MEMS devices. The sealing is realized by means of a metalbased seal ring that encircles the whole signal path. The size of the WLP is 3 × 3 mm, with a cap-wafer thickness of 400 μm. The size of the micromachined cavity is 800 × 800 μm, and its height is 20 μm (Fig. 10-4).

RF MEMS package Test board Port 1 CPW structure Port 2

FIGURE 10-4

Dimensional model of the package.

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Chapter Ten In order to understand and quantify the electromagnetic behavior of the WLP, a three-dimensional (3D) model of the package mounted on an organic board (FR4) has been built and solved using the highfrequency structure simulator (HFSS), which is a finite-element method (FEM) solver from Ansoft (Fig. 10-5). The main idea behind this work E, V/m

E, V/m

FIGURE 10-5 Electric filed distribution around the vias and at the dummy die surface.

Accelerometer Packaging 0.0 Dummy die

–0.2

Through-hole via interconnection

Whole package

–0.4 –0.6 –0.8 –1.0 –1.2 0

2

4 6 Frequency, GHz

8

10

FIGURE 10-6 Insertion loss in decobels for the dummy die, through-hole via interconnection, and the whole package.

is to extract the electrical characteristics of the through-hole via such that the influence of the interconnection on the whole package can be understood and quantified. In order to extract the characteristics of the through-hole via interconnection, first, the full model (test board + package + dummy die; see Fig. 10-6) has to be simulated. The dummy die chosen for this work was a simple coplanar waveguide (CPW) structure that was designed to have the characteristic impedance Zo of 50 Ω (Fig. 10-4). The test board on which the package dummy chip was mounted has been designed in a similar way, having a CPW line of 50-Ω characteristic impedance. The material of the test board is FR4 with a relative dielectric constant of 4.4 and copper metalization. The dummy chip is made of highly resistive silicon (low loss) with gold metalization. The resistivity of the silicon substrate is 1000 Ω-cm. With the material properties just specified, the simulation results showed that insertion loss better than –0.5 dB could be obtained at up to 6 GHz (see Fig. 10-6). The computed loss is a sum of the loss that occurs in the interconnection (in and out) and the loss owing to the dummy structure. Note that the loss of the test board was removed after the fullwave solution was computed through a de-embedding procedure available in HFSS. To understand how much the dummy die has contributed to overall loss, a model of the die was solved in the full-wave simulator. The simulation results showed that the die has only a –0.2-dB insertion loss at about 8 GHz. In the 100-MHz to 3-GHz bandwidth, the dominant losses are at the die level. After 3 GHz, most of the losses are due to the via through the silicon substrate (Fig. 10-7). For 4 GHz, the losses at the die level are –0.16 dB compared with the losses in the interconnection, which are at level of –0.2 dB.

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Chapter Ten Signal path

Dummy die In

FIGURE 10-7 and “out”).

Out

Overall structure (cascaded networks: “in,” “dummy die,”

10.2.3 Extraction Methodology of the Interconnection Characteristics For extracting the electrical interconnection characteristics, the structure of the package could be considered as a cascade of three two-port networks (Fig. 10-8). The first of the two-port networks is considered to start on the pads of the test board and end on the pads of the die; similarly, the third of the two-port network starts on the pads of the die and terminates on the test-board pads. For easier reference, the first network is called “in,” and the third is called “out.” The “middle” part in Pad on the dummy die Copper column (400 µm)

Solder ball (300 µm)

Pad on the test board

FIGURE 10-8 board pad.

Through-hole via interconnection: (top) die pad; (bottom)

Accelerometer Packaging between the “in” and the “out” networks defines the second two-port network, which is the passive die. The physical length of the “in” and “out” part is about 700 μm, from which 300 μm is the height of the solder ball and 400 μm is the height of copper via through the silicon cap wafer. The “middle” part of the structure is the dummy die, which has been described previously; the total length of the die is 1.9 mm. For the structure discussed above, the following equation could be written: Tall = Tin T Tadd × Tout

(10-1)

where the Ts are the transmission matrices of the “in,” “dummy die,” and “out” sections and the overall structure, respectively. The S matrices of the overall structure and the dummy die can be calculated through simulation. ⎡S11 Sall = ⎢ all ⎣S21all

S12all ⎤ S22all ⎥⎦

(10-2)

The whole structure that has been modeled is symmetric; therefore, S11 = S22, and S12 = S21. Similarly, Eq. (10-2) can be written for the dummy die, which again is a symmetric structure. The S parameter matrices can be translated easily into transmission matrices through the following relationships [Eq. (10-3)]:24 A=

(1 + S11)(1 − S22) + S12 ⋅ S21 2 ⋅ S21

B = Z0

(1 + S11)(1 − S22) + S12 ⋅ S21 2 ⋅ S21

C=

1 (1 + S11)(1 − S22) + S12 ⋅ S2 1 Z0 2 ⋅ S21

D=

(1 + S11)(1 − S22) + S12 ⋅ S21 2 ⋅ S21

(10-3)

For the overall structure the transmission matrix could be written as follows: ⎡A Tall = ⎢ all ⎣Call

Ball ⎤ Dall ⎥⎦

(10-4)

Equation 10-1 can be written then as. ⎡Aall ⎢C ⎣ all

Ball ⎤ ⎡Ain = Dall ⎥⎦ ⎢⎣Cin

Bin ⎤ ⎡Add Din ⎥⎦ ⎢⎣Cdd

Bdd ⎤ ⎡Aout Ddd ⎥⎦ ⎢⎣Cout

Bout ⎤ Dout ⎥⎦

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Chapter Ten In which Tin and Tout are the unknown. It can be noticed that due to the particularities of this structure (symmetric structure), Ain = Dout, Din = Aout, Bin = Cout and Cin = Bout, and due to the same reason only two independent equations can be written. Therefore, the system can be solved only if the following assumption is made. Ain = Din Aout = Dout Bin = Cin

(10-5)

Bout = Cout The preceding assumption is true only when the length of the structure under study is very small in comparison with the wavelength. The simulation results showed that the extraction method just described could be used successfully for frequencies up to 3 GHz. For higher frequencies, a slightly different approach has to be employed. The main error introduced by the extraction method is due to the assumption in Eq. (10-5), and to overcome this, an extra simulation model is needed. The new model, built and solved with the full-wave simulation tool, is presented in Fig. 10-9. As in the initial model, the test board is included in the simulation, but only one interconnection is used. The wave is captured with port 2, which is placed on an extension of the dummy die that can be de-embedded once the fullwave solution is obtained. The methodology presented above has been proven through a few examples. The package described in Sec. 10.2.2 has been modeled, and the frequency response of the through-hole via interconnect has been extracted and is shown in Figs. 10-10 and 10-11. To validate the

Dummy die

Test board

FIGURE 10-9

Dimensional model of the half-structure.

Accelerometer Packaging –10

–20

100

1000

dB –30

–40

–50 0

2

4

6

8

10

Frequency, GHz

FIGURE 10-10 Magnitude of S11 of the full-wave model and the recreated model.

200

Angle

100

0

–100

–200 0

2

4

6

8

10

Frequency, GHz

FIGURE 10-11

Phase of S11 of the full-wave model and the recreated model.

de-embedding procedure, the S parameters are imported in ADS in a .citi format and cascaded such that the initial structure is recreated in circuit format. The results of this simulation are compared with the full-wave simulation of the model. Good agreement has been obtained, as shown in Figs. 10-12 through 10-14. As explained in the introduction to this paper, one of the driving forces in the packaging of MEMS devices is the cost of the package. This was the reason why silicon was chosen for the cap wafer of the package. The initial simulation showed that regular silicon has low resistivity (6 Ω-cm), and the loss at RF frequencies becomes too high. The immediate alternative that has been found to work is higher-resistive silicon (100 to 1000 Ω-cm), in which the losses are acceptable, as shown in Fig. 10-15.

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Chapter Ten 0.0 –0.2 –0.4 dB –0.6 –0.8 –1.0 0

2

4

6

8

10

Frequency, GHz

FIGURE 10-12 model.

Magnitude of S12 of the full-wave model and the recreated

m1

0.0

m2 –0.2 m1 Freq. = 2.524 GHz dB (S(1, 2)) = –0.054

–0.4 –0.6

m2 Freq. = 2.524 GHz dB (via only S (1, 2)) = –0.092

–0.8 –1.0 0

2 Frequency, GHz

4

5

FIGURE 10-13 Insertion loss of the through-silicon via: (top) glass cap wafer; (bottom) highly resistive silicon.

Once the frequency characteristics of the through-silicon via interconnect had been extracted, a detailed study of the whole package (geometry and material properties) was done, which resulted in an optimized design that was to be fabricated. Through the methodology described in Sec. 10.2.3 the insertion loss of the interconnection was extracted. The insertion losses of through-silicon via interconnects of highly resistive silicon and glass have been compared. It can be seen (see Fig. 10-15.) that at the center frequency (2.5 GHz), the value of the insertion loss is better than –0.1 dB, which is acceptable for RF MEMS applications. Glass-cap wafer had better performance, but it is more difficult to have

Accelerometer Packaging S11 (magnitude)

–10

Via diameter 300 μm (400-μm spacing btw vias)

–20 Via diameter 300 μm (600-μm spacing btw vias)

dB –30

Via diameter 100 μm (600-μm spacing btw vias)

–40 –50

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Frequency, GHz –0.1 –0.2

S21 (magnitude) Via diameter 300 μm (600-μm spacing btw vias)

–0.3

Via diameter 100 μm (600-μm spacing btw vias)

dB –0.4 –0.5

Via diameter 300 μm (400-μm spacing btw vias)

–0.6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Frequency, GHz

FIGURE 10-14 Magnitude of S11 and S12 for different via diameters and different pitches.

through glass via interconnections in glass, and it is expensive to integrate as a WLP. The initial design started with a 300-μm via diameter and a pitch of 700 μm. In this configuration, the return loss was –14 dB, and the insertion loss was –0.4 dB at 3 GHz. The targeted values for this package were –20 dB reflection loss and –0.4 dB insertion loss at 3 GHz. To improve the return loss, two methods have been proposed: reducing the diameter of the via and keeping the pitch constant or keeping the diameter constant and increasing the pitch (see Fig.10-14). By doing this, the spacing between the signal and the ground vias is increased, and the impedance is increased as well, resulting in a better match between the CPW line on the board and achieving the interconnect scheme. With this approach, the return loss has been reduced to –23 dB and the return loss has been kept at –0.4 dB at 3 GHz. Another parameter that has been studied is the position of the solder seal ring for hermetic sealing purposes because its position can influence the performance of the package. The simulation showed that a minimum of 50 μm between the pads on die and the seal ring is enough for

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Chapter Ten HR silicon cap (1000 Ω-cm)

S11 (magnitude)

–10 HR silicon cap (5000 Ω-cm)

–20 –30 dB

Glass cap –40 –50 –60 0.0

0.5

1.0

1.5

2.0 2.5 3.0 Frequency, GHz

3.5

4.0

4.5

5.0

S 21 (magnitude)

0.0 –0.1

Glass cap

–0.2 dB –0.3

HR silicon cap (5000 Ω-cm)

–0.4

HR silicon cap (1000 Ω-cm)

–0.5 –0.6 0.0

0.5

1.0

1.5

2.0 2.5 3.0 Frequency, GHz

3.5

4.0

4.5

5.0

FIGURE 10-15 Magnitude of S11 and S21 for different cap-wafer materials (glass and highly resistive silicon with different resistivities).

the package to meet target specifications. Figure 10-16 shows the magnitude of S11 and S21 for different positions of the seal ring. The influence of the material properties of the cap wafer on RF performance has been studied as well. As expected, the materials with higher resistivity performed better from the insertion-loss point of view. A few types of silicon have been modeled, starting with regular silicon with a resistivity of about 6 Ω-cm up to very highly resistive silicon with a resistivity of about 10,000 Ω-cm. The performance of the silicon has been compared with that of better materials, such as ceramic and glass, but materials that are more expensive for WLPs.

10.3 Wafer-Level Packaging Process One method to lower the cost and at the same time improve reliability is to adopt a WLP method in which device packaging can be completed at the wafer level with no additional assembly steps. Since MEMS devices require a small footprint, wafer-level chip scale packages (CSP)

Accelerometer Packaging S11 (magnitude)

0

Sealing inside –10 –20

Sealing outside (50, 100, 200, 400 μm)

dB –30 –40 –50 0.0

0.5

1.0

1.5

2.0 2.5 3.0 Frequency, GHz

3.5

4.0

4.5

5.0

S12 (magnitude)

0.0 –0.5 dB –1.0

Sealing inside

–1.5

Sealing outside (50, 100, 200, 400 μm)

–2.0 0.0

0.5

1.0

1.5

2.0 2.5 3.0 Frequency, GHz

3.5

4.0

4.5

5.0

FIGURE 10-16 S11 and S21 magnitude for different positions of the seal ring.

can be used for MEMS applications. Determination of package footprint will be based on the standard assembly process so that no additional cost will be incurred for tooling. Through-wafer via interconnects are an effective option that can be used to interconnect devices vertically to form surface-mountable devices. This helps in reducing the size and improves the performance of devices used in high-frequency applications. Vertical integration can be used to connect devices with different functions so that system functions can be achieved. Vertical interconnection on silicon wafers is realized by through-hole vias filled with higher electrically conductive and lower capacitive materials. Through-wafer vias are targeted to interconnect the front side of one wafer with the backside side of another wafer. Current packaging trends show that vertical interconnects are favored because of space efficiency and design simplicity, leading to the increased popularity of WLP devices. In array-sized devices, the input/output (I/O) leads are limited when electrical connections are located at the periphery of the devices primarily owing to limited space along the edges of

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Chapter Ten such devices. This limitation necessitates the use of through-wafer interconnects for microdevices. The wafer used in the experiment was a p-type (100) 6-in silicon wafer. The through-silicon via (TSV) was made by the deep reactiveion etching (DRIE) method, and copper was filled by the electroplating/ electroless method. The thickness of the wafer used was between 400 and 450 μm, and wafer-to-wafer bonding was done using the Electronic Vision Group (EVG) wafer bonder. There are three methods to make TSV interconnects in silicon and subsequently form a threedimensional (3D) WLP. Method 1 is explained in detail, and the other methods are evolved out of the first method. Development and selection of these three methods are based on the process limitations and the advantages of one method over another.

10.3.1

Method 1: TSV with Sacrificial Wafer

Deep trenches are etched first by a Surface Technology Systems (STS) machine. A 2-μm-thick silicon oxide is deposited by thermal oxidation. Optionally, an additional layer of Ti/TiN also may be deposited over the oxide lining of the TSVs. The oxide barrier provides insulation, whereas the metal barrier provides good adhesion between the fill material in the TSVs and the oxide layer. It also prevents diffusion of the filler material into the cap material. A seed layer then is deposited on a sacrificial wafer. The seed layer can be a metal such as gold (Au) or copper (Cu) that also acts as a bonding layer for thermocompression bonding. Before he seed layer is deposited on the sacrificial wafer, a metal barrier consisting of titanium or tantalum is deposited on the sacrificial wafer to provide adhesion between the seed layer and the sacrificial wafer. It is important that both bonding surfaces have a layer of Au or Cu for a thermocompression bonding. Thermocompression bonding is done by an Electroglass bonder at a critical temperature depending on the intermediate material (Au/Cu/solder) that is used. For Au, the temperature is 365 to 375°C and for copper, it is 400 to 425°C. The bonded wafer is subjected to copper electroplating. Planarization of the top wafer and removal of the bottom wafer are done using a high-speed backgrinding machine. The detailed process is illustrated in Figs. 10-17 through 10-20. The patterned cap wafer is aligned with the MEMS wafer using an EVG aligner/bonder. The aligned wafer is brought down to the wafer-bonding stage for thermocompression bonding. A seal ring with the same under-bump metallization (UBM) as the pad is patterned outside the TSV for hermetic sealing of the package.

10.3.2

Method 2: TSV without Sacrificial Wafer

In this method, no sacrificial wafer is used for a seed layer. A seed layer is deposited directly on the backside of the cap wafer. TSVs are etched directly on the cap wafer. Subsequently, oxide and barrier

Accelerometer Packaging Barrier layer

SiO2

An

FIGURE 10-17

Through-hole via etch and oxide barrier-layer deposition.

Seed layer (Au/Cu)

Sacrificial wafer

FIGURE 10-18 Solder-layer deposition on sacrificial wafer and wafer bonding by thermocompression. Electroplated via

Cavity

UBM

FIGURE 10-19 Electroplating, wafer backgrinding, under-bump metallization (UBM) definition, and MEMS cavity etch.

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Chapter Ten

Solder

FIGURE 10-20

Solder deposition and patterning.

layers are deposited in the TSVs. Both sides of the wafer are polished for planarization, and the metallization is done for UBM and TSV wafer preparation. The process is illustrated in Figs. 10-21 through 10-23.

10.3.3

Method 3: TSV with MEMS Wafer

In this method, TSVs are formed after wafer bonding with the MEMS wafer. The cavity and pad metal are formed at the first stage and are bonded to the MEMS wafer. The advantage of this method is that the cap wafer is more robust during the bonding process than in the preceding techniques. The process is illustrated in Figs. 10-24 and 10-25.

Barrier layer

Oxide

Electroplated through-hole via

FIGURE 10-21 TSV etch, oxide/barrier-layer deposition, etch back oxide/ barrier layer, and electroplating of metal and CMP.

Accelerometer Packaging UBM

Cavity

FIGURE 10-22

UBM definition, cavity etch, solder deposition, and patterning.

UBM

Cavity

FIGURE 10-23

Cavity formation and UBM patterning on cap wafer.

MEMS device

FIGURE 10-24

Wafer-to-wafer bonding of cap and MEMS wafers.

Three different approaches have been explained for TSV interconnection. These new approaches, in which filling of the conductive material in the TSVs is accomplished using a bottom-up approach, does not require a very straight via profile. They also do not require a

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Chapter Ten Through silicon via

MEMS device

FIGURE 10-25 TSV etch on cap wafer after bonding and via fill process by electroless plating.

long plating time because they need to plate only through exposed vias, which makes the plating process more economical. Moreover, the process described in Method 1 requires only a few process steps for seed-layer deposition, TSV etching, electroplating, and UBM patterning. Another advantage relates to the combination of the process of forming solder bumps and TSVs for providing interconnects through the electroplating process by switching the electroplating solution and/or process. All three methods have their own advantages and disadvantages in realizing the TSV interconnection. However, Methods 2 and 3 are found to be more effective in terms of simplicity, reliability, and cost-effectiveness. In this section, we show the experimental results of Method 1 (TSV with sacrificial wafer) only. Work is still ongoing on the other two methods. In Method 2, no sacrificial wafer is required for the cap/ASIC wafer for TSV application. Backgrinding of the sacrificial wafer is not required in Method 2 (TSV without a sacrificial wafer) when compared with Method 1. Backgrinding is an additional process, and removing a process step can reduce the cycle time and increase process yield. In Method 3 (TSV with MEMS wafer), the cap wafer is attached directly onto the MEMS wafer. However, the TSV process and via filling are done after wafer bonding with the MEMS wafer. A TSV with smooth sidewalls can be achieved. Figure 10-26 shows a scanning electron microscope (SEM) photograph of a cross section of the trench. For TSVs on a wafer, an additional sacrificial wafer is bonded, and the vias are created. The vias are filled with copper by electroplating in Method 1, and this is shown in Fig. 10-27. Different via dimensions have been attempted, and it has been found that uniform via filling is possible even with 50-μm vias (Fig. 10-28). For MEMS

Accelerometer Packaging 321 μm 415 μm

420 μm

FIGURE 10-26

TSV etching of silicon by the DRIE method.

Cap wafer Electroplated copper

100 μm 400 μm

Au seed

Sacrificial

FIGURE 10-27

TSV filling.

applications, larger vias are sufficient, whereas for high-density 3D packaging, smaller vias are required. To make sure that the via holes are filled completely, more time is allowed, and this may produce an overplated mushroom-shaped interconnect (Fig. 10-29). This overplated interconnect can be leveled or planed by a CMP/backgrinding process. For via holes with a high aspect ratios, copper filling is more difficult, and for larger via holes, the depth will be nonuniform. With this new method, the problems of TSV filling in narrow/larger via holes have been reduced substantially. The DRIE process is used in forming TSV holes in a 6-in silicon wafer. The process starts with depositing oxide on side one of the wafer. This oxide serves as an etch-stop layer during the TSV process. A seed metal layer for electroplating is sputtered on top of the oxide and then a barrier layer of silicon nitride. A thick photoresist is deposited on side two of the wafer for good selectivity during the etch process.

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Chapter Ten

400 μm

Overplated interconnect

200 μm

FIGURE 10-28

Copper-filled 50-, 200-, and 400-μm TSVs.

Photoresist mask Seed layer

1-μm oxide

1000-Å nitride

Silicon wafer 5-kÅ etchstop oxide

FIGURE 10-29

Side 1

Side 2

TSV formation.

The photoresist is patterned using a mask aligner. The wafer is etched using the DRIE method. After etching, the photoresist is stripped and cleaned using a photoresist strip solution. The oxide on side 2 is etched away to expose the TSV. To isolate the TSV from the wafer substrate, an insulation layer and a barrier layer are deposited.

Accelerometer Packaging

Si3N4 PECVD oxide

FIGURE 10-30

Insulation- and barrier-layer formation.

The insulation layer used is a PECVD (plasma enhanced chemical vapor deposition) oxide, and the barrier layer is silicon nitride. Silicon nitride acts as a barrier layer by preventing the filler metal (copper) from diffusing into the silicon wafer, whereas silicon oxide will serve as a dielectric isolation layer, and its quality is critical for RF applications (Fig. 10-30). The uniformity of the insulation and barrier layers has been measured and found to have a conformal coating along the via. The TSV wafer is bonded to another wafer, a handler wafer, for the electroplating process (Fig. 10-31). The TSV wafer then is bonded with the handler wafer either by thermocompression bonding or resist bonding. One of the plating electrodes is connected from the edge of the wafer to the seed layer on the handler wafer. The bonded wafer is transferred to a plating bath for electroplating. The metal (Cu) is uniformly deposited in the vias until it reaches the top of the TSVs (Fig. 10-32). After electroplating the vias, the handler wafer needs to be separated so that the electroplated TSV wafer can be used for MEMS 3D

Isolation layer

Barrier layer

Handler wafer

FIGURE 10-31

Wafer bonding between TSV wafer and handler wafer.

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Chapter Ten

Cu-filled via

Handler wafer

FIGURE 10-32

Copper electroplating in the TSV wafer.

packaging. The technique chosen to remove the sacrificial wafer was the grinding plus polishing method or the grinding plus etching method. However, neither method could achieve complete removal/ separation of the sacrificial wafer. This posed a critical issue in integrating TSV wafers into MEMS wafers or 3D stacking.

10.4 Wafer Separation Process A new process to separate the TSV wafer from the handler wafer has been developed. In this process, a photoresist is used to bond the TSV wafer and the handler wafer and is shown in Fig. 10-33. Photoresist is a low-temperature bonding process that does not provide any additional thermal stress on the wafer. Since photoresist can be stripped easily by a stripping solution, separation of the wafer will be easier. However, the

Photoresist Seed metal Adhesion layer

Polymer Handler wafer

FIGURE 10-33

Handler wafer for lift-off technique.

Accelerometer Packaging

Cu via Photoresist Seed metal

Polymer

FIGURE 10-34

Handler wafer

Wafer bonding with handler wafer and electroplating.

TSVs are rooted to the seed layer on the handler wafer, and this has proven problematic in separating/delaminating the wafer. Preparation of the TSV wafer is the same as for the grinding method except that there is no metal on the backside of the wafer. The handler wafer is prepared separately in order to have a seed layer for the electroplating process, and at the same time, the seed layer should have low adhesion to the handler wafer (Fig. 10-34). A polymer that has low adhesion to metal is spin-coated on the handler wafer and hard baked for curing. A seed layer (Au, Cu, or Ni) is deposited on the polymer by sputtering or evaporation. Since adhesion of metal to polymer is low, an additional adhesion promoter layer such as titanium may be deposited on the lift-off polymer. Adhesion of the seed metal to the lift-off polymer is essential to ensure that the metal does not peel off during further lithographic processing, wafer bonding, and electroplating. A positive photoresist is spin-coated on the top of the seed metal of the handler wafer. The TSV wafer prepared after deposition of the insulating layers is bonded to the handler wafer. In this case, a waferbonding machine may not be required. A hotplate or custom-made small machine can be used for bonding the two wafers. During bonding, a small amount of pressure is applied to achieve a uniform thickness of resist between the wafers. Using an EVG proximity aligner, the photoresist is exposed in the TSV wafer. The exposed resist is developed through the vias. Before the wafer is subjected to electroplating, the whole wafer is hard baked about 130°C. The TSVs are filled by copper electroplating. After completing the plating process, the TSV wafer has to be separated from the handler wafer. Since the wafers are bonded together by photoresist, a photoresist strip solution can be used for stripping the photoresist. However, the wafers are bonded together, and thus it will be difficult for the solution to go deep into the bonding or penetrate to the center of the wafer.

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Chapter Ten

Cu via

Seed metal

Polymer Handler wafer

FIGURE 10-35

Handler wafer being separated during ultrasonic agitation.

To enhance the process, an external force such as ultrasonic vibration is used. The whole wafer is submerged in an ultrasonic bath of photoresist strip solution. When the strip solution attacks the photoresist at the edges of the wafer, the ultrasonic agitation works in such a way that the solution penetrates into the space between the wafers. The ultrasonic agitation widens the gap between the wafers and allows the solutions to move toward the center of the wafer. With the use of photoresist strip solution and ultrasonic agitation, a gap is created between the TSV wafer and the handler wafer (Fig. 10-35). However, the wafer cannot be fully separated because of the copper vias rooted to the handler wafer. Thus there should be another mechanism to delaminate the interface between the copper vias and the seed layer. However, the weakest point of the interface between the copper vias and the handler wafer is at the seed layer and polymer interface. Since the polymer is also removed by the photoresist strip solution, the adhesion of the seed layer to the polymer weakens. By means of the combined effect of ultrasonic agitation and the weak adhesion of seed layer, the vias are uprooted from the handler wafer (Fig. 10-36), and the entire wafer separates from the handler wafer.

10.4.1 Process Integration The separated TSV wafer is postprocessed with different combinations of metallization for solder bonding with the MEMS 3D stacking applications. The metallization is patterned depending on the via dimensions and the solder-ball size of the pad for attaching to the substrate (Fig. 10-37). Patterning of metallization has been done on either side of the TSV for further processes. The TSV wafer is bonded to the MEMS wafer by solder bonding. Solder balls are attached to

Accelerometer Packaging

Cu via

Seed metal

Polymer Handler wafer

FIGURE 10-36 Handler wafer separated completely by combined lift-off process and ultrasonic agitation.

Metallization

Silicon wafer

Solder

FIGURE 10-37

Metallization and solder patterning on the TSV wafer.

the metal pads on side 1 of the TSV wafer, and a surface-mountable WLP for MEMS applications has been formed (Fig. 10-38). This process can be applied to stacked wafers as well. At the through-silicon via locations, the electroplated copper is attached to the seed layer. The adhesion of the metal to the polymer is low and is the weakest point of the link. Since the polymer used also softens in the presence of the photoresist strip solution, the adhesion of the metal to the polymer is weakened further. With an additional mechanical pull by ultrasonic agitation, the metal adhered to the vias will try to separate/delaminate from the handler wafer. A combined mechanism of ultrasonic agitation and lift-off technique owing to poor adhesion allows separation of all the vias rooted to the handler wafer.

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Chapter Ten Solder ball

Silicon wafer

Solder

MEMS device

FIGURE 10-38 Wafer bonding with MEMS wafer and attachment of solder balls.

The separated wafer is cleaned to remove the remains of the seed layer on the TSV wafer. In this method, no grinding is required to remove the handler wafer. Wafer bonding is achieved using a lowtemperature polymer material, and hence thermal loading is minimal. Another major advantage is that the handler wafer can be reused for the next process, unlike in grinding removal, where a fresh handler wafer is required for each new bonding process.

10.5 Sacrificial Wafer Removal Figure 10-39 shows the via imprints on the handler wafer after the TSV wafer has been separated from the interface. The seed layer on the handler wafer is not delaminated completely. However, the seed

Via (top view)

FIGURE 10-39

TSV wafer after plating.

Silicon

Accelerometer Packaging

Silicon Via imprint

FIGURE 10-40 Via imprints on the handler wafer after the TSV wafer has been separated from the interface.

layer at the vias is not seen (Fig. 10-40). The process has been tried with vias of various dimensions, and there has been no difficulty in separating the wafer. Cross-sectional analysis was done to check the integrity of the vias. No delamination, cracks, or voids were seen in the vias (Figs. 10-41 and 10-42). A CMP is required to planarize the vias on either side of the wafer for further processing. A WLP for MEMS accelerometers and RF MEMS

318.0

271.9

Cu filled via

Silicon 309.2

FIGURE 10-41 Cross-sectional view of a Cu-filled TSV.

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464

Chapter Ten 50 μm

Silicon

340.6

Copper via

FIGURE 10-42 Top view of a TSV.

applications has been developed with this TSV format. Miniaturization, surface mountability, and high-volume manufacturing are possible with this kind of packaging format. Surface mountability is one of the concerns in WLP for MEMS devices because of the requirement for hermeticity to protect the MEMS devices from moisture and not damage or contaminate the structure. A TSV wafer can act as a cap for a MEMS structure and at the same time provide the electrical connections for signal transmission. A vertical WLP for an accelerometer is presented. Since MEMS structures have moving parts or suspended beams, air inside the package can dampen the moving structures. Another performance-related requirement involves thermal stability. Vacuum is a poor conductor of heat and is used for packages with high thermal isolation or stability. Thus vacuum in many MEMS packages is an essential requirement to improve the device performance.6–11

10.6 Wafer-Level Vacuum Sealing A surface-micromachined, laterally isolated silicon accelerometer has been used for vacuum-packaging development. A wafer-level vacuum-packaging method will be described herein.12–23 Wafer-towafer bonding has been used for WLP of an accelerometer. A 6-in accelerometer wafer was bonded with a Pyrex glass wafer using frit glass.5 Both the silicon wafer and the glass wafers were used as cap wafers. Frit glass on the glass wafer is patterned by either screen printing or lithography, and the wafer is shown in Fig. 10-43. Since the thickness of the frit glass was more than 50 μm, no additional cavity

Accelerometer Packaging

Getter

FIGURE 10-43

Getter-deposited wafer with a frit-glass seal ring.

was formed on the glass substrate. A glass wafer was selected as the cap wafer for measuring the Q-factor response of the chip by an optical method. Frit-glass paste was patterned as a seal-ring area covering all sides of the device. The getters are located in the center area surrounded by the 400-μm-wide frit-glass seal ring (Fig. 10-44). Getter paste from SAES getters was coated onto the glass wafer at a thickness of 40 μm and patterned by lithography. The getter-deposited cap wafer and the accelerometer wafer were aligned in an aligner and bonded with a wafer bonder. The wafers

Getter Accelerometer structure

Frit glass

FIGURE 10-44

WLP with getter deposition.

465

466

Chapter Ten were kept in the wafer-bonder chamber for 30 minutes for purging and to create a vacuum between the wafers. Getter is used to absorb the outgassing gases during the lifetime of the package. To absorb the gases, the getter needs to be activated, and activation is done by heating or passing a current through the getter. In this package, the getter is activated by the thermal method because the bonding temperature of the frit glass is about 430°C and well matched with the getter activation temperature of 430 to 440°C. A simultaneous bonding and getter activation process simplifies the wafer-level vacuum-sealing process. The bond pads are exposed by cutting open a portion of the top wafer. Finally, the MEMS package is singulated, and the 6 × 6 mm WLP is ready for testing. When a voltage is applied, the accelerometer structures move in plane. The movement of the structures can be accelerated by having them in vacuum. In vacuum, there is no damping and no air resistance. Performance of the accelerometer can be measured by finding the Q factor in air and in vacuum. The targeted vacuum inside the package was 1 mtorr. An outgassing study was carried out to verify the stability of the vacuum inside the sealed package. The vacuum sealed package was kept inside a chamber and baked at 200°C to reduce background signal owing to water vapor. The sample was opened by a piercing tool, and the device internal ambient was exposed to an analyzer. The outgassing study showed that devices at the center exhibit a higher percentage of outgassing (Table 10-1). This occurs because the vacuum level at the center was lower than at the edges of the wafer when the wafer bonding was performed. During wafer-to-wafer Pressure (mbar) Gas

Center

Edge

H2

0.407

0.685

He

0.020

0.013

CO

0.135

0.114

N2

9.953

5.227

CH4

1.123

1.096

H2O

1.303

0.325

C2H6

–

0.015

C3H8

0.090

0.021

Ar

0.164

0.233

CO2

0.230

0.581

Total

13.423

8.300

TABLE 10-1 Outgassing Rate from the Package with Respect to the Position on the Wafer

Accelerometer Packaging bonding, a spacer is used to provide a slight separation between the wafers to allow the air between the wafers to be pumped down. The spacer is removed when the desired vacuum is reached in the bond chamber. Since the force applied is concentrated more at the center of the wafer during bonding, the center of the wafer gets bonded first and then the edges of the wafer as the chamber pumps out the air between the wafers. This explains why the vacuum at the center is lower than at the edges of the wafer and why higher outgassing occurs at the center.

10.7 Vacuum Measurement Using a MEMS Motion Analyzer A MEMS motion analyzer (MMA) is used to determine the Q-factor response of the accelerometer in vacuum conditions (Fig. 10-45). The MMA is used for dynamic displacement measurement of MEMS devices on actuation by an electric signal. The advantages of an MMA are that mechanical frequency response can be obtained using an imaging method and dynamic in-plane measurements also can be obtained. Disadvantages include a long measurement time, limited maximum frequency, and limited precision time. Since the system is very sensitive to mechanical noise, it requires a vibration-free environment. A laser system is used to direct the laser beam onto the moving structure of the MEMS device. The MMA is used to analyze motion in the horizontal direction to the MEMS structure. The in-plane movement is measured by the MMA, and the responses of the accelerometer device in air and vacuum are shown. The package with ambient air in the device’s cavity did not exhibit a

Accelerometer

Device under test

FIGURE 10-45

MEMS motion analyzer test setup.

467

468

Chapter Ten 1.2 Series1

Displacement, μm

1

0.8

0.6

0.4

0.2

0 0

2000

4000

6000

8000

10,000

12,000

14,000

Frequency, Hz

FIGURE 10-46

Package performance without vacuum.

resonance and is dampened by air (Fig. 10-46). Tested packages with resonance showed a presence of vacuum inside the package. The Q factor is higher for the package with high vacuum and a narrow peak in the frequency function. This is shown in Fig. 10-47. 0.45 Series1 0.4 0.35

Displacement, μm

0.3 0.25 0.2 0.15 0.1 0.05 0 8400

8600

8800

9000

9200

9400

Frequency, Hz

FIGURE 10-47

Package performance in vacuum.

9600

9800

10,000 10,200

Accelerometer Packaging

10.8 Reliability Testing: Vacuum Maintenance The WLP has been subjected to different reliability conditions, such as the moisture sensitivity test (MST), the temperature-humidity test, the temperature cycle test, and high-temperature storage. The responses of the device have been monitored at different intervals of the reliability tests. No significant degradation has been observed in the Q factor of the device. As a functional response, capacitance-voltage (CV) measurements also have been done to find whether the device response has changed during the different reliability conditions, such as temperature cycle, temperature-humidity, and the like. Devices with different vacuum conditions were calibrated to identify the vacuum inside the package. The vacuum-sealed package was measured to quantify the vacuum condition inside the package. The main advantage of the MMA method was in the measurement of structures that move in plane. The WLP was subjected to 1000 hours of high-temperature storage (Fig. 10-48). Devices were been taken out of the storage chamber periodically. The frequency responses of the devices also were measured periodically. It was found that there is no change in the frequency response of the device. This proves that the vacuum inside the package had not degraded and that the device would function properly. The package was subjected to different reliability conditions to check the level of vacuum inside the package. A sample of 11 devices was used for reliability tests. The temperature-humidity test, MST 0.45 0h 0.4

250-h HTS 750-h HTS

0.35

1000 h Displacement, μm

0.3 0.25 0.2 0.15 0.1 0.05 0 8400

8600

8800

9000

9200

9400

9600

9800

10,000 10,200

–0.05 Frequency, Hz

FIGURE 10-48 Package responses after high-temperature storage (150°C for 1000 hours).

469

470

Chapter Ten level 3, and the temperature-cycle test have been carried out to see the change in Q factor (Figs. 10-49 through 10-52). The device was tested at different intervals. Most of the devices showed no substantial change in Q factor. 0.45 0h 500 h 85/85

0.4

Displacement, μm

0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 8000

8500

9000

9500

10,000

10,500

Frequency, Hz

FIGURE 10-49 Device response after the temperature-humidity test (85°C/85 percent relative humidity). 0.7 0h MST3

0.6

Displacement, μm

0.5 0.4 0.3 0.2 0.1 0 8000

8500

9000 Frequency, Hz

9500

FIGURE 10-50 Device response after the MST level 3 test (30°C/60 percent relative humidity).

10,000

Accelerometer Packaging 0.25 0h 500-TC 750-TC 1000-TC

Displacement, μm

0.2

0.15

0.1

0.05

0 8000

FIGURE 10-51

8500

9000 Frequency, Hz

9500

10,000

Device response after the temperature-cycle text (–40 to 125°C).

18.35

Capacitance, pF

18.3 0h

18.25

750 TC 18.2

1000 TC

18.15 18.1 –4

–2

0 Voltage, V

2

4

FIGURE 10-52 CV test measurement after temperature-cycle test (–40 to +125°C) on a 3D WLP for an accelerometer.

10.9 Wafer-Level 3D Package for an Accelerometer A WLP with vertical interconnects was developed for an accelerometer. TSVs filled with copper interconnects were formed on the silicon cap wafer and bonded to the accelerometer wafer.8 The TSV filled interconnects on the cap wafer were aligned with the bond pads of the

471

472

Chapter Ten

Accelerometer

Copper via 300 μm

Cap

300 μm

500 μm Solder ball

Substrate (PCB)

FIGURE 10-53

Cross section of 3D wafer-level temperature cycles.

accelerometer and bonded with AuSn solder. Hermeticity of the package was tested before and after the reliability test of the package. The reliability test used here is the thermal-cycling test, and functional testing such as CV measurement was done to verify device functionality after the thermal-cycling test. The TSV interconnects were developed with copper filling by the bottom-up approach and are shown in Fig. 10-53. CV measurements showed that there was no change in accelerometer response even after the 1000 temperature cycles on the 3D WLP. Besides the CV and hermeticity tests, shear tests also were done to evaluate the strength of the bonding between the two wafers (Table 10-2). A cross section of the 3D package showed that no

Temperature cycle

0h

250 h

Hermeticity test (atm · cc/s)

4.50 × 10

9.40 × 10

1.00 × 10

1.1 × 10–8

Shear test (kgf)

13.15

11.04

9.08

CV test on board level

0/5

15.13 0/4∗

0/4

0/4

–9

750 h –9

1000 h –8

∗One device was damaged during testing.

TABLE 10-2

Reliability Test Results on a 3D WLP for an Accelerometer

Accelerometer Packaging

Cu-TSV

MEMS

Cap wafer

Solder ball PCB-substrate

FIGURE 10-54

Cross-sectional picture the fabricated WLP.

delamination or cracks occurred on the silicon TSV interconnects. Vacuum inside the package could not be measured because of the silicon cap wafer. Difficulty in fabricating TSV interconnects on glass/ transparent substrate restricted use of the motion analyzer in measuring the vacuum. A 3D WLP with TSV interconnects in a silicon cap wafer was developed for an accelerometer and is shown in Fig. 10-54. The 3D package with through-silicon vias was subjected to temperature-cycle conditions and found to have no degradation on CV performance. Hermeticity and shear-test data also met the qualification requirements after the reliability test. A reliable 3D WLP with through-silicon vias on the cap wafer bonded to the MEMS wafer was found to be suitable for the accelerometer.

References 1. Al Sarawi, F. S., Abbott, D., and Franzon, P. D. “A review of 3D packaging technology.” IEEE Trans. Components Packag. Manufact. Technol. B 1998, 21(1):2–14. 2. Premachandran, C. S., Ranganathan, N., Chen, Y., Zhang, X., and Chong, S. C.” A novel electrically conductive wafer through hole filled vias interconnect for 3D MEMS packaging.” Presented at the 53rd Electronic Components Technology Conference, New Orleans, LA, May 27–30, 2003. 3. “A wafer-level package for microelectromechanical systems.” U.S. Patent No. 6,846,725. 4. “A method of through hole via fabrication for vertical wafer level packaging.” U.S. Patent No. 7,183,176. 5. “A method of stacking thin substrates by transfer bonding method.” U.S. Patent No. 7,326,629. 6. Li, G., and Tsang, A. A. “Low stress packaging of a micromachined accelerometer.” IEEE Trans. Electron. Packag. Manufact. 24(1):18-25, 2001. 7. Premachandran, C. S., Ranganathan, N., Raj, M., Chong, S. C., and Iyer, M. K. “A vertical wafer level packaging using through hole filled via interconnect by lift off polymer method for MEMS and 3D stacking application.” In Proceedings of the 55th Electronic Components Technology Conference, FL, pp. 1094–1098, May 2005.

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Chapter Ten 8. Premachandran, C. S., Chong, S. C., Chai, T. C., and Iyer, M. K. “Vacuum packaging development for a 128 × 128 uncooled IR bolometer device.” Electronic Components Technology Conference, Las Vegas, NV, 2004. 9. Rotaru, M. D., C. S. Premachandran, and Iyer, M. K. “Design and Electrical Characterization of a Novel Wafer Level Package for RF MEMS Applications” Electronic Components and Technology Conference, New Orleans, LA, pp. 1626–1630, May 27–30, 2003. 10. Chong, S. C., Mohanraj, S., Zhang, X., Premachandran, C. S., and Ranganathan, N. “The effect of passivation on frit glass bonding method for wafer level hermetic sealing on MEMS devices.” Electronics Packaging Technology Conference, Singapore, 10–12 December, 2003, pp 307–310. 11. Junseok, C., Giachino, J. M., and Najafi, K. “Wafer level vacuum package with vertical feed throughs.” In Proceedings of the IEEE International Conference on MEMS, Miami Beach, FL, January 30–February 3, 2005, pp. 359–362. 12. Marinis, T. F., Soucy, J. W., Lawrence, J. G., and Owens, M. M. “Wafer level vacuum packaging of MEMS sensors.” In Proceedings of the International Conference on Electronic Components and Technology, Lake Buena Vista, FL, May 31–June 3, 2005, pp. 1099–1102. 13. Mitchell, J., Lahiji, G. R., and Najafi, K. “Encapsulation of vacuum sensors in a wafer level packaging using a gold-siliconeutectic.” In Proceedings of Transducers ’05, Seoul, Korea, June 5–9, 2005, pp. 928–931. 14. Lee, B., Seok, S., and Chun, K. “A study on wafer level vacumm packaging for MEMS devices.” J. Micromech. Microeng. 12:663–669, 2003. 15. Lin, C. J., Lin, M. T., Wu, S. P., and Tseng, F. G. “High density and through wafer copper interconnections and solder bumps for MEMS wafer-level packaging.” Microsyst. Technol. 10:517–521, 2004. 16. Sparks, D. R., Massoud-Ansari, S., and Najafi, N. “Chip level vacuum packaging of micromachines using nanogetters.” IEEE Trans. Adv. Packaging 26: 277–282, 2003. 17. Sridhar, U., How, L. C., Jun, L. L., Bo, M. Y., Tan, K.-S., and Foo Pang Dow. “Trench oxide isolated single crystal silicon micromachined accelerometer.” IEDM ’98. Technical Digest 6–9:475–478, 1998. 18. Hwang, L.-T., Li, L., Drye. J., and Kuo, S.-M. “Performance evaluation of rf MEMS packages.” In Proceedings of the 52nd Electronic Components and Technology Conference, San Diego, CA, 2002, pp. 1032–1036. 19. Tilmans, H. A. C., Ziad, H., Janson, H., Di Monaco, O., et al. “Wafer-level packaged rf MEMS switches fabricated in a CMOS fab.” In Proceedings of the IEEE International Electron Device Meeting, Washington, DC, 2001, pp. 41.4.1–41.4.4. 20. Park, Y.-K., Park H.-W., Lee D.-J., Park J.-H., Song I.-S., Kim C.-W., et al., “A novel low-loss wafer-level packaging of the rf-MEMS device.” In Proceedings of the 50th IEEE Conference on MEMS, Las Vegas, NV, 2002, pp. 681–684. 21. Ok, S. J., and Baldwin, D. “High density, aspect ration through-wafer electrical interconnect vias for low cost generic modular MEMS packaging.” In Proceedings of the 8th International Symposium on Advanced Packaging Materials, Stone Mountain, UT, 2001, pp. 8–11. 22. Ok, S. J., Neysmith, J. M., and Baldwin, D. F. “Generic, Direct-chip-attach MEMS packaging design with high density and aspect ratio through-wafer electrical interconnect.” In Proceedings of the 52nd Electronic Components and Technology Conference, San Diego, CA, 2002, pp. 232–237. 23. Reichl, H., and Grosser, V., “Overview and development trends in the field of MEMS packaging.” In Proceedings of the 14th IEEE International Conference on MEMS, Interlaken, Switzerland, 2001, pp. 1–5. 24. D.M. Pozar, Microwave Engineering, 2nd ed. J Wiley & Sons, Canada, 1998.

CHAPTER

11

Radiofrequency MEMS Switches 11.1 Introduction Radiofrequency (RF) microelectromechanical systems (MEMS) switches are devices that use mechanical movement to achieve a short circuit or an open circuit in an RF transmission line. Usually, an RF MEMS switch is integrated into a planar transmission line [e.g., as a microstrip, coplanar waveguide (CPW), slotline, etc.]. The RF MEMS switch consists of, at least, a metal bridge, a transmission line, and a lower pad (this can be part of the transmission line). RF MEMS switches have been developed with various actuators, such as electrostatic, magnetostatic, piezoelectric, and thermal actuators. To date, only electrostatic-type switches have been demonstrated at 0.1 to 100 GHz with high reliability and wafer-scale manufacturing techniques. Compared with field effect transistor (FET) switches and PIN diodes, RF MEMS switches have demonstrated several advantages. Table 11-1 compares RF MEMS switches with other switches. Compared with FET switches and PIN diodes, the disadvantages of RF MEMS switches include their high driven voltage (mostly >20 V), slow switching speed (on the order of microseconds), and smaller powerhanding ability.1 RF MEMS switches can be categorized based on four characteristics: (1) RF circuit configuration, (2) mechanical structure, (3) form of contact, and (4) method of actuation. Various classifications of RF MEMS switches are shown in Table 11-2. From the contact point of view, there are two types of switches: capacitive switches and metal-contact switches. In each, there are two RF circuit configurations: series or shunt.

11.2

Design of RF MEMS Switches 11.2.1

Design of Capacitive Switches

Capacitive switches are key elements in various applications, such as tunable capacitors and tunable bandpass filters.2 For a capacitive

475

476

Chapter Eleven Parameter

RF MEMS

PIN

FET

Voltage (V)

20–80

±3–5

3–5

Current (mA)

0

3–20

0

Power consumption (mW)

0.05–0.1

5–100

0.05–0.1

Isolation (1–10 GHz)

Very high

High

Medium

Isolation (10–40 GHz)

Very high

Medium

Low

Isolation (60–100 GHz)

High

Medium

None

Loss (1–100 GHz) (dB)

0.05–0.2

0.3–1.2

0.4–2.5

TABLE 11-1 Performance Comparison of RF MEMS Switch, PIN Diodes, and FET Switches

Circuit configuration

Shunt switch Series switch

Mechanical structure

Clamp-clamp beam Cantilever beam

Contact mechanism

Metal-metal contact Capacitive switch

Actuation mechanism

Electrostatic Electromagnetic Piezoelectric Thermal

TABLE 11-2

Classification of RF MEMS Switches

switch, a thin layer of dielectric is needed above the lower directcontact pad that is used to isolate the metal bridge and the lower direct-contact pad when the metal bridge is driven down. Most capacitive switches are implemented in shunt configuration. In this construction, when the metal bridge is at the up-state position, the RF signal can go through from an input port to an output port, which is called the switch on state, as shown in Fig. 11-1b. When the metal bridge is driven down, most of the RF signal is shorted to ground, which is called the switch off state, as shown in Fig. 11-1c. The equivalent circuit of the capacitive shunt switch is shown in Fig. 11-2.1 It is modeled by two short sections of transmission line with characteristic impedance Z0 and a lumped LCR model of the bridge with the capacitance having an up-state value Cu or a downstate value Cd as shown in Fig. 11-2.

Radiofrequency MEMS Switches

Lower dc pad

Dielectric layer

Anchor

W

w

Signal line

Ground (a) Anchor

Dielectric layer

Ground Metal bridge g0

Ground Substrate

Ground

Lower dc pad

(b) Anchor

Dielectric layer

Metal bridge

Ground

Ground Lower dc pad Substrate

(c)

FIGURE 11-1

Schematic drawing of a shunt capacitive switch.

The capacitances of the up state and the down state can be calculated using the parallel-plate capacitance model as ε 0wW Cu = + Cf (11-1) g con + td/ε r

Cd =

ε 0ε r wW td

(11-2)

where Cu and Cd = the up-state and down-state capacitances, respectively Cf = the fringing field capacitance td = the thickness of the dielectric layer w = the width of the bridge

477

478

Chapter Eleven 1

2 Z0

Z0 R L C

1–

FIGURE 11-2

2–

Equivalent circuit of a shunt switch.

W = the width of the coplanar waveguide (CPW) central conductor under the metal diaphragm ε0 = the permittivity of air εr = the permittivity of the dielectric layer (7.6 for SiN) In the up state, the fringing field capacitance can be as much as 30 percent of Cu, whereas in the down state, it can be neglected. From the equivalent circuit, the shunt impedance of the switch is given by 1 Zs = R + j ω L + (11-3) jω C The relationship between the capacitances and the RF performance of the switch can be expressed as3 Z0 S11 = − (11-4) 2 Zs + Z0 S21 =

2 Zs 2Zs + Z0

(11-5)

where S11 is return loss and S21 is insertion loss for the up state or isolation for the down state. An important figure of merit for an RF MEMS capacitive switch is the ratio of down-state capacitance to up-state capacitance, that is, R = Cd/Cu, where Cd is the down-state capacitance with a typical value of several picofarads and Cu is the up-state capacitance with a typical value of tens of femtofarads. The larger the capacitance ratio, the smaller is the up-state insertion loss and the higher is the down-state isolation; therefore, a broader frequency band can be obtained. Unfortunately, because of the down-state capacitance degradation problem, which means that the actual down-state capacitance is always smaller than the designed value, it is difficult to obtain a capacitance ratio that is larger than

Radiofrequency MEMS Switches 150 for conventional capacitive switches. The down-state capacitance degradation is caused mainly by nonplanarization of the metal bridge, surface roughness of the capacitance area, and etching holes in the metal bridge.4 For a capacitive switch, it is believed that a flat metal bridge and minimal roughness of the dielectric layer are important to reduce down-state capacitance degradation. In most cases, RF capacitive switches are more suitable for highfrequency (>10 GHz) applications because of their capacitive coupling nature. Especially at W-band, only capacitive switches can be implemented because the direct-contact switches have large contact resistance, which gives rise to high loss at W-band. Therefore, to develop capacitive switches suitable for low-frequency (<10 GHz) applications, one method is to increase the capacitance ratio by using dielectric material with a high dielectric constant.5 Another method is to use an inductive tuning method.6 Besides shunt capacitive switch, series capacitive switches also are reported. In this construction, when the metal bridge is at the up-state position, the RF signal cannot pass the signal line, and this state is called the switch off state, whereas when the metal bridge is at the down-state position, the RF signal can go through the signal line, and therefore this state is called the switch on state, as shown in Fig. 11-3.

11.2.2

Design of Metal-Contact Switches

Metal-contact switches use metal-to-metal direct contact to achieve an ohmic contact between a switch membrane and its signal line. This ohmic-contact characteristic makes the device suitable for lowfrequency applications, including dc, as well as high frequencies. Also because of the ohmic contact, a separate direct-contact pad is needed to drive the switch membrane down. In contrast to capacitive switches, metal-contact switches are usually constructed in series configuration, whereas there are also some shunt types of metal-contact switches. Gold is the common contact material for metal-contact switches because of its noble nature, superior conductivity, and compatibility with monolithic microwave integrated circuits (MMICs). Other materials, such as AuNi5 and Rh, have been investigated7 as material candidates for metal-contact switches. In the selection of contact materials, a number of key parameters, including contact resistance, metal sticking behavior, lifetime, and environmental and packaging compatibility need to be considered carefully.

11.2.3 Mechanical Design of RF MEMS Switches Beside RF design, mechanical design is another important aspect of RF MEMS switches. Generally, it is critical to fabricate a flat metal bridge, as well as to control thin-film stress level in the metal bridge.8

479

480

Chapter Eleven

Ground

Dielectric layer

Lower dc pad

Anchor

Signal line Release hole in metal bridge

Metal bridge

Ground

(a) Anchor

Metal bridge

Dielectric layer

Lower dc pad

Signal line

Signal line

(b) Metal bridge

Dielectric layer

Lower dc pad

Signal line

Signal line

(c)

FIGURE 11-3

Schematic of a series capacitive switch.

Pull-down voltage has been discussed extensively and can be calculated simply as9

Vp =

8keff g 03 27 ε 0wW

(11-6)

Radiofrequency MEMS Switches where w is width of the lower driven pad, W is the width of the metal bridge (or the cantilever beam), g0 is the initial gap between the lower direct-contact pad and the metal bridge (cantilever beam), as indicated in Fig. 11-1, and keff is the effective stiffness of the metal bridge (or the cantilever beam) and can be calculated as

keff = k ′ + k ′′

(11-7)

where k′ is the stiffness that accounts for the material characteristics, such as Young’s modulus E and the moment of inertia I, and k′′ is the stiffness that due to the residual stress within the metal bridge (or the cantilever beam). Figure 11-4 shows a schematic cross section of an RF MEMS switch in clamp-clamp beam shape. The lower direct-contact pads are positioned under the two edges of the metal bridge. Supposing that ξ is the force per a unit length, then the displacement y of point P can be thought of as the total deflection caused by a number of small concentrated forces ξ · ds on a small portion of the beam, where ds is a small portion of the beam that is within distance s from the support. Because of the symmetry of the structure, it is only necessary to calculate half the force effect on the beam, and the entire deflection y is two times this effect. ⎧ d 2 y1 = M A + RA x ⎪EI 2 ⎪ dx ⎪ ⎨x = 0, y1 = 0 ⎪ dy1 ⎪ ⎪⎩x = 0, dx = 0

s

ds

ξ

x≤s

(11-8)

Metal bridge (clamp-clamp beam)

ξ

MB

MA RA

I1

d

d

I1

RB

I x y

FIGURE 11-4

Fixed-fixed beam with distributed load at the ends of the beam.

481

482

Chapter Eleven and ⎧ d 2 y2 = M A + RA x − ξ ds (x − s) ⎪EI 2 ⎪ dx ⎪ ⎨x = l, y 2 = 0 ⎪ dy 2 ⎪ ⎪⎩x = l, d x = 0

x≥a

`

(11-9)

and with the continuous condition ⎧y1 (s) = y 2 (s) ⎪ ⎨dy (s) dy (s) ⎪ 1 = 2 dx ⎩ dx

(11-10)

where l is the length of the metal bridge, MA (N-m) and RA (N) are the reaction moment and the vertical reaction at the left end, respectively. I = wt3/12 is the moment of inertia for a rectangular across section, where w and t are the width and thickness of the metal bridge, respectively. Therefore, the deflection function can be expressed as y1 =

M A x 2 RA x 3 + 2EI 6EI

y2 =

M A x 2 RA x 3 ξ ds ( x − s)3 + − 2EI 6EI 6EI

MA = − RA =

x≤s

(11-11) x≥s

ξ ds s(l − s)2 l2

ξ ds (l − s)2 (l + 2 s) l3

(11-12) (11-13) (11-14)

For deflection of the center part of the beam, the deflection of the beam at the center is used to determine the spring constant. Combining Eqs. (11-11) through (11-14), when the load is distributed across the width of the electrode shown in Fig. 11-4, the deflection at the center point of the beam (x = l/2) can be derived as

y = 2∫

l1 + d

l1

y 2 (l/2)

=

2ξ l1 + d ⎛ 4s3 − 3ls2 ⎞ ds EI ∫l1 ⎜⎝ 48 ⎟⎠

=

ξd {(2l1 + d)[(l1 + d)2 + l12 ] − l[(l1 + d)2 + l1 (l1 + d) + l12 ]} 24EI

(11-15)

Radiofrequency MEMS Switches The spring constant k′ at the center can be found to be k′ = −

2ξ d 1 = 4Ewt 3 y l[(l1 + d)2 + l1 (l1 + d) + l12 ] − (2l1 + d)[(l1 + d)2 + l12 ]

(11-16) The part of the spring constant that is due to the biaxial residual stress within the beam is derived from modeling the beam as a stretched wire. It should be noted that this model applies only for tensile stress. The force associated with biaxial residual stress σ0 can be expressed as S = σ 0 (1 − υ)tw

(11-17)

where ν is Poisson’s ratio. For the load on the beam as shown in Fig. 11-5, the deflection that results from the residual stress at x can be expressed as

y1 =

ξ ds (l − s) x x≤s Sl

y2 =

ξ ads (l − x) x ≥ s Sl

(11-18) (11-19)

Therefore, the total deflection for the distributed load caused by the residual stress at the center point of the beam can be expressed as y = 2∫

l1 + d

l1

y 2 (l/2) =

ξd (2l + d) 2S 1

(11-20)

From Eq. (11-20), the spring constant k′′ that is due to the residual stress can be expressed as k ′′ =

2ξd 4S 1 = = 4σ 0 (1 − ν)wt y 2l1 + d 2l1 + d

ds

s

ξ y1 x y

FIGURE 11-5

Deflection results from the stress on a fixed-fixed beam.

(11-21)

483

484

Chapter Eleven For the situation when l1 = 1/3l and d = 1/6l, from Eqs. (11-16) and (11-21) it can be determined that 3

⎛ t⎞ ⎛ 27 ⎞ k ′ = 32Ew ⎜ ⎟ ⎜ ⎟ ⎝ l ⎠ ⎝ 49⎠ ⎛ t ⎞ ⎛ 3⎞ k ′′ = 8σ 0 (1 − υ)w ⎜ ⎟ ⎜ ⎟ ⎝ l ⎠ ⎝ 5⎠

11.3

(11-22) (11-23)

Fabrication of RF MEMS Switches Both surface- and bulk-micromachining processes have been used to fabricate RF MEMS switches. These two processes have their respective advantages. For instance, the bulk-micromachining process is simple, where only one or two masks are needed. It allows for very precise control of device dimensions with high reliability. The surface-micromachining process, on the other hand, can deposit and pattern different metal and dielectric layers with different thicknesses and hence is more suitable for the fabrication of capacitive switches and circuits based on capacitive switches. The advantages of these two fabrication processes allow greater flexibility in developing different types of RF MEMS switches and in eventually integrating those switches into switching circuits.

11.3.1

Surface Micromachining of RF MEMS Switches

Surface micromachining is based on thin-film deposition and patterning. Almost all capacitive switches are fabricated with the surface micromachining; in addition, most metal-contact switches also are fabricated with surface micromachining. Fabrication of switches using surface micromachining normally needs five to nine masks. Critical steps include low-stress thin-film deposition for the metal bridge, surface-roughness control for the capacitance area, and fabrication of the flat metal bridge. Low-stress thin film can be achieved by optimizing thin-film deposition conditions, such as deposition gas pressure, power, and the like. The surface roughness of the capacitance area can be improved by using a refractory metal layer underneath the metal bridge.10 A flat metal bridge can be obtained by planarizing the sacrificial layer underneath the metal bridge.4 Although each process has its own specific implementations, the basic steps are the same and consist of 1. Formation of a transmission line, which is made up of a highly conductive metal layer, such as aluminum, copper, or gold. 2. Formation of a dielectric layer. This step is needed only for capacitive switches. Normally, the dielectric layer used is silicon nitride or silicon oxide, which is deposited by plasma-enhanced

Radiofrequency MEMS Switches chemical-vapor deposition (PECVD) at about 300 to 400°C. Sometimes anodized tantalum oxide or sputtered strontium titanate oxide also are used. 3. Formation of a sacrificial layer, typically consisting of photoresist or oxide that is 2 to 4 μm thick. 4. Formation of a metal bridge or cantilever beam, typically consisting of aluminum, gold, or nickel that is 0.5 to 2 μm thick. 5. Removal of the sacrificial layer and release of the metal bridge (or the cantilever beam). This is done by isotropic dry etch in an oxygen plasma if the sacrificial layer is photoresist or by wet etch in buffered oxide etchant (BOE) or HF vapor etch if the sacrificial layer is oxide. Many processes have been developed for the fabrication of capacitive switches.5,10,11 In all these processes, one of the most critical steps is to obtain a flat metal bridge in order to achieve intimate contact when the metal bridge (or the cantilever beam) is driven down. Formation of a flat metal bridge depends on two issues. The first is to control the residual stress in the metal bridge because high stress can lead to deformation of the bridge, and hence the pull-down voltage increases. The second is to planarize the sacrificial layer under the metal bridge because a nonplanar sacrificial layer results in a ragged metal bridge. One method to planarize the sacrificial layer is to fill a CPW transmission-line slot with a layer of photoresist. The method improves the isolation by 70 percent. However, two layers of photoresist are required. As a result, temperature control is critical in the process to avoid bubbles in the sacrificial photoresist.4 Another method is to use a thin (normally < 0.5 μm) lower direct-contact pad under the metal bridge.10 This thin direct-contact pad is also a part of the CPW center conductor, which results in 0.1 dB of transmission loss. Another important aspect that needs to be studied is residual stress in the metal bridge. Residual stress is “the self-equilibrium internal stresses existing in a free body of equilibrium with no externally imposed surface tractions.”12 It not only results from the metal thin-film deposition process, but it is also affected by other process steps, especially the dry releasing process. Generally, stress in thin films can be categorized into two types: thermal stress and intrinsic stress. Thermal stress results from differences in thermal expansion, whereas intrinsic stress originates from the microstructure created in the deposited film as atoms are deposited on the substrate. At substrate temperatures that are 20 percent below the melting point, intrinsic stress owing to incomplete structural ordering dominates.13 Intrinsic stress can be divided further into tensile stress and compressive stress. Tensile stress results from microvoids in the thin film,

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Chapter Eleven which lead to the attractive interaction of atoms across the voids, whereas compressive stress results when heavy ions or energetic particles strike the film during deposition. The impacts are like hitting the film with a hammer, packing the atoms more tightly.14 Although stress in the thin film can affect the mechanical properties of the thin film, the stress gradient along the depth of the thin film also will affect the mechanical properties of the thin film. The stress in a thin film deposited on a substrate can be approximated in second order by a biaxial homogeneous stress superimposed on a linear biaxial stress gradient, which varies linearly from the top surface to the bottom surface. The homogeneous stress can force the microstructures to elongate and has been evaluated by measuring buckling beams, deformed rings or diamonds, or deflecting indicator structures, whereas the stress gradient can cause changes in the shape of the structures that can influence device characteristics, stability, and performance and has been evaluated from the deflection of cantilevers or the rotation of spirals or from Raman measurements on film cross sections.15 Therefore, it is important to characterize and deduce the intrinsic stresses in released microstructures. Many methods are currently used to determine stress in the released microstructures.16 Among them, a microcantilever is one of the simplest and most frequently used test structures, and it can be used to investigate different combination of uniform mean stress and stress gradient.17 The residual stress gradient can be caused by more localized effects such as atomic peening, atomic diffusion through the film thickness, interstitial or substitutional defects, or grain-size variation through film thickness.18 The stress and stress gradient are affected not only by the thin-film deposition process but also by the process after deposition, such as the release process if oxygen plasma is used to remove the sacrificial photoresist. Figure 11-6 shows a typical capacitive shunt switch that was developed by Raytheon Systems Company.10 This switch is considered by

(a)

FIGURE 11-6

(b)

Micrograph of an RF switch at the (a) up and (b) down positions.

Radiofrequency MEMS Switches

Oxide

Dielectric

Metal posts Electrode

Substrate (a)

(b) Membrane

Spacer

(c)

(d)

(e)

FIGURE 11-7

Schematic illustration of process flow.

many to be the most mature MEMS capacitive shunt switch available to date and has been used extensively in X-band and K-band phase shifters, switched capacitor banks, and tunable filters. The Raytheon switch is fabricated on a high-resistivity silicon substrate. The main fabrication process includes the following (as shown in Fig. 11-7): 1. One micrometer of insulating thermal oxide is grown on the substrate. 2. A layer of tungsten (<0.5 μm) is sputtered and patterned to define the electrodes. 3. A thin layer (<2000 Å) of dielectric (PECVD silicon nitride) is deposited and patterned to insulate the electrodes. 4. A 4-μm-thick aluminum layer is evaporated and wet etched using a commercial aluminum etchant to define the transmission lines and the posts for the membranes. All the line widths need to be oversized by 5 μm to compensate for the decrease in line width owing to the wet etch. 5. A photoresist sacrificial spacer layer is spin-coated and patterned. 6. An aluminum alloy membrane layer is sputtered and wet-etched.

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488

Chapter Eleven 7. The spacer material is removed by oxygen plasma etch to release the membrane. There are access holes (2 × 2 μm2) on the membrane to accelerate the release rate. The total etch time is about 100 minutes.

11.3.2

Bulk Micromachining of RF MEMS Switches

The bulk micromachining process is used only to fabricate metal-contact switches with lateral metal contact. The main process steps include DRIE of Si, release of the movable part, and metal coating. Compared with surface micromachining, bulk micromachining is easier and requires fewer masks because the movable and fixed parts of the switch can be fabricated at the same time. The fabrication process for the University of California, Davis, polysilicon direct-contact switch is shown in Fig. 11-8.1,19 The process is as follows: 1. A 0.6 μm of low-pressure chemical-vapor-deposited (LPCVD) low-stress silicon nitride layer is deposited at 850°C to isolate the switch from the substrate to reduce substrate loss. 2. A 2 μm of sacrificial SiO2 layer is deposited, and anchors are patterned, followed by another 0.6 μm of LPCVD low-stress silicon nitride layer. The SiN layer is patterned to form the electrical and thermal isolation between the driven structure and the contact structure. 3. A 2 μm of in situ doped n-type polysilicon film is deposited at 680°C and patterned using 0.4 μm oxide as hard mask. SiN SiO

(a) Poly-Si

(b) Au

(c)

FIGURE 11-8 Fabrication process of the University of California, Davis, lateral direct-contact switch.

Radiofrequency MEMS Switches

Contact head

Signal line

SiN

Poly-Si

Au

FIGURE 11-9 (a) SEM image of the polysilicon-SiN-polysilicon connection. (b) The contact sidewalls and signal line coated with sputtered gold.

4. A 0.5 μm of gold layer is sputtered around the contact area and on the polysilicon transmission lines, and the switch is released using hydrofluoric (HF) acid followed by a supercritical carbon dioxide drying. Figure 11-9 shows the uniform coverage of the gold layer over the contact areas, which is due to the sputtering process used.

11.4

Characterization of RF MEMS Switches 11.4.1 RF Performance To characterize the RF performance of a switch, the main parameters include insertion loss, return loss, and isolation. Figure 11-10 shows the RF performance for the capacitive switch of Fig. 11-6. The insertion loss and return loss as a function of frequency are shown in Fig. 11-10a. The isolation and return loss of the switch in the on state (actuated) are shown in Fig. 11-10b. The switch has less than 0.5 dB of insertion loss and better than 15 dB of return loss even up to 40 GHz (unactuated state). This is due to the low off capacitance of this switch, which is on the order of 25 to 50 fF. The isolation of the switch is approximately 15 dB at 10 GHz and 35 dB at 35 GHz, which are sufficient for switching signals. Figure 11-11 shows the RF performance for the lateral metal contact series switch of Fig. 11-9. The off-state isolation is 20 dB at 12 GHz.

11.4.2 Mechanical Performance To characterize the mechanical performance of a switch, the main parameters include pull-down voltage and switch speed. As discussed earlier, pull-down voltage is determined mainly by stress in the metal bridge and mechanical stiffness of the metal bridge. The turn-on and turn-off switching waveforms for the membrane switch are shown in Fig. 11-12. The measured switching actuation

489

0

0 Insertion loss

–5

–1

–10

–1.5

–15 Return loss

–2

–20

–2.5

–25

–3

–30

–3.5

–35

–4

Return loss, dB

Insertion loss, dB

–0.5

–40 0

30 20 Frequency, GHz

10

(a)

40

50

0 Return loss

Return loss, Isolation, dB

–5 –10 –15 –20 –25 –30 –35

Insertion

–40 –45 –50 0

10

20 30 Frequency, GHz

(b)

40

50

FIGURE 11-10 (a) Switch insertion loss and return loss as a function of frequency (up position). (b) Switch isolation and return loss as a function of frequency (down position). 0

Isolation, dB

–20

–40

–60

–80 2

FIGURE 11-11

490

4

6 8 Frequency, GHz

10

Measured off-state isolation of the relay shown in Fig. 11-9.

Radiofrequency MEMS Switches

Control signal

20 V/div

+50 V

0V Detected RF signal

Time (500 μs/div)

3.5 μs

Time (10 μs/div)

FIGURE 11-12

5.3 μs

Time (10 μs/div)

Switching speed measurement results.

time is about 5.3 μs, whereas the measured switching actuation time is 3.5 μs. It should be noted that these waveforms were taken without any dielectric charging present. When actuating switches on and off, it is possible for the high electric field across the thin dielectric to cause charges to tunnel into the dielectric and become trapped. These charges screen the applied electric field, causing the switches to need higher switching voltages and to have difficulties switching using unipolar dc control voltages. Techniques to mitigate this charging are an area of ongoing research. To accurately evaluate switching speed, a nonlinear dynamic model that captures the effects of electrostatics, deformation, residual stress, inertia, damping, Van der Waals force, impact, contact, and air dynamics is essential. There is neither a closed-form solution nor a simulation tool for MEMS dynamics at present. As a first-order approximation, the switching speed of these

491

492

Chapter Eleven devices is determined by the mechanical primary natural frequency of the devices. Finite-element analyses using ABAQUS show that the primary frequencies of these devices range from 56 to 150 kHz depending on the magnitude of residual stresses. A rule of thumb for switching speed is that the switches will change state (between up and down) in one-quarter of a cycle of the primary frequency. This puts the switching speed (up or down) in the range of 1.67 to 4.5 μs (Fig. 11-12).

11.5

Reliability of RF MEMS Switches 11.5.1

Reliability of Capacitive Switches

Capacitive switches have the advantage of more flexibility in constructing tunable or reconfigurable switching circuits. The long-term reliability of capacitive switches is limited mainly by dielectric charging and can be improved by using a high-quality dielectric layer, properly designing the metal bridge, and using bipolar actuation voltage.1 Charging in the dielectric layer is the main reason for the failure of capacitive switches, which results in the stiction problem.

11.5.2

Reliability of Metal-Contact Switches

The predominant failure mechanisms of a metal-contact switch are damage, pitting, or hardening of the metal contact area. These failure mechanisms are due to impact forces between the top and bottom of the metal contacts. Other failure mechanisms include organic deposits and contamination around the contact area, but these can be mitigated by a clean packaging environment.20,21 The later direct-contact switches have advantages in high fabrication yield, low fabrication costs, and high stability and reliability. The long-term reliability can be improved by using hard contact materials, a large contact area, and hermetic packaging.20 The later directcontact switch can be implemented easily in a switching matrix.

11.6 Summary This chapter has presented design, fabrication, and characterization of RF MEMS switches. Compared with FETs and PIN diode switches, RF MEMS switches have lower insertion loss, higher isolation, negative power consumption, and higher linearity. Different kinds of RF MEMS switches have been developed and studied. Among them, capacitive shunt switches and metal-contact series switches are the two most commonly instrumented kinds of switches. Both surface micromachining and bulk micromachining have been used to fabricate RF MEMS switches. In surface micromachining,

Radiofrequency MEMS Switches one of the most critical steps is to obtain a flat metal bridge in order to achieve intimate contact when the metal bridge (or the cantilever beam) is driven down. Another important issue is to reduce residual stress in the metal membrane. Bulk micromachining is used only to fabricate metal-contact switches with lateral metal contacting. The process is simpler than the surface-micromachining process. However, it is difficult to integrate other RF circuits in the same fabrication process because normally RF circuits are fabricated with surface micromachining. The insertion loss of a MEMS switch could be lower than 0.5 dB until 40 GHz, and the isolation is higher than 15 dB at 10 GHz. The long-term reliability of capacitive switches is limited mainly by dielectric charging and can be improved by using a high-quality dielectric layer, properly designing the metal bridge, and using a bipolar actuation voltage. The predominant failure mechanisms of metal-contact switches are damage, pitting, or hardening of the metal contact area.

References 1. Rebeiz, G. M. Rf MEMS Theory, Design, and Technology. New York: WileyInterscience, 2003. 2. Zavracky, P. M., McGruer, N. E., Morrison, R. H., and Potter, D. “Microswitches and microrelay with a view toward microwave applications.” Int. J. RF Microwave CAE 9:338–347, 1999. 3. Pozar, D. M. Microwave Engineering. New York: Wiley, 1998. 4. Yu, A. B., Liu, A. Q., Zhang, Q. X., Alphones, A., Zhu, L., and Peter, S. A. “Improvement of isolation MEMS capacitive switch via membrane planarization.” Sensors & Actuators A 119:206–213, 2005. 5. Park, J. Y., Kim, G. H., Chung. K. W., and Bu, J. U. “Monolithically integrated micromachined rf MEMS capacitive switches.” Sensors & Actuators A 89:88–94, 2001. 6. Muldavin, J. B., and Rebeiz, G. M. “High-isolation inductively-tuned X-band MEMS shunt switches.” IEEE MTT-S Int. Microwave Symp. Digest 1:169–172, 2000. 7. Schimkal, J. “Contact measurements providing basic design data for microrelay actuators.” Sensors & Actuators A 73:138–143, 1999. 8. Yu, A. B., Liu, A. Q., Zhang, Q. X., and Hosseini, H. M. “Characterization and optimization of dry releasing for the fabrication of capacitive switches.” J. Micromech. Microeng. 17:2024–2030, 2007. 9. Roark, R. J., and Yooung, W. C. Formulas for Stress and Strain, 6th ed. New York: McGraw-Hill, 1989. 10. Yao, Z. J., Chen, S., Eshelman, S., Denniston, D., and Goldsmith, C. “Micromachined low-loss microwave switches.” J. MEMS 8:129–134, 1999. 11. Firebaugh, S. L., Charles, H. K., Edwards, R. L., Keeney, A. C., and Wilderson, S. F. “Fabrication and characterization of a capacitive micromachined shunt switch.” J. Vac. Sci. Technol. A 22:1383–1387, 2004. 12. Mura, T. Micromechanics of Defects in Solid. The Hague, Netherlands: Martinus Nijhoff, 1982. 13. Saif, M. T. A., and MacDonald, N. C. “Planarity of large MEMS.” J. MEMS 2: 79–97, 1996. 14. d’Heurle, F. M., and Harper, J. M. E. “Note on the origin of intrinsic stresses in films deposited via evaporation and sputtering.” Thin Solid Films 171:81–92, 1989.

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Chapter Eleven 15. Greek, S., and Chitica, N. “Deflection of surface micromachined devices due to internal, homogeneous or gradient stresses.” Sensors & Actuators A 78:1–7, 1999. 16. van Drieenhuizen, B. P., Goosen, J. F. L., French, P. J., and Wolffenbuttel, R. F. “Comparison of techniques for measuring both compressive and tensile in thin films.” Sensors & Actuators A 37–38:756–765, 1993. 17. Fang, W., and Wickert, J. A. “Determining mean and gradient residual stresses in thin films using micromachined cantilevers.” J. Micromech. Microeng. 6:301–309, 1996. 18. Huang, S., and Zhang, X. “Gradient residual stress induced elastic deformation of multilayer MEMS structures.” Sensors & Actuators A 134:177–185, 2007. 19. Wang, Y., Li, Z. H., McCormick, D. T., and Tien, N. C. “Low-voltage lateralcontact microrelays for rf applications.” In Proceedings of the 15th IEEE International Conference on Microelectromechanical Systems, Las Vegas, NV, January 2002, pp. 645–648. 20. Hyman, D., and Mehregany, M. “Contact physics of gold microcontacts for MEMS switches.” IEEE Trans. Comp. Packag. Technol. 22:357–364, 1999. 21. Hyman, D. “Physics of microcontacts for MEMS relays,” Ph.D. thesis, Case Western Reserve University, May 2000.

CHAPTER

12

RF MEMS Tunable Capacitors and Tunable Band-Pass Filters 12.1 Introduction As mentioned in Chapter 11, microelectromechanical systems (MEMS) switches can be used to construct tunable switching circuits, such as tunable capacitors, tunable filters, phase shifters, and matching networks. This chapter discusses tunable capacitors and tunable filters in detail.

12.2

RF MEMS Tunable Capacitors High-quality, stable, low-phase-noise voltage-controlled oscillators (VCOs) with a wide tuning range are essential elements in many modern wireless systems, such as low-noise amplifiers, harmonic frequency generators, and frequency controllers. The tuning range of these VCOs must be large enough to cover the entire frequency band of interest. Tunable capacitors are the key elements in such VCOs. A tunable capacitor is one whose capacitance can be tuned or varied via electrical means, for example, by applying a tuning voltage, which makes the capacitance voltage-dependent, that is, C = C(V ). Compared with semiconductor on-chip varactors, MEMS tunable capacitors have lower losses because of highly conductive thick metal layers used as structural material and air as a dielectric. Further, since a MEMS tunable capacitor acts as a low-pass filter, any radio frequency (RF) excitation will be filtered, and the interference between

495

496

Chapter Twelve the capacitance variations and the applied RF signal will be small, thus offering excellent linearity. In addition, MEMS tunable capacitors promise a wide tuning range, low noise, and the ability to keep the signal circuit separate from the control circuit, which greatly simplifies the bias circuitry. For a MEMS tunable capacitor, its quality factor (Q factor) can be defined as1 Q=

XC − X L ESR

(12-1)

where |XC − XL| is the net reactance, ESR is the equivalent series resistance and it should be taken into account over the entire frequency band of interest. It can be seen from Eq. (12-1) that the larger the resistance, the smaller is the Q and the greater is the resistive loss for the device. Also, the inductance associated with the tunable capacitor will resonate at a frequency known as the electrical selfresonance for the capacitor. The capacitor becomes unusable beyond the self-resonance frequency because the inductance dominates the total device impedance. Therefore, the inductance associated with a capacitor needs to be kept as low as possible, so the self-resonance should be much higher than the signal frequencies for which the tunable capacitor is designed. MEMS capacitors tune their capacitance by adjusting the device’s physical parameters and dimensions via electromechanical means— electrostatic or thermal. After neglecting the fringing fields, the capacitance of the capacitor with two electrodes of area A separated by a gap d can be written as

C=

ε 0ε r A d

(12-2)

where A = denotes the electrode area d = the spacing between the plates ε0 = the permittivity of free space εr = the dielectric constant of the medium in between the two plates1

12.2.1 Analog Tuning of RF MEMS Capacitors Based on Eq. (12-2), a capacitor can be tuned in three ways: 1. By tuning the dielectric constant εr 2. By tuning the spacing d, called gap tuning 3. By tuning the area A, called area tuning Among these three methods, the first one employs ferroelectric thin films such as barium strontium titanate (BaSrTiO3 or BST) or

R F M E M S Tu n a b l e C a p a c i t o r s a n d Tu n a b l e B a n d - P a s s F i l t e r s strontium titanate (SrTiO3 or STO), which have an electric field– tunable dielectric constant. However, they are not truly considered to be MEMS tunable capacitors because there is no movable structure in them. Therefore, they are not discussed here.

Gap-Tuning MEMS Capacitor Normally, a gap-tuning MEMS capacitor is made up of two parallel plates. Figure 12-1 shows a functional model.2 The top plate of the capacitor is suspended by a spring with spring constant k, whereas the bottom plate is fixed mechanically. When a bias voltage V1(t) = V1 is applied across the two plates, the suspended plate is attracted to the bottom plate owing to the resulting electrostatic force. The suspended plate moves toward the fixed plate until an equilibrium between the electrostatic and spring forces is reached. This can be written as follows: kx =

1 dCD 2 1 ε d AV12 V =− 2 dx 1 2 (d1 + x)2

(12-3)

where εd = the dielectric constant of air A = the area of the capacitor plates d1 = the separation of the capacitor plates when the spring is in its relaxed state The capacitance tuning range of a gap-tuning capacitor is limited by pull-in instability, which for a simple spring-mass system occurs at d1/3. Therefore, theoretically, the maximum tuning range of a gaptuning capacitor is 50 percent. However, because of the proximity capacitance effect, in reality, the measured maximum tuning range is far less. In 1996, Young and Boser3 developed the tunable capacitor shown in Fig. 12-2. The entire structure is made on top of a silicon wafer with

Suspended plate

d1 + x(t)

k

CD

V1(t)

Fixed plate

FIGURE 12-1 Functional model of an electromechanically tunable plate capacitor with two parallel plates.

497

498

Chapter Twelve

200 μm

FIGURE 12-2 Top view of a micromachined variable capacitor.

an aluminum ground plane shielding the parasitic layer from the lossy silicon substrate to ensure a high Q. In order to maintain the parasitic capacitance below 220 fF, a 4-μm-thick oxide layer was deposited on top of the aluminum ground plane before the tunable capacitor was fabricated. In the structure, a 1-µm-thick aluminum plate was suspended in air with four mechanical folded-beam suspensions acting as springs. The electrodes are 200 × 200 µm with 2 × 2 µm holes spaced 10 µm apart to ensure complete removal of the sacrificial material. The initial gap was 1.5 µm. The capacitance varied from 2.11 pF without voltage applied to 2.46 pF with a 5.5 V tuning voltage, which corresponds to a tuning range of 16 percent. The equivalent series resistance is 1.2 Ω at 1 GHz, corresponding to a Q of 62, which is competitive with discrete silicon and GaAs diodes. In order to increase the tuning range, Dec and Suyama2 used polysilicon for the bottom plate and polysilicon/gold for the suspension and movable plate, as shown in Fig. 12-3. This capacitor consists of two parallel plates (a 210 × 230 μm capacitor). The capacitor has a Q factor of 20 at 1 GHz and a Q factor of 11.6 at 2 GHz. The selfresonant frequency is beyond 6 GHz. The tuning characteristics of the tunable capacitor are shown in Fig. 12-4. When a zero bias voltage (V1 = 0 V) is applied, the measured capacitance is 2.05 pF. The measured capacitance is 3.1 pF when V1 = 4 V is applied. The tuning range of the micromachined tunable capacitor is 1.5:1. To further increase the maximum tuning range, Dec and Suyama3 proposed a three-plate capacitor in which the theoretical limit for the running ratio would be increased from 50 to 100 percent.

R F M E M S Tu n a b l e C a p a c i t o r s a n d Tu n a b l e B a n d - P a s s F i l t e r s

FIGURE 12-3 Microphotograph of a two-plate tunable capacitor (0.6-pF design value).

3.2 3.0

CD, pF

2.8 2.6 2.4 2.2 2.0 0.0

0.5

1.0

1.5

2.0 V1, V

2.5

3.0

3.5

4.0

FIGURE 12-4 Measured tuning characteristics of the two-plate tunable capacitor (0.6-pF design value).

Figure 12-5 shows a conceptual model of a three-plate electromechanically tunable capacitor where, under zero-bias conditions, the distances between parallel plates are d1 and d2, respectively.2 The top and bottom plates of the capacitor are fixed mechanically, whereas the middle plate is suspended by two springs with a spring constant of k/2 each. If a bias voltage V1(t) = V1 is applied and V2(t) = 0 V, the electrostatic force causes the suspended plate to move toward the top

499

500

Chapter Twelve

Fixed plate k/2

k/2 d1 + x (t)

CD

d 2 – x(t)

CP

Suspended plate

Fixed plate

FIGURE 12-5 Conceptual model of an electromechanically tunable parallelplate capacitor with three parallel plates.

plate. Similarly, if a bias voltage V2(t) = V2 is applied and V1(t) = 0 V, the suspended plate moves toward the bottom plate. Under direct-contact conditions, x(t) = x, V1(t) = V1, V2(t) = V2, and the equilibrium between the electrostatic and spring forces can be expressed as kx =

1 dCD 2 1 dCp 2 1 ε d AV12 1 ε d AV22 V1 + V2 = − + 2 2 (d2 − x)2 2 dx 2 dx 2 (d1 + x)

(12-4)

The maximum capacitance that this capacitor can be tuned to is still 3CD/2. However, the minimum capacitance that this capacitor can be tuned to is 3CD/4 (which means the capacitance can be tuned smaller than the original value) if distances d1 and d2 are equal. Hence the maximum theoretical tuning range is 2:1. For this design, the middle plate of the tunable capacitor must be connected to a small-signal ground in a practical circuit application so that only the desired capacitance CD plays a role in the actual circuit. Figure 12-6 shows a fabricated three-plate tunable capacitor (400 × 400 μm capacitor).2 The tunable capacitor has a measured Q factor of 15.4 at 1 GHz and 7.1 at 2 GHz. The self-resonant frequency is approximately 6 GHz. Figure 12-7 shows the tuning characteristics of this tunable capacitor. Under zero-bias conditions (i.e., V1 = 0 V and V2 = 0 V), the measured capacitance (i.e., the desired capacitance CD) is 4.0 pF. The measured capacitance is approximately 6.4 pF when V1 = 1.8 V and V2 = 0 V are applied. When V1 = 0 V and V2 = 4.4 V are set, the measured capacitance is 3.4 pF. The tunable capacitor thus has a tuning range of 1.87:1. If V2 is more than 4.4 V while V1 = 0 V, bistability and discontinuity in tuning are observed. The capacitance suddenly drops to approximately 2.2 pF and returns to 2.3 pF when the bias voltages are set back to 0 V. The capacitor is still tunable, but the tuning range in this mode is only 1.12:1. The device returns to the previous

R F M E M S Tu n a b l e C a p a c i t o r s a n d Tu n a b l e B a n d - P a s s F i l t e r s

FIGURE 12-6 Microphotograph of a three-plate tunable capacitor (1.9-pF design value).

4.1 4.0

6.0

V1 = 0 V V2 = VB

5.5 5.0

3.9 3.8

V1 = VB V2 = 0 V

4.5

3.7 3.6 3.5

4.0 3.5

CD (pF) V1 = 0 V V2 = VB

CD (pF) V1 = VB V2 = 0 V

6.5

3.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 VB, V

3.3

FIGURE 12-7 Measured tuning characteristics of the three-plate tunable capacitor (1.9-pF design value).

mode (i.e., 4.0 pF of nominal capacitance) provided that V1 = 5.0 V and V2 = 0 V are applied before the bias voltages are reset to 0 V. Another approach to increase the tuning range involves using separate signal and control electrodes.4,5 This allows making the actuator gap different from the actual capacitor gap. If the actuator gap is at least three times the capacitor gap, an infinite tuning ratio theoretically can be obtained.

501

502

Chapter Twelve

Area-Tuning MEMS Capacitor A larger tuning ratio can be achieved easily by the area-tuning method. A typical implementation of an area-tuning MEMS capacitor as developed by Yao and colleagues6 in 1998 is shown in Fig. 12-8. This design is actually based on the concept of a comb-drive actuator. The device actually consists of two mechanically joined capacitors with the center-suspended attachment grounded electrically. One movable capacitor is for electrostatic actuation, and the other is for the RF signals. The RF capacitance can be designed to increase or decrease with the applied control voltage depending on the orientation of the interdigital fingers in the RF and drive capacitors. Unlike the gap-tuning parallel plate system, there is no theoretical tuning limit for an area-tuning interdigitated comb structure. The only practical limits for tuning range are within the supporting spring design and length of the comb fingers. The device is fabricated using a deep reactive-ion etch (DRIE) of single-crystal silicon or silicon-on-insulator (SOI) wafer. After releasing the structure, the device is coated with metal (Al) thin film to improve the quality factor of the tunable capacitor (like the fabrication process of a contact switch). Based on this process, several designs have been fabricated and tested at 0.1 to 6 GHz. A tuning ratio of 100 percent at 5 V has been measured by Yao and colleagues.6 Tuning ratios in excess of 300 percent have been demonstrated at higher voltages, along with Q factors close to 100 (at 400 MHz) and an SRF as high as 5 GHz for a device with a base capacitance of around 3.3 pF.6 In the design, if a low-resistivity (e.g., 10 to 20 Ω-cm) silicon substrate was used, it would be quite lossy and contribute significantly to the total parasitic capacitance in the bond-pad areas. Parasitic capacitance as high as 2 pF for such a silicon substrate has been observed in a tunable capacitor with a nominal capacitance of 3 pF. For the same device, the 2-pF parasitic capacitance is reduced to 0.2 pF

500 μm

80 μm

FIGURE 12-8 Scanning electron microscope (SEM) images of tunable capacitors with area tuning.

R F M E M S Tu n a b l e C a p a c i t o r s a n d Tu n a b l e B a n d - P a s s F i l t e r s

30 MHz

30 MHz

30 MHz

3 GHz

3 GHz 3 GHz 6 GHz

6 GHz

6 GHz

(a)

(b)

(c)

FIGURE 12-9 S11 plots in Smith charts of parasitic capacitance when the tunable capacitor is made on (a) low-resistivity silicon substrates, 2.05 pF; (b) high-resistivity silicon substrates, 0.212 pF.

when a high-resistivity (e.g., >4000 Ω-cm) silicon substrate is used. The parasitic capacitance can be reduced further to 0.0825 pF if a glass substrate is used. Figure 12-9 shows the RF characterizations of these parasitic effects in the form of S11 parameters. The disadvantages of the area-tuning tunable capacitor include large size and process integration problems with other devices.

12.2.2

Digital Tuning of RF MEMS Capacitors

Digital-type tunable capacitors are constructed with MEMS switches (capacitive or metal-contact) and metal-insulator-metal (MIM) capacitors. Their capacitances are tuned digitally. Theoretically, their tuning range can be unlimited. However, owing to the metal-insulator-metal capacitors used, normally, the Q factors of these tunable capacitors are in the range of 40 to 80. Also, they suffer from a parasitic series inductance owing to their relative large size, and this limits their operation to 1 to 10 GHz.1 Goldsmith and colleagues developed a digital-type tunable capacitor bank suitable for 0.1- to 6-GHz applications.7,8 Figure 12-10

C4 Control lines

FIGURE 12-10 Schematic of a tunable capacitor using numerous shunt MEMS capacitor elements.

C3 C2

C1 C0

503

504

Chapter Twelve

Switch capacitor

MIM capacitor

FIGURE 12-11

Micrograph of a tunable RF MEMS capacitor.

shows an ideal 4-bit switched capacitor in a shunt and series implementation, and Fig. 12-11 presents an SEM picture of the fabricated tunable capacitor. This design results in a capacitance change from C0 + 4Cu to C0 + 15Cu. The series switches used in this design are capacitive switches. (Cu = 30 fF, Cd = 3 pF) and are placed in series with MIM capacitors of values 0.23, 0.5, 1.18, and 3.88 pF. There is also a fixed 3.08-pF MIM capacitor between the input and output ports. The larger capacitors are placed closer to the RF lines in order to minimize the inductance and to improve the self-resonant frequency. The fixed MIM capacitors are not geometrically progressive owing to the different series inductance in the input/output paths for each capacitance state. The total capacitance varied from 3.1 to 6.5 pF (0.25-pF steps), with a Q above 100 at 50 to 400 MHz and a self-resonant frequency above 1200 MHz for all capacitance stats.

12.3

RF MEMS Tunable Band-Pass Filters Tunable band-pass filters are often used as tracking blocks for multiband telecommunication systems, radiometers, and wide-band radar systems. This can greatly simplify the complexity of these systems and reduce the loss. For those applications, tunable band-pass filters have to be as flexible as possible in terms of center frequencies and bandwidth. In addition, the tunable band-pass filter must be tunable over a wide frequency range with high-performance characteristics such as high rejection, ease of integration, and the like.9,10 Generally, the tunable band-pass filters described in literature can be classified into three basic categories: mechanically tunable filters, magnetically tunable filters, and electronically tunable filters.11–25 However, none of these satisfies the requirements of miniaturization and mass production.

R F M E M S Tu n a b l e C a p a c i t o r s a n d Tu n a b l e B a n d - P a s s F i l t e r s In recent years, tunable band-pass filters based on MEMS technology have been widely studied. It is expected that MEMS technology can bring much improvement to the tradeoffs between tuning range and losses in filter designs. Both the capacitive switch and the metal-contact switch can be used to construct MEMS tunable band-pass filters. The tunable capacitor discussed in the preceding section can be used to construct a tunable band-pass filter. Since there are two types of tunable capacitors, the band-pass filter also can be tuned either analogically or digitally.

12.3.1 Analog Tuning of a MEMS Band-Pass Filter When a band-pass filter is tuned analogically, the metal bridges can be implemented in the structure of the distributed-type band-pass filter. By lowering the metal bridge without provoking pull-down, the capacitance and thus the electric length of the distribution section are changed. As a result, the center frequency of the band-pass filter can be tuned accordingly. A 20-GHz three-pole tunable filter based on the distributedtransmission-line approach was developed,26 as shown in Fig. 12-12. The filter demonstrates an insertion loss of 4 to 5 dB and a 3.8-percent tuning range, which is comparably small, as shown in Fig. 12-13.

Loaded line resonator

CPW

RF IN

RF OUT

CPW Bias pad

MEMS capacitor

0

10

–10

0

–20

–10

–30 –40 –50 10

FIGURE 12-13

S11, dB

S21, dB

FIGURE 12-12 Photograph of fabricated three-pole MEMS tunable band-pass filter with distributed MEMS transmission line (DMTL) resonators.

S21@ V = 0 V S21@ V = 50 V S21@ V = 60 V

15 20 25 Frequency, GHz

–20 –30

30

–40 10

S11@@ V = 0 V S11@ V = 50 V S11@ V = 60 V

15 20 25 Frequency, GHz

30

Measured S parameter of capacitively coupled MEMS tunable filter.

505

506

Chapter Twelve

3622 μm

Air bridges

Shunt inductive inverters

FIGURE 12-14

Micrograph of the fabricated MEMS miniature filter.

0 Vb = 80 V

–20 –30

Vb = 80 V

Vb = 0 V

–10

–20

–40 –50 12

Measured Simulated

0 S11, dB

S21, dB

–10

10

Measured Simulated Vb = 0 V

14

16

18

20

22

Frequency, GHz

24

26

28

–30 12

14

16

18

20

22

24

26

28

Frequency, GHz

FIGURE 12-15 Measured and simulated S parameters of the miniature tunable filter for V = 0 and 80 V.

In order to increase the tuning range and reduce size, another miniature three-pole tunable band-pass filter with 8.6 percent bandwidth based on high-Q MEMS bridge capacitors was reported.27 The tuning range is 14 percent from 18.6 to 21.4 GHz, with midband insertion loss of 2.5 dB at 21.1 GHz. Figure 12-14 is an SEM photograph of the tunable filter, and Fig. 12-15 gives the measurement results.

12.3.2

Digital Tuning of an RF MEMS Filter

When the band-pass filter is tuned digitally, the capacitive switches are used to form the tunable capacitor and therefore change the capacitance values of the structure. For example, a large set of tunable band-pass filters has been developed based on lumped elements and MEMS switched capacitors.8 In these designs, series resonators are converted to shunt parallel resonators using impedance inverters first, and then both the series and shunt capacitors are tuned by the capacitive switches, as shown in Fig. 12-16. In this design, the key is the wide selection of capacitance values and capacitance steps that can be achieved with a 4-bit MEMS switched capacitor. Figure 12-17 is a picture of the fabricated tunable filter. The measurement results are given in Fig. 12-18, which shows an insertion loss of between –6.6 and –7.3 dB along with a reflection coefficient that is better than –10 dB for all 16 tuning steps.

R F M E M S Tu n a b l e C a p a c i t o r s a n d Tu n a b l e B a n d - P a s s F i l t e r s l = 2057 μm w = 125 μm 0.29 pF 0.65 pF 1.62 pF 8.55 pF

FIGURE 12-17

Layout of the UHF five-pole filter.

0

10

–5

5

–10

0

–15

–5

–20

–10

–25

–15

–30

–20

–35

–25

–40 0.6

FIGURE 12-18

0.7

0.8

0.9 1 1.1 Frequency, GHz

1.2

1.3

Return loss, dB

Schematic of a capacitively coupled five-pole band-pass filter.

Insertion loss, dB

FIGURE 12-16

0.22 pF

3.43 pF

7.21 pF

5.32 pF 1.22 pF

0.17 pF

1.87 pF

6.96 pF

0.39 pF

2.13 pF 0.80 pF

0.42 pF

0.89 pF

7.69 pF

1.62 pF 2.16 pF

0.17 pF

1.87 pF

6.96 pF

0.39 pF

l = 2057 μm w = 125 μm 0.075 pF 0.15 pF 0.32 pF 0.71 pF

0.54 pF

l = 2057 μm w = 125 μm 0.06 pF 0.12 pF 0.24 pF 0.52 pF

1.62 pF 0.80 pF

0.22 pF

3.43 pF

2.13 pF 0.54 pF 1.22 pF 7.21 pF

5.32 pF

l = 2057s w = 125 μm 0.06 pF 0.12 pF 0.24 pF 0.52 pF

0.17 pF

l = 2057 μm w = 125 μm 0.075 pF 0.15 pF 0.32 pF 0.71 pF

0.29 pF 0.65 pF 1.62 pF 8.55 pF

–30 1.4

UHF responses.

The center frequency of the tunable band-pass filter also can be tuned by the direct-contact switches. Normally, the filter is tuned digitally. The direct-contact switch can be used to change the inductance of the filter, which is presented in ref. 28 and shown in Fig. 12-19. The filter has a precise and stable frequency tuning ratio because the center frequency is changed by total inductance change owing to

507

508

Chapter Twelve LC resonators

Spiral inductor

Direct-contact MEMS switch

MIM capacitors (a) LC resonators L1

L1

Input

Output

C2 R

R

C1 L2 C3

MEMS switch location

L2

C3

L2

C1 L2

C3

C3

Switch inductor

(b)

FIGURE 12-19

Schematics of the contact-type tunable filter.

on/off actuation of the direct-contact switch. The filter has two states with center frequencies of 2.5 and 5.2 GHz, respectively. The insertion loss is 4.7 dB at 2.5 GHz and 5.2 dB at 5.1 GHz, as shown in Fig. 12-20. The other research work uses a single-pole, multithrough (SPMT) direct-contact switch to contact different filter tanks with different center frequencies so that the center frequency of the whole circuit can be shifted at the different center frequencies of the filter tanks.29 Figures 12-21 through 12-23 present the schematic, fabricated device, and measurement results, respectively. The Ku-band tunable filter consists of two single-pole, triple-throw (SP3T) direct-contact switches and three fixed three-pole, end-coupled band-pass filters. A tuning range of 17.7 percent from 14.9 to 17.8 GHz is achieved with a fractional bandwidth of 7.7 percent and a midband insertion loss ranging from 1.7 to 2.0 dB. The design gives flexibility in the selection of filter

R F M E M S Tu n a b l e C a p a c i t o r s a n d Tu n a b l e B a n d - P a s s F i l t e r s 0 Simulation Measurement

Su

–10

S Parameters, dB

S Parameters, dB

0

S21 –20 –30

Center frequency : 2.5 GHz

Su Simulation Measurement

–10 –20

S21 –30 Center frequency : 5.4 GHz

Insertion loss 4.7 dB

–40

Insertion loss 5.2 dB

–40 0

(a)

FIGURE 12-20

2

4 6 Frequency, GHz

8

0

2

(b)

4 6 Frequency, GHz

Measured RF responses of the contact-type tunable filter.

End-coupled fixed filters

FIGURE 12-21 Switched filter bank based on MEMS SP3T switches.

14.9 GHz

17.8 GHz

16.2 GHz SP3T MEMS switch

14.9-GHz filter

17.8-GHz filter

SP3T switches Indium sheet Wire bond

FIGURE 12-22

16.2-GHz filter

Layout of the switched filter bank.

8

509

Chapter Twelve 0 Measured Simulated

–10

S21, dB

–20 –30 –40 –50 –60 –70 8

10

12

14 16 Frequency, GHz

18

20

21

0 Measured Simulated –10 S11, dB

510

–20

–30

–40 8

10

12

14

16

18

20

21

Frequency, GHz

FIGURE 12-23

Insertion loss and return loss for the switched filter bank.

tanks with different center frequencies. Therefore, the filter can be easily tuned. However, the size of the whole circuit is large compared with other MEMS tunable band-pass filters. The digital MEMS tunable band-pass filters mentioned earlier have wide tuning ranges. However, they do not have enough resolution to obtain near continuous coverage at microwave frequency band or they have large size. To overcome those shortcomings, a 4-bit digital differential tunable filter was developed.30 Figure 12-24 presents a two-pole filter which is suitable for a differential implementation. The response of the differential filter can be tuned over a wide frequency range by varying CR. The shape and relative bandwidth of the filter is approximately fixed due to the filter topology, i.e., capacitive tuning with an inductive inverter. The input/output matching is

R F M E M S Tu n a b l e C a p a c i t o r s a n d Tu n a b l e B a n d - P a s s F i l t e r s CM

CM

k

+

+ CR

CR –

– LR

LR

CM

FIGURE 12-24

CM

Lumped model for a two-pole differential tunable filter.

maintained better than 16 dB over the tuning range by varying CM. The resonant capacitor is substituted by a capacitor bank with four unit cells. This results in 16 different filter responses using 16 different combinations of switches in the up- and down-state positions. Each matching capacitor is composed of three unit cells, and provides enough capacitive variation to result in a well-matched circuit over the whole tuning range. The photograph of the complete 6.5–10-GHz filter is shown in Fig. 12-25. The measurement results are shown in Fig. 12-26 for 16 different states. The insertion loss is 4.1 and 5.6 dB at 9.8 and 6.5 GHz respectively, and the relative bandwidth is approximately fixed for the whole tuning range. The return loss is always better than 16 dB for the whole tuning range.

4 mm

5 mm

Bias lines

FIGURE 12-25

Bias pad

CR

Transformer

CM

Photograph of the complete 6.5- to 10-GHz filter.

511

512

Chapter Twelve 0 (0000)

(1111)

S21, dB

–10

–20

–30

–40

–50

6

8 Frequency, GHz

10

12

0

S11, dB

–10

(0000) –20 (1111)

–30

6

8 Frequency, GHz

10

12

FIGURE 12-26 Measured (a) insertion loss and (b) return loss of the tunable two-pole 6.5- to 10-GHz filter.

12.4 Summary This chapter discussed MEMS varactors and tunable band-pass filters. MEMS varactors can be tuned analogically or digitally. The analog parallel-plate designs result in very high-Q operation at millimeterwave frequencies, but with a limited capacitance ratio of 1.3 to 1.9:1. The digital capacitors have shown impressive performance

R F M E M S Tu n a b l e C a p a c i t o r s a n d Tu n a b l e B a n d - P a s s F i l t e r s and versatility with a Q of 50-80 at microwave frequencies (0.3 to 4 GHz). Low-loss MEMS varactors are an essential component in tunable networks and filters. MEMS-based tunable band-pass filters can bring much improvement in the tradeoffs between the tuning range and losses in filter designs, and they also can be tuned either analogically or digitally. Normally, digitally tuned band-pass filter have larger tuning ranges.

References 1. Rebeiz, G. M. RF MEMS Theory, Design, and Technology. New York: WileyInterscience, 2003. 2. Dec, A., and Suyama, K. “Micromachined electro-mechanically tunable capacitors and their applications to RF ICs” IEEE Trans. Microwave Theory Tech. 46: 2587–2596, 1998. 3. Young, D. J., and Boser, B. E. “A micromachined variable capacitor for monolithic low-noise VCOs.” In Proceedings of the International Conference on SolidState Sensors and Actuators, IEEE, Washington, 1996, pp. 86–89. 4. Chi, C.-Y., and Rebeiz, G. M. “A low-loss 20 GHz micromachined bandpass filter.” IEEE MTT-S Int. Microwave Symp. Dig. 3:1531–1534, 1995. 5. Chi, C.-Y., and Rebeiz, G. M. “Design of Lange-couplers and single-sideband mixers using micromachining techniques.” IEEE Trans. Microwave Theor. Tech. 45:291–294, 1997. 6. Yao, J. J., Park, S., and DeNatale, J. “High tuning ratio MEMS based tunable capacitors for RF communications applications.” In Proceedings of Solid-State Sensors and Actuators Workshop, IEEE, Washington, 1998, pp. 124–127. 7. Goldsmith, C. L., Malczewski, A., Yao, Z. J., Chen, S., Ehmke, J., and Hinzel, D. H. “RF MEMS variable capacitors for tunable filters.” Int. J. RF Microwave Computer-Aided Eng. 9:362–374, 1999. 8. Brank, J., Yao, Z. J., Eberly, M., Malczewski, A., Varian, K., and Goldsmith, C. L. “RF MEMS-based tunable filters.” Int. J. RF Microwave Computer-Aided Eng. 11:276–284, September 2001. 9. Hunter, I. C., Biloner, L., Jarry, B., and Guillan, P. “Microwave filters: Application and technology.” IEEE Trans. Microwave Theory Tech. 50:794–805, 2002. 10. Uher, J., and Hofer, J. R. “Tunable microwave and millimeter-wave bandpass filters.” IEEE Trans. Microwave Theory Tech. 39:643–653, 1991. 11. Fano, R. M., and Lawson, W. Microwave Transmission Circuits. New York: McGraw-Hill, 1948. 12. Tsui, J. B. Microwave Receivers with Electronic Warfare Applications. New York: Wiley, 1992. 13. Hassan T. “A broadband tracking YIG-tuned mixer for a state of the art spectrum analyzer.” In European Microwave Conference Digest, Rome, Italy, September 1987, pp. 482–490. 14. deGreese, R. W. “Low-loss gyromagnetic coupling through single crystal garnets.” J. Appl. Phys. 30:1555–1559, 1958. 15. Keane, W. J. “YIG filters aid wide open receivers.” Microwave J. 17:50–54, 1978. 16. Carter, P. S. “Equivalent circuit of orthogonal-loop-coupled magnetic resonance filters and bandwidth narrowing due to coupling resonance.” IEEE Trans. Microwave Theory Tech. 18:100–105, 1970. 17. Fierstal, R. F. “Some design considerations and realizations of iris-coupled YIG-tuned filters in the 12–40 GHz region.” IEEE Trans. Microwave Theory Tech. 18:205–212, 1970. 18. Tanbakuchi, H., Nicholson, D., Kunz, B., and Ishak, W. “Magnetically tunable oscillators and filters.” IEEE Trans. Magn. 25:3248–3253, 1989. 19. Chandler, S. R., Hunter, L. C., and Gordiner, J. C. “Active varactor tunable bandpass filters.” IEEE Microwave Guided Wave Lett. 3:70–71, 1993.

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Chapter Twelve 20. Brown, A. R., and Rebeiz, G. M. “A varactor-tuned RF filter.” IEEE Trans. Microwave Theory Tech. 48:1157–1160, 2000. 21. Munter, I. C., and Rhodes, J. D. “Electronically tunable microwave bandpass filters.” IEEE Trans. Microwave Theory Tech. 30:1354–1360, 1982. 22. Shen, K., Hui, F., Wong, W., Chen, Z., Lau, J., Chan, P. C. H., and Ko, P. K. “A three-terminal SOI gated varactor for RF applications.” IEEE Trans. Electron. Devices 48:289–293, 2001. 23. Mockly, B. H., and Zhang, Y. “Struntium titanate thin films for tunable YBa2Ca3O7 microwave filters.” IEEE Trans. Appl. Superconduct. 11:450–453, 2001. 24. Kozyrev, A., Ivanov, A., Keis, V., Khazov, M., Osadchy, V., Samoilova, T., Soldatenkov, O., Pavlov, A., Koepf, G., Mueller, C., Galt, D., and Rivkin, Τ. “Ferroelectric films: Nonlinear properties and applications in microwave devices.” IEEE MTT-S Int. Microwave Symp. Dig. 2:985–988, 1998. 25. Tombak, A., Maria, J., Ayguavives, F. T., Jin, Z. Z., Stauf, G. T., Kingo, A. I., and Mortazawi, A. “Voltage-controlled RF filter employing thin-film bariumstruntium-titanate tunable capacitors.” IEEE Trans. Microwave Theory Tech. 51:462–467, 2005. 26. Liu, Y., Borgioli, A., Nagra, A. S., and York, R. A. “Distributed MEMS transmission lines for tunable filter applications.” Int. J. RF Microwave Computer-Aided Eng. 11:254–260, 2001. 27. Tamijani, A. A., Dussopt, L., and Rebeiz, G. M. “Miniature and tunable filters using MEMS capacitors.” IEEE Trans. Microwave Theory Tech. 51:1878–1885, 2003. 28. Kim, J.-M., Lee, S., Park, J.-H., Im, J.-M., Baek, C.-W., Kwon, Y., and Kim, Y.-K. “MEMS-based compact dual-band bandpass filters with applications to wireless local area network.” J. Micromech. Microeng. 16:1135–1142, 2006. 29. Reines, I. C., Goldsmith, C. L., Nordquist, C. D., Dyck, C. W., Kraus, G. M., Plut, T. A., Finnegan, P. S., Austin, F., IV, and Sullivan, C. T. “A low loss RF MEMS Ku-band integrated switched filter bank.” IEEE Microwave Guided Wave Lett. 15:74–76, 2005. 30. Entesari, K., and Rebeiz, G. M. “A differential 4-bit 6.5–10-GHz RF MEMS tunable filter.” IEEE Trans. Microwave Theory Tech. 53:1103–1110, 2005.

CHAPTER

13

Advanced Packaging of RF MEMS Devices 13.1

Introduction Similar to IC packaging, packaging of radiofrequency (RF) MEMS devices must provide environmental protection, an electrical signal path, mechanical support, thermal dissipation and have a low parasitic capacity in the chip-substrate interconnection with low insertion loss and minimal interference. Packaging of RF MEMS devices should also prevent moisture and particulates, which may impair the movement of freestanding MEMS structures. Therefore RF MEMS devices must be packaged using hermetic or near-hermetic seals with certain vacuum level. It is possible to package MEMS switches or switch networks using conventional hermetic packages, such as ceramic package or metal package, and the like. The hermetic seal is achieved using seam-sealing, roller-sealing, or laser-sealing techniques, and these methods have been proven to be without any long-term reliability issues. The feed-throughs are coaxial, with glass or ceramic dielectrics, and satisfy the stringent hermetic leak conditions. In order to avoid difficulties in handling MEMS circuits, after release, MEMS devices should be packaged during wafer processing, which is carried out at the wafer level and before die singulation. This packaging step is referred to as zero-level packaging (or wafer level packaging). Once zero-level packaged, the MEMS product wafers can be handled like IC wafers and can be diced without great danger of breaking them. After dicing, the zero-level packaged devices are treated as individual dies that next can be one-level packaged.1,2

13.2

Zero-Level Packaging In zero-level packaging, two general approaches have been taken, here referred to as chip capping and thin-film capping, as shown in Fig. 13-1.2

515

516

Chapter Thirteen MEMS Device, e.g., resonator

Closed-off channel (seal)

Thin-film cap Etch Sealed cavity channel

Thin-film cap (broken away)

ME

Substrate

Mr

eso

nat

or

Substrate

Before sealing

After thin-film sealing

(a) MEMS substrate Sealing ring

Cavity Bond and seal layer

“Chip capsule”

Signal line RF MEMS device

RF MEMS device Feed-through line

(b)

MEMS substrate Side view

Top view

FIGURE 13-1 Zero-level packaging. (a) Using a thin-film capsule. The scanning electron microscope (SEM) photograph shows a sealed MEMS resonator after purposely removing the thin-film capsule. (b) Using a bonded-chip capsule.

13.2.1

Chip Capping

For the chip-capping technique, the bonding must be performed at sufficiently low temperatures (typically below 400°C) that the metallization and other material of the RF MEMS device are not adversely affected. In packaging an RF MEMS device, the package itself should have minimal effect on device performance. In an ideal package, the RF characteristics before and after capping should be the same. This requires low-loss RF transitions and minimal induced loss and detuning of the transmission lines owing to proximity coupling to the cap. According to Fig. 13-2,3 for MEMS switch Cavity Seal

Cap

Contact pad

Seal MEMS switch Cavity Contact pad

Substrate

Dielectric

Cap

Substrate Planar RF feed-throughs

(a)

Buried RF feed-throughs (b)

MEMS switch Seal

RF cap via Contact pad

Cavity Seal

Cap

Cap

Substrate Switch

Substrate

Cavity

RF substrate via Contact pad (c)

(d)

FIGURE 13-2 Possible implementation of the F transitions for a zero-level packaged RF MEMS switch: (a) horizontal planar RF feed-through; (b) horizontal buried RF feed-through; (c) substrate RF via; (d ) cap RF via.

Advanced Packaging of RF MEMS Devices

Sealing cap CPW

h

BCB

0.0 Naked CPW

AF 45 glass substrate Side view CPW ground

S21, dB

1

3

h = 5 μm Std Si cap (h = 85 μm)

–0.5 0

Top view

(a)

h = 45 μm h = 25 μm h = 15 μm

HRSi caps

4

CPW signal line CPW ground

2

2

4

6

8 10 12 14 Frequency, GHz

16

18

20

(b)

FIGURE 13-3 Zero-level packaged CPW line (25/100/25 μm, 2.3 mm long, 3-μmthick Cu) implementing a horizontal coplanar feed-through: (a) side and top views; (b) measured S21 on AF45 substrate capped with a LRSi cap (1 to 10 Ω-cm, h = 85 μm) and HRSi (>4000 Ω-cm) caps with varying cavity heights.

packaging of RF MEMS devices, the first thing is to fabricate a cap with a cavity or a thick sealing ring, the second is to design the feed-through, and the third is to bond the cap to the substrate.

Design of Cap with Cavity The use of low-loss, high-resistivity cap materials and a cap with sufficient cavity height largely will suppress the degrading influence of the presence of the cap, as shown in Fig. 13-3,1,4 which presents the RF performance of a coplanar feed-through (as in Fig. 13-3a) using benzocyclobutene (BCB) as the dielectric measured on a traversing coplanar waveguide (CPW) line. It is found that the impact on the RF characteristics of an RF MEMS device built on a 50-Ω CPW line with ground-toground spacing of 150 μm is kept negligibly small by using capping chips made of high-resistivity silicon with a cavity height exceeding 45 μm, that is, approximately one-third of the ground-to-ground spacing. However, it should be noted that a larger cap size may lead to an unwanted interfere traveling wave.5 Therefore, the cap should be kept as small as possible, which also meets industry trend toward smaller form factor.

Design of Feed-Through for RF MEMS Packaging From Fig. 13-2, electrical feed-throughs can be implemented horizontally (see Fig. 13-2a and b) or vertically (see Fig. 13-2c and d). Vertical vias present a more compact solution than horizontal vias, but the process is more complex. Actually, through-silicon vias (TSVs) are very suitable for vertical vias. For a planar RF feed-through, the sealing material should be dielectric, such as BCB, whereas for a buried RF feed-through, the sealing material could be dielectric, metal, or solder. For a vertical RF feed-through, any sealing material could be used. In this structure, the via is filled with metal (such as copper).

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Sealing Method In chip capping, it is common practice to bond a recessed capping chip onto the MEMS device wafer. The sealing ring is typically 50 to 300 μm in width. The bonding must be performed at sufficiently low temperatures (<400°C) so that the metallization and other materials used in the RF MEMS device are not adversely affected. Bonding materials that can be used for this purpose include polymer adhesives, frit glass, solder, and metal (mostly gold).

Sealing with Polymer Adhesives BCB is one of the most frequently used polymer adhesives. The capping wafer is processed independently from the MEMS wafer. A layer of BCB is spin-coated on the cap wafer and patterned to make rings of various dimensions. The capping chips are flip-chip-bonded onto the MEMS wafer at a temperature in the range 200 to 250°C. At these elevated temperatures, the BCB starts to flow, the bond is made, and the cavities are sealed off. Jourdain and colleagues6 developed a near-hermetic package using a thick BCB layer that acts as a bond and a seal layer (100 μm wide and 5 μm thick) as shown in Fig. 13-4. The leak rate of BCB sealed cavities strongly depends on the BCB sealing ring width, and leak rates as low as 10−15 mbarr ·l· s−1 are measured for BCB widths of 800 μm and drop to 10−8 mbarr·l·s−1 for BCB width of around 100 μm. Gross leak rate tests indicate that BCB seals are leak-tight, which means that the RF MEMS devices are well protected during backside processing, handling, and shipping. A great advantage of the BCB seals is that the RF lines can be fed directly underneath the seal ring and result in easy RF transitions. Sealing with Frit Glass Figures 13-5 and 13-6 shows a packaged switch that was developed by Omron.7 It is a series switch, but the same method can be applied to a shunt switch. The process consists of silicon-on-insulator (SOI) process, glass process, bonding process, and BCB ring 100-μm width 5-μm height

Edge of cap (borosilicate glass AF45)

Slot width 83 μm

MEMS switch

FIGURE 13-4

Line width 85 μm

A wafer-level packaged RF MEMS switch using BCB.

RF signal feed-through

Advanced Packaging of RF MEMS Devices

Frit glass

Glass cap

Bumps

Si actuator

GND

Glass sub.

Signal lines

Through-holes (transmission line)

(a)

(b)

FIGURE 13-5 Schematic assembly scheme (top) and photograph (bottom) showing a zero-level packaged RF MEMS relay with substrate via transitions. p-doped layer

Si substrate SiO2 Si structure layer (a)

Au alloy electrode (b)

SiO2 passivation layer

SiO2 passivation layer

Au electrode

Glass substrate

(c)

(d)

(e)

(f)

Glass cap

Frit glass

FIGURE 13-6

The fabrication process of the hermetically sealed Omron switch.

post bonding process. The first step is gap formation which creates recesses for electrode, interconnection, and contact gaps. Second, a contact metal and an isolation layer are patterned. A layer of gold is used for contact metal and LTO is used for isolation layer. Next, fixed contacts of gold, a fixed electrode of gold, and a sputtered-SiO2 passivation layer are patterned on a glass wafer. The SO1 wafer and the glass wafer are bonded anodically. A base silicon layer of the SO1 wafer is etched away by KOH after the process. In this process, etching automatically stops at the buried SiO layer, which makes precise silicon thickness control without any fancy apparatus. Finally, a part of the thin silicon diaphragm is etched by RIE. This process is also called wafer transfer method, which means the structures on the SOI substrate is transferred onto the glass substrate.

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FIGURE 13-7

Packaged FBAR devices with AuSn solder sealing.

The solder used here is not conventional solder paste because solder paste releases a lot of organic compounds during the curing process and may not be compatible with RF MEMS devices. In order to seal a RF MEMS device with solder, the solder material can be electroplated on the wafer or deposited by evaporation and then patterned on the wafer by a lift-off process. Figure 13-7 shows a packaged film bulk acoustic resonator (FBAR) device using an Au-Sn solder ring.8 The key technologies are hermetic wafer-to-wafer bonding and through-wafer interconnects, which are also important for stable RF signal connectivity. From a cross section of the AuSn sealing ring, a void-free structure is obtained within the solder layer (as shown in Fig. 13-8) so that a hermetic sealing of the packaging is expected. The packaged device also has undergone thorough harsh environment tests, such as the pressure-cooker test for 300 hours, the high-humidity storage test at 85°C/85 percent relative humidity for 1000 hours, the high-temperature storage test at 125°C for 1000 hours, and the temperature-cycling test (–55 to 125°C) for 1000 cycles. No physical damage to the package was observed after several reliability tests, which demonstrates the robustness of the package. For evaluation of RF signal-transmission characteristics of the RF MEMS device, RF characteristics of the RF packaging were measured with the CPW line instead of the RF MEMS device. Figure 13-9 shows the insertion loss after bonding, which is the sum of the package loss and the CPW line loss. The measurement results indicate a total insertion loss of around 0.06 dB at 2 GHz, and the insertion loss for the

Sealing with Solder

Advanced Packaging of RF MEMS Devices

1 2 3 4 5

FIGURE 13-8 SEM image of a cross section of the bonding layer.

0.0 IL at 2 GHz = 0.006 dB

Insertion loss, dB

–0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7

1

2

3

4 5 6 7 Frequency, GHz

8

9

10

FIGURE 13-9 Result of insertion-loss measurement. Insertion loss after bonding is the sum of package loss and CPW line loss.

packaging itself is very small. This result shows that the RF signal could be well transmitted under acceptable loss. Figure 13-10 shows that the amounts of frequency shift and IL increase were quite small. Mean values of fr and fa shifts after a 300-hour test were 2.0 and 0 MHz, respectively. Also, the increase in insertion loss is 0.014 dB. This indicates that there is no change in the transmission response of the FBAR device and excellent package hermeticity.

521

Chapter Thirteen 0 –5 –10 Loss, dB

522

–15 –20 –25 311 (Before test) 321 (Before test) 311 (After PCT 300 h) 321 (After PCT 300 h)

–30 –35 –40 1.9

2.0

2.1 Frequency, GHz

2.2

2.3

FIGURE 13-10 Measured performance characteristics of the fabricated FBAR device before and after 300-hour PCT test.

The most frequently used metal is gold (sometimes the sealing happened between Au and Si, which is AuSi eutectic bonding). Figure 13-11 shows a schematic of a packaged RF switch with dc and RF via transitions, and Fig. 13-12 shows an SEM image of an RF MEMS switch suspended over the RF transition.9 Gold-to-gold thermocompression bonding is used to connect a silicon cap to the substrate wafer. The switch displays an insertion loss of 0.15 dB between 11 and 2 GHz and an isolation of 16 dB at 24 GHz. The via

Sealing with Metal

Au bonding rim MEMS switch RF pad

RF feed line

Top wafer

dc pad

dc feed line Lower wafer

FIGURE 13-11 Schematic of packaged RF switch with dc and RF via transitions.

Advanced Packaging of RF MEMS Devices Top FGC line Actuation pads

MEMS switch

Anchor points RF vias

FIGURE 13-12 transition.

SEM image of an RF MEMS switch suspended over the RF

transition displays a 0.1-dB insertion loss, a 32-dB return loss at 20 GHz, and 55-percent bandwidth.

13.2.2 Thin-Film Capping Thin-film capping relies on surface micromachining and has been implemented in the past for various MEMS devices such as pressure transducers,10 MEMS resonators,11 and accelerometers.12 In preparing the thin-film encapsulation, an access or etch channel in the cavity wall is created. The sacrificial-layer etchant, for example, a buffered HF solution if silicon oxide is used as the sacrificial layer, enters through this channel. After removal of the sacrificial layer, the etch channel is sealed off using, for instance, a conformal coating of lowpressure chemical vapor deposition (LPCVD) nitride,11 a plasmaenhanced chemical vapor deposition (PECVD) oxide layer,12 or deposited metal.13 Figure 13-13 shows an RF MEMS switch capped with thin film.14 A conventional switch process sequence through membrane patterning was used, including (1) wafer clean, (2) deposit/pattern/etch (D/P/E) 300-nm gold electrode, (3) D/P/E 250-nm SiO2 switch dielectric, (4) electroplate 2.5-µm copper transmission lines, (5) pattern organic sacrificial layer, and (6) D/P/E 350-nm aluminum alloy membrane. Instead of releasing the membrane at this point in the process flow, as would occur for unpackaged switches or other packaging schemes, an additional cage sacrificial layer was applied over the unreleased switch membrane. Next, the dielectric cage was deposited. This cage sacrificial layer creates the desired separation between the membrane and packaging cage. Holes were patterned and etched into the cage, and the sacrificial layers were plasma-etched to create a released switch

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Membrane Device/package cross section

Cage structure

Transmission lines

Switch dielectric Electrode

Substrate ground plane

Encapsulant

Glass substrate

(a)

(b)

FIGURE 13-13 (a) A cross section of the microencapsulated package reveals a cage, encapsulation, and a sealant protecting the MEMS switch inside. (b) Photograph of a microencapsulated RF MEMS switch.

with a packaging superstructure above it. After release, a liquid encapsulate, such as spin-on-glass (SOG) or Cyclotene Series 4000 BCB, was applied over the entire wafer while in a dry-nitrogen atmosphere. The surface tension of the SOG or BCB ensures that it covers the cage structure but does not wick through the cage holes to encroach onto the switch. The SOG or BCB then was cured at 250°C to form a closed seal over the switch. At this point in the process flow, the microencapsulation provides the minimum level of protection from humidity. Additional sealant overcoats can be applied to increase the level of protection.

Advanced Packaging of RF MEMS Devices 0

0

Average sw electrode

Insertion loss, dB

–10

Average pkg sw electrode

–0.2

–15 –20

–0.3

–25

–0.4

–30 –0.5

Return loss, dB

–5

–0.1

–35

–0.6

–40 0

5

10

15

20 25 30 Frequency, GHz

35

40

45

50

FIGURE 13-14 Comparison of losses for an unpackaged and packaged RF MEMS switch through 50 GHz.

RF measurements were repeated for unpackaged and micropackaged RF MEMS switches, as shown in Fig. 13-14. The package-added insertion loss, based on the switch data, is approximately 0.06 dB at 35 GHz. The total packaged-switch insertion loss is a very respectable 0.12 dB at 35 GHz. This micropackaged switch insertion loss will be lower in a phase shifter because the off-capacitance will be impedancematched. It is also apparent that the difference in the return loss is more pronounced. This can be explained by the fact that these measurements were performed on separate wafers from different lots. Hence there is more wafer-to-wafer variation in the membrane gap than in the electrode dimensions. Therefore, the switch RF data are expected to have more variation. At 35 GHz, the package adds between 0.02 and 0.06 dB of insertion loss for the switch electrode and RF MEMS switch data, respectively. It is believed that the switch electrode data more accurately portrays the added insertion loss, but to be conservative, 0.04 dB is used.

13.3

One-Level Packaging In one-level packaging, the packaged and diced die can be mounted in a ceramic package or a plastic molded package.1,15,16 Alternatively, using more advanced packaging technologies, the assembly can be handled as a chip-scale package (CSP) and joined directly to a printed wiring board or ball-grid array (BGA) laminate, as shown in Fig. 13-15. One-level packages provide mechanical and environmental protection to the devices they hold, but not without degrading electrical performance. At microwave frequencies (and higher), the impact the package has on the electrical performance becomes an important element in the design of the device.17 Plastic packaging is the most common packaging solution applicable for frequencies below several

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One-level package Zero-level package Wire bond MEMS substrate MEMS substrate Lead frame

Zero-level packaged MEMS chip PGA

Ceramic package

(a)

Mould epoxy

(b)

Plastic package (e.g., SOIC-8) Solder bump interconnect

MEMS substrate

Underfill MEMS

Solder ball

MEMS device

PWB, MCM-D, LTCC,.... Direct mounting (CSP)

(c)

FIGURE 13-15

(Laminate) BGA

ASIC

Solder ball

(d)

Examples of one-level packaging of RF MEMS devices.

gigahertz. Careful choice of the plastic molding material and RF design of the lead frame allow use up to 10 GHz. For use at higher frequencies, ceramic packages based on multilayer low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) technology, employing low-loss dielectrics combined with flip-chip assembly of the device for short interconnects, exhibit the potential for good performance into the millimeter-wave regime (as high as 80 GHz).18

13.4

Reliability of Packaged RF MEMS Devices The reliability of packaged RF MEMS devices with the preceding packaging approach can be tested with reliability standards, such as the pressure-cooker test, high-humidity storage test at 85°C/85 percent relative humidity, high-temperature storage test at 125°C, and the temperature-cycling test. The reliability of packaging for RF MEMS devices has been discussed in a great deal of literature. For example, in ref. 8, the reliability of FBAR devices with AuSn sealing has been studied in detail. Table 13-1 lists the reliability test conditions, and Table 13-2 lists the long-term reliability test results. For a 300-hour test duration, there were seven parameter-checking interruptions, and the trend of variation is plotted in Fig. 13-16. The amounts of frequency shift and IL increase were quite small, as shown in Fig. 13-10. Mean values of fr and fa shifts after the 300-hours test

Advanced Packaging of RF MEMS Devices Item

Condition

Samples

Pressure-cooker test

121°C, 100% RH, 2 atm, 300 h 85°C, 85% RH 1000 h 21°C, 100% RH 1000 h –55 to 125°C, 15-minute dwell, 1000 cycles

21

High-humidity storage test High-temperature storage test Temperature-cycle test TABLE 13-1

Long-Term Reliability Test Conditions for the Package

Item Pressure-cooker test High-humidity storage test High-temperature storage test Temperature-cycle test

TABLE 13-2

Mean SD Mean SD Mean SD Mean SD

Dfr (MHz)

Dfa (MHz)

D IL (dB)

2 0.79 2 0.67 2 0.57 2 0.81

0 0 0 0.43 0 0 0 0

0.014 0.015 0.016 0.004 0 0.006 0 0.005

Variation of resonance frequency Δfr, MHz

4 2 0

–2

Variation of anti-resonance frequency Δfa, MHz

Long-Term Reliability Test Results for the Package

6

3 2 1 0

–1

–4

–2

–6

–3

Initial 16

(a)

21 21 21

32

48

96

148 192 240 300

Initial 16

(b)

Storage time, h

32

48

96

148 192 240 300

Storage time, h

Variation of insertion loss, ΔIL, dB

0.10

.05

0.00

–0.05

–0.10 Initial 16

(c)

32

48

96

148 192 240 300

Storage time, h

FIGURE 13-16 Variations inf the characteristic parameters during PCT tests: (a) variation in fr; (b) variation in fa; (c) variation in insertion loss.

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Chapter Thirteen were 2.0 and 0 MHz, respectively. Also, the increase in insertion loss was 0.014 dB. This indicates that there is no change in transmission response of FBAR devices and excellent package hermeticity. The high-humidity storage test, which is 85°C, 85 percent relative humidity for 1000 hours; the high-temperature storage test, which is 125°C for 1000 hour; and the temperature-cycle test, which is –55°C (15 minutes) to 125°C (15 minutes) and back for 1000 cycles, also were performed. The test results are summarized in Table 13-2, and it shows similar variation trends to PCT. Imperfection of the bonded area and via filling may cause hermeticity problems, acting as a leak path and finally leading to reliability failure. With these reliability-test results, it can be said that RF MEMS devices are well bonded with cap and bottom wafers hermetically and that through-wafer vias are well filled with copper without any leak path or electrical problems.

13.5

Summary This chapter addressed zero- and one-level packaging of RF MEMS devices. The packaging of MEMS switches provides a larger challenge than the packaging of standard MEMS devices owing to the need for hermeticity, temperature, and outgassing constraints. Also, MEMS switches must be packaged in a nitrogen or dry-air atmosphere for high reliability. In zero-level packaging, capping of RF MEMS devices can be categorized as chip capping and thin-film capping. In the first approach, it is common practice to bond a recessed capping chip onto the MEMS device wafer. Bonding materials include polymer adhesives, frit glass, solder, and metal. Thin-film capping has a smaller form factor, but it is difficult to release the MEMS devices in this method. In both the capping methods, the input and output RF transitions do not pose any design problems up to 40 GHz, and excellent results have been achieved up to 40 GHz using via-hole transitions. In one-level packaging, plastic packaging is the most common solution applicable for frequencies below several gigahertzes. For use at higher frequencies, ceramic packages based on multilayer LTCC or HTCC technology employing low-loss dielectrics combined with flip-chip assembly of the device for short interconnects exhibit the potential for good performance into the millimeter-wave region.

References 1. De Los Santos, H. J., Fischer, G., and Tilmans, H. A. C. “RF MEMS for ubiquitous wireless connectivity: I. Fabrication” IEEE Microwave Magazine, December 2004, pp. 36–49. 2. Legtenberg, R., and Tilmans, H. A. C. “Electrostatically driven vacuum encapsulated polysilicon resonators: I. Design and fabrication.” Sensors & Actuators A 45:57–66, 1994.

Advanced Packaging of RF MEMS Devices 3. Tilmans, H. A. C. “MEMS components for wireless communications” (invited paper). In Proceedings of the 16th European Conference on Solid-State Transducers, Prague, Czech Republic, September 15–18, 2002, pp. 1–34. 4. Jourdain, A., Rottenberg, X., Carchan, G., and Tilmans, H. A. C. “Optimization of 0-level packaging for RF MEMS devices.” In Proceedings of Transducers’03, Boston, MA, June 8–12 pp. 1915–1918, 2003. 5. Min, B.-W., and Rebeiz, G. M. “A low-loss silicon-on-silicon DC-110 GHz resonance-free package.” IEEE. Trans. Microwave Theory Tech. 54:710–716, 2006. 6. Jourdain, A., De Moor, P., Pamidighantam, S., and Tilmans, H. A. C. “Investigation of the hermeticity of BCB-sealed cavities for housing RF MEMS devices.” In Proceedings of the 15th IEEE International Conference on Microelectromechanical Systems, Los Vegas, NV, January 20-24, 2002, pp. 677–680. 7. Sakata, M., Komura, Y., Seki, T., Kobayashi, K., Sano, K., and Horike, S. “Micromachined relay which utilizes single crystal silicon electrostatic actuator.” In Proceedings of the 12th IEEE International Conference on Microelectromechanical Systems, Orlando, FL, January 17-21, 1999, pp. 21–24. 8. Suk-Jin Ham, Byung-Gil Jeong, Ji-Hyuk Lim, Kyu-Dong Jung, Kae-Dong Baek, Woon-Bae Kim, and Chang-Youl Moon. “Characterization and reliability verification of wafer-level hermetic package with nano-liter cavity for RF-MEMS applications” In Proceedings of the 57th IEEE Electronic Components and Technology Conference, Las Vegas, NV, May 29–June 1, 2007 pp. 1127–1134. 9. Herrick, K. J., Yook, J.-G., and Katehi, L. P. B. “Microtechnology in the development of three dimensional circuits.” IEEE Trans. Microwave Theory Tech. 46:1832–1844, 1998. 10. Guckel, H., and Burns, D. W. “A technology for integrated transducers.” In Proceedings of Transducers ’85, Philadelphia, PA, 1986, pp. 90–92. 11. Legtenberg, R., and Tilmans, H. A. C. “Electrostatically driven vacuum encapsulated polysilicon resonators: I. Design and fabrication.” Sensors & Actuators A 45:57–66, 1994. 12. Stahl, H., Hoechst, A., Fischer, F., Metzger, L., Reichenbach, R., Laermer, F., Kronmueller, S., Breitschwerdt, K., Gunn, R., Watcham, R., Rusu, C., and Witvrouw, A. “Thin film encapsulation of acceleration sensors using polysilicon sacrificial layers.” In Proceedings of Transducers ’03, Boston, MA, 2004, pp. 1899–1902. 13. Stark, B. H., and Najafi, K. “An ultra-thin hermetic package utilizing electroplated gold.” In Proceedings of Transducers ’01, Munich, Germany, 2002, pp. 194–197. 14. Forehand, D. I., and Goldsmith, C. L. “Wafer level microencapsulation.” Presented at Government Microcircuit Applications Conference (GOMACTech ‘05), Las Vegas, NV, April 2005. 15. Tilmans, H. A. C., Fullin, E., Ziad, H., Van de Peer, M., Kesters, J., Van Geffen, E., Bergqvist, J., Pantus, M., Beyne, E., Baert, K., and Naso, F. “A fully packaged electromagnetic microrelay.” In Proceedings of MEMS ’99, Orlando, FL, 2000, pp. 25–30. 16. Fujii, M., Kimura, I., Satoh, T., and Imanaka, K. “RF MEMS switch with wafer level package utilizing frit glass bonding.” In Proceedings of the 32nd European Microwave Conference, Milan, Italy, 2002, Vol. 1, pp. 279–281. 17. Chandrasekhar, A., Brebels, S., Stoukatch, S., Beyne, E., De Raedt, W., and Nauwelaers, B. “The influence of packaging materials on RF performance.” Microelectronics Reliability 43:351–357, 2003. 18. Ito, M., Maruhashi, K., Senba, N., Takahashi, N., and Ohata, K. “Low cost multilayer ceramic package for flip-chip MMIC up to W-band.” In 2000 IEEE MTT-S Digest, 2000, pp. 57–60.

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Index Note: Page numbers followed by “t” indicate tables and page numbers followed by “f ” indicate figures.

A accelerometer, 2, 3, 49, 438f MEMS device, 51f packaging, 435–473 ultracompact encapsulated, 177 wafer-level 3D package for, 471–473, 472f, 472t, 473f access networks, 210 actuation force: on membrane material, 382t, 383t on silicon rubber, 383t actuation mechanisms, in optical MEMS applications, 211–224 actuator movement, space for, 157 actuator speed, flow rate to, 393t actuators/mirror, of PZT, 257f adhesive, ultraviolet curable liquid, 105 adhesive bonding, 169 adhesive tape, double-sided, 367f Agilent Technology, 297 Ag-In, long-term room-temperature storage of, 187–188 aging test, HTHH, 275 aging treatment, effect of, 188 Alchimer’s electrografting, Ti barrier/ adhesion layer and Cu seed layer by, 88, 88f alkaline etchants, 162 aluminum foil, reservoirs with, 380f aluminum pad, 53 amorphous silicon, 259 Analog Devices, 5, 49f analog tuning: of RF-MEMS tunable band-pass filters, 505–506, 505f , 506f of RF-MEMS tunable capacitors, 496–503 angular mirror loss, 283

anisotropic etchants, 162 anisotropic geometries, 159 anisotropic silicon etchants, 160 anisotropic wet-etched Si V-grooves, 173 annealing, bonded interface after prolonged additional, 192f annealing effect, bonded interface under additional, 191f anodic bonding, 169 ANSYS software, 336 antireflection material, 279 AOI test. See automated optical inspection test APM. See Asia Pacific Microsystems area tuning, of RF-MEMS tunable capacitors, 502–503, 502f, 503f arsenide, 1 Asia Pacific Microsystems (APM), 240 ASIC chip, 49, 49f MEMS device bonded on, 72f MEMS device on, solder-bumped flip-chip, 72f MEMS device wire bonded on, 71f solder-bumped flip-chip, on MEMS device, 69, 69f TSV MEMS device solder bonded on, 71f ASIC wafer, 67, 68f Cu-Ni-Au UBM on, 92, 92f fabricated, 122f with low-temperature solders, 122f MEMS device bonding, 124f with TSV, 91–92 Cu-Ni-Au front-side metallization on, 92f as-received evaporated composite coating surface, 114f as-received evaporated/electroplated bonding ring, 114

531

532

Index attenuation curve: of bright operation, 243f for dark operation, 247f vs. dc driving voltage, 259f at two temperatures, 274f attenuation fluctuation, 273f Au layer, 53 Au0.03/(InSn)3/Au0.03/Cu2 metallization, TEM analysis of, 193f Au-In, phase diagram, 120f Au-Sn solder, lift-off process, 145 Au-Sn solder phase diagram, 145f Au-Sn solders, for MEMS packaging, 145 automated optical inspection (AOI) test, 146 Avago Technologies, 5 axial resolution, 410 axial scanning test result, of optical probes, 427–429, 428f, 429f Axsun Technologies, 261

B back-end packaging process factors, 264 back-grinding machine, 101, 106f, 109f back-wafer, 101–104 ball grid array (BGA), 139, 279 barrier/adhesion and seed metal layer deposition, 87–88 base chip, cap chip and, 119f BCB. See benzocyclobutene beam size study, optical stimulation for, 413f bend tests, 146 bent-beam structures, for mechanical amplification, 217 benzocyclobutene (BCB), 170 BGA. See ball grid array BHC. See bottom-side half-cut biased 85/85 tests, 140 bidirectional electrostatic comb actuator, 227 bioapplications, of microelectronics, 354 biocartridge overview, in DNA/RNA extraction, 363–364 biochip attachment, to microfluidic package, 365–366 biocompatible polymeric materials, 359–361 biologic testing, microfluidic package, 392–393 bio-MEMS: applications, 2 chip, 355–356 packaging, 353–395 biomicrofluidic package: integrated, 354f schematic, 354f

biosensor packaging, 397–433 GRIN lens in, 401–403, 403f micromirror in, 401, 401f single-mode optical fiber in, 401–403 bistable micromechanisms, 227 bistable optical crossbar switch, 228, 229f bistable optical switches, 218 bistable switching, 228 Boehringer Ingelheim Microparts, 5 bolometer, 327 sensitivity vs. vacuum for, 330f vacuum packaging of, 340–343 bolometer chip, 329–330 photo of, 329f temperature stability, 331 bolometer package: deformation for, 339f, 340f designs of, 337f final temperature stability testing of, 334–335 fully assembled, 346f during getter activation, 345f image testing, 350–351, 351f structural optimization of, 335–340 with TEC, 332, 332f temperature stabilization during cooling of, 335f temperature stabilization during heating of, 335f testing setup for, 346–350 thermal optimization for, 330–335 vacuum measurement technique, 346–350 warpage of germanium window and, 338t bolometer response: under different air pressures, 350f under different vacuum conditions, 349f bolometer voltage, under different vacuum conditions, 349t bolt deformation, under pretension, 323f bolt finite-element model, 320–325 configuration/surrounding materials, 320f description, 320–322 package, 321f schematic, 321f bolted photonic switch, responses to, 322–325 bolt-up load formula, 322 bond chamber, 106–107 bond interface, 115 after pull test, 116f TEM image of, 117f bond pad, 125f bonded 8-in diameter stack wafers, 186f

Index bonded chips, with poor hermeticity, 200 bonded devices, using Ti/Cu/Ni/Au UBM, 197f bonded interface: under additional annealing effect, 191f EDX analysis, 187f after long-term room-temperature storage, 189f under low-temperature aging, 190f microstructure of, 198f after prolonged additional annealing, 192f reliability study of, 198, 198f bonded wafers, 126 with 100% yield, 197f bonding, temporary, 107f bonding chamber, 125 bonding conditions, bonding strengths and, 114f bonding couples: contact, 115 pull test results of, 114, 114f bonding process, device-wafer/ perforated support-wafer, 108, 110f bonding rings, cross section of, 115f bonding strengths, bonding conditions and, 114f bonding with intermediate level, 168 bonding yield, 194 bonding/pickup tool, 123f Bosch etch process, 84 DRIE using, 166f etch cycle, 85t etch rate, 85t passivation cycle, 85t bottom-side half-cut (BHC), 128f boundary-value problem, of photonic switch, 302–306 bounded beams, free space propagation of, 210 bow data/bending profiles, 103f of stress-sensor wafer, 100f bow of stress-sensor wafer, 103t BOX. See buried oxide Brewer Science, 105 bright operation, attenuation characteristic curves of, 243f brominated flame retardants, 133 bubble-switch elements, 300f buckled-beam arch-shaped leaf-spring geometry, 227 buckled-beam spring, 228, 229 bulk micromachining, 159–170, 221, 225 of RF-MEMS switches, 488–489 for vertical-comb-driven two-axis mirror, 236 buried oxide (BOX), 185

C C2C bonding. See chip-to-chip bonding C2W bonding. See chip-to-wafer bonding cadmium exemptions, RoHS, 136 calculation method, of package deflection, 319f Canon, 5 cap: for MEMS packaging, 6 wafer, 68f cap chip, base chip and, 113f, 119f cap wafer: with cavities, 124f with seal ring, 124f with TSV, cavity and, 93 capacitance-gauge calibration curve, isothermal fatigue tests, 312f capillary electrophoresis, microfluidics and, 353 capillary-force passive valve, in microfluidic components, 359f casting method, replication technologies and, 362–363 cavity: cap wafer, 67, 68, 124f with TSVs, 93 length control, 263 CDF. See cumulative distribution function cell sorting, microfluidics and, 353 central processing unit (CPU), 52 CFD. See computational fluid dynamic channel layer, PMMA to PMMA bonding for, 385–387 chemical vapor deposition (CVD), 174 chemical/mechanical polishing (CMP), 89f, 222 Cu polishing by, 91–92 chip capping, of RF-MEMS, 516–523, 517f chip scale package (CSP), 139 chip thickness, temperature maps for, 65f chips, large, 50 chip-to-chip (C2C) bonding, 51 reliability assessment of, 121f chip-to-wafer (C2W) bonding, 51 cleanability test, 146 C-mode scanning acoustic microscope (SAM), 309, 310f CMOS. See complementary metaloxide-semiconductors CMOS-MEMS-based scanning mirror, 219 CMP. See chemical/mechanical polishing CO2 laser-induced thermal stress, 132

533

534

Index COC. See cyclic olefin copolymers coin-stack packing canister, 107 cold arm, 216 Colibrys, 5 collimating lens, in 3D VOAs, 256f collimator misalignment loss, 283 comb actuator, 213f bidirectional electrostatic, 227 static displacement of, 213 comb fingers, 213, 213f comb-drive actuator, 226, 228 complementary metal-oxidesemiconductors (CMOS), 1 MEMS devices, 168 composite solder, melting temperature of, 118 compressive stress, 102 computational fluid dynamic (CFD), 58, 332 conformal SiO2, 86, 86f contact printing, 171 contamination risk, 129 Continental Automotive, 5 conventional wafer-bonding technologies, for packaging, 168–171 cooling temperatures, package deflection at, 319f copper electroplating, in TSV, 458f copper-filled TSV chips equivalent thermal conductivity for, 60f 3D IC integration of, 58, 59f coupling efficiency: mirror curvature and, 415–417, 416f, 417t optical stimulation for, 413f CPU. See central processing unit crack extension, 129f creep hysteresis loops, 306, 306f creep strain rate, 305f creep-strain energy-density range, 308, 309f creep-strain energy-density range per cycle, 300 crossbar switches, 225, 228 cross-sectional scanning acoustic microscopy (C-SAM), 194 cross-sectioning, solder joint FA and, 141 cryonic approach, 165 C-SAM. See cross-sectional scanning acoustic microscopy CSP. See chip scale package Cu bonding rings vs. In-Sn low-temperature solders, 195t Cu electroplated wafer: CT of, 90f, 91f x-ray of, 90f, 91f Cu electroplating solution, 89

Cu overburden, from long plating time, 89f Cu polishing, by CMP, 91–92 Cu-based metallization, eutectic In-Sn solder for, 192f Cu-filled TSV chips: junction temperature of, 64f, 65f, 67f staggered heat sources on, 67f thermal resistance of, 64f, 67f Cu-In, phase diagram, 120f cumulative distribution function (CDF), 139 Cu-Ni-Au front-side metallization, on TSV ASIC wafer, 92f Cu-Ni-Au under-bump metallurgy (UBM), on ASIC wafer, 92, 92f curved-flexure-beam electrostatic actuator, 266f Cu-Sn solder microbumps, electroplated: focused-ion-beam image of, 54f scanning electron microscope image of, 54f, 55f Cu-Sn solder microbumps, scanning electron microscope image of, 54f Cu/Sn-In solder interlayer, reaction zone, 115, 117f CVD. See chemical vapor deposition cyclic load vs. displacement curve, 311 cyclic olefin copolymers (COC), 361 cylindrical reservoirs, 373f

D dark operation, attenuation characteristic curves for, 247f dark-type VOA, 244 DAVID project. See Downscaled Assembly of Vertically Interconnected Devices project dc driving voltage vs. attenuation curve, 259f de Rooij, N. F., 238, 239, 242 debonding, 107–108, 107f, 109f deca-BDE exemption, RoHS, 136 dedicated wafer cassette, 107 deep reactive ion etching (DRIE), 82, 108, 165, 222, 226 vs. laser, Sematech’s cost model of, 83f using Bosch process, 166f deep reactive ion etching (DRIE)derived planar VOAs dual-reflection mirrors and, 247–248 rotary-comb actuator and, 248–251 shutter/single-reflection mirror and, 242–247 using electrostatic actuators, 242–252 using electrothermal actuators, 252–254

Index Dektak, 316 Delphi, 5 dense wavelength divisionmultiplexed (DWDM), 238 Denso, 5 depth of focus (DOF), 409 design for reliability (DFR), 140, 141, 142 design software, for TSVs, 82 design technology, for TSVs, 82 device-wafer/perforated supportwafer bonding process, 108, 110f DFR. See design for reliability DGE. See dynamic gain equalizer diamond saw, 126 dicing of silicon-on-glass wafers, 130–133, 132f of silicon-on-silicon wafers, 130 of SOI wafers, 129, 131f dicing-tape expansion, 126 die temperature stability, with TECs, 334f dielectric constant, 212 dielectric isolation layer (SiO2) deposition, 86–87 by plasma deposition, 87f by wet thermal oxidation, 86f differential scanning calorimetry (DSC), 121, 121If diffractive MEMS VOA, 259f, 260 digital tuning of RF-MEMS tunable band-pass filters, 506–512, 507f, 508f, 509f, 510f, 511f of RF-MEMS tunable capacitors, 503–504, 503f, 504f DIP. See dual-in-line package direct bonding, 168, 169 directive–compliant three-dimensional (3D) bubble actuated photonic cross-connect switches, 297 DISCO, 130 displacement curve vs. cyclic load, 311 DLP technology, 2 DNA, microfluidic package for, 371f DNA analysis, microfluidics and, 353 DNA chip, attached to PDMS substrate, 368f DNA extraction: cartridge pretreatment, 394 eluted amount, 393t elutions, 394f PCR amplification, 394 sample preparation/setup, 394 DNA/RNA extraction: biocartridge overview in, 363–364 microfluidic chip for, 355f reagent protocol for, 356t

DOF. See depth of focus Downscaled Assembly of Vertically Interconnected Devices (DAVID) project, 129 DRIE. See deep reactive ion etching dry-etching gases, selection of, 163, 164t dry-etching-process technologies, 162 DSC. See differential scanning calorimetry dual-in-line package (DIP), 186 dual-reflection mirrors, DRIE-derived planar VOAs and, 247–248 dummy bumps, 53 DWDM. See dense wavelength division-multiplexed dye and pry, solder joint FA and, 141 dynamic attenuation characteristics, 273t dynamic gain equalizer (DGE), 238 dynamic reliability, of optical switches, 283

E ECR. See electron cyclotron resonance EDA. See electronic design automation EDFAs. See erbium-doped fiber amplifiers EDP. See ethylene diamine pyrochatechol EDX. See energy dispersive x-ray EEE. See electrical and electronic equipment eight-channel MEMS VOA, 264f electric field distribution, in wafer level package, 440f electrical and electronic equipment (EEE), 133 electrical interconnects, 172–175 extraction methodology for, 442–448, 442f, 443f, 445f, 446f, 447f, 448f electrical modeling, wafer level package and, 438 electrodes, in electrostatic actuation, 213 electroless Ni and immersion Au (ENIG), 53 focused-ion-beam image of, 56f schematic, 54f electroless Ni and immersion Au (ENIG) UBM pad, 54f focused-ion-beam image of, 56f scanning electron microscope image of, 54f, 56f electromagnetic actuation, VOA, 261 electromechanically tunable parallel-plate capacitor, 500f electromigration tests, 140

535

536

Index electron cyclotron resonance (ECR), 165 electronic design automation (EDA), 47 Electronics, 47 electronics industry compliance, of RoHS, 138 electroplated nickel thick-film cap, 178 electrostatic actuation design tradeoff for, 215 DRIE-derived planar VOAs using, 242–252 electrodes in, 213 mechanism, 235 in optical MEMS applications, 212–217 electrostatic chuck (ESC), 84 electrostatic comb-drive actuators, 228 electrostatic VOA, optical MEMS applications and, 269–275 electrothermal actuator (ETA), 228, 240 DRIE-derived planar VOAs using, 252–254 elliptical mirror, 251–252 Eloy, Jean Christophe, 2, 3 emerging microelectromechanical systems (MEMS), 3 energy dispersive x-ray (EDX), 118, 186 solder joint FA and, 142 ENIG. See electroless Ni and immersion Au epitaxial Si encapsulation technology, 177, 177f epitaxial Si layer, 177 equivalent thermal conductivity, 59, 59f for copper-filled TSV chip, 60f erbium-doped fiber amplifiers (EDFAs), 238 ESC. See electrostatic chuck ETA. See electrothermal actuator etch mask, cleaning and stripping of, 86 etching chemistry, 159 etch-rate calibration, 168 ethylene diamine pyrochatechol (EDP), 160 eutectic Au-Sn solder, 170 eutectic bonding, 169 In/Sn/Cu systems after, 194 eutectic composition, 119, 184 eutectic In-Sn solder, for Cu-based metallization, 192f EVG, 105 EVG bonder, 109 EVG debonding process flow, 109f EVG850TB, 107 EVG temporary bonding/debonding process flow, 107f

EVG temporary bonding/debonding system, 105–108 EVG wafer-coating chamber, 108f EVG’s Smart-View Bond Aligner, 125 exothermic reaction, 168 expansion process, 128f external actuator, acting on reservoirs, 372f extraction methodology, for electrical interconnects, 442–448, 442f, 443f, 445f, 446f, 447f, 448f

F FA. See failure analysis fabrication process parameters: for and Cu seed layer, 88t for Ti barrier/adhesion layer, 88t face-to-face low temperature bonding, 112f failure analysis (FA), 140 failure probability, 139 fast chips, 50 fatigue failure, 138, 139 FBAR. See film bulk acoustic resonator FC150 bonder, 123f FIB. See focused ion beam fiber-alignment, with micromirror, 428f fiber-alignment trenches, 242 fiber-to-the-home (FTTH), 238 field-assisted bonding, 168, 169 50-μm-device wafer, 110f, 111f 50-μm-diameter vias, 85f film bulk acoustic resonator (FBAR), 171 film-frame carrier, 107 final temperature stability testing, of bolometer package, 334–335 finite-element method, package deflection by, 317–320 fixed-fixed beam, 481f deflection results from, 483f flat micromirror: lateral tilt of, 417–419 , 418t, 419t vertical tilt of, 420–421 , 420t, 421t flip-chip solder bumps, 58 Flir Systems, 5 flow rate, to actuator speed, 393t fluid flow-control mechanism, 375–377, 377f fluid testing, 389, 389t microfluidic package, 391–392 fluid/electric interconnections, microfluidic package with, 369f fluidic chip, microfluidic package with, 358f fluidic dispensing control, 355

Index fluxless process, 184 focused ion beam (FIB), solder joint FA and, 141 fracture surfaces, after pull tests, 115 Fraunhofer Institute, 129 free space propagation, of bounded beams, 210 Freescale Semiconductor, 5 fringe pattern, 316, 318f FTTH. See fiber-to-the-home functional cycling tests, 140 functional shutter, 251–252 functional test, 146 fusion bonding, 112, 168

G gallium, 1 gap tuning, of RF-MEMS tunable capacitors, 497–501, 497f Garofalo-Arrhenius constitutive equation, 303 Garofalo-Arrhenius creep constitutive law, 300 gas phase etchants, 167f gas xenon diflouride, 168 gate switches, 225 Gaussian beams, 261, 409f Gaussian distribution, of optical power, 407f GE Sensing, 5 germanium substrate: different metallizations for, 343t metallization peel-off, 343f germanium window, 335, 342–343 thickness, 338f UBM layer on, 344f getter activation, bolometer package during, 345f getter attachment/activation, 344–345 getter deposition, 465f getter lead attachment, with solder, 344f getter temperature, with different currents, 345f glass support plate, 105 glass-frit bonding, 169 graded-index (GRIN) lens in biosensor packaging, 401–403, 403f design of, 413f parameters of, 408f on SiOB substrate, 424f GRIN lens. See graded-index lens gripper, 228 Gwang-Ju Institute of Science and Technology, 252 gyroscopes, 3

H Hamamatsu Photonics, 127 handler wafer, 436 for lift-off technique, 458f, 461f during ultrasonic agitation, 460f for wafer bonding, 459f hard-mask materials, 160 H-beam actuator, 230 H-beam thermal actuators, 218, 218f H-beam-driven crossbar switch, 230 H-beam-driven optical switch, in transmission state, 231f HDI. See high-density interconnect heat sources: overlapping, 66 staggered, 66 helium leakage, 121, 121f rate testing, 198 rates, 175 hermeticity, of vacuum package, 327 Hewlett-Packard, 5 hexavalent chromium exemptions, RoHS, 136, 137 HF vapor etching, 176, 178 high input-output pin counts, SiP with, 175 high through-put screening, microfluidics and, 353 high-aspect-ratio tapered silicon vias, 84 high-density interconnect (HDI), 181 high-density plasma etching, 163 high-humidity storage, 198 high/low-temperature storage tests, 140 high-melting point (HMP), 182 high-power microscopy, solder joint FA and, 141 high-speed logic, 82 high-temperature, high-humidity (HTHH) aging test, 275 high-temperature wafer-level encapsulation, 177–178, 177f high-temperature-storage test (HTS), 121 high-voltage extended-life tests, 140 high-yield process, 179 HMP. See high-melting point HNA, 159 homogeneous material, 134 Honeywell, 5 hot arm, 216 hot embossing, replication technologies and, 363 H-shaped beam actuator, VOA using, 272f H-shaped beam-driven VOA, 273 H-shaped silicon beam structure, 253, 253f HT Brewer Science, 106

537

538

Index HTHH. See high-temperature, highhumidity HTS. See high-temperature-storage test hysteresis loops, isothermal fatigue tests, 313f

I IBL. See intermediate bonding layer ICP. See inductively coupled plasma ICs. See integrated circuits ICT. See in-circuit test IMCs. See intermetallic compounds IMOD. See interferometric modulator displays In-Ag phase diagram, 182f In-Ag system, on noneutectic composition, 183–194 in-circuit test (ICT), 146 inductive-coupled plasma (ICP)-based deep reactive ion etching system, from STS, 84 inductively coupled plasma (ICP), 165 infrared bolometer, vacuum package for, 327 infrared bolometer vacuum package, 342f infrared package, 335 injection molding, replication technologies and, 363 inkjet printers, 2, 3 in-line VOA, 244 schematic of, 245f in-plane displacement, 216 insertion loss, in wafer level package, 441f In-Sn layer, 118 In-Sn low-temperature solders vs. Cu bonding rings, 195t In-Sn phase diagram, 183f InSn solder vs. Ti/Cu/Ni/Au UBM metallization, 196f In/Sn/Cu systems, after eutectic bonding, 194 Instron microtester, 96 insulating oxide layer, 178 integrated circuits (ICs), 1 integrated circuits (ICs) packaging, advanced, 47–67 integrated circuits (ICs) packaging industry, 158 integrated micromachining processes, 221–224 in optical MEMS applications, 211–224 Intel’s roadmap, of packagearchitecture transitions, 52f interconnects, 158–178 interdigitated comb actuation, 215

interfacial cracks, after reliability tests, 200, 201f interfacial microstructure: of joint bonding, 198f of seal joints, 200, 201f interference signal, from mirror package, 429f interferometric modulator displays (IMOD), 2 intermediate bonding layer (IBL), 184, 184f solder-based, 175–176 intermetallic compounds (IMCs), 56, 115, 118, 119, 176, 182 ion milling etching, 163 ion-bombardment etching, 163 isothermal fatigue tests, 309–313 capacitance-gauge calibration curve, 312f hysteresis loops, 313f load drop curves, 312f results, 312–313, 313f sample preparation of, 309 of solder sealing ring, 300 test setup/procedures, 309–312 isotropic geometries, 159

J Japanese patents, on MEMS packaging, 21–27 joint bonding, interfacial microstructure of, 198f Joule heating effect, 215 junction temperature, of Cu-filled TSV chips, 64f, 65f, 67f

K KGDs. See known good dies Knowles Electronics, 5 known good dies (KGDs), 50 KOH. See potassium hydroxide Korean Aerospace Research Institute, 251 Kovar case, 170

L lab-on-a-chip (LOC), 354, 355 land-grid array (LGA), 279 large chips, 50 larger volume expansion, 216 large-scale optical switch packages, 275 large-scale optical switches, 233–237 laser ablation, 126 laser breading, 126 laser machining, MEMS cap wafer by, 83f

Index laser source, detected by screen, 406f laser welding, 340 lateral electrical feedthrough, 3D MEMS packaging: assembly process for, 73f, 75f wire-bonding with, 68f lead exemptions, RoHS, 135, 136, 137, 138 lead zirconate titanate (PZT), 220 actuators/mirror, 257f layer, 256, 257 3D VOA, 256 lead-free MEMS PBGA solder joints, reliability tests of, 146–148 lead-free solder, material properties of, 142–145 lead-free solder joints, 81 quality of, 146 reliability of, 138–149 lead-free 256-pin PBGA package, 147f, 148f leak rates, 200 Lexmark, 5 LGA. See land-grid array lift-off technique: Au-Sn solder, 145 handler wafer for, 458f, 461f light clipping loss, 283 light path, in probe, 414f light-to-heat conversion (LTHC) layer, 105, 105f linearity of attenuation, 252 liquid etchants, 167f lithography determined planar-layer structure, 240 Littman-Metcalf geometry, 262 LMP. See low-melting point load drop curves, isothermal fatigue tests, 312f loading conditions, of photonic package, 305 LOC. See lab-on-a-chip long plating time, Cu overburden from, 89f long-haul networks, 210 long-term room-temperature storage: of Ag-In, 187–188 bonded interface after, 189f Lorentz-force actuation, 219 low cost/simple packaging, 179 low outgassing rate, of vacuum package, 327 low temperature bonding, 112–113 fundamentals of, 112f schematic, 112f with solders, 112–113 low-cost solder microbumps, for 3D IC SiP, 52–58

lower substrate: of OCT endoscope, 405f for single-mode optical fiber, 404, 404f low-melting point (LMP), 182 low-pressure chemical vapor deposition (LPCVD), 176, 196 low-pressure glow-discharge plasmas, 163 low-temperature aging, bonded interface under, 190f low-temperature bonding, for MEMS packaging, 111–126 low-temperature C2C bonding, 112–121 low-temperature C2W bonding, 122–124 low-temperature processes, WLP using, 179f, 180f low-temperature solder, 112f low-temperature wafer bonding, 175 low-temperature wafer-level encapsulation, 178–182, 179f, 180f LPCVD. See low-pressure chemical vapor deposition L-shaped curved beam, 266f LTHC layer. See light-to-heat conversion layer Lucent Technology, 239, 240, 276, 277f, 278

M magnetic actuation, in optical MEMS applications, 219 MANs. See metropolitan-area networks manufacturability, optical MEMS applications, 264–268 MARS. See mechanical antireflection switch material properties, in structural modeling, 336t matrix controller chip (MCC), 297 maximum concentration value (MCV), 134 MCC. See matrix controller chip MCDM technology. See multichip direct mounting technology MCM technologies. See multiple-chip module technologies MCV. See maximum concentration value Measurement Specialties, Inc., 5 mechanical amplification, bent-beam structures for, 217 mechanical antireflection switch (MARS), 238 mechanical bending, shearing, and twisting tests, 140 mechanically disjointed material, 134

539

540

Index melting temperature, of composite solder, 118 membrane material: actuation force on, 382t, 383t permeability of, 381–384, 382t, 383t, 384t memory chip, 3D IC stacking, 52f MEMS. See microelectromechanical systems mercury exemptions, RoHS, 135 metal contact switches, design, 479 metal housing, of optical switches, 282f metal/ceramic packaging, MEMS device cost with, 341f metallization lines and probing pads, of piezoresistive stress sensors, 94f metallization/solder patterning, on TSV, 461f metropolitan-area networks (MANs), 210, 238 metropolitan-scale fiber rings, 225 MFL. See Micro Fabrication Laboratory Micro Fabrication Laboratory (MFL), 86 micro total analysis systems, 353 microactuators, 211 microbolometers, 3 microbumps, 50 microcracks, 192 microdisplays, 3 microelectromechanical systems (MEMS): commercial applications of, 2 emerging, 3 industrial application areas, 3 market forecast, 2–5 as MTM, 49 size of, 1 top 30 suppliers, 5 vacuum and, 327 value market forecast, 3f volume market forecast, 4f wafer, 68f microelectromechanical systems (MEMS)-based DGE filter, 239 microelectromechanical systems (MEMS)-based tunable laser, packaged, 263f microelectromechanical systems (MEMS) cap wafer: with cavity, 83f by KOH wet etch, 83f by laser machining, 83f TSV fabricated, 83f microelectromechanical systems (MEMS) chip, after SD dicing, 131f

microelectromechanical systems (MEMS) device: ASIC wafer bonding, 124f bonded on ASIC chip, 72f CMOS, 168 microsolder-bumped, 70 pick and placement of, 123f solder-bumped, 70 with TSV substrate, 69, 69f solder-bumped flip-chip, on ASIC chip, 69, 69f, 72f wafer, 67 wire bonded, on ASIC chip, 71f microelectromechanical systems (MEMS) device cost: with metal/ceramic packaging, 341f with wafer-level packaging, 341f microelectromechanical systems (MEMS) micromirror, optical probe with, 400f microelectromechanical systems (MEMS) motion analyzer, vacuum measurement using, 467–468, 467f, 468f microelectromechanical systems (MEMS) packaging, 5–6, 157 advanced, 67–68 Au-Sn solders for, 145 cap for, 6 challenges of, 157 enabling technologies for, 81–150 expense of, 6 functions of, 6 Japanese patents on, 21–27 lead-free solder-joint reliability, 138–149 low-temperature bonding for, 111–126 piezoresistive stress sensors for, 93–104 protection in, 158 TSVs for, 81–82 U.S. patents on, 6–21 worldwide patents on, 27–43 microelectromechanical systems (MEMS) technology: commercial success factors, 157 contributions to microoptical systems, 211 research on, 157 microelectromechanical systems (MEMS) VOA, 238, 239, 240 diffractive, 259f, 260 eight-channel, 264f retroflective, 249f with rotary-comb actuator, 248, 250f SEM photograph of, 241f with shutter, 267f surface-micromachined, 241f

Index microelectromechanical systems (MEMS) wafer, with TSV, 452–458, 453f, 454f, 455f, 456f, 457f microelectromechanical systems (MEMS) wafer dicing, 126–133 microelectromechanical systems (MEMS) wafer-level packaging, advanced, 157–203 microelectronics, bioapplications of, 354 microfabrication technology, 1 microfluidic cartridge: with 12 reservoirs, 388f self-contained, 371–377 microfluidic chip, for DNA/RNA extraction, 355f microfluidic components, 357–361 capillary-force passive valve in, 359f reagent injection port in, 359f substrate channels in, 359f microfluidic device, design of, 353 microfluidic package, 362–364 biochip attachment to, 365–366 biologic testing, 392–393 for DNA, 371f with fluid, 379f fluid testing, 391–392 with fluid/electric interconnections, 369f with fluidic chip, 358f PDMS, 364–370 with reservoirs, 372f without reservoirs, 366–370 rubber membrane and, 384f schematic, 357f with self-contained reservoirs, 371–374 substrate fabrication, 377–381, 378f microfluidics, 3, 353 capillary electrophoresis and, 353 cell sorting and, 353 DNA analysis and, 353 high through-put screening and, 353 PCR and, 353 protein analysis and, 353 microfuel cells, 3 micromachining, 158–178 micromechanical elements, 1 micromirror: in biosensor packaging, 401, 401f device, 185f, 226 fiber-alignment with, 428f microoptical systems, MEMS technology contributions to, 211 micro-opto-electromechanical systems (MOEMS), 1, 3 micropads, 112f microresistive heater, 181 microsolder-bumped, MEMS device, 70 microtips, 3

miniaturization, 353 mirror curvature: coupling efficiency and, 415–417, 416f, 417t tilted fold mirror and, 415 , 416f working distance and, 415 , 416f mirror device. See also micromirror electrical connection of, 423f on silicon substrate, 423f mirror package, interference signal from, 429f mirror-array package, 281f Mo substrate, time-history deflection of, 323f, 324f MOEMS. See micro-optoelectromechanical systems moisture-sensitivity tests, 140 molded surface-micromachining and bulk etch release (MOSBE) II process, 222 mirrors made by, 224f process flow of, 223f mole fraction, 120f molybdenum substrate, 299 Moore’s Law, 47–49 Moore’s observation of silicon integration, 48f of transistors on IC, 48f more than Moore (MTM), 47, 49 MEMS as, 49 morphotropic phase boundary (MPB), 220 MOSBE. See molded surfacemicromachining and bulk etch release II process mounting on dicing tape, stresses in wafers after, 98–101, 98f movement-translation micromechanism (MTM), 240 MPB. See morphotropic phase boundary MTM. See more than Moore; movement-translation micromechanism multichanneled variable optical attenuators (MVOAs), 264 histogram of, 265f multichip direct mounting (MCDM) technology, 280, 281f multi/demultiplexers (MUXs/ DEMUXs), 238 multiple-chip module (MCM) technologies, wafer-level chip capping and, 180–184 Murata, 5 MUXs/DEMUXs. See multi/ demultiplexers MVOAs. See multichanneled variable optical attenuators

541

542

Index

N Najafi, K., 181 nanoelectromechanical systems (NEMS), 1 Nanyang Technological University (NTU), 240, 251, 252 NDT. See nondestructive testing NEDO. See New Energy and Industrial Technology Development Organization NEMS. See nanoelectromechanical systems New Energy and Industrial Technology Development Organization (NEDO), 132 Ni layer, 53 non-BOSCH process, 84 nondestructive testing (NDT), 91 noneutectic composition, In-Ag system on, 183–194 nonlinear analyses, of 3D photonic switch, 306–309 NTU. See Nanyang Technological University numerical aperture, 406

O OADM. See optical add/dropmultiplexing OCT. See optical coherence tomography OEO. See optical-electrical-optical off-axis misalignment–based light-attenuation, 242 Official Journal of the EU, 134 Okamoto GNX 200, 91, 101 Olivettii-Jet, 5 Omron, 5 on-chip active alignment, 211 one-level packaging, for RF-MEMS, 525–526, 526f optical add/drop-multiplexing (OADM), 225 optical alignment accuracy, 211 optical back-reflection, 279, 281 optical bubble switch, 302f optical coherence tomography (OCT), 398–400 bioimaging, 397 with optical probes, 399f optical coherence tomography (OCT) endoscope, lower substrate of, 405f optical coherence tomography (OCT) system, 398 optical communication applications, VOA for, 237–261 optical cross-connect (OXC), 225, 233, 264

optical crosstalk, 279, 281 optical device, fully assembled, 298f optical efficiency testing, 431–432, 432f, 432t optical fibers, alignment of, 226 optical MEMS applications, 159, 327–351 actuation mechanisms in, 211–224 electrostatic actuation in, 212–217 electrostatic VOA and, 269–275 integrated micromachining processes in, 211–224 magnetic actuation in, 219 manufacturability, 264–268 optical switches and, 275–285 packaging of, 211, 261–285 piezoelectric actuation in, 219–221 reliability issues, 261–285 self-assembly, 264–268 small-scale optical switches in, 225–233 testing, 261–285 thermal actuation in, 215–219 optical MEMS packaging, 297–325 3D packaging, 297–301 optical MEMS systems, 209–286 telecommunication applications of, 210 optical model, of probe, 412–415 optical network topologies, 210 optical path, power detection on, 415t optical power, Gaussian distribution of, 407f optical probes: alignment of, 427 assembly of, 421–427 axial scanning test result of, 427–429, 428f, 429f configuration of, 404–406 housing, 425–427, 426f imaging, 429–430, 430f, 431f light path in, 414f with MEMS micromirror, 400f OCT with, 399f optical model of, 412–415 optical stimulation of, 414f testing, 427–432 optical properties/theories, 406–410 optical stimulation, 412–421 for beam size study, 413f for coupling efficiency, 413f of probe, 414f optical switches, 209, 225–237 dynamic reliability of, 283 large-scale, 233–237 metal housing of, 282f optical MEMS applications and, 275–285 performance parameters, 283 small-scale, 225–233 static reliability of, 283, 284f

Index optical switching technology, 2 optical-electrical-optical (OEO), 225 optical-loss mechanisms, for 2D optical switch mirrors, 283 optoelectronics hybrid package, 262f optofluidic technology, 261 orientation effect, 66 out-of-plane microstructures, 157 overlapping heat sources, 66 overload failure, 138 OXC. See optical cross-connect

P package deflection: calculation method of, 319f at cooling temperatures, 319f by finite-element method, 317–320 by Twyman-Green interferometry method, 314–317 package sealing techniques, 340 package-architecture transitions, Intel’s roadmap of, 52f parabolic micromirror pair, 252 parallel shift effect, 279 parallel-plate actuation, 215 passivation layers, 53 patents, Japanese, on MEMS packaging, 21–27 patents, U.S., on MEMS packaging, 6–21 patents, worldwide, on MEMS packaging, 27–43 path-length-dependent loss, 283 patterned-planar-layer structure, 240 PBDEs. See polybrominated diphyenyl ethers PBDs. See polybrominated diphyenyls PBGA. See plastic ball-grid array PCB. See printed circuit board PCR. See polymer chain reaction PCT. See pressure-cook test PDMS. See polydimethylsiloxane PECVD. See plasma-enhanced chemical vapor deposition perforated support wafer, 109f wafer device and, 110f PGA. See plastic grid array phosphosilicate glass (PSG), 168 photonic package: finite-element model of, 303f loading conditions of, 305 photonic switch: boundary-value problem of, 302–306 geometry of, 302 materials, 302–305 packaging elements, 299 photoresist lithography, 108, 109f photoresist patterns, 159 PID. See proportional-integral-derivative

piezoelectric actuation, in optical MEMS applications, 219–221 piezoelectric materials, 220 piezoresistive coefficients, 98 determined by the stress-sensor strip, 96f piezoresistive stress sensors, 81 calibration of, 95–98 design/fabrication of, 93–94 for MEMS packaging, 93–104 metallization lines and probing pads of, 94f rosette of, 94f pin valve: closed, 375f design, 374–375 open, 376f three level of sealing, 376f Pirani vacuum sensor, 178 planar lightwave circuit (PLC), 297 on silicon chip, 298f planar micropositioners, 218 planar tilted mirror, 3D VOAs of, 255f plasma deposition, dielectric isolation layer (SiO2) deposition by, 87f plasma etchants, 167f plasma generation, 172 plasma-assisted etching, 162 plasma-assisted wafer-bonding technologies, 172 plasma-enhanced chemical vapor deposition (PECVD), 86, 87f, 94, 102, 102f, 103f, 110 Plasm-Therm chamber, 111f plastic ball-grid array (PBGA), 146, 147f, 148f plastic grid array (PGA), 235 platen, independent biasing of, 84 PLC. See planar lightwave circuit PMMA. See poly(methyl methacrylate) point EDX analysis, 118t Poisson’s ratio, 302 polarization-dependent loss, 252 poly(methyl methacrylate) (PMMA), 170, 360–361 thermal compress bonding of, 386t polybrominated diphyenyl ethers (PBDEs), 133 polybrominated diphyenyls (PBDs), 133 polycrystalline silicone layer, 178 polydimethylsiloxane (PDMS), 360 layers, 364, 365, 366 microfluidic packages, 364–370 polydimethylsiloxane (PDMS) substrate: bonding, 367f DNA chip attached to, 368f upper/lower, 366f

543

544

Index polymer chain reaction (PCR), microfluidics and, 353 polymer chain reaction (PCR) amplification, for DNA extraction, 394 polymer chain reaction (PCR) thermal cycle conditions, for DNA extraction, 395t polymer passivation, 165 polymer sealing interface, wafer-level packaging approach using, 171f polymer-based bonding, 175 polymeric microfabrication methods, 362 polymer/metal coatings, 180f polypropylene to PMMA bonding process optimization of, 389t for reservoir/channel layer, 387–389, 387f polysilicon, 172 mirror, 214f plate, 215 shutter, 214f thermal actuators, 216–217 polysilicon-based surface micromachining, 221, 225 poly(methyl methacrylate) (PMMA) to PMMA bonding for channel layer, 385–387 side view, 386f polyvinylidene fluoride (PVDF), 220 pop-up microshutter, 268 pop-up mirror, 226f postbonding annealing additional, 188–194 effect of, 186–187 postbonding temperature stability, 175 potassium hydroxide (KOH), 160 potassium hydroxide (KOH)-etched mirror, 227 potassium hydroxide (KOH) wet etch advantages of, 84 MEMS cap wafer by, 83f power cycling tests, 140 pressure sensors, 3 pressure-cook test (PCT), 121, 140 primary/secondary flats, of and wafers for both n- and p-type doping, 161f printability test, 146 printed circuit board (PCB), 58 projectors, displays in, 2 proportional-integral-derivative (PID), 317 protection, in MEMS packaging, 158 protein analysis, microfluidics and, 353 PSG. See phosphosilicate glass

pull tests, 146 bond interface after, 116f of bonding couples, 114, 114f fracture surfaces after, 115 interface after, 116f PZT. See lead zirconate titanate

R radiofrequency microelectromechanical systems (RF-MEMS), 3 advanced packaging of, 515–528 chip capping of, 516–523, 517f one-level packaging for, 525–526, 526f reliability of, 526–528, 527f, 527t sealing method for, 518–523, 518f, 519f, 520f, 521f, 522f, 523f thin-film capping for, 523–525, 524f, 525f value market forecast, 4f volume market forecast, 5f zero-level packaging of, 515–525, 516f, 517f radiofrequency microelectromechanical systems (RF-MEMS) switches, 475–493, 486f classification, 476t design of, 475–484 fabrication of, 484–489, 487f, 488f, 489f mechanical design, 479–484 mechanical performance of, 489–492, 490f, 491f performance comparison of, 476t radiofrequency performance of, 489, 490f reliability of, 492 surface micromachining of, 484–488 radiofrequency microelectromechanical systems (RF-MEMS) tunable band-pass filters, 504–512 analog tuning of, 505–506, 505f, 506f digital tuning of, 506–512, 507f, 508f, 509f, 510f, 511f radiofrequency microelectromechanical systems (RF-MEMS) tunable capacitors, 495–504, 499f, 500f analog tuning of, 496–503 area tuning of, 502–503, 502f, 503f digital tuning of, 503–504, 503f, 504f gap tuning of, 497–501, 497f radius of curvature (ROC), 234 RDL. See redistribution layers

Index reaction zone, Cu/Sn-In solder interlayer, 115, 117f reactive-ion etching (RIE), 84, 163 reagent cross-mixing, 355 reagent injection port, in microfluidic components, 359f reagent protocol, for DNA/RNA extraction, 356t reagent valve, 370f reconfigurable optical add/drop multiplexers (ROADM), 210 redistribution layers (RDL), for TSVs, 82 reflection mirror, 185 reflection VOA, schematic of, 246f refractive-type VOA, 251 relative permittivity, 212 reliability engineering, of solder joints, 140–142, 141f reliability issues, optical MEMS applications, 261–285 reliability study, of bonded interface, 198, 198f reliability tests: definition of, 139 interfacial cracks after, 200, 201f of lead-free MEMS PBGA solder joints, 146–148 methods of, 140 objective of, 139 vacuum maintenance and, 469–471, 469f, 470f, 471f repeatability, 280 replication technologies: casting method and, 362–363 hot embossing and, 363 injection molding and, 363 reservoir membrane, design, 380f reservoir/channel layer, polypropylene to PMMA bonding for, 387–389, 387f reservoirs: with aluminum foil, 380f cylindrical, 373f design, 371–374 external actuator acting on, 372f microfluidic package with, 372f microfluidic package without, 366–370 modified design of, 381f reagent storage in, 370f self-contained, 371–374 of thermoplastic material, 392f residual gas analysis (RGA), 346 on vacuum sealing, 347t resistance measurement, 101 resistive element, on silicon chip, 299

Restriction of the Use of Certain Hazardous Substances (RoHS), 81, 297 cadmium exemptions, 136 deca-BDE exemption, 136 electronics industry compliance of, 138 in European Union, 133–134 exemptions in European Union, 133–134 hexavalent chromium exemptions, 136, 137 lead exemptions, 135, 136, 137, 138 mercury exemptions, 135 retroflective MEMS VOA, 249f retroflective mirrors, VOA with, 253f RF-MEMS. See radiofrequency microelectromechanical systems RGA. See residual gas analysis RIE. See reactive-ion etching ring-type networks, 225 ROADM. See reconfigurable optical add/drop multiplexers Robert Bosch, 5 ROC. See radius of curvature Rohms and Hass, strong-removal-rate slurry from, 91 RoHS. See Restriction of the Use of Certain Hazardous Substances rosette, of piezoresistive stress sensors, 94f rotary-comb actuator: DRIE-derived planar VOAs and, 248–251 MEMS VOA with, 248, 250f for VOA, 248–251 rubber membrane, microfluidic package and, 384f

S sacrificial oxide layer, 178 sacrificial polymer, thermal decomposition of, 179 sacrificial polysilicon, 259 sacrificial wafer: removal, 462–464, 462f, 463f, 464f wafer level package with, 450, 451f, 452f wafer level package without, 450– 452, 452f, 453f salt-atmosphere tests, 140 SAM. See scanning acoustic microscopy scan angle, 234 scanning acoustic microscopy (SAM), solder joint FA and, 141 scanning electron microscopy (SEM), solder joint FA and, 141

545

546

Index scanning mirrors, thermally driven, 218 scratch-drive actuator (SDA), 214, 214f SD OCT. See spectral-domain OCT SD technology. See stealth dicing technology SDA. See scratch-drive actuator seal joint, TEM/EDX analysis of, 198, 199f, 199t seal joints, interfacial microstructure of, 200, 201f seal ring, 125f cap wafer with, 124f sealed vacuum package, construction of, 328f sealing method, for RF-MEMS, 518– 523, 518f, 519f, 520f, 521f, 522f, 523f sealing ring, thermal fatigue life prediction of, 314 seam welding, 340 Seiko Epson, 5 self-assembled VOA, 266f self-assembly, optical MEMS applications, 264–268 self-assembly mechanism, 268f self-contained microfluidic cartridge, 371–377 self-contained reservoirs, 371–374 SEM. See scanning electron microscopy Sematech’s cost model of DRIE vs. laser, 83f for TSVs, 83, 83f sensitivity vs. vacuum, for bolometer, 330f sensor wafer, layers of, 102 series capacitive switch, 480f shear strength, 121If shear test, 146, 198 shear-creep- time-history, 307, 308f shear-stress time-history, 307, 308f shock (drop) tests, 140 shunt capacitive switch, 477f circuit of, 478f shutter/single-reflection mirror, DRIEderived planar VOAs and, 242–247 side-beam structure, 230 sidewall metallizations, 299 signal lines, 68f silicon (Si), 1 internal transformation of, 132 silicon base, 113f silicon cap, 113f silicon carbide, 160 silicon carrier, 52f silicon chip, 52f PLC on, 298f resistive element on, 299 well-bonded flat, 116f

silicon chip/silicon carrier scanning electron microscope image of, 57f underfill between, 57f silicon crystal orientation, 160 silicon dioxide deposition chamber, 111 silicon etching mechanism, 162 silicon integration, Moore’s observation of, 48f silicon micromachining, selection of, 163, 164t silicon microphones, 3 silicon microshutter, 239 silicon nitride, 160 silicon nitride film, 176 silicon optical bench (SiOB) for 3D micromirror, 422f fabrication, 421–422 silicon optical bench (SiOB) substrate 3D micromirror on, 424f GRIN lens on, 424f silicon pressure sensors, 2 silicon region, TEM image of, 117f silicon rubber, actuation force on, 383t Silicon Sensing Systems, 5 silicon substrate, mirror device on, 423f silicon-on-glass wafers, dicing of, 130–133, 132f silicon-on-insulator (SOI) wafers, 126 dicing of, 129, 131f silicon-on-silicon wafers, dicing of, 130 SiN film sealing, 176 single-crystal silicon layer, 178 single-element bolometer: time response, 348f vacuum package development, 348f single-mode optical fiber: in biosensor packaging, 401–403 lower substrate for, 404, 404f upper substrate for, 403, 403f single-reflection-type VOA, curves of wavelength-dependent loss for, 243f SiOB. See silicon optical bench SiP. See system-in-package SIR test. See surface-insulationresistance test slow chips, 50 small chips, 50 small-scale optical switches, 225–233 SMT. See surface mount technology SnAgCu solder bump, 92 SOI wafers. See silicon-on-insulator wafers solder joint, reliability engineering of, 140–142, 141f

Index solder joint FA: cross-sectioning and, 141 dye and pry and, 141 EDX and, 142 FIB and, 141 high-power microscopy and, 141 methods, 141–142 SAM and, 141 SEM and, 141 TAMI and, 142 TEM and, 142 visual inspection and, 141 x-ray inspection and, 141 XRD and, 142 solder joints, through-wafer vertical interconnects with, 174f solder microbumps, 53 solder microbumps/under-bumpmetallurgy (UBM) pads, distribution of, 53f solder sealing, 340 solder sealing ring, isothermal fatigue tests of, 300 solderability test, 146 solder-based intermediate-layer bonding, 175–176 solder-based thermocompression bonding, 169 solder-bumped, MEMS device, 70 with TSV substrate, 69, 69f solder-bumped flip-chip, MEMS device, on ASIC chip, 69f, 72f solder-bumped MEMS device flipchip, with vertical electrical feed-through TSV, 71f solders, low temperature bonding with, 112–113 solder-spreading test, 146 spectral-domain OCT (SD OCT), 399 spot size, 406 sputtering rate, 163 SS OCT. See swept-source OCT stack wafers, bonded 8-in diameter, 186f staggered heat sources, 66 on Cu-filled TSV chips, 67f Stark, B. H., 181 static actuated displacement, 214 static displacement, of comb actuator, 213 static reliability, of optical switches, 283, 284f stealth dicing (SD) technology, 126, 128f images of, 130f MEMS chip after, 131f principles of, 126–129, 127f processes of, 127–128 STMicroelectronics, 5

stress: compressive, 102 as a function of wafer thickness, 101 tensile, 102 thermomechanical, 104 vs. wafer thickness, 102f stress and applied force equation, 96 stress components, on thin wafers, 101t stress measurement locations, on stress-sensor wafer, 99f stress sensors resistances, as function of applied stress, 97f stresses in wafers: after mounting on dicing tape, 98–101, 98f after thinning, 101–104 stress-sensor strip, piezoresistive coefficients determined by the, 96f stress-sensor wafer: bow data/bending profiles of, 100f stress measurement locations on, 99f strong-removal-rate slurry, from Rohms and Hass, 91 structural modeling, material properties in, 336t STS. See Surface Technology Systems substrate assembly, 405 substrate bonding, PDMS, 367f substrate channels, in microfluidic components, 359f substrate fabrication, microfluidic package, 377–381, 378f SU-8, 170 sulfur hexafluoride (SF6), 84 support-wafer, bonded perforated, 111f support-wafer fabrication process flow, 109f support-wafer method, 110 surface micromachining, 221 of RF-MEMS switches, 484–488 surface mount technology (SMT), 113, 176 Surface Technology Systems (STS), 84 inductive-coupled plasma (ICP)based deep reactive ion etching system from, 84 surface-activation bonding, 172 surface-insulation-resistance (SIR) test, 146 surface-micromachined MEMS VOA, 241f surface-micromachined polycrystalline silicon substrate, 213 surface-micromachined polysilicon pop-up shutter, 226f surface-micromachined silicon shutter, 227f

547

548

Index swept-source OCT (SS OCT), 398–399 switch time, 280 switching time, 230 SYLGARD 184 silicone elastomer kit, 364 system-in-package (SiP), 49 with high input-output pin counts, 175 solutions, 158 thermal resistance of, 63f Systron Donner, 5

T Ta adhesion layer, 53 TAC. See Technical Adaptation Committee TAMI. See tomographic acoustic microimaging Tango System’s AXCECA chamber, 87, 87f tape expansion, 128f Taxi Instruments, 5 TCT. See thermal cycling test TEC. See thermal expansion coefficient Technical Adaptation Committee (TAC), 135 TECs. See thermoelectric coolers telecommunication applications, of optical MEMS systems, 210 Telecordia GR1209 regulation, 275 Telecordia GR1221 regulation, 272, 275 TEM. See transmission electron microscope TEM/EDX analysis, of seal joint, 198, 199f, 199t temperature cycling condition, 306f temperature cycling tests, 140 temperature maps, for chip thickness, 65f temperature stability, bolometer chip, 331 temperature stability measurement, of TECs, 333f temperature stabilization during cooling, of bolometer package, 335f temperature stabilization during heating, of bolometer package, 335f temperature-profiling test, 146 temporary bonding, 106–107 tensile creep-strain rate, 144, 144f tensile stress, 102 tensile test, 390–391, 390f, 391f test-die temperature, 333 tetramethyl ammonium hydroxide (TMAH), 160, 223, 261

thermal actuator: design of, 218 in optical MEMS applications, 215–219 VOA using, 271–275 thermal bimorph, 215 thermal compress bonding, of PMMA, 386t thermal cycling deflections, 300 thermal cycling test (TCT), 121, 147f thermal decomposition, of sacrificial polymer, 179 thermal expansion coefficient (TEC), 81, 102 thermal fatigue life prediction, of sealing ring, 314 thermal issues, 50, 51 thermal management, of 3D IC SiP with TSV, 58–67 thermal optimization, for bolometer package, 330–335 thermal performance, of 3D IC stacked TSV chips with nonuniform heat source, 63–67 with uniform heat source, 61–62, 61t thermal resistance of Cu-filled TSV chips, 64f, 67f of SiP, 63f thermal-bimorph actuator, 215 thermally activated slide lift-off approach, 107 thermocompression approach, 175 thermocompression bonding, 384–391 thermoelectric coolers (TECs), 297, 331 bolometer package with, 332, 332f die temperature stability with, 334f temperature stability measurement of, 333f thermomechanical stress, 104 thermoplastic material, reservoirs of, 392f thin-film capping, for RF-MEMS, 523–525, 524f, 525f thin-film technologies, 158–159 thinning, stresses in wafers after, 101–104 thin-wafer handling, 50, 81 wafer thinning and, 104–111 3D circuits, 50 3D IC integration, 47, 49 of copper-filled TSV chips, 58, 59f with WLP, 49 3D IC packaging roadmap, 51f 3D IC SiP, for low-cost solder microbumps, 52–58 3D IC SiP with TSV, thermal management of, 58–67, 59f 3D IC stacked TSV chips maximum junction temperature, 62f

Index 3D IC stacked TSV chips (Cont.): thermal performance of with nonuniform heat source, 63–67 with uniform heat source, 61–62, 61t 3D IC stacking, 50, 51, 52f 3D MEMS packaging, 49f designs of, 68f with lateral electrical feed-through, assembly process for, 73f, 75f with vertical electrical feed-through, assembly process for, 73f, 74f wire-bonding, with lateral electrical feedthrough, 68f 3D MEMS WLP: designs, 68–72 materials, 68–72 processes, 72–76 3D micromirror: SiOB for, 422f on SiOB substrate, 424f 3D optical switches, 233, 234 based on Z-configuration, 277, 278f simple configuration of, 277f 3D packaging, of optical MEMS packaging, 297–301 3D photonic switch, nonlinear analyses of, 306–309 3D VOAs, 254–258 collimating lens in, 256f optical microscope photograph of, 271f of planar tilted mirror, 255f PZT, 256 schematic, 256f 3M UV-Curable Liquid Adhesive LC-2201, 105 3M wafer support system, 104–105, 104f with glass supporting plate, 105, 105f process flow, 106f three-plate tunable capacitor, 501f through-silicon vias (TSVs), 50, 51, 52 ASIC wafer with, 91–92 cap wafer/cavity with, 93 copper electroplating in, 458f cost, 82 design software, 82 design technology for, 82 for MEMS packaging, 81–82 with MEMS wafer, 452–458, 453f, 454f, 455f, 456f, 457f metallization/solder patterning on, 461f quality inspection of, 91 RDL for, 82

through-silicon vias (TSVs) (Cont.): Sematech’s cost model of, 83, 83f via formation, 82–86 wafer fabrication process, 92f, 455–462 wafer warpage, 82 wafer yields of, 82 through-silicon vias (TSVs) fabricated, MEMS cap wafer, 83f through-silicon vias (TSVs) MEMS device solder bonded, on ASIC chip, 71f through-silicon vias (TSVs) substrate, microelectromechanical systems (MEMS) device, solder-bumped with, 69f through-wafer vertical interconnects, with solder joints, 174f Ti adhesion layer, 53 Ti barrier/adhesion layer and Cu seed layer, 87f by Alchimer’s electrografting, 88, 88f depositions of, 88 fabrication process parameters for, 88f Ti/Cu/Ni/Au UBM, bonded devices using, 197f Ti/Cu/Ni/Au UBM metallization vs. In-Sn solder, 196f tilted fold mirror, mirror curvature and, 415 , 416f time response, single-element bolometer, 348f time-history deflection, 307, 307f time-history stick and slide friction status, 325f of Mo substrate, 323f, 324f TMAH. See tetramethyl ammonium hydroxide tomographic acoustic microimaging (TAMI), solder joint FA and, 142 total analysis systems, 353 transistor structure, 112f transistors on IC, Moore’s observation of, 48f transmission electron microscope (TEM), 115 solder joint FA and, 142 transmission state, H-beam-driven optical switch in, 231f transverse resolution, 409 trench sidewalls, vapor-silica interface of, 299 trench-refilled polysilicon film, 223 TSVs. See through-silicon vias tunable filters, 210 tunable lasers, 210 25-W CO2 laser, 132

549

550

Index 2D optical switch, 232, 232f 2D optical switch mirrors, optical-loss mechanisms for, 283 two-axis mirror, 233 process flow, 236f with wafer-bonded electrostatic actuator, 235f two-plate tunable capacitor, 499f Twyman-Green interferometry method, 300 finite-element model, 315f measurement results, 317 package deflection by, 314–317 procedure, 316 sample preparation, 315 simulation results, 318f temperature conditions, 317, 317f test results, 318f test setup, 316, 316f

U UBM pads. See under-bumpmetallurgy pads Ulis, 5 ultrasonic agitation, handler wafer during, 460f ultraviolet curable liquid adhesive, 105 under-bump-metallurgy (UBM), 113, 145, 184 under-bump-metallurgy (UBM) layer, on germanium window, 344f under-bump-metallurgy (UBM) pads, 53 under-bump-metallurgy (UBM) pads/ solder microbumps, distribution of, 53f under-bump-metallurgy (UBM) rings, 196 underfill, between silicon chip/silicon carrier, 57f unsaturates, 165 upper substrate, for single-mode optical fiber, 403 upper/lower substrates assembly, 402f of PDMS, 366f U.S. patents, on MEMS packaging, 6–21 U-shaped thermal actuator, 216, 216f

V vacuum: MEMS and, 327 vs. warpage of germanium window, 339f vacuum maintenance, reliability testing and, 469–471, 469f, 470f, 471f

vacuum measurement: bolometer package, 346–350 using MEMS motion analyzer, 467–468, 467f, 468f vacuum package: of bolometer, 340–343 challenges of, 328–329 cross section of, 331f elements of, 327 hermeticity of, 327 for infrared bolometer, 327 low outgassing rate of, 327 outgassing study in, 346 requirements of, 328 single-element bolometer, 348f at wafer level, 341f vacuum permittivity, 212 vacuum sealing: RGA test on, 347f wafer level, 464–467, 465f, 466t valve, reagent, 370f van der Waals forces, 365 vapor etching, 162 vapor-phase sacrificial-layer etching, 222 vapor-silica interface, of trench sidewalls, 299 variable optical attenuators (VOA) dark-type, 244 early development work on, 238 electromagnetic actuation, 261 H-shaped beam-driven, 273 in-line, 244 for optical communication applications, 237–261 with retroflective mirrors, 253f rotary-comb actuator for, 248–251 self-assembled, 266f single-port, 237 using H-shaped beam actuator, 272f using thermal actuator, 271–275 using various mechanisms, 258–261 V-beam actuator, 229f V-beam electrothermal actuators, 253, 253f vernier-type latching mechanism, 260 vertical electrical feed-through, 3D MEMS packaging with, assembly process for, 73f, 74f, 75f, 76f vertical electrical feed-through TSV, solder-bumped MEMS device flip-chip with, 71f vertical interconnects, V-grooves with, 173f vertical-comb actuator, 235 with step height difference, 236f vertical-comb-driven two-axis mirror, bulk-micromachining process for, 236

Index V-groove mirror, 261 V-grooves: anisotropic wet-etched Si, 173 with vertical interconnects, 173f via corner rounding process, 85t via filling, 89–91 via formation, in TSVs, 82–86 via tapering process, 85t vibration tests, 140 visual inspection, solder joint FA and, 141 VOA. See variable optical attenuators void-free joints, 183 V-shaped beam actuator, 217, 217f V-shaped torsion springs, 235 VTI Technologies, 5

W W2W bonding. See wafer-to-wafer bonding wafer-bonded electrostatic actuator, two-axis mirror with, 235f wafer bonding, 110f, 340 experiment, 194 handler wafer for, 459f process flow, 110f technologies, 158–178 wafer bow, 102 wafer debonding, 110f wafer device, perforated support wafer and, 110f wafer fabrication process, of TSVs, 455–462 integration flow and, 92f wafer level: vacuum package at, 341f vacuum sealing, 464–467, 465f, 466t wafer level package: electric field distribution in, 440f electrical modeling and, 438 insertion loss in, 441f package structure and, 438–442, 442f process, 448–458, 449f requirements, 437–448 with sacrificial wafer, 450, 451f, 452f without sacrificial wafer, 450–452, 452f, 453f wafer separation process, 458–462 wafer thickness: vs. stress, 102f stress as a function of, 101 wafer thinning, 50, 81 thin-wafer handling and, 104–111 wafer warpage, of TSVs, 82 wafer yields, of TSVs, 82 wafer-based batch-type process, 181 WaferBOND, 106 Waferbond remover solution, 109

wafer-level chip capping, MCM technologies and, 180–184 wafer-level encapsulation, 176–182 high-temperature, 177–178, 177f low-temperature, 178–182, 179f, 180f wafer-level MEMS packaging, 158 wafer-level packaging (WLP), 47 with high-temperature processes, 177f with low-temperature processes, 179f, 180f MEMS device cost with, 341f using polymer sealing interface, 171f wafer-level 3D package, for accelerometer, 471–473, 472f, 472t, 473f wafer-to-wafer (W2W) Au-Sn solder bonding, 146 wafer-to-wafer (W2W) bonding, 51 schematic, 125f warpage of germanium window bolometer package and, 338t vs. vacuum, 339f Waste Electrical and Electronic Equipment (WEEE), 133 wavelength equalizers, 264 wavelength-dependent loss, 252 wavelength-dependent loss curves, for single-reflection-type VOA, 243f wavelength-division-multiplexing (WDM), 210, 224, 264 WDM. See wavelength-divisionmultiplexing WEEE. See Waste Electrical and Electronic Equipment weight fraction, 120f well-bonded flat silicon chip, 116f well-bonded flat silicon chip, wellbonded pattern chips and, 116f wet etchants, selection of, 163, 164t wet isotropic silicon etch solution, 159 wet thermal oxidation, dielectric isolation layer (SiO2) deposition by, 86f wetting balance test, 146 wire-bonding, 3D MEMS packaging, with lateral electrical feedthrough, 68f WLP. See wafer-level packaging working distance, mirror curvature and, 415 , 416f worldwide patents, on MEMS packaging, 27–43

X x-ray diffraction (XRD), 115 solder joint FA and, 142 x-ray inspection, solder joint FA and, 141

551

552

Index x-ray inspection test, 146 XRD. See x-ray diffraction

Y yield loss, 264 Yole Development, 2, 3 Young’s modulus, 144, 144f, 302

Z Z-configuration, 3D optical switches based on, 277, 278f zero-bias state, 244 zero-level packaging, of RF-MEMS, 515–525, 516f, 517f ZnO thin films, 220