Microvias: For Low Cost, High Density Interconnects

Source: Microvias

Chapter

1 Introduction to Microvia and WLCSP Technologies

1.1 Semiconductor Industry Update The semiconductor industry is firing on all cylinders. Worldwide semiconductor sales are predicted to grow by a combined annual growth rate (CAGR) of 16.2 percent from 2000 to 2004, reaching $316.2 billion as shown in Fig. 1.1. Sales remain strong across all product segments, including digital signal processors (DSPs), standard-cell applicationspecific integrated circuits (ASICs), dynamic random access memories (DRAMs), microprocessors, and flash and telecom analog chips. The applications driving booming chip demand are personal computers, networking equipment, and wireless communications. The networking hardware market will grow to $104 billion by 2004, while the worldwide number of broadband subscribers will climb to $61 billion during the same time frame. The wireless communications market will reach $132 billion by 2004, while the total number of cellular handsets (cell phones) shipped will soar to 1.4 billion units. The region of fastest growing equipment consumption is the Asia Pacific region, led by Taiwan and South Korea, which have consumed $6.8 billion and $3.4 billion worth of equipment, respectively, in 2000. The Asia Pacific region will surpass the Americas as the largest equipment consumer by 2001, while Europe and Japan will both approach the $10 billion mark by 2002. There are almost forty 12-in. semiconductor fabrications (FABs) in the world. Two-thirds of these FABs are located in the Asia Pacific region, led by Taiwan, Japan, and South Korea.

1

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Chapter One

Figure 1.1

Worldwide semiconductor revenue growth.

1.2 System-on-a-Chip (SOC) One of the 12-in. FABs’ future semiconductor integrated circuit (IC) products is system-on-a-chip (SOC), which contains diverse functions on a single, large, and complex chip. These chip designs and build cycles usually are long and require multiple design passes to complete. The advantages of SOC are performance, small system form factor, and potentially low system cost. The challenges of SOC are: (1) to deal with the cost of large ICs, the slowdown in the reduction of cost per transistor as a result of very low IC yields, and the very high wafer FAB costs that are estimated to be in the range of $3 to 5 billion; (2) to integrate the intellectual property from multiple, possibly independent sources, with attendant interoperability, integration, and liability hurdles; and (3) to meet the mixed-signal requirements of future products, mixed technology systems, design issues, and limitation of on-chip performance that the industry faces for the first time. 1.3 System-on-a-Package (SOP) Based on the trends in the semiconductor industry, IC packaging1–12 can look forward to solid growth in the next few years, as shown in Table 1.1. It can be seen that chip scale packages (CSPs) have the largest percentage of CAGR, followed by the ball grid array (BGA) and the direct chip attach (DCA). Although there is no way to determine the exact

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Introduction to Microvia and WLCSP Technologies

Introduction to Microvia and WLCSP Technologies

TABLE 1.1

3

IC Package Forecast by Package Family

Package units (M)

1999

2000

2001

2002

DIP

9,413

8,880

8,838

7,974

2003 8,126

2004 8,165

−2.80%

CAGR

SO

40,163

43,803

49,167

52,123

58,793

63,477

9.59%

CC

3,430

3,570

3,851

3,890

4,092

4,276

4.51%

QFP

6,371

7,241

8,138

8,939

9,794

10,912

11.36%

PGA

244

268

294

333

397

428

11.90%

BGA

1,742

2,491

3,311

4,244

5,237

6,205

28.92%

CSP

1,180

2,402

3,762

5,395

7,516

9,908

53.04%

DCA

5,588

6,257

7,099

7,999

9,201

10,311

13.04%

Total

68,130

74,914

84,461

90,898

103,157

113,683

10.78%

total revenue of IC packaging, 10 percent of the total semiconductor revenue is a reasonable guess for the total IC packaging revenue. In that case, the total revenue of IC packaging should be $32 billion by 2004. For very high-volume and simple applications, SOC is particularly appropriate. However, for mixed technologies, lower volumes, and the integration of passives, SOP is the most appropriate. SOP is an attractive alternative to SOC design complexity and uses a lower-risk approach that permits the use of mature semiconductor and packaging technologies and standard chip-to-package attach methods. In the case of printed circuit board (PCB) design of multiple packaging technologies such as wire bonding, DCA, CSP, and BGA, it is often clear that designing and manufacturing a PCB containing all these diverse technologies can be expensive and time consuming. Moreover, in these designs, clusters of functionally related components can be identified as ideal candidates for functional subassemblies—a microprocessor and its buffer memory, an input/output (I/O) processor and interface chips. Packaging technology has now progressed to the point where these “systems” (subsystems) can be contained on an independent package called a few-chip module (FCM). This package can be assembled and tested separately, often resulting in saving of PCB space and cost, simplication of the substrate carrier (either organic or ceramic), and lower overall packaging costs. Electrical performance is enhanced through shorter interconnections of chip on SOP. The use of reference planes allows isolation of critical nets. Impedance/coupling levels can be controlled. Current design ground rules allow regions of very dense wiring to permit interconnection of high chip pin counts. Using glass-ceramic or organic materials offers the fastest propagation speeds and lowest line resis-

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Introduction to Microvia and WLCSP Technologies

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Chapter One

tances. The close physical proximity of the components mounted on SOP can minimize operating temperature deltas and permit thermal tracking, improving system performance. Use of an FCM allows designers to optimize that set of components for performance through functional subsystem testing prior to PCB assembly, allowing simplification of board test. The compacting of several electrical functions into SOP usually leads to some thermal challenges. Unless power and airflow levels are such that no heat management is necessary, the package components will have their own unique solutions. On simple two (or three)-chip SOPs, separate heat spreaders can be attached to each chip, depending on its power level. If space permits, an advanced thermal compound can be dispensed onto each component and a full module cap can be used. The differing expansion rates of each element in the SOP demand mechanical isolation for thermal management. Often, common heat sinking approaches can be used with SOP to minimize the number and handing of individual thermal solutions. Both direct lid attachment (DLA) and thermal paste solutions can be used when components are closely spaced; individual applications will require differing solutions. 1.4 Microvia and Wafer-Level Chip-Scale Package (WLCSP) As mentioned earlier, CSP will have the largest percentage of CAGR in the future of IC packaging. WLCSP is not only one of the CSPs, but the real CSP. Also, WLCSP is considered potentially the most cost-effective and reliable package. There are more than 30 different types of WLCSP reported in the literature, and their advantages and disadvantages have already been discussed.1–4 Just like many other new technologies, however, WLCSP still faces many critical issues (only solder-bumped WLCSP will be considered13–30): ■

The infrastructure of WLCSP is not well established.

■

The standard of WLCSP is not well established.

■

WLCSP expertise is not commonly available.

■

Bare wafer is not commonly available.

■

Bare wafer handling is delicate.

■

The Cost for poor-yield IC wafers is high.

■

Wafer bumping is still too costly.

■

There is a high cost for low wafer-bumping yield, especially for highcost dies.

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■

Wafer-level redistribution is still too costly.

■

There is a high cost for low wafer-level redistribution yield, especially for high-cost dies.

■

Troubles can occur with system makers if the die shrinks.

■

Test at speed and burn-in at high temperature on a wafer are difficult.

■

Single-point touch-up on the wafer is difficult.

■

PCB assembly of WLCSP is difficult.

■

Solder joint reliability is critical.

■

Microvia build-up PCB affects WLCSP solder joint reliability.

■

Alpha particle emission occurs through the lead-bearing solder on WLCSP.

■

Lead-free solder regulations have an impact on WLCSP.

■

Who should do the WLCSP? IC foundries or bump houses?

■

What are the cost-effective and reliable WLCSPs and for what IC devices?

■

How large is the WLCSP market?

■

What is the life cycle of WLCSP?

One of the unique features of most WLCSPs is the use of a metal layer to redistribute the very fine-pitch peripheral-arrayed pads on the chip to much larger-pitch area-arrayed pads with much taller solder joints on the PCB or substrate, as shown in Figs. 1.2 through 1.5. Figure 1.2 shows the wafer-level redistribution. Figure 1.3 shows a cross section of the redistribution. Figure 1.4 shows a typical cross section of the WLCSP assembled on a PCB, and Fig. 1.5 shows the cross section of the WLCSP-PCB assembly in more detail. In this book a few new solder-bumped flip-chip WLCSPs will be discussed in Chap. 10. Also, solder developments for the next-generation high-density interconnects will be presented in Chap. 9. In general, with WLCSPs, the underfill encapsulant may not be necessary (as shown in Fig. 1.4) and the demands on the PCB or substrate are relaxed. Since there is no underfill for most of the WLCSP assemblies, solder joint reliability becomes one of the most critical issues. Chapter 12 will address the solder joint reliability issues. A few new and high-throughput processes for assembling WLCSPs on PCB or substrate will be discussed in Chap. 11. For solder-bumped flip chip on low-cost substrate or PCB applications, even with wafer-level pad redistribution (from peripheral array to area array) to relax the pressure on PCB or substrate, in many cases

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Chapter One

Figure 1.2

Wafer-level redistribution on a peripheral-arrayed

chip.

one to two or even three to four build-up layers with microvias are needed to fan out the circuitry. Chapters 3 through 7 will present, respectively, five different methods of forming the microvias, namely mechanical numerical control (NC) drilling, laser drilling, photo defining, etching, and conductive-material fill. A few very special and novel microvia build-up substrates for solder-bumped flip chip in packages are discussed in Chap. 8. Some necessary fundamental knowledge for making the conventional PCB or substrate is presented in Chap. 2. In this chapter, microvia build-up PCBs or substrates will be briefly discussed. However, since packaging cost is the most important issue, the WLCSP costs will be discussed first.

A typical cross section of the wafer-level redistributed chip.

Figure 1.3

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Figure 1.4

7

PCB assembly of the WLCSP.

1.5 WLCSP Costs Since 100 percent perfect wafers cannot be made at high volume today, the true IC chip yield YT plays the most important role in cost analysis. Also, the physical possible number of undamaged chips Nc stepped from a wafer is needed for cost analysis, since (YTNc) is the number of truly good dies on a wafer. Nc is given by1, 2, 16

Figure 1.5

PCB assembly of the WLCSP (enlarged view).

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Chapter One

[φ − (1 + θ)兹A/θ 苶]2 Nc = π ᎏᎏᎏ 4A

(1.1)

A = xy

(1.2)

x θ=ᎏ ≥1 y

(1.3)

where

and

In Eq. (1.1) through (1.3), x and y are the dimensions of a rectangular chip (in mm), with x no less than y; θ is the ratio between x and y; φ is the wafer diameter (mm); and A is the area of the chip (in mm2). For example, for a 200-mm wafer with A = 10 × 10 = 100 mm2, then Nc ∼ 255 chips. 1.5.1 Wafer redistribution costs

Wafer-level redistribution is the heart of the WLCSPs, since only a handful of companies have the area-arrayed IC technology. The cost of wafer-level redistribution is affected by the true yield YT of the IC chip, the wafer-level redistribution yield YR , and the good die cost CD. The actual wafer-level redistribution cost per wafer CR is CR = CWR + (1 − YR)YTNcCD

(1.4)

where CWR is the wafer-level redistribution cost per wafer (ranging from $50 to $200), YR is the wafer-level redistribution yield per wafer, CD is the good die cost, Nc is given in Eq. (1.1), and YT is the true IC chip yield after at-speed/burn-in system tests. Again, it can be seen that the actual wafer-level redistribution cost per wafer depends not only on the wafer-level redistribution cost per wafer but also on the true IC chip yield per wafer, wafer-level redistribution yield per wafer, and good die cost. Wafer-level redistribution yield YR plays a very important role in WLCSP. The wafer-level redistribution yield loss (1 − YR) could be due to: 1. More process steps 2. Wafer breakage 3. Wafer warping

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4. Process defects such as spots of contamination or irregularities on the wafer surface 5. Mask defects such as spots, holes, inclusions, protrusions, breaks, and bridges 6. Feature size distortions 7. Pattern misregistration 8. Lack of resist adhesion 9. Overetching 10. Undercutting 11. Incomplete etching 12. Wrong materials It should be noted that rework of wafer-level redistribution is very difficult if not impossible. It has to be right the first time; otherwise, someone has to pay for it! The uses of Eq. (1.1) and (1.4) are shown in the following examples. If the die size of a 200-mm wafer is 100 mm2, true IC chip yield per wafer is 80 percent (since the importance of YT has been shown in Refs. 1, 2, and 28, only one value of YT will be considered in this study), wafer-level redistribution yield per wafer is 90 percent, wafer-level redistribution cost per wafer is $100, and die cost is $100 (e.g., microprocessors), then from Eq. (1.1), Nc = 255, and from Eq. (1.4), the actual wafer-level redistribution cost per wafer is $2140. For the same size of wafer, if the die cost is $5 (e.g., memory devices), then the actual waferlevel redistribution cost per wafer is $202. It is noted that for both cases the actual wafer-level redistribution cost per wafer is much higher than the wafer-level redistribution cost (CWR = $100)! On the other hand, if the wafer-level redistribution yield is increased from 90 percent to 99 percent, then the actual cost for redistributing the microprocessor wafer is reduced from $2140 to $304 and for redistributing the memory wafer it is reduced from $202 to $110.2 (Table 1.2). Thus, wafer-level redistribution yield plays an important role in the cost of wafer-level redistribution and the wafer-level redistribution houses should strive to make YR > 99 percent, especially for expensive good dies. 1.5.2 Wafer bumping costs

Wafer bumping is the heart of solder-bumped WLCSPs. The cost of wafer bumping is affected by YT, CD, YR and the wafer-bumping yield YB. The actual wafer-bumping cost per wafer CB is CB = CWB + (1 − YB)YRYTNcCD

(1.5)

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99%

90%

90%

90%

$1956

$4096

$3876

$20.08

Wafer-level bumping yield

Actual wafer-level bumping cost

Total actual cost of WLCSP per wafer

Hidden cost of WLCSP per wafer

Actual cost of WLCSP per good die

$11.98

$2223.60

$2443.60

$303.60

90%

90%

$11.98

$2223.60

$2443.60

$2139.60

$304

$3.07

$405.96

$625.96

$321.96

$2.03

$193.80

$413.80

$211.80

$202

$1.62

$111.18

$1.62

$111.18

$331.18

90% $220.98

99%

$331.18

99%

99%

$1.18

$20.30

$240.30

$130.10

$110.20

$129.18

Number of physically possible dies on wafer

$2140

255

255

Wafer-level bumping cost

Actual wafer-level redistribution cost

$120

$120

Wafer-level redistribution cost

Wafer-level redistribution yield

80% $100

80% $100

IC chip yield

99%

$5

$100

Good die cost

99%

Memory device

Item

WLCSP Cost Analysis Microprocessor device

TABLE 1.2

Introduction to Microvia and WLCSP Technologies

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11

where CWB is the wafer-bumping cost per wafer (ranging from $25 to $250), YB is the wafer-bumping yield per wafer, YR is the wafer-level redistribution yield per wafer, CD is the good die cost, Nc is given in Eq. (1.1), and YT is the true IC chip yield after at-speed/burn-in system tests. Again, it can be seen that the actual wafer-bumping cost per wafer depends not only on the wafer-bumping cost per wafer but also on the true IC chip yield per wafer, wafer-bumping yield per wafer, good die cost, and wafer-level redistribution yield per wafer. Just like YR, wafer-bumping yield YB plays a very important role in WLCSP. The wafer-bumping yield loss (1 − YB) could be due to: 1. Wrong process 2. Different materials 3. Too tall or short of a bump height 4. Not enough shear strength 5. Uneven shear strength 6. Broken wafers or dies 7. Solder bridging 8. Damaged bumps 9. Missing bumps 10. Scratching of the wafer For the previous example, if the wafer-bumping yield per wafer is 90 percent and wafer-bumping cost per wafer is $120, then the actual wafer-bumping costs per (microprocessor) wafer are, respectively, $1956 if YR = 90 percent and $2139.60 if YR = 99 percent, and the actual wafer bumping costs per (the memory) wafer are, respectively, $211.80 if YR = 90 percent and $220.98 if YR = 99 percent (Table 1.2). Again, it should be noted that the actual wafer-bumping cost per wafer is much higher than the wafer-bumping cost (CWB = $120). On the other hand, if the wafer-bumping yield is increased from 90 percent to 99 percent, then the actual costs for bumping the microprocessors wafer are, respectively, $303.60 if YR = 90 percent and $321.96 if YR = 99 percent, and the actual costs for bumping the memory wafer are, respectively, $129.18 if YR = 90 percent and $130.10 if YR = 99 percent. Thus, wafer-bumping yield plays an important role in the cost of wafer bumping and the wafer-bumping houses should stride to make YBYR > 99 percent, especially for expensive good dies. If there is no wafer-level redistribution, then there is no wafer redistribution yield loss, i.e., YR = 1, and Eq. (1.5) degenerates to that shown in Refs. 1 and 2.

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Chapter One

1.5.3 Wafer redistribution and wafer-bumping costs

Based on the foregoing discussions, the total actual cost for solderbumping and wafer-level redistribution CBR becomes CBR = CWBR + (1 − YRYB)YTNcCD

(1.6)

CWBR = CWR + CWB

(1.7)

where

is the sum of wafer-level redistribution cost and wafer-bumping cost CWBR usually charged by the wafer-bumping houses. For our example, the total actual costs of the microprocessor WLCSP are: CBR = $4096 if YR = YB = 90 percent; CBR = $2443.60 if YR = 90 percent and YB = 99 percent or YR = 99 percent and YB = 90 percent; and CBR = $625.96 if YR = YB = 99 percent. The total actual costs of the memory WLCSP are: CBR = $413.80 if YR = YB = 90 percent; CBR = $331.18 if YR = 90 percent and YB = 99 percent or YR = 99 percent and YB = 90 percent; and CBR = $240.30 if YR = YB = 99 percent (Table 1.2). Thus (1) for both devices, the actual WLCSP costs are higher than the cost ($100 + $120 = $220) charged by the redistribution-bumping houses; (2) this is even more so for the more expensive dies; and (3) YR and YB play very important roles in WLCSP and YRYB > 99 percent is a must for WLCSP to be competitive. 1.5.4 WLCSP hidden costs

The hidden cost per wafer is defined as the difference between the actual wafer-bumping and wafer-level redistribution cost, and the waferbumping and wafer-level redistribution cost charged by the waferbumping houses. From Eq. (1.6), the hidden cost per wafer for solder-bumped WLCSP CH is given as CH = CBR − CWBR

(1.8)

CH = (1 − YRYB)YTNcCD

(1.9)

or

It can be seen that, if YR = YB = 1, then there is no hidden cost (CH = 0) in solder-bumped WLCSP, meaning the wafer-bumping houses are perfect in doing the wafer-level redistribution and wafer bumping. Unfortunately, they cannot and never will be perfect, which is what makes the costs of wafer-level redistribution and wafer bumping so expensive, especially for expensive good dies.

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For our example, the hidden costs of the microprocessor WLCSP are: CH = $3876 if YR = YB = 90 percent; CH = $2223.60 if YR = 90 percent and YB = 99 percent or YR = 99 percent and YB = 90 percent; and CH = $405.96 if YR = YB = 99 percent. The hidden costs of the memory WLCSP are: CH = $193.80 if YR = YB = 90 percent; CH = $111.18 if YR = 90 percent and YB = 99 percent or YR = 99 percent and YB = 90 percent; and CH = $20.30 if YR = YB = 99 percent (Table 1.2). The fact that someone has to pay for (or share) the hidden costs is one of the major reasons why solder-bumped WLCSP is not very popular today. 1.5.5 WLCSP cost per good die

The actual wafer-bumping and wafer-level redistribution cost per good die CBR/D can be determined by CBR/D = CBR/YTNc

(1.10)

CBR/D = CWBR/YTNc + (1 − YBYR)CD

(1.11)

or

For our example, the actual WLCSP costs per the good microprocessor die are: CBR/D = $20.08 if YR = YB = 90 percent; CBR/D = $11.98 if YR = 90 percent and YB = 99 percent or YR = 99 percent and YB = 90 percent; and CBR/D = $3.07 if YR = YB = 99 percent. The total actual WLCSP costs per the good memory die are: CBR/D = $2.03 if YR = YB = 90 percent; CBR/D = $1.62 if YR = 90 percent and YB = 99 percent or YR = 99 percent and YB = 90 percent; and CBR/D = $1.18 if YR = YB = 99 percent (Table 1.2). Comparing with the wire bonding technology, these costs are much too high for solder-bumped WLCSP to be competitive, unless it is compensated for by performance, density, and form factor. Thus, again, YRYB >> 99 percent is a must for WLCSP to be popular. 1.5.6 Wafer-level underfill costs

For some special applications, such as portable electronic products under drop (shock) and vibration kinds of operation conditions, underfills are needed for ensuring the solder joint reliability of WLCSPs. Recently, in order to increase throughput and reduce production time, the research in wafer-level underfill materials and process has been very active.20 For WLCSP, in this process, the underfill is deposited on the entire solder-bumped wafer prior to dicing. During surface-mount technology (SMT) assemblies, the singulated chip is processed as in standard flip chip reflow operations. The key difference is that the pre-underfilled (with build-in flux) solder-bumped chip will be reflowed and cured concurrently between the chip and the organic substrate.

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Chapter One

The actual wafer-level underfill cost per wafer CU can be determined by CU = CWU + (1 − YU)YBYRYTNcCD

(1.12)

where CWU is the wafer-level underfill cost per wafer and YU is the wafer-level underfill yield per wafer. The wafer-level underfill yield loss (1 − YU) could be due to: 1. More wafer process steps 2. Wrong process 3. Wrong materials 4. Dicing 5. Nonuniformity 6. Incompletely cured underfill 7. Damage to solder bumps 8. Breaking of the wafer 9. Scratching of the wafer 10. Too high a thermal expansion coefficient 11. Too low a modulus The actual wafer-level underfill cost per good die CU/D can be determined by CU/D = CWU/YTNc + (1 − YU)YBYRCD

(1.13)

Thus, from the cost point of view, wafer-level underfill is not a good idea and makes solder-bumped WLCSP even more expensive. It can be seen from the first term of the right side of Eq. (1.13) that the underfill costs of the good dies are increased because some of the expensive underfills are wasted on the bad dies. Also, the hidden cost of wafer-level underfill per good die is high and is shown in the second term of Eq. (1.13). It should be pointed out that, in most of the conventional solderbumped flip chip on low-cost substrate applications, the underfill operation is usually applied to the individual dies after the system test of the assemblies.1–5 The reasons are: (1) it is easy to rework; (2) underfill is needed for only the good dies; and (3) there is no chance to damage the very expensive wafer. Also, from the process point of view, waferlevel underfill will reduce the self-alignment characteristic (which is so unique) of solder-bumped flip chip technology.

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If there is no wafer-level pad redistribution operation, then the actual wafer-level underfill cost per wafer can be determined by CU = CWU + (1 − YU)YBYTNcCD

(1.14)

Also, the actual wafer-level underfill cost per good die CU/D without wafer-level pad redistribution can be determined by CU/D = CWU/YTNc + (1 − YU)YBCD

(1.15)

Again, from both cost and process points of view, wafer-level underfill is not a good idea for solder-bumped flip chip on low-cost substrates. 1.5.7 Summary

More than 20 different critical issues regarding WLCSP have been mentioned. The most important issue of WLCSP (cost) has been analyzed in terms of the true IC chip yield, wafer-level redistribution yield, wafer-bumping yield, wafer-level underfill yield, and die size and cost. Also, useful equations in terms of these parameters have been presented and demonstrated through examples. Some important results are summarized as follows. ■

IC chip yield YT plays the most important role in WLCSP. If YT is low for a particular IC device, then it is not cost effective to house the IC with WLCSP, unless it is compensated for by performance, density, and form factor.

■

Wafer-level redistribution yield YR plays the second most important role in WLCSP. Since this is the first postwafer processing after the IC FAB, the wafer-level redistribution houses should strive to make YR > 99 percent (99.9 percent is preferred). Otherwise, the subsequent steps will be made very expensive by wasting of the material and process on the damaged dies.

■

Wafer-bumping yield YB plays the third most important role in WLCSP. The wafer-bumping house should strive to make YRYB > 99 percent (99.9 percent is preferred) to minimize the hidden cost, since they cannot afford to damage the already redistributed good dies.

■

Based on cost and process points of view, wafer-level underfill is not a good idea for solder-bumped flip chip on low-cost substrates.

1.6 Microvia Microvias are the keys to making low-cost and high-density PCBs and substrates. In order to make cost-effective PCB and substrates, the

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Chapter One

sequential buildup (SBU) fabrication technique is a must. This is done by adding a minimum of one layer of dielectric to the double-sided or multilayer core. Non-through-hole microvias are selectively formed to reclaim real estate and are used to accommodate the fine I/O pitch and redistribute circuits from the chip to the internal layers of the PCB, reduce PCB layer count and size, and enhance electrical performance. By IPC’s definition, holes of 6 mils (0.15 mm) or less on PCBs and substrates are called microvias. There are many advantages of microvia:31–78 (1) it requires a much smaller pad, which saves the board size and weight; (2) more chips can be placed in less space or a smaller PCB, which results in a low cost; and (3) electrical performance improves as well, since the parasitic capacitance is increased due to the smaller via length and diameter and the inductance is reduced due to the shorter pathway created by the microvia compared to the plated through-hole (PTH).31–37 According to a recent study by TechSearch International, the market for microvia substrates will reach $1.6 billion this year. That number is expected to grow to $8.6 billion by 2005. Currently, 75 companies around the world are producing microvia substrates. Japan is the world leader, with more than 50 percent of the world’s microvia production. Europe and the Asia Pacific region come in second in microvia production. Most of the products that use microvia technology are mobile phones (Fig. 1.6), notebook computers, and other handheld products. The U.S. will not have high volume production until after 2000. The reason is that most U.S. companies are currently focusing on high-value applications like workstations, servers, and network systems. Table 1.3 shows the usage of microvias in different business sectors. It can be seen that the largest market is in personal communications such as the mobile phone (Fig. 1.6). Figures 1.7 through 1.10 show a few examples (by Intel and Mitsubishi) of using the microvia build-up substrates for solder-bumped flip chips, usually microprocessors and ASIC applications. Figure 1.11 shows a microvia build-up PCB with two thinfilm metal layers by X-LAM, which will be discussed in Chap. 8. 1.6.1 Categories of vias

Typical via hole diameters range from 50 to 300 µm and are divided into three categories. Blind vias. Blind vias are located on the outer layer of the top and bottom of the circuit board and are formed to a depth at which they make contact with the first inner layer. The depth of this hole usually does not exceed 1 aspect ratio (hole diameter).

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Figure 1.6 Mobile phone with microvia build-up PCB. (Courtesy of Samsung)

Buried vias. Buried vias are holes that are plated within the core of the circuit board without access to the surface on either side of the board. These holes are formed before the board is laminated. The innerlayer material has the holes created by a through-hole processing method. The inner layers may be stacked several layers high during this hole formation process. Through-hole vias. Through-hole vias are formed through the entire thickness of the board. These vias are used as interconnect or as mounting locations for components. Basically, there are five major processes for microvia formation: (1) NC drilling; (2) laser via fabrication including CO2 laser, yttrium aluminum garnet (YAG) laser, and Excimer laser, (3) photo-defined vias, wet or dry; (4) etch via fabrications, including chemical (wet) etching and plasma (dry) etching; and (5) conductive-ink-filled vias, wet or dry. In general, even though photo-defining and chemical and plasma etching processes can make microvias in very high throughput, laser drills can make finer vias. 1.6.2 Microvias made by mechanical NC drilling

Currently, NC drilling is the most common process for generating holes on the PCB. However, NC drilling is technically limited to hole sizes of

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Cisco, Lucent, Alcatel, Nortel, Sun, Ericsson, NEC, Schlumberger, Agilent, HP

Mainly North American and some European, with limited opportunity in Asia Pacific

Accelerating growth in largearea boards as multiple highleadcount ASICs drop to 1-mm pitch and below.

Players

Geography

Direction

Very rapid growth driven by both demand and conversion to CSP/microvia by majors. Cellphones will become smaller due to baseband and RF integration and despite multimode function.

Mainly Japan and Southeast Asia; now rapidly becoming global with Europe and U.S.

Samsung and all Japanese cellphone makers (Panasonic, NEC, Sharp, Fujitsu, Kyocera, etc.); Motorola, Nokia, and Ericsson (combined 67% of market and rapidly converting to microvia— 104 million units 1997)

$180 million → $970 million

$18 million → $450 million

Market size

Personal communications Cellphones, pagers, personal communications, handheld global positioning systems (GPSs), satellite phones

Workstations, servers, processor modules, transmission, switching, router boards, test equipment

Computing and data communications

Usage of Microvias in Different Business Sectors

Products

TABLE 1.3

Digital imaging

Steady growth in camcorders and cost reduction through integration. Digital cameras going from 2 million units to 8 million units per year in 2002, and converting from ceramic to microvia.

Mainly Japan, with Japan remaining dominant

JVC Victor, Sony, Panasonic, Kodak (9 million camcorders and 2 million digital cameras in 1997)

$125 million → $280 million

Camcorders, digital cameras, digital receivers

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Figure 1.7 Intel’s microprocessor supported by a microvia build-up substrate.

Figure 1.8

Schematic of Intel’s microvia build-up substrate.

Figure 1.9

Mitsubishi’s microvia build-up substrate.

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Chapter One

Mitsubishi’s solder-bumped flip chip plastic ball grid array (PBGA) package with microvias.

Figure 1.10

Figure 1.11

Schematic of X-LAM’s thin-film metal layer substrate.

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200 µm and up (not microvias). Although smaller holes may be possible, these would come at the cost of significant productivity (such as minimal stack height). In addition, the blind vias are virtually impossible where typical dielectric thickness is 50 µm or less.38 In general, mechanical drilling cannot make microvias. However, it should be pointed out that some special machines are being designed to drill very small vias. For example, Excellon Automation have been developing drilling machines that can drill vias as small as 4 mils (100 µm) in diameter. For more information on mechanical NC drilling, please read Chap. 3. 1.6.3 Microvias made by laser drilling

Laser drilling can be a single or multiple via generation process that replaces the existing mechanical drilling process. Laser drilling differs from mechanical drilling in that the focused beam used to create the holes can produce smaller holes than those produced by conventional drilling. One of the most important advantages of laser drilling is that it is compatible with many copper-clad or unclad dielectrics and reinforced or nonreinforced PCBs. Laser drilling can be used to create both blind vias and holes. The process follows standard multilayer and is capable of resolving smaller features. Low productivity is one of the weaknesses of laser drilling; that is, one beam produces one blind via at a time.31 Laserdrilled microvias have been reported by several authors,39–51 and a typical PCB including a blind via is shown in Fig. 1.12. Several laser processes have been developed to generate small via holes; these are categorized as Excimer laser, YAG laser, and CO2 laser. The CO2 lasers have significantly higher productivity for holes larger than 70 µm in diameter. They can ablate more than 15,000 (100 µm diameter) holes through 50-µm-thick dielectric in 1 min. In general,

Figure 1.12

laser.

Via (75 µm) on 45-µm resin by UV:YAG

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Chapter One

carbon dioxide laser is used to drill holes on the dielectric layer and not to drill holes on copper, because the visible wavelength (1060 nm) of CO2 is too large to have enough energy to penetrate the copper at high speed. Today, the companies that supply the CO2 laser drilling machines are Hitachi, Lumonics, Panasonic (Matsushita), Mitsubishi, and Sumitomo. On the other hand, the ultraviolet (UV):YAG laser, with smaller wavelengths (365 to 255 nm) and much higher energy, is used to drill holes on the copper and dielectric (the so-called imaging method) at a much lower speed. UV:YAG lasers have demonstrated great productivity through both dielectric and copper layers, but for both processes ablation time is proportional to hole diameter and neither process is therefore competitive above 100 µm diameter. Today, ESI, Excellon, Exotech, Hitachi, and Sumitomo supply the UV/Nd:YAG laser machines. Also, Hitachi and Lumonics of Canada now offer a combination of Nd:YAG/CO2 laser machines. The excimer laser has a wavelength of 248 nm with krypton fluoride (KrF) and of 193 nm with argon fluoride (ArF). Excimer lasers can generate holes smaller than 50 µm in diameter through dielectric or copper layers. Controlled-depth drilling is also possible, thus allowing blind vias to be created. The slow etch rate, however, makes this process impractical for microvia formation. Today, Litel, JPSA, and Tamarack supply UV:excimer machines, to which JPSA can add either T-CO2 or diamond CO2 laser heads. For more information about laser-drilled microvias, please read Chap. 4. 1.6.4 Photo-defined vias

In 1990, IBM at Yasu, Japan, commercially produced microvias using a modified liquid photoimageable dielectric (PID). Modern PID is either a liquid or dry film. For photovias with liquid photodielectric, the dielectric is curtain-coated and cured, microvias are exposed, and the dielectric is developed. Panel plating follows with patterning to create signal traces. For photovias with dry-film photodielectric, the dielectric is laminated, microvias are exposed, and the dielectric is developed. Panel plating follows with patterning to create signal traces.55 The equipment needed for photo-defined via technology includes exposure unit, developer, and wet process. The suppliers of exposure unit are Bacher, Byers, Colight, Csun, Dupont, Dynachem, Gyrex, HiTech, Mirmir, Morton, Olec, Optical Radiation, ORC, Peak Measuring, Tamarac, and Theimer. The suppliers of developer are Advanced Chemill Systems, ASI, Chemcut, Ciba-Geigy, Circuit Services, Danippon Screen, Glenbrook, James River, Lantronic, Microplate, Quan-

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tum, Rexham Graphics, and Technifax. The suppliers of wet process (develop-etch-strip) are ASI, Chemcut, Hollmuller, Lantronic, and Schmid. For more information about photo-defined microvias, please read Chap. 5. 1.6.5 Chemical (wet)- and plasma (dry)-etched vias

Microvias can be formed by various etching techniques. The most common etching technique is to use a microwave-gas plasma, which is a dry etching process. Wet etching by hot KOH has been used for polyimide films. Both methods are isotropic such that they etch inward while they etch down. On the positive side, these formation techniques involve mass via generation in that they form all vias at the same time without regard to number or diameter. Plasma etching and chemical etching can be extremely cost effective for generating high volumes of small holes in dielectric layers. The principle in this case is to create a mask, which defines the position and size of the holes. This may be achieved by using dry film to image and then etch a hole pattern in a copper layer, or simply by using the dry film as the etch mask by imaging and developing. In either case the process cost is derived by the number of holes in a given working area. All the holes are generated simultaneously, and the process time is dependent on how long it takes to erode or dissolve the unmasked dielectric. Plasma etching has the added benefit of removing organic contaminants, and with careful conditioning, the amount of slope (undercut) created in the hole can be minimized. Chemical etching is the lowest-cost process for generating small holes on dielectrics. Both plasma and chemical etching processes can create blind vias, usually using the target pad as a means of defining the bottom of the blind via.57–58 The dry etching process needs extra processes like plasma etching and copper thinning (etch-back) processes. Micro Via Hole (MVH) formation by gas-microwave plasma (GMP) has been promoted by Dyconex of Switzerland. Dyconex has sixteen licensees worldwide because it sells a basic plasma drill for $55,000, compared to a laser drill that costs from $500,000 and up or to a photoimaging facility that requires around $300,000. The plasma equipment can be found from Advanced Plasma Systems, Inc. or Plasma Etch Inc. For more information about etched microvias, please read Chap. 6. 1.6.6 Conductive-ink-filled vias

Conductive ink describes a single-layer dielectric with microvias formed by laser, photoimaging, or insulation displacement. A conduc-

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Chapter One

tive paste (or film) is used to fill the microvias and act as the conductive path between layers. Surface metallization may be accomplished either by laminating copper foil onto the dielectric surface or by chemical deposition. For more information about conductive-ink-filled microvias, please read Chap. 7. 1.6.7 Microvia production in Japan

Since more than half of the world’s microvia PCBs and substrates are made in Japan, it is interesting to note the status of some key manufacturers in this area. These are reported as follows. (See Table 1.4 for additional details.) Fujitsu Limited. Fujitsu’s FLD (Fujitsu Laminate and Deposit) buildup process is currently in production and utilizing photoimaging system. FLLD (Fujitsu Laminate with Laser via and Deposit) process is under development and utilizes a laser drilling system. The technology is capable of producing 50-µm copper lines with 50-µm spaces and 100-µm-diameter vias for packaging substrates. Fujitsu is changing from photovia to laser via for its next generation packaging substrates. Highly Accelerated Stress Test (HAST) and reliability test results are presented in Ref. 64. Hitachi Chemical Co. Hitachi has developed two types of PCBs, namely, HITAVIA Type 1 and Type 3 using metal clad B-stage insulation resin film (MCF). Type 1 is used for motherboards and liquid crystal display drivers; Type 3 is used for semiconductor packages such as PBGA. The interstitial via holes (IVHs) are formed using mechanically predrilled metal-clad film. A CO2 laser is used to etch the microvias. The technology is capable of producing 100-µm copper lines with 100-µm spaces for Type 1 and 50-µm lines with 50-µm spaces for Type 3. The size of vias can be 250 µm on 500-µm pads for both types. All passed the qualification tests.65 Ibiden. Ibiden has developed a double-sided four-layer build-up board using fully additive copper plating and photosensitive epoxy. This technology is capable of producing 75-µm lines with 75-µm spaces for motherboards and 35-µm copper lines with 35-µm spaces for packages. Using the photovia process, it is possible to make 150-µm-diameter via on 250-µm lands for motherboards and 80-µm-diameter via holes on 125-µm lands for packages.66 IBM at Yasu. The IBM (at Yasu) Surface Laminar Circuit (SLC) also uses liquid-dispensed photoimaged epoxy in the build-up layers on FR-4 or bismaleimide triazine (BT) substrates. The photo-sensitive epoxy

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TABLE 1.4

25

Microvia Build-up PCB and Substrate Suppliers

Company Amitec

Via formation method Thin film

Via/pad diameter (µm)

Line/space (µm)

Maximum number of multilayers

25/50

15/15

2–4

ASTI

Laser

25/125

35/35

16

Canon

Laser

150/300

75/75

3+core+3

Compaq

Laser

75/195

75/30

10

Daisho Denshi

Laser

100/300

75/75

8

D. T. Circuit

B2it

200/400

75/75

4+core+4

Fujitsu

Photovia Laser

80/130 50/100

40/40 35/35

6 3+core+3

Hitachi Cable

Laser

50/80

25/25

2

Hitachi Chemical

Laser

100/125

50/50

10

Ibiden (IBSS)

Photovia Laser

85/125 150/250

40/40 75/75

4-2-4 10

IBM (HPCC)

Laser

50/100

28/33

9

IBM (SLC)

Photovia

100/150

50/50

3+core+3

JCI

Laser

100/160

40/40

8

JVC

Laser

150/250

60/60

2+core+2

K&S (X-Lam)

Thin film

25/54

18/14

2-4

Kyocera/JME

Photovia

50/100

30/30

4-8-4

Matsushita

Laser

100/125

50/50

4+core+4

Mitsubishi

Laser

75/125

30/30

3+core+3

Multek

Photovia

75/150

75/75

8

NEC

Photovia

40/60

20/20

3+core+3

NTK

Photovia Laser

90/130 50/130

35/35 40/40

3+core+3 9

Samsung

Photovia with laser

150/200

50/50

3+core+3

Sheldahl

Laser

25/140

50/37.5

Shinko

Laser

50/110

45/45

3+core+3

2

SMI

Photovia

95/135

37/37

2+core+2

STP

Photovia

100/200

75/75

1+8+1

Toppan

Photovia Laser

80/130 100–125/300

40/40 75/75

3+core+3 —

W. L. Gore

Laser

50/87

25/25

9

The number before and after the core is the number of build-up layers.

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Chapter One

resin is exposed and developed to form the via hole. The via diameter can be 100 µm and the land diameter can also be 100 µm. The line width and space can be 38 µm. The flip chip attached on SLC board has passed reliability tests with 100°C delta temperature cycling and temperature/humidity/bias test.67–70 JVC. The Victor Company of Japan (JVC) has produced the Variously Interconnected Layers (VIL) type of build-up PCB by applying thermosetting material to insulation and by the laser processing of via holes through the mask imaging method. Lines and spaces of 100 µm have been produced. JVC has succeeded in making a skip via hole as small as 280 µm in diameter.71 Matsushita. Matsushita has developed a unique stacked type of substrate technology called ALIVH, which is discussed in Sec. 7.3.30–33 Laser ablation (currently CO2 laser) and Cu paste are used for buried holes. It is reported that Matsushita’s share of the Japanese cellular phone market has risen to 60 percent with the introduction of ALIVH substrates. The company’s conductor line and space resolution are 50 µm and 50 µm, respectively.72 Reliability data for ALIVH-CSP have been shown in Ref. 63. NEC. NEC Toyama has developed a high-density microvia (µV) PCB for advanced microelectronic packaging application. The more advanced technology can produce 50-µm copper lines with 50-µm spaces. The via diameter can be 50 µm and land diameter can be 150 µm. The via is formed by laser processing. Most of the samples pass reliability tests, although there are less than 3 percent fails on the interconnection reliability test, MIL-STD-107G (−65°C for 30 min to +125°C for 30 min) after 500 cycles.73 Toshiba. Toshiba has introduced a unique Buried Bump Interconnection Technology (B2it). Silver paste is used to form conductive bumps on copper foil. Conically shaped bumps can penetrate the insulator and form a conductive path through the prepreg. The conductive lines and spaces, currently 75 µm in width each, are being formed by subtractive processing using photoresist. The “via” (bump) diameter is 200 µm and the land diameter is 400 µm. These are now under mass production.74 Recently, Toshiba and Dai Nippon Printing Co., Ltd formed a new start-up company called D. T. Circuit Technology Co., Ltd for making the B2it PCB and substrate. A summary of the line width and space width capabilities of these eight Japanese microvia manufacturers is shown in Fig. 1.13. It can be seen that Ibiden can make the finest lines and spaces. Figure 1.14 is a

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Figure 1.13

27

Line/space width technologies for some Japanese companies.

summary of the microvia and pad diameter capabilities of the eight Japanese microvia manufacturers. The smallest via and pad can be manufactured by NEC Toyama Corporation. It should be pointed out that five (Hitachi, Ibiden, JVC, Matsushita, and Toshiba) of the eight Japanese companies have developed their own new materials for the microvia process and formation. Four

Figure 1.14

Via/pad diameter technologies for some Japanese companies.

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Chapter One

(Hitachi, JVC, Matsushita, and NEC) use laser drilling. Two (Ibiden and IBM-Yasu) use photoimaging, and Fujitsu is changing from photoimaging to laser drilling. Toshiba (D. T. Circuit) has changed from the conventional (drilling and plating) process to a new process. 1.6.8 Summary

In general, laser drilling can create the smallest holes. Photo-defined via technology has highest productivity. Laser drilling technology gains 70 percent of the microvia market because of its straightforward nature and compatibility with all kinds of materials (including clad laminates, copper-coated foil, and dielectrics). The photoimaging method is the second most popular technology used in making microvias. Japan is the leader in making microvias, and the U.S. is very well back. However, some U.S. companies are catching up. For example, Johnson Matthey is the largest supplier of microvias in North America. It has 10 laser drills (4 YAG to ablate copper for RCC processing and 6 CO2 units to remove dielectric). Johnson Matthey’s electronic materials division was sold to Allied Signal Electronic Materials unit in August 1999. Allied Signal sold its laminate systems business to Rutgers AG, based in Essen, Germany, in order to enter higher-margin specialty segments. 1.7 A Note on High-Speed and High-Density Interconnects In Ref. 77, IPC-2141 gives the equations for estimating the characteristic impedance for some very simple circuits. Since these are approximate formulas, very often they lead to great errors, especially for high-speed and high-density interconnects. For example, for the simplest case (surface microstrip) shown in Fig. 1.15, with T = 35 µm, H = 794 µm, W = 3300 µm, εr = 4.2, IPC-2141’s equation underpredicts the characteristic impedance by almost 30 percent. In this book, some useful design charts for the surface microstrip, differential edge-coupled surface microstrip, embedded microstrip, differential microstrip, embedded stripline, differential symmetrical broadside-coupled stripline, differential symmetrical edge-couple centered-embedded stripline, and surface microstrips are shown in Figs. 1.15 through 1.26. It should be noted that all the data to make the curves are determined (with εr = 4.2) from numerical simulations of the Maxwell equations and checked randomly with some well-known solutions such as those given in Ref. 78. In these charts, Z0 is the characteristic impedance and Zdiff ⬵ 2 × Z0o, where Z0o is the odd-mode impedance.

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Figure 1.15

29

Characteristic impedance of a surface microstrip (εr = 4.2).

Figure 1.16 Differential impedance of a differential edge-coupled surface microstrip (εr = 4.2).

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Chapter One

Figure 1.17 Differential impedance of a differential edge-coupled surface microstrip (εr = 4.2).

Figure 1.18

Characteristic impedance of a embedded microstrip (εr = 4.2).

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Figure 1.19 Differential impedance of a differential centered-embedded microstrip (εr = 4.2).

Differential impedance of a differential centered edge-coupled embedded microstrip (εr = 4.2).

Figure 1.20

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Chapter One

Figure 1.21

Characteristic impedance of an embedded stripline (εr = 4.2).

Figure 1.22 Differential impedance of a differential symmetrical broadsidecouple stripline (εr = 4.2).

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Figure 1.23 Differential impedance of a differential symmetrical embeddedcentered stripline (εr = 4.2).

Differential impedance of a differential symmetrical embeddedcentered stripline (εr = 4.2).

Figure 1.24

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Chapter One

Figure 1.25

Capacitance of surface microstrips (εr = 4.2).

Figure 1.26

Inductance of surface microstrips (εr = 4.2).

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1.8 References 1. Lau, J. H., Low-Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies, McGraw-Hill, New York, 2000. 2. Lau, J. H., and S.W.R. Lee, Chip Scale Package, Design, Materials, Process, Reliability, and Applications, McGraw-Hill, New York, 1999. 3. Lau, J. H., C. Wong, J. L. Prince, and W. Nakayama, Electronic Packaging, Design, Materials, Process, and Reliability, McGraw-Hill, New York, 1998. 4. Lau, J. H., and Y.-H. Pao, Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies, McGraw-Hill, New York, 1997. 5. Lau, J. H., Flip Chip Technologies, McGraw-Hill, New York, 1996. 6. Lau, J. H., Ball Grid Array Technology, McGraw-Hill, New York, 1995. 7. Lau, J. H., Chip on Board Technologies for Multichip Modules, Van Nostrand Reinhold, New York, 1994. 8. Lau, J. H., Handbook of Fine Pitch Surface Mount Technology, Van Nostrand Reinhold, New York, 1994. 9. Frear, D., H. Morgan, S. Burchett, and J. Lau, The Mechanics of Solder Alloy, Van Nostrand Reinhold, New York, 1994. 10. Lau, J. H., Thermal Stress and Strain in Microelectronics Packaging, Van Nostrand Reinhold, New York, 1993. 11. Lau, J. H., Handbook of Tape Automated Bonding, Van Nostrand Reinhold, New York, 1992. 12. Lau, J. H., Solder Joint Reliability, Theory and Applications, Van Nostrand Reinhold, New York, 1991. 13. Garrou, P., “Wafer Level Chip Scale Packaging (WL-CSP): An Overview,” IEEE Trans. Adv. Packaging, 23(2): 198–205, May 2000. 14. Nguyen, L., N. Kelkar, and H. Takiar, “A Manufacturing Perspective of Wafer Level CSP,” IEEE Proceedings of Electronic Components & Technology Conference, pp. 97–100, Las Vegas, NV, May 2000. 15. Topper, M., J. Auersperg, V. Glaw, K. Kaskoun, E. Prack, B. Keser, P. Coskina, D. Jager, D. Petter, O. Ehrmann, K. Samulewicz, C. Meinherz, S. Fehlberg, C. Karduck, and H. Reichl, “Fab Integrated Packaging (FIP): A New Concept for High Reliability Wafer-Level Chip Size Packaging,” IEEE Proceedings of Electronic Components & Technology Conference, pp. 74–80, Las Vegas, NV, May 2000. 16. Ahn, M., D. Lee, and S. Kang, “Optimal Structure of Wafer Level Package for the Electrical Performance,” IEEE Proceedings of Electronic Components & Technology Conference, pp. 530–534, Las Vegas, NV, May 2000. 17. Mirza, A. R., “One Micron Precision, Wafer-Level Aligned Bonding for Interconnect, MEMS and Packaging Applications,” IEEE Proceedings of Electronic Components & Technology Conference, pp. 676–680, Las Vegas, NV, May 2000. 18. Simon, J., and H. Reichl, “Board Level Reliability of a Waferlevel CSP using Stacked Solder Spheres and a Solder Support Structure (S3),” IEEE Proceedings of Electronic Components & Technology Conference, pp. 81–86, Las Vegas, NV, May 2000. 19. Teutsch, T., T. Oppert, E. Zakel, E. Klusmann, H. Meyer, R. Schulz, and J. Schulze, “Wafer Level CSP using Low Cost Electroless Redistribution Layer,” IEEE Proceedings of Electronic Components & Technology Conference, pp. 107–113, Las Vegas, NV, May 2000. 20. Tong, Q., B. Ma, E. Zhang, A. Savoca, L. Nguyen, C. Quentin, S. Luo, H. Li, L. Fan, and C. P. Wong, “Recent Advances on a Wafer-Level Flip Chip Packaging Process,” IEEE Proceedings of Electronic Components & Technology Conference, pp. 101–106, Las Vegas, NV, May 2000. 21. Lau, J. H., C. Chang, and S. W. Lee, “Solder Joint Crack Propagation Analysis of Wafer-Level Chip Scale Package on Printed Circuit Board Assemblies,” IEEE Proceedings of Electronic Components & Technology Conference, pp. 1360–1368, Las Vegas, NV, May 2000. 22. Lau, J. H., S. Pan, and C. Chang, “Nonlinear Fracture Mechanics Analysis of WaferLevel Chip Scale Package Solder Joints with Cracks,” Proceedings of IMAPS Microelectronics Conference, pp. 857–865, Boston, MA, September 2000.

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23. Lau, J. H., T. Chung, S. W. Lee, C. Chang, and C. Chen, “A Novel and Reliable WaferLevel Chip Scale Package (WLCSP),” Proceedings of SEMI Chip Scale International, pp. H 1–8, San Jose, CA, September 1999. 24. Jim, K. L., G. Faulkner, D. O’Brien, D. Edwards, and J. H. Lau, “Fabrication of Wafer Level Chip Scale Packaging for Optoelectronic Devices,” IEEE Proceedings of Electronic Components & Technology Conference, pp. 1145–1147, Las Vegas, NV, June 1999. 25. Lau, J. H., S. W. Lee, and C. Chang, “Solder Joint Reliability of Wafer Level Chip Scale Packages (WLCSP): A Time-Temperature-Dependent Creep Analysis,” ASME Trans., J. Electronic Packaging, 122(4): 311–316, December 2000. 26. Lau, J. H., “Cost Analysis: Solder Bumped Flip Chip Versus Wire Bonding,” IEEE Trans. Electronics Packaging Mfg., (23): 4–11, March 2000. 27. Lau, J. H., and C. Chang, “Overview of Microvia Technologies,” Circuit World, 26(2): 22–23, January 2000. 28. Lau, J. H., “Critical Issues of Wafer-Level Chip-Scale Package (WLCSP) with Emphasis on Cost Analysis and Solder Joint Reliability,” IEEE Proceedings of International Electronic Manufacturing Technology Symposium, pp. 33–46, San Jose, CA, October 2000. 29. Lau, J. H., S. Pan, and C. Chang, “Creep Analysis of Wafer Level Chip Scale Package (WLCSP) with 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints and Microvia BuildUp Printed Circuit Board,” in Packaging of Electronic and Photonic Devices, ASME Book No. HO1217, pp. 79–89, November 2000. 30. Lau, J. H., S. Pan, and C. Chang, “A New Thermal-Fatigue Life Prediction Model for Wafer Level Chip Scale Package (WLCSP) Solder Joints,” in Packaging of Electronic and Photonic Devices, ASME Book No. HO1217, pp. 91–101, November 2000. 31. Gonzalez, C. G., R. A. Wessel, and S. A. Padlewski, “Epoxy-Based Aqueous Processable Photo Dielectric Dry Film and Conductive ViaPlug for PCB Build-Up and IC Packaging,” IEEE Trans. Adv. Packaging, 22(3):385–390, August 1999. 32. Singer, A. T., “Microvia Cost Modeling,” Proceedings from IPC Works, p. S-14-2, Washington, DC, October 1997. 33. Burgess, L. W., and P. D. Madden, “Blind Vias in SMD Pads,” Printed Circuit Fabrication, 21(1): 28–29, January 1998. 34. Castro, A., “Chip Carrier Package Constructions Made Easier with Dry Film Photo Dielectric,” Proceedings from IPC Works, p. S01-5-1, Washington, DC, October 1997. 35. Thorne, J., “Using New Interconnection Technologies to Reduce Substrate Cost,” IPC EXPO ’98, p. S-10, Long Beach, CA, April 1998. 36. Nargi-Toth, K., and P. Gandhi, “Manufacturing Methodologies for High Density Interconnect Structures (HDIS),” CSI Technical Symposium, pp. 63–70, San Jose, CA, September 1998. 37. Nargi-Toth, K., “ITRI Microvia Technology Roadshow,” IPC EXPO ’99, p. S17-1, Long Beach, CA, March 1999. 38. Numakura, D. K., S. E. Dean, D. J. McKenney, and J. A. DiPalermo, “Micro Hole Generation Processes for HDI Flex Circuit,” HDI EXPO ’99, pp. 443–450, Mesa, AZ, August 1999. 39. Noddin, D. B., E. Swenson, and Y. Sun, “Solid State UV-LASER Technology for the Manufacture of High Performance Organic Modules,” Proceedings of 48th Electronic Components and Technology Conference, pp. 822–827, Seattle, WA, May 1998. 40. Cable, A., “Improvements in High Speed Microvia Formation Using Solid State Nd:YAG UV Lasers,” IPC EXPO ’97, p. S-2, San Jose, CA, March 1997. 41. Owen, M., “Production Experiences with CO2 and UV YAG Drilling,” IPC EXPO ’97, p. S7-3, San Jose, CA, March 1997. 42. Tessier, T. G. and J. Aday, “Casting Light on Recent Advancements in Laser Based MCM-L Processing,” Proceedings 1995 International Conference on Multichip Modules, pp. 6–13, Denver, CO, April 1995. 43. Illyefalvi-Vitez, Z., M. Ruszinko, and J. Pinkola, “Recent Advancements in MCM-L Imaging and Via Generation by Laser Direct Writing,” Proceedings of 48th Electronic Components and Technology Conference, pp. 144–150, Seattle, WA, May 1998. 44. Moser, D, “Sights Set on Small Holes? How to Get There with Lasers,” Printed Circuit Fabrication, 20–22, February 1997.

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45. Owen, M., E. Roelants, and J. Van Puymbroeck, “Laser Drilling of Blind Holes in FR4/Glass,” Circuit World, 24(1): 45–49, 1997. 46. Contini, H. S., “Machining Lasers Find Niches by Solving Very Small Problems,” Photonics Spectra, 116–118, November 1997. 47. Illyefalvi-Vitez, Z. and J. Pinkola, “Application of Laser Engraving for the Fabrication of Fine Resolution Printed Wiring Laminates for MCM-Ls,” Proceedings of 47th Electronic Components and Technology Conference, pp. 502–510, San Jose, CA, May 1997. 48. Kobayashi, K., N. Katagiri, and S. Koyama, “Development of a Build Up Package with High Density of Circuits for High Pin Count Flip Chip Application,” IPC Expo 99, pp. S01–4, Long Beach, CA, March 1999. 49. Burgess, L. W., and F. Pauri, “Optimizing BGA to PCB Interconnections Using MultiDepth Laser Drilled Blind Vias-in-Pad,” Circuit World, 25(2): 31–34, 1999. 50. Raman, S., J. H. Jeong, S. J. Kim, B. Sun, and K. Park, “Laser (UV) Microvia Application in Cellular Technology,” IPC EXPO ’99, p. S17-6, Long Beach, CA, March 1999. 51. Schaeffer, R. D., “Laser Microvia Drilling: Recent Advances,” CircuiTree, 12, 38–44, 1998. 52. Petefish, W. G., D. B. Noddin, and D. A. Hanson, “High Density Organic Flip Chip Package Substrate Technology,” Proceedings of 48th Electronic Components and Technology Conference, pp. 1089–1097, Seattle, WA, May 1998. 53. Young, T. and F. Polakovic, “Thermal Reliability of Laser Ablated Microvias and Standard Through-Hole Technologies,” IPC Expo 99, pp. S17–2, Long Beach, CA, March 1999. 54. Gaku, M., H. Kimbara, N. Ikeguchi, and Y. Kato, “CO2 Laser Drilling Technology for Glass Fabrics Base Copper Clad Laminate,” IPC Expo 99, pp. S17–3, Long Beach, CA, March 1999. 55. Estes, W. E., T. R. Overcash, S. Padlewski, B. D. Neve, E. B. Murray, R. E. Anderson, R. C. Mason, and J. P. Lonneville, W. L. Hamilton and M. Periyasamy, “Photodielectric Dry Films for Ultra High Density Packaging,” SMI Proceedings, pp. 47–53, San Jose, CA, September 1997. 56. McDermott, B. J., and S. Tryzbiak, “The Practical Application of Photo-Defined Micro-Via Technology,” SMI Proceedings, pp. 199–207, San Jose, CA, September 1997. 57. Reboredo, L., “Microvias: A Challenge for Wet Processes,” IPC Expo 99, pp. S12–1, Long Beach, CA, March 1999. 58. Schmidt, W., “High Performance Microvia PWB and MCM Applications,” IPC Expo 99, pp. S17–5, Long Beach, CA, March 1999. 59. Ho, I., “What’s Up with SBU Technology?” Printed Circuit Fabrication, 64–68, March 1997. 60. Felten, J. J., and S. A. Padlewski, “Electrically Conductive Via Plug Material for PWB Applications,” IPC EXPO ’97, p. S6-6, San Jose, CA, March 1997. 61. Wessel, R. A., J. F. Henderson, J. J. Felten, S. Padlewski, M. A. Saltzberg, P. Charest, J. L. Parker, and P. T. Miscikowski, “A New Approach to Fill Conductive Vias in PCBs,” Printed Circuit Fabrication, 42–45, November 1997. 62. Nishii, T., S. Nakamura, T. Takenaka, and S. Nakatani, “Performance of Any Layer IVH Structure Multi-Layered Printed Wiring Board,” Proceedings of 1995 Japan IEMT Symposium, pp. 93–96, Omiya, Japan, December 1995. 63. Itagaki, M., K. Amami, Y. Tomura, S. Yuhaku, Y. Ishimaru, Y. Bessho, K. Eda, and T. Ishida, “Packaging Properties of ALIVH-CSP using SBB Flip-Chip Bonding Technology,” IEEE Trans. Adv. Packaging, 22(3): 366–371, August 1999. 64. Miyazawa, Y., T. Shirotsuki, H. Sugai, and Y. Yoneda, “Highly Accelerated Stress Test and Reliability Analysis for Build-up Circuits,” 1998 International Symposium on Microelectronics, pp. 430–434, San Diego, CA, November 1998. 65. Arike, S, K. Otsuka, N. Urasaki, A. Nakaso, K. Shibata, K. Kobayashi, K. Tsuyama, K. Suzuki, and H. Nakayama, “PWB using Mechanically Pre-drilled Metal Clad Film for IVH and Build-up PWB with Laser Via Hole for Semiconductor Package Substrate,” 1998 International Symposium on Microelectronics, pp. 425–429, San Diego, CA, November 1998.

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66. Enomoto, R., M. Asai, and N. Hirose, “High Density MLB using Additive and Buildup Process,” 1998 International Symposium on Microelectronics, pp. 399–404, San Diego, CA, November 1998. 67. Tsukada, Y., and S. Tsuchida, “Surface Laminar Circuit, a Low Cost High Density Printed Circuit Board,” Proc. Surface Mount Int., 1: 537–542, August 1992. 68. Tsukada, Y., Y. Mashimoto, T. Nishio, and N. Mii, “Reliability and Stress Analysis of Encapsulated Flip Chip Joint on Epoxy Base Printed Circuit Board,” Proceedings of ASME/JSME Joint Conference on Electronic Packaging, vol. 2, pp. 827–835, San Jose, CA, September 1992. 69. Tsukada, Y., Y. Maeda, and K. Yamanaka, “A Novel Solution for MCM-L Utilizing Surface Laminar Circuit and Flip Chip Attach Technology,” Proceedings of 2nd International Conference on Multichip Modules,” pp. 252–259, Denver, CO, April 1993. 70. Tsukada, Y., “Solder Bumped Flip Chip Attach on SLC Board and Multichip Module,” in Chip on Board, Lau, J. H., ed., van Nostrand Reinhold, New York, pp. 410–443, 1994. 71. Segawa, K., “Build-Up PWB with Laser-Processed Via Holes ‘VIL’,” 1998 International Symposium on Microelectronics, 419–424, San Diego, CA, November 1998. 72. Kohl, P. A., C. S. Patel, and K. Martin, “Wafer-Level Batch Packaging and the Interface Between ICs and PWBs,” Chip Scale International 99, p. B-1, San Jose, CA, September 1999. 73. Maniwa, R., “Finer Micro-Via PWB by Laser and Additive Process,” 1998 International Symposium on Microelectronics, 413–418, San Diego, CA, November 1998. 74. Fukuoka, Y., T. Oguma, and Y. Tahara, “New High Density Substrates with Buried Bump Interconnection Technology (B2it)—Design Features of Electrical and Thermal Performances with the Actual Applications,” 1998 International Symposium on Microelectronics, pp. 405–412, San Diego, CA, November 1998. 75. Jimarez, M., L. Li, C. Tytran, C. Loveland, and J. Obrzut, “Technical Evaluation of a Near Chip Scale Size Flip Chip/Plastic Ball Grid Array Package,” Proceeding of IEEE ECTC, pp. 495–502, Seattle, WA, June 1998. 76. Mawer, A., K. Simmons, T. Burnette, and B. Oyler, “Assembly and Interconnect Reliability of BGA Assembled onto Blind Micro and Through-Hole Drilled Via in Pad,” Proceedings of SMI Conference, pp. 21–28, San Jose, CA, August 1998. 77. IPC-2141, Controlled Impedance Circuit Boards and High-Speed Logic Design, April 1996. 78. Wadel, B., Transmission Line Design Handbook, Artech House, 1991.

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Source: Microvias

Chapter

2 Conventional Printed Circuit Board Technologies

2.1 Introduction Modern electronic packaging has become very complex. Interconnections are pushed more into lower levels of packaging. The choice of which packaging technology to use is governed by many factors: cost, electrical requirements, thermal requirements, density requirements, and so on. Material also plays a very important role. All things considered, PCBs play very important roles in electronic packaging.1 Since the invention of printed circuit technology by Dr. Paul Eisner in 1936, several methods and processes have been developed for manufacturing PCBs of various types. Most of these have not changed significantly over the years. However, some specific trends continue to exert major influences on the types of PCBs required and the processes that create them: 1. Computers and portable telecommunications equipment require higher-frequency circuits, boards, and materials, and also use more functional components that generate considerable amounts of heat that need to be extracted. 2. Consumer products have incorporated digital products into their design, requiring more functionality at ever lower total cost. 3. Products for all uses continue to get smaller and more functional, driving the total circuit package itself to become more dense, causing the PCBs to evolve to meet these needs.

39

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These will be discussed in this chapter, along with the traditional board structures and processes. The terms printed circuit board, PCB, and board will be used synonymously. Also, the words laminate, substrate, and panel will be used interchangeably.

2.2 Types of Printed Circuit Boards 2.2.1 Basic PCB classifications

PCBs may be classified in many different ways according to their various attributes. One fundamental structure common to all of them is that they must provide electrical conductor paths that interconnect components to be mounted on them. There are two basic ways to form these conductors: 1. Subtractive. In the subtractive process, the unwanted portion of the copper foil on the base substrate is etched away, leaving the desired conductor pattern in place. 2. Additive. In the additive process, formation of the conductor pattern is accomplished by adding copper to a bare (no copper foil) substrate in the pattern and places desired. This can be done by plating copper, screening conductive paste, or laying down insulating wire onto the substrate on the predetermined conductor paths. The PCB classifications given in Fig. 2.1 take into consideration all these factors, i.e., fabrication processes as well as substrate materials. The use of Fig. 2.1 is as follows: ■

Column 1 shows the classification of PCBs by the nature of the substrate.

■

Column 2 shows the classification of PCBs by the way the conductor pattern is imaged.

■

Column 3 shows the classification of PCBs by their physical nature.

■

Column 4 shows the classification of PCBs by the method of conductor formation.

■

Column 5 shows the classification of PCBs by the number of conductor layers.

■

Column 6 shows the classification of PCBs by the existence or absence of PTHs.

■

Column 7 shows the classification of PCBs by production method.

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Conventional Printed Circuit Board Technologies

Conventional Printed Circuit Board Technologies

Figure 2.1

41

Classification of printed circuit boards.

2.2.2 Other classifications of PCBs

One of the major issues that has arisen with the ever higher speed and functionality of components used in computers and telecommunications is the availability of materials for the PCB substrate that are compatible with these product and process needs. This includes the stresses on substrate material created by more and longer exposure to soldering temperatures during the assembly process, as well as the need to match the coefficient of thermal expansion for components and substrate. The resultant search has found new materials, both organic and nonorganic based.

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Organic substrates consist of layers of paper impregnated with phenolic resin or layers of woven or nonwoven glass cloth impregnated with epoxy resin, polyimide, cyanate ester, BT resin, etc. The usage of these substrates depends on the physical characteristics required by the application of the PCB, such as operating temperature, frequency, or mechanical strength. Nonorganic substrates consist mainly of ceramic and metallic materials such as aluminum, soft iron, and copperinvar-copper. The usage of these substrates is usually dictated by the need for heat dissipation, except for the case of soft iron, which provides the flux path for flexible disk motor drives. PCBs may be classified into two other categories, graphical and discrete-wire boards, based on the way they are manufactured. A graphical PCB is the standard PCB and the type that is usually thought of when PCBs are discussed. In this case, the image of the master circuit pattern is formed photographically on a photosensitive material, such as treated glass plate or plastic film. The image is then transferred to the circuit board by screening or photoprinting the artwork generated from the master. Due to the speed and economy of making master artwork by laser plotters, this master can also be the working artwork. Discrete-wire boards do not involve an imaging process for the formation of signal conductors. Rather, conductors are formed directly onto the wiring board with insulated copper wire. Wire-wrap® and Multiwire® are the best known discrete-wire interconnection technologies. Because of the allowance of wire crossings, a single layer of wiring can match multiple conductor layers in the graphically produced boards, thus offering very high wiring density. However, the wiring process is sequential in nature and the productivity of discrete-wiring technology is not suitable for mass production. Despite this weakness, discrete-wiring boards are in use for some very high-density packaging applications. Another class of boards is made up of the rigid and flexible PCBs. Whereas boards are made of a variety of materials, flexible boards generally are made of polyester and polyimide bases. RigiFlex boards, a combination of rigid and flexible boards bonded together, have gained wide use in electronic packaging (see Fig. 2.2). Most RigiFlex boards are three-dimensional structures that have flexible parts connecting the rigid boards, which usually support components; this packaging is thus volumetrically efficient. 2.2.3 Graphically produced boards

The majority of boards produced in the world are graphically produced. There are three alternative types: single-sided boards, double-sided boards, and multilayer boards.

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Conventional Printed Circuit Board Technologies

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Figure 2.2

43

RigiFlex printed circuit board.

2.2.3.1 Single-sided boards (SSBs). Single-sided boards have circuitry on only one side of the board and are often referred to as print-and-etch boards because the etch resist is usually printed on by screen-printing techniques and the conductor pattern is then formed by chemically etching the exposed, and unwanted, copper foil. This method of board fabrication is generally used for low-cost, highvolume, and relatively low-functionality boards. In the Far East, for example, the majority of SSBs are made of paper-based substrates for lowest cost, with the most popular grade of paper-based laminate being

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XPC-FR, which is a flame-retardant phenolic material that is also highly punchable. In Europe, FR-2 grade paper laminate is the most popular substrate for SSBs because it emits less odor than XPC-FR when placed in high-voltage, high-temperature environments, such as inside a television set chassis. In the United States, CEM-1 material, which is a composite of paper and glass impregnated with epoxy resin, is the most popular substrate for SSBs. While not as low-cost as XPC-FR or FR-2, CEM-1 has gained popularity because of its mechanical strength and also because of the relative unavailability of paper phenolic laminates. 2.2.3.2 Double-sided boards (DBs). By definition, double-sided boards have circuitry on both sides. They can be classified into two categories: with and without through-hole metallization. The category of throughhole metallization can be further broken into two types: plated throughhole (PTH) and silver through-hole (STH).2 Metallization of holes by copper plating has been practiced since the mid-1950s. Because PCB substrate is an insulating material, and therefore nonconductive, holes must be metallized first before subsequent copper plating can take place. The usual metallization procedure is to catalyze the holes with palladium catalyst followed by electroless copper plating. Then, thicker plating is done by means of galvanic plating. Alternately, electroless plating can be used to plate all the way to the desired thickness, which is called additive plating. The biggest change in the manufacturing process of double-sided PTH boards, and also of multilayer boards (MLBs), is the use of direct metallization technologies. In this case the electroless copper process is eliminated. The hole wall is made conductive by palladium catalyst, carbon, or polymer conductive film, and then copper is deposited by galvanic plating. The elimination of electroless copper, in turn, allows the elimination of environmentally hazardous chemicals, such as formaldehyde and EDTA, which are two main components of electroless copper-plating solutions. STH boards are usually made of paper phenolic materials or composite epoxy paper and glass materials, such as CE-1 or CE-3. After double-sided copper-clad materials are etched to form conductor patterns on both sides of the panel, holes are formed by drilling. Then the panel is screened with silver-filled conductive paste. (Instead of silver, copper paste can also be used.) Since STH boards have a relatively high electrical resistance compared with PTH boards, the application of STH boards is limited. However, because of their economic advantage (the cost of STH boards is usually one-half to two-thirds that of functionally equivalent PTH boards), their application has spread to high-volume, low-cost products such as audio equipment, floppy disk controllers, car radios, remote controls, etc.

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2.2.3.3 Multilayer boards (MLBs). By definition, MLBs have three or more circuit layers (see Fig. 2.3). Main applications of MLBs used to be confined to sophisticated industrial electronic products. Now, however, they are the mainstream of all electronic devices, including consumer products such as portable video cameras, cellular phones, and audio discs. As personal computers and workstations become more powerful, mainframe computers and supercomputers are being replaced in many applications by these smaller machines. As a result, the use of highly sophisticated MLBs, which have layer counts over 70, is being reduced, but the technology to produce them is proven. At the other end of the layer-count spectrum, thin and high-density MLBs with layer counts between four and eight are mainstream. The drive toward thinner MLBs will continue and is made possible by the continuing concurrent advancement of materials and equipment to handle thin core materials. As PCBs have had to address the issues of higher speed, higher density, and the rise of surface-mount components that use both sides, the need to communicate between layers has increased dramatically. At the same time, the space available for vias has decreased, causing a continuing trend toward smaller holes, more holes on the board, and the decline of the use of holes that penetrate the entire board, which use space on all layers. As a result, the use of buried and blind vias has become a standard part of multilayer board technology, driven by the need for this increased package density (Fig. 2.3). One of the immediate issues that arise from these trends is the problems of drilling and the associated cost of this fabrication step. Printed circuit boards, which once were stacked three high on a drilling machine, must be drilled individually, and the number of holes per board has risen to accommodate the need for vias. This has caused a major problem for fabricators, who find that a lack of drilling capacity is creating a big demand on funds for additional machines, while

Figure 2.3

Cross section of multilayer board with buried via

holes.

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the cost of drilling continues to increase dramatically. Therefore, alternate methods for creating vias are being developed. These pressures will be ongoing, and therefore the process listed here, or some equivalent, will undoubtedly become more important as the drive toward miniaturization continues and drilling individual holes becomes less and less practical.

2.3 Base Materials 2.3.1 Copper-clad laminates

It is important to understand the types of copper-clad laminates that are available, how they are made, where they are used, and the advantages and disadvantages of each before selecting the material most suitable for the intended application. Many types of copper-clad materials are available (see Fig. 2.4). The copper-clad laminates most widely used in the manufacture of printed circuit boards, however, are FR-2, CEM-1, CEM-3, FR-4, FR-5, and GI. These are the materials that are primarily discussed in this section. The FR-2 laminates are composed of multiple plies of paper that have been impregnated with a flame-retardant phenolic resin. The major advantages of FR-2 laminates are their relative low cost and their good electrical and punching qualities. FR-2 is typically used in

Figure 2.4

PCB designations and materials.

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applications where tight dimensional stability is not required, such as in radios, calculators, toys, and television games. FR-3, the other all-paper-base laminate, is also made of multiple plies of paper that have been impregnated with an epoxy-resin binder. The FR-3 laminate has electrical and physical properties that are higher than those of the FR-2 but lower than those of epoxy laminates that have woven glass cloth as a reinforcement. FR-3 is used to manufacture printed circuits used in consumer products, computers, television sets, and communication equipment. CEM-1 is a composite material that has a paper core impregnated with epoxy resin. Woven glass cloth impregnated with the same resin covers the two surfaces. This construction allows the material to have punching properties similar to those of FR-2 and FR-3, with electrical and physical properties approaching those of FR-4. CEM-1 is used in smoke detectors, television sets, calculators, and automobiles as well as in industrial electronics. CEM-3, a composite of dissimilar core material, uses an epoxy-resinimpregnated nonwoven fiberglass core with epoxy-resin-impregnated woven glass cloth surface sheets. It is higher in cost than CEM-1, but it is more suitable for plated through-holes. CEM-3 is used in applications such as home computers, automobiles, and home entertainment products. FR-4 laminates are constructed on multiple plies of epoxy-resinimpregnated woven glass cloth. It is the most widely used material in the printed circuit board industry because its properties satisfy the electrical and mechanical needs of most applications. Its excellent electrical, physical, and thermal properties make it a well-suited material for high-technology applications. It is used in aerospace, communications, computers and peripherals, industrial controls, and automotive applications. FR-5 laminates are composed of multiple plies of woven glass cloth impregnated with mostly polyfunctional epoxy resin. The glass transition temperature Tg is typically 150 to 160°C, as compared with FR-4, which has a glass transition temperature of 125 to 135°C. FR-5 is used where higher heat resistance is needed than is attainable with FR-4, but not where the very high thermal properties of GI-type materials are needed. GI-type materials are composed of multiple plies of woven glass cloth impregnated with a polyimide resin. The materials have a glass transition temperature in excess of 200°C, which virtually eliminates “drill smear” caused by heat during the drilling process. It also exhibits excellent mechanical properties and z-axis dimensional stability at high temperatures. GI materials have a lower interlaminar bond strength

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Chapter Two

than the epoxy systems; therefore, care should be taken during drilling and routing. 2.3.2 Considerations in glass transition temperature Tg

Tg has become a measure of how well a laminate resin system resists softening from heat. When the Tg temperature is reached, the resin changes from its “glassy” state and causes changes in the laminate’s properties. Tg is not a measure of the resin’s melting point, but rather a point at which molecular bonds begin to weaken enough to cause a change in physical properties (dimensional stability, flexural strength, etc.). Its value is determined by the intersection of the two slopes of the temperature-property-change curve (Fig. 2.5a). FR-4 epoxy exhibits a Tg of 125 to 135°C and polyimide 260 to 300°C. Although the Tg value is a measure of the toughness of a material under heating, it is not meant for comparison purposes once the Tg

TE21

Property change

Tg Temperature

(a)

Property change

Resin x Resin y Tg(x)

Tg(y)

Temperature

(b)

(a) Determination of glass transition temperature Tg. (b) General features of Tg. Figure 2.5

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is exceeded. For example, materials with a higher Tg are desirable because they maintain their stability over a wider temperature range up to the Tg. However, once the Tg is exceeded, the material properties of a high-Tg resin could change much more rapidly than those of a material with a low Tg. At a higher temperature, the lower-Tg material may often exhibit superior properties (Fig. 2.5b). 2.3.3 Lamination process 2.3.3.1 Material preparation. The base raw material—paper, glass matte, woven glass cloth, quartz, or Kevlar®—is impregnated or coated with resin. The resin is then polymerized to a point suitable for storage and final pressing. A machine called a treater or coater is used for treating the material. First the material passes through a dip pan of resin, where it is impregnated, and then through a set of metering rollers (squeeze rollers) and a drying oven. The oven is air-circulating or infrared and can be up to 120 ft long. Most of the volatiles such as solvents in the resin are driven off in the oven, and the resin is polymerized to what is called a B-stage. This semicured material is also known as prepreg. The prepreg is dry and nontacky. The treater illustrated in Fig. 2.6 is a vertical treater that runs principally woven glass cloth; horizontal treaters impregnate mainly paper and glass matte. Rigid process control is applied during treating so that the ratio of resin to base material, the final thickness of the prepreg, and the degree of resin polymerization can be monitored. Beta-ray gauges may compare the raw material with the final semicured product and automatically adjust the metering rollers above the resin dip pan so that the proper

Figure 2.6

Features of the vertical tower processing system.

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Chapter Two

ratio of resin to base material is maintained. The degree of polymerization of the resin is controlled by the treater air temperature, the air velocity, and the speed at which the material passes through the treater. The prepreg material is usually stored in an area where the temperature and humidity are controlled below 21°C and 35 percent relative humidity (RH), respectively, until the time of the pressing operation. Each roll or stack of prepreg is tagged with the processing date and the test results for resin content, gel time, resin flow, cured thickness, and volatile content. 2.3.3.2 Copper inspection. Besides the base material and resin, the other principal component of copper-clad laminates is copper foil. Today, almost all copper is electrodeposited rather than rolled. Each roll of copper is inspected by the laminator for visual surface quality and pinholes, and a sample is taken for trial pressing. The trial pressing sample is tested for copper peel strength, solder blister resistance, copper oxidation after heat exposure, and general surface quality. The side of the foil to be pressed against the prepreg is treated with an alloy to improve adhesion of the copper to the laminate. The alloy is a proprietary coating, usually of zinc or brass, in a controlled ratio to enhance the chemical bond between the copper and the resin. 2.3.3.3 Laminate buildup. Most laminators build up their sheets in clean room facilities with filtered air-conditioned systems to control the temperature and humidity as well as to keep dust particles away from the copper and prepreg during buildup. Electrostatic attraction of dust particles to the treated material and copper before pressing is a source of contamination in the laminate and a source of pits and dents on the copper surface of the finished laminate. During the buildup operation, the copper foil is first laid against a large polished stainless steel press plate. Then a number of sheets of prepreg are laid on top of the copper. The number of layers depends on the desired thickness of the laminate and the characteristics of the prepreg material. Some of the art of laminating comes in balancing all of these variables to produce a final dense material to relatively close tolerances. The final sheet of copper foil is placed on top of the prepreg if the material is to have copper on both sides. If copper is desired on only one side of the laminate, a release film such as Tedlar® replaces one of the sheets of copper. 2.3.3.4 Laminate pressing. The press plates, with the material, are removed from the buildup room and stacked in a large, multiopening press. Several sheets are pressed into each press opening, with typical presses being capable of molding 80 sheets 36 × 48 in. to 250 sheets 48 × 144 in., 1⁄16 in. thick. The presses, which are hydraulic, are capable of developing pressure in excess of 1000 lb/in2. Steam is a typical heat source. It is released into the press platens until the platens reach the Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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uniform laminating temperature. The packs or books of material are then loaded into the press, and the desired pressure is applied so that the material is cured into a final homogeneous sheet. To ensure that all of the sheets in the pack or book receive the desired state of cure, thermocouples are placed in several sheets in the press. A timer automatically records time against a preset cure cycle. When the desired stage of cure is achieved, the steam is automatically cut off and cold water is pumped through the press platens until the material reaches approximately 27°C. The material is then removed from the press, and the edges are trimmed from the sheet to remove irregular resin flow areas. 2.3.3.5 Laminating quality control system. Statistical process control methods are used to verify that each step in the manufacturing process is controlled. Figure 2.7 outlines laminate traceability. Each press load is tested according to the appropriate sampling plan to ensure that the material will meet customer requirements. Each sheet is then identified as to manufacturer, appropriate specification, and load or lot number. Most manufacturers retain samples of material from each load for at least 1 year to enable them to effectively check any processing problems or questions that may result from the use of that lot in the field. Periodically, laminators are required to run a complete set of physical and electrical tests as set forth by the National Electrical Manufacturers Association (NEMA) or MIL-P-13949. 2.3.4 Grades and specifications

The grades and specifications of some standard laminates are presented in Tables 2.1 to 2.3. The most common method of designating copper-clad materials is described in MIL-P-13949 and illustrated in Fig. 2.8. As an example, GFN-0620-CN/CI-A-2-A means no coloring in flame-retardant glass-epoxy laminate, 0.062 in thick, 1⁄2-oz/ft2 copper, drum side out, on one side, and 1-oz/ft2 copper, drum side out, on the other side, Grade A pits and dents, Class 2 thickness tolerance, and Class A warp and twist.

Figure 2.7

Flow chart for laminate quality control.

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GP

GH

GI

FR-5

None

None

FR-6

G-11

None

CEM-3

GE

None

CEM-1

GF

PX

FR-3

FR-4

None

FR-2

G-10

None

XXXPC

Polyimide

Epoxy

Epoxy

Epoxy

Epoxy

Polyester

Epoxy

Epoxy

Epoxy

Phenolic

Phenolic

Glass

Glass

Glass

Glass

Glass

Glass matte

Glass matte

Paper-glass composite

Paper

Paper

Paper

Base

Military designation MIL-P-13949F

NEMA grade

Resin system

Standard Materials for Printed Circuit Boards

TABLE 2.1

Color

Translucent dark brown

Translucent

Translucent

Translucent

Translucent

Opaque white

Translucent

Opaque tan

Opaque cream

Opaque brown

Opaque brown

Description

Polyimide resin, glass laminate with high continuous operating temperature and high property retention at temperature, low z-dimensional expansion

High-temperature epoxy-glass with flame-resistant resin system with strength and electrical retention at elevated temperatures

High-temperature epoxy-glass with strength and electrical retention at elevated temperatures

Epoxy-glass with self-extinguishing resin system

Epoxy-glass, general purpose

Polyester, random glass fiber, flame-resistant, designed for low-capacitance or high-impact applications

Epoxy resin nonwoven glass core with woven glass surfaces, self-extinguishing, punchable with properties similar to FR-4

Epoxy resin paper core with glass on the laminate surface, self-extinguishing, economic fabrication of paper base, mechanical characteristics of glass

Epoxy resin, paper base with flame-resistant resin system, cold punching, and high insulation resistance

Phenolic paper, punchable, with flame-resistant (self-extinguishing) resin system

Phenolic paper with punchability at or above room temperature Conventional Printed Circuit Board Technologies

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52

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TABLE 2.2

53

Materials for High-Frequency Applications

NEMA grade

Military Designation MIL-P13949

GT

GX

Resin system

Base

Color

Description

GT

TFE

Glass

Opaque brown

Glass fabric base, PTFE (Teflon) resin, controlled dielectric constant

GX

TFE

Glass

Opaque brown

Glass fabric base, PTFE (Teflon) resin dielectric constant with closer controlled limits than GT

Polystyrene

Glass

Opaque white

Polystyrene cast-resin base for low-dissipation-factor applications

Cross-linked polystyrene

Glass

Opaque white

Polyethylene cast base, radiation cross-linked for low dissipation factor

The conditioning designations used to describe the environment in which tests were run are as follows: ■

Condition A. As received; no special conditioning

■

Condition C. Humidity conditioning

■

Condition D. Immersion conditioning in distilled water

■

Condition E. Temperature conditioning

■

Condition T. Test conditioning

Conditioning procedures are designated in accordance with the following: ■

First, a capital letter indicating the general condition of the specimen to be tested, i.e., as received or conditioned to humidity, immersion, or temperature.

■

A number indicating the duration of the conditioning, in hours, follows.

2.3.5 Mechanical properties of laminates

The principal characteristics usually required in the mechanical design of printed boards are outlined here. If a specific test is required, the test is listed under a particular heading. Whenever they are available, the minimum standards set forth in MIL-P-13949 or NEMA standards for industrial laminates are used.

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Military designation MIL-P-13949

None None None None

None None None None None

None

None None None

None

XXXPC FR-2 FR-3 FR-4

XXXPC FR-2 FR-3 FR-4 CEM-1

CEM-3

FR-2 FR-3 FR-4

FR-4

Epoxy

Phenolic Phenolic Epoxy

Epoxy

Phenolic Phenolic Phenolic Epoxy Epoxy

Phenolic Phenolic Phenolic Epoxy

Resin system Base

Color

Opaque brown Opaque brown Opaque brown Translucent

Adhesives

Glass

Translucent

Swell and etch

Paper Paper Glass, glasspaper composite

Sacrificial aluminum-clad

Opaque brown Opaque brown Opaque brown Translucent Opaque tan, blue, white Translucent

Seeded and coated Paper Paper Paper Glass Paper-glass composite Glass-matte composite

Paper Paper Paper Glass

Materials for Additive Circuit Processing

NEMA grade

TABLE 2.3

This laminate is used in the commercially available swell-and-etch additive process. The epoxy-glass laminate has a 0.0015-in.thick resin-rich surface and a specially designed surface for swell-and-etch chemicals.

These laminates are the patented sacrificial additive process. They are clad on two sides with a specially anodized aluminum foil. The sacrificial aluminum cladding makes the laminate surface acceptable for the additive process.

These laminates are used in the patented seeded and coated processes. They are seeded with a small percentage of the catalytic seeding agent dispersed throughout the resin system and are coated with a catalyzed adhesive.

These laminates are designed for use with additive processes using adhesive bonding techniques.

Description

Conventional Printed Circuit Board Technologies

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Figure 2.8

55

Designation of Cu-clad laminates.

2.3.5.1 Thickness tolerance. Nominal thicknesses and tolerances should be specified per MIL-P-13949. At least 90 percent of the area of a sheet should be within the tolerance given, and at no point should the thickness vary from the nominal by a value greater than 125 percent of the specified tolerance. Cut sheets less than 18 × 18 in. should meet the applicable thickness tolerance in 100 percent of the area of the sheet. Class of tolerance is as specified in the type designation. For nominal thicknesses not shown in this table, the tolerance for the next greater thickness shown applies. The nominal thicknesses include metal foil except in the case of microwave materials, which are without foil. (See Table 2.4.) 2.3.5.2

Flexural strength. Method: ASTM D 790. Unit of value: lb/in2.

This test is measure of the load that a beam will stand without fracture when supported at the ends and loaded in the center, as shown in Fig. 2.9. (See Table 2.5.) 2.3.5.3 Coefficient of thermal expansion (CTE). Method: ASTM D 696 (at 130°F). Unit of value: in./in./°F. The coefficient of thermal expansion (Table 2.6) is the change in length per unit of length per degree change in temperature. The coefficient may vary in different temperature ranges, so the temperature range must be specified.

TABLE 2.4

Nominal Thickness and Tolerance for Laminates (MIL-P-13949F) Class 1

Thickness (in. × 10−3)

PX paper base only

Glassreinforced

Class 2 glassreinforced

Class 3 glassreinforced

Class 4 for microwave application

0010 to 0045 0046 to 0065 0066 to 0120 0121 to 0199 0200 to 0309 0310 to 0409 0410 to 0659 0660 to 1009 1010 to 1409 1410 to 2400

— — — — — ⫾0045 ⫾0060 ⫾0075 ⫾0090 ⫾0120

⫾0010 ⫾0015 ⫾0020 ⫾0025 ⫾0030 ⫾0065 ⫾0075 ⫾0090 ⫾0120 ⫾0220

⫾00075 ⫾0010 ⫾0015 ⫾0020 ⫾0025 ⫾0040 ⫾0050 ⫾0070 ⫾0090 ⫾0120

⫾0005 ⫾00075 ⫾0010 ⫾0015 ⫾0020 ⫾0030 ⫾0030 ⫾0040 ⫾0050 ⫾0060

— — — — — ⫾002 ⫾002 ⫾002 ⫾0035 ⫾0040

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Chapter Two

Figure 2.9

Flexural strength test.

2.3.5.4 Water absorption. Unit of value: Percent water absorption is the ratio of weight of water absorbed by the material to the weight of the dry material. (See Table 2.7.) 2.3.5.5 Flammability. According to Underwriters Laboratories, materials tested for flammability are classified 94V-0, 94V-1, and 94V-2. For material flame ratings, see Table 2.8. Definitions of those classifications, as tested by the Underwriters Laboratories flammability procedure, are outlined as follows. ■

94V-0. Specimens must extinguish within 10 s after each flame application and a total combustion of less than 50 s after 10 flame applications. No samples are to drip flaming particles or have glowing combustion lasting beyond 30 s after the second flame test.

■

94V-1. Specimens must extinguish within 30 s after each flame application and a total combustion of less than 250 s after 10 flame applications. No samples are to drip flaming particles or have glowing combustion lasting beyond 60 s after the second flame test.

■

94V-2. Specimens must extinguish within 30 s after each flame application and a total combustion of less than 250 s after 10 flame applications. Samples may drip flame particles, burning briefly, and no specimen will have glowing combustion beyond 60 s after the second flame test.

TABLE 2.5

Flexural Strength (Condition A, Minimum Average psi) Material

Lengthwise

Crosswise

XXXPC FR-2 FR-3 FR-4 FR-5 FR-6 G-10 G-11 CEM-1 CEM-3 GT GX GI

12,000 12,000 20,000 60,000 60,000 15,000 60,000 60,000 35,000 40,000 15,000 15,000 50,000

10,500 10,500 16,000 50,000 50,000 15,000 50,000 50,000 28,000 32,000 10,000 10,000 40,000

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TABLE 2.6

57

Coefficient of Thermal Expansion

(CTE) Coefficient, × 10−5 Material

Lengthwise

Crosswise

Ordinary applications XXXP XXPC FR-2 FR-3 CEM-1 CEM-3 FR-6 G-10 FR-4 G-11 FR-5 GI

1.2 1.2 1.2 1.3 1.1 1.0 1.0 1.0 1.0 1.0 1.0 1.0

1.7 1.7 2.5 2.5 1.7 1.5 1.0 1.5 1.5 1.5 1.5 1.2

High-frequency applications GT GX Polystyrene Cross-linked polystyrene

TABLE 2.7

1.0 1.0 7.0 5.7

2.5 2.5 7.0 5.7

Water Absorption (Condition D 24/23)

Material

⁄32 in.

1

⁄16 in.

1

⁄32 in.

3

Ordinary applications XXXP XXXPC FR-2 FR-3 CEM-1 CEM-3 FR-6 G-10 FR-4 G-11 FR-5 GI

1.3 1.3 1.3 1.0 0.50 0.50 0.50 0.50 0.50 0.50

1.0 0.75 0.75 0.65 0.30 0.25 0.40 0.25 0.25 0.25 0.25 1.0

0.85 0.65 0.65 0.60 0.25 0.20

0.10 0.10 0.05 0.01

0.09 0.09

0.20 0.20 0.20 0.20

High-frequency applications GT GX Polystyrene Cross-linked polystyrene

0.20 0.20

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Chapter Two

TABLE 2.8

Grade XXXPC FR-2 FR-3 CEM-1 CEM-3

■

Flammability Classifications UL classification

Grade

UL classification

94HB 94V-1 94V-0 94V-0 94V-0

G-10 FR-4 G-11 FR-5 FR-6

94HB 94V-0 94HB 94V-0 94V-0

94HB. Specimens are to be horizontal and have a burning rate less than 1.5 in./min over a 3.0-in. span. Sample must cease to burn before the flame reaches the 4-in. mark.

2.3.6 Electrical properties of laminates 2.3.6.1 Surface resistivity. The effect of humidity on the surface resistance of glass-epoxy was measured by using the American Society for Testing Materials (ASTM) three-electrode circular pattern, starting with 97.5 percent RH at 40°C and decreasing the humidity to 64 percent. The results, shown in Fig. 2.10, indicate that the surface resistivity decreases logarithmically with an increase in humidity at approximately the rate of 1 decade per 20 percent humidity change. 2.3.6.2 Dielectric strength. (Perpendicular to the laminations at 23°C.) Method: ASTM D 149. Unit of value: V/mil. Dielectric strength is the ability of an insulation material to resist the passage of a disruptive discharge produced by an electric stress.3 A disruptive discharge is measured by applying 60-Hz voltage through the thickness of the laminate, as shown in Fig. 2.11. All the tests are run under oil. In the shorttime test the applied voltage is increased at a uniform rate of 0.5 kV/s. In the step-by-step test, the initial voltage is 50 percent of the shorttime breakdown voltage; thus, the voltage is increased in increments according to a predetermined schedule of 1-min intervals. The test val-

Figure 2.10

Surface resistivity vs. relative humidity.

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Figure 2.11

59

Dielectric strength test.

ues for dielectric strength vary with the thickness of the material, the form and size of electrodes, the time of application of the voltage, the temperature, the frequency and wave shape of the voltage, and the surrounding medium. Step-by-step data for 1⁄16-in.-thick material are as shown in Table 2.9. 2.3.6.3 Dielectric breakdown. (Parallel to the laminations at 23°C.) Method: ASTM D 149. Unit of value: kV. Condition D 48/50. Dielectric breakdown is the disruptive discharge measured between two electrodes (Pratt and Whitney No. 3 taper pins) inserted in the laminate on 1-in. centers perpendicular to the laminations.4 All tests are run under oil. The short-time and step-by-step tests are performed as in the test for dielectric strength perpendicular to laminations. Step-by-step data on 1⁄16-in.-thick material are given in Table 2.10. 2.3.6.4 Dielectric constant (permitivity). Method: ASTM D 150. Unit of value: dimensionless. Dielectric constant is the ratio of the capacitance of a capacitor with a given dielectric to the capacitance of the same capacitor with air as a dielectric, as illustrated in Fig. 2.12. The dielectric constant is a measure of the ability of an insulating material to store electrostatic energy. It is calculated from the capacitance as read TABLE 2.9

Material XXXP FR-2 FR-3 CEM-1 CEM-3

TABLE 2.10

Dielectric Strength Data V/mil

Material

V/mil

740 740 550 500 500

G-10 G-11 FR-4 FR-5 GI

510 600 500 500 750

Dielectric Breakdown Data

Material

kV

Material

kV

XXXPC FR-2 FR-3 FR-6 CEM-1 CEM-3

15 15 30 30 40 40

G-10 FR-4 G-11 FR-5 GT GX

40 40 40 40 20 20

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Chapter Two

Dielectric constant test.

Figure 2.12

on a capacitance bridge, the thickness of the specimen, and the area of the electrodes. It varies with temperature, humidity, and frequency. (See Table 2.11.) 2.3.6.5 Dissipation factor. (Average at 1 MHz.) Method: ASTM D 150. (See Fig. 2.13.) Unit of value: dimensionless. In an insulating material, the dissipation factor is the ratio of the total power loss, in watts, in the material to the product of the voltage and current in a capacitor in which the material is a dielectric. It varies over a frequency range. (See Tables 2.12 and 2.13.)

2.4 Imaging/Drilling/Plating/Etching 2.4.1 Imaging processes

The imaging process comprises several sequential steps that together allow for the metal interconnect pattern to be formed on a bare substrate. The steps themselves are interactive and it is a balance between them that allows for the reproduction of a master pattern into a metal TABLE 2.11

Materials

Permittivity Permittivity at 1 MHz (Condition D 24/23)

Ordinary applications XXXPC FR-2 FR-3 CEM-1 CEM-3 FR-6 G-10 FR-4 G-11 FR-5 GI

4.1 4.5 4.3 4.4 4.6 4.1 4.6 4.6 4.5 4.3 4.8 High-frequency applications

GT GX Polystyrene Cross-linked polystyrene

2.8 2.8 2.5 2.6

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Figure 2.13

61

Dissipation factor test.

pattern with high fidelity. The success of the steps in the sequence is dependent on the materials or chemicals used, but also to a large extent on the equipment utilized. Thus, again there is a balance of various factors needed in order to obtain a stable, reproducible, and highyield/low-cost process. The details of the chemistry and the equipment used to perform it will be outlined, and as often as possible the tradeoffs of various choices will be highlighted so that both the inexperienced process engineers and the designers and procurers of PCBs who need an overview of the process considerations will be able to proceed in their work to obtain a manufacturable product. The process sequence for imaging is given in Fig. 2.14, where the resulting pattern is used for either subtractive or additive metal pattern transfer. The details of these processes are given in the subsequent chapters. In a generic sense the process involves the coating of a polymeric material onto the substrate of interest, patterning the TABLE 2.12

Dissipation Factors Dissipation factor at 1 MHz

Materials

Condition A

Condition D 24/23

Ordinary applications XXXP XXXPC FR-2 FR-3 CEM-1 CEM-3 FR-6 G-10 FR-4 G-11 FR-5 GI

0.028 0.028 0.024 0.024 0.027 0.020 0.020 0.018 0.018 0.019 0.019 0.020

0.03 0.03 0.026 0.026 0.028 0.022 0.028 0.019 0.020 0.020 0.028 0.030

High-frequency applications GT GX Polystyrene Cross-linked polystyrene

0.005 0.002 0.00012–0.00025* 0.0004–0.0005†

0.006 0.002 0.00012–0.00066* 0.0005

* Condition A, 10 MHz. † Condition A, 10 GHz.

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Chapter Two

TABLE 2.13

Permittivity and Dissipation Factors of FR-4 (Condition D 24/23) Frequency

Dielectric constant

Dissipation factor

100 Hz 1,000 Hz 10,000 Hz 100,000 Hz 1 MHz 10 MHz 100 MHz 1,000 MHz 10,000 MHz

4.80 4.75 4.70 4.65 4.60 4.55 4.50 4.45 4.40

0.009 0.012 0.015 0.018 0.020 0.022 0.024 0.025 0.025

material either by depositing the initial layer in a patterned fashion (screen printing) or by the use of a master of the pattern desired and a photographic sequence of exposing and developing for copying the master to the polymer coating. The choice between these patterning sequences is governed by the feature size desired. Larger features (8 mil and greater) can be very economically formed by screen printing. Feature sizes smaller than 8 mil are formed using a photolithographic process.

Clean Surface

Apply Photoresist

Expose Photoresist

Develop Photoresist Image

Pattern Transfer Image (plating or etching)

Strip Photoresist Process flow chart of photolithography.

Figure 2.14

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2.4.1.1 Photosensitive materials. The photosensitive polymeric systems used in the PCB industry are used either as liquids directly or as dry films of an initial liquid solution. Both types of materials are used widely and are excellent solutions for a variety of processing requirements. In addition, these materials may function in a photographic sense in a positive or negative tone. The difference is illustrated in Fig. 2.15 and arises from the distinct chemical compositions and in the photoinitiated reaction within the film itself. The key factor to the functioning of these materials is that their solubility in the developing solution changes on exposure to light. In the case of the common negative-acting systems, the photoreaction provides a polymer network that is less soluble in the developing solution by promoting cross-linking between one or more of the components in the polymeric matrix. The resulting molecular weight change in the exposed region of the film reduces the material’s solubility, and it is these regions that remain after development of the image. In the positive-acting systems, the chemistry is very often that of the novalac resin-based materials utilized by the semiconductor industry. Upon irradiation, the material becomes more soluble than the original, and it is these exposed regions that are removed in the developer solution. There are many reports of the inherent differences in product yield associated with either positive- or negative-acting material. Positive-acting materials are often considered to provide for a higher-yield process. This could be due to the division of lines and spaces on the phototool; spaces are a greater area than lines. For a positive-acting material, the spaces are clear and these large areas are less sensitive to defect-causing debris. In contrast, for negative phototools, a small size and amount of contaminant will be reproduced as an open in the conductor. It is unfortunate that there are few materials that don’t have some other obvious attribute such as thickness, coating method, etc., which will alter the yield other than their photographic tone. There is a large variety of materials commercially available, but how does one determine which is likely to perform best for a given application? There are several key factors to consider—several technical and many economic, the latter of which are unique to each manufacturing facility. The technical decision sequence is summarized in Fig. 2.16. The foremost consideration is the end use of the pattern; the material must have chemical compatibility with the subsequent pattern transfer steps. The chemical nature of these steps, especially the solution pH, must be distinct from the photoresist’s unique solubility. Only then can the photoresist perform as an accurate mask for pattern transfer. Another key factor is the nature of the substrate itself in terms of topography and surface features; i.e., is the mask required to cover or tent plated through-holes or tooling features, and must it conform to

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Figure 2.15 Procedures for positive and negative tone photoresists.

existing circuitry? This consideration will dictate whether dry film or liquid material is appropriate and, in some instances, the required tone of the photoresist material. Equally important is the required product feature dimension and allowable variation. This is usually specified in terms of line width and spacing with a given allowable variation on the nominal. Since these product parameters are for the final conductor features, some estimate of the photoresist processing contribution to this value must be established. Each material has its inherent contrast or ability to switch from exposed to unexposed. This, along with the resist thickness, phototool, and light source used for exposure, governs the feature dimensions that can be defined with a given material. For the materials used in the PCB industry, the following rule usually holds: the minimum line width definable in production is usually 0.5 to 1.0 mil greater than the photoresist thickness. New process sequences have demonstrated improvements beyond this traditional barrier.5 Of a more practical nature, the material chosen must have adhesion to the underlying substrate. There are many approaches to promoting adhesion between dissimilar materials, but there must be an inherent compatibility.

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Figure 2.16

65

Selection criteria for photoresist materials.

2.4.1.2 Equipment alternatives. The process steps for obtaining a usable image are all interactive and, therefore, the equipment plays a very large role in the success of the overall process. For each step there are numerous options. The choice between options is governed by the product specifications with respect to layer thickness and feature size and, in some instances, by the chosen photoresist, in addition to the economic factors that are unique to each installation. The alternative equipment for each process step will be described with criteria by which to compare them. Cleanliness considerations. Cleanliness is of concern for the entire photolithography process. This includes yellow room contamination level

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(cleanliness class), solution filtration, equipment cleanliness class, and product handling. The relative importance of each of these must be established for the product feature dimensions. The sensitivity of the photolithographic sequence to the size and location of contamination can be determined, and then the appropriate level of cleanliness can be instituted and maintained.6–8 In addition, equipment to remove contamination from flat surfaces—either panels or equipment—can be used throughout the processing sequence. These sticky rollers are available as freestanding equipment and as handheld items. Preclean. This step provides the foundation for all the others since only an appropriately cleaned substrate allows for good adhesion between the photoresist and the substrate and for the remainder of the process to be successful.9 All laminates arrive at the imaging area dirty and, depending on the type of contamination, the exact process sequence is chosen. Contamination—epoxy dust—from trimming and processing the laminate itself is removed by mechanical cleaning. The surface copper is either foil or foil with electroless or electroplated copper. The foil is treated with an antitarnishing agent of chromium and zinc, which is removed for reproducible imaging results. Not only are contaminants removed, but also the texture or surface roughness of the copper is altered to promote mechanical adhesion between the base copper and the photoresist. The extent of this texturing is measured by the usual parameters for surface roughness where the height and spacing of the topography is quantified by profilometer measurements (see Fig. 2.17). Chemical cleanliness can be determined in a variety of ways. Wetting is often tested using a water break test or more analytically in terms of contact angle where a low value is desirable. In addition, analytical techniques can be used to evaluate the chemical composition of the surface (Auger and x-ray photoelectron spectroscopy [XPS]) (Table 2.14). Photoresist apply. The numerous choices for applying the photoresist are tied in most instances to the photoresist choice. The discussion here will be divided between liquid and dry film methods. Irrespective of the method chosen, the cleanliness of the operation—both the equipment and the clean room—and the handling of the product are important. It is also advisable to minimize the handling at this stage with the use of automated operation. Specifically, in-line equipment, with the preclean step and automatic loading and unloading, is advised. Expose. In this key step for image formation, the master pattern is aligned to and exposed in the product so that the relief image can be subsequently developed. The elements of the process are the phototool, the registration of the phototool to the panel, and the light source used for exposure. The choices for phototools (film or glass) differ as to sharp-

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Figure 2.17

67

Surface roughness parameters.

ness of the transition from opaque to clear, the pattern’s dimensional stability, and the substrate absorption of the exposing light. The panel is aligned either mechanically with pins holding the phototool with respect to the product or optically with alignment features dictating the movement of the phototool and product. The alignment requirements are interrelated with those achieved at composite lamination and drilling. The registration scheme is contained within the exposure equipment. The light source alternatives include contact printing with either a collimated or uncollimated light source, proximity printing, projection printing, and laser direct imaging.10 The latter three methods separate the phototool from the substrate and are expected to have an increased product yield due to reduced contamination. No phototool is used in laser direct imaging since the laser beam exposes the image based on the design data. TABLE 2.14

Sample Initial Preclean 1 Preclean 2

Copper Surface Chemical Composition as Measured by XPS % Cu

%O

%C

12 6

46 19 10

24 68 70

%N

% Zn

% Cr

16

12

14

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Develop. In this process step, the solubility difference between the exposed and unexposed portions of the photoresist is realized. Immersion in an appropriate solvent results in a relief image of the master pattern. The process conditions are adjusted to alter the clearing time for dissolving the unexposed or negative materials or exposed or positive ones. The total dwell time is set to approximately double the time to clear, commonly called a 50 percent breakpoint. Additional variables include the solution temperature, agitation, and concentration. The resulting photoresist images should be distinct with vertical sidewalls. Failure to accomplish this is an indication that the previous process step setpoints require adjustment. Images larger than the phototool dimension result from incomplete development, overexposure, or poor contact at expose. If the images are smaller than expected, then the exposure dose is too low or development is too aggressive. Distorted images can be caused by problems with precleaning, application, or exposure. The common equipment for developing is spray conveyorized, either horizontally or vertically. Additives to the developer solution are required in many instances to prevent foaming. The solution is filtered to remove resist particles and either replenished with fresh solution to maintain a consistent dissolved resist value and solution concentration or operated continuously for a certain amount of product and replaced. Waste developer solution is treated (aqueous and semiaqueous) or distilled and reused (solvent). Rinsing is also important to stop the dissolution reaction. In addition, water with a high mineral content often improves the aqueous photoresist resist image and the conductor yield. Tank systems can also be used, especially for materials with a wide process latitude. Often, ultrasonic agitation is used to aid in the dissolution. There are additional steps that improve the resist removal in the line channels and the conductor formation yield. Plasma treatment has been used effectively to improve product yield, especially with respect to shorts in a print-and-etch process. In addition, for some aqueousdevelopable dry films, a heat treatment after exposure improves the space definition, and spaces equal to or smaller than the resist height have been resolved.5 Thus, these process steps ensure that tight resolution requirements can be met. Strip. The photoresist is removed from the substrate after it has functioned in the pattern transfer step. The equipment used for this process step is identical to that used for developing. The removal is accomplished by swelling and dissolving the material. Some materials are removed in sheets or as small particles and, depending on the equipment design, can be accommodated. Often brushes and ultrasonic

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agitation are added to aid in the resist removal. As with developing, filtration is important to keep fresh solution reaching the part and the nozzles of a spray tool clean. For stripper chemistries that oxidize the copper, an antitarnishing agent is often added to either the stripping or rinsing solution. 2.4.1.3 Design for manufacturing. A high-yield conductor formation process can be enhanced by the optimization of several design features. These concern the conductor dimensions and the process used to form them. Specifically, these are the process sequence to be used (etched or plated metal), the division of conductor pitch between line and spacing, and the PTH capture land size and shape. Process sequence: etch vs. plate considerations. For a given product conductor dimension, there is often a question of the appropriate process sequence. Although the capabilities of imaging and the pattern transfer step dictate the overall limitations, the decision depends on the unique capabilities of the manufacturing line to be used. Some general considerations can clarify the true issues for most production situations. The photoresist patterns for plating and etching are very distinct. For etching, a thin photoresist is desirable to maximize the etchants’ attack in the line channel. Thus, the resolution of the photoresist does not limit the process, since very small spaces can be resolved in liquidcoated materials. The challenge for conductor formation resides with the etching. Depending on the metal thickness and the etching equipment, it can be very difficult to remove the copper in tight spaces. Therefore, the key criterion defining the capabilities of the print-andetch process is the minimum spacing cleared as constrained by the final conductor height and the etchant chemistry and equipment. For plated products, the photoresist thickness must be greater than or equal to the final thickness of the conductor wire and it must be possible to clear a photoresist space equal to the final conductor width. These fine spaces are challenging when the conductor height increases. The photoresist resolution is on the order of its thickness, so that for 1-mil-thick plating, it would be difficult to resolve a photoresist space smaller than 1.5 mil, irrespective of the final conductor spacing. Thus, the challenge for plating is to resolve the fine spaces in thicker photoresist materials and then to ensure that the plating solution wets the bottom of the narrow photoresist channels. Thus, in choosing the conductor formation process, the thickness of the conductor and the line width and spacing are the key parameters. A generalized relationship between them is found in Fig. 2.18. It is important that this type of plot is known for the production area before the process sequence is determined.

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2

1.8

1.6

Cu Thickness (mils)

1.4 1.2

1 0.8

0.6 0.4

0.2 0 2

4

5

9

10

Line / Space Pitch (mils)

Figure 2.18

Typical manufacturing line process capability to aid in sequence decisions.

Line and space division for a fixed pitch. It is common for product designs to have a fixed pitch, whether it refers to the I/Os for direct chip or packaging attachment or to the spacing between PTHs. This space is often divided equally between conductors and spacing. As mentioned previously, for either additive or subtractive processing, the photoresist and pattern transfer process yield can be enhanced by avoiding the resolution limitations of each sequence. In subtractive conductor formation, an etch factor is used to obtain straighter sidewalls and improved line width control. If lines and spaces are equally allocated, then the photoresist must resolve a smaller space than a line. This is difficult, except when very thin coatings are used in conjunction with one of the enhancement schemes.5 Thus, it is a higher-yielding process to have larger spaces than lines. For additive processing, the spacing in the photoresist is the limiting factor. After pattern transfer, this will become the line. In this instance, equal lines and spaces are more acceptable, but based on the photoresist concerns, a wider final line than space is preferred. At the same time, it is desirable to increase the spacing for reduced incidence of line shorting, which translates to a wider “line” in the photoresist. The former is usually more important. Therefore, for both process sequences there is preferably balance between line width and spacing. PTH capture pad size and shape for optimum line formation. Just as the conductor line and spacing can be optimized, the PTH capture pad shape and size can be altered to further increase the yield. The absolute

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dimension of the feature is dictated by the placement accuracy of the drilling process and the overall dimensional stability of the product. The feature is sized to ensure that the PTH and conductor are connected. There are varying specifications as to the extent of capture that is required. Depending on the direction and magnitude of the dimensional stability and the drill wander and accuracy, the shape required to capture the PTH can be changed. This would reduce the size of this feature in at least one direction. In consequence, the spacing between the line and pad increases. Since this location is a change to the nominal line-to-line spacing, the narrowing of the channel results in shorting between the features in both print-and-etch and additive processes. In the former case, it is more difficult to clear the space, and in the latter, the narrower resist width is often underplated. Thus, when possible, an elongated pad will benefit the final conductor yield. 2.4.2 Drilling processes

The purpose of drilling printed circuit boards is twofold: (1) to produce an opening through the board that will permit a subsequent process to form an electrical connection between top, bottom, and sometimes intermediate conductor pathways; and (2) to permit through-theboard component mounting with structural integrity and precision of location. The quality of a drilled hole through a printed circuit board is measured by its interface with the following processes: plating, soldering, and forming a high-reliability nondegrading electrical and mechanical connection. It is possible to drill holes meeting these requirements with high productivity, consistency, and yield. The elements of this process are materials, such as laminates, drill entry, and backup, and drills; processes including machine parameters, techniques, and operating personnel; and control evaluation of hole quality, drills, and process machinery. When all these elements are properly developed and implemented, high-quality printed circuit board holes are a natural result. Such holes can be plated directly, eliminating remedial processes of deburring, desmearing, and etchback, and resulting in process simplification, higher yields, and lower costs. The interaction and practice of elements shown in Fig. 2.19 can optimize the drilling process for the fabrication of printed circuit boards. While all of the elements shown are interdependent, it is hole quality and location accuracy that ultimately steer decisions on feeds and speeds, material choices, and productivity.

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Figure 2.19

Essential elements of successful PCB drilling.

2.4.2.1 Drills. Drills for making holes in printed circuit boards are usually made of tungsten carbide. This is due to interrelated needs of cost, wear properties, machinability, and handling properties. No other material has proved to be as suitable. The design of a drill is just as important as the materials used. The design and the wear of the drill affect its drilling temperature, ability to remove chips, tendency to create entry and exit burrs, and smoothness of the hole wall (all directly related to hole quality). Figure 2.20 shows a typical drill bit geometry. The point angle is usually between 90° and 110° for paper-base materials and between 115° and 130° for glass-base materials. By far the most common point angle

Figure 2.20

Typical drill bit geometry.

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used in drilling is 130°. The flute or helix angle determines the drill’s ability to remove chips from the hole. Helix angles vary from 20° to 50°. A 20° angle provides fast chip removal with poor cutting efficiency. A high helix angle (50°) creates a smaller material plastic zone but yields slower chip removal, as shown in Fig. 2.21, angle A. A helix angle of 30° is a good compromise between a small plastic zone and quick chip removal. This compromise minimizes drilling temperature. Figure 2.20 also shows an important characteristic of highperformance drills described as a relieved land. Increases in temperature during drilling can also be caused by the amount of drill surface area in direct contact with the hole wall. To minimize this surface area, most manufacturers remove material just behind the margin or cutting area to reduce friction and thus lower the temperature of drilling. Other geometries being equal, the narrower the margin, the cooler the drilling temperature. The length of the margin relieved area also affects the drilling temperature. Figure 2.22 shows the relief area in a (a) partially relieved, (b) fully relieved, and (c) spade-head drill. A drill design with a larger relief area will drill cooler because of the smaller drill surface area in contact with the hole wall. Other factors being equal, the partially relieved design will drill hotter than the fully relieved design and the spade head design will drill cooler than the fully relieved design. The surface finish of the drill is important; that is, the smoother the surface, the cooler the drilling. Surface finishes lower than 4 µin. should be used. The volume of empty space in the drill flutes is another important design consideration. The greater the open volume, the higher the capacity of the drill to remove chips efficiently. Conversely, greater volume (thinner center web) implies a weaker drill that is more prone to breakage. Figure 2.23 shows (a) a standard microdrill and (b) a step design that strengthens the drill without increasing the web thickness by adding a step in the diameter reduction between the drill shank and the fluted area. The added step strengthens the drill bit by

Schematic diagram for the cutting process of drill bit.

Figure 2.21

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Figure 2.22 Drill bit flute designs. (a) Partially relieved. (b) Fully relieved. (c) Spade-head.

reducing the abruptness of the transition between the flute and the shank of the drill bit. In general, the best drill designs are those that drill with the lowest drill temperature. Drills that drill cooler have a good surface finish, thin webs, no geometrical defects or chips, sharp cutting edges, and durable carbide. In addition, the best operating parameters for drills are those that also minimize drill temperatures. Finally, as drills wear, they drill hotter and hole quality decreases. Run length must be carefully determined. It should not be assumed that all manufactured drills are of equal quality. Differences in design, manufacturing processes, surface finish, raw materials, and consistency vary widely and should be evaluated prior to the purchase of production quantities of drills. 2.4.2.2 Laminates. All laminates are manufactured to specifications that take into account electrical and physical properties. Ease of drilling ordinarily is not considered by laminate engineers. It is left up to the printed circuit board fabricator to develop the correct parameters to drill laminates for the best hole quality. The various types of laminates are formed from several resins and supporting materials. These vary from common to exotic types that differ in the ease with which they may be drilled. From easiest to most difficult to drill, some commonly available laminates are G-10 epoxy-glass, FR-4 epoxy-glass, multifunctional epoxy, polyimide-glass, phenolic-paper, Teflon-glass, polyimide-quartz, and exotics.

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Figure 2.23

75

Geometry of microdrill bits. (a) Standard design. (b) Step

design.

Where cloth is used, the weave and fiber thickness affect drill wander. The finer the fiber, the less drill wander. In addition, laminate is produced with various thicknesses of copper, either in double-sided laminates or in multilayers. The ratio of the copper thickness to total thickness of the laminate changes the optimum drilling parameters so that feeds and speeds should be adjusted based on the ratio of copper to substrate. Dimensional stability, warping, bow, and twist specifica-

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tions are important to the drilling operations. For example, laminates that are not flat drill with high burrs. The thickness of the laminate to be drilled is controlled by the smallest drill diameter to be used. The controlling factor is 10 times the drill diameter. For example, the maximum material thickness for a 0.020-in.diameter drill is 0.200 in. As drill depth increases, the drill’s deviation from true center increases. For minimum-sized drills, the deviation increases by 0.001 in. for each 0.0625 in. of laminate thickness. For example, a 0.020-in.-diameter drill drilling through 0.200-in. laminate provides deviations of 0.005 in. If this is unacceptable, laminate thickness must be reduced. Good multilayers and double-sided laminates should not require prebaking before drilling to fully cure the laminate. Uncured laminate is unacceptable from the supplier. Prebaking is often practiced to stress-relieve the laminate. Edges of laminate panels for drilling should be free of burrs so that stacking can occur with good interlaminate contact. To produce quality holes for each series or type of laminate, the following generalities can be stated: ■

The higher the Tg of the laminate, the better.

■

The laminate should be flat, uniform in thickness, and smooth, and it should exhibit high copper peel strength.

■

Prebaking the laminate before drilling helps dimensional stability but does not “correct” uncured resin.

■

The storage of laminate under controlled conditions of temperature and humidity is necessary. These conditions should be the same as the ambient conditions surrounding the drilling machine.

■

The more glass cloth layers and the higher the glass-to-resin ratio, the more drill wear is obtained per hole drilled.

■

The thicker the glass cloth diameter, the greater the drill wander.

■

Laminates that are not flat will cause interlaminate entry and exit burring.

■

The more abrasive the supporting fibers (quartz, for example), the greater the drill wear and the shorter the drilling run per drill.

■

Harder and thicker copper shortens the life of the drill.

Laminate panels are normally stacked three high between entry and backup materials for 0.062-in.-thick double-sided laminates and one or two high for multilayers. They are placed in a pinning machine that drills a minimum of two holes and inserts tooling pins to hold the stack firmly.

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Foreign materials and burrs on the laminate must be removed. This is true for entry and backup materials as well. The stack must be tight. Loose pinning causes burrs and poor registration. Poor pin alignment can cause bowed stacks. Pins and bushings should be checked for wear, and drilling machine operators should be instructed on the importance of cleanliness when handling laminates and entry and backup materials. 2.4.2.3 Drilling machines. Drilling machine types vary over a wide range, from single-spindle, manually operated, bottom-drilling types, using templates for locating holes, to multiple-drill-station, computer numerically controlled (CNC), automatic machines that accept stacks of laminate, eject laminate, and change tools automatically. Machines are designed to accept laminate panels of various sizes, up to 24 × 24 in. Costs range from $10,000 at the low end to $500,000 for the largest and most automated machines. The type of machine needed depends on production capacity and the type of process design. Whatever the type, it is important to prepare and design the machine’s environment. Machines should be located in temperature- and humiditycontrolled, dust-free environments. Floors should be adequately designed to carry the machine weight. Machines should be isolated from any external vibrations. Isolated electrical power and grounding are necessary. Rigorous and well-planned maintenance programs are important. The items in the following list are most important, but the list is not inclusive.

1. The actual revolutions per minute and feed rate of the machine should be determined by an independent method. Do not rely on the machine readout. 2. Vacuum systems should be maintained at high flow rates and full efficiency. It is better to overdesign this function. Filters should be replaced regularly. 3. Spindle cooling systems, coolant, and heat exhangers should be checked and kept clean so that they work efficiently. 4. Spindles and collets should be kept clean at all times, using noncorrosive cleaners that keep thin protective films on the metallic parts. 5. Spindle runout should be kept to less than 0.0005 in. for heart of the range drilling and to less than 0.0002 in. for small hole drilling. 6. Drill bars, springs, and air-pressure seals should be carefully checked and maintained. 7. Pressure foot pressures should remain as high as the laminate will allow. 8. The z-axis alignment should be checked often.

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Machine manufacturers’ instructions regarding warmup before use should be followed carefully. Machines should be kept scrupulously clean. Dirt, chips, and debris left on machine tables should be removed with a vacuum cleaner. Never blow surfaces with compressed air to remove dirt. There are two aspects to drill wander: precision and accuracy. Only accuracy is affected by machine performance. The machine accuracy can be checked by drilling a square matrix of holes. The lines of holes can be defined in the x and y directions by comparing the mean lines to reference holes via regression analysis. These best-fit lines are compared with the desired lines the machine was instructed to place. From the slopes, the orthogonality of the machine can also be determined. Precision of drilling is dependent on many factors. One of these is spindle runout. The less the spindle runout, the greater the precision of drilling. With good spindles and a well-maintained machine, precision and accuracy are about equal for 0.0135-in.-diameter drills. These calculations are based on drilling 0.100 in. of laminate. Precision is also affected by chip load, roughness of laminate surface, entry material roughness, entry material construction, drill bit diameter, glass weave, glass thickness, drill design, and drill concentricity. 2.4.2.4 Accuracy and precision. It is important to understand how to produce not only high hole quality but also accurate, precisely drilled holes. Accuracy can be defined as how well the hole location agrees with the correct or target value. Precision is defined as how reproducible the hole location is. Accuracy problems are usually due to drilling machine problems. Machine problems are due to mechanical wear, loss of computer data, and electromechanical error. Precision problems are due to poor entry material, laminate thicknesses that are too great for the drill diameter, excessive chip loads, drill resonance, and excessive spindle runout. 2.4.3 Plating processes

A major part of manufacturing printed circuit boards involves wet process chemistry. The plating aspects of wet chemistry include deposition of metals by electroless (metallization) and electrolytic (electroplating) processes. Topics to be described here are electroless copper, electroplating of copper and resist metals, nickel and gold for edge connector (tips), tin-lead plating, and alternative coatings. Specific operating conditions, process controls, and problems in each area will be reviewed in this section. (See printed circuit plating flowchart in Fig. 2.24.) Two driving forces have had major influence on plating practices: the precise technical requirements of electronic products and the demands

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Plating flowchart for printed circuit board manufacturing.

Figure 2.24

of environmental and safety compliance. Recent technical achievements in plating are evident in the capability to produce complex, highresolution multilayer boards. These boards show narrow lines (3 to 6 mil), small holes (12 mil), surface-mount density, and high reliability. In plating, such precision has been made possible by the use of improved automatic, computer-controlled plating machines, instrumental techniques for analysis of organic and metallic additives, and the availability of controllable chemical processes. Mil-spec-quality boards are produced when the procedures given here are closely followed. 2.4.3.1 Electroless copper plating.11–15 This series of chemical steps (after smear removal) is used to make panel side-to-side and innerlayer connections by metallizing with copper. The process steps needed include racking, cleaning, copper microetching, hole and surface catalyzing with palladium, and electroless copper. Typical steps are as follows:

1. Cleaner-conditioner. Alkaline cleaning is used to remove soils and condition holes.

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2. Microetch. This slow acid etching is used for removal of copper surface pretreatments, oxidation, and presentation of uniformly active copper. Persulfates and sulfuric acid–hydrogen peroxide solutions are commonly used. 3. Sulfuric acid. Used for removal of persulfate residues. 4. Predip. Used to maintain balance of the next step. 5. Catalyst (activator). Neutral or acid solutions of palladium and tin are used to deposit a thin layer of surface-active palladium in the holes and on the surface. 6. Accelerator (postactivator). Used for the removal of colloidal tin on board surfaces and holes. 7. Electroless copper. Alkaline-chelated copper reducing solution that deposits thin copper in the holes (20 to 100 µin.) and on surfaces. 8. Antitarnish. A neutral solution that prevents oxidation of active copper surfaces by forming a copper conversion coating. Selection from several types available depends on the type of image transfer desired. Operation and control of three bath types and the function of constituents are given in Tables 2.15 and 2.16. The following outline presents the typical steps in an electroless copper process: 1. Rack 2. Clean and condition 3. Water rinse 4. Surface copper etch (microtech) TABLE 2.15

Operation and Control of Electroless Cu Processes Low deposition

Medium deposition

Heavy deposition

Copper HCHO NaOH Temperature Air agitation Filtration Tank design

3 g/l 6–9 g/l 6–9 g/l 65–85°F Mild Periodic Static

Heater Panel loading Replenish mode

Teflon 0.25–1.5 ft2/gal Manual

2.0 g/l 3.3 g/l 8 g/l 115 ⫾ 5°F Moderate Continuous Overflow, separate sump Teflon 0.1–2.0 ft2/gal Automatic

Idle time, control Deposition time Thickness

70–85% 20 min 20 µin.

2.8 g/l 3.5 g/l 10–11 g/l 115 ⫾ 5°F Mild/moderate Continuous Overflow, separate sump Teflon 0.1–2.0 ft2/gal Manual or continuous Turn off heat 20 min 40–60 µin.

Turn off heat 20–30 min 60–100 µin.

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TABLE 2.16

81

Function of Constituents for Electroless Cu Plating Constituent

Copper salt Reducing agent Complexer pH controller Additives

CuSO4 ⋅ 5 H2O HCHO EDTA, tartrates, Rochelle salts NaOH NaCN, metals, S, N, CN organics

Function Supplies copper Cu+2 + 2e → Cu0 Holds Cu+2 in solution at high pH; controls rate Controls pH (rate) 11.5–12.5 optimum for HCHO reduction Stabilize, brighten, speed rate, strengthen

5. Water rinse 6. Sulfuric acid (optional) 7. Water rinse 8. Preactivator 9. Activator (catalyst) 10. Water rinse 11. Postactivator (accelerator) 12. Water rinse 13. Electroless copper 14. Rinse 15. Sulfuric acid or antitarnish 16. Rinse 17. Scrub (optional) 18. Rinse 19. Copper flash plate (optional) 20. Dry 21. Release to image transfer 2.4.3.2 Copper electroplating. Because of its high electrical conductivity, strength, ductility, and low cost, copper is the most commonly used metal for the structure of a printed circuit board. In addition, copper is readily plated from simple solutions and is easily etched. MIL-STD275 states that electrode-posited copper shall be in accordance with MIL-C-104550, and shall have a minimum purity of 99.5 percent as determined by ASTM E 53. The minimum thickness shall be 0.001 in. (1 mil). Requirements for good soldering also indicate the need for 1 mil of copper and smooth holes.30 Copper plating is generally regarded as the slow step in manufacturing PCBs. New methods that cut plating

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times by as much as 50 percent include high-speed additives, pulse plating, and rapid solution-impingement machines.16–24 Key factors for uniform plating. To have day-to-day control and to achieve ductile, strong deposits and uniform copper thickness, the following controls are required:25–27

1. Maintain equipment following best practices, such as uniform air agitation in the tank, equal anode-cathode distances, rectifier connection on both ends of tank, and low resistance between rack and cathode bar. 2. Maintain narrow range control of all chemical constituents, including organic additives and contaminants. 3. Conduct batch carbon treatment regularly. 4. Control temperature at 70°F to 85°F. 5. Eliminate contaminants in tank from preplate cleaners, microetchants, and impure chemicals. 6. Plate at one-eighth to one-half of the conventional cathode current density when using thick boards (0.100 in.) with small holes (0.015 in.) and fine lines (6 to 8 mil). Acid copper sulfate. The preferred industrial process uses an acid copper sulfate solution containing copper sulfate, sulfuric acid, chloride ion, and organic additives. Using the proper additives, the resultant copper is fine-grained with tensile strengths of 50,000 lb/in2 (345 MPa), a minimum of 10 percent elongation, and a surface-to-hole thickness ratio of 1.2. (See Table 2.17.) Copper pyrophosphate. Once the standard of the industry, pyrocopper has been almost entirely replaced by acid copper, except in military and special applications. Pyrocopper continues to be used because of its resistance to cracking, high throwing power, and purity of deposits. The use of organic additives with pyrocopper is optional,28–30 but it is preferred because such additives provide wider tolerance of cracking control and improve deposit quality.31–34 The additive PY-61H, identified as dimercaptothiadiazole, is effectively controlled in production by CVS. (See Table 2.18.)

2.4.3.3 Solder (Sn-Pb) electroplating. Solder plate (Sn60-Pb40) is widely used as a finish plate on printed circuit boards. This process features excellent etch resistance to alkaline ammonia, good solderability after storage, and good corrosion resistance. Tin-lead plating is used for several types of boards, including tin-lead/copper, tin-lead/tin-nickel/copper, solder mask on bare copper (SMOBC), and surface-mount (SM). Fusing

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TABLE 2.17

83

Operation and Control of Acid Cu Sulfate Conventional

Operating variables Copper Copper sulfate Sulfuric acid Chloride Additives Temperature Cathode current density Anodes† Type Composition Bags Hooks Length Anode current density Properties Composition Elongation Tensile strength

2–3 oz/gal 8–12 oz/gal 22–28 oz/gal 40–80 ppm As required 70–85°F 20–40 A/ft2*

High-speed 3–4.5 oz/gal 12–18 oz/gal 24–36 oz/gal 40–80 ppm As required 75–100°F 40–150 A/ft2

Bars or baskets Phosphorized 0.04–0.06% P Closed-napped polypropylene Titanium or Monel Rack length minus 2 in. 10–20 A/ft2 conventional; 25–50 A/ft2 high speed 99.8% (99.5% min, ASTM E 53) 10–25% (6% min, ASTM E8 or E 345) 40–50 kpsi (36 kpsi min, ASTM E 8 or E 345)

* A/ft2 refers to amperes per square foot and is sometimes expressed as ASF. † Operating anodes should have a thin, brown or black, easily removed film.

TABLE 2.18

Operation and Control of Cu Pyrophosphate

Operating conditions pH Copper Pyrophosphate Orthophosphate Ammonia (NH3) Ratio (pyro/Cu) Temperature Cathode current density Aqua ammonia PY 61-H* Anodes† Type Composition Bags Current density Hooks Length

8.1–8.5 copper 2.7–3.5 oz/gal 19.4–26.3 oz/gal 8 oz/gal max 0.2–0.3 oz/gal 7.5–8.0/L 115–125°F 20–35 A/ft2 As needed; about 1–2 qt/day 0.25–0.75 ml/(Ah) Control with CVS Bars or baskets OFHC copper Optional, none required 20–30 A/ft2 Titanium Rack length minus 2 in

* Product of M&T Chemicals, Rahway, N.J. † Operating anodes should have a thin golden or light tan film.

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is required on all tin-lead-plated surfaces. Thickness minimums are not specified. The preferred composition contains a minimum of 55 percent and a maximum of 70 percent tin. This alloy is near the tin-lead eutectic, which fuses at a temperature lower than the melting point of either tin or lead, and thus makes it easy to reflow (fuse) and solder. (The composition of the eutectic is 63 percent tin, 37 percent lead with a melting point of 361°F.) Fusing processes include infrared (IR), hot oil, vapor phase, and hot-air leveling for SMOBC. Plating solutions currently available include the widely used high-concentration fluoboric acidpeptone system, as well as low-fluoboric, nonpeptone, and a nonfluoboric organic aryl sulfonic acid process. These processes are formulated to have high throwing power and give uniform alloy composition.35 The sulfonic acid process has the advantage of using ball-shaped lead-tin anodes but is difficult to operate. Table 2.19 gives details of operation and control of two high-throw tin-lead (solder) baths. 2.4.3.4 Tin electroplating. Tin is used extensively for plating electronic components and PCBs due to its solderability, corrosion resistance, and metal etch-resist properties. The current MIL-STD-275 does not include tin plating, although earlier versions stated a required thickness of 0.0003 in. Specifications covering tin plating are MIL-T-10727 and MILP-38510, which say that tin must be fused on component leads. Acid tin sulfate is the most widely used system. Among the many processes available, some produce bright deposits for appearance and TABLE 2.19

Operation and Control of Sn-Pb Fluoborate High HBF4 /peptone

Lead Stannous tin (Sn+2) Free fluoboric acid Boric acid Additive Temperature Cathode current density Agitation Anodes Type Composition Purity Bags Hooks Length Current density

Low HBF4 /proprietary

1.07–1.88 oz/gal 1.61–2.68 oz/gal 47–67 oz/gal Hang bag in tank Use as needed by Hull cell and Ah usage 60–80°F 15–18 A/ft2

1.4–2.0 oz/gal 2.8–4.0 oz/gal 15–25 oz/gal Same

Solution circulation

Mechanical and solution circulation

70–85°F 10–30 A/ft2

Bar Sn60-Pb40 Federal Specification QQ-S-571 Polypro Monel Rack length minus 2 in. 10–20 A/ft2

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corrosion resistance; others give matte deposits that can be fused as well as soldered after long-term heating. Tin sulfate baths are somewhat difficult to control, especially after prolonged use.36 Operation and control are given in Table 2.20. Nickel electroplating. Nickel plating is used as an undercoat for precious and nonprecious metals. For surfaces such as contacts or tips that normally receive heavy wear, the use of nickel under a gold or rhodium plate will greatly increase wear resistance. When used as a barrier layer, nickel is effective in preventing diffusion between copper and other plated metals. Nickel-gold combinations are frequently used as metal etch resists. Nickel alone will function as an etch resist against the ammoniacal etchants.37 MIL-STD-275 calls for a low-stress nickel with a minimum thickness of 0.0002 in. Low-stress nickel deposits are generally obtained using nickel sulfamate baths in conjunction with wetting (antipit) agents. Additives are also used to reduce stress and to improve surface appearance. Nickel sulfamate is commonly used both as undercoat for throughhole plating and on tips. Conditions given in Table 2.21 are applicable for through-hole and full-board plating. Nickel sulfate is typically plated with an automatic edge connector (tip) plating machine. Table 2.22 gives the operating conditions that apply to these systems. Nickel anodes are preferred in tip machines because the pH and the metal content remain stable. The pH will decrease rapidly when insoluble anodes are used. The pH should be maintained at 1.5 or higher with additions of nickel carbonate. Stress values are higher than in sulfamate baths with values of about 20 kpsi.

2.4.3.5

TABLE 2.20

Operation and Control of Acid Sn Sulfate

Operating conditions Tin Sulfuric acid Carrier, additives Temperature Cathode current density Current efficiency Solution color Plating rate Anodes Type Composition Bags Length Hooks Current density

2 oz/gal 10–12% by volume Replenish by Ah usage and spectrophotometry 55–65°F preferred 65–85°F hazy 20–35 A/ft2 100% Milky, white 0.3 mil @ 25 A/ft2 for 10 min Bars Pure tin Polypropylene Rack length minus 2 in. Monel or titanium 5–20 A/ft2

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TABLE 2.21

Operation and Control of Ni Sulfamate

Operating conditions pH Nickel As nickel sulfamate Nickel chloride Boric acid Additives Antipit Temperature Cathode current density Anodes Type Composition Purity Hooks, baskets Bags Length

3.5–4.5 (3.8) 10–12 oz/gal 43 oz/gal 4 oz/gal 4–6 oz/gal As required As required 130 ⫾ 5°F 20–40 ASF Bars or chunks Nickel Rolled depolarized, cast, or electrolytic; SD chips in titanium basket Titanium Polypro, Dynel, or cotton Rack length minus 2 in.

Early printed circuit board technology used gold extensively. In addition to being an excellent resist for etching, gold has good electrical conductivity, tarnish resistance, and solderability after storage. Gold can produce contact surfaces with low electrical resistance. Despite its continued advantages, the high cost of gold has restricted its major application to edge connectors (tips) and selected areas, with occasional plating on pads, holes, and traces (body gold). Both hard alloy and soft, pure gold are currently used. Plating solutions are acid (pH 3.5 to 5.0) and neutral (pH 6 to 8.5). Automatic plating machines for edge connectors and manual lines are in use. 2.4.3.6

Gold electroplating.38

Acid hard gold. To a large extent, acid golds are used for compliance to MIL-STD-275, which states that gold shall be in accordance with MILG-45204, Type II, Class 1. The minimum thickness shall be 0.000050 TABLE 2.22

Operation and Control of Ni Sulfate

Operating conditions pH Nickel Nickel chloride Boric acid Stress reducer Antipit Temperature Cathode current density Current efficiency

1.5–4.5 15–17 oz/gal 2–4 oz/gal (with soluble anodes) 3–4 oz/gal As required As required 130 ⫾ 5°F 100–600 A/ft2 65%

Anodes Composition

Nickel or platinized titanium

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in. (50 µin.); the maximum shall be 0.000100 in. in areas that are to be soldered. A low-stress nickel shall be used between gold overplating and copper. Nonmilitary applications require 25 to 50 µin. Type II hard gold is not suited for wire bonding. These systems use potassium gold cyanide in an organic acid electrolyte. Deposit hardness and wear resistance are made possible by adding complexes of cobalt, nickel, or iron to the bath makeup. Automatic plating machines are being used increasingly because of the enhanced thickness (distribution) control, efficient gold usage, productivity, and quality. A comparison of automatic versus manual plating methods for edge connectors is given in Table 2.23. Pure 24-karat gold. High-purity 99.99 percent gold processes are used for boards designed for semiconductor chip (die) attachment, wire bonding, and plating solder (leaded) glass devices due to their solderability and weldability. These qualities comply with Types I and III of MIL-G-45204. The processes are neutral (pH 6 to 8.5) or acid (pH 3 to 6). Pulse plating is frequently used. Table 2.24 gives typical conditions for a neutral bath. Alkaline, noncyanide gold. Various processes for alloy and pure gold deposits are available. Solutions are based on sulfite-gold complexes

TABLE 2.23

Operation and Control of Acid Au-Co Alloy Manual

Gold content, troy oz/gal pH Cobalt content Temperature Solution density Replenishment per troy oz gold Current efficiency Agitation Anode-to-cathode distance Anodes, composition Cathode current density Thickness Deposition rate for 40 µin. Deposition composition Hardness

Automatic

0.9–1.1 4.2–4.6 800–1000 ppm 90–110°F 8–15 Be 8 Ah 50% 5 gal/min 2–3 in. Platinized titanium 1–10 A/ft2 40 ⫾ 10 µin. 3–6 min Au99.8-Co0.2 150 Knoop

1–3 4.5–5.0 800–1200 ppm 100–125°F 12–18 Be 6.5 Ah 60% 50 gal/min 1 ⁄4 in. Platinized titanium 50–100 A/ft2 40 ⫾ 2 µin. 0.3–0.6 min Au99.8-Co0.2 150 Knoop

Gold solution contaminants Metal Lead Silver Chromium Copper

Maximum ppm

Metal

Maximum ppm

10 5 5 50

Iron Tin Nickel

100 300 300–3000

Organics: tape residues, mold growth, and cyanide breakdowns.

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TABLE 2.24

Operation and Control of Neutral Pure Au

Gold content pH Temperature Agitation Solution density Replenishment Current efficiency Cathode current density Deposition rate for 100 µin., 5 A/ft2 Deposit composition Hardness

0.9–1.5 troy oz/gal 6.0–7.0 150°F Vigorous 12–15 Be 4 Ah/troy oz 90–95% 1–10 A/ft2 8 min Au99.99 60–90 Knoop

and arsenic additives and operate at a pH of 8.5 to 10.0. A decision to use this process is based primarily on the need for uniformity (leveling), hardness (180 Knoop), purity, reflectivity, and ductility. PCB use is limited to body plating, since the wear characteristics of sulfite-gold are not suitable for edge connector applications. The microelectronics industry uses these processes for reasons of safety and gold purity. Semiconductor chip attachment, wire bonding, and gold plating on semiconductors are possible applications and are enhanced by using pulse plating without metallic additives. 2.4.3.7 Silver electroplating. Silver is not widely used in the PC industry, although it finds applications in optical devices and switch contacts. Thicknesses of 0.0001 to 0.0002 in. (0.1 to 0.2 mil) in conjunction with a thin overlay of precious metal are specified. Silver plating should not be used when boards are to meet military specification. The reason for this is that, under certain conditions of electrical potential and humidity, silver will migrate along the surface of the deposit and through the body of insulation to produce low-resistance leakage paths. Tarnishing of silver-gold in moist sulfide atmospheres also produces electrical problems on contact surfaces due to diffusion of the silver to the surface. Another reason for the lack of acceptance of silver is that silver is plated from an alkaline cyanide bath, which is highly toxic. Bright plating solutions produce deposits with improved tarnish and corrosion resistance, relative freedom from porosity, and greater hardness. Plating troubles are usually related to black anodes and are due chiefly to solution imbalance, impurities in anodes, or solution roughness and pitting. Most metals to be plated, particularly the less noble metals, require a silver strike prior to silver plating to ensure deposit adhesion. 2.4.3.8 Immersion and electroless plating. Interest in these methods has increased due to their ability to produce coplanar (flat and even pad-to-

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pad) surfaces required for fine-pitch, surface-mount devices (SMDs). In effect, these systems offer alternatives to hot-air solder leveling and tinlead alloy plate fusing. These processes are nonelectrolytic. Immersion tin. Immersion tin remains in widespread use to clean boards after etching, to cover copper trace edges with tin, and to act as a soldering aid. Self-limiting by nature, immersion tin processes work by displacement of the copper substrate. Deposits are thin—about 30 µin.—and must be processed immediately for effective results. Aging and thermal excursions cause the growth of the copper-tin intermetallics, which degrades solderability. In addition, tin readily forms a thick oxide when exposed to high temperatures and humidity. Electroless nickel. Electroless nickel (EN) followed by immersion or electroless gold also provides coplanar pad surfaces for SMDs. Electroless nickel is an autocatalytic process that utilizes a reducing agent such as hypophosphite or borohydride. Hypophosphite is the preferred choice for printed circuits. Deposition rate from a bath at pH 4.4 to 5.2 is 1⁄2 to 1 mil/h. The deposit contains 9 to 13 percent phosphorus. EN provides wear resistance, hardness, and excellent uniformity. Thicknesses of 50 to 250 µin. are specified when EN is used as a diffusion barrier between gold and copper. Immersion gold. Immersion gold systems deposit a maximum of 4 to 12 µin. of gold over nickel. Additional gold thickness must be applied by an electroless gold system.

Processes are reported that are capable of depositing 0.5 to 4 mil gold on immersion gold and gold-isolated circuitry by true electroless (autocatalytic) means. These systems contain organic amine boranes and borohydride reducing agents and cyanides and operate at a high pH and temperature. Deposition rate is 80 µin./h. Deposits meet the requirements of MIL-G-45204, Type III, Grade A with 99.9 percent purity and hardnesses of 90 KHN. They are suitable for edge connectors, semiconductor wire bonding, and die attachment. Electroless gold.39

Organic solderability preservatives (OSPs). The OSP processes (also known as prefluxes) are applied to bare copper surfaces after solder mask. Generally, these flat surfaces provide reliable solderability after thermal excursions such as adhesive curing, solder past reflow, and wave soldering, and provided they are adequately protected from oxidation. The OSP must be thermally stable and provide corrosion protection. Options for OSP systems include chemistry based on substituted azoles and rosin/resin bases. The coatings can generally be applied in immersion, spray, or flood mode. The coatings must bind to copper, preventing humidity and high temperatures from degrading solderabil-

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ity, and must be compatible with no-clean assembly fluxes. Proper surface preparation of the boards is required for OSP coatings to be effective. An alternative to this process is the use of benzotrizole. However, this is an extremely thin coating that gives very limited protection against oxidation and moisture. Improved protection can be achieved by following the benzotrizole step with posttreatment of a preflux. The preflux will prevent moisture penetration.40 Both solvent-based and water-based prefluxes are available. The following points should be considered when deciding on alternative coatings previously described. 1. Ease of assembly. Fine-pitch technology may require immersion tin or other electroless plating systems. Mixed-technology boards may be better suited for OSP coatings. 2. Rework and handling. OSP coatings are the easiest to rework but are the most fragile compared to metallic systems. OSPs can be removed with organic solvents or with 5 percent hydrochloric acid if the OSP is a water-based structure. 3. Shelf life. The shelf life of immersion, electroless-plated, and OSP coatings is not as long as that of leveled or fused solder surfaces. Storage time should be kept to a minimum for alternative coatings. 2.4.4 Etching processes

One of the major steps in the chemical processing of subtractive printed boards is etching (removal of copper) to achieve the desired circuit patterns. Etching is also used for surface preparation with minimal metal removal (microetching) during inner-layer oxide coating and electroless or electrolytic plating. Technical, economic, and environmental needs for practical process control have brought about major improvements in etching techniques. Batch-type operations, with their variable etching rates and long downtimes, have been replaced with continuous, constant-etch-rate processes. In addition, the need for continuous processing has led to extensive automation along with complete, integrated systems. The most common etching systems are based on alkaline ammonia, hydrogen peroxide–sulfuric acid, and cupric chloride. Other systems include persulfates, ferric chloride, and chromic-sulfuric acids. Process steps include resist stripping, precleaning, etching, neutralizing, water rinsing, and drying. This chapter describes the technology for etching high-quality, fine-line (0.004 to 0.006 in.) circuits in high volume at a lower cost, as well as closed-loop continuous processing, constant etch rates, control at high dissolved copper capacities, regenerationrecovery, less pollution, and increased safety. Problems of waste dis-

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posal and pollution control have been minimized by adapting these principles. Typical procedures are given for etching organic (i.e., dry film) and metal-resist boards, and for inner layers. Strippers and procedures for resist removal are described based on resist selection, cost, and pollution problems. The properties of available etchants are also described in terms of finish plate compatibility, control methods, ease of control, and equipment maintenance. Other considerations include chemical and etchant effects on dielectric laminates, etching of thin-clad copper and semiadditive boards, SMOBC, equipment selection techniques, production capabilities, quality attained, and facilities. 2.4.4.1 General etching considerations and procedures. Good etching results depend on proper image transfer in both organic inner layer print-and-etch and plated-metal etch resists. Etch personnel must be familiar with screened, photosensitive, and plated resists commonly used. The etching of printed boards must begin with suitable cleaning, inspection, and pre-etch steps to ensure acceptable products. Plated boards also require careful and complete resist removal. The steps after etching are important because they are necessary to remove surface contamination and yield sound surfaces. This discussion considers the various types of resists and outlines typical procedures used to etch printed boards using organic and plated resist patterns. Screened resists. Screen printing is a common method for producing standard copper-printed circuitry on metal-clad dielectric and other substrates. The etch resist material is printed with a positive pattern (circuitry only) for copper etch-only boards or with a negative image (field only) when plated through-holes and metal resist are present. The type of resist material used must meet the requirements for proper image transfer demanded by the printer. From the metal etcher’s point of view, the material needs to provide good adhesion and etch solution resistance; be free of pinholes, oil, or resin bleed-out; and be readily removable without damage to substrate or circuitry. Typical problems are excessive undercutting, slivers, unetched areas, and inner-layer shorts in multilayer boards. In addition, conductor line lifting may occur when the copper-to-laminate peel strength is below specification. Hole plugging. Plugged-hole, copper-only boards use alkaline-soluble screen resists in a unique manner. The technique, called hole plugging, makes the SMOBC board possible. UV-cured screen resists. Ultraviolet-cured solventless systems are available for print-and-etch and plating applications. These products are resistant to commonly used acidic plating and etching solutions. Stripping must be evaluated carefully.

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Photoresists. Dry film and liquid photoresist materials are capable of yielding fine-line (0.004 to 0.006 in.) circuits needed for production of surface-mount circuit boards. Like screened resists, photosensitive resists can be used to print either negative or positive patterns on the metal-clad laminate. Although dry film and liquid materials differ in both physical and chemical properties, they will be considered together for our purpose. In general, both positive- and negative-acting resists offer better protection in acidic rather than alkaline solutions; however, negative-acting types are more tolerant of alkaline solutions. Negative resists, once exposed and developed, are no longer light-sensitive and can be processed and stored in normal white light. The positive resists remain light-sensitive even after developing and must therefore be protected from white light. Liquid photoresists, although less durable, are capable of finer line definition and resolution. Positive-acting resists are subject to the same problems as are negative-acting resists, although they are easier to remove cleanly, after exposure, from areas to be etched or plated. Plated etch resists. At present, the most extensive use of metal-plated resists is found in the production of double-sided and multilayer plated through-hole circuit boards. The most commonly used resists are solder plate (Sn60-Pb40), tin, nickel, tin-nickel, and gold. Silver is used to some extent for light-emitting and liquid crystal applications. Etching of the metal-resist-plated boards begins with removal of the resist using commercial solvents and strippers. Gold, solder, and tin resists must be handled carefully because they scratch very easily. Tinnickel alloy and nickel plate, however, are very hard and resistant to abrasion. The procedure after etching includes thorough water rinsing and acid neutralizing to ensure removal of etchant residues on the board surface and under the traces. Alkaline etchants are followed by treatment with proprietary ammonium chloride acidic solutions, ferric and cupric chloride with solutions of hydrochloric or oxalic acid, and ammonium persulfate with sulfuric acid. Alkaline cleaning is used for tinlead boards etched in chromic-sulfuric acid. Etchant residues not removed before drying or reflow result in lowered electrical resistance of the dielectric substrate and in poor electrical contact and soldering on the conductive surfaces.

Resist removal. The method used for resist stripping is important when a resist is selected. The effect on board materials, cost and production requirements, and compliance with safety and pollution standards must be taken into account. Both aqueous and solvent stripping systems are widely used.

2.4.4.2

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Screen resist removal. Alkali-soluble resist inks are generally preferred. Stripping in the case of thermal and UV-curable resists is accomplished in 2 percent sodium hydroxide or in proprietary solutions. The resist is loosened and rinsed off with a water spray. Adequate safety precautions must be taken, since caustics are harmful. Conveyorized resist-stripping and etching machines use highpressure pumping systems that spray hot alkaline solutions on both sides of the boards. Single-sided boards and certain laminate materials such as the polyimides may be attached by alkaline strippers. Measling, staining, or other degradation is noted when strippers attack epoxy or other substrates. Screened vinyl-based resists are removed by a dissolving action in solutions of chlorinated, petroleum, or glycol ether solvents. Methylene chloride and toluene are used extensively in cold stripper formulations.41 Commercial cold strippers are classified according to their pH in a 10 percent stripper-water mixture. The most common strippers are acidic formulations that contain copper brighteners and swelling, dissolution, and water-rinsing agents. The usual procedure for static tank stripping involves soaking the coated boards in at least two tanks of stripper. Excessive time in strippers is to be avoided because of attack on the “butter” (top epoxy) coat, especially on print-and-etch or singlesided boards. Water is a contaminant in most cold strippers. Solvent stripping machines are commercially available. High-volume users save costs by using conveyorized systems equipped with reclamation and pollution-control facilities. Distillable cold strippers generally contain methylene chloride or trichloroethylene (TCE). Some heating may be used, but only in closed systems because of health and fire hazards. In all cases, proper safety, ventilation, pollution control, and certified waste disposal must be provided. Methylene chloride, toluene, and TCE are priority pollutants (TTO) regulated by the Environmental Protection Agency (EPA). Alternatives to methylene chloride are available as glycol ethers. Photoresist removal. Dry-film resists have been formulated for ease of removal in both aqueous-alkaline and solvent solutions. Strippers of each type are available for both static tank and conveyorized systems. Cold stripper solvent-type formulations are similar to those used on vinyl screen inks in which the primary solvent is methylene chloride.42 Aqueous-alkaline stripping results in undissolved residues of softened resist films. These residues can be captured in a filter system and disposed of in accordance with waste disposal requirements. Negative-acting, liquid-applied photoresist can be readily removed from printed boards that have not been baked excessively. Baking is critical to removal because it relates to the degree of polymerization.

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Since overbaking is also damaging to the insulating substrates, processes should stress minimal baking—only enough to withstand the operations involved. The negative-acting resists are removed by using solvents and commercial strippers. In this case, the resist does not dissolve; instead, it softens and swells, breaking the adhesive bond to the substrate. Once this has taken place over the entire coated area, a water spray is used to flush away the film. Positive-acting photoresists are removed by dissolving in acetone, ketone, cellusolve acetate, or other organic solvents. Commercial organic and inorganic strippers are suitable if baking has not been excessive. Removal by exposure to UV light and subsequent dipping in sodium hydroxide, trisodium phosphate (TSP), or other strong alkaline solutions is also effective. Overbaking also makes removal difficult. Machine stripping is done in a solution of 0.5 N sodium hydroxide, nonionic surfactants, and defoamers. 2.4.4.3 Etching solutions. This section is a survey of the technology and chemistry of the copper etching systems in common use. Changes from batch-type operation to continuous constant-rate systems with increased process automation represent major innovations in etching practices. Problems encountered in the control of equipment and etchant solutions are frequently difficult to separate. Often, the utmost in performance and life of the etchant is not attained. A current understanding is needed in the areas of fine-line production, regeneration and recycling of materials, and pollution control. Alkaline ammonia. Alkaline etching with ammonium hydroxide complexing is increasingly used because of its continuous operation, compatibility with most metallic and organic resists, minimum undercut, high capacity for dissolved copper, and fast etch rates. Both batch and continuous (closed-loop) spray machine systems are in use. Continuous operation provides constant etch rates, high work output, ease of control and replenishment, and improved pollution control. However, costs are relatively high, neutralization after etching is critical, and the ammonium ion introduced into the rinses presents a difficult waste treatment problem. Complete regeneration with chemical recycling is not routinely practiced. Sulfuric acid–hydrogen peroxide. Sulfuric-peroxide systems are used extensively for copper surface preparation (microetching), i.e., for oxide coating of inner layers, and for electroless and electrolytic copper plating. The reasons for this wide acceptance are the ease of replenishment, simple waste treatment needed, closed-loop copper recovery, and optimum surface texture of the copper. In addition to these advantages, the compatibility of these systems with most organic and metallic resists,

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their steady etch rates, and the optimum undercut they provide make them especially suited to be used as final etch step. Both tank immersion and etching systems are commercially available. Continuous processing equipment is also available for the electroplating-throughetching operations. Cupric chloride. Cupric chloride systems are typical of the innovations to achieve closed-loop regeneration, lower costs, and a constant, predictable etch rate. Steady-state etching with acidic cupric chloride permits high throughput, material recovery, and reduced pollution. Regeneration in this case is somewhat complex but is readily maintained. Dissolved copper capacity is high compared with that of batch operation. Cupric chloride solutions are used mainly for fineline multilayer inner details and print-and-etch boards.43 Resists are screened inks, dry film, gold, and tin-nickel. Solder and tin boards are not compatible with cupric chloride etchant. Persulfates. Ammonium, sodium, and potassium persulfates modified by certain catalysts have been adopted for the etching of copper in PC manufacturing. Continuous regenerative systems and a batch system using ammonium persulfate are common. Wide use is made of persulfates as a microetch for inner-layer oxide coating and copper electroless and plating processes. Persulfate solutions allow all common types of resists on boards, including solder, tin, tin-nickel, screened inks, and photosensitive films. Persulfate solutions are not suitable etchants for gold because of excess undercut and low etch factors. Formulations of ammonium persulfate catalyzed with mercuric chloride have etch rates comparable to those of the chloride etchants and are preferred for solder, print-and-etch, and tin-nickel boards. Formulations with proprietary additives other than mercury catalysts are available and have been improved to give good etch factors. Regenerative systems have made possible higher copper capacities and constant etch rates. In general, persulfate etchants are unstable and will exhibit decomposition, lower etch rates versus copper content, and lower useful copper capacity. The use of persulfate etching systems has declined recently because of high costs and other improvements in alkaline ammonia etchants. Ferric chloride. Ferric chloride solutions are used as etchants for copper, copper alloys, Ni-Fe alloys, and steel in PC applications, electronics, photoengraving arts, and metal finishing. Ferric chloride is used with screen inks, photoresist, and gold patterns, but it cannot be used on tin-lead or tin-plated boards. However, ferric chloride is an attractive spray etchant because of its low cost and its high holding capacity for copper.

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The composition of the etchant is mainly ferric chloride in water, with concentrations ranging from 28 percent to 42 percent by weight (see Table 2.25). Free acid is present because of the hydrolysis reaction. This HCl is usually supplemented by additional amounts of HCl (up to 5 percent) to hold back the formation of insoluble precipitates of ferric hydroxide. Commercial formulations also contain wetting and antifoam agents. The effects of ferric chloride concentration, dissolved copper content, temperature, and agitation on the rate and quality of etching have been reported in the literature.41 Commercial availability includes lump FeCl3⋅6H2O and aqueous solutions with and without additives. Ferric chloride with additives has the advantage of low foaming (reduced odor and fuming), fast and even etching (due partly to added strong oxidizers and surface-wetting properties), and reduced iron hydroxide precipitate formation, owing to the slight acidity and to the chelating additives. The useful life of ferric chloride etchants and the uniformity of etching rates have been greatly improved by the manufacturers of proprietary solutions. Chromic-sulfuric acids. These etchants for solder- and tin-plated boards were preferred for many years. More recently, their use has been limited drastically because of the difficulty in regeneration, the inconsistent etch rate, the low limit of dissolved copper (4 to 6 oz/gal), and especially the pollution concerns. Chromic acid etchant is suitable for use with solder, tin-nickel, gold, screened vinyl lacquer, and dry or liquid film photoresists. Although chromic acid etchants are strong oxidizing agents, they do not attack the solder, since insoluble lead sulfate is formed. Undercut is seen less with solder-plated patterns than with gold and organic resists. Nitric acid. Etchant systems based on nitric acid have not found extensive application in PC manufacture. Copper etching is very exothermic, which may lead to violent runaway reactions. Problems with this system include solution control, attack on resists and substrates, and toxic gas fuming. However, nitric acid has certain advanTABLE 2.25

Composition of FeCl3 Solutions Low strength

Percent by weight Specific gravity Baumé lb/gal g/L Molarity

28 1.275 31.5 3.07 365 2.25

Optimum 34 1.353 38 3.9 452 2.79

38 1.402 42 4.45 530 3.27

High strength 42 1.450 45 5.11 608 3.75

Data taken at 68–77°F (20–25°C). Photoengraving FeCl3 42° Baumé has 0.2–0.4% free HCl. Proprietary etchants contain up to 5% HCl.

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tages. These include rapid etching, high dissolved copper capacity, high solubility of nonsludging products, easy availability, and low cost. 2.4.4.4 Equipment and techniques. Etching techniques and the equipment used today have evolved from four basic etching methods: immersion, bubble, splash (paddle), and spray etching. Spray etching is the most common method, since it is fast, well suited to high production, and capable of very fine line definition. Spray techniques include single- and double-sided etching with either horizontal or vertical positioning of the boards. These techniques yield high etch factors and short etching times, due in part to high solution controls and to the introduction of high quantities of air. As in all etching procedures, however, the highest definition (fine-line patterns) or the use of thicker copper foils requires control of the undercutting by careful selection of equipment and etchants. Spray-etching machines have evolved simultaneously with the availability of chemical-resistant metals and plastics essential to their construction (polyvinyl chloride [PVC] and titanium alloys). Titanium is suitable for constant use in all common etchants except sulfuric acid–hydrogen peroxide, which requires stainless steel materials. Polycarbonate, polypropylene, and Hastelloy C alloys are also used. Automatic vertical etching. This type of machine is designed for higher production rates. A mechanism carries a loaded rack through the etch chamber, where it is sprayed on one or both sides by oscillating banks of spray nozzles. The rack goes through water (spray-rinse) and neutralizing chambers. Cooling coils are available for sulfuric-peroxide etchants. Control of pressure to each bank of spray nozzles and on-off valves provide additional versatility. The etchant sump has a larger volume of etchant than drawer-type vertical etchers, as well as a capability for continuous replenishment. Fine-line etching is attainable when spray nozzles, pressure, speed, and other variables are working optimally. Horizontal etching. Double-sided horizontal etchers are generally preferred in PC manufacturing, since the majority of the boards are twosided. The etcher is available with a drawer-type holding rack and also has a built-in sink at the left of the chamber. The etch operation proceeds and automatically pushes the rack into the rinse area after a timed cycle. Etching is done via independently controlled spray-nozzle banks at the top and bottom. Automatic horizontal etching machines. Made for high-volume production, these machines incorporate the features previously listed for horizontal machines, plus the advantages of conveyorized loading and han-

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dling of boards up to 36 in. wide and of indefinite length, as well as built-in rinsing and neutralizing. In operation, machines are loaded by laying boards flat on an open horizontal conveyor belt that carries them progressively through the etch chamber and subsequent rinses. Rollers on conveyor belts are spaced so as to allow the bottom spray to reach the board. Automatic equipment is available for flow-through solution replenishment, which gives constant etch rates. 2.5 Solder Resist Materials and Processes IPC-T-50b defines a solder resist (mask) as “a coating material used to mask or to protect selected areas of a printed circuit board (PCB) from the action of an etchant, solder, or plating.” A somewhat more useful working definition for a solder resist is as follows: a coating that masks off a printed circuit board surface and prevents those areas from accepting any solder during reflow or wave soldering processing (see Fig. 2.25). The prime function of a solder resist is to restrict the molten solder pickup or flow in those areas of the PCB, holes, pads, and conductor lines that are not covered by the solder resist. PCB designers, however, often expect more functionality out of the solder resist than just a means to restrict the solder pickup. Table 2.26 lists the functions of a solder resist. 2.5.1 Design considerations for solder resists

The design goals for the selection and application of a solder resist should be carefully considered. As with all design goals, one should try to achieve maximum design flexibility, reliability, and functionality at a cost consistent with the required level of system performance. The system’s performance and reliability requirements are the keys in determining the selection process for a solder resist. Critical life-support systems will require different materials and standards than a less critical system such as a video cassette recorder (VCR).

Figure 2.25

Major features of solder resist on a PCB.

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99

Functions of Solder Resists

Reduce solder bridging and electrical shorts Reduce the volume of solder pickup to obtain cost and weight savings Reduce solder pot contamination (copper and gold) Protect printed circuit board (PCB) circuitry from handling damage, i.e., dirt, finger prints, etc. Provide an environmental barrier Fill space between conductor lines and pads with material of known dielectric characteristics Provide an electromigration barrier for dendritic growth Provide an insulation or dielectric barrier between electrical components and conductor lines or via interconnections when components are mounted directly on top of the conductor lines

Table 2.27 outlines some of the factors to consider in the design process when selecting a solder resist. It is not very likely that a single solder resist material or application technique will satisfy all the design considerations that are viewed as necessary. It should also be noted that not all the design factors listed in Table 2.27 carry the same weight or value, so the designer needs to prioritize those design factors, analyze the necessary trade-offs, and then specify the solder resist material and process that gives the best balance of properties or characteristics. 2.5.2 Solder resist selection

The solder resists available are broadly divided into two categories, i.e., permanent and temporary. The breakdown of the solder resist types is shown in Fig. 2.26. The permanent solder resist materials are classiTABLE 2.27

Design Factors for Solder Resists

Criticality of system’s performance and reliability Physical size of PCB Metallization on PCB, i.e., SnPb, copper, etc. Line and space (density) of PCB Average height of conductor line (amount and uniformity of the metallization) Size and number of drilled PTHs Annual ring tolerance for PTHs Placement of components on one or both sides of PCB Need to have components mounted directly on top of conductor line Need to tent via holes in order to keep molten solder out of selected holes Need to prevent flow of solder up via holes, which may have components sitting on top of them Likelihood of field repair or replacement of components Need for solder resist to be thick enough to contain the volume of solder needed to make good solder connections Choice of specifications and performance class that will give the solder resist properties that are necessary to achieve design goals

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Figure 2.26

Solder resist selection considerations.

fied by the means used to image the solder resist, i.e., screen printing or photoprint. In addition, the screen-printed resists are further classified by the curing technique, i.e., thermal or UV curing. The photoprint solder resists are distinguished from each other by whether they are in the form of liquid or dry film. The temporary resist materials are classified by chemistry or means of development. 2.5.2.1 Temporary resists. A distinction is made between permanent and temporary solder resists. The temporary resists are usually applied to a selected or limited area of a PCB to protect certain holes or features such as connector fingers from accepting solder. The temporary resist keeps solder out of the selected holes and thus allows for certain process- or temperature-sensitive components to be added manually at a later time. The temporary solder resists usually consist of a latex rubber material or any of a variety of adhesive tapes. These materials can be applied by an automatic or manual dispenser. Some of the temporary mask materials dissolve in the solvents or cleaning processes that are used to clean off the soldering flux residues. This is really a benefit, since it eliminates the need for a separate manual removal and/or cleaning step for the temporary resist. 2.5.2.2 Permanent resists. Permanent solder resists are not removed and thus become an integral part of the PCB. The demand for permanent solder resist coatings on PCBs has greatly increased as the trend toward surface mounting and higher circuit density has increased. When the conductor line density was low, there was little concern about solder bridging, but as the density increased, the number and complexity of the components increased. At the same time, the incidence of soldering defects, such as line and component shorts, greatly increased. Inspection, testing, and rework costs accelerated as effort went into locating and repairing the offending solder defects. The additional cost of the solder resist on one or both sides of the PCB was viewed as a cost-effective means to offset the higher inspection, testing, and rework costs. The

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addition of a solder resist also had the added value for the designer of providing an environmental barrier on the PCB. This feature was important and dictated that the materials considered for a permanent solder resist should have similar physical, thermal, electrical, and environmental performance properties to the laminate material. See Table 2.28 for a comparison of properties for permanent solder resist types. 2.5.2.3

Selection factors

General considerations ■

Reliability and performance data on the solder resist material

■

Cost effectiveness

■

Past experience

■

Vendor reliability and technical support

■

Number of panels required

■

Appearance and cosmetics of solder resist

■

Number of sources for application and supply Material considerations

■

IPC-SM-840 class designation callout

■

Cost and availability of materials

TABLE 2.28

Permanent Solder Resist Selection Guide Screen print

Feature Soldering performance Ease of application Operator skill level Turnaround time Inspectability Feature resolution Adhesion to SnPb Adhesion to laminate Thickness over conduct or lines Bleed or residues on pads Tenting or plugging of selected holes Handling of large panel size with good accuracy Meeting of IPC-SM-840 Class 3 specification Two-sided application Capital equipment cost

Dry film

Thermal

UV

Aqueous

Solvent

Liquid photoresist

1 1 2 2–3 2–3 3 1 1 3–4

1 1 2 2–3 2–3 3 3 1–2 3–4

1 2 2 2 3 1 1–2 1 1–2

1 2 2 2 3 1 1–2 1 1–2

1 2 2 2 3 1 1 1 2

3–4 4

3 4

1 1

1 1

1 4

3

3

1

1

1

3–4

3–4

1–2

1

1

4 4

4 4

1 1–2

1 1–2

3–4 1

1 = good or high; 2 = moderate; 3 = fair; 4 = poor or low.

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■

Lot-to-lot consistency record

■

Setup and cleanup times

■

Working time and shelf life of solder resist

■

Safety concern for release of noxious or toxic fumes during processing or curing steps

■

Degree of workability Process considerations

■

Operator skill level requirement

■

Need for special applications or curing equipment

■

Cleaning requirements for PCB before and after application

■

Size of PCB

■

Need for solder resist on one or both sides of PCB

■

Number of panels to be processed

■

Turnaround time required

■

Machinability

■

Need to tent selected holes

■

Touchup or rework limitations

■

Inspectability and conformance to specification Performance considerations

■

Testing to IPC-SM-840 specification requirements

■

Adhesion after soldering and cleaning

■

Bleed-out of resist onto pads or PTHs

■

Solvent resistance to flux and flux cleaners

■

Ionic contamination levels

■

Integrity of resist after soldering and thermal cycling

2.5.3 Solder mask over bare copper (SMOBC)

SMOBC is a major solder resist application technology. A problem for conventional copper-tin-lead electroplated PCBs is the flow of tin-lead solder under the solder resist during the wave or vapor phase or infrared soldering. This flow of molten metal underneath the resist can prevent the resist from adhering to metal or laminate. If the resist fractures because of this hydraulic force, the surface integrity is lost and the effectiveness of the resist as an environmental or dielectric barrier can be severely impaired. In fact, such breaks in the resist can actually

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trap moisture, dirt, and soldering flux and serve as a conduit to direct liquids down to the resist-laminate interface. This solder resist situation could lead to serious reliability and/or performance concerns. The SMOBC process addresses the tin-lead flow problem by eliminating the use of tin-lead electroplating on the conductor lines under the solder resist. An all-copper PTH printed circuit board is often produced by a tent-and-etch process. This process is one in which the PCB is drilled and plated with electroless copper, which is immediately followed by copper panel plating with the full-thickness copper required for the PTHs. A dry-film resist process is often used with a negative phototool (clear conductor lines and pads) to polymerize the resist in only those clear areas of the phototool. This polymerized resist will now protect the lines and PTHs during a copper-etching process that will remove all the unwanted background copper. The photoresist is then stripped off, and the solder resist material is applied and processed through curing. Tin-lead is next added to the open component pads and PTHs by the hot-air leveling process. An alternative process uses conventional procedures to create a pattern-plated board. After etching, however, the metal etch resist is removed chemically, leaving the underlying copper bare. Subsequent process steps are the same as for SMOBC. The primary function of tin-lead in the PTHs and on the component pads is to improve solderability and appearance. It is important to demonstrate the solderability of the holes and pads on the SMOBC panel. This is accomplished by a hot-air leveling process that places a thin coating of molten tin-lead on only those copper areas of the PTH that have not been covered by the solder resist. This hot-air leveling process improves the ability of the copper surface to be soldered and also improves the appearance and solderability after longer-term storage of the PTHs and pad surfaces. Since there is no flowable metal under the solder resist during the hot-air leveling step or later during component soldering, the resist maintains its adhesion and integrity. The lower metallization height of the conductor lines allows the use of a thinner dry-film resist and also makes the liquid and screen-printing application somewhat easier. One variation on the basic SMOBC process is to make the PCB by the conventional pattern-plate copper and tin-lead process followed by etching of the background copper. Then another photoresist step is used to tent the holes and pads so that the tin-lead can be selectively stripped from the conductor lines. This is followed by infrared or oil reflow, cleaning, and application of solder resist. A second process variation strips off the tin-lead plating completely and is followed by cleaning, solder resist application, and hot-air leveling. There are still other PCB fabricators that do not like either of these processes and are opt-

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ing to use a nonflowable, copper-etchant-resistant metal like tin-nickel under the solder resist. The major shortcoming of tin-nickel is that it is considered more difficult to solder with low-activity soldering fluxes. 2.5.4 Cleaning and PCB preparation prior to solder resist application

Optimum solder resist performance and effectiveness can be obtained only if the PCB surfaces are properly prepared prior to the application of the resist. Surface preparation usually consists of a mechanical brush scrubbing for the non-tin-lead PCBs followed by an oven-drying step. The tin-lead PCBs should not be scrubbed and require less aggressive cleaning procedures. The cleaning options prior to solder resist application are shown in Table 2.29. Dry-film and liquid-photopolymer resists applied to meet the IPCSM-840 Class 3 requirements are particularly sensitive to the cleaning processes and baking step used to remove volatiles prior to the application of the resist. Tin-lead-coated PCBs should not be mechanically brush-scrubbed because of the smearing potential of such a malleable metal as tinlead. Scrubbing can cause a thin smear of the metal to be wiped across the substrate, leaving a potentially conductive path or, at a minimum, a decrease in the insulation resistance between the conductor lines. Pumice scrubbing is also unacceptable for tin-lead circuitry, since the pumice particles may become embedded in the soft metal, which can lead to poor soldering performance. Solvent degreasing with Freon or 1,1,1-trichloroethane cleaners is necessary with tin-lead PCBs in order to remove the light process oils from the solder reflow step, dirt, and fingerprints that are usually found on the PCB at the solder resist step. Solvent degreasing will not remove metal oxides or contaminates that are not soluble in the degreasing media. The last step prior to the application of a solder resist to the PCB should be an oven-drying step in which absorbed surface moisture and low-boiling volatiles are removed. This drying step should immediately precede the resist application step in order to minimize the reabsorption of moisture. TABLE 2.29

Preparation for Solder Resists Panel metallization

Operation

Cu

Sn-Pb

Others

Mechanical brush Pumice Solvent degrease Chemical cleaning Oven drying

Yes Yes Yes Yes Yes

No No Yes Yes Yes

Yes Yes Yes Yes Yes

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The most stringent performance specifications will in turn require the most stringent cleaning procedures prior to the resist application. Not all resists and performance specifications require the same degree of cleaning. In certain cases, where performance requirements are less stringent, some screen-printed resists may be used successfully without any particular cleaning or oven-drying steps. 2.5.5 Solder resist applications

Permanent solder resists may be applied to the PCB by any of several techniques or pieces of equipment. Screen printing of liquid solder resists (ink) is the most common; with regard to photoprint solder resists, the dry-film solder resists are applied to one or both sides of the PCB by a special vacuum laminator, and the liquid-photoprint solder resists are applied by curtain coating, roll coating, or blank-screenprinting techniques. 2.5.5.1 Screen printing. Screen printing is typically carried out in manual or semiautomatic screen-printing machines using polyester or stainless steel mesh for the screen material. If solder resist is required on two sides, the first side is coated and cured or partially cured and then recycled to apply the solder resist on the second side using the screen pattern for that side, and then the entire PCB is fully cured. 2.5.5.2 Liquid photoprint. For some liquid-photoprint solder resists, a screen-printing technique is used to apply the resist in a controlled manner to the surface of the PCB. The screen has no image and serves only to control the thickness and waste of the liquid solder resist. There is no registration of the screen, since there is no image. The actual solder resist image will be obtained by exposing the coated PCB using ultraviolet light energy and the appropriate phototool image. The unexposed solder resist areas defined by the phototool are washed away during the development step. Some liquid-photoprint solder resists require a highly mechanized process (roller or curtain coating) and therefore, because of the equipment costs and the setup, cleanup, and changeover costs, are best suited to high-volume production. The liquid solder resists do not tent holes as effectively as the dry-film solder resist materials. 2.5.5.3 Dry film. Dry-film solder resists are best applied using the vacuum laminators that have been designed for that purpose. The equipment removes the air from a chamber in which the PCB has been placed. The solder resist film is held out of contact from the PCB surface until atmospheric pressure is used to force the film onto one or both sides of the PCB.

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The roll laminators that apply the dry-film resists for plating or etching are usually found to be unacceptable for solder resist application. The roll laminators were designed to apply a resist to a smooth, flat surface such as copper foil, and not to a three-dimensional surface such as an etched and plated PCB. Air is usually trapped adjacent to the conductor lines as the lamination roll crosses over a conductor line running parallel to the lamination roll. Entrapped air next to the conductor lines can cause wicking of liquids, which in turn causes reliability and/or performance concerns. The dry-film resist thickness, as supplied, is usually 0.003 or 0.004 in. and will meet the requirement of the Class 3 specification for a 0.001-in. minimum thickness of solder resist on top of the conductor lines. The resist thickness chosen depends on the expected thickness of the copper circuitry to be covered, allowing for filling of the spaces between circuit traces with resist. 2.5.6 Curing

Once the solder mask has been applied to the PCB, it must be cured according to the manufacturer’s recommendations. Typically, curing processes include thermal curing by oven baking or infrared heating, UV curing, or a combination of the two processes. The general objective of the curing process is to remove any volatiles (if present) and to chemically cross-link and/or polymerize the solder resist. This curing toughens the resist to help ensure that it will maintain its integrity during the chemical, thermal, electrical, and physical exposure the PCB will see during its service life. Undercuring, or an out-of-control curing process, is usually the prime cause for solder resist failure. The second leading cause for failure is inadequate cleaning prior to solder resist application. All PCBs should be carefully inspected for defects prior to curing. Once a solder resist has been cured, it is usually impossible or impractical to strip the resist for rework without seriously damaging the PCB. 2.5.7 Liquid photoimageable solder resist (LPISR)

With the advent of SMT in the early 1980s, the requirements for tighter registration of solder mask to circuit features have become ever more demanding. As the lead pitch of SMT components became finer, as illustrated in Table 2.30, conventional thermal and UV-curable screen resists could no longer satisfy the requirements to deposit material completely and consistently between the board features, such as adjacent traces or traces and pads. Although dry-film solder resist (DFSR) is able to satisfy many of these tighter tolerance requirements, it is expensive and sometimes it has difficulty in coverage of spacings

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TABLE 2.30

107

Standard Design Rules for Surface Mount Device Pads (mm) Pad

Kind of SMD

Number of pins

Pitch

SOP (PLCC)

8–28

1.27

QFP

64 80 100 48 224 300

1.0 0.8 0.65 0.5 0.4 0.3

Solder mask

Width

Space

Clearance

Width

0.5–0.6

0.77–0.67

0.1–0.15

0.37–0.57

0.6–0.7

0.67–0.57

0.1–0.15

0.27–0.47

0.6 0.5 0.35 0.3 0.22 0.15

0.4 0.3 0.3 0.2 0.18 0.15

0.135 0.085 0.085 0.05 0.05 0.04

0.2 0.13 0.13 0.1 0.08 0.07

PLCC: plastic leaded chip carrier. SOURCE: NEC Corporation.

between tightly formed fine-line conductors at their base area, leaving small air pockets that tend to erupt during the soldering operation. Therefore, the use of DFSR has declined as SMT has proliferated and LPISR has gained acceptance. The usage of DFSR seems to be confined to some special cases when requirements such as hole tenting, small lot size, and thicker mask (3 mil or more) are present. When Ciba-Geigy introduced the Probimer 52 LPISR system in 1978, SMT was not yet in place and most of the PCB manufacturers were reluctant to adopt it because the cost of the Probimer system was expensive compared to what they were then using. However, some PCB manufacturers catering to the telecommunication industry started to adopt it because of its excellent corrosion resistance; then, as SMT started to gain momentum in the mid-1980s, other solder resist ink makers saw the value of LPISR and followed Ciba-Geigy into the marketplace. Today, there are a great number of LPISR manufacturers offering material and process alternatives, and nearly all SMT boards are coated with LPISR. 2.5.7.1 Panel preparation. Before proceeding with the topic of coating methods, a discussion of panel preparation is appropriate because it is the starting point of all processes. When cleaning copper circuitry for solder mask application, it is important to remove all intermetallic compounds, oxides, and organic and ionic contaminants. A typical cleaning process may consist of the following steps: ■

Acid spray rinse (5 percent hydrochloric acid, for example)

■

Water spray rinse

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■

Mechanical abrasion (jet scrub, pumice scrub, brush scrub, etc.)

■

High-pressure water and deionized water rinse

■

Dry and optional bake at about 160 to 180°F for 30 min

Mechanical abrasion ensures better adhesion of solder resist to copper and helps resist ink to flow into spacings more naturally by removing sharp conductor edges that sometimes block the smooth flow of resist ink. 2.5.7.2 Screen coating. Open screen coating is the simplest entrylevel method for most PCB manufacturers, although screen coating can be very sophisticated when the process is to be automated. Single-sided screen coating. On a worldwide basis, the most popular coating method by far is single-sided open screen coating because it is relatively easy to do successfully and has a low entry cost. By its nature, however, screen coating tends to remove resist ink at the conductor edge that makes the first contact with the squeegee and leave spacings between densely spaced conductors uncovered, whether it is single-sided or the simultaneous double-sided coating to be explained in the next subsection. (Figure 2.27 shows this weakness.) To overcome this weakness, the users of the screen-coating method normally screen the panel twice or even three times to ensure sufficient coverage at conductor edges and spacings, particularly at their bottom area. Users of PCBs usually demand that the thickness of the solder resist be about 0.6 mil (or 0.15 mm) at the edges of the conductors. Simultaneous double-sided screen coating. This method was conceived by a Japanese PCB manufacturer, Satosen, and the hardware implementation was made by another Japanese company, Toshin Kogyo. Depending on the models, double-sided screening equipment can coat between 120 and 180 panels per hour. These screening machines are equipped with back-side scrapers to prevent resist ink from falling into holes.

Figure 2.27

“Skipping” problem associated with screen coating.

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There is another maker of double-sided screening equipment: Circuit Automation. The equipment made by this company is essentially the same as the Japanese machine. However, the Circuit Automation machine, sold under the trade name of DP series, avoids ink getting into holes by moving the screen slightly and changing the skew angle of the squeegee on the second screening. Double-sided screen coating advantages/disadvantages. One major advantage of the double-sided simultaneous screening method is that the panel receives tack-free curing only once, and therefore the degree of cure on both sides of the panel is equal. Single-sided screening makes the first side cure more than the second side, and, in some extreme cases, the colors of the two sides may become different. Double-sided screen coating has one weakness in that it is difficult to screen thin panels. To overcome this problem, the makers of such equipment provide a special frame on which to mount thin panels, which gives tension to the panel and makes screening possible. However, the throughput by the thin-panel version is somewhat reduced due to the more intricate panel-mounting scheme.

2.5.7.3 Curtain coating. Ciba-Geigy introduced the first curtain coating system, the Probimer 52, in 1978. Coates Circuit Products of the United Kingdom followed. Years later, Maas of Germany started to offer curtain-coating equipment, but no resist ink. Figure 2.28 shows a typical fully automated configuration of a curtain-coater line.

Dryer

Coater

Turn-over device (not shown)

Cart

Dryer

vel Tra yor e v n Co

Coater

Cart

Figure 2.28

Typical fully automated configuration of a curtain-coater line.

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The speed of the belt conveyor under the curtain of resist ink determines the thickness of the coating. One pass is sufficient to secure the required coating thickness. The quality of coverage by curtain coating is excellent. Curtain coating can accommodate mixed panel sizes of different thicknesses without any setup change, but it can coat only one side of the panel at a time. Because of the nature of coating, the entire panel surface gets coated. To provide room for tooling holes and test coupons, 15 to 25 percent of the panel area is used as trimming, and resist ink coated on this trimming area is wasted in curtain coating. That is, “useful” ink utilization in curtain coating is usually between 75 and 85 percent. However, the newer curtain coaters have the provisions to block two edges of the panel from being coated, thus improving resist ink utilization. In the early days of curtain coaters, it was difficult to coat thin panels since the leading edge of a thin panel tends to droop down at the end of the fast conveyor belt under the curtain. However, this problem is overcome by a flipping mechanism provided at the end of the conveyor belt. To avoid the “lap-around” effect of resist ink at the leading edge of the panel, the panel is usually fed into the curtain at a slightly skewed angle. Curtain coating can process typically 180 panels per hour; a high-productivity model can handle in excess of 300 panels per hour. The process after coating is more or less the same as in screen coating. Newer types of tack-free curing ovens are made much shorter than the original one, and the entire length of a fully automated line with two curtain coaters in series is no more than 60 to 70 ft. 2.5.7.4

Spray coating

When it comes to the arrangement of spray guns (atomizers), there are also a few variations. In one variation, a single gun sways sideways back and forth, perpendicular to the direction of panel travel. In a second single-gun system, the gun is stationary. In other coaters, two stationary guns are arranged in staggered position. Each one of these gun arrangements has its strength and weaknesses. In electrostatic spray systems, effective grounding is essential for good results. Also, it is important to keep a distance of about half an inch between adjacent panels. If the adjacent panels get closer than this clearance, sparks may be induced at the edges of these panels, leaving uncoated spots. In such a system, the typical coating speed is about 240 panels per hour. Vertical spray systems.

Horizontal spray systems. All horizontal systems coat one side at a time. In most such systems, the panel is tack-free cured before being coated

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on the second side. In some systems, however, the panel is carried on a V belt. After the first side is coated, the panel is flipped and the other side gets coated. In this case, tack-free curing is done only once, but it is difficult to process thin panels in such a system. Thin panels are usually spray coated vertically. Overspray. Unlike screen and curtain coating, spray coating creates an overspray. There are various ways to treat oversprayed ink. In one system, a roll of paper 800 to 1000 yards long is used to absorb oversprayed ink. When the entire length of paper is used up, it is removed and treated for waste disposal. In other systems, a container tank is provided underneath the carrying belt to collect oversprayed ink. When the tank gets filled to a certain level (about once every two to three months), chemicals are added to coagulate the ink, and the coagulated ink is carted away for waste disposal. Curtain-coating and spray-coating methods can process panels of different sizes and shapes without special setup, which is an advantage in dealing with small lot sizes. On the other hand, when panels of mixed sizes are passed through a spray coater, ink utilization can be very poor—as low as 40 percent. Some resist ink manufacturers claim oversprayed ink can be used again by adding solvent, but in reality, reutilization of oversprayed ink is not done because such solvents are not a part of ink formulation and are not compatible with the main ingredients. Spray coating gives the best conformal coverage on the peaks and valleys of the panel surface. Because of this, however, spray coating can create skips in subsequent legend screening when valleys are too low, as illustrated in Fig. 2.29. After years of struggle, ink makers have now corrected this “skipping” problem by formulating spray inks to fill the valleys high.

2.5.8 Tenting holes

All coating methods described so far have one problem in common. None of the methods can effectively and reliably tent holes. Closely

Figure 2.29 Spray coating can create good conformity with circuits, which, however, may cause skipping problems in legend screening.

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placed feed-through holes can cause bridging at the time of soldering. Flux can be entrapped in small holes. Therefore, some users of PCBs demand that the holes be tented or filled with solder mask. Dry-film solder mask can provide tenting, but it is usually expensive and often fails to fill the narrow valleys between tightly spaced conductors. To overcome this difficulty, DuPont came up with a solution with the VALU system, in which the panel is first coated thinly with LPISR and then dry-film solder mask is laminated on top of it. When hole tenting is required in conjunction with screen, curtain, or spray coating, holes are filled with epoxy-based ink by screening after the panel is coated with LPISR. Some PCB manufacturers fill the holes first before coating with LPISR. Such processes add extra cost, but there seems to be no better alternative way to accomplish hole tenting. 2.5.9 Electroless Ni/Au plating issues for solder resists

Hot-air solder leveling (HASL) is the most popular surface finish for SMT. As the density of SMT boards becomes higher, first-pass assembly yields tend to be poorer and repair is very costly and error prone. In recent years, electroless nickel-gold finish has been gaining popularity as an alternative finish to HASL. MLBs for cellular telephone applications and a large portion of Personal Computer Memory Card International Association (PCMCIA) cards (now called PC cards) are finished with electroless Ni-Au plating, which provides excellent protection against oxidation before the soldering operation. Boards with Ni-Au finish can withstand a few soldering cycles without oxidation. Initially, some LPISRs could not withstand the electroless Ni-Au plating operation. Improvements have been made on most LPISRs available in the market to accommodate electroless Ni-Au plating. If a given LPISR is not suitable for electroless Ni-Au plating, LPISR makers offer versions of their resist inks that can satisfy the plating requirement. 2.6 Machining and Routing Laminate machining consists of the mechanical processes by which circuit boards are prepared for the vital chemical processes of image transfer, plating, and etching. Such processes as cutting to size, drilling holes, and shaping have major effects on the final quality of the printed board. This section will review the basic mechanical processes that are essential to producing the finished board. 2.6.1 Punching holes (piercing) 2.6.1.1 Design of the die. It is possible to pierce holes down to one-half the thickness of XXXPC and FR-2 laminates and one-third that of FR-

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3 (Fig. 2.30). Many die designers lose sight of the fact that the force required to withdraw piercing punches is of the same magnitude as that required to push the punches through the material. For that reason, the question of how much stripper-spring pressure to design into a die is answered by most toolmakers: “as much as possible.” When space on the dies cannot accommodate enough mechanical springs to do the job, a hydraulic mechanism can be used. Springs should be so located that the part is stripped evenly. If the board is ejected from the die unevenly, cracks around holes are almost certain to occur. The bestquality holes are produced when the stripper compresses the board an instant before the perforators start to penetrate. If the stripper pressure can be made to approach the compressive strength of the material, less force will be required and the holes will be cleaner. If excessive breakage of small punches occurs, determine whether the punch breaks on the perforating stroke or on withdrawal. If the retainer lock is breaking, the cause is almost certain to be withdrawal strain. The remedy is to grind a small taper on the punch, no more than 11⁄2 in. and to a distance no greater than the thickness of the material being punched. If the grinding is kept within those limits, it will have no measurable effect on hole quality or size. The other two causes of punch breakage are poor alignment, which is easily detected by close examination of the tool, and poor design, which usually means that the punch is too small to do the job required. 2.6.1.2 Tolerance of punching holes. If precise hole size tolerance is required, the clearance between punch and die should be very close; the die hole should be only 0.002 to 0.004 in. larger than the punch for paper-based materials (Fig. 2.31 and Table 2.31). Glass-based laminates generally require about one-half that tolerance. Dies have, however, been constructed with as much as 0.010 all-around clearance between punch and die. They are for use where inspection standards permit rough-quality holes.

Proper sizing and locating of pierced holes for paper laminates.

Figure 2.30

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Figure 2.31 Proper tolerance of a punch and die.

A die with sloppy clearances is less expensive than one built for precision work, and wide clearance between punch and die causes correspondingly more breakage and less shear than a tight die will cause. The result is a hole with a slight funnel shape that makes insertion of components easier. Always pierce with the copper side up. Do not use piercing on designs with circuitry on both sides of the board, because lifting of pads would probably occur. 2.6.1.3 Hole location and size. Designs having holes whose distance from the edge of the board or from other holes approaches the thickness of the material are apt to be troublesome. Such designs should be avoided; but when distances between holes must be small, build the best die possible. Use tight clearance between punch and die and punch and stripper, and have the stripper apply plenty of pressure to the work before the punch starts to enter. If the distance between holes is too small, cracks between holes may result even with the best of tools. If cracks between holes prove troublesome, plan the process so that the piercing is done before any copper is etched away. The reinforcing effect of the copper foil will help eliminate cracks. Most glass-epoxy laminates may be pierced, but the finish on the inside of the holes is sometimes not suitable for through-hole plating. 2.6.1.4 Press size. The size of the press is determined by the amount of work the press must do on each stroke. The supplier of copper-clad TABLE 2.31

Tolerances for Punching or Blanking Paper-Based Laminates

Material thickness To and including 1 ⁄16 in. Over 1⁄16 in. to and including 3⁄32 in. Over 3⁄32 in. to and including 1⁄8 in.

Base material

Tolerance on hole size (in.)

Up to 2 in.

2–3 in.

3–4 in.

4–5 in.

Tolerances for blanked parts, overall dimension (in.)

Paper

0.0015

0.003

0.004

0.005

0.006

0.003

Paper

0.003

0.005

0.006

0.007

0.008

0.005

Paper

0.005

0.006

0.007

0.008

0.009

0.008

Tolerances (in.) on distance between holes and slots (90°F)

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sheets can specify a value for the shear strength of the material being used. Typically, the value will be about 12,000 lb/in2 for paper-based laminate and 20,000 lb/in2 for glass-epoxy laminate. The total circumference of the parts being punched out multiplied by the thickness of the sheet gives the area being sheared by the die.

2.6.2 Blanking, shearing, and cutting of copper-clad laminates Blanking glass-based laminates. Odd shapes that cannot be feasibly produced by shearing or sawing are either blanked or routed. Glass blanking is always done at room temperature. Assuming a close fit between punch and die, the part will be about 0.001 in. larger than the die that produced it. The tools are always so constructed that a part is removed from the die as it is made. It cannot be pushed out by a following part, as is often true when the material has a paper base. If material thicker than 0.062 in. is blanked, the parts may have a rough edge. The life of a punch, pierce, or blank die should be evaluated with reference to the various copper-clad materials that may be used. One way to evaluate die wear caused by various materials is to weigh the perforators, or punches, very accurately, punch 5000 pieces, and then reweigh the punches. Approximately 5000 hits are necessary for evaluation, because the initial break-in period of the die will show a higher rate of wear. Also, of course, the quality of the holes at the beginning and end of each test must be evaluated. Greatly enlarged microphotos of the perforator can be used for visual evaluation of changes in the die.

2.6.2.1

2.6.2.2 Shearing. When copper-clad laminates are to be sheared, the shear should be set with only 0.001 to 0.002 in. clearance between the square-ground blades (Fig. 2.32). The thicker the material to be cut, the greater the rake or scissor angle between the top and bottom shear blade. The converse also is true: The thinner the material, the smaller the rake angle and the closer the blades. Hence, as in many metal shears, the rake angle and the blade gap are fixed; the cutoff piece can be twisted or curled. Paper-based material can also exhibit feathered cracks along the edge that are due to too wide a gap or too high a shear angle. This can be minimized by supporting both piece and cutoff piece during the shear operation and decreasing the rake angle. Epoxy-glass laminate, because of its flexural strength, does not usually crack, but the material can be deformed if the blade clearance is too great or the shear angle is too large. As in blanking, the quality of a part produced from paper-based laminates by shearing can be improved by warming the material before performing the operation.

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Figure 2.32

Typical adjustable shear blades for Cu-clad laminates.

2.6.2.3 Sawing glass-based laminates. When glass-based laminates are to be sawn, carbide-tooth circular saws can be used; but unless the volume of work is quite low, the added investment required for diamondsteel-bonded saws will be paid for in future savings. The manufacturer’s recommendation for saw speed should be followed; usually it will be for a speed in the neighborhood of 15,000 ft/min at the periphery of the saw blade. When economics dictate the use of carbide-tooth circular saws for cutting glass, use the instruction previously given for paper-based laminates (see Fig. 2.33 for tooth shape) and remember that each caution regarding runout, vibration, and alignment becomes more important when glass-reinforced laminates are sawn. 2.6.3 Routing

Modern circuit board fabricators rely principally on routing to perform profiling operations. The high cost and extended lead times for blanking dies, combined with the problem of design inflexibility of hard tooling, limit the punching operation generally to very high volumes or designs specific to die applications. Shearing or sawing are limited to

Figure 2.33 Typical saw tooth designs for paper and cloth laminates.

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rectangular shapes and generally are not accurate enough for most board applications. In the modern circuit board fabrication industry, rapid response to customer lead times and economies of universal process application are well served by routing, especially multiple-spindle computer numerically controlled (CNC) routing. Routing consists of two similar, yet vastly different fabrication processes: CNC multiple-spindle routing and manual pin routing. The similarities consist of the use of highspeed spindles, utilizing carbide cutting tools, and generating high cutting rates. 2.6.3.1 Pin routing. Pin routing is a manual routing process utilizing a template machined of aluminum, FR-4 laminate, or a fiber-reinforced phenolic. The template is made to the finished board dimensions and has tooling pins installed to register to the board’s tooling holes. The package (which can have up to four pieces in a stack) is routed by tracking the template against a pilot pin protruding from the router table. The pin height is less than the template thickness. Usually, the machine pilot pin is the same diameter as the router bit and can be offset adjusted to give the operator flexibility in optimizing dimensions. Work should be fed against the rotation of the cutter to prevent the cutter from grabbing. Pin routing can be an economical process when a small generation of boards is profiled, or if the shapes required are relatively simple. For pin routing to be effective, generally a very skilled operator is required to fabricate the template and to route the boards. Outside machine shops can build aluminum route fixtures for each customer application; however, lead times and costs per order must be considered. Pin routing is usually used by small shops not able to invest in the CNC equipment and its associated support, or as a specialty process, offline from CNC routing. In the best pin routing operations, the volumes produced cannot be compared with multiple-spindle routing. 2.6.3.2 CNC operation. CNC router equipment has the ability to process high volumes of circuit boards very accurately and economically, yet it is coupled with features to enable quick program and setup. This coupling enables the same processing used for high volume to be utilized for prototypes and short-lead-time production. With circuit board data files so universally available, the part programming time has dropped to a few minutes, as opposed to the hours it once took, while setups remain at about 15 to 20 min, plus cutter labyrinth and first article routing. Router operation consists of multiple spindles (two to five) capable of operating at 6,000 to 36,000 rpm or more. The router path (x-y table

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movement and spindle plunge and retract) is determined by program. This permits any number of paths and any location. The preferred method of registration of the panel to the machine table is to use the full panel and the tooling holes previously drilled. Tooling holes internal to the part provide for the highest accuracy, although manufacturing panel tooling may be used if considered earlier in the process. 2.6.3.3 Tooling. To simplify tooling and expedite loading and unloading operations, effective hold-down and chop-removal systems should be provided as part of the machine design. Various methods may then be devised to mount the boards to the machine table while properly registering them to facilitate routing the outline. Some machine designs will have shuttle tables available so that loading and unloading may be accomplished while the machine is cutting. Others will utilize quick-change secondary tooling pallets or subplots that allow rapid exchange of bench-loaded pallets with only a few seconds between boards. Tooling plates. Tooling plates utilize bushings and a slot on the centerline of the active pattern under each spindle. They are doweled to the machine table (Fig. 2.34). The plates may be made by normal machine shop practice, or the router may be used to register and drill its own tooling plate. Mounting pins in the tooling plate should be light slip fit. Subplates. Subplates should be made of Benelax, linen phenolic, or other similar material. Subplates should have the pattern to be routed cut into their surfaces. The patterns act as vacuum paths and aid in chip removal. Part-holding pins should be an interface fit in subplates and snug to loose fit in the part, depending on cutting technique used (Fig. 2.35). It is recommended that the programmer generate the tool-

Figure 2.34

Typical tooling of numerically controlled routing.

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Tooling schematics for numerically controlled routing.

Figure 2.35

ing and hold-down pinholes in addition to the routing program. That will provide absolute registration between the tooling holes and the routing program. 2.6.4 Scoring

Scoring is a circuit board fabrication method used to make long, straight cuts quickly, and therefore it is often used to create rectangular profile board shapes. More commonly, however, it is used in concert with CNC routing for complex shapes, enabling each tool to be used to its unique advantage. When used with routing, scoring has a much wider application and can provide simple breakaway for complex profiles (Fig. 2.36). 2.6.4.1

Operation. Two major types of panel scoring systems are

available:

Scoring process. (a) Typical scoring lines and routed corners. (b) Scoring lines and routed complex features.

Figure 2.36

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■

Dedicated CNC scoring machines utilizing high-speed carbide or diamond-embedded cutter blades, operating as a pair, one on each side of the board. This generates the V groove on each side simultaneously.

■

Drills or driller/routers equipped with scoring software and spadetype carbide bits, generating score lines on one side of the panel at a time (Fig. 2.37).

Dedicated scoring equipment. The dedicated CNC scoring machines are high-production, precision computer-driven machines. With an exception or two, they utilize blade-type cutting tools of all carbide or with carbide inserts, as well as diamond-embedded varieties, and are designed to self-center the panel. The panel feed rate is high due to the blade’s ability to operate at highsurface-feet cutting rates. Scoring both sides simultaneously with one pass contributes greatly to elevated production processing. This equipment utilizes pin or edge registration, with positioning of score lines and steps by programmed instructions. The vertical adjustment of the cutter blades permits variation in V groove depth, and on many models jump scoring is available. The ability to do jump scoring, or score/no-score segments along a simple line at desired points, is programmable. Multiple-role machines. Scoring with CNC drillers or driller/router machines equipped with scoring software produces score lines only on one side of the panel per machine cycle, although each spindle can be used. The panel and program data must be flipped to score the second side. The panel registration method is similar to that of routing, using existing tooling holes to pin the panel to the machined tooling plates. The tooling plates must be machined flat to assure uniformity of score depth. Brush-type spindle pressure foot inserts should be used to apply downward pressure during score line cutting. Spade-type carbide tools of various angles and configurations are used in the spindles. Typically, multiple passes (two or three) may be required to produce a clean, uniform score line.

2.6.4.2 Applications. Scoring is accomplished by machining a shallow, precise, V groove into the top and bottom surfaces of the laminate, gen-

Figure 2.37

Double-pin method.

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erally with the use of CNC equipment. The two most significant elements of the score line are as follows: ■

The positional accuracy from the reference feature (usually the registration hole)

■

The depth of the score, which determines the web thickness

The final edges of a scored circuit board are yielded by breaking the panel, or border, at the score line (Fig. 2.38). The angle of the cutting tool is reflected in the V groove geometry, and limiting this angle to 30 to 90° will minimize score line intrusion into traces near the edges of the circuit board. The score line exposes the laminate glass fibers and resin. Measurements from these surfaces will vary greatly, even though the score line is precisely machined (Fig. 2.39). These irregular surfaces will be noticed as dimensional growth and should be considered in design or planning when designated as a scored edge. The dimensional accuracy of the final board is determined by the degree of precision with which the following are performed: ■

Misalignment within ⫾0.003 in. of the score line from the desired location

■

Web thickness within ⫾0.006 in. of the designated dimension

Typically, nominal web thickness is 0.020 in. for 0.060-in.-thick FR-4 boards and 0.014 in. for 0.030-in.-thick FR-4 laminate. For CEM-1 or CEM-3 materials, 0.040-in. and 0.024-in. nominal web thicknesses apply, respectively. These web thickness values enable sufficient module strength to avoid accidental or premature score separation, while providing simple breaking efforts without excessive edge roughness or growth.

Figure 2.38

Cross section of boards showing finished V grooves and break.

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Chapter Two

Figure 2.39

Single-pin method.

2.7 References 1. Coombs, C. F. Jr., Printed Circuits Handbook, 4th ed., McGraw-Hill, New York, 1996. 2. Swiggett, Robert L., Introduction to Printed Circuits, John F. Rider Publisher, Inc., New York, 1956. 3. Senturia, S. D., N. F. Sheppard, H. L. Lee, and S. B. Marshall, “Cure Monitoring and Control with Combined Dielectric Temperature Probes,” Proc. SAMPE, 19(4):22–26, 1983. 4. Kranbuehl, D. E., S. E. Belos, and P. K. Jue, “Dynamic Dielectric Characterization of the Cure Process: LARC-160,” Proc. SAMPE, 19(4):18–21, 1984. 5. Stoll, R., “High Definition Imaging,” PC Fab, 17(6):31, June 1994. 6. Hecht, L., and M. Cibulsky, “Particle Collection Using a Cascade Impactor,” PC Fab, 34, May 1992. 7. Wisnosky, M., “Modeling of Defects in the Print and Etch Process of Printed Circuit Board Manufacturing,” Proc. IEEE Electronic Components & Technology Conference, p. 520, 1986. 8. Moreau, W., Semiconductor Lithography, Plenum Press, New York, pp. 267–281, 1989. 9. Crum, S., “Surface Preparation Process Improvements,” Electronic Packaging & Production, 24, July 1993. 10. Heden, D. J., “Improving Fine Line Resolution with High Intensity Exposure,” PC Fab, 48, December 1987. 11. Deckert, C. A., “Electroless Copper Plating,” ASM Handbook, vol. 5, pp. 311–322, 1994. 12. Murray, J., “Plating, Part 1: Electroless Copper,” Circuits Manufacturing, 25(2):116–124, February 1985. 13. Polakovic, F., “Contaminants and Their Effect on the Electroless Copper Process,” IPC Technical Review, 12–16, October 1984. 14. Blurton, K. F., “High Quality Copper Deposited from Electroless Copper Baths,” Plating and Surface Finishing, 73(1):52–55, 1986. 15. Lea, C., “The Importance of High Quality Electroless Copper Deposition in the Production of Plated-Through Hole PCBs,” Circuit World, 12(2):16–21, 1986. 16. Glasstone, S., Introduction to Electrochemistry, D. Van Nostrand, New York, 1942. 17. Potter, E. C., Electrochemistry, Cleaver-Hume Press, Ltd., London, 1961. 18. Raub, E., and K. Muller, Fundamentals of Metal Deposition, Elsevier, Amsterdam, 1967. 19. Lowenheim, F. A., Modern Electroplating, 3d ed., J. Wiley & Sons, New York, 1974. 20. Safranek, W. H., The Properties of Electrodeposited Metals and Alloys, 2d ed., American Electroplaters and Surface Finishers Society, Florida, 1986. 21. Bard, J., and L. R. Faulkner, Electrochemical Methods: Fundamentals and Applications, J. Wiley & Sons, New York, 1980. 22. Luke, D. A., “Electroplating Copper for Printed Circuit Manufacture,” Circuit World, 13(1):18–23, 1986. 23. Carano, M., “High Speed Copper Plating for Printed Wiring Boards,” Printed Circuit Fabrication, 6(7):1983.

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24. Sullivan, B., “Electroplating Theory and the High Speed Copper Debate,” Printed Circuit Fabrication, 8(8):35–54, 1985. 25. Mattoon, T. R., P. McSwiggen, and S. A. George, “Printed Circuit Plating Bath Process Control,” Metal Finishing, 83: Parts I, II, and III, 1985. 26. Darikh, P. J., “Electro-deposited Copper for Hi-Rel PCs,” Electronic Packaging & Production, 17(3):61–65, 1977. 27. Jawitz, M. W., “Trouble Shooting Manual for Printed Circuit Production,” Insulation/Circuits, 22(4):5–36, 1976. 28. Strickland, G. R., “Pyrophosphate Copper Plating in Printed Circuit Manufacture,” Product Finishing, 4:20–24, 1972. 29. Rothschild, B. F., “The Effect of Ortho-phosphate in Copper Pyrophosphate Plating Solutions and Deposits,” Metal Finishing, 84(1):49–51, 1978. 30. Dini, J. W., H. R. Johnson, and J. R. Helms, “Effect of Some Variables on the Throwing Power and Efficiency of Copper Pyrophosphate Solutions,” Plating, 54(12):1337, 1967. 31. Rothschild, B. F., “Copper Electroplating Systems: An Evaluation,” Electronic Packaging & Production, 15(8):102–107, 1975. 32. Owen, C. J., H. Jackson, and E. R. York, “Copper Pyrophosphate Plating without Additives,” Plating, 54:821–825, 1967. 33. Hayes, L. E., “Organic Additives for Pyrophosphate Copper: Panacea or Poison?” Electronic Packaging & Production, 17:102–104, 1977. 34. Sherlin, D. E., and L. K. Bjelland, “Improve Electrodeposited Copper with Organic Additives and Baking,” Insulation/Circuits, 24(9):27–32, 1978. 35. Price, J. W., Tin and Tin Alloy Plating, Electrochemical Publications Ltd., AYR, Scotland, 1983. 36. Davis, P. E., and E. F. Duffek, “The Proper Use of Tin and Tin Alloys in Electronics,” Electronic Packaging & Production, 15(7), 1975. 37. Kilbury, R. G., “Producing Buried Via Multilayers: Two Approaches,” Circuits Manufacturing, 25(4):30–49, 1985. 38. Reid, Frank H., and William Goldie, Gold Plating Technology, Electrochemical Publications Ltd., AYR, Scotland, 1974. 39. Ali, H. O., and R. A. Christie, “A Review of Electroless Gold Deposition Processes,” Circuit World, 11(4):10–16, 1985. 40. Goldman, P., et al., “Enhanced SMT Solderability with No HASL: Proprietary Treatments for Copper Pads,” IPC Technical Review, December 1990. 41. Murski, K., and P. M. Wible, “Problem-Solving Processes for Resist Developing, Stripping, and Etching,” Insulation/Circuits, February 1981. 42. Deforest, S., Photoresist Materials and Processes, McGraw-Hill, New York, 1975. 43. Gorman, F., “Regenerative Cupric Chloride Copper Etchant,” Electronic Packaging & Production, 43–46, January 1974.

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Source: Microvias

Chapter

3 Microvias by Mechanical Drilling

3.1 Introduction There is a strong global market trend toward handheld devices such as cellular phones and digital personal assistants. While the first challenge was miniaturization and weight reduction, the focus now is on additional features or customer value. Highly prized models combine more and more functions, increasing the complexity of the devices. Examples are integrated cell phones, Internet browsers, global positioning systems, and so forth. This trend coincides with ever shorter product lifetimes and decreasing prices. Hot products used this year will be either obsolete next year, or at best offered at much lower prices. Microvia technology can be successfully applied to achieve higher density and smaller feature sizes. Mechanical drilling covers a wide diameter range while pushing the limits toward smaller via sizes. Conventional mechanical drilling for non-microvias can drill all kinds of PCB materials, such as FR-4, Mitsubishi Gas and Chemical’s BT, General Electric’s GETEK, Hitachi Chemical’s MegTran (FR-4.5), and Matsushita’s MCL-679. There are many equipment vendors supplying various mechanical drilling systems, such as Advanced Controls, ATI, Ching Huei, Datron, Electro Scientific Industries, Inc., Excellon, Hitachi, OZO, Panasonic, Pluritec, Posalux, Sieb & Meyer, Technic, and Yaskawa.1 In general, mechanical drilling is not suitable for forming microvias. However, with innovative technologies of high-speed spindle and numerical control, it is still possible to make small holes at the scale of microvias by mechanical drilling. For instance, Excellon Automation has been developing an NC drilling machine that may form microvias down to 100 µm (4 mil).1 125

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3.2 Mechanical Drilling for Via Formation Mechanical drilling is a proven technology, but still shows a high potential for innovation. High-speed spindles, for example, exceed 250,000 rpm, and high-velocity tables enable axis speeds in excess of 2,000 IPM. Parallel processing of up to eight panels or multiple spindles per panel greatly improves the throughput of the machines and makes the process more cost effective. Higher accuracy, on the other hand, is achieved by implementing “smart” sensor technology. For mechanical drilling of blind vias and microvias, there have been different approaches to control the drilling depth. In the past, accuracy of z-axis control on the order of ⫾50 µm (⫾2 mil) could be achieved, which is not sufficient to form microvias. A breakthrough in depth control technology brought forth a new concept—the electric field sensor (EFS). The EFS generates an electromagnetic field inside of the pressure foot. The drill bit is used as an antenna to sense this field and the output signal is monitored. The monitored signal dramatically changes when the drill bit touches a metal surface, such as the copper layer of the board. The drop of the antenna signal is used to “zero” the z-axis position and drill from this reference position precisely into the board material. This way, a depth accuracy of ⫾5 µm (0.2 mil) can be expected in a manufacturing environment. Additionally, EFS is extremely robust, since it involves neither optical parts that could be disturbed by debris nor mechanical parts that could wear out. The accuracy is not even affected by surface debris. Figure 3.1 shows microvias produced utilizing EFS technology.2 EFS produces nicely shaped vias with straight-angled walls down to 100 µm (4 mil), as detailed in the images in Fig. 3.1. EFS can be used on single-spindle and multiple-spindle machines and can even be retrofitted. Therefore, EFS offers an opportunity to start manufacturing microvias using (existing) mechanical drill equipment. The importance of being able to transit from traditional drilling to microvia formation on existing equipment must not be overlooked. This allows the PCB fabricator to fine-tune upstream and downstream processes (plating, inner-layer alignment, etc.) without having to consider new process variables from the hole formation process itself. If the upstream and downstream processes are understood, faster adoption of a laser via formation tool is possible. 3.3 Comparison Among Various Via Drilling Technologies Currently, NC drilling is the most common process for generating holes in PCB. However, NC drilling is technically limited to hole sizes of 200 µm and up (not really microvias). Although smaller holes may be pos-

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Microvia formation with EFS depth control.

Figure 3.1

sible, these would come at the cost of significant productivity (minimal stack height). In addition, creation of blind vias is virtually impossible where typical dielectric thickness is 50 µm or less.3 In subsequent chapters, several other microvia forming technologies are introduced. Figure 3.2 shows the comparison of inner diameters for vias formed by various technologies.4 Further comparison is given in Table 3.1 as well. It is obvious that all other via-forming methods outperform conventional mechanical drilling. Figure 3.3 illustrates the via profiles with different forming processes.4 Although in general mechan-

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Chapter Three

Figure 3.2 Comparison of via diameters formed by various technologies.

Figure 3.3

Typical via profiles with different forming processes.

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25–50 µm

LPI/dry film

Phototool Developer

Average (3)

Yields/cleanliness Material development

25–50 µm

Material used

Consumables

Process control

Technical challenge

Resolution

Relative rating: 1 = lowest, 5 = highest

Productivity Process development

Medium-high (2)

Dielectric cost

Low-average (4)

Phototool Photoresist Gases

Liquid/film

Low-medium (4)

(2) Coater (liquid only) Laser system (∼$500,000)

(3) Coater (LPI only) Printer Developer

Initial investment

Low (1) 2–3

High (5) 60–120

Laser drill (cladded laminate)

Productivity (panels/h)

Photovia (bare resin)

Comparison of Various SBU Technologies

Items

TABLE 3.1

50–80 µm

Cost Productivity

Average-high (2)

Phototool Photoresist Gases

Single-cladded laminates

Medium (3)

(3) Laser system (∼$500,000)

Low (1) 2–3

Laser drill (coated foil)

50–80 µm

Cost Productivity

Average-high (2)

Phototool Photoresist Gases

Coated foil

High (1)

(3) Laser system (∼$500,000)

Low (1) 2–3

Laser drill (coated foil)

75–100 µm

Cost Productivity

Average-high (2)

Phototool Photoresist Gases

Coated foil

High (1)

(3) Plasma unit ($300,000–400,000)

Low-medium (2) 12–18

Plasma etch (coated foil)

Microvias by Mechanical Drilling

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Microvias by Mechanical Drilling

130

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ical drilling is not suitable for making microvias, compared to other processes this method has the merit of giving good via wall conditions (straight and smooth). Therefore, mechanical NC drilling is still a possible candidate for via formation in some special applications. 3.4 References 1. Lau, J. H., and C. Chang, “An Overview of Microvia Technology,” Circuit World, 26(2): 22–32, January 2000. 2. Kauf, M., L. Ekblad, and H. Martinez, “Mechanical and Laser Via Formation,” Board Authority, 2(2):61–65, July 2000. 3. Numakura, D. K., S. E. Dean, D. J. McKenney, and J. A. DiPalermo, “Micro Hole Generation Processes for HDI Flex Circuit,” Proc. HDI EXPO ’99, pp. 443–450, San Jose, CA, 1999. 4. Lau, J. H., Low Cost Flip Chip Technologies, p. 124, McGraw-Hill, New York, 2000.

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Source: Microvias

Chapter

4 Microvias by Laser Drilling

4.1 Introduction Although lasers have been evaluated for use in the circuit board industry for many years, only since 1995 has laser drilling been used in mass production. As of early 1999, the total number of systems in use was estimated to be in excess of 400 units. The rate of installations is more than 50 percent greater than the previous 12-mo period, a clear indication of the rapid adoption of this technology in the organic substrate fabrication industry. This increase in the popularity of the laser as a via formation tool is due partly to the flexibility of the process and partly to the wide range of circuit board materials that are laser compatible. This provides fabricators with the lowest entry cost to high-density interconnect (HDI) available today. The rapid productivity advances provided by system manufacturers have ensured that laser technology is moving into high volume production, with more microvias formed today by laser than by any other method.1 While mechanical drilling is dominant for through-holes with large diameters, laser via formation is more favorable for blind vias and microvias. At the end of 1999, laser via formation was still limited to only a few products. Worldwide, there were 400 laser systems in production, with 300 of those systems installed in Japan. Between 2000 and 2002, this situation is expected to change dramatically. Estimates predict that 350 million phones will be needed for the cellular market in the course of these 3 years. Production of these 350 million cellular phones will require 2000 laser systems. This number does not even include the growing need for Internet communicators, personal computers, global positioning systems, and other devices.2 131

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4.2 Mechanism of Laser Drilling There are two mechanisms by which the laser removes dielectric materials in the drilling process. These are photothermal ablation and photochemical ablation.1 4.2.1 Photothermal ablation

As is indicated by its name, photothermal ablation is a heating and vaporization process and is generally accomplished by using a laser that operates in the visible or infrared (IR) spectrum, between 500 and 10,600 nm. The absorbed laser energy heats the material, causing it to melt and vaporize. The area around the via is affected by the heat of the process, and the via sidewall is often carbonized, requiring cleaning with an aggressive desmear process before plating. 4.2.2 Photochemical ablation

This mechanism is seen only where photo energies exceed about 2 eV, with laser wavelengths in the ultraviolet (UV) spectrum below 400 nm. These high-energy photons can break bonds at the molecular level in long-chain organic materials.3 The resulting particles, occupying more volume than their original molecules, are forcibly ejected from the via and are usually left as a powder on the substrate surface or are removed by extraction mechanisms. This process is sometimes known as a “cold” process due to the general lack of thermal damage seen around the via. The cleaning process is used optionally, and tends to be less aggressive than that required in photothermal processes. Figure 4.1a shows a via formed with the photochemical process using a UV laser, which contrasts with Fig. 4.1b, a via in the same organic material formed with the photothermal process using an IR laser.

Vias formed with (a) UV laser energy, (b) IR laser energy. Figure 4.1

(a)

(b)

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4.2.3 Combination processes

In practice, the nonhomogeneous nature of printed circuit boards consisting of both organic and inorganic materials often requires that the via formation process with UV lasers be a combination of both photothermal and photochemical processes. Results indicate that UV ablation of inorganic materials (copper and glass) is a thermal process. The shallow penetration depth, high energy absorption, and short pulse of the laser contribute to a fast cutting rate with minimum collateral thermal damage to surrounding materials. 4.2.4 Absorption curves

The key to efficient laser ablation is strong absorption in the target materials at the chosen laser wavelength. Figure 4.2 shows the absorption of some commonly used printed circuit board materials.4 The absorption of resins depends very much on the additives used in their fabrication. They all absorb strongly in the ultraviolet, but have variable characteristics through the visible and infrared, where they can absorb or transmit. Copper foil is a very strong reflector down to about 60 nm, at which point its absorption increases steadily into the ultraviolet. 4.3 Types of Laser Tools for Microvias

4.3.1 CO2 laser

Most of the older installed laser systems are equipped with CO2 lasers only, working in the far IR between 9,600 and 10,600 nm. These systems use the first-generation process invented in Japan, where a CO2 laser is used for drilling of the dielectric material. The CO2 laser beam can be simply focused onto the surface of the substrate via a mask with a projection lens. A variant of the first-generation process is the CO2 ablation of unclad rigid or RigiFlex material that lends itself well to reel-to-reel applica-

Strong absorption in all materials

UV

VISIBLE

IR

Resins vary in th based on additives be almost transpa

Total Absorption

1 0.9 0.8 0.7 0.6 0.5

FR4 Matte Cu

0.4 0.3 0.2 0.1 0

Glass

Copper is refl

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1 1.1 1.2

Energy absorption curves for FR-4 resin, E-Glass, and matte Cu.

Figure 4.2

Glass is transpa

Wavelength (microns)

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tions. A mask is imaged with a projection lens onto the surface of the material. The via diameter is then defined by the image size of the mask. Due to the long wavelength of the CO2 laser, the minimum size of the vias is also limited to approximately 100 µm (4 mil). The resulting accuracy is limited due to the tendency of unclad materials to stretch/shrink more during the lamination process than do clad materials. In addition, parallel surfaces have to be created to control impedance, and direct dielectric ablation is limited to processing only one single layer.2 To overcome some of the limitations, oxidized copper-clad material can be used to enable the absorption of the CO2 laser. The top copper layer has to be etched down to approximately 5 µm, and a black oxide layer is applied onto the surface. After the via formation process with the CO2 laser, the oxide is removed and the vias are plated. This process involves additional steps for etching, oxidizing, and later removing the oxide. Still, the attainable via diameter is limited by the long wavelength of the CO2 laser to approximately 100 µm (4 mil).2 In RF-excited CO2 laser, the gas plasma is excited by a radio frequency electrical pulse. These lasers are typically sealed units that require no external gas supplies. The rise time of the unmodified laser pulse is around 50,000 to 100,000 ns. To achieve the shorter pulses required to minimize thermal damage, some external modulation of the beam is often required. This limits maximum pulse rates to around 3000 to 4000 pulses per second.1 The transverse excited atmospheric (TEA) CO2 laser uses a highvoltage (12-kV) DC pulse to excite a gas plasma that generates a single large laser pulse. These lasers have been used in the marking industry for many years. The systems require external gas supplies, and fastflow versions of this laser can operate at between 300 and 600 pulses per second. Pulse duration varies between 100 and 1000 ns, depending on the gas mixture. Routine maintenance of these lasers involves replacing electrodes and optical components, making them more expensive to operate than the sealed CO2 units.1 The CO2 lasers have significantly higher productivity for holes larger than 70 µm in diameter. They can ablate more than 15,000 (100-µm diameter) holes through 50-µm-thick dielectric in 1 min. In general, the CO2 laser is used to drill in the dielectric layer and not to drill holes in copper, because the visible wavelength of CO2 is too large to give enough energy to penetrate the copper at high speed. Therefore, additional processing is required prior to drilling. For instance, windows must be selectively pre-etched through the copper foil at positions where holes in the dielectric are to be formed. (This is called the conformal mask method, and it presents the problem of higher costs and limitation of resolution in both vias and circuits.) Recently, Hitachi has

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Microvias by Laser Drilling

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135

shown that with its CO2 laser drilling machine, it can drill through copper foil (<9 µm) by coating a layer of black oxide (called multibond in Japan) or Cobra® onto the copper. Today, the companies that supply the CO2 laser drilling machines are Hitachi, Lumonics, Panasonic (Matsushita), Mitsubishi, and Sumitomo.5 4.3.2 UV:YAG laser

The UV:YAG laser, with smaller wavelengths (255 to 365 nm) and much higher energy, is used to drill holes in the copper and dielectric (the socalled imaging method) at a much lower speed.6 UV:YAG lasers have demonstrated great capability in drilling both dielectric and copper layers, but for both processes the ablation time is proportional to the hole diameter and neither process is therefore competitive above 100-µm diameters. Thus, the YAG laser is the preferred laser for drilling when the hole diameter becomes very small—50 µm, for example. Because YAG lasers also ablate copper, it is more difficult to control the formation of blind vias using a copper stop-pad. Although the speed of the YAG is only one-tenth that of the CO2 laser, when copper is to be drilled through, some makers of high-end MLBs prefer to use the YAG because it does not require that the copper be etched to create windows. Figure 4.3 shows a cross section of a microvia made by UV:YAG laser. Today, ESI, Excellon, Exotech, Hitachi, and Sumitomo supply the UV/ Nd:YAG laser machines. Also, Hitachi and Lumonics of Canada now offer a combination of Nd:YAG/CO2 laser machines.5 4.3.3 Excimer laser

The excimer laser has a wavelength of 248 nm with KrF and 193 nm with ArF. Excimer lasers can generate holes smaller than 50 µm in diameter through dielectric or copper layers. Controlled-depth drilling is also possible, thus allowing blind vias to be created. Their slow

Figure 4.3 Cross section of microvia drilled by a UV:YAG laser.

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drilling speed, however, makes them impractical for microvia formation. Nevertheless, the excimer laser still can drill 10,000 holes per minute through a conformal mask that has a predetermined hole pattern. However, an effective mask can only be made of quartz material and the cost of this mask is prohibitively expensive for small panel runs. Today, Litel, JPSA, and Tamarack supply excimer laser machines, to which JPSA can add either T-CO2 or diamond CO2 laser heads.5 4.3.4 Comparison among various laser tools

Table 4.1 shows the comparison between the three laser processes for microvia formation. It can be seen that there are some important benefits of using the UV:YAG lasers, as shown in the following list. ■

The capability to drill through copper, which eliminates the printing and chemical etch steps for opening windows in the outer layer

■

The capability to form microvias as small as 25 µm

■

The capability to drill multilayer vias, providing opportunities to reduce sequential buildups

Table 4.2 shows that microvias formed with the UV:YAG laser technology pass all qualification tests.7 Table 4.3 shows the test results of another case using the UV:YAG laser technology. It can be seen that the samples pass all qualification tests. This indicates that laser drilling is a robust process. That is why more than 70 percent of the world’s microvia boards are made by laser ablation. Laser-formed microvias are thermally and electrically more reliable than traditional PTHs.8 It should be noted that laser drilling of SBU PCB and substrate is still in its infancy; therefore, further research on micromachining technology and reliability engineering is necessary. In particular, the maintenance of laser pointing stability, power stability, depth of field, and system positioning tolerances are critical issues to be resolved. In addition, lasers are not very energy efficient. Thus, putting lasers into TABLE 4.1

Comparison of Various Laser Methods for Microvia Formation

Capabilities

Excimer

UV:YAG

CO2

Diameter (µm)

10–100

25–100

For copper For resin (epoxy and polyimide) For FR-4 Hole sharpness Process cost

Very slow Slow Very slow Very good High

Slow Slow Slow Good High

70–250 (50–250) No Fast Fair Slope Low

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Microvias by Laser Drilling

Microvias by Laser Drilling

TABLE 4.2

137

Summary of Qualification Tests and Results Substrates tested

Results

30°C, 60% RH, 192 h, followed by three reflows at 215°C

98

Pass

MIL-STD-883 Method 1011 Condition B

500 cycles, −55°C to 125°C, liquid to liquid

98

Pass

Thermal cycle

MIL-STD-883 Method 1011 Condition B

1000 cycles, −55°C to 125°C, air to air

98

Pass

Pressure cooker

JESD22-A102-B

96 h, 15 psig, 121°C

16

Pass

High-temperature storage

MIL-STD-883 Method 1008

150°C, 1000 h

55

Pass

Temperature/ humidity/bias

JESD22-A101-A

1000 h, 85°C, 85% RH, 5-V bias

16

Pass

Test

Specification

Description

Preconditioning

JESD22-A113-A Level 3

Thermal shock

TABLE 4.3

Qualification Tests and Results

Test

Conditions

Observation

Results

Thermal cycle

−65–125°C, 30 min each 100 cycles 200 cycles 300 cycles

No corner crack Resistance <10% change

Pass

Wet proof

40°C/90–95% RH for 240 h

Resistance <10% change

Pass

Voltage

20°C/65% for 96 h and 500 V DC for 60 s

No crack of copper in the vias

Pass

Thermal shock

260°C (10 s)–25°C (20 s) for 30 cycles

No corner crack No copper lift No solder resist (S/R) lift

Pass

Solder

260°C, solder dip 10 s

No delamination No corner crack No S/R lift No delamination No corner crack No S/R lift No delamination No corner crack No S/R lift

Pass

288°C, solder float 10 s

288°C, solder float 5 s

Pass

Pass

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around-the-clock manufacturing tools for making microvia SBU PCB and substrate poses a great challenge.5 4.4 Material Selection 4.4.1 General considerations

There is a wide range of materials available today for microvia formation. Some of the materials known to be qualified in the PCB industry today for laser drilling are:9 ■

Allied Signal RCC® and Polyclad RCF®

■

Gore Speedboard® N and C

■

DuPont Thermount® E210, E220, and E230

■

FR-4 and FR-5 with glass fabrics: 1 × 104, 1 × 106, 1 × 1080, 1 × 1065, 1 × 2113, 1 × 3070, 2 × 104, 2 × 106, 3 × 104

■

Novaclad® Polyimide

■

Materials from other laser dielectric suppliers including BF Goodrich, Ciba, Specialty Chemical, Enthone-OMI, Hitachi Chemical, MacDermid, Mitsubishi Gas & Chemical, Park, Shipley, and Taiyo Ink.

For telecommunication applications, there are two typical resins used for microvia formation, namely, Resin Coated Copper Foil® (RCC or RCF) for subtractive PCB processes and Thermal-Curing Resin (TCR) for additive PCB processes. RCC is the material of choice for the fabrication of cellular phones. The reasons for choosing RCC and not any other dielectrics in this application are:5 ■

RCC is readily available.

■

The cost of RCC has dropped in the past few years, making it more attractive.

■

From a manufacturing perspective, it is easy to form microvias using the UV:YAG laser compared with photovia technology, and there is no need for any of the special chemical processes associated with other technologies.

■

The dielectric has a laminated thickness of 40 to 60 µm, which allows for good impedance control.

■

It is possible to make blind vias through multiple layers.

4.4.2 Laser-drillable fabrics10

One key factor of a new family of materials that enables easier laser drilling is the weaving and postweaving processes implemented by the

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glass fabric suppliers. By careful formation of the glass fiber bundles, the glass manufacturer can provide a flatter bundle in both the warp and the fill directions as compared to the rounder bundles usually associated with standard E-Glass weaving technologies. Included in this new process is a spreading of the glass fibers to achieve a more even glass distribution across the entire area of the fabric. In this manner, the fabric has a smaller range of highs and lows in glass density. With standard materials, the area where two fiber bundles overlap has a high glass density and is more difficult to laser-drill. When the fibers are spread out, these high-density areas of glass fibers have a lower glass content and can be laser-machined with less laser pulses. Of course, different glass manufacturers utilize slightly different processes to achieve this spreading of fibers, but the different glass manufacturers arrive at the same resulting glass distribution characteristics. Figure 4.4 illustrates the differences between a standard EGlass fabric and a fabric that has been optimized for laser drilling. Utilizing this enhanced glass fabric and a compatible resin technology, the laminator can produce a multilayer system that has many advantages compared to resin-coated copper technology or to laminates made with conventional E-Glass fabrics. These laser-drillable fabrics are currently available in limited glass styles, but are gradually becoming commercially available in more standard glass fabric styles.11 The first materials to be utilized in the industry are presently thin fabrics, which are prepregged with high-Tg resin systems for the chip packaging applications. Although the fabric provides a building block for this technology, the resin systems utilized have to complement the glass finishes to achieve optimum performance in laser drilling.12 Table 4.4 provides the typical properties of laser-drillable multilayer materials as compared to both resin-coated copper and standard materials. As outlined in the table, fiber-reinforced materials with this

(a) Figure 4.4

(b)

Standard E-Glass fabric (a) vs. laser drillable E-Glass (b).

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enhanced glass fabric can provide numerous advantages in the design of printed circuit boards and HDI, including improved thermal and mechanical characteristics of the finished interconnect. Another key benefit of laser-drillable fabrics is the reduction in print-through of the internal circuit pattern to the outside of the multilayer board after the pressing operation. It is not uncommon, with thin external dielectrics and thin external copper, for the pattern of Layer 2 or Layer n-1 to be transferred to the outer surfaces. This printthrough topography can reduce outer-layer circuitry formation yields when fine lines are predominant. RCC-type materials can sometimes

TABLE 4.4

Comparative Benefits of Laser-Drillable Multilayer Materials

Property

Resin coated copper

Print-through Outer dielectric tolerance Maximum laserdrillable dielectric thickness Laser-drilled hole geometry and plateability Dimensional stability Resin cracking Typical laser-drilling speed (500-Hz TEA CO2 Laser, 75-µm dielectric)* Material options (volume availability)

x-y CTE range (PPM/°C) Tg range (°C) Plasma compatibility Optimum layer counts Minimum copper (µm) BGA rework Chip packaging

30–40 130–170 Yes 2–12 5 Fair Yes

E-Glass standard materials

Laser drillable LD advanced materials

Moderate ⫾15%

Good ⫾10%

Excellent ⫾10%

80 µm

240 µm (2,3-ply)

240 µm (2,3-ply)

Good

Fair

Excellent

Moderate Possible 50 µm: 1 pulse

Good No 50 µm: 4–5 pulses

Excellent No 50 µm: 3–4 pulses

80 µm: 1 pulse*

80 µm: 6–8 pulses*

80 µm: 5–6 pulses*

Epoxy High-Tg epoxy

Epoxy High-Tg epoxy Low-loss epoxy Low-CTE epoxy APPE Polyimide Low-loss polyimide Cyanate-ester 10–16 130–250 No 2–50 5 Excellent Yes

Epoxy High-Tg epoxy Low-loss epoxy Low-CTE epoxy APPE Polyimide Low-loss polyimide Cyanate ester 10–16 130–250 No 2–50 5 Excellent Yes

* Application dependent.

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show more print-through than conventional materials depending on the design, the copper weight, and the lamination process. The use of laser-drillable fabrics reduces print-through because of the glass reinforcement and good surface planarity compared to standard E-Glass or resin-coated copper dielectric technologies. In addition to reduced print-through, the laser-drillable materials have inherently lower surface roughness as measured with a surface profilometer when compared with standard E-Glass dielectrics. Laser-drillable prepregs and laminates allow many options for laser microvia formation in a conventional multilayer process. Back-plane technology with high overall thickness designs can easily benefit from this approach because of the need for the lower z-axis expansion afforded by fiber reinforced dielectrics. The benefits of laser-drillable E-Glass reinforced materials include faster laser processing, cleaner hole formation, lower thermalmechanical expansion rates, better hole-wall adhesion during the metalization process, uniformity of material in the multilayer structure, easier Underwriters Laboratories (UL) approval of new products, and better fill of buried via stacks. Laser-drillable fabric technology provides other options to the fabricator and to the original equipment manufacturer (OEM) end user, including a broad spectrum of available resin systems. 4.4.3 Dielectric thickness capability and resin filling10

There are more benefits associated with laser-drillable fabric technology, namely thickness uniformity and resin filling. Most resin-coated copper technologies are somewhat limited in outer-layer dielectric thickness capability due to the process of manufacturing. Because of this limitation, certain applications of impedance control and buried via designs are more difficult to achieve. Laser-drillable prepregs and laminates offer some alternatives to enhance these types of applications. Since resin-coated coppers are relatively thin by their nature (80 µm and below), it is difficult to achieve standard impedance without external fine lines (100 µm) for microstrip applications. To complicate the issue, resin-coated coppers have slightly worse thickness tolerance compared to standard prepregs, a characteristic that does not assist in tight impedance control. This is not the case with laser-drillable fabrics, where higher overall thickness can be achieved with tighter thickness tolerance. With the thicker dielectrics provided by the laser-drillable fabrics, 50-Ω impedance can be targeted with standard external line geometries, such as 125-µm lines and spaces, thereby providing the possibility of better final interconnect yield. In addition, HDI manufacturing is often associated with buried vias, which require resin filling during the fabrication process. Usually Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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resin-coated copper technologies have difficulty in filling buried via pairs due to the thin nature of the product. Also, with resin-coated copper, it is sometimes difficult to guarantee a minimum insulation thickness over circuit lines after the relamination. With laser-drillable (LD) fabric materials, insulation thickness of 40 µm or greater is possible, with the glass fabric acting as a spacer to guarantee the insulation between the layers. Figure 4.5 illustrates a micrograph of a cross section of a multi-layer board, which utilizes laserdrillable fabrics both internally for the buried vias and externally for the microvias. Notice the excellent filling of the buried vias by the laserdrillable prepreg. A further benefit of the laser-drillable fabric technology is its ability to be supplied as a core for buried via applications. This will enable fabricators to create vias generated by laser ablation from Layer 1 and n to Layer 3 and n − 2, respectively. This cannot be accomplished using resin-coated copper technology. Because of the glass reinforcement, dimensional stability during processing and of the final multilayer are improved with the laser-drillable fiberglass-reinforced materials compared with resin-coated copper. As shown in Table 4.4, the x-y CTE for glass-reinforced materials is considerably improved over that for resin-coated copper. A key factor in this improved x-y CTE is the low CTE of the glass fabric itself. Figure 4.6 illustrates the tighter range achieved on dimensional stability in ppm movement when utilizing the laser-drillable fabrics. 4.4.4 Laser drilling robustness10

Figure 4.7 contains two micrographs comparing the conventional 1080 dielectric to the new laser-drillable dielectric for the formation of a

Figure 4.5 Buried vias resin filling utilizing laser-drillable LD materials.

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Figure 4.6 Comparison of dimensional stability (106 LD and 1080 LD types vs. resin-coated foil).

microvia utilizing a CO2 laser. After four laser pulses on the dielectric, some residual resin is left at the bottom of the microvia formed in the conventional dielectric, which will disrupt the integrity of the plating process. In addition, the circumference of the resulting hole is not uniform due to the glass-rich bundles associated with conventional fabrics. On the contrary, the LD dielectric shows clean laser-drilled holes with clean lands at the bottom of the microvia. Several laser drilling equipment manufacturers now utilize multiplefrequency lasers that provide sequential processing of the laser formation of microvias. By tailoring the wavelength of one laser to remove the copper foil, the alternate laser can be made to have a different wavelength and pulse configuration that allows fast and clean removal of the glass fibers and resin, thereby forming a reliable microvia hole. These laser machines all use galvo technology for speed enhancement and provide software programming of the process to optimize the hole texture.

(a) Figure 4.7

(b)

Comparison of conventional 1080 (a) and LD (b) dielectrics (4 pulses of TEA

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Chapter Four

As the technology of laser drilling and microvia processing progresses, thicker dielectric substrates, such as 1080 and 2113, become viable candidates for blind and buried via formation. With the laserdrillable prepreg and laminate materials and the new technology of dual laser drilling machines, the laser process can be adjusted to provide approximately 25 percent improvement in laser drilling speed while simultaneously providing a rounder, more plateable internal surface geometry. Since the LD fabrics do not have as many glass-rich areas, the possibility of glass wicking is reduced considerably. Although very popular, the resin types and thickness ranges of resincoated coppers are somewhat limited. For example, most resin-coated coppers have just two generic FR-4 resin categories: (1) 130 to 140°C Tg and (2) 150 to 175°C Tg. There are a few higher-performance resins that have been applied to resin-coated copper and SBU approaches. Although these products have excellent technical merit, they are not being used in high-volume nonreinforced applications at this time. The weaknesses of nonreinforced resin technology may not be readily apparent for the lower layer counts. As the layer count increases, however, a number of factors provide a compelling argument for considering fiber-reinforced options and, more importantly, laser-drillable fabrics. Higher-layer-count designs in general require lower thermal expansion in order to improve via reliability and to prevent pad lifting on the external circuitry. Also, with more complex designs, buried vias are being used more often in conjunction with blind vias to increase density. Buried vias often are designed into the HDI board as the second or third dielectric. Because of their location in the multilayer structure, they require more dimensional stability and better via-filling capability. The options for laser-drillable fabrics systems are listed in Table 4.5. Perhaps the biggest advantage of utilizing fiber-reinforced fabrics is lower CTE. 4.5 Via Formation Processes Laser drilling is a single- or multiple-via formation technology that replaces the existing mechanical drilling process. Laser drilling differs from mechanical drilling in that the focused beam used to create the vias can produce smaller holes than conventional drilling. The laser drilling process is shown in Fig. 4.8. A typical laser-drilled build-up PCB containing two blind vias and a buried via is shown in Fig. 4.9. One of the most important advantages of laser drilling is that it is compatible with many copper-clad or unclad dielectrics and reinforced or nonreinforced PCBs. Laser drilling can be used to create both blind vias and through-holes. It follows the standard multilayer process and is capable of resolving smaller features.

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TABLE 4.5

145

Advanced HDI Material Properties for LD Systems

Resin type Resin-coated copper Epoxy Epoxy Epoxy, low-CTE Epoxy, low-loss BT BT JEDEC APPE

Fiber type None HDI N4000-2 LD N4000-6 LD N4000-7 LD N4000-13 LD N5000-32 LD N5000 LD N6000 LD

Application

Tg (°C), DSC, TMA, DMA*

x-y CTE (−40 to 125°C), PPM/°C

135–140 Broad spectrum Low CTE Low CTE Low ∆k 1–5 GHz Telecom PBGA, HDI 1–10 GHz

155–170 140 180 155 210 180 190* 210*

30–40 12–16 10–14 10–14 10–14 10–14 10–14 10–14

* by DMA

4.5.1 Direct via formation

The simplest via formation method is to use a focused laser beam to directly drill the board material, including both the copper and dielectric.13 The smallest via size achievable is approximately the spot size of the focused laser beam. Larger vias can be made by expanding the laser beam optically or by moving it in a circular pattern while trepanning (Fig. 4.10) or spiraling (Fig. 4.11). The process is often used to drill

Figure 4.8 Basic process flow for microvia formation by laser.

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A seven-layer PCB with blind-buried-blind via net.

Figure 4.9

through-holes and blind vias.14 In Fig. 4.10, the laser beam is gated on in the center of the via. It then completes a programmable number of circumferences of the via before returning to the center. This process is often used for through-hole vias with programmable diameters. In Fig. 4.11, the laser beam is gated on in the center of the via. It spirals out to the circumferences of via, removing all material to a certain depth. This process is often used for blind vias with programmable diameters. Figure 4.12 shows two 50-µm (2 mil) and one 75-µm (3 mil) vias formed by direct laser punching and trepanning, respectively. At present, only the UV:YAG laser is used for this process.

Laser Beam Trajectory

Laser Beam Turns On & Off

To Nex Via

Programmable Via Size Solid State, UV Laser

Figure 4.10 Reinforced Organic Material

Copper Plane

The trepanning pro-

cess.

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Figure 4.11

147

The spiraling pro-

cess.

4.5.2 Ablation threshold

When creating blind vias, it is important to have a drilling process that self-limits on the target conductor layer. In the case of UV:YAG laser, the fluence (or energy density) of the laser beam on the substrate is adjusted so that it is unable to ablate copper. Figure 4.13 shows the relative ablation threshold of materials used in board manufacture.15 The laser fluence is adjusted by expanding the beam diameter or attenuating the output power until it is between the values of the target dielectric material and copper. In this way, dielectrics can be removed without affecting the conductor layer (Fig. 4.14). In the case of CO2 laser, the power must be lowered to the point where copper is not vaporized, and the target conductor layer should not have a black surface that absorbs IR. 4.5.3 Multilayer vias

Most blind vias in foil constructions are formed in two steps.16 The first step removes the outer layer copper and some of the dielectric, which is used as a buffering zone. UV:YAG lasers are used almost exclusively

Direct via formation (50-µm vias formed by direct laser punching). Figure 4.12

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Relative Ablation Threshold 9 8 7 6 5

4.13 Relative ablation thresholds of materials used for PCB fabrication.

Figure

4 3 2 1 0 P.I./PTFE

FR4/Aramid

E-Glass

Cu

for this process. The second step removes only the dielectric, and is accomplished either with a low-fluence UV:YAG laser or a CO2 laser. The process steps are shown in Fig. 4.15; vias at each stage of production are shown in Fig. 4.16. The two steps are performed automatically in a process sequence, and require only one insertion of the circuit board into the drilling machine. The two-step process can be expanded to form vias from Layer 1 to 3 (or n to n − 2) directly (Fig. 4.17). The sequence is similar to the standard two-step process except that both conductor layers 1 and 2 are removed in the first step. The usefulness of this multilayer process is limited by present plating restrictions. Deeper vias require a proportional increase in diameter, negating some of the original benefits of microvia technology. 4.5.4 Projection mask1

In a projection mask drilling system, the image of a single via, or of a complete via pattern, is projected onto the surface of the panel to be drilled. Figure 4.18 shows the layout of a simple projection system capable of drilling a single via at a time. A hole in the mask is illuminated with the laser beam, and the image of this hole is projected onto the panel surface. The masks are typically made of material that is reflective or resistant to the laser wavelength, and the optical systems are often demagnifying, which enables a relatively low power density to be used at the mask, thus extending the mask life. In the case of lasers that have large, high-power output beams, like excimers, the mask often contains an entire via pattern and is scanned

Figure 4.14 A 75-µm via formed in resin with a UV:YAG laser.

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Figure 4.15 Two-step processes for laser via drilling.

by the laser beam. If a number of vias in the mask can be illuminated by the laser beam, then they can be formed at one time using larger projection optics. These masks have to be very robust and spotlessly clean; therefore, they are often made of deposited dielectric materials on quartz. Projection mask systems that form single vias require minimal tooling, but via size is dependent on the mask. If programmable via size is required, some automated way of changing the mask size must be implemented. 4.5.5 Conformal mask1

Conformal masks are generally an integral part of the panel to be processed. In the case of a printed circuit board, holes are etched in the surface copper using conventional develop-etch-strip technology. The laser beam then illuminates these holes and removes the exposed

(a)

(b)

(a) A 75-µm via in RCC after step one. (b) The rest of the dielectric is removed and the copper surface is cleaned.

Figure 4.16

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A 150-µm via formed from Layer 1 to 3 in two layers of RCC.

Figure 4.17

dielectric material (Fig. 4.19). This process requires the mask material either to be reflective to the laser wavelength or to have an ablation threshold much greater than that of the dielectric material; i.e., the mask material will be undamaged by the laser beam but dielectric material will be ablated. Both these situations occur in practical examples. Vias can be formed one at a time if just a single hole in the mask is illuminated. If a large laser beam is used, multiple vias can be formed at once by scanning the laser beam over the panel surface. Conformal mask via formation is very common with TEA CO2 and excimer lasers. The additional cost is attributable to the phototools required to image the via pattern on the copper surface layers of every panel and the additional develop-etch-strip processes. Via size tends to be limited by the size of the window etched in the copper, with 100 µm (4 mil) to 150 µm (6 mil) being a practical range that offers reasonable yields. Smaller via diameters can be achieved with copper-clad materials. A lithographic etching process defines the via diameter; the CO2 laser

Figure 4.18 Projection imaging— a single via is projected onto the surface of a panel.

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Conformal mask process—the window is etched in the copper and the dielectric material removed by laser ablation.

Figure 4.19

uses the openings in the copper surface as a mask (conformal mask) to ablate the exposed dielectric material below (see Fig. 4.20). The process uses CO2 lasers with high pulse repetition rates and high average power. State-of-the-art systems use RF-excited CO2 lasers, running in super-pulsed mode, that don’t have gas flowing through the laser and therefore don’t need any laser gas installation. After 10,000 hours or more, the laser unit is simply replaced with a refilled unit, resulting in lower cost of operation and lower downtime. RF excitation of the laser gas and super-pulsed mode ensure high peak power, a high repetition rate of up to 100 kHz, and a good beam profile close to the theoretical optimum of TEM00. This enables fast and accurate shaping of the vias. The combination of superior laser sources with high-speed and precise beam guiding and motion systems (scanners, scan lenses, and working tables) provides high-quality vias at ablation rates exceeding 60,000 vias per minute. The diameter range doesn’t depend on the laser because the copper is pre-etched, and is typically between 75 and 125 µm (3 to 5 mil). Some taper angle is preferred for easy plating of the microvia. One solution to effectively process copper-clad materials is the use of UV laser sources. UV lasers to be considered include gas lasers, such as excimer or copper vapor lasers, but their use in the PCB industry is limited due to the use of toxic gases (excimer) or long-term reliability issues (copper vapor). Broadly accepted are solid-state lasers using neodymium (Nd3+) as the laser active material. Although these are often called YAG lasers, the host crystal carrying the neodymium can

Figure 4.20

Flow chart of conformal mask process.

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actually be yttrium-lithium-fluoride (YLF) or yttrium-vanadate (YVO). Since the laser wavelength is defined by the laser active material, not by the host crystal, all configurations share the same laser wavelength of 1,064 nm. Using laser diodes instead of lamps for pumping the laser rod results in a real all-solid-state laser. The advantage is the long lifetime of the diodes—in the range of 20,000 h instead of 500 h for arc lamps. This not only greatly reduces maintenance, but also eliminates unscheduled downtime caused by lamp breakdown. Pumping diodes have a predictable life cycle, so that replacement can be scheduled. In addition to availability and reliability, the stability of diodepumped lasers is better. Due to their broad emission spectrum, pumping lamps put a lot of heat into the laser crystal, causing thermal distortion. The consequence is lower laser beam quality and higher pulse-to-pulse fluctuations. Conversely, diodes deliver a very stable pumping light at precisely the wavelength needed for the laser process, thus avoiding undesired heat effects. As shown in Fig. 4.21, the “fundamental” wavelength of neodymium lasers can then subsequently be frequency multiplied to 532 nm (second harmonic), 355 nm (third harmonic), or 266 nm (fourth harmonic). It is important to keep in mind that in the IR the achievable resolution is low and the ablation process is of a thermal nature. This means the material is simply heated and evaporated by depositing a certain amount of energy per pulse into the bulk material. Going toward the UV range, the achievable resolution increases and the process will move toward photochemical ablation. Every photon can crack a bonding in the bulk material and thus remove the atom or molecule directly without heating effects. Photochemical ablation results in the best quality and no thermal damage to the surrounding materials.

Figure 4.21

Laser wavelength spectrum.

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State-of-the-art industrial UV lasers are “black-box” in design with no maintenance parts inside. After the lifetime of the diodes, the complete unit is simply replaced by a refurbished unit. There are systems using 532 nm as well as 266 nm for special applications, but the majority are working at 355 nm (frequency tripled). The minimum via diameter is defined by the diameter of the UV laser spot at the copper surface. It is possible to achieve via sizes below 10 µm (<0.5 mil), but diameters of 25 µm (1 mil) and up are common. The strategy of attaining vias with diameters larger than the UV beam spot is similar to the mechanical milling process and is called trepanning. The UV laser starts at the center of the via and moves in concentric circles with increasing diameter to ablate the copper on the complete area of the via. This shows clearly the advantage of the laser for small vias, since the processing time increases with increasing diameter of the vias. Of course, the UV laser can also be used for ablation of the via dielectric, but the ablation rate of UV light is much lower and the process has to be set up very accurately so the second copper layer is not damaged. Certain blind via drilling processes use the laser to remove the outer layer of copper. Copper’s low absorption in the infrared makes it difficult to cut with CO2 lasers without using very high power, which can cause damage to the area surrounding the via. Attempts have been made to increase the efficiency of this process by adding proprietary organic or black oxide coatings to the copper to increase its absorption. These processes are still in their infancy. 4.5.6 Dual laser via formation2

The dual-laser system is a device with both a UV and a CO2 laser. This combines the advantages of both processes: the precise and damage-free UV ablation of the copper surface and the fast and efficient ablation of the dielectric with the IR laser. Dual-laser processing is viewed as a “third-generation” process, developed independently in many different industries, mainly in the United States and Europe (see Fig. 4.22). The via size is defined by the UV laser, as described earlier, and the CO2 laser with a fixed beam diameter (up to 250 µm) is applied subsequently. Results are via sizes in the range of 25 µm (1 mil) to 250 µm (10 mil) (see Fig. 4.23). Dual-laser systems offer the broadest process compatibility. The same laser system can be used for prototype work, small batches, and large production runs. Looking at a typical PCB life cycle clearly demonstrates the advantages of the dual-laser concept; in the early design stages there are many changes in the via positions. The dual-laser process allows the fabricator to use the UV laser to define the vias in the copper and subsequently to use the CO2 laser to drill the dielectric,

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Chapter Four

Figure 4.22

Flow chart of dual-laser via formation process.

avoiding high mask costs. Even the desmear process (for prototypes) can be done with subsequent UV processing (laser desmear). In a later stage, the majority of the via positions are fixed, but there are still some via position changes. Pre-etching the copper layer, the dual-laser system lets the manufacturer drill the few vias that have to be changed with the UV laser and the main part of the vias with the CO2 laser only. In a mature design with all vias well defined, only the CO2 laser is used, in combination with copper pre-etching, for highest throughput rates. An example of a dual-laser system is shown in Table 4.6. The CO2 laser is sealed, RF-excited, and super-pulsed with a maximum pulse repetition rate of 25 kHz. The UV laser is diode-pumped and Qswitched, delivering 355 nm with a maximum pulse repetition rate of 100 kHz. Fast galvanometer scanners in combination with f-theta lenses cover scan areas of 50 × 50 mm2 (approximately 2 × 2 in2) for the IR beam and 30 × 30 mm2 (1.2 × 1.2 in2) for the UV beam. Panels are handled by a vacuum chuck on an x-y table with linear motors and scales, combining a high speed of 60 m/min (2360 IPM) with a large working area of up to 610 × 711 mm2 (24 × 28 in2) and a precision of ⫾25 µm (1 mil). 4.5.7 Future trends2

Microvia formation will continue to experience frequent and rapid changes of technologies. With declining via diameter, direct dielectric

Scanning electron microscope (SEM) micrograph of a dual laser-drilled microvia.

Figure 4.23

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TABLE 4.6

155

Dual-Laser System—LVD 2001 DP Laser generator

Laser type Wavelength Beam mode Pulse energy (max) Frequency (max) Peak power (max) Average power (max)

CO2 RF-excited, sealed off 9600 nm TEM00 1.5 mJ 25,000 Hz 350 W 80 W

Scan area (mm) Scan speed

50 × 50 1,000 pos./s, 1-mm spacing

Diode-pumped UV Q-switched 355 TEM00 0.3 mJ 100,000 Hz ∼10 kW 3.5 W

Galvonometer scanner 30 × 30 1,000 pos./s, 1-mm spacing

ablation with the CO2 laser will reach its limits. Dual-laser systems, featuring higher accuracy and the capability of processing smaller via diameters, will increase in number. To avoid the risk of investing in capital equipment that will end up as stranded assets, modular duallaser systems might be the safest investment. Dual-laser systems differ distinctly in design. Some manufacturers are bound to certain components, such as their own laser sources and scanners. Other designs are more flexible and modular, integrating components of leading brands and offering upgrades when more advanced laser sources or optics become available. Modular and flexible design enables the user to adapt the system to different processes and react to market requirements, and provides an insurance policy against obsolescence costs. Modularity doesn’t have to end with the components integrated into the system, but includes the complete design of the laser system, software, and automation capabilities. This way, the user can start with a system for manual loading and add automation components when the order volume increases. The autoloader is set beside the laser system, only occupying the left side of the machine and keeping the opportunity open to add yet another laser system to the left side of the autoloader. This way, only one autoloader per two laser units is needed, saving investment costs and floor space. Understanding the utilization factor for automation equipment dedicated to only one machine, the wisdom of feeding two machines with one automation system becomes clear. The autoloader loads, unloads, and might even flip panels, thus enabling a fully automated process starting with raw panel and ending with panels processed on both sides (Fig. 4.24). The panels are provided from the feeder cart, prealigned, and forwarded to the machine tables. After finishing side A is finished, the panels are flipped and side B is processed.

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Figure 4.24

Material flow from autoloader to laser system.

The finished panels are then stored in the stacker cart. The concept includes drill time parallel flipping when both lasers are involved. The ideal solution depends on the product spectrum to be processed. For through-holes and blind vias with a diameter of 200 µm (8 mil) or more, mechanical drilling is surely predominant. In contrast, laser drilling is predominant for diameters of 150 µm (6 mil) and less. The gap between these technologies makes it hard for users to decide which technology to use. EFSs can clearly bridge this gap, providing an overlap down to 100 µm (4 mil) and therefore a smooth transition from mechanical to laser via formation. The via quality is excellent, and, with the opportunity to retrofit EFS, it offers an entry into microvia technology using existing equipment. This way, microvia technology can be evaluated and all production processes can be streamlined before a completely new technology is introduced. Figure 4.25 presents at the economic aspect and shows a significant increase in costs when drill diameters of 150 µm (6 mil) or 100 µm (4 mil) are used. The higher costs are caused by a higher tool (drill bit) price and a reduced via formation (hit) rate. Combining these two costs results in significantly higher cost per via for diameters of 150 µm (6 mil) and 100 µm (4 mil), while the costs per via for diameters of 200 µm (8 mil) and larger are nearly constant. The laser becomes more favorable with smaller via sizes. Applying the dual-laser formation, the ablation of the copper with the UV laser is the limiting time factor. The area to be ablated is scaled to the square diameter of the via. The economic crossover point is approximately 150 µm (6 mil), where dual-laser drilling becomes more economical than mechanical drilling. Conformal mask processing with CO2 laser involves the highest investments in wet chemical processes and lithographic equipment,

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Figure 4.25

157

Comparison of via drilling costs.

but has the lowest running costs per via due to the extremely high drill rates achieved. It is therefore the process of choice for high-volume production (assuming that the board fabricator already has an investment in clean room resources for photolithographic processes). As with any manufacturing decision, there are other factors to consider that drive the process selection. Besides the issue of obsolescence risk, one needs to consider the supply chain, particularly if there are plans to export the processes abroad. Prior to moving PCB fabrication overseas, one must ensure that equipment providers have sufficient support infrastructure to provide parts, training, and assistance. Finally, there may be specific process needs that are required by a particular PCB fabricator (automation, laser wavelengths, beam path, etc.) that will push equipment providers into semi-customization of their equipment. 4.6 Practical Laser Drilling Systems1 4.6.1 Parallel projection imaging systems

Laser drills that project images of multiple vias or entire circuits are very similar to optical imaging systems (Fig. 4.26). The laser beam is scanned over a projection mask that is imaged on the surface of the panel. These systems are rarely used in the fabrication of printed cir-

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Figure 4.26 Simplified diagram of a projection mask system.

cuit boards, but have had extensive use in multichip module and package manufacturing. 4.6.2 Sequential via formation systems

These machines make up the vast majority of systems in use today by the PCB industry. The beam positioner is the most critical subsystem in the laser drill. It has a number of important functions: ■

To focus or project the laser spot with equal size and power density over the entire drilling area

■

To place the laser beam accurately in the drilling area

■

To move the laser beam at very high speed between drilling locations, or within drilling locations if trepanning and spiraling techniques are used

The two most common beam positioning systems available today are the galvanometer with x-y table combination and compound beam positioner. 4.6.3 Galvanometers with X-Y tables

The deflection galvanometer has become a very common tool in laser beam positioning over the past 30 years. Figure 4.27 shows a simplified galvanometer beam positioner layout. Very small rotations of the mirrors deflect the laser beam over a relatively large area. These systems are very fast, with random positioning times of between 1 and 4 ms.

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Figure 4.27

159

A simplified layout of an x-y galvanometer system.

In practice, galvanometer systems have a number of limitations: ■

In an uncorrected state, they project the laser at an angle to the work surface. This is unacceptable for most via drilling, so special telecentric lenses have been developed to keep the beam orthogonal to the work surface, no matter at what angle it enters the lens system (Fig. 4.28).

■

In drilling applications, they are usable only over small areas, typically 50 mm2 (2 in2) or less; and their accuracy degrades exponentially toward the edge of the field.

To solve the accuracy problem, galvanometer systems are used in conjunction with x-y tables. The galvanometer drills a small section of the field, and then the table steps to the next position. In this way, the

A telecentric lens keeps the laser beam perpendicular to the work piece at all times.

Figure 4.28

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A compound beam positioner. The galvanometer and linear motors all move continuously during the drilling process.

Figure 4.29

panel is drilled as a series of small squares that are butted together to cover the entire area. Care must be taken to avoid abutment errors in these systems. At the join between two squares, the positioning error between two adjacent vias is the sum of the total positioning error of the x-y table and the galvanometer system. These abutment areas should be kept away from high-density via arrays. 4.6.4 Compound beam positioners

This technique uses a combination of cross-axis linear motor and galvanometer technologies to create a system that can effectively drill with multiple laser pulses on the fly (Fig. 4.29). The linear motors and galvanometer systems are moving continuously during the drilling operation. When a via is being drilled, the laser beam is held in position over the correct location by counteracting motions of the linear motors and galvanometers. Fast motions between vias are accomplished by the galvanometers alone. There is no stepping between areas covered by the galvanometer, as the movement between vias is continuous, thus avoiding abutment errors. The future for laser drilling looks bright. Every year sees advances in laser sources, beam positioning technology, and compatible materials. There is every reason to assume that productivity will continue to double on an annual basis, making this technology a difficult one for alternative via formation methods to catch. 4.7 References 1. Cable, A., “Microvia Generation Equipment—Laser,” Board Authority, 1(2):40–46, June 1999. 2. Kauf, M., L. Ekblad, and H. Martinez, “Mechanical and Laser Via Formation,” Board Authority, 2(2):61–65, July 2000. 3. Brannon, J., “Excimer Laser Ablation & Etching,” American Vacuum Society Monograph, 1993. 4. Owen, M., H. Bleiweiss, J. V. Puymbroeck, E. Roelants and A. Mattelin, “The Introduction of UV YAG Laser Drilled Microvias in PCBs,” Proceedings of PC World Conference, 1996. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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5. Lau, J. H., and C. Chang, “An Overview of Microvia Technology,” Circuit World, 26(2):22–32, January 2000. 6. Cable, A., “Microvia Formation in Flip-Chip Packages Using a New Diode-Pumped Ultraviolet Laser Technology,” Proceedings of SEMICON, Singapore, 1999. 7. Petefish, W. G., D. B. Noddin, and D. A. Hanson, “High Density Organic Flip Chip Package Substrate Technology,” Proceedings of the 48th ECTC, pp. 1089–1097, Seattle, WA, May 1998. 8. Young, T., and F. Polakovic, “Thermal Reliability of Laser Ablated Microvias and Standard Through-hole Technologies,” Proceedings of the IPC Expo, p. S17–2, Long Beach, CA, March 1999. 9. Raman, S., J. H. Jeong, S. J. Kim, B. Sun, and K. Park, “Laser (UV) Microvia Application in Cellular Technology,” Proceedings of the IPC Expo, p. S17–6, Long Beach, CA, March 1999. 10. Forcier, B., “Laser Drillable E-Glass Multilayer Materials: An Overview of Laser Enhanced Materials,” Board Authority, 2(2):67–70, July 2000. 11. Forcier, B., and F. Hickman, “The Design and Fabrication of HDI Interconnects Utilizing Total Integration of Fiber Reinforced Materials,” Board Authority, 2(1):64–68, April 2000. 12. Kimura, Y., “Specially Developed Glass Fabrics for Ultimate Small Diameter Hole of High Density Package Board by Build-up Method,” Proceedings of IPC Expo, April 2, 2000. 13. “Ultraviolet Laser System and Method for Forming Vias in Multi-Layered Targets,” U.S. Patent 5,593,606, January 14, 1997. 14. Noddin, D. B., P. Fischer, W. L. Gore, and E. Swenson, “Solid State UV-Laser Technology for the Manufacture of High Performance Organic Modules,” Proceedings of 48th ECTC, May 1998. 15. Cable, A., “New Laser Processes and Wavelengths for Drilling Through-Hole and Blind Vias in a Wide Range of Circuit Board Materials,” Proceedings of IPC Printed Circuits Expo, San Jose, CA, 1996. 16. “Method Employing UV Laser Pulses of Varied Energy Density to Form Depthwise Self-Limiting Blind Vias in Multilayered Targets,” U.S. Patent 5,841,099, November 24, 1998.

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Source: Microvias

Chapter

5 Microvias by Photoimaging

5.1 Introduction The first commercially used PID was a modified liquid solder mask produced in 1990 by IBM at Yasu, Japan. Modern PIDs are in the form of either liquid or dry film. For photovias with liquid photodielectric, the dielectric is curtain-coated and cured, microvias are exposed, and the dielectric is developed. Then the panel plating follows with patterning to create signal traces. For photovias with dry-film photodielectric, the dielectric is laminated, microvias are exposed, and the dielectric is developed. Panel plating follows with patterning to create signal traces.1 There are many PID materials available in the market, such as Probelec by Ciba, ViaLux PDDF by DuPont, ENVISION® PDD-9015 by Enthone-Omi, and photoimageable resins produced by Dow, MacDermid, Morton, Shipley, Taiyo Ink, etc. The determining factors in materials selection depend upon the characteristics required. These can be categorized by dielectric type, e.g., epoxy or polyimide; the form the dielectric takes, e.g., liquid or film; and general physical characteristics of the dielectric, such as Tg, dielectric constant, or moisture absorption. In selecting a dielectric material on the basis of these criteria, both manufacturing choices and end product design requirements must be taken into consideration.2 5.2 Photoimageable Dielectrics for Microvias 5.2.1 Typical process for photo-defined vias2

Microvias can be formed in mass production by photoimaging technology. The dielectric is applied over the base substrate, and the microvias are 163

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imaged and developed. Then this via layer is cured, adhesion-promoted, and copper-plated to connect the microvias. A final primary resist is applied to complete the outer-layer imaging; then the circuits are etched or pattern-plated. Conductive paste can also be used to fill the microvias and circuit pattern. A step-by-step process flow is illustrated in Fig. 5.1. ■

Step 1. The photosensitive polymer is applied to the base substrate.

■

Step 2. The coated substrate is exposed to UV light through a rightreading mask containing the desired circuit pattern to selectively cross-link the material.

Figure 5.1 Process flow chart for fabricating multilayer PCB using photoimageable dielectric and conductive ink technology.

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■

Step 3. The dielectric is developed, removing the un-cross-linked polymer, leaving the final photoexposed, cross-linked polymer with the desired conductor pattern.

■

Step 4. The conductive ink is applied to fill the photoexposed conductor holes.

■

Step 5. A second layer of photosensitive dielectric is applied and exposed to a mask containing the pattern of the vias.

■

Step 6. Step 3 is repeated.

■

Step 7. Step 4 is repeated. The vias are filled with conductive ink and cured.

■

Step 8. A third layer of photosensitive dielectric is applied. This layer is then exposed, developed, filled, and cured with the circuitry for the second conductor layer. Figure 5.2 shows a cross section of a photo-defined via.

5.2.2 Liquid photoresist systems3

There are a growing number of liquid photoresists being developed for the PCB and photochemical milling (PCM) industries. Within this array of products, a variety of different photochemical systems are used that impart unique properties to the finished photoresist materials. Factors such as resolution, photospeed, and chemical resistance are affected by the choice of these systems. Several of these liquid photoresist materials are reviewed and compared here, along with the process and application techniques for their use. All of these photoresist systems rely on exposure to light to create differential solubility between the exposed and unexposed regions. A negative-working resist relies on exposure to photopolymerize or cross-link the material to produce a region that is insoluble in a developer solution. Positive-working sys-

Figure 5.2

Cross section of photo-defined microvia.

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Figure 5.3

Solubility in a devel-

oper.

tems create regions of enhanced solubility in a developer in regions where the resist is exposed. The difference between the soluble and insoluble regions of the material can be thought of as the resist contrast (see Fig. 5.3). 5.2.2.1 Negative free-radical resists. A negative-working free-radical system uses a photoinitiator that, upon exposure to light, creates free radicals. These free radicals initiate a chain reaction with the monomers, causing them to polymerize and hence harden the photoexposed areas. This hardening prevents the developer solution from solubilizing the exposed area. The sensitivity of the system to various wavelengths of light (spectral sensitivity), which affects photospeed, can be tuned through the use of a sensitizer. The sensitizer will absorb light at a wavelength usually different from the photoinitiator and then act as an energy transfer agent to aid in the formation of additional reactive free radicals. The sensitizer can then return to its ground state and participate in further reactions. Additional exposure will continue the cross-linking reaction. The more cross-linked the system becomes, the more resistant the material is to developer solutions (see Fig. 5.4). 5.2.2.2 Negative cationic resists. A variation of the negative-working cross-linking scheme is found in the negative cationic system. Here the

Figure 5.4

Negative free-radical

reaction.

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cross-linking occurs through the aid of an acid catalyst. The photosensitive material is a photoacid generator (PAG). Upon exposure to light, the PAG forms an acid, which is mobile in the resist matrix. When heated, this acid catalyzes a reaction between reactive sites on the polymer chains with reactive sites on the cross-linker (a novolac polymer and a melamine cross-linker are shown in the example in Fig. 5.5). The extent of the reaction that occurs depends on the amount of acid generated, the amount of heat applied, and the length of heating time. The example in Fig. 5.5 shows up to six reactions occurring per crosslinker molecule. 5.2.2.3 Positive diazonaphthoquinone (DNQ) resists. The common positive-working system is based on a photoactive compound (PAC) and soluble binder reaction, which has been a mainstay of the microelectronics industry for chip manufacturing. This system typically starts with a novolac binder, which by itself has solubility in base (OH−). To this binder is added a PAC that lowers the solubility of the entire mixture. The PAC is a DNQ. When exposed to UV light, the DNQ forms a ketene intermediate that, in the presence of water, forms an indene carboxylic acid (see Fig. 5.6). This acid species enhances the solubility in base of the

Figure 5.5

Negative cationic reaction.

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Figure 5.6

DNQ photolysis. Figure 5.7

DNQ-novolac solubility.

entire resist system to a level much higher than that of the PAC-novolac mixture or the novolac binder alone (see Fig. 5.7). 5.2.2.4 Positive cationic resists. Another version of the positiveworking system utilizes the cationic deblocking reaction, sometimes referred to as chemical amplification. This system was developed to address the photospeed problems encountered in deep-UV (DUV) exposure and is now beginning to see widespread use in the semiconductor industry. The energy outputs of most exposure systems at DUV wavelengths are small compared to the mid- and near-UV. To combat this deficiency, these systems use a PAG to create the acid catalyst for the reaction. In this case, the reaction is a deblocking of a dissolution inhibitor from the backbone polymer (see Fig. 5.8). This acid catalyst reaction improves the photosensitivity of the material by orders of magnitude. Also, the choice of dissolution inhibitor will affect the initial solubility of the photoresist and change the resulting solubility contrast, usually improving it over the level achieved with PACnovolac resists (see Fig. 5.9). So far, these resists have not been applied in the chemical milling or PCB industries.

Figure 5.8

Positive cationic reaction.

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Figure 5.9

169

Photoresist solubility.

5.2.3 Direct-write film4

Laser direct imaging (LDI) offers one solution for elimination of steps. Direct imaging is a gigantic leap in the PCB manufacturing process. LDI eliminates the entire phototooling area and puts imaging directly into the chemical process of the PCB manufacturing. This is a radical change in the entire manufacturing process and requires tight control and process monitoring. Not every company is ready or able to commit the resources required to make this leap. Direct-write film or film that is imaged thermally also offers a way to eliminate steps and to simplify the entire process of phototool production without drastic changes to the current manufacturing process. It offers an alternative to the major change required when laser direct imaging is introduced into the process. Phototools must provide a clear and sharp circuit image with quality that satisfies fabricator requirements for imaging onto photoresists. Silver halide film imaged on a photoplotter is a proven technology for providing phototools. This technology has been in use since 1964, when the first photoplotter was invented. These early photoplotters used a vector technology to move a beam of light across silver halide film to produce the circuit image. This process was slow and not very flexible but got the job done. There have been many improvements in photoplotters over the years. Photoplotters today use lasers in a raster format to produce high-quality tools in minutes instead of hours. The raster plotters can create very complex images out of the arrays of laser dots. Circuit boards today are much more complex, with smaller features and tighter tolerances. Raster laser photoplotters have provided fabricators with the means to generate phototools that can accommodate today’s geometry requirements. There have also been major improvements in silver halide films. However, the basic process is the same. First the film must be acclimated to the temperature and humidity in the photo area. After being exposed to light, the film goes to an automatic processor for developing. The processor includes a developing solution tank, a fixer tank, a water Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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rinse tank, and a dryer section. The film is subject to extreme humidity and temperature changes that cause it to change size. The film must then go through a stabilizing time to restore the correct image size before it can be used in production. There are then two alternatives regarding how to use the film. The film may become the master copy, and contacting it to diazo makes a working phototool. As the diazo deteriorates due to use, more diazo can be contacted. The other method is to use the original as the working phototool and create new original masters off the photoplotter as needed. The first-generation phototool provides the best-quality image because it is the original. Newer silver halide films offer improved resolution and sensitivity that allows them to produce the higher-quality images required for today’s complex technology. Silver halide film, however, still requires time to acclimate and time to stabilize after being subjected to heat and moisture in the processor. This stabilization time is becoming a bigger factor as production cycles decrease and costs increase. Environmental restrictions have put pressure on PCB fabricators regarding the handling and disposal of the chemicals and waste associated with silver halide. These factors all contribute to the need for direct-write film. Direct-write film produces phototools without the need for chemical processing. These films are thermally imaged using high-powered lasers that use the laser energy to alter the media and create dark areas and light areas. Several direct-write films have appeared on the market over the years, including ones from AGFA, Kodak, and Polaroid. Mastertool from AGFA is one of the direct-write films that has created a lot of excitement in the industry. It eliminates the need for chemical processing and the associated stabilization time. Because it has no gelatins, there is no need for acclimation before exposure. It is very dimensionally stable. Mastertool consists of a polyester base with a layer of bismuth on the base. A thin polyester sheet is laminated on top of the bismuth to protect the material. A high-powered laser melts the bismuth, which then solidifies into extremely fine drops. These drops are sufficiently dispersed to permit light to pass through the media. Unfortunately, the method has a problem. The drops remain in the media and result in the Dmin being significantly higher than for silver halide film. Special attention and care has to be used in the contacting process. Care has to be taken in setting up the exposures using Mastertool film. More light is required—and for a longer time. Mastertool is not a direct replacement for silver halide in the contacting process, and this has hindered the wide acceptance of Mastertool in PCB applications. Ideally, a film must fit right into the current process without the need for special setups. Still, because of the advantages of directwrite film, there are a large number of Mastertool users.

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The interest generated by Mastertool does show the need in the industry for this type of solution. Mastertool and other direct-write films are still offered in the market. More films will continue to appear on the market to fill the need in the industry. Key to their success will be the convenience of use and quality of image. The film must be daylight-safe, with no need for a darkroom. Ideally it should allow direct digital exposure (no over- or underexposure due to processing), it must have no wet processing (no waiting for stabilization, no chemicals, and no processor maintenance), and it has to be translucent for easy registration (no need to contact to diazo). The film must have a low UV Dmin and a high UV Dmax so it can be inserted into the existing process with a minimum of changes to the process. It should be used like silver halide film yet still eliminate the steps users are looking to shed. A film with these characteristics will serve a broad spectrum of the market. Fast-turnaround shops will appreciate the elimination of the processing and stabilization time. Medium- and long-run fabricators will benefit from the resistance to scratching and film deterioration. All users will appreciate the elimination of chemical processing and the associated environmental concerns. The basic price of the direct-write film does not need to compete directly with the price of silver halide film. Users will still recognize costs savings. These savings will come from eliminating the darkroom, the costs of processors and chemicals, and the need to make diazo and waste material processing—along with the labor associated with these steps. Recently a new type of direct-write film has been under development. This direct-write film shows promise of filling industry needs. The film has been chemically formulated to be imaged on the Barco Prism IR imager that has an internal drum architecture. An internal drum consists of a stationary concave surface. A vacuum holds the medium to the inside surface of the drum. Above the drum, a rotating mirror scans the laser across the drum while the entire optical assembly moves continuously down the drum. The internal drum platen allows the medium to remain stationary, thereby making it easier to accommodate many types of flexible media. The laser is an Nd:YAG infrared laser that transmits large amounts of energy to the medium to create an image. The construction of the film is shown in Fig. 5.10. The key to the technology is the IR-absorbing layer. This IR layer bonds the dye coat to the polyester base and is totally environmentally friendly. The dye coat is also bonded to the top coat, or what is called the peel layer. When the laser (Fig. 5.11) ablates the IR-absorbing layer, the dye coat is no longer bonded to the base. The top layer (peel coat) remains bonded to the dye layer. In Fig. 5.12, the peel coat has been removed, and that portion of the dye coat that is no longer bonded to the base is removed with the peel coat. The

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Figure 5.10

Direct-write film (before Figure 5.11

exposure).

Direct-write film (after

exposure).

bond of the dye to the IR layer is stronger than the bond to the peel layer, so the unablated material and dye remain on the film base. The peel coat may be disposed of easily without special environmental care. This finished film looks very much like diazo but has been imaged like film. It is used just like silver halide film, except that it is daylight safe, is direct-digital exposed, and involves no wet processing. The film is translucent for easy registration and has a low UV Dmin, a high UV Dmax, and an infinite shelf life. It appears to satisfy all the criteria users have for direct-write film. 5.3 Surface Laminar Circuit Technology5 5.3.1 Configurations and design rules

Surface Laminar Circuit (SLC) technology was the first of the microvia build-up technologies to reach the interconnect market in volume. Development of SLC technology began during the late 1980s at IBM’s development laboratory in Yasu, Japan, and the first product was introduced in 1990. The first flip chip direct chip attach product employing SLC technology was shipped from Yasu in 1992, and in 1995 IBM shipped the first printed wiring boards that utilized SLC technology from the company’s Endicott, New York, site.6 SLC technology was originally conceived as an alternative to multilayer lamination as a way to make multilayer PCBs. Instead of cir-

Figure 5.12

Direct-write film (after

peeling).

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cuitizing several double-sided cores and subsequently laminating them to make a multilayer PCB, SLC technology builds up each signal layer on top of the previous layers in a sequential fashion. The base under all of the outer build-up layer is a conventional double-sided circuit board containing voltage and ground planes. All signal interconnections between layers are made with photo-defined microvias. Mechanically drilled and plated holes are used only to make connections to the backside of the laminate base and to accommodate mounting pinned components. As SLC technology evolved, its usefulness was significantly enhanced with the build-up layers on a multilayer subcomposite. This allowed design and fabrication options, such as striplines for controlled impedance, using the higher-density, more expensive build-up layers for component escape wiring while employing less dense, lowercost multilayer PCB technology for component interconnect (global wiring). It is advantageous from a wiring density standpoint to use PTHs, which extend only through the base PCB structure and not through the build-up layers, especially when two or more build-up layers are used. These internal interconnects are termed resin-filled PTHs (RFPs). RFPs allow designers to use the board area above the RFP holes and lands for wiring on the build-up layers, significantly improving wiring density. Fig. 5.13 shows a partial cross-section with three SLC technology build-up layers on one side of a multiplayer base PCB with RFPs.7 The photoimageable solder mask [photoimageable dielectric/(PID)] materials were chosen as interlayer dielectrics due to their proven compatibility with the PCB assembly process and their ability to withstand exposure to service environments, as well as having the necessary via imaging characteristics. SLC technology was originally developed and implemented with a liquid photoimageable solder mask applied by curtain coating. In 1995 it was also qualified with a dry-film

Figure 5.13 Cross section of a typical SLC 3+3 structure with filled PTHs and a staircase of microvias going from the PTH to the upper surface.

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TABLE 5.1

Design Rules of SLC Technology Feature Size (µm) Feature

Standard

High-density

Prototype

Future

Photovia diameter (min) Photovia land diameter, top/bot (min) Line width (min) Space (min) Line thickness (min) Dielectric thickness (min) Stacked photovias

125 300 75 125 18 40 No

100 200 50 75 12 30 No

70 110 30 40 7 30 No

50 80/70 20 30 5 20 Yes

photoimageable dielectric. The liquid and dry-film PIDs have virtually identical electrical properties, and have been qualified using the same accelerated stress tests and acceptance criteria.8 Current design rules for SLC technology build-up layers are given in Table 5.1. Larger PCBs can be designed with more relaxed rules to achieve optimized yields and minimize the cost.9 5.3.2 SLC processes10

SLC technology is based on the use of photoimageable polymeric systems to form blind microvias in the dielectric material between layers of circuitry. The use of PIDs allows all microvias on a panel to be formed in parallel, with no incremental per-via cost. Its use is particularly advantageous on applications having high densities of vias (e.g., more than 50,000 on an 18 × 24-in. panel). Figure 5.14 is a typical flowchart of the SLC technology fabrication process, including the options for multiple build-up layers and RFPs. Figures 5.15 and 5.16 provide a pictorial representation of the required processes. At this level the process for SLC technology is the same whether a liquid or dry film PID is used. Figure 5.17 presents flowcharts that include details for the PID processing, highlighting the process differences between liquid and dry-film PIDs. The liquid and dry-film PIDs do give slightly different via wall profiles. The liquid PID has tapered via walls, as seen in Fig. 5.13, while the dry-film PID has essentially vertical via walls, as shown in Fig. 5.18. The tapered via walls provide good plating coverage on the via walls and base; the vertical walls allow for a smaller via top opening, and correspondingly smaller capture land, for a given via bottom diameter. The use of a liquid PID requires two unique pieces of equipment: a curtain or slot coater (with associated drying ovens) and a leveling tool (surface sander). Curtain coaters are common tools in many PCB shops, but if a shop does not already have one, installation of a curtain

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Circuitize Inner Layer Cores Filled Sub-Composite PTH Option

Laminate Sub-Composite No Sub-Composite PTH Option

Drill, Plate, and Fill Sub-Composite Holes

Apply Photoresist, Expose, Develop, Etch, and Strip Last Build-Up Layer Only

Apply, Image, and Cure PID Layers 1 to N-1

Drill Composite Holes

Surface Treat for Cu Adhesion Plate Vias and Surface

Repeat N Times

Apply Photoresist, Expose, Develop, Etch, and Strip After Last Build-Up Layer

Apply Solder Mask and Surface Finish Profile Cards from Panel Final Test and Inspect

Figure 5.14

Process flow chart for SLC technology.

coater to produce SLC technology PCBs represents a significant capital investment (several million dollars). The leveling tool is required to planarize the surface of the cured liquid PID to accommodate fine-line photolithography on its surface. The liquid PID provides a conformal coating over the underlying circuit features, producing nonuniform planarity. The leveling operation also removes a lip of exposed PID that overhangs the via openings in these processes.

(Case of 1 double sided build up layer) Base Core (with circuitized layers)

Drill Thru Hole

Circuitize

Cu Plate

Apply Dielectric

Photo Via Build

Figure 5.15

Circuitize

Solder Precoat

Schematic diagram of SLC process flow.

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(Case of 1 double sided build up RFP) Base Cores (with circuitized layers)

Apply Dielectric

Drill Thru Hole

Photo Via Build

Cu Plate

Cu Plate

Resin fill

Circuitize

Schematic diagram of SLC process flow with resinfilled PTHs.

Figure 5.16 Circuitize

Solder Precoat

Liquid PID

Coat & Dry Liquid PID (1st side)

Dry Film PID

Vacuum Laminate (2 sides)

Expose & Develop PID (1st side)

Pre-Bake PID

Partial Cure PID (1st side)

Expose PID (2 sides)

Coat & Dry Liquid PID (2nd side)

Post Expose Bake PID

Expose & Develop PID (2nd side)

Develop PID

Full Cure PID (both sides)

UV Flood and Cure PID

PID process details for SLC technology.

Figure 5.17

Level PID Surfaces

Inspect & Repair (optional) PID

Inspect & Repair (optional) PID

Cross section of an SLC microvia with dry-film PID.

Figure 5.18

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The use of a dry-film PID requires only one unique piece of equipment: a vacuum laminator. Vacuum laminators are common in the production of PCB; in addition, the capital to obtain one is significantly less than that required for a curtain or slot coater. The dry-film PID has excellent planarization and does not require a leveling process due to the film’s low solvent content and low shrinkage and the vacuum lamination process. 5.3.3 Reliability and applications

Normal reliability requirements for SLC technology PCBs include the following tests (zero fails): 1. Temperature/humidity/bias ■ 85°C/85 percent RH/5 V, 1000 h ■ 110°C/85 percent RH/5 V, 150 h 2. Thermal cycle ■ −40 to 65°C, 5 cycles ■ −25 to 115°C, 2500 cycles 3. Flammability ■ UL 94 V-0 SLC technology products may also be qualified to meet additional requirements for specific applications. SLC technology has been used to manufacture high-density PCBs for integrated circuit package substrates, computer and communications equipment, and consumer electronics. Board sizes up to 65 in2 (400 cm2) have been produced in high volumes. Figure 5.19 is an example of the system board used in one of IBM’s ThinkPad laptop computers, and Fig. 5.20 illustrates the main board used in a Sony digital camcorder. Figure 5.21 shows a high-end 3-D graphics adapter having four layers

Figure 5.19 ThinkPad motherboard with SLC technology.

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Figure 5.20 Sony digital camcorder motherboard with SLC technology.

3-D graphics adapter card with SLC technology.

Figure 5.21

of build-up on each side, and Figs. 5.22 and 5.23 illustrate single- and multichip IC modules used on this graphics card. Many of the SLC technology products have been used with chip scale packages and direct chip attach, both flip chip and wire bond. 5.4 Laser Direct Imaging11 High-density interconnection positions a spectrum of technologies and processes on the PCB fabricator’s capability roadmap. The printed circuit board industry is continually moving toward smaller features to achieve the interconnect density required by present and future packaging technologies. As feature sizes decrease and signal speeds increase, the demands on the manufacturing processes for low defect density and high quality become increasingly stringent. Accordingly, the lithography of HDI circuits—namely the patterning of conductors and pads—becomes a most demanding stage in the fabrication process. Substantial efforts have been directed at meeting HDI fabrication challenges by continuous improvement of various process stages. However, lithography requirements seem to have been neglected. LDI systems naturally lend themselves to addressing these HDI challenges. In addition to their proven advantages in obviating phototooling and Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Flip chip single-chip module with SLC technology.

Figure 5.22

Flip chip multichip module with SLC technology.

Figure 5.23

repeated defects in a standard fabrication environment, they provide an indispensable tool for HDI fine-feature requirements. Laser direct imaging in general and thermal direct imaging in particular provide a readily available patterning tool for high-density interconnection fabrication. The ultrafine feature imaging capability matches or exceeds the most demanding HDI pattering applications. The precise patterning capability offered by thermal direct imaging (TDI) may, in some cases, become an enabling capability for HDI PCB manufacturers; higher density and more complex parts can be accepted for production, thus enabling fabricators to shift a higher percentage of their production capacity to higher-density and highermargin jobs. In addition to fine-line patterning capability, LDI lends itself readily to microvia formation. It utilizes “best-fit” registration of the imaged pattern to the drilled microvia holes on each individual panel through real-time hole location recognition and adaptation. Positive liquid resist provides good coating for via holes, eliminating the need for land area associated with dry-resist tenting, actually enabling padless via holes. LDI also may be used for CO2 laser drilling conformal mask generation. It is also a high-capability patterning tool for demanding Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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controlled-impedance applications. The combination of accurate hole generation and image registration, which eliminates the need for land, is expected to influence future design rules.12–15 5.4.1 HDI lithography capability

HDI involves a variety of applications, materials, and processes. The following capabilities are directly or indirectly related to lithography: ■

Finer lines and spaces. These are most commonly 3 mil and under. Packaging substrates utilize 2-mil lines and spaces as mainstream. Figure 5.24 illustrates how routability options on the mounting layer become scarce with increasing IC complexity and higher I/O count. Clearly, fine-line imaging capability, down to 2 mils or less, would allow for more interconnections per layer, thus decreasing interconnect structure by lowering the layer count. In the extreme case, shown in the lower left corner of Fig. 5.24, only an imaging capability of 2-mil lines and spaces enables production of an interconnect structure for this IC type.

■

Smaller holes. With HDI technology, 50-µm via holes become commonplace. Made possible with the advent of laser drilling, smaller holes are being drilled to increase circuit board density.

■

Smaller pads. With smaller via holes, smaller pads are possible. As illustrated in Fig. 5.24, small pads allow for more tracks per channel on HDI circuit boards.

■

Tighter registration. Feature-to-feature, pad-to-hole, and side-to-side registration all require higher registration accuracy of smaller features and tighter spaces between them.

Figure 5.24

Routability options with high-I/O ICs.

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181

Tighter line width control. This control is necessary for impedance uniformity and for buried resistors and capacitors.

LDI has proven itself as a viable patterning tool for demanding applications. Most currently available systems use UV light on UVsensitive resist for imaging. These LDI machines generally work with a special LDI dry-film resist that is four to five times more sensitive than the standard UV dry film in order to provide an acceptable productivity level. A recently introduced TDI system works with an IR light source on a matching liquid resist (thermal resist). This system’s strongest feature is its extraordinarily sharp and consistent imaging capability. Some of the benefits discussed in this section are unique to the TDI system, and are accordingly pointed out. With the high-definition patterning capability of thermal direct imaging, HDI application limits are pushed further. Fine-line capability down to 2-mil lines and spaces becomes common practice with TDI. High-resolution patterning coupled with thin liquid resist facilitates improved fine-line capability. This combination allows the use of existing wet process lines commonly used in conventional intermediate interconnect fabrication processes. The following thermal direct imaging characteristics provide key advantages for HDI lithography. First, high-definition direct imaging with 5-µm resolution is achievable, along with a 5-µm square spot for sharp and accurate feature definition. A thermal positive resist with binary reaction provides true digital-quality imaging with a wide process latitude. With a positive etch resist, levels of near-shorts and microshorts are significantly reduced or eliminated. The positive-working liquid resist is suitable for tent-and-etch microvia processing. The tent-and-etch process, also known as the panel plating process, allows a straightforward sequence with a lower number of process steps when compared to a pattern plating process. The use of liquid resist allows coating thickness down to 5 µm, which provides higher-accuracy imaging and etching at a lower cost, as well as reduced material waste. Also, TDI allows the elimination of film-based defects, costs, and processing time while enabling work flow flexibility of direct CAM-to-panel imaging. A higher etch factor, characteristic of thin resists, enables narrower spaces, avoiding microshorts and near-shorts associated with lower etch factors. 5.4.2 Subtractive patterning

Features—including conductors, spaces, and pads—are getting smaller for ordinary applications, and even smaller for HDI applications. Boards with 2-mil lines and spaces along with 2- or 3-mil annular rings are not uncommon.

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Subtractive processing is highly regarded as a straightforward printand-etch process, very similar to the inner-layer patterning process. Positive liquid resist, which protects via holes, makes this process feasible. Furthermore, hole wall protection capability may be the only factor that allows small annular ring capability in a panel-plating process. In fact, positive liquid resist may even allow padless hole patterning. Figure 5.25 is a demonstration of a padless feature generated by thermal direct imaging technology. This imaging capability naturally fits in a build-up process utilizing laser drilling over an RCC layer. In such cases, the subtractive microvia process is inherently adequate. The patterning process would be tentand-etch. Tenting the vias with dry resist poses a growing difficulty as annular ring sizes shrink. As the annular ring becomes smaller, the dry tenting patch has less hold area, which in turn gives rise to a likely via failure. Positive-liquid-resist-based LDI—with its via wall protection capability—makes patterning of such features possible. 5.4.3 LDI as conformal mask for laser drilling

CO2 laser drilling involves the formation of a mask that defines the location and extent of the vias to be drilled. With RCC material, the mask is the copper, which cannot be drilled by a CO2 laser. Thus, the mask preparation here involves the standard print-and-etch process of the microvia holes to be drilled. Thermal direct imaging aids CO2 laser drilling with its high definition and high geometric accuracy. The holes defined by a TDI system are very accurate and feature a controlled diameter. In addition, hole location is very precise due to the inherent geometric accuracy of the system. 5.4.4 Controlled impedance lithography

High-speed applications (i.e., mobile communications) require tighter impedance control. Controlled impedance impacts lithography in the

Figure 5.25 Micrograph of a 75-µm via in a 50-µm trace.

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following two areas: line width control and interlayer registration. Line width uniformity requirements as tight as 2 percent have been presented to fabricators for applications requiring controlled impedance. Such tight line width control capability is rare in conventional PCB lithography systems due to their inherently loose edge definition. Thermal direct imaging addresses this demanding requirement by providing a sharp edge and precise line width control. TDI process capabilities that meet or exceed these requirements have been demonstrated with unmodified wet-processing equipment. Another aspect of controlled impedance is the registration between pads or conductors on the opposing sides of a panel. This is also significant in high-frequency applications such as mobile communication devices. The issue becomes particularly critical with HDI technologies, where the dielectric material is considerably thinner compared to standard applications. LDI offers the capability of precisely registering to existing holes, ensuring resultant pad-to-pad registration. 5.4.5 Registration capability and accuracy

As HDI pushes the envelope of circuit density, it also increases the requirement for much tighter registration. With much smaller laserdrilled via holes, smaller pads around such holes are designed to enable more tracks per channel. This in turn calls for drastic improvement of pad-to-hole registration, leading to smaller annular rings. Since LDI obviates the dimensional instability of phototools, substrate feature placement is inherently more accurate. The ability to accurately locate pads facilitates the smaller tolerance of pad location relative to the holes; hence, the pads can be made smaller, saving precious board real estate. Moreover, as a real-time imaging system, LDI can adapt imaging to varying board dimensions. By looking at existing features on the board during imaging time, the system can adjust geometric parameters to best fit the microvias and other board features. This further enables smaller pad or annular ring size and further saves space to be used for denser routing. Film-based imaging uses artwork having preset dimensions, which cannot be modified unless a new film is plotted with different dimensions. While exposure machines align the films to targets on both sides of the panel, this alignment merely rotates and shifts the x and y axes of a fixed image to its panel. Minimization of image-to-target misalignment is usually achieved by optimizing (dividing) the errors among all the targets used. With exposure machines, no scaling correction can be applied to the image in order to fit the misplaced targets. A feedback procedure may be used after stripping, in which the scale of the image may be modified to fit the observed distortion of the postimaging process. This is done by producing a new film with the optimized corrected scales. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Laser direct imaging has inherent capabilities for improved image registration. The circuit image is given as a CAM bitmap file that can be modified before or during the actual imaging process, as opposed to a film “hard copy” that is fixed for all panels imaged with that film. Through manipulation of the image data and the LDI electronics, the image can be manipulated to compensate for misplacement errors, thus improving imaging registration. Such modifications may be universal (global scale or rotation) or local (compensating for nonlinear errors). Figure 5.26 shows a few examples of image data manipulation that LDI can implement as part of registration compensation. The image scale can be modified locally by controlling position-dependent variations in the laser exposure (pixel) rate or by altering the relative speed between the imaging head and the panel. Figure 5.26a illustrates this for one axis, while Fig. 5.26b shows a combined effect of changing a linear scale in both axes. For example, scale

Figure 5.26

LDI image adaptation.

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reduction in the y-axis can be achieved by gradually increasing the pixel imaging rate in the y-axis while the imaging operation progresses in the x-axis, and maintaining a constant relative speed between the laser beam and the substrate. Alternatively, the relative speed in the y-axis between the laser beam and the substrate may be gradually reduced, while the pixel imaging rate remains constant. Such a method can also be used locally to compensate for nonlinear hole misplacement. Another example focuses on controlling the start timing of the actual scanning. This facilitates a local shift profile, such as the one shown in Fig. 5.26c, in which the start position in the y-axis changes while the x-axis speed is constant. This results in local corrections in the y-axis.

5.5 Special Considerations and Reliability 5.5.1 Notes on photo-defined vias2

The benefit of using photo-defined via technology is that it can form thousands of vias at once (i.e., it is a mass production process). However, there still are several drawbacks to the use of photo-defined via technology that should be noted. ■

Only photosensitive dielectric can be used, instead of the wide range of dielectrics that can be used with laser drilling technology.

■

Making a dielectric photosensitive can degrade its electrical performance and reliability.

■

Photovia technology is limited to blind vias with small aspect ratios (less than 2:1); vias must be formed and plated at every layer.

■

This approach cannot be used with laminated metal foils.

■

Minimum via size in production is limited to about 75 µm with most technologies.

■

This technology generally requires starting with a rigid PCB core and building outward; this core has generally poor flatness (nonuniform dielectric thickness) and dimensional performance.

■

Photovias cannot go through unpatterned metal layers.

5.5.2 Design guidelines and equipment with photo-defined vias

Table 5.2 illustrates some design guidelines for dry-film or liquid-type photosensitive dielectrics. Via diameter can be as small as 50 µm and trace width can be less than 25 µm. In comparison, via diameter can be 25 µm for laser drilling.16 The equipment needed for photo-defined via technology includes exposure unit, developer, and wet processor. The suppliers of exposure units Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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TABLE 5.2

Comparison of Dry-Film and Liquid Types of Photoimaging Technology Dry-film type Epoxy acrylic

Applicator

(Vacuum) laminator

Thickness range (µm) Minimum opening (µm) Trace width Electrical performance Chemical resistance Handling Cost

Liquid type

Polyimide

Epoxy

Polyimide

25–50

Roll laminator Screen print Spray coat Curtain coat 25–50 10–25

Screen print Spray coat Roll coat 10–20

70

70

70

50

50 Good

50 Good

50 Good

25 Excellent

Acceptable Easy Fair

Good Difficult High

Good Fair Low

Very good Difficult High

are Bacher, Byers, Colight, Csun, Dupont, Dynachem, Gyrex, Hi-Tech, Mirmir, Morton, Olec, Optical Radiation, ORC, Peak Measuring, Tamarac, and Theimer. The suppliers of developer are Advanced Chemill Systems, ASI, Chemcut, Ciba-Geigy, Circuit Services, Danippon Screen, Glenbrook, James River, Lantronic, Microplate, Quantum, Rexham Graphics, and Technifax. The suppliers of wet processors (develop-etchstrip) are ASI, Chemcut, Hollmuller, Lantronic, and Schmid.2 5.5.3 Reliability data

Some qualification tests reported in the literature17–19 show promising results for photo-defined via technology. Also, photovia processes are currently being used. Ibiden, IBM at Yasu, and Micro Via, Inc. are already running volume production. 5.6 Impact of HDI on Fine-Line Lithography20 With pin densities increasing above 20 I/O per cm2, and total pin counts for high-end devices quickly exceeding 300 pins, area-array technology has become the interconnect package technology of choice. While 1-mm BGA pitch is standard for high-end applications today, 0.8- and 0.5-mm pitch are also in limited use, and will become more predominant as predicted by the National Technology Roadmap for Semiconductors. These fine-pitch packages, which include ball grid arrays and chip scale and flip chip packages, will all require interconnect lines and spaces that are predicted to reach 10 µm. While microvia and other build-up technologies have proven their ability to meet the exacting requirements of fine-line interconnects, patterning solutions have only recently made significant improvements. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Contact printing processes are rapidly approaching maturity and will have great difficulty supplying the patterning needs for costeffective fine-line production. LDI solutions have the ability to record fine features and provide best-fit image registration, both pivotal in breaking through fine-line patterning roadblocks. LDI is presently being introduced in high-performance PCB production environments. As this technology becomes accepted, PCB and high-density interconnect suppliers will gain flexibility and quality improvements. The concept of “each board is an original” (typified by laser printing processes) can create new opportunities for custom and semicustom applications. 5.6.1 Current technology limitations

To provide the technical solutions in a cost-effective manner, development needs to take place within the existing PCB manufacturing process. Conventional technology is limited for three major reasons. First, the conventional drilling processes limit feature sizes to about 100 µm with 50-µm placement accuracy. Second, the inherent instability of organic material creates extreme registration errors as a result of processing. Third, the abilities of conventional imaging systems to produce dense features with good yields are reaching their limits. A partial solution to the drilling problem is through the use of microvia, or build-up multilayer processes. As shown in Fig. 5.27, the first inner layers are processed conventionally, with conventional vias. A thin layer of laminate is applied with heat, pressure, and vacuum to fill the conventional holes. The copper is then etched down to 3 to 5 µm, allowing microvias to be laser-drilled or photo-etched. Copper is then redeposited to about 20 µm, covering the board and contacting the outside copper contact pads of the conventionally processed core. The plate is then laminated with dry-film resist and the board returned to finish

Figure

5.27

Typical

microvia

construction.

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with conventional processes. A completed example of this process is shown in Fig. 5.28, which is a cross section taken from a BGA package carrier (interposer) in a Fujitsu cellular phone. Examination of the conventional blind vias displays the processing-induced registration errors. These registration errors can be significant, and are induced during the lamination process. Each layer that consists of an epoxy-fiberglass core will distort under the pressure (up to 200 psi) and heat (up to 350°F) of lamination. This distortion can vary with direction, and may be nonuniform as well. Circuit board material such as FR-4 can change by as much as 4 to 6 µm/in., and other organics such as polyimide can change by 25 to 50 µm/in. The registration problem can be solved one of two ways: use of materials with very low coefficient of thermal expansion (CTE) to minimize shear stresses, or compensation for the movement. While discussion of the first solution is outside the scope of this paper, the second solution is at the heart of it. Conventional imaging systems for PCB and high-density interconnect (HDI) are traditional contact printers, one-to-one projection scanners or, more recently, step-and-repeat projection printers. All three have advantages and disadvantages, depending on the size and type of features to be imaged. Contact printers are well known to the PCB industry and are low in cost and have low recurring tooling cost and good productivity for many applications. However, these tools have no ability to scale the artwork to compensate for distortion, and will not match the feature size and overlay accuracy required by HDI and microvia technology. (Some fabricators have achieved marginal success with feature size by reducing the field to less than 14 × 14 in2, but the distortion and scaling compensation issues remain.) One-to-one projection scanners have much better resolution capability than contact printers, are known solutions, and can image over large substrate sizes. The phototool is typically glass and thus has higher recurring costs. Again, these systems suffer from poor overlay accuracy and do not provide scaling compensation for the laminate distortions.

Eight-layer photovia multichip package carrier on six-layer main board.

Figure 5.28

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Step-and-repeat systems have made a brief appearance, and can meet the resolution and overlay requirements for HDI. They are also able to compensate for scaling to some extent, but cannot independently scale orthogonal directions. The image size is limited to 4 × 4 in2, which relegates this tool exclusively to interposer imaging; it cannot be used for general PCB applications. Glass masters again make the recurring tooling costs expensive. 5.6.2 Market drivers

Evolution of technology within the semiconductor industry has continued to drive interconnect densities to higher levels, requiring more sophisticated packaging solutions. As the pin counts increase above 20 I/O per cm2, area-array technology has become the predominant packaging solution. This can be seen from the Semiconductor Industry Association (SIA) roadmap (Figure 5.29), where high-end packages quickly exceed 1000 pins. Quad-flat packs are predicted to have maximum pin counts of about 300. With the majority of product categories exceeding this pin count within the next several years, area-array technology will dominate package and interconnect solutions. While pin count is increasing, the spacing between contact points must decrease. An example of this is seen in the high-end ASIC devices, pin counts of which are predicted to be around 5000 by the year 2015. If the spacing of ball grid arrays remains at around 1 mm, then the interposer (carrier) will need to be at least 3 in. per side to sustain this number of pins! The National Technology Roadmap for Semiconductors (NTRS) (Fig. 5.30) displays these trends more clearly. Ball grid array, chip-scale packaging and flip chip substrates all require higher-density package solutions. Within 5 years, the infrastructure to support 0.65mm array pitch should be in place. This technology will require feature sizes that will extend down to 10 µm.

SIA package pin count segmented by product category.

Figure 5.29

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First Year of IC Production

1997

1999

2001

2003

2006

2009

2012

BGA SUBSTRATES PTH pitch (mm) 1.0 0.8 0.65 0.50

FINE PITCH BGA/CSP Line width/spacing (µm) 50 / 65 40 / 50 30 / 35 25 / 33

FLIP CHIP SUBSTRATES Line width/spacing (µm) 50 / 50 34 / 38 30 / 30 20 / 20 10 / 11 Research Required

Development Underway

Qualification/Pre-Production

This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution.

Figure 5.30 NTRS interconnect roadmap—ball pitch and line width/spacing targets. (Source: National Technology Roadmap for Semiconductors)

Not only is pin count increasing, but the cost per cm2 of board area is decreasing, and the total number of array packages is predicted to exponentially increase as through-hole processes are replaced. Pin grid, ball grid, and chip-scale packages all display this enormous growth potential, as seen in Fig. 5.31. 5.6.3 LDI benefits and challenges

LDI tools are more complex than conventional tools, and have demonstrated the ability to record fine-line features. LDI provides other

Comparison of organic substrate market price.

Figure 5.31

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important features that are pivotal in breaking through the roadblocks to large-area HDI patterning. The tool must accommodate the processinduced panel distortions, meet production throughput requirements, and maintain sufficient process latitude to support the subsequent development and etch processes. LDI tools are unique in that each image can be considered an “original.” This implies that each image can be customizable to accommodate some specific process artifact. This customization can range from bar coding of each image within a panel to specification of unique image “compensation” values, which change the image database to precompensate for a priori distortions. At current technology feature sizes (greater than 50 µm), linear image scaling that is independent for the x- and y-axes of the image is sufficient. As the feature sizes and accuracy requirements decrease, higher-order distortions may come into play. This could mean that generalized image mapping and nonlinear “predistortion” might be required to accommodate the instability of the media. LDI tools differ significantly from conventional phototools in that they replace production tools that perform massive parallel processing (e.g., contact printing of the entire image) with the serial process of rasterimaging a bitmap. As feature sizes decrease, the amount of information to be processed increases. (Note: with conventional imaging, the serial bitmap imaging process still exists, but it takes place offline, where the time to image does not significantly impact the production throughput.) In addition, the resolving power of the imaging system increases. 5.6.4 Future tool requirements

To compare existing to future LDI tool requirements, we can borrow a concept from the field of information processing known as spacebandwidth product (SBP): SBP = (number of pixels) × (average data rate) This metric is a measure of the amount of information handled within a given period. However, this metric alone does not adequately describe the complexity of the imaging system, since the pixel size could be arbitrary. Since the f-number of the optical system is proportional to the pixel size, and since SBP is an area function, we can divide the SBP by ( f-number)2 to give a more useful comparative metric. Figure 5.32 shows a potential LDI roadmap, including two additional raster-imaging tools for comparative purposes. At the low end is a conventional drum laser photoplotter. At the high end is a mask pattern generator used for fabrication of IC photomasks. As resolution of the

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Potential LDI roadmap compared to conventional photoplotter and semiconductor mask pattern generator.

Figure 5.32

LDI tools increases, so does the information content and the complexity of the optical systems. Two inferences can be made from this rough comparison. One could conclude that given current technology, the cost of the 10-µm-feature LDI tools would start to approach that of IC mask pattern generators. A second inference could be made that a revolutionary change to the technology base is required to provide cost-effective solutions. Clearly, reduction in the metric SBP/( f-number)2 will yield a less costly solution for a given performance level. Reduction in the amount of information to be handled by the LDI tool is one way to manage the space-bandwidth product issue. One technique is to minimize the number of pixels required to image a minimum feature size. This leads to an artifact of LDI systems known as grid snapping, as shown in Fig. 5.33. Here, the image bitmap is shown for a 4-pixel per minimum line width data set. Grid snapping to the nearest pixel location is evident, especially on diagonal lines. This artifact can be minimized by increasing the number of pixels per minimum feature. However, for a given maximum average data rate, the throughput of the tool will be reduced by the increased number of pixels in the bitmap.

Bitmap of 4-pixelper-minimum-feature database displaying grid snap artifacts.

Figure 5.33

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Theoretical aerial image of a 25-µm feature (6.25-µm pixels with 6.25-µm spots). Figure 5.34

Another method to manage the SBP/( f-number)2 metric is to reduce the optical resolution. For example, a 25-µm feature can be imaged using four 6.25-µm laser spots on 6.25-µm grid (pixel) spacing, or it can be imaged using four 12.5-µm laser spots on 6.25-µm grid spacing. While the 12.5-µm laser spot system could potentially be more cost effective, there is a significant reduction in process latitude. This is evident in the computer simulations shown in Fig. 5.34, which illustrates that the 12.5-µm spots give shallower aerial image sidewalls than the 6.25-µm spots for a 4-pixel-per-feature image. The larger spot size will require better control over the resist chemistry, process, and exposure to retain equivalent control in feature resolution and critical dimension parameters. As the semiconductor industry creates components with greater pin counts and higher pin densities, the interconnect industry must keep up with higher-resolution tools and processes. While development of the LDI tool faces definite technical challenges ahead, the ability to meet the expected roadmap targets will also be dependent upon photoresist suppliers, material manufacturers, and process developers. As feature sizes continue to shrink, even the cleanliness of the process environment must continue to improve. The ability of the PCB and HDI industries to provide a solution will not be dependent upon any one technology. Communication and cooperation between suppliers will continue to be pivotal in achieving success. 5.7 References 1. Estes, W. E., T. R. Overcash, S. Padlewski, B. D. Neve, E. B. Murray, R. E. Anderson, R. C. Mason, J. P. Lonneville, W. L. Hamilton, and M. Periyasamy, “Photodielectric Dry Films for Ultra High Density Packaging,” Proceedings of SMI, pp. 47–53, San Jose, CA, September 1997. 2. Lau, J. H., and C. Chang, “An Overview of Microvia Technology,” Circuit World, 26(2):22–32, January 2000.

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3. Sutter, T. C., “Liquid Photoresist Systems—An Overview,” Board Authority, 1(3):22–29, October 1999. 4. Manas, J., “Direct Write Film,” Board Authority, 1(3):14–17, October 1999. 5. Barr, D., and D. O. Powell, “Technology from Japan: Surface Laminar Circuit (SLC) Technology,” Board Authority, 2(1):87–90, April 2000. 6. Tsukada, Y., “Surface Laminar Circuit and Flip Chip Attach Packaging,” Proceedings of 42nd ECTC Conference, 1992. 7. Tsukada, Y., S. Tsuchida, and Y. Mashimoto, “Surface Laminar Circuit Packaging,” Proceedings of 42nd ECTC Conference, pp. 22–27, 1992. 8. Boyko, C., F. Bucek, V. Marovich, and D. Mayo, “Film Redistribution Layer Technology,” Proceedings of 2nd International MCM Conference, pp. 196–199, 1993. 9. Carpenter, R., and I. Memis, “SLC: An Organic Packaging Solution for the Year 2000,” Proceedings of NEPCON-West Conference, 1996. 10. Tummala, R., E. Rymazewski, and A. Klopfenstein, Microelectronics Packaging Handbook, Subsystem Packaging, Chapman & Hall, pp. 265–268, 1997. 11. Atiya, Y., “Thermal LDI: Meeting HDI Lithography Challenges,” Board Authority, 2(2):10–14, July 2000. 12. Ganjei, J., “Advantages and Disadvantages of Liquid vs. Dry Film,” Printed Circuit Fabrication, May 1997. 13. Ehlin, M. J., “The Wonderful World of Laser Direct Imaging and How to Realize It,” Board Authority, 1(3):50–55, October 1999. 14. Atiya, Y., and E. Halevi, “An Innovative LDI,” CircuiTree, June 1998. 15. Taff, I., and H. Benron, “Liquid Photoresist for Thermal Laser Direct Imaging,” Board Authority, 1(3):66–71, October 1999. 16. Numakura, D. K., S. E. Dean, D. J. McKenny, and J. A. DiPalermo, “Micro Hole Generation Processes for HDI Flex Circuit,” Proceedings of the HDI Expo, pp. 443–450, San Jose, CA, September 1999. 17. Gonzalez, C. G., R. W. Wessel, and S. A. Padlewski, “Epoxy-based Aqueous Processable Photo Dielectric Dry Film and Conductive Viaplug for PCB Build-up and IC Packaging,” IEEE Trans. Adv. Packaging, 22(3):385–390, August 1999. 18. McDermott, B. J., and S. Tryzbiak, “The Practical Application of Photo-defined Microvia Technology,” Proceedings of SMI, pp. 199–207, San Jose, CA, September 1999. 19. Nargi-Toth, K., and P. Gandhi, “Manufacturing Methodologies for High Density Interconnect Structures,” Proceedings of the CSI Technical Symposium, pp. 63–70, San Jose, CA, September 1998. 20. Tamkin, J. M., “The Impact of HDI on Fine-line Lithography,” Board Authority, 1(3):56–59, October 1999.

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6 Microvias by Etching

6.1 Introduction The development of very complex ICs with extremely high I/O counts and steadily increasing clock rates has forced electronics manufacturers to develop new packaging and assembly techniques. In addition, more and more electronic devices have to be portable and, consequently, system integration, volume, and weight are rapidly gaining importance. At the same time, the pressure to eliminate any environmental impact and to reduce cost is exponentially increasing. As a result of these considerations, the future substrates have to be hightech, low-cost interconnects characterized by very fine lines and spaces and the use of microvias, as both through-vias and blind vias as well as combinations thereof. In addition, the increasing demand for 3D packaging calls for flexible and rigid-flexible designs and highlights the importance of new interconnect substrate technologies able to cope with these recent and emerging requirements in modern electronics.1 Microvias can be formed by various etching techniques. Plasma etching and chemical etching can be extremely cost effective for generating high volumes of small holes in dielectric layers. In either case, the process cost is derived from the number of holes in a given working area. The basic principle of via etching is to create a mask that defines the positions and sizes of the holes. This may be achieved by using dry film to image, then etching a hole pattern in a copper layer, or simply by using the dry film as the etch mask by imaging and developing. Both methods are isotropic such that they etch inward while they etch downward. All holes are generated simultaneously, and the process time is dependent on how long it takes to erode or dissolve the unmasked dielectric. Plasma etching has the added benefit of removing 195

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organic contaminants, and with careful conditioning the amount of slope (undercut) created in the hole can be minimized. Both plasma and chemical etching processes can create blind vias, usually using the target pad as a means of defining the bottom of a blind via.2 6.2 Etching Processes 6.2.1 Chemical etching

Chemical etching is the least expensive process for generating small holes on dielectrics. Wet etching by hot KOH has been used for polyimide films. This formation technique is capable of mass via generation in that all vias are formed at the same time without regard to number or diameter.2 6.2.2 Plasma etching

The dry etching process requires procedures such as plasma etching and copper thinning (etch-back). Microvia hole (MVH) formation by gasmicrowave plasma (GMP) has been promoted by Dyconex of Switzerland and its licensee, Hewlett-Packard. Dyconex has 16 licensees worldwide because it sells a basic plasma drill for $55,000, compared to a laser drill that costs $500,000 and up or a photoimaging facility that requires around $300,000. The plasma equipment can be obtained from Advanced Plasma Systems, Inc. or Plasma Etch Inc. A step-by-step process flow is illustrated in the following list: Step 1. Fabricate core by standard double-sided rigid or multilayer board methods. Step 2. Laminate adhesive-coated copper foil to core. Step 3. Print and develop via pattern. Step 4. Etch via pattern and strip etch resist. Step 5. Plasma-ablate dielectric and etch copper overhang. Step 6. Electroless-copper-plate panel. Step 7. Laminate photo resist; print and develop outer-layer image. Step 8. Pattern-electroplate copper. Step 9. Strip resist and etch. There are some plasma-etchable materials like adhesiveless polyimide foil, FR-4 buttered Cu-foil, Aramid-paper-reinforced FR-X, liquid crystal polymer (LCP), and Cu foil buttered with FR-5 or polyimide glass or cyanate ester (CE) resin.2

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6.3 Plasma Etching for Via Formation 6.3.1 Plasma ablation3–5

Plasma has long been known as a dry-etching medium and is widely used in the semiconductor industry for the formation of very fine features. In 1991 Dyconex (Zurich) started to apply plasma ablation for the mass formation of microvias in organic material.2 Since then, the technology and the related equipment have been developed for volume production of rigid, rigid-flexible, and flexible HDIs and multichip modules (MCMs) for almost any kind of applications. The process is known as DYCOstrate®. The basic process sequence is shown in Fig. 6.1 for through-vias as well as blind vias. Usually, the base material is a copper-clad dielectric where the copper is in a first process used as an etching mask for the plasma ablation. In order to generate the mask, the copper is photochemically patterned by conventional PCB technology (via definition). When thin dielectrics, such as polyimide films, are used, the plasma generates micro-through-vias (Fig. 6.1a), whereas blind microvias are formed when a target pad is placed underneath the opening in the copper mask (Fig. 6.1b). In the case of through-vias, the overhanging copper fringes generated during the isotropic plasma etching process are too small and do not affect the subsequent plating. When blind vias are etched, the copper overhang can be critical and, due to shielding effects and a reduced exchange of chemicals, reliable plating is not possible. Therefore, a proprietary hole-forming method has been developed. During this process, the copper fringes are etched off completely and, at the same time, the total thickness of the copper layer is reduced to approximately 5 µm. This process allows the blind microvias to be plated without any addi-

Process flow chart for plasma-etched through-hole and blind vias.

Figure 6.1

(a)

(b)

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tional precautions and, additionally, minimizes the overall copper thickness, resulting in an improved yield in the subsequent photochemical patterning of the outer layers. Figure 6.2 shows microsections of a through-via with a diameter of 60 µm and a blind microvia with a diameter of 100 µm. As is clearly visible in Fig. 6.2b, the thickness of the plated copper is very uniform, a result of the teacup-shaped microvia. Another important advantage of plasma drilling is that it is a parallel process: all via holes are formed simultaneously. In order to maximize throughput and optimize etching uniformity, dedicated plasma drilling equipment has been developed that allows the simultaneous front and back processing of six panels (18 × 24 in2). In addition to the formation of microvias, plasma can also be used as a micromilling tool to form any kind of microfeatures. Figure 6.3 shows a summary of various possibilities that have all been applied already in specific applications. 6.3.2 Build-up constructions

The use of microvias automatically implies so-called sequential build-up constructions, as in the ceramic multilayer technology. In general, there are basically two build-up options, depending on the dielectric material used. For flexible dielectric materials, in many cases a rigidizing carrier is necessary in order to stiffen the flexible substrates locally or completely.3 In the case of rigid dielectric materials, a rigidizer is not necessary, yet with the drawback of being restricted to rigid applications only. The whole concept of this technology approach is shown in Fig. 6.4.

Polyimide

(a)

(b)

Micrographs of plasma-etched (a) through-hole via and (b) blind via.

Figure

6.2

Various microstructures processable by plasma ablation.

Figure 6.3

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Basic concept for plasmaprocessed HDI substrates.

Figure 6.4

In addition to the two options, combinations of flexible and rigid build-ups can be designed for specific requirements. Figure 6.5 shows a number of microsections taken from various examples used in medical devices, avionics, telecom, etc. While some of the build-ups are very simple, others are extremely complex, particularly when constraining cores with CIC, CMC, or carbon fibers are used. The nomenclature 3D2C3D, for instance, means that there is a three-layer DYCOstrate® on the backside. One particular build-up has turned out to be very powerful and at the same time cost effective. This build-up is a 4D construction, as shown in Fig. 6.6. Besides all the pros regarding the electrical performance, like EMI shielding, less cross talk and improved signal integrity, the total thickness of this build-up is approximately 200 µm. When such a substrate is bonded to a heat sink, the thermal management is improved substantially—in particular when thermal microvias are placed underneath the hot ICs. Although only two signal layers are available for routing, the achievable wiring density is extremely high due to via-pad diameters of 200 to 250 µm and lines and spaces down to 50 µm. Such a 4D construction can often be substituted for a 16-layer conventional multilayer board, and has been successfully used for complex, high-end MCM applications.

Figure 6.5 Selection of build-up constructions with plasmaetched microvias.

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Advantages of a standard 4D build-up.

Figure 6.6

6.3.3 Special considerations2

Even though plasma technology can form many vias at one time, there are several drawbacks, as shown in the following list, that limit popular acceptance of plasma techniques. ■

Plasma batch processes are suitable only for small volumes or prototypes.

■

Plasma techniques usually have a via size limit of 75 µm.

■

Isotropic etching results in undercutting (anisotropic etching is desired.)

■

Plasma techniques require removal of the copper-clad overhang from blind via holes prior to copper plating.

■

Plasma techniques rely on a special resin-coated copper foil (nonreinforced dielectric layer).

Figure 6.7 shows a via generated by the plasma etching process. Compared to the microvias created by laser drilling (Fig. 4.3) and photoimaging (Fig. 5.2), the via formed by plasma etching shows undercut. This is why the plasma etching process cannot surpass the laser drilling and the photoimaging processes.6,7

Figure 6.7 Cross section of plasma-etched microvias.

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6.4 Applications of Plasma-Etched HDI Plasma processing, well known in the semiconductor industry, can also be applied very successfully in the production of flexible and rigidflexible substrates. The possibility of ablating not only microvias, but also profiles, windows, etc., in a very cost-effective way, opens up totally new opportunities for the design and production of high-end, low-cost HDI and MCMs. The concept of combining a thin and flexible highdensity interconnect substrate with almost any kind of support carrier also allows optimization of the overall performance of a substrate in terms of thermal management, CTE matching, and/or mechanical rigidity. The technology, known as DYCOstrate®, is very reliable and approved for all demanding applications, from automotive uses and implantables to extreme space applications.1 6.4.1 Flexible HDI 6.4.1.1 Hearing aids. The 2D substrate shown in Fig. 6.8 has a total length of approximately 56 mm and is used in a high-end hearing aid device. The design is very innovative and the circuit contains various plasma-milled features: ■

Plasma-drilled microvias 60 µm in diameter

■

Plasma-milled large holes and windows

■

Plasma-milled profile

■

Plasma-milled blind microholes

The circuit has several assembly areas that are connected by integrated flexis. The assembly areas are surrounded by a small sealing rim, in which a row of small blind holes is etched (Fig. 6.9). A microsection through one of these blind holes is also shown in Fig. 6.9. It clearly shows that the depth of the hole is just about half the total dielectric thickness and the undercut is present with this holeforming process. The reason for this micromechanical feature is to provide a mechanical anchoring for the injection mold material applied after assembly. The mold is pressed into the cavities and hardened. As

Figure 6.8 Two-dimensional flexible HDI for a high-end hearing aid.

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6.9 Sealing rim with plasma-etched microfeatures.

Figure

a result of this, the foil cannot be peeled off the mold, and the reliability of the final assembly is substantially increased. Forty pieces of this particular circuit on one manufacturing panel and 12 panels simultaneously processed in the plasma drilling equipment result in 480 pieces drilled, profiled, and milled in about 15 min. 6.4.1.2

Sensors. Figure 6.10 shows a two-layer flexible DYCOstrate®

(2D) with several microfeatures manufactured by plasma milling. The circuit is assembled on one side only and is folded together like a little box in order to minimize the volume. The fold lines are partially perforated by plasma. The backside is used for shielding and for the placement of some test pads. In addition to the microvias as well as some larger via holes, plasma is use to mill the profile and the perforation in the fold lines and to ablate windows and alignment holes. Also, a cable fixture is included in the outline. All these features are etched in one single process. 6.4.2 Rigidized flexible HDI 6.4.2.1 Pacemakers. Figure 6.11 shows the traditional way of making a ceramic-based substrate for an implantable pacemaker. Usually, the substrate is manufactured in 4 × 4-in2 or 5 × 5-in2 ceramic panels,

Foldable flex HDI for a high-end sensor application incorporating various plasma-processed microfeatures.

Figure 6.10

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Traditional ceramic-based manufacturing approach for pacemaker circuits.

Figure 6.11

mostly in HTCC or LTCC technology with six to eight conductor layers. After the sintering process is finished, the substrates are cut out by laser and assembled on the first side, including wire bonding or flip chip soldering. Afterward, the substrate is assembled on the backside and additional flexis or cables are connected to the ceramic by soldering or laser welding. Finally, the circuit is functionally tested by in-circuit testing and assembled into the system. This process is very costly and a lot of human interference causes handling defects and low yield. In order to address performance issues as well as cost issues, a new concept for the manufacturing of this kind of circuit has been recommended and implemented. In a flexible approach, the process uses a single-sided assembly where the flexible board is folded up like a butterfly and all the flexible interconnects to the battery and the sensor are integrated directly into the circuit. The substrate is locally rigidized by a suitable carrier material and kept within the large manufacturing panel (12 × 18 in2) by some tabs (Fig. 6.12). Before assembly, the large panel is separated into smaller assembly panels. The attachment of flexible cables is eliminated and the functional test is done using fanned-out test pads arranged in a large pitch pad array, eliminating costly test fixtures and also saving real estate area. After functional test, the circuit is depanelized using a simple cutting tool or by laser cutting and subsequently folded together. When one single joining technique, such as soldering, is used, the assembly can be done directly on the large manufacturing panel using conventional pick-and-place equipment. It is obvious that this approach not only reduces the production cost, but also improves the technical performance of the entire system by minimizing the overall size and weight of the implantable device, resulting in higher acceptance and growing market shares.

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New manufacturing concept based on plasmaprocessed flexible organic substrates.

Figure 6.12

6.4.2.2 High-end mobile communications. The rigid-flexible MCM substrate shown in Fig. 6.13 is used in a high-end military mobile communication system. It consists of four assembly areas connected by integrated flex circuits. The assembly areas are supported by a copper heat sink. The assembly is both C&W and SMT. The large pads around the wire-bonded ICs serve as in-circuit test pads only and do not contain any via holes. The build-up is a 4DC construction, with few signal lines embedded into the GND plane. 6.4.2.3 Missile DSPs. The example in Fig. 6.14 relates to a missile application, where a fast DSP has to be packed into an almost hermetically sealed package. The MCM substrate is a 4D build-up bonded to a CMC carrier. The CMC is a low-CTE material and constrains the substrates very effectively. In addition, it is a good heat conductor and allows high heat dissipation.

Figure 6.13 Rigid-flexible MCM for a high-end mobile communication device.

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Fast DSP MCM for a missile application.

Figure 6.14

The build-up is a standard 4D construction with two signal layers on layers 2 and 3. The backside (layer 4) is a full GND layer without signals. The front side contains all pads and VCC. The substrate has almost 2000 internal I/Os, most of which are for wire-bond assembly. In order to seal the circuit quasi-hermetically, a metal lid is soldered onto the surface after assembly and testing. The CMC carrier and the metal lid provide for a very effective diffusion barrier, but humidity may still creep into the cavity from the periphery. Therefore, special diffusion barriers are designed into the inner layers and the almost full copper coverage on the top layers also helps to minimize gas diffusion. Hermeticity tests have shown a very good performance. This type of low-cost package eliminates the need for high-priced Kovar metal can packages with glass feed-through contacts, and also allows a simple connection of the external I/Os to a flexible bus substrate, connecting all the various modules within the electronic system. 6.4.3 Rigid-flexible HDI

The HDI board shown in Fig. 6.15 is the central sensor board for the XMM satellite, the new generation of the x-ray telescope which was launched in 2000. The rigid-flexible HDI is 640 mm long and has a very complex build-up. On both sides of a molybdenum core, which simultaneously provides for rigidity, heat conduction, and CTE matching, two 8D packages are bonded. The actual sensor chip has a dimension of 4 × 4 in2 and is die- and wire-bonded to the central area of the HDI. Since the signals generated by the sensor—which operates at −150°C—are very sensitive, most of the signal lines on the inner layers are designed in the form of real twisted pairs. In order to prevent heat

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Figure 6.15 Complex rigid-flexible HDI substrate for the XMM satellite.

from flowing from the flex tails toward the central sensor area, the copper thickness in the flexibles must be less than 6 µm. The HDI board has been fully approved for the ABRIXAS and XMM mission and is considered one of the most complex HDIs ever produced. 6.5 References 1. Schmidt, W., “Plasma Processed Rigid-Flexible MCMs,” Board Authority, 2(1): 70–74, April 2000. 2. Lau, J. H., and C. Chang, “An Overview of Microvia Technology,” Circuit World, 26(2): 22–32, January 2000. 3. Schmidt, W., “DYCOstrate Technology,” Circuitress, June 1996. 4. Schmidt, W., “A Revolutionary Answer to Today’s and Future Interconnect Challenges,” Proceedings of the Third European Joint Conference (EIPC), Brussels, Belgium, June 17–19, 1992. 5. Schmidt, W., “DYCOstrate Technology: From PCBs to MCMs,” Proceedings of the German EIPC Seminar, Freiburg, Germany, September 23, 1994. 6. Reboredo, L., “Microvias: A Challenge for Wet Processes,” Proceedings of the IPC Expo, S12–1, Long Beach, CA, March 1999. 7. Schmidt, W., “High Performance Microvia PWB and MCM Applications,” Proceedings of the IPC Expo, S17–5, Long Beach, CA, March 1999.

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Chapter

7 Conductive Paste/Ink-Filled Microvias

7.1 Introduction Due to the fast growth in demands for mobile computing and telecommunication, the technologies of microelectronics packaging require high density, fine pitch, high performance, high reliability, and low cost. In particular, it is becoming more and more difficult for the conventional PCBs with mechanically drilled vias and PTHs to meet the packaging density requirements and to justify their manufacturing cost. To overcome these challenges, new PCB manufacturing schemes for high-density and high-performance multilayer PCBs have been developed recently. These new HDI technologies are categorized as SBU or build-up multilayer (BUM) processes for making laminatebased substrates or PCBs containing microvias formed by laser drilling, photoimaging, or plasma etching. Conductive paste or ink materials may be used to fill the microvias and through-holes to make reliable vertical or z-interconnects.1 The surface metallization may be accomplished either by chemical deposition or by laminating copper foil onto the dielectric surface. A few examples of this category of high-density PCBs include Matsushita’s any-layer inner via hole (ALIVH),2 DuPont’s CB100,1 and Ormet’s OrmeLink.3 The SBU technology with conductive paste/ink-filled microvias can achieve a connection pad density of up to 100 pads/cm2, while the conventional PTHs can reach only 20 pads/cm2. The general fabrication processes for conductive paste/ink-filled BUMs consist of: (1) formation of microvias in individual prepreg layers by laser drilling or photo-

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imaging, (2) filling via holes with conductive paste/ink materials, (3) lamination of copper foil onto the prepreg with filled microvias, (4) circuitization of copper foil by photolithography, (5) testing of individual layers, (6) lamination of tested individual layers, and (7) circuitization of the outer layers by photolithography. The paste/ink materials used for via filling must have corrosion resistance, electrical conductance, easy adaptability to the existing manufacturing process (e.g., screen-printable), low shrinkage after processing, high strength, good adhesion to PCB materials, and yet low cost. Most such materials comprise metallic particles such as copper, an epoxy resin, a hardener, and, if necessary, a dispersant. The paste/ink having low viscosity and low volatility under high shear should be used to fill microvias and through-holes. 7.2 Conductive Paste and Ink 7.2.1 Conductive paste for via filling4

A conductive paste material usually consists of a conducting filler powder coated with a low-melting-point metal or alloy, a mixture of several thermoset resins, and other minor organic additives. By varying the filler content and resin chemistry, several formulations have been produced to fill via holes with a high aspect ratio. As a common practice, via fill experiments should be performed to demonstrate void-free microstructure with good electrical continuity. Also, various bulk properties such as thermal, electrical, and mechanical properties should be characterized in order to understand the material behavior during via filling as well as field service. 7.2.1.1 Conducting adhesive materials. An electrically conducting adhesive material is made of metallic filler particles loaded in the matrix of a polymer material. The polymer matrix can be either thermoplastic, thermoset, or mixtures of these polymers. Silver-particle-filled epoxy is the most common example of the electrically conducting adhesive materials in use. The silver particles, usually in the shape of flakes, provide electrical conduction via percolation, while the epoxy matrix provides an adhesive bond between the components and a substrate. The silver-filled epoxy material has been long used in electronic applications as a diebonding material,5 where its good thermal conduction rather than electrical conduction property is utilized. Recently, this material has been further developed for applications requiring high electroconduction and fine pitch connection.6–13 The silver-filled epoxy material still has several limitations for electronic applications. These are low electrical conductivity, increase in contact resistance during thermal exposure, low joint

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strength, silver migration, difficulty in rework, and others. Since the silver-filled epoxy material is electrically conductive in all directions, it is classified as an isotropic material. In order to overcome the limitations of the silver-filled epoxy materials, several new formulations have been developed recently for various applications. To meet the reworkability requirements of high-performance applications, such as in an MCM, a reworkable thermoplastic resin has been incorporated with the proper solvent and silver particles.10 Solvent removal from the thermoplastic resin has been carefully controlled during the reflow cycle. Another reworkable thermoplastic conductive paste has also been reported for fine-pitch flip chip applications.7 In this case, by loading fine silver particles in excess of 40 percent by volume, high electrical conductivity superior to the Pb-Sn eutectic solder has been achieved. A new class of conductive adhesive materials has been developed by replacing silver particles with other conducting particles, such as solder particles,14 a mixture of solder and copper,8, 15 tin-coated copper,11, 16 silver-coated copper,17 and others. A solder-polymer composite paste material has been developed by mixing solder powder particles, thermoplastic polymer resin in a volatile solvent, and a fluxing agent.14 Upon reflow, an oxidefree, partially coalesced solder connection is obtained, which is polymer strengthened and reworkable at a low reflow temperature or in the presence of an organic solvent. A hybrid of solder and conductive adhesive joining technologies has been developed to exploit the advantages of both.8 This new conductive adhesive is a mixture of a solder powder, a metal powder of high melting point such as copper, a fluxing agent, a polymer resin, and other additives. Here, the electrical connection is established through transient liquid phase sintering (TLPS) among metal and solder powder as well as to the conducting pads. Promising results have been reported with SMT joints made from the TLPS conductive paste in terms of electrical conductivity, impact strength, and reliability, which are substantially better than those of the conventional conductive adhesives.15 Another improvement has been reported with high-conductivity Pb-free conducting materials. Several formulations have been developed of materials made of a conducting filler powder coated with a low-melting-point metal, a thermoplastic polymer, and other minor organic additives.16, 18 Similar to the TLPS conductive paste, these high-conductivity Pb-free conducting materials also provide metallurgical bonding between adjacent filler particles, and between the filler particles and the contact pads to be joined, in addition to the adhesive bonding from the polymer matrix. Their salient properties have been reported for two different applications; one for high-temperature applications with ceramic substrates, and another for low-temperature applications with organic substrates.19

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7.2.1.2 Pb-free conductive materials for via fill applications. A new Pb-free conductive adhesive has been developed for via fill applications with the intent of utilizing the enhanced properties discussed previously. The BiSn-coated Cu powder developed previously18 has been chosen as the conducting filler particles. The BiSn-coated Cu conducting particles are fusible during lamination under heat and pressure. This leads to metallurgical bonds among the conducting particles as well as to the conducting pads, which enhance mechanical and electrical properties of the filled via holes. Since the BiSn coating on Cu powder also provides a protective layer against oxidation on the Cu surface, the longterm reliability of the filled via holes is expected to be superior to the via structure filled with the conventional materials, such as silver-filled epoxy or copper-filled adhesives. Another advantage of the BiSn-coated Cu powder comes from the absence of silver particles in the filled via holes. Silver metal is notorious for corrosion under the condition of moisture and a bias voltage, which often leads to a serious reliability issue in high-performance electronic packages. The resin formulation used in the present conductive adhesive material is unique in low shrinkage and controlled viscosity. The resin system is formulated by mixing several thermoset resins, such as cycloaliphatic-type epoxy, phenoxy polymer, monofunctional limonene oxide, and others. Flux resin is also incorporated into the resin mixture. A controlled viscosity of the resin mixture required for screen printing into a high-aspect-ratio PTH is achieved by adjusting the components of the monofunctional limonene oxide. Several formulations are made by varying the resin mixture as well as the conducting filler content, as listed in Table 7.1. The electrical and mechanical properties of these formulations are measured with the model joints as listed in Table 7.1. The geometry of a model joint and testing methods are given in the literature.19 Table 7.1 lists several examples of the new conductive paste formulations designated, such as BiSn48, BiSn49, BiSn53, and BiSn54. For comparison, it also includes one commercial paste formulation, AgCu01, which contains a mixture of silver and copper particles as a conducting filler in the matrix of an epoxy resin.20 As noted in Table 7.1, the electrical and mechanical properties measured with the new conductive paste formulations are superior to those obtained from the commercial substrates having different characteristics, such as thickness, PTH diameter, aspect ratio, and others. For a thick PCB with a high aspect ratio, a formulation having a high-flow resin such as BiSn49 or BiSn54 is required to fill the vias. For a thin PCB with a small aspect ratio, it is appropriate to use the formulation with a medium-flow characteristics, such as BiSn48. To demonstrate the hole-filling behavior of the new conductive paste formulations, via fill experiments have been performed with two differ-

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TABLE 7.1

Electrical and Mechanical Properties of Conductive Adhesive Materials for Via Fill Applications Paste ID

Electrical (Ω) (mean/SD)

Mechanical (lb) (mean/SD)

Remarks

Filler(%)

Resin

Reflow

AgCu01

Ag & Cu (>93)

Epoxy

150°C, 25 psi, 30 min

0.00040 (0.00002)

4.3(0.9)

Commercial

BiSn48

BiSn/Cu (68)

Epoxy Phenoxy Flux

188°C, 50 psi, 30 min

0.00041 (0.00006)

6.7(0.5)

Mediumflow resin

BiSn49

BiSn/Cu (76)

Epoxy Lim-oxide Phenoxy Flux

188°C, 25 psi, 30 min

0.00027 (0.00004)

5.4(0.9)

High-flow resin

BiSn53

BiSn/Cu (77)

Epoxy Lim-oxide Phenoxy Flux

188°C, 25 psi, 30 min

0.00023 (0.00003)

5.1(0.3)

High-flow resin

BiSn54

BiSn/Cu (81)

Lim-oxide Epoxy Phenoxy Flux

188°C, 25 psi, 30 min

0.00018 (0.00002)

3.4(0.3)

Very-highflow resin

ent PCBs—one 0.024 in. thick with a PTH diameter of 0.008 in. (aspect ratio = 3), and another 0.105 in. thick with a diameter of 0.010 in. (aspect ratio = 10). For the thin PCB, the new conductive paste is applied directly by blading and the excess paste is wiped off. For the thick PCB, a coating (0.004 in. thick) of the paste is applied to a polyester carrier film by blading. The carrier film is then laminated into the holes of the PCB by applying a pressure of 500 psi and the use of a mask.21, 22 The via-filled PCB is later cured at 150°C for 30 min. To demonstrate the hole-filling characteristics, the cross sections of the via-filled PCB have been prepared metallographically. Figure 7.1 shows a typical cross-sectional view of the thin PCB filled with the use of blading. A void-free via structure is observed. In the enlarged view in Fig. 7.2, a uniform distribution of the conducting filler particles is noted in the filled via structure. Figure 7.3 shows a typical cross-sectional view of the thick PCB with a high aspect ratio, where the via fill was accomplished by a high-pressure lamination of a carrier layer. Again, a void-free via structure is noted. Figure 7.4 shows an enlarged view of Fig. 7.3, in which a uniform and compact distribution of the conducting filler particles is observed. A Pb-free conductive adhesive material has been developed to fill via holes in the new PCB structure manufactured by the build-up multilayer technology. The new conductive paste material consists of a con-

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Cross-sectional micrograph of a through-hole filled with a conductive adhesive (BiSn49, listed in Table 7.1).

Figure 7.1

ducting filler powder coated with a low-melting-point metal or alloy, a mixture of several thermoset resins, and other minor organic additives. Via fill experiments have been performed to demonstrate void-free microstructures with good electrical continuity. Bulk properties of the new conductive adhesive materials have also been measured to understand the materials’ behavior during via filling as well as reliability testing.

Enlarged view of the cross section shown in Fig. 7.1.

Figure 7.2

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Cross-sectional micrograph of a through-hole filled with a conductive adhesive (BiSn54, listed in Table 7.1).

Figure 7.3

7.2.2 Conductive ink for through-hole plugging23

STH technology describes a method of creating an electrical interconnect between the top and bottom sides of a printed circuit board. STH production has gained and continues to rapidly gain acceptance worldwide due to its low-cost, reliable, and environmentally friendly process. Even though the technology necessary to produce STH boards is mature, the performance of current through-hole ink relies on different PCBs. The stability of electrical conductivity on exposure to solder

Enlarged view of the cross section shown in Fig. 7.3.

Figure 7.4

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baths or to thermal cycling is a predominant issue. This problem is associated with different metal fillers, resin systems, and PCB types. For example, the electrical resistance of the ink on FR-2 substrate gradually increases after each solder bath dip. Fundamental studies have been conducted on the root cause of the hole resistance drifts after solder bath. Thermal mechanical analysis (TMA) and dynamic mechanical analysis (DMA) have been used to characterize the CTE and curing performance of the ink and PCB substrates. The failure mechanism has been proposed and confirmed by designed experiments. Experimental results demonstrated that hole resistance drift on FR-2 substrate is caused by several factors. First, the higher thermal expansion of the substrate itself stretches the coating layer. Second, the continued curing makes the resin matrix fixed at a higher temperature. The final factor is the CTE mismatch between the conductive ink and the PCB substrate. STH technology describes a method of creating an electrical interconnect between the top and bottom sides of a printed circuit board. This method involves screen printing a conductive paste into drilled holes and then drying and curing the paste. The paste can be filled with silver, copper, or any combination of conductive metals. STH production continues to rapidly gain acceptance worldwide for several reasons. The selling price of an STH-produced paper phenolic board is 30 percent to 40 percent less than that of an electroless-copper-plated epoxyglass board. The STH process is environmentally more friendly than plated through-hole processes. The technology necessary to produce through-hole boards is mature and not excessively complicated. The cost of the equipment is very low, and equipment is most often already available from a printed circuit board producer. Besides, the reliability of STH boards meets or exceeds the requirements for many applications. Even though the technology necessary to produce STH boards is mature, the STH ink needs to be improved for the final product reliability. The vast majority of the PCB through-hole inks in the marketplace today are based on modified phenolics. The stability of electrical conductivity on exposure to solder bath or thermal cycling is a predominant issue for the current products on FR-2 board. Reduction of the STH ink cost is another major issue for the current products. These problems are associated with different metal fillers, resin systems, and printed circuit boards. Fundamental studies have been conducted on the root cause of the two issues. The understanding of the failure mechanism leads to new product development.24 7.2.2.1 Process for through-hole connection. Through-hole connections can be applied to single- or double-sided PCB materials such as FR-2, FR-4, and CEM-1. The general process for through-hole connections is as

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follows. After etching, the via holes can be drilled. The most frequently used hole dimensions are 0.5 to 1.0 mm in diameter. The PCB substrate is usually 1.0 to 1.6 mm thick, with copper pads that are generally 0.8 to 1.2 mm larger than the hole diameter. The printed silver dots are generally 0.4 to 0.7 mm larger in diameter than the hole. Drilled holes are recommended, since punching does not provide a smooth enough surface to allow consistent deposition of ink. Furthermore, the reliability of punched hole boards is inferior with respect to resistance stability and silver migration. A standard copper cleaning process has to be done before the through-hole print to remove any copper oxidation and contamination. After cleaning, the board must be properly dried or the moisture trapped in the holes will cause voiding. The through-hole conductive ink is screen-printed into the holes. Three generations of printing techniques are now common, and several variations of these have been developed by many companies. The oldest and most traditional is the folded-over squeegee technique, where high squeegee pressures fold the squeegee onto the screen. The second, newer, and increasingly more popular technique is the beveled squeegee technique. The third and newest technique uses a 20-mm-wide squeegee and a very small printing angle. All methods are used with a high degree of success by many companies. Drying and curing refer to different processes. Drying refers to the removal of solvent prior to the actual curing cycle, during which resins cross-link and form the final network. A final coating of solder mask is applied to cover the printed holes in order to provide protection from oxidation and physical and/or chemical damage. 7.2.2.2 Electrical resistance test vehicle. The materials used for the electrical resistance tests are commercially available Electrodag PR408 and PR-011 silver polymer thick film ink for through-hole printing. The conductive paste is homogenized properly and may be diluted to the required process viscosity. Several tests should be conducted to identify the mechanisms responsible for the unstable resistance of the ink after solder bath. Sheet resistance test vehicle preparation (Fig. 7.5) involves printing the material on a glass substrate and then drying and curing it under appropriate conditions. The sheet resistance in Ω/square at 25 µm of a particular conductive track can be calculated from Eq. (7.1) by measuring the actual resistance R of the conductive track, the number of squares N involved, and actual coating thickness t, as follows:

Sheet resistance = (R × t)/(N × 25) (Ω/square/25µm)

(7.1)

Note that the number of squares N equals length divided by width of the coating layer.

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Figure 7.5

Test vehicle for sheet

resistance.

The hole resistance is measured over a row of several through-hole connections (Fig. 7.6) using a digital multimeter. For measuring the resistance of one hole, four-point measuring equipment is needed to overcome the contact resistance between the leads and copper circuit. All samples should be dried for 30 min and then cured at 175°C for 30 min to mimic the manufacturing cure timing. The initial resistance Ro is measured once the samples equilibrate to room temperature. Then the samples are dipped into a solder bath at 250°C for 10 s. The resistance Rt should be measured after the samples cool down to room temperature. 7.2.2.3 Coefficient of thermal expansion. CTE measurement of a cured formulation and PCB boards is performed on a thermomechanical analyzer. The CTE of PCB substrate should be measured along three different orientations. The x- and y-directions are along the surface of the board, while z is perpendicular to the board surface and along the through-hole direction. In order to achieve the minimum thickness requirement of TMA without voids in the sample, multilayer coatings may be applied for through-hole ink. Each individual drying is conducted at 70°C after a new coating layer is applied, and final curing at 150°C is performed after the total coating layers reach 2 mm thick. The CTE should be measured from −50 to 200°C at a heating rate of 5°C/min. 7.2.2.4 Dynamic moduli and curing characterization. Curing is studied by monitoring changes in dynamic moduli as a function of temperature

Figure 7.6

Test vehicle for hole resistance.

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and time using a dynamic mechanical analyzer. The preparation of a specimen used for the DMA test should be the same as that for the TMA test except for the size. The measurement is performed in a singlecantilever mode under 10-Hz sinusoidal strain loading. Heat should be applied from room temperature to 200°C at a heating rate of 5°C/min. 7.2.2.5 Reliability testing. Figure 7.7 shows the results of electrical resistance change after solder bath at 250°C for PR408 on FR-2 and FR-4 boards. The reliability performance is quite different for FR-4 boards compared with FR-2 boards when the samples are cured at 150°C for 30 min. On FR-4 boards, the hole resistance drops a little after the first solder dip, then remains stable when the specimen experiences further solder dips. On FR-2 boards, instead of maintaining stable resistance after the first solder dip, the hole resistance gradually increases. This unstable resistance makes the through-hole conductive ink finally fail the solder bath reliability test after several dips. In order to understand the failure mechanism of current formulations of FR-2 boards, the physical properties of the through-hole ink and PCB substrates are characterized. CTE values as well as softpoints of through-hole ink and PCB substrates are listed in Table 7.2. It has been observed that CTE is similar for FR-2 and FR-4 along the x- and y-directions. However, the CTE value is significantly larger for FR-2 than for FR-4 along the through-hole z-direction. Comparing the CTE value in the z-direction between the through-hole ink and substrates, it was found that the CTE of through-hole ink is very close to that of FR-4, but much smaller than that of FR-2. The softpoint of FR2 is lower than that of FR-4, but both are much higher than the softpoint of conductive ink when the samples are cured at 150°C for 30 min. However, the softpoint of the conductive ink increases after it experiences heating up to 200°C. This increase in the softpoint of con-

Figure 7.7

The effect of solder bath on hole resistance.

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ductive ink indicates that further curing occurs at elevated temperatures. The curing at elevated temperatures should be further investigated by DMA to characterize the dynamic storage modulus changes with temperature for PR-408 and PR-011. The initial run indicates that the glass transition temperature of PR-408 is about 50°C after the sample is dried at 70°C for 30 min followed by curing at 150°C for 30 min. Notably, the storage modulus increases when the sample is held at 200°C for 10 min. Then the same specimen is tested for the second time. At this time, both storage modulus and glass transition temperature have increased. The same phenomenon is observed on PR-011 formulations based on the same resin system. The DMA results confirm that further curing occurs at elevated temperatures. Based on the observed failure phenomenon and characterized physical properties, a failure mechanism has been proposed. Figure 7.8 schematically illustrates the failure mechanism due to the CTE mismatch and continued curing. Corresponding dimension changes of conductive ink and PCB substrates at different stages are shown in Fig. 7.9. When PCB substrate coated with through-hole ink is dipped into solder bath, the PCB substrate stretches due to thermal expansion. Since the glass transition temperature of the ink is below that of the PCB substrate, the coating layer will expand at the same level. The conductive ink on FR-4 is stretched much more than that on FR-2 substrate since the CTE of FR-2 is much higher than that of FR-4. Assuming that the relative dimension change at 0°C is zero, then the thermal expansion of the FR-2 board is about 60,000 ppm while that of FR-4 is about 16,000 ppm based on CTE measured by TMA. When the temperature cools down to the glass transition temperature of the ink, the resin matrix is fixed. If no further curing occurs, the through-hole conductive ink coated on the hole should shrink back to its original state with the PCB substrate when it reaches room temperature. Therefore, TABLE 7.2

CTE (ppm/°C)

CTE of Through-Hole Inks and PCB Substrates PR408

PR011

FR-2

FR-4

1st run −50 to 200°C x-

48

58

19

19

y-

48

58

20

17

z-

48

58

115/279

44/78

0°C

64°C

100°C

Softpoint

10°C

2nd run −50 to 200°C x-, y-, zSoftpoint

50

54

No change

No change

175°C

175°C

No change

No change

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the hole resistance, determined by the volume fraction of the conductive fillers, should keep the same value before and after solder bath. However, due to the further curing of the resin system, the glass transition temperature of the ink increases; thus, the resin matrix is fixed at a higher temperature as shown in Fig. 7.9. When the temperature further cools down to room temperature, the ink will shrink based on its own CTE below Tg instead of shrinking along with the board. The resin matrix fixed at higher Tg causes the final resin matrix after the solder bath to be larger than that before the solder bath. In other words, the volume fraction of the conductive ink becomes smaller. As a consequence, resistance increases. Since the CTE of FR-4 is much smaller than that of FR-2 and the CTE mismatch between the ink and FR-4 is also less than that for FR-2, the relative dimension change before and after solder bath dip on FR-4 substrate is much smaller than on FR-2 substrate. For example, the relative dimension change on FR-2 is about 30,000 ppm, while that on FR-4 is about 1,600 ppm assuming Tg is about 50°C and 175°C before and after the solder bath, respectively. In order to confirm the proposed failure mechanism, the sample is cured at 250°C for 30 min to guarantee that no further curing occurs during solder bath at 250°C. Then the solder bath reliability test is conducted. Since there is no further curing happening during solder dip, the resistance should stay stable before and after solder bath based on the assumption. The experimental results in Fig. 7.10 show that resistivity stays stable after several solder dips for both FR-4 board and FR2 board. This result supports the proposed failure mechanism. The electrical resistance of the through-hole conductive ink on FR-2 substrate gradually increases after each solder bath dip. But the hole resistance is stable on the FR-4 substrate. Experimental results demonstrate that a hole resistance drift on FR-2 substrate is caused by several factors. First, the higher thermal expansion of the substrate itself stretches the coating layer. Second, the continued curing of the ink during the solder bath test causes the resin matrix to become fixed at higher temperatures. The final factor is the CTE mismatch between the conductive ink and PCB substrate. FR-2 substrate has a much larger CTE than FR-4. The CTE mismatch between conductive ink and FR-2

Figure 7.8 Schematic diagram of dimension change under solder bath dip.

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Relative dimension change of conductive inks and PCB substrates.

Figure 7.9

is much bigger than that between ink and FR-4. Current PR-408 and PR-011 formulations will continue to cure at elevated temperatures. As a consequence, the volume fraction of conductive filler becomes smaller after solder dip, which causes the resistance increase. 7.2.3 Example of application1

CB100 is a screen-printable paste made of silver, copper, and epoxy. Figure 7.11a shows a stacked via over filled PTH, and Fig. 7.11b shows an integrated IC-PCB assembly with the CB100 conductive via plug. CB100 is usually stencil-printed in the plated or unplated throughholes. After drying and curing, the plugged through-holes are planarized and plated to make them solderable. The design rules for CB100 are: aspect ratio = 1:1 to 6:1 with vacuum assist; via size = 6 to 25 mil (152 to 635 µm); and core thickness = 6 to 85 mil (152 to 2159 µm). The CTE is less than 35 ppm/°C. The CB100 assembly process is as follows:

Hole resistance change after solder bath with sample cured at 250°C for 30 min.

Figure 7.10

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(a)

(b)

(a) Stacked via over filled PTH with DuPont’s CB100. (b) Fully integrated IC-PCB with redistribution layer, controlled impedance, thermal dissipater, buried capacitor/resistor, and EMI shielding.

Figure 7.11

■

Drill through-holes on the double-sided copper clad substrate.

■

Screen/stencil-print CB100 into the through-holes.

■

Dry and cure the via-plugged CB100.

■

Scrub and planarize the surfaces.

■

Plate the filled board with about 0.3 to 0.5 mil to enhance electrical conductivity and solderability. (With a multilayer core, the throughhole is first flash-copper-plated with a minimum of 0.1 mil copper to ensure interplane connection.)

■

External flash-electroplate copper.

■

Form wiring patterns on both sides of laminate by printing and etching.

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There are some qualification data for the CB100 ViaPlug.20 It can be seen that the material can pass 1000 temperature cycles (−65 to 125°C) and pass 5 solder dips at 286°C.

7.3 Any-Layer Inner Via Hole (ALIVH)2 Matsushita has developed a unique stacked-type substrate technology called ALIVH. Laser ablation (currently CO2 laser) and conductive paste (with Cu particles/epoxy carrier) are used for the formation of interconnects. It is reported that Matsushita’s share in the Japanese cellular phone market has risen to 60 percent with the introduction of ALIVH substrates (Fig. 7.12). The ALIVH process is very popular in Japan. However, in order to gain market share, ALIVH must migrate to other fabrication facilities outside Japan. The ALIVH technology has the capability to carry HDI processes well into the next several generations of build-up multilayer requirements. As with all HDI processes, the cost of additional processes and special materials must be traded off against the benefit of greater circuit density and other metrics such as time to market and reliability. There could also be a “pull” effect from OEMs whose future designs require the capabilities of a process not constrained by conventional plating processes, where aspect ratio and plating distribution do not impede circuit density. In the future, it may also be possible to eliminate the intermediate pads and create structures that have even greater routing density.

7.3.1 Classification of ALIVH

The three versions of the ALIVH process, currently available in Japan, are designated ALIVH, ALIVH-B, and ALIVH-FB. Each has the capability of providing high-density interconnect capability for different packaging complexities and market segments required by

(a)

(b)

(a) ALIVH substrate for mobile phones. (b) Cross-sectional view of a typical ALIVH substrate.

Figure 7.12

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OEMs.25 All three ALIVH processes use laser drilling to create microvias in individual sheets of prepreg. The holes are subsequently screen-filled with a conductive paste, which creates a conductive path from one side of the prepreg to the other. Internal layers that are equivalent to conventional inner-layer cores are created in an extra lamination step by laminating foil to the prepreg and then completing a standard print-and-etch process sequence to create the circuit features of each layer pair. The fabrication process concludes by adding additional layers of dielectric material (also with conductive paste in the holes) and the outer-layer foil before laminating the package together and completing a print-and-etch process that creates the outer-layer circuit features and a thick multilayer structure. The standard ALIVH structure is best suited for the smaller/lighter product segments in consumer electronics (over 18 million cell phones have been manufactured with this process). The ALIVH-B and -FB processes are focused on the motherboard, chip-scale packaging, and direct chip attach segments of the industry. The -B and -FB processes are competing for market share where more complex HDI board designs are required and where product reliability is a key metric. ALIVH structures do not use conventional PCB substrates for rigidity like some of the high-volume build-up multilayer structures using photoimageable dielectrics or resin-coated copper. The common thread in the ALIVH processes is the use of an Aramid/epoxy prepreg and a conductive paste to provide electrical connection. Blind and buried vias are standard ALIVH features, but the competitive advantage is that these vias can be connected to any other layer in the stack-up. A stacked, solid via-on-via or via-on-pad replaces conventional drilled, lasered, or imaged microvias and electroplating. There are no aspect ratio constraints. There is also no hole plugging required after solder mask in the ALIVH processes. 7.3.2 Characteristics and advantages

The premier benefit of ALIVH is described in its name. Designers can connect from any layer to any other layer (Fig. 7.13)—a capability that is not available in other build-up structures. Take a six-layer design, for example. Connections can be made from one layer to any other layer (say, from layer 2 to layer 5) with no aspect ratio constraints (as for electroplating). This capability will change the way designers create a structure. Design flexibility is increased and overall layer count is reduced because of the routing opportunities created when individual layers are manufactured one at a time. In addition, by laser drilling the holes and screening the conductive paste into each layer of prepreg

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Figure 7.13

ALIVH—any layer to any other layer.

prior to the final lamination step, each layer can be electrically tested and repaired or replaced, if necessary. The ALIVH inner layers are “known-good” before the outer layer is created. This is a distinct advantage in yield compared to typical build-up processes where the substrate is at risk each time it makes one of the required multiple passes through the processes required to create the build-up structure. ALIVH also has a unique attribute from an environmental standpoint; since it is essentially a “dry/mechanical” process requiring only inner-layer FAB to print and etch the circuitry (no electroless copper, electroplating, or final strip and etch), much of the wastewater treatment and support cost associated with the high-maintenance outerlayer processes is eliminated. Because ALIVH is less complex compared to some other alternatives, it should also be less expensive. 7.3.3 Design and tooling26

In the ALIVH processes, the ability of the design systems to capture the unique hole formation pattern on each prepreg layer and match it to the corresponding foil layer could be a challenge. There are at least two systems currently available that can support ALIVH designs. In addition, fully utilizing the via-on-via and via-on-pad capabilities will require extra effort on the part of the designers to learn how to create new products with another degree of freedom. Greater design flexibility is obtained because blind and buried via connections are not constrained by the mechanical operations or electroplating aspect ratios, and outer-layer traces are created by a print-and-etch process, eliminating the effects of plating distribution.

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Table 7.3 shows some of the minimum design features available with ALIVH. It should be noted that circuit density is not a significant advantage in the ALIVH process because these feature sizes can be obtained by other HDI processes. The tooling processes prior to manufacturing will need modification and additional documentation to address the multiple passes through inner-layer FAB and lamination. 7.3.4 Features of materials

The ALIVH prepreg uses a nonwoven Aramid-reinforced cloth impregnated with a high-Tg (168 to 180°C) epoxy resin. The resin content can be varied somewhat to meet other design trade-offs. This family of prepregs has a lower in-plane CTE, ranging from 6 to 10 ppm/°C versus ∼15 ppm/°C for standard FR-4. Also, when compared to a conventional FR-4 multilayer with woven glass, a similar structure using ALIVH can be 30 percent to 50 percent lighter. In ALIVH processes conventional copper electroplating of the hole walls is replaced with uniform via plugging using a conductive paste that has copper particles embedded in an epoxy carrier. Copper particles vary in size and are as small as 4.45 µm in the high-end ALIVHFB process. The conductivity variation using the conductive paste is ⫾20 percent, including the microvias, and dielectric resistance variation is greater than 1 × 107 Ω after testing. The dielectric constant Dk ranges from 4.1 at 1 MHz to 3.5 at 1 GHz. TABLE 7.3

Design Minimums of Standard ALIVH, ALIVH-B, ALIVH-FB Features

Lines

Spaces

Pads

100 µm (4 mil) 100 µm (4 mil)

400 µm (16 mil) 400 µm (16 mil)

50 µm (2 mil) 50 µm (2 mil)

250 µm (10 mil) 250 µm (10 mil)

25 µm (1 mil) 25 µm (1 mil)

150 µm (6 mil) 150 µm (6 mil)

Standard ALIVH Outer layer Inner layer Via diameter = 200 µm (8 mil) Dielectric thickness: 50–125 µm (2–5 mil)

100 µm (4 mil) 100 µm (4 mil)

Outer layer Inner layer Via diameter = 125 µm (5 mil) Dielectric thickness: 50–125 µm (2–5 mil)

50 µm (2 mil) 50 µm (2 mil)

ALIVH-B

ALIVH-FB Outer layer Inner layer Via diameter = 50 µm (2 mil) Dielectric thickness: 12.5 µm (0.5 mil)

25 µm (1 mil) 25 µm (1 mil)

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Since ALIVH processes are different from conventional processes, extra development time has been spent to ensure that critical risk factors for OEMs have been addressed. In these ALIVH processes to enhance the bond strength between the conductive paste and the copper foil, a new surface treatment process for the foil was developed. In addition, modifications to the copper particle geometry, paste viscosity, and epoxy binder system were also made to ensure reliability and assembly survivability. One of the known disadvantages of Aramid-epoxy resin systems is moisture absorption. A special formulation of prepreg to reduce the effects of moisture has been developed in Japan. North American suppliers may also offer similar low-moisture-absorption materials. Also, most of the applications for ALIVH will be thin, low-layer-count, highdensity structures because the z-axis expansion of Aramid-epoxy is worse than that of FR-4. 7.3.5 Manufacturing processes 7.3.5.1 Basic procedures. The fabrication process flowcharts for ALIVH substrates are shown in Fig. 7.14. The basic procedures are illustrated as follows. ■

The nonwoven Aramid-epoxy prepreg is used as a substrate material. The B-staged Aramid-epoxy sheets are drilled out to form via holes using a CO2 laser for the electrical connection between conductive layers.

■

The via holes are filled with the via conductor paste. The via conductor paste consists of copper particles and a thermosetting resin. Two copper foils and the via-filled Aramid-epoxy prepreg are stacked to be laminated, sandwiching the aramid-epoxy prepreg between two copper foils with no gap. The lamination and curing of the aramidepoxy prepreg are performed under a pressure and a temperature. Wiring patterns are formed by etching the copper foil layers.

■

The other via-filled Aramid-epoxy prepregs are stacked on both sides of the wiring-patterned Aramid-epoxy sheet. Furthermore, two copper foils are stacked on both sides of the stacking laminates. Lamination is performed under a pressure and a temperature. Finally, the wiring patterns of both sides of laminate are formed by etching

7.3.5.2 Fabrication of ALIVH. The manufacturing process is different from conventional circuit board fabrication in a number of ways, but, aside from requiring the use of unique materials (conductive paste and nonconventional prepreg) and multiple passes through core processes and typical HDI equipment (laser drill), the ALIVH process can be

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(a) Figure 7.14

227

(b)

Process flow chart for (a) ALIVH and ALIVH-B, and (b) ALIVH-FB.

integrated into a conventional process flow. An assumption is made that there is adequate excess capacity in the inner-layer FAB and lamination processes or sufficient space to expand capacity to support these and other special process steps. At the tooling process, each layer must now be analyzed as having both a copper component and a prepreg component. Depending on the stack-up, one or more lamination steps may be required to create the finished product. A decision is then required as to which layers have copper patterns (signal or power/ground), and these layers are routed through lamination and back to inner-layer print and etch. A drilling machine using a CO2 laser—which has been modified to use a mask or aperture system as part of the optical path to control the characteristics of the beam—is directed by galvanic mirrors to cover an area of approximately 400 mm2 in each step. Inner-layer fabrication begins with CO2 laser drilling of the Aramidepoxy prepreg in the pattern of the conductive pathways for each layer. All of the prepreg pieces for the complete stack-up are processed through a screen-printing operation to push the conductive paste inside the laser-drilled holes. If the prepreg is between the component layer and layer 2, or the circuit layer and layer n−1, these prepreg pieces (uncured) are set aside until the package is laminated later in the process. Those

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inner-layer prepreg pieces that are the equivalent of inner-layer cores are sent to lamination to have copper foil attached to both sides. These “cores,” which now have conductive pathways from side to side, are then processed through conventional inner-layer print-and-etch processes (clean, laminate resist, expose, DES, and AOI) to create the circuit/plane and pad patterns required by the design. Once this step is completed, the finished core(s) and the prepreg pieces for the outer layers—with conductive paste applied—are sent back into lamination to complete a conventional layup with a second application of foil and a second lamination cycle. The outer-layer image is created using an inner-layer print and etch process. Any remaining process steps (solder mask, etc.) are completed using standard processes. 7.3.5.3 Fabrication of ALIVH-B. The basic manufacturing process for ALIVH-B is the same as that for ALIVH, and the CO2 laser system with a mask in the optional path is the same. However, to achieve the lines and spaces and hold registration, additional modifications may be required in the image transfer and tooling processes. Image transfer may require a collimated light source, a thinner dry-film resist, film alignment capability at exposure, and/or a ferric chloride etchant with spray pattern enhancements. Registration from layer to layer may need to be improved with process control and designed experiments or a more robust tooling system. 7.3.5.4 Fabrication of ALIVH-FB. The manufacturing process for ALIVH-FB begins with the creation of the necessary support structure (the “substrate”) using the processes and design rules of ALIVH-B (see the preceding text). The ALIVH-FB build-up process begins with the creation of the outermost copper layers on a carrier material, such as aluminum. This can be accomplished either additively or using a subtractive process. In the additive process, for lines/spaces at 25 µm (1 mil) or less, photoresist is applied to the carrier, and the image is transferred using a projection mask, then developed and electroplated and the resist stripped. The dielectric for the build-up layers is a double adhesive polyimide film that is 12.5 µm (0.5 mil) thick. All of the polyimide layers are drilled using a YAG laser with an optical mask set for 50 µm (2 mil), and these vias are filled with conductive paste using the screen-printing technique common to all ALIVH processes. Next, the imaged carrier is aligned with one side of the polyimide film and copper foil is matched with the other side. This structure is laminated together. During lamination, the polyimide fills in around the patterned copper on the carrier side, using the carrier as a continuous, flat barrier. The copper foil bonds to the polyimide on the opposite side. After pressing, the copper foil side is patterned using standard inner-

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layer print-and-etch techniques. If more than one layer of FB build-up is required, the carrier is etched away and the first-pass lamination steps are repeated before the copper foil is patterned. FB layers are aligned with the Aramid-epoxy substrate layers created previously and the package is laminated a final time to create the competed FB structure. The carrier layers are etched away in the final processing step before finishing. 7.3.6 Electrical performance27

In order to design packages in the gigahertz frequency range, accurate equivalent circuits such as an interstitial via hole in an ALIVH substrate and a through-hole in an FR-4 substrate were extracted using a resonant method from 1 to 10 GHz. The ALIVH substrate is a highwiring-density multilayered organic substrate with inner via hole structure. The resonant method uses the principle that the resonant frequency of a resonator is perturbed by the connection of a lumped element. The via hole was described as a single π-type network model: a series inductance and two parallel capacitances. Consequently, it was confirmed that signal reflections at the via hole were perfectly suppressed by an optimization of geometric dimensions of the via hole, such as the size of a ground plane cutout. Based on these results, the ALIVH substrate was found to be good enough to apply to high-speed systems up to 10 GHz. The via holes in the ALIVH substrate and the FR-4 substrate were characterized by actual measurement using the resonant method in the high frequency range. The influence of the radius of the ground plane cutout and the height of the via hole was also evaluated. Consequently, it was confirmed that the signal reflections at the interstitial via hole were perfectly suppressed by an optimization of geometric dimensions of the interstitial via hole such as size of the inner ground plane cutout. Based on these results, the ALIVH substrate was found to be good enough to apply to high-speed systems up 10 GHz. 7.3.6.1

Geometric influence

A reference resonator and target resonator with different radius r of the inner ground plane cutout in the ALIVH substrate were fabricated, as shown in Fig. 7.15. This is a cross-sectional view of the target resonator with r = 0.45 nm and h = 448 nm. The radius of the via hole and the via land were 0.1 mm and 0.2 mm, respectively. The thickness of the inner ground plane was 18 µm. The resonant characteristics were measured using an HP8719D network analyzer from 1 to 10 GHz frequency. Measure values Xseries and Xshunt were inductive and capacitive, respectively. In Figs. 7.16 and 7.17, the equivalent series inducCutout size.

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Cross-sectional view at the center region of the target resonator with four stacked vias in the ALIVH substrate.

Figure 7.15

Figure 7.16 Equivalent series inductance of the via hole as a function of the resonant frequency for different radii of the inner ground plane cutout (ALIVH).

tance and shunt capacitance of the via hole are shown as a function of resonant frequency from 1 to 10 GHz for the radius r = 0.3 mm, r = 0.45 mm, r = 0.7 mm, and r = 1.2 mm of the inner ground plane cutout. The influence of the radius r of the inner ground plane cutout is shown in Figs. 7.18 and 7.19. The equivalent series inductance and the equivalent shunt capacitance were L = 0.167 nH and C = 0.084 pF, respectively, for radius r = 0.45 mm of the inner ground plane cutout. The equivalent series inductance increases gradually with the radius r. On

Figure 7.17 Equivalent shunt capacitance of the via hole as a function of the resonant frequency for different radii of the inner ground plane cutout (ALIVH).

Equivalent series inductance of the via hole as a function of the radius of the inner ground plane cutout at 1 GHz (ALIVH).

Figure 7.18

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Figure 7.19 Equivalent shunt capacitance of the via hole as a function of the radius of the inner ground plane cutout at 2 GHz (ALIVH).

231

Equivalent series inductance of the via hole as a function of the height of the via hole for different radii of the inner ground plane cutout (ALIVH).

Figure 7.20

the other hand, die equivalent shunt capacitance decreases gradually with the radius r. Via hole height. In order to evaluate the influence of the height of the via hole, a reference resonator and target resonators with height h = 224 µm of the via hole in the ALIVH substrate were fabricated. In Figs. 7.20 and 7.21, the equivalent series inductance and shunt capacitance of the via hole are shown as a function of resonant frequency from 1 to 6 GHz for the radius r = 0.3 mm, 0.45 mm, and 0.7 mm of the inner ground plane cutout. The comparison for the equivalent series inductance and shunt capacitance with different height h of the via hole is shown in Table 7.4. The equivalent series inductance increases with

Equivalent shunt capacitance of the via hole as a function of the height of the via hole for different radii of the inner ground plane cutout (ALIVH).

Figure 7.21

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TABLE 7.4 Comparison of the Equivalent Series Inductance and Shunt Capacitance with Different Heights of the Via Hole

h (µm)

r (mm)

L (nH)

C(pF)

224

0.45

0.070

0.093

448

0.45

0.167

0.084

the height h. On the other hand, the equivalent shunt capacitance decreases slightly with the height h. Through-hole in an FR-4 substrate. The high-frequency properties of the through-hole in PR-4 substrate with a conventional four-layered structure were evaluated as shown in Fig. 7.22. The figure is a cross-sectional view of a center region of the target resonator in die FR-4 substrate. A reference resonator and target resonators with different radius r of the inner ground plane cutout were fabricated. The radii of the throughhole and the through-hole land were 0.15 and 0.3 mm, respectively. The total thickness of the substrate was 1.6 mm. The thickness of the inner ground plane was 35 µm. In Figs. 7.23 and 7.24, the equivalent series inductance and shunt capacitance of the via hole are shown as a function of resonant frequency from 1 to 6 GHz for the radius r = 0.45 mm, 0.55 mm, 0.8 mm, and 1.3 mm of the inner ground plane cutout. The equivalent series inductance and shunt capacitance were L = 0.685 nH at 1 GHz and C = 0.248 pF, respectively, at 2 GHz for radius r = 0.45 mm.

7.3.6.2 Simulation analysis. In order to validate the signal response at the die via hole, the calculation of die reflected step waveforms was carried out using an HP85150 microwave design system (MDS). The simulated circuit model shown in Fig. 7.25 represents the π-type network model of the via hole connected to ideal transmission lines with a series resistor in order to match the characteristic impedance of the die transmission line. Figure 7.26 shows the time domain pulse response for the reflected waves for the radius r = 0.3 mm, 0.45 mm, and 1.2 mm of the inner ground plane cutout. Rise time of the input step waveform with 1-V swing was 45 ps. Propagation delay time in the ideal trans-

Figure 7.22 Cross-sectional view at the center region of the target resonator with conventional PTH in the FR-4 substrate.

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Equivalent series inductance of the through-hole as a function of the resonant frequency for different radii of the inner ground plane cutout (PTH in FR-4).

Figure 7.23

233

Figure 7.24 Equivalent shunt capacitance of the through-hole as a function of the resonant frequency for different radii of the inner ground plane cutout (PTH in FR-4).

mission lines was 50 ps. The element values to perform this calculation are shown in Table 7.5. The waveforms varied significantly according to the radius of the ground plane cutout. Figure 7.27 shows the magnitude of |S11| for the radius r = 0.3 mm, 0.45 mm, and 1.2 mm of the inner ground plane cutout. The reflections were 3.3 percent for radius r = 0.45 mm and 14 percent for radius r = 0.3 mm and 1.2 mm at 10 GHz. 7.3.6.3 Comparison and discussion. Comparison of the design specification of the ALIVH and build-up substrate is shown in Table 7.6. Though there are many differences in the geometry and dimensions between the ALIVH and build-up substrates, they perform the same functions. The via hole that connected each surface of the substrate was noted. Since the geometry of the ALIVH substrate is very similar to the geometry in the previous section, the inductance of the four stacked via holes is about 0.2 nH. Build-up substrate includes the FR-4 substrate as a core layer. Since the thickness of the core layer in the build-up substrate is half of that in the previous section, the inductance of the through-hole is about 0.4 nH. Therefore, it is concluded that the inductance of the via hole in the ALIVH substrate is half of that in the build-up substrate.

Figure 7.25

Circuit model for simulation.

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Figure 7.26 Reflected pulse waveform for different radii of the ground plane cutout.

7.3.7 Reliability testing2

In the literature, it has been reported that the ALIVH substrate can pass 1000 thermal cycles for the temperature range from −55 to 125°C. The reliability test data of ALIVH and ALIVH-B are presented in Tables 7.7 and 7.8, respectively. The reliability testing for the FB structures is still ongoing. The available data show that the pressure cooker test has been completed at 121°C, 2 atm for 480 h. An atmospheric thermal shock test from −40 to 80°C, with a 30-min cycle time, has run for 1500 cycles. In all cases, the resistance of the 50-µm (2-mil) holes remains stable. 7.3.8 Applications

The basic ALIVH process should be considered for products requiring lightweight, small, low-layer-count, thin profiles and high reliability. Many cell phones currently being manufactured in Japan use this technology. The ALIVH-B process capability was developed for the motherboard, chip-scale package, and multichip module market segments of the computer products sector. As you can see from the design rules, the ALIVH-B process is very competitive with the most advanced HDI processes. The ALIVH-FB process is designed for direct chip attach applications. It is designed to address the issues of coplanarity in assembly for this TABLE 7.5

Electrical Parameters Used for Simulation r (mm)

L (nH)

C (pF)

0.3

0.108

0.134

0.45

0.147

0.081

1.2

0.269

0.019

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Magnitude of |S11| for the radii of r = 0.3 mm, 0.45 mm, and 1.2 mm of the inner ground plane cutout.

Figure 7.27

industry segment. The ALIVH-FB process is the equivalent of a build-up multilayer process using a conventional FR-4 substrate and laminating photoimageable dielectric or resin-coated copper layers to the outside. In this case, the ALIVH-FB layer or layers are added to a “substrate” that is one or more layers manufactured using the ALIVH-B process described previously. The FB process requires both CO2 and YAG laser capability, additional image transfer capability, and implementation of an etchable carrier system for the build-up layers. However, the breakthrough in the FB process is the embedding of circuitry into the outermost dielectric layer—which is 12.5-µm (0.5 mil)-thick polyimide film using the carrier sheet as a barrier. The resulting surface coplanarity of the structure (measured at 1 µm over 9 mm in prototype volumes) is capable of meeting the assembly process requirements for direct chip attachment. 7.4 OrmeLink Parallel Build Technology While current leading-edge products have achieved 495 leads/in2 (76.7 leads/cm2), projections for the year 2000 show a need for 17,760 TABLE 7.6

Comparison of Design Specifications Between ALIVH and Another Build-up Substrate ALIVH

Build-up

Layer structure

4

2-2-2

Substrate thickness

0.4 mm

0.8 mm (core layer)

Via diameter

0.2 mm

0.3 mm (core layer)

Land diameter

0.4 mm

0.6 mm (core layer)

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TABLE 7.7

Reliability Test Results of Standard ALIVH Results

Conductivity

High-temperature storage

Test description

150°C/1000 h

Test conditions

Pass

N/A

Low-temperature storage

−65°C/1000 h

Pass

N/A

High humidity

60°C/90% RH/1000 h

Pass

Pass

High humidity + load

60°C/90% RH/15VDC/ 1000 h

Pass

Pass

Thermal cycling

−65°C to 125°C/100 cycles

Pass

N/A

Hot oil

260°C (10 s) to 20°C (10 s)/ 10 cycles

Pass

N/A

Reflow resistance

240°C peak temperature, 4 times

Pass

N/A

leads/in2 (2,753 leads/cm2).28 At the same time, flip chip packages are increasingly being made from laminate materials instead of the more conventional ceramic or thin-film technologies. To meet these needs, a new generation of printed circuit boards and laminate packages is needed that can achieve the high density required. The density in conventional substrate technology is primarily limited by the need to drill through the entire stack to achieve vertical interconnections. Large capture pads are required and, in the layers where the connection is not desired, circuitry must be routed around these drilled vertical interconnects. To achieve blind and buried vias using printed circuit board technology, one approach is to use controlled-depth drilling. TABLE 7.8

Reliability Test Results for ALIVH-B

Test description

Test conditions

Results

High-temperature storage

150°C, 2000 h

Pass

Low-temperature storage

−65°C, 2000 h

Pass

High-temperature and highhumidity storage

85°C/85% RH, 2000 h

Pass

Pressure cooker test (PCT)

121°C, 0.2 MPa, 200 h

Pass

Thermal shock (high and low temperature)

−65°C for 30 min to 150°C for 30 min, 1000 cycles

Pass

Thermal shock (high-temperature immersion)

20°C for 10 s to 260°C for 10 s, 200 cycles

Pass

Reflow soldering heat

260°C for 10 s, 10 cycles

Pass

High temperature and humidity + reflow heat

85°C/85% RH, 16 h + 260°C, 10 s, 3 times

Pass

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However, mechanical drilling depth control is limited to ⫾35µm. Alternatively, sequential lamination of predrilled copper-clad laminate sheets and prepregs has also been used to make blind and buried via constructions. Ultimately, however, these approaches are limited not only by the capabilities of the mechanical drilling to make the fine vias, but also by their high cost. Drilling costs increase substantially for smaller holes, with the cost for 100-µm (4 mil) holes being 18 times that for 340-µm (13.5 mil) holes.29 Furthermore, capture pads still remain an issue with this approach. A number of novel blind and buried via technologies have been proposed over the last few years to eliminate the density limitation. Most of these techniques utilize additive or sequential build-up. Because of this, and because of the fact that the vias are small compared to standard drilled vias, these structures are alternately called build-up technologies (BUT) or microvia technologies. They are generally classified according to the different methods of via formation as photovia, plasmaetched via, and laser-drilled via technologies. The first of these uses permanent photoimageable inner-layer dielectric materials (coated liquids or laminated dry films) that are photoprocessed similarly to solder mask materials, except that these materials are designed to remain on the board permanently and become the inner layers. Plasma processing, the second of these, utilizes plasma ablation of dielectric, most commonly using the top copper circuit as an etch mask. The last technique, laser drilling, is done by ablation of the via using a conformal mask or a directly focused beam, with either a UV-Nd:YAG or a CO2 laser. Combinations of the laminate technology with thin-film deposition have also shown good results, but carry a substantial penalty in capital equipment costs. An alternative approach that addresses both the in-plane and vertical density requirements as well as price targets uses circuit “layer pairs” manufactured using adhesiveless copper clad polyimide film. Roll-to-roll manufacturing allows cost reduction through reduced labor costs and improved yields.30 Prior to deposition of any metal, 1- to 2-mil vias are laser-cut into the unreinforced, precast polyimide film in a regular grid pattern or in specified locations. The planar surfaces and vias are then simultaneously metallized, resulting in a significant cost savings in processing. High-density layer pairs with virtually landless through-holes can thus be constructed on a very cost-effective basis. These layer pairs can be laminated to create a multilayer circuit using conventional drilled stack vertical interconnection. Traditionally, vertical interconnection in these multilayer stacks is accomplished by drilling and plating holes through the entire construct. An innovative interconnection strategy is required to reclaim the wasted real estate

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on both surface and interior layers that is endemic to this process. However, in order to take the best advantage of the technology, blind and buried vertical interconnections are required on a layer-to-layer basis. One method of achieving cost-effective selective interconnection uses an anisotropically conductive adhesive film. While this approach supports the creation of low- and medium-density vertical interconnects, it is not capable of achieving higher densities and does not adequately address the issue of dielectric separation between layers. The alternative approach presented here uses a patterned organic-metallic TLPS conductive composite material to achieve a high-density, reliable vertical interconnect. 7.4.1 TLPS conductive composite

Most conductive polymer materials are thermosetting or thermoplastic resins loaded with metal powder that provides conduction through contact of particles. They can be either isotropic or anisotropic depending on the level of the conductive particle loading and the method of application. The main deficiencies of these passively loaded polymers occur with temperature and humidity fluctuations. These fluctuations cause loss of electrical continuity due to the oxidation of the contact pads and the expansion of the polymer.31 In addition, no metallurgical connection is formed with the pads when conventional conductive compositions are used. These deficiencies are addressed by a novel conductive composite material that was introduced a few years ago for the purpose of replacing copper traces in selected applications.32 The combination of TLPS of the metals and a permanent adhesive flux binder delivers electrical conduction through sintered metal joints and mechanical properties based on a tailorable polymer matrix. In some ways, these materials are analogous to cermets, except that unlike the ceramic composites, processing of Ormet® (organic-metallic) composites is done at temperatures compatible with standard printed circuit board materials and processing conditions. Once cured, the material is stable in thermal exposures well above the initial process temperature. These conductive composites overcome several of the disadvantages of passively loaded compositions. Of particular importance to the application for vertical interconnection, they provide a low and stable bulk resistance value on the order of 35 µΩ/cm. This stable electrical performance under both normal use and environmental and thermal cycling is the result of the alloyed metallurgical web. This alloyed web microstructure is contiguous not only through the bulk material, but to solderable pad finishes as well.

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Specialized versions of these TLPS conductive composites have been used in applications as diverse as fabrication of additively processed circuit boards with fine lines and blind and buried microvias, surface mount attach of electronic components, and vertical interconnections for the fabrication of the high-density substrates presented here. In the development of TLPS composite materials for the vertical interconnect application, the following parameters were considered: interconnect configuration used, application methodology, B-staging conditions and requirements, and lamination/joining conditions. With these issues in mind, appropriate TLPS composites were developed for the two primary methods of vertical interconnect investigated and described here. 7.4.2 High-density multilayer substrate development33–38

Development of vertical interconnections was undertaken in conjunction with the development of multilayer lamination. This included consideration of a number of issues including feature sizes, type of adhesive system, vertical interconnect configuration, application methodologies for the Ormet® composite material, and lamination conditions. Double-sided circuits (layer pairs) were first constructed of polyimide with drilled and plated vias and copper circuits. Initial circuit features were 50-µm (2 mil) lines and spaces and 200-µm (8 mil) pads on 500-µm (20 mil) pitch. A micromachining laser was used to drill vias in specified locations in the film that were then plated up. Vias in the layer pairs were typically 25 µm (1 mil). Later work used 38-µm (1.5 mil) lines with 50-µm spaces and 125-µm (5 mil) pads. These layer pairs were then laminated using various B-stage adhesive systems. Vertical interconnections were established in a number of configurations that utilized the TLPS conductive composite. A significant amount of the development was devoted to choosing the appropriate B-stage adhesive system for the construction. Reinforced and nonreinforced adhesives were examined. Issues of importance included thermal, dimensional, and mechanical material properties, handling, lamination at close to standard printed circuit board industry temperatures, flow of the adhesive system, circuit and interconnect encapsulation, and dielectric separation control. Among the reinforced systems, both woven and nonwoven fiber reinforcements were examined for their properties with regard to drilling capabilities and resin flow during lamination. Nonreinforced systems explored included glasssphere-filled adhesives as well as adhesives coated on polyimide film. While the former has shown promise and will be important as the

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dimensions get finer, the adhesive materials used in the constructions discussed here were of the reinforced type or coated on film. 7.4.3 Vertical interconnect configurations

The three basic vertical interconnect configurations developed are shown in Fig. 7.28. The first of these uses a perforated B-stage dielectric bond-ply material. The vias in the bond-ply are filled with the TLPS composite by one of many methods including stenciling, doctor blading with the use of a cover sheet, or filling the pattern-perforated dielectric with a custom pressure-assisted tool. The bond-ply is then placed between the two parts that are to be connected, aligned, and cured. The second configuration uses stenciling of the TLPS composite directly onto the circuit pads of the top layer to create a post. The post serves as a contact point and is aligned with a copper pad on the circuit that is to be connected. The composite will form a metallurgical bond with both pads during the cure cycle. In both configurations, the vertical interconnection relies totally on the Ormet® conductive composite to achieve the vertical interconnect link (OrmeLink). The third configuration uses stenciling of the TLPS composite directly onto the circuit pads of the top layer, but this time it is used to

Three configurations of vertical interconnects utilizing TLPS conductive composite.

Figure 7.28

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create a reduced-volume post. The bottom layer is plated up with a copper post. When the two layers are aligned, the plated post will make contact with the B-staged TLPS ink post and in the lamination cycle a metallurgical connection will be made between the two posts. This configuration relies on the combination of post and TLPS composite to achieve the vertical interconnect. In all cases, the TLPS material is B-staged for handling and storage life. The circuit layer pairs and the bond-ply sheets are interleaved and aligned and the stack is inserted into a lamination press. Lamination conditions are typical of printed circuit board industry practices. A variety of test structures have been used to determine the properties of vertical interconnects using TLPS composites. Early work highlighted the importance of concurrent engineering in the choice of materials and process conditions. Following the feasibility experiments, two representative test vehicles were developed using the structures described previously. The first was a six-layer structure that is being developed as a flip chip substrate. This structure used configuration I or III. The second was a selective multilayer patch for high density in certain portions of the circuit board. It used the TLPS contact points described in configuration II. 7.4.4 Multilayer chip package

As mentioned before, flip chip package substrates require high densities in order to route the signal from the die. Increased I/O means finer lines and spaces as well as smaller pads and vias. This also requires the capability of stacking the vias in the substrate. A six-layer daisy chain test vehicle designed to emulate a multilayer flip chip package was used to develop the methods for achieving vertical interconnections using the TLPS conductive composites. The structure used 200-µm-diameter pads, which is adequate for a 500- to 700-pin package. Figure 7.29 shows the cross-section of a six-layer structure in which the adhesivecoated 50-µm polyimide film was filled with the TLPS conductive composite and laminated between two pads. The alignment of the vertical stack is within ⫾12 µm. For 1600-pin packages, 125-µm or smaller pads will be required. Development is currently under way on both of the previously mentioned vertical interconnect configurations to achieve these higher densities. Figure 7.30 shows a cross section of stacked vias made using the method of plated posts and reduced-volume TLPS posts to connect two 100-µm pads. The plated posts are connected to the TLPS posts as seen in Fig. 7.30. Vias of this size have been used to connect 200-µm pads, but smaller pads are possible, although registration may be an issue. Smaller vias are also considered feasible with this approach. The lim-

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Figure 7.29

Cross section of vertical interconnects between 200-µm pads in a multilayer

substrate.

its of this technology have also been under investigation. Figure 7.31 shows the 225-µm pads connected with 55-µm TLPS joints in an eightlayer structure. In this case the whole joint is made of the composite material. Even though the pads in this case were rather large, the cross-section reveals that with proper registration, pad size could be significantly reduced. 7.4.5 Selective multilayer patch

Many applications, such as those required for flip chip attach, require high densities only in certain areas of the board. In these situations, it is uneconomical to fabricate the entire printed circuit board at this high density level. To overcome this problem, a layer pair patch can be laminated onto a conventionally fabricated low-density printed circuit board to create a localized area of high density. This concept is illustrated in Fig. 7.32. The electrically conductive adhesive contact points illustrated in Fig. 7.32 were created by stencil printing on top of plated posts. This approach (configuration II) was used because of the availability of large interconnection pads on the low-density PCB. Additionally, the printed circuit board used in this case had a through-hole to which this patch was connected, thus necessitating a larger post to achieve the

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Figure 7.30

243

Cross section of stacked plated post/TLPS composite vias between 100-µm

pads.

Cross section of an eight-layer circuit that uses conductive composite-filled bond-ply.

Figure 7.31

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Figure 7.32

High-density laminate patch application.

vertical connection. A top view of the laminated PCB with the highdensity patch underneath is given in Fig. 7.33. A cross section of the vertical connection between the TLPS conductive composite stenciled on a plated post and a 0.5-mm (20 mil) plated through-hole on a low-density PCB is seen in Fig. 7.34. The TLPS conductive composite forms a metallurgical contact with the copper (blind joint on the side of the through-hole) and also fills part of the throughhole in the low-density PCB, forming a good fillet. This construction was then laminated to a heat sink as shown in Fig. 7.32 and subsequently assembled with components. This product is currently undergoing long-term reliability testing in an automotive environment. The multilayer patch can also be applied on or incorporated between two or more standard PCBs. This design allows for the construction of a multilayer structure with the use of standard printed circuit boards.

High-density film patch laminated onto a lowdensity PCB.

Figure 7.33

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Figure 7.34 Cross section of a vertical interconnect made for a high-density patch.

7.4.6 Reliability test results

The constructions discussed have been tested for shorts and opens. Some of them have also been subjected to basic reliability testing. Multilayer connections with 200-µm pads that use the plated post and the TLPS post approach have been tested with 250 liquid-to-liquid thermal shocks (−100 and +100°C, 3 min at each extreme with 15-s transfer). After every 25 cycles, measurements were taken to determine the resistance of each daisy chain pattern, which includes 1857 25-µm plated copper vias and 1238 100-µm post joints. There were no failures in the seven daisy chain samples tested, and the change in resistance averaged less than 10 percent. Constructions that used an all-TLPS joint were also subjected to environmental testing. Humidity testing at 85°C/85 RH for 7 days as well as 1000 air-to-air thermal shock cycles between −55 and +150°C showed less than 10 percent change in resistance. The all-TLPS joints averaged less than 10 mΩ, with most being less than 5 mΩ. With the drive toward higher density substrates, laser processing has allowed the fabrication of a circuit layer pair with plated vias as small as 25 µm. To achieve a high-density multilayer construction, lamination of the layer pairs is needed with appropriate vertical interconnects. Several approaches have been explored for this purpose, including various anisotropic adhesives. As an alternative, the use of patterned TLPS vertical interconnects guarantees a better electrical connection as well as assurance of controlled dielectric separation with the use of an appropriate bond-ply. The TLPS conductive composites used for vertical interconnects either alone or in combination with a plated post have demonstrated the capability of joining pads as small as 100 µm to create multilayer structures. The composites form a good metallurgical connection to the circuit pads, as shown by the cross sec-

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tions of the eight-layer circuits done so far. These composites are currently being tested for multilayer chip carriers as well as for attachment of high-density multilayer circuit patches. Environmental and electrical testing is under way at several companies. The substrates that are feasible with the use of these technologies offer a number of advantages over current interconnect densities. The fine-line capabilities of the flexible circuit layer pairs together with the very fine vias in the layer pairs and in the bond-ply allow for very dense circuitry in a thin substrate. Additionally, this technology allows for buried, blind, and stacked vias, which will further enhance the circuit density and allow for reduction of the layer count. 7.5 References 1. Lau, J. H., and C. Chang, “An Overview of Microvia Technology,” Circuit World, 26(2): 22–32, January 2000. 2. Boggio, B., “The Any-Layer Interstitial Via Hole Processes,” Board Authority, 2(1): 91–95, April 2000. 3. Matijasevic, G., C. Gallagher, and P. Gandhi, “High Density Multilayer Substrates Using Patterned Microvia Interposers,” Proceedings of IEEE Aerospace Conference, Snowmass, CO, March 1998. 4. Kang, S. K., S. Buchwalter, N. LaBianca, J. Gelorme, and S. Purushothaman, “Development of Conductive Adhesive Materials for Via Fill Applications,” Proceedings of 50th ECTC Conference, pp. 887–991, Las Vegas, NV, May 2000. 5. Gilleo, K., “Die Attachment for Today’s Packaging Challenges,” Elec. Pack. Prod., 2: 109, 1994. 6. Gilleo, K., “Evaluating Polymer Solders for Pb-Free Assembly,” Circuit Assembly, 1: 52, 1994. 7. Saraf, R. F., and J. M. Roldan, “Polymer/Metal Composite for Interconnection Technology,” Proceedings of 45th Elec. Comp. Tech. Conf., p. 1051, Las Vegas, NV, 1995. 8. Gallagher, C., G. Matijasevic, and M. Capote, “Transient Liquid Phase Sintering Conductive Adhesives,” Proceedings of Surf. Mount Tech. Int. Conf., p. 568, San Jose, CA, 1995. 9. Kang, S. K., and S. Purushothaman, “New High Conductivity Lead (Pb)-Free Conducting Adhesives,” Proceedings of IEEE Int. Sym. on Electronics & the Environment, p. 177, Orlando, FL, 1995. 10. Dietz, R., and D. Peck, “An Innovation in Thermoplastic Reworkable Adhesive Pastes,” Microelectron. Int. (U.K.), 1(39): 52, 1996. 11. Kang, S. K., R. Rai, and S. Purushothaman, “Development of High Conductivity Lead (Pb)-Free Conducting Adhesives,” Proceedings of 46th ECTC, p. 565, 1996. 12. Klosterman, D., L. Li, and J. Morris, “Materials Charact., Conduction Dev. and Curing Effects on Reliability of Isotropic Conductive Adhesives,” Proceedings of 46th ECTC, p. 571, 1996. 13. Kotthaus, S., B. Gunther, R. Haug, and H. Schafer, “Study of Isotropically Conductive Bondings Filled with Aggregates of Nano-sized Ag-Particles,” IEEE Trans. CPMT, Part A, 20(1): 15, 1997. 14. Huang, W. S., I. Khandros, R. Saraf, and L. Shi, “Solder/Polymer Composite Paste and Method,” U.S. Patent 5,062,896, November 5, 1991. 15. Gallagher, C., G. Matijasevic, and J. F. Maguire, “Transient Liquid Phase Sintering Conductive Adhesives as Solder Replacements,” Proceedings of 47th ECTC, p. 554, 1997. 16. Kang, S. K., R. S. Rai, and S. Purushothaman, “Dev. of High Conductivity Lead (Pb)Free Conducting Adhesives,” IEEE Trans. CPMT, Part A, 21(1): 18, 1998. 17. Iwasa, Y., “Conductive Adhesive for Surface Mount Devices,” Elec. Pack. & Prod., 11: 93, 1997.

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18. Kang, S. K., and S. Purushothaman, “Development of Low Cost, Low Temp Conductive Adhesives,” Proceedings of 48th. ECTC, p. 1031, Seattle, WA, 1998. 19. Kang, S. K., and S. Purushothaman, “Development of Conducting Adhesive Materials for Microelectronic Applications”, J. Elec. Mat’s, 2(11): 1312, 1999. 20. Gonzalez, C., R. Wessel, and S. Padlewski, “Epoxy-Based Aqueous-Processable Photodielectric Film and Conductive ViaPlug for PCB Build-Up and IC Packaging,” Proceedings of 48th Elec. Comp. Tech. Conf., p. 138, 1998. 21. Bhatt, A., D. Glatzel, A. Moring, V. Markovich, K. Papa-Thomas, and D. Russell, “Manufacturing Circuit Board Assemblies Having Filled Vias,” U.S. Patent 5,822,856, October 20, 1998. 22. Kulesza, J., V. Markovich, K. Papathornas, and J. Sabia, “Method for Applying Curable Fill Composition to Apertures in a Substrate,” U.S. Patent 5,887,345, March 30, 1999. 23. Xiao, A. Y., Q. K. Tong, A. C. Savoca, R. L. Frentael, M. C. Rendle, and H. V. Oosten, “Conductive Ink for Through Hole Application,” Proceedings of 50th ECTC Conference, pp. 882–886, Las Vegas, NV, May 2000. 24. Gilleo, Ken, “Conductive Adhesives—Making the No-Lead Connection,” Assembly, March 1995. 25. Andoh, Daizo et al., “New Concept High Density Multilayered Printed Circuit Board for Bare LSI Chip Direct Attach,” Proceedings of Printed Circuits World Convention 8, Tokyo, Japan, 1999. 26. Ishimaru, Yukihiro et al., “Advanced ALIVH Substrate with Fine Design Rules for High Density Packaging,” Proceedings of Printed Circuits World Convention 8, Tokyo, Japan, 1999. 27. Iwaki,, H., Y. Taguchi, Y. Bessho, and K. Eda, “High Frequency Electric Characterization of a Via Hole in a Multi-layered Organic Substrate,” Proceedings of IMAPS International Symposium on Microelectronics, pp. 100–105, April 1999. 28. Holden, H., “Micro-Via PCB’s: The Next Generation of Substrates and Packages,” Future Circuits International, 1(1): 71–76, 1997. 29. Tessier, T. G., and J. G. Aday, “Casting Light on Recent Advancements in Laser Based MCM-L Processing,” Proceedings 5th International Conference on Multichip Modules, pp. 6–13, Denver, CO, April 1996. 30. Gengel, G., “A Process for the Manufacture of Cost Competitive MCM Substrates,” Proceedings 3rd International Conference on Multichip Modules, pp. 182–187, Denver, CO, April 1994. 31. Keusseyan, R. L., and J. L. Dilday, “Electric Contact Phenomena in Conductive Adhesive Connections,” Proceedings Surface Mount International, pp. 567–571, San Jose, CA, August 1993. 32. Capote, M. A., M. Todd, P. Gandhi, C. Carr, W. Walters, and H. Viajar, “Multilayer Printed Circuits from Revolutionary Transient Liquid Phase Inks,” Proceedings NEPCON West, pp. 1709–1715, Anaheim, CA, February 1993. 33. Tsukada, Y., and Y. Mashimoto, “Low Temperature Flip Chip Attach Packaging on Epoxy Base Carrier,” Proceedings Surface Mount International, p. 294, San Jose, CA, 1992. 34. Okano, M., S. Nakamura, Y. Isozaki, K. Kawakita, H. Sogou, T. Kojima, and T. Ogawa, “Any Layer IVH Structure Multi Layered Printed Wiring Board,” Proceedings of Microelectronics Symposium, pp. 163–166, 1995. 35. Uno, H., and M. Kawade, “Multilayer Printed Circuit Board and Method of Producing the Same,” U.S. Patent 5,827,604, October 27, 1998. 36. Lasky, R., “New PCB Technologies Emerge for High Density Interconnect,” Elec.Packg.&Prod, 75, 1998. 37. Kawakita, K., S. Nakatani, T. Ogawa, M. Suchiro, K. Iwaisako, and H. Aklyama, “Conductive Paste Compound for Via Hole Filling, Printed Circuit Board which Uses the Conductive Paste,” U.S. Patent 5,652,042, July 29, 1997. 38. Eda, K., “Advanced Packaging and Substrate Technology Using Conductive Adhesives,” Proceedings of 3rd Int. Conference on Adhesive Joining and Coating Technology in Electronics Manufacturing, p. 144, Binghamton, NY, 1998.

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Source: Microvias

Chapter

8 Special High-Density Interconnects for Flip Chip Applications

8.1 Introduction As the technology advances in IC density, speed, and function, so does the need for improved packaging performance. The trend toward higher device frequencies and higher I/Os on chips increases the need for an optimized next level of packaging hierarchy or interconnect. The focus is on improving both the electrical and thermal performances of the package (or substrate) and its density for enhancing the functionality of the finished device. A high-density substrate (or interconnect) should have the following characteristics:1–7 ■

Enhanced mechanical, electrical, thermal, physical, and chemical properties, such as low relative dielectric constant, low moisture absorption, low dissipation factor, low thermal coefficient of expansion, high glass transition temperature Tg, high thermal conductivity, high copper ductility, high copper peel strength, high dimensional stability, good solvent resistance, good chemical resistance, and high reliability

■

Microvias

■

High-density and fine-line circuitry while ensuring signal integrity

■

Enhanced adhesion of thin metal films to the dielectric and base substrate

249

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The substrate (or interposer) of a solder-bumped flip chip (FC) constitutes a very critical element in a PBGA package. Important functions of the FC-PBGA interposer are shown in the following list: ■

To provide a path for the electrical current that powers the circuits on the chip

■

To enhance device performance beyond interconnection wiring

■

To route signals

■

To reconnect data from one sector of the chip to another

■

To increase density and switching speeds

■

To improve bandwidths and control impedance

■

To utilize integral inductive/resistive/capacitive layers

■

To help to remove the heat from the chip

■

To support the chip and protect it from hostile environments

In this chapter, high-density substrates made by three different companies (Toshiba, X-LAM, and Amitec) for flip chip applications are discussed. It is noted that Toshiba and Dai Nippon Printing Co., Ltd. have recently formed a new start-up company called D.T. Circuit Technology Co., Ltd. for making the B2it™ PCB and substrate. 8.2 Toshiba’s Buried Bump Interconnect (B2it‰) Technology Toshiba introduced a unique buried bump interconnect (B2it™) technology in 1996.1 A silver paste is deposited by printing to form conductive bumps on the backing copper foil. The conical bumps can pierce through dielectric prepregs to establish interconnections between conducting layers. The routing linespace patterns on the conducting layers are formed by a subtractive process using photoresist.2 Just like any other build-up board technologies, the B2it™ structure is intended to provide high-density electrical passages in the vertical dimension. An en bloc laminating process was developed by Toshiba to achieve this function. An x-ray lay-up machine was also developed to align the conductive bumps and the corresponding patterns with high accuracy. By repeating the lamination several times, a vertical array of multilayer stacked interconnects can be fabricated. Consequently, the massive signal I/Os of the high-density components can be fanned out in a 3-D fashion. By using the B2it™ method, it is possible to omit the outer-layer plating process. This is a significant advantage for fine-line technology because the circuits can be patterned by etching the copper foil alone.

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The B2it™ technology is now in mass production in Japan. In October 2000, Toshiba and Dai Nippon Printing (DNP) Co., Ltd., established a joint venture in printed circuit boards. The Toshiba Circuit Technology Corporation (PCB and Module Division of Toshiba) merged with DNP to form a new company called D.T. Circuit Technology Co., Ltd. The B2it™ technology is a major business sector of this new joint venture. The projected annual sales are aimed at 25 billion yen in the next 3 years.3 8.2.1 Design rules

The design rules for the current (standard) and future B2it™ methods are shown in Table 8.1. The ratio of conductor width to conductor space, denoted as L:S, will be improved from the current 100:100 µm to 75:75 µm in the future. The ultimate goal for the L:S ratio will be 50:50 µm. The bump diameter will be changed from the current 300 µm (with land diameter of 500 µm) to 150 or 200 µm (with land diameter of 300 µm), and then to 100 µm (with land diameter of 200 µm). These future high-density printed circuit boards are named Fine B2it™.4 According to Toshiba’s technology roadmap, further extended highdensity PCBs are under development using B2it™ printed circuit boards as the core and then adding thin layers of Cu/PI (polyimide) or Cu/BCB (benzocyclobutane) to the surface of B2it™ boards. Such PCB design is called D/L (deposit/laminate) structured boards, and is denoted as Fine φ3.4 8.2.2 Fabrication processes

Figure 8.1 shows an overview of the B2it™ printed circuit board manufacturing processes. First a conductive paste is deposited onto a copper foil using a printing technique. Subsequently the printed paste dries up and forms conductive bumps, as shown in Fig. 8.1a. These bumps are controlled to be in a conical shape so that they can pierce through the dielectric layer easily. Afterward, the bumps are pressed to pierce into a dielectric layer (prepreg). Figure 8.1b illustrates the tip of a bump emerging from the other side of the prepreg layer. A cross-sectional micrograph of a “buried” bump is shown in Fig. 8.1c.4 TABLE 8.1

B2it™ Design Rules Standard

Fine φ1

Fine φ2

Fine φ3

100:100

75:75

50:50

30:30

Bump diameter

300

150, 200

100

50

Pad diameter

500

300

200

75

Bump pitch

600

400

300

100

L:S

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(a)

(b)

(c)

2

Overview of B it™ processes. (a) Printing bumps. (b) Piercing into prepreg. (c) Interconnection between layers.

Figure 8.1

It should be noted that the original material of buried bumps is a silver-particle-filled conductive paste. The bonding between the copper foil and the formed silver bumps results from a combination of several physical phenomena such as the anchor effect, the rivet effect, and the diffusion between metals.5 The shapes of silver bumps after printing are shown in Fig. 8.2. The relationship between the diameter and the height of the bumps is presented in Fig. 8.3. A monotonic linear relationship is observed. It is very critical for the successful implementation of B2it™ technology to select appropriate dielectric layers and to control the height of the bumps. In order to accurately align the bumps with the printed circuit board pattern, a new x-ray lay-up machine has been developed by Toshiba. The working principle of alignment for this x-ray lay-up machine is illustrated in Fig. 8.4. First the target bumps on the copper foil are aligned to the corresponding identification patterns on the PCB (the board to be laminated) using an x-ray and charge-coupled device (CCD) apparatus. Afterward, a cream solder is printed at certain locations on the copper foil. A thermal compression process follows to attach the

Figure 8.2

Shapes of B2it™ bumps after printing.

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253

Correlation between diameter and height of B2it™ bumps after printing.

Figure 8.3

copper foil to the PCB. The accuracy of alignment should be within ⫾30 µm. After the attachment, the whole board is laminated using the conventional vacuum-lamination process. Figure 8.5 shows the schematic flow chart of the en bloc laminating process for the fabrication of B2it™ PCBs. It should be noted that the en bloc laminating process may be applied to form double-sided boards, PTH double-sided boards (buried or nonburied holes), multilayer PCBs, and B2it™ PCBs.5 With multiple laminations of bumped copper foils, a vertical array of stacked interconnects can be achieved. The signal distribution can then be extended horizontally on the dielectric layers. Such a feature is very effective in accommodating the assembly of SMT components with high-density grid I/O terminals, e.g., BGAs, butt-pin grid arrays, and flip chips with area-arrayed bumps. The electrical passage can be

Figure 8.4

X-ray lay-up machine.

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Chapter Eight

Figure 8.5

En bloc laminating process and cross section after

lamination.

routed vertically to as many layers down as required to fan out all signals from the mounted high-I/O components. 8.2.3 Application of high-density B2it‰ PCBs

By using the B2it™ method, it is possible to omit the outer-layer plating process. This is advantageous for PCBs with fine lines. A B2it™ PCB has been fabricated to mount a package with 190 pins and 0.5-mm pitch size.6 Bumps (0.2 mm in diameter) are butted to the double-sided board (0.3-mm thick BT resin) with drilled and plated (15 µm thick) holes. The electro deposition method was used to pattern the circuit. A photosensitive resin deposit of 8 µm thickness was formed by electrodeposition. By etching the copper foil alone, it is possible to create 60/60-µm fine-pattern circuits. A cross-sectional view (structure) is shown in Fig. 8.6a. The hot oil tests were performed by applying a heat shock of 260°C for 20 s (high temperature) and 20°C for 20 s (low temperature) for 100 cycles and measuring the rate of change or resistance values. Figure 8.6b shows a cross section of a bump after the solder float test at 260°C for 20 s. No sign of failure is observed.

photo 3 (a)

photo 3 (b)

(a) Cross section of B2it™ structure. (b) Crosssection of a single bump.

Figure 8.6

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Figure 8.7

Results of hot oil tests.

Figure 8.8

Results of solder float tests (260°C for 20 s).

255

Figure 8.7 shows the result of the hot oil test, indicating that the resistance is stable. Figure 8.8 shows the result of the solder float test, also indicating that the resistance is stable. Other items were tested as well. The testing results are given in Table 8.2. The B2it™ printed circuit boards show high reliability under all test conditions.

TABLE 8.2

Reliability Test Data for f0.2 Bumps

Item

Condition

Criteria

Results

DC500V 1 min

⭌100 MΩ

Passed

25°C ↔ 65°C/90–98% RH 10 cycles (240 h)

⭌100 MΩ

Passed

THBT

85°C/85% RH DC12 V/60 V 500 h

⭌100 MΩ

Passed

Thermal shock test

−65°C (30 min) ↔ 125°C (30 min) 100 cycles

<+20%

Passed

100°C 0.3A 1000 h

<+20%

Passed

Dielectric strength Temperature/humidity

TBT

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Chapter Eight

8.2.4 Application of fine B2it‰-to-semiconductor packaging

For φ0.15 via bumps, sharp printed tops were formed using a special paste as reported in Ref. 7. The shape of bumps observed by SEM is shown in Fig. 8.9. Further improvements were made to increase the height after printing. The shape observed by SEM is shown in Fig. 8.9c. The distribution of bump height (after printing and drying) was also improved as shown in Fig. 8.10. The reliability of interconnection was evaluated using test patterns. The results are shown in Table 8.3. Interconnection of the φ0.1 bumps can withstand even the solder dip test condition.

(b)

(a)

(c)

Micrographs of B2it™ bumps using (a) normal paste; (b) special paste; (c) modified paste.

Figure 8.9

Figure 8.10

Distribution of bump height.

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As shown in Table 8.1, it is necessary to create a fine pattern width as well as to reduce the size of the bumps. The B2it™ method makes a flat surface after lamination, and this advantage is utilized to introduce a circuit-patterning process that uses a spin coater. The patterning process is shown in Table 8.4. First, liquid resist is applied to the PCB using a spin coater. If the coating thickness is too thin, it has the role of an etching resist, although it is effective for fine-line imaging. If, on the other hand, the coating is too thick, the imaging resolution is lowered. The viscosity of the resist and the revolution speed of the spin coater should be well controlled in order to achieve a resist thickness of 5 µm. After exposure and developing, etching is performed using acid etching liquid and stripping the resist with caustic soda. Figure 8.11 shows

TABLE 8.3

Test Board Specifications

Number

Before (mΩ)

After (mΩ)

Rate of change (%)

1

2.855

2.925

2.5

2

2.809

2.898

3.2

3

2.848

2.940

3.2

4

2.297

2.358

2.7

5

2.386

2.416

1.3

6

2.778

2.855

2.8

7

2.859

2.940

2.8

8

2.443

2.490

1.9

TABLE 8.4

Major Parameters in the Patterning Process

Resist coat (5 µm) Dry Exposure Developing

Viscosity 100 CP Condition 500 rpm, 5 s 2000 rpm, 20 s 120°C × 30 min Exposure unit for liquid crystal 120 mJ tetramethylammoniumhydroxide (TMAH) 60-s dip

Postcure

120°C × 30 min

Etching

Copper chloride etching solution

Resist remover

Caustic soda

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Chapter Eight

Top view of patterns after etching.

Figure 8.11

top views of the patterns after etching. Using this technology, a prototype of high-density PCB was fabricated for the mounting of a 900-pin package. An overview is shown in Fig. 8.12. The product is a six-layer board with gold flash finish. The bump diameter is 100 µm and the L:S = 50:50 µm.

Front

Back

Specification -Bump diameter Φ 0.1 -6 layers (butted 4 times) -plated-through-hole (PTH) double-sided boards (buried) Cross-sectional structure

Figure 8.12

High-density B2it™ PCB for 900-pin

package.

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259

8.2.5 B2it‰ for low-cost BGA packaging

Due to their superior performance, thermally and electrically enhanced plastic BGA (EP-BGA) packages have gained more and more attention in the microelectronics industries.8 However, EP-BGA has the trade-off of relatively high price. With the aim of reducing the packaging cost, the B2it™ technology has been used as a substitute for conventional PTH technology to make high-performance printed circuit substrates. An EP-BGA package has been developed paying an attention to three major concerns, namely package structure, material selection, and assembly line construction.9 A high-density build-up board was fabricated with B2it™ technology. The B2it™ PCB makes it possible to locate ball pads and bond pads just above bumps. Besides, the B2it™ method does not require any special pad for bumps. Therefore, the wire traces may be easily designed. The required lead time for board fabrication is shorter than for other PWBs, which require special pads and through-holes. This technology can be use for high-speed I/O packages. A very simple cavity-down EPBGA structure has been realized that has only stiffener, adhesive, and B2it™ PWB. Other EP-BGAs have two stiffeners, but the developed EP-BGA has a stiffener that is a heat sink as well. So cost reduction can be achieved over other EP-BGAs with two stiffeners. The EP-BGA is mounted on a lead frame to make it possible to use a current QFP line for assembly of the EP-BGA. It does not require a special assembly line, which means any extra assembly cost is not required. The sample was mounted on the SEMI standard substrate and the thermal resistance was measured under conditions of air velocity at 0, 1, 2, and 3 m/s and power dissipation of 2 W. The thermal resistance was characterized as 12°C/W under natural convection. This result is superior to that of conventional tape ball grid array (TBGA). The results of thermal cycling on board with selected adhesive materials show no contact resistance degradation beyond 1400 cycles under the test condition of −65 to 125°C. 8.3 X-LAM’s High-Density Thin-Film Substrates For its UltraVia substrates, X-LAM uses microlithography techniques typically used in semiconductor processing to obtain fine features and tight pitches. Flat panel display (FPD)–type equipment is used to deposit thin film layers on 16 × 16 in. PCB panels (efficient manufacturing of packaging substrate with large panels). Thin-film substrates offer unique advantages compared with traditional build-up substrates, especially with regard to providing more and finer lines with tighter pitches. The thin-film substrate described in this section provides a routing density 2 to 3 times higher than that obtainable by con-

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Chapter Eight

ventional build-up methods (Figs. 8.13 and 8.14, Table 8.5). In this section, the design, process, performance, and reliability of UltraVia substrates will be discussed.10–12 8.3.1 Design of UltraVia substrates

A schematic representation of an UltraVia substrate is shown in Fig. 8.15. It is a 1+2L+1 core and 2 thin-film metal layers of substrate, i.e., (1 + 2L + 1) + 2. This means the substrate consists of a conventional PCB, one conventional build-up layer on each side of the conventional PCB, and two thin-film metal layers on top of the conventional build-

(a)

Comparisons of (a) conventional build-up FC-PBGA substrate vs. (b) X-LAM thin film.

Figure 8.13

(b)

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(a)

261

(b)

Comparisons of (a) X-LAM thin film vs. (b) conventional build-up at 250- and 500-µm flip chip pad pitch.

Figure 8.14

up layer. Figure 8.16 shows other configurations available in the UltraVia substrates. It can be seen that many thin-film metal layers could be built up on the conventional build-up PCB to increase its wiring density. A typical set of design rules available with UltraVia substrates is shown in Table 8.6. It can be seen that the via diameter, via pitch, line width, and line pitch on the thin-film metal layers can be as low as 30, 68, 18, and 32 to 50 µm, respectively. X-LAM’s technology roadmap is shown in Table 8.7. It can be seen that that the line widths and spacings (L:S) will decrease from L:S of 18:14 µm in 2000 to 8:8 µm in 2004. Also, the UltraVia technology is scalable and allows for future shrinks; escape routing of 10 chip pad rows at 225-µm flip chip pad pitch today will be accomplished at 150 µm in 2002.

TABLE 8.5

Comparisons of Thin-Film vs. Conventional Build-up at 250-mm Flip Chip

Pad Pitch

FC

Pad pitch (µm)

Pad size (µm)

Line width (µm)

Line space (µm)

Number of tracks

X-LAM

250

105

18

14

4

Build-up

250

105

40

40

1

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Chapter Eight

Figure 8.15

Cross section of UltraVia substrate with 2 thin-film metal layers.

(a) Figure 8.16

(b)

(c)

Configurations available in UltraVia substrates.

8.3.2 Process of UltraVia substrates

The processing of X-LAM’s UltraVia technology is carried out on a standard BT resin laminate board. This core laminate may have two (2L) or four build-up copper layers (1 + 2L + 1). The core is supplied with PTHs filled with epoxy, as well as solder-mask-defined (SMD) BGA pads.

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TABLE 8.6

263

X-LAM Design Rule Summary

X-LAM design summary

Dimensions (µm)

Thickness (µm)

Via

30

10–15

Landing pad

54

Line width

18

Line pitch

32 min/50 typical

3.7

Surface pad (Cu/Ni/Au)

3.7/1.3/0.2

Surface passivation (chip side)

Highresolution photosensitive dielectric

Via pitch

8

68

TABLE 8.7

X-LAM Technology Roadmap Year (line width/line spacing/pad size [µm]) 2000 (18/14/52)

2001 (12/12/44)

2002 (10/10/40)

2003 (10/10/40)

2004 (8/8/32)

Flip chip pitch

Top layer

Inner layer

Top layer

Inner layer

Top layer

Inner layer

Top layer

Inner layer

Top layer

Inner layer

250

4

6

5

9

6

11

6

11

8

14

225

4

5

5

8

6

9

6

9

7

12

200

3

5

4

7

5

8

5

8

6

11

175

3

4

4

5

4

7

4

7

5

9

150

2

3

3

4

4

6

4

6

5

7

125

2

2

3

3

3

4

3

4

4

6

100

2

2

2

2

3

3

3

3

3

4

75

1

1

2

1

2

2

2

2

2

3

Figure 8.17 shows the complete processing of a two-thin-film metallayer on top of a two-layer build-up laminate board. Step 1 in Fig. 8.17 shows the laminate before UltraVia processing. In contrast to the traditional two-sided build-up processes, UltraVia substrates are processed on one side only. (In this case, it is on the top side of the

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Figure 8.17

Processing of a two-layer BT board involving deposition of two metal thin-film layers.

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265

substrate). Such single-sided processing is made possible by the thinness of the metal layers, which minimizes the thermal expansion mismatch stresses and the associated warping. On a four-layer board, processing begins with the spin coating of a layer of photoimageable dielectric onto the core. The dielectric, which has a Tg of 220°C and a dielectric constant of 3.3, is used for interlayer electrical insulation and for topmost substrate surface passivation. Vias are created in the dielectric by photolithographic patterning, which involves the selective developing and curing of the dielectric. Upon metallization, the vias provide reliable and precise layer-to-layer connectivity. The metal layers are deposited on the dielectric by a combination of sputtering and pattern plating. Sputtering is used first to generate an adhesion-promoting layer and then to deposit a thin layer of copper. This seed layer of copper is coated with photoresist, which is selectively exposed and developed to leave exposed copper onto which further copper is deposited by electroplating (pattern plating). The photoresist is removed and the unplated seed layer is etched away. A layer of dielectric is then coated followed by another layer of metal in the previously described manner. The top metal layer has a nickel-gold surface finish to promote good intermetallic connection between thin film pads and the eutectic lead-tin solder. Finally, a layer of dielectric is deposited on the surface for passivation purposes. Test vehicles (TVs) have been designed and built around the UltraVia platform as fully testable products. Figure 8.18 shows a 27 × 27mm UltraVia substrate with 675 solder balls distributed in full array at 1-mm pitch (TV3). Figures 8.19 and 8.20 show the cross sections of this substrate supporting a 12 × 12-mm chip with 2180 solder bumps at 200 µm pitch. (In this book, the solders on the chip are called solder bumps and the solders on the substrate are called solder balls.)

Figure 8.18

UltraVia substrate for flip chip applications.

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Chapter Eight

Figure 8.19

SEM micrographs of UltraVia substrate.

8.20 Cross section UltraVia substrate.

Figure

of

8.3.3 Performance of UltraVia substrates

Figure 8.21 shows a schematic cross section of the UltraVia substrate. It can be seen in this substrate that the top two metal layers of the laminate PCB are used for power (CORE-TOP) and ground (M1), and the two thin-film layers (M2 and M3) are used for routing. Note that the thin-film dielectric layers result in a partially planarized structure so that the top surface of the dielectric has a step height of 1.7 µm higher directly over a copper trace than over dielectric. The cross-section shown in Fig. 8.21 is used to calculate the characteristic impedance and cross talk of microstrip lines in the two routing layers M2 and M3. A 3-D electromagnetic, full-wave field solver is used for this purpose. A set of S parameter curves is obtained over a frequency range from the field solver which is converted into an RLGC equivalent circuit or an HSPICE w-element transmission line model.

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Figure 8.21

267

Cross section of the top layers of the substrate.

Since all signals need to pass through power and ground planes to get through the board to the FC-PBGA solder balls, these layers typically will have numerous cutouts at the corresponding PTH locations (approximately 0.4 mm in diameter). All the impedance and cross talk calculations assume that the signal lines do not cross over these openings in the ground plane. These calculations also do not take any line crossings into account. The characteristic impedance and line width data have been plotted in Fig. 8.22. It can be seen that a characteristic impedance of 50 Ω is obtained with a line width of 18 µm (M2) and 36 µm (M3). The corresponding line resistances are 2.85 and 1.43 Ω/cm,

Figure 8.22

Characteristic impedance as a function of different line widths.

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Chapter Eight

respectively. M3 is the preferred routing layer for applications requiring low line resistance. Saturated backward wave cross talk on coupled 50-Ω impedance lines is also modeled. These calculations are used to generate the nearest neighbor cross talk curves as shown in Fig. 8.22 for typical signal rise time of 300 ps and typical coupled lengths of 1 cm. These curves are generated by multiplying the saturated cross talk by the ratio of the coupled length to the “rise length.” Rise length is defined as the product of the signal rise time and the propagation speed of 165 µm/ps. A plot of the cross talk between parallel traces in M2 and M3 assuming a smaller coupled length of 0.1 cm is included in Fig. 8.23. For the rise time and lengths shown in Fig. 8.22, nearest neighbor cross talk can be kept below 1 percent by routing on a 50-µm pitch on M2, or a pitch greater than 75 µm on M3 (contributions from two adjacent lines would double the cross talk to 2 percent). Parallel traces on M2 and M3 that are 0.1 cm long can also result in up to 1 percent cross talk; therefore, it is important to route the design to avoid this as much as possible. We also note that there will typically be additional contributions to cross talk between the flip chip pads to the edge of the chip and from the plated through-holes. X-LAM has been able to route designs with over 800 signals, and on a flip chip pitch of under 200 µm, consistent with the restrictions that no lines cross over openings in the ground plane and that no parallel traces in M2 and M3 exceed 1 mm in length. One of the efficient routing design examples is shown in Fig. 8.24 for TV3.

Figure 8.23

Cross talk as a function of different line pitches.

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Figure 8.24

269

Example of a routing design.

8.3.4 Qualifaction of UltraVia substrates

The UltraVia substrates are presently being qualified by X-LAM. Several TVs have been designed to investigate the reliability of the substrate. TV1 is designed with three metal layers and has been evaluated for thin-film design rules, dielectric materials, and metal adhesion. TV2 is also designed with three metal layers, but is used to test the interaction of thin-metal and dielectric layers with the PCB. In addition, high-frequency electrical measurements are also conducted. TV1 and TV2 show that the insulation resistance between the metal layers and features is greater than 10 MΩ. Via resistance does not appear to change, and the current stress test through the vias shows a current rating of over 1 amp. In process testing of the TVs, a flying probe tester has been employed to check for open and short circuits involving signal, power, and ground connections. TV3 is being tested with and without a lid, as well as in the form of an assembled package mounted on the board. The procedures and criteria used for qualification testing conform to the applicable Joint Electronics Devices Engineering Council (JEDEC) standards. The test methods used to evaluate the qualities of the substrate are summarized in Table 8.8. Preliminary qualification test results are presented in Table 8.9. It can be seen that TV3 passes all the tests.

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Chapter Eight

8.4 Amitec’s High-Density Thin-Film Substrates13–15 By combining thin-film with thick-film build-up technology, Amitec is able to provide a high-performance, cost-effective, and high-density substrate solution for solder-bumped flip chip applications. It is based upon a miniature PCB having an advanced thin-film multilayer structure built on one of its sides. Assembling high-density and fine-pitch solder-bumped flip chips on the thin-film build-up structure and then attaching the other side of the substrate (with solder balls) to a PCB enables redistribution of densities (or pitches) from the “chip world” to

TABLE 8.8

Tests Used in Full Qualification Test type

Conditions

Preconditioning (level 3)

30°C, 60% RH, 192 h, 3× reflow at 220°C

Temperature cycle condition B*

−55–125°C, 1000 cycles

Temperature cycle condition C*

−65–150°C, 500 cycles

Pressure cooker test

121°C, 96 h

Highly Accelerated Stress Test

130°C, 85% RH, 168 h; 6 V

High-temperature storage

150°C, 1000 h

High-temperature operating life*

125°C, 1000 h; 100 mA

* Preconditioning at level 3.

TABLE 8.9

Preliminary TV3 Qualification Test Results Configuration

Fails/sample size

Preconditioning level 3

Die on substrate Flip chip package

0/37 0/37

Thermal shock condition B*

Die on substrate Flip chip package

0/15 0/15

Temperature cycle condition B*

Die on substrate Flip chip package

0/22 0/22

High-temperature storage

Die on substrate Flip chip package

0/15 0/15

Test

* Preconditioning at level 3.

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271

the “PCB world.” In this section the design, process, performance, and reliability of Amitec’s thin-film substrates for FC-PBGA are discussed. 8.4.1 Design of Amitec’s FC-PBGA Substrates Figure 8.25 schematically shows a cross section of a typical FC-PBGA package employing Amitec’s thin-film substrate. A typical set of design parameters (e.g., line width, via size, layer number) available with Amitec’s substrates is shown in Table 8.10. It can be seen that with the thin-film technology, the line width and spacing could be as low as 15 µm. Also, the via diameter could be as low as 10 µm. Certain requirements of the base structure have to be met in order to build the Amitec substrate at high yields and low costs. These are: ■

The base structure has to enable an electrical connection to the “bottom side” (the PBGA solder-ball side) of the substrate while ensuring a smooth and flat surface for thin-film processes implemented on the “top side” of the base structure.

■

The base structure needs to have multilayer metal capabilities and low cost characteristics.

■

The base structure’s temperature and thermal coefficient of expansion characteristics need to comply with the thin-film layers built on top of it.

Figure 8.25

Amitec’s FC-PBGA package.

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Chapter Eight

TABLE 8.10

Characteristic Features of Amitec’s Flip Chip PBGA Substrate Substrate part

Feature Line

Via (filled)

Dielectric

Maximum layers Overall thickness Metal finish

Parameter

Base PWB

Build-up layers

Thickness

10–17 µm

3–5 µm

Minimum line: space

100 µm

15 µm

Thickness

0.82 mm

15 µm

Diameter

0.25 to 0.15 mm

10 µm

Type

Polyimide

BCB

Dielectric constant

4.2

2.7

6

4

2

0.92 mm

0.88 mm

35 µm

BGA and FC pads

Ni/Au electrolytic

Ni/Au electroless

One option to meet these requirements is to use a polyimide/glass PCB (PI-PCB). A rigid multilayer polyimide PCB has a Tg of 260°C, which is above the curing temperature of BCB (250°C), and the right TCE characteristics. Also, the polyimide has excellent adhesion to the BCB. 8.4.2 Process of Amitec’s FC-PBGA substrates

The thin-film multilayer structure is built by using copper traces down to 10 µm in width and space, surrounded by BCB dielectric (made by Dow Chemical). The BCB used is the nonphotosensitive version of the materials with a dielectric constant of 2.7 and high thermal stability (Tg = 350°C). The top masking material defining the flip chip pads is the photosensitive version of the BCB, typically 5 to 7 µm thick and fully compatible with the nonphotosensitive BCB underneath. The photosensitive BCB functions as a high-resolution passivation layer defining flip chip pads down to 25 µm in diameter while allowing additional routing of lines on the external metal layer of the substrate. The exposed copper pads are deposited with Ni-Au to ensure good solderability. In order to interconnect the different levels of the thinfilm copper traces in the z-axis, a novel micro-filled aluminum via (MFAV) technology is used. The use of MFAV allows designs with via diameters down to 10 µm and captures pads down to 20 µm. Via stacking and “via in flip chip pad” structures—enabled by MFAV—improve substrate real estate utilization and overall electrical performance. A typical vertical dielectric spacing between metal layers of 10 to 15 µm is used in order to ensure 50 to 70 transmission lines.

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8.4.3 Performance of Amitec’s FC-PBGA substrates

An electrical performance test vehicle (EPTV) is built using two thinfilm build-up layers over a PI-PCB base structure. The build-up layers consist of microstrip lines (ranging from 20 to 25 µm lines/spaces), microstrip cross talk structures, MFAV chain structures (with via diameters of 10, 20, and 30 µm), capacitors, and inductors. These structures are then measured from 50 MHz to 10.05 GHz and from this data their properties are extracted using the HP MDS software. The test results are reported in Table 8.11. It can be seen that the electrical performance such as the delay, characteristic impedance, and cross talk are adequate. The combined structure (PCB base with thin-film buildup layers) is being used not only to redistribute the chip’s I/Os but to efficiently interconnect the chip to the motherboard. Long and noncritical nets that can be wired in the PCB are structures that will improve thin-film yields. Also, due to the smaller area required for the stacked MFAV structures, greater wiring densities can be achieved. Thus, a larger number of controlled-impedance wiring channels are available. Additionally, there is a significant enhancement of the power distribution system. The power paths associated with the stacked vias are less inductive and therefore are able to support increased switching activities. Also, the voltage drop for each via structure is reduced, providing better electrical interconnection to the chip. 8.4.4 Qualification of Amitec’s FC-PBGA substrates

The qualification test vehicle of the substrates consists of a four-layer polyimide PCB having two thin-film build-ups on the top side (near the flip chip bumps). The build-up layers are designed to close an electrical loop between two isolated PBGA pads on the other (bottom) side of the substrate (near the PBGA solder balls). The bare and diced substrates

TABLE 8.11

Electrical Characterization of Test Vehicle

Electrical parameters Delay Characteristic impedance Loss @ 10 GHz Cross talk Via inductance

Values obtained 130 ps/in. 50–70 Ω <1 dB/cm 3.9% for 20-µm lines and spaces 5.7 pH for 10-µm via diameter

Via capacitance

6.0 fF for 10-µm via diameter

Series resistance

<10 mΩ per via (10-µm diameter)

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TABLE 8.12

Qualification Tests and Results Test parameters

Test designation

JEDEC standard number

Temperature range

Number of cycles or h

Result

22-A106-A

−55 to +125°C

500

Passed

Thermal cycle (air to air)

22-A104-A

−55 to +125°C

500

Passed

High-temperature storage

22-A103-A

150°C

1000

Passed

High-temperature and humidity storage (no bias)

22-A100-A

85°C/85% RH

1000

Passed

Thermal shock (liquid to liquid)

are environmentally stressed by the tests shown in Table 8.12. The substrates are electrically tested at discrete intervals by probing all the PBGA pads. After completion of testing, all substrate are visually inspected and several representative samples are cross-sectioned. Table 8.12 and Fig. 8.26 present test results. It can be seen that all the samples pass all the environmental tests. Also, the average resistances measured at different cycles are quite consistent. Figure 8.27 shows a cross section of a typical two thin-film build-up multilayer structure over a PCB with filled PTH. MFAV with a diameter of 20 µm interconnects the two thinfilm build-up layers. The thin-film dielectric spacing is 10 µm. Figure 8.28 shows the cross section of a 20 µm via interconnecting the copper PCB layer to the first thin-film build-up layer.

Figure 8.26

Via chain resistance.

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Cross section of PCB and thin-film build-up layer.

Figure 8.27

8.5 Microvia-in-Pad Substrate16, 17 As discussed in Chaps. 1 through 7, microvias will save substrate drilling area and increase routing space, which are the basic requirements for solder-bumped flip chip technology. Combined with via-in-pad

Figure 8.28 Cross section of copper PCB layer and interconnecting via.

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(VIP) construction, microvias will save even more. In this section, the design, analysis, assembly, and modeling of a novel micro-VIP (µVIP) substrate for housing a 32-pin static random access memory (SRAM) solder-bumped flip chip in a CSP format are presented. Because of the special design, the substrate consists of a single core of organic material and two metal layers of copper, and is manufactured with the conventional PCB process at very low cost. Furthermore, the vias are drilled with lasers, and thus very small hole size (0.15 to 0.1 mm) can be achieved. 8.5.1 The 32-pin SRAM IC chip

The functional 32-pin SRAM as shown in Figs. 8.29a and 8.29b is designed and manufactured at very high yield and low cost by United Microelectronics Corporation (UMC) on an 8-in. wafer. The major function of this SRAM chip is very high-speed and low-power applications. The major characteristics of the chip for designing the Cu µVIP are listed as follows:

(a)

(a) SRAM chip with solder bumps. (b) Dimensions of the chip.

Figure 8.29

(b)

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■

Chip sizes are 5.334 × 3.662 mm.

■

Pad sizes are 0.075 × 0.075 mm.

■

Pad pitch is 0.195 mm (minimum).

■

Chip thickness is 0.675 mm.

■

Chip pads are distributed on two shorter sides.

■

There are two pads for ground and two pads for power.

277

8.5.2 mVIP substrate

A novel VIP substrate has been designed for the 32-pin SRAM. Figures 8.30a and 8.30b show, respectively, the top and bottom sides of the substrate, which is 0.164-mm-thick BT HL832 organic material with a high glass transition temperature. It can be seen from the top side that the traces from the peripheral pads are redistributed (fanning) inward and

(a)

(a) Top side of the µVIP substrate. (b) Bottom side of the µVIP substrate.

Figure 8.30

(b)

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Chapter Eight

connected to the copper pads on the bottom side of the package substrate through the microvias. The diameter of the microvias is less than 0.15 mm and the diameter of the copper pads is 0.32 mm. The dimensions of the µVIP substrate are 5.5 × 3.8 × 0.164 mm. The microvias are plugged in with nonconductive ink. The pitch of the µVIP is 0.75 mm. The raw material for manufacturing the µVIP substrate is BT HL832, and the core thickness is 0.1 mm. The major process steps are as follows. Step 1. Use mechanical drill to make holes for handling and referencing. Step 2. Apply a 30-µm-thick dry-film photoresist on the Cu and open a 150-µm-diameter circle for the microvia. Step 3. Pre-etch the copper foil at positions where microvias are to be formed. Step 4. Use CO2 laser to drill holes on the BT substrate. Step 5. Electroplate copper to 25 ⫾ 5 µm thick. Step 6. Plug in nonconductive ink (S 500-R01). Step 7. Apply photoresist and circuit layout mask, then use photolithography technique to open the locations of pad, trace, and Cu ring. Step 8. Inspect. Step 9. Print and cure solder mask to 15 +10/−5 µm thick. Step 10. Perform electroless plating. Step 11. Route the large panel to 172 × 60-mm panels. Step 12. Perform final inspection. Figures 8.31a and 8.31b show the top and the bottom sides of the µVIP substrate for the 32-pin solder-bumped flip chip SRAM. Figures 8.31c and 8.31d show cross sections of the µVIP substrate. Figures 8.31e and 8.31f show x-ray images of the µVIPs. It can be seen that, since there are no dog-bone pads, saving space is obvious. Also, since this is a very simple structure, lower cost is expected. 8.5.3 Solder-bumped flip chip on mVIP substrate

The assembly process of µVIP substrate with the 32-pin SRAM chip is very similar to that of the NuCSP reported in Ref. 18, except that in this study solder balls are mounted on the bottom side of the µVIP substrate. Figures 8.32a, 8.32b, and 8.32c show the cross sections of the CSP with the present µVIP substrate. Figure 8.32a shows the cross section along the chip pads. Figure 8.32b shows the cross section along

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(a)

(b)

(c)

(d)

(e)

(f)

279

(a) Top side of the µVIP substrate. (b) Bottom side of the µVIP substrate. (c) Cross section of µVIP. (d) Cross section of µVIP. (e) X-ray image of cross section of µVIP. (f ) Closed-up x-ray image of µVIP.

Figure 8.31

the µVIPs, and Fig. 8.32c shows the schematics. Figures 8.32d and 8.32e show cross sections of the solder-bumped flip chip CSP with µVIP substrate. Figure 8.32f shows the x-ray image, indicating the perfect alignment of the µVIP CSP assembly. Detailed dimensions of the µVIP will be shown in Secs. 8.5.5 and 8.5.6.

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(a)

(c)

(e)

(b)

(d)

(f)

Figure 8.32 The µVIP CSP cross sections (a) along the chip pads, (b) along the µVIP. (c) Schematic of the µVIP solder joint. (d) Cross section of the CSP with µVIP. (e) Cross section of the CSP with µVIP. (f ) X-ray image of the µVIP CSP assembly.

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8.5.4 PCB assembly of the mVIP CSP

The assembly process of the µVIP CSP on the PCB is very similar to that of the conventional no-clean surface mount technology (SMT).18 Figure 8.33a shows the cross sections of the µVIP CSP PCB assembly. Because of the self-alignment characteristic of solder, PCB assembly of the µVIP CSP is very robust and has very high yield. Figure 8.33b shows cross sections of a µVIP CSP PCB assembly with both solder bump on the chip and solder joint on the PCB. 8.5.5 Elastoplastic analysis of mVIP CSP on PCB

Detailed dimensions of the µVIP solder joint are shown in Fig. 8.34. The commercial finite element code ANSYS (version 5.5) is employed

(a) Figure 8.33

Cross sections of the µVIP CSP PCB assembly.

Figure 8.34

Details of the µVIP solder joint.

(b)

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in this study. A two-dimensional model is established using the eightnode plane strain elements. It should be noted that all detailed assembly structures such as the chip, underfill, solder mask, BT substrate, Cu µVIP, solder joint, Cu pads, and FR-4 PCB are modeled in the finite element analysis. Besides, due to the symmetry in the assembly structure, only half of the cross section is considered. 8.5.5.1 Material properties. The material properties used in this computational modeling are shown in Table 8.13. The copper µVIP is considered an elastoplastic material (yield stress = 58.32 MPa, yield strain = 0.0007, Young’s modulus = 76 GPa, and tangent modulus of plastic curve = 7.6 GPa). The eutectic solder (63Sn-37Pb) is assumed to be a temperature-dependent elastoplastic material.18 All other constituents are considered to be linear elastic materials. The thermal loading condition for this study is shown in Fig. 8.35 for the case from 25 to 110°C. 8.5.5.2 Results of elastoplastic analysis. A typical deformation of the µVIP CSP PCB assembly is shown in Fig. 8.36. It can be seen that the maximum relative deformation (dominated by shear) is at the corner µVIP solder joint. This is due to the globe thermal expansion mismatch among the chip-BT substrate and PCB, and to a temperature change of 85°C.

TABLE 8.13

Material Properties of the Assembly Young’s modulus (GPa)

Poisson’s ratio (ν)

Thermal expansion coefficient (α) ppm/°C

FR4 substrate

22

0.28

18.5

Copper

76

0.35

17

63Sn37Pb solder

See note

0.4

21

6

0.35

30

Silicon chip

131

0.3

2.8

Solder mask

6.9

0.35

19

Material properties

Underfill

Microvia filler

7

0.3

35

BT

26

0.39

15

Young’s modulus as well as stress-strain relationships of solder are temperature dependent.

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Figure 8.35

283

Temperature profile for modeling and testing.

The maximum von Mises stress and accumulated equivalent plastic strain range at the corner µVIP solder joint and their contour distributions are shown in Figs. 8.37 and 8.38, respectively. It can be seen that the maximum values in the corner µVIP solder joint are located at the interface between the lower left corner of the µVIP and the solder joint.

Figure 8.36 Deformed shape of the µVIP CSP PCB assembly.

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Figure 8.37

solder joint.

Maximum von Mises stress in the corner µVIP

Maximum equivalent plastic strain in the corner µVIP solder joint.

Figure 8.38

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However, these values are very small compared with those of flip chip on board assembly without underfill or wafer-level CSP.21,22 This is because the thermal expansion mismatch between the FR-4 PCB and the BT substrate is very small. The von Mises stress contour distribution in the µVIP is shown in Fig. 8.39. It can be seen that the maximum von Mises stress appears at the lower left inner corner, and is equal to 75 MPa. This is much smaller than the strength of Cu, which is in the area of 200 MPa. 8.5.6 Creep analysis of mVIP CSP on PCB

In this section, in addition to the elastoplastic strains, the creep strain of the solder joints on PCB is included. The 63Sn-37Pb is assumed to follow the Norton’s steady-state creep law. 8.5.6.1

Material properties. The Norton’s steady-state creep relation18

dγcrp /dt = B*exp{−∆H/kT}τn is used for creep analysis of the solder joints. In this equation, γcrp is the creep shear strain, dγcrp /dt is the creep shear strain rate, τ is the shear stress, ∆H is the activation energy, T is the absolute temperature, k is Boltzmann’s constant (= 8.61 × 10−5 eV/K), and n is the stress exponent. For 63Sn-37Pb eutectic solder, the material constants of the Norton equation are given in Table 4.2 of Ref. 18 as n = 5.25, ∆H = 0.49 eV,

Figure 8.39

µVIP.

von Mises stress (MPa) in the copper

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B* = 0.205 MPa−5.25s − 1, τ is in MPa, and dγcrp /dt is in 1/s. Figure 8.40 shows the Norton constitutive relation of 63Sn-37Pb. In Fig. 8.40, the constitutive relation of the 62Sn36Pb2Ag in terms of the Garofalo steady-state creep law obtained by Darveaux19 is also given. From the comparison, it can be seen that the Norton (obtained by Pao18) and the Garofalo law (obtained by Darveaux19) for the eutectic solders for most of the operating temperatures are very different. For a given steady-state creep strain rate, the Garofalo model yields much higher stress than the Norton model. This is unexpected, since 63Sn-37Pb and 62Sn-36Pb-2Ag are very similar solder alloys. 8.5.6.2 Boundary condition. The temperature loading imposed on the µVIP CSP PCB assembly is shown in Fig. 8.35. It can be seen that for each cycle (60 min) the temperature profile is between −20 and 110°C with 15 min ramp, 20 min hold at hot, and 10 min hold at cold. There are two reasons for choosing this temperature profile: (1) the glass transition temperature of the FR-8.32 PCB is 120°C and we don’t want to introduce additional failure mechanisms of the solder joint due to the degradation of the PCB; and (2) the behavior of solder below −20°C is not very well understood. Three full cycles are executed. 8.5.6.3 Results of creep analysis. The deformed shape is very similar to that in the elastoplastic analysis. Also, the location of the maximum shear stress and creep shear strain hysteresis response is in the corner joint at the interface between the lower left corner of the µVIP and the solder joint. The shear stress and shear creep strain of three cycles at the maxi-

Steady-state creep constitutive relations for the 63Sn-37Pb (Norton creep law) and 62Sn-2Ag-36Pb (Garofalo creep law) solders.

Figure 8.40

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mum location are shown in Figs. 8.41 and 8.42, respectively. Figure 8.43 shows the shear stress and shear creep strain hysteresis loops for multiple cycles. Figure 8.44 shows the time history of creep strain energy density at the µVIP solder joint’s critical location for three cycles. The average creep strain energy density range per cycle ∆W can be obtained by averaging the creep strain energy density of the last two cycles, which is 0.129 N/mm2 = 18.7 psi. As expected, the value of ∆W calculated in this study for the 63Sn-37Pb solder joints based on the Norton model18 is much lower than that for the 62Sn-36Pb-2Ag solder joints (0.189 N/mm2 = 27.4 psi)17 calculated based on the Garofalo model.15

Figure 8.41 Time-dependent shear stress at the corner µVIP solder joint’s critical location.

Figure 8.42 Time-dependent shear creep strain at the corner µVIP solder joint’s critical location.

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Hysteresis loops of the shear stress and shear creep strain at the corner µVIP solder joint’s critical location.

Figure 8.43

Time-dependent creep energy density at the corner µVIP solder joint’s critical location.

Figure 8.44

8.5.6.4 Thermal fatigue life prediction. Once ∆W is obtained, the thermal fatigue crack initiation life No can be estimated from Darveaux’ Eq. (13.35) of Ref. 19, i.e.,

No = 7860∆W−1 = 421 cycles and the thermal fatigue crack propagation life N based on the linear fatigue crack growth rate theory can be estimated by Darveaux’ Eq. (13.36) of Ref. 19, i.e.,

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da/dN = 4.96 × 10−8∆W1.13 or N = No + (af − ao)/(4.96 × 10−8∆W1.13) where a is the crack length of the solder joint; ao is the initial crack length, which is assumed to be zero; and af is the final crack length. It can be seen that in order to determine N we need to choose an af. For example, if af = 0.347 mm (solder cracks through near the bottom of the Cu µVIP), then N = 10,515 cycles. On the other hand, if af = 0.433 mm (solder cracks through the diagonal of µVIP solder joint, i.e., from the corner interface between the lower left corner of the µVIP and the solder joint to the lower right corner interface between the upper right corner of the Cu pad on the PCB and the solder joint), then N = 12,946 cycles. For both cases, the predicted thermal fatigue life with the Norton model for the 63Sn-37Pb solder joint is much larger than that with the Garofalo model for the 62Sn-36Pb-2Ag solder joint. Again, this is due to the large difference in the constitutive values from these two creep models; even these two solders are very similar. It should be pointed out that due to a numerical integration scheme error in the old version of the finite element code ANSYS, Darveaux’ thermal fatigue life prediction equations may involve some errors.20 8.5.7 Summary

A low-cost µVIP substrate for supporting a solder-bumped flip chip in a CSP format has been presented. It is a single-core, two-sided structure with µVIPs to which solder balls are attached. Dog-bone pad structures are not needed and thus there is more space for routing. The application of the µVIP substrate is demonstrated by housing a SRAM device in a CSP format. It is found that the solder-bumped SRAM chip is very easy to assemble on the µVIP substrate, and the solder balls are very easy to mount on the copper µVIP. Also, the µVIP CSP is very easy to assemble on the PCB. The thermal stress in the copper µVIP is calculated by a nonlinear finite element analysis. It is found that the maximum von Mises stress in the copper µVIP is much less than the strength of the copper. Thus, under the thermal cycling condition (25 to 110°C), the copper µVIP should be reliable under most operating conditions. The thermal fatigue life of the µVIP corner solder joint is predicted by a creep analysis based on Norton’s creep law and Darveaux’ empirical equation. It is found that the average creep strain energy density

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is very small in the corner solder joint, and thus the joint can last for a long time. It should be pointed out that the constitutive response of the 63Sn37Pb solder based on the Norton model obtained by Pao is very different from that of the 62Sn-36Pb-2Ag solder based on the Garofalo model obtained by Darveaux. (The Norton model yields a much lower constitutive response.) Consequently, based on Darveaux’s life prediction model, the predicted thermal fatigue life of the corner solder joint from these two creep material models is very different. (The Norton model yields a much larger thermal fatigue life.) 8.6 References 1. Oodaira et al., “Proposed New Method (B2it) for Production of Printed Wiring Boards,” Proceedings of the 9th Circuits Mounting Conference, pp. 55–56, 1996. 2. Lau, J. H., and C. Chang, “An Overview of Microvia Technology,” Circuit World, 26(2):22–32, January 2000. 3. “DNP and Toshiba Establish Joint Venture in Printed Circuit Boards” (Toshiba Press release), 3 October 2000. 4. Goto, K., T. Oguma, and Y. Fukuoka, “High-Density Printed Circuit Board Using B2it™ Technology,” IEEE Transactions on Advanced Packaging, 23(3):447–451, August 2000. 5. Fukuoka, Y., “New B2it™ Method for High-Density Printed Circuit Boards,” Circuit Mounting Society Journal, 475–478, 1998. 6. Fukuoka, Y., et al., “B2it™ Method for Production of Printed Wiring Boards with Interlayer Connection Using Conductive Bumps,” Circuit Mount Technology, 1:65–74, 1997. 7. Takeuchi et al., “High-Density Printed Circuit Board Using Bump Interconnection Technology,” Proceedings of MES’97, pp. 145–148, 1997. 8. H. Yamagata et al., “Development of Enhanced BGA,” Proceedings of MES’98, pp. 133–136, December 1998. 9. Takano, T., J. Nagano, H. Yamagata, M. Ikemizu, and S. Nakao, “Advanced Low Cost Packaging of EP-BGA with B2it,” Proceedings of IEMT/IMC, pp. 101–105, Omiya, Japan, 1999. 10. Smith, L., C. H. Ang, F. Fu, D. Chosnek, and D. Perkins, “Low Cost Few-Chip X-LAM BGA Packages,” Proceedings of the MCM Conference, Denver, CO, April 1999. 11. Strandberg, J., “UltraVia Substrate for Advanced Ball Grid Array Applications,” Connections, 1:42–47, 2000. 12. Chou, W., “High Density Organic Substrates,” Proceedings of HDI Expo, pp. 167–252, Mesa, AZ, August 1999. 13. Hurwitz, D., E. Igner, M. DiOrio, and R. Hilton, “Benefits of a New Thin Film Technology for Flip Chip Substrate Applications,” Proceedings of HDI Expo, pp. 455–461, Mesa, AZ, August 1999. 14. Hurwitz, D., et al., “AMI: A New Thin Film Substrate Technology,” Proceedings of Multichip Modules and High Density Packaging, April 1998. 15. DiOrio, et al., “Advocating a Change in Substrate Technology Manufacturing Methods for Advance IC Packaging Applications,” MEPTEC Newsletter, July 1999. 16. Lau, J. H., S. W. R. Lee, S. Pan, and C. Chang, “Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications,” in Packaging of Electronic and Photonic Devices, ASME Book No. HO1217, pp. 135–144, November 2000. 17. Lau, J. H., C. Chang, S. W. R. Lee, T. Chen, D. Cheng, T. Tseng, and D. Lin, “Design and Manufacturing of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications,” Journal of Electronic Manufacturing, 10(1):79–87, March 2000.

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18. Lau, J. H., and Y. H. Pao, Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies, McGraw-Hill, New York, 1997. 19. Lau, J. H., Ball Grid Array Technology, McGraw-Hill, New York, 1995. 20. Darveaux, R., “Effects of Simulation Methodology on Solder Joint Crack Growth Correlation,” Proceedings of IEEE Electronic Components and Technology Conference, pp. 1048–1058, Las Vegas, NV, May 2000. 21. Lau, J. H., and S. W. R. Lee, Chip Scale Package, McGraw-Hill, New York, 1999. 22. Lau, J. H., Low Cost Flip Chip Technologies, McGraw-Hill, New York, 2000.

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Source: Microvias

Chapter

9 Solders for Next-Generation High-Density Interconnects

9.1 Introduction Solders are the electrical and mechanical “glue” of high-density interconnects. Low-cost tin-lead solders have been used as joining materials in the electronics industry for many years. The unique physical and mechanical properties of tin-lead solders have facilitated PCB assembly choices that have fueled creative advances in packaging developments, such as solder-bumped flip chip, BGA packages, and WLCSP. In the past few years, different bills have been introduced in the U.S. Congress to ban lead from a wide variety of uses, including solders. The reasons are, among others: (1) lead and its compounds are ranked as one of the top 10 hazardous materials, and (2) lead is the number one environmental threat to children. Since then, many major electronics companies, national laboratories, universities, research organizations, and solder vendors worldwide have responded by initiating research programs to eliminate lead from solders. Lead-free solders will be discussed in Sec. 9.4. The trend toward sub-0.18-µm IC feature size and the continuous reliance on lead-bearing solder alloys bring up a new issue—soft error due to alpha particle emission of lead-bearing solders. These alpha particles do not cause permanent physical damage to the chip but are sufficiently energetic to switch the capacitor from 0 to 1 or vice versa, and resulted in so called “soft error.” Alpha particles and related issues will be discussed in Sec. 9.3. Because most of the solder alloys are used at high homologous temperatures, creep deformation plays a very impor-

293

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Chapter Nine

tant role in almost all aspects of their mechanical behavior and it will be discussed next. 9.2 Creep of Solders Some of the electronic interconnection materials such as solders develop strains, in addition to elastic and plastic strains, over long periods of time and are said to creep. Creep is a mathematical model for ratesensitive elastoplastic materials operating at elevated temperatures. Creep strain may be broadly defined as elastoplastic time-dependent deformation under constant load at high temperatures.1–26 Since different materials have different melting temperatures, it is convenient to define a homologous temperature (the ratio of the test or use temperature to the melting temperature on an absolute temperature scale). In general, creep becomes of engineering significance at a homologous temperature greater than 0.5. For some electronic packaging materials, such as solders, creep deformation becomes important even if it is at room temperature. 9.2.1 Creep curves

Figure 9.1 shows a typical family of creep curves that can be obtained from long-time uniaxial tests or shear tests at constant temperature and various stress conditions (σ4 > σ3 > σ2 > σ1). The slope of these curves (dεi/dt = tan Ψi ) is referred to as creep rate. At the first stage, the creep rate is undefined and the initial creep strain consists of either entirely elastic strain or partially elastic strain

Figure 9.1

Strain (ε)-vs.-time (t) creep curves.

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295

and partially plastic strain. During the second stage, the creep rate decreases with time because the effect of strain hardening is greater than that of annealing (recovery). These two effects are in equilibrium (balance) during the third stage and the creep rate reaches an essentially steady state and changes very little with time. However, during the fourth stage, the creep rate increases rapidly with time until fracture occurs. This is because the reduced cross-sectional area (either due to necking or internal void formation) causes an increase in stresses. Andrade’s pioneering work on pure metals has had considerable influence on the thinking on the mechanisms of the second and third stages of creep. Andrade considered the second and third stages of creep as being the superposition of transient creep (with a creep rate decreasing with time) and quasi-viscous creep (with a constant creep rate) processes that occur right after the sudden strain (first stage of creep) that results from applying the load (Fig. 9.1). The second stage of creep is called primary creep. During this period, the primary creep is predominated by transient creep. For low temperatures and stresses, as in the creep of lead at room temperature, primary creep is the predominant creep process. The third stage of creep is called secondary creep or steady-state creep. The average value of the creep rate during secondary creep is called the minimum creep rate. For example, Fig. 9.1 shows the angles Ψ4 > Ψ3 > Ψ2 > Ψ1 of the minimum creep rate at various creep curves. The fourth stage of creep, called tertiary creep, is often associated with microstructure changes such as coarsening of precipitate particles, recrystallization, or diffusional changes in the phases that are present. 9.2.2 Stress-creep strain rate curves

The family of creep curves shown in Fig. 9.1 can be plotted in various ways with certain objectives in mind. Mechanics analysts usually plot the family of creep curves in the following two ways. Figure 9.2 shows the corresponding stresses versus minimum creep rates curve at a constant temperature. This curve can be used as the constitutive relation for steady-state creep analysis of structures at high temperatures. 9.2.3 Isochronous stress-strain curves

Another useful way to plot the family of creep curves (Fig. 9.1) generated at constant temperature and various stress conditions (σ4 > σ3 > σ2 > σ1) is shown in Fig. 9.3. These curves, which relate the stresses and creep strains at selected values of time for a constant temperature, are called isochronous stress-strain curves and can be used as the constitutive relations for creep strain analysis of structures.

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Chapter Nine

Figure 9.2

Stress-strain rate curves.

9.2.4 Common empirical constitutive equations

Some of the commonest empirical uniaxial constitutive equations for describing the second (primary) and third (secondary) stages of creep (Figs. 9.1 though 9.3) are presented. In the broadest sense, the creep strain εc is a function of applied load or stress σ, time t, and temperature T, that is,

Figure 9.3

Isochronous stress-strain curves.

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εc = p(σ, t, T)

297

(9.1)

which is usually assumed to be separable into εc = f (σ)g(t)h(T)

(9.2)

In Eq. (9.2), the stress dependence term has been proposed by Norton, Prandtl, Dorn, and Garofalo as

f (σ) =

冦

Aσn B(σ − F)n C sinh (ασ) D exp(βσ) E[sinh (γσ)]n

Norton Friction stress Prandtl Dorn Garofalo

(9.3) (9.4) (9.5) (9.6) (9.7)

The time dependence term has been proposed by Bailey, Andrade, Graham, and Walles as

g(t) =

冦

t ηtm (1 + ηt1/3)ekt Σ ηitmi

Secondary creep Bailey Andrade Graham and Walles

(9.8) (9.9) (9.10) (9.11)

The temperature dependence term in Eq. (9.2) is usually associated with the Arrhenius law and has the form: h(T) = G exp(−∆H/RT)

(9.12)

In Eq. (9.3) through (9.12), ∆H is the activation energy, R is Boltzmann’s constant, T is the absolute temperature, t is time, and all the remaining symbols other than σ are material constants that can be determined by fitting the creep curves from experiment. It can be seen from Eq. (9.2) to (9.12) that there are many ways to write the creep equation. 9.2.5 Creep constitutive equations of solders under twisting and axial force

For Pb97.5-Sn-2.5, Sn62-Pb36-Ag2, and Sn96.5-Ag3.5 solders, it has been shown by Darveaus and Banerji23 that the Garofalo-Arrhenius creep equation fits very well with the test data (Figs. 9.4, 9.5, and 9.6, respectively). These curves can be used as the constitutive relations for creep analysis of solder interconnects at high temperatures. In this section, the load deformation behavior of twisting T of a thin-

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298

Chapter Nine

Figure 9.4

Constitutive equation of Pb97.5-Sn2.5 solder.

walled circular solder interconnect in the presence of an axial force N as shown in Fig. 9.7 is studied. This kind of specimen (Figs. 9.8 and 9.9) is used for the creep test of solder materials under combined load.24,25 The material is assumed to be incompressible and to follow GarofaloArrhenius creep equation (Sec. 9.2.4). Hencky’s total strain theory is

Figure 9.5

Constitutive equation of Sn62-Pb36-Ag2 solder.

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Figure 9.6

299

Constitutive equation of Sn96.5-Ag3.5 solder.

assumed to be valid. Due to the geometry of the structure and the loading conditions, σr = σθ = τrz = τrθ = d(γrθ)/dt = d(γrz)/dt = 0. It is also assumed that the thickness of the structure is so thin, compared with the inner radius, that all the nonzero stresses are uniformly distributed across the wall thickness.

Figure 9.7 Torsion (T) of thin-walled circular solder cylinder in the presence of axial force (N).

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300

Chapter Nine

Figure 9.8

Thin-walled circular solder cylinder for creep testing.

The Garofalo-Arrhenius creep equation (see Sec. 9.2.4) is generally expressed as dγ G τ ᎏ = C ᎏ sinh ω ᎏ dt ⌰ G

冢 冣冤

冢

冣冥

n

−Q exp ᎏ k⌰

冢 冣

(9.13)

where γ is the shear creep strain dγ/dt is the shear creep strain rate t is the time C is a material constant G is the temperature-dependent shear modulus Θ is the absolute temperature (K) ω defines the stress level at which the power law stress dependence breaks down τ is the shear stress n is the stress exponent Q is the activation energy for a specific diffusion mechanism k is Boltzmann’s constant (8.617 × 10−5 eV/K)

Figure 9.9

Thin-walled circular solder cylinder for creep

testing.

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301

For Pb97.5-Sn2.5, Sn62-Pb36-Ag2, and Sn96.5-Ag3.5 solder alloys, the material constants of Eq. (9.13) have been experimentally determined by Darveaux and Banerji with a single hyperbolic sine function and are shown in Figs. 9.4, 9.5, and 9.6, respectively. By using test data from Ref. 23 on the Pb97.5-Sn2.5 solder alloy, Eq. (9.13) can be written as τ . γ = γo sinh ᎏ τo

冤

冢 冣冥

7

(9.14)

where 1.62 × 107(1140 − Θ) −12765 γo = ᎏᎏᎏ exp ᎏ Θ Θ

冢

冣

(9.15)

and τo = 1710 − 1.5Θ

(9.16)

By using test data from Ref. 23 on the Sn62-Pb36-Ag2 solder alloy, Eq. (9.13) can be written as τ . γ = γo sinh ᎏ τo

冤

冢 冣冥

3.3

(9.17)

where 802(508 − Θ) −6360 γo = ᎏᎏ exp ᎏ Θ Θ

冢

冣

(9.18)

and τo = 3163 − 6.23Θ

(9.19)

Again, by using test data from Ref. 23 on the Sn96.5-Ag3.5 solder alloy, Eq. (9.13) can be written as τ . γ = γo sinh ᎏ τo

冤

冢 冣冥

5.5

(9.20)

where −5802 31(553 − Θ) γo = ᎏᎏ exp ᎏ Θ Θ

冢

冣

(9.21)

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Chapter Nine

and τo = 3687 − 6.67Θ

(9.22)

If the Pb97.5-Sn2.5, Sn62-Pb36-Ag2, and Sn96.5-Ag3.5 solder alloys obey the von Mises criterion, then Eq. (9.14) through (9.16) can be written as (for the Pb97.5-Sn2.5 solder alloy) σ . ε = εo sinh ᎏ σo

冤

冢 冣冥

7

(9.23)

where 1.4 × 107(1140 − Θ) −12765 εo = ᎏᎏᎏ exp ᎏ Θ Θ

冢

冣

(9.24)

and σo = 2962 − 2.6Θ

(9.25)

Similarly, Eq. (9.17) through (9.19) can be written as (for the Sn62Pb36-Ag2 solder alloy) σ . ε = εo sinh ᎏ σo

冤

冢 冣冥

3.3

(9.26)

where 463(508 − Θ) −6360 εo = ᎏᎏ exp ᎏ Θ Θ

冢

冣

(9.27)

and σo = 5478 − 10.79Θ

(9.28)

Also, Eq. (9.20) through (9.22) can be written as (for the Sn96.5Ag3.5 solder alloy) σ . ε = εo sinh ᎏ σo

冤

冢 冣冥

5.5

(9.29)

where −5802 18(553 − Θ) εo = ᎏᎏ exp ᎏ Θ Θ

冢

冣

(9.30)

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303

and σo = 6386 − 11.55Θ

(9.31)

. In Eq. (9.23), (9.26), and (9.29), σ is the uniaxial stress, and ε is the uniaxial creep strain rate. The unit for σ, τ, σo, and τo is lb/in2 (psi), the . . unit for γ and ε is 1/s, and the unit for temperature Θ is degrees Kelvin (K), which is obtained by adding 273.16 to the temperature in degrees Celsius (°C). Equations (9.14), (9.17), (9.20) and (9.23), (9.26), (9.29) can only be applied to, respectively, pure shear and uniaxial tension conditions. For the combined stresses state, it is necessary to define an effective creep . strain rate εe and an effective stress σe as follows . . . 2 εe = 兹苶 ⁄3 εij εij

(9.32)

⁄2 Sij Sij苶 σe = 兹3苶

(9.33)

Sij = σij − 1⁄3σββδij

(9.34)

where

. In Eq. (9.32), εij is the creep strain rate tensor. In Eq. (9.33) and (9.34), Sij is the deviatoric stress tensor, σij is the stress tensor, and δij is the Kronecker delta. Assuming that there exists a universal stressstrain rate curve and it coincides with the uniaxial curves, Eq. (9.23), (9.26), and (9.29), then we have σ . εe = εo sinh ᎏe σo

冤

冢 冣冥

n

(9.35)

which is shown in Fig. 9.10.

Figure 9.10 Stress-strain rate relation for this study.

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Chapter Nine

In view of Fig. 9.4 (Pb97.5-Sn2.5 solder), it can be seen that the power law breaks down at approximately τ/G = 10−3. The stress exponent, n = 7, suggests a dislocation pipe-assisted diffusion deformation mechanism. It occurs by dislocation glide (dislocations moving along slip planes and overcoming barriers by thermal activation) aided by vacancy diffusion. The glide step produces almost all the strain, but the climb step controls the velocity. Since dislocation climb requires diffusion of vacancies or interstitials, the rate-controlling step is atomic diffusion. The activation energy (Q = 1.1 eV) is very close to that of the lattice diffusion in lead (1.1 eV), however, which is somewhat inconsistent with n = 7 for pipe-assisted diffusion (Q = 0.66 eV). In view of Fig. 9.5 (Sn62-Pb36-Ag2 solder), it can be seen that the power law breaks down at approximately τ/G = 10−3. The stress exponent, n = 3.3, indicates a dislocation viscous glide deformation mechanism (which involves dislocations moving along slip planes and overcoming barriers by thermal activation). Due to its stress dependence, the activation energy (Q = 0.548 eV) is somewhat below the expected value of solute interdiffusion. In view of Fig. 9.6 (Sn96.5-Ag3.5 solder), it can be seen that the power law breaks down at approximately τ/G = 10−3. The stress exponent, n = 5.5, indicates a dislocation climb deformation mechanism. It occurs by dislocation glide (dislocations moving along slip planes and overcoming barriers by thermal activation) aided by vacancy diffusion. The glide step produces almost all the strain but the climb step controls the velocity. Since dislocation climb requires diffusion of vacancies or interstitials, the rate-controlling step is atomic diffusion. Due to its stress dependence, the activation energy (Q = 0.5 eV) is somewhat below the expected value of lattice or dislocation pipe diffusion (1.1 and 0.66 eV, respectively). Figure 9.7 shows the thin-walled circular solder cylinder subjected to an axial force N and a twisting moment T. Due to the geometry of the structure and the loading condition, the nonzero stress and strain rate components are σz (normal stress in the z-direction), τθz (shear stress in . the z-direction of the plane normal to the θ-axis), εr (creep normal . strain rate in the r-direction), εθ (creep normal strain rate in the θ. . direction), εz (creep normal strain rate in the z-direction), and γθz (creep shear strain rate in the z-direction of the plane normal to the θ-axis). Consequently, Eq. (9.32) and (9.33) become 兹2 . . 2 . . 2 . . 2 3 .2 苶 . εr − εθ苶 + (εθ苶+ − εz) 苶 (εz −苶 ⁄2 γ zθ εr) + 苶 εe = ᎏ 兹(苶) 3

(9.36)

and

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2 2 σe = 兹σ 苶τ zθ z + 3苶

305

(9.37)

. . Since σr = σθ = 0, then εr = εθ; and since the solder material is assumed . . . to be incompressible, that is, εr + εθ + εz = 0, then we have . . . εr = εθ = −1⁄2 εz

(9.38)

.2 1 . 2 . 苶 εe = 兹ε苶 z + ⁄3γ zθ

(9.39)

Equation (9.36) becomes

Substituting Eq. (9.37) and (9.39) into Eq. (9.35) yields 2 2 .2 1 . 2 兹σ 苶τ zθ z + 3苶 兹ε苶 zθ = εo sinh ᎏᎏ z + ⁄3 γ苶 σo

冤

冢

冣冥

n

(9.40)

For the problem under consideration, the Hencky theory26 simplifies to . . 3εz γzθ ᎏ = ᎏᎏ σz τzθ

(9.41)

By solving Eq. (9.40) and (9.41), we have the following stress distributions σz = βσo sinh−1 (K1/n)

(9.42)

兹1 苶 − β2 τzθ = ᎏ σo sinh−1 (K1/n) 兹3 苶

(9.43)

and

in which . ε K = ᎏe > 0 εo . εz β = ᎏ. ᎏ ≤ 1 εe

(9.44) (9.45)

have been substituted. Thus, the strain rate components can be written as . εz = βKεo

(9.46)

and

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Chapter Nine

. 2 苶β −苶 ) γzθ = Kεo兹3(1

(9.47)

The equilibrium equations for N and T are defined by the relations (Fig. 9.7):

冕 Rhσ dθ

(9.48)

冕 R hτ dθ

(9.49)

N=

2π

z

0

and T=

2π

2

0

zθ

Substituting Eq. (9.42) and (9.43) into Eq. (9.48) and (9.49) yields, respectively N = 2πRhβσo sinh−1 (K1/n)

(9.50)

2 苶 − β2 sinh−1 (K1/n) T = ᎏ πR2hσo兹1 兹3 苶

(9.51)

and

Equations (9.50) and (9.51) are plotted in Fig. 9.11 (for the Pb97.5Sn2.5 solder, n = 7), Fig. 9.12 (for the Sn62-Pb36-Ag2 solder, n = 3.3), and Fig. 9.13 (for the Sn96.5-Ag3.5 solder, n = 5.5) for a wide range of values of β and K that were introduced for the sake of convenience. Thus, for a given temperature Θ and a set of values of twisting moment T and axial force N, the values of β and K can be read from Fig. 9.11, 9.12, or 9.13 (depending on which solder material) and the stresses (σz, . . τzθ) and creep strain rate (εz, γzθ) can be obtained from Eq. (9.42), (9.43), (9.46), and (9.47). The values of εo and σo for the Pb97.5-Sn2.5, Sn62Pb36-Ag2, and Sn96.5-Ag3.5 solders can be obtained from Eq. (9.24), (9.27), (9.30), and (9.25), (9.28), (9.31), respectively. It is noteworthy that curves of constant β are nearly radial lines so that, as long as the ratio of N and T remains constant, each volume element of the solder interconnect can be assumed with negligible error to be subjected to proportional loading (a sufficient condition for the total strain theory coincides with the incremental theory). Similar behavior has been observed by Smith and Sidebottom26 for the case of a solid circular cylinder subjected to tension and twisting moment. Smith and Sidebottom have also shown that the error in using the incompressible solution to predict the behavior of tension-torsion members made of compressible materials is very small. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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307

Dimensionless torsion and axial force interaction curves (Pb97.5-Sn2.5).

Figure 9.11

Dimensionless torsion and axial force interaction curves (Sn62-Pb36-Ag2).

Figure 9.12

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308

Chapter Nine

Dimensionless torsion and axial force interaction curves (Sn96.5-Ag3.5).

Figure 9.13

Considering the geometrically compatible deformation of the cylinder (Fig. 9.7), we have . . . dφ γ zθ = Rϕ = R ᎏ dz

(9.52)

. . in which ϕ is the twist rate per unit length and φ is the total angle of the twist rate. Equations (9.47), (9.51), and (9.52) lead to the twisting moment–twist rate per unit length relation . 2 1 Rϕ 苶 − β2 sinh−1 ᎏ2 ᎏ T = ᎏ πR2hσo兹1 兹3 苶 兹1 苶 − β 兹3 苶εo

冤

冥

1/n

(9.53)

and is plotted in Fig. 9.14 (for the Pb97.5-Sn2.5 solder, n = 7), Fig. 9.15 (for the Sn62-Pb36-Ag2 solder, n = 3.3), and Fig. 9.16 (for the Sn96.5Ag3.5 solder, n = 5.5). Thus, for a given Θ, N, and T, we can read the value of β from Fig. 9.11, 9.12, or 9.13 (depending on which solder mate. rial is used) and then read the value of ϕ from Fig. 9.14, 9.15, or 9.16 with β and T known.

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309

Twisting moment vs. twist rate per unit length (Pb97.5-Sn2.5).

Figure 9.14

Figure 9.15 Twisting moment vs. twist rate per unit length (Sn62-Pb36-Ag2).

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310

Chapter Nine

Figure 9.16

Twisting moment vs. twist rate per unit length (Sn96.5-

Ag3.5).

9.2.6 Torsion of thick-walled circular solder interconnects

Figure 9.17 shows a thick-walled hollow circular cylinder made of Pb97.5-Sn2.5, Sn62-Pb36-Ag2, and Sn96.5-Ag3.5 solders subjected to a twisting moment T. The inner and outer radii of the cylinder are labeled a and b, respectively. For a solid cylinder, a = 0. Due to the geometry of the cylinder and the loading condition, the only nonzero . stress is τzθ and the only nonzero strain rate is γzθ. In this case, Eq. (9.14), (9.17), or (9.20) can be used directly and written as . γ zθ τzθ = τo sinh−1 ᎏ γo

冢 冣

1/n

(9.54)

As in the previous case, by considering the geometrically compatible deformation of the cylinder (Fig. 9.17), we have . . dφ . γ zθ = Rϕ = R ᎏ dz

(9.55)

. . in which ϕ is the twist rate per unit length and φ is the total angle of twist rate. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Figure 9.17

311

Torsion of a thick-walled circular solder column.

Substituting Eq. (9.55) into Eq. (9.54) yields the shear stress distribution through the wall thickness . r bϕ τzθ = τo sinh−1 ᎏ ᎏ b γo

冢

冣

1/n

(9.56)

The twisting moment T equilibrium equation is defined by (Fig. 9.17) T=

冕 冕 τ r dθdr b 2π

a 0

zθ

2

(9.57)

Substituting Eq. (9.56) into Eq. (9.57) yields T = 2πτob3

.

bϕ 冕 sinh 冢ξ ᎏ γ 冣 1

−1

α

1/n

ξ2dξ

(9.58)

o

where a α=ᎏ b

(9.59)

r ξ=ᎏ b

(9.60)

and

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Chapter Nine

Equation 9.58 is plotted in Fig. 9.18 (for the Pb97.5-Sn2.5 solder, n = 7), Fig. 9.19 (for the Sn62-Pb36-Ag2 solder, n = 3.3), and Fig. 9.20 (for the Sn96.5-Ag3.5 solder, n = 5.5) for the case of a solid solder column . (α = 0). Thus, for a given Θ and T, the twist rate per unit length ϕ can be obtained from Fig. 9.18, 9.19, or 9.20 (depending on the solder material) and the stress distribution through the wall thickness is given by Eq. (9.56). The values of γo and τo for the Pb97.5-Sn2.5, Sn62-Pb36-Ag2, and Sn96.5-Ag3.5 solders can be obtained from Eq. (9.15), (9.18), (9.21), and (9.16), (9.19), (9.22), respectively. For design purposes, sometimes it is convenient to introduce to nondimensional “shear stress ratio” λ defined by τmax λ=ᎏ τo

(9.61)

in which . bϕ τmax = τo sinh−1 ᎏ γo

冢 冣

1/n

(9.62)

Twisting moments vs. twist rate per unit length of a solder column (Pb97.5-Sn2.5).

Figure 9.18

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313

Twisting moments vs. twist rate per unit length of a solder column (Sn62-Pb36-Ag2).

Figure 9.19

Figure 9.20 Twisting moments vs. twist rate per unit length of a solder column (Sn96.5-Ag3.5).

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314

Chapter Nine

is the largest stress that occurs at the exterior surface of the solder cylinder. Substituting Eq. (9.61) and (9.62) into Eq. (9.56) yields the shear stress distribution in terms of λ τzθ = τo sinh−1

冤冢ᎏb 冣 r

1/n

冥

sinh λ

(9.63)

Substituting Eq. (9.63) into Eq. (9.57), we have T = 2πτob3

冕 sinh 1

α

−1

(ξ1/n sinh λ) ξ2dξ

(9.64)

which is plotted in Fig. 9.21 (for the Pb97.5-Sn2.5 solder, n = 7), Fig. 9.22 (for the Sn62-Pb36-Ag2 solder, n = 3.3), and Fig. 9.23 (for the Sn96.5-Ag3.5 solder, n = 5.5) for convenience’s sake (α = 0). Thus, for a given Θ and maximum allowable shear strength, and the radius of a solder column, the allowable applied twisting moment can be determined from Fig. 9.18, 9.19, or 9.20 (depending on which solder material is used).

Figure 9.21

Twisting moment vs. shear stress ratio (Pb97.5-

Sn2.5).

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Figure 9.22

315

Twisting moment vs. shear stress ratio (Sn62-Pb36-

Ag2).

Figure 9.23

Twisting moment vs. shear stress ratio (Sn96.5-Ag3.5).

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316

Chapter Nine

9.2.7 Bending of thick-walled circular solder interconnects

Figure 9.24 shows a thick-walled hollow circular cylinder made of Pb97.5-Sn2.5, Sn62-Pb36-Ag2, and Sn96.5-Ag3.5 solders subjected to a bending moment M. The inner and outer radii of the cylinder are labeled a and b, respectively. Due to the geometry of the cylinder and the loading condition, the only nonzero stress is σz and the only . nonzero strain rate is εz. In this case, Eq. (9.23), (9.26), and (9.29) have to be used and can be written as .ε σz = σo sinh−1 ᎏz εo

冢 冣

1/n

(9.65)

Considering the geometrically compatible deformation of the cylinder (Fig. 9.24), we have y . εz = ᎏ . ρ

(9.66)

. in which ρ is the bending curvature rate (Fig. 9.24). Substituting Eq. (9.66) into Eq. (9.65) yields the bending stress distribution through the wall thickness

冢 冣

y σz = σo sinh−1 ᎏ . εoρ

Figure 9.24

1/n

(9.67)

Bending of a thick-walled circular solder column.

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317

The bending moment M equilibrium equation is defined by (Fig. 9.24) M=4

冕 σ ydA + 4 冕 σ ydA a

0

b

z

(9.68)

z

a

Substituting Eq. (9.67) into Eq. (9.68) yields M = 4σob3

b − ζ sinh 冢ζ ᎏ . 冤冕 ζ 兹1苶 ε ρ冣 1

2

1/n

−1

0

dζ

o

−

b 冕 ζ 兹α苶 − ζ苶 sinh 冢ζ ᎏ . ε ρ冣 α

2

2

0

1/n

−1

o

冥

dζ

(9.69)

where y ζ=ᎏ b

(9.70)

a α=ᎏ b

(9.71)

2 2 苶 − y2 − 兹a 苶 − y2苶) dy. . . . .0 ≤ |y| ≤ a dA = (兹b

(9.72)

2 dA = 兹b 苶. − y2 . . . .a ≤ |y| ≤ b

(9.73)

and

have been substituted. Equation 9.69 is plotted in Fig. 9.25 (for the Pb97.5-Sn2.5 solder, n = 7), Fig. 9.26 (for the Sn62-Pb36-Ag2 solder, n = 3.3), and Fig. 9.27 (for the Sn96.5-Ag3.5 solder, n = 5.5) for a solid solder column. Thus, for a given temperature Θ and a moment M the cur. vature rate (ρ) can be read from Fig. 9.25, 9.26, or 9.27 (depending on which solder material is used) and the stresses distribution can be obtained from Eq. (9.67). The values of εo and σo for the Pb97.5-Sn2.5, Sn62-Pb36-Ag2, and Sn96.5-Ag3.5 solders can be obtained from Eq. (9.24), (9.27), (9.30), and (9.25), (9.28), (9.31), respectively. For design purposes, sometimes it is convenient to introduce to nondimensional “bending stress ratio” µ defined by σmax µ=ᎏ σo

(9.74)

in which

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318

Chapter Nine

Figure 9.25

Bending moment vs. curvature creep rate (Pb97.5-

Sn2.5).

Figure 9.26

Bending moment vs. curvature creep rate (Sn62-

Pb36-Ag2). Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Figure 9.27

319

Bending moment vs. curvature creep rate (Sn96.5-

Ag3.5).

冢 冣

b σmax = σo sinh−1 ᎏ. εoρ

1/n

(9.75)

is the largest bending stress that occurs at the exterior surface of the solder cylinder. Substituting Eq. (9.74) and (9.75) into Eq. (9.67) yields the bending stress distribution in terms of µ σz = σo sinh−1

冤冢 冣 r ᎏ b

1/n

sinh µ

冥

(9.76)

Substituting Eq. (9.76) into Eq. (9.69), we have M = 4σob3

− ζ sinh 冤冕 ζ 兹1苶 1

2

−1

0

−

(ζ1/n sinh µ) dζ

冕 ζ 兹α苶 − ζ苶 sinh α

0

2

2

−1

(ζ1/n sinh µ) dζ

冥

(9.77)

which is plotted in Fig. 9.28 (for the Pb97.5-Sn2.5 solder, n = 7), Fig. 9.29 (for the Sn62-Pb36-Ag2 solder, n = 3.3), and Fig. 9.30 (for the Sn96.5-Ag3.5 solder, n = 5.5) for a solid solder column. Thus, for a given Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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320

Chapter Nine

Θ, M, and a maximum allowable tensile strength of the solder σmax, the radius of the solder column b can be designed by reading the value of M/2πσob3 from Fig. 9.28, 9.29, or 9.30. 9.2.8 Summary

An exact creep analysis has been presented for (1) the twisting of a thin-walled circular solder cylinder in the presence of axial force, (2) the torsion of a thick-walled circular solder interconnect, and (3) the bending of a thick-walled circular solder column. The solder alloys are Pb97.5-Sn2.5, Sn62-Pb36-Ag2, and Sn96.5-Ag3.5 and obey the Garofalo-Arrhenius constitutive equation. Results have been presented in the form of equations and dimensionless charts. The use of these equations and charts has been shown for determining the shear and normal stress and creep shear and normal strain rate distributions in the solder interconnects. Also, the resultant axial force, bending moment, twisting moment, twist rate, and curvature rate acting on the solder interconnects are presented. The results presented herein can be used to interpret the test data of solders and to verify the finite element procedures for creep analyses. Also, it should be useful for studying the solder joint creep behavior of the ceramic column grid array package.27

Figure 9.28

Bending moment vs. bending stress ratio (Pb97.5-Sn2.5).

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Figure 9.29

321

Bending moment vs. bending stress ratio (Sn62-

Pb36-Ag2).

Figure 9.30

Bending moment vs. bending stress ratio (Sn96.5-

Ag3.5). Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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322

Chapter Nine

9.3 Low-Alpha-Bearing Solders Since the effect of alpha particles was first recognized by Intel in 1978, it has become well known that alpha particles from thorium and uranium impurities in packaging raw materials such as lead-bearing solder alloys do not cause permanent damage to the chip but are sufficiently energetic to produce soft errors (data loss)—random, nonrecurring single-bit errors.28,29 Alpha particles produce soft errors by penetrating through the lead-bearing solder joint, under-bump metallurgy (UBM), Al pad, passivation, silicon, and pn junction and generating carriers as a result of giving up kinetic energy as they slow down. The carriers generated by alpha penetration through the junction distort the electric field and also generate charges. In this section, some basic physics of soft errors and alpha particle emissions are discussed. Also, the sources, prices, and current usage of low-alpha-bearing solders are presented. 9.3.1 Soft error

Soft errors induced by alpha particles can be a reliability concern for microelectronics, especially semiconductor memory devices. The soft errors are (1) reversible and not associated with any permanent damage to the device, and (2) completely removed on the next write cycle, with the affected bits being no more susceptible to failure than any other bit in the device. Alpha particle radiation is the most common cause of soft errors in memory devices. The primary source of alpha particles in semiconduc237 tor devices is the decay chains of uranium (238 92 U), thorium (90 Th), polo212 210 210 nium (84 Po), and lead isotopes (82 Pb and 82Pb), which are present in trace amounts in the electronic packaging materials. The trend toward increased chip density, lower power supply voltages, and smaller device dimensions further increases the susceptibility of many devices to soft errors. Also, soft errors can be caused by cosmic rays at sea level or higher. If the material is very hot (i.e., emits many alpha particles), soft errors will be very significant. 9.3.2 Alpha particle emissions

The alpha particles are doubly charged helium nuclei containing two protons and two electrons. They are released from high-atomic-number atoms during radioactive decay and then interact with other atoms due to their charge and high energy. The energy range of alpha particles emitted from all naturally occurring elements that undergo alpha decay ranges from 1 to 9 MeV.28–30 Alpha particles released from the decay of 238U and 232Th in packaging materials can penetrate into silicon devices.

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323

U has a radioactivity of 6.85 × 10−7 C/g.31,32 The decay of 238U to stable Pb produces eight alpha particles with energies ranging from 4.15 to 7.69 MeV.33,34 Alpha particles having this energy can travel 10 to 25 µm in alumina substrates that have a density of 3.85 g/cm.35 These high-energy alpha particles can travel up to 50 µm in silicon substrates that have a density of 2.3 g/cm3. 232 Th has a radioactivity of 1.1 × 10−7 C/g.31,32 The decay of 232Th to sta206 ble Pb produces six alpha particles with energies ranging from 3.95 to 8.8 MeV.33,34 Alpha particles having this energy can travel 9 to 31 µm in alumina substrates and can travel up to 50 µm in silicon substrates. The soft errors caused by the emission of alpha particles from packaging materials are due to the generation of electron-hole pairs. Highenergy alpha particles passing through the silicon device can generate up to 2.5 × 106 electron-hole pairs in several picoseconds.28 The number of electron-hole pairs produced depends on the energy of the emitted alpha particles and the density of the material. The amount of energy required to produce an electron-hole pair in silicon is 3.6 eV.31 Figure 9.31 shows the effect of an alpha-particle-generated electron-hole pair on a silicon device.28 For example, in n-channel metal-oxide semiconductor (MOS) memory devices, the charge carriers are electronic and the capacitors are potential wells in p-type silicon. Alpha particles emitted from trace levels of uranium and thorium in the packaging materials can penetrate the surface of the semiconductor device. As the alpha particle passes through the semiconductor device, electrons are dislodged from the crystal lattice sites along the track of the alpha particle. If the total number of generated electrons collected by an empty storage well exceeds the number of electrons that differentiates between a 1 and a 0, the collected electron charge can flip a 1 to a 0, generating a soft error in the semiconductor device. Alpha particle levels are reported as alpha activity or as alpha flux. Alpha activity is defined as the alpha particle disintegration rate per unit weight of the material—usually reported in pC/g (picocuries per gram). Alpha flux is defined as the rate (per time unit and per area unit) of alpha emissions from the surface of a material—usually reported in particles per hour per cm2. Alpha flux is the more common method of reporting alpha particle content. As a rule of thumb, an alpha flux of 1 alpha/(h⋅cm2) corresponds to ∼1 ppm of 238U in the material.35 The relationship between the 238U concentration and the alpha flux in ceramic (or other packaging materials) is shown as follows, based on the assumptions that (1) all of the decay isotopes of 238U have the same radioactivity as the parent 238U; (2) 25 percent of the generated alpha particles escape from the ceramic; and (3) the alpha particles travel 14.3 µm: 238

206

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324

Chapter Nine

(a) Figure 9.31

Effects of an alpha particle.

Alpha flux = 1 ppm 238U/(g of ceramic) × 3.85 (g of ceramic)/(cm3 of ceramic) × 10−6 (g of 238U)/(ppm 238U) × 6.85 × 10−7 C/(g of 238U) × 2.2 × 1012 disintegrations/(min-C) × 8 alpha particle/(238U disintegration) × 14.3 µm {average alpha particle travel} × 0.25 {escape factor} = 0.996 alpha particle/(h-cm2)

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325

(b) Figure 9.31

(Continued)

In memory devices, data are stored as the presence or absence of charge carriers in storage wells. The amount of charge typically stored in a potential well ranges from 0.3 × 106 to 3 × 106 electrons.28 However, the susceptibility of a memory device to soft errors does not depend primarily on the total stored charge but on the critical charge (the number of electrons that differentiates a 1 and a 0). When the number of electrons generated by an alpha particle and collected by a storage well exceeds the critical charge, a soft error occurs. Critical charge is the most important gauge of alpha particle sensitivity and soft error rates (SER) in memory devices.28 If a device has the critical charge larger than 2.5 × 106 electrons, soft errors are not generated by alpha particle emissions because naturally occurring alpha particles do not have enough energy to generate enough electronhole pairs. For critical charges less than 0.05 × 106, practically all alpha particle emissions result in soft errors. In the region between these two extremes, other factors such as cell geometry, collection efficiency,

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326

Chapter Nine

alpha particle flux, and critical charge determine the SER in memory devices. 9.3.3 Alpha particle sources from solders

Lead-bearing solders have been identified as the primary source of alpha particles, as demonstrated by a study done at the Microelectronics Center of North Carolina (MCNC) (see Table 9.1)36 where the alpha emission was monitored step by step along with the waferbumping process. The radioactivity of lead can be traced back to 238U. Starting from 238 U, it decays into 210Pb, which further decays into Bi in 22 years, then to Po, then to 206Pb in 138 days as shown in Fig. 9.32. Besides alpha emission, the decay process also involves beta particle (electron) emission. The beta particle has no impact on soft error. The content of uranium in natural sources of lead differs by as much as three orders of magnitude. During the smelting and chemical purification process, although other elements may be removed, the radioactive 210Pb gets concentrated together with nonradioactive 206Pb, due to the same chemical nature of both lead isotopes. Lead having alpha activity as high as 100 alpha/(cm2⋅h) for secular equilibrium can be reached within 8 to 9 mo after smelting and purification. The following decay chain illustrates the birth of an alpha particle −1 −1 4 Pb ⇒ 210 ⇒ 210 ⇒ 206 83Bi + β 84Po + β 82Pb + 2α

210 82

9.3.4 Protection against alpha particle emission

Most of the elements involved in major viable lead-free alternatives such as Sn, In, Ag, and Cu are all considered safe, and hence pose no concerns about alpha particle emission in the coming lead-free era. However, Bi may be an issue, primarily due to the existence of radioactive 214Bi, which will eventually convert into stable 206Pb by going through three beta decays and two alpha decays in about 24 years. The primary concern about alpha particle emission is still associated with lead. For most of the flip chip applications, the challenge of soft error persists due to the continuous dependence on lead-bearing solders, especially the Pb95-Sn5. Although gold-wire bonding is still widely used on chips including DRAM and SRAM, solder-bumped flip chip is gradually applied to DRAM and SRAM devices. At the same time, in some other devices, particularly logic (ASIC) and microprocessor chips, solder-bumped flip chips become an indispensable option. Thus, the trend toward higher I/Os and performance prompts the

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α counts / time (α / h)

104 / 23.49 68 / 23.25 102 / 25.85 2718 / 44.88

Si Si + BCB Si + BCB + UBM Si + BCB + UBM + PbSn

Background rate (α / h) 4.03 ⫾ 0.41 4.03 ⫾ 0.41 4.07 ⫾ 0.42 4.07 ⫾ 0.42

Gross α / time (α / h) 4.43 ⫾ 0.43 2.92 ⫾ 0.35 3.95 ⫾ 0.39 60.56 ⫾ 1.16

Baseline Alpha Measurements for MCNC’s Standard Solder-Bumping Process

Material

TABLE 9.1

710 ⫾ 71 900 ⫾ 90 900 ⫾ 90 335 ⫾ 34

Sample area (cm2)

0.7 ⫾ 1.0 −1.5 ⫾ 0.7 −0.2 ⫾ 0.7 198.4 ⫾ 15.1

Corrected activity (0.001 α/cm2 h)

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327

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328

Chapter Nine

Natural decay chain from 238U to Equilibrium, Pure Technologies Literature.)

Figure 9.32

206

Pb. (Source: Peter Bokhan, Secular

urgency of solving alpha particle emission problems.37 The most pressing concern is alleviating soft errors in larger systems, such as servers, that run on multiple processors and use large banks of DRAMs. Solutions may include increasing the size of the nodes. Although this will raise the level of the charge needed to touch off a false switch, thus reducing the chance of soft error, power consumption will rise.38 The alpha particle produced by the decay of 210Po (which comes from 210 Pb by two beta decays) has an energy of 5.4 MeV. Since there is considerable variation in travel distance, the range of the alpha particle

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TABLE 9.2

Estimated Ranges for Alpha Particles in Common Materials Material

Range (µm)

Si Pb Al Cu Polyimide Au Resist Air

23.6 11.5 19.5 7.9 28 6.6 24 47,000 (4.7 cm)

can be specified with high accuracy. Table 9.2 shows the calculated ranges for the alpha particles produced by 210Po going through common materials. Although an alpha particle cannot pass through a 25-µm bump of solder, it can penetrate 25 µm of an Si layer.37 In addition, it can also easily pass through thin-metal films and many tens of micrometers of organic materials.37 For flip chip applications, lead is close to IC, and it needs 25 to 50 µm of polyimide passivation. For flip chip bipolar devices, there is substantial alpha particle release from glass frit. To protect the IC, 50 to 75 µm of silicone gel is used by IBM to keep alpha particles from reaching ceramic sources. For those designs, the I/O count is low, and solder bumps can be put at the perimeter of the chip; therefore it is acceptable for memory chips. However, for logic devices (ASIC), there is a very high I/O count, and the solder bumps have to be placed virtually everywhere on the IC surface.39 In this case, a low-alpha-particle-emission solder will be required. For wafer-level packages, such as WLCSP, the concerns about alpha particle emission due to solder interconnects are quite similar to those for flip chip packages, due to the proximity of solder bumps to ICs. 9.3.5 Sources of low-alpha lead-bearing solders37

Low-alpha leads can be obtained from several sources, including: (1) “cold” lead ore; (2) the laser isotope separation process; and (3) antique lead. Lead is extracted from lead sulfide ore. Some ores are colder (less alpha particle emission) than others. Current mines in operation yield materials with surface activity rates between 0.05 and 70.0 count/ cm2⋅h. Typical lead alpha particle emission rates are about 10 to 100 count/cm2⋅h. Some suppliers, such as Johnson Matthey, have found sources of lead ore with low alpha particle emission. The radiations of those ores are rated as LC1 (low count class 1), with alpha particle emission rates of 0.2 to 0.5 count/cm2⋅h, and as LC2 (0.05 count/cm2⋅h).

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Chapter Nine

Cosmic ray has an alpha particle emission rate of ∼0.005 count/cm2⋅h and is considered LC3. The second low-alpha lead source is laser isotope separation technology. This technology, developed in Russia, uses laser radiation to vaporize the lead. The foundation for laser purification (isotope separation), as noted by Pure Technologies, is the capability of laser radiation to select specific frequencies (energies) from substances with great accuracy. All basic substances are formed from atoms. Atoms carry their own specific frequencies (energies), which may be specifically “excited” by specially tuned laser radiation. Laser radiation targeted at a specific frequency causes electrons in this frequency to selectively ionize, or become charged. These selectively charged atom particles are then separable and removable. Undesirable particles may, therefore, be removed, thereby cleansing the basic substances. This technology reduces 210Pb concentration by 10 to 100 times by means of one stage of isotope separation, and is claimed to be able to get the alpha activity down to less than 0.001 count/cm2⋅h. If the consumption rate of lowalpha lead exceeds the natural regeneration rate of natural low-alpha lead, this separation technology may eventually be the long-term source of low-alpha lead. The third low-alpha lead source is through sea salvage companies, such as Aloveo and Sea Recovery Ltd. (SRL). In many sunken ships, lead is used to clad holes to avoid barnacle formation underwater. In this lead, after it has sat on the ocean for 500 years, most of the 210Pb has already turned into very cold 206Pb through natural decay. Thus, there is no alpha particle emission concern. A lot of lead materials in sunken ships have been located. The 206Pb left on the ships can be purified for reclassification processing. About 600 tons of lead have been identified or located. The price is not very expensive, and the rating is about LC3.37 The alpha particle emission rate is even as low as 0.0002 count/cm2⋅h, according to the SRL data.37 Another source for antique lead is through recovering the old lead used for water pipes in ancient Roman cities or the old lead used in some old buildings, such as lead on the roofs of old churches in the U.K. There is at least one company, AFAIR, that offers to reroof old churches free provided the company can keep the old lead it removes.37 The limited quantity of antique lead suggests that this source may only be temporary. 9.3.6 Price of low-alpha lead-bearing solders37

Low-alpha lead is considerably more expensive than regular lead, which is about $0.30/lb. At this stage, the price of low-alpha lead may

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331

vary significantly from vendor to vendor. The price range for low-alpha lead is detailed in Table 9.3, based on the listed prices of several vendors. Unless otherwise specified, the price in Table 9.3 refers to that of lead itself. For the LC3 class, antique lead seems to be cheaper than lead produced by laser isotope separation. 9.3.7 Current usage of low-alpha lead-bearing solders

Many companies, such as Intel, IBM, Delco, and Solectron, use lowalpha lead-bearing solders for advanced microprocessors and ASICs. Compaq also uses low-alpha lead-bearing solder for the Alpha chips. Commodity products do not need low-alpha lead-bearing solders at this stage. However, deep submicron (0.25 or 0.18 µm) applications will definitely have more need for low-alpha lead-bearing solders. The semiconductor industry is currently using solders with alpha particle emission levels ranging between 0.05 and 0.01 count/cm2⋅h (LC2 level). With increasing I/O density, decreasing power supply voltage, and further miniaturization of the IC devices, the requirement for alpha particle emission level may soon move to the LC3 level.37 Flip chip volume worldwide is expected to be 2514 million units by 2002, with a calculated annual growth rate of 34.62 percent.39 Assuming the average I/O of flip chip is 100, with each solder bump being 10 mil in diameter, and assuming the use of solder alloy Sn63-Pb37, the quantity of lead needed will be 6.2 metric tons. Obviously this is very likely the high end of low-alpha lead consumption needed for waferlevel interconnects, and appears to be well within the reach of the lowalpha lead supply.37

TABLE 9.3

Prices of Low-Alpha Lead-Bearing Solders

Alpha emission rate (count/cm2⋅h) <0.5 <0.05 <0.02 <0.01 <0.01 <0.005 <0.002 <0.001 <0.0006

Product type

Price ($/lb)

Ingot Ingot Sn63, type 5 and type 6 powder Ingot Sn63, type 5 and type 6 powder Ingot Ingot Ingot Ingot

10 50–150 1050–4050

LC1 LC2 LC2

90–190 1140–4400

LC2 LC2

220–360 80–150 310–500 680–1150

Note

LC3 LC3, old Pb LC3 LC3

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Chapter Nine

9.4 Lead-Free Solders Lead poisoning has been well recognized as a health threat. The majority of lead produced worldwide is used for storage batteries, as shown in Table 9.4.40 Since the batteries are almost 100 percent recycled, they are not considered an environmental issue. Of the 5 million tons of lead produced annually, only about 0.5 percent is used in electronic solder applications. However, this small amount of lead in solder poses more concern for human health than the lead in storage batteries. This is due to the fact that, although solder is only a small percentage by weight of electronic products (televisions, refrigerators, personal computers, phones, etc.), these pieces of equipment often end up in landfills after being disposed, and the lead could be leached out into the water supply. A recent study41 demonstrates that the lead leached out from solder can be several hundred times higher than the limit. This concern about polluting the groundwater is essentially driving the whole world to launch a quest for lead-free soldering.42 9.4.1 Global efforts

In 1998 the European Union (EU) introduced a draft directive (law) called the Waste from Electrical and Electronic Equipment (WEEE) Directive. The WEEE Directive calls for a ban on lead in all electronics (except automotive) by January 1, 2004. The WEEE Directive is

TABLE 9.4

Lead Consumption by Product Product

Storage batteries

Consumption (%) 80.81

Other oxides (paint, glass and ceramic products, pigments, chemicals)

4.78

Ammunition

4.69

Sheet lead

1.79

Cable covering

1.10

Casting metals

1.13

Brass and bronze billets and ingots

0.72

Pipes, traps, other extruded products

0.72

Solder (excluding electronic solder)

0.70

Electronic solder

0.49

Miscellaneous

2.77

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intended to ban the selling and/or import of electrical/electronic equipment containing lead interconnect. The move toward Pb-free products raised the attention of some major manufacturers. Nortel Networks is one of the lead-free pioneers in Europe. The company initiated a leadfree program in 1991, selected Sn99.3-Cu0.7 in 1994, built 500 leadfree phones in 1998, and targeted meeting the second WEEE Directive in 2001.43 In Japan, on January 30, 1998, the Japanese Electronic Industry Development Association (JEIDA) and the Japanese Institute of Electronics Packaging (JIEP) presented a lead-free roadmap. In view of the inevitable trend toward a green world, some major Japanese OEMs begin to jointly develop recycling processes for electronic products. A number of major Japanese companies have made commitments to go lead-free by 2001 in their products. This is in advance of Japanese legislation on “take-back” due to come into force in April 2001, and will allow the Japanese to be positioned to exclude from Japan products that do not meet these environmental standards. Obviously, the aggressive move of the Japanese manufacturers will justify European legislation requiring Pb reduction and highly recyclable electronic products by 2004,9 and therefore further increase the pressure on the rest of the world to convert to Pb-free products. Recently, EU has postponed Pb elimination to 2008. In the U.S., lead-free soldering has been a forgotten issue since the initial interest in the early 1990s. Now, the message from both shores is loud and clear: you either work on lead-free soldering now, or you can forget about doing business. Hence, NEMI reinitiated activity in February 1999, and has been coordinating the efforts of U.S. industry to find viable solutions for lead-free soldering. IPC also organized a conference IPC Works ’99, which was held in October 1999 at Minneapolis with major emphasis on the Pb-free issue. Overall, the U.S. industry is trying to catch up with offshore lead-free activity. 9.4.2 Viable lead-free solder alloys

The following alloys are considered representative of viable candidates for replacing the eutectic Sn-Pb system. Many of the systems are based on adding small quantities of third or fourth elements to binary alloy systems in order to lower the melting point and increase the wetting and reliability. 9.4.2.1 Sn96.5-Ag3.5. Sn96.5-Ag3.5 (221°C) is one of most promising alloys, used by NCMS, Ford, Motorola, and TI Japan. German studies suggested it to be one of the most suitable alloys. There is a long experience of using this alloy. Indium Corp. reported this alloy to have the poorest wetting for reflow soldering among high-Sn alloys.37,42,44

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Chapter Nine

Sn99.3-Cu0.7. Sn99.3-Cu0.7 (227°C) is reported by Nortel to have soldering quality equal to that of eutectic Sn-Pb in telephone manufacturing. In air reflow, the wettability is reduced and the fillet exhibits a rough and textured appearance. Sn99.3-Cu0.7 is probably the poorest in mechanical properties of all available Pb-free solders. It is recommended by NEMI for wave soldering.37

9.4.2.2

9.4.2.3 Sn-Ag-Cu. A ternary eutectic at 217°C, its exact composition is likely to be in the range Sn-Ag(3.5 to 3.8)-Cu(0.7 to 1). Cu is added to Sn-Ag in order to slow the Cu dissolution, lower the melting temperature, and improve wettability, creep, and thermal fatigue characteristics. Nokia and Multicore find yields and reliability comparable to or better than those of eutectic Sn-Pb alloy. The Brite-Euram Project reported better reliability and solderability than those of Sn-Ag and Sn-Cu, and recommended this alloy for general purpose use. ITRI Limited (International Tin Research Institute, U.K.) recommends alloys within the compositional range of Sn-Ag(3.4 to 4.1)-Cu(0.45 to 0.9) as the general replacement for Sn-Pb. NEMI recommends Sn95.5-Ag3.9Cu0.6 for reflow applications.37 Some other specific compositions of interest include: ■

Sn95-Ag4.0-Cu1 (217 to 219°C, AMES Labs, covers any alloy containing 3.5 percent to 7.7 percent Ag and 1 percent to 4 percent Cu)

■

Sn95.5-Ag4.0-Cu0.5 (217 to 219°C, published 50 years ago; unpatentable)

■

Sn95.5-Ag3.8-Cu0.7 (217 to 219°C, unpatented)

■

Sn96.3-Ag3.2-Cu0.5 (217 to 218°C, unpatented)

■

Sn95.75-Ag3.5-Cu0.75 (Senju)

9.4.2.4 Sn-Ag-Cu-X. Sn96.2-Ag2.5-Cu0.8-Sb0.5 (213 to 218°C, AIM, Castin Alloy) is reported by International Tin Research Institute, Lucent Technologies, Ford, and Sandia Labs to have greater fatigue performance than eutectic Sn-Pb alloy. The Brite-Euram Project reported that addition of 0.5 percent Sb may strengthen the alloy further. Sn-Ag-Cu-In (Tamura) may also be promising. 9.4.2.5 Sn-Ag-Bi-X. Addition of ≤5 percent Bi lowers the melting point and improves wettability of Sn-Ag systems. Solderability is the best among a range of Pb-free alloys, confirmed by Indium Corp.44 and Matsushita. Addition of Cu and/or Ge results in strength improvement, and possibly wettability improvement. However, adding Pb to Sn-Bi alloys can cause a 96°C ternary eutectic Bi52-Pb32-Sn16 to form; hence Sn-Pb surface finishes should be avoided. The Japan Electronic

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Industry Promotion Association recommended both Sn-Ag-Cu and SnAg-Bi. Some examples are shown in the following list. ■

Sn91.8-Ag3.4-Bi4.8 (202 to 215°C, Sandia Labs): Considered by the National Center for Manufacturing Sciences (NCMS), along with eutectic Sn-Ag and eutectic Sn-Bi, the most promising alloys

■

Sn93.5-Ag3.5-Bi3 (210 to 217°C, Nihon Handa)

■

Sn90.5-Bi7.5-Ag2 (191 to 210°C, Tamura Kaken)

■

Sn-Ag-Bi (Matsushita)

■

Sn94-Ag3-Bi3 (213°C)

■

Sn92-Ag3-Bi5 (210°C)

■

Sn92.7-Ag3.2-Bi3-Cu1.1-Ge (Japan Solder)

■

Sn93-Ag3.5-Bi0.5-In3 (Harima, Mitsui Metals)

Sn-Sb. Sn95-Sb5 (232 to 240°C) has poor wetting (although better than Sn96.5-Ag3.5), and liquidus temperature is too high.

9.4.2.6

9.4.2.7 Sn-Zn-X. Sn91-Zn9 (eutectic 199°C) is fairly reactive, since Zn causes oxidation and corrosion. Japanese home electronics manufacturers are interested in Sn89-Zn8-Bi3. Bi replaces Zn to reduce the Zn corrosion in humid conditions. Sn-Zn-Bi alloys can have melting points close to that of eutectic Sn-Pb. Sn-Zn-Bi alloys were developed primarily by home electronics manufacturers targeting low-cost products. ■

Sn90-Zn9-In1 (AT&T)

■

Sn89-Zn8-Bi3 (191 to 195°C, Matsushita, Senju)

■

Sn-Zn-Bi-X (Hitachi Harima, Tamura)

9.4.2.8 Sn-Bi. Bi58-Sn42 (138°C) is recommended by NCMS as a promising replacement. Eutectic Bi58-Sn42 is unusually resistant to coarsening. It is reported by HP to have properties better than or equivalent to those of eutectic Sn-Pb. Sn-Bi is promising for low-temperature applications or some consumer products. Addition of 1 percent Cu dramatically slows coarsening of eutectic Sn-Bi. The concerns are: (1) eutectic Bi52-Pb32-Sn16 (96°C) is formed on Pb surface finishes, and (2) Bi is a by-product of Pb mining. 9.4.2.9 Sn-In-Ag-(X). Here X represents either no addition or a small amount of a quaternary element. Indium Corporation has developed Sn-In-Ag alloy systems,45,46 with composition ranges of Sn(71.5 to 91.9)-In(4.8 to 25.9)-Ag(2.6 to 3.3). Within this family, but with a slight

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Chapter Nine

variation, LF-1 (Sn85.9-In10-Ag3.1-Cu1) by Delphi Delco Electronic Systems47 has been reported to be promising for flip chip bonding applications.48 A recent work by Indium Corporation rated the compatibility of the major viable lead-free solders with reflow process,44 with results summarized in Fig. 9.33. Compatibility of those alloys with a variety of representative flux chemistries is considered essential, and is determined for performance in handling ability (including shelf life and tack time), and, more importantly, soldering capability (including solder balling, wetting, and solder joint appearance). Results indicate that the control Sn63-Pb37 is still the most compatible alloy, rated 27.1 in compatibility out of a full scale of 30 when using warm profile. The primary factor that distinguishes Sn63-Pb37 from the rest of the alloys is the soldering performance, particularly wetting and solder appearance. As to solder balling, although Sn63-Pb37 is also the best, it is fairly close to the best lead-free systems. Among the lead-free options, both of the Sn-Ag-Bi alloys studied here (Sn91.7-Ag3.5-Bi4.8 and Sn90.5-Bi7.5-Ag2) turn out to be at the top of the lead-free systems, rated 22.9 and 22.8, respectively. This is mainly attributed to the better wetting and solder balling performance. Shelf lives and tack times for the Sn-Ag-Bi systems are also fairly good, while the solder appearance is at best considered average.

Compatibility of lead-free solder alloys with reflow process. (A higher compatibility value represents a better compatibility.)

Figure 9.33

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The six alloys (Sn99.3-Cu0.7, Sn95.5-Ag3.8-Cu0.7, Sn93.6-Ag4.7Cu1.7, Sn96.2-Ag2.5-Cu0.8-Sb0.5, Bi58-Sn42, and Sn95-Sb5) show fairly comparable performance, with compatibility ranging from 19.3 to 20.3. In general, the whole group displays a quite noticeably poorer wetting than Sn-Ag-Bi systems. Bi58-Sn42 exhibits a fairly poor solder balling performance, but an outstanding solder appearance among leadfree systems. Sn96.2-Ag2.5-Cu0.8-Sb0.5 shows a relatively poor performance in both wetting and solder appearance among these six alloys. Sn96.5-Ag3.5, rated 17.1 in compatibility, is ranked below the other alloys described, mainly due to poor solder balling performance, and particularly poor wetting. Sn89-Zn8-Bi3, rated only 2.2 in compatibility, falls far short in every category when compared with all other alloy systems. Obviously, this is attributable to the very reactive nature of zinc, which results in excessive oxidation of metal and excessive reaction with fluxes, and consequently a definitely unacceptable performance for solder paste applications. High-tin-content lead-free alloys seem to display a thicker intermetallic layer than eutectic Sn-Pb when reflowed. NEMI recommends Sn95.5-Ag3.9-Cu0.6 for reflow soldering and Sn99.3-Cu0.7 for wave soldering.37 The preference for Sn-Ag-Cu systems over Sn-Ag-Bi is primarily based on concerns about lead contamination, which can cause a 96°C ternary eutectic Bi52-Pb32-Sn16 to form. Table 9.5 shows some of the leading replacement candidates for lead solder and their users. Tables 9.6 and 9.7 show the pros and cons of some

TABLE 9.5

The Top Lead-Free Solder Alloys Alloy

Melting point

User

Sn99.3-Cu0.7

227°C

Nortel (N2 wave and reflow)

Sn96.5-Ag3.5

221°C

NCMS, Ford, Motorola, TI Japan

Sn95.5-Ag3.8-Cu0.7 Sn-Ag-Cu

217–219°C 217°C

Motorola, Nokia GEC Marconi

Sn97.25-Ag2-Cu0.75

217–219°C

Sn91.8-Ag3.4-Bi4.8

205–210°C

NCMS, Sandia Labs

Sn91.75-Ag3.5-Bi5-Cu0.7

210–215°C

Hitachi

Sn94.25-Ag2-Bi3-Cu0.75

210–215°C

NEC

Sn90.5-Ag3.5-Bi3

220°C

Sn42.9-Bi57-Ag0.1

138–140°C

NEC

Matsushita/Panasonic Fujitsu

Sn93.4-Ag2-Bi4-Cu0.5-Ge0.1

216°C

Sony

Sn-Ag-Cu-Sb

217°C

Texas Instruments

Sn89-Zn8-Bi3

191°C

Matsushita, Senju, NEC

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TABLE 9.6

Pros and Cons of Some Lead-Free Solders

Composition

Advantages

Disadvantages

Sn63-Pb37

Overall good properties, low cost

Structural coarsening; prone to creep

Au80-Sn20

Creep and corrosion resistance

Hard and brittle; melting point too high; expensive

Bi60-Cd40

Toxic

Bi67-In33

Poor wetting on Cu

Bi57-In26-Sn17 Bi58-Sn42

Melting point too low Good fluidity

Strain rate sensitivity; poor wetting

Creep and fatigue resistance

Developmental stage

Bi95-Sn5 Bi54.5-Sn43-Fe2.5 Bi56-Sn42-In2 Bi95-Sb5 In97-Ag3

Poor wetting; expensive

In90-Ag10 In48.8-Bi31.6-Sn19.6 In51.0-Bi32.5-Sn16.5 In60-Sn40 In52-Sn48

Au soldering

Melting point too low; poor fatigue and mechanical properties; expensive

100Sn

Wetting

Whisker and tin pest growth

Sn96.5-Ag3.5

Good strength; creep resistance

Poor isothermal fatigue at low strain; melting point slightly too high

Sn95-Ag5

No coarsening

In50-Sn50

Sn93.6-Ag4.7-Cu1.7 Sn96.2-Ag2.5-Cu0.8-Sb0.5 Sn65-Ag25-Sb10

Slightly high melting point High strength

Expensive; melting point too high

Sn95.5-Ag3.5-Zn1.0

Good mechanical strength

Slightly high melting point

Sn95-Ag3.5-Zn1.0-Cu0.5

Good ductility

Slightly high melting point

Sn91.8-Bi4.8-Ag3.4 Sn48-Bi46-Cu4-Ag2 Bi(0.08–20)-Cu(0.02–1.5)-Ag (0.01–1.5)-P(0–0.20)-rare earth mixture (0–0.20)-balance Sn

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TABLE 9.6

339

Pros and Cons of Some Lead-Free Solders (Continued)

Composition

Advantages

Disadvantages

Sn91.0-Bi4.5-Ag3.5-Cu1.0 Sn67.8-Cd32.2 Sn99.3-Cu0.7

Toxic Fatigue resistance

Sn99-Cu1 Sn97-Cu3 Sn95.5-Cu4-Ag0.5

Melting range too wide and too high

Sn95.5-Cu3-Sb1-Ag0.5

Melting point too high

Sn70-In30

Poor creep

Sn58-In42 Sn77.2-In20.0-Ag2.8

Creep resistance; virtual drop-in replacement

Slightly expensive

High strength

Melting point too high

Sn80-In10-Bi9.5-Ag0.5

Creep and fatigue resistance

Slightly expensive

Sn95-Sb5

Creep resistance; good high-temperature shear; mechanical strength

Melting point too high

Good strength; abundance

Poor corrosion resistance and wetting; high drossing

Sn88.5-In10.0-Ag1.0-Sb0.5 Sn90-In8-Bi2 Sn80-In10-Bi10 Sn78.4-In9.8-Bi9.8-Ag2

Sn(∼90–95)-Sb(3–5)-Bi(1–4.5)Ag(0.1–0.5) Sn91-Zn9 Sn87-Zn8-In5

Poor wetting; eutectic In52Sn46-Zn2 (106°C) a concern

Sn87-Zn8-In5-Ag0.1 Sn87-Zn8-In5-Cu0.1

lead-free solders and their manufacturers or investigators.37,42,44 Tables 9.8 and 9.9 show the estimated costs of some lead-free solder materials. Table 9.10 shows the relevant lead-free solder patents. Tables 9.11 and 9.12 show the reflow temperature ranges of some lead-free solders.37,42,44 More information can be found at the Web site of Indium Corporation of America. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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TABLE 9.7

Chapter Nine

Lead-Free Solder Alloys Recently Manufactured or Investigated

Alloy category

Composition

Solidus (°C)

Liquidus (°C)

Note

Density

Manufacturer or investigator

Sn-Pb

Sn63-Pb37

183

183

Eutectic

8.40

Au-Sn

Au80-Sn20

280

280

Eutectic

14.51

Bi-Cd

Bi60-Cd40

144

144

Eutectic

9.31

Indium

Bi-In

Bi67-In33

109

109

Eutectic

8.81

Indium

Bi-In-Sn

Bi57-In26-Sn17

79

79

Eutectic

Bi-Sn

Bi58-Sn42

138

138

Eutectic

Bi95-Sn5

134

251

(Control)

8.56 9.64

Indium

Bi-Sn-Fe

Bi54.5-Sn43-Fe2.5

137

AT&T

Bi-Sn-In

Bi56-Sn42-In2

138

IBM

Bi-Sb

Bi95-Sb5

∼308

Ford

In-Ag

In-Bi-Sn

In-Sn

Sn Sn-Ag

∼275

In97-Ag3

143

143

In90-Ag10

141

237

Eutectic

7.38

Indium

7.54

Indium

7.88

Indium

In48.8-Bi31.6-Sn19.6

59

59

Eutectic?

In51.0-Bi32.5-Sn16.5

60

60

Eutectic

In60-Sn40

118

∼127

In52-Sn48

118

118

7.30

Indium

In50-Sn50

118

125

7.30

Indium

100Sn

232

232

7.28

Indium

7.36

Indium

Sn96.5-Ag3.5

221

221

Sn95-Ag5

221

∼250

Eutectic

Eutectic

Sn-Ag-Cu

Sn93.6-Ag4.7-Cu1.7

216

216

Sn-Ag-Cu-Sb

Sn96.2-Ag2.5Cu0.8-Sb0.5

210

217

Eutectic

AIM (CASTIN)

Iowa State U

Sn-Ag-Sb

Sn65-Ag25-Sb10

233

Motorola

Sn-Ag-Zn

Sn95.5-Ag3.5-Zn1.0

217

Sn-Ag-Zn-Cu

Sn95-Ag3.5Zn1.0-Cu0.5

Sn-Bi-Ag

Sn91.8-Bi4.8-Ag3.4

211

Sandia

Sn-Bi-Ag-Cu

Sn91.0-Bi4.5Ag3.5-Cu1.0

210

Senju

Sn-Bi-Cu-Ag

Sn48-Bi46Cu4-Ag2

IBM

Sn-Bi-Cu-Ag-P

Bi(0.08–20)Cu(0.02–1.5)-Ag (0.01–1.5)-P(0–0.20)rare earth mixture(0–0.20)balance Sn

Cookson

Sn-Cd

Sn67.8-Cd32.2

AT&T AT&T

177

177

Eutectic

7.68

Indium

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TABLE 9.7 Alloy category Sn-Cu

Lead-Free Solder Alloys Recently Manufactured or Investigated (Continued) Composition

Solidus (°C)

Liquidus (°C)

Sn99.3-Cu0.7

227

227

Sn99-Cu1

227

227

Sn97-Cu3

227

∼330

Sn-Cu-Ag

Sn95.5-Cu4-Ag0.5

225

349 (260)

Sn-Cu-Sb-Ag

Sn95.5-Cu3Sb1-Ag0.5

Sn-In

Sn70-In30

120

∼175

Note

Density

Manufacturer or investigator

Eutectic Ford Engelhard (Silvabrite 100)

256

Motorola

Sn58-In42

118

145

7.30

Indium

Sn-In-Ag

Sn77.2-In20.0Ag2.8

175

187

7.25

Indium

Sn-In-Ag-Sb

Sn88.5-In10.0Ag1.0-Sb0.5

Sn-In-Bi

211

Qualitek

153

199

IBM

179

201

Ford

∼234

240

Motorola

Sn90-In8-Bi2 Sn80-In10-Bi10

Sn-In-Bi-Ag

341

IBM

Sn78.4-In9.8Bi9.8-Ag2 Sn80-In10Bi9.5-Ag0.5

Sn-Sb

Sn95-Sb5

Sn-Sb-Bi-Ag

Sn(∼90–95)-Sb(3–5)Bi(1–4.5)-Ag(0.1–0.5)

Sn-Zn

Sn91-Zn9

199

199

Sn-Zn-In

Sn87-Zn8-In5

175

188

Sn-Zn-In-Ag

Sn87-Zn8In5-Ag0.1

AT&T

Sn-Zn-In-Cu

Sn87-Zn8In5-Cu0.1

AT&T

Willard Industries Eutectic

7.27

Indium AT&T

9.4.3 Lead-free solders for wafer-level packaging

For wafer-level area-array interconnect options, several systems are commonly in use, including metal studs, polymer bumps, conductive particles, and solder bumps. Among these, the solder bump interconnect approach is the most popular choice, due to convenience, cost, and reliability considerations. Depending on applications, the conventional solder alloys used for solder bumping include high-melting-temperature solders, such as Pb97-Sn3 (316 to 321°C) and Pb95-Sn5 (308 to 312°C), and medium-melting-temperature solders, such as Sn60-Pb40 (183 to 191°C), Sn63-Pb37 (183°C), and Sn62.5-Pb36.1-Ag1.4 (179°C).

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TABLE 9.8

Relative Costs of Lead-Free Solders

Solder alloy

Bar relative cost ($/kg)

Paste relative cost ($/kg)

Sn63-Pb37

1

1

Sn96.5-Ag3.5

2.29

1.07

Sn95-Ag3-Bi2

2.17

1.06

Sn96.1-Ag2.6-Cu0.8-Sb0.5

2.06

1.05

Sn91.8-Ag3.4-Bi4.8

2.26

1.06

Sn95-Ag3.5-Cu0.5-Zn1

2.27

1.06

Sn93.6-Ag4.7-Cu1.7

2.56

1.08

Sn96.1-Ag3.2-Cu0.7

2.21

1.06

Sn95.2-Ag3.5-Cu1.3

2.28

1.06

Relative cost of selected metals: Pb 1, Zn 1.7, Cu 3, Sb 3.9, Bi 8.6, Sn 11, Ag 260, Au 15,000

The changeover to lead-free solders is not an easy route for waferlevel interconnects. For medium-melting-temperature solders, there is no drop-in replacement with a comparable melting temperature in the first place. Virtually all of the viable alternatives exhibit melting temperatures at least 10°C higher, and mostly 20 or 30°C higher, than those of the current solders in use. The higher melting temperature directly poses a concern about compatibility with the substrate and packaging materials associated with wafer-level interconnects, mainly due to thermal damage considerations. On top of the challenge to thermal performance imposed by the higher melting temperature, the TABLE 9.9

Estimated Costs of Lead-Free Solders Based on Metal Prices Alone Alloy

Metal cost

Sn63-Pb37

$1.61/lb

Sn96.5-Ag3.5

$4.90/lb

Sn96-Ag3.5-Bi5

$4.96/lb

Sn94-Ag3-Bi3

$4.58/lb

Sn95.5-Ag4-Cu0.5

$5.24/lb

Sn99.3-Cu0.3

$2.41/lb

Sn96.7-Ag2-Cu0.8-Sb0.5

$3.82/lb

Sn89-Zn8-Bi8

$2.32/lb

Sn42-Bi58

$3.11/lb

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Pending

08-132277

08-206874

4,778,733

5,527,628

08-215880

05-050286

Japan

Japan

USA

USA

Japan

Japan

* Add Cu 0.1–3 or Zn 0.1–15.

4,879,096

USA

Patent number

Senju/Matsushita

Ishikawa Kinzoku

Iowa State University; Sandia

Engelhard Corporation

Matsushita

Ishikawa Kinzoku

Kester Solder

Oatey Company

Assigned to

Relevant Lead-Free Solder Patents

USA

Country

TABLE 9.10

Balance

Balance

Balance

92–99

Balance

Balance

90–93.5

88–99.35

Sn

3.0–5

0.5–3.5

3.5–7.7

0.05–3

0.1–20

1.0–3

2.0–5

0.05–3

Ag 0.1–3

0.5–3

0.5–2.0

1.0–4.0

0.7–6

0.5–2

0–5

0.0–10.0

0.1–25*

1.0–10

0.5–7

0.5–6 0.3–2

Bi

Cu

0–5

Sb

0.0–1.0

Zn

0.1–20*

In

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Chapter Nine

TABLE 9.11

Recommended Reflow Temperatures for Sn-Ag-Cu Solder Alloys

Composition

Alloys

Sn96.5-Ag3.5 Sn99.3-Cu0.7 Sn93.6-Ag4.7-Cu1.7 Sn95-Ag4.0-Cu1 Sn96.5-Ag3.0-Cu0.5 Sn95.5-Ag4.0-Cu0.5 Sn95.5-Ag3.8-Cu0.7 Sn95.75-Ag3.5-Cu0.75

Tin/silver Tin/copper Tin-silver-copper Tin-silver-copper Tin-silver-copper Tin-silver-copper Tin-silver-copper Tin-silver-copper

Liquidus temperature Reflow temperature 221°C 227°C 216°C 218°C 218°C 218°C 218°C 218°C

240–250°C 245–255°C 237–247°C 238–248°C 238–248°C 238–248°C 238–248°C 238–248°C

majority of the lead-free soldering exploratory work focuses on the conventional surface-mount board-level assembly. As a result, few or no data have been reported on the performance of area-array packages, including BGA, CSP, and flip chip applications. A recent study by Flip Chip Technologies/Delphi Delco Electronic Systems48 indicates that the reliability of simple binary lead-free solder alloys, such as Sn96.5-Ag3.5 or Sn95-Sb5, is typically 30 to 60 percent that of Sn63-Pb37 solder in nonunderfilled applications. Other lead-free alloys promising in SMT applications also display a thermal cycle fatigue resistance inferior to that of eutectic Sn-Pb bumps. For instance, the value for Sn96.2-Ag2.5-Cu0.8/Sb0.5 is about 80 percent that for Sn63-Pb37. On the other hand, Indalloy 227 (Sn77.2-In20Ag2.8) results in a premature deterioration of the UBM due to the presence of a low-temperature Sn-In eutectic phase at around 115°C. The same study reported that a new alloy, LF-1 (Sn85.9-In10-Ag3.1Cu1), developed by Delphi Delco, exhibits a reliability about 1.5 times better than that of Sn63-Pb37 for nonunderfilled systems that have been thermally cycled from −50 to 150°C. For an underfilled flip chip system thermally cycled from −40 to 125°C, a similar reliability improvement of 1.5 to 2.0 times is observed. This profound improve-

TABLE 9.12

Recommended Reflow Temperatures for Sn-Ag-Cu-X Solder Alloys

Composition

Alloys

Liquidus temperature

Reflow temperature

Sn96.2-Ag2.5-Cu0.8-Sb0.5 Sn97-Cu2-Sb0.8-Ag0.2 Sn91.8-Ag3.4-Bi4.8 Sn93.5-Ag3.5-Bi3 Sn90.5-Bi7.5-Ag2 Sn94-Ag3-Bi3 Sn92-Ag3-Bi5 Sn92.7-Ag3.2-Bi3-Cu1.1 Sn93-Ag3.5-Bi0.5-In3

Tin-silver-copper-antimony Tin-copper-antimony-silver Tin-silver-bismuth Tin-silver-bismuth Tin-bismuth-silver Tin-silver-bismuth Tin-silver-bismuth Tin-silver-bismuth-copper Tin-silver-bismuth-indium

213°C 226°C 205°C 210°C 191°C 213°C 210°C 210°C 210°C

233–243°C 246–256°C 225–235°C 230–240°C 220–230°C 233–243°C 230–240°C 230–240°C 230–240°C

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ment in reliability is attributed to the lack of 115°C eutectic Sn-In phase in LF-1 when compared with Indalloy 227. Delphi Delco reported that this lack of 115°C Sn-In eutectic phase is caused by the combined effect of (1) addition of Cu and (2) reduction of In content from 20 percent to 10 percent.47 These results definitely suggest that the Sn85.9-In10-Ag3.1-Cu1 alloy is very promising for wafer-level interconnects. The need for In in this composition also strongly suggests that the soft nature of In is indispensable for high-reliability area-array interconnect applications. A careful study by the Indium Corporation indicates that the potentially viable alloys for wafer-level interconnect as well as for BGA and CSP solder bumping may have much more variety than is initially apparent. Figures 9.34 through 9.37 show the differential scanning calorimeter (DSC) data for Sn76.2-In20-Ag2.8-Cu1, Sn77.2-In20-Ag2.8 (Indalloy 227), Sn85.9-In10-Ag3.1/Cu1 (LF-1), and Sn86.9-In10-Ag3.1 (Indalloy 254), respectively. Comparison of these DSC data indicates that the presence or disappearance of the 113°C low-temperature eutectic Sn-In phase is dictated by the content of In only. Thus, at 20 percent In (Figs. 9.34 and 9.35), the 113°C peak exists, with or without Cu addition. At 10 percent In (Figs. 9.36 and 9.37), no 113°C peak can be discerned, with or without Cu addition. As a matter of fact, additional data indicate that the lack of impact on low-temperature phase by Cu presence holds true for Sn-In-Ag-(X) systems with In content up to at least about 50 percent. Although Cu has nothing to do with the critical low-temperature Sn-In phase, addition of Cu does slightly reduce the melting temperature of alloys by 1 to 3°C.

Figure 9.34

DSC curve of Sn76.2-In20-Ag2.8-Cu1 solder

alloy.

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Chapter Nine

Figure 9.35

DSC curve of Sn77.2-In20-Ag2.8 solder alloy.

These findings indicate that virtually the whole Sn-In-Ag-(X) family could be promising, as long as the In content is low enough (10 percent, and no more than 15 percent). The system may be further optimized for a wider processing window or better reliability performance by (1) adjusting the In content for further lowering the melting temperature and (2) introducing a quaternary element, possibly Cu, Ni, etc., for the possibility of modulating the metallurgical grain structure. On the other hand, for high-temperature solder replacement, no valid Pb-free alternative has been identified as of today. According to Ref. 37, alloys other than high Pb, such as high Sn, Sn63, or Pb50/In50—which IBM has tried earlier—all have problems related to thermal migration, electromigration, lack of compliance, low thermal cycle fatigue

Figure 9.36 DSC curve of Sn85.9-In10-Ag3.1-Cu1 solder alloy (LF-1).

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Figure 9.37

347

DSC curve of Sn86.9-In10-Ag3.1 solder

alloy.

performance, or higher reactivity. They can react with UBM or crack the die. 100In or 100Pb exhibits better performance in this regard. For UBM, although Ni can reduce the reaction with solder, it has its own problem due to stress under the bump. Since the early 1990s, IBM has tried to find alternative lead-free solders for Pb95-Sn5 C4 (controlledcollapse chip connection) applications, and still has no answers. 100Sn is not a viable solution. First of all, Sn is not quite compliant. The thermal cycle fatigue is acceptable, but the thermal migration of tin poses a problem. IBM scientists have demonstrated that a big ∆T (100 to 200°F, created by using torch at one side, liquid nitrogen at the other side) across a solder joint can create voids in the solder joint due to thermal migration. The metal migrated (solid-state diffusion) from the cold side to the hot side, and created microvoids at the cold side. This is similar to the electromigration effect caused by electrical current (Fig. 38). When passing current through and generating ∆T across the solder joint, voids can be formed. Besides the issues just discussed, solder extrusion can also be an issue, as shown in Fig. 9.38. The solder-bumped WLCSP process is sometimes followed with an underfill process. If the alloy used for the solder bumps remelts during a subsequent assembly process, it can behave like millboard. The molten solder will deform to fill the vacancy, extrude around the polymeric underfill, and eventually cause circuit shorts, as demonstrated in Fig. 9.38. Thus, this essentially rules out the possibility of using solders that will remelt during the subsequent assembly process. Since the surface-mount assembly process very likely will move toward lead-free solders such as Sn-Ag-Cu or Sn-Ag-Bi systems with melting temperatures around 210 to 220°C, the solder used for flip chip will have to exhibit a melting temperature above the high end of the process temperature (approximately 260°C). At this Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Chapter Nine

(a)

(b)

Popcorning led to solder migration into the die-underfill interface and into underfill voids.38 (a) Normal underfilled flip chip. (b) Popcorn delaminated assembly with solder extruded through the delaminated area.

Figure 9.38

stage, lead-free solders meeting this temperature requirement are very limited, including Sn20-Au80 (280°C), Au88-Ge12 (356°C), and Au96.76Si3.24 (363°C). Unfortunately, none of these are considered viable solutions for flip chip bumping applications due to considerations including compliance, temperature range, and cost. In summary, lead-free soldering, originally started as an environmental issue, is evolving rapidly into a business survival tool for the worldwide electronics industry. Promising lead-free solder alternatives for surface-mount assembly applications include eutectic Sn-Ag, eutectic Sn-Cu, Sn95-Sb5, eutectic Sn-Bi, Sn-Ag-Cu, Sn-Ag-Cu-X, Sn-BiAg-X, Sn-Zn-X, and Sn-In-Ag-(X). However, for solder-bumped flip-chip interconnects, most of those options fall short in terms of fatigue resistance. Sn-In-Ag-(X) appears to be superior when compared with Sn63Pb37, as demonstrated by Sn-In-Ag-Cu. For applications involving high-lead solders, no solder alternatives have been developed yet. While the industry is advancing toward finer, smaller, lighter, and faster wafer-level packages, the use of area-array solder interconnects is suffering from soft error due to alpha emission from the lead in the solders. Although lead-free solder alternatives for eutectic Sn-Pb are virtually free from alpha emission, the continuous dependence on the use of high-lead solders for C4 applications indicates that the challenge of alpha emission from lead-containing solders will persist regardless of the lead-free move of the industry. This challenge is getting tougher with the rapid advancement of IC design toward further miniaturization. Low-alpha lead can be obtained from cold lead ore, old lead, and Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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349

laser isotope separation processes, with the latter having potential as a long-term solution. Low-alpha lead is very expensive when compared with regular lead. Due to the increase in I/O density, requirements for alpha emission levels may soon move from LC2 to LC3 level. The supply of low-alpha lead for wafer-level interconnects does not seem to be an issue.37 9.4.4 Microstructure of lead-free solders49

The microstructure of the interface between the lead-free solders (SnAg-Bi, Sn-Ag-In, Sn-Zn-Bi, and Sn-Zn-In) and the copper substrate obtained in Ref. 49 is presented in this section. It is well known that the Cu6Sn5 compound is thicker than Cu3Sn. However, there is still ambiguity about the formation of intermetallics in the Cu-Zn system. Therefore, the focus is on understanding the reaction between the Znbearing lead-free solder and the copper substrate, especially the effect of cooling rates of the soldering temperature on the microstructure of the solder joints. The Sn-Ag3.5-Bi(1.0, 3.0, and 5.0), the Sn-Ag3.5-In(1.0, 3.0, and 5.0), the Sn-Zn9.0-Bi(1.0, 3.0, and 5.0), and the Sn-Zn9.0-In(1.0, 3.0, and 5.0) alloys are prepared from Sn (99.8 percent purity), Ag (99.0 percent purity), Zn (99.8 percent purity), Bi (99.0 percent purity), and In (99.0 percent purity). The alloys are melted in argon, held at 350°C for 15 min, and cooled down to room temperature in argon flow. Commercial PCBs with and without tin coated on the copper pads are used for the substrates. Before soldering, solders and copper substrates are ultrasonically cleaned in acetone. The samples are heated at 250°C using a soldering iron with a commercial flux in air. Some of the samples are heat-treated at 250°C in a furnace by flowing nitrogen gas and then cooled in a furnace at a rate of 10°C/min. For the observation of the reaction layer at the interface, all samples are observed by using an optical microscope and SEM. The melting points of solidified alloys are shown in Fig. 9.39. It can be seen that the melting points of these samples tend to decrease when the third element such as Bi or In is increased. The melting point of three-component alloys tends to approach that of eutectic Pb-Sn solder. Typical optical micrographs of as-solidified alloys are shown in Fig. 9.40. It can be seen that most of the microstructure consists of regions of alternating lamellae (β-Sn and Ag3Sn [ε phase]) in Sn-Ag3.5 alloy.49 The β-Sn grains are also observed in the Sn-Ag3.5 alloy sample. The diameter of the β-Sn grains is about 30 µm. The structure of the lamellae appears to be rough, showing wide spacing and distribution with the addition of Bi. The β-Sn grains are much larger and the grain boundaries are irregularly shaped in the Bi-added sample. The same coarseness of structure is observed in the In-added sample. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Chapter Nine

9.39 Relationship between melting point and solder composition.

Figure

(a)

(b)

(c)

(d)

Micrographs of as-solidified lead-free solders used: (a) Sn-Ag3.5; (b) Sn-Ag3.5-Bi3; (c) Sn-Zn9; (d) Sn-Zn9-Bi3.

Figure 9.40

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351

A different microstructure develops in the Sn-Zn9.0 alloy. Large needle-shaped Zn precipitates are observed together with the eutectic structure. By adding Bi and In, the number of needle-shaped Zn precipitates is reduced and the eutectic structure appears to be rough. It is assumed that the lower solidified temperature, which is close to the melting point, is responsible for the coarse structure in the ternary systems. Typical backscattered SEM images of the Sn-Ag3.5 from two different heat treatments are shown in Fig. 9.41. The interface between the SnAg3.5 solder and the copper substrate is composed of two intermetallic layers as shown in Fig. 9.41a, showing Cu3Sn of about 2 µm in thickness next to the copper substrate and Cu6Sn5 of about 6 µm that grows into the solder. Even though the cooling rate is rapid, the formation of Cu6Sn5 occurs because the alloy with high tin composition in the Cu-Sn phase diagram forms Cu6Sn5 readily at a solidus temperature of 227°C. The higher-magnification image (Fig. 9.41b) of the sample that was cooled rapidly from the soldering temperature demonstrates that the solder reacted with copper, forming an intermetallic about 1 µm thick on the surface of the copper. It is interesting to note that a rapid reaction between the solder and copper took place while the solder solidified very quickly. Judging from the backscattered image, the intermetallic that is formed on the copper substrate is thought to be Cu6Sn5 because Cu3Sn intermetallic was formed by consuming the remaining tin or transforming Cu6Sn5 into Cu3Sn. It is also known that if the tin concentration is higher than that of copper and annealing up to 210°C is allowed, only Cu6Sn5 is formed, not Cu3Sn. As reported by the authors of Ref. 49, the eutectic Ag3Sn precipitates in a round shape, forming a network in the Sn matrix. These Ag3Sn precipitates have also a specific orientation relationship with the tin matrix. Ag3Sn precipitates also make a network in the tin matrix in the present study. The same intermetallic was observed at the interface between the solder and the Sn-coated copper substrate, as shown in

10 µm

(a)

1 µm

(b)

Solder Intermetallic Intermetallic

Copper Figure 9.41 Backscattered SEM images of the Sn-Ag3.5 solder. (a) Soldered at 250°C for 3 min in a nitrogen reflow furnace and cooled at a rate of 10°C/min. (b) Soldered using a soldering iron at 250°C for 5 s.

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Chapter Nine

1 µm Solder

Intermetallic

Backscattered SEM image of the interface between the solder and the Sn-coated copper.

Figure 9.42

Copper

Fig. 9.42. It was also found that the rapid formation of intermetallic occurred at the interface between the solder, the added third element such as Bi or In, and the copper substrate. Large, teardrop-shaped Ag3Sn particles precipitate in the tin matrix. By adding an element such as Bi or In, which reduces the temperature at which solidification takes place, the particles grow in the molten solder, resulting in large precipitates. A typical backscattered SEM image (on the right) and the results of point analyses marked in the image in the Sn-Zn9.0 solder that is cooled slowly are shown in Fig. 9.43. It is obvious that two types of intermetallics are formed on the copper substrate. One is the thick, Znrich intermetallic that “grows” to the solder, and the other is the very thin intermetallic layer on the tin-coated copper substrate. However, there is still ambiguity regarding the intermetallic formation in the Cu-Zn binary system. No precise identification of the intermetallics formed on the copper can be reported here. 9.4.5 Effects of Bi content on mechanical properties of Sn-Ag solders

The effects of Bi content on the mechanical properties of Sn-Ag solder alloys50,51 are presented in this section. First, the effects of Bi content on the temperature dependence of the tensile strength and the breaking elongation of Sn-Ag solder alloys are evaluated to optimize the amount of Bi in Sn-Ag solder alloys. Also, the effect of Bi content on creep characteristics is evaluated using stress relaxation tests. The evaluated solder alloy compositions are listed in Table 9.13. The melting points are measured by a DSC. Figure 9.44 shows the effect on melting point of Bi additions to the Sn-Ag solder alloys. It can be seen that the solidus and liquidus temperatures are lowered at a rate of −0.8K and −3.9K per 1 percent Bi added to Sn-Ag solder alloys, with the difference between the two temperatures ∆T becoming larger as the Bi content in the Sn-Ag solder alloys increases.

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Solder

1 2 Intermetallic Copper

10 µm

Figure 9.43 Point analysis on intermetallics in the Sn-Zn9 solder cooled rapidly from the soldering temperature.

The microstructure of the solder alloys is investigated using a SEM and an energy dispersion x-ray microanalyzer (EDX). Figure 9.45 shows the microstructures of the Sn-Ag solder alloys. It can be seen that the microstructure of Sn-Ag-C (SAC) consists of a matrix of the Sn phase, intermetallic Ag3Sn, and Cu precipitates. As the Bi content is increased, Bi dissolves in the Sn phase (Figs. 9.45b and 9.45c). When the Bi content exceeds the maximum soluble amount of Bi in the Sn phase, Bi begins to precipitate in the Sn phase (Fig. 9.45d). Since the EDX results show that the amount of Bi in the Sn phase at the moment when Bi precipitates appear is in the range of 3.5 percent to 4.1 per-

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Chapter Nine

TABLE 9.13

Compositions of Lead-Free Alloys Composition (weight %)

Designation

Sn

Pb

Ag

Bi

Cu

A

B

SABC

Balance

—

2.0

7.5

0.5

235

0.48

Sa-Bi5

Balance

—

3.5

Sa-Bi3

Balance

—

3.5

5.0

0.75

263

0.59

3.0

0.75

208

0.44

Sa-Bi1.5

Balance

—

3.5

1.5

0.75

160

0.33

SAC

Balance

—

3.5

—

0.5

88

0.16

Sn-Ag

Balance

—

3.5

—

—

83

0.16

Pb-Sn

Balance

37.0

—

—

—

cent, it is clear that the maximum soluble amount of Bi in the Sn phase is about 3 percent to 4 percent at 297K. The tensile test specimens have a total length of 120 mm, a gauge length of 25 mm, and a thickness of 3.5 mm. Tensile tests are carried out in a deformation temperature range from 297 to 423K. A strain rate of 10−4/s is chosen for this test considering the temperature cycle test (TCT) conditions. Figure 9.46 shows the relation between the tensile strength and the Bi content. The tensile strength (MPa) of Pb-Sn is shown on the right vertical axis. The plots on the left vertical axis are SAC data. The tensile strengths of Sn-Ag solder alloys are higher than those of Pb-Sn for every temperature from 297 to 423K. At 297K, the addition of up to 5 percent Bi to Sn-Ag solder alloys increases tensile strength, but there is no further improvement beyond 5 percent. Since the maximum soluble amount of Bi in the Sn phase is about 3 percent to 4 percent, the cause of tensile strength enhancement by the addition of up to 3 percent Bi to Sn-Ag solder alloys is presumably solution hardening. Further increase in the tensile strength due to the addition of

Figure 9.44 Relation between melting point and Bi content.

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Figure 9.45

(a)

(b) (b)

(c) (c)

(d) (d)

355

Microstructures of Sn-Ag solder alloys.

sB/MPa

more than 3 percent Bi appears to be caused by precipitate dispersion hardening. Furthermore, the rate of the tensile strength increase due to the addition of up to 3 percent Bi is larger than that due to the addition of over 3 percent Bi. As a result, it has been clarified that solution hardening is more dominant than precipitate dispersion hardening as the cause of tensile strength enhancement of Sn-Ag solder by Bi addition. As the deformation temperature rises, the tensile strength enhancement by Bi addition is reduced. At 423K, in particular, addition of 3 percent or more Bi hardly affects the tensile strength. In order to evaluate the dependence of the solder alloy strength on deformation temperature, tensile strength σB has been defined as a function of deformation temperature T considering the dislocation migration (σB = A − BT). In this case, A is a constant and B is the temperature-strengthening coefficient that indicates the degree of the tensile strength changes with temperature.50,51 The Bi content dependence of A and B is listed in

9.46 Relation between tensile strength and Bi content.

Figure

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Chapter Nine

Table 9.13. It is clear that the addition of up to 5 percent Bi to Sn-Ag solder alloys increases B, but there is no further change beyond 5 percent. The increase in B corresponds to the fact that the tensile strength decreases with a greater rate as the deformation temperature rises. Therefore, the addition of Bi is considered to have little effect on the tensile strength at higher temperatures. Breaking elongation (percent) is the main index of material ductility. Figure 9.47 shows the Bi content dependence of breaking elongation. The plots on the left vertical axis are SAC data. Breaking elongation decreases with the increase in the amount of Bi addition for every temperature from 297 to 423K. The cause is presumably that cracks are generated more easily, since the number of points where stress concentrates increases with the increase in Bi solute and precipitates. Moreover, when Bi precipitates arise by superfluous Bi addition to Sn-Ag solder, the ductility of Sn-Ag-Bi solder alloys is reduced extremely at temperatures beyond 411K because Sn-Bi eutectic crystals arise. Therefore, it is considered necessary to restrict the amount of Bi so that no Bi precipitation takes place in the Sn phase.51 From these results, it is deduced that the effective Bi content in Sn-Ag solder alloys for the enhancement of bump interconnection reliability is 3 percent or less. The stress relaxation tests are conducted on the same specimens as those for tensile tests under constant strain conditions with 5 percent strain and in the holding temperature range from 297 to 423K.50,51 Figure 9.48 shows the stress relaxation of the Sn-Ag3.5-Bi1.5 solder alloy. It can be seen that most of stress relaxation is observed in the first 100 s, and then the stress levels off within a holding time of 10,000 s except at a holding temperature of 297K. The time until stress relaxation is completed becomes shorter as holding temperature rises. There-

Relation between breaking elongation and Bi content.

Figure 9.47

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sR/MPa

Solders for Next-Generation High-Density Interconnects

Figure 9.48 Stress relaxation of the Sn-Ag3.5-Bi1.5-Cu0.75 alloy.

sR/MPa

fore, stress relaxation is considered to be dominant in the thermal activation process. Figure 9.49 shows the stress at the end point of stress relaxation (relaxation stress) at each holding temperature. The relaxation stress of Pb-Sn is shown on the right vertical axis. Data for 0 percent Bi signify those of Sn-Ag. At a holding temperature of 323K, the relaxation stresses of all Sn-Ag solder alloys are twice those of Pb-Sn and do not depend much on the amount of Bi. On the other hand, for holding temperatures over 373K, it turns out that relaxation stress becomes smaller as the amount of Bi addition to Sn-Ag solder alloys increases. This indicates that the thermal energy beyond 373K is sufficient to move the defects introduced at the time of deformation. Furthermore, the relaxation stress of Sn-Ag3.5-Bi3 is equivalent to that of Pb-Sn at a holding temperature of 423K, while the relaxation stress of Sn-Ag3.5-Bi5 is equivalent to or lower than, that of Pb-Sn at holding temperatures of 373 and 423K, respectively. It can be considered that the inelastic strain generated in bumps becomes larger as the relaxation stress decreases. Therefore, in order to make the inelastic strain generated in Sn-Ag-Bi solder alloy bumps smaller than that in

9.49 Relation between relaxation stress and Bi content.

Figure

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Relation between reduction in stress and Bi content.

Figure 9.50

st/MPa

Pb-Sn bumps during the holding time, it is considered necessary to limit the Bi content to 3 percent or less. In order to carry out quantitative evaluation of the stress relaxation characteristics, the percentage reduction from the initial stress R has been defined as R = (1 − σ[t]/σ[0]) × 100, where σ(t) is the stress at holding time t and σ(0) is the initial stress. Figure 9.50 shows the relation between the percentage reduction in stress and the Bi content. It is clear that the percentage reduction in stress increases with increasing Bi content. Therefore, it appears that addition of Bi to Sn-Ag solder alloys makes stress relaxation occur more easily. On the other hand, stress relaxation is caused by the migration of defects produced at the time of deformation. Therefore, it is considered that the increase in the percentage reduction in stress corresponds to the increase in the quantity of defects introduced at the time of deformation. In other words, the increase in the percentage reduction in stress caused by addition of Bi to Sn-Ag solder alloys appears to be evidence that addition of Bi to Sn-Ag solder alloys makes the straincontrolled low cycle fatigue characteristics degrade. Consequently, SnAg solder alloys containing 3 percent or lower Bi are considered the most practical for solder interconnection. The true stress-true strain

Figure 9.51 True stress-true strain curves of the Sn-Ag3.5Bi1.5-Cu0.75 alloy.

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TABLE 9.14

359

Solder Alloys and Test Temperatures

Solder alloy Sn-Pb37

Melting point (°C)

Test temperature (°C)

∆T (°C)

183

210

27

Sn-Ag3.4-Bi4.8

205–210

235

25

Sn-Ag3.5-In1.5

217

235

18

Sn-Ag3.8-Cu0.7

217

235

18

Sn-Ag3.5

221

245

24

Sn-Cu0.7

227

245

18

curves of the Sn-Ag3.5-Bi1.5 solder alloy for different temperatures are shown in Fig. 9.51. These are very useful for finite element analysis of interconnects with this solder alloy. 9.4.6 Wetting performance of lead-free solders

The compatibility of lead-free solders and PCB finishes is discussed in Refs. 52 and 53 and is presented in this section. The solder alloys evaluated are Sn-Ag3.5-In1.5, Sn-Ag3.4-Bi4.8, Sn-Ag3.8-Cu0.7, SnAg3.5 and Sn-Cu0.7, as shown in Table 9.14. The PCB surface finishes are immersion Sn, immersion Ag, electroless Pd, electroless Ni/Au, and OSP. Eutectic Sn-Pb37 solder is used for baseline comparisons. The test coupon is designed in accordance with the IPC J STD-003 standard. The coupon dimensions are 0.25 × 0.25 × 0.062 in. The coupon is routed prior to copper plating and application of the surface finish. Thus only finished metal is exposed in the solder bath during dipping. Test coupons are shown in Fig. 9.52. The test coupons are studied in as-received and after-reflow conditions. Prior to testing, the as-received boards are stored in a positivepressure nitrogen-purged chamber. Reflowed boards are run through a Heller 1700 forced-convection reflow oven under nitrogen (<25 ppm O2). The peak temperature is 260°C and the time above 217°C is 55 s. Double-sided reflow is common, and the ability of the finish to survive at least one reflow cycle prior to assembly is critical. The surface finishes (as-received and after one reflow cycle) are characterized by Rutherford backscattering spectroscopy (RBS), Auger electron spectroscopy (AES), and XPS. Wetting balance measurements are used to quantify solder wetting of each finish and alloy. Both a noclean (NC2) and a water soluble (WS1) flux are used in the wetting balance tests.

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Chapter Nine

Figure

9.52

IPC

solderability

test coupons.

Solderability test methods are broadly classified in two categories:52,53 ■

Measurement under dynamic conditions, involving investigation of wetting times, wetting forces, rates of wetting, etc.

■

Measurement under static conditions, involving investigation of the contact angle, degree of spreading, etc.

In a wetting balance measurement, the instrument records the dynamic wetting force as the solderable surface is dipped into the molten solder. In the operation of a wetting balance, the specimen is suspended from a sensitive balance and immersed edgewise, at a predetermined and controlled rate, and to a specified depth, into the molten solder maintained at a controlled temperature. As a result of the interaction between the molten alloy and the board finish, the wetted coupon is subject to time-variant vertical buoyancy forces and downward surface tension forces. The forces are detected by a transducer and are converted into an electrical signal, which in turn is recorded by the data acquisition system in a computer.54 The specimen is first dipped in flux, attached to the balance, and then immersed in the molten solder to a specified depth by raising the solder bath. The coupon is then held in that position for a specified period of time. The test ends when the solder bath is lowered. The force experienced during the wetting is recorded and plotted as wetting force vs. time. The key wetting balance parameters measured are Ta and Fmax. Ta is the time to the buoyancy-corrected force line. At this time the contact angle of the solder and the test coupon is 90° and the wetting forces pulling the coupon into the molten solder equal the buoyancy force

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361

pushing the less dense coupon out of the molten solder. Fmax is the maximum wetting force exerted by the solder on the coupon and is directly proportional to the height the solder climbs up the coupon. A multicore universal solderability tester (MUST II) is used in the experiments.52,53 The wetting balance tests are conducted in accordance with the standard IPC J-STD 003. The solder alloys are brought to within ⫾1°C of the specified test temperature (see Table 9.14). The coupon is dipped in flux for 5 s and the excess flux is drained off. After fluxing, the coupon is placed on a mounting clip and placed on the wetting balance. Any dross that may have formed on the solder is wiped away from the molten solder surface prior to coupon dipping. The coupon is then dipped into the molten solder at a constant speed of 20 mm/s to a depth of 5 mm. The total immersion time is 10 s. At the end of 10 s, the solder bath is lowered and the coupon is removed from the clip. The testing is carried out in air. Seven specimens are tested for each flux-finish-solder alloy combination. The data acquisition software collects data points every 0.001 s for the test duration. Wetting curves result for the wetting force vs. time, with extracted values for wetting time Ta and maximum wetting force Fmax measured relative to the buoyancy-corrected zero-force line. Measurement with respect to the buoyancy-corrected zero-force line and not to the instrument zero-force line allows the data obtained to be independent of the sample size and shape. Since solder wetting is a surface interaction process, the characterization of the surface finish is important in solderability studies. RBS provides a nondestructive depth profile of layered materials by measuring the energy of a 2-MeV incident He+ beam after collision with atomic nuclei in the target material. The layer thickness, layer stoichiometry, and interfacial sharpness are determined using RBS. AES utilizes an incident beam of electrons to excite atoms in the surface, which relax by emission of Auger electrons characteristic of the parent atom. This provides an elemental analysis of the surface and is useful in identifying surface contaminants. XPS utilizes an incident x-ray beam to eject photoelectrons from surface atoms. The photoelectrons have characteristic energies and indicate the concentration of surface species with a particular bonding type. This technique is useful in identifying the chemical bonding between elements such as metal oxides. A Kratos XSAM 800 multitechnique surface analysis system is used for both Auger and XPS analysis.52,53 Figures 9.53 through 9.56 plot the effect of temperature on Fmax and Ta for Sn and Au-Ni board finishes with Sn-Ag3.8-Cu0.7 and the two different fluxes. As expected, the wetting time Ta decreases with increasing temperature. The melting point of Sn is 232°C. Above this

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Effect of test temperature on Fmax for Au-Ni PCB finish with the Sn-Ag3.8-Cu0.7 alloy.

Figure 9.53

Effect of test temperature on Fmax for Sn PCB finish with the Sn-Ag3.8-Cu0.7 alloy.

Figure 9.54

Effect of test temperature on Ta for Au-Ni PCB finish with the Sn-Ag3.8-Cu0.7 alloy.

Figure 9.55

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Effect of test temperature on Ta for Sn PCB finish with the Sn-Ag3.8-Cu0.7 alloy.

Figure 9.56

Figure 9.57

Average Fmax for Sn PCB finish.

Figure 9.58

Average Ta for Sn PCB finish.

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Chapter Nine

Figure 9.59 XPS spectrum of the Sn PCB finish in asreceived condition.

Figure 9.60

XPS spectrum of the Sn PCB finish after one

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Figure 9.61

Average Fmax for Ag PCB finish.

Figure 9.62

Average Ta for Ag PCB finish.

365

XPS spectrum of the Ag PCB finish in asreceived condition.

Figure 9.63

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Chapter Nine

XPS spectrum of the Ag PCB finish after one

Figure 9.64

reflow cycle.

Figure 9.65

Average Fmax for Pd PCB finish.

Figure 9.66

Average Ta for Pd PCB finish.

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Figure 9.67 XPS spectrum of the Pd PCB finish in asreceived condition.

Figure 9.68

XPS spectrum of the Pd PCB finish after one

reflow cycle.

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Chapter Nine

Figure 9.69

Average Fmax for Au-Ni PCB finish.

Figure 9.70

Average Ta for Au-Ni PCB finish.

Figure 9.71 XPS spectrum of the Au-Ni PCB finish in asreceived condition.

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XPS spectrum of the Au-Ni PCB finish after one reflow cycle.

Figure 9.72

Figure 9.73

Average Fmax for OSP PCB finish.

Figure 9.74

Average Ta for OSP PCB finish.

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Chapter Nine

XPS spectrum of the OSP PCB finish in asreceived condition.

Figure 9.75

Figure 9.76

XPS spectrum of the OSP PCB finish after one

reflow cycle.

temperature, the Sn finish melts (fusible finish), while the gold finish must dissolve at all test temperatures. Increasing the test temperature does not change Fmax significantly for either finish. For both Sn and AuNi board finishes, Fmax is smaller with no-clean flux (NC2), but Ta is slightly larger with NC2, especially at lower temperatures. For the comparative solderability tests, relatively low solder temperatures were used (in many cases <20°C above the melting point) to exaggerate any differences between the alloys, finishes, or fluxes. Fig-

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371

ures 9.57 through 9.76 provide the results of the wetting balance and XPS surface analysis for each finish. Some important results are summarized as follows.52,53 9.4.6.1

Wetting balance.

With the water-soluble flux, Fmax is generally larger for the Sn finish compared to the other finishes (Fig. 9.57), indicating the greatest tendency to wet. The combinations of Sn finish, water-soluble flux, and Sn-Ag3.5 and Sn-Ag3.8-Cu0.7 alloys have the highest Fmax values in the test matrix. For the Sn finish, Ta is minimum for the SnAg3.5 alloy and maximum for the Sn-Cu0.7 alloy (Fig. 9.58). One reflow cycle in nitrogen does not significantly impact the wetting behavior. Sn finish.

Ag finish. Fmax is slightly higher for the water-soluble flux compared to the no-clean flux and did not vary significantly with alloy composition for either flux (Fig. 9.61). The Ta for all of the solder alloys is low (comparable to the OSP coating), indicating rapid wetting (Fig. 9.62). The fastest wetting time is for the Sn-Pb37 eutectic alloy. Wetting force is not impacted by the reflow cycle. The effect of a reflow cycle on wetting time varies with solder alloy. Pd finish. In general, Fmax is greater with the water-soluble flux compared to the no-clean flux. Fmax for the Pd finish is highest for the SnPb37 eutectic alloy (Fig. 9.65). With the lead-free alloys, the Pd finish generally has the lowest Fmax of all the finishes. Ta is comparable for the water-soluble and the no-clean flux (Fig. 9.66). Ta is generally greater for the Pd finish than for the other finishes. The reflow preconditioning does not significantly change the wetting behavior. Ni-Au finish. Fmax is higher with the water-soluble flux compared to the no-clean flux (Fig. 9.69). The reflow cycle increases the wetting time and decreases the wetting force with the no-clean flux and the SnAg3.5-In1.5 and the Sn-Cu0.7 alloys (Fig. 9.70). With the water-soluble flux, the change with these alloys after reflow is less. OSP. Fmax for the combination of OSP, no-clean flux, and Sn-Ag3.8Cu0.7 and Sn-Cu0.7 alloys is the lowest in the test matrix (Fig. 9.73). Ta is low and comparable for the OSP and the Ag finish (Fig. 9.74). The wetting results after reflow vary with alloy. It should be remembered that the coupons are stored in nitrogen after the reflow cycle, which may have help preserve solderability after reflow.

9.4.6.2

Surface analysis.

The usual Sn oxide (SnO2, SnO, and Sn) chemical states are observed at the surface of the Sn finish. With 5 min of Ar sputter cleanSn finish.

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Chapter Nine

ing, the oxygen concentration decreases dramatically, indicating the oxide layer is thin. The reflow cycle does not alter the surface finish (Figs. 9.59 and 9.60). Ag finish. It is not possible to determine the chemical state for the small amount of oxygen at the surface because the XPS signatures for elemental Ag and Ag2O are nearly identical. The interface between Ag and Cu is well behaved and relatively sharp. The surface is unchanged by reflow in nitrogen (Figs. 9.63 and 9.64). Pd finish. It is difficult to determine the chemical state for the small amount of oxygen at the surface because the XPS signatures for elemental Pd and native Pd oxide are nearly identical (Figs. 9.67 and 9.68). The surface is unchanged by the reflow cycle. Ni-Au finish. The XPS data indicate a slight amount of C on the asreceived surface. This is always observed on Au films exposed the the atmosphere and is not a result of the plating process. There is no indication of Ni diffusion to the surface after a single reflow cycle (Figs. 9.71 and 9.72). OSP. Cl is observed at the surface (and in the bulk) Figures 9.75 and 9.76. OSPs often use Cl compounds to increase the rate at which OSP is formed on a Cu surface. Therefore it is not unusual to find Cl in OSP films. The C in the OSP film appears to consist of a variety of C-Corganic, C-C, and C-Hx bonds. After the nitrogen reflow cycle, the surface is discolored. All fluxes, finishes, and solder alloys considered in Refs. 52 and 53 yield acceptable wetting results. The water-soluble flux yields higher Fmax than the no-clean flux for all of the lead-free alloys. The impact of flux type on Fmax for the eutectic Sn-Pb37 alloy is small for all finishes. The effect of flux type on Ta is generally small and varies by solder alloy and finish. In general, Fmax is greatest for the Sn finish and lowest for the OSP and Pd finishes with the lead-free alloys. Ta is generally lower for the Ag and OSP finishes and higher for the Pd finish with all alloys. Since Ta is strongly dependent on the test temperature, the relative performance of the finishes is also dependent on test temperature.

9.5 References 1. Lau, J. H., and G. K. Listvinsky, “Bending and Twisting of Internally Pressurized Thin-Walled Cylinder with Creep,” Journal of Applied Mechanics, Transactions of ASME, 48:439–441, June 1981. 2. Lau, J. H., “Bending of Circular Cylinder with Creep,” Journal of Engineering Mechanics Division, Proceedings of ASCE, 107:265–270, 1981.

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3. Lau, J. H., “Bending and Twisting of Pipe with Creep,” International Journal of Nuclear Engineering and Design, 367–374, June 1981. 4. Lau, J. H., and T. T. Lau, “Creep of Pipes Under Axial Force and Bending Moment,” Journal of Engineering Mechanics Division, Proceedings of ASCE, 108:190–195, 1982. 5. Lau, J. H., and T. T. Lau, “Deformation of Elbows with Creep,” Proceedings of the 4th ASME National Congress on Pressure Vessel and Piping Technology, June 1983. 6. Lau, J. H., S. S. Jung, and T. T. Lau, “Creep of Thin-Wall Cylinder Under Axial Force, Bending, and Twisting Moments,” Journal of Engineering for Power, Transactions of ASME, 106:79–83, 1984. 7. Lau, J. H., and C. K. Hu, “Creep of Thin-Wall Cylinder Under Combined Loads,” Proceeding of the 5th ASCE Engineering Mechanics Conferences, pp. 917–920, 1984. 8. Lau, J. H., and T. T. Lau, “Bending and Twisting of Pipes With Creep,” Journal of Pressure Vessel Technology, Transactions of ASME, 106:188–195, May 1984. 9. Lau, J. H., and C. K. Hu, “Deformation of Curved Bars with Creep,” Journal of Engineering for Power, Transactions of ASME, 107:225–230, 1985. 10. Lau, J. H., and T. T. Lau, “Creep of Pipes Under Axial Force and Twisting Moment,” Journal of Engineering Mechanics, Proceedings of ASCE, 108:174–179, 1982. 11. Lau, J. H., “Creep of Solder Interconnects under Combined Loads,” IEEE Transactions on CHMT, 16(8):794–798, December 1993. 12. Lau, J. H., “Bending and Twisting of 63Sn37Pb Solder Interconnects with Creep,” Journal of Electronic Packaging, Transactions of ASME, 116:154–157, June 1994. 13. Lau, J. H., “Creep of 96.5Sn3.5Ag Solder Interconnects,” Soldering & Surface Mount Technology, (15):45–49, September 1993. 14. Evans, H. E., Mechanics of Creep Fracture, Elsevier Applied Science Publishers, New York, 1984. 15. Evans, H. E., and Wilshire, B., Creep of Metals and Alloys, The Institute of Metals, London, UK, 1985. 16. Conway, S. B., Numerical Methods for Creep and Rupture, Gordon and Breach, Science Publishers, New York, 1967. 17. Garofalo, F., Fundamentals of Creep and Creep-Rupture in Metals, The Macmillan Company, New York, 1965. 18. Clauss, F. J., Engineer’s Guide to High Temperature Materials, Addison-Wesley, Reading, MA, 1969. 19. Wilshire, B., and R. J. Owen, Recent Advances in Creep and Fracture of Engineering Materials and Structures, Pineridge Press, Swansea, UK, 1982. 20. Ponter, A. R. S., and F. A. Leckie, “Constitutive Relationships for the Time Dependent Deformation of Metals,” Journal of Engineering Materials and Technology, Transactions of ASME, 98:47–51, 1976. 21. Miller, A. K., “An Inelastic Constitutive Model for Monotonic, Cyclic, and Creep Deformation,” Journal of Engineering Materials and Technology, Transactions of ASME, 98:97–105, 1976. 22. Hart, E. W., “Constitutive Relations for the Non-elastic Deformation of Metals,” Journal of Engineering Materials and Technology, Transactions of ASME, 98:193–202, 1976. 23. Darveaus, R., and K. Banerji, “Constitutive Relations for Tin-Based Solder Joints,” IEEE Transactions on CHMT, 15(6):1013–1024, December 1992. 24. Schroeder, S. A., and M. R. Mitchell, “Torsional Creep Behavior of 63Sn-37Pb Solder,” ASME Proceedings of Advances in Electronic Packaging, 649–653, April 1992. 25. Cortez, R., E. Cutiongeo, M. Fine, and D. Jeannotte, “Correlation of Uniadial TensionTension, Torsion, and Multiaxial Tension-Torsion Fatigue Failure in a 63Sn-37Pb Solder Alloy,” Proceedings of the 42nd IEEE Electronic Components & Technology Conference, pp. 354–359, May 1992. 26. Smith, J. O., and O. M. Sidebottom, Inelastic Behavior of Load-Carry Members, Wiley, New York, 1965.

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27. Caulfield, T., J. A. Benenati, and J. Acocella, “Surface Mount Array Interconnections for High I/O MCM-C to Card Assembles,” Proceedings of International Conference on Multichip Modules, pp. 320–325, Denver, CO, April 1993. 28. May, T. C., and M. H. Woods, “A New Physical Mechanism for Soft Errors in Dynamic Memories,” Proceedings of International Reliability Physics Symposium, pp. 33–40, 1978. 29. Hasnain, Z., and A. Ditali, “Building-in Reliability: Soft Errors—A Case Study,” Proceedings of International Reliability Physics Symposium, pp. 276–280, 1992. 30. Ditali, A., and Z. Hasnain, “Monitoring Alpha Particle Sources During Wafer Processing,” Semiconductor International, 136–140, June 1993. 31. Fano, U., “Penetration of Protons, Alpha Particles and Mesons,” Semiconductor International, 136–140, June 1993. 32. Drumer, J. E., “Table of Isotopes,” Los Alamos Handbook of Radiation Monitoring, LA-1835, 3rd ed., chap. 10, Los Alamos, NM, 1958. 33. Lederer, C. M., J. M. Hollander, and I. Perlman, Table of Isotopes, John Wiley & Sons, New York, 1967. 34. Friedlander, G., and J. M. Kennedy, Introduction to Radiochemistry, John Wiley & Sons, New York, 1949. 35. Woolley, J. A., L. E. Lamar, N. H. Stradley, and D. M. Harshbarger, “Low Alpha Particle Emitting Ceramics: What’s the Lower Limit?” Proc. IEEE, 273–276, 1979. 36. Roberson, M. W., “Soft Error in Solder Bumped Packaging,” Proceedings of the 4th International Symposium and Exhibition on Advanced Packaging Materials, pp. 15–18, Atlanta, GA, March 1998. 37. Lee, N. C., “Lead-Free Soldering and Low Alpha Solders for Wafer Level Interconnects,” Proceedings of International Symposium on Microelectronics, pp. 541–550, Boston, MA, October 2000. 38. Electronic Engineering Times, 21 June 1999. 39. Berry, S., and S. Winkler, “Flip Chip Market Expanding to Meet Speed Performance Demands,” Chip Scale Review, p. 6, November/December 1999. 40. National Center for Manufacturing Sciences, Lead and the Electronic Industry: A Proactive Approach, May 1995. 41. Smith III, E. B., and L. K. Swanger, “Are Lead-free Solders Really Environmental Friendly?” SMT, 64–66, March 1999. 42. Lee, N. C., “Lead Free Soldering—Where the World Is Going,” Advancing Microelectronics, 26(5):29–35, September/October 1999. 43. Gibbs, F., “Pb Free Interconnect,” Proceedings of NEMI Lead Free Meeting, Chicago, 25 May 1999. 44. Huang, B. L., and N. C. Lee, “Prospects of Lead Free Alternatives for Reflow Soldering,” Proceedings of International Symposium on Microelectronics, pp. 29–35, Chicago, IL, October 1999. 45. Slattery, J. A., et al., “Lead-Free Alloy Containing Tin, Silver, and Indium,” U.S. Patent 5,580,520, 3 December 1996. 46. Slattery, J. A., et al., “Lead-Free Alloy Containing Tin, Silver, and Indium,” U.S. Patent 5,256,370, 26 October 1993. 47. Yeh, S., “Fatigue Resistant Lead Free Solder,” U.S. Patent 5,938,862. 48. Elenius, P., and S. Yeh, “Lead Free Solder for Flip Chip and Chip Scale Packaging (CSP) Applications,” Proceedings of IPCWorks, pp. S-03-2-1–S-03-2-6, Minneapolis, MN, 23–28 October 1999. 49. Nakamura, Y., Y. Sakakibara, Y. Watanabe, and Y. Amamoto, “Microstructure of Solder Joints with Electronic Components in Lead-Free Solders,” Soldering & Surface Mount Technology, 10(1):10–12, 1998. 50. Tateyama, K., H. Ubukata, Y. Yamaoka, K. Takahashi, H. Yamada, and M. Saito, “Effects of Bi Content on Mechanical Properties and Bump Interconnection Reliability of Sn-Ag Solder Alloys,” The International Journal of Microcircuits and Electronic Packaging, 23(1):131–137, First Quarter 2000. 51. Tateyama, K., et al., “Evaluation of Mechanical Properties of Pb Free Solder Alloys,” The Journal of Japan Institute of Interconnecting and Packaging Electronic Circuits, 12(7):503–506, 1997.

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52. Sattiraju, S. V., R. W. Johnson, D. Z. Gene, and M. J. Bozack, “Wetting Performance of Several Pb-free Board Finishes and Solder Alloys,” Proceedings of IPCWorks, September 2000. 53. Sattiraju, S. V., R. W. Johnson, D. Z. Gene, and M. J. Bozack, “Wetting Performance vs. Board Finish and Flux for Several Pb-free Solder Alloys,” Proceedings of IEEE Electronics Manufacturing Technology Symposium, pp. 253–262, San Jose, CA, October 2000. 54. Lea, C., “Solderability of Fine Pitch Surface Mount Components,” in Handbook of Fine Pitch Surface Mount Technology, Lau, J. H. (ed.), van Nostrand Reinhold, New York, 1994.

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Source: Microvias

Chapter

10 Solder-Bumped Flip Chip WLCSP

10.1 Introduction One of the most cost-effective packaging technologies is DCA, such as the solder-bumped flip chip on PCB. However, because of the thermal expansion mismatch between the silicon chip and epoxy PCB, underfill encapsulant is usually needed for solder joint reliability.1–6 However, due to the underfill operation, the manufacturing cost is increased and the manufacturing throughput is reduced. In addition, the rework of underfilled flip chip on PCB is very difficult, if not impossible. This further complicates the known good die (KGD)-related issues. There is another reason why DCA is not yet very popular. Usually, the pitch and size of the pads on the peripheral-arrayed chip are very small and impose great demands on the supporting structure—the PCB. The high density and the fine-line width/spacing PCB with microvia sequential built-up circuits are not yet commonly available at a reasonable cost, as discussed in Chaps. 1 through 8. Thus, alternative low-cost and high-performance electronic packaging techniques are needed. WLCSP provides a solution to these problems.1–4 The unique feature of most WLCSPs is the use of a metal layer to redistribute the very fine-pitch peripheral-arrayed pads on the chip to much larger-pitch area-arrayed pads with much taller solder joints on the PCB. Thus, with WLCSPs, the demand on the PCB is relaxed, the underfill may not be necessary, and the KGD issues are much simpler. From the system houses’ point of view, WLCSP is just like another “solder-bumped flip chip” surface-mount component, except for the following: (1) the solder bumps of WLCSP are much taller and bigger; (2) the PCB assembly of WLCSP is more robust; and (3) they are so happy that they do not have to struggle with the underfill encapsulant. 377

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Chapter Ten

In Lau and Lee, the authors discuss the design, materials, process, manufacturing, reliability, and applications of WLCSPs from more than 20 different companies.1,2 In this book, two WLCSPs from two new organizations are presented. Since wafer bumping is the key to solderbumped WLCSP, two different solder-bumping methods, especially for lead-free solders, will be discussed first. 10.2 Taguchi Design of Experiment for Wafer Bumping by Stencil Printing Wafer bumping is the heart of solder-bumped flip chip technology.1–11 Today, there are many different ways to put the tiny solder bumps on the wafer. Usually, the solder bumps are no larger than 100 µm for the conventional flip chip applications and are as large as 400 µm for the wafer-level packaging applications. In Ref. 1, Lau shows 12 different wafer-bumping methods; in Refs. 7 through 11, we see that the stencilprinting method is cheaper than most of the other methods, especially for wafer-level packaging. Wafer bumping by the stencil-printing method is not only potentially low in cost and high in throughput, but is also welcomed by system manufacturers, because stencil printing of solder paste is one of their most important steps in surface mount technology.12 The only limitation is the very fine pitch of the pads on the chip. Today, stencil-printing solder paste on the wafer in volume production is limited to 150 µm.7 Figure 10.1 shows the cause-and-effect (fishbone) diagram for solder paste printing on wafers. It can be seen that there are eight major categories (operator, environment, printing parameter, printer, stencil, wafer, squeegee, and solder paste) that influence the quality of Printing Parameter

Operator

squeegee travel

experience

motivation skill/ knowledge air humidity chem.phys. impacts

squeegee force cleaning lift squeegee speed

angle of attack

speed of separation

Squeegee

squeegee cross frame squeegee profile section

squeegee type of material process squeegee width material

stencil solvent pickup dimensions squeegee guidance thixotropy org. binder antivibration viscosity squeegee pickup substrate pos. particle material size clearance betw. substrate support additives mov. parts holder frame

Quality of Solder Paste Printing

transient response temperature

Environment Figure 10.1

Stencil

Printer

Wafer

Solder Paste

Fishbone diagram for paste printing on a wafer.

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solder paste printing on the wafer. This diagram helps us to sort out the potential causes for solder paste printing defects and to organize the causes into defined categories to yield high-quality solder paste printing. To perform a Taguchi design of experiment with all the parameters shown in Fig. 10.1 is impossible. However, by selecting some of the important parameters, the characteristics of stencil printing for waferlevel packaging could be analyzed. In this section, Taguchi experiments are designed and carried out with five critical factors that influence the solder bumping of a 200-mm (8-in.) wafer through the stencil-printing method. These factors include: paste types (types 3 and 4), squeeze forces (9 and 12 lb), snap-off heights (0 and 5 mil), aperture shapes (square and circle), and aspect ratios (2.5 and 2.75). They are varied to form a two-level L8 orthogonal array experiment. The analysis of the mean (ANOM) and the analysis of variance (ANOVA) are used to choose the most influential factors. After fixing the most influential factors, a two-level L4 orthogonal array experiment is followed to optimize the other material and process parameters. 10.2.1 Sample description and experiment setup

The wafer used in this study13 is a 200-mm (8-in.) wafer, which is shown in Fig. 10.2a. The chip size and its critical dimensions are shown in Fig. 10.2b. It can be seen that there are 48 pads for each chip and the pad pitch is 0.75 mm. The pad diameter is 0.33 mm. Figure 10.3a shows a photo of the pad with a copper stud, and Fig. 10.3b shows the dimension of the copper stud, which is about 60 µm tall.

(a) Figure 10.2

(b)

(a) Die layout of a 200-mm wafer. (b) Die dimensions and bump dimension

and pitch.

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Chapter Ten

(a) Figure 10.3

(b)

(a) Copper stud. (b) Geometry of copper stud.

It should be pointed out that the focus of this section is to study the printing characteristics of solder paste on wafers using the Taguchi design of experiments. The strength and reliability of solder bumps are out of the scope of this section. The stencil is a 8-mil- (0.2-mm)-thick stainless-steel sheet drilled with a phase-quadrupled Nd:YAG laser system made by LPKF. The stencil is then electropolished in a 30 percent potassium hydroxide solution. The stencil contains four different quadrants with varying aperture shapes and sizes, as shown in Fig. 10.4. It can be seen that the first quadrant has a 20-mil square opening; the second quadrant has a 20-mil round opening; the third quadrant has a 22-mil square opening; and the fourth quadrant has a 22-mil round opening. The MPM SPM-AV autovision semiautomatic printer is used for this study. The paste materials are Alpha Metals’ types 3 and 4 Sn63-Pb37

Stencil design with four different openings, which divide the 200-mm wafer into four quadrants.

Figure 10.4

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solder alloys. The distributions of type 3 powder sizes are as follows: more than 80 wt% of the nominal diameters are between 20 and 45 µm; less than 1 wt% of the nominal diameters are larger than 45 µm; no more than 10 wt% of the nominal diameters are less than 20 µm; and none of the powder size is larger than 50 µm. The distributions of type 4 powder sizes are as follows: more than 90 wt% of the nominal diameters are between 20 and 38 µm; less than 1 wt% of the nominal diameters are larger than 38 µm; no more than 10 wt% of the nominal diameters are less than 20 µm; and none of the powder size is larger than 40 µm. The targeted solder-bump height on the wafer is 13 mil (0.33 mm). 10.2.2 Control factors in stencil printing

Table 10.1 shows the control factors: paste types (types 3 and 4), squeeze forces (9 and 12 lb), snap-off heights (0 and 5 mil), aperture shapes (square and circle), and aspect ratios (2.5 and 2.75). The aspect ratio is defined as the stencil opening divided by the stencil thickness. The twolevel Taguchi L8 orthogonal array with these control factors is shown in Table 10.2. 10.2.3 Paste printing and reflow

The stencil parameters, paste, and process conditions for each test run are shown in Table 10.3. The typical printed solder paste results in each quadrant are shown in Fig. 10.5. The solder pastes on the wafers are reflowed in a DIMA reflow oven. The SMT-compatible reflow temperature profile is shown in Fig. 10.6. Figure 10.7 shows the solder bumps with different stencil openings, and Fig. 10.8 shows their cross sections. It can be seen that the largest cross sections are from the stencil with 22-mil square openings and that the smallest cross sections are from the stencil with 20-mil round openings. The cross sections are about the same for both the 22-mil round openings and the 20-mil square openings. TABLE 10.1

Control Factors of L8 Taguchi Design Experiment* Control factors

Level 1

Level 2

1

Paste type

Type 3

Type 4

2

Squeeze force

9 lb

12 lb

3

Snap-off height

0 mil

5 mil

4

Aperture shape

Square

Round

5

Aspect ratio

2.50

2.75

* Stencil thickness = 8 mil.

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Chapter Ten

TABLE 10.2

Taguchi L8 Orthogonal Array Control factors

Test run

Paste type

Squeeze force

Snap-off

Shape

Aspect ratio

E1*

E2†

1

1

1

1

1

1

1

1

2

1

1

1

2

2

2

2

3

1

2

2

1

1

2

2

4

1

2

2

2

2

1

1

5

2

1

2

1

2

1

2

6

2

1

2

2

1

2

1

7

2

2

1

1

2

2

1

8

2

2

1

2

1

1

2

* E1 = error 1. † E2 = error 2.

10.2.4 Solder volume

The solder bump heights and diameters are measured by focusing the bump shadow from its cross section under a high-power microscope. The bump shadow is formed by the rear white light through a transparent molding material. Table 10.4 shows the measured raw data of the solder bump volume from the two-level L8 experiments. The formula for calculating the volume of the solder bump (i.e., trucked sphere) is π × [h3/6 + h × φ2/8], where h is the height of the trucked sphere and φ is the diameter of the sphere. TABLE 10.3

Stencil Parameter, Paste, and Process Condition for Each Run*

Test run

Paste

Force (lb)

Snap-off height (mil)

Shape

Aspect ratio

Dimension (mil)

1

Type 3

9

0

Square

2.5

20

2

Type 3

9

0

Circle

2.75

22

3

Type 3

12

5

Square

2.5

20

4

Type 3

12

5

Circle

2.75

22

5

Type 4

9

5

Square

2.75

22

6

Type 4

9

5

Circle

2.5

20

7

Type 4

12

0

Square

2.75

22

8

Type 4

12

0

Circle

2.5

20

* Stencil thickness = 8 mils.

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Solder paste geometry before reflow of four different stencil opening designs.

Figure 10.5

Figure 10.6

Reflow temperature profile.

Figure 10.7

Solder bump geometry after reflow.

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Chapter Ten

(a)

(b)

(c)

(d)

Cross sections from four different stencil openings. (a) Solder bump from a 22-mil round opening. (b) Solder bump from a 20-mil square opening. (c) Solder bump from a 22-mil square opening. (d) Solder bump from a 20-mil round opening.

Figure 10.8

The target value (signal-to-noise ratio [S/N]) of the solder bump volume is the larger the better, which is defined as −10 log [MSD], where MSD = 1/n Σ (1/y)2 is the mean square deviation, y is the measured response, and n is the number of measurements. The larger the better means that the MSD is minimized, which is the same as maximizing the S/N. 10.2.5 Data analysis of the L8 experiments

The solder bump volume data from the L8 orthogonal array experiments is analyzed by the ANOVA software. This software is a computational technique that enables someone to quantitatively estimate the relative contribution that each control factor makes to the overall measured response and to express it as a percentage. This software performs at least two analyses: ANOM (raw data) and ANOVA (signal-to-noise ratio [S/N ratio]). Table 10.5 shows the result of the ANOM, where S is the sum of the squares of the source; V is the variance of the source; S′ is the pure sum of the squares of the source; rho% is the percent contribution of the source; and F is equal to MS/Se2 (MS is the mean square of V and Se2 is the error variance). Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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TABLE 10.4

385

Solder Bump Volume* Raw Data Measurements for L8 Experience

Test run

Vol.1

Vol.2

Vol.3

Vol.4

Vol.5

Vol.6

Vol.7

Vol.8

Vol.9

Vol.10

Avg. vol.

1

3.16

3.55

3.12

3.42

3.45

3.42

3.30

3.37

3.22

3.23

3.32

2

3.33

3.17

3.05

3.25

3.25

3.39

3.39

3.44

3.38

3.38

3.30

3

3.35

3.48

3.15

3.41

3.50

3.42

3.57

3.38

3.30

3.42

3.40

4

3.03

2.96

2.99

3.06

2.90

3.03

3.21

3.25

2.99

3.03

3.04

5

4.06

3.97

3.86

4.00

4.00

3.99

3.73

4.14

3.74

3.97

3.94

6

2.55

2.56

2.48

2.33

2.2

2.25

2.33

2.34

2.57

2.58

2.42

7

3.78

3.93

3.82

3.70

3.74

3.77

3.88

3.84

3.76

3.82

3.80

8

2.47

2.39

2.31

2.26

2.55

2.40

2.26

2.34

2.46

2.46

2.39

* Volume = ×10 µm . 7

3

The ranking for the F-ratio has some physical meanings: (1) F < 1— the experimental error outweighs the source (control factor) effect; the source is insignificant and indistinguishable from the experimental error; (2) F ≈ 2—the source factor has only a moderate effect compared with the experimental error; and (3) F > 4—the source factor is strong compared with experimental error and is clearly significant. In the present study, for all of the source factors, the F-values in Table 10.5 are larger than the experimental error. Figure 10.9 shows the effect of the control factor (source) for the target value of the experiment. It can be seen that, by comparing all of the parameters, the aperture shape (circle or square) and the aspect ratio (2.5 or 2.75 [since the stencil thickness is 8 mil, which means that the opening sizes are 20 or 22 mil]) of the stencil have the biggest effects. The 22-mil square-opening stencil produces the largest solder bump volume (D1 and E2 in Figs. 10.9 and 10.10 and Table 10.1).

TABLE 10.5

Taguchi L8 ANOM (Raw Data)*

Source (factors)

S

V

F

S′

rho%

A (paste type) B (squeeze force) C (snap-off height) D (aperture shape) E (aspect ratio)

0.033 0.016 2.71E-05 1.372 0.823

0.033 0.016 2.71E-05 1.372 0.823

1219.512 591.279

0.033 0.016

1.39 0.67

1.372 0.823

57.84 34.7

e1 e2 (e)

0 0.098 2.71E-05

0.001 2.71E-05

0.096 0.002

4.05 0.08

50702.14 30413.9 36.955

* S, sum of squares of source; V, variance of source; F = S/(e); S′, pure sum of squares of source; rho%, percent contribution of source; e1, interaction error; e2, repetition error; (e), pooled error.

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Chapter Ten

Figure 10.9

Average of raw data for two-level L8 experiment.

In addition to the ANOM, the ANOVA is performed. The result of the ANOVA is shown in Table 10.6. The F-values indicate that all source factors are significantly larger than the experimental error. Figure 10.10 shows the S/N of the parameters for the target value of the experiment. Again, it demonstrates that the dominant factors for solder bump volume are the opening shape and opening size of the stencil. The role of the other parameters for solder bump volume is not important under the dominant factors. 10.2.6 Data analysis of the L4 experiments

Next, a Taguchi experiment is designed to investigate the effects of the printing process (squeeze force and snap-off height) and material (solder paste type) on solder bump volume for the 22-mil square-opening

Figure 10.10

Signal-to-noise ratios for two-level L8 experiment.

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TABLE 10.6

387

Taguchi L8 ANOVA (S/N Ratio)*

Source (factors)

S

V

F

S′

rho%

A (paste type) B (squeeze force) C (snap-off height) D (aperture shape) E (aspect ratio)

0.691 0.101 0.002 10.895 6.714

0.691 0.101 0.002 10.895 6.714

345.5 50.5

0.689 0.099

3.7 0.53

5447.5 3357

10.893 6.712

58.51 36.05

0 0 2.00E-03

2.00E-03

0.014

0.08

e1 e2 (e)

* For a definition of the variables, see the asterisked footnote in Table 10.5.

stencil. The target value of the solder bump volume is, again, the larger the better. Table 10.7 shows the control factors. Table 10.8 shows the L4 orthogonal array. Table 10.9 shows the material and process conditions for the L4 design experiment. Table 10.10 shows the solder bump volume raw data for the L4 orthogonal array. The result of the ANOM is shown in Table 10.11. The F-values indicate that the snap-off height is the only factor significantly larger than the experimental error. This is also demonstrated in the effect of the control factor (parameter) for the target value trend, as shown in Fig. 10.11. The snap-off height (5-mil difference) has a larger effect than either the squeeze pressure (3-lb difference) or the solder paste type (type 3 versus type 4). The result of the ANOVA is shown in Table 10.12. Again, the F-values indicate that the snap-off height is the only factor that is significantly larger than the experimental error. Figure 10.12 plots the S/N ratio of the parameters for the target value. Again, this figure shows that the effects of neither a 3-lb squeeze force difference nor of a paste type difference on the solder bump volume are as significant as the 5-mil snapoff height difference (C2 in Figs. 10.11 and 10.12 and Table 10.7). 10.2.7 Summary and recommendations

By choosing the paste type, squeeze pressure, snap-off height, aperture shape, and aspect ratio as the critical parameters, a two-level L8 orthogonal array experiment has been performed on the solder bumpTABLE 10.7

Control Factors of L4 Taguchi Design

Experiment Control factors

Level 1

Level 2

1

Paste type

Type 3

Type 4

2

Squeeze force

9 lb

12 lb

3

Snap-off height

0 mil

5 mil

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Chapter Ten

TABLE 10.8

Taguchi L4 Orthogonal Array Control factors

Test run

Paste type

Squeeze force

Snap-off height

1

1

1

1

2

1

2

2

3

2

1

2

4

2

2

1

TABLE 10.9

Paste and Process Conditions for Taguchi L4 Design Experiment*

Test run

Paste

Force (lb)

Snap-off height (mil)

1

Type 3

9

0

2

Type 3

12

5

3

Type 4

9

5

4

Type 4

12

0

* Based on the 22-mil square aperture.

TABLE 10.10

Solder Bump Volume* Raw Data Measurements for L4 Experiment

Test run

Vol.1

Vol.2

Vol.3

Vol.4

Vol.5

Vol.6

Vol.7

Vol.8

Vol.9

Vol.10

Avg. vol.

1

3.89

3.70

3.68

3.89

3.78

3.86

3.63

3.71

3.91

3.89

3.79

2

3.81

3.85

3.91

3.82

3.93

3.84

4.10

3.61

4.13

3.58

3.86

3

4.06

3.97

3.86

4.00

4.00

3.99

3.73

4.14

3.74

3.97

3.94

4

3.78

3.93

3.82

3.70

3.74

3.77

3.88

3.84

3.76

3.82

3.80

* Volume = ×10 µm . 7

TABLE 10.11

3

Taguchi L4 ANOM (Raw Data)*

Source (factors)

S

V

F

S′

rho%

A (paste type) B (squeeze force) C (snap-off height)

0.002 0.001 0.011

0.002 1.00E-03 0.011

2

1.00E-03

2.27

11

0.01

22.73

e1 e2 (e)

0 0.029 0.03

1.00E-03 1.00E-03

0.032

72.73

* For a definition of the variables, see the asterisked footnote in Table 10.5.

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22-mil square

Figure 10.11

Average of raw data for two-level L4 experiment.

ing of a 200-mm (8-in.) wafer by the stencil-printing method. Also, by performing the ANOM and ANOVA, the most influential factors have been determined. Furthermore, a two-level L4 orthogonal array experiment has been performed to optimize the other material and process factors. Some important results are summarized in the following: ■

For wafer-level packaging, because of the larger-pitch area-arrayed pads on the chip, wafer bumping by the stencil-printing method is not only low-cost, but it is also the logical choice, especially for larger solder bumps without an underfill encapsulant.

■

From the L8 experiments, we found that the stencil designs (size and shape) are the dominant factors for solder bump volume. The 22-mil square-opening stencil produces the largest solder bump volume without bridging (0.75-mm pitch).

■

From the L4 experiments, based on the 22-mil square-opening stencil, we found that the effect of the snap-off height on the solder bump volume is larger than the squeeze pressure and paste type.

TABLE 10.12

Taguchi L4 ANOVA (S/N Ratio)*

Source (factors)

S

V

F

S′

rho%

A (paste type) B (squeeze force) C (snap-off height)

0.011 0.006 0.054

0.011 0.006 0.054

1.833

0.005

7.04

9

0.048

67.61

e1 e2 (e)

0 0 0.006

0.006

0.018

25.35

* For a definition of the variables, see the asterisked footnote in Table 10.5.

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Chapter Ten

Signal-to-Noise R

390

Figure 10.12

■

22-mil square

Signal-to-noise ratios for two-level L4 experiment.

Alignment plays a very important role, even though it is not considered one of the critical factors in this study. Based on the present study, we found out that good alignment prevents solder bump bridging.

10.3 Wafer Bumping by Electroplating of Lead-Free Solders Wafer bumping by stencil printing is invariant to the kinds of solders, either lead-bearing or lead-free. Also, as mentioned in Chap. 9, there are many vendors who provide lead-free solder pastes at reasonable prices. This is not the case, however, for wafer bumping with electroplating of lead-free solders, where the plating chemicals are not commonly available at a reasonable cost, yet. Also, the plating process for lead-free solders is not as straightforward as for eutectic solders. In this section, the plating chemistries and the process of lead-free solder bumping with electroplating method, obtained by Karim and Schetty, are presented.14 10.3.1 Lead-free solders

Five different lead-free solder compositions are considered for wafer bumping by electroplating using a fountain plating system: (1) Sn with a melting point of 232°C; (2) Sn80-Bi20 with a melting point of 200°C; (3) Sn96.5-Ag3.5 with a melting point of 221°C; (4) Sn99.3-Cu0.7 with a melting point of 227°C; and (5) Sn95.8-Ag3.5-Cu0.7 with a melting point of 216°C. 10.3.2 Test wafer and PCB

The silicon wafer consists of chips with 20 × 20 lead-free solder bumps, each 200 µm in diameter (postreflow) and on a 400-µm pitch. These test Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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wafers are patterned with aluminum-metallized daisy chains. A 5-µmthick layer of plated copper is used as the under-bump metal (UBM). PCBs with the corresponding daisy chains are made with FR-4 and BTepoxy. 10.3.3 Electroplating of lead-free solder bumps

The key process steps reported in Ref. 14 are shown in the following: ■

Removing, through a back-sputter cleaning step, the naturally formed oxide layer on the aluminum bond pads on the wafer followed by the sputter deposition of two metal layers consisting of chrome (with a thickness of 500 Å) and copper (with a thickness of 5000 Å). These two sputtered layers effectively form the adhesion, barrier to indiffusion, and electrical buss layers (for plating).

■

Patterning the wafer, using an 80- to 100-µm-thick layer of positivetone liquid photoresist and a photomask to define the areas to be bumped.

■

Developing the thick photoresist, which provides a protective layer to areas that are not to be plated.

■

Opening the electrical contacts points (at the edges of the wafer) to the underlying sputtered copper layer followed by selective plating of a 5-µm-thick copper layer that acts as a “wettable” foundation to the lead-free solder bump upon reflow.

■

Electroplating the lead-free solder bumps using the appropriate type of plating solution, anodes, and either direct current (DC) or pulseplating techniques in a fountain (cup) plating system. The lead-free plating solutions are composed of methylsulfonic acid metal concentrates and electrolytes, and proprietary additives.

■

Removing the thick photoresist and back-etching of the exposed sputtered copper and chrome layers (by chemical etching).

■

Applying flux and reflow of the as-plated bumps in a five-zone reflow oven to form the spherical solder shape.

10.3.4 Lead-free solder bumping results

Examples of the as-plated and postreflowed lead-free Sn, Sn-Bi, and Sn-Cu solder bumps using the aforementioned fabrication process steps are shown in SEMs in Figs. 10.13 through 10.15, respectively. Some important results are summarized in the following: ■

XPS measurements on cross-sectioned and reflowed Sn, Sn-Bi, SnCu, Sn-Ag, and Sn-Ag-Cu solder bumps indicate composition uniformities within the bulk of the solders to within ⫾1 percent of the target compositions.

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(a)

(b)

(a) As-plated tin-bismuth solder bumps. (b) Reflowed tin-bismuth solder bumps.

Figure 10.13

■

The lead-free solder bumps are subjected to shear tests after multiple reflows. Results for Sn, Sn-Bi, and Sn-Cu solder bumps indicate shear values in excess of 0.05 kg for reflow of up to 10 times. The fracture locations are within the bulk of the lead-free solder bumps.

■

The lead-free solder joints are subjected to a shear test after PCB assembly of the solder-bumped chips on PCB. Results for Sn, Sn-Bi, and Sn-Cu solder joints (without underfill) indicate shear values in excess of 15 kg.

10.4 United Test and Assembly Center’s (UTAC’s) Build-Up (UBU) WLCSP15 As mentioned earlier, most of the WLCSPs use a metal layer to redistribute the pads on the silicon chip in order to reduce the PCB or subDownloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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(a)

(b)

(a) As-plated pure-tin solder bumps. (b) Reflowed pure-tin solder bumps.

Figure 10.14

strate cost and increase the next-level interconnect-manufacturing yields. Also, there is a need to deposit a UBM for good adhesion and reliability of the packaging system. The two most widely used processes for depositing a thin-metal film, either for redistribution or UBM, are physical vapor deposition (sputtering) and evaporation. Usually, these processes are expensive and are significant contributors to the cost of wafer bumping. A new WLCSP, which minimizes the cost of the bumped wafer that requires redistribution of its bond pads and at the same time offers the advantages of a wafer-level packaging solution, has been obtained by UTAC15 and is presented in this section. 10.4.1 UBU package process development

UTAC’s build-up (UBU) packaging technology is aimed at reducing the semiconductor packaging cost by using processes and technologies that Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Chapter Ten

(a)

(b)

(a) As-plated tin-copper solder bumps. (b) Reflowed tin-copper solder bumps.

Figure 10.15

are more cost-effective than what is being practiced today.1–5 UBU process, as the name signifies, is a build-up process in which a bond pad site on a silicon chip is sequentially built up to a connection with the PCB. Figure 10.16 shows the detailed process flow for the UBU packaging technology. The first step includes coating the wafer with a photoimageable dielectric (polyimide) and patterning it to create the openings on the bond pad. Following this, a plasma desmearing process is performed using O2 or O2-CF4 plasma. The desmearing process provides the surface roughening for good metal adhesion on the dielectric layer. The wafer then goes through a zincation followed by electroless nickel process to fill the dielectric openings on the bond pad. The electroless nickel provides the required interconnect between the bond pad and the next-level metallization.

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Bond Pad

Bond Pad

Figure 10.16

Process flow for UBU packaging technology.

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After the interconnect is formed, a copper seed layer is deposited on the entire wafer using a low-cost electroless copper process providing a copper thickness of about between 0.3 and 0.5 µm. The electroless bath that is used is based on hypophosphite chemistry that is more environmentally friendly as compared with conventional formaldehyde-based chemistries. A palladium colloid solution is used for activating the polyimide surface prior to the electroless copper bath. A series of process parameters regarding bath compositions and process timings is evaluated to provide a repeatable and consistent copper seed layer on the wafer. A subsequent copper electroplating process builds up the copper thickness to between 4 and 5 µm. The plated copper is patterned to define the routing from the bond pad to the solder bump array. This is followed by a final passivation process in which a photoepoxy dielectric (15 to 17 µm) is patterned to expose the solder bump pads. A final pad finish of Ni-Au is provided by using conventional PCB processing. The 0.3-mm solder bumps are then placed and reflowed to complete the packaging process. Finally, the wafer is sawed into individual packages. Figure 10.17 shows the schematic cross section of the UBU package. 10.4.2 UBU WLCSP

The UBU WLCSP test vehicle is shown in Fig. 10.18, and the design parameters are shown in Table 10.13. It can be seen that there are 160 solder bumps on a chip, and the pitch is 0.5 mm. The solder bumps’ diameter is 0.3 mm. The total package height, including solder bumps, is designed to be less than 1 mm. The polyimide used for this package is HD 2732, which provides the foundation to the copper metallization process. As discussed previously, O2 or O2/CF4 plasma is used to desmear or modify the surface in order to provide good adhesion with the copper metallization. The pure O2 plasma is more suitable for this application because it provides the required surface profile for the subsequent processing; i.e.,

Figure 10.17

Schematic cross section of the UBU package.

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Figure 10.18

397

UBU package design.

the maximum peak-to-valley distance of the polyimide layer is about 1 µm. For the UBU WLCSP, a typical electroless nickel height of between 15 and 20 µm is used, as shown in Fig. 10.19. This nickel height is desirable for a good interconnect formation. Figure 10.20 shows the copper metallization (with a thickness of between 0.3 and 0.5 µm of electroless copper and between 4 and 5 µm of electrolytic copper) on the nickel interconnect and the polyimide dielectric. Figure 10.21 shows the finished UBU WLCSP. The cross section of the solder bump on the copper with Ni-Au finish is shown in Fig. 10.22. Figure 10.23 shows the cross section of the nickel interconnection plated with copper.

TABLE 10.13

UBU Design Rule of the Test Vehicle

Wafer size

6 in

Wafer thickness

675 µm

Die size

9.00 × 9.00 mm

Bond pad pitch

254 µm

Polyimide

HD 2732

Polyimide thickness

5 µm

Final passivation

Epon SU 8

Final passivation thickness

18 µm

Ball pitch

0.50 mm

Ball diameter

0.30 mm

Package I/O

160 ball

Package thickness

<1.0 mm

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Figure 10.19

Electroless nickel bumps.

20µm Electroless copper on nickel bump.

Figure 10.20

Figure 10.21

UBU package.

Figure 10.22 Cross section of the solder bump on copper with Ni-Au finish.

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Figure 10.23

399

Cross section of the nickel bump plated

with copper.

10.4.3 Note on the UBU WLCSP

There are at least three reasons why the UBU WLCSP could be a potentially low-cost package: (1) simplicity, (2) electroless Ni-Au process, and (3) bump-mounting process. It is well known that the less process steps the less reliability issues and lower cost. Also, Ni-Au is the cheapest UBM or seed bump. Furthermore, the solder bump–mounting method is the way to go in the future of wafer bumping due to the next level of interconnection operations. The challenges of the UBU WLCSP include: (1) repeatable and reproducible Ni-Au process, (2) repeatable and reproducible electroless copper process, (3) good adhesion and robust passivation materials, and (4) copper-dielectric interface issues. 10.5 Fraunhofer IZM’s FIP-CSP The technological structure of the FAB integrated packaging (FIP) CSP (FIP-CSP) is a pad-redistributed die with a solder bump array. A stress compensation layer (SCL) embeds the solder bumps before second solder bumps are stencil-printed or mounted on top of embedded bumps. The goal of the FIP project of Fraunhofer IZM and Motorola is to develop a new WLCSP based entirely upon wafer-level processes. In this section, the design, materials, process, performance, and reliability of the FIP-CSP will be presented.19 10.5.1 Test vehicles

The test vehicle is a 1-cm2 chip, which is redistributed to a 14 × 14 solder bump array with a pitch of 0.5 mm. The PCB is made of FR-4 and is 0.5 mm thick.

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10.5.2 Process of FIP-CSP

The concept of FIP is based on the redistribution technology of Fraunhofer IZM/TU-Berlin.16–19 The principle of the redistribution process is to route the peripheral Al pad of the chip to an array arrangement of Cu-Ni-Au pads using an electroplating copper and low relative dielectric constant polymer (such as BCB) thin-film process. The routed pads end with a UBM of electroplated Ni and electroless Au. In general, the redistribution allows larger solder bumps due to the increased pitch of the redistributed I/Os. High-melting Pb-Sn solder is printed on the redistributed I/O pads of the wafer, reflowed, and cleaned, leaving an array of high lead solder bumps on the wafer, as shown in Fig. 10.24. The high-melting Pb-Sn creates a temperature hierarchy in the FIP package so that, during the reflow of the second solder bumps as well as during the PCB assembly, the solder bumps encased in the SCL do not remelt. Essential for the adhesion of the SCL is the cleanliness of the final BCB surface of the redistribution layer (RDL). Figure 10.25 shows an SEM photo of an array of reflowed high-melting Pb-Sn bumps. An SCL is applied to the wafer to form a thick layer of filled epoxy material, as shown in Fig. 10.26. After SCL curing, the height of the SCL over the high-lead solder bumps is about 200 ⫾ 10 µm (including bump height), and the height of the solder bumps is about 150 µm. Cured SCL over redistributed and bumped wafer is shown in Fig. 10.27. The SCL has three functions for the FIP-CSP:19 1. Reduction of the accumulated equivalent creep strain of the solder bumps due to the thermal expansion mismatch of the silicon die and the PCB. The SCL acts like an underfiller, but it can be applied on the whole wafer. 2. Serves as mechanical support for the second solder bump printing process to achieve taller solder heights.

10.24 Redistributed with high-lead solder bump.

Figure

wafer

Figure 10.25

High-lead sol-

der bumps.

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Microscopic view of the SCL embedding the high-lead solder bumps.

Figure 10.27

SCL deposition on highlead solder bump. Figure 10.26

3. The normal (peeling) stress of a FIP package with a matched SCL is lower compared with a package without SCL. To allow for the second solder paste printing and electrical connection, the wafer is planarized, as shown in Fig. 10.28. The height difference between the top of the polished solder bumps and the surface of the SCL is about 5 µm. The difference of the height of the solder bump arrays is below 10 µm, as shown in Fig. 10.29 The final step for the FIP package is to apply eutectic solder bumps on top of the high-lead solder pads, as shown conceptually in Fig. 10.30. A mean total height for the staggered bumps of 330 µm, as shown in Fig. 10.31, can be achieved with the solder bump prototype-mounting machine made by Fraunhofer IZM. The solder bump reflow is fluxless and on wafer level. Nitrogen acts as a shielding atmosphere leading to smooth hemispherical bumps. Figure 10.32 shows the reflowed solder bumps on the planarized SCL. A total standoff height of the solder joints of around 425 µm can be achieved, as shown in Fig. 10.33. However, it is impossible to achieve the second solder bump height of over 200 µm by

Figure 10.28

FIP wafer after planarization.

Figure 10.29 Pad array after planarization of the SCL.

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Chapter Ten

Final FIP-CSP with high-lead and eutectic solder bumps.

Figure 10.30

Cross section of the staggered solder bumps with SCL and RDL.

Figure 10.31

300-µm mounted eutectic solder bumps on FIP test vehicle.

Figure 10.32

Cross section of solder bumps using mounted eutectic solder bumps (after thermal cycling).

Figure 10.33

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stencil printing for the 0.5-mm-pitch FIP test vehicle. Figure 10.34 shows a singulated FIP-CSP. (It is noted that in this section, the solders on the chip before joining to the PCB are called solder bumps. After the solder bumps have been reflowed on the PCB, they are called solder joints.) 10.5.3 FIP-CSP component qualification tests19 10.5.3.1 Test conditions. A moisture-sensitive test for delamination failures is performed on the FIP-CSPs using the standard JEDEC level 3 test. By means of the C-mode scanning acoustic microscope (C-SAM) images, no significant changes between the initial status and the status after the JEDEC level 3 test have been observed. Also, an electrical DC test is done with 10 FIP-CSPs to confirm the results from the JEDEC level 3 test. The continuity testing is performed by selectively contacting the solder bumps, which are interconnected by the redistribution metallization using probe needles. No opens have been detected. 10.5.3.2 Air-to-air thermal cycling (AATC). To investigate the adhesion between different materials and the material stability of the SCL, a component-level test using AATC is performed. The thermal cycling condition is from −55°C to 125°C (20-min ramp and 10-min dwell). After AATC, the FIP packages are analyzed by cross section. Figure 10.35 shows an SEM picture of a cross section of the FIP-CSP after 1000 cycles. No delamination between the SCL and the RDL or solder bumps is detected. The double-bump has a zone of a Pb-Sn phase transition around 30 µm below the joining area of the bumps due to the reflow of the eutectic solder. 10.5.3.3 FIP-CSP autoclave testing. Autoclave testing (121°C at 2 atm) is performed with 20 FIP parts. Ten of the parts are exposed to MSL-1 preconditioning (168 hr, 85 percent RH, 85°C, followed by

Figure 10.34

SEM of diced FIP-

CSP.

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Cross section of FIP-CSP after 1000 cycles.

Figure 10.35

three reflows peaking at 220°C). Then, all 20 parts are electrically tested before exposure to autoclave testing. The 20 parts have been exposed to four times (each time lasting for 48 h) of autoclave testing with no visible delamination and minimal resistivity change in the nets. 10.5.4 AATC of FIP-CSP on PCB—second solder bumps made by stencil printing

Four boards with a total of 60 FIP-CSPs selected from 10 different wafers are subjected to thermal cycling between −55°C and 125°C. The percentage of failed FIP-CSPs with respect to the number of thermal cycles is shown in Fig. 10.36. Cross sections are made at different locations of a package after 700 cycles (Fig. 10.37). It can be seen that (1)

Percentage of failed shorter-standoff FIP-CSPs with respect to the number of thermal cycles (without outer row = 12 × 12 array).

Figure 10.36

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(a)

(b)

(c)

(d)

405

FIP-CSP after 700 cycles, cross section of the outermost solder row and the centric solder ball row. (a) Centric row: edge of CSP. (b) Center of CSP. (c) Outermost row: edge of CSP. (d) Center of CSP.

Figure 10.37

most of the cracks are at the interface between the upper and lower solder bumps in a solder joint, and (2) most of the cracked solder joints are at the corner of the package. (It should be noted that some of the chips don’t have the outer-row solder joints.) 10.5.5 AATC of FIP-CSP on PCB—second solder bumps made by bump mounting

In this case, everything is the same as in Sec. 10.5.4, except that the solder joint’s standoff is much taller because of the mounted solder bump (300 µm). The AATC results are shown in Fig. 10.38. It can be seen that this package performs much better than that with printed solder bumps with low standoff height. Cross sections are made at different locations on a package after 1000 cycles (Fig. 10.39). It can be seen that the failure modes are different compared with the case with smaller second solder bumps and shorter solder joints. No damage of the RDL/Si or of the PWB metallization can be seen. A drastic bump deformation of the embedded solder bumps in the solder joints is the reason for the opens during the resistance measurement in the interconnection. No cracks and fractures of the upper bumps in the solder joints are observed.

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Figure 10.38 Percentage of failed taller-standoff FIP-CSPs with respect to the number of thermal cycles (−55/125ºC) (without outer row = 12 × 12 array).

10.5.6 A note on FIP-CSP

There are at least three reasons why FIP-CSP could be a potentially low-cost and reliable package: (1) because of the SCL, the solder joint is reliable for most of the applications; (2) it uses electroless Ni-Au UBM; and (3) it uses the bump-mounting process. The challenge is to maintain the manufacturing throughput with a few additional process steps.

(a)

(b)

(c)

(d)

FIP-CSP after 1000 cycles (−55/125). (a) Centric row: edge of CSP. (b) Center of CSP. (c) Outermost row: edge of CSP. (d) Center of CSP. Figure 10.39

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10.6 References 1. Lau, J. H., Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies, McGraw-Hill, New York, 2000. 2. Lau, J. H., and S. W. Lee, Chip Scale Packages: Design, Materials, Process, Reliability, and Applications, McGraw-Hill, New York, 1999. 3. Lau, J. H., C. P. Wong, J. L. Prince, and W. Nakayama, Electronic Packaging: Design, Materials, Process, and Reliability, McGraw-Hill, New York, 1998. 4. Lau, J. H., and Y. H. Pao, Solder Joint Reliability of PBGA, CSP, and Flip Chip Assemblies, McGraw-Hill, New York, 1997. 5. Lau, J. H., Flip Chip Technologies, McGraw-Hill, New York, 1996. 6. Lau, J. H., Ball Grid Array Technology, McGraw-Hill, New York, 1995. 7. Elenius, P., J. Leal, J. Ney, D. Stepniak, and S. Yeh, “Recent Advances in Flip Chip Wafer Bumping Using Solder Paste Technology,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 260–265, San Diego, CA, June 1999. 8. Li, L., S. Wiegele, P. Thompson, and R. Lee, “Stencil Printing Process Development for Low Cost Flip Chip Interconnect,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 421–426, Seattle, WA, May 1998. 9. Wiegele, S., P. Thompson, R. Lee, and E. Ramsland, “Reliability and Process Characterization of Electroless Nickel-Gold/Solder Flip Chip Interconnect Technology,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 861–866, Seattle, WA, May 1998. 10. Kloeser, J., K. Heinricht, E. Jung, L. Lauter, A. Ostmann, R. Aschenbrenner, and H. Reichl, “Low Cost Bumping by Stencil Printing: Process Qualification for 200 µm Pitch,” Proceedings of International Symposium on Microelectronics, pp. 288–297, San Diego, CA, October 1998. 11. Cho, M., S. Kang, Y. Kwon, D. Jang, and N. Kim, “Flip-Chip Bonding on PCB with Electroless Ni-Au and Stencil Printing Solder Bump,” Proceedings of SMTA International Conference, pp. 159–164, San Jose, CA, September 1999. 12. Lau, J. H., Handbook of Fine Pitch Surface Mount Technology, van Nostrand Reinhold, New York, 1994. 13. Lau, J. H., and C. Chang, “Taguchi Design of Experiment for Wafer Bumping by Stencil Printing,” IEEE Transactions on Electronic Packaging Manufacturing, 21(3):219– 225, July 2000. 14. Karim, Z. S., and R. Schetty, “Lead-Free Bump Interconnections for Flip-Chip Applications,” Proceedings of IEEE Electronics Manufacturing Technologies Symposium, pp. 274–278, San Jose, CA, October 2000. 15. Kapoor, R., S. Khim, and G. Hwa, “A Low Cost Wafer Level Packaging Process,” Proceedings of IEEE Electronics Manufacturing Technologies Symposium, pp. 94–101, October 2000. 16. Töpper, M., M. Schaldach, S. Fehlberg, C. Karduck, C. Meinherz, K. Heinricht, V. Bader, L. Hoster, P. Coskina, A. Kloeser, O. Ehrmann, and H. Reichl, “Chip Size Package—The Option of Choice for Miniaturized Medical Devices,” Proceedings of International Symposium on Microelectronics, pp. 749–754, San Diego, CA, October 1998. 17. M. Töpper, J. Simon, and H. Reichl, “Redistribution Technology for Chip Scale Package Using Photosensitive BCB,” Future FAB 2, 1997. 18. M. Töpper, K. Heinricht, A. Kloeser, O. Ehrmann, H. Reichl, and L. Danzer, “Chip Size Package—Redistribution at Wafer-Level and Assembly,” Future Circuits International 3, 1998. 19. Topper, M., J. Auersperg, V. Glaw, K. Kaskoun, E. Prack, B. Keser, P. Coskina, D. Jager, D. Petter, O. Ehrmann, K. Samulewicz, C. Meinherz, S. Fehlberg, C. Karduck, and H. Reichl, “Fab Integrated Packaging (FIP): A New Concept for High Reliability Wafer-Level Chip Size Packaging,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 74–80, Las Vegas, NV, May 2000.

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Source: Microvias

Chapter

11 Assembly of Flip Chip on PCB/Substrate

11.1 Introduction Since the publication by Tsukada et al.1 in 1992, the electronic packaging industry has witnessed an explosive growth in the research and development efforts devoted to solder bumped flip chip on low-cost PCB or organic substrate. Theoretically speaking, the solder-bumped flip chip on organic PCB/substrate1–36 is one of the most cost-effective electronic packaging techniques. However, because of the very large thermal expansion mismatch between the silicon chip (2.5 × 10−6/°C) and the epoxy PCB (18.5 × 10−6/°C), underfill encapsulant is usually needed for solder joint reliability.1–36 Unfortunately, due to the underfill operation, the manufacturing throughput is reduced and the rework of an underfilled flip chip on PCB is very difficult, if not impossible. Even though the research efforts on fast-flow, fast-cure, reworkable underfill materials are very active,1–8,11,13–15,27,28 most of them are using solvent chemical, and most of the chips (such as passivation) and substrates (such as solder mask, via, and copper pads and traces) are degraded or even damaged after rework. These issues indicate that more work needs to be done in these areas. In this section, the reworkable underfill materials from two different vendors are considered. As to the manufacturing throughput issue, fast-flow and fast-cure underfill encapsulants are on their way.19,20,22–25 However, the material properties of these underfills can be degraded (due to excessive or large voids, too high a thermal coefficient of expansion, and too low a Young’s modulus) and thus affect the mechanical and physical properties of the solder-bumped flip chip on PCB/substrate assemblies. At the same 409

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time, a class of no-flow underfill encapsulant materials is emerging. The advantages of no-flow underfills are that they reduce manufacturing processing steps and increase production throughput. The work done at the Georgia Institute of Technology19,20,23,24,33–36 will be presented in this section. 11.2 Flip Chip on PCB/Substrate with Reworkable Underfills In this section, the fast-flow, fast-cure, and reworkable underfill materials from two different vendors are considered. Emphasis is placed on the determination of the curing conditions such as temperature and time, and the material properties such as the CTE, storage modulus, loss modulus, glass transition temperature (Tg), and moisture uptake of these underfill materials. Also, the key elements and steps of the solderbumped flip chips on low-cost substrates with these underfill materials such as the chip, PCB, flip chip assembly, and underfill application are presented. Furthermore, the key elements and steps of the rework of the solder-bumped flip chip assemblies with these underfill materials such as chip removal, chip reballing, substrate cleaning, and new chip placement are discussed. Finally, shear test results of the assemblies with one-time rework and no rework are presented. 11.2.1 Underfill materials

Two different fast-flow, fast-cure, and reworkable underfills, namely, underfill A and underfill B, are considered. Both of them are SMT compatible, and consist of epoxy, filler, and anhydride hardener. Underfill A contains 30 percent fillers, and underfill B contains no filler. The function of the cured epoxy and hardener is to act as a structural adhesive. This provides the necessary strength to hold the chip and the substrate together such that the solder joints are subjected to the minimum relative displacements. Since there are very low or even no filler contents in the materials, their storage modulus is very small and their CTE is very large. 11.2.2 Curing conditions

To determine the curing conditions of underfills A and B, they are placed into an aluminum pan (which will form a disc sample with the following dimensions: 6.4 ⫾ 0.2 mm in diameter and 1.6 ⫾ 0.1 mm in thickness), weighed, and then placed in a DSC. The objective of the DSC is to measure the amount of energy (heat) absorbed or released by a sample as it is heated, cooled, or held at a constant (isothermal) temperature. Since the system is always directly measuring energy flow to or from the sample, the DSC can directly measure tempera-

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ture onset of curing. The kinetic software enables us to analyze a DSC peak to obtain specific kinetic parameters that characterize a reaction process. Figure 11.1 shows the DSC thermal scan curves, and it can be seen that the peak of curing temperature of underfills A and B is 143.2°C and 119.1°C, respectively. Thus, underfill A needs a higher temperature to be cured than underfill B. In general, lower curing temperatures lead to lower thermal stresses in the assembly. Because the curing reaction results in a characteristic exothermic peak as heat is released during the curing process, based on kinetic calculations, the heat flow–versus–temperature curves can be converted to the percent reaction–versus–time curves (100 percent reaction means fully cured). Figures 11.2 and 11.3 show, respectively, a set of percent reaction–versus–time curves of underfills A and B with different curing temperatures. It can be seen that for 5 min of curing time at temperatures of 150°C and 165°C, respectively, the percent reactions are 98.7 and 99.6 percent for underfill B, and are 92.7 and 99.1 percent for underfill A. The larger difference in percent reaction of underfill A is due to its higher peak of curing temperature. 11.2.3 Material properties

The material properties such as the CTE, storage and loss moduli, tan δ, Tg, and moisture uptake of underfills A and B are determined in Secs. 11.2.3.1 through 11.2.3.4.

Figure 11.1

DSC thermal scan curves for underfills A and B.

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Chapter Eleven

Figure 11.2

Degree of conversion–vs.–time curves for underfill A.

11.2.3.1 CTE. The CTE of underfills A and B (with sample dimensions of 6.4 ⫾ 0.2 mm in diameter and 1.6 ⫾ 0.1 mm in height) is determined by TMA in an expansion quartz system (50 to 200°C) at a 5°C/min heating rate. The CTE is obtained by the first slope of the dimensional change–versus–temperature curve.

Figure 11.3

Degree of conversion–vs.–time curves for underfill B.

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Figure 11.4 shows the expansion curves of underfills A and B. It can be seen that the CTEs of underfills A and B are 81.5 × 10−6/°C and 101.2 × 10−6/°C, respectively. They are very large in comparison with that of the conventional underfills (20 ∼ 40 × 10−6/°C).26–29 This is because there are very low filler (underfill A) or even no filler (underfill B) contents in the reworkable underfills. For better solder joint thermal fatigue reliability, it is preferable to have lower CTE underfill materials (≤27 × 10−6/°C) because of the thermal expansion mismatch among the Si chip, underfill, solder joints, and PCB.29 11.2.3.2 Moduli. The storage modulus and loss modulus of underfills A and B can be determined with a three-point bending specimen ([3.0 ⫾ 0.3 mm] × [2.9 ⫾ 0.3 mm] × [19 ⫾ 3 mm]) in a DMA unit (50 to 200°C) at a heating rate of 5°C/min. The flexural storage modulus is a measure of the energy stored per cycle of deformation, and the flexural loss modulus is a measure of the energy lost per cycle of deformation. Figure 11.5 shows the flexural storage modulus of underfills A and B. It can be seen that the storage modulus of all the reworkable underfill materials is temperature dependent—the higher the temperature the lower the modulus. Also, the storage modulus of all the reworkable underfill materials is smaller than that of the conventional underfill materials (4 ∼ 7 GPa), because there are very low filler (underfill A) or even no filler (underfill B) contents in the reworkable underfills.26–29 High CTE and low modulus are not favorable for solder joint thermal fatigue reliability.

Figure 11.4

Expansion curves for underfills A and B.

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Chapter Eleven

Figure 11.5

Flexural storage moduli of underfills A and B.

11.2.3.3 Tg. Tangent delta (tan δ), which is a measure of the materialrelated damping property, of underfills A and B can be obtained by dividing the loss modulus by the storage modulus. The temperature at the peak of a tan δ curve is often reported in the literature as Tg. Figure 11.6 shows the typical tan δ curves of underfills A and B. It can be seen that since the Tg curve for underfill A is wider than that of

Figure 11.6

Tangent delta curves for underfills A and B.

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underfill B, then the stiffness of underfill A is worse. This is because the stiffness of underfill A becomes softer during a wider transition temperature range. On the other hand, the Tg (94.4°C) for underfill A is slightly higher than that (85.2°C) for underfill B. However, it should be noted that the Tg of underfills A and B is much lower than that of the conventional underfills (140 ∼ 180°C).26–29 High Tg is favorable for endurance in higher-temperature environments. 11.2.3.4 Moisture content. Two sets of tests are carried out for determining the moisture content of underfills A and B, one is for a dry specimen and the other is for a steam-aged specimen. The steam-aged specimen is prepared under steam evaporation for 20 h in a closed hotwater bath. The packages are not immersed in hot water. They are placed on a metal mesh that is above the water surface. Steam is generated by boiling the water. All packages are exposed within the evaporated steam. (It has been shown that this condition is equivalent to the 85°C/85%RH for 168 h.28) All of the specimen dimensions are 6.4 ⫾ 0.2 mm in diameter and 1.6 ⫾ 0.1 mm in height. Weight loss of underfills A and B is measured with the thermal gravimetric analysis (TGA) equipment under 104°C for 4 h. The change in weight during a thermal scan can be expressed as

(Wf − Wi)/Wi where Wf is the final weight after a thermal scan, and Wi is the initial weight before a thermal scan. Figures 11.7 and 11.8, respectively, show

Figure 11.7

Moisture absorption for underfills A and B (before steam aging).

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Chapter Eleven

Figure 11.8

Moisture absorption for underfills A and B (after 20 h steam

aging).

the percent weight loss (moisture content) of underfills A and B before and after 20 h of steam-aging. It can be seen that, for dry conditions, the moisture absorption of underfills A and B are, respectively, 0.2 and 0.1 percent. For steam-aging condition, the moisture absorption of underfills A and B are, respectively, 3.1 and 1.9 percent. Thus, the moisture content of underfills A and B after 20 h of steam-aging is much more than before (the dry condition). Also, they absorb more moisture than the conventional underfills (<0.1 percent for dry condition and 0.3 ∼ 0.5 percent for steam-aging condition).26–29 Low moisture absorption underfills can extend shelf life and are preferable. 11.2.4 Flip chip on board assembly

The design, materials, and assembly process flow of the solder-bumped flip chip on PCB are shown in Fig. 11.9. Some of the major steps will be discussed in the following sections. Test chip. The test chip dimensions are 5 × 4.2 × 0.5 mm. It has peripheral-arrayed pads (0.12 × 0.12 mm). The passivation opening is 0.1 × 0.1 mm. The Sn63-Pb37 solder bumps are deposited by the electroplating method.32 The average bump height is 0.094 mm (Fig. 11.10). The average shear strength is 63 g, as shown in Fig. 11.11. (The shear blade speed is 100 µm/s, and the shear blade tip is 25 µm from the chip surface.) The failure location is in the solder and not at the terminal metals. A real chip with solder bumps can be seen in Fig. 11.12. 11.2.4.1

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Figure 11.9

417

Solder-bumped flip chip on board with reworkable underfill process.

In this book, the solders on the chip before it is joined to the substrate are called solder bumps. After the solder bumps have been reflowed on the substrate, they are called solder joints. 11.2.4.2 Test board. The corresponding test board for the test chip is shown in Fig. 11.13 and is made of BT. The thickness of the test board is 0.5 mm. The size of the copper pad is 0.1 mm in diameter, and the solder mask opening is 0.16 mm (i.e., non-solder-mask-defined copper pads). The finishing condition of the copper pads is Ni/Au. 11.2.4.3 Flip chip assembly. Before fluxing on the PCB and pick-andplace of the chip, both the solder-bumped chip and the corresponding

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Chapter Eleven

Figure 11.10

Solder-bump height.

PCB are cleaned by isopropanol to reduce particle contamination. (Also, the PCB is baked at 125°C for 24 h.) In this study, a no-clean flux is applied to the PCB. Pick-and-place of the chip is operated on a flip chip bonder with a look-up and look-down camera for alignment. The alignment accuracy is within ⫾12 µm. Upon finishing alignment, the solder-bumped chip is flipped down to the PCB. After fluxing and pickand-place, the flip chip on PCB is placed on the conveyor belt of a reflow system with a nitrogen gas environment (even though it is not necessary) for reflowing the solder bumps.

Figure 11.11

Solder-bump strength.

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Figure 11.12

419

Test chip with sol-

der bumps.

Due to the very large thermal expansion mismatch between the silicon chip and the laminate organic substrate, the solder joints are subjected to a very large deformation and may crack. To ensure the solder joint reliability, underfill encapsulant is usually used to cement the chip on the substrate. In that case, the encapsulant is not only preventing the solder joints from cracking but also protecting the chip from moisture, ionic contaminants, radiation, and hostile operating environments such as mechanical shock and vibrations. The average standoff height of the solder joints is about 0.08 mm. The assembled flip chip is placed on a hot plate at 90°C. Approximately 0.025 cc of room temperature reworkable underfill is beaded around two chip sides using a syringe in an L pattern. Both underfills are cured at 165°C for 20 min. Thus, according to their characteristics shown in Sec. 11.2.2, they should be fully cured.

Figure 11.13

Test board.

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Chapter Eleven

11.2.4.4 Shear tests and results. The Royce Instruments Model 550 is used to perform the mechanical shear tests. The shear wedge is placed very close to the substrate and against one edge of the solder-bumped flip chip with underfill on the BT substrate, which is clamped on the stage. A push of the wedge is applied to shear the chips, bumps, or underfill away. The speed of the shear wedge is 150 µm/s, and the shear blade tip is 100 µm from the substrate surface. A set of typical force displacement curves is shown in Fig. 11.14 for underfills A and B. It can be seen that the shear force (strength) of underfill A (304 N) is much smaller than that of underfill B (510 N). This is because the modulus of underfill A is smaller than that of underfill B. It should be noted that the shear force of most of the conventional underfills is larger than 510 N.26–29 11.2.5 Rework

Some of the solder-bumped flip chip assemblies obtained in Sec. 11.2.4.3 are used to perform rework experience. The chip removal, chip reballing, substrate cleaning, new chip placing, and shear test results are discussed in Secs. 11.2.5.1 through 11.2.5.5. 11.2.5.1 Chip removal. Removing the chip is easy. Simply heat the solder-bumped flip chip with the reworkable underfilled assembly from

Average shear load–displacement curves of the assemblies with reworkable underfills A and B (no rework).

Figure 11.14

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25°C to between 210°C and 220°C in 4 min, and keep it at a high temperature for 30 s. The reworkable underfill would become softened (but the conventional underfills would not) and could be removed easily by twisting the chip with a twister. Figure 11.15a shows the chip surface after it has been removed from the substrate for underfill A. It can be seen that there are many underfill residues on the chip surface. An enlarged picture of the chip surface is shown in Fig. 11.15b. It can be seen that there are some solder mask residues peeled off from the substrate. In this study, there are no passivation peel-off nor Al pad and UBM failures. Similar phenomena are observed for underfill B. 11.2.5.2 Chip cleaning and reballing. If the chip is bad, then it can be thrown away and a new solder-bumped chip should be used. However,

(a)

(a) Chip surface with messy underfill residues after chip removal. (b) Enlarged photo showing some solder masks peeled off from the PCB.

Figure 11.15

(b)

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Chapter Eleven

if the chip is good and expensive, then it should be cleaned and reballed (just like the ball grid array package). Unfortunately, almost none of the reworkable underfill vendors took this into consideration. Because the silicon chip is very brittle, it cannot withstand the mechanical brushing like that on the substrate surface (which will be discussed in the next section). Strong solvent might be needed to dissolve the underfill’s residues on the chip surface. Also, because the solder bumps on the flip chip surface are very small (∼100 µm), most of the conventional solder ball mounter cannot be used for reballing. (However, for the flip chip to be popular and low in cost, wafer bumping and chip reballing by microball mounting method32 is a must! A few equipment and micro–solder ball vendors are working in this direction.) Meantime, PAC TECH GmbH developed a new laser-bumping repair system that can bump a 200-mm wafer with a ball diameter down to 100 µm at the speed of 100 balls/s. This system can be utilized as a repair station. It allows a selective removal of defective solder joints by means of laser reflow and vacuum. The removed solder is sucked off through the capillary and is stored in a small waste disposal. At the same time, a nitrogen flow prevents the oxidation of the pad surface. After removing the defective solder joint, the bond head drives the capillary exactly above the pad position, then solder balls from the loading station are singulated through a singulation unit simultaneously. Using a pneumatic pulse, the ball is transported from the singulation unit down to the tip of the capillary. The reflow of the solder ball is performed by a Nd:YAG laser beam, which passes through a glass fiber into the capillary directly above the placed ball and then reflows the solder ball. Also, with PAC TECH’s machine, single-point touch-up on the wafer or chip is possible. 11.2.5.3 Substrate cleaning. After the chip is removed from the BT substrate, an electric rotary tool equipped with a stiff-horsehair flatend brush is used to mechanically remove the adhesive from the substrate surface. After brushing, isopropanol is used to wipe out the dirt. Figure 11.16a shows the substrate surface (before cleaning) with underfill A right after chip removal. It can be seen that there are many underfill residues on the substrate surface. Figure 11.16b is an enlarged picture of Fig. 11.16a, showing that some of the solder masks have been peeled off and that some of the copper traces are exposed. Figure 11.16c shows the substrate surface after it has been cleaned with the method just mentioned. It can be seen that more solder masks are peeled off and, thus, more copper traces are exposed. Figure 11.17a shows the top left-hand corner of another substrate surface (before cleaning) with messy underfill residues. Figure 11.17b

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(a)

(b)

(a) PCB surface with messy underfill residues after chip removal (before cleaning). (b) Enlarged photo showing copper traces without solder masks (before cleaning). (c) Enlarged photo showing exposed copper traces after cleaning. Figure 11.16

(c)

shows the substrate surface after brush cleaning, and Fig. 11.17c shows the enlarged photo of one of the copper pad surfaces. It can be seen that some underfill residues (that are not easily removed) still adhere on the copper pad surface. Similar phenomena are observed for underfill B. 11.2.5.4 New chip placement. Placement process of a new solderbumped chip on the reworked substrate is the same as that illustrated in Sec. 11.2.4.3, “Flip chip assembly.” However, after solder reflowed,

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Chapter Eleven

(a)

(b)

Figure 11.17 (a) PCB surface with messy underfill residues after chip removal (before cleaning). (b) Enlarged photo showing the underfill residues on the copper pads after brush cleaning. (c) A closer look at the copper pad with underfill residues. (c)

the electrical continuity tests show that some of the solder joints are opened. Figure 11.18a shows the substrate surface (with messy underfill A residues) after the chip has been removed. Figure 11.18b is an enlarged photo of Fig. 11.18a, which shows that there are no solder

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(a)

(b)

(a) One-time rework PCB surface after the chip has been removed. (b) Enlarged photo showing the underfill residues on copper pads. (c) A closer look at the copper pad with underfill residues.

Figure 11.18

(c)

residues on the copper pad. This copper pad is further enlarged in Fig. 11.18c, which clearly shows that, because of the underfill residues, the solder bump cannot wet on the copper surface. This could be due to the brush not being fine enough to brush out the underfill residues from the copper pad surface. Similar phenomena are observed for underfill B. 11.2.5.5 Shear tests and results. Shear tests are performed on the solder-bumped flip chip assemblies with the reworkable underfills. Some have one-time rework and some are without rework. The average results are shown in Figs. 11.19 and 11.20, respectively, for underfills A

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Chapter Eleven

Average shear load–displacement curves of the assemblies with reworkable underfill A (one-time rework and no rework).

Figure 11.19

and B. It can be seen that, for both underfills, the shear force (strength) for the assemblies without rework is larger than that for the assemblies with one-time rework. This could be due to the degradation and damage of the substrate (reduction of adhesion) and the opening of the solder joints.

Average shear lead–displacement curves of the assemblies with reworkable underfill B (one-time rework and no rework).

Figure 11.20

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11.2.6 Summary

The characteristics of two different epoxy-based reworkable underfills used for solder-bumped flip chips on low-cost substrates have been studied. Emphasis has been placed on the curing temperature and time, CTE, storage and loss moduli, tan δ, Tg, and moisture absorption of these materials. Also, the design of the silicon chip and PCB, and the key flip chip assembly and rework process steps such as fluxing, solder reflowing, underfilling, chip removing, chip reballing, substrate cleaning, and new chip placement have been provided. Furthermore, the solder-bumped flip chip assemblies with one-time rework, as well as those with no rework, have been subjected to shear (destructive) tests. Some important results are summarized as follows: ■

For the reworkable underfills considered, the heat flow changes with heating rate changes.

■

For the reworkable underfills considered, the underfills cure faster at higher temperatures.

■

For the reworkable underfills considered, their CTE is much higher than that of the conventional underfills.

■

For the reworkable underfills considered, their storage modulus is temperature dependent and is much lower than that of the conventional underfills.

■

For the reworkable underfills considered, their Tg is much lower than that of the conventional underfills.

■

For the reworkable underfills considered, their moisture absorption is higher than that of the conventional underfills.

■

Since low CTE and high modulus are favorable for solder joint thermal fatigue reliability, it is recommended that the vendors lower the CTE and increase the modulus of their reworkable underfills.

■

Since high Tg is favorable for endurance at higher temperature environments, it is recommended that the vendors raise the Tg of their materials.

■

The vendors should lower the moisture absorption of their reworkable underfills to extend the shelf life.

■

With the reworkable underfills considered, even though the chip removal is easy, some solder masks are peeled off from the substrate and the copper traces are exposed. In addition to developing a better chip-removing method, the vendors should develop reworkable underfills that are more user friendly and that create less damage on both the chip and the substrate.

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Chapter Eleven

■

Since chip reballing is often required, the vendors should develop their reworkable underfills, which are not only easy to be cleaned off from the substrate, but also from the chip.

■

With the reworkable underfills considered, substrate cleaning is not easy. Because of the taller solder mask (than the copper pad) and the very small diameter of the copper pad, the underfill residues on the copper pad are very difficult to remove with an electrical rotary tool equipped with a stiff-horsehair flat-end brush. In addition to having a better design of the solder mask–copper pad on the substrate and developing a better cleaning method, the vendors should develop reworkable underfills that are more easily cleaned off from the substrate.

■

The shear force of the assemblies with the reworkable underfills considered (without rework) is smaller than that with the conventional underfills.

■

The shear force of the assemblies with the reworkable underfills considered (without rework) is larger than that with one-time rework.

11.3 Flip Chip on PCB/Substrate with No-Flow Underfills A schematic demonstrating a no-flow underfill assembly process developed at the Georgia Institute of Technology19,20,23,24,33–36 is shown in Fig. 11.21. The process begins with depositing a controlled geometry and amount of liquidlike no-flow underfill on a PCB/substrate. Possible deposition methods include stencil printing, jetting, and dispensing. A flip chip is then placed onto the PCB/substrate with a high-speed flip chip system. This process compresses the underfill, forming fillets, which promotes chip adhesion to the PCB/substrate. Finally, the assembly is sent through the reflow oven, which simultaneously

Figure 11.21

Schematic of GIT’s no-flow underfill assembly process.

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429

reflows the solder interconnects and cures the underfill, thus bonding the chip to the PCB/substrate. Six test vehicles and four reliability tests are used to evaluate and analyze the reliability performance of several commercial no-flow underfill materials. Different test vehicles are used to evaluate the effect of varying chip size, interconnect density, pad surface finish metallization, and solder mask opening design. Accelerated reliability tests such as liquid-liquid thermal shock (LLTS), air-air thermal cycling (AATC), moisture sensitivity preconditioning, and temperature-humidity (TH) aging are performed. 11.3.1 Test chip

Four different test dies are used to evaluate the effect of bump pitch, bump layout, and chip size on reliability. All test dies are daisy-chained devices with tin-lead eutectic solder bumps and silicon nitride passivation. The UBM consists of an aluminum–nickel-vanadium–copper system. The daisy-chained structure allows continuity measurements to be taken. The specifications of the test die are shown in Table 11.1. 11.3.2 Test vehicles

Six different test vehicles are used to evaluate the effect of chip size, bond pad metallization, and bond pad definition on reliability. The PB8-4 chip is used on three different test vehicles, and the remaining chip types are used on one test vehicle each. The important variables for each test vehicle are listed in Table 11.2. All of the test vehicles utilize high-temperature FR-4 substrate with a Tg of 180°C. The substrate thickness for the six test vehicles is approximately 787 µm (31 mil). The OSP is between 0.05 and 0.13 µm thick. The Cu-Ni-Au boards have an electrolytic nickel layer approxi-

TABLE 11.1

Chip type

Test Die Used for Reliability Testing Chip size (mm)

Bump count

Bump pitch (µm)

Bump layout

PB8-4

10.16

352

200 (8 mil)

Perimeter

PB8-2

5.08

88

200 (8 mil)

Perimeter

FA10-4

10.16

1268

250 (10 mil)

Area

FA10-2

5.08

317

250 (10 mil)

Area

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Chapter Eleven

TABLE 11.2

Test Vehicles

Test vehicle

Chip type

Metallization on PCB

PCB bond pad definition

TV1

PB8-4

Cu-Ni-Au

Circular mask

TV2

PB8-4

Cu-Ni-Au

Rectangular mask

TV3

PB8-4

Cu-OSP

Circular mask

TV4

PB8-2

Cu-Ni-Au

Rectangular mask

TV5

FA10-4

Cu-Ni-Au

Rectangular mask

TV6

FA10-2

Cu-Ni-Au

Rectangular mask

mately 3.8 µm thick and an immersion gold layer between 0.05 and 0.30 µm thick. Figure 11.22 shows an example of a circular defined bond pad and a rectangular defined bond pad. 11.3.3 No-flow underfills

Seven no-flow underfills are evaluated in this study (Table 11.3). All but one are supplied by commercial vendors. All of these materials are dispensed during assembly with a controlled geometry and volume. Two of the materials studied require a postcure of 30 min at 160°C. 11.3.4 Flip chip assembly

Before assembly, the test vehicles are baked out for 1.5 h at 125°C to drive off any entrapped moisture and solvents. Both substrates and die are stored in a desiccant chamber prior to use. A controlled amount of underfill is dispensed on each bond site using a CAM/ALOT 3800 automated dispense system with a 22-gauge needle. Two different dispense patterns are used during processing. The underfill amount necessary is determined by the chip size, bump layout, and the bump height.

Copper Trace (covered soldermas)

Copper Trace (covered soldermas)

Soldermas

FR-4 Bond Soldermas

Bond

(a)

(b)

(a) Circular mask opening. (b) Rectangular mask opening.

Figure 11.22

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TABLE 11.3

431

No-Flow Underfills

Underfill

Postcure used

A

No

B

Yes

C

No

D

No

E

No

F

No

G

Yes

Following underfill dispense, the flip chips are placed on the boards using either a K&S 6900 Flip Chip Bonder or a high-speed Siemens F5 with a DCA placement system. Previous work has shown that placement force and dwell (bond) time can have an effect on yield when processing with a no-flow underfill. Table 11.4 lists the placement forces used for the different test chips. After placement, the substrates are reflowed, simultaneously curing the underfill and forming the solder interconnects. The reflow profile used is determined by the chemistry of the underfill. For this study, three different profiles are used: (1) a rapid-ramp profile, (2) a conventional-step eutectic-style profile, and (3) a low-soak-temperature eutectic profile. All reflow profiles use an ambient-air environment without nitrogen inerting. A postcure step for 30 min at 160°C is used for underfills B and G. 11.3.5 Test methods

Several different standard accelerated tests are used to evaluate the no-flow underfills. Table 11.5 summarizes the series of tests used. LLTS testing is performed using an ESPEC TSB5 environmental test chamber. Test conditions are from +125°C to −55°C with 5-min dwells in each bath. AATC is performed using a Thermotron ATS-320-DD test chamber. Test conditions are from +125°C to −55°C with 10-min dwells TABLE 11.4

Placement Forces

Test die

Placement force

PB8-4

800–1600 g

PB8-2

400–1000 g

FA10-4

800–1600 g

FA10-2

400–1000 g

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at each temperature. TH aging is performed in a Thermotron SM-8C test chamber. Test conditions are 85°C and 85%RH for a total of 1000 h. Finally, moisture preconditioning tests are done at levels 1 and 3 according to J-Standard-020 Revision A. 11.3.6 C-SAM analysis, continuity testing, and failure criteria

During accelerated life testing, test vehicles are tested for electrical continuity and examined with an acoustic microscope. Every 100 h or 100 cycles, electrical continuity is checked. A change in resistance of greater than 5 percent is classified as a failure. Every 200 cycles, a sample of the test vehicles is examined with a Sonoscan D6000 acoustic microscope using a 180- or 230-MHz transducer. Scans are taken at the die/underfill interface to investigate delamination, void growth, die cracking, and underfill cracking. The underfill-to-substrate interface is also scanned. After scanning, test vehicles being subjected to AATC and LLTS are baked out for a minimum of 2 h at 80°C before testing continues. This is done to drive off trapped moisture introduced by the C-SAM, which could induce early failures. 11.3.7 LLTS results

Table 11.6 summarizes the reliability data for four no-flow underfills subjected to LLTS using the PB8-4 test die with Cu-Ni-Au metallization and circular solder mask–defined pads (TV1). Under this set of conditions, underfill E performed the best by a slight margin with the Weibull characteristic life Θ. α is the Weibull slope.30

TABLE 11.5

Reliability Test Methods and Conditions Industry standard

Test conditions

Cycle time

Reliability test Air-to-air thermal cycling

JESD22 A104-A

+125 to −55°C

20 min

Liquid-to-liquid thermal shock

JESD22 A106-A

+125 to −55°C

10 min

Temperature/ humidity

JESD22 A101-B

85°C/ 85% RH

100 h

Level 1 preconditioning

J-STD 020-A

85°C/ 85% RH

168 h

Level 3 preconditioning

J-STD 020-A

30°C/ 60% RH

192 h

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Table 11.7 summarizes data for four no-flow underfills on TV2 with a rectangular solder mask opening consisting of a hybrid mask and metal-defined pad. In this case, underfill C performed worse on boards with rectangular openings (600 cycles) compared with boards with circular openings (1000 cycles; Table 11.6), as in comparing TV1 and TV2. The results for Cu-OSP are summarized in Table 11.8. Comparing the effect of substrate metallization, using Tables 11.6 and 11.8, on the Weibull characteristic life Θ shows that underfill C performed slightly worse on Cu-OSP (1832 cycles) relative to Cu-Ni-Au (1991 cycles), whereas underfills E and F performed slightly better. Again, underfill TABLE 11.6

Weibull Parameters for TV1 (PB8-4-Au-Circular) Subjected to LLTS Underfill

Θ

α

Cycles to first failure

C

1991

4.4

1000

D

1930

3.9

1000

E

2037

3.5

1000

F

1766

5.5

1100

TABLE 11.7

Weibull Parameters for TV2 (PB8-4-Au-Rectangular) Subjected to LLTS Underfill

Θ

α

Cycles to first failure

A

1550

3.9

600

B

972

3.0

100

C

1184

5.4

600

G

2212

5.1

1200

TABLE 11.8

Weibull Parameters for TV3 (PB8-4-OSP-Circular) Subjected to LLTS Underfill

Θ

α

Cycles to first failure

A

1375

4.8

600

C

1832

5.5

1000

E

2166

5.2

1100

F

1843

6.0

800

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Chapter Eleven

E is the best performer, followed by underfill C. Figures 11.23, 11.24, and 11.25, respectively, show the Weibull plots for TV1, TV2, and TV3 subjected to LLTS. Underfill C is tested on all six test vehicles to examine the effects of bump geometry, chip size, metallization, and pad definition on reliabil-

Figure 11.23

Weibull plot for TV1 subjected to LLTS.

Figure 11.24

Weibull plot for TV2 subjected to LLTS.

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Figure 11.25

435

Weibull plot for TV3 subjected to LLTS.

ity performance. The data show as expected, that with all other variables equal, smaller dies are more reliable than larger dies. The Weibull characteristic life Θ for the FA10-2 is approximately 400 cycles longer than the FA10-4. Similar results hold for the PB8-4 test die as well, with an approximate difference in Θ of 300 cycles. Underfill C is also more reliable on the PB8-4 format with circular solder mask–defined pads relative to a hybrid defined pad, with a difference in Θ of approximately 800 cycles. These results are summarized in Table 11.9 and Fig. 11.26.

TABLE 11.9

Weibull Parameters for Underfill C on All Test Vehicles Subjected to LLTS Chip

Pad definition

PCB metallization

Θ

α

PB8-4

Circular

Cu-Ni-Au

1991

4.4

PB8-4

Rectangular

Cu-Ni-Au

1184

5.4

PB8-4

Circular

Cu-OSP

1832

5.5

PB8-2

Rectangular

Cu-Ni-Au

1509

3.3

FA10-4

Rectangular

Cu-Ni-Au

1295

7.8

FA10-2

Rectangular

Cu-Ni-Au

1685

6.0

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Chapter Eleven

Figure 11.26 Weibull plot for underfill A on all test vehicles subjected to LLTS.

11.3.8 AATC results

AATC results on TV2 (PB8-4-Au-rectangular) are shown in Table 11.10 and Fig. 11.27. In general, performance in AATC is substantially worse for all of the underfills tested. Underfills C, A, and G had first failure 300 cycles earlier in AATC (Table 11.10) than in LLTS (Table 11.7), and their Θ is reduced by 300 to 900 cycles. The more rapid failure rate may be attributed to the longer dwell time in AATC, which accelerates solder creep and increases solder fatigue. Hybrid pads impart a larger stress concentration, which could also promote more rapid joint fatigue. Three additional underfills (D, E, F) are tested on TV1 (PB8-4-Aurectangular). The time to first failure is lower than it was in LLTS (Table 11.6) for underfills F and D, as shown in Table 11.11. Underfills D, E, and F are also being tested on TV3 (PB8-4-OSP-circular) with no failures as of 900 cycles. TABLE 11.10

Weibull Parameters for TV2 (PB8-4-Au-Rectangular) Subjected to AATC Underfill

Θ

α

Cycles to first failure

A

800

3.8

300

B

1040

2.8

100

C

823

3.3

300

G

1336

7.8

900

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Figure 11.27

437

Weibull plot for TV2 subjected to AATC.

11.3.9 85∞C/85%RH test data

In addition to LLTS and AATC testing, TH testing is also performed. The no-flow underfills tested do not appear to be susceptible to the 85°C/85%RH test condition, as shown in Tables 11.12 and 11.13. Underfills C and A are also subjected to J-STD-020A levels 1 and 3 preconditioning. As the data in Table 11.14 show, both underfills passed level 3 preconditioning. Underfill A comes very close to passing level 1 preconditioning, with only one chip failing after reflow. Underfill C has over 50 percent of the assemblies passing level 1 preconditioning. 11.3.10 Solder fatigue

The dominant failure mode for flip chip assemblies using no-flow underfills is solder fatigue cracking. Ultimately, solder fatigue cracking is responsible for all electrical failures observed in test vehicles subjected to LLTS and AATC. All of the electrical failures produced during TABLE 11.11

Weibull Parameters for TV1 (PB8-4-Au-Rectangular) Subject to AATC Underfill

Θ

α

Cycles to first failure

D

NA

NA

600

E

NA

NA

800

F

NA

NA

600

Data as of 1100 cycles AATC.

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Chapter Eleven

TABLE 11.12

TH Data for TV3 (PB8-4-OSP-Circular) Underfill

Failures at 1000 h/ total sample size

A

0/32

C

0/32

D

0/20

E

0/20

F

0/20

TABLE 11.13

TH Data for TV1 (PB8-4-Au-Circular) Underfill

Failures at 600 h/ total sample size

D

0/20

E

0/20

F

0/20

TABLE 11.14

J-STD 020 Preconditioning Data for TV3 (PB8-4-OSP-Circular) Underfill

Preconditioning level

Passed chips/ total tested

A

1

19/20

A

3

32/32

C

1

11/20

C

3

32/32

AATC occurred prior to delamination of the chip-underfill or the boardunderfill interfaces. In addition, all electrical failures observed in assemblies that were subjected to LLTS occurred either prior to delamination, or, if after delamination, showed no significant correlation to the locations of delamination. That is, fatigue cracks causing chip failure are not typically located in regions of the chip experiencing delamination. Based on the AATC and LLTS electrical failure observations, it can be assumed that the mode of interconnect failure was solder fatigue leading to fatigue cracking. Figure 11.28 shows an example of solder fatigue cracking occurring through the UBM side of the bump propagating through the solder causing an electrical open.

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Scanning electron micrograph of a typical solder fatigue crack.

Figure 11.28

11.3.11 Delamination

Delamination refers to a loss of adhesion between surfaces. In the case of an underfilled flip chip, the adhesion loss is at the chip passivationunderfill interface, the underfill-solder interface, or the underfillsolder mask interface. Delamination in the test vehicles that were subjected to LLTS testing occurred at the chip-underfill interface. In most cases, the delamination is initiated in the corners of the test die. This results from the large stresses that are generated by the CTE mismatch between the silicon chip, the FR-4 substrate, and the no-flow underfill. Underfill delamination typically does not occur until after solder fatigue failure has begun to occur. Underfill A. Exhibited chip-to-underfill delamination in all LLTS assemblies subject to testing, and only one assembly failed J-STD020A level 1 preconditioning due to chip-to-underfill delamination. Delamination in LLTS testing was very similar between underfills A and C. Typically, the delamination was minor and originated predominantly in the chip corners and chip perimeter. Figure 11.29 shows a typical delamination progression found in TV2 assembled with underfill A. In all cases, the first instances of delamination occured after 1200 cycles. From the time of delamination initiation to chip failure, the regions of delamination remained small and experienced very little growth. Assemblies subjected to AATC did not show any evidence of delamination prior to chip failure. Underfill B. Exhibited chip-to-underfill delamination in test vehicles that were subjected to LLTS and AATC. Underfill B delamination occured the earliest and was the most severe of all underfill materials tested. Figure 11.30 shows typical delamination progression for AATC. The first signs of delamination appeared at 700

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Chapter Eleven

Figure 11.29 Delamination progression for underfill A (TV2) subjected to LLTS.

cycles, with delamination spreading to all four sides of the chip by 1200 cycles. Underfill C. Exhibited chip-to-underfill delamination in all test vehicles that were subjected to LLTS for TV1. Over one-half of the underfill C assemblies that were subjected to J-STD-020A level 1 preconditioning failed due to chip-to-underfill delamination. Delamination occurring in LLTS was minor and originated in the chip corner or along the chip perimeter. Figure 11.31 shows typical delamination progression for test vehicle 1 assemblies that were subjected to LLTS.

Delamination progression for underfill B (TV2) subjected to AATC.

Figure 11.30

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Delamination progression for underfill C (TV1) subjected to LLTS.

Figure 11.31

Underfill D. When subjected to LLTS for TV2 showed very small amounts of chip-to-underfill delamination. Delamination began around 1000 cycles and progressed through 1800 cycles. Again, the delamination could be found in the chip corners and perimeter. Figure 11.32 shows typical delamination progression for TV2 that was subjected to LLTS. Underfill E. Showed little to no underfill-to-chip delamination in LLTS through 1800 cycles. Figure 11.33 shows a progression of acoustic micrographs through 1800 cycles, showing no visible delamination. However, underfill cracking was visible at 1400 cycles. Underfill F. Showed chip-to-underfill delamination in assemblies that were subjected to LLTS. Figure 11.34 shows typical delamina-

Delamination progression for underfill D (TV2) subjected to LLTS.

Figure 11.32

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Chapter Eleven

Delamination progression for underfill E (TV2) subjected to LLTS.

Figure 11.33

tion progression for LLTS assemblies. Delamination initiated around 600 cycles and grew as cycling continued. Figure 11.34 shows the delamination occurring along the perimeter of the chip. Underfill G. Exhibited chip-to-underfill delamination only in assemblies that were subjected to LLTS. Assemblies subjected to AATC did not show any delamination prior to electrical failure. Figure 11.35 shows typical delamination progression for the LLTS assemblies. Delamination first occurred around 1900 cycles and exhibited only minor growth through the next 900 cycles. Figure 11.35 shows that delamination occurred mainly in the chip corners and along the perimeter of the chip.

Figure 11.34 Delamination progression for underfill F (TV2) subjected to LLTS.

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Delamination progression for underfill G (TV2) subjected to LLTS.

Figure 11.35

11.3.12 Cracking of underfill fillets

Underfill fillet cracking is a common underfill material failure for noflow underfills, although it can also occur in filled capillary underfills. Fillet cracking occurs mainly in assemblies subjected to LLTS and AATC cycling. Fillet cracks may be classified as one of three types: (1) chip side cracks, (2) board side cracks, and (3) complete fillet cracks. Figure 11.36 shows examples of the three crack types.

Chip Side Cracks

Figure 11.36

Underfill fillet crack

types.

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Chapter Eleven

Chip side cracks are small cracks that originate at the chip-underfill interface and usually form a V-shaped pattern that extends partially down the fillet. Board side cracks are short cracks that extend up the fillet or run parallel to the fillet edge. Chip side cracks can lead to localized areas of delamination between the underfill and the side of the chip, while board side cracks can lead to localized areas of delamination between the underfill and substrate–solder mask. A complete fillet crack extends from the top of the fillet to the substrate and propagates completely through the fillet. In cases of extreme cracking, the underfill fillet separates from the chip, eliminating the stress relief properties of the underfill. Fillet cracking is driven by the large hoop stress that is produced by the underfill generated during the cooling cycle of LLTS. The net difference between the CTE of the underfill (∼70 ppm/°C) and the silicon (∼3 ppm/°C) produces very large hoop tensile and interface shear stress in the fillets. Figure 11.37 shows a typical fillet crack found in underfill B assemblies that were subjected to LLTS. All underfills that were tested have fillet-cracked during cycling. The number of cycles before cracking occurred and the severity of the cracking varied from material to material. For example, underfill B begins to fillet-crack after 200 cycles of LLTS, and underfill E begins to filletcrack after 1300 cycles of LLTS. 11.3.13 Cracking of bulk underfills

In addition to fillet cracking, cracks may be seen in the bulk underfill underneath the test die occurring during AATC and LLTS testing. Typical underfill cracks in the no-flow underfills are shown in Fig. 11.38. It is important to notice that the cracks typically occur adjacent to the solder joints propagating between the joints. In addition to cracks propagating between solder joints, cracks were also seen to initiate and propagate along the metallization pattern on the test die, as seen in the second image in Fig. 11.38. Moreover, it has been observed that solder from the joints tends to extrude into underfill cracks during AATC and

Typical fillet cracks found in underfill B assemblies subjected to LLTS.

Figure 11.37

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Figure 11.38

445

Examples of bulk underfill cracking.

LLTS cycling, which has the potential to cause electrical shorting, as shown in Fig. 11.39. Figure 11.40 shows a series of C-SAM images at the chip-to-underfill interface where fine lines near the solder joints appear and expand as cycling continues. Cross sections show that these fine lines correspond to cracks in the bulk underfill, as illustrated in Fig. 11.40, indicating that C-SAM analysis can be used to detect bulk underfill cracks. Bulk underfill cracking has been seen in no-flow underfills, as well as capillary underfills. In addition, for no-flow underfills, bulk cracking occurs before chip failure due to solder fatigue cracking. The chip shown in the acoustic images in Fig. 11.40 fails at 2400 cycles LLTS, yet underfill cracking is visible in acoustic images at 1400 cycles. Figure 11.41 shows C-SAM images of a cycled chip showing underfill cracking at the chip interface and the board interface. Bulk underfill cracking is seen in all seven underfills tested to varying degrees. Cracking occurred the earliest and was the most severe in underfill B. Underfills A, C, E, and F all exhibited similar amounts of bulk cracking. Minimal underfill cracking is seen in underfills D and G. Figure 11.42 shows a schematic of copper circuit trace on a substrate, covered by solder mask and underfill. A simple analysis of this microstructure gives one explanation for the underfill and substrate cracks observed. During the reflow process, the underfill material hardens at a temperature of approximately 200°C and locks the assembly in a zero-stress state at this temperature. As the assembly cools to

Figure 11.39 Example of solder extrusion into underfill cracks between adjacent bumps.

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Chapter Eleven

(b)

(a)

(c)

Underfill E—C-SAM images at (a) 0 cycles, (b) 1400 cycles, and (c) 2000 cycles.

Figure 11.40

room temperature, all four materials attempt to contract different distances based on their respective CTE. The larger the CTE, the more the material wants to contract. Based on the approximate CTE values presented in Fig. 11.42, both the underfill material and substrate will contract to a greater extent than the copper trace. The difference in CTE between the substrate and the underfill generates large in-plane stresses in the underfill layer. When the assembly is cycled, it experi-

(a)

(b)

C-SAM images of TV3 Subjected to LLTS at (a) the chip-underfill interface and (b) the underfill-board interface. Figure 11.41

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ences temperatures as low as −55°C, which represents a ∆T of 250°C from the zero-stress state. The large temperature change produces large cyclical in-plane stresses that may promote underfill cracking. Sharp corners found on the copper circuitry generate local regions of stress concentration that increase the tendency for crack initiation near the corners of the copper trace. Cracks that form in the solder mask have a tendency to propagate into the bulk underfill layer. Figure 11.42 shows the areas of stress concentration that promote underfill and substrate crack initiation. Figure 11.43 indicates that underfill cracks can also form between solder bumps. An analysis similar to the one presented previously provides one explanation for underfill cracks forming between solder interconnects. Figure 11.43 shows a top-view schematic of solder interconnects surrounded by underfill material. The CTE of the underfill is nearly three times greater than the CTE of solder. During cycling, the large difference in CTE generates a stress concentration along the circumference of the solder-underfill interface. Any microcracks in the underfill that exist along the interface can be initiation points for underfill cracks. The most common cracks that initiated along the circumference of the solder occurred in the narrowest region between interconnects. This region has the smallest cross-sectional area and, therefore, is the likeliest location for fatigue crack initiation.

Stress concentration regions produced by substrate circuitry.

Figure 11.42

Stress concentrations caused by solder interconnects.

Figure 11.43

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11.4 References 1. Tsukada, Y., S. Tsuchida, and Y. Mashimoto, “A Novel Chip Replacement Method for Encapsulated Flip Chip Bonding,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 199–204, Orlando, FL, June 1993. 2. Pompeo, F. L., A. J. Call, J. T. Coffin, and S. Buchwalter, “Reworkable Encapsulation for Flip Chip Packaging,” Proceedings of the International Intersociety Electronic Packaging Conference, pp. 781–787, Maui, HI, March 1995. 3. Suryanarayana, D., J. A. Varcoe, and J. V. Ellerson, “Reparability of Underfill Encapsulated Flip-Chip Packages,” Proceedings of IEEE Electronic Components & Technology Conference,” pp. 524–528, Las Vegas, NV, May 1995. 4. Nguyen, L., P. Fine, B. Cobb, Q. Tong, B. Ma, and A. Savoca, “Reworkable Flip Chip Underfill—Materials and Processes,” Proceedings of the International Symposium on Microelectronics, pp. 707–713, San Diego, CA, November 1998. 5. Wang, L., and C. P. Wong, “Epoxy-Additive Interaction Studies of Thermally Reworkable Underfills for Flip-Chip Applications,” Proceedings of IEEE Electronic Components & Technology Conference,” pp. 34–42, San Diego, CA, June 1999. 6. Crane, L., A. Torres-Filho, E. Yager, M. Heuel, C. Ober, S. Yang, J. Chen, and R. Johnson, “Development of Reworkable Underfills, Materials, Reliability and Proceeding,” Proceedings of NEPCON WEST, pp. 144–151, Anaheim, CA, February 1999. 7. Wun, K. B., and J. H. Lau, “Characterization and Evaluation of the Underfill Encapsulants for Flip Chip Assembly,” Circuit World, 21:25–32, March 1995. 8. Wun, K. B., and G. Margaritis, “The Evaluation of Fast-Flow, Fast-Cure Underfills for Flip Chip on Organic Substrates,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 540–545, Orlando, FL, May 1996. 9. Pascarella, N., and D. Baldwin, “Advanced Encapsulation Processing for Low Cost Electronics Assembly—A Cost Analysis,” The 3rd International Symposium and Exhibition on Advanced Packaging Materials, Processes, Properties, and Interfaces, pp. 50–53, Braselton, GA, March 1997. 10. Nguyen, L., L. Hoang, P. Fine, Q. Tong, B. Ma, R. Humphreys, A. Savoca, C. P. Wong, S. Shi, M. Vincent, and L. Wang, “High Performance Underfills Development— Materials, Processes, and Reliability,” Proceedings of IEEE 1st International Symposium on Polymeric Electronics Packaging, pp. 300–306, Norrkoping, Sweden, October 1997. 11. Wong, C. P., M. B. Vincent, and S. Shi, “Fast-Flow Underfill Encapsulant: Flow Rate and Coefficient of Thermal Expansion,” Proc. ASME—Advances in Electronic Packaging, 19(1):301–306, 1997. 12. Vincent, M. B., and C. P. Wong, “Enhancement of Underfill Encapsulants for FlipChip Technology,” Proceedings of Surface Mount International Conference, pp. 303–312, San Jose, CA, August 1998. 13. Tong, Q., A. Savoca, L. Nguyen, P. Fine, and B. Cobb, “Novel Fast Cure and Reworkable Underfill Materials,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 43–48, San Diego, CA, June 1999. 14. Houston, P. N., D. F. Baldwin, M. Deladisma, L. N. Crane, and M. Konarski, “Low Cost Flip Chip Processing and Reliability of Fast-Flow, Snap-Cure Underfills,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 61–70, San Diego, CA, June 1999. 15. Anderson, B., “Development Methodology for a High-Performance, Snap-Cure FlipChip Underfill,” Proceedings of NEPCON WEST, pp. 135–143, Anaheim, CA, February 1999. 16. Erickson, M., and K. Kirsten, “Simplifying the Assembly Process with a Reflow Encapsulant,” Electronic Packaging & Production, 81–86, February 1997. 17. Gamota, D., and C. Melton, IPC-TP-1098, Reflowable Material Systems to Integrate the Reflow and Encapsulant Dispensing Process for Flip Chip on Board Assemblies, 1996. 18. Ito, S., M. Kuwamura, S. Sudo, M. Mizutani, T. Fukushima, H. Noro, S. Akizuki, and A. Prabhu, “Study of Encapsulating System for Diversified Area Bump Packages,”

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19. 20.

21. 22. 23. 24.

25. 26. 27. 28. 29.

30. 31. 32. 33.

34. 35. 36.

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Proceedings of IEEE Electronic Components & Technology Conference, pp. 46–53, San Jose, CA, May 1997. Wong, C. P., S. H. Shi, and G. Jefferson, “High Performance No Flow Underfills for Low-Cost Flip-Chip Applications,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 850–858, San Jose, CA, May 1997. Wong, C. P., D. Baldwin, M. B. Vincent, B. Fennell, L. J. Wang, and S. H. Shi, “Characterization of a No-Flow Underfill Encapsulant During the Solder Reflow Process,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 1253–1259, Seattle, WA, May 1998. Ito, S., M. Mizutani, H. Noro, M. Kuwamura, and A. Prabhu, “A Novel Flip Chip Technology Using Non-Conductive Resin Sheet,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 1047–1051, Seattle, WA, May 1998. Lau, J. H., C. Chang, and O. Chien, “SMT Compatible No-Flow Underfill for Solder Bumped Flip Chip on Low-Cost Substrates,” Journal of Electronics Manufacturing, 8(3/4):151–164, December 1998. Thorpe, R., and D. F. Baldwin, “High Throughput Flip Chip Processing and Reliability Analysis Using No-Flow Underfills,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 419–425, San Diego, CA, June 1999. Shi, S. H., and C. P. Wong, “Recent Advances in the Development of No-Flow Underfill Encapsulants—A Practical Approach Towards the Actual Manufacturing Application,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 770–776, San Diego, CA, June 1999. DeBarros, T., P. Neathway, and Q. Chu, “The No-Flow Fluxing Underfill Adhesive for Low Cost, High Reliability Flip Chip Assembly,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 955–960, San Diego, CA, June 1999. Lau, J. H., and C. Chang, “Characterization of Underfill Materials for Functional Solder Bumped Flip Chips on Board Applications,” IEEE Transactions on Components and Packaging Technology, Part A, 22(1):111–119, March 1999. Lau, J. H., and C. Chang, “How to Select Underfill Materials for Solder Bumped Flip Chip on Low Cost Substrates?” IMAPS Transactions, International Journal of Microelectronics & Electronic Packaging, 22(1):20–28, First Quarter 1999. Lau, J. H., C. Chang, and R. Chen, “Effects of Underfill Encapsulant on the Mechanical and Electrical Performance of a Functional Flip Chip Device,” Journal of Electronics Manufacturing, 7(4):269–277, December 1997. Lau, J. H., S.-W. R. Lee, C. Chang, and C. Ouyang, “Effects of Underfill Material Properties on the Reliability of Solder Bumped Flip Chip on Board with Imperfect Underfill Encapsulants,” Proceeding of IEEE 49th Electronic Components and Technology Conference, pp. 571–582, San Diego, CA, June 1999. Lau, J. H., and Y.-H. Pao, Solder Joint Reliability of BGA, CSP, and Fine Pitch SMT Assemblies, McGraw-Hill, New York, 1997. Lau, J. H., and S. W. R. Lee, Chip Scale Package: Design, Materials, Process, Reliability, and Applications, McGraw-Hill, New York, 1999. Lau, J. H., Low Cost Flip Chip Technologies for DCA, WLCSP, PBGA Assemblies, McGraw-Hill, New York, 2000. Smith, B. A., R. Thorpe, and D. F. Baldwin, “A Process and Reliability Analysis of No Flow Underfill Materials for High Throughput Flip Chip Processing,” Proceedings of IEEE Electronics Manufacturing Technology Symposium, pp. 178–190, San Jose, CA, October 2000. McGovern, L. P, and Baldwin, D. F., “High-Throughput Low-Cost Flip Chip-OnBoard Assembly,” Electronic Packaging and Production, 38(2):68–76, 1998. Wong, C. P., and S. Shi, “Study of the Fluxing Effects on the Properties of No-Flow Underfill Materials for Flip Chip Applications,” Proceeding of IEEE 48th Electronic Components and Technology Conference, pp. 117–124, Seattle, WA, May 1998. Thorpe, R., and D. F. Baldwin, “Reliability Analysis of Flip Chip on Board Using NoFlow Underfill Materials,” Proceedings of SMTA International Conference, pp. 153–158, San Jose, CA, September 1999.

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Assembly of Flip Chip on PCB/Substrate

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Source: Microvias

Chapter

12 Solder Joint Reliability of Flip Chip on Microvia PCB/Substrate

12.1 Introduction The effects of lead-free solders, underfills, and microvia build-up PCBs/ substrates on the solder joint reliability of WLCSP and DCA are discussed in this chapter. Also, three new empirical equations for predicting the thermal fatigue life of WLCSP solder joints on PCB are presented. 12.2 Elastic, Plastic, and Creep Analyses of WLCSP on Microvia PCB The solder joint reliability of solder-bumped WLCSP on microvia build-up PCB subjected to thermal cycling conditions is investigated in this section. The Sn62-Pb36-Ag2 solder joints are assumed to be (1) an elastic material; (2) an elastoplastic material; and (3) a creep material that obeys the Garofalo-Arrhenius creep constitutive law. The stress and strain in the corner solder joint of the WLCSP assembly are presented and compared for these three material models. Also, the results presented here are compared with those from creep analysis of the WLCSP on PCB without the microvia build-up layer. Since the research of Tsukada et al.1–3 in 1992, the electronic packaging industry has witnessed an explosive growth in the research and development efforts devoted to solder-bumped flip chips on low-cost PCB or organic substrate in a PBGA package (see for example Refs. 4 to 10). Because of the thermal expansion mismatch between the silicon chip and the epoxy substrate, underfill encapsulant is usually needed

451

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for solder joint reliability. However, due to the underfill operation, the manufacturing cost is increased and the manufacturing throughput is reduced. In addition, the rework of an underfilled flip chip on PCB is very difficult, if not impossible. This further complicates the knowngood-die-related issues. There is another reason why directly attaching flip chips on low-cost PCB is not very popular yet. Usually, the pitch and size of the pads on the peripheral-arrayed chips are very small and pose great demands on the supporting structures such as the PCB or organic substrate. The high-density and fine-linewidth/spacing PCBs with sequential buildup circuits connected through microvias are not commonly available at reasonable cost yet. Meantime, a new class of packaging called WLCSP7–26 provides a solution to these problems. The unique feature of most WLCSPs is the use of a metal layer to redistribute the very fine-pitch peripheral-arrayed pads on the chip (on a wafer) to much larger-pitch area-arrayed pads with much larger solder bumps on the chip and to form much taller solder joints on the PCB. Just like many other new technologies, WLCSPs still face many critical issues. In the development of solder-bumped WLCSP on highdensity PCB or on the substrate in a PBGA package, the following must be noted and understood:25 ■

The infrastructure of WLCSP is not well established.

■

The standard for WLCSP is not well established.

■

WLCSP expertise is not commonly available.

■

Bare wafer is not commonly available.

■

Handling of bare wafer is delicate.

■

Costs are high for poor-yield IC wafers.

■

Wafer-level redistribution is still too costly.

■

Costs are high for low wafer-level redistribution yield, especially for high-cost dies.

■

Wafer bumping is still too costly.

■

Costs are high for low wafer-bumping yield, especially for high-cost dies.

■

There can be trouble with system makers if the die shrinks.

■

Test at speed and burn-in at high temperature on a wafer are difficult.

■

Single-point touch-up on the wafer is difficult.

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453

■

PCB assembly of WLCSP is more difficult.

■

Solder joint reliability is more critical.

■

Microvia build-up PCB affects solder joint reliability.

■

Alpha particles produce soft errors by penetrating through the leadbearing solder on WLCSP.

■

Lead-free solder regulations impact WLCSP.

■

Is underfill encapsulant necessary for WLCSP?

■

Who should do the WLCSP? IC foundries or bump houses?

■

What are the cost-effective and reliable WLCSPs and for what IC devices?

■

How large is the WLCSP market?

■

What is the life cycle of WLCSP?

In Sec. 12.2, the solder joint reliability of WLCSP on microvia build-up27,28 PCB or substrate in a PBGA package is investigated. The Sn62-Ag2-Pb36 eutectic solder is assumed to be: (1) an elastic material; (2) an elastoplastic material; and (3) a creep material. Only thermal cycling loadings are considered. 12.2.1 Structures

Figure 12.1 schematically shows the silicon chip under consideration. The dimensions of the chip are 9 × 9 × 0.51 mm. It has 121 (0.06 × 0.06-mm) peripheral pads with a spacing of 0.1 mm. After wafer-level redistribution, the pads are 0.3 mm in diameter and are in an areaarrayed format with 0.75-mm pitch. Figure 12.2 shows the microvia build-up PCB assembly of the solderbumped WLCSP under consideration. It can be seen that there is an electroplated copper microvia build-up layer 0.15 mm thick on the 1.575-mm-thick PCB. The PCB is made of FR-4 epoxy glass. The copper pad thickness is 0.018 mm as shown in Fig. 12.3. The solder joint is made of Sn62-Ag2-Pb36 eutectic solder alloys; its height is 0.1524 mm. Figure 12.4 shows the finite element model of the Sn62-Ag2-Pb36 solder-bumped WLCSP on the one-layer build-up with microvia PCB. It can be seen that the diameters of the microvia vary from 0.1 to 0.15 mm. The thickness of the microvia copper is 0.025 mm. The thickness of the build-up resin is about 0.125 mm. Due to symmetry, only half of the diagonal cross section of the assembly is modeled and it is a 2-D analysis. Since the focus is on the corner solder joint, finer and more meshes are used to model it.

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Chapter Twelve

(a)

(b) Figure 12.1 Schematic of a chip with pad redistribution. (a) Top view and (b) cross-sectional view of the WCLSP.

12.2.2 Material properties

The Young’s modulus, Poisson ratio, and thermal expansion coefficient of the resin are 20 GPa, 0.3, and 50 × 10−6/°C, respectively. The electroplated copper is considered an elastoplastic material for creep and elastoplastic analysis (yield stress = 54 MPa, yield strain = 0.007, Young’s modulus = 76 GPa, ultimate strength = 200 MPa, and tangent modulus of the plastic curve = 7.6 GPa). The thermal expansion coeffi-

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Solder Joint Reliability of Flip Chip on Microvia PCB/Substrate

Figure 12.2

455

Schematic of half of the WLCSP on microvia build-up

PCB.

Dimensions of the solder joint and copper pads.

Figure 12.3

Finite element model of half of the WLCSP on microvia build-up PCB.

Figure 12.4

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Chapter Twelve

cient of the electroplated copper is 17 × 10−6/°C. The elastic and elastoplastic material properties of the Sn62-Ag2-Pb36 solder are given in Ref. 10. The creep material properties of the solder are given in the following text. The finite element code used here is ANSYS, release 5.6.1.29 It can solve boundary-value problems with the Garofalo-Arrhenius creep constitutive equation expressed by:30 τ

冢 冣 冢sinh 冤ω ᎏG 冥冣

dγ G ᎏ=C ᎏ dt Θ

n

冢

Q exp − ᎏ kΘ

冣

(12.1)

where γ is the creep shear strain, dγ/dt is the creep shear strain rate, t is the time, C is a material constant, G is the temperature-dependent shear modulus, Θ is the absolute temperature (K), ω defines the stress level at which the power law stress dependence breaks down, τ is the shear stress, n is the stress exponent, Q is the activation energy for a specific diffusion mechanism (for example, dislocation diffusion, solute diffusion, lattice self-diffusion, and grain boundary diffusion), and k is Boltzmann’s constant (8.617 × 10−5 eV/K). For Sn62-Ag2-Pb36, Sn96.5-Ag3.5, and In100 solder alloys, the material constants of Eq. (12.1) have been experimentally determined by Darveaus and Banerji31,32 with a single hyperbolic sine function given by31–33 dγ τ ᎏ = A sinh ᎏ dt B

冢

冤 冥冣

n

冢

Q exp − ᎏ kT

冣

(12.2)

Table 12.1 shows the values of the constants n, Q, A, and B. Equation (12.2) for these three solder alloys at 27 and 100°C is plotted in Fig. 12.5. It can be seen that: (1) for all the solder alloys and for all the temperatures, the higher the stress, the higher the creep strain rate; (2) for all the solder alloys and for all the shear stresses, the higher the temperature, the higher the creep strain rate; (3) for all the temperatures and for all the shear stress levels, the creep strain rate of the In100 is

TABLE 12.1

Fitted Equations from Shear Creep Test Results

Solder alloy

n

Q (eV)

Sn62-Ag2-Pb36

3.3

0.548

Sn96.5-Ag3.5

5.5

0.5

In100

5

0.72

A (1/s)

B (psi)

801 (508 − T)/T

3,163 − 6.23T

31 (553 − T)/T

3,687 − 6.67T

70,400 (593 − T)/T

158 − 0.27T

See Eq. (12.2). T is absolute temperature in K.

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Solder Joint Reliability of Flip Chip on Microvia PCB/Substrate

Figure 12.5

457

Creep constitutive relations of the solders.

much larger than that of the Sn62-Ag2-Pb36 and Sn96.6-Ag3.5; (4) for all the stress levels, the creep strain rate of the In100 is much larger than that of the Sn62-Ag2-Pb36 and Sn96.6-Ag3.5; and (5) for all the operating temperatures and for most operating stresses, the creep strain rate of Sn62-Ag2-Pb36 is larger than that of Sn96.5-Ag3.5, especially for higher temperatures and lower stresses. If the solder obeys the von Mises criterion,34 then Eq. (12.2) can be written as

冢 冣

C dε ᎏ = C1 (sinh [C2σ])C3 exp − ᎏ4 dt T

(12.3)

where C1, C2, C3, and C4 are given in Table 12.2 for the three solder alloys under consideration. It should be noted that Eq. (12.3) is exactly the same form of input for implicit creep model (TBOPT = 8) of ANSYS TABLE 12.2

ANSYS Input for Implicit Creep Analysis

Solder alloys Sn62-Pb36-Ag2 Sn96.5-Ag3.5 In100

C2 (1/psi)

C3

C4 (K)

462 (508 − T)/T

C1 (1/s)

1/(5,478 − 10.79T)

3.3

6,360

18 (553 − T)/T

1/(6,386 − 11.55T)

40,647 (593 − T)/T

1/(274 − 0.47T)

5.5

5,802

5

8,356

See Eq. (12.3). T is absolute temperature in K. For ANSYS release 5.6.1 inputs, C2 and C3 should be interchanged.

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Chapter Twelve

release 5.6.1.29 In Eq. (12.2) and (12.3), σ is the uniaxial stress, dε/dt is the uniaxial creep strain rate. The unit for σ and τ is in lb/in2 (psi). The material properties of the silicon chip, FR-4 PCB, and copper are shown in Table 12.3. 12.2.3 Boundary conditions

The temperature loading imposed on the solder-bumped WLCSP on PCB assemblies is shown in Fig. 12.6. It can be seen that for each cycle (60 min) the temperature is between −20 and +110°C, with 15 min ramp, 20 min hold at hot, and 10 min hold at cold. There are two reasons for choosing this temperature profile: (1) the glass transition temperature of the FR-4 PCB is 120°C and we don’t want to introduce additional failure mechanisms of the solder joint due to the degradation of the PCB; and (2) the behavior of solder below −20°C is not very well understood. For elastic and elastoplastic analyses, the only input is from −20 to 110°C, and for creep analysis, five full cycles are executed. 12.2.4 Elastic analysis and results

Figure 12.7 shows the elastic deformation (50×) of the solder-bumped WLCSP on the microvia build-up PCB. It can be seen that the whole assembly is deformed (with a maximum deflection of 0.0255 mm) into a concave shape under a temperature rise of 130°C. This is because of the global thermal expansion mismatch between the silicon chip (2.8 × 10−6/°C) and the FR-4 epoxy glass PCB (18 × 10−6/°C). Also, it can be seen from Fig. 12.7 that the microvia build-up layer and the upper portion of TABLE 12.3

Material Properties of Flip Chip Assemblies

Material properties

Young’s modulus (MPa)

Poisson ratio (ν)

CTE (α) (ppm/°C)

Sn62-Ag2-Pb36

34,441 − 152T

0.35

24.5

52,708 − 67.14T − 0.0587T2

0.4

21.85 + 0.02039T

Sn96.5-Ag3.5 In100

2,200

0.4

32.1

9,292 − 35.4T

0.35

31.0395 + 0.0923T

131,000

0.3

2.8

FR-4

22,000

0.28

18

Copper

76,000

0.35

17

Build-up resin

20,000

0.3

50

Underfill Si

T is temperature (°C). The electroplated copper is assumed to be elastoplastic.

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Solder Joint Reliability of Flip Chip on Microvia PCB/Substrate

Figure 12.6

459

Thermal cycling conditions.

Figure 12.7 Elastic deformation of the WLCSP on microvia build-up PCB.

the PCB want to bend downward due to the local thermal expansion mismatch between the build-up resin (50 × 10−6/°C) and the PCB. The von Mises stress contours in the microvia are shown in Fig. 12.8. It can be seen that the maximum von Mises stress is 407 MPa, which is much larger than the ultimate strength of electroplated copper. The effective linear elastic strain contours in the microvia are shown in Fig. 12.9. It can be seen that their values are very small. These unreasonable stress and strain results are due to the limitations of linear elastic analysis. The von Mises stress and strain contours in the corner solder joint are shown in Figs. 12.10 and 12.11, respectively. It can be seen that the maximum stress (163 MPa) is too high and the strain (0.0124) is too low because of linear elastic analysis. 12.2.5 Elastoplastic analysis and results

In this analysis, the microvia and the solder joints are assumed to be elastoplastic materials. Figure 12.12 shows the deformation (50×) of

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Chapter Twelve

Figure 12.8

Elastic von Mises stress (MPa) in the microvia.

the whole assembly under a temperature change from −20 to 110°C. It can be seen that the maximum deflection (0.0219 mm) is (16.4 percent) smaller than that (0.0255 mm) of the elastic analysis. This is due to the plastic deformation of the solder joints, which reduces the bonding between the chip and the microvia build-up PCB. The von Mises stress and strain contours in the microvia are shown in Figs. 12.13 and 12.14, respectively. It can be seen that the maximum von Mises stress (121 MPa) is much smaller than that (407 MPa) from

Figure 12.9

Elastic effective strain in the microvia.

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Solder Joint Reliability of Flip Chip on Microvia PCB/Substrate

Figure 12.10

461

Elastic von Mises stress (MPa) in the corner solder

joint.

the linear elastic analysis. Also, the maximum effective total strain (elastic strain + plastic strain = 0.007 + 0.0071 = 0.0141) is much larger than that (0.007) from the linear elastic analysis. The von Mises stress and strain contours in the corner solder joint are shown in Figs. 12.15 and 12.16, respectively. It can be seen

Figure 12.11

Elastic effective strain in the corner solder joint.

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Chapter Twelve

Figure 12.12

Elastoplastic deformation of the WLCSP on microvia build-up PCB.

Figure 12.13

von Mises stress (MPa) in the microvia (elastoplastic

analysis).

Figure 12.14

Total (elastic + plastic) effective strain in the microvia.

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463

von Mises stress (MPa) in the corner solder joint (elastoplastic analysis).

Figure 12.15

that, due to the elastoplastic nonlinear analysis, the maximum von Mises stress (62.61 MPa) is much smaller than that (163 MPa) of the linear elastic analysis, and the maximum effective total strain (0.0124 + 0.0176 = 0.03) is much larger than that (0.0124) from linear analysis.

Figure 12.16 Total (elastic + plastic) effective strain in the corner solder joint.

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Chapter Twelve

12.2.6 Creep analysis and results 12.2.6.1 Deformed shapes. Figures 12.17a through 12.17e show the deformed shapes (50×) of the Sn62-Ag2-Pb36 solder-bumped WLCSP on the microvia build-up PCB assembly at 588, 4,188, 7,788, 11,388, and 14,988 s (temperature ∼110°C). It can be seen and expected that, due to the thermal expansion mismatch among the silicon chip, the FR-4 epoxy glass PCB, and the build-up resin, the solder joints are subjected to very large shear deformation (especially the corner solder joint). At 588 s, the maximum deflection of the assembly is 0.017 mm, which is 29 percent smaller than that (0.0219 mm) of the elastoplastic analysis and 50 percent smaller than that (0.0255 mm) of the linear elastic analysis. This is because (1) the global thermal expansion mismatch between the silicon chip and the build-up PCB forces the whole assembly to deform into a concave shape; (2) the local thermal expansion mismatch between the build-up resin and the FR-4 PCB forces the build-up PCB to deform into a convex shape (exactly opposite to the global deformation); and (3) the local thermal expansion mismatch between the silicon chip and the build-up resin creates a considerable amount of shear creep strains in the solder joints. However, at 4188 s, the deformity of the whole assembly is no longer in a concave shape but expands in the horizontal direction only. The reasons are basically the three just mentioned, except that the accumulated creep strains in the solder joints are much larger than before, i.e., the structure is less bonded between the silicon chip and the build-up PCB. Consequently, the local thermal expansion mismatch between the build-up resin and the PCB becomes larger than the global thermal expansion mismatch between the chip and the build-up PCB. At 7,788, 11,388, and 14,988 s, the whole assembly (except the chip) is beginning to bend into a convex shape. This is because (1) the bonding between the chip and the build-up PCB is much less, and (2) the local mismatch is much more than the global mismatch. 12.2.6.2 Stress and strain in the microvia. The von Mises stress contours in the microvia at 588 and 14,988 s are shown in Fig. 12.18. It can be seen that: (1) at a high temperature (110°C) the stress does not change much from thermal cycle to cycle, and (2) the maximum value (103 MPa) is 17.5 percent smaller than that (121 MPa) from elastoplastic analysis and 295 percent smaller than that from linear analysis. Again, this is due to the creep deformation of the solder joints, which makes the structure less bonded together. The effective total strain contours in the microvia at 588 and 14,988 s are shown in Fig. 12.19. Again, at high temperature the strain does not change much from thermal cycle to cycle. It is interesting to note that, due to the very large creep deformation of the solder joints, the plastic

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Figure 12.17 Creep deformation of the WLCSP on microvia build-up PCB at (a) 588 s, (b) 4,188 s, (c) 7,788 s, (d) 11,388 s, and (e) 14,988 s.

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Figure 12.18

von Mises stress (MPa) in the microvia (creep analysis) at 588 s (left) and 14,988 s (right).

Solder Joint Reliability of Flip Chip on Microvia PCB/Substrate

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Figure 12.19

Effective creep strain in the microvia at 588 s (left) and 14,988 s (right).

Solder Joint Reliability of Flip Chip on Microvia PCB/Substrate

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Chapter Twelve

strain in the microvia is smaller than that from elastoplastic analysis of the solder joints. 12.2.6.3 Hysteresis loops, stress, and creep strain in the corner solder joint. Figures 12.20, 12.21, 12.22 show, respectively, the shear stress

and shear creep strain hysteresis loops, shear stress history, and shear creep strain history of the corner solder joints of the WLCSP on microvia build-up PCB. It can be seen from Fig. 12.20 that the creep responses converged at the third thermal cycle. Also, it can be seen from Fig. 12.21 that the stress range (33.37 MPa) in the corner solder joint is 79 percent less than that (62.61 MPa) from elastoplastic analysis. Also, it is much larger than that (28.5 MPa) of the case without the build-up layer.34

Shear Stress (MPa)

35 30 25 20 15 10 5 0 -5 -10 -15 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01

0.00

Shear Creep Strain

Shear stress and creep shear strain hysteresis loops for the WLCSP corner solder joint on build-up PCB.

Figure 12.20

Shear Stress (MPa)

35 30 25 20 15 10 5 0 -5 -10 0

5000

10000

15000

20000

Time (sec) Figure 12.21 Shear stress time history for the WLCSP corner solder joint on build-up PCB.

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Shear Creep Strain

0.00 -0.01 -0.02 -0.03 -0.04 -0.05 -0.06 -0.07 -0.08 0

5000

10000

15000

20000

Time (sec)

Creep shear strain time history for the WLCSP corner solder joint on build-up PCB.

Figure 12.22

Similarly, from Fig. 12.22, the shear creep strain range (0.015) is much larger than that (0.01) of the case without the microvia build-up layer.34 Since the thermal fatigue life of the solder joints is nonlinearly inverse to the strain, creep analysis is necessary, because the elastic and elastoplastic analyses underestimate the strains and overpredict the thermal fatigue life. 12.2.7 Summary

Detailed elastic, elastoplastic, and creep analyses of solder-bumped WLCSP solder joints on microvia build-up PCB have been presented. Some important results are summarized as follows. ■

In general, the elastic material model of the microvias and solder joints predicts the largest deflection of the WLCSP on the microvia build-up PCB assembly and the creep material model of the solder joints predicts the smallest.

■

In general, the elastic material model of the microvias and solder joints predicts the largest stress and smallest strain in the microvias and the creep material model of the solder joints predicts the smallest stress.

■

In general, the elastic material model predicts the largest stress and smallest strain in the solder joints. On the other hand, the creep model predicts the largest strain and smallest stress in the solder joints.

■

Since the thermal fatigue life of the solder joints is nonlinearly inverse to the strain, both elastic and elastoplastic analyses will underpredict the strains and hence overpredict the thermal fatigue

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Chapter Twelve

life, which is dangerous! Thus, creep analysis of the solder joints is necessary. ■

The effect of the microvia build-up layer on PCB on the WLCSP solder joints is to increase the shear stress range and creep shear strain range and to reduce their thermal fatigue lives.

■

The implicit model of ANSYS for solders obeying the GarofaloArrhenius creep constitutive equation works very well and converges very fast. The input data (C1, C2, C3, and C4 for creep analysis of ANSYS) for a few solder alloys are provided. It should be noted that there is an error in the present release (the constants C2 and C3 should be switched),34 and it will be corrected in the next release of ANSYS.

12.3 Lead-Free Solder-Bumped WLCSP on Microvia PCB Low-cost tin-lead solders have been used as joining materials in the electronics industry for many years. The unique physical and mechanical properties of the low-cost tin-lead solders have facilitated PCB assembly choices that have fueled creative advanced packaging developments, such as solder-bumped flip chips, BGA packages, and CSP. For these packaging technologies, the tin-lead solders are the electrical and mechanical “glue” of the PCB assemblies. Since 1992, different bills have been introduced in the U.S. Congress to ban lead from a wide variety of applications, including solders. The reasons are, among others: (1) lead and its compounds are ranked as one of the top 10 hazardous materials, and (2) lead is the number one environmental threat to children. Many major electronics companies, national laboratories, universities, research organizations, and solder vendors worldwide responded by initiating research programs to eliminate lead from solders.34–70 In North America, for example, the world’s first lead-free PCB telephone was produced by Nortel Networks in 1997. They used the eutectic Sn99.3-Cu0.7 to replace Sn-Pb solder for both surface-mount and through-hole components. The European Union proposed banning all lead in electronic products by the year 2004. Recently, the ban was postponed to 2008. In Japan, some electronics manufacturers have announced voluntary plans to reduce their use of lead in solders. For example, Hitachi reduced its use of lead in 1999 by half of that used in 1997 and plans to stop using lead solders by 2001. (Sn-Bi-Ag-type alloys are some of Hitachi’s favorites.) NEC intends to reduce lead use in solders by 50 percent by 2002 compared to its usage in 1997. (Sn-Ag, Sn-Zn, and Sn-Ag-Cu alloys are some of NEC’s choices.) NTT intends to purchase only equipment safe for the environment (i.e., no lead or cadmium) by 2001. Sony reduced the usage of lead solders in 1999 by half of that used in 1996 and Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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plans to stop using lead solders (except high-density packaging) by 2001. (For example, Sony developed the Sn-Ag2-Bi4-Cu0.5-Ge0.1 solder for its own products.) Toshiba intends to remove lead from all mobile phones by 2002. Fujitsu plans to stop using lead in its LSI products by October 2000, in half the PCB used in its products by December 2001, and for all its products by December 2002. (Fujitsu has explored, for example, SnBi-Ag alloys.) Matsushita aims to stop using lead solders by 2001. (Matsushita picks, for example, Sn-Ag-Bi-X alloys.) It is interesting to point out that “green” products sell! For example, the market share of Matsushita’s lead-free MiniDisc player jumped from 4.6 to 15 percent in 6 mo in Japan in 1999. Toshiba’s bromine-free PCBs help the company sell its Libretto and Dynabook notebook computers in Europe and earned it some romantic names such as Blue Angel (in Germany), White Swan (in Finland), and TCOGY (in Sweden). With the pressure for “green” products, one of the challenges is to find an alternative solder alloy that is as cost effective, manufacturable, available, and reliable as the industry standard eutectic tin-lead or high-lead solders. Unfortunately, there are no drop-in replacements yet. In this section, the Sn96.5-Ag3.5 lead-free solder is considered. The melting point for Sn96.5-Ag3.5 is 221°C. The Sn62-Pb36-Ag2 solder alloy considered in Sec. 12.2 is used to establish a baseline. From the cost point of view, Sn96.5-Ag3.5 is more expensive than Sn62-Pb36-Ag2. 12.3.1 Structure

The structure under consideration is exactly the same as the one in Sec. 12.2, except the solder material is Sn96.5-Ag3.5 instead of Sn62Pb36-Ag2. 12.3.2 Material properties

The material properties of the Sn96.5-Ag3.5 solder alloy are shown in Fig. 12.5 and Table 12.1. Again, the constitutive behavior of Sn96.5Ag3.5 solder is assumed to obey the Garofalo-Arrhenius creep equation. 12.3.3 Creep analysis and results Deformed shapes of the WLCSP assembly. Figures 12.23a through 12.23e show the deformed shapes (50×) of the Sn96.5-Ag3.5 solder-bumped WLCSP on microvia build-up PCB assembly at 588, 4,188, 7,788, 11,388, and 14,988 s (Fig. 12.6, temperature ∼110°C). Also, the maximum deflections (square root of the sum of square of the displacement components in the x-direction and y-direction) at these instants are shown in the second column of Table 12.4. It can be seen and expected that, due to the thermal expansion mismatch among the silicon chip (2.8 ppm/°C), the build-up resin (50 ppm/°C), and the FR-4 12.3.3.1

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,

,

,

, Deformation of WLCSP assembly with build-up layer and microvia (all at 110°C).

Figure 12.23

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TABLE 12.4

473

Comparison of Maximum Displacement (mm) Sn96.5-Ag3.5 on microvia build-up PCB

Sn62-Ag2-Pb36 on microvia build-up PCB

Sn96.5-Ag3.5 on conventional PCB

588

0.019

0.017

0.028

4,188

0.017

0.018

0.022

7,788

0.017

0.018

0.021

11,388

0.017

0.019

0.020

14,988

0.017

0.019

0.019

Time (s)

epoxy glass (18 ppm/°C) PCB, the solder joints are subjected to a very large shear deformation (especially the corner solder joint). It is interesting to note that at 588 s, the maximum displacement of the assembly is 0.019 mm. This value is 46 percent smaller than that of the same Sn96.5-Ag3.5 solder-bumped WLCSP PCB assembly without the build-up layer (column 4 of Table 12.4.)24 This is because: (1) the global thermal expansion mismatch between the silicon chip and the build-up PCB forces the whole assembly to deform into a concave shape; (2) the local thermal expansion mismatch between the build-up resin and the FR-4 PCB forces the build-up PCB to deform into a convex shape (opposite to the global deformation); and (3) the local thermal expansion mismatch between the silicon chip and the build-up resin introduces a considerable amount of shear creep deformation in the solder joints. At 4,188, 7,788, 11,388, and 14,988 s, the global deformation of the assembly becomes less concave and the local deformation of the build-up PCB becomes more convex. These deformed shapes are very different from those of the WLCSP on the conventional PCB assembly, which always deform in concave shapes. This is because there is less bonding between the chip and the build-up PCB and more creep strains in the solder joints. The deformed shapes of the Sn62-Ag2-Pb36 solder-bumped WLCSPs on the same build-up microvia PCBs have been obtained in Sec. 12.2, and the corresponding maximum displacements are shown in the third column of Table 4. It can be seen that there is not much difference between the assemblies with Sn96.5-Ag3.5 and Sn62-Ag2-Pb36. 12.3.3.2 Responses in the microvias. The von Mises stress contours in the microvia of the WLCSP assembly at 588 s (110°C of the first thermal cycle) and at 14,988 s (110°C of the fifth thermal cycle) are shown in Figs. 12.24 and 12.25, respectively. It can be seen that the stresses in the microvia do not change much from thermal cycle to cycle. Also, it

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Chapter Twelve

Figure 12.24 von Mises stress contours in microvia (time = 588 s).

Figure 12.25 von Mises stress contours in microvia (time = 14,988 s).

should be noted that the maximum von Mises stress (108 MPa) in the microvia is less than the ultimate strength (∼200 MPa) of the electroplated copper. The total effective plastic strains in the microvia of the WLCSP assembly at 588 s and 14,988 s are shown in Figs. 12.26 and 12.27, respectively. It can be seen that the strains in the microvia also do not change much from thermal cycle to cycle. Also, the maximum effective strain in the microvia is very small (<1.2 percent). 12.3.3.3

Responses in the corner solder joint

Figure 12.28 shows the shear stress and shear creep strain hysteresis loops for multiple cycles at the center of the corner solder joint made of the Sn96.5-Ag3.5 solder. It can be seen that the hysteresis loops converge after the third thermal cycle. The loop size of the present case is larger than that24 of the case without the build-up layer. This is because the thermal expansion mismatch among the chip, the build-up resin, and the PCB is larger than that between the chip and the PCB. Hysteresis loops.

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12.26 Effective plastic strain contours in microvia (time = 588 s).

Figure

12.27 Effective plastic strain contours in microvia (time = 14,988 s).

Figure

Creep hysteresis loops at the center of the corner solder joint.

Figure 12.28

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Chapter Twelve

Time-dependent shear stress. The shear stress history at the center of the corner Sn96.5-Ag3.5 solder joint on the microvia build-up PCB is shown in Fig. 12.29. It can be seen that the shear stress range at the fifth thermal cycle is 35.4 MPa. This is much larger than that (28 MPa) at the center of the corner Sn96.5-Ag3.5 solder joint on the conventional PCB.24 Again, this is because of the larger thermal expansion mismatch among the chip, the build-up resin, and the PCB. The shear stress history at the center of the corner Sn62-Ag2-Pb36 solder joint on the microvia build-up PCB has been determined in Sec. 12.2, and the shear stress range at the fifth thermal cycle is 33.37 MPa (Table 12.5), which is smaller than that for the Sn96.5-Ag3.5 lead-free solder. Time-dependent shear creep strain. The shear creep strain history at the center of the corner Sn96.5-Ag3.5 solder joint on the microvia build-up PCB is shown in Fig. 12.30. It can be seen that the shear creep strain range at the fifth thermal cycle is 0.016. This is much larger than that (0.01) at the center of the corner Sn96.5-Ag3.5 solder joint on the conventional PCB.24 Thus, the effect of the build-up layer is to increase the stresses and creep strains in the solder joints. The shear creep strain history at the center of the corner Sn62-Ag2-Pb36 solder joint on the microvia build-up PCB has been determined in Sec. 12.2, and the shear creep strain range at the fifth thermal cycle is 0.015 (Table 12.5), which is slightly smaller than that for the Sn96.5-Ag3.5 solder. Creep strain energy density range. The creep strain energy density range at the center of the corner Sn96.5-Ag3.5 solder joint on the microvia build-up PCB can be determined from the area of the fifth shear stress and shear creep strain hysteresis loop, which is 0.36 MPa. This is much larger than that (0.26 MPa) at the center of the corner Sn96.5-Ag3.5 sol-

Shear stress time history at the center of the corner solder joint.

Figure 12.29

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TABLE 12.5

477

Comparison of Creep Analysis Results Sn96.5-Ag3.5 on microvia build-up PCB

Sn62-Ag2-Pb36 on microvia build-up PCB

Sn96.5-Ag3.5 on conventional PCB

Shear stress range (MPa)

35.400

33.37

28.00

Creep shear strain range

0.016

0.015

0.010

Creep strain energy density range (MPa)

0.36

0.32

0.26

Item

der joint on the conventional PCB.24 Thus, the effect of the build-up layer is to increase the creep strain energy density range of the solder joints. The creep strain energy density range at the center of the corner Sn62-Ag2-Pb36 solder joint on the microvia build-up PCB has been determined in Sec. 12.2, and the creep strain energy density range at the fifth thermal cycle is 0.32 MPa (Table 12.5), which is slightly smaller than that for the Sn96.5-Ag3.5 lead-free solder. 12.3.4 Summary

Time-temperature-dependent nonlinear analyses of solder-bumped WLCSP on PCB assemblies with Sn96.5-Ag3.5 solder joints have been presented. The effects of microvia build-up PCB on the WLCSP solder joint reliability have also been provided. The implicit creep model (TBOPT=8) of ANSYS release 5.6.1 is used for this chapter. Some important results are summarized as follows.

Shear creep strain time history at the center of the corner solder joint.

Figure 12.30

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Chapter Twelve

1. The effects of the additional microvia build-up layer in the Sn96.5Ag3.5 lead-free solder-bumped WLCSP PCB assemblies are to reduce the global deflection of the assemblies and to increase the local displacement of the solder joints. 2. The effects of the additional microvia build-up layer in the Sn96.5Ag3.5 lead-free solder-bumped WLCSP PCB assemblies are to increase the shear stress range, shear creep strain range, and creep strain energy density range in the solder joints, especially the corner one. 3. The effect of the additional microvia build-up layer in the Sn96.5Ag3.5 lead-free solder-bumped WLCSP PCB assemblies is to reduce the thermal fatigue life of the solder joints, especially the corner one. 4. The shear stress range, shear creep strain range, and creep strain energy density range in the Sn96.5-Ag3.5 lead-free solder joints of the microvia build-up PCB assemblies are slightly larger than those in the Sn62-Ag2-Pb36 solder joints on the microvia build-up PCB assemblies. Thus, the thermal fatigue life of the Sn62-Ag2-Pb36 solder joints is slightly better than that of the Sn96.5-Ag3.5 solder joints. 5. The maximum stress in the microvia for the current imposed thermal loading condition is less than the ultimate strength of the electroplated copper. Also, the maximum strain in the microvia is very small. 12.4 Microvia PCB Thickness Effect on WLCSP Solder Joint Reliability71 In Secs. 12.2 and 12.3, we showed that the effects of build-up layers are (1) reduced global deformation of the whole assembly and increased local deformation of the solder joints; (2) increased shear stress range in the solder joints; (3) increased creep shear strain range in the solder joints; and (4) reduced solder joint thermal fatigue life. In the present section, the focus is placed on the effects of PCB thickness on the WLCSP solder joint reliability. Three cases with various PCB thicknesses, namely, 1.575 mm (62 mil), 1 mm (40 mil), and 0.5 mm (20 mil), are considered. All the other constituents and boundary conditions are the same as in the previous cases. 12.4.1 Deflection of the WLCSP assemblies 12.4.1.1 PCB without build-up layer. Figures 12.31a through 12.31e show the deformed shape (50×) of the Sn62-Ag2-Pb36 solder-bumped WLCSP on the 1.575-mm-thick PCB assembly (Fig. 12.2, without the microvia build-up layer) at 588, 4,188, 7,788, 11,388, and 14,988 s. It is observed as expected that, due to the mismatch of thermal expansion between the silicon chip and the FR-4 PCB, the solder joints are subjected to very large shear loading (especially the corner solder joint). Also, the whole structure deforms into a concave shape at these instants (all at 110°C). Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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s

,

s

,

s

,

s

,

s

Deformation of WLCSP assembly without build-up layer (all at 110°C). Figure 12.31

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Chapter Twelve

It is interesting to note that the maximum deflection of the assembly is 0.028 mm at 588 s. However, at 4188 s, the maximum deflection of the assembly is reduced by 21 percent to 0.022 mm. This is because the increasing deformation of solder joints relaxes the bonding between the chip and the PCB. By the same token, at 7,788 s, the maximum deflection of the assembly is reduced by 5 percent to 0.021 mm; at 11,388 s, the maximum deflection of the assembly is reduced by 4.7 percent to 0.020 mm; and at 14,988 s, the maximum deflection of the assembly is reduced by 2 percent to 0.0196 mm. 12.4.1.2 PCB with microvia build-up layer. Figures 12.32a through 12.32e present the deformed shapes (50×) at 588, 4,188, 7,788, 11,388, and 14,988 s. (They are the same as those in Figs. 12.23a through 12.23e, except that a different finite element mesh is used.) It is observed again that, due to the mismatch of thermal expansion among the silicon chip, the FR-4 PCB, and the build-up resin (CTE = 50 × 10−6/°C), the solder joints experience very large shear deformation (especially the corner solder joint). At 588 s, the maximum deflection of the assembly is 0.017 mm, which is 65 percent smaller than that of the PCB without the build-up layer (Fig. 12.31a). This is because (1) the global mismatch of thermal expansion between the silicon chip and the build-up PCB forces the whole assembly to deform into a concave shape; (2) the local mismatch of thermal expansion between the build-up resin and the FR-4 PCB forces the build-up PCB to deform into a convex shape (exactly opposite to the global deformation); and (3) the local mismatch of thermal expansion between the silicon chip and the build-up resin introduces a considerable amount of creep shear strain into the solder joints. However, at 4188 s, the deformity of the whole assembly is no longer in a concave shape. Instead, the assembly expands in the horizontal direction. This phenomenon may be attributed to the three aforementioned reasons except that the cumulative creep shear strain in the solder joints is much larger than before. In other words, the structural constraint between the silicon chip and the build-up PCB has been substantially relaxed. As a result, the local mismatch of thermal expansion between the build-up resin and the PCB becomes larger than the global mismatch between the chip and the build-up PCB. At 7,788, 11,388, and 14,988 s, the whole assembly (except the chip) tends to bend into a convex shape. This is because (1) the structural constraint between the chip and the build-up PCB is much less than before, and (2) the local mismatch is much more than the global mismatch. In summary, the solder joints on the build-up PCB with microvias are subjected to much larger deformations than those on the conventional PCB, especially the corner solder joint. Similar phenomena have been observed for the assemblies with other two PCB thicknesses. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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481

,

,

,

,

Deformation of WLCSP assembly with build-up layer and microvia (all at 110°C).

Figure 12.32

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Figure 12.33

Deformation of WLCSP on microvia PCB with different thicknesses.

Solder Joint Reliability of Flip Chip on Microvia PCB/Substrate

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Chapter Twelve

12.4.1.3 PCB thickness effects. Figure 12.33 shows the deformations of the WLCSP on microvia build-up PCB with different thicknesses. The presented results are the deformed shape (25×) of the fifth thermal cycle at four different temperatures (110, 70, 25, and −20°C, respectively), as shown in Fig. 12.6. It can be seen that, in general: (1) the thinner the PCB (less bending stiffness), the larger the global deformation; (2) the lower the temperature (less creep strain in solder joints), the larger the global deformations (stiffer structural constraint between the chip and the build-up PCB); and (3) when the temperature becomes negative, the build-up PCB starts to bend upward (especially near the free edge of the assembly) due to the local mismatch of thermal expansion between the resin and the FR-4 PCB (the resin tends to shrink more than the FR-4 PCB). 12.4.2 Stress and strain in the microvia

The von Mises stress contours and effective plastic strain contours in the microvia on the 1.575-mm-thick PCB of the WLCSP assembly at

p ,

,

p , Figure 12.34

,

Stress/strain in microvia (PCB thickness = 1.575 mm).

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485

14,988 s (110°C) and 17,088 s (−20°C) are shown in Figs. 12.34a through 12.34d, respectively. It can be seen that the stresses and strains in the microvia at high temperatures are smaller than those at low temperatures. This phenomenon may be attributed to the fact that, at low temperature, the global deformation is larger due to less creep strain in the solder joints (as explained in the previous section). The von Mises stress contours and effective plastic strain contours in the microvia on the 1-mm- and 0.5-mm-thick PCBs of the WLCSP assembly are shown in Figs. 12.35 and 12.36, respectively. It can be seen that their behaviors are very similar to those for the 1.575-mmthick PCB. Therefore, it may be concluded that the von Mises stress and the effective plastic strain in the microvia are not sensitive to the PCB thicknesses under consideration. Also, it should be noted that all obtained von Mises stresses in the microvia are lower than the ultimate strength of electroplated copper.

p ,

,

p , Figure 12.35

,

Stress/strain in microvia (PCB thickness = 1.0 mm).

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Chapter Twelve

p ,

,

p , Figure 12.36

,

Stress/strain in microvia (PCB thickness = 0.5 mm).

12.4.3 Nonlinear responses of solder joints 12.4.3.1 Creep hysteresis loops. For creep analyses, the material responses should be investigated for multiple cycles until the hysteresis loops are stabilized. For the three PCB thicknesses under investigation, Figs. 12.37, 12.38, and 12.39 present five cycles of shear stress and shear creep strain hysteresis loops at various locations in the corner solder joint of the WLCSP assembly. It is found that the hysteresis loops become stable after three cycles and the loop size becomes smaller for the thinner PCB. It should be noted that the diagrams in the right columns of Figs. 12.37, 12.38, and 12.39 show the hysteresis loops of the fifth thermal cycle, which will be used to determine the shear stress range, creep shear strain range, and strain energy density range in the following sections.

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j

s

s

c

487

j

s

j

Creep hysteresis loops (right column shows the fifth loops of the left column) (PCB thickness = 1.575 mm). Figure 12.37

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Chapter Twelve

j

s

s

c

j

s

j

Figure 12.38 Creep hysteresis loops (right column shows the fifth loops of the left column) (PCB thickness = 1.0 mm).

12.4.3.2 Shear stress range. The shear stress ranges at the center, top, and upper right corner of the corner solder joint are 33.37, 34.03, and 39.43 MPa, respectively, for the case with 1.575-mm-thick PCB; 31.03, 30.98, and 39.40 MPa, respectively, for the case with 1-mm-thick PCB; and 28.96, 26.96, and 39.40 MPa, respectively, for

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s

s

c

489

j

j

s

j

Figure 12.39 Creep hysteresis loops (right column shows the fifth loops of the left column) (PCB thickness = 0.5 mm).

the case with 0.5-mm-thick PCB. These values are summarized in Table 12.6. It can be seen that (1) the thinner the PCB, the smaller the shear stress range, and (2) the shear stress range at the upper right corner of the corner solder joint is the largest due to stress concentration.

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Chapter Twelve

TABLE 12.6

Comparison of Shear Stress Range PCB thickness (mm) 1.575

Location in solder joint

1.0

0.5

Shear stress range of the 5th cycle (MPa)

Center

33.37

31.03

28.96

Top

34.03

30.98

26.96

Corner

39.43

39.4

39.4

It should be pointed out that the shear stress range at the center of the corner solder joint on the 1.575-mm PCB without microvias is 28.5 MPa,24,25 which is much smaller than that with microvias (33.4 MPa). Thus, the effect of the microvia build-up layer on PCB is to increase the shear stress in the solder joints. 12.4.3.3 Creep shear strain range. The creep shear strain ranges at the center, top, and upper right corner of the corner solder joint are 0.015, 0.023, and 0.087, respectively, for the case with 1.575-mm-thick PCB; 0.011, 0.017, and 0.083, respectively, for the case with 1-mm-thick PCB; and 0.008, 0.012, and 0.082, respectively, for the case with 0.5-mmPCB. These values are summarized in Table 12.7. It can be seen that: (1) the thinner the PCB, the smaller the creep shear strain range, and (2) the creep shear strain range at the center of the corner solder joint is the smallest and that at the upper right corner of the corner solder joint is the largest due to strain concentration. It should be noted that the creep shear strain range at the center of the corner solder joint on the 1.575-mm PCB without microvias is 0.01,24,25 which is much smaller than that (0.015) with microvias. Thus, the effect of the microvia build-up layer on PCB is to increase the creep shear strain range in the solder joints. 12.4.3.4 Strain energy density range. The strain energy density ranges at the center, top, and upper right corner of the corner solder joint are TABLE 12.7

Comparison of Creep Shear Strain Range PCB thickness (mm) 1.575

Location in solder joint Center

1.0

0.5

Creep shear strain range of the 5th cycle 0.015

0.011

0.008

Top

0.023

0.017

0.012

Corner

0.087

0.083

0.082

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0.32, 0.498, and 2.09 MPa, respectively, for the case with 1.575-mm-thick PCB; 0.194, 0.318, and 1.94 MPa, respectively, for the case with 1-mmthick PCB; and 0.131, 0.185, and 1.91 MPa, respectively, for the case with 0.5-mm PCB. These values are summarized in Table 12.8. It can be seen that (1) the thinner the PCB, the smaller the strain energy density range, and (2) the strain energy density range at the center of the corner solder joint is the smallest and that at the upper right corner of the corner solder joint is the largest due to stress and strain concentrations. It should be pointed out that the strain energy density range at the center of the corner solder joint on the 1.575-mm PCB without microvias is 0.16 MPa,24,25 which is much smaller than that (0.32 MPa) with microvias. Thus, the effect of the microvia build-up layer is to increase the strain energy density range in the solder joints. As a result, the build-up layer on PCB tends to reduce the thermal fatigue life of solder joints. 12.4.4 Summary

The solder joint reliability of a WLCSP on three different thicknesses of build-up PCBs with microvias has been investigated. Nonlinear finite element analyses with implicit creep constitutive model have been performed to study the effects of PCB thickness. Some important results are summarized as follows. ■

In general, the effect of the build-up layer of PCB on the solder joint reliability is to increase the stress range, creep strain range, and creep strain energy density range in the solder joints and to reduce the thermal fatigue life.

■

With the presence of the microvia build-up layer, the thinner PCB leads to larger global deflection but smaller local deformation under thermal loading.

■

For all cases investigated, the maximum stress in the microvia is lower than the ultimate strength of the electroplated copper.

■

In general, the creep responses in the solder joint converge in less than four thermal cycles.

TABLE 12.8

Comparison of Creep Strain Energy Density Range PCB thickness (mm) 1.575

Location in solder joint Center

1.0

0.5

Creep strain energy density range of the 5th cycle (MPa) 0.320

0.194

0.131

Top

0.498

0.318

0.185

Corner

2.090

1.940

1.910

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■

In the corner solder joint, the creep hysteresis loop size is the smallest at the center and the largest at the upper right corner due to stress and strain concentrations.

■

With the presence of the microvia build-up layer, the thinner PCB results in smaller shear stress range, creep shear strain range, and creep strain energy density range in the solder joints under the thermal loading. Hence, the thinner build-up board should lead to longer thermal fatigue life of solder joints.

■

In order to reduce the mismatch of thermal expansion among the chip, solder, build-up layer, and PCB (and to have less stress and strain on the solder joints), build-up resins with a lower coefficient of thermal expansion (<30 × 10−6/°C) are recommended.

12.5 Crack Propagation in Flip Chip Solder Joints How does a crack grow (propagate) in flip chip solder joints during thermal cycling? This is a frequently asked question, and the answer could be useful in designing for the reliability of flip chip solder joints. In this section, the crack length of a WLCSP solder joint is measured as a function of the number of thermal cycles. Empirical equations for predicting the thermal-fatigue life of flip-chip solder joints are proposed that use the crack tip fracture characteristics, such as those shown in Sec. 12.6 for the stress intensity factors KI (opening mode) and KII (shearing mode), those shown in Sec. 12.7 for the J-integrals, and those shown in Sec. 12.8 for the average creep strain energy density. 12.5.1 A low-cost WLCSP

Figure 12.40 shows the silicon chip under consideration. This chip is 6.5 × 6.5 × 0.5 mm and has 48 pads (with 0.2-mm pitch) on two opposite sides. After wafer-level redistribution, the pads (0.33 mm in diameter) are in area-arrayed format with 0.75-mm pitch. The WLCSP consists of a copper conductor layer and two low-cost polyimide dielectric layers. Figure 12.41 shows the details of redistribution. It can be seen that the Sn63-Pb37 solder bump is supported by a copper core, which is connected to the redistributed Cu-Ni pad through the Cu-Ti UBM. The redistributed metal layer is made of Cu-Ni. A typical cross section of the WLCSP bump (∼0.33 mm in height and ∼0.39 mm in diameter) is shown in Fig. 12.42. The average shear force of the solder bumps is ∼400 gf.19 It is very easy to assemble the WLCSP on a 0.52-mm-thick FR-4 PCB. After the Sn63-Pb37 solder-bumped WLCSP is aligned with the PCB with look-up and look-down cameras, then a no-clean flux is applied on the PCB, and finally the chip is placed face down on the PCB Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Figure 12.40

493

A memory chip with redistribution.

Figure 12.41

Cross section of the

WLCSP.

with a very minimal force. After the chip is placed, it is put on the conveyor belt of a reflow oven with a maximum on-PCB temperature of ∼230°C (Fig. 12.43). Due to the large amount of solder volume and the surface tension during solder reflow, the assembly process is very robust. A typical cross section of the WLCSP-PCB assembly is shown in Fig. 12.44, which clearly demonstrates the unique solder-bumped flip chip selfalignment characteristics. (The solders on the chip before joining to the PCB are called solder bumps. After the solder bumps have been reflowed on the PCB, they are called solder joints.) Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Chapter Twelve

Figure 12.42 WLCSP bump with copper core.

Figure 12.43

solder

SMT reflow temperature profile.

12.5.2 Thermal cycling of WLCSP on PCB assemblies

The WLCSP on PCB assemblies are subjected to thermal cycling tests. The temperature loading imposed on the assemblies is shown in Fig. 12.45. It can be seen that for each cycle (60 min) the temperature is between −20 and +110°C, with 15 min ramp, 20 min hold at hot, and 10 min hold at cold. Again, there are two reasons for choosing this temperature profile: (1) the glass transition temperature of the FR-4 PCB is 120°C and we don’t want to introduce additional failure mechanisms of the solder joint due to the degradation of the PCB; and (2) the behavior of solder below −20°C is not very well understood. 12.5.3 Crack propagation of the corner solder joint

It should be pointed out that, unlike most of the solder-joint reliability studies, which are done to generate enough test data to fit into a life distribution,10 one of the objectives of this section is to determine the crack initiation and crack propagation in solder joints of the WLCSP on PCB assemblies. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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(a)

(a) Cross section of the WLCSP assembly. (b) Enlarged cross section of the WLCSP assembly.

Figure 12.44

(b)

Figure 12.45

Temperature cycling profile.

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The initiation and propagation of cracks in any structures have always been very complicated phenomenon. The initial crack length and crack growth length are also difficult to define. In this chapter, at 100, 200, 500, 800, 1000, 1200, 1500, 2000, and 2400 cycles, three of the WLCSP on PCB assemblies are taken out from the thermal cycling chamber for inking and cross-sectioning. Cracks of the cross-sectioned samples are inspected under a high-power microscope. Important results are summarized as follows: 1. No obvious cracks occur in the solder joints up to 800 cycles (Figs. 12.46a and 12.47a). It should be pointed out that, because of the

Figure 12.46

Cross sections of the corner solder joint at different thermal cycles.

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Figure 12.47 Schematic of the corner solder joint at different stages of thermal cycles.

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Chapter Twelve

small sample size (three samples) and the power of the microscope, there could be some very small cracks initiated much earlier. 2. Between 800 and 1000 cycles, there are visible cracks on both sides of the corner solder joint. The inner crack length (toward the center of the chip) is 25 µm and the outer crack length is 40 µm (Fig. 12.46b). The outer crack is initiated first, as shown in Fig. 12.47b. 3. Between 1000 and 1200 cycles, the inner crack length propagates to 37 µm while the outer crack length grows to 48 µm (Figs. 12.46c and 12.47c). 4. Between 1200 and 1500 cycles, the inner crack length is 70 µm and the outer crack length is 100 µm (Fig. 12.46d). 5. Between 1500 and 2000 cycles, the inner crack length grows to 100 µm and the outer crack length grows to 140 µm (Fig. 12.46e). 6. Between 2000 and 2400 cycles, the cracks separate the corner solder joint (Figs. 12.46f and 12.47d). 7. In the corner solder joint, the cracks initiate and grow near the copper pad of the PCB. 12.5.4 Fatigue crack growth rate

Figure 12.48 shows the inner and outer crack lengths of the corner solder joint as a function of the thermal cycling number N. The results can be curve-fitted, as shown in Fig. 12.49, into the following forms: log (a) = C1 log (N) + C2

Figure 12.48

(12.4)

Test results: crack length vs. thermal cycle

number.

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Figure 12.49

499

Curve-fitting of crack length vs. thermal cycle

number.

or a = 10C2 NC1

(12.5)

N = 10−C2/C1 a1/C1

(12.6)

and

Differentiating Eq. (12.5) with respect to N yields da ᎏ = C1 10C2 N(C1 − 1) dN

(12.7)

Substituting Eq. (12.6) into Eq. (12.7) gives da ᎏ = C1 10C2/C1 a(C1 − 1)/C1 dN

(12.8)

where a is the crack length, N is the number of cycles, and C1 and C2 are given in Table 12.9. Thus, for the corner solder joint, the length of outer and inner cracks can be determined by Eq. (12.5) for a given number of thermal cycles. Also, the fatigue crack growth rate da/dN of the corner solder joint can be obtained from Eq. (12.8). 12.5.5 Crack length distribution of all solder joints

Because of the solder joints’ distance to neutral point (DNP) is not the same, the crack length of all the solder joints can be different. In general, the solder joint with the largest DNP will lead to the largest crack

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TABLE 12.9

Curve-Fitting Constants C1, C2, C3, C4 (DK)

Curve-fitted

Location

C1

C2

C3

C4

Crack length vs. cycles

Inner crack Outer crack

1.8605 1.8019

−4.1427 −3.8061

— —

— —

Stress intensity factor vs. crack length

Inner crack Outer crack

— —

— —

0.5868 0.6104

0.4851 0.5196

length for the same number of thermal cycles. Figure 12.50 shows the mapping of the outer crack lengths in the solder joints at 2400 cycles. Indeed, the outer crack lengths of the first-row solder joints (labeled 1, 9, 17, 25, 33, and 41) are larger than those of the second- and third-row solder joints. Also, the corner solder joints have the largest crack length. 12.6 Elastic Thermal Fatigue Life Prediction Model (DK) Even though the initiation and propagation of the outer crack and the inner crack (toward the chip center) of the corner solder joint are not exactly the same, for the sake of modeling simplicity, they are assumed to be equal. Figure 12.51 shows the corner solder joint for fracture mechanics finite element modeling. It can be seen that the solder joint is 0.24 mm tall and the diameters of the bottom and top surfaces are 0.28 and 0.3 mm, respectively. 12.6.1 Boundary-value problem

The solder joint is made of Sn63-Pb37 solder and has a Young’s modulus of 10 GPa, a Poisson ratio of 0.4, and a CTE of 21 × 10−6/°C. The

Figure 12.50

Crack length distribution in solder joints.

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Figure 12.51

501

Corner solder joint for modeling.

Young’s modulus, Poisson ratio, and CTE for copper are 76 GPa, 0.34, and 17 × 10−6/°C, respectively. The CTE of FR-4 PCB is 18.5 × 10−6/°C, and that of Si chip is 2.5 × 10−6/°C. Because of the WLCSP on PCB assembly’s global thermal expansion mismatch (3.2259 × 130 × [18.5 − 2.5] × 10−6 = 0.0067 mm) between the Si chip and the FR-4 PCB, and the thermal expansion of the corner solder joint, the solder is subjected to a complex state of stress and strain during thermal cycling conditions. These stresses and strains produce the driving force for solder joint failure. Since most of the thermal fatigue life of ductile materials such as solder is spent in propagating the crack (i.e., fatigue crack growth), the stresses and strains (stress intensity factors, J-integral, or creep strain energy density) around the crack tips of cracks of different lengths in the solder joint are of utmost interest. In this section, five different crack lengths are considered for the stress intensity factors. These cracks are located symmetrically 10 µm above the copper pad on the PCB. The eight-node plain strain element is used, and the units are newtons and millimeters. At the crack tip, the mid-side nodes are placed at the quarter points to capture the singularity in the stresses. The boundary conditions imposed on the corner solder joint are shown in Fig. 12.51, where the bottom surface is fixed, the top surface (nodes) of the solder joint is subjected to a displacement of 0.0067 mm, and the whole solder joint is subjected to a temperature change of Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Chapter Twelve

130°C. The top surface is also restrained from rotation by specifying nodal couplings of vertical displacement to those nodes so that the vertical displacements are the same. With the prescribed loadings, the left crack in Fig. 12.51 is expected to pop open and the right crack should remain closed. Instead of using contact elements, nodal couplings are conveniently used to simulate the closing and sliding of the right crack surfaces. In ANSYS, the nodes on the right crack surfaces are nodal-coupled in the vertical direction at the coincident nodes while being free to slide in the horizontal direction. Using nodal couplings means there is no penetration of the crack surfaces when the crack is closed. Figures 12.52 through 12.56 show the deformed (with finite element meshes) and undeformed shapes of the corner solder joint with different crack lengths: 0.028, 0.056, 0.084, 0.112, and 0.133 mm. The typical von Mises stress contours around the crack tips (with a crack length = 0.112 mm) are shown in Fig. 12.57. It can be seen that, due to stress concentration, the stresses at the crack tip are very large. The stress intensity factors ∆KI (opening mode I) and ∆KII (shearing mode II) at the inner and outer crack tips for different crack lengths of the corner solder joint are shown in Fig. 12.58. It can be seen that the fracture characteristics at the crack tips are dominated by the shearing mode of fracture (due to the thermal expansion mismatch between the Si chip and FR-4 PCB), especially at larger crack lengths.

Figure 12.52 Deformation shape of the corner solder joint (crack length = 0.028 mm).

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Figure 12.53 Deformation shape of the corner solder joint (crack length = 0.056 mm).

Figure 12.54 Deformation shape of the corner solder joint (crack length = 0.084 mm).

12.6.2 Elastic thermal fatigue life prediction model

Define the effective stress intensity factor range ∆Keff as 2 ∆Keff = 兹∆K 苶 ∆K2II I +苶

(12.9)

The curves in Fig. 12.58 can be curve-fitted, as shown in Fig. 12.59 (only the middle three points are used since the crack initiation [near the first point] is not very well defined and the solder joint fracture [near the fifth point] is not stable) into the following forms:

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Figure 12.55 Deformation shape of the corner solder joint (crack length = 0.112 mm).

Figure 12.56 Deformation shape of the corner solder joint (crack length = 0.133 mm).

log (∆Keff) = C3 log (a) + C4

(12.10)

a = 10−C4/C3 ∆K1/C eff

(12.11)

or 3

The constants C3 and C4 are given in Table 12.9. Substituting Eq. (12.11) into Eq. (12.8) yields da (C1−1)/C1C3 ᎏ = C1 10(C2C3 − C1C4 + C4)/C1C3 ∆Keff dN

(12.12)

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von Mises stress contour at the tip of outer (left) and inner (right) cracks (crack length = 0.112 mm).

Figure 12.57

Figure 12.58

Stress intensity factor vs. crack length.

Thus, for the inner crack, C1 = 1.8606; C2 = −4.1427; C3 = 0.5868; C4 = 0.4851, and Eq. (12.12) becomes da ᎏ = 0.0046∆K 0.79 eff dN

(12.13)

For the outer crack, C1 = 1.8019, C2 = −3.8061, C3 = 0.6104, C4 = 0.5196, and Eq. (12.12) becomes da ᎏ = 0.0058∆K0.73 eff dN

(12.14)

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Figure 12.59 Curve-fitting of the effective stress intensity factor range at the crack tip of different crack length in the corner solder joint.

By averaging the coefficients of Eq. (12.13) and (12.14), the elastic thermal fatigue life prediction equation (in the form of Paris’s law) for flip chip solder joints can be expressed as da ᎏ = 0.0052∆K0.76 eff dN

(12.15)

Thus, for a given solder-bumped flip chip assembly, once the effective stress intensity factor range ∆Keff in terms of the crack length a is determined for a given temperature cycling condition by computational modeling, the number of cycles to failure N can be estimated by Eq. (12.15). 12.6.3 Summary

Crack initiation and propagation in WLCSP on PCB solder joints subjected to a thermal cycling condition has been presented in Sec. 12.5. Cross sections of the assemblies at different thermal cycles have been inspected and discussed. Stress intensity factors at the tips of cracks of different lengths in the corner solder joint have also been determined in Sec. 12.6 by fracture mechanics with the finite element method. Some important results are summarized as follows: ■

Corner solder joint cracks were seen to initiate at two different locations, one near the chip center (inner crack) and the other on the opposite side of the solder joint (outer crack). These cracks are right above the copper pad of the PCB.

■

The outer crack of the corner solder joint initiates first and grows slightly larger than the inner crack at higher thermal cycles.

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■

The outer and inner cracks of the corner solder joint meet between 2000 and 2400 cycles. This indicates that the present WLCSP on PCB solder joints are reliable for use under most of the operating conditions, even without underfill encapsulant.

■

For the WLCSP on PCB under consideration, the crack length of the corner solder joint as a function of the number of thermal cycles has been measured and determined as shown in Eq. (12.5). Also, the thermal fatigue crack growth rate of the corner solder joint is given in Eq. (12.7) in terms of the number of thermal cycles and in Eq. (12.8) in terms of the crack length.

■

For the WLCSP on PCB under consideration, the effective stress intensity factor range at the crack tip as a function of the crack length of the corner solder joint has been determined and is given by Eq. (12.11). Also, the thermal fatigue crack growth rate in terms of the effective stress intensity factor range of the corner solder joint is given by Eq. (12.12).

■

A new thermal fatigue life prediction model for flip chip solder joints is proposed as shown in Eq. (12.15).

12.7 Plastic Thermal Fatigue Life Prediction (DJ) In Sec. 12.6, based on linear elastic theory, a thermal fatigue life prediction model for solder-bumped flip chip on PCB/substrate is obtained. In this section, another new model is proposed that is based on elastoplastic properties of the solder joints. 12.7.1 Boundary-value problem

The boundary-value problem is exactly the same as that in Sec. 12.6, except that now the solder joints are assumed to be an elastoplastic material (Fig. 12.60). Also, the Young’s modulus (Fig. 12.61) and the stressstrain relations (Fig. 12.62) of the solder are temperature dependent. Again, because of the WLCSP on PCB assembly’s global thermal expansion mismatch (3.2259 × 130 × [18.5 − 2.5] × 10−6 = 0.0067 mm) between the Si chip and the FR-4 PCB, and the thermal expansion of the solder joints, the solder is subjected to a complex state of stress and strain during thermal cycling conditions. These stresses and strains produce the driving force for solder joint failure. Since most of the thermal fatigue life of ductile materials such as solder is spent in propagating the crack (i.e., fatigue crack growth), the nonlinear stresses and strains (Jintegrals) around the crack tip of different crack lengths in the solder joint are of utmost interest. In its simplest form, the J-integral is defined as a path-independent line integral that measures the strength of the singular stresses and strains near a crack tip (Fig. 12.63). The following equation shows an Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Figure 12.60

Corner solder joint for modeling.

Figure 12.61

Temperature-dependent Young’s modulus

of solder.

expression for J in its two-dimensional form. It assumes that the crack lies in the global cartesian x-y plane, with x parallel to the crack. J=

∂u ∂u 冕 Wdy − 冕 冢t ᎏ + t ᎏ 冣ds ∂x ∂y x

Γ

Γ

x

y

y

(12.16)

where: Γ = any path surrounding the crack tip W = strain energy density tx = traction along x-axis = σxnx + σxyny Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Figure 12.62

509

Temperature-dependent stress-strain relation

of solder.

Figure 12.63 J-integral contour path surrounding a crack tip.

ty = traction along y-axis = σyny + σxynx σ = stress component n = unit outward normal to path u = displacement s = distance along the path In this section, five different crack lengths are considered. These cracks are located symmetrically 10 µm above the copper pad on the PCB. The eight-node plain strain element is used, and the units are in newtons and millimeters. At the crack tip, the mid-side nodes are placed at the quarter points to capture the singularity in the stresses. The boundary conditions imposed on the corner solder joint are shown in Fig. 12.60, where the bottom surface is fixed, the top surface (nodes) of the solder joint is subjected to a displacement of 0.0067 mm, and the whole solder joint is subjected to a temperature change of 130°C. The top surface is also restrained from rotation by specifying Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Chapter Twelve

nodal couplings of vertical displacement to those nodes so that the vertical displacements are the same. Again, with the prescribed loadings, the left crack in Fig. 12.60 is expected to pop open and the right crack should remain closed. Instead of using contact elements, nodal couplings are conveniently used to simulate the closing and sliding of the right crack surfaces. In ANSYS (a commercial finite element code),29 the nodes on the right crack surfaces are nodalcoupled in the vertical direction at the coincident nodes while being free to slide in the horizontal direction. Using nodal couplings means there is no penetration of the crack surfaces when the crack is closed. Figures 12.64 through 12.68 show the deformed (with finite element meshes) and undeformed shapes of the corner solder joint with different crack lengths: 0.056, 0.084, 0.112, 0.1225, and 0.133 mm. The typical von Mises stress contours around the crack tips (with a crack length = 0.112 mm) are shown in Fig. 12.69. It can be seen that, due to stress concentration, the stresses at the crack tip are very large. The J-integrals at the inner and outer crack tips for different crack lengths of the corner solder joint are shown in Fig. 12.70. 12.7.2 Elastoplastic thermal fatigue life prediction model

The curves in Fig. 12.70 can be curve-fitted, as shown in Fig. 12.71 (only four points are used since the solder joint fracture [near the fifth point] is not stable) into the following forms: log (∆J) = C3 log (a) + C4

(12.17)

a = 10−C4/C3 ∆J1/C3

(12.18)

or

Deformed shape of the corner solder joint (crack length = 0.056 mm, ∆J_inner crack = 0.0704 MPa/mm, ∆J_outer crack = 0.0791 MPa/ mm).

Figure 12.64

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Deformed shape of the corner solder joint (crack length = 0.084 mm, ∆J_inner crack = 0.0918 MPa/mm, ∆J_outer crack = 0.126 MPa/mm). Figure 12.65

Deformed shape of the corner solder joint (crack length = 0.112 mm, ∆J_inner crack = 0.175 MPa/mm, ∆J_outer crack = 0.183 MPa/mm).

Figure 12.66

Deformed shape of the corner solder joint (crack length = 0.1225 mm, ∆J_inner crack = 0.284 MPa/mm, ∆J_outer crack = 0.313 MPa/mm). Figure 12.67

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Chapter Twelve

Deformed shape of the corner solder joint (crack length = 0.133 mm, ∆J_inner crack = 1.163 MPa/mm, ∆J_outer crack = 1.133 MPa/mm).

Figure 12.68

Figure 12.69 von Mises stress contour at the tip of outer (left) and inner (right) cracks (crack length = 0.112 mm).

Figure 12.70 J-integral ranges of different crack lengths in the corner solder joint.

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Figure 12.71 Curve-fitting of the J-integral ranges of different crack lengths in the corner solder joint.

The constants C3 and C4 are given in Table 12.10. Substituting Eq. (12.18) into Eq. (12.4) yields da ᎏ = C1 10(C2C3 − C1C4 + C4)/C1C3 ∆J (C1 − 1)/C1C3 dN

(12.19)

Thus, for the inner crack, C1 = 1.8606, C2 = −4.1427, C3 = 1.655, C4 = −4.108, and Eq. (12.19) becomes da ᎏ = 0.155∆J0.279 dN

(12.20)

For the outer crack, C1 = 1.8019, C2 = −3.8061, C3 = 1.557, C4 = −3.854, and Eq. (12.19) becomes da ᎏ = 0.176∆J0.286 dN

(12.21)

Equations (12.20) and (12.21) are shown in Fig. 12.72. By averaging the coefficients of Eqs. (12.20) and (121.21), the thermal fatigue life prediction equation (Fig. 12.72) for flip chip solder joints can be expressed as da ᎏ = 0.166∆J0.28 dN TABLE 12.10

(12.22)

Curve-Fitting Constants C1, C2, C3, C4 (DJ)

Curve-fitted

Location

C1

C2

C3

C4

Crack length vs. cycles

Inner crack Outer crack

1.8605 1.8019

−4.1427 −3.8061

— —

— —

J-integral vs. crack length

Inner crack Outer crack

— —

— —

1.655 1.557

−4.108 −3.854

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Chapter Twelve

Figure 12.72

Fatigue crack growth rate curves.

Thus, for a given solder-bumped flip chip assembly, once the J-integral range (∆J) in terms of the crack length a is determined for a given temperature cycling condition by computational modeling, the number of cycles to failure N can be estimated by Eq. (12.22). 12.7.3 Summary

A simple empirical equation for predicting the thermal fatigue life of solder bumped flip chip on low-cost PCB or substrate has been presented. It is derived by combining the measured thermal fatigue crack growth rate of the corner solder joint and the simulated nonlinear fracture characteristics (J-integral) at the crack tip of the corner solder joint with various crack lengths. The use of the proposed equation is very simple. For any given Sn63Pb37 solder-bumped flip chip on FR-4 epoxy PCB assembly, once the J-integral range in terms of the crack length is determined for a given temperature cycling condition by computational modeling, then the number of cycles to failure of the solder joint can be estimated by the integration of the proposed equation. 12.8 Creep Thermal Fatigue Life Prediction Model (DW) In Sec. 12.6 and Ref. 19, an empirical equation for predicting the thermal fatigue life of WLCSP solder joints is presented. However, the equation was based on linear fracture mechanics, and the resulting equation was in terms of the stress intensity factors at the crack tip of the solder joint. In Sec. 12.7 and Ref. 20, the solder is assumed to be an elastoplastic material with temperature dependence, and the resulting

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equation is in terms of the J-integrals at the crack tip of the solder joint. In this section, in addition to being elastoplastic and temperature dependent, the solder is assumed to be a creep material with time dependence, and the resulting equation is in terms of the average strain energy density range (∆W) at the crack tip of the solder joint. In the present approach, the crack length of a WLCSP solder joint is measured as a function of the number of thermal cycles. An empirical equation for predicting the thermal fatigue life of WLCSP solder joints is proposed that uses the nonlinear time and temperature-dependent fracture characteristics, such as the average strain energy density range at the crack tips of cracks of different lengths. 12.8.1 Boundary-value problem

The boundary conditions imposed on the structure are shown in Fig. 12.73. Figure 12.74 shows the corner solder joint for fracture mechanics finite element modeling. It can be seen that the solder joint is 0.24 mm tall and the diameters of the bottom and top surfaces are 0.28 and 0.3 mm, respectively. Because of the WLCSP on PCB assembly’s global thermal expansion mismatch between the Si chip and the FR-4 PCB, and the thermal expansion of the solder joints, the solder is subjected to a complex state of stress and strain during thermal cycling condition. These stresses and strains produce the driving force for solder joint failure. Since most of the thermal fatigue life of ductile materials such as solder is spent in propagating the crack (i.e., fatigue crack growth), the stresses and strains (such as the strain energy density)26 around the crack tips of cracks of different lengths in the solder joint are of utmost interest.

Figure 12.73

Thermal and displacement cycling profiles.

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Chapter Twelve

Figure 12.74

Corner solder joint for modeling.

The solder joint is made of Sn60-Pb40 solder and has a Poisson ratio of 0.4 and a coefficient of thermal expansion (CTE) of 21 × 10−6/°C. The material properties of the solder are time dependent (see Fig. 12.75 for the constitutive equation) and temperature dependent.9,10 The Young’s modulus, Poisson ratio, and CTE for copper are 76 GPa, 0.34, and 17 ×

Figure 12.75 Constitutive equation of Sn60-Pb40 solder under creep conditions.

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10−6/°C, respectively. The CTE of FR-4 PCB is 18.5 × 10−6/°C and that of Si chip is 2.5 × 10−6/°C. In this section, three different crack lengths are considered. These cracks are located symmetrically 10 µm above the copper pad on the PCB. The 8-node plain strain element is used, and the units are newtons and millimeters. At the crack tip, the mid-side nodes of the triangular elements, as shown in Fig. 12.76, are placed at the quarter points to capture the singularity in the stresses.29 Contact elements are used to simulate the closing and sliding of the crack surfaces. The whole solder joint is subjected to a temperature profile T(°C). As shown in Fig. 12.73, the bottom surface is fixed. The top surface (nodes) of the solder joint is subjected to a global thermal expansion mismatch displacement, ∆ = 3.2259 × T(°C) × [18.5 − 2.5] × 10−6 mm, as shown in Figs. 12.73 and 12.74. The top surface is also restrained from rotation by specifying nodal couplings of vertical displacement to those nodes so that the vertical displacements are the same. Figures 12.77 through 12.79 show the deformed (with finite element meshes) and undeformed shapes of the corner solder joint with different crack lengths: 0.056, 0.084, and 0.112 mm. The typical von Mises stress contours around the crack tips (with a crack length = 0.112 mm) are shown in Fig. 12.80. It can be seen that, due to stress concentration, the stresses at the crack tips are very large. Figures 12.81 through 12.83 show the shear creep strain history, shear stress history, and shear stress and shear creep strain hysteresis loops at the middle between the crack tips (Fig. 12.79 with crack length = 0.112 mm) of the corner solder joint for three full thermal cycles. It can be seen

Figure 12.76 Elements around a crack tip for averaged strain energy density calculation.

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Chapter Twelve

Deformed shape of the corner solder joint (crack length = 0.056 mm, t = −20°C).

Figure 12.77

Deformed shape of the corner solder joint (crack length = 0.084 mm, t = −20°C).

Figure 12.78

Deformed shape of the corner solder joint (crack length = 0.112 mm, t = −20°C).

Figure 12.79

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Figure 12.80 von Mises stress contour at the tips of the outer (left) and inner (right) cracks (crack length = 0.112 mm).

Shear creep strain history at the middle of crack tips of the corner solder joint.

Figure 12.81

that the responses converge. The shear creep strain range is about 0.33 and the shear stress range is about 90 MPa. Figures 12.84 through 12.86 show the shear creep strain history, shear stress history, and shear stress and shear creep strain hysteresis loops at a point near the crack tip (crack length = 0.112 mm) of the corner solder joint for three full thermal cycles. Again, the responses converge. However, as expected, the shear creep strain range is very large (about 0.72) and the shear stress range is also very large (about 115 MPa). Theoretically speaking, because of singularity, the strain energy density at the crack tip is infinite. Practically, however, the average strain energy density per thermal cycle around the crack tip is used to deterDownloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Chapter Twelve

Shear stress history at the middle of crack tips of the corner solder joint.

Figure 12.82

Hysteresis loops at the middle of crack tips of the corner solder joint.

Figure 12.83

mine the thermal fatigue life of solder joints. In this section, the strain energy density around a crack tip is obtained by averaging across the elements in an area of 0.02 × 0.02 mm in the two-dimensional model as shown in Fig. 12.76. (For the case of conventional solder-bumped flip chip on board assembly, where the copper pad is about 3 to 4 mil and the solder joint height is about 1 to 2 mil for eutectic solder and 3 to 4 mil for high-temperature solder, the area for averaging the strain energy density should be 0.008 × 0.008 mm.) There are about 100 elements in the 0.02 × 0.02-mm area. The crack tip is modeled with two rows of elements. The elements in the first row are triangular with the mid-side nodes skewed to 1⁄4 points, as suggested by ANSYS29 for the effect of crack tip singularity. The radius of the first row is 0.0037 mm, i.e., about 20 percent of the length of one Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Figure 12.84 Shear creep strain history near one of the crack tips of the corner solder joint.

Shear stress history near one of the crack tips of the corner solder joint.

Figure 12.85

side (0.02 mm) of the square area as shown in Fig. 12.76. (For the case of conventional flip chip on board assembly, the radius is about 0.0016 mm.) There are 16 uniform angular divisions around the crack tip. The quadrilateral elements on the second row have a radial length half of that of the first row. Regular meshes are generated for the remaining area used in the strain energy density calculation. The average strain energy density of the elements in this area at any instant during the viscoplastic process is normalized by the volume of the elements. ΣWelement × Velement Wt = ᎏᎏᎏ ΣVelement

(12.23)

where Wt is the average viscoplastic strain energy density at time point t, Welement is the viscoplastic strain energy density in each element and Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Chapter Twelve

Hysteresis loops near one of the crack tips of the corner solder joint.

Figure 12.86

is directly extracted from ANSYS in its postprocessing, and Velement is the volume of each element. For a two-dimensional problem, however, ANSYS gives the volume of each element in its postprocessing by assuming a unit thickness. The accumulated average strain energy density in a complete thermal cycle from time t1 to time t2 is calculated by Wt2 − Wt1. Here, values of t1 = 7,200 s and t2 = 10,800 s at the beginning and ending of the third cycle, respectively, are used. The accumulated average strain energy density range in the third thermal cycle around the inner and outer crack tips for different crack lengths of the corner solder joint is shown in Fig. 12.87. It can be seen that the larger the crack length, the larger

Average strain energy density range of different crack length in the corner solder joint.

Figure 12.87

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the average strain energy density range. Also, for a given crack length, the average strain energy density range around the outer crack tip is larger than that around the inner crack tip. 12.8.2 Elastoplastic creep thermal fatigue life prediction model

The curves in Fig. 12.87 can be curve-fitted, as shown in Fig. 12.88, into the following forms log (∆W) = C3 log (a) + C4

(12.24)

a = 10−C4 /C3 ∆W 1/C3

(12.25)

or

The constants C3 and C4 are given in Table 12.11. Substituting Eq. (12.25) into Eq. (12.24) yields da ᎏ = C1 10(C2C3 − C1C4 + C4)/C1C3 ∆W(C1 − 1)/C1C3 dN

(12.26)

Thus, for the inner crack, C1 = 1.8606, C2 = −4.1427, C3 = 2.406, C4 = −3.887, and Eq. (12.26) becomes da ᎏ = 0.062∆W 0.192 dN

(12.27)

Curve-fitting of the average strain energy density range of different crack length in the corner solder joint.

Figure 12.88

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Chapter Twelve

TABLE 12.11

Curve-Fitting Constants C1, C2, C3, C4 (DW)

Curve-fitted

Location

C1

C2

C3

C4

Crack length vs. cycles

Inner crack Outer crack

1.8605 1.8019

−4.1427 −3.8061

— —

— —

Strain energy vs. crack length

Inner crack Outer crack

— —

— —

2.406 1.677

−3.887 −2.347

For the outer crack, C1 = 1.8019, C2 = −3.8061, C3 = 1.677, C4 = −2.347, and Eq. (12.26) becomes da ᎏ = 0.058∆W0.265 dN

(12.28)

Equations (12.27) and (12.28) are shown in Fig. 12.89. By averaging the coefficients of Eqs. (12.27) and (12.28), the thermal fatigue life prediction equation (Fig. 12.89) for flip chip solder joints can be expressed as da ᎏ = 0.06∆W0.25 dN

(12.29)

Thus, for a given solder-bumped flip chip assembly, once the average strain energy range (∆W) in terms of the crack length a is determined for a given temperature cycling condition by computational modeling, the number of cycles to failure N can be estimated by Eq. (12.29).

Figure 12.89

Fatigue crack growth rate curves.

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12.8.3 Summary

A new and simple empirical equation for predicting the thermal fatigue life of solder-bumped flip chip on low-cost PCB has been presented. It is derived by combining the measured thermal fatigue crack growth rate of the corner solder joint and the simulated nonlinear fracture characteristics (average strain energy density range per cycle) around the crack tips of cracks of different lengths in the corner solder joint. The use of the proposed equation is very simple. For any given WLSCP PCB assembly and solder-bumped flip chip on PCB assembly, once the average strain energy density range per thermal cycle in terms of the crack length is determined for a given temperature cycling condition by computational modeling, then the number of cycles to failure of the corner solder joint can be estimated by the integration of the proposed equation. The element sizes and shapes and the area around the crack tip for calculating the average strain energy density are recommended for the WLCSP PCB assembly. For the conventional solder-bumped flip chip on PCB assemblies, these parameters for determining the average strain energy density are also recommended. 12.9 Solder Joint Reliability of Underfilled Flip Chip on Microvia PCB/Substrate In this chapter so far, only nonunderfilled solder-bumped flip chip or WLCSP on PCB or substrate with and without microvias have been considered. The effects of underfill encapsulant on the solder joint reliability of flip chips on low-cost PCBs or substrates have been discussed extensively in the literature (see for examples, Refs. 72–126).72 The focus of this section is to investigate the effects of microvia build-up PCBs or substrates on the reliability of underfilled solder-bumped flip chip. 12.9.1 Structure

Figure 12.90 schematically shows the silicon chip under consideration. The dimensions of the chip are 8 × 8 × 0.51 mm. It has peripheral pads (0.1 × 0.1 mm) with a spacing of 0.1 mm. All the pads have solder bumps and the bump height is about 0.1 mm. Figures 12.91 and 12.92 show the solder-bumped flip chip on PCB with underfill encapsulant. It can be seen that the PCB is 1.575 mm thick and is made of FR-4 epoxy glass. The copper pad thickness is 0.018 mm. The underfill is about 0.07 mm thick and is made of silica filler and bis-phenol-type epoxy and trade secret resins. Figure 12.93 shows the finite element model of the assembly with dimensions of the microvia and solder joint. It doesn’t look good, but it captures the key features of the present problem and saves lots of computing time.

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Chapter Twelve

Figure 12.90

mm chip.

Figure 12.91

Dimensions for finite element model.

Figure 12.92

Dimensions of solder joint and

Schematic of 8 × 8

copper pad.

12.9.2 Material properties

In this section the solder alloy is Sn62-Pb36-Ag2, which obeys the Garofalo-Arrhenius constitutive equation and is shown in Fig. 12.5. The material properties of the silicon chip, FR-4 PCB, copper, and underfill are shown in Table 12.3. Figures 12.94 and 12.95 (E = Young’s modulus) show the temperature dependence of the underfill. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.

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Figure 12.93

527

Finite element model of DCA with micro-

via PCB.

Figure 12.94

Coefficient of thermal expansion for underfill.

Figure 12.95

Young’s modulus for underfill.

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Chapter Twelve

12.9.3 Loading conditions

The temperature loading imposed on the solder-bumped flip chip on board assemblies is shown in Fig. 12.6. Five full cycles are executed. 12.9.4 Deformed shapes

Figures 12.96a through 12.96e shown the deformed shapes (50×) of the Sn62-Ag2-Pb36 solder-bumped flip chip on microvia build-up PCB with underfill encapsulant at 588, 4,188, 71,1388, and 14,988 s (temperature ∼110°C, Fig. 12.6). It can be seen that the whole assembly is deformed into a concave shape. This is due to (1) thermal expansion mismatch among the chip, solder joint, underfill, build-up resin, microvia, and PCB; (2) the underfill encapsulant, which tightly holds the chip and the build-up PCB together; and (3) the CTE of the silicon chip, which is the smallest among all the materials. It is interesting to note from Fig. 12.96 that the build-up PCB is trying to bend downward (in the opposite direction of the global deformation). This is because of the local thermal expansion mismatch between the build-up resin (50 × 10−6/°C) and the PCB (18 × 10−6/°C). 12.9.5 Shear stress

The shear stress (MPa) in the solder joint at 588, 4,188, 7,788, 11,388, and 14,988 s (temperature ∼110°C, Fig. 12.6) is shown in Figs. 12.97a through 12.97e. It can be seen that at these instants the shear stress contours do not change much from thermal cycle to cycle and the maximum shear stress—about 12.5 MPa—occurs near the lower right corner of the solder joint. 12.9.6 Shear creep strain

The shear creep strain in the solder joint at 588, 4,188, 7,788, 11,388, and 14,988 s is shown in Figs. 12.98a through 12.98e. It can be seen that at these instants the shear creep strain contours are increasing from thermal cycle to cycle. Due to strain concentration, the maximum shear creep strain occurs near the lower right corner of the solder joint. With the build-up PCB, the maximum shear creep strain is larger than that with the conventional PCB. 12.9.7 von Mises stress in the microvia

The von Mises stress (MPa) in the microvia at 588, 4,188, 7,788, 11,388, and 14,988 s is shown in Figs. 12.99a through 12.99e. It can be seen that at these instants the von Mises stress contours do not change much from thermal cycle to cycle and the maximum von Mises stress—

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Deformed shapes at (a) 588 s, (b) 4,188 s, (c) 7,788 s, (d) 11,388 s, and (e) 14,988 s.

Figure 12.96

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Chapter Twelve

Stress contours at (a) 588 s, (b) 4,188 s, (c) 7,788 s, (d) 11,388 s, and (e) 14,988 s.

Figure 12.97

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Shear creep strain contours at (a) 588 s, (b) 4,188 s, (c) 7,788 s, (d) 11,388 s, and (e) 14,988 s. Figure 12.98

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Chapter Twelve

Figure 12.99 von Mises stress contours (MPa) at (a) 588 s, (b) 4,188 s, (c) 7,788 s, (d) 11,388 s, and (e) 14,988 s.

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about 97 MPa—occurs near the lower right corner of the microvia and is less than the ultimate strength of the electroplated copper. 12.9.8 Effective plastic strain in the microvia

The effective plastic strain in the microvia at 588, 4,188, 7,788, 11,388, and 14,988 s is shown in Figs. 12.100a through 12.100e. It can be seen that at these instants the effective plastic strain contours do not change much from thermal cycle to cycle and that the maximum effective plastic strain is <1 percent. 12.9.9 Hysteresis loops

For creep analysis, it is important to study the responses for multiple cycles until the hysteresis loops become stabilized. Figure 12.101 shows the shear stress and shear creep strain hysteresis loops for multiple cycles at the center of solder joint made by the Sn62-Ag2-Pb36 solder alloy. It can be seen that the creep shear strain is quite stabilized after the first cycle and converges after the third cycle. 12.9.10 Shear stress time history

The shear stress history at the center of solder joint made by the Sn62-Ag2-Pb36 solder alloy is shown in Fig. 12.102. It can be seen that at this location the shear stress history follows the imposed thermal cycling condition (Fig. 12.6). The shear stress range is 16.5 MPa, which is larger than that (12.5 MPa) of the conventional PCB. This is due to the high CTE of the build-up resin and the thicker build-up PCB. 12.9.11 Creep shear strain time history

The creep shear strain history at the center of the solder joint made by the Sn62-Ag2-Pb36 solder alloy is shown in Fig. 12.103. It can be seen that, at this location, just as with the shear stress history, the creep shear strain history follows the imposed thermal cycling condition. 12.9.12 Summary

Nonlinear time history analyses of underfilled flip chip on microvia build-up PCB with the Sn62-Ag2-Pb36 solder joints have been presented. Some important results are summarized as follows. ■

The maximum stress in the microvia is less than half of the ultimate strength of the electroplated copper.

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12.100 Effective total strain contours at (a) 588 s, (b) 4,188 s, (c) 7,788 s, (d) 11,388 s, and (e) 14,988 s. Figure

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Hysteresis loops for the Sn62-Pb36Ag2 corner solder joint.

Figure 12.101

Shear stress history for the Sn62-Pb36Ag2 corner solder joint.

Figure 12.102

Shear creep strain history for the Sn62Pb36-Ag2 corner solder joint.

Figure 12.103

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■

The maximum total strain in the microvia is less than 1 percent.

■

The effects of the microvia build-up layer on PCB on the solder joints are to increase the stress and strain and to reduce the thermal fatigue lives of the solder joints. However, it should be pointed out that, because of the underfill encapsulant, these effects are not as pronounced as those without underfill encapsulant.

12.10 Effects of Double-Side Microvia Build-Up Layers on WLCSP Solder Joint Reliability In Secs. 12.2 through 12.4 and Sec. 12.9, the effects of microvia build-up (on only the top side of the PCB) on the solder joint reliability of WLCSP have been presented. In this section, the effects of microvia build-up (on both top and bottom sides) on the solder joint reliability of WLCSP are discussed. The problem considered herein is exactly the same as that in Sec. 12.2 with creep analysis, except in the present case there is microvia build-up on both sides of the PCB. The deformations of the double-side microvia build-up WLCSP assembly at different time steps are shown in Fig. 12.104b, along with those with microvia build-up on only the top side of the PCB (Fig. 12.104a, Fig. 12.32, or Fig. 12.23). It can be seen that they are very similar, except that: (1) the one with the double-side build-up layer has more global deformation between the silicon chip and the microvia build-up substrate, and (2) the one with the single-side build-up layer has more local deformation between the microvia build-up layer and the epoxy PCB. This is because (1) the effective TCE of the double-side build-up layer substrate is larger than that of the single-side build-up layer substrate, and (2) the local bending of the double-side build-up layer substrate is smaller. The deformations at various temperatures at the fifth cycle for these two cases are shown in Figs. 12.105a and 12.105b. Again, it can be seen that the one with double-side build-up substrate has more global deformation between the chip and the substrate and less local bending of the substrate. Figures 12.106a and 12.106b show the stress (MPa) and strain in the top-side microvia for these two cases. It can be seen that at the fifth cycle, the differences between these two cases are not very significant. The creep hysteresis loops at the center of the corner solder joint for these two cases are shown in Figs. 12.107a and 12.107b. It can be seen that they are very similar. The shear stress ranges, creep shear strain ranges, and creep strain energy density ranges for these two cases are summarized in Table 12.12. It can be seen that for all these parame-

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(a)

537

(b)

Comparison of deformation at various thermal cycles (all at 110°C). (a) Single-side build-up layer. (b) Double-side build-up layers.

Figure 12.104

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(a)

(b)

Figure 12.105 Comparison of deformation at various temperatures (all in the fifth cycle). (a) Single-side build-up layer. (b) Double-side build-up layers.

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(a)

(b)

Comparison of stress/strain contours at the top-side buildup layer in the microvias. (a) Single-side build-up layer. (b) Double-side build-up layers.

Figure 12.106

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(a)

(b)

(c)

(d)

Figure 12.107 Comparison of creep hysteresis loops at the center of the corner solder joint (PCB thickness = 62 mil). The right column shows the fifth loops of the left column. (a) Single-side build-up layer. (b) Double-side build-up layers.

ters, the values for the double-side build-up layer assembly are higher than those for the single-side build-up layer assembly. This could be due to the increased thickness of the double-side build-up layer substrate. Of course, the difference in global and local thermal expansion mismatch between these two cases plays some role as well.

TABLE 12.12

Single-Side vs. Double-Side Microvia Build-up PCB WLCSP corner solder joint

Item Shear stress range (MPa)

On single-side microvia build-up PCB 33.37

On double-side microvia build-up PCB 30.3

Creep shear strain range

0.015

0.013

Creep strain energy density range (MPa)

0.32

0.23

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83. Zhao, J., X. Dai, and P. Ho, “Analysis and Modeling Verification for Thermal-Mechanical Deformation in Flip-Chip Packages,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 336–344, Seattle, WA, May 1998. 84. Matsushima, H., S. Baba, and Y. Tomita, “Thermally Enhanced Flip-Chip BGA with Organic Substrate,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 685–691, Seattle, WA, May 1998. 85. Gurumurthy, C., L. G. Norris, C. Hui, and E. Kramer, “Characterization of Underfill/Passivation Interfacial Adhesion for Direct Chip Attach Assemblies Using Fracture Toughness and Hydro-Thermal Fatigue Measurements,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 721–728, Seattle, WA, May 1998. 86. Palaniappan, P., P. Selman, D. Baldwin, J. Wu, and C. P. Wong, “Correlation of Flip Chip Underfill Process Parameters and Material Properties with In-Process Stress Generation,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 838–847, Seattle, WA, May 1998. 87. Qu, J., and C. P. Wong, “Effective Elastic Modulus of Underfill Material for Flip-Chip Applications,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 848–850, Seattle, WA, May 1998. 88. Sylvester, M., D. Banks, R. Kern, and R. Pofahl, “Thermomechanical Reliability Assessment of Large Organic Flip-Chip Ball Grid Array Packages,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 851–860, Seattle, WA, May 1998. 89. Wiegele, S., P. Thompson, R. Lee, and E. Ramsland, “Reliability and Process Characterization of Electroless Nickel-Gold/Solder Flip Chip Interconnect,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 861–866, Seattle, WA, May 1998. 90. Caers, J., R. Oesterholt, R. Bressers, T. Mouthaan, and J. Verweij, “Reliability of Flip Chip on Board: First Order Model for the Effect on Contact Integrity of Moisture Penetration in the Underfill,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 867–871, Seattle, WA, May 1998. 91. Roesner, B., X. Baraton, K. Guttmann, and C. Samin, “Thermal Fatigue of Solder Flip-Chip Assemblies,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 872–877, Seattle, WA, May 1998. 92. Pang, J, T. Tan, and S. Sitaraman, “Thermo-Mechanical Analysis of Solder Joint Fatigue and Creep in a Flip Chip on Board Package Subjected to Temperature Cycling Loading,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 878–883, Seattle, WA, May 1998. 93. Gopalakrishnan, L., M. Ranjan, Y. Sha, K. Srihari, and C. Woychik, “Encapsulant Materials for Flip-Chip Attach,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 1291–1297, Seattle, WA, May 1998. 94. Yang, H., S. Bayyuk, A. Krishnan, A. Przekwas, L. Nguyen, and P. Fine, “Computational Simulation of Underfill Encapsulation of Flip-Chip ICs, Part I: Flow Modeling and Surface-Tension Effects,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 1311–1317, Seattle, WA, May 1998. 95. Liu, S., J. Wang, D. Zou, X. He, Z. Qian, and Y. Guo, “Resolving Displacement Field of Solder Ball in Flip-Chip Package by Both Phase Shifting Moire Interferometry and FEM Modeling,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 1345–1353, Seattle, WA, May 1998. 96. Wang, L., and C. P. Wong, “Novel Thermally Reworkable Underfill Encapsulants for Flip-Chip Applications,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 92–100, Seattle, WA, May 1998. 97. Shi, S. H., and C. P. Wong, “Study of the Fluxing Agent Effects on the Properties of No-Flow Underfill Materials for Flip-Chip Applications,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 117–124, Seattle, WA, May 1998. 98. Wong, C. P., D. Baldwin, M. B. Vincent, B. Fennell, L. J. Wang, and S. H. Shi, “Characterization of a No-Flow Underfill Encapsulant During the Solder Reflow Process,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 1253–1259, Seattle, WA, May 1998.

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Chapter Twelve

99. Hong, B., and T. Yuan, “Integrated Flow—Thermomechanical and Reliability Analysis of a Low Air Cooled Flip Chip–PBGA Package,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 1354–1360, Seattle, WA, May 1998. 100. Wang, J., Z. Qian, D. Zou, and S. Liu, “Creep Behavior of a Flip-Chip Package by Both FEM Modeling and Real Time Moire Interferometry,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 1439–1445, Seattle, WA, May 1998. 101. Peterson, D. W., J. S. Sweet, S. N. Burchett, and A. Hsia, “Stresses from Flip-Chip Assembly and Underfill: Measurements with the ATC4.1 Assembly Test Chip and Analysis by Finite Element Method,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 134–143, San Jose, CA, May 1997. 102. Zhou, T., M. Hundt, C. Villa, R. Bond, and T. Lao, “Thermal Study for Flip Chip on FR-4 Boards,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 879–884, San Jose, CA, May 1997. 103. Wong, C. P., M. B. Vincent, and S. Shi, “Fast-Flow Underfill Encapsulant: Flow Rate and Coefficient of Thermal Expansion,” Proceedings of the ASME—Advances in Electronic Packaging, 19(1):301–306, 1997. 104. Wong, C. P., S. H. Shi, and G. Jefferson, “High Performance No Flow Underfills for Low-Cost Flip-Chip Applications,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 850–858, San Jose, CA, May 1997. 105. Gektin, V., A. Bar-Cohen, and S. Witzman, “Thermo-Structural Behavior of Underfilled Flip-Chips,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 440–447, Orlando, FL, May 1996. 106. Wu, T. Y., Y. Tsukada, and W. T. Chen, “Materials and Mechanics Issues in Flip-Chip Organic Packaging,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 524–534, Orlando, FL, May 1996. 107. Doot, R. K., “Motorola’s First DCA Product: The Gold Line Pen Pager,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 535–539, Orlando, FL, May 1996. 108. Greer, S. T., “An Extended Eutectic Solder Bump for FCOB,” Proceedings of IEEE Electronic Components & Technology Conference, pp. 546–551, Orlando, FL, May 1996. 109. Lau, J. H., Krulevitch, T., Schar, W., Heydinger, M., Erasmus, S., and Gleason, J., “Experimental and Analytical Studies of Encapsulated Flip Chip Solder Bumps on Surface Laminar Circuit Boards,” Circuit World, 19(3):18–24, March 1993. 110. Lau, J. H., M. Heydinger, J. Glazer, and D. Uno, “Design and Procurement of Eutectic Sn/Pb Solder-Bumped Flip Chip Test Die and Organic Substrates,” Proceedings of the IEEE International Manufacturing Technology Symposium, pp. 132–138, San Diego, CA, September 1994. 111. Wun, K. B., and J. H. Lau, “Characterization and Evaluation of the Underfill Encapsulants for Flip Chip Assembly,” Proceedings of the IEEE International Manufacturing Technology Symposium, pp. 139–146, San Diego, CA, September 1994. 112. Kelly, M., and J. H. Lau, “Low Cost Solder Bumped Flip Chip MCM-L Demonstration,” Proceedings of the IEEE International Manufacturing Technology Symposium, pp. 147–153, San Diego, CA, September 1994. 113. Lau, J. H., “Solder Joint Reliability of Flip Chip and Plastic Ball Grid Array Assemblies Under Thermal, Mechanical, and Vibration Conditions,” IEEE Trans. Component, Packaging, and Manufacturing Technol. B, 19(4):728–735, November 1996. 114. Lau, J. H., E. Schneider, and T. Baker, “Shock and Vibration of Solder Bumped Flip Chip on Organic Coated Copper Boards,” ASME Trans. J. Electronic Packaging, 118:101–104, June 1996. 115. Lau, J. H., C. Chang, and R. Chen, “Effects of Underfill Encapsulant on the Mechanical and Electrical Performance of a Functional Flip Chip Device,” J. Electronics Manufacturing, 7(4):269–277, December 1997. 116. Lau, J. H., and C. Chang, “How to Select Underfill Materials for Solder Bumped Flip Chip on Low Cost Substrates?” IMAPS Trans. Int. J. Microelectronics & Electronic Packaging, 22(1):20–28, first quarter 1999.

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117. Lau, J. H., C. Chang, and O. Chien, “SMT Compatible No-Flow Underfill for Solder Bumped Flip Chip on Low-Cost Substrates,” J. Electronics Manufacturing, 8(3,4): 151–164, December 1998. 118. Lau, J. H., and C. Chang, “Characterization of Underfill Materials for Functional Solder Bumped Flip Chips on Board Applications,” IEEE Trans. Components and Packaging Technol. A, 22(1):111–119, March 1999. 119. Lau, J. H., S.-W. Lee, C. Chang, and O. Chien, “Effects of Underfill Material Properties on the Reliability of Solder Bumped Flip Chip on Board with Imperfect Underfill Encapsulants,” IEEE Trans. Components and Packaging Technol., 23(2): 323–333, 2000. 120. Lau, J., C. Chang, C. Chen, R. Lee, T. Chen, D. Cheng, T. Tseng, and D. Lin, “Design and Manufacturing of Micro Via-In-Pad (VIP) Substrates for Solder Bumped Flip Chip Applications,” J. Electronics Manufacturing, 10(1):79–87, 2000. 121. Lau, J. H., “Cost Analysis: Solder Bumped Flip Chip Versus Wire Bonding,” IEEE Trans. Electronics Packaging Manufacturing, 23:4–11, March 2000. 122. Lau, J. H., and R. Lee, “Fracture Mechanics Analysis of Low-Cost Solder Bumped Flip Chip Assemblies with Imperfect Underfill,” ASME Trans. J. Electronic Packaging, 122(4):306–310, December 2000. 123. Lau, J. H., C. Chang, and R. Lee, “Failure Analysis of Solder Bumped Flip Chip on Low-Cost Substrate,” IEEE Trans. Electronics Packaging Manufacturing, 23(1): 19–27, 2000. 124. Lau, J. H., C. Chang, and C. Chen, “Characteristics and Reliability of No-Flow Underfills for Solder Bumped Flip Chips on Low Cost Substrates,” IMAPS Trans. Int. J. Microelectronics & Electronic Packaging, 22(4):370–381, 1999. 125. Lau, J. H., C. Chang, and R. Chen, “Effects of Underfill Encapsulant on the Mechanical and Electrical Performance of a Functional Flip Chip Device,” J. Electronics Manufacturing, 7(4):269–277, December 1997. 126. Lau, J. H., and R. Lee, “Effects of Underfill Delamination and Chip Size on the Reliability of Solder Bumped Flip Chip on Board,” IMAPS Trans. Int. J. Microelectronics & Electronic Packaging, 23(1):33–39, 2000.

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Solder Joint Reliability of Flip Chip on Microvia PCB/Substrate

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.