Electrostatic Discharge: Understand, Simulate, and Fix ESD Problems

Electrostatic Discharge IEEE Press 445 Hoes Lane Piscataway, NJ 08854 IEEE Press Editorial Board Lajos Hanzo, Editor i...

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Electrostatic Discharge

IEEE Press 445 Hoes Lane Piscataway, NJ 08854 IEEE Press Editorial Board Lajos Hanzo, Editor in Chief R. Abari J. Anderson S. Basu A. Chatterjee

T. Chen T. G. Croda S. Farshchi B. M. Hammerli

O. Malik S. Nahavandi M. S. Newman W. Reeve

Kenneth Moore, Director of IEEE Book and Information Services (BIS) Jeanne Audino, Project Editor

Electrostatic Discharge Understand, Simulate, and Fix ESD Problems Third Edition

Michel Mardiguian

A John Wiley & Sons, Inc., Publication

Copyright © 2009 by the Institute of Electrical and Electronics Engineers, Inc. Published by John Wiley & Sons, Inc., Hoboken, New Jersey. All rights reserved. Published simultaneously in Canada. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 750-4470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748-6011, fax (201) 748-6008, or online at www.wiley.com/go/permission. Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at (800) 762-2974, outside the United States at (317) 572-3993 or fax (317) 572-4002. Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic formats. For more information about Wiley products, visit our web site at www.wiley.com. Library of Congress Cataloging-in-Publication Data is available. ISBN: 978-0470-39704-6 Printed in the United States of America 10 9 8 7 6 5 4 3 2 1

Contents

Preface to the First Edition

ix

Preface to the Third Edition Acknowledgements

xi

xiii

1. The Electrostatic Discharge Phenomenon 1.1. 1.2. 1.3. 1.4.

Physics Involved 1 Influencing Parameters 6 Various Types of Electrostatic Charging with Humans and Objects 9 Statistics of Voltages and Currents Reached During ESD 1.4.1. Personnel ESD Statistics 15 1.4.2. Furniture and Objects ESD Statistics

1.5.

1

Waveforms of Electrostatic Discharges

13

18 23

1.5.1. Personal ESD Waveforms 23 1.5.2. Furniture ESD Waveforms 28 1.5.3. Summary: Comparison of Dynamic Parameters for Personnel and Furniture ESD 30 1.5.4. Actual versus Idealized ESD Waveforms 31 References 37

2. Effects of ESD on Electronics 2.1. 2.2. 2.3. 2.4.

Direct Discharge to an Electronic Component 39 Direct Discharge to Electronic Equipment Enclosure 50 Indirect Discharge 53 Coupling Mechanisms of ESD Pulse into the Victim’s Circuitry 2.4.1. Magnetic Field Coupling 55 2.4.2. Electric Field Coupling from Indirect ESD on Floating Parts 58 2.4.3. Measured E- and H -Field Values near an ESD to a Grounded Structure 60 2.4.4. Effect of Wave Impedance on Voltages Induced in Nearby PCBs and Small Circuits 64

39

54

vi

Contents

2.5.

2.4.5. Effect of a Typical Metallic Cabinet on ESD-Radiated Effects 2.4.6. Common Impedance Coupling with an ESD 69 Response of Victim Circuits and Type of Errors 70 2.5.1. Influence of Circuit Impedances 72 2.5.2. Specific Disturbance Created by the Hand/Metal Initial Spike 2.5.3. Errors/Malfunctions Induced in Analog Devices 74

67

74

2.6.

Prediction of Actual ESD-Induced Error, Fast Approximation Method 75 2.7. Remarks on the Actual Current Paths and Associated Radiation 2.8. Personnel or Furniture ESD: Which One is Worse? 78 References 79 3. Principal ESD Specifications ESD Test Specifications for Device Sensitivity 82 3.1.1. MIL-Std 883 82 3.1.2. EIA/JEDEC and ESD Association Test Methods 83 3.2. ESD Specifications for Equipment Immunity 84 3.2.1. International Standard IEC 61000-4-2 84 3.2.2. ANSI C.63-16, ESD Test Methods, and Criteria for Electronic Equipment 85 3.2.3. ESD Immunity for Automobile Electronics, SAE J1113-13 and ISO 10605 85 3.2.4. MIL-Std 1541, ESD Immunity Requirements for Space Systems 3.3. Antistatic Control Procedures 86 3.3.1. Military Domain: MIL-Std 1686 and MIL 263 Handbook 86 3.3.2. Industry Standards for Static Control Programs 87 References 88

78

80

3.1.

4. ESD Diagnostics and Testing 4.1.

4.2. 4.3. 4.4.

4.5.

ESD Simulators: How They Work 90 4.1.1. Arc or Direct Contact 92 4.1.2. Simulators for Equipment Test, Based on IEC 61000-4-2 Standard 95 4.1.3. Detailed Review of the IEC 61000-4-2 Simulator Definition 96 4.1.4. Generators with Different Networks, Very High Voltage and Field Enhancement Accessories 105 4.1.5. Special Relays Required for ESD Simulators 108 Furniture Versus Personnel ESD Simulation 109 Other Types of ESD Simulators for Component Testing 112 ESD Test Setup—Direct and Indirect ESD 114 4.4.1. Ground Reference 115 4.4.2. Direct versus Indirect ESD 115 4.4.3. Roles of the HCP and VCP 118 4.4.4. Grounding the Simulator and the EUT 120 4.4.5. External Cables and System Configuration 120 ESD Test Routine and Discharge Procedures 121

86

89

Contents 4.5.1. Preparation of EUT for Test Readiness 4.5.2. Application of the Discharges 122

4.6. 4.7.

121

No Error/No Damage Concept: The Several Layers of Severity The Error per Discharge Concept or Multiple-Trials Approach 4.7.1. Practical Application of the Error per Pulse Concept 4.7.2. ESD Test Plan with Cost-Effectiveness Constraints ESD Test During Design and Development 137

140 143

5. Design for ESD Immunity

5.2.

148

ESD Protection at Component Level 150 5.1.1. Integrated Circuits with Internal ESD Protection 150 5.1.2. Additional ESD Protection: When Is It Needed and How Much? 153 ESD Protection at the PCB Level (Internal Circuitry) 5.2.1. 5.2.2. 5.2.3. 5.2.4.

5.3. 5.4.

125 129

134 135

4.8. 4.9. ESD For Field Diagnostics and Forced Crash Method 4.10. Home-Made Investigation Tools and Diagnostic Hints References 146

5.1.

vii

Reducing the Field-to-PCB Coupling Mechanisms PCB Connectors Areas 159 Signal Ground versus Chassis Ground 160 PCB Hardening with Plastic Products 160

157 158

ESD Protection by Internal Wiring and Mechanical Packaging ESD Protection by Box Shielding and Envelope Design 169

161

5.4.1. 5.4.2. 5.4.3. 5.4.4. 5.4.5.

5.5.

Some Shielding Basics 170 How to Maintain Shield Integrity with Metal Housings 178 How to Make Shield Barriers for Plastic Housings 183 Treatment of Shield Openings 187 Nonmetallized Plastic Boxes 189 ESD Protection of External Cables and I/O Ports 191 5.5.1. External Cable Shielding 192 5.5.2. ESD Hardening of I/O Ports 200 5.5.3. I/O Cable Entries ESD Protection with Plastic Products 219

5.6. ESD Immunity by Software and Noise Inhibition Techniques 5.7. ESD Immunity with Miniature, Portable Devices 223 5.8. System ESD Immunity 225 5.9. ESD Control at Installation Level 226 References 228 6. ESD Cases Studies 6.1. 6.2. 6.3. 6.4. 6.5.

Case Case Case Case Case

1: 2: 3: 4: 5:

The Reradiating Ground Strap 231 ESD Hardening of a Printer 232 The Data Terminal with Floating Tray The Safety Wire “Antenna” 235 The Touchy Watchdog 236

221

230

233

viii

Contents

6.6. 6.7.

Case 6: The Trigger-Happy Air bag Initiator Conclusion: Troubleshooting Hints 237

236

Appendix A. ESD Protection by Design of Chips and Microcircuits

240

Appendix B. Prediction of ESD Damage Level for a Semiconductor Junction 252 Appendix C. Spark-Over Voltages

255

Appendix D. Fatigue Phenomena During Repeated ESD Testing

258

Appendix E. Prediction of ESD-Induced Noise by Fast FrequencyDomain Calculations 260 Appendix F. More Experiments on ESD Coupling to Boxes

269

Appendix G. Examples of Simple SPICE Modeling of ESD Coupling Effects 279 Appendix H. Time-to-Frequency Conversion for a Single Transient Index

295

293

Preface to the First Edition

Static electricity is the most ancient form of electricity known to humans. More than 2000 years ago, the Greeks recognized the attraction between certain materials when they were rubbed together; indeed, the word electricity comes from the Greek elektron, which means amber. During the seventeenth and eighteenth centuries, several key experiments were conducted to understand and measure static electricity. But the discovery of electromagnetism and its formidable breakthrough has rapidly outgrown interest in static electricity. Even today, where the industrial applications of static electricity are not insignificant, they cannot compare with those of electromagnetism and electrodynamics. Ironically, as much as static electricity was relegated to the attic of scientific evolution, she continuously occupied (I say “she” because electricity, in French, is feminine—don’t ask me why) the headlines with her undesirable effects. If we consider the thousands of lightning strikes hitting the terrestrial atmosphere every minute, we have to realize that our planet with its surrounding clouds is nothing more than a huge electrostatic machine constantly charging and discharging on itself. For decades, people have been learning the hard way that statics can cause explosions of fuels and ammunitions. In 1937, the German flying boat Hindenburg arriving in Lakehurst, New Jersey, caught fire while anchoring at its landing mast. What could have been a severe incident became a tragedy: Due to international tension, the United States had put an embargo on helium sales to Germany and the vessel was inflated with hydrogen instead. The resulting fire caused the death of 37 of its hundred or so passengers. Although the causes have not been completely understood, electrostatic discharge (ESD) is at the top of the list. More recently, during the 1970s in the United States, a spacecraft lauching rocket exploded during the fueling operation, killing three engineers. The cause was, beyond any doubt, identified as ESD. Satellites have paid a heavy toll because of ESD, from minor anomalies to severe malfunctions, as in the European Space Agency (ESA) MARECS satellite. In January 1985, during the assembly of a Pershing missile near Heilbronn, Germany, the motor case, made of Kevlar, was repeatedly rubbed against the cushioning in its container. The ensuing ESD caused the 4 tons of highly flammable propellant to catch fire and the motor exploded, blowing parts 125 meters away, killing three people and injuring nine. Although such catastrophes are terrible and spectacular, they are quite rare; but a more insidious aspect of ESD bloomed in the early 1970s, with the massive

x

Preface to the First Edition

arrival of integrated microelectronics. The plants producing integrated circuits (ICs) started to experience disappointing percentage yields. Once thoroughly investigated, the problem was found to be largely due to ESD during all fabrication steps and handling. Although the problem has been fully explained and drastic solutions adopted, ESD is still costing millions of dollars a year of pure losses. Considering the astronomical quantities of ICs manufactured each year, the mere fact that 3 to 30% of them die in infancy because of ESD represents an impressive amount of money. To quote G. C. Quinn, technical editor of Electronics Test Magazine (April 1984): “The volume range of ESD sensitive components is rising faster than the development and usage of ESD protections . . . Estimating costs of ESD failures not caught at manufacturing inspection is far more difficult. Many of the degraded, walking-wounded devices may not show up until after termination of the manufacturer’s guarantee.” Around 1980, Lockheed Corporation reported a one-year cost savings of $1.8 million through static protection measures, which reduced ESD-related failures by a 16 to 1 ratio. Arithmethic, then, tells us that Lockheed had endured losses of $1.92 million the previous year. Even with severe protection measures, some manufacturers still confess that ESD is causing 39 to 48% of their IC rejects. The only hope that the plague will ever be dominated is a progressive awareness of people and the growing use of robots on manufacturing lines. But the worst was yet to come: With the proliferation of microelectronics in all possible applications, an even bigger number of complaints flourished about ESD-related erratic bugs, transient malfunctions, erased memories, and the like. Although the economic losses resulting from erroneous transactions and corrupted data of all kinds are difficult to evaluate, it is probably an even larger figure than the one for chip damage during fabrication. It seems ironic that a physical fact, known for 2500 years as doing nothing but nasty things to us, has continued to defy electronics engineers. Solving the problem of transient errors induced by ESD has not been given the same concerted effort as the manufacturing aspect. Most early research was performed by isolated pioneers fighting with their own weapons. Initiating the research themselves, seldom supported by vast budgets, these men used their sagacity and all the resources they could find to investigate a problem for which no measuring techniques existed. They had to invent the tools they needed, and they had to be statisticians, chemists, and radio-frequency (RF) designers all at once. The names of Ted Madzy, W. Byrne, Michael King, Ralph Calcavecchio, Richard Simonic, and many others that I don’t know of are the people to whom all of us who followed are indebted. By mentioning their work, this book will try to render a piece of the recognition they deserve: They paved the road for bringing the understanding of ESD from black magic up to an analytic method. We hope this book will demystify ESD and give a step-by-step strategy for predicting, testing, and reducing its effects on electronic equipment. Gainesville, Virginia June 1985

Michel Mardiguian

Preface to the Third Edition

The two previous editions of this book had a very favorable reception from the EMC community. However, the first and second editions, published by the EMC consulting firm Interference Control Technologies, had a rather limited distribution and have been out of print since the year 2000. A new edition was sorely needed, incorporating current technological advances with the needs of the engineering community. Since the first edition of this book 22 years ago, the electrostatic discharge (ESD) phenomenon has continued to plague the electronic industry. In spite of undisputable progress in ESD awareness and protection measures, which are inforced by regular audits and accreditations, the “sleeping sentinel” syndrome takes its toll. Inspections often reveal that in an assumed static-free manufacturing chain, all but one of the workstations or handling/packing posts are adequately protected. This single defective link is enough to compromise the entire ESD line of defense. Sometimes it was the very apparatus intended to eliminate human influence, for example, automatic handling by robots, that created a new ESD problem, sometimes worse than the one it was supposed to cure. Once these pernicious problems are fixed, the return on investment of a flawless ESD control program is often spectacular, not forgetting that this is a constant battle because today’s problem is frequently the consequence of some unanticipated effect of yesterday’s solution. Nonetheless, once marketed and sold, some modern equipment, although it has undergone a compete EMC test program that includes ESD, is still experiencing malfunctions, a tangible share of which is traceable to ESD. Consider a recent example: This author, among other consultants, was asked to solve a problem on a certain model of car. Five percent of owners were experiencing a very unpleasant dashboard failure: During operation some displays would freeze up, eventually becoming totally dark without a possibility of reset, even after a stop-and-start action. The problem was a peculiar ESD configuration that had escaped the standard test program. In order to cope with such omnipresent threats, intensive research has continued worldwide, using instrumentation that is much more elaborate than that available in the 1970s and 1980s to the pionneers of ESD studies. Recent studies have covered arc formation, initial spike with the hand/metal scenario, fields radiated in the vicinity of the discharge, and the like. Among the engineers who

xii

Preface to the Third Edition

investigated these facets of ESD, one of the most prolific has certainly been D. Pommerenke of Missouri University. In the first few chapters of this new edition, we give an overview of these recent studies. The problem of poor repeatability has always also plagued ESD testing, as with many EMC tests in general. But, while other tests have gained significant improvements in accuracy and credibility, ESD remains the black sheep of the herd, raising sarcastic jokes among EMC practicioners and lab technicians, who are struggling constantly with these “ESD guns that don’t shoot right” or “ESD tests that make failing products pass and good products fail.” Therefore, a substantial share of the R&D effort has been aimed at reducing the uncertainty attached to ESD generators and test procedures. However, we have some reservations: While a tremendous amount of activity has been deployed toward ESD generator modeling, calibration, and error analysis that is basically “simulating the simulators,” it seems that the EMC community has lost sight of the actual fact we are trying to counteract: the real, everyday electrostatic discharge. To our knowledge, no organized, wide ranging statistical survey of ESD events has been conducted since the last outstanding work done by R. Simonic around 1973–1974. Things have changed: People’s habits are different: interior decoration, furniture, and clothing are different. Instrumentation that could capture and record ESD is now more accurate, with much greater bandwidth than in the early 1970s. As a result there is a danger that we may very well be trying to reproduce perfectly, with today’s advanced simulators, events as they were recorded 35 years ago. St. Remy les Chevreuse, France May 2009

Michel Mardiguian

Acknowledgments

After writing the word end , my gratitude goes to to those who provided their timely assistance and information: Etienne Sicard and Alain Charoy who gave me valuable details on IC protection, David Pommerenke who shed some light on his very specific series of measurements and modeling, Diethard Mohr and William Rhoades for bringing me up to date on some current ESD documents status. My thanks go also to Joel Raimbourg and Sebastien Bazzoli who provided invaluable support for some practical experiments. Last, but not the least, I am grateful to Mark Montrose and Michael King—the latter being a living memory of the pionneering era of ESD—who expressed their encouragement for the making of this third edition. Many thanks also to Jeanne Audino and Steve Welch of the IEEE Press team, for their very professionnal assistance that gave life to my crude manuscript, and again to Mark Montrose who did the technical review, adding some precious remarks. Very special thanks go to the editorial team at Wiley: Lisa Van Horn, Ernestine Franco, and Dean Gonzalez, respectively, senior production editor, copy editor, and illustration manager, who performed a meticulous editing and turned my crude sketches into fine drawings. I also thank my wife Corinne for her patience, not to mention that she has been the one who typed some of the chapters, as it is often the case with we engineers, who pretend to become writers. M. M.

Chapter

1

The Electrostatic Discharge Phenomenon Although a thorough description of the electrostatic phenomenon is beyond the scope of this book and has been covered by several authors (1–4), it might be useful to start by reviewing briefly how static electricity takes place, what are the contributing parameters, and why, eventually, it ends abruptly in its threatening consequence: the electrostatic discharge (ESD). The following section is an extremely simplified view of the electrostatic charging mechanisms. While clearly not a treatise on static electricity, it illustrate the physics involved, in a simple manner. Readers with a good basic knowledge of electrostatics can probably skip this preliminary portion.

1.1. PHYSICS INVOLVED Any material is made of atoms. Unless submitted to certain external influences (heating, rubbing, electrical stress, etc.), the atom is at equilibrum; that is, the amount of negative charges represented by the electrons orbiting around the nucleus is exactly balanced by an equal number of positive charges or protons aggregated in the nucleus. Therefore, the net electric charge seen from the ouside is zero. In good conductors, the mobility of electrons is such that the conditions of equilibrium will always exist; that is, no significant static field will exist between different zones of the same piece of metal. With nonconductive materials, however, the lesser mobility of electrons does not provide such a rapid recombination of charge unbalance. If heated, or rubbed strongly (which also creates heat), a nonconductor will free up electrons. Depending on the nature of its outer valence orbit, a nonconductive material may be likely to give up electrons or to capture wandering electrons. Electrostatic Discharge, Third Edition, by Michel Mardiguian Copyright © 2009 the Institute of Electrical and Electronics Engineers, Inc.

1

2

Chapter 1 The Electrostatic Discharge Phenomenon

− −

−

+ + + + + +

−

−

−

Figure 1.1 If by heating, rubbing, and the like, one electron is leaving the orbit, the material is left with six protons and only five electrons.

A nonconductive material that gives up an electron, as shown in Figure 1.1, will become positively charged. Such unbalanced atoms with a lack of electrons are called positive ions. A nonconductive material that takes extra electrons will become negatively charged, and its atoms with excess electrons are called negative ions. Charges with like sign repel while charges with opposite sign attract. Therefore, it seems that nature will rapidly take care of the unbalance by recombining the charges. Unfortunately, while this recombination is instantaneous in metals (i.e., indeed, how a current flows), the high resistance of nonconductive materials makes it unlikely to happen, until such a high gradient of field is reached that either an arc or a mechanical attraction will occur. Besides rubbing or heating, which is the common generation mechanism, an object can become charged by contact with another previously charged object. This ability of nonconductive materials to acquire electrostatic charges is known as triboelectricity. Once a nonconductive material has been subject to triboelectric charging, the charges trapped on its dielectric surface are not easily removed. Grounding the piece of material will do nothing since, on insulators, charges have no mobility. Only a flow of ionized air, hot steam, or conductive liquid can remove the charge unbalance. Static charging ability is frequently shown on triboelectric scale, such as the one in Table 1.1 Materials labeled “positive” will take on a positive charge every time they are frictionned against a material lower on the scale. Although this kind of scale is true overall, the precise ranking of each material within the scale should not be definitely relied upon in real-life situations. Many authors and practicians in the ESD community, such as A. Testone (3), have shown how deceptive such triboelectric tables can be.

1.1. Physics Involved

3

Table 1.1 Triboelectric Series More (+)

More (−)

Dry air Plexiglass Bakelite Cellulose acetate Silicon wax Glass, mica Nylon Wool Human hair Silk Paper, cotton, wood Amber, resins (natural or synthetic) Styrofoam, polyurethane Polyethylene Rubber Rayon, Dacron, Orlon PVC Silicon Teflon

For example, let us take a reel of ordinary office adhesive tape. If we quickly unwind some length of tape, everyone knows that this segment becomes charged and can attract small particles of dust, hairs etc and the like. But since both sides of the tape are the same material, they rank the same (e.g., positive for acetate) on the table, and this piece of film could not develop an electric field against itself. However, after unwinding this short segment (Fig. 1.2), we notice that it is strongly attracted by the rest of the reel, which indicates that there has been a charge transfer, whereas one side of the tape has acquired electrons that the other side has lost. How can the same material be at the same time a “taker” and a “giver” of electrons, thus contradicting the triboelectric scale? Furthermore, if we cut this piece of tape (using insulating gloves and scissors to prevent our conductive body from influencing the results), and approach it to the reel, some areas of the tape are attracted, while others may be repelled. The mechanisms coming into play in this apparently simple experiment are multiple and complex. For one, the materials involved are not just acetate against acetate; there is the adhesive layer and also the air itself, which is on the top (+) side of the scale. Then, the tape surfaces have changed their radii as they were separated, such as the “run-away” electrons do not face exactly the same region as when the contact was tight. Therefore, even two insulating materials of the same nature can eventually develop opposite charges if sufficient friction, shear, or bending is applied. This happens hundreds times a day in a photocopier when foil is slipped over the paper stack.

4

Chapter 1 The Electrostatic Discharge Phenomenon

−

+

+

+

+

+

−

−

−

−

Figure 1.2 Stripped end of acetate tape is attracted by the surface of the tape reel.

Thus, although triboelectric scale is a fair indication of the polarity of the charge acquired by materials, we must stay away from peremptory statements when facing an electrostatic charging situation. Static field meters are good instruments to get a true measure of the static voltage acquired by various materials. Now consider the classical example of a person walking on a synthetic carpet, rubbing his body on an insulated chair pad, or moving his nylon shirt sleeve over a polyvinyl chloride (PVC) surface: the farther apart the two materials are on the triboelectric scale and the faster the relative motion of the person, the more electrons will be freed by the givers and captured by the takers. This creates a charge unbalance—hence a latent electric field. Figure 1.3 suggests a scale of merit for the propensity of materials to create more or less ESD problems. It is based on the surface resistance in ohms per square (i.e., the resistance of a sample square, whether it is 1 cm2 or 1 m2 , yields the same results). Material with more than 109 /square are likely to develop electrostatic potentials that will not bleed-off by themselves due to the high insulation of

Ω /square 1014

Static generating materials

1012 1010 108 10

Insulators Anti-static, but Non-dissipative Anti-static, dissipative

6

104

Conductors Conductors

Figure 1.3 Propensity of materials to create ESD problems, based on surface resistance in ohms/square.

1.1. Physics Involved

5

the material. Materials with less than 109 /square, even if not real conductors, will not keep the charge unbalance very long because recombination will occur through the material itself. Aguet (5) relates the propensity to electrostatic charge to the dielectric constant of the materials that are rubbed. He indicates the surface charge density σs : σs = 15 × 10−6 (εr1 − εr2 ) Coulomb/m2

(1.1)

where εr1 , εr2 are the relative permittivity of the two materials. For instance, if one looks at a rubber shoe sole (εr1 = 2.5) representing 250 cm2 and a nylon carpet (εr = 5), the maximum total charge Q that can be acquired is Q = 15 × 10−6 (5−2.5)250 × 10−4 m2 = 0.93 × 10−6 Coulomb If the corresponding foot-to-ground capacitance C is about 100 pF, the static voltage is derived from Q = CV

(1.2)

Hence, V =

Q = 9300 V C

It might seem, therefore, that there is practically no upper limit to what voltage a person can attain. Why not 50 kV 100 kV? Richman, in his very illustrative pamphlet on ESD (6), explains that, hopefully, personnel electrostatic voltage cannot exceed 30 kV in the most extreme cases because: 1. The capacitance of the human body, no matter what we do, cannot drop below 30–40 pF, a value that Richman calls our “capacitance to infinity.” 2. Above approximately 25 kV, the corona will start to self-limit our voltage by bleeding off the charge, that is, the assumption of constant charge Q is no longer valid. So, in most practical situations, the upper range of human body static voltage is 20–25 kV. Summarizing this short description of electrostatic charging, we can say that static electrification is a complex phenomenon that one cannot solely characterize by any single parameter, such as the ranking of the material on a triboelectric scale, its surface resistivity, or dielectric constant. To the contrary, static dissipation can be dependably related to resistivity.

6

Chapter 1 The Electrostatic Discharge Phenomenon

1.2. INFLUENCING PARAMETERS Once the type of materials present is known, the most important parameter is relative humidity. It is well known that, during winter and spring seasons, all integrated circuit manufacturers have recorded an increased rate of “infant mortality” in their chips, and field engineers report an increasing number of service calls for computer failures. Several things happen when relative humidity is low: •

•

Normally, the moisture content in the air tends to decrease the surface resistance of floors, carpets, table mats, and the like by letting wet particles create a vaguely conductive (or say, less than 109 /square) film over an otherwise insulating surface. If the relative humidity decreases, this favorable phenomenon disappears. The air itself, being dry becomes a part of the electrostactic buildup mechanism every time there is an airflow (wind, air conditioning, blower) passing over an insulated surface.

Many evaluations have been made of the electrostatic voltages reached by a person walking on several types of floors. Generally, these tests are made using a kind of “standard walking procedure.” The person walks a given number of steps with a given type of shoes; then his (her) charging voltage is immediately measured with an electrostatic voltmeter having a quasi-infinite input impedance. The importance of measuring the voltage immediately after charging, and preferably having this same short time for all experiments, is seen in Figure 1.4. If the time elapsed between the end of the charging phase and the instant of the measurement is not kept constant, comparisons between materials, clothes, shoes, and the like become inaccurate. Figure 1.5 shows the range of acquired electrostatic voltages for several floor types and two values of the relative humidity (RH). On the left side, the voltages are shown for an RH of 50%. Even with a notoriously bad type of carpet such as nylon, the voltage stays within 1–3 kV. Note that this is already enough to kill some integrated circuits if the person touches directly a module or a printed circuit board (PCB). But the scale in the middle merely suggests the likely consequences when the charged person touches a typical electronic cabinet, without direct contact to a module or connector pin. What is shown as “likely consequences” assumes that the stressed equipment is of an ordinary design, not especially hardened against ESD. (Chapter 5 will explain how a system can be made reasonably immune to ESD.) The right side of the chart shows what happens with the same kind of floor coverings when RH goes down to 20%. Nylon jumps to 6–11 kV, and some other synthetic carpets cause people to charge up to 8 kV. The diagram in Figure 1.5 is restricted to the most current types of floors. With some specific materials, things can go even worse. The worst floor ever is probably a silicon waxed wooden floor where human ESD voltages over 20 kV

1.2. Influencing Parameters

7

Time in seconds 10

20

30

40 500

200

200

100

100

50

50

20

20

10 0

10

30

20

Operator potential in volts

Operator potential in volts

500

0

10 40

Time in seconds Legend Shoe sole Composition or leather Leather Composition Leather Composition Composition Conductive

Floor

RH

Vinyl

4%

Conductive (0.27 MΩ) Conductive (0.95 MΩ) Conductive (0.27 MΩ) Conductive (0.27 MΩ) Conductive (0.27 Ω) Conductive

5% 4% 45% 5% 45%

Figure 1.4 Electrostaticgenerated voltages will decay at a rate that is dependent on relative humidity, floor covering, and type of clothing worn by personnel. Decay times can take several minutes to reach safe levels (7).

have been commonly reported. A well-known, and often painful, static environment is that of an automobile interior (Fig. 1.6), since a car is a metallic envelope isolated by its tires and replete with plastic and synthetic textiles. It may seem that a relative humidity of 20% is a rather low. Indeed, as shown in Table 1.2 for relative humidity over the year in major U.S. cities, only a few locations have an RH less than 20%. But in absolute numbers, cities such as Albuquerque, Tucson, and Phoenix are industrial/business areas representing millions of people with hundreds of thousands of electronic devices installed, which must function correctly, even during the winter/spring months. In fact, the problem is more critical than Table 1.2 would have us believe: The recorded RH values are those found outdoors by the weather bureau. A significant difference may exist between the RH outdoors and its actual value in a heated building. This is due to the fact that, given the same quantity of water, warm air has a greater ability to absorb moisture; therefore, its relative humidity (compared to saturation) is lower. Equation (1.3) shows that in a restricted space whose temperature is T2 , the relative humidity is RH2(T2 ) = RH1(T1 )

T2 C(1/T2 −1/T1 ) e T1

(1.3)

8

Chapter 1 The Electrostatic Discharge Phenomenon 20 15

Static voltage in kV

10

× 5

Range for nylon and acrylic

3 2

ol

Wo

c” tati ) ti s ative n “A sip s (Di

×

1 0.6 60

50

30

20

15

10

Relative humidity in % 12

8

10 1

8

6

6 Poor

4

2

4

5 Marginal 1

3 2

2

3 4

4

5

6

Static voltage in kV

Static voltage in kV

10

12 Disastrous Material Code 1. Regular nylon 2. Com’l antistatic nylon Possible 3. Vinyl asbestos tile physical 4. High pressure laminate damage 5. Acrylic and polyester Very 6. Compu-Carpet poor

Safe

0

6

2 0

50% RH

Equipment reliability

20% RH

Figure 1.5 Typical range of static voltages generated by walking on common floor covering materials (adapted from Ref. 8).

where RH1 is the relative humidity of the outer ambient, at temperature T1 , and C a constant equal to 5370 between −20◦ C and +70◦ C; T1 and T2 in the formula are given in kelvins. The equation has been plotted in Figure 1.7 for a few typical situations. For instance, on a winter day where the outside temperature is 0◦ C (273◦ K) and the

1.3. Various Types of Electrostatic Charging with Humans and Objects

9

25

Charge voltage in kv

Polyester seat Nylon clothing

20

Vinyl seat Nylon clothing

15 Polyester seat Polyester clothing

10 Nylon/

5 Viscose

Nylon/ Viscose seat

seat Cotton Polyester clothing clothing

Leather seat Cotton clothing

Leather seat Nylon clothing

Vinyl seat Cotton clothing

Figure 1.6 Electrostatic charging voltages for various car driver/car seat combinations (9).

RH about 40%, the actual RH in a room heated at 22◦ C will be only 9%! Unless the heating, ventilation, or air-conditionning system (if there is one) compensates for this lack of water vapor, which it generally does rather poorly, or a humidifier is installed, the ESD risk is very high. Besides the type of material and the relative humidity, other factors play a role in the severity of the human electrostatic charge: Type of clothing and shoes Speed and manner of walking Sex and size of the person Body capacitance Body resistance The two last factors will be discussed in the next section because they strongly influence the dynamic characteristics of the discharge.

1.3. VARIOUS TYPES OF ELECTROSTATIC CHARGING WITH HUMANS AND OBJECTS Although an infinity of ESD cases have been reported, the ones that are plaguing the electronic industry belong to either the human body discharge or the charged object discharge. (9) So far, we have emphasized the electrostatic charges generated by human beings, as shown in the most common scenarios of Figure 1.8.

10

Chapter 1 The Electrostatic Discharge Phenomenon

Table 1.2

1.3. Various Types of Electrostatic Charging with Humans and Objects For :

11

θ2 = 20°C inside

100

80

θ1 = 30°C θ1 = 40°C

θ1 = 20°C

Inside

Hθ2 (%)

60

θ1 = 10°C

40

20

θ1 = 0°C Outside

0 0

20

40

60

80

100

Hθ1 (%) Hθ2 = Hθ1K·

θ2K 1 _ 1 · e 5400 ( θ1K θ2K) θ1K

Hθ : Relative humidity at temperature θ θ : Temperature in K (formula valid for −20 to + 60°C)

Figure 1.7 Actual vs. apparent relative humidity.

Notice that depending on the nature of the two materials being rubbed together, the person can exhibit positive or negative charging. Although humans tend to treat themselves as very special, physics does not care and treats us as a mere conglomerate of materials, vaguely conductive. There are thousands of occasions where the human body is not the electrostatic generator, but simply the carrier, or even is not involved at all (Fig. 1.9). An example of a human as a carrier occurs when a person gets out from a car after a ride on a bright, cold, and windy winter day. The moment he puts his foot on the ground while his hand is touching the door handle, he often feels a violent ESD zap. The body was not the electrostatic generator in this case, the car was.There have been reports of highway toll gate attendants who could not stand their job because of too many ESD zaps when drivers where handling them the money! Following is a list of some nonhuman ESD sources: • • • •

Wheelchairs, carts, rolling furniture Rubber or textile belts and conveyors and their pulleys/rollers Cooling fans with plastic rotor blades Helicopter rotor blades (generally made of composite material)

12

Chapter 1 The Electrostatic Discharge Phenomenon

+ −

− +

−

−

+

+

−

−

−

−

+

+

+

−

−

−

− +

+

+

+

+

+

+ −

+ −

+ −

Figure 1.8 Some of the classical ways a human can accumulate static charges.

+ + + + + +

− − − − − −

Figure 1.9 ESD with or without a human body involved.

1.4. Statistics of Voltages and Currents Reached During ESD • •

• •

13

Paper movement (printers, copiers) Rapid flow or friction of gas, liquid, or granule against an insulating material or unground conductor such as: • Cleaning with airgun • PVC “skin-packing” with hot air blast • Cleaning with solvent • Fuel lines (including filling-in or draining-off a fuel tank) • Loading or dumping grains in silos • Rocket exhaust nozzle • Radomes, fiberglass hoods, and tips • Thermal blankets (spacecrafts) Device-manipulating robots on manufacturing lines Electrostatic painting process (the spray nozzle being charged around 80–100 kV)

Also, we must remember that a nonconductive object can become charged by contact with another, previously charged, object. This static-contaminated object will, in turn, be a potential hazard for electronics. In all cases, whether a person is involved or not, the charged object will “seek” the first opportunity to recombine the unbalanced charges: This may occur smoothly by a progressive bleed of charges through a moderately conductive path, or may occur abruptly and generally accompanied by an arc. In the case of a “self”-recombination, a small amount of current will flow during a certain time, and the result will be generally harmless. To the contrary, with an abrupt recombination, the discharge will occur during a very short time due to the high-voltage gradients involved, and the corresponding current will be high. Since its average value is I (A) =

Q(Coulomb) t (s)

(1.4)

when a discharge of microcoulombs takes place within tens of nanoseconds, the average current amounts to several amperes, with peak values that can reach up to hundreds of amperes.

1.4. STATISTICS OF VOLTAGES AND CURRENTS REACHED DURING ESD Although the ESD phenomenon has been experienced and fought against for decades by electrical and electronics industries, it is only around the early 1970s that thorough studies were carried on its dynamic parameters. Measurements have been published of voltages and/or currents encountered during real or re-created ESD situations, sampled over a certain period of time or among a certain number of individuals. The statistics that have been gathered, to the knowledge of this author, can be classified as follows:

14

Chapter 1 The Electrostatic Discharge Phenomenon • • • •

Measured voltages of human ESD, depending on the materials involved (garments, type of shoes, type of floor covering) Measured voltages of human ESD, depending of the relative humidity (correlated or not with the time of the year) Measured voltage of objects and furniture ESD, against the type of objects and sometimes the type of environment (humidity and floor covering) Measured currents with furniture ESD, against type of environment and time of the year

Although they are more spectacular and seem to relate the most obviously with the severity of the discharge, the data collected on ESD voltages are not the most meaningful, neither are they the most crucial when trying to develop representative specifications for ESD simulation. The voltages at which the persons were charged during the measurement campaign can be an ambiguous or inaccurate database. Was the voltage measured at its peak, right after a static buildup? Or was it recorded at the moment of an actual discharge? What were the mean value and standard deviation of the voltage decay between its peak value (as generated) and its value at the exact moment of the discharge? Were the people in the study aware that ESD voltages were gathered? Every statistician knows that people in such surveys often tend to “sympathize” with the experimenter, helping him to find what he likes to find (in our case, for instance, by shuffling their shoes more conscienciously on the carpet). Statistics is a discipline requiring specific precautions. In some of the often mentionned experiments, it is not clear that these precautions were taken or were feasible. Doing a parallel between ESD and lightning, one could say that focusing on ESD voltages only is probably as irrelevant as would be concentrating on cloud-to-Earth voltages when studying lightning strikes: all sound statistics on lightning severity are based on lightning currents. Similarly, ESD statistics based on current seem the most dependable and usable. As for any transient, random events, statistical analysis is important for determining what is the risk that a certain value of electrostatic discharge will be reached (or the probability P that this value will be exceeded). Do we want to test the immunity of an electronic device or equipment to something that can happen once a day or once a year? How many failures per week or month do we risk by testing a machine only to a certain ESD level? A rough example of recording the number of electrostatic discharges is shown in Figure 1.10. During a particularly cold and dry spring (early April 1982) in Virginia, the author had taken a limited survey of the number of discharges (as they were felt by people) in a set of offices where about 12 people were using one copier, a telex, a desk-top computer, a postage meter, and a word processor. Discharges were recorded on Tuesdays, Wednesdays, and Thursdays for 3 weeks. These discharges did not necessarily cause equipment malfunction—in fact most of them did not—but the purpose of the survey was to count the

1.4. Statistics of Voltages and Currents Reached During ESD

15

29

18 16 13

Wed.

7

8

10

10 Thur.

Tues.

11

11

6

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Week 1 Week 2 Week 3 Day of the month

Figure 1.10 Number of discharges/day in a medium-size office area with copier, computer, word processor, telex, and mailing machine.

ESD events, not the eventual failures. It must be also noted that discharges of less than 1500–2000 V were generally not felt by a person and, therefore, were not recorded: They represent no risk for normal electronic equipment, but their absence in a sampling could skew the statistical analysis and produce overly pessimistic conclusions. A much more intensive survey was done by Simonic (10, 11). During two surveys spread over several years, he has compiled with an impeccable rigor thousands of measurements of both human and furniture ESD in quasi-real-life conditions. His work represents such an outstanding contribution to the subject that it deserves a detailed analysis, as shown hereafter.

1.4.1. Personnel ESD Statistics The first compilation made by Simonic covered personnel ESD events. The survey was run for 16 months, and its analysis allows one to predict, given a human contact discharge, the probability P of exceeding a peak discharge current I . The highlights of the analysis are the following: • • •

The rooms surveyed had a high human activity (terminal room with 16 operator-attended stations). The rooms had uncontrolled (or poorly controlled) RH and wool carpet. The purpose of the survey was to record the number of discharges, not the number of machine failures, which would have restricted the scope of the study.

16

Chapter 1 The Electrostatic Discharge Phenomenon

Therefore, to be sure that what was measured was the ESD current caused by people (and not furniture ESD), and to provide every person with the same calibrated discharge path, a special monitoring setup was devised: • • •

•

•

IESD was measured by a current probe (current transformer) placed on a specially equipped metal doorknob. Only the interior side of the door handle was equipped, so only personnel ESD from inside the room was recorded. The current probe was connected to a recorder with 9 separate channels, set to specific threshold levels. The probe had a 100-MHz bandwidth, but accounting for the whole instrumentation chain, the final 3-dB bandwidth was 30 MHz. Each channel was recording the number of occurrences its own threshold was exceeded [therefore it can be directly translated in a P (I > 1x) statistic]. The RH was constantly monitored.

The study collected data from 498 eight-hour shifts, with an average of 120 discharges per shift. Thus, about 60,000 ESD events were logged and arranged in 3800 data entries. Using sound statistical practices, a regression analysis weighted to the number of human contacts was performed. Over a more limited period, one type of antistatic carpet was also surveyed. Since some people had finger rings, wrist straps, and the like, it is likely that a certain percentage of human/metal discharge is included in the collected data. The 30-MHz bandwidth seems insufficient to measure ESD pulses with 1-ns rise time (which would need at the very least a 350-MHz bandwidth). But the system was calibrated by a reference ESD pulser delivering a waveform with a 2-ns rise time, 320-ns time constant, and a source impedance of 2000 (behaving like a current source). Thus, the correlation between the 30-MHz limited bandwidth and the actual pulse bandwidth was taken care of by the calibration. The analysis reveals, of course, a strong correlation between the RH and the peak currents reached. A convenient equation for predicting the current I , given a probability P , was derived from the analysis: I ≥ 10A P B (RH)C

(1.5)

with A = 4.12

B = −0.645

within the following range: 0.95 confidence RH% comprised between 15 and 55 Probability P (I ) = 0.001 < P < 1

C = −3.39

1.4. Statistics of Voltages and Currents Reached During ESD

17

Table 1.3 Peak Current (in Amperes) Having a Probability P (I ) of Being Exceeded by Personnel ESD P (I ) RH Percent 15 < 20 < 25 < 30 < 35 < 40 < 45 < 50 <

< 20 < 25 < 30 < 35 < 40 < 45 < 50 < 55

1

0.5

0.1

0.01

0.22 0.14 0.11 0.072 0.059 0.052 0.042

0.80 0.73 0.35 0.20 0.11 0.075 0.055

2.4 1.9 1.1 0.80 0.40 0.17 0.10 0.072

8.7 7.1 3.5 2.2 1.3 0.56 0.25 0.15

For example, what is the current that will be exceeded only 10% of the time, given a RH% of 20, with 95% confidence? I ≥ 104.12 (0.1)−0.645 0.645.(20)−3.39 I ≥ 2.2 A Equation (1.5) has been arranged in a tabular form in Table 1.3, with the results of the survey plotted in Figure 1.11, where personnel ESD event curves give the current I having a probability P (0.01 < P < 1) of being exceeded. Table 1.3 shows the current increasing approximatively like the inverse cube of RH. Given a same probability (P ), currents will be 20–40 times greater at

Current (I ) .03

.1

.3

1

3

30 1

−2 0%

.1

%

−35

30

50% 45−

.03

15

RH

RH

.1

.3

RH

.3 Probability (P)

10

.03

.01

.01

.003

.003

.001 .01

.03

.1

.3

1

3

10

Current (I )

Figure 1.11 Simonic’s personnel event curves.

30

.001

Probability (P)

.01 1

18

Chapter 1 The Electrostatic Discharge Phenomenon

RH = 15% than at RH = 45%. Also a given current I will be exceeded 100 times more often at RH 15% than at RH 45%. Since the RH% has been recorded at intervals of 15–20, 20–25, and so on, the curves shown in Figure 1.11 are mean values of P in these intervals. Given the strong dependency of P (I ) on the relative humidity, even a 5% RH interval corresponds to large variations of P for a given I , around the mean value. For instance, for a 15–20 RH interval, assuming the average RH is 17.5%, a current of 5 A will have a 0.025 (or 2.5%) probability of being exceeded. However, for this interval and a same (P ) the lower bound (RH = 15%) corresponds to 8.4 A, while the upper bound (RH = 20%), gives only 3.2 A. To complicate the issue, the average value of RH in the interval does not correspond to the mean value of P (I ) in that interval. Therefore, the curves of Figure 1.11 are a good indication considering that, in reality, RH has daily fluctuations that often exceed 5%; if a more accurate prediction is needed, Eq. (1.5) should be used. A reconstituted histogram of the personnel ESD events is shown on Figure 1.12. In addition to the current intervals, two voltages are also indicated on its lower scale: • •

The voltage at which a 1-k pulse generator should be charged to replicate the same event. The voltage at which an IEC-type simulator (see Section 3.2) should be charged to create the same currents. This takes into account the fact that above 8 kV, the IEC simulators switch from contact discharge (hand/metal) mode to air discharge.

Of course, this attempt of relating P to a number of events/shift is broadly indicative. While the probability P for a current I is a well-supported figure, the total number of events/shift in a room depends strongly on its size, occupancy, and activity. The rooms in this study could have exhibited from a few tens to several hundred events/shift. A gross estimate would give, for a low RH and carpeted room, an average total of 100 events per shift. Also not shown, but reported in Simonic’s study, is the fact that antistatic carpet (acrylic carpet incorporating conductive fibers) did show a 36 times reduction in ESD currents for the (15–20)% RH interval and 23 times reduction for the (30–35)% interval.

1.4.2. Furniture and Objects ESD Statistics The second of Simonic studies covered furniture ESD events. The survey lasted several years, and addressed ESD voltages in both computer rooms and data processing offices. The statistics are not compiled in percent probability but in number of ESD events per shift. Being a meticulous experimenter, Simonic had to select sites with significant probability of ESD occurrences. With ordinary offices, as was the case

1.4. Statistics of Voltages and Currents Reached During ESD

19

RH = 15–20% 10 8 RH = 45–50%

5.5 .15

.25

(3–5)

(5–8)

(8–15) (15–25) IESD in A

3–5 kv

5–8 kv

8–15 kv 15–25 kv

[4.5–7.5 kV]

[500–1 kV]

[300–500 V]

VESD, based on an IEC–type gun (Ztot ≅ 300 Ω)

[150–300 V]

(1–1.7) (1.7–3) Hypothetical VESD, assuming 1 kΩ body 500–1 kv 1–1.7 kv 1.7–3 kv resistance

[2.5–4.5 kV]

(.5–1)

.8

[1.5–2.5 kV]

(.1–.5)

1.3

[1–1.5 kV]

Number of events/shift/room (based on ≅ 100 events)

(Personnel discharge currents were recorded by a current probe on the doorknob.) 30 20

Figure 1.12 Reconstituted histogram. Events/shift for personnel ESD.

with the personnel ESD survey, site selection was not a problem because a large sample of locations was available. The situation was different with computer rooms: Sites with a significant history of ESD events were sometimes modified prior or during the survey, for instance, by increasing the RH%, or replacing some furniture with antistatic type, to correct a serious ESD problem. As a result, the measured event rate was biased by artificially reduced ESD voltages. Simonic did his best to document such situations when they could not be avoided. The highlights of the analysis are: • •

The sites selected were locations with ESD problems, preferrably where no corrective measures had yet been taken. The two kinds of sites were: • •

•

Computer rooms with raised metal floor and humidity control: 10 sites, 11 machines, totaling 3360 eight-hour shifts Carpeted offices with no humidity control: 8 sites, 8 terminals, 282 shifts

All machines were floor standing units with metal covers.

20

Chapter 1 The Electrostatic Discharge Phenomenon • • •

•

This time, the ESD event detector was a current probe placed around the machines input/output and power cables. The detector was sensing the peak current and was calibrated to correlate with a given discharge at typical contact points on the machine. The detector was optimized for furniture ESD, that is, voltage source (low impedance metal object). Then the readout was converted into an assumed ESD source voltage (see Note 1). The detector 3-dB bandwidth was 100 MHz. As for the personnel study, the recorder had nine channels with preset levels, which counted each occurrence where the treshold was exceeded.

Note 1 The idea behind this detector was that a charged furniture behaves much like a voltage source. By knowing the average value of the discharge path impedance, which includes the total loop resistance, the arc resistance and the loop inductance, the unknown ESD voltage can be derived as VESD = Ipeak × Zloop . The only questionable point would be how dependable is the conversion factor when the actual ESD current waveform did not fit the standard “template.” A calibration setup, simulating the minimum (worst-case) loop impedance of the ESD is shown in Figure 1.13. Its dynamic R,L,C impedance is approximately 45 , therefore:

VESD (unknown) = Ipeak (measured) × 45 √ For such an RLC network with R < 2 L/C, the discharge is an underdamped oscillatory waveform, with a 20–80% rise time Tr approximately equal to the charging time constant, that is, ≈ 10 ns. It is important to stress once more that this calibration assumes the furniture discharge to behave as a voltage source, whose current is only dependent on the load, that is, the above discussed loop impedance. As a consequence, a personnel-type discharge will be also seen by the recorder, with its true current, but the derivation of the actual ESD voltage would be wrong, the human body having a significantly higher internal resistance. In contrast to the former personnel discharge measurements, where the probe on a door handle prevented any other-than-people ESD from being captured, here the furniture ESD survey had no means to segregate between actual furniture

16 Ω 155 pF

180 nH

Figure 1.13 Circuit used for the reference discharge.

1.4. Statistics of Voltages and Currents Reached During ESD

21

events and possible human events. A more thorough examination of the statistic curves will provide us, nevertheless, with a basis for this differentiation. Figure 1.14 shows the event rate (events/machine/shift) in the 10 computer rooms surveyed, with the table on top giving the spread of RH for both the computer and the terminal rooms. The curve labeled mean is the mean of all recorded events (all machines and seasons combined), weighted by the number of shifts monitored at each site. For instance, the likelihood of having a 1-kv furniture discharge (corresponding to approximately 22-A discharge current) on a computer frame is about 0.11 per shift, that is, 50 times a year for 250 working days and 2 shifts/day. This does not seem catastrophic unless the dependability of the system is such that one error per week is intolerable. But one must remember that this is an average figure. It is very likely that the majority of these events will be concentrated in the low RH period, that RH in % Season

Min

Max

V MAX Recorded

Winter & Spring

14

55

5.4 kV

Summer

42

53

1.7 kV

3

10 100

10 wi

nt

m

er ,w or stn, ca we se ig ht loc ed at ion by nu m be ro fs hi

ea

1

1

su

.1

.1

er

m

m

Events per machine/shift

10

.01 Likelihood that recorded data also contain .001 human ESD .3

fts

1

2

3

Events per machine/shift

100

Furniture ESD in kV 1 2

.3

.01

5

.001 10

Furniture ESD in kV (6 A) 2 kV

(20 A) 6 kV

Necessary charging voltage for an IEC-type simulator

(60 A) 20 kV

(200 A) (Corresponding current in the monitoring probe)

Figure 1.14 Computer room furniture ESD events (3360 shifts, 10 sites, 11 machines). Graph combines sites dependency and season dependency.

22

Chapter 1 The Electrostatic Discharge Phenomenon

is, January to March, which may actually translate into one error per day! The threshold between what a computer user feels as being tolerable and what is not is always subtle, and by no means a step function, but a system experiencing one error per day, during several weeks, is generally unacceptable. In Figure 1.14, the 95% confidence interval is shown as an upper bound of worst-case locations (site and season) and a lower bound of least occurrences. Keeping our previous example of a 1-kV furniture ESD, one sees that there is high probability (95%) that more than 0.025 events/shift exceeds that level, but only 5% chances (1–0.95) that it occurs more than 0.5 times/shift. From the statistical regression analysis, an equation was derived, giving (more accurately than the curves) the furniture ESD events exceeding a certain voltage. For low values of P (P ≤ 1 ), the mean event rate/shift is Pfurn = 10A × E(volts)B

(1.6)

with, for computer rooms: A = 6.37,

B = −2.44

for terminal rooms (carpeted floor, no RH control): A = 5.5, Example will be

B = −1.86

In computer room, the average number of event/shift exceeding 1 kV Pfurn = 106.37 × 1000−2.44 = 0.11

Although the study does not specifically give a quantitative correlation between a given event rate and a given RH%, this can almost be deduced from the data. For a 20-A(≈ 1 kV) discharge, there is a 25 : 1 ratio between the highest and lowest event rate extremes. There is a strong chance that the highest voltages (5 kV) were recorded during the lowest RH periods, and the lowest on the highest RH period (although some low readings could occur during dry season as well, if a piece of furniture did not have the time to yield a high static voltage before a contact occurred). Addressing terminal rooms (severe environment), Figure 1.15 is even more revealing. The 8 carpeted offices with workstations show a spread of Emax /Emin = 62 times. In the personnel statistics for carpeted offices, Eq. (1.5) showed that for a given event rate P , the ESD current was varying like (RH)−3.39 for 15 ≤ RH ≤ 55. If we apply this relationship to the carpeted offices for furniture ESD (there is no reason to believe that carpets would not behave the same way), the predicted ratio of Emax /Emin would be 71 times, which is close to what it was in reality. The mean event rate for a 1-kV furniture discharge in these carpeted offices without RH control is about 1 per machine per shift. When attempting to determine what fraction of these readouts could be due to personnel ESD being mixed in the presumed furniture data, we must keep

1.5. Waveforms of Electrostatic Discharges

23

RH in % Season

Min

Max

V MAX Recorded

Winter & Spring

20*

25

5.6 kV

Summer ? *RH can go as low as 5% at times.

53

.09 kV

Furniture ESD in kV .3

100

1

2

3

10 100

wi

nt

m

er ,w or st n, -c we as igh e lo te ca d by tio n nu m be ro fs

10

ea

1 .3

su

m

.1

m

er

1 .3 .1

hif

ts

.03 .01

.001 .1

.03 Likelihood that recorded data also contain human ESD

(2 A)

.3

Events per machine/shift

Events per machine/shift

10

.01

1 2 3 Furniture ESD in kV

(6 A) 2 kV

(Corresponding current in the monitoring probe)

(20 A) 6 kV

5

(60 A) 20 kV

.001 10 (200 A)

Necessary charging voltage for an IEC-type simulator with total discharge impedance ≅ 300 Ω

Figure 1.15 Terminal room furniture ESD events (282 shifts, 8 sites, 8 machines). Graph combines sites dependency and season dependency.

in mind that the highest voltage a person can realistically build up and keep more than a few seconds is about 20 kV. With a typical human body resistance during an ESD being 1 k, the highest likelihood of personnel ESD data being inadvertantly mixed in furniture data woud be Ip = 20 A, which would appear as 800 V on the event rate curves in Figures 1.14 and 1.15 and Fig. 1.16 histogram. This has been shown as a shaded area on the left in both figures.

1.5. WAVEFORMS OF ELECTROSTATIC DISCHARGES 1.5.1. Personal ESD Waveforms In trying to match the measured waveforms with the physical explanations of Sections 1.2 and 1.3, simple waveforms for the ESD current have been devised

24

Chapter 1 The Electrostatic Discharge Phenomenon

Events/machine/shift

35

RH = 45−50%

17

RH = 15−20%

5 1.7

.2

.035

5–8

8–15

15–25

1.5–2.5 kV 2.5–4.5 kV

25–40

.6

.15

40–70

70–120

7.5–12 kV 12–21 kV 21–36 kV

IESD in A Vtest based on IEC-type gun (Ztot ≅ 300 Ω)

Figure 1.16 Reconstituted histogram, events/machine/shift for furniture ESD.

with the following parameters: I = peak value of the current tr = rise time of the current, measured between the10 and 90% points (approximate fit to the rise time of the triangle envelope) τ = pulse width at 50% amplitude = 0.7RC If we concentrate on the human body discharge, the main electrical parameters that play a role in the rise and fall of the current are: L = self-inductance of the loop formed by the body, its arm, the machine, and the ground return. The range of values is 0.3 to 1.5 μH, with 0.7 μ H typical Rd = resistance of the discharge loop, dominated by body resistance, practically ranging from 1 to 30 k (Fig. 1.17) C = capacitance of human body to ground, with the following range of values: min = 50 pF max = 300 pF typ. = 150 pF The pulse rise time would be infinitely small if the capacitor simply discharged in a resistive network. In reality, this rise time is dictated by the charging time constant L/Rd . The pulse width of the discharge depends on the RC time constant of the circuit.

1.5. Waveforms of Electrostatic Discharges

100

1

Human body resistance in kΩ 3 10

25

20 100

30

Body voltage ≈ 1kV

10

3

30

10

1

3 10 Human body resistance in kΩ

Cumulative distribution in %

Cumulative distribution in %

Body voltage 20v

3 20

Figure 1.17 Distribution of human body resistances.

Table 1.4 gives a recap of the approximative range of rise times (tr ) and pulse widths (τ), given all combinations of the extremes values for R, L, and C. They correlate rather well with actual measured waveforms. One could be tempted to combine some average values and come up with a “standard” waveform. However, this is quite risky—an average figure for a normal distribution represents the value that is met in 50% of the cases, hence exceeded in 50% of the cases. A specification designed upon this criteria would “underprotect” the equipment. It is safer to consider a reasonable maximum, such as the upper decile, for instance (the value that is exceeded in 10% of the cases only). To come up with a reasonably severe waveform, let us look at the table showing the influence of R, L, and C and select the combination that provides the worst influence of each: For the human model Rd is generally larger than L/dt, the inductive impedance of the loop; when L decreases, the charging time constant decreases, when Rd decreases, the peak current increases, for a given static voltage, but this also slows down the rise time by varying the charging time constant. Byrne (12) has performed a thorough analytical study of human ESD by assimilating the body to a set of cylindrical shapes with their respective capacitances and inductances. He ends up with some low-end extremes of 30 ps

26

Chapter 1 The Electrostatic Discharge Phenomenon

Table 1.4 Possible Combinations of R, L, C Variables for Personal ESD and Their Influence on Pulse Rise Time and Fall Time L RD Current rise τr ∼ = 1.4 L/Ra C RD Decay time constant τC = RC

Min Min 420 psc Min Min 50 ns

Min Max 13 psb Min Max 1.5 μs

Max Min 2.1 ns Max Min 300 ns

Max Max 63 ps Max Max 10 μs

Typ Typ 280 ps Typ Typ 750 ns

Typc Min 980 ps Typ Min 150 ns

a

The 20–80% rise time is approximately equal to 1.4 times the charging time constant L/R. The 50% pulse width would be ∼ = 0.69τC . b The interest of this figure is purely academic. It would correspond to a peak current of a few hundred milliampere. However, dI /dt would still be there. c The spread of human body inductances is not very large; therefore, a standard waveform based on a typical value of L is justified. In contrast, the spread of human body resistances is huge, and a standard waveform for a “reasonable worst case” should aim to the lower bound of human body RD .

for the rise time. Such short rise times were not found in actual measurements. This does not mean they cannot exist; displaying a 30-ps rise without distortion requires an analog bandwidth of 12 GHz, which was not within the possibilities of memory oscilloscopes at the time. In any case, such a discharge would be associated with large values of Rd corresponding to smaller peak current: Therefore, the dI /dt derivative, which is, what counts for the magnetic coupling of the pulse to the victim, is fairly constant. As an attempt to allocate R,L,C elements to the human body, Figure 1.18, top, displays what resembles their physiological location, although it is not strictly workable as an equivalent model for simulation software tools. Different models have been devised that produce close-to-real ESD waveforms. Of the many equivalent circuits that have been tried, one is described on the lower schematic of Figure 1.18. It generates in a 1- shunt a current pulse very similar to the standard IEC hand/metal test. The hand/metal sharp current spike and the longer human body pulse can be seen separately by the two dedicated 1- shunts, acting as current mirrors. To see the whole pulse at once, the user needs to run a plot adding the voltages across R01 and R02 . Figure 1.19 shows a simplified waveform corresponding to a “standard” severe case, with a sharp 1-ns rise time and a long exponential decay. A simplified frequency spectrum of this pulse is also shown based on a triangular waveform; being a single event, the pulse repetition period is infinite, and the corresponding spectrum has no discrete spectral lines: It is a Fourier integral, with spectral density given in amperes per megahertz of bandwidth. The spectrum starts (at a frequency equal to 1/infinity) with an amplitude of 2Ipeak τ (for I in amperes and τ in microseconds). The A/MHz envelope is flat up to the first corner frequency F1 = 1/πτ, then decrease like 1/F , or −20 dB per decade slope, up to the second corner frequency F2 = 1/πtr reciprocal of the rise time and often referred to as the “occupied bandwidth.” From then on, the amplitude rolls off like 1/F 2 , or −40 dB per decade.

1.5. Waveforms of Electrostatic Discharges

27

short ground path or long ground path

Forearm, hand and finger C1

R1

L1

150–200 Ω 120–180 nH

6.5 pF C2

R2

V02 ≡ i02

L2

320 Ω

145 pF

1Ω

V0

R01 1Ω

V01 ≡ i01

R02

Figure 1.18 More complete lumped-element model of personnel ESD.

Spectral density

−20

2At A/MHz

ec

/d ad

tc tr = 1 ns time tc = RC = 150 ns t(50%)= 0.69 RC = 100 ns

e

Current (I)

R

ade dB

t (50%)

e−t/RC

dec

0

I=

V

dB/

−4

10 A

A

3

350

Frequency in MHz 2At = 2 × 10 × 10−7 A/Hz ≡ 2 A/MHz = 126 dBmA/MHz

Figure 1.19 Simplified current waveform and spectrum occupancy, for a 10-kV personnel ESD (1-k human body resistance assumed).

28

Chapter 1 The Electrostatic Discharge Phenomenon

1.5.2. Furniture ESD Waveforms If we look now at the furniture or large-object discharge, the parameters are significantly different, as seen below: L = self-inductance of the loop formed by the furniture (e.g., a cart), the victim (equipment, device etc.) and the ground return. The range of values is min : 0.03 μH

max : 1 μH

typ : 0.3 μH

Rd = resistance of the discharge loop. This can be extremely low, a few ohms, for instance. C = capacitance of the furniture or object to ground; can vary widely, from 30 to 500 pF. Here the inductive part of the loop cannot be neglected versus Rd . Compared to the human body discharge, the charging time constant has increased. On the other hand, the peak current will reach much higher values. Worst is that, instead of a slow falling slope, we now have a damped sine wave, typical of an underdamped, “ringing” RLC circuit. Chapter 2 will explain the impact of this ringing on the severity of the radiation coupling into nearby electronics. Figure 1.20 shows the waveform of a severe furniture discharge. Note that the ESD voltage at which the furniture was charged is significantly less than for the human discharge. This seems to contradict the fact that furniture discharge often appears more severe. However, consider this: The furniture has a capacitance to the surounding (i.e., the ground and the victim equipment) that is typically larger than for the human body case. This is due to the larger dimension of the conductive areas facing each other. A cart or metallic chair may have two to five times more capacitance than a person. Given that the quantity of electricity involved is about the same as for human—in fact in many cases, the furniture has been charged from a human source, by charge transfer—the equation Q = CV implies that for a given energy storage Q, if C increases, the corresponding voltage has to be less. Figure 1.20 also displays a corresponding frequency spectrum, with the rise in spectral amplitude around the ringing frequency. Several well-documented measurements, such as those of King (16) support this model of a low-impedance ringing circuit. Together with Simonic’s study (see Section 1.4) they tend to prove that the classical triangular pulse of human ESD is not enough to cover the variety of possible ESD events, and a furniture-type test with a discharge network having less than 50 impedance would be a necessary supplement. To facilitate extrapolation, Figure 1.21 shows a typical furniture ESD waveform normalized to a 1-kV charging voltage.

1.5. Waveforms of Electrostatic Discharges

2.9 A/MHz

A0

e cad

Current (I) in A

/de

A2 = 10 A

(120 dB μ A/MHz)

dB

A/MHz

A1

40

−40

1 A/MHz

20

12.5 ns Time

50 ns

Frequency in MHz

Initial electrostatic voltage = 2000 Volts L = 0.3 μH

RD < 2 L/C, Underdamped oscillation

RD = 15 Ω

damping =

C = 200 pF

A0 = A1 =

n A1/A2 2π

= R/2 C/L = .195

V

A1/A2 = n−1 (π R C/L)

L/C − R2/4 V

L/C + 1.6 R (L/C)½

Figure 1.20 Furniture ESD current waveform and frequency spectrum.

15 Ω

Solution for underdamped oscillation, i.e., R<2 L/C (imaginary roots)

1 kV

ω0 = 1.28 × 108 rad/s

0.3 μH

f0 ≅ 20 MHz (pseudo-frequency of oscillation)

I2 ≅ 0.3I1

30

0

10

20

Time in ns 30 40

200 pF 50

60

70 30

Current (I) In A

I1 20

20 I2

10 0

10 0

0

10

20

30

40

50

60

Current (I) In A

Ipeak =

V L/C + 1.6 R (L/C)½

70

Time in ns

Figure 1.21 Furniture ESD current waveform, normalized to 1-kV initial charge.

29

30

Chapter 1 The Electrostatic Discharge Phenomenon

VESD

1 Personnel R = 1000 Ω

2 Furniture R = 15 Ω L = 0.3 μH, C = 200 pF

3 Personnel (IEC) with hand / metal contact

10,000 V

2,000 V

8,000 V

ΔI/Δt

10 A/ns

Duration of steepest current change

≅ 3.5 ns

≅ 5 A/ns

30 A/ns (initial peak)

≅ 10 ns (during the negative going of the 1st pulse)

1 ns

40 2

Current (A)

3 30

20 1

10

10

20

30

50

100

time (ns)

Figure 1.22 Comparison of dynamic parameters of typical personnel and furniture ESD.

1.5.3. Summary: Comparison of Dynamic Parameters for Personnel and Furniture ESD In order to compare the dynamic characteristics of personnel versus furniture discharge, two typical waveforms, representing a severe (but not overly severe) case, have been overlaid in Figure 1.22. An interesting result is that, given two ESD events having similar probabilities of occurring in a busy work space with uncontrolled RH, the personnel discharge is the one that seems to have the highest dI/dt, and therefore likely to create the worst-case couplings. However, the duration of the steep change, that is, the time during which the derivative exists is 20 larger for the furniture discharge than for personnel. The important consequences of this will be discussed in Chapter 2.

1.5. Waveforms of Electrostatic Discharges

31

1.5.4. Actual versus Idealized ESD Waveforms No two electrostatic discharges look alike. Pretending that the personnel or furniture ESD waveforms seen before are close to what actually happens would be presumptuous. The idealized waveforms such as those in Figures 1.21 and 1.22 have been devised as a repeatable test criterion, such as equipment that resists such standard ESD waveforms is likely to resist real ESD waveforms of similar amplitudes in the field. As early as the end of the nineteenth century, engineers tried to figure out what sort of electrical circuit could be equivalent to a charged human body. The prime concern at the time was the spontaneous explosions in coal mines and ammunition or gunpowder storage. They came up with the resistor/capacitor set very similar to the basic human body model (HBM) in use today. It was only around the 1960s that accurate ESD current measurements began to be performed. (Fig. 1.23, 1.24) Mazdy (13), one of the first to measure ESD waveshapes, has selected a group of fearless volunteers who charged themselves to a high-voltage power supply, then discharged on a grounded 1- shunt. The waveform was recorded, then a calculation was made to retrieve what RC network would best fit with actual data. Figure 1.24 shows a summary of the results. No inductance was put into the model because the study was mainly aimed at determining the destructive effect of ESD when handling modules, that is, the pulse duration was the concern, not the rise time. However, at a time where no standard existed for ESD immunity of integrated circuits, Mazdy’s data and the simulator he built using them, has been widely used by IBM for the quality control of its modules. As early as 1968 Tucker (14) recorded current waveforms from body discharges. His data show differences between ESD from the fingertip, ESD from the side of hand, and ESD enhanced by a sharp handheld tool (the most severe; see Fig. 1.23). Later, King (15) began a thorough study of ESD waveshapes (Figs. 1.26, 1.27) involving mainly personnel, except in one case where an oscilloscope cart pushed against the discharge set was used. The bulk of King’s data for personnel is shown in Figure 1.25. One sees that with the classical personnel discharge, with the finger approaching not too fast, such as ionization occurs, the measured waveforms are fairly close to the idealized waveshapes of Figure 1.20. In contrast, when the field is locally enhanced by a sharp tool, the raising edge shows some odd shapes, with a “precursor” current spike having only a few hundred picoseconds of rise time. This is somewhat reminiscent of lightning where a precursor is often followed by one or several restrikes. This sharp precursor mostly appear with fast speed of approach and the so-called hand/metal ESD. It does not happen with the hand alone, which generates less peak current. King and other ESD pioneers attribute this precursor to a localized generator where the hand (and the handheld tool) distributed capacitance to the target object is discharged first, and so fast that this segment of the body is likely disconnected from the rest.∗ This mechanism could be described as follows: When the charged ∗ This

also occurs with wristbands, rings, coins, keys, and the like.

32

Chapter 1 The Electrostatic Discharge Phenomenon

Time in ns 20

40

60

80

100 Experimental calculated

Vo = 40 kV

60

60 Current I in A

120 80

Vo = 30 kV 40

40 Vo = 20 kV

Current I in A

80

0

20

20 Vo = 10 kV 0

0

20

40

60

80

100

0 120

200

250

300

Time in ns (a)

0

50

100

Time in ns 150

Vo = 40 kV

15

15

10

10

Vo = 20 kV

5

Current I in A

Current I in A

Vo = 30 kV

5

Vo = 10 kV 0

0

50

100

150

200

250

0 300

Time in ns (b)

Figure 1.23 (a) Personnel ESD waveforms recorded with an artificially charged person discharging via a handheld metal tool (14). (b) Personnel ESD waveforms recorded with an artificially charged person discharging by his fingertip (14).

1.5. Waveforms of Electrostatic Discharges

33

T = 5t

Discharge Rp Charge

Cp

Equivalent circuit of human body RC experiment—nonconductive shoes/surface Cp/Rp experimental results Person #

Cp (pF)

1 2 3 4 5 6 Average

140 145 140 170 180 80 142.5

t (ms)

Rp (kΩ)

.30 .30 .30 .40 .35 .15 .30

2.1 2.0 2.1 2.3 1.9 2.4 2.1

Figure 1.24 Experiment validating an equivalent circuit of the human body (13).

tool edge comes close enough to the target surface, the strong local E field is causing the local air gap breakdown. The corresponding current circulates in the small loop formed by the finger, target, and forearm. Then the current decreases for a few hundred picoseconds, with eventually a deionization of the path, until the rest of the charges left behind reach the finger area and are responsible for the main discharge, with the current returning by the entire human–machine–ground loop. After King, several authors (17–19) have closely studied this predischarge and the way to simulate it. They found that the dI /dt during the predischarge can be as high as 30 A/ns if a finger is approached fast enough, and the phenomenon can be adequately modeled with an additional R,L,C element replicating the human hand (Fig. 1.28). The investigations of Ryser and Daout (18) and Frei and co-workers (20) also reveal that, for personal ESD, the dI /dt of the rising edge is strongly dependent on the speed of approach; these measurements were made by using an artificial finger with a motor-driven movement, such that the speed could be recorded accurately. More recent studies, so far, are generally in

34

Chapter 1 The Electrostatic Discharge Phenomenon

(a)

(b)

(c)

Time base: 20 ns/div Vertical: 5 V/div @ 1 Ω load

Time base: 5 ns/div Vertical: 2 V/div @ 1 Ω load

Same as (b)

Measurement conditions: The above data were taken under the conditions of • Initiating level: 5000 V • Human subject holding metallic intervening object (screwdriver) as the ESD path • Motion: Discharge load slowly approached to allow maximum ionization to occur. Vvolts

Extremes of IESD range (Amp)

IESD aver.

Zaver. = V/Iaver.

500

0.9 to 1.8

1.3

385 Ω

1000

1 to 3.6

2.3

435 Ω

2000

4 to 5.8

3.5

570 Ω

4000

1.8 to 7.6

4.25

940 Ω

6000

1.2 to 26

10

600 Ω

8000

1.8 to 8

6

1250 Ω

5.2

1920 Ω

10,000

4 to 6.5

Figure 1.25 A few of the personnel ESD waveforms recorded by King (15) using artificially charged volunteers and enhanced discharges with screwdrivers. Pictures (b) and (c) with expanded scale show large variations of rise times—1–15 ns— between different persons and attitudes. Currents/voltages compilation reveal an increase of dynamic impedance with voltage. This nonlinearity can be explained (to some extent) by the increasing arc impedance.

accordance with these former findings. However, increasing attention has been paid to this predischarge spike because it is extremely aggressive for modern high-speed digital circuits and complicates the making and repeatability of ESD tests (see Chapters 2 and 4). At low levels, say up to 6 kV, the localized charge distribution between hand/finger and the target creates the precursor current spike (Fig. 1.29). At higher levels, the increased arc path length and inductance (a 1.5-cm arc has about 15 nH of inductance, presenting 15 to a nanosecond current rise) slow down the rise front and permit a more complete transfer of the whole body charges, without the sharp spˆıke seen at lower levels. The transition between

1.5. Waveforms of Electrostatic Discharges

35

Discharge points Grounded plane Target To mem. Discharge point scope

0.60 m

Double shielded coax

0.90m Mobile furniture for cart-type ESD

ESD

9 × 1.8 Ω carbon res.

50 Ω

50 Ω

0.2 Ω

To scope 50 Ω input

BNC connector Discharge plate

Grounded plane

Equivalent circuit

Coaxial ESD “Target”

Figure 1.26 Test setup used by King (16) for furniture discharge study. For the chair and the cart, the person was initially charged through a dc power supply. In desk chair, ESD from chair base

Discharge from chair base

Vertical: 10 A/div Time: 10 ns/div

Vertical: 20 A/div Time: 20 ns/div

Vertical: 20 A/div Time: 10 ns/div

Displayed: Ip: 45 A Spike 25 A Surge

Displayed: Ip: 64 A

Displayed: Ip: 79 A

Cart (5000 Volts)

Note 30 A early component

Figure 1.27 A few of the 50 furniture ESD signatures recorded by King (16). Large variations are attributed to small changes in speed of motion toward the target. The predischarge phenomenon is visible, as in personnel ESD, but disappears above 2.5 kV, instead of 6–8 kV for personnel.

36

Chapter 1 The Electrostatic Discharge Phenomenon VESD in kV dl/dt 30

5

10

15 30 25

20

20

15

15

10

10

Current rise in A/ns

Current rise in A/ns

max 25

min 5

5

5

10

15

VESD in kV

Figure 1.28 Range of dI /dt reported by Ryser (18), depending on the speed of approach of discharge probe. In top right corner, see the ambiguity in dI /dt caused by the precursor and other odd wave shapes.

low- and high-level behavior occurs around 6–8 kV [a phenomenon also shown in the earlier measurements by Tucker (14)]. An additional explanation for this is that around 6–8 kV, the physics of arc discharge, that is, the transition from simple gap breakover to corona effect, introduce some nonlinearity between VESD and Ipeak . For instance, if a real 5-kV initiation generates a 10-A peak current, a 15-kV level does not necessarily create a 30-A current. Nevertheless, although personnel ESD waveforms seem to vary widely, in a random, unpredictable manner defeating any serious simulation, they appear as essentially governed by three basic variables: electrode geometry, electrostatic voltage, and speed of approach of the charged finger or electrode. Once these varaibles are set, the spread of discharge waveforms is greatly reduced. Pommerenke (21) developed a mathematical model that replicates closely this hand/metal discharge. In a follow-up of these experiments, King (16) adressed furniture discharge. The main findings are shown in Figure 1.26–1.27. The √ decaying oscillations typical of an underdamped R,L,C circuit with R < 2 L/C are clearly seen. The peak currents are impressive as well. King’s experiments were conducted with many precautions concerning the high-frequency response of his setup. A copper ground plane was used to avoid uncontrolled parasitic inductance in the return path. The shunt used to read the current was a coaxial mount and the instrument 3-dB bandwidth was larger than 500 MHz.

References

37

1 L1

2

C1 i2

Fast approach + hand holding metal

Typical 1st slope: 10–30 A/ns with 5 kV

1

2

+

2

Human body only, slow approach

Figure 1.29 Proposed explanation for the precursor discharge. C1 and L1 being very small, the rise time and duration of the current are very short.

REFERENCES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.

Jowett, C. E. Electrostatics in the Electronics Environment. McMillan, New York, 1976. Horvath, A., and Berta, I. Static Elimination. Wiley New York, 1982. Testone, A. Static Electricity in Electronic Industry. Testone Enterprise, Lee, MA. 1981. Jonassen, N. Static Electricity. Applied Physics Laboratory, Technical University of Denmark, 1991. Aguet, M. D´echarges d’origine electrostatique. Bulletin SEV/VSE 74, Switzerland, 1983. Richman, P. ESD Protection Handbook . Keytek Instrument Corp., 1983. Kirk, W. Eliminate Static Discharges. Electronic Design, March, 1976. p. 80–85. Yenni, D. Huntsman, J. and Mueller, G. 3M Static Products Documentation, 1995. ISO-TC 22, 1989. Simonic, R. Personnel ESD Statistics. IEEE/EMC Symposium, Boulder, CO, 1981. Simonic, R. Furniturel ESD Events Rates. IEEE/EMC Symposium, Santa Clara, CA, 1982. p. 191– 197. Byrne, W. An ESD Model for Electronic Systems. IEEE/EMC Symposium, Santa Clara CA. 1982, p. 199– 205.

38

Chapter 1 The Electrostatic Discharge Phenomenon

13. Mazdy, T. Static Discharge Modelling. EMC Symposium, Montreux, Switzerland, 1975, p. 134– 139. 14. Tucker, T. Spark Initiation Requirements. Annals of New York Academy of Sciences, Vol. 152, Oct. 1968. 15. King, M. Dynamic Waveforms of Personnal ESD. EOS/ESD Symposium, Denver, 1979, p. 78–87. 16. King, M. Pulse Waveforms of Personnel/Furniture ESD. IEEE/EMC Symposium, Santa Clara, CA, 1982, p. 212– 219. 17. Hyatt, H. and Mellberg, H. Bringing ESD Testing into the 20th Century. IEEE/EMC Symposium, Santa Clara, CA, 1982, p. 220–225. 18. Ryser, H. and Daout, B. Fast Discharge Mode in ESD. EMC Symposium, Zurich, 1985, p. 41–46. 19. Richman, P., and Tasker, A. ESD Testing: Interface between Simulator and EUT.” EMC Symposium, Zurich, 1985, p. 25–30. 20. Frei, S., Senhgaas, M., and Jobava, R. Influence of Speed of Approach and Humidity on Intensity of ESD. EMC Symposium, Zurich, 1999. 21. Pommerenke, D. and Aidam, M. ESD Waveform Calculation of Human & Simulated ESD. Journal of Electrostatics, Vol. 38, Nov. 1996, p. 33–51.

Chapter

2

Effects of ESD on Electronics B

efore addressing the various ESD simulators and test methods, we found it necessary to cover the essential coupling mechanisms by which an ESD actually disturbs or damages electronic circuits. The reason being that, a sound test should not only reproduce the discharge itself but also excite, in a realistic manner, the complex interactions between the charged person (or object) and the test item. Not accounting for the multitude of ESD incidents in the modern environment, and focusing on the impact of ESD on electronic devices, the phenomenon can be broken down into three essential scenarios: • • •

Direct discharge to an electronic component (integrated or discrete) Direct discharge to an electronic equipment housing Indirect discharge

2.1. DIRECT DISCHARGE TO AN ELECTRONIC COMPONENT Direct electrostatic discharge to an electronic device is one of the most severe threats to component reliability during the manufacturing and handling of electronic parts. It costs millions of dollars in losses of dead chips and severe breeches in the percent yield of integrated circuit (IC) manufacturing lines, not to mention the latent wounds that will later show up as unexplained failures in the field. This problem was recognized in the late 1960s, and all the large manufacturers of electronic components have since implemented strict static control programs consisting of: • •

Static awareness for employees Static-free work areas and manufacturing hardware

Electrostatic Discharge, Third Edition, by Michel Mardiguian Copyright © 2009 the Institute of Electrical and Electronics Engineers, Inc.

39

40

Chapter 2 Effects of ESD on Electronics • •

Monitoring of percent yields and chip infant mortality to detect ESD symptoms Antistatic precautions for card handling in the field

The scope of this book is not to address thoroughly component failure but rather the malfunctions of a complete device. The reader who is also interested in the component damage aspect of ESD in manufacturing is referred to the abundant literature on the subject (1–4). We will simply consider a brief reminder of this aspect of ESD by showing a few typical episodes. In Figure 2.1(a), the module on a workbench is “zapped” by a person who touches it. Note that: •

•

The culprit may not even notice the ESD event if he (she) was charged at less than 1.5–2 kV (threshold of feeling); therefore no warning exists of a possible damage. The sad thing is that if the workbench was conductive and grounded (an intuitively good antistatic practice) this would only make things worse, by decreasing the impedance of the ground path.

The moral is that antistatic precautions should be applied across the board. Nobody should handle modules without using a grounded wrist-strap or, at the very least, touching a grounded structure first; workbenches should be conductive but “softly” grounded by a few hundred kilohm resistor. Plastic-encased modules are prime victims of this type of event since the field gradient creates arcing or charge transfer from the case surface to the chip itself then sinks to ground via the leads. Metal-encapsulated modules have better chances of surviving if the arc flows on a metal can and breaks over the can-to-benchtop air gap. Figure 2.1(b) shows the opposite situation where the module is standing leads-up, often referred to as the “dead bug” case. Here metallic-canned modules may be as badly damaged. Figure 2.1(c) shows a more insidious scenario: The module has become charged by sliding in carousel rails or by being put in ordinary plastic bags, crates, skin packing and the like. The device can remain charged a significant amount of the time, until it finds an occasion to get rid of its charge, hence experiencing a self-inflicted wound. A variation of this, known as the charged device model (CDM) has been analyzed in several studies (5). There is no such massive statistical data base for this charged device pulse as there is for the human body model (HBM) or furniture event. In fact, the shorted IC internal impedance is extremely dependent on the nature of the current path. Given that the through resistance of the device, as well as the resistance of the discharge path, can be very low on some pins, one can expect a significant peak current, while other IN/OUT pin arrangements in the same module could present a high resistance. Furthermore the package (leaded, unleaded, ball-grid, socketed, or not) is also playing a significant role. As a result, with a real charged device, no definite discharge waveform can be taken for granted. Instead, a corresponding, equivalent CDM circuit test setup

2.1. Direct Discharge to an Electronic Component

41

(a) Charged person zapping a module placed on a conductive workbench: discharge from finger → IC case → chip → pins

(b) Charged person zapping a module placed on a conductive workbench: discharge from finger → pin → chip → IC case.

(c) Charged modules (from nonconductive plastic bags, rails, crates etc…) discharging on grounded personnel.

2 A/division

(d) Charged IC discharging on itself (charged device model)

1 ns/division

Figure 2.1 Integrated circuit ESD damage during handling.

has been defined, briefly described in Chapter 3. Notice that, thanks to the low value of the devices self-capacitance (typically less than 20 pF), the discharge pulse duration is only a few nanoseconds. A third possibility exists in the manipulation of ICs with robots, automatic handlers, and the like. Similar to the furniture discharge (see Chapter 1), this

42

Chapter 2 Effects of ESD on Electronics

scenario assumes that the IC will be handled by a massive device, some elements of which, like three-dimensional (3D) rotating arms, jaws, conveyor belts, and the like are poorly grounded or nonmetallic. This ESD threat, for ICs, is known as the (charged) machine model, or MM (6–8). The solution against these potential ESD damages is to always ship ESD-sensitive devices in static dissipative bags, preferably the shielded type, and to have their pins shorted-out in a conductive foam pad. Remember also that all the above scenarios repeat themselves throughout the life of a device: • • • • •

During wafer processing, test, and cutting During chip transport, test, substrate mounting, and encapsulation During module handling, test, and storage At the next step, that is, PCB level; contrary to a common myth, an IC mounted on a PCB is still vulnerable In the host machine itself, during maintenance

Figures 2.2 and 2.3 show a typical static-free workstation and examples of static dissipative hardware used at the factory or repair shop. What ESD levels does it take to damage a component that is at rest, unpowered? The answer, of course, depends on: • •

The type of technology The dimensional rules: SiO2 thickness, traces width and thickness, traces and pad spacing

Ionized Air Blower

1-MΩ Resistor Table Mat

Wrist Strap Building Ground 1-MΩ Resistor Heel Strap Floor Mat

Figure 2.2 Example of a static-free workstation.

2.1. Direct Discharge to an Electronic Component

(a)

1. Conductive and humidity independent metallic (Ni) outer layer that is: • Continuous • 100 A° thick Transparent (40% or more light transmission) • Resistant to UV exposure • High abrasion resistance

2. A polyester film of nominal 1 mil thickness • High tensile strength • High tear resistance • High puncture resistance • High dielectric strength

3. A polythylene film of nominal 1.5 mil thickness • Anti-static formulation • Heat sealable

(b) static shielding bag and its construction (Courtesy of 3M Static Control)

(c) Conductive tote boxes with ≤104 Ω/sq. resistance (Courtesy of WEZ Plastic Industries)

Figure 2.3 Static protection at the factory.

43

44

Chapter 2 Effects of ESD on Electronics •

The type of built-in protection provided by the manufacturer (assuming the protection resistances and clamping diodes are themselves ESD resistant, which is not always true)

Electrostatic discharge failures occur generally by upsetting the breakdown voltage of the SiO2 isolation or overheating of the metallization. For instance, in metal–oxide semiconductor (MOS) structures with typical oxide thicknesses ˚ (10−7 m), the rigidity of 5–7 MV/cm is exceeded if a voltage of of 1000 A 50–70 V is reached between two isolated channels. Failure by joule effect occurs where a junction or a metallized trace deteriorates and blows up like a fuse: When the current density exceeds 2 kA/mm2 , aluminum particles start migrating, reducing the available section in the conductor, which ultimately will melt, above 30 kA/mm2 for a typical ESD duration, or delaminate. Copper metallization can handle about 2.5 times more current. Integrated active or passive elements can also be damaged: 300- polysilicon resistors for complementary MOS (CMOS) input protection or surge clamping diodes for transistor-transistor logic (TTL) and bipolar are generally damaged above 2.5–3 kV with the HBM test. Damages can also be parametric, mainly with bipolar logic and op-amp, causing fan-out alteration, gain loss, and an increase in noise factor. Latch-up is a different failure mode, affecting powered CMOS circuits when overstressed. In either case of damage the criteria is often the available pulse energy. For current MOS technology, for instance, the threshold of damaging energy is on the order of 1–10 μJ. A straightforward calculation, based on the available energy in a capacitor, will give the damaging voltage range, for a human body discharge. Since W (joule) = 0.5CV 2 where solving for W = 1 − 10 μJ and C = 100 pF (average human body capacitance) we get, for 1 μJ, Vmax = 140 V and for 10 μJ, Vmax = 450 V Also, since energy = power × time, and given that the 50% pulse duration of human ESD is about 150 ns,we can derive, based on 1 μJ, a not-to-exceed pulse power of P =

10−6 = 6.6 W 150 × 10−9

Another approach is to calculate the not-to-exceed peak current, based on the damaging energy. For a triangular approximation of an exponentially decaying pulse, with 50% duration T50 : W = 0.7RI 2 T50

2.1. Direct Discharge to an Electronic Component

45

where T50 = 50% pulsewidth R = device through resistance √ Solving for Wmax = 1 × 10−6 J and T50 = 150 ns, we get Imax = 3/ R. For instance, if the device resistance (pin-to-ground) R = 100 , Imax = 0.3 A peak For a 1500- human body resistance and an unprotected device, this correspond to VESDmax = 0.3(1500 + 100) = 480 V Figures 2.4(a) and 2.4(b) show some typical ESD damage in microelectronics. Although CMOS and field-effect transistor (FET) devices are notorious for their fragility to ESD, other technologies can be victims too. The trend toward hyperintegration (VLSI and ULSI with 10,000 to a million devices per ˚ make things worse since all spacchip) and gate dielectric down to 250 A ings and thicknesses are further reduced. Most highly integrated chips now have several layers (up to six–eight levels of metallizations). It is not an overstatement to say that if ESD vulnerability is not treated drastically, it can be a major obstacle in the challenge toward faster speeds and shorter propagation delays. Table 2.1 is often reported in the literature (1) and shows the susceptibility of various electronic devices to a standard human body ESD. For someone used to dealing with a certain degree of accuracy, this table may appear as neither very serious or reliable. Which ESD level destroys a JFET: 140 V or 7000 V? or a CMOS: 250 V or 3000 V? How can any protection strategy be optimized if the data are so vague? Nobody is to blame; there was no sloppiness in the gathering or compilation of data. But actual thresholds of ESD failure can, indeed, vary by 1 order of magnitude or more, based on the following: •

• •

• •

Damage thresholds differ depending on how the pulse is applied: one pin against all (n − 1) pins shorted together? Or each pin selectively against the grounded case? Or all possible combinations? Damage thresholds differ according to pulse polarity. Damage thresholds of a same part number, same manufacturer, vary from one vintage to another, depending on the plant of origin or the serial number of the masks used. Damage thresholds are not the same for a unique test pulse than as for repeated pulses. Damage thresholds of identical, compatible part numbers from different manufacturers vary widely.

46

Chapter 2 Effects of ESD on Electronics

Junction burnout E B C

• PJ = IVBD • TJ → TC

Junction Bipolar discrete short IC

Alloy

• Junction Short (90% of damages with Bipolar) Oxide punchthrough AL

V

• V > VBD

SiO2

• Punchthrough

SI

• Oxide Short

Oxide short

MOS discretes

(27% of damage with MOS) Metallization burnout AL

• PM = i2R

SiO2

• TM → TC

Open Bipolar & MOS

• Open Trace ( 10% of damage for Bipolar 63% of damage for MOS) (a)

3

C2

(b)

Figure 2.4 (a) Typical ESD damages in microelectronics. (b) Magnified view of IC damaged by ESD. (Adapted from JPL, report by Trigonis.)

2.1. Direct Discharge to an Electronic Component

47

Table 2.1 ESD Susceptibility of Various Electronic Devices to Human Body ESD Device Type

Range of ESD Susceptibilty (V)

VMOS MOSFET GaAsFET EPROM JFET SAW OP AMP CMOS Schottky diodes Film resistors (thick, thin) Bipolar transistors ECL (PC board level) SCR Schottky TTL HCMOS (74HCOO) with integrated protection NMOS 3 μ (with protection) NMOS 1 μ (with protection)

•

30–1800 100–200 +100, −800 100 140–7000 150–500 190–2500 250–3000 300–2500 300–3000 380–7000 500–1500 680–2500 1100–2500 2000–4000 6000 3000

Reported levels depend on the criteria selected: Was a part declared failed when it was functionnally wrong? Or as soon as its direct current (dc) parameters deviated from initial specification?

In Figure 2.5 a check of V , I characteristics reveals a breakdown voltage deterioration. Figure 2.6 shows, on a Weibull distribution graph, the ESD threshold of CMOS inverters from four different brands. The monitored parameters consist in an input current > 1 μA (indicating a damaged gate insulator) or an output not responding to input change, whichever failure came first. The graphs show ratios of 3 to 1 or 4 to 1 between the best part and the worst part of the sample. Also the deviation varies widely from one manufacturer to another. Another example showing that the ESD damage level is never a “green light/red light” situation is shown in Table 2.2. The product tested was a bipolar logic gate type 54L04 (TTL, low power). One hundred devices were tested for multiple pulses until a failure occurred. The criteria for failure was to monitor the deviation of two critical parameters from their normal value: Iinput

High

Voutput

Low

Normal = 10 μA max;

failure if I > 20 nA

Normal = 0.3 V max;

failure if V > 0.05 V

The results are shown in number of parts that did not survive to N pulses at level V . All the parts survived after the application of up to 175 pulses at 2000 V; then 10 died between 176 and 200 pulses. The survivors were stressed to 2750 V, where casualties are seen as soon at the first pulse. Finally, of the 15 survivors that came victoriously through the 200 pulses at 5000 V, 10 died at the first

48

Chapter 2 Effects of ESD on Electronics 4

8

12

20 30

Gate section D out of specification (inputs low)

20

20

Gate section C in specification (inputs low)

10

0

16

CD4001A ISS vs. VDD

0

4

8

10

12

Leakage current in mA

Leakage current in mA

30

0 20

16

Volts

Figure 2.5 Example of deteriorations in reverse breakdown (9).

Table 2.2 Failure Decision Is Never a Step Function (11) Pulse Level (V)

Number of Pulses to Cause Failure (N) 1

5750 5000 4250 3500 2750 2000

10 12 16 9 2

2

3

4

1 2 1

8 2 1 1 1

50

1

75

1

125

1

175

2

200

3 8 11 10

application of a 5750-V ESD. Can we then say that we have a product that can withstand ESD at 2000 V? or up to 5000 V? This is the case where all the usual methodology of stress tests and quality control (QC) have to be used to come up with a reliable number that will characterize the ESD immunity with a certain confidence level (12). In all these tests an unstressed sample lot should be verified to avoid the introduction of an uncontrolled variable not related to ESD. An interesting question arises: Would the 15 heroes that came through 5000 V have gone even further if they had not been inflicted, at lower levels, with 600-V discharges? Some test plans require that after every run at a given ESD voltage, the entire lot under test be replaced by a new one. This is a way to characterize the true ESD immunity of this product. However, the cumulative effect of multiple discharges, with increasing levels, is missed. Some technologies can be significantly more fragile than the previous example. The following relates to the ESD test results of an analog

2.1. Direct Discharge to an Electronic Component

100 99.9

300

Stress in volts 1000

49

99.9

In (time/stress) B

99 C,D

A

50 30

50 30

10

10

3

3

1

1

0.3

0.3

0.1

0.1

0.03

0.03

0.01 100

300

1000

Cumulative failutre in %

Cumulative failure in %

99

0.01

Stress in volts

Figure 2.6 ESD failure level for 4001 inverters from Manufacturers A, B, C, and D (10).

radio-frequency (RF) mixer IC, containing GaAs components, in a SOT (small outline technology) package: Sample size: 30 parts Type of test: human body, pass/fail treshold: 100/200 V Type of test: machine model, fail treshold: 100 V This is clearly a very ESD-sensitive device because of GaAs technology, requiring serious handling precautions and external protection components in its application. Another related problem is one of latent failures: a part which still appears undamaged after an ESD test may in fact have its lifetime affected. There are several confirmations that parts which have been subjected to ESD (either by fortuitous or intentional event) become “walking-wounded” that will exhibit abnormal failure rates in the field (12). But even this is not always true: some sample lots which were ESD stressed have exhibited, during accelerated life tests, better life-times than the sample lot, unstressed! This self-healing phenomena has been given several explanations, the description of which would be far beyond the scope of this book.

50

Chapter 2 Effects of ESD on Electronics

Since 1980, the U.S. Department of Defense (DOD) has issued a standard document, DOD-Std 1686, defining all the requirements for an ESD control program for electronic components and assemblies. Originally intended for suppliers and subcontractors of the DOD, it has become a commonly used reference for the industry in general. The DOD Standard (2006 Rev.) calls for: •

• • • •

Identification and tagging of ESD-sensitive items (Class 1 with sensitivity between 250 and 2000 V and Class 2 with sensitivity between 2000 and 4000 V); details of the corresponding test given in Chapter 3 Built-in circuit protection at chip and card level ESD-proof handling, shipping, and other procedures QC and audits Field maintenance precautions

The standard also requires that subcontractors rule out Class 1 devices when a Class 2 device is available that could perform identical functions. As a complement to DOD-Std 1686, the Department of Defense has issued Handbook 263, which gives ESD control guidelines and details of failure mechanisms. The document also contains classifications of ESD protection equipment, materials, manufacturing, and shipping procedures. (For an excerpt from Handbook 263, see Appendix A.) Other organizations such as the ESD Association or the IEC (International) also publish complete static control programs intended for manufacturers of electronic devices and equipment (see Chapter 3).

2.2. DIRECT DISCHARGE TO ELECTRONIC EQUIPMENT ENCLOSURE The direct discharge is the most classic case and the easiest to understand. The charged person or object (the “source”) touches a metal enclosure (the “load”). Most of the time [Fig. 2.7(a)] the discharge occurs on a purely mechanical part, which is touched intentionally (knob, key, switch, handle) or fortuitously (frame, covers, connector shell). Some more severe occurrences are shown in [Fig. 2.7(b)]: • • •

Finger approaching an unprotected input/output (I/O) connector Finger arcing through, or arc creeping around, a light-emitting diode (LED) or incandescent display Discharge on a PCB-mounted switch in which case a subsequent arc occurs internally between the toggle and the active contacts of the switch

In these latter cases, the ESD current can in fact reach directly the electronic components by a conducted path. Except for some damping caused by the wire or trace length, the situation is almost as severe as the direct discharge to a module pin, as was discussed in Section 2.1.

2.2. Direct Discharge to Electronic Equipment Enclosure

51

Metallic loudspeaker element

Wiring or PCB

to PBX ground

Plastic housing (a)

(b)

(c)

Figure 2.7 Personnel ESD coupling by direct contact.

Figure 2.7(c) shows another variation where the discharge occurs on a telephone set, via the earphone and its loudspeaker capsule. The consequences in this case are severe: The ESD transient is causing a hang-up of the conversation or loss of the memorized numbers. Whatever the scenario, the current then returns to ground by all possible routes, with amplitudes prorated to the impedances of these respective paths. This means that the bulk of the current will flow by the lowest impedance path, the remainder flowing through all other possible routes. For instance, Figure 2.8 illustrates what these routes can be for a single stand-alone machine. At this point in our discussion, let us briefly return to the actual waveform of a hand/metal (the most severe) type of personnel ESD, seen in Section 1.5 and Figure 1.29. The sharp peak of initial current caused by the local discharge of the forearm-to-target capacitance does not return by the machine-to-ground path. Instead, it remains confined in the loop formed by the hand and the machine cover. Only the main part of the current pulse, with rise time of 5–10 ns, is reclosing by the machine-to-ground impedance. In Figure 2.8(a), the discharge current path seems obvious, the machine being grounded by its safety wire and/or its neutral wire (neutral is generally grounded at the building level). However, the reality of this path does not resist a closer

52

Chapter 2 Effects of ESD on Electronics (a) Charged body

Grounded item IESD

(b) Charged body

Ungrounded item IESD

Several kV (c) Uncharged body

Charged item IESD

Figure 2.8 Personnel ESD coupling routes, showing return current paths.

look. The self-inductance of a round wire above ground is 1–1.5 μH/m, resulting in 3 μH of inductance for a typical 2-m power cord. For a current rise time of 5 ns, its dynamic impedance would be 3 × 10−6 L = = 600 dt 5 × 10−9 notwithstanding the additional length of building earth wire. Why would the entire ESD current choose to run across more than 600 while a lower impedance path exists in parallel? Figure 2.8(b) shows what this easier path can be. Any machine containing conductive parts has a capacitance to ground. In the case of a metallic casing, the capacitance to ground can reach 100 or even 1000 pF. For instance, a mainframe having a bottom area of 1 m2 , located 8–10 cm above ground, will have a parasitic capacitance of 100 pF. For a rise time of 5 ns, this corresponds to a dynamic impedance of about 50 . If the machine is lifted 0.80 m above ground, on a nonconductive table, this stray capacitance will decrease to approximately 40 pF, representing 120 of impedance, still less than what the ground wire can offer. Therefore a large proportion of the ESD current (specially during its rise, the most threatening one) will sink via the chassis-to-ground stray capacitance. This can be verified by the following, simple experiment: An ESD simulator is discharged on a grounded equipment. Then the power cord is removed completely

2.3. Indirect Discharge

53

and the test is repeated on the now floating frame. A discharge will occur with no difficulty and, if a current probe is inserted over the generator tip, it will read about the same peak current as with the grounded configuration. What will be affected is the discharge time constant of the pulse; in other words, the machine will stay charged for a longer time. Does this mean that for a normally grounded machine, no current is flowing into the ground wire? Certainly not: The same current probe, slipped over the power cord, would read a peak current that can be few percent to 10% of the total ESD current. In Figure 2.8(c) a third possibility is shown: the reverse discharge. In this case a machine has been charged by: • • •

Successive previous discharges from people and objects Internal static generations Laminar flow of air, specially dry or cold air or rubbing against a dry, isolated material

If the machine is floating versus ground (table-top equipment with power cord not connected, battery-powered device, and the like), the recombination of charges is not occurring or very slowly. When somebody approaches the machine, or takes the power cord to plug it in, a discharge will occur. If the machine is off, no harm is done to it, but the resulting surge creates locally a power line transient that may alter the operation of other machines nearby. Eventually, if the machine was in a stand-by, self-powered mode, a lock-up can occur that may necessitate a more or less elaborate restart.

2.3. INDIRECT DISCHARGE With an indirect discharge, the person does not (or even cannot) discharge directly on the equipment. For instance, if the machine is entirely housed in plastic with no or few accessible metal parts, nobody will discharge on it. In the early 1970s, with the massive arrival of plastic housings for electronic office products and electronic data processing (EDP) terminals, there was a general belief that they would mark the end of the electrostatic nightmare. “Bye-bye ESD” was the song, but people did not dance to it for very long: Field reports came in by legions to show that these products were experiencing even more ESD crashes than those with metal casings! Figure 2.9 shows what happens. A person discharges on any nearby metallic part: a door frame, a water pipe, a furniture, perhaps the very desk on which the machine is standing. Then, the ESD pulse radiates a strong local electromagnetic field, which couples into the nearby electronics since a plastic enclosure offers no shielding at all. With a desktop machine, for instance [Fig. 2.9(a)], if the motherboard lies flat on the bottom of the unit, the printed circuit is within 2 or 3 cm of the ESD current path. Figure 2.9(b) is a more diabolic variation of indirect ESD witnessed

54

Chapter 2 Effects of ESD on Electronics

IESD

IESD

(a) On metallic desk supporting a plastic product

(b) On a desk lamp

Figure 2.9 Indirect discharge.

by the author: A battery-operated calculator with a printer was being used by a draftman. During winter months, when the draftman switched his desk lamp on and off, the calculator would print a burst of erratic figures. At first a power-line transient was suspected but, besides the fact that the unit was not plugged into anything, the printer would turn on even when the lamp was simply touched. In fact, the ESD current was flowing via the lamp shade and the stem, coupling to the power cord via the large capacitance between the flexible tube and the wire inside and then to the ground. This long current path was radiating like an antenna on the plastic calculator circuit board. [Note: The author remembers a cocktail party where he experienced discharges on a large metal dish where the hors-d’oeuvres were arranged: The dish was on a cloth-covered wooden table, obviously grounded nowhere. But the charge transfer was enough to cause a violent ESD. Hopefully, sauteed chicken livers on toast and shrimps-a-la-creole are fairly ESD immune.]

2.4. COUPLING MECHANISMS OF ESD PULSE INTO THE VICTIM’S CIRCUITRY At the very instant of the discharge, a locally strong electromagnetic field excitation takes place: • •

The electric (E) field, which was established at a high value by the charged body, is collapsing abruptly. A magnetic (H ) field caused by the discharge current suddenly raises to a large value.

Both dE /dt and dH /dt field derivatives play a role, but all practical experience has confirmed that the severity of the threat is strongly related to the magnitude of

2.4. Coupling Mechanisms of ESD Pulse into the Victim’s Circuitry

55

the current. This is not to say that it could not be predicted from the initial voltage, but everything being equal—generator capacitance, discharging path dimensions, initial voltage, and arcing gap length—tests done with the least source resistance are generally causing the most machine malfunctions. The hypothesis that the arc length and the E field in its vicinity are predominant factors in the ESD susceptibility is usually contradicted by this fact: A machine withstanding 10 kV ESD with a generator having 2000 of internal resistance will almost certainly fail at a lower level with a tester having only 150 or 300 of internal resistance. In fact, a test condition considered as the most severe of all is one where the arc no longer exists, the discharge being done with direct contact of the probe tip. The role of the arc for air discharge is important in that it dictates the speed of ionization of the gap, hence contributing to the rise time, but the arc itself is not the predominant radiator. Instead, the radiating structure is made of: • • •

The human body (or charged furniture) The arm, terminated by the short arc The wall of the victim structure, with return by a more or less defined ground path

In the majority of cases [with the exception of Fig. 2.8(b) acknowledged], the electronic circuits of the victim equipment are not directly in the conducted path of the ESD current, which flows usually on housings and metallic structures. There is, therefore, a near-field coupling mechanism by which the localized field created by the discharge induces a voltage spike into the exposed circuit.

2.4.1. Magnetic Field Coupling Figure 2.10 shows a simplified model of this phenomenon, based on the discharge current only. A first thing to point out is that the dimensions of the ESD generating circuit are large compared to its distance to the receiving circuit. Therefore, it cannot be treated as a punctual source. Simple solutions of Maxwell’s equation for small electric or magnetic doublets with their resulting (1/d)2 and (1/d)3 field-to-distance dependency cannot be straightforwardly applied. A rigorous approach would be to apply the method of moments to the current path, broken down in small filaments. The much simpler model shown assimilates the ESD current path to a long radiating wire for which the resulting magnetic field is easily calculated from the Biot and Savart law. The ESD drain path to ground being long versus the distance of observation the magnetic field is given by: H (A/m) = I /(2πd) where I = ESD current in amperes d = distance from ESD path to victim circuit

(2.1)

56

Chapter 2 Effects of ESD on Electronics IESD

S

R

H

Simplified model: the H field is modeled from an infinite straight wire, carrying IESD

Ampère's law: H = I /2p R Example: IESD = 15 A (from a 4 kV simulated ESD) Distance R

H peak

Voltage induced in 1 cm2 loop Rise time 1 ns Rise time 5 ns

3 cm

80 A/m

10 V

2V

10 cm

24 A/m

3V

0.6 V

30 cm

8 A/m

1V

0.2 V

Figure 2.10 ESD coupling by radiation.

If the area of the circuit illuminated by the ESD field is known, a derivation of the field over the rise time gives an approximation of the open-loop voltage induced, generally sufficient for a quick prediction. Vi = −

dφ A dB = dt dt

(2.2)

where Vi = induced voltage, V A = victim circuit area, m2 B = induction in teslas, with 1 tesla = 104 gauss = 80 × 104 A/m Rearranging Eqs. (2.1) and (2.2) and using more convenient units, we end up with: I A Vi = 2 (2.3) td

2.4. Coupling Mechanisms of ESD Pulse into the Victim’s Circuitry

where I A t d

= = = =

57

change in ESD current, A victim circuit loop area, cm2 rise time of the ESD current, ns distance from ESD path to victim circuit, cm

Figure 2.10 gives the results in voltages induced per centimeter squared of victim area, for three distances from the ESD path, assuming rise times of: • •

1 ns typical of the fast precursor peak with a hand/tool discharge ≤ 8 kV 5 ns more typical of simple hand discharge, or air discharge above 8 kV

Example Two printed traces 1 cm apart, with a 5-cm parallel run, located at 10 cm from the ESD flow will see a peak transient of 1 V/cm2 × 5 cm2 = 5 V. This is enough to create an erroneous bit in most logic technologies. Although very elementary, this method of predicting the ESD pulsed fields, hence the induced parasitic voltages, gives adequate approximation when compared to actual measurements. Even though the current flows more as a spread stream than as in a thin wire, the H field around its path can still be found by Eq. (2.3). This field from the ESD pulse has two effects: • •

It couples to the inner circuits of the machine: circuit boards, flat cables, discrete wiring It illuminates also the outside, all around the ESD source and discharge path (Fig. 2.11), where external signal and power cables behave as receiving antennas as well

1 2A Ipeak

−

+ 3

2B

Figure 2.11 ESD coupling mechanisms: (1) The discharge current flows over the equipment cabinet. (2A) Cabinet imperfections let the high-frequency component (near or above the λ/2 resonances) penetrate and shine inside. (2B) The discharge current radiates on the I/O cables. (3) Circuits inside intercept the high-frequency field. Note that these mechanisms are derivative, that is, frequency dependent.

58

Chapter 2 Effects of ESD on Electronics

Another criticism could be raised against this overly simple model: Considering the frequencies involved, the current flow is supposed to stay confined on the outer skin of the metallic cabinet (assuming a direct discharge) because of the skin effect: At 100 MHz, for instance, the skin depth in steel is about 30 μm, therefore, a 1-mm steel cover would be 30 skin depths thick and, according to basic shielding theory, no ESD current should be found on the inner side. This would be true if the whole housing was a homogeneous shield, which is not the case: Slots, joints, vents, displays, cable entries create huge leakages especially at these high frequencies (this will be addressed in Chapter 5, under packaging aspects). As a result, the ESD current excites the many slot antennas formed by box discontinuities, cooling apertures, ungasketed seams, and the like. At the lower part of the frequency spectrum, these openings represent a minuscule fraction of wavelength, and their attenuation is significant. But for that part of the ESD spectrum that approaches or exceeds their λ/2 resonance, they shine inside with practically no attenuation. Therefore, in a device not specially hardened against ESD [or high-frequency electro magnetic interference (EMI), up to 1 GHz], the ESD current will flow on the inside of the cabinet as well as the outside. Now guess which part of the ESD-radiated field induces the largest voltages in the exposed PCB traces and in the cables? The high-frequency end, of course. However, knowing just the magnetic field may not be sufficient. A deeper knowledge of the nature of the electromagnetic field near the ESD path may be wished, as explained next.

2.4.2. Electric Field Coupling from Indirect ESD on Floating Parts Electrostatic discharge to an ungrounded, passive structure is a peculiar, although quite common, variation of indirect ESD. The basic coupling scenario is shown in Figure 2.12 and found in many practical situations such as in Figure 2.13. The charged person touches a floating, conductive object representing a sufficient surface—say more than a few tens of square centimeters. At the instant of contact, this object is acting as the armature of a capacitor that suddenly raises to the intruder’s voltage. In contrast with the previous cases with a grounded structure, where the ESD source was basically short-circuited by the target, what we have here is: • • •

A floating armature that is abruptly brought to kilovolts (+ or −) The local, narrow current spike i1 due to the small finger-to-target discharge, with the corresponding H field A strong E field impressed on the circuits of the victim equipment facing this armature

The effects of this E-field surge are generally less a problem than those caused by the H field in the previous examples. However, the circuits that are basically

2.4. Coupling Mechanisms of ESD Pulse into the Victim’s Circuitry i1

Floating armature A C1-G Victim circuit

59

1 to 2 kΩ A

VESD i2

C1-G

τ

ZGND

i2 Z(PCB-to-Ground) Impedance, wired or capacitive

Equivalent schematic

Example:

General scenario

VESD = 5 kV Rd = 1 kΩ

C1-G = 5 pF

ZC1−G << 1 kΩ ZGND << 1 kΩ i2 = 5 A peak RC = 5 ns τ50% = 3.5 ns

Figure 2.12 Scenario of E-field ESD coupling via floating structures.

Victim equipment

Metallic top

Plastic dashboard PCB

C1-G

Electronic module

Plastic or wooden desk Chassis GND

Actual event On the metalic top of a nonconductive desk (a)

Actual event On the metal portion (floating trim or button) of plastic dashboard (b)

Figure 2.13 Two practical situations of indirect ESD with E-field (capacitive) excitation.

“trapped” between the hot armature and ground will see a capacitive current: V i2 = C1−G (simplified formula, assuming a constant voltage slope) t (2.4) V0 −t (2.5) i2 = e RC1−G (more general formula) R

60

Chapter 2 Effects of ESD on Electronics

where C1−G = stray capacitance of the floating armature to the exposed circuit V0 = source voltage Capacitance C1−G depends on the area of the exposed vicim circuitry and its distance to the armature. Typical values range from one to tens of picofarads; t is the time it takes for the floating structure to reach the full intruder’s electrostatic voltage. This time, in turn, is related to the stray capacitance involved (Fig. 2.13). Example Taking 3 pF as an average value for C1−G , and a 5-kV/1 ns voltage front, the equivalent circuit of Figure 2.13 results in

i2 = 5 A peak RC = 5 ns,

and τ (50% pulsewidth) = 3.5 ns

Depending on how the victim circuits are arranged versus the path of this capacitive current, whether they are shielded or protected by a PCB ground plane and the like this coupling can cause a malfunction such as a logic change-of-state or lock-up. In the IEC type of ESD test (see Chapter 4), this configuration is re-created by using a vertical or horizontal coupling plate (VCP or HCP).

2.4.3. Measured E - and H -Field Values near an ESD to a Grounded Structure In 1984 this author conducted a set of experiments to evaluate both E and H fields. Fields were measured by miniature monopoles, short balanced dipole, and magnetic loop (electrically shielded). The probes were connected to an Electro-Metrics ESA 1000 spectrum analyzer. A slow scan speed and sufficient RF attenuation were chosen to avoid spectrum analyzer error due to the broadband nature of the measurement. The ESD simulator was a Schaffner NSG 430 (150 /150 pf Network) set on repetitive mode in order to obtain multiple scan overlays. First, the test setup of Figure 2.14 was arranged to measure the field amplitude facing an ESD in the absence of any protective shield. This would be the case of a discharge to a grounded metal object near an equipment having only a plastic enclosure. This also serves as a reference to further shielding effectiveness assessment. Although the nonuniformity of the field makes closer measurements less accurate, E- and H -field magnitudes have been measured at 10 cm, 30 cm, and 1 m. The vertical structure was a 50-cm by 6-cm aluminum plate, firmly bonded to the copper ground plane. The ESD gun was set to 10 kV. An arc discharge, with a slow repetition rate was made on the upper edge of the plate. The ground return for the ESD gun was a flat strap about 30 cm long to reduce the effect of both inductance and location of the return conductor. For the same repeatability reason, the orientation of this strap was always kept in the vertical plane formed

2.4. Coupling Mechanisms of ESD Pulse into the Victim’s Circuitry

61

Grounded metal plate

Electric or magnetic field probe

50 cm

ESD simulator

Short, wide ground strap

Feed-through BNC

Copper ground plane Coaxial lead to spectrum analyzer

Figure 2.14 Experimental setup for ESD field measurements.

by the gun and the target structure. Figure 2.15 shows the results of electric and magnetic fields, after bandwidth and antenna factor correction. A few remarks are in order. 1. Comparison with other measurements: The 1-m results correlate within about 15 dB with few other reported measurements, done with similar ESD simulators on air discharge mode. 2. Field roll-off with distance: Compared to the 1-m results, the 30-cm and 10-cm results seem to show a 1/(distance)1/2 dependency instead of a 1/(distance)2 or 1/(distance)3 as one would expect in such induction (near-field) regions. In this instance, it must be kept in mind that the radiator is the whole circuit formed by the simulator and the vertical discharge structure. Seen from an antenna located at less than 1 m, this structure behaves as a long radiating wire and not a dot source or small doublet. 3. Wave impedance: Comparing E dBμV/m and H dBμA/m (see Table 2.3) shows a wave impedance E/H varying: • At 1 m from about 100 around 30 MHz to 300 above 300 MHz • At 10 cm from about 10 around 10 MHz to 150 above 300 MHz This indicates that for actual arcing on a metallic structure, the ESD generates a predominately magnetic (low-impedance) field in the induction region, tending to the theoretical 120-π wave impedance in the far-field zone. Since the changeover of near to far field is wavelenght dependent, the transition occurs at different frequencies for the various distances of the experiment; the change is very pronounced for the 10-cm case.

62

Chapter 2 Effects of ESD on Electronics ESD fields at a distance of 1 m Frequency in MHz 1

3

10

30

100

300

dBmV/m/MHz and dBmA/m/MHz

E-field (vertical monopole) 100

100 E-field (horizontal)

80

80

TS

60

60 H-field (loop at maximum orientation) 40

40

TS Near field

20

20

dBmV/m/MHz and dBmA/m/MHz

120

120

Far Field 1

3

10

30

100

300

Frequency in MHz (a) ESD fields at a distance of 30 cm Frequency in MHz 10

30

120 dBmV/MHz and dBmA/m/MHz

100

300

E-field (vertical monopole)

120 100

100 E-field (horizontal) 80

TS

60

60 H-field (loop at maximum orientation)

40 20

80

40 TS

Threshold of sensitivity (TS) is shown for reference Near field 3

10

30

100

20 Far field 300

Frequency in MHz (b)

Figure 2.15 ESD field at (a) 1-m, (b) 30-m, and (c) 10-cm free-field radiation.

dBmV/MHz and dBmA/m/MHz

3

2.4. Coupling Mechanisms of ESD Pulse into the Victim’s Circuitry

63

Frequency in MHz 1

3

10

30

100

300

140

140 120

120

100

100 H-field (loop at maximum orientation)

80

80

TS

60

60 40

40

TS

20

Near field

20

1

3

10

30 100 Frequency in MHz

dBmV/m/MHz

dBmA/m/MHz

E-field (vertical monopole)

300

(c)

Figure 2.15 (continued)

Table 2.3 Average Wave Impedance of ESD Radiated Fields Frequency

3 MHz

30 MHz

Distance 1 m Zwave Aver

Near Region 100

Transition 120 160

Distance 10 cm Zwave Aver

100 MHz

300 MHz Far Region 317

Near Region 14

40

158

500 MHz

Transition Region 178

Stating that the field is predominately magnetic near the discharge path may be surprising. It is a common belief that ESD, being electrostatic, has to be an electric field. A close look at the discharge network can clarify this: Simple field theory says that in the near-field region, low-impedance (<377 ) sources will radiate predominately magnetic fields, while high-impedance (<377 ) sources radiate predominately electric fields. The ESD simulator used was an IEC-65 (1985) type, with an internal resistance of 150 , thus behaving more as a magnetic source in near field. Will “real-life” electrostatic discharges really appear like this? Actual furniture-type discharges from large metal objects, carts, chairs, and the like

64

Chapter 2 Effects of ESD on Electronics

Table 2.4 Combined Results of Actual ESD Related Field, from Several Authors ESD Type and Voltage (All actual human, except 4)

Distance (m)

Peak Field E field H field

Results Normalized to 1 kV and 0.10 m

1. 2. 3. 4. 5.

1.50 1.50 1 1 0.1 0.10 0.45

120 V/m 60 V/m 200 V/m 110 V/m 13 kV/m 10 A/m 11 kV/m 30 A/m 3 A/m

450 V/m/kV 150 V/m/kV 300 V/m/kV 110 V/m 2.6 kV/m 2 A/m 2.2 kV/m 6 A/m 2.7 A/m

4 kV (fastest rise time) 6 kV (slow) 7 kV (fast) 10 kV (slowest rise time) 5 kV (slow arc) (fast discharge) 6. 5 kV simulator (fast)

may exhibit dynamic impedances 10 times smaller or even less, creating more magnetic field in the near region. While human body resistance, being at least 3 times higher, will create less magnetic field. 4. Integration of the field spectrum: a rough integration over the frequency domain gives the following approximation for the time-domain E- and H -field peak amplitudes: • At 1m = 70 V/m 0.4 A/m • At 30 cm = 120 V/m 1.2 A/m • At 10 cm = 220 V/m 6 A/m A few authors (13–16) have also measured the E field during human or artificial ESD, using calibrated wide-band antennas. Their field spectrum data are close to the plots of Figure 2.15. Since they also recorded peak field values in the time domain, some other results are reproduced in Table 2.4, being well in the range with the results of our coarse integration. The last column artificially normalizes all results to 1 kV ESD and 0.10 m distance.

2.4.4. Effect of Wave Impedance on Voltages Induced in Nearby PCBs and Small Circuits In the second part of the experiment, the antennas were replaced by a PCB having a unique trace representing a loop of 10 cm × 10 cm. This trace was alternatively terminated into 1 k, open-ended, and then terminated into a short. The voltage induced was read on the spectrum analyzer, with all precautions to prevent possible pick-up by the coaxial cable.The effects of varying the far end terminating resistances is interesting in the perspective of understanding which of the H -field or E-field coupling predominates. Figure 2.16 shows the induced voltages in dBμV/MHz, the PCB being oriented tangent to wavefront. For better comprehension, Figure 2.17 shows the traditional model for a small rectangular circuit illuminated by an electromagnetic field. The E field creates a transverse voltage V2 , which appears as a

2.4. Coupling Mechanisms of ESD Pulse into the Victim’s Circuitry Frequency in MHz 3

10

30

100

100

C

300

110 100

Z

90

90 Ground 80

80 A or B 70 60

dBmV/MHz

110

1

70

1

3

10

30

100

60

300

Frequency in MHz A : with Zfar end = 1 kΩ B : with Zfar end = ∞ (open)

in all cases Znear end (Receptor) = 50 Ω

C : with Zfar end = 0 (short) Calculated voltage based on H-field coupling only Calculated voltage based on E-field coupling only

Figure 2.16 Broadband voltage induced in a 100-cm2 PCB run located 10 cm from the ESD path, parallel to wave front (PCB not oriented for maximum H -field interception).

1 V1 = −

Zwire

h

Z1

df dt

Z2 2

Vx E

l′

q H

Figure 2.17 Traditional model for voltages induced in a small circuit illuminated by an EM field.

65

66

Chapter 2 Effects of ESD on Electronics

high-impedance source (current source) with an open-circuit voltage: V2 = E.2l

π cos θ cos α λ

(2.6)

where θ = angle between the E field and the direction of propagation α = angle between the plane of the loop and the direction of propagation λ = wavelength Given the 50- input of the “victim” receptor end (spectrum analyzer), a high impedance on the far end, like 1 k or ∞, will double the available transverse voltage, while a shorted end will nullify it. In contrast, the H field creates a longitudinal voltage V1 appearing as a low-impedance source (voltage source) with a value: V1 = −

dφ = −ωBlh dt

(2.7)

Here the effect of varying impedances is totally different. The voltage Vx across the receptor end is V1(H coupling) =

Z2 Z1 + Z2 + Zwiring

(2.8)

In our experiment, Z2 = 50 and Zwiring = 0.1 + j ω(0.4 μH). A highimpedance Z, on the far end, will nullify the magnetically induced voltage. A short circuit on the far end will maximize it. In Figure 2.16 the curve C corresponds to the far end being shorted. Therefore, the electrical contribution is minimum while the magnetic contribution is enhanced. The flat portion of the voltage spectrum corresponds to the domain where the H field decreases like 1/F [as seen in Fig. 2.15(c)], while at the same time the coupling coefficient increases like F . Above 10 MHz, the wiring impedance in Eq. (2.8) starts to create series insertion loss, causing less and less voltage available at the 50- end. Finally, above 150–200 MHz, the H -field spectrum itself decreases like 1/F 2 , causing the available voltage to collapse even more rapidly. By comparison, the values for magnetically induced voltage using Eqs. (2.7) and (2.8), or the graphical method (17) are also plotted in Figure 2.16. They are in fair agreement with the measured data. Curves A and B of Figure 2.16 correspond to a high impedance on the far end, which minimizes the magnetic contribution. What is left is the electrical contribution, which is clearly one order of magnitude less than the magnetic one. This furthermore supports the previous statement that the radiation of the “standard” discharge, in the near field, tends to be predominantly magnetic. Then, the PCB was rotated 90◦ to be perpendicular to the wavefront, such as to intercept the maximum magnetic flux. The results are shown in Figure 2.18 and can be interpreted in exactly the same way as for the previous case. In this

2.4. Coupling Mechanisms of ESD Pulse into the Victim’s Circuitry

67

Frequency in MHz 3

10

30

100

110

300

110

Z C

dBmV/MHz

Ground 90

90

A

80

dBmV/MHz

100

100

80 B 70

70 60

3

10

30

100

300

60

Frequency in MHz A : with Zfar end = 1 kΩ B : with Zfar end = ∞ (open)

in all cases Znear end (Receptor) = 50 Ω

C : with Zfar end = 0 (short)

Figure 2.18 Broadband voltage induced in a 100-cm2 PCB run located 10 cm from the ESD path perpendicular to wave front (PCB intercepting maximun H field).

setup, however, the magnetic contribution is so pronounced that even with a far end termination of 1 k (curve A), it overrides the electric contribution. In fact the difference between curves A and C below 10 MHz correspond approximately to the ratio of 1000- to 50- termination. Interestingly enough, integrating the spectrum of curve C corresponds to a peak voltage of about 15 V.

2.4.5. Effect of a Typical Metallic Cabinet on ESD-Radiated Effects If instead of being plastic, the cabinet housing the electronic circuit is metallic (or metallized), the ESD field should be attenuated by the normal shielding effect of the material. Therefore, and not accounting for the external pick-up by I/O cables, shown in Figure 2.11, it seems that internal circuit boards and wiring should be fairly well protected. However, real-life enclosures are full of slots, seams, apertures, and the like, disrupting the shield integrity. Every shield discontinuity across the ESD current path will “shine” inside, with an efficiency proportional to its length compared to the half wavelength. The ESD spectrum extending up to, and sometimes above 500 MHz, any slot longer

68

Chapter 2 Effects of ESD on Electronics

than a few centimeters will exhibit significant leakage. To show this effect on the ESD mechanism, the “witness” PCB was placed inside a 1-mm-thick aluminum rack; to calibrate the experiment, all mating surfaces were thoroughly brushed and screwed, and the ESD gun, set to 10 kV, was discharged on all sides and especially in the seam areas. No value exceeded the sensitivity level of the test setup. Then, several typical shield imperfections were introduced by removing some of the top cover screws and inserting thin cardboard liners under the seams to simulate an ungasketed cover with ordinary manufacturing tolerances. Figure 2.19 shows the results: The induced voltage can be read up to 100 MHz, for the enhanced magnetic coupling (far end shorted), which demonstrates two points: • •

The thin seam unequivocally spoils the protection offered by the box to ESD coupling. The reradiated field inside is, once again, predominantly magnetic.

An interesting effect was also simulated: One of the threaded holes used to attach the top cover was painted and the cover was mounted using a long screw, protruding about 2.5 cm (1 inch) inside the box. The results are also shown in Figure 2.19. It seems that the screw generates a secondary arc inside, between the fillets and the inner box surface.

3

10

Frequency in MHz 30

100

40

90 dBmV/MHz

cm

50 cm

100

C

80

300

Victim PCB

100

Grounded aluminum rack

90

80

B

dBmV/MHz

1

70

70 A

60

60

1

3

10

30

100

300

Frequency in MHz A

ESD on protruding screw head, PCB terminated into 1 kΩ

B

ESD on protruding screw head, PCB terminated into short

C

ESD on vertical or horizontal seam with a forced 1 mm gap, PCB being 5 cm behind discharge point

Figure 2.19 Voltage induced on the 10-cm × 10-cm PCB trace housed in an aluminum rack.

2.4. Coupling Mechanisms of ESD Pulse into the Victim’s Circuitry

69

As formerly shown in Figure 2.11, this radiated field from the ESD pulse has therefore two effects: 1. It couples to the inner circuits of the machine: circuits boards, flat cables, discrete wiring. 2. It also exists outside, causing external cable pick-up, all around the ESD source, and therefore couples into the external signal and power conductors. Starting in 1995, very fast digital sampling oscilloscopes became widely available, with analog bandwidths greater than 1 GHz, along with ESD generators having fast 0.7–1 ns calibrated rise times. Several authors, including this one, using miniature field probes, did more experiments. Some are reported in Appendix F, with results generally in line with the ones just described, accounting for the wider available frequency range.

2.4.6. Common Impedance Coupling with an ESD Finally, another coupling mechanism, generally of second order, has to do with common impedance pollution (Fig. 2.20). Even if they are conductive, metal or metallized parts have a certain RF impedance. The impedance of a 1-mm-thick steel plate for a 1-ns rise time is 0.4 /sq. As long as the ESD current is concentrated on the exterior side, the ZI longitudinal voltage has little influence, thanks to the skin effect. But as soon as metal-to-metal assembly exists, like spot-welding, riveting, or even tightly screwed joints, there is a strong local increase of the longitudinal impedance. Another example would be a metallized plastic, whose conductive paint cannot match a real metal barrier. For instance, the resistance of some nickel or graphite paints range from 1 to 10 /sq. For a 10-A ESD current, this corresponds to an instantaneous ground shift of 10–100 V, respectively, between A and B.

lESD

A Z increase

Z

B Actual Ideal (Skin depth for steel = 10 μm @ 1 ns)

Figure 2.20 Common impedance coupling caused by the ESD current.

70

Chapter 2 Effects of ESD on Electronics

Two electronic subassemblies having their signal reference (0 V) grounded at these points will be submitted to this common mode voltage.

2.5. RESPONSE OF VICTIM CIRCUITS AND TYPE OF ERRORS So far, we have evaluated the peak amplitude of voltages induced into victim circuits illuminated by the ESD pulse. In many cases, the amplitudes were far above the logic thresholds, so an erroneous change in logic status was expected. However, the induced transient is extremely short and it must be compared, on a time scale, to the alternating current (ac) noise immunity ot the victim logic (Fig. 2.21). For instance, a bipolar gate of the TTL-Low-power Shottky (TTL-LS) scheme with 7 ns switching speed has a worst-case dc noise margin of 0.4 V (0.8 V typ.) for a junction temperature of 85◦ C. If the noise pulse is shorter than 7 ns, it takes more amplitude to trigger the gate, that is, to provide the nanojoules that the gate needs to operate. As shown on the curve, the faster the logic, the more vulnerable it is to ESD induced pulses. One could also compare the frequency spectrum of ESD with the various bandwidths of CMOS, TTL, ac, and so forth (Fig. 2.22). The slow CMOS [Fig. 2.22(a)] is no longer used in new developments and is shown for reference to emphasize the fact that slow technologies can be efficiently out-of-band filtered against ESD. Applications requiring rise times < 3 ns cannot be error-protected by simple filtering, since most of the ESD spectrum is present in their useful bandwidth.

5

V τ

Volts

3

OS HCM ACT

4

2

CMOS standard

1 STTL

mi typ n TTL

ECL .3 .5

1

2 3 5

Typical induced pulse width (personnel)

10

30

100

Typical induced ESD pulse width (furniture)

τ in ns

Figure 2.21 Noise immunity of logic families versus pulse width.

2.5. Response of Victim Circuits and Type of Errors

10 Ref 0 dB

71

A 100 ns t

1 ns

−20 dB

−40 dB

A

10 kHz

30

100 kHz 300

1 MHz

3

B

10 MHz 30 100 MHz 300

C D

1 GHz

3

10 GHz

Frequency

Figure 2.22 Time and frequency aspects of the current from a 10-A/1-ns human body ESD pulse, compared to typical logic bandwidths: (a) slow CMOS, no longer used in new developments; (b) HC and HCT; (c) ac and ACT; (d) Bi-CMOS.

An important aspect to take into consideration is the coupling factor by which the ESD transient induces a parasitic voltage. Except for the cases where the discharge is directly impressed on the victim circuit, the coupling factor is a time (or frequency) dependent term: the induced voltage is not a replica of the ESD waveform but its derivative. Thus, the duration of the induced spike will be approximately equal to the rise time of the ESD current (the time during which the derivative dφ/dt exists). This is shown in Figure 2.23(a). Note also the sign of the voltage Vi , which is the opposite to the sign of the field change: Of course, in terms of the actual polarity of the induced noise, this sign will depend on the orientation of the victim circuit. In Section 1.3, we did say that depending on the nature of the triboelectric materials that created the electrostatic charge, the ESD pulse can be positive or negative. A polarity reversal in the ESD pulse would create a corresponding reversal in the induced noise: A typical logic gate is susceptible to a positive-going level when it is in a LOW input (logic 0) state, and susceptible to a negative-going level when it is in a HIGH input (logic 1) state. But it is not always so: Some critical entries such as Reset, Watchdog, and the like can be normally at a HIGH level, activated by a LOW level. Therefore, it makes sense to perform an ESD test with both polarities: Depending on what the logic circuits are doing at the

72

Chapter 2 Effects of ESD on Electronics (b) Furniture

(a) Personnel IESD

IESD

time

HESD =

1 2πd

time

HESD time

VInduced =

−d∅ dt

time VInduced

time

time

τr personnel

τr furniture

Example: 10 kV personnel, 10 A peak, 1ns. Open voltage induced in 1 cm2 circuit area, 10 cm from discharge

Example: 2.5 kV furnlture, 50 A, τr = 15 ns Open voltage induced in 1 cm2 circuit area, 10 cm from discharge 0.7 V

7 mV 2 volts

1.2V 1 ns

A

12.5 ns

B

Figure 2.23 Comparison of induced voltages from normal human body and furniture ESD, showing influence of time derivatives.

time of the ESD event, the equipment under test could be more vulnerable to one polarity than the other. Figure 2.23(b) shows the same cascade of couplings for a furniture discharge. Since the rate of change of the ESD current, in amperes/nanoseconds is generally less than for personnel, it seems that the threat is less severe: however, the rise time being much longer (e.g., 15 ns), the induced spike is also longer and could exceed the dc noise margin of most logics: This is why, among other things, a furniture discharge can be a more threatening kind of ESD.

2.5.1. Influence of Circuit Impedances In most cases where the ESD event is causing a high peak current, we have seen that the strongest contributor to induced noise is the magnetic field: Consequently,

2.5. Response of Victim Circuits and Type of Errors −

+

ZW

VL

Vi

ZS

73

ZL

Iinduced

VL = Vi

ZL | ZS | + | ZW | + | ZL |

ZS ZL

CMOS

TTL

Output low

150–500

30

Output high

150–500

150

1 MΩ /7 pF

3-5 kΩ/5 pF

Input

Figure 2.24 Influence of victim’s circuit impedances on coupled voltage.

the induced voltage will appear in series in the circuit (Fig. 2.24). The resulting voltage at the victim component input will be Vdiff = Vi

ZL ZL + Zs + Zw

(2.9)

where ZL = input impedance of victim component (e.g., logic gate, op-amp) Zs = source impedance of driver Zw = impedance of wiring Since, for obvious reasons, the victim input generally has a higher impedance than the signal source, Eq. (2.9) shows that most of the noise will appear at the victim input. For the same reason, this usual impedance configuration will cause the noise coupled by the electric field to be less a problem since it will appear differentially across the line, seeing the parallel combination of ZL shunted by ZS . In any case, two other considerations may prevail: •

•

Above a certain level (50–100 V for some ESD-sensitive technologies) even if the device is not triggering a malfunction, some permanent overstress may have occurred. Certain technologies, such as CMOS, exhibit a latch-up mechanism if the input becomes more positive than Vcc or goes more negative than the 0-V reference. In these conditions the parasitic PNP and NPN transistors within the device behave like an SCR (Silicon-Controlled Rectifier) that is fired. Even once the pulse has gone, the SCR stays in conduction. The current is limited only by the external loads and can lead the device to destruction since the parasitic switch can only be defused by powering off the supply.

74

Chapter 2 Effects of ESD on Electronics

2.5.2. Specific Disturbance Created by the Hand/Metal Initial Spike We have shown that in the case of a personnel discharge with the hand/metal scenario (person holding a key, a coin, tool, wearing a ring, wrist bracelet), a very narrow “precursor” discharge takes place. Actual 10–90% rise time ranges from 100 ps to 1 ns, with a fall time more or less in the same range. Remembering that, locally, the H -field pulse has the same shape as the current, the dH /dt field derivative is the replica of the current derivative. Therefore this sharp current spike can cause significant induced voltage in exposed circuitry. For instance, assume a victim loop at 10 cm from the discharging finger, with an 8-kV ESD voltage; taking Ipeak = 30 A and t = 0.7 ns, we get from Eq. (2.3): I Acm2 Vi = 2 td =

2 × 30 Acm2 = 8.5 V/cm2 0.7 × 10

Clearly, this short initial spike can be a bigger threat than the subsequent, longer pulse. This peculiar aspect has been a growing concern for the manufactures of ESD generators and the test engineers using them (17). As we will see in Chapter 4, a substantial uncertainty in ESD test results can be attributed to this precursor spike, which is not always produced the same way by different brands of generators.

2.5.3. Errors/Malfunctions Induced in Analog Devices So far, we have emphasized the ESD effect on logic circuits because of their inherent ability to respond to a unique, isolated short pulse. However, although the likelihood of an ESD disturbing analog circuits is low, because of their generally limited bandwidth and the long time averaging of their response, the possibility exist. Consider this example: If an ESD discharge is made in the room while an ordinary radio set or audio-amplifier is turned on, a popping noise will be heard in the loudspeaker. Therefore, although limited to a few tens kHz passband, the IF circuits and amplifiers did pick up some ESD noise. This can be visualized in the frequency domain, by considering the broadband spectrum of an ESD-induced glitch, a portion of which will fall within the bandwidth of the analog (tuned or baseband) device. This can be visualized also in the time domain by considering that the short-width, high-amplitude pulse will be integrated through the long time constant of the analog device. The pulse will stretch over a longer time, with less amplitude, but yet enough to initiate a circuit response since the threshold of analog amplifiers is usually very low (Fig. 2.25).

2.6. Prediction of Actual ESD-Induced Error, Fast Approximation Method

75

Frequency response of a tuned circuit ESD induced noise

ESD spectrum

Time response of analog Bp

Resulting pulse Frequency

Frequency domain

Time Time domain

Figure 2.25 Conceptual view of the response of an analog device to ESD noise.

Besides these dynamic aspects, low-speed analog devices can present another inherent problem, because of their typically very high input impedance. In the presence of an electrostatic field (without a discharge), the input(s) can raise to any voltage, depending on the divider network formed by the electrostatic source-to-device capacitance and the device-to-ground capacitance. Solutions to this problem, more a static than an actual ESD issue, are presented in Chapter 5.

2.6. PREDICTION OF ACTUAL ESD-INDUCED ERROR, FAST APPROXIMATION METHOD The following, expedited method is using the simple H -field time derivative of Eq. (2.3), assuming a regular slope for the peak ESD current. A more elaborate method, based on frequency spectrum considerations, and cascading all the frequency-dependent coupling mechanisms is described in Appendix E. The principle of frequency approach for a complete vulnerability prediction, very classical in EMI (18), is summarized in Figure 2.26. Since these parameters, such as induction, half-wave length resonances, shielding attenuation, and out-of-band rejection, are best described in frequency domain, a more organized approach to the solution can be made. On the other hand, time domain offers the advantage of a straightforward solution whose accuracy is generally sufficient. In contrast, frequency domain requires some more complex transformations. Example The ESD scenario of our application is shown in Figure 2.27. A personnel ESD occurs near a flat cable running running close from the ESD “drain path.” The cabinet structure is metallic, but no integral shielding is expected from the cover (they could be plastic). The ESD is a severe, 8-kV hand/metal-type discharge as simulated by IEC 61000-4-2 or similar specification. The standard current waveform for such 8-kV discharge is sketched, but we have overlaid a simplified envelope, which we will use in our quick calculation.

76

Chapter 2 Effects of ESD on Electronics

IESD peak

Volts induced per Gauss = wBS

BG/MHz

B (or H) peak

× τr

τr

ESD waveform (time domain)

Induced V/MHz

=

F1

Frequency

Calculation of magnetic field (time domain)

Frequency

T→F conversion

Victim input rejection

×

F2

Pass

F3

Fcut-off

Frequency

V/MHz

=

Stop

Frequency

F1 F2 F3 Frequency

Figure 2.26 Frequency domain aspects of a complex ESD coupling.

PCB

#1 f 0vReframe to

Ipk = 30 A

Triangular approximation of actual waveform

25 cm

IESD 60 ns B

PC

#2

ef 0vR frame to

4 cm 8 cm

Ins Simplified

−5V

120 ns

600 V Induced voltage into (25 x 4)cm2 loop Actual t

Figure 2.27 ESD scenario for the prediction example of Section 2.6.

The victim element of our concern is a 25-cm ribbon cable interconnection between the backplanes of two stacked racks. For such a short link, the two interconnected daughter cards are simply using high-speed CMOS (HCMOS) logic interfaces with the following characteristics: DC noise margin (worst case): 0.7 V Logic rise time: 4 ns Single-ended (nondifferential) drivers and receivers

2.6. Prediction of Actual ESD-Induced Error, Fast Approximation Method

77

Assuming that the hand-held tool (or key) is touching a metal member at 8-cm from the vertical cable chute, with the discharge current running along this frame edge, returning to the source by the ground plane, is there a risk of error by ESD field coupling? Note that the signal ground (0-V reference) is connected to the chassis ground at both ends. The center of the loop can be averaged at a distance d = 8 cm + 4 cm/2 = 10 cm. The bulk induced voltage is given by Eq. (2.3): Vi = 2(I A cm2 /td) = 2 × 30 × 100 cm2 /(1.10) = 600 V This is the common-mode voltage appearing in series in the loop. Since the PCBs signal references (0 V) are grounded at both ends, the rejection of common mode (CM) noise is extremely poor, for such a nondifferential link. In addition, CMOS having a high input impedance, virtually the full CM voltage will appear at the input end (see Section 2.5.1) of the victim circuit. However, H-CMOS offers a somewhat limited bandwidth∗ compared to the spectral occupancy of the induced pulse, considering that the duration of the induced spike is approximately equal to the rise time of the ESD current. An attenuation due to bandwidth limitation must be accounted for: Victim’s impulse BWidth ESD Spectral BWidth ESD rise time ≈ Victim logic time constant

Bwidth rejection =

Finally, the equivalent voltage seen by the HCMOS input will be 600 V

1 ns 4 ns

= 150 V

In conclusion: •

•

∗ The

The bulk 600-V transient impressed on the wires versus ground could be damaging with sensitive ICs. But we can assume that this is at least a Class 2 device (see discussion of component sensitivity classes in Chapter 3) with ≥ 2-kV ESD immunity to human ESD, so it will not suffer permanent damage. With 150 V, the equivalent input voltage is 200 times the 0.7-V dc noise margin. Logic errors will occur. Notice that the slower part of the pulse induces also −5 V on the same loop, which is not totally innocuous to the logic, and the solution must be able to reduce the two effects.

impulse bandwidth of a first-order low-pass circuit is approximated by its 7-dB bandwidth.

78

Chapter 2 Effects of ESD on Electronics •

Any attempt to solve the problem by “opening the ground loop,” that is, floating either one of the PCBs from chassis ground would be useless: For a nanosecond rise time, the parasitic capacitance of the PCB represents a rather low impedance, behaving as a virtual short.

2.7. REMARKS ON THE ACTUAL CURRENT PATHS AND ASSOCIATED RADIATION Although the current waveform, as measured on artificial targets, which are basically discrete resistors, appears as a unique pulse, it results actually from the combination of two currents, which in real-life ESD do not follow the same path, as visible in Figure 1.29. 1. The narrow spike i2 is confined to the limited hand-to-machine zone and its corresponding capacitance. This current is a radiating element of limited length, approximately 10–30 cm long, depending on the incident angle of the finger, or the ESD test electrode. This “cone of influence” is well described by Pommerenke (17). Therefore, the “infinite wire” model used in the previous example can only be applied to the victim’s elements shorter than 30 cm and not farther than ≈ 30 cm from the discharge point. So, as explained in Section 2.5.2, this precursor spike is a major threat, but only within its limited 3D boundary of influence. 2. The bulk of the current pulse i1 with rise time of 5–15 ns, depending on the inductance of the return path, runs along the entire machine-to-ground path. Taking a typical height for human torso/arm, the path length represents a one-way trip of about 1.50 m, so the “long wire model” is perfectly applicable up to 1 m around the discharge path. The outcome of this is that a more accurate calculation should take into account the two currents i2 and i1 with their respective shapes and paths and combine their effects on the exposed victim circuit.

2.8. PERSONNEL OR FURNITURE ESD: WHICH ONE IS WORSE? From what we have seen (Fig. 2.23), it looks like the furniture ESD, due to higher current and resultant magnetic field, is the biggest threat. However, consider this: 1. Furniture ESD will only occur at some points of the victim equipment. Some other areas will never be touched by a moving cart, chair, and the like. 2. Furniture ESD usually exhibit much lower voltages than personnel: Therefore recessed parts and metal parts or cicuits behind a plastic barrier will never be zapped by a furniture ESD because the voltage does not reach

References

79

the breakdown value of the air gap or plastic barrier. On the contrary, a 15- or 20-kV personnel ESD will reach by arcing these remote points. Therefore, as already said in Chapter 1, it seems that a complete ESD simulation should address both types of discharges.

REFERENCES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18.

Yenni, D. Huntsman, J. and Mueller, G. 3M Static Products Documentation, 1995. Greason, W. ESD Damage in Electronics. Research Study Press, Letchworth, England, 1990. ESD with Passive Components, EMC Technology Magazine, Nov., 1988, p. 45. Vinson, J, Bernier, J., and Croft, G. ESD Design & Analysis Handbook. Kluwer Amsterdam, 2003. Verhage, K. Compound Level ESD Testing. μ Electronics Reliability Journal , 1998. Fukuda, K. VLSI Protection, HBM and MM. EOS/ESD Symposium, 1988. Kelly, M, et al. Comparison of ESD Models for CMOS. EOS/ESD Symposium, 1995. Boissieres, F. Electrical Interface Presentation. ST MiCroElectronics Corp. 2008. Allen, R. How to Set Up an ESD Control Program. Evaluation Engineering Magazine, Feb., 1999. Petrizio. Electrical Overstress vs Device Geometry. EOS/ESD Symposium, Denver, 1979. Branberg, G. ESD and CMOS Logic. EOS/ESD Symposium, Denver, 1979. Denson, D. ESD Testing of Advanced Schottky TTL. EOS/ESD Symposium, Orlando, FL, 1982. Kozlowski, A. Barski, M. and Stulchly, S. Characterization of ESD Tester. IEEE/EMC Symposium, Washington, DC, 1990, p. 270–273. Wilson, P.-Ma, M. Fields Radiated by ESD. IEEE/EMC Transactions, Feb., 1991, p. 10– 18. Pommerenke, D., and Aidam, M. ESD Waveform, Field and Current of Human & Simulated ESD. Journal of Electrostatics, Vol. 38, 1996, Nov. 1996 p. 33– 51. Smith, D. Unusual Forms of ESD. EOS/ESD Symposium, 1999, Orlando, FL. Pommerenke, D., and Aidam. To What Extent Do Contact Mode and Indirect ESD Test Reproduce Reality? EOS/ESD Symposium, 1995, San Diego CA, p. 101– 109. White, D., and Mardiguian, M. EMI Control Methodology & Procedures. ICT, Gainesville, VA, 1989.

Chapter

3

Principal ESD Specifications Since the discovery of the ESD threat to electronic equipment, several testing specifications have been established by international and professional bodies. Although they more or less address the same phenomenon, the values recommended by the different organizations vary widely, depending on the type of application with which they deal. Some call for a specific rise time, some others do not. This chapter describes briefly the esssential ESD specifications in use. No details are given on test methods since these will be covered in Chapter 4 for the major ESD test specifications for components and equipment. The standards and specifications reviewed hereafter are only those exclusively dedicated to ESD testing or static control. There are hundreds of other specifications, practices and the like that cover various industries or families of products where a simple section or paragraph deals with ESD. They have, of course, not been listed here. For most of them, they follow or refer to the major ESD documents presented hereafter. Electrostatic discharge specifications can be classified into two simple categories: component level (1, 2) and machine/system level:

1. At component level : They specify the device’s (integrated and discrete components) immunity to static discharges, to characterize the risk of immediate or latent failures. It is essentially a test of the unpowered device survival, in a manufacturing or servicing environment. 2. At machine/system level : They specify the immunity of electronic equipment to ESD-induced errors or alterations. This is a survival issue as well as a test for functional integrity of the powered equipment, in a user-type environment, Table 3.1 gives a recapitulation of the various types of ESD specifications presently in effect. The test voltage is labeled “maximum” because many

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ECMA 237 (from TC20) SAE J1113 Part13 & ISO 10.605 (Automobile) MIL-Std 1541 Spacecraft STANAG 4235, 4239 (NATO Std)

For Equipment IEC 61000.4.2 (former IEC 801-2) ANSI C.63-16

IEC 61.340-5.1 and 5.2 replaces former 1000.15.1

DOD Std 1686 & Handbook 263 EIA/JEDEC Test Method 5.1 HBM Test Method 5.2 MM Test Method 5.3 CDM

For Devices MIL-Std 883

Category

4–8 kV (contact) 4–25 kV (Air) 10 kV & more 25 kV 300 kV

Up to 8 kV (contact) 15,000 V (Air) Up to 8 kV (contact) 15,000 V (Air) 2 k/330 pF or 330 /150 pF Arc source 500 /500 pF 1 /1 μH/1 nF

330 /150 pF

330 /150 pF

15 /0.5 μH/200 pF 30 /30 nH/10 pF

Up to 800 V Up to 2 kV N.A

100 pF/1500

100 pF/1500

Discharge Network

Up to 8 kV

2 kV(Class 1) up to 8 kV N.A.

Max. Voltage Pol. +/−

Table 3.1 Summary of Current and Proposed ESD Standards

Mandatory, part of EMC regulatory compliance Similar to IEC, with differences in simulator and test procedure Follows IEC 61000.4.2 Different test for modules and for vehicle install. Network depends on application Personnel Helicopter discharge

ESD control program ESD protection guidelines Used for device sensitivity evaluation (nonmandatory) (theoretically, R = 0) R,L,C parameters may vary depending on IC package Antistatic control procedures Approach similar to MIL-Std

Human Body Model (HBM)

Comments

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Chapter 3 Principal ESD Specifications

specifications regulate the amplitude in function of the type of environment (controlled or not) where the product is marketed.

3.1. ESD TEST SPECIFICATIONS FOR DEVICE SENSITIVITY 3.1.1. MIL-Std 883 The Military Standard 883 (2006 revision) is a voluminous document describing all reliability tests (electrical, mechanical, etc.) for microcircuits. ESD test method 3015.7 is only a tiny portion. It clearly excludes electroexplosive devices (EEDs)∗ and ammunitions. The highlights are as follows: •

•

•

According to the results, the device under test (DUT) is classified into the following categories: • Class 1: sensitivity of 2 kV or less • Class 2: sensitivity of 2–4 kV • Class 3: sensitivity of 4 kV or more The test pulse is generated via a 100-pF, 1500- discharge network, typical of the human body model (HBM). Maximum rise time is 15 ns. Figure 3.1 shows the basic test circuit, with an example of the current of a 2-kV test pulse. It is clear that this test pulse is significantly less severe than most actual personnel discharges (see Chapter 1). One reason is that ESD test of devices is generally aimed at IC factories, where a minimum of antistatic precautions are expected. The test pulse is applied: • All pins together vs. case = (+) and (−) • All combinations of input vs. ground, output vs. ground, Vcc vs. ground, for (+) and (−) pulse

1 to 3000 MΩ

HV supply

1500 Ω Ipeak : 1.33 A for 2 kV Test

Bounceless switch 100 pF∗ ∗Insulation resistance > 1010 Ω

T50% = 100 ns Device under test (DUT)

t tr = 15 ns

Figure 3.1 Test circuit for MIL-Std 883, with a 2-kV test pulse shown as example.

∗ ESD immunity of EEDs is generally covered in specific equipment specifications, such as MIL-Std 1512 (USAF), requiring a 25-kV pulse via a 500-pF/5-k network.

83

3.1. ESD Test Specifications for Device Sensitivity •

The calibration is checked via a current probe clipped on a short replacing the DUT. Notice that the simulator behaves as a current source only for DUT resistances 1500 .

3.1.2. EIA/JEDEC and ESD Association Test Methods These device test methods cover all the possible variations of ESD events, arranged in three test setups: •

•

•

ESD Test Method S.5.1 (HBM): The human body model is the oldest and most widespread method. The test circuit is similar to MIL-Std 883. Test voltage is up to 8 kV, eventually 15 kV for harsh environment applications. ESD Test Method S.5.2 (MM): The need for a machine model was urged by the findings that robots and automatic chips or wafer handling tools could generate strong ESD (see discussion of furniture discharge in Chapter 1). Typical device test circuit and waveform are shown in Figure 3.2 ESD Test Method S.5.3 (CDM): The charged device model is an attempt to replicate actual situations of device handling or storage in manufacturing/servicing areas (see discussion in Chapter 2 on, direct discharge to components). The test setup, simulating a device discharging on itself, is shown in Figure 3.3. A variation of this test uses the socketed device model (SDM).

None of the test voltages is a mandatory criteria but rather a way to characterize various devices, making the users aware of their susceptibility and eventually apply adequate protection measures. In general, manufacturers or their clients set their own acceptable failure criteria. For comparison of the respective threats posed by these HBM, MM, and CDM tests, see Appendix A.

1 to 1000 MΩ

HV Supply

(Theory : 0 Ω 0.5 μH Low R Practically: few ohms)

200 pF

DUT

I peak : 7 A for 400 V Test

Shunt for measuring I t 60 ns

Figure 3.2 ESD test circuit for Machine Model (MM).

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Chapter 3 Principal ESD Specifications

DUT Dielectric C 1 to 1000 MΩ

Charging armature

Example : 7 A peak for 500 V Test Rd = 30 Ω C = 10 pF Lp = 20 nH

Rd Lp

I measur.

HV supply

Figure 3.3 ESD test circuit for Charged Device Model (CDM). The DUT in “dead bug” position is charged through its self-capacitance and the charging plate. The device is then discharged on itself.

3.2. ESD SPECIFICATIONS FOR EQUIPMENT IMMUNITY 3.2.1. International Standard IEC 61000-4-2 Among the many standards and proposals existing in the industry, the IEC 61000-4-2 has the stature of an international reference. Initially released in January 1985 as IEC 801-2, it was at first intended for industrial control equipment and used the simple arc discharge. In 1990 a definite improvement was introduced by imposing a high voltage (HV) relay for triggering the discharge. Since then, it has continuously evolved into a very complete—and complex—document, whose important practical contents will be described in Chapter 4. Several test severities are recommended, according to the class of environment: Relative

Discharge Test Voltage

Severity Level

Humidity %

Floor Material

Contact

Air

1 2 3 4 Xa

≥ 35 ≥ 10 ≥ 50 ≥ 10

Antistatic Antistatic Synthetic Synthetic

2 4 6 8

2 4 8 15

a X is a special “open choice” category for specific environments, with levels that can be between or above the others.

Application of discharge is normally done by direct contact to the target zone. For the recessed areas that cannot be physically touched by the probe, but are still reachable by arc, the air discharge (similar to the early version) is still required. For equipments having no, or very little, metal structure, an indirect ESD test is applied via a coupling plane placed at 10 cm from the test item. Although its prime scope was directed to industrial controls, this standard has been rapidly generalized and adopted by the European Community under the

3.2. ESD Specifications for Equipment Immunity

85

title EN (European Norm), legally mandatory for any equipment marketed in Europe, as part of the general (EMC) electro magnetic compatibility compliance. In many areas for which it was not intended in the first place, such as medical devices, public transportation, metrology, and the like, this test method has been also found convenient and is called for in various product specifications. Recognizing the wide variety of equipments to be tested, and the diversity of operations they perform, this IEC standard does not establish specific criteria for success/failures but recommends categorizing the severity of ESD effects as follows: • • •

ESD ESD ESD ESD

causes a random but repeatable event. causes a consistent and permanent malfunction, suggesting that after is applied, an error condition persists. causes permanent hardware damage or loss of data.

3.2.2. ANSI C.63-16, ESD Test Methods, and Criteria for Electronic Equipment This standard is, in general, similar to the IEC 61.1000-4-2, this being due to the fact that many experts in the EMC community, worldwide, are sharing their views in the preparation of the two documents. Yet, the American National Standards Institute (ANSI) standard contains substantial differences on the test procedures and pass/fail criteria, the presentation of which are better organized and justified. The initial rise time for the contact discharge, being 0.4–0.6 ns, is faster than the IEC, which means an IEC successfull test could eventually fail if repeated with ANSI instrumentation. The early versions of the ANSI ESD standard did mention the furniture discharge test, but this requirement has been suppressed in the more recent versions.

3.2.3. ESD Immunity for Automobile Electronics, SAE J1113- 13 and ISO 10605 Although it generally follows the IEC 61000-4-2 test principles, ESD standard for automobiles is using different R,C discharge networks, taking into account the specifics of vehicle environment. Since the occupant is basically inside a metallic envelope, isolated from ground, with many synthetic parts (upholstery, dashboard, seats, etc.), the body model capacitance is 330 pF for inside elements that are touchable by the normal user or eventually a repairman. For example: • • • •

Radio and audio/video entertainment devices Power door locks and window switches Power seat control Blinkers and multifunctions levers

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Chapter 3 Principal ESD Specifications • • •

Headlight switches Steering wheel and column Side mirror controls

This includes accessible connector pins such as diagnostic connector socket, dashboard removable devices, and the like. Severity ranges from 4 to 8 kV for contact discharge and up to 25 kV for air discharges, depending on the critical aspect of a temporary or permanent malfunction. Complete airbag systems, including EEDs, are always tested in the most severe configurations. Corresponding test methods are briefly described in Chapter 4.

3.2.4. MIL-Std 1541, ESD Immunity Requirements for Space Systems As for airborne equipment, systems installed in satellites and other space vehicles are exposed to severe ESD threats. Based on NASA experience (3), and depending on which part of the vessel and which phase of the flight is concerned (lauching, stages separation, orbital, galactic trajectory, etc.), several generators are recommended: HV coil, flat plate, and direct capacitor injection: • •

Test voltages range from kV up to 300 kV, available energy from nanojoules to hundreds of millijoules. Source capacitances vary from nanofarads to hundreds of nanofarads, with peak discharge currents from 1 A to kA.

3.3. ANTISTATIC CONTROL PROCEDURES Apart from the strict device/equipment testing, a vast number of standards and recommendations have been published by the DOD and industry associations, regarding handling, packaging, grounding, and antistatic material evaluations. These ESD avoidance programs include also quality control (QC), people awareness, and educational aspects.

3.3.1. Military Domain: MIL-Std 1686 and MIL 263 Handbook The MIL-Std 1686 (1995 Rev.), ESD Control Program, is deemed to be a complementary document to MIL 883, dealing uniquely with electronic components, EEDs being namely excluded. In the past, the two standards did not cross reference each other, and the sensitivity classes were not harmonized, leaving some doubt as to whether or not they were part of a concerted strategy. This has been fixed, and the two documents are now coordinated.

3.3. Antistatic Control Procedures

87

MIL-Std1686 is a very complete document, including antistatic recommendations and control plan for parts, assemblies, and devices. Its main contents are as follows: • • • •

Requirements for device ESD test, per MIL 883, with identification/tagging of sensitive (ESDS) parts. Details of test plan with minimum number of pulses, pass/fail criteria, and failure analysis. Parts that have been submitted to ESD characterization should not be considered as deliverable items. ESD is NOT a burn-in kind of test. Obligation to vendors/subcontractors of military equipment to implement full ESD control at manufacturing, storage, delivery, and maintenance levels. This includes periodic audits of percent yields.

In later versions, the document also requires that assemblies and equipments meet the 2- or 4-kV immunity of industry standard IEC 61000-4-2. A recent trend of military agencies to standardization and paperwork reduction seems to indicate that MIL 1686 will be withdrawn and replaced by the corresponding ANSI/ESD S.20-20. The MIL 263 Handbook is an ESD control guide, helping in the successfull implementation of the 1686 ESD control program. Not a mandatory requirement, it covers: • • •

Basics of ES discharge and device failure mechanisms Implementation of protected areas, workstations, and static-free harware (handling, shipping etc.) Design tips and integrated protection networks for IC immunity

3.3.2. Industry Standards for Static Control Programs In addition to device testing, the ESD Association (accredited by ANSI) publishes technical reports and develops ESD standards, covering testing of antistatic materials. The EIA (Electronic Industry Association) and its related JEDEC (Joint Electronics Development Engineering Council) publish standards and procedures, such as EIA-625, for ESD-sensitive device handling. The international IEC 61340 Parts 1 to 5 (endorsed by the European CENELEC Comit´e Europ´een de Normalisation Electrique) provides a complete ES control strategy: • • •

Characterization of electronic components ESD sensitivity Static control procedures in factories: working areas, shipping, marking, packing, workers garments, machinery, and the like Evaluation methods and QC of antistatic materials, equipment, and working practices

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Except for a few details, these standards and recommended practices are generally in line with the military documents, their technical authors often sharing their expertise among several technical Committees.

REFERENCES 1. Verhaege, K., Recommendations to Improvement of HBM Component Test Specification, EOS/ESD Symposium, 1996. 2. Sicard, E., Bendhia, S., and Ramdani, M., EMC of Integrated Circuits. Springer, New York, 2006, Chapter 5. 3. Guidelines for Controlling Spacecraft Charging Effects, NASA Tech. Report, No. 2361.

Chapter

4

ESD Diagnostics and Testing U

ntil the early 1980s, it seemed that electromagnetic interference (EMI) and ESD were two different worlds. The two worlds paralleled, and in many companies and organizations the same people were wearing the two hats—but there were still two hats. EMI susceptibility studies were checking the behavior of equipment exposed to steady electromagnetic ambient fields and power line disturbances, while ESD tests attempted to reproduce human or furniture discharges and their effect on fragile circuits. Yet, testing a product for ESD vulnerability is one of the most important, versatile, and relatively easy to perform of all the EMI tests. Thanks to its huge bandwidth, greater than 300 MHz, and to the strong field created locally, the test can reveal all at once many weak spots of an equipment: • • • • •

Vulnerable PCB layout Insufficient immunity of I/O ports Missing or improperly bonded cable shields Improperly mounted filters Missing or inadequate shielding of the housing

These defects could have taken a much longer time to detect by classical methods, such as radiated susceptibility testing, which requires a shielded/ anechoic room, a set of transmitting antennas, and a powerful amplifier. However, as simple as it may look, the foundation of sound ESD testing is, of course, an accurate, repeatable test setup. Not all ESD simulators were created equal, and the test arrangement can also introduce some severe discrepancies. The early tests of the 1970s were quite often a “hit-or-miss” game. Product designers had to be content with such foggy results as “the equipment stand 2 kV but fails at 6–8 kV,” with results that could vary depending on where, when, or by whom the test was done. Although those days are gone, an ESD test giving dependable

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results is still a hard-to-reach goal, the first stumbling block being the core of the test set: the generator.

4.1. ESD SIMULATORS: HOW THEY WORK The earliest ESD generators were quite rough, people using sometimes home-made devices from ignition coils, TV set high-voltage power supplies, piezoelectric lighters, or even high-voltage cattle prods. Since 1970, many ESD simulators (which the EMC community quickly nicknamed “guns” or “zappers”) have been marketed, the most recent ones being generally thoroughly designed. Improvments have aimed at the reproducibility of the rise time, the accuracy of high-voltage setting, and the like. These simulators are based on the simplified models of Section 1.5, with the R,C network packaged in a convenient, generally handheld, unit (Fig. 4.1). A capacitor is charged by a high-voltage dc supply, then discharged on the equipment under test (EUT), through a determined resistance. One armature of the high-voltage capacitor is connected to the injection probe, generally shaped like a finger. The other armature is connected to the reference ground or any desired return path. To perform ideally, an ESD simulator should have the following features: •

A variable ESD voltage, easy to set∗ with an accurate readout (10% is an absolute minimum, with 5% being recommended). The setting can be continuous or by 100- to 300-V increments. Rch

Rd

≥ 1 MΩ

HV

Cd

EUT or calibration target

Figure 4.1 ESD simulator basic schematic. ∗

A problem exists as to how this voltage is monitored. Simple simulator designs set the capacitor charging voltage, then disconnect its hot side from the high-voltage supply (this is the isolated capacitor scheme) before the probe is discharged. This makes it difficult to retain a good voltage accuracy more than few seconds since the capacitor charge will constantly bleed-off, especially as the probe is approaching the target. To some extent, this happens also with real human body ESD. Other simulators monitor constantly the tip voltage (regulated high-voltage scheme) to keep it constant until the actual discharge. This gives a good repeatability, at the expense of an artificially severe condition, whereas the charge is constantly fed into the tip, even during the milliseconds preceding the discharge.

4.1. ESD Simulators: How They Work • • •

•

• • •

• • • • • •

• • • •

•

91

A selectable positive or negative discharge. The ability to deliver up to 3.7 A/kV in a shorted output mode, with 0.5to 1-ns rise times. Several (at least two) discharging resistors, easily interchangeable, for instance, 330–2000 for personnel and 10–50 for furniture, along with several capacitor options. The ability to generate a discharge with or without an arc (in the latter, the high voltage is applied only once the probe tip is in electrical contact with the EUT). A shot counter, such as the operator, applies a known number of discharges on each part of the EUT. A time-out device disabling the HV probe when the preselected number of shots is reached. An option of selecting a single shot or a repetitive mode, for instance, slow rate (e.g., 0.5–5 pulses/s) for formal testing and accelerated rate (20–50 pulses/s) for quick investigations. A warning (audible or visible) signal in case of aborted or sputtering discharge (restrikes). A way to bleed off smoothly the charge from the tip in case of discharge to floating parts. A ground return connection hardware that is safe, convenient, and idiot-proof. An automatic electromechanical or electronic safety latch that removes the HV from the tip when the gun is at rest. A remote control interface for unmanned operation. A filtered ac power input to avoid pollution of the ac mains, which could create false ESD problems by pulses coming through the back door (the power cord), thus yielding misleading test results. A sturdy hardware fixture for stand-mounted, instead of handheld, operation. This stand, tripod, and the like must be nonmetallic. Good portability and sturdy construction, for occasional or frequent field usage. Ease of calibration checks. A built-in, or separate quick checking device, which can be used before a new series of test to verify that no serious malfunction or component alteration has occurred. This is independent from the normal yearly calibration (1). Carefully selected components in the high-voltage section, for a long life expectancy.† Relay, resistors, capacitors, and switches must be of the

† An ordinary ESD test will easily totalize 1000–10,000 discharges applied to the entire EUT. For an EMC lab performing 50 tests/year, and adding the development test iterations, this could mean 100,000 to one million of high-voltage on/off switching per year for the discharge circuit .

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high-voltage/high-frequency brand: no arcing, no creepage, minimum parasitic inductance, no bouncing. Resistances must have a low R/V voltage coefficient. Of the existing simulators available commercially, to the author’s knowledge, no one meets all these criteria, although some models have almost all of them. Differences exist among the current models, concerning the maximum voltage, the making of the RC discharge network, and the like. Variations are also found in the operator–instrument interface. The access to the various settings (voltage, polarity, air or contact discharge, preset number of shots, etc.) can make significant differences. Some simulators have very intuitive controls, while others have menu-driven options that are a real nightmare. Each manufacturer advocates his choices using arguments whose technical basis are not always clear. One must admit that, although the basic schematic is simple, the making of an ESD simulator is not. The realization faces all the difficulties of a high-voltage transient generator, compounded by the challenge of extremely short rise times. Moreover, the basic construction bears an inherent weakness: It is presumptuous to assume that an assembly of discrete capacitors, resistors, and wires will act in the same manner as the capacitance of a human body, which is distributed over a wide surface. So far only one simulator has faithfully replicated the body (or furniture) spread capacitance: This tester was the IBM Type 5800 ESD simulator, which is briefly described in Section 4.2 but no longer available to our knowledge.

4.1.1. Arc or Direct Contact Another dilemna, nowhere near to being resolved, is the following: •

•

Should the simulator replicate by all means the conditions of an actual human (or furniture) discharge, by arcing, eventually at the expense of losing some reproducibility? Should the simulator sacrifice the arc conditions and inject, without an air gap, a calibrated, repeatable pulse waveform, that will stress the EUT “as if” it were the actual event, even though the electrical mechanisms are not all there?

Indeed, the issue is one of test philosophy, and the two theories have their pros and cons.The patrons of the “with-an-arc” ESD put forward several positive aspects: Air discharge does include, naturally, all real-life arc parameters (air gap disruption, strong localized electric field near the tip, arc resistance in the path, etc.). It can also, under certain conditions, create the “precursor” phenomenon, that prearcing we have seen occurring below 6–8 kV (see Section 1.5.4). And zapping with an arc can be performed rather easily on any accessible point of the EUT, even recessed areas such as spacing between keys and the like.

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93

The supporters of direct injection ESD have also many strong points, some being an answer to the weaknesses of “arc ESD.” For instance, the arc introduces an uncertainty because air breakdown will not reproduce itself exactly from one discharge to another, causing test conclusions that can be inaccurate. By eliminating the arc, direct contact ESD guarantees a clean, “sanitized,” easily reproducible waveform. “Not true” will argue the supporters of air discharge: Unless the target area is a clean metal zone, discharging on a painted or coated area does include an arc. Though not seen, it crosses through the paint, still creating the same uncertainty that the direct contact was deemed to eliminate. Therefore, true direct ESD can only be achieved by making a firm electrical contact on bare metal parts, protruding screws, keys and the like. For other areas, the operator must scratch or pierce the paint, then trigger the discharge, which complicates the test routine. The counterargument to this is that the so-called easier setup of the air discharge is, indeed, masking a real difficulty: regardless of the actual voltage setting on the HV dial, the arc will occur at the breakdown voltage of the air gap. In case of repeated discharges, it is the spacing of the probe tip to the discharge surface that will trigger the arc and may actually set the test voltage (Fig. 4.2). The only way to recreate actual arc ESD is to either: • •

•

Approach the EUT with the probe until an arc occurs, and keep moving to touching the target. Then move back and start all over again. Given a specified ESD voltage, set a gap slightly larger than the breakdown distance (using 13 kV/cm as a rule of thumb) and reduce the gap gradually until an arc occurs. Then retain this setting for the given test run. Monitor constantly the probe voltage instead of merely the HV supply setting. This is what some simulators do (KeyTek).

Another issue in favor of direct contact ESD is that it eliminates most of the operator’s body effects. With air discharge, the added stray capacitance of the operator may influence the test waveform, especially if he stays close to the probe. Finally, arc ESD necessitates control of the relative humidity during the test (air ionization can be influenced by the RH) while direct contact ESD is less sensitive to RH. A whole chapter could be filled with these arguments. In an attempt to clear the waters, Table 4.1 lists seven pros and cons and gives to each item a (+) or (−) score, weighted by its relative importance. Although the score unavoidably bears some subjective biasing of the author, we see that the two methods come very close. The next section will show how some typical ESD simulators have handled these conceptual problems.

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Chapter 4 ESD Diagnostics and Testing

?

doptimal (cm) ≅

VESD, kV 13

(a) ESD with single probe arc gap Problem: • Inaccuracy of gap setting • Different results when probe not perpendicular

(b) Improvement with a spacer • More accurate gap setting • Probe 90° to target • Does not work if target is a protruding shape: switch, key, etc. Graduations can be scaled in mm or approximate discharge voltage Contact probe

Arc setting distance (c) Further improvement The gap is set independently of contact shape and angle of approach. Relay in high-pressure bulb Enable/Disable

Rdischarge

HV setting

Pulser (single shot or repetitive) (d) Ultimate evolution • No more air gap arcing

Figure 4.2 Evolution of the discharge probe concepts.

d

4.1. ESD Simulators: How They Work

95

Table 4.1 Arc Discharge vs. Contact Discharge, Pros and Consa Topic

Arc ESD

Replicates real-life arc condition Guarantee of a well-reproducible waveform Cannot be performed on hard-to-reach recessed areas Requires scratching the paint Requires a carefully set gap dimension Insensitive to operator’s body proximity and other human factors Insensitive to RH Totals:

+3

−1

+2

Direct Contact ESD +3 −3 −2 +2 +1 +2

a Each

topic is either a bonus or a penalty, but is never counted on both sides. A 1 (less important) to 3 (most important) weigthing factor has been used.

4.1.2. Simulators for Equipment Test, Based on IEC 61000-4-2 Standard Since this standard enjoys a large international acceptance, the corresponding simulator will be briefly described. As shown in Figure 4.4, it is based on the simplified equivalent circuit of human body ESD (see Section 1.5), but with a discharge resistor of 330 , instead of the 1–2 k, more typical of human body models. The 150-pF storage capacitor is charged through a 10- to 100-M limiting resistor, providing a maximum charging time constant RC of 15 ms, such that after about 0.075 s (5 × RC) the capacitor is considered fully charged. This 330- value for the discharge resistor, replacing the 150- early versions, has several advantages: 1. For a given inductance L of the complete discharge loop, it forces a smaller L/R time constant, hence a faster rise for the main discharge current. 2. It is closer to the statistical low value for human body resistance, when in the kilovolt/nanosecond region. The schematic in the earlier, pre-1990 version simply used a switch on the capacitor charging side. The discharge was triggered by approaching the probe on the target surface; thus it was always an air discharge. The subsequent updates imposed that the capacitor be discharged by a switch, which is unavoidably a high-voltage relay. This relay permits a contact discharge without an arc, except for the recessed areas that the probe cannot physically touch. Consequentely, two probe tips are prescribed: • •

A pointed tip for contact discharge, so, eventually, a paint or oxide film can be penetrated, avoiding an uncontrolled arc through the paint. A spherical tip, as in the earlier versions, for air discharges.

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Looking at the IEC recommended test levels (see Chapter 3), we see that the contact discharge test, simulating the field-enhanced hand/metal object is only required up to 8 kV. Above this voltage, the standard requires air discharge. There are two reasons for this: One is that ESD event studies have shown that above 6–8 kV, the superfast initial spike is unlikely to occur. The other is that HV relays capable of switching millions of times 10–16 kV are expensive. For these reasons, many IEC-type generators, when in the air discharge mode, do not actually switch on and off the relay above 8 kV, but simply keep it closed during this test option.

4.1.3. Detailed Review of the IEC 61000–4-2 Simulator Definition The IEC (2) type of ESD simulator, along with its companion procedure, offers the advantage of a worldwide agreed-upon evaluation technique, with broadly accepted values. This provides a common baseline for assessing ESD immunity of many products (not always remembered, though, is the fact that the original IEC 801–2 “mother version” did not claim to address all sorts of electronic equipment, but simply industrial process controls). The following review is based on the current version (2001) of the standard but also takes into account the essential amendments of the recent drafts (2000–2006), not yet released at the time of this writing. The earlier, pre-1990 version, IEC simulator and its standard setup did have several shortcomings, of which a practitioner should be aware: Not that we intend to lead a visit through the museum of ESD history, but because we think that mentioning some past deficiencies will enlighten the comprehension of the more recent versions. Also, thousands of simulators of the first definition are still in use since some product specifications and purchasing requirements still refer to the IEC-801–2 standard, with the air discharge and 150-/150-pF network. Therefore we will describe the most significant problems of IEC 801–2 and how they are corrected in the current IEC 61000-4-2, acknowledging that the choice between direct contact or air discharge is still possible, and sometimes mandatory. 4.1.3.1. The Former, IEC 801–2 Simulator

Armed with the discussion about “arc vs. no arc” (Section 4.1.1), the reader will probably identify some of the latent weaknesses of the IEC in its earlier definition. Besides the problems pertinent to the sole air gap discharge, few others were peculiar to the IEC document itself: 1. The rise time and peak current requirements indulge too much on the simulator inacurracy. The specified rise time at 4 kV is 5 ns + 30%, with the corresponding current 18 A + 30%. This gives way to a large variance between the highest and lowest possible time derivatives: one compliant

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97

generator could deliver dI /dt, which is 3.5 times greater than another. The current IEC standard sets tighter tolerances for the current and rise time (Figs. 4.3 and 4.4). 2. The sharp precursor effect, typical of hand/metal discharge in dry air was neither specified or measured. It was more or less left to chance, depending on the speed and angle of approach, notwithstanding that the 8-mm spherical electrode does not invite the initial predischarge. The current IEC version impose a template for the initial peak . 3. The choice of a unique discharge resistance of 150 is a trade-off: Being midway between a severe human ESD (the low range of body resistance is about 1 k) and a furniture ESD (very low impedance), it has the

150 Ω + EUT

100 MΩ 150 pF

HV

2−16.5 kV

Grounding strap: 2 m × 20 mm width Insulating sleeve

Brass electrode

Steel ball

6 mm

8 mm

80 mm Probe discharge finger Circular array of discharger ≥2 Ω

Total parallel combination ≥ 2 Ω 50 Ω

0.9 I t

9 A @ 2 kV 37 A @ 8 kV 70 A @ 15 kV

0.1 I tr To simulator ground electrode test setup to check IESD waveform

Ipeak requirement: ± 30% when tested according to setup

Required waveform @ 4 kV: Rise time tr = 5 ns ± 30% Pulse width t = 30 ns ± 30%

Figure 4.3 Early IEC 801– 2 simulator characteristics (air discharge only).

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Chapter 4 ESD Diagnostics and Testing Vacuum relay (bounceless)

330 Ω

50-100 MΩ

EUT

150 pF

HV ±

Ground Strap Probe for air discharge: Slmilar to 1984 standard

Probe for contact discharge

φ8 25°−40°

Ipeak 1 (100%) 90% Ipeak 2 at 30 ns

I at 60 ns 10% 30 ns τr = 0.7 to 1 ns

60 ns

t

Ipeak1 (±10%)

Ipeak2 at 30 ns (±30%)

I at 60 ns (±30%)

7.5 A

4A

2A

8A

4A

22.5 A

12 A

6A

30 A

16 A

8A

Level (contact discharge)

HV (kV)

1

2

2

4

15 A

3

6

4

8

Figure 4.4 IEC 61000– 4-2 simulator characteristics. Current waveform is measured via a 2- coaxial target, with the measuring instrumentation in a shielded enclosure. The location of the discharge resistor is as shown on the IEC document, but manufacturers may choose to put it on the probe side.

advantage of simplicity. Yet it lacks the important aspect of furniture discharge, that is, the oscillatory waveform of the underdamped RLC network (see Section 1.5). It is not clear if this shortcut was supported by ad hoc studies or if it was a deliberate choice, for the sake of simplicity. No rationale for it was given in the IEC recommendation or subsequent annex. This is somewhat improved in the current IEC version. In fact, by changing

4.1. ESD Simulators: How They Work

99

to a higher (330 ) discharge resistance, the new simulator comes closer to the actual human body resistance for the kilovolt/nanosecond domain, but it is departing even farther from the furniture high current ringing waveform. 4. The pulse polarity was positive only. 5. The requirement for the discharge current return path was rather sloppy, leading to large differences between the calibration current waveform and the actual waveform delivered during a test, leading to poor repeatability. Figure 4.5 shows the stretching of the pulse rise time caused by the 1.5- to 2-μH inductance of the 2-m ground strap. The present calibration method with the coaxial target (see next section) eliminates the impact of the ground return strap on the rise time of the first peak. With the predischarge being generated at the probe itself, and thanks to the higher value of the discharge resistance, the ground strap has less critical effect, the location of the main current hump being somewhere between 10 and 30 ns after the initial peak (Fig. 4.6).

LS

RS:150 Ω

18 A

Ipeak

ZD ≥ 2 Ω

tr = 5 ns (a) Calibration LS

RS 18 A

Lloop 15 ns

(b) Actual test conditions, Lloop ≅ 1.2 mH for 2 m

Figure 4.5 Effect of self-inductance of the generator ground strap, stretching the rise time.

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Chapter 4 ESD Diagnostics and Testing IA

20 15 8 KV (AD)

10

4 KV (CI)

5 0 0

5

10

15

20

25

30

35

40

45

50

tns

IA 30 25 20

15 KV (AD)

15 8 KV (CI) 10 5 0 0

5

10

15

20

25

30

35

40

45

50

tns

Figure 4.6 Measured currents with an IEC 61000– 4-2 generator, for air discharge (AD) vs. current injection (CI) on a coaxial 2- target [after Mohr (9)].

4.1.3.2. A Few Specific Aspects of the Latest IEC Simulators

The research on the ESD generator improvements for better accuracy and repeatability has been intense during the past decade (3–8). Some of the results of these works are reflected in the latest draft versions of IEC, as well as ANSI C-63.16 (9), ESD test standards, and we will review them briefly: Template for the Current Waveform A min/max window is prescribed for the contact discharge waveform. If we look at the present specifications, the tolerances are:

Output voltage ±5% Output current (first peak) ±15% Contact discharge rise time (first peak) 0.8 ns ±25% Output current at 30 ns (beginning of the main “hump” fall off) ±30% No tolerances are given for the air discharge, the assumption being that a generator capable of meeting the above template will deliver a correct air

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101

discharge waveform. Calibration is done with a 2- coaxial target (25, leadless, 51- resistors), matched to 50 via a conical coaxial adapter. The total insertion loss of the calibration jig, from target to oscilloscope input must be ≤ ±0.5 dB up to 1 GHz. The oscilloscope must have a minimum 2-GHz analog bandwidth, and be installed in a shielded enclosure, with the coaxial target mounted as a feed-through. However, although the tolerances have been severely tightened, probably close to the limits of what high-voltage components technology can achieve today, the uncertainty on the initial discharge spike is still significant. Let us assume two simulators, with tolerances set at their worst, for a 8-kV discharge:

Ipeak (Nom. 30 A) Rise time (Nom. 0.8 ns) dI /dt (Nom. 37.5 A/ns) Total departure from nominal Voltage induced per cm2 for a victim circuit located at 15 cm Total peak-to-peak deviation between the two generators:

Generator 1

Generator 2

−15% 25.5A +25% 1 ns 25.5 A/ns −3.3 dB 3.4 V/cm2

+15% 34.5 A −25% 0.6 ns 57.5 A/ns +3.7 dB 7.7 V/cm2 7 dB

Although both generators conform to the specifications, the test made with generator 2 will be 2.2 times more disturbing than with generator 1. If we compare this uncertainty, regarded as systematic, nonrandom instrument error, to the typical error budget of a radiated EMC test, we find radiated EMC instrument error at about 3 dB (one instrument). Therefore, instrumentwise, an ESD test has a mediocre score on uncertainty, yet not much worse than an ordinary radiated EMC test. Figures 4.7 and 4.8 show two modern ESD simulators conforming to the IEC standard. As of 2008, about eight manufacturers worldwide offer ESD generators that conform to IEC, with various hardware options. The one in Fig. 4.7 is made by Teseq (ex Schaffner). It is extremely handy, battery-operated, easy to hand carry on a plane for short-notice trips, and is rated up to 16 kV (30 kV for the NSG437 model). Its discharge probe is strictly based on the IEC prescription. The one in Figure 4.8 is the MiniZap, by Keytek. It has been the workhorse of many test labs and EMC specialists for more than 15 years, being constantly improved. It also has options of several possible discharge head adaptors, to enhance either the E or H field. Transient Electromagnetic Field During Initial Spike At the very instant of contact closure, the HV side of the relay and associated hardware generate locally a transient E field. The way this field is distributed and the corresponding

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Chapter 4 ESD Diagnostics and Testing

Figure 4.7 Example of commercial ESD generator: TESEQ//SCHAFFNER NSG 435. The gun is shown with its demountable elements: battery pack, pointed and ball discharge tips, mounting plate for fixed stand, and external power supply.

Figure 4.8 The KEYTEK MiniZap. The HV relay has guaranteed 2 million operations at full current. There is an option of ultra-short 0.4-ns rise time for low-voltage discharges, per ANSI C.63– 16.

4.1. ESD Simulators: How They Work

103

charge displacement current are very different from the actual human hand/metal event (Fig. 4.9). The reason can be understood by comparing the geometry of an actual hand/metal event with that of the ESD simulator front end. With the actual event, the air gap breakdown is equivalent to an ultrafast switch closing the HV circuit exactly at the point of contact. The “hot” side of the circuit is the metallic tip of the handheld object. In contrast, the switch of an ESD gun is located at 10–15 cm from the contact tip. The right-hand part of the discharge network is at the target (EUT surface) potential, while the “hot” side is on the left side of the yet-open switch. The gun-to-target stray capacitance as well as E-field distribution are different. This distribution of the E-field lines is also dependent on the hardware design, shape, and dimensions of the gun head, which include the exact location of the discharge resistor. This introduces an additional uncertainty in the test results from different guns discharging on the same EUT. A “round-robin” test performed in 2006–2007 at the request of the IEC Technical Committee has confirmed that not

Actual

Simulated

Rd E field

HV 330 Ω Discharge head

EUT surface

Figure 4.9 Simulated vs. actual hand-metal transient field: the geometry of the initial spike artificial generation (right) is quite different from the actual phenomenon (left).

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only the EUT response to the precursor radiated coupling is not the same with an artificial contact discharge than with an actual human ESD, but it also varies between several IEC-compliant simulators (3). This variation, for the same EUT error rate correspondes to differences of several kilovolts in the HV setting. The problem cannot be controlled by the current calibration since the coaxial target mount is by nature insensitive to the radiation coupling (4). Attempts made to shield the HV head switch to prevent its spurious radiation resulted in unacceptable alteration of the rise time, due to the added capacitance. In fact, the point is not to eliminate this field but to render it more close to the “standard” hand and object phenomenon in a way that all simulators would replicate. One key improvement, for instance, could be to relocate the switch very close to the contact point. Problems with Steepness of Initial Spike The poor repeatability of the air discharge has been eliminated by the clean and fast closing of a relay. But in some cases, this fast relay was found to be too fast, closing in 100 ps, that is, 3–10 times faster than the fastest hand/metal discharge. As a result, the intended and spurious effects of the initial spike, related to the dI /dt value, are exaggerated, and the EUT will be overtested [Fig. 4.10 and (5)]. Many manufacturers have tried hardware solutions to overcome this problem, which in fact is linked with that of the constant rise time, as will be seen in the next section. The falling slope of the spike also raises some suspicion, as it is not specified in the IEC calibration. However, attempts to compare the results of modified, controlled fall time ESD guns with unmodified ones were not strongly conclusive, and this topic has not been incorporated in the latest simulator requirements. Problems with Constant Rise Time With the ESD generator in contact discharge, the rise time of the first spike is dictated by the relay closure and associated R,L,C elements; in other words, the rise time is constant. Measurements of low voltage, quasi-natural ESD with small gap length and fast approach 12 simulator A simulator C simulator B

20

10 E-field kV/m

Current derivative [A/ns]

40

0 20

A

8

B

6

C

4

D

2 −40

0

1

5 Time [ns]

10

0

0

2

4

8

Time [ns]

Figure 4.10 Variations in current derivative and E field at 0.10 m, from several IEC-compliant generators and 5-kV discharge [from Rhoades (5) and Pommerenke (6)]. All these different dI /dt and field waveforms correlated with different run/fail thresholds for the same EUT.

4.1. ESD Simulators: How They Work

105

(11) have shown that discharges below 3 kV have very short rise times. For instance (Fig. 4.11), a fast 1-kV metal-to-metal discharge exhibits initial current rise <0.5 ns, the rise time being more or less linear with voltage in this submillimeter region. Since most ESD-induced malfunctions are related to the current (or field) derivative, it appears that a 1-kV hand/metal ESD with 0.3 ns rise time can be as threatening as 4 kV with 1.2 ns rise time. The two induced disturbances have the same amplitude, the difference being in their duration. Considering that in a given environment, there are statistically much more 1-kV discharges than 4-kV ones, this would lead to an ESD test plan imposing more error-free discharges at lower levels (see Error per pulse criteria, Section 4.7).

4.1.4. Generators with Different Networks, Very High Voltage and Field Enhancement Accessories A certain number of applications such as automobile electronics, aircraft and aerospace equipment, and electroexplosive devices require different RC Rise time vs. voltage for low voltage discharge (small gap and fast approach)

tr (ns)

2 1.5 1 0.5 1

2

3

4

5

kVESD (Aver. of pos. and neg. discharges) Discharge current I (3 kV) I (2 kV) I (1 kV)

t Induced PCB voltage Vi 0.4 ns

0.8 ns

1.2 ns t

Figure 4.11 Rise time with low-voltage, small gap discharges.

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Chapter 4 ESD Diagnostics and Testing

networks. Most modern IEC-type simulators have such options, offered as user-replaceable modules (Fig. 4.12, 4.13). In this case the specifc current and waveforms can be different from the original IEC definition. Ultrahigh voltage ESD generators are required for automobile and airborne equipment tests. Because of the physical nature of their environment (high static buildup in a confined space, isolated from ground) and the life-threatening consequences of some ESD-induced failures, test voltages higher than maximum severity class of the IEC or ANSI standards are required. The most common example is the ISO 10605 or SAE J1113-13, which require 25 kV immunity for safety-critical automotive systems such as braking/ABS, airbags, and door locks. In order to have some design margin for prototype testing and investigations, manufacturers offer in general up to 30 kV capability

(a)

(b)

Figure 4.12 ESD generator with very high voltage, mostly used in automobile and airborne applications. It has a quick self-check option, (a) automatic residual charge dumper and (b) convenient plug-in discharge networks. (Courtesy of Schloder.)

4.1. ESD Simulators: How They Work Discharge Network (DN)

107

Relay Module (RM)

ESD3000

Batteries standard type AA

Sharp Tip for contact discharge (CD) Rounded Tip for air discharge (AD) 30 mm Tip Electrode for (AD) V > 16 kV

Figure 4.13 Example of easily interchangeable discharge modules. (Courtesy of EMC Partner.)

Figure 4.14 A 30-kV ESD generator testing a portion of an automobile harness. (Courtesy of Schaffner/Teseq.)

(Fig 4.14). Although 30 kV is just twice the highest IEC test value (severity 4), such simulators must be used with some precautions. At 30 kV, the discharge electrode starts exhibiting ionization and corona effects about 5–10 cm around the probe tip. Even though a 30-kV/100 ns duration pulse is not lethal, it is an unpleasant experience and the test people should as much as possible operate the generator in remote control mode (Fig 4.15), once the preliminary adjustments are completed.

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Figure 4.15 Air-discharge generator with fully automated robotic operation, eliminating the error-prone manual handling. (Courtesy of Schaffner/Teseq.)

4.1.5. Special Relays Required for ESD Simulators Either for the ESD guns implementing the direct contact (no-arc) principle, or for the component ESD testers of Section 4.3, a special relay is needed to switch the capacitor into discharging mode. Although it looks trivial on the basic schematic, this relay or switch is key to a well-reproducible waveform, in the direct contact, “no-arc” discharge. This relay has to withstand the full charging voltage and operate the transfer without bouncing. Also, even though the direct contact technique was deemed to eliminate the arc problem, nothing is free in physics, and there is still an arc, but it now occurs inside the relay. Until time comes where solid-state switches with subnanosecond transition time will handle 20 kV, the only way is to use high-voltage relays with minimum arcing and bouncing. A former study (12) found that, after all, rather than eliminating the arc, a well-controlled triggered spark gap (manufacturer EG & G) can give also an acceptable waveform, but the range of possible voltages is limited to the specific type of gap used. Hopefully, modern industry has become an important consumer of HV switches, for applications such as defibrillators, electrosurgery, magnetic resonance imagers, RF antenna switching, and the like so the limited markets for ESD generators have benefited from this high demand. For instance, mercury relays like those made by Magnecraft/USA can be successfully used up to 10 kV or more. The Paschen law (see Appendix C) indicates that, in a high degree of vaccum, breakdown voltage rises to much higher values than in air at normal pressure, with the added benefit of a long contact lifetime, since the arc occurs in an oxygen-free space. Accordingly, high-voltage relays have been developed

4.2. Furniture Versus Personnel ESD Simulation

109

by manufacturers such as Kilovac, who offers hard vacuum, fast bounceless relays up to 15 kV. Above this voltage, vacuum relays tend to generate X rays, so relays with pressurized SF6 gas are used instead. The relay contacts are in a sealed bulb with a high-pressure gas that can withstand more than 20 kV/mm of gap (see Appendix C). These SF6 relays are “make-only” (no break). Simple, almost home-made ESD generators can be made using reed relay switches: Inexpensive models can be found with 1–2 kV continuous rating, but they can switch up to 6 kV in pulsed mode. Beyond this value they exhibit multiple arcing and ringing because of their parasitic capacitance. A primitive ESD generator can also be made with gas tube overvoltage protectors: They have fast switching times, but they trigger for only one given voltage, thus requiring several devices.

4.2. FURNITURE VERSUS PERSONNEL ESD SIMULATION Section 1.5 showed that furniture or large objects creates waveforms, hence frequency spectra and induced effects, that are very different from personnel ESD. While in the near-field region, the higher voltages of personnel ESD create a strong E-field transient but lower H field, furniture ESD by its low source resistance creates stronger H field. Because of the longer duration of the ringing wave, the induced voltage in exposed electronics can be more disturbing, especially with medium-speed circuits. One should not conclude that an equipment passing a furniture-type ESD test would be implicitly immune to personnel ESD, rendering this latter test needless. We have seen (Section 2.8) that furniture discharge is not feasible in all areas of the EUT, and that its lower voltages (always below 5 kV) do not permit arcing on many hidden or recessed areas. In addition, the super fast rise time of hand/metal personnel ESD creates intense E-field transients that are not replicated by furniture discharge. Having selected discharges with approximately identical probability of occurrence, the respective frequency spectra of personnel (direct hand/metal and air discharge) and furniture ESD are displayed in Figure 4.16. This comparison shows where furniture spectrum overrides the others. Therefore we can say that: • • •

A single test based on personnel ESD alone (Rd > few hundred ohms) may overestimate the equipment immunity to furniture ESD. A single test based on furniture ESD alone (Rd < 50 ) may overestimate the equipment immunity to personnel ESD. Although it simplifies testing, a trade-off discharge network with 330 resistance and approximately 2 μH of loop inductance does not replicate adequately the large oscillatory current of furniture ESD.

This leads to the conclusion that, for the time being, a fully representative test program should include both personnel and furniture ESD (8). If the objective

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Chapter 4 ESD Diagnostics and Testing

100 300 1 MHz

10

Frequency 3 10 30

10

10

B

C

3

A/MHz

100 300 1 GHz 3

3

1

1

.3

.3

.1

.1

A

.03

.03

.01

.01

.003

.003

.001

.001

10 kHz 30

100 300 1 MHz

3 10 30 Frequency 40 A

30 A

100 300 1 GHz 3

A/MHz

10 kHz 30

10

40 A

16 A

30 ns 0.7-1ns

60 ns

A New IEC contact discharge 8 kV

≥ 20 ns

60 ns

B Air discharge 15 kV

Fo ≅ 20 MHz C Furniture discharge 2 kV

Figure 4.16 Waveforms and frequency spectra of 3 test discharges, representing severe ESD events having approximately the same probability; between 15 and 60 MHz, the furniture-type spectrum overrides the others.

of a product manufacturer is merely to design a product that passes the tests and complies with the standard requirements for getting a CE (Communaut´e Europ´eenne) mark or other approval, the personnel ESD test is a sufficient shelter. But this includes the risk of having a compliant product that will sometimes fail in the field. Simulators capable of reproducing furniture (as well as personnel) ESD have been commercially available. The EMC engineers at the IBM R&D laboratory in Kingston had developed for their own use the ESD tool 5800 (also made by Andy Hish). It performed very efficient and repeatable tests (13). Commercial versions were marketed after 1990 by ElectroMetrics and by Keytek Corp. but not widely used. The essential features of this tester are shown on Figure 4.17.

0.30 m

0.50 m

4.2. Furniture Versus Personnel ESD Simulation

111

H.V. relay and discharge resistance

Relay coil control

C1

Base ref. plate

EUT i1 surface

HV C2

I2

EUT-to-gnd impedance

i1, C1 = gap capacitive current path i2, C2 = machine capacitive current path

Figure 4.17 Vane-type ESD simulator (13). The charges are evenly spread as surface charges, instead of concentrated in a “gun.”

One of its definite advantages belongs to the crossed-vanes structure, which ideally replicates the distributed capacitance of a human body, or large metal object, standing close to the EUT. Moreover, the capacitance of this X-shaped armature is insensitive to the presence of other nearby conductive objects. Another remarkable aspect is that this armature is coupled to the entire setup in a way that is very similar to an actual ESD, via two distributed capacitances: • •

The vane-to-EUT distributed capacitance, C1 , representing approximately 20 pF. The vane-to-ground capacitance, C2 (150 pF), of which the vane pedestal acts as the “hot” armature, the other armature being simply the simulator base, that is, the local ground plane.

This close-to-real capacitance arrangement eliminates the 2-m ground strap of the ESD gun. Paramount to the effective generation of a fast initial rise time, the HV switch—a 7-kV, mercury-wetted relay—is located exactly where an actual ESD would be arcing, thus solving the problem of the correct transient field generation (see discussion in Section 4.1.3.2). It is packaged in a small module

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Chapter 4 ESD Diagnostics and Testing

with the contact probe. This module can be equipped with a 15- (furniture) or 1800- (personnel) discharge resistor. A slotted bracket, by sliding on the vane wing, allows to adjust the module at the desired discharge height facing the EUT, without changing the distributed capacitances. And finally, indirect ESD was easily made by discharging the vane on its own base. Regrettably, because of its weight and size, this tester was rather bulky to install and required some practice to use, so the industry has been reluctant to adopt it. ECMA European Computers Manufactures Association and ANSI working groups, which recommended its use in the early versions of their ESD standard, have since abandoned this concept.

4.3. OTHER TYPES OF ESD SIMULATORS FOR COMPONENT TESTING Referring to the gun described by the IEC-61000-4-2, ESD Test standard, to our knowledge, there is no fundamental difference between the types of ESD simulators available on the market today for equipment testing. Differences lay principally in the RC networks required by specifications others than the IEC, the sophistication of the features and commodities offered (see list in Section 4.1), and the possibility or not to create a direct contact (no air gap) discharge. However, there is a category of ESD testers that is quite different in its realization: These testers are the simulators used to address component vulnerability per MIL-StD 883 or JEDEC/ESDA, for instance. The purpose is to subject a given ESD level to every possible pin combination of an integrated circuit (or eventually any ESD-sensitive component) (Fig. 4.18). These tools do not look any more like a handheld gun but rather as a workstation with a programmable module socket. The selected pin(s) and the test sequence can be semi- or fully automated. Discharges can be configured for HBM, and machine or charged device models. A more accurate test waveform (transmission line pulse) has been recently introduced. The test results can be visualized on a separate curve tracer or sometimes on a screen displaying the I,V curves of the stressed device, an overall bar chart printout (Fig. 4.19) On some models, like the one in Figure 4.20, the user can program complex test sequences. All these features may seem a luxury; however, simply look at a manufacturer who has to monitor regularly the ESD sensitivity of its products. Consider, for example, a 56-pin integrated circuit. Each pin must be tested, for instance, against all the other pins grounded together. That makes 56 tests times 2 polarities. And since what is looked at is a quality figure, a statistical distribution of the failure levels is necessary. Therefore, the voltage will be gradually increased from 500 to 4000 V, in 250-V steps. Let us assume also that we need to repeat each pulse 5 times. For the sole HBM, the total number of measurements to take, depending on the spread of the devices characteristics, will vary between:

4.3. Other Types of ESD Simulators for Component Testing

ESD injection contact

To V,I measure and read out

Test socket

Polarity reversal HV relay > 1 MΩ +/− HV supply 1500 Ω 5 kV minimum 100 pF − /+

Grounding contact

Programmed sequencing for driving injection pin and grounding pin

Figure 4.18 Principle of an automated ESD tester for components.

Voltage 1K

2K

3K

4K

5K

1

1

5

5

10

10

15

15

20

20

25

25

30

30

35

35

40 0

1K

2K

3K

4K

Pin #

Pin #

0

40 5K

Voltage

Figure 4.19 Example of a bar chart printout from an automated ESD IC tester (Hartley AutoZap).

113

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Figure 4.20 Example of a modern ESD test station for components evaluation (Keytek ZapMaster). It accepts uncanned chips and packaged ICs upto 768 pins. Human body (HBM) and machine (MM) discharge models can be selected. Advanced design prevents spurious non-ESD effects, like trailing edge of the SF6 high-voltage relay. It provides full pretest and post-test status report.

56 × 2 × 5 = 560 for those devices failing after the first voltage step 56 × 2 × 5 × (4000 − 500)/250 = 7840 for those devices that resist up to 4000 V It is of course out of the question to have these tests done manually.

4.4. ESD TEST SETUP—DIRECT AND INDIRECT ESD The following sections describe the details of the test installation. When there are variations between what is recommended here and what some of the principal specifications require, this will be mentionned. The basic setup for ESD testing is shown on Figure 4.21. The equipment under test (EUT) is normally installed above a ground reference plane (GRP), at a height dictated by its wheels, feet, casters, and the like. By default, 5- to 10-cm insulating spacers can be used. The return conductor (preferably a strap) of the generator is grounded to this reference plane. For EUT with metal housing, the test is made by direct discharges (D-ESD), that is, the discharges are applied to all points of the EUT likely to be touched by personnel and, eventually, furniture. For EUT with plastic housing, the test is made by indirect discharges (I-ESD) on a nearby horizontal or vertical metal plate. Several variations of this basic installation will be described, especially when the EUT housing is not entirely metallic.

4.4. ESD Test Setup—Direct and Indirect ESD

115

10 Ω to several kΩ Adjustable up to 25 kV Rd EUT

100 to 300 pF Ground return strap Safety ground

Test ground plane

Figure 4.21 Basic setup of an ESD test.

4.4.1. Ground Reference A GRP is of prime importance and must be present every time to stabilize the EUT-to-ground capacitance, thereby allowing repeatable testing. Without this plane, the return path of the discharges would be totally uncontrolled, shared between some undefined ground plane and the room/building grounding wires; thus the rise time and the spread of the return currents would differ, and the test results would not be reproducible from one setup to another. The GRP is the common reference for all the elements participating in the test: The generator, the EUT, the various accessories will be directly or indirectly referenced to the GRP. This plane can be made of a copper or aluminum plate or foil, which must extend at least 0.30 m around the EUT, or more, enough to widely encompass both the EUT (which can be a system of several units) and the simulator. A good rule of thumb is that the GRP boundaries shall exceed the EUT perimeter by a dimension equal to the EUT height. To avoid the GRP from raising up to an undefined potential after many successive discharges, possibly creating testing unacurracy or even shock hazard, the plane must be connected to the local ground terminal. This connection to the grounding network is regarded as an ordinary safety wire, having no importance for the high-frequency response of the test itself.

4.4.2. Direct Versus Indirect ESD The EUT-to-ground configuration can be more complex than the simple sketch of Figure 4.21. The EUT can be an upright, floor-standing machine, a table-top device, or eventually a wall-mounted device. It may have a metallic housing

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or a nonconductive one. The following recommendations address these different options, summarized in Figure 4.22. For Equipment with Metallic Housing (Direct ESD)

If floor standing, the equipment should stand over the GRP, as shown in the typical configuration of Figure 4.23. Regarding the height above this GRP, a default value of 10 cm is generally adopted, except when a fixed height above a conductive floor is defined by specific application constraints. If the EUT is a table-top equipment, most standards state that it should rest on a nonconductive table, and a horizontal coupling plane (HCP) be added to simulate the coupling with a metallic table (Fig. 4.24). A legitimate question arises: Since table-top devices can be used on metallic as well as nonmetallic desks and workbench, why select a wooden table, and then simulate a metallic desk by adding a sheet of metal? Why not use a metallic table from the start? The choice is not that simple; whether the EUT is metallic, as is the case here, or plastic, its coupling to the floor-level plane will be different whether it is resting on a metallic top or not. Deciding which configuration is the worst case for ESD is very speculative, as it depends on the internal design of the EUT and the I/O cable arrangement. Only a comparative test could identify the most vulnerable configuration, and this could vary with each EUT. So the standard setup of IEC or other industry specifications is a fair trade-off, given that it is easier to turn a wooden table into a metallic desk top than doing the reverse (see discussion on HCP in Section 4.4.3). Testing metallic and plastic table-top equipment with both a conductive and nonconductive table would seem extravagant, but experience has shown that

or

GRP

GRP Metal housing, floor standing

GRP

Metal housing, table top

VCP HCP

GRP Plastic housing, floor standing

GRP Plastic housing, table top

Extended GRP System test

Figure 4.22 Overview of various ESD test setup depending on types of machines.

4.4. ESD Test Setup—Direct and Indirect ESD wall at ≥ 1 m

Typical position for Direct ESD Safety ground wire

117

EUT

Typical position for Indirect ESD 0.1 m

VCP 470 kΩ

Power cables Signal cables

L=2m

> 0.5 m

Insulating stand-off 10 cm thick GRP

Figure 4.23 Test installation for floor standing equipment (per IEC or ANSI). For I-ESD, notice the horizontal position of the gun at the edge of the VCP.

depending on the orientation of PCBs inside the unit, the points of entry and internal routing of the cables, one configuration may be more critical than the other. As a suggestion to save test time, one can run a first exploratory test with both configurations and find out which one gives the weakest ESD fail levels. Then retain this setup for the rest of the testing. For Equipment with Plastic Housing (Indirect ESD)

If floor standing, the EUT will be installed on a ground plane, as for the previous case. However, since there are no or very few accessible metal parts for direct discharge, the test following procedure will apply: • •

Direct discharges on all eventually accessible metal parts. Indirect discharge by discharging the probe on vertical coupling plates (VCP), grounded via high value resistances to the GRP. Discharges will be made at 10 cm from each side of the EUT. (This 10-cm distance is deemed to represent the closest reasonable worst case where people will actually discharge on nearby metallic objects. However, for some specific products, another distance can be selected.)

For table-top equipment, the EUT will be installed on a nonconductive table, covered with the HCP. The height of the EUT above this plane is simply dictated by its feet or stand-offs. No incidental contact to the HCP should occur by protruding screws or metallic parts on the bottom of the EUT. This is usually taken

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Chapter 4 ESD Diagnostics and Testing Simulator position for discharges to the EUT

Simulator position for discharges to the VCP Safety earth conductor

0.1 m >0.5 m to next structure and walls

VCP Insulation 0.1 m HCP Simulator position for discharges to the HCP

HCP discharging resistors (2 × 470 KΩ)

Ground reference plane (GRP)

Keep ground strap >0.2 m from the EUT and its cables

Figure 4.24 Test installation for table-top equipment. During the test, the EUT may need to be relocated on the HCP (or the HCP cut to size) to achieve the 0.1-m distance from the edges.

care of by putting an insulating foil on top of the HCP. A VCP will be installed on the HCP, via an insulating stand. The following test procedure will apply: •

•

Direct discharge on any accessible metal part (switches, keys, screws, conductive elements of an otherwise plastic cover, etc.). This includes contact or arc, whichever comes first. Indirect discharge by discharging the probe on a VCP (as done above), and on the table-top HCP, following a perimeter about 10 cm from the EUT sides.

4.4.3. Roles of the HCP and VCP With I-ESD, the test aims at reproducing the scenario where a charged person is touching a metallic structure (furniture, other equipment or appliance, door or window frame, etc.), very close to the nonmetallic EUT (see Chapter 2). For replicating the case where the EUT is resting on a metallic desktop, the gun will be discharged on the edge of a metal plate (the HCP). All the same, to simulate the case where the EUT would be close to a large vertical object, the gun will be discharged on the edge of a 0.50 × 0.50 m vertical coupling plate (VCP). Although this seems a sound approach, several issues are not clearly addressed or resolved in IEC and major testing standards:

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1. The connection of the HCP (or VCP) to the ground reference plane (GRP) is treated differently depending on the specification. The IEC demands that they be virtually isolated from the GRP via two 470-k resistors, acting only as a “soft” static sink for discharging the plate a few milliseconds after each discharge. At the moment of the discharge, this makes the VCP (or HCP) jump abruptly to the tip voltage, creating locally a strong E-field transient, hence a capacitive coupling to the EUT circuits (a plastic housing offers no Faraday shielding). But this is missing the large VCP-to-ground discharge current that would occur with a true grounded structure, radiating a correspondingly high magnetic field. A wise approach, at least during development time, is to arrange a test with the VCP (or HCP) alternatively floated via the 470 k, then directly grounded, and concentrate on the worst susceptible configuration. 2. How should the VCP be located with respect to the actual EUT target zone? Intuitively, and this is what the IEC document is suggesting, one would align the VCP center to face target zone. In fact, theory and experiments (14) have shown that the maximum current density, hence field concentration, is near the edges of the VCP. 3. The VCP and HCP are required regardless of nonmetallic or metallic type of EUT. There seems to be not much sense in discharging on a metal plate at 10 cm from an EUT, while this latter is already in a metallic housing, submitted to the much more threatening direct discharges. However, some rare situations (see Section 4.5.1) can justify this demand. 4. For EUTs with a very low height-to-perimeter form factor, such as 35 × 35 cm device only 5–6 cm high (e.g., a DVD player), there is no sense exciting the VCP since the E-field coupling from the HCP will be a much more severe threat. So, except for “going by the book,” ESD investigation and troubleshooting can be made with the HCP alone. 5. The E and H fields generated by the gun’s HV circuitry vary significantly with its tilt angle on the HCP (or VCP). With guns held vertically, Pommerenke and Frei (14) measured 2/1 H -field and up to 6/1 E-field variations between different guns. These ratios reduce to 1.25/1 if the gun is held co-planar with the HCP. On the other hand, the strongest coupling with the initial spike occurs with the gun held vertical. Thus, the dilemna was the following: •

•

The larger amplitude (vertical position) reproduces better the worst-case field near a human/metal discharge, but it aggravates the differences between various simulators. Differences are reduced with the gun held horizontally, but at the expense of a lesser field value.

Waiting for a better definition of simulator characterization, and at the risk of some undertesting, the second choice is retained in the IEC standard.

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4.4.4. Grounding the Simulator and the EUT The EUT should be grounded through its normal grounding conductor, to the ground terminal of the power outlet. If the EUT has no ground conductor (class II equipment) or is battery operated, it will then be ungrounded. In no circumstances should the EUT be directly grounded to the GRP, unless this is the way it would be normally installed in the field, as, for instance, airborne or automobile equipment. The return path for ESD pulse to the generator must be a large strap, its recommended length being 2 m (see discussion in Section 4.1.3 about how of this length can affect the rise time), bonded to the GRP via a “C” clamp or similar. This dimension is a trade-off between the need of a limited length with less inductance, and a sufficent slack for being able to move the gun around the EUT. This wire or strap must have an insulating jacket to prevent other uncontrolled ground loops. The simulator should not be grounded to the EUT frame or the table-top HCP, except for some exploratory diagnostics. Note This deviates from some older test methods, which showed in certain cases the simulator being grounded to the EUT itself. This is questionable since, in real life, charged people will have their feet on the ground, and not on the EUT cabinet. In addition, grounding the simulator to the EUT frame will decrease, or even nullify, the electric field gradient between the lower part of the EUT (especially the bottom plate) and the ground plane. This field change is important in the possible coupling to I/O cables near their entry points. When the EUT has no connection to ground (battery-operated system, completely floating power sytem, etc.), there must be a way to discharge the floating metal parts after each discharge. This can be made by touching them with a grounded wire loaded by a few 100-k resistors. Some ESD gun manufacturers provide a bleeder network attached to the discharge tip, which systematically remove the discharge after each shot.

4.4.5. External Cables and System Configuration Very often, the ESD test may have to replicate the conditions of a system configuration. There can be several reasons for this: For instance, the EUT may be one unit of a multiple box set in which case the vulnerability of the whole system must be evaluated by testing one box after the other. Alternatively, the EUT may be designed as stand-alone, “attachable” to several types of peripherals or ancillary equipment. In this case, the peripheral devices must be connected to the EUT, even if they are not themselves being tested. However, in the latter, it is necessary that the units not being tested have an ESD level consistent with the test objective (see Section 5.7).

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For a system configuration, the whole system must be installed over the GRP. If this is not practical, one ground plane per box can be used, provided that these planes are interconnected by wide straps. All the external cables that can be connected to the EUT in its maximum configuration should be in place and be laid out in a typical installation arrangement. To avoid too much variance in results due to different heights, they should be laid at a constant, repeatable height above the ground plane. Unless other heights are dictated by specific applications, a height of 10 cm, using wooden or plastic spacers, is a good average.

4.5. ESD TEST ROUTINE AND DISCHARGE PROCEDURES 4.5.1. Preparation of EUT for Test Readiness 1. Determine a clear, indisputable malfunction status that can be recognized without the need of an external oscilloscope, data-logger, and the like such as hard-error, wrong readout, inadvertent reset, alarm, on power down. This point is very important. No external ancillary equipment should be used to diagnose a fault condition because the very presence of additional probes and cables, and the monitoring device itself, can cause the EUT to fail at lower levels and give wrong test results. Very possibly, the oscillscope or data-logger can itself be disturbed by the ESD and give misleading information. The only exception would be by using a fiber-optic link to detect a change of state of some critical signals; but this assumes the EUT is already fitted with such diagnostic commodities. Therefore, if the EUT is a programmable device, it may be useful to develop a software routine that: • •

Exercises continuously all EUT operations, in closed loops without requiring an operator intervention. Indicates clearly by a printout, display message, alarm, buzzer, indicator light, dead display, locked keyboard, and the like that a fault has occurred.

With a large computer-based system, it would be sound to develop for all the transient immunity tests—not just ESD—a software that exercises every special-purpose routine, designed to operate in specific hardware areas. This will give a better efficiency for the hardware test program to approach a 100% probability of shooting in the worst sensitivity window, without running an excessively long test. It also facilitates the error diagnosis and faultly hardware location. It is not recommended to go to the extreme by trying to synchronize the ESD pulse rate with the EUT operation. Static discharges and machine cycles must remain two independent events (see Section 4.7).

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Chapter 4 ESD Diagnostics and Testing Type of equipment

YES

Metal covers on six sides ?

D-ESD only

NO

I-ESD (For instance : 4 – 16 kV for personnel ESD)

D-ESD • On all metallic touchable parts • On all arc-reachable parts

Figure 4.25 Decision chart for discharges mode. Notice that a D-ESD is practically always to be attempted on a plastic-covered product because of the possibility of a few metallic targets.

2. Make a zoning by dividing each side of the equipment into approximately 0.1-m2 (30 cm × 30 cm) areas. Mark/code each ESD target area. Include signal cables and power cord entry areas. Determine if the discharges will be entirely direct (D-ESD), indirect (I-ESD), or hybrid (Fig. 4.25). It may seem wasteful applying I-ESD on a 6-sided metallic housing and, indeed, it generally proves to be useless, whereas the worst suspeptibility is found by D-ESD. However, there are rare cases where an I-ESD test with a metallic EUT reveals a weaker failure level than a direct discharge on the envelope: This happens when the EUT has much smaller dimensions than the 0.50 m × 0.50 m of the VCP, and is equipped with unshielded (or poorly shielded) external cables. In this specific case, the cable exposure to ESD field is stronger with the VCP than with the direct discharge on the EUT.

4.5.2. Application of the Discharges 1. Set the ESD level at about 3 kV (for a personnel-type discharge) or other determined value, depending on whether it is an investigation or a quality control (QC) test.‡ ‡ Some standards (e.g., IEC) recommend that, with D-ESD, the test be started only at the required immunity level, without passing by the lower levels, but this is risky. Even with D-ESD, EUTs can exhibit the following response: Assume Vs is the specification level: For voltages Vi < Vs , the discharge current follows a certain path on the EUT, eventually inside. For levels > Vi , and up to Vn , internal arcings can take place, giving way to a different current path that can be more, but sometimes less, disturbing than with a test at Vi . By testing only at the highest level, one could miss this response. It is safer testing at ALL inferior levels.

4.5. ESD Test Routine and Discharge Procedures Metal spring

Conductive paint

Metallic name plate/logo

Magnetic head LCD module with metal rim

123

Metallic connector PC board

Metallic card frame Targets : • Accessible metal parts connected to internal conductive parts • Floating metal parts (no arc, but E-field coupling inside) • Internal parts reachable by arc

Figure 4.26 Fictitious plastic equipment showing potential D-ESD targets.

2. Zap each of the coded areas marked in the preliminary step. If this area includes switches, keys, indicators, connectors, screws, rivets, and the like, apply the discharge on those points. Apply also the discharge on the seams, slots, display edges, and any protruding shape, angle, or surface discontinuity existing in the area. Otherwise, simply apply the discharge in the middle of the coded area. If the EUT housing is plastic, perform indirect ESD, applied on the edge of the HCP and of the VCP, at 10 cm from the target face. However, a direct discharge should still be tried on screws, rivets, decorative trims, and the like as suggested in Figure 4.26. There can be EUT areas that are accessible only under specific circumstances, such as: • •

Parts touched by end user during service (batteries, cassettes, ink cartridges., etc) I/O connectors not equipped with their cables.

Since some of these service operations are performed “Power On”, the corresponding zones should be tested with a minimum requirement of no damage or no permanent change of conditions (loss of data, alarm, etc.).§ § Some

standards (IEC) recommend that these areas be exempted from the test. In our opinion, this exemption is not justified since these operations are often done with the equipment being simply in stand-by. For instance, metallic receptacles, even with recessed female contacts, can still be reached by a frontal air discharge before the finger even touches the peripheral shell.

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3. For those targets that cannot be touched by direct contact (pointed tip), use the air discharge. 4. Repeat the discharges until the prescribed number have been applied without unacceptable EUT response. If no minimum number of pulses is prescribed, use 50 as a default, in each polarity. However, the minimum number of pulses to guarantee the test depends on the complexity of the EUT operations (see Fig. 4.30). Section 4.7 discusses this problem of the number of trials more in detail. 5. Repeat step 4 for all coded areas and record which ones failed. If none failed, increase the level by 1 kV and rerun the test. Above 8 kV, most specifications recommend changing from contact discharge (pointed tip) to air discharge (round tip). 6. For each failed area, decrease the ESD level to find the go/no-go threshold, and record it. 7. Starting with the weakest spot, apply EMI-hardening methods, described in Chapter 5, to meet 8 kV, 15 kV, or other objective. Many simulators have a selectable repetition rate. This is a useful feature because manually applying 50 or more discharges times n points in a single-shot mode would be tedious. Also, for a first check with low ESD voltage, a quick sweep of all the target zones with accelerated pulse rate such as 20 or 50 pulses/second can give a rough estimate of the immunity, saving a lot of time. This first scan, intuitively thought of as a quick way to detect the weak spots, is in fact a way to eliminate the nonweak spots, by using an accelerated pulse rate. Within 1 min (at 50 pulses/second), 3000 discharges have been injected, giving a decent confidence that the selected area is fairly immune. Then, and only then, are the areas that did not pass this first exam candidates for a deeper search of the weakest spots (quite often, the designer assisted by an EMC engineer may have guessed where the weak spots are). These will be submitted to the number of specified discharges. As soon as a failure level seems to have been reached, the repetition rate must be slowed down sufficiently for allowing EUT software recoveries (if it has such features); otherwise, it could be stuck in a repetitive error mode, misrepresentative of real ESD situations where there are never several ESD events per second. Another phenomenon may occur that also fouls up the test if too fast a discharge rate is selected. Some circuits have very high input resistance; if, in addition, their 0-V reference is floating, the ESD bleed path to ground can be rather intricate, with an R,C discharge time constant that can reach tens of milliseconds. This means that the first ESD may induce a voltage pulse that is not sufficient to upset the device, but will leave a residual voltage that has not dissipated when the next pulse comes. A new residual voltage will add up to the previous one, and so on. After a certain number of pulses, the stack gradually reaches the upset level, causing a malfunction that is mistaken as a “true” ESD

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125

failure. The typical symptom in this case is an EUT that is insensitive to the first discharges, but will fail regularly after the same number of pulses. Therefore, because of the two possible EUT responses mentioned above, it is a safe practice to check, by slowing down the repetition rate, whether the ‘‘fail” level is correlated with the pulse rate. For the test validity, what is important is the minimum number of pulses to apply, not their repetition rate. To help document the test results in an orderly manner, a test log form is suggested in Figure 4.27. It will allow one to keep an accurate track of the failing zones, and record the fixes that worked and those that did not. Too often, this is neglected and people have to “reinvent the wheel” at every test. A dual indication “RUN/FAIL” is also recommended to show the level at which the EUT undoubtedly meets the criteria and the level at which it fails.

4.6. NO ERROR/NO DAMAGE CONCEPT: THE SEVERAL LAYERS OF SEVERITY Like any surge-type test, testing for ESD involves threshold criteria. Before testing, the designers of the EUT as well as the test people must clearly define what is to be considered a failure. Too often, statements are made like: Our system has been tested up to 8-kV ESD. Does this mean: 1. The system does not exhibit ANY malfunction up to and including 8 kV? 2. The system does exhibit malfunction starting 8 kV? And if so: a. Were these malfunctions only soft, self-recovered errors? b. Were they hard errors? c. Were they solid damages, requiring component replacement? To clarify the situation, Figure 4.28 shows a three-limit ESD criterion. No voltages have been put on the scale since they will depend on the type of product and the type of market (15). For instance, in selecting the actual ESD test voltages one should consider: • • •

The likelihood of high human activity around this product The type of environment (controlled or uncontrolled RH, antistatic floor carpeting, etc.) The sensitivity of the user to a temporary malfunction or error; that is, how often a week or a month can a malfunction occur and be considered “tolerable” by the user? This can depend on the price range of the product, the seriousness of a temporary loss of data for the customer, and, finally, the general EMI immunity claimed in the product specifications.

Up to V1 , the lower level, no malfunction at all (recoverable or not) is tolerated. Consider, for instance, an airline reservation terminal that exhibits

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EUT:

Test Date: Prototype:

Test Type EUT

Pre production /Release test: Qc test:

Config. & Program Used:

Extern. Cables:

Simulator:

Checked:

Ω

R discharge: pF

C discharge:

Number of discharges / point: 5

Points of discharge 1

2

4 3

Point VESD Result +/− N° Direct/Ind. kV 1 to 4

Comments failure, mode, fixes...

EUT response: 1. Perform, not altered 2. Self-recoverable failure 3. No-recoverable failure, but no damage 4. Solid failure or permanent loss of data

Figure 4.27 Suggested ESD test log form.

Figure 4.28 Multilevel ESD test criteria.

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127

recoverable errors for 3-kV personnel ESD. The number of ESD events exceeding 3 kV in a counter type of environment is very high (Section 1.4). Even if the ESD-induced errors are automatically detected and the transaction is canceled, then retried, these operations take some time, and this terminal will spend too large a percentage of time recovering from errors, especially during the winter/spring season. From V1 to V2 , errors are permitted if they are “transparent” to the user, that is: They are self-corrected. They do not require a user intervention (halt–restart, data reentry, program reload, etc.) to restore normal operation. Above V2 and up to V3 “hard” errors are permitted; that is, this level is high enough to have a low probability of occurrence, which will not upset the user if an operator intervention is necessary to resume normal operation. However, it may be required that the error be visible to the user and not left unnoticed since it is not automatically corrected. No component damage is accepted, even those parts (like a fuse) that are replaceable by the client. No unsafe condition, leading to safety hazard, or expensive financial prejudice should result from this temporary upset. The IEC-suggested ESD test levels (see Chapter 3) are only indicative. In fact, each industry, government agency, or professional association decides the ESD immunity level for its respective products and applications. Examples of products/application categories are: Category A: Household Appliances and Entertaiment Devices

High human activity, uncontrolled environment. Aggravating factors (e.g., dust and friction with vacuum cleaners, cloth friction with dryers, etc.), but utilization is rather fault-tolerant as long as there is no solid damage. Category B: Office Products, Small Business and Point-of-Sale Equipment

High human activity, uncontrolled environment. RH can be as low as 15%, and any type of floor/carpet may be involved. Irritability factor quite high, but partial alteration of data not catastrophic because generally detectable by operator or user. Category C: Large Business Computers, Scientific or Medical Computing Centers, Large Systems Handling Critical Data (Banks, Government, etc.)

Such applications require high reliability, hence a low error rate (ER), but on the other hand the RH, floor treatment, and general environmental factors are fairly well controlled.

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Examples of coherent ESD test criteria, adapted from ANSI.C63-16 are given in Tables 4.2 and 4.3. These test levels correspond to discharges applied with a 330-/150-pF IEC or similar ESD simulator. Table 4.2 shows test levels for data processing equipment (officially designated as “information technology equipment,” or ITE). Two classes of severe environment are considered: Controlled environnement corresponds to: RH always> 20% and antistatic floor material Standard (but eventually severe) environment corresponds to RH being as low as 10% for some periods and synthetic carpet

Table 4.2 Suggested Personnel ESD Test Values for Information Technology Equipment Test Voltage

Criteria

Environment

Worst allowed EUT response at and above the indicated voltage

Controlled

Standard

2-kV contact

4-kV contact

Temporary loss of function or performance,

4-kV air 4-kV contact 8-kV air

8-kV air 8-kV contact 15-kV air

self-corrected Loss of function or performance, requiring operator intervention to be corrected. No permanent damage or loss of data

(Optional, Furniture Test) × (1 kV)

Self-corrected errors

×

Hard errors (no damage or loss of data)

(2 kV)

Table 4.3 Suggested Personnel ESD Test Values for Consumer Equipment Test Voltage Air Discharge (kV)

Criteria

Contact Discharge (kV)

5

3

10

6

15

7

(Worst allowed EUT response) Audible click, or visible short noise in video/audio No loss of function or performance, even self-corrected Momentary self-recoverable changes in user interface or equipment performance Operation suspended but can be restarted by normal user interface, without power OFF/ON

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129

Starting with the test levels, and doing a backward calculation based on the ESD current statistics, we can approximate that the corresponding accepted error rate (ER) for standard environment is: Less than 1.5 soft errors (autorecoverable) per shift for the worst-case periods of the year and in the worst possible installation Less than 0.3 hard error (no damage, but requiring operator action to be corrected) per shift Notice that no test levels are indicated for furniture discharge since this test is not widely practiced. If a furniture ESD test was also to be made, optional test levels are indicated that would guarantee an ER consistent with the accepted personnel ER of the standard environment. They are based on Simonic’s statistics (see Chapter 1) of furniture events, with a simulator having a 45- equivalent dynamic impedance. Another widely applied example of specific ESD test criteria is found in automobile electronic devices (Fig. 4.29). The influencing factors are multiple and may vary depending on manufacturers: 1. Environmental a. The device can be accessible only from inside the vehicle. b. The device can be accessible from outside as well. 2. Related to the condition of the vehicle: stopped with engine off, stopped with engine on, or running 3. Related to the benign to critical aspect of a malfunction a. Comfort equipment without direct impact on driveability b. Equipment providing information on driving and engine conditions c. Equipment influencing safety (steering, braking, air bag, driver seat control, etc.) In this latter case, the ESD test voltage can reach 25 kV.

4.7. THE ERROR PER DISCHARGE CONCEPT OR MULTIPLE-TRIALS APPROACH Not exclusive of, but rather complementary to, the severity layers, another concept, the error-per-discharge probability, has been recommended, although not widely used. Good rationales for this are explained in various studies (16–19). The basic principle is that the unwanted response (UR) of a machine is a probabilistic encounter between a randomly occurring event—the discharge—and the “sliding window” of the most vulnerable configurations of certain critical logic inputs (Fig. 4.30). The collision of these two random events cannot be predicted by a deterministic approach; therefore, any standard, such as IEC or others, requiring simply 10 discharges without errors is ill-fated. The unwritten, but implicit, statement that “if the EUT did not fail in 10 discharges,

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1. Test on vehicle, using car frame as reference

Device under test (DUT)

ESD gun

220 VAC/HV DC converter

DUT

ESD gun

Metal ground plane

2. Test on vehicle, using ground level reference

Figure 4.29 Example of ESD test setup for car on-board equipment (from ISO TC-22).

it will never fail” is about as sound as throwing a pair of dice 10 times and deciding that if you do not get two aces, you will never get two aces. Instead, the fail/no-fail decision must be based on a large enough number of independent trials, which the theory of probabilities helps us to define. The rationale is that the error sensitivity of a machine to ESD is almost never a step function. Figure 4.31 shows conceptually an “ideal” behavior (curve A), of a machine experiencing no error at all (regardless of how many pulses are applied) below a given ESD level, then making one error per pulse, that is, P (error/discharge) = 100% above that level.

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ESD Induced Glitches (a) 0

1

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1.5V VIL Threshold #2 for pulse width 1 ns VIL Threshold # 1 0.3V for pulse width ≥ 5 ns

1 ns 5 ns A

B

C

D

E

No Error: Amplitude too low No Error: Logic is in “HIGH” state No Error: Duration is too short for VIL # 1, and amplitude does not exceed VIL # 2 Error: Duration is ∠ logic rise time, but amplitude exceeds VIL # 2 Error: Amplitude and duration are above VIL # 1 (b)

Figure 4.30 (a) The ESD-induced transient is a random event that occurs anywhere vs. the sequence of logic operations and message formats of the machine. A minimum number of discharges is necessasry to explore the worst-case coincidences of the ESD transient with certain patterns of logic transitions. (b) In addition, to cause a logic error, the glitch amplitude and duration must exceed certain values (fictitious example shown for a 3.5-ns logic pulse train).

By comparison, the behavior of an actual machine (curve B) is plotted as the number of errors per ESD event, which is less than, or equal to, unity since in fact: Number of errors per ESD pulse =

1 Number of pulses to cause an error

This number is recorded versus the ESD voltage applied by the simulator. Due to the random occurrence of the ESD event versus the operations of the

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Chapter 4 ESD Diagnostics and Testing Number of 1 discharges to cause one error

Errors/Discharge

1 10−1

101

10−2

B

102 A

10−3

103

10−4 2

4

6

8 10 VESD (kV)

12

14

16

104

Figure 4.31 Concept of error per pulse: the behavior of a machine during ESD test is not a step function (a), but a steep slope like (b) due to the random occurrence of ESD pulses vs. logic operations.

EUT, the error/pulse concept allows the replacement of the go/no-go concept with a better approach. The following assumptions are made: •

•

• •

The result of each trial (an ESD pulse) is independent from the previous one: Chances of hit-or-miss are the same for each trial, that is, the EUT has no “memory” of the former events. The stimulus of each event is received exactly the same way by the EUT: This assumption is not totally true since an ESD test carries substantial uncertainties, but we will accept it. The ocurrence of an UR to an ESD stimuli is of random nature for logic errors only. Component damage is practically never related to a “high” or “low” status of a logic input or to a byte pattern but to the coupled voltage and current exceeding the safe limits of the component. Therefore, the URs, which are addressed here, are exclusively logic errors.

A 100% confidence that no error will occur for a given ESD level would require an infinite number of trials. Hopefully, probability calculations for large sample sizes can help us, in several ways: •

It is generally sufficient, for ESD-related errors, to guarantee that the machine will not suffer more than Nr errors per day (or shift) or per week; such a figure is application-dependent and can be established by the product manager as being what the users can tolerate.

4.7. The Error PER Discharge Concept or Multiple-Trials Approach •

133

This number Nr will be confronted with the number of ESD events per shift exceeding a given voltage, such as in field conditions: Number of errors/shift

= P (Error, V ) × N (EventV ) per shift

(4.1)

with P (Error,V ) = Probability that the machine will make an error, given a discharge voltage V N (Event ≥ V ) = Number of ESD events/shift that will equal or exceed V One can derive such criteria that, for an ESD test, Error rate at given levelVESD =

Tolerable number of errors/shift Number of events/shift V

(4.2)

The probability of ESD events decreases continuously with increasing voltages. Inversely, the percent probability of error per pulse increases with increasing voltages (Fig. 4.32). Unfortunately, the EUT error curve is not known by the designer and has to be approached by a sufficient number of trials. Probability theory tells us that to guarantee no default within N occurrences, the number of trials has to be much greater than N . How much greater depends on the degree of confidence that is desired. For instance, to guarantee less than one failure in 50 occurrences, with a 95% confidence level, a minimum of 150 trials without error is necessary. The residual risk, then, is twofold: 1. Accepting a machine that should have been rejected, that is, number of trials was too low (type 2 decision error) 2. Rejecting a machine that made one error but could have been accepted (type 1 decision error) In this case, the escalation strategy (given as informative annex in recent drafts of IEC and ANSI standards) allows for one error, provided an additional number of zero-error trials be performed. Rather than any arbitrary number of discharges imposed by a “fits-all” clause, this approach is personalized to the application, the market, and its environment. In addition, although a certain percentage of risk remains, a substantial margin is inherent to the method: •

•

The ESD event statistics (see Chapter 6) selected were for the worst case of a given class of the environment. Actually, the lower RH does not exist 100% of the time nor for 100% of the installed equipments. The IEC type of test systematically simulates a hand/metal type of discharge. Except for specific cases where the equipment is always touched first with a tool, a coin, or a key, the handheld sharp object represents only a fraction of the total number of ESD events.

Chapter 4 ESD Diagnostics and Testing

1

0.1

0.1 Confidence interval

0.01

0.01

Nevents

0.001

NER

2

0.001

Machine Response N Errors/pulse

Number of ESD events/shift (8 hr) busy office uncontrolled RH and floor-type worst season

134

4

6 8 10 12 Vi VESD (kV) expressed as simulator voltage For each given ESD level Vi, the probable machine error/shift is equal to : Nev × NER

Figure 4.32 Example of combined curves for ESD event rate and machine error curve.

4.7.1. Practical Application of the Error per Pulse Concept An example will describe how the error rate can be handled: Figure 4.33 shows a histogram of personnel ESD for the worst-case months (RH% = 15–20) compiled after Simonic data (see Section 1.4.1). Although the ESD events were given in amperes, they have been translated into an equivalent IEC simulator voltage assuming a uniform impedance of 300 . This will allow obtaining the results directly in the test levels. Assume that the objective is to have less than 1 error/shift (5 errors/week) during the worst-case months and for the worst-case installations (synthetic carpet). The EUT error profile, in its initial state, has been plotted on curve A. For 7 kV with an IEC simulator, there is one error per shot. Decreasing to 4 kV, it takes, on average, 30 pulses to cause one error. For each 2-kV interval of the histogram, the corresponding error/pulse figure is multiplied by the number of events per shift, to come up with the number of errors per shift. The total amounts to 2 errors/shift, which is excessive. By default, one can assume that the slope of the error curve has nothing to do with the fixes (shields, decouplings, etc.) existing in the machine, but rather with the nature of the operations and messages performed by the EUT. Therefore, hardware improvements will not change this slope but merely shift the curve. For instance, curve B shows the same unit after certain ESD fixes. The total is now 0.65 error/shift, which is below the one error objective.

4.7. The Error PER Discharge Concept or Multiple-Trials Approach

1

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8

10

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0.3

A

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0.4 2

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12 10 VESD (kV)

Error/Pulse A before B after Improvement Improvement 0.015 0.1 1 1 1 1 1

Error rate of the EUT

Number of events per shift for RH = 15%–20 and worst environment

2

135

negligible 0.001 0.01 0.1 1 1 1

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0.001

16

Events/Shift for worstcase months 12 3 0.5 0.4 0.3 0.2 0.1 Total

Error/Shift A

B

0.18 0.3 0.5 0.4 0.3 0.3 0.1 2

neglig. 0.003 0.005 0.04 0.3 0.2 0.1 0.6

Figure 4.33 Application example of the error per pulse method.

Boxleitner (20, 21) has given very good examples of a comprehensive test plan, taking into account the increasing event rate with low-voltage ESD. A short excerpt of it is shown in Table 4.4.

4.7.2. ESD Test Plan with Cost-Effectiveness Constraints For mass production situations, it can be desirable optimizing the ESD test to avoid overtesting, hence unnecessary hardware costs. For instance, let us consider a low-cost personal computer, or similar microprocessor-based equipment, with manufacturing forecast of 100,000/ year over 3 years. Preliminary tests have shown that an additional $2 of hardware cost is needed to upgrade the ESD

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Table 4.4 Events

Example of Test Plan, Weighted by Increased Probabilty of Low-Voltage

Maximum Number of Test Voltage Number of Applied EUT Failures Corresponding (kV) Discharges Recoverable/Nonrecoverable Calculated Failure Rate 5 10 12.5 5

600 300 45 12

24/0 21/0 9/0 3/0

0.06/0.005 0.1/0.01 0.3/0.07 0.5/0.2

immunity from 6 to 7 kV and overcome a test uncertainty with the standard 10 discharges program. Therefore, the manufacturer is facing a potential expense (or savings) of $600,000 over 3 years. It is worthwhile to investigate an optimized test plan to decide what is really needed. A first approach for increasing the test efficiency consists in devising a deterministic—instead of random—test strategy (22). It appears generally that only very short time frames of the various program executions are actually vulnerable to ESD-induced glitches. For instance, more than 99% of the time the software-driven logic transactions inside the machine are in rather shake-proof states, with critical phases happening less than 1% of time. It seems interesting to develop a test software that would run repeatedly vulnerable program cycles, and a fast ESD repetition rate that would increase the chances to shoot in the worst susceptibility window. Some studies have even gone as far as suggesting to synchronize the ESD discharges with the principal clock frequencies of the EUT to reach a close to 10/10 “hit-the-mark” score. As attractive as they seem in theory, these approaches are confronted with some hard facts. It is true that creating a specific test software to emulate exclusively the vulnerable sequences is feasible, and this approach has been applied successfully with some products. But it has to be done over and over for each new product or new version of an existing one. This is upfront money to be spent before sales have actually started, which will only pay-off along the product life, so a financial analysis of the return-on-investment needs to be conducted. Next, synchronizing the ESD pulses with subnanosecond clock pulse edges is not an easy task, in practice: From the point of discharge to the susceptible circuit, there is a 30-ps/cm propagation delay of the field wavefront, that is, 0.3 ns for a 10-cm trip. Thus, for each discharge point the exact firing of the discharge should be adjusted for compensating this time lag. And finally, this technique is conflicting with the self-recovery routines: On one hand, forcing repetitive ESD pulses to reach the worst place at the worst moment is overkill, while at the same time a smart software in the machine is spending time correcting the errors. Another refinement, also described by Pratt and Davis (16) is more practical. It consists in assigning a weighting factor (0–100%) to each side or zone of the machine, to represent the percentage of ESD events that will occur at that position.

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137

The sum of all the weighting factors over all test points is 100%. Thus, parts of the machine that are less exposed than others will be given a lesser penalty. The merit of this method lies in the fact that it replaces the traditional single go/no-go voltage with a finer characterization of the EUT response. However, the search for machine error rate and position weighting can be delicate and is not the kind of iteration to be made during a manufacturing QC test. Therefore, the following is recommended: 1. At the end of the design stage, when the prototype is sufficiently representative of the final product, especially concerning the logic speeds, clock rates, architecture and sequence of the logic functions, interface protocols, and the like, a characterization of the EUT error curve will be made, taking into account: • Machine error rate over the complete voltage range, in 1- or 2-kV increments • Position weighting, if justified • ESD environmental weighting (controlled vs. uncontrolled RH, etc.) 2. Knowing the above, engineering tests will be pursued to see if the machine meets the maximum error/shift or error/month objective, and improvements will be made if necessary. 3. From then on, the routine QC test will not need to repeat the above but will simply check the average error rate at one voltage only. For instance, in our example of Fig. 4.33 if the simulator is set to 10 kV, the QC will ensure that it takes, on average, a minimum of 4 pulses to cause one error. As an added security, a sample check could be run to verify that, at 7 kV, the EUT makes less than1 error in 100 pulses (something that, relying on the IEC criteria, would have good chances to go undetected). This is acknowledging the fact that in real environments, there will be more 7-kV events than 10-kV ones, therefore, the machine exposure is greater. This also allows sample comparison and detects possible degradation after hardware changes. A clear effect of such a problem is that the slope of the error curve would not change, but its position will shift. The test procedure imposed by the QC must guarantee that the “average number of pulses to cause an error” is based on a sufficient number of trials (21). For instance, just doing 100 discharges without error is not enough to declare that the error rate is less than 1%. Such a 1% objective, with 95% confidence, requires a minimum of 300 discharges at the same point (Fig. 4.34).

4.8. ESD TEST DURING DESIGN AND DEVELOPMENT Given that ESD testing is very efficient and relatively easy to conduct, it can be applied to the machine as soon as an early prototype exists; and, furthermore, as soon as functional subassemblies exist. For instance, an early ESD test is easy to perform on a breadboard prototype using an indirect discharge setup.

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3 × 103

Number of test pulses

103

% 99 V: 95% V: 90% V:

300

100

30

10 10−3

3 × 10−3 0.01 0.03 0.1 0.3 Permissible failure rate (error/pulse)

Example:

1

To guarantee ≤ 0.03 error per discharge, with 95% confidence, a test program with a minimum of 100 discharges without failure is required

Figure 4.34 Required number of discharges to apply with zero faillure.

A most rewarding approach is to start an ESD immunity evalulation at the PCB level. Later on, when functional cards have been designed and the first run of prototype boards is available, the following is suggested: •

•

•

Identify the principal Printed Circuit Boards (PCBs) in the machine, that is, those that perform essential functions and constitute block diagrams in the machine architecture. Prepare each of those boards so they can be tested as stand-alone items. Identify few lines to be considered as “witnesses” of the card’s good condition (e.g., WATCHDOG, RESET, IRQ lines, etc.) and equip them with a LED soldered directly on the card, so that when everything is normal, the LED is ON (or OFF). Preferrably, provide a dc power source without the need of an external bench supply. The easiest way to do this is to merely attach an ordinary battery pack to the card with adhesive tape, and solder the terminals to the Vdc bus via ultrashort, twisted wires. Perform an I-ESD test of the board , as shown in Figure 4.35. The discharge is applied on a metal plane, the card being placed at a distance

4.8. ESD Test During Design and Development

Supply batteries

139

ESD gun ground strap

“C” clamp “Witness” LEDs

Insulating spacers Copper or aluminum foil 10 cm (4” ) typ.

Figure 4.35 Workbench mounting for early ESD testing of a PCB. The height h depends on the final configuration of the machine. It can be equaled to the average distance of the card from the bottom plate or the closest wall of the housing. By default, 5 cm (2 inches) can be used. The cable will be added later to check the immunity of the I/O interfaces. Discharges are made following a route around the card perimeter. One discharge point at each corner plus one midway is usually sufficient.

that is representative of the actual card-to-housing distance of the future machine. The test voltage depends on the criteria for the final product. If the product is planned with a plastic, nonconductive cabinet, the ESD voltage should be set as for the final product. If the machine will be a metal or metallized cabinet, a certain derating should be taken. This derating can be found by testing a similar machine or a mock-up (same size, identical card location) with and without covers, the difference in kilovolts between the two conditions is the derating. By default, a good rule of thumb is to test each stand-alone card for 6 kV. A machine equipped with cards that sustain that level will not be too difficult to harden up to 15 kV or more. This single card test probably represents some of the best invested time in the entire ESD strategy (perhaps even in the whole EMC strategy). It reveals PCB layout weaknesses (see Chapter 5) at a time when they are relatively easy to correct. Using the setup of Figure 4.35 makes it quite simple to identify weak spots and find the peculiarity of the layout in that area that causes such weakness. Nonetheless, by no means can we consider that zapping a bare PCB stripped of all its associated cables and surrounding hardware is a one-to-one anticipation of the actual machine behavior. •

Harden the I/O zones; this remains to be done when the card alone has been brought up to the desired level. A well-hardened card can still make

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errors if ESD-induced glitches enter by the connector pins (remember, the test done so far involved only the direct radiation pickup by the card). To this end, a typical length of flat cable, multipair cable, or any conductor that replicates the reality should be plugged on the card connector(s). Due to the localized nature of ESD, it is generally not necessary to put more than 1 or 2 m of cable (1 m of cable is already beyond the half-wave length for the typical ESD bandwidth). On its other end, the cable should be terminated with passive resistors simulating the actual impedance seen at this end. The test could be refined by connecting this cable to an exerciser that will actually reproduce the normal I/O transactions with the card. In that case, great caution must be taken to be sure that the part of the gear that is stressed is actually the card, and not the exerciser.

4.9. ESD FOR FIELD DIAGNOSTICS AND FORCED CRASH METHOD Transfer function theory states that any system can be viewed as a black box with input/output ports. To the degree that a system can be approximated as a two-port network, its transfer function can determined very conveniently by measuring its response to a step impulse. Just like there are many instances where one would use a small coin as a tool because no real screwdriver is available, the handy, easily carried ESD generator can be used as a quick, first check of the susceptibility of an equipment to almost any kind of EMI . A properly simulated ESD event can excite and reveal much more of the weaknesses of an equipment than its mere vulnerability to static discharges. Testing EMI susceptibility by traditional methods is a long and complex process. Although it cannot pretend to replace these conventional and mandatory compliance tests, the wideband field of an ESD flashes the equipment all at once, revealing many of the same weak spots that a true EMI test will explore. Furthermore, an ESD test is simple to run, hence ideally suited to on-site testing. Forced crash is a technique by which one decides that instead of waiting for a random, hard-to-catch problem to show up, he intentionally injects into the equipment a very fast transient pulse that broadly covers the frequency spectrum of any possible intermittent event, ESD or other. Very often, microprocessor-based devices experience random malfunctions once they are installed, even though they were tested compliant and declared good for shipment by the manufacturer QC department. These environmental problems quickly become exasperating because of their typically intermittent and inconsistent nature. Usually, after the first customer call, a field technician will check out the machine, run diagnostics, reinstall software programs, trim some settings, replace a couple of PCBs, and leave after a last, positive sanity check (needless to say, no malfuction occurred while the technician was there to see it). Back at the office, the technician in good faith will probably report an NTF (no trouble found). Of course, the problem recurs at the same unpredictable rate,

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141

correlated to nothing, or to so many things that no explanation seems possible. The customer asks for a higher level of assistance and the district field engineer comes to the rescue, and so on, until someone eventually calls an EMC specialist. Is the problem an ESD one? Maybe or maybe not. In any case, forcing an EMI failure with an ESD test applied on site is a powerful diagnostic tool and a very localized stimulus. It will be merciless in pinpointing hardware EMC deficiencies. Since the pulse is calibrated, progress can be quantified, and a susceptibility map can be drawn. This on-site procedure is rather similar to the ESD test in the lab, but there are some differences: You are not testing a development or premanufacturing unit with diagnostic tools, but a machine actually in service. Make sure that the test does not lead to a risk of serious material damage or even safety hazard. Try to inhibit temporarily any peripheral that could create such risk. 1. Install a temporary ground plane (a double-fold of kitchen foil will do) underneath the machine. This will stabilize the RF reference and improve the test repeatability, so that the results can be compared to typical immunity objectives. Do not try to ground the EUT to this plane since it is normally grounded by its power cord. Connect this ground plane to the next safety earthing (e.g., a power outlet ground terminal). 2. Using chalk or water-soluble pen, make a zone/coding on the EUT housing, as described in Section 4.5. 3. Establish a clear, indisputable “fail” criteria of the system, preferrably with the same symptoms as the problem that was detected by the user. 4. Ground the ESD gun to the reference plane. Set a low level, such as 2 kV, and zap every coded area, including switches, keys, screw heads, front panel edges, display edges, and the like. Do not forget the areas around connectors and cable entry ports. Start with at least 50 pulses of each polarity, in a repetitive mode (5 or 10 pulses/second). If the product is mainly plastic, apply I-ESD by discharging on a metal plate located about 10 cm (4 inches) from each EUT face. 5. Increase the level by 1-kV steps until you reach a fail level, or the ESD immunity objective plus a 1-kV margin, whichever comes first. 6. If failures are detected, come back to the failed area with a single-shot mode to allow for possible automatic recoveries. 7. Record and map the confirmed pass and fail areas. 8. For each failed area, lower the test voltage until reaching a sure no-fail level and document the results as suggested in the log form shown in Figure 4.27. Once repeatable pass/fail levels have been confidently determined for all areas, what remains is to inspect and critique the hardware immediately behind each failing area, and especially nearby cables and I/O ports. Cables are privileged points of ESD entry because thay act as efficient pick-up antennas for the ESD field around the discharge area. Then the induced currents are carried inside

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by shield pigtails, unprotected wires, and the like. For I/O cables, a radical improvement is obtained when unshielded, or poorly shielded, cables are changed for homogeneous shields plus metallic connectors with integral grounding to the mainframe. If a weak spot exists, a close look will probably show one of these typical flaws, detrimental to high-frequency immunity: • • • • • • • •

Improper high-frequency bonding and grounding of the machine parts, high-frequency wise Deficient subsystems or OEMs (Other Equipment Manufacturers) attached to an otherwise healthy system Poorly shielded I/O cables or original manufacturer’s cables and connectors replaced by cheaper look-alike (but not perform-alike) items Deteriorated shields or housing integrity, missing RF gaskets Mediocre filtering hardware or improperly bonded to the chassis Filter located too far inside Input and output wires of the filter tangled or harnessed together Safety ground wire forming a loop extending inside the housing

After quickly installable field fixes have been applied (23), rerun a test to see if the ESD critera are now met. Be sure to rerun the test on all zones, even those that were previously okay: ESD and Murphy are old mates, and a local improvement may have caused a degradation in another place (especially any change implying rerouting of wires). Document your progress with a new pass/fail map. Never remove a fix that seems to bring no improvement: Add them up to the final success. The philosophy behind all this is that if a unit at its site, with all its external cables and peripherals in place, is fixed to 8-kV ESD, it will be vaccinated against any type of short, fast rising transients, even if the actual reason for the field problem is never found . There are, of course, exceptions to this rule. One is that if the trouble was due to a casual power line overvoltage or undervoltage, lasting a half-cycle or so, an ESD check will not detect it. But such troubles are generally traceable by putting a spy monitor on the power line. Another problem is that more and more systems are using automatic recovery software, which tends to make the error invisible to the user. Yet, with some specific customer applications, repeated errors could indirectly cause problems. If this is suspected, the ESD simulator should be used continuously with a nonperturbing monitoring device (e.g., a fiber-optic link), synchronized to the ESD pulse repetition rate, making it possible to capture erroneous data. Finally, certain civilian environments, and many military ones, are exposed, for short time periods, to very strong ambient RF fields, from nearby radio or radar transmitters. However (portable transmitters and cell phones excepted), such exposure is generally not random and usually is detectable by a field survey.

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143

Warning

An ESD gun delivers high voltages, which could be dangerous for devices whose vulnerability is not known. Always start the test at low levels since temporary malfunctions occur generally well below a possible damage level. This is not a survival test : Do not zap directly parts such as connector pins, membrane switches, and LEDs, if they are directly wired to sensitive components, Keep away all people who are not absolutely required to attend the test (especially bearers of cardiac pacemakers). Isolate the test zone with a colored strip or any kind of temporary barrier.

4.10. HOME-MADE INVESTIGATION TOOLS AND DIAGNOSTIC HINTS Investigating ESD susceptibility after a failed test or an actual field problem can be very frustrating for someone with no experience or preliminary knowledge of the ESD coupling mechanisms. On the contrary, with some background and a minimum set of appropriate diagnostic hardware, it will turn into a rewarding experience. Besides the ESD simulator, a few basic tools are needed [more on this subject can be found in (23) and (24)]: •

• • •

A fast digital memory oscilloscope, with an equivalent analog bandwidth of at least 500 MHz, corresponding to the 3-dB bandwidth for a 0.7-ns rise time An E-field injection adapter to mount on the gun tip An H -field injection adapter to mount on the gun tip A shielded EMI-type of passive current probe, with a minimum 500-MHz bandwidth and preferrably a flat response (transfer impedance) for the 5to 500-MHz range

Because of the limited area that they cover, the two field enhancement adaptors can help finger-pointing equipment weaknesses like shielding deficiencies of the housing, breeches in a PCB ground plane, or unfiltered (or poorly filtered) input ports. The E-field injection adapter is added to the tip of the ESD gun (Fig. 4.36). Some vendors of ESD simulators are offering this optional feature. It can also be homemade with any round metal plate. For a 8-cm diameter, the disk has an area of 50 cm2 , which approached at 1 cm from the target area will create 5 pF of coupling capacitance, which is about 200 of coupling impedance for a 1-ns rise time. A bracket is used to hold the disk against the pointed tip and to provide a smooth return path for the discharge current. Without it, the gun would probably not trigger, or display a “misfire” condition. The bracket can be screwed to the ground return threaded hole of the gun. To make sure that the disk will rise at the

144

Chapter 4 ESD Diagnostics and Testing er sh red a w lde ze , so ire n o Nylon or PVC rod br ead re w all w h ent drilled 12 mm m c e Nylon screw S scr the r o o t ld ESD gun ie d tip Sh ate flo

Shield soldered to center wire Det ail AWG 12 or 10 for ground connection back to generator

S = 20 cm2

Dia. 5 cm Semi-rigid coax RG405 (2 mm dia.) Ring terminal soldered to the shield Center wire, fold back and solder Self-tapping screw 2.5 or 3 mm dia.

H-field adapter

E-field disc 80 mm dia. (S = 50 cm2)

10 kΩ Insulating spacer (nylon or PVC) Steel bracket Generator ground screw E-field adapter

Figure 4.36 Homemade E-field and H -field adapters. For the E-field adapter, any round metal plate, like the cap of a preserves glass jar or the like, can be used.

tip voltage, a 10-k, 5-W resistor is inserted between the metal disk edge and the bracket end, through an insulating spacer for preventing the 10-k resistor from being shorted by the mounting bracket. A 1-cm plastic rod can be used as a distance gage to keep the disk-to-target interval. When the gun is switched on, the disk rises abruptly to the full tip voltage, re-creating approximately the conditions of the E-field coupling from an I-ESD (see Section 2.4.2 and Fig. 4.12). The capacitive current is injected in the

4.10. Home-Made Investigation Tools and Diagnostic Hints

145

victim’s target as a short spike of about 3 A/kV. By starting with a low level, like 1 kV, this method can be used for a detailed exploration of the failed areas (25). Typical examples of vulnerable PCB spots that can be detected by this “teaser” include microprocessor-related lines like clock traces, RESET, WATCHDOG, and CHIP-SELECT. E-field sensitivity can also be found on special connectors (J-TAG), test pads, or FLASH programming pads because they present large footprints, generally not screened by the PCB ground plane. The H -field injection adapter is also added to the tip of the ESD gun (Fig. 4.36) and available from some ESD simulator vendors. This H -field radiating loop can also be homemade from a piece of semirigid coaxial (RG405), forming a so-called Moebius loop. At the drive end of the loop, the copper shield is stripped and left floating. At the return end, the center conductor is soldered to the shield and extended via a piece of AWG 12 or 10 wire (2-mm diameter) back to the grounding post of the gun. This forms a perfect H -field antenna, with the single-end grounded shield acting as a Faraday screen against the E field. With the dimensions shown, this antenna generates, at a distance D = 0.1 m from its center, a magnetic field pulse with amplitude H per ampere of loop drive: H =

I (A)S(m2 ) = 1.6A/m 4πD 3

For instance, with an IEC-type gun set to 2 kV (i.e., 7 A for the first peak current), the field at 10 cm will be H = 11A/m This correspond to the field that the target zone would see for an actual 2-kV ESD. Note In the near-field region, the H field from a small loop is falling-off like 1/D 3 . For the frequency range of concern, the near-field region extends up to 10 cm from the loop. Therefore, the given field is very localized to tens of square centimeters and collapses strongly as one moves away, which provides this investigation tool with a good directivity. This method is used for a detailed exploration of the failed areas, which can be responsive to H -field excitation: shield leakages, nonscreened traces loops on a PCB, missing, or poorly bonded cable shields. The EMI passive current probe is associated with a fast sampling oscilloscope. This probe can be used as a sniffer to identify the ESD current paths on external cables and grounding wires. The point is to get an idea of the way the ESD current is spreading from the discharge point to the different parts of the system. While doing repetitive discharges (like 1 pulse/second), the current probe is successively slipped on the EUT cables, including the ground wires. For each cable, the probe must be placed close to the entry point. The shape and amplitude of these currents, seen on the oscilloscope (set to 50- input), is recorded and listed in order of magnitude. Then a last measurement is made of the total return current on the ground wire of the generator. This current does not necessarily

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amount to the summ I1 + I2 + I3 and so forth for the individual cable currents. The difference corresponds to the capacitive current, which flows directly from the EUT to the ground plane, via stray capacitance. Although this current tracing will not solve the ESD problem, it helps to understand the preferred current routes and what are the circuits or subassemblies in the machine that are crossed by the largest share of the total current (see also Chapter 5). One word of caution: Oscilloscopes are notoriously susceptible to the radiated field of an ESD. To prevent false triggering and misleading results, the oscilloscope should not be placed too close to the EUT; 1.50 m would be a minimum distance, the farther being the better. The mediocre common mode rejection of the oscilloscope input makes it also vulnerable to the outer shield current on the probe coaxial cable. To reduce this parasitic coupling, coil 2 or 3 turns of the probe cable (RG58 or else) in the window of a lossy ferrite: Select a ferrite toroid with at least 12.5 mm (0.5 inch) inner diameter, and a ferrite impedance 150 (for one through pass), from 30 to 300 MHz. A good check for this desensitization of the oscillope is to apply discharges on the EUT, with the current probe close to the EUT, but not clamped on any cable. If a significant signal is still displayed, this means that the oscilloscope is disturbed.

REFERENCES 1. Kocharian, V., and Tolman, D. Express Diagnostic for ESD Simulators. IEEE/EMC Symposium. Boston, 2003, p. 708– 712. 2. IEC 61000– 4-2 ElectroStatic Discharge Immunity Test (2001 + Amendments). 3. Hirata, T., Takahashi, T., and Shibuya, N. Evaluation of Fall Time Restriction of ESD Test Current. IEC Tech. Comm. 77 Report, 2007. 4. Smith, D., Barth, J., and Hyatt, H. Simulators Should Simulate. EOS/ESD Symposium, Orlando, FL, 1996, p. 211 5. Rhoades, W., and Maas, J. New ANSI ESD Standard Overcoming Deficiencies of Worldwide Standards. IEEE/EMC Symposium. Denver, 1998, p. 1078– 1081. 6. Pommerenke, D. Characteristics of Human/Metal ESD Ref. and Generators Parameters. IEEE/EMC Transactions, Nov., 2004, p. 498–511. 7. Caniggia, S. and Maradei, F. Circuit Modelling of ESD Generators. IEE Transactions on Industr. Appl., Nov., 2006. 8. Maas, J. S., and Pratt, D., Study of the Repeatability of ESD Simulators. IEEE/EMC Symposium. Washington, 1990, p. 265– 269. 9. ANSI C63-16 Standard for ESD Test Methodology and Criteria. Draft, 2005. 10. Mohr, D. How to Compare Old and New ESD Test Methods. EMC Expo, Washington, DC, 1989, p. B.3.9– B.3.14. 11. Honda, M. Characteristics of Low Voltage ESD. EOS/ESD Symposium, Las Vegas, 1991, p. 18. 12. Vrachnas, S. Testing Switches for ESD Simulators. Electronic Test, Feb. 1985, p. 44–52. 13. Calcavecchio, R. A Standard Test to Determine ESD Susceptibility. IEEE/EMC Symposium 1986, San Diego, p. 475– 480. 14. Pommerenke, D., and Frei, S. Analysis of Fields on Horizontal Coupling Plane in ESD Test. Journal of ElectroStatics, No. 44, 1998, p. 177– 190.

References

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15. Richman, P. A Realistic ESD Test Program. EMC Technology Magazine, July 1983, p. 50. 16. Pratt, D., and Davis, J. ESD Failure Rate Prediction. IEEE/EMC Symposium, San Antonio, 1984. 17. Habiger, E. F. ESD Immunity Testing Reproducibility from a Statistic Point of View. Zurich EMC Symposium. 1995, p. 645– 648. 18. Renninger, R. Improved Statistical Method for System Level ESD Test. IEEE/EMC Symposium, Dallas, 1993, p. 20–25. 19. Rittenour, T. J., and Gisin, F. Statistical ESD Test, Using New ANSI Guide. IEEE/EMC Symposium, 1992, Anaheim p. 464– 467. 20. Boxleitner, W. ESD and Electronic Equipment, IEEE Press, 1989. 21. Boxleitner, W. Design and Test for ESD Immunity, Based on Actual Equipment Use. EMC Expo, Washington, DC, 1989, P.B.3.15– 3.22. 22. Nick, H., Osborn, B., and Chang, Y. W. Diagnostic Effectiveness in Computers Using Deterministic ESD. IEEE/EMC Syposium Washington DC. 1990, p. 274– 279. 23. Mardiguian, M. EMI Troubleshooting Techniques. McGraw-Hill, New York, 2000. 24. Smith, D. Investigate System-Level ESD Problems. Test & Measurement World , 1999. 25. Pommerenke, D. Finding the Root Cause of an ESD Upset Event, Design Conference, 2006.

Chapter

5

Design for ESD Immunity E

lectrostatic discharge should not be fought with twelfth-hour fixes and costly retrofits. Rather, it must be treated as any potential environmental condition; that is, it should be dealt with during the equipment design. As for any organized EMI control, ESD protection consists in anticipating, or correcting, the unwanted effects of a hostile electromagnetic ambient. Like any EMI threat, ESD manifests through conducted and radiated phenomena, with the latest being often the predominant mode. But there is some unique aspect to ESD that is not found in ordinary EMI-radiated susceptibility: unlike classical Radio Frequency Interference (RFI) scenario where the victim equipment and its cables are illuminated by a uniform field, ESD generates locally a very strong field pulse, typically >1 kV/m near the discharge point, attenuating rapidly as one moves away toward other parts of the machine. Therefore, although ESD hardening should be part of a general EMI control strategy, and not handled as a separate constraint, some of the classical EMC solutions may not be sufficient and should be complemented by additional protections. Looking at Figure 5.1, we can expect ESD immunity to be considered at the following stages: • • • • • •

At component level At circuit board level By software and noise cancellation features At internal packaging and wiring level At housing/cabinet level At installation and environment level

A full ESD protection could be implemented at one of these levels only. Costwise, however, it is generally more efficient for ESD control to be shared between several levels. Like the skins of an onion, there are several layers, going from the physical envelope (metallic or not) of the machine down to the center core Electrostatic Discharge, Third Edition, by Michel Mardiguian Copyright © 2009 the Institute of Electrical and Electronics Engineers, Inc.

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149

Chip core I/O area: buffers and voltage translators

Software IC Module

External cables Components

Internal wiring

PCBs Discretes, electro-mechnical devices Physical envelope User's interface

Figure 5.1 Several layers to be considered for an ESD protection strategy.

of its electronic activity (the ICs that perform the essential functions). Each layer corresponds to a certain power level and frequency band of the signals being handled. For instance: Going from the external envelope where inputs/outputs can handle tens or, eventually, hundreds of volts if we think of power supply, levels as low as 1 V and few tens of milliamperes are reached after a few layers, when it comes to the chip core. In terms of frequency, the functional bandwidths can range from kilohertz, for low-speed analog, up to hundreds of megahertz, eventually gigahertz with high-speed digital processing. No single device, whatever it is deemed to protect from damage, or to prevent errors or signal alterations, or whether it is based on clamping, filtering, or shielding, can perform alone for all these different amplitudes and frequency domains. Instead, protection components are best installed at the boundary of

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these different layers, with current handling capacity, bandwidth, and physical size that are commensurate to the layer that is to be protected downstream.

5.1. ESD PROTECTION AT COMPONENT LEVEL A first degree of ESD immunity can be achieved by selecting components (logic or analog ICs, operational amplifiers, resistor networks, etc.) that already have built-in ESD protections. Appendix A gives some information on the type of embedded ESD damage protection incorporated by some vendors.

5.1.1. Integrated Circuits with Internal ESD Protection With the gigantic growth of the IC market, and the need for cost and volume reduction, a vast effort has been accomplished by manufacturers to incorporate ESD protection in the chip itself. However, as is often the case for technical progress, another trend is conflicting with the first one: Size reduction, or shrinking, by reducing the IC features size down to the submicron region, is causing such a squeeze in oxide thickness and metal trace width that even the protection devices such as diodes, crowbar transistors, and polysilicon resistors can no longer handle the required pulse energy. Several trade-offs are used to accommodate this conflict (1–4): 1. When scaling down by a k factor, for example, going down √ from 1- to 0.1-μm rule, it is possible to apply a lesser scaling factor, like k for the chip periphery where I/O pads and protection components are located. 2. While keeping the benefits of downscaling for the chip core, the I/O pads and protection components can be arranged in a double ring, with staggered pads such as the occupied real estate is optimized. 3. The effective dissipation area and contact area of the protections can be artificially improved by using slotted traces, multifingered shapes, and multiple contacts for diodes. Although the protection efficiency of these techniques can be tested through the standard HBM, MM, and CDM tests (see Chapter 3), a more recent design tool has been introduced: the TLP (transmission line pulse) where a calibrated square pulse is injected into the device via an RF-type jig, using precision-etched stripline. By varying the pulse amplitude and duration, more insight is obtained for critical failure parameters of each IC pin, including I ,V curves and mismatch. This technique is easily simulated by sofware tools such as SPICE, and results are correlatable to those of a real HBM or CDM pulse with equivalent (current–time) area. Another need that urged IC manufacturers into designing overvoltage suppression is the latch-up phenomenon, characteristic of CMOS, but also found

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151

with bipolar technologies. Caused by a parasitic bipolar (PNPN lateral thyristor), it manifests as a stable, low-resistance path, bridging Vdd with Vss if a transient current exceeding a few 100 mA is applied. It generally ends up in IC damage by overheating. Figure 5.2 shows some of the frequently used passive overvoltage protections that can be embedded in the chip. Their main features are summarized in Table 5.1. This table does not include subminiature protections incorporated by IC manufacturers in the chip core itself. Some other protection techniques have been devised that are not integrated in the chip but implemented in the module package, which does not suffer the same dimensional restrictions. One of them is shown in Figure 5.3. It consists in a ZnO varistor ring laid on the periphery of the chip carrier or substrate, such as all the module leads are 90◦ crossing with this varistor trace. The ZnO material, acting as a voltage-dependent resistor, is applied in the form of sinterable ink, whose width and thickness are adjusted for the desired capacitance and breakdown

INPUT

OUTPUT VCC

Bond pad

VSS DIE EDGE (a) Simple Diodes Protection

(b) CMOS Transistor (Crowbar) Protection Rwell

(c) Resistor and Transistor Protection

Figure 5.2 Few widely used ESD protection schemes, embedded in the IC itself.

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Table 5.1 Summary of Chip-Integrated ESD Protections Type of Embedded Protection

IC Technology CMOS

Unprotected (bare chip) Clamp diode + series resistance Input protected by Schottky diode (Vbr: 30 V) Crowbar transistor Thyristor Output, unprotected Diodes + resistance + low-pass filter

CMOS Bipolar

Low-speed drivers (RS 232)

ESD Withstanding, No-Damage Level (HBM test, 150-ns pulse) 50 V (for 0.50-μm rule) 2–4 kV

700 V 2 kV 5 kV 2 kV Up to 15 kV

8 5 7 6 4 e

5

3 4

Figure 5.3 Varistor “ring” for collective clamping of all the IC pins (6). The printed varistor ink trace (6) is crossing the chip leads (4, 5). On top of it, a grounding ring (7) collects the surge currents.

voltage (5, 6). For instance, with a 20-μm thickness and 0.25-mm2 crossover area, the following charateristics have been obtained: Breakdown voltage (Vbr) Vbr: 10 V Peak current for ESD-type pulse duration (100 ns): 50 A Energy handling: 1 mJ Clamping efficiency, α = 7, which translates into a clamping voltage ≈ 50V for I = 50A Capacitance to ground: 2–4 pF/pad In summary, efficient integrated protections, up to 15 kV, are achievable, but they are expensive and take chip real estate. Fast I/Os can be protected on

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153

the chip, but with some prejudice to their speed, because of the capacitance of the integrated diodes (typically 10 pF). Thus, if no technology or vendor can be found with built-in ESD protection that matches the objectives and constraints, application-specific protections are necessary. This is especially true for lines that are connected to “user-touchable” items, mostly connectors, as explained next.

5.1.2. Additional ESD Protection: When Is It Needed and How Much? It is, of course, cost-effective to purchase parts that are ESD immune (e.g., with a 2- to 4-kV ESD grade) rather than adding external transient protection devices to each component. Yet, in many cases, an additional protection is necessary, with performances selected to fulfill the expected ESD immunity of the equipment, because: 1. Integrated resistors, zeners, and crowbars are efficient against damage but cannot prevent errors if a few volt transient is induced by ESD. 2. The 2- or 4-kV vendor-specified ESD immunity is only granted against a human body (HBM) type of discharge, with a maximum current of 2.6 A (for a 4-kV grade). This covers the IC during handling, manufacturing, assembly, packing/unpacking, or maintenance. In actual machine life, and during ESD tests per IEC 61000-4-2 or automobile SAE J1113, ESD currents up to 30 A, for a 8-kV direct contact, and 45 A for an air discharge can be applied to the equipment. Although many circuits will never be directly exposed to such currents, but only to their radiated effects (Fig. 5.4), some others will. This is the case for ICs that connect directly to a user-touchable connector pin, a manual switch, or keyboard or that are arc-reachable by an air discharge, whereas the arc jumps from a discontinuity of the machine envelope to an internal component or trace. These added protections can be perform by: Decoupling (clamp diodes, crowbars, and capacitors): the pulse current is bypassed to Gnd or +Vcc Blocking (inductances): A high impedance is opposed to the ESD current. Absorbing (lossy ferrites and resistors): the ESD pulse is dissipated into heat. Depending on the selected components, their action can: Ensure a damage-free, but not an error-free operation. Filter the high-frequency components of ESD spectrum, that is, preventing errors with short pulses (less than 10 ns), but cannot attenuate long ESD pulses, typical of a direct injection. Ensure both survival and error-free protections. Following is the list of the commonly used ESD protection components, mounted close to the IC to be protected.

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ESD Gun

VDD

VSS

Figure 5.4 Voltage at the Vcc pin of a keyboard IC when a 1-kV indirect ESD is applied to the HCP at 10-cm distance. Although not destructive, the 130-V pulse causes a lockup of the keyboard in a frozzen state, requiring a power off/on action (7).

1. Transient protectors (in discrete or integrated packages) such as the ones shown in Figure 5.5. Leadless SMT devices, with 2–8 terminals (SO-8) are available, capable of handling the full current of a 15-kV IEC-type discharge. 2. Series resistances on the sensitive, high-impedance inputs, to limit the current below the damage level. 3. Capacitive decoupling next to critical signal pins. On signal inputs, 30 pF or more can be added, depending on what capacitive loading can be tolerated by this line, without affecting the performance. While transient protectors will not eliminate low-level glitches (those above the detection threshold, but not high enough to cause damage), decoupling capacitors will. 4. Capacitive filtering next to the power input pin. A 100-nF ceramic capacitor can be added, even if not considered necessary, at the initial circuit design (though less sensitive than signal inputs, some Vcc supply pins can cause a logic error if the parasitic pulse has enough amplitude. An interesting alternative, although not particularly developed for ESD, is shown in Figure 5.6), where the power supply buffer capacitor is integrated in the substrate of the IC. There is now a general trend among IC manufacturers

5.1. ESD Protection at Component Level

155

Typical transmission line pulse response graph 360 Trigger voltage

PESD0603-140

320

Voltage response (40V/div)

280 240 200 160 Clamping voltage

120

1,000V TLP pulse 800V TLP pulse

80 40 500V TLP Pulse

0

0

D

20

60 40 Time (10 ns/div)

80

100

Dimensions in millimeters (inches)*

A

B

Length A Part Min. Max. 0402 0.95 (0.037) 1.05 (0.041) 0603 1.40 (0.055) 1.80 (0.071)

Height B Min. Max. 0.33 (0.010) 0.43 (0.017) 0.38 (0.015) 0.58 (0.023)

Figure 5.5 Transient voltage suppressors, with very low parasitic capacitance. (Source Tyco/Raychem.)

to incorporate such capacitors in the chip itself, using diffused junction capacitances. A final precaution must be taken when cascading external clamping devices with chip internal protection diodes. It relates to clamping coordination: If a fast acting diode exists already inside the chip, it parallels the external clamp, and one must make sure that the first one will not react faster. This would cause the full pulse current to cross the IC protection, with the external protection not even triggering. In other words, the faster but fragile device would prevent the triggering of the bigger one, and would be destroyed by an energy that it cannot handle. The solution is to always place some series impedance (a resistance or a small inductance) between the two (Fig. 5.7).

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.160"

.156" .400"

.015"

.330" <.020"

Identifies top surface

Silver terminations

Silver termination 1

16

8

9

Capacitance pin 8 to pin 16 Normal voltage Operating temperature Capacitance substrate to pin 16 (optional) Typ ΔVcc for current transient of +20 mA/ns Vcc to ground

0.1 to 0.5 mfd −10 V to + 10 V −55° C to + 125° C 0.001 to .005 mfd +0.040 Volts

Figure 5.6 A Vcc decoupling capacitor integrated into the IC lead frame. The die can be put on the capacitor, and the whole assembly is ready for conventional bonding/encapsulation (AVX “Bitguard”).

Most of the above solutions, however, have their limitations: They rapidly add to the parts count and to the cost, a disadvantage if these aspects are critical. They often work against the circuit speed and performances.Varistors and Zeners, especially, have parasitic capacitances typically exceeding 100 pF. Hopefully, the need for ESD and RF immunity of faster digital circuits has prompted the development of specific, low-capacitance suppressors. For protecting very low level inputs, such as a few hundred millivolts or less, a low-capacitance directly polarized signal diode can be used. The diode is rated for a peak instantaneous current corresponding to a worst-case ESD condition,

5.2. ESD Protection at the PCB Level (Internal Circuitry) ESD

ESD Medium size, 10 mJ external prot. Small, IC-embedded prot.,10 μJ

Distance too short (few mm ≡ few nH) The small device is faster and may trigger first, taking all the current

ΔV 1 cm = 10 nH

157

IC

or 10 Ω BETTER

Figure 5.7 Clamping devices coordination.The voltage drop across a 10- resistance or 10-nH inductance, will raise the voltage seen by the first device (left), forcing its triggering.

that is practically a direct injection of 30 or 40 A over 100 ns, on the corresponding line. With a forward barrier voltage of 0.5–0.6 V, the diode appears as an infinite resistance for small signals, but will sink all voltages exceeding 0.6 V. A last approach, often neglected, is to make sure to not use a technology with transitions that are too fast, unless it is absolutely needed for a specific function. Many times, logic families with 2- or 3-ns. transitions are used all over the board by a sort of intellectual license, assuming that “the faster the better.” Chapter 2 showed that a good immunity can be achieved, at no additional cost, by using devices with the lowest bandwidth compatible with the function. The designer must still watch for the device’s input impedance. A device 10 times slower will not show much improvement over a TTL, Schotthy TTL, or Advance CMOS (AC) if it has a quasi-infinite input impedance. By creating a weak tie to a fixed potential, pull-up/pull-down resistors can help decreasing the vulnerability of high-impedance inputs. The growing use of surface-mount technology (SMT) brought a substantial reduction of the ESD field pick-up area, at and around the component itself. The size reduction factor k provided by the smaller footprints corresponds approximately to a k 2 reduction of the ESD-induced effects.

5.2. ESD PROTECTION AT THE PCB LEVEL (Internal Circuitry) The printed circuit board is certainly the area where the improvement/cost ratio is the largest (8). The effort invested in sound PCB layout will be paid off many times over by a gain in immunity that can be drastic, often at no additional parts cost. There are many cases where ESD immunity has been built at PCB and interface levels so that even without additional shielding of the housing, the equipment can withstand ESD levels above 10 kV. Nevertheless, quoting Hubing (9): “Some of the worst PCB design choices are made by engineers who tried to comply with a list of EMC design guidelines.

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To make things worse, there are as many design guidelines as there are design engineers.” The guidelines given hereafter are a short compilation of time-proven, non-self-conflicting rules, that build up the ESD defense without compromising other EMC or functional performances, simply because they all concur to high immunity and low emissions, up to and beyond 300 MHz.

5.2.1. Reducing the Field-to-PCB Coupling Mechanisms Not mentioning the direct contact by the ESD intruder, an aspect that will be addressed in the next sections (box shielding, I/O port protection, etc.), two ESD field-coupling mechanisms play a role in the PCB susceptibility, as described in Section 2.4 : magnetic field coupling and near electric field (or capacitive) coupling. Against H-Field Coupling

The rule here is to minimize the exposed loop areas by checking all the runs against signal-to-return loops or Vcc -to-0-V loops: •

Never let a signal or a Vcc trace running without a close ground return (trace or, preferably, plane): Use ground planes or largest possible copper lands to act as noiseless ground and shield. In that respect, double-sided boards with maximum unetched copper on one side are better than single-sided boards, multilayers being even better.

Against E-Field Coupling

Here the risk is not that of some “loop” antenna effect. Instead, one can think of a rod, or whip radio-receiving antenna, or more simply of an invisible capacitor between the PCB and the charged source: the gun tip, the edge of the HCP or VCP during the test, or a person’s finger during an actual event. Any exposed sensitive trace, high-impedance IC input, or IC package itself can capture a sufficient capacitive current during the abrupt ESD voltage change. Although it is not a destructive scenario, such a target should always be protected by a ground plane underneath (or above): • •

•

Minimize the length of open-ended high-impedance lines. Do not allow unused inputs to be floating, hence making easy targets for capacitive pick-up. If not detrimental, connect them to ground or load them with pull-up/pull-down resistors. Never run critical signals (Clock, Reset, Watchdog, etc.) near the board edge. Such locations are prone to capacitive coupling from a nearby ESD. This warning applies even to PCB with full ground planes because copper planes themselves are often etched near the fringe of the epoxy board edge.

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159

For reinforcing the screening effect of the ground plane at the board edges, use a peripheral ground trace on the opposite (component side) face of the board. This guard trace must be frequently connected to the ground plane by holes. It can also serve as a collector ring for the I/O decoupling capacitors.

Figure 5.8 shows several “no-no” in PCB design with respect to these rules. Once these have been purged from the PCB, the ESD immunity improves significantly, at no cost. Eventually, one may use a compartment shield to protect some critical areas where ground plane could not be implemented or was insufficient. This shield should be most directly grounded to the chassis, to prevent the shield from reradiating on the PCB, or contaminating the 0-V reference with shield currents.

5.2.2. PCB Connectors Areas Particular attention must be given to PCB connector areas, especially those directly receiving I/O cables from the outside. Normally I/O cables should be shielded, or at least decoupled, at their point of entry into the enclosure, but there is often no such interface and they plug directly into the PC board. Since these cables are privilegied ESD pick-up antennas, they can ruin the best PCB design. 5V

0V

+

VCC input decoupling capacitor Local VCC decoupling

CLK GND

RST

Induced voltage HF filtering

Ground ring

Figure 5.8 Example of a vulnerable PCB layout. Long capacitor traces are rendering the decoupling inefficient; Instead they offer pickup loops to the ESD field. The so-called ground ring is shifted inboard, not protecting the clock trace, which is on the card edge, exposed to capacitive coupling. The HF decoupling capacitor for the RST line is too far from the IC: An induced noise in series in the loop will entirely appear on the critical input since the capacitor is an HF short circuit.

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Such connectors should preferably be on the same edge, or same angle (two perpendicular edges) of the board: This will prevent ESD-coupled currents from external cables to cross the entire board where they may cause longitudinal ground noise. This is due to the fact that, even ground planes that seem perfect are not: small-dimension planes have always some parasitic inductance, typically 0.1 nH/cm. Thus, a 1-A/ns current pulse will cause 0.1 V of ground noise per centimeter of trip. Therefore, when a PCB connector is also the equipment frontier with the external world, it should be treated as a potential ESD entry port. Incoming lines can be filtered at the board edge by one of the following: Discrete ceramic capacitors, with ultrashort leads, or better, surface-mount type Capacitor arrays Capacitors teamed with miniature ferrites, discrete or integrated into the connector This crucial ESD topic will be addressed in detail in Section 5.5.

5.2.3. Signal Ground versus Chassis Ground Wether or not the PCB 0-V reference should be grounded to the equipment chassis, and where, is a recurring issue. Generally speaking, it is better EMC-wise, to have the signal GND being equipotential with the chassis, especially in the PCB area. However, some designers, for specific reasons, such as preventing low-frequency ground loops, keep the PCB isolated from the chassis ground. Considering the frequency domain covered by an ESD, this issue is irrelevant since even a floated PCB becomes virtually grounded above a few tens of megahertz anyway. However, if a PCB ground has to be floating, a VHF connection to chassis must be established, via a few nanofarads ceramic capacitor, preferably in the I/O connector area. This is to prevent the ESD-induced currents to spread across the PCB, sinking to the ground plane by the existing PCB-to-frame parasitic capacitance via uncontrolled paths.

5.2.4. PCB Hardening with Plastic Products An increasing number of devices are designed with plastic housing and with no intention to apply a conductive coating. In such cases, if indeed all but one of the EMC constraints can be satisfactorily met with a nonconductive envelope, it would be regrettable to be obliged to change for a full metallized plastic just because of the ESD requirement. So, we are facing a situation where the PCB itself becomes the ultimate, and sole physical barrier to ESD coupling. Even if only indirect ESD is contemplated—which may not be true if the envelope is still accessible to the arc creepage—a bare PCB and its population of ICs and active circuitry are first-class targets for field induction.

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161

Here, all that has been said before has to be emphasized, especially regarding E-field, capacitive coupling. A PCB with at least a full ground plane on one side and a ground ring on the edge is a must. Since practically all complex ICs (microprocessors, Application-Specific IC (ASIC), Flash memories, DSPs, etc.) have multilayered chip structures, the chip’s internal ground reference plane is tied to the PCB’s ground plane by the many GND pins of the IC package, such as the whole PCB plus IC assembly benefits from a monolithic ground plane. This benefit should not be degraded by empty spots or gaps in the 0-V plane. Slots or discontinuities in the ground plane are particularly detrimental in zones with oscillator inputs, Reset, or (Interrupt Request) IRQ. This also applies to pads intended for chip resident programming or manufacturing debugging/customization (such as JTAG), since these functions are not normally exercised by the user but can be wrongly activated during an ESD. If necessary, the “monolithic ground plane” two-dimensional (2D) configuration of the PCB copper plane plus the ICs internal plane can become a real 3D Faraday case, by soldering small 5-sided stamped sheet metal covers, which are found from manufacturers of shielding hardware. Another option exists by using heat-formable conductive polymer overlay, which can be tailor-cut to the populated PCB (10). Summary of ESD Protection Measures at PCB Level • • • •

• • •

Select ICs that are inherently ESD protected to ≥ 2 kV (HBM test). Clamp/decouple critical inputs and Vcc pins, close to the critical ICs. Select logic technologies with longer rise times, compatible with the function. Use PCB with ground (0-V) plane, without slots. Multilayers are best. If single-layer/single-side have to be used, landfill (do not etch) voids, with copper linked to all 0-V nodes. No critical traces (Clock, RST, etc.) near the board edges. Keep space for I/O ports decoupling with SMT components, right at entry points. All general EMC rules have a positive effect on immunity to ESD, provided that its high-frequency spectrum (>300 MHz) is kept in mind.

5.3. ESD PROTECTION BY INTERNAL WIRING AND MECHANICAL PACKAGING Several practices in component selection, placement, mounting, bonding, and cabling can upgrade an equipment’s defenses against ESD. As far as selection, there are basically two things to consider: Some components or subassemblies can be generators of internal ESD, some others can be carriers or even victims. In the generator category, we find the parts that are made of insulating material can be momentarily or permanently rubbing, rotating, sliding, and the like. This would be the case, for instance, with:

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Paper trays or containers Insulating pulleys or rollers with rubber belts or conveyors Cooling fans with polycarbonate blades High-voltage dc power supplies When these components are selected, preference should be given to those that the manufacturer has designed as antistatic or static-free, through material selection, conductive additives, or shielding. All metal parts around these items should be grounded to the metallic mainframe of the machine. For sliding or rotating parts, wiping contacts or conductive grease can be used. However, these solutions may create graphite dust or maintenance problems. If regular maintenance cannot be counted-on, smooth wiping made by soft conductive brushes, grounded to the chassis (Fig. 5.9) can be used. As a variation of this, metallic tinsels arranged as antistatic combs or neutralizers are available: Their multitude of grounded needles act as a static collector that bleeds the charges to ground even without physically touching the electrostatic charged object (Fig. 5.10). High-voltage dc supplies, due to the nonnull value of their static field, can charge by influencing all insulated parts (even ungrounded metallic parts) that are in the path of the electric field lines. To reduce this charging, high-voltage dc sources should be surrounded by a grounded Faraday shield to minimize their pararasitic capacitance with the other nearby components. In extreme cases of serious static generation within a machine, active static eliminators can be installed: They generate locally a high-voltage alternating field that ionizes the air, hence allowing the separated opposite charges to recombine (Fig. 5.11). ESD Protection of Keyboards and Flat Displays

The other category of components, that is, the “carriers” or “victims,” is by far the largest. A special problem is posed by the keyboards and especially by the membrane keyboards. Initially, these devices need a more or less large opening in the shield, creating a privileged entry port for ESD coupling. Moreover, they have a high probability of being hit by a direct discharge, with the arc directly reaching

Figure 5.9 Grounding of shafts and rotating parts with carbon brush or bronze spring.

5.3. ESD Protection by Internal Wiring and Mechanical Packaging

163

Figure 5.10 Tinsel and spring-loaded tinsel bleeders. (Courtesy of Chapman Co.)

the touch-sensing circuits under the domes or capacitive arrays (Fig. 5.12). One question that needs to be clarified first is what sort of unwanted response to an ESD hitting the keyboard is acceptable or not. The criteria could be as liberal as “no-damage” only or more demanding in cases where an illegal keyboard action could cause a dangerous reaction from the device. An example of a keyboard with an ESD-shielded membrane is shown in Figure 5.12. Note that a thin metal interlayer has been provided, which is multipoint grounded to the chassis so that the discharge current does not penetrate the inner part of the keyboard. Cheaper versions exist where, to save one layer, the flexible contact layer has simply a grid of conductive ink acting as a modest “shield.” Although it reduces radiation, it may not be efficient enough to block direct ESD. Other, cheaper solutions can be used for keyboard ESD immunity, if the ESD risk is moderate: •

•

Use, for the outer membrane where symbols are printed, a thick (0.3-mm) polyester film that can resist an arc punch-through, and keep the signal traces of the underlayer far from the edges to avoid a lateral flashing. Add series resistors (10 k) on the signal traces coming out from the membrane, before they reach the active circuits layer.

Contactless “virtual switches” keyboards using capacitive detection of a finger’s touch are naturally protected against ESD because their glass or thick

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Specifications Operating potential: 8 kV rms Effectiveness: 0.024 microamperes per mm of effective length at 10 mm distance from a metal plate maintained at - 1 kV DC Shock hazard: Shockless (less than 40 microamperes per point short circuited) Air pressure: 7-21 p.s.i. dry air not required.

Figure 5.11 Static eliminator bar.

dielectric touch panel can withstand 15 kV or more without breakdown. However, two problems may still occur: The dielectric panel is sometimes porous, allowing cascades of internal avalanches arcing, such that the discharge current could reach the internal circuitry. The capacitive current through the dielectric can exceed the detection treshold, causing an undesired switching. In both cases, 10-k series resistors, like for the membrane keyboard, are a simple and efficient solution. Transient voltage suppressors (TVS) are not recommended because of their significant parasitic capacitance, which interfere with the capacitive sensor circuitry. Regular button-and-pluger keyboards are not necessarily exempt from D-ESD intrusion, depending on the free air trip (Fig. 5.13) between finger tip

5.3. ESD Protection by Internal Wiring and Mechanical Packaging

165

Membrane keyboard

IESD going into PCB traces Contact circuit

Capacitance (touch sensitive) keyboard

IESD Capacitance sensor (a)

Steel membrane with domes (grounded)

Insulating layer with conductive shorting patterns underneath (b)

Figure 5.12 (a) Risk of ESD damage or malfunction with buttonless keyboards. (b) Membrane keyboard with EMI and ESD shielding solutions.

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PCB with electromechanical switches

Labyrinth path

PCB

Flexible plastic overlay

Figure 5.13 ESD protection with conventional keyboard. The lower sketches show two solutions.

and the PCB traces underneath. One solution consists in creating a labyrinth path for the key (this will require a redesign of the manufacturing mold, not always feasible as a late fix). Another solution is to apply a soft plastic overlay on the PCB, which can withstand up to 15 kV for the air discharge. This overlay is embossed above each switch, such as to increase the arc path length. A quite similar problem occurs with LCD displays, when they are mounted flush on a device fac¸ade. As shown in Figure 5.14, a discharge can reach the edge of the LCD frame, without necessarily being totally evacuated by the housing, because: Even if metallic, the housing can be painted (some cured paints or hard coatings have surprisingly high breakdown voltages, exceeding 5 kV). A nonconductive weather gasket is pressed between the LCD rim and the aperture edge. To make things worse, the LCD’s metallic frame is frequently, by construction, connected to the internal signal GND,∗ such that the full discharge current could flow via the ribbon cable down to the equipment boards. Of course, all the above is even more true when the equipment box is plastic. ∗ This, in itself, may create another problem, not particular to ESD: Some devices have, by design, an isolated PCB 0-V reference. This uncontrolled LCD 0-V-to-chassis connection may conflict with the designer’s choice.

5.3. ESD Protection by Internal Wiring and Mechanical Packaging

167

Equipment box LCD

Metal frame PCB

OV

Ribbon cable

ESD current to PCB ground

Figure 5.14 ESD entry path with LCD displays.

The solutions depend on the nature—conductive or not—of the housing. •

•

With metallic (or conductive plastic) housing: • Provide a tight electrical bond, on all sides, between the LCD rim and the aperture edge. This can be made by conductive gasket or spring contacts. • Add a transparent, conductive overlay such as ITO (indium tin oxide), with a typical 3- to 10-/sq surface resistance, and bond the edges of this film to the aperture stepped edge. With a plastic, nonmetallized housing, the display is viewed as a “sacrificed” entry port for ESD: • Use a shielded flat cable, with the shield connected one end to the LCD frame, the other end to the PCB ground. • Add series resistors (10 k) on the signals coming out from the LCD, right at the cable entry on the main PCB.

Finally, ESD has to be considered when it comes to the location of sensitive items such as critical PCBs, magnetic sensors, or storage media and their associated circuit. Not only should their location avoid the proximity of the ESD sources described above, but also the proximity of possible ESD routes such as cooling or display apertures, seams, openings, and the like. Near these places, shielding effectiveness of the housing will be null or minimal and ESD currents will reradiate inside. If covers are bonded by straps, beware that during a discharge, these straps will generate a strong magnetic field. Therefore, no sensitive components or their cabling should be placed close to them. Cables deserve a special mention. Internal wiring, being exposed to ESD reradiation inside, will carry some induced ESD noise. Besides the precautions at their termination into the PCB connectors, the following guidelines will avoid excessive pick-up: Avoid excessive runs of cables along cover seams, hinges, on bonding wires. Do not press cable harnesses and specially flat cables against the edges of metallic covers, which are likely ESD targets: Move them away from the edges or use thick shield.

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Avoid large Vdc -to-0 V and signal-to-0 V loops. As for PCBs, always carry a signal close to its own return conductor. Since, even after these precautions, an excessive ESD pick-up may still exist by coupling into common-mode (cable-to-chassis) loops, an interesting solution is to use common-mode ferrite beads and sleeves over the whole cable. This solution will work best if the circuit is a low-impedance one. Add-on ferrites exist in the form of split beads and yokes. Some of them have been developped especially for flat cables (Fig. 5.15) and recent progresses in lossy ferrite materials can provide 6–15 dB of reduction above 30 MHz, which is precisely the domain where ESD couplings become critical. When using common-mode ferrite, ensure that all of the wires to be enclosed in a same toroid are coming from the same area of the device. With forked harnesses, different branching lengths may cause different ESD pick-up from one wire to another. And since the CM ferrite is based on the mutual cancelling of identical currents, this effect would be spoiled. In such cases, it would be safer to split a large bundle into several subgroups of one or a few wire pairs

Frequency in Hz 10

6

107

108

109 104

Impedance (Z) in Ohms

103

102

103

Split flat cable

Split bundle

102

101

100 105

Impedance (Z) in Ohms

10 104

5

101

100 10

6

10

7

10

8

10

9

Frequency in Hz

Figure 5.15 Impedance vs. frequency of split ferrite beads for flat-ribbon cables and wire bundles. (Source: Fair-rite Co.)

5.4. ESD Protection by Box Shielding and Envelope Design

169

0 10 20 dB

30 40 50 60

Ferrite powder + binder

Insulator jacket

70 80 100

1,000 f/MHz

Figure 5.16 Lossy ferrite-loaded wire. Attenuation for a 0.30-m sample. (Source: Eupen Cables.)

(hot and return, for not affecting the useful signals) having the same “from” and “to” terminations, and equip each subgroup with dedicated ferrites. This has also the advantage of using smaller, lighter ferrites with a smaller bore, and making it easier to do two or three passes of the wire pairs through the window (remember: With ferrites, doubling the number of turns makes the series impedance four times larger). A further application of the ferrite concept is made possible by flexible ferrite tubings and wire coating (Fig. 5.16). A ferrite + soft binder compound makes a sort of “lossy” hose around the conductors, which dissipates high-frequency energy into heat, certainly the best thing to do with HF noise! The efficiency of this technique cannot match that of a real ferrite bead because the percent of pure ferrite in the compound is modest, to keep cable flexibility. It is generally in the 5- to 10-dB range at 150 MHz, for 1-ft lengths. Interestingly, although not widely known among the EMC community, this technique is used universally in car ignition wires for suppressing RF interference.

5.4. ESD PROTECTION BY BOX SHIELDING AND ENVELOPE DESIGN If the components, PCBs, and internal elements have been hardened to a certain ESD level Vx , while the specification requires a level Vs > Vx , the housing is what is left to make up for the difference. The shielding precautions for the housing are basically the same as for any EMI susceptibility problem, keeping in mind, however, that the 300-MHz or higher spectrum of concern obliges the designer to consider the possible leakage of seams and slots exceeding a few centimeters. This dictates that a machine that relies on its housing for ESD hardening should be shielded with the same precautions as any VHF equipment or

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sensitive RF device! In the late 1960s, when ESD problems started to become a nightmare with computers (but its mechanisms were not understood yet), some manufacturers of large computers had to take the “steam roller” approach by making all the covers RF-tight, entirely plating their frame with nickel and the like. Consequently, the main frames took on the appearance of a vault. Additional drawbacks are that the designer of the machine to be hardened may not be familiar with these techniques, which can drastically increase the cost of the cabinet and associated hardware, and generally complicate maintenance, accessibility, and may degrade with aging. In addition to the cost, there are aesthetic/cosmetic reasons that may prohibit the usage of certain shielding and gasketing techniques, particularly for consumer equipment. So, typically, designers are now looking for shielding methods that are economical, will remain unaltered after intensive use of the equipment, and provide a moderate shielding effectiveness in the range of 10–40 dB (i.e., a reduction of electromagnetic fields by a 3–100 factor). But they must provide this attenuation up to the 300- to 1000-MHz region.

5.4.1. Some Shielding Basics Although a full coverage of shielding theory is beyond the scope of this book, a few reminders are provided on how and why shields work and examples of when they do not. The reader who wants to know more about the principles and applications of shields is invited to refer to more complete textbooks (11–13). Shielding effectiveness (SE) is defined as the ratio of the impinging field to the residual field (the part that gets through). For E fields: Ein SE(dB) = 20 log Eout For H fields:

Hin SE(dB) = 20 log Hout

If shields were perfect, Eout , Hout , and therefore Pout would be zero. In practice, a shield can be viewed as an attenuator, performing on two cascaded mechanisms: Absorption and reflection. Absorption increases with: • • • •

Thickness Conductivity Permeability Frequency

5.4. ESD Protection by Box Shielding and Envelope Design

171

Reflection increases with: • •

Surface conductivity Wave impedance

Absorption

To evaluate absorption, or penetration losses, one needs to know how many skin depths the metal barrier represents at the frequency of concern—knowing that the field intensity will decrease by 8.7 dB (or will lose 63% of its amplitude) each time it goes through one skin depth. Entering all the electrical constants, we come to a simple expression for absorption loss: AdB = 131t F μr σr (5.1) where t F μr σr

= thickness of conductive barrier, mm = frequency, MHz = permeability relative to copper = 1, for all nonferrous metals = conductivity (the inverse of resistivity) relative to copper = 0.6 for regular aluminum = 0.16 for standard, cold-rolled steel = 0.3 for zinc

For instance, a 0.03-mm (1 mil) aluminum layer will offer at 100 MHz an absorption loss of: √ A(dB) = 131 × 0.03 100.1 × 0.6 = 30.4 dB This is equivalent to a reduction of the field strength by a factor of (10)30.4/20 , that is, 33 times. Looking at Eq. (5.1) leads to a few remarks: 1. For nonmagnetic materials (μr = 1), the penetration losses increase with conductivity σr . Since no metal has a better conductivity than copper (exception granted for silver with σr = 1.05), any nonmagnetic metal will show less absorption than copper. Nickel, for instance, with σr = 0.2, will exhibit for the same thickness of 0.03 mm (1 mil) an absorption loss of: √ A(dB) = 131 × 0.03 100.1 × 0.2 ≈ 17dB 2. For magnetic materials (μr > 1), the penetration losses increase with μr . On the other hand, their conductivity is inferior to that of copper. Since μr for steel or iron is in the range of 300–1000, while σr is about 0.17, a definite advantage exists for magnetic materials. However, above a few hundred kilohertz (ferrites excepted), μr generally collapses to equal 1, while σr is still mediocre.

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Reflection

For evaluating reflection, it is necessary to know if the shield is in near- or far-field conditions. Near-field conditions, where the shield is closer than λ/6 to the source, are the most critical. For pure electric fields, since their wave impedance is high, it is relatively easy to get good reflection properties because the field-to-barrier mismatch is large. For near magnetic fields, the wave impedance is low and it is difficult to get good reflection (Fig. 5.17). For near-field conditions, the reflection losses are equal to: For E fields: 120π λ R(E)dB = 20 log (5.2) 4Zb 2πr = 20 log

4500 F r.Zb

(5.2a)

For H fields

R(H )dB

120π 2πr = 20 log 4Zb λ

2rF = 20 log Zb

(5.3)

(5.3a)

where Zb = shield barrier impedance, /square F = frequency, MHz r = distance from radiating source, m

Wave impedance Z = E/H

Predominantly E field

377 Ω

Predominantly H field Distance from source λ/6

Figure 5.17 Conceptual view of near vs. far fields.

5.4. ESD Protection by Box Shielding and Envelope Design

173

In both Eq. (5.2) and (5.3), the first term in brackets is the far-field reflection term, independent of the E or H predominant nature, while the second term is the near-field correction. How does one know if, at distances << λ, the field is more electric or magnetic in nature? By looking at the radiating source, one might have an idea of the predominant mode: circuits switching large currents like power supplies, solenoid drivers, heavy current logics generate strong magnetic fields. Conversely, voltage-driven high-impedance or open-ended lines create electric fields. If we apply the specific conditions of ESD to the properties of shields, we see that: •

•

•

The most threatening part of the ESD spectrum being in the high-frequency region, practically any barrier having a thickness of 0.1 mm or more, made of a homogeneous metal, will provide an excellent absorption loss. Conductive paints or coatings will not perform well by absorption because their film thickness barely represents one skin depth or less, therefore their absorption loss is rather low. Here, again, conductivity makes the difference. Silver, copper, and zinc films would still provide some absorption loss in the range of what is aimed for ESD. Graphite paints provide marginal or null absorption loss because of their relative conductivity of 10−5 –10−6 . For reflection, the ESD situation complicates the issue: True personnel ESD, coming from a source whose total impedance is larger than 377 , will tend to generate high-impedance fields (i.e., predominant E term) while furniture ESD will generate low-impedance fields (i.e., predominant H term). Artificial ESD conditions such as IEC test, with 330- generator resistance are almost re-creating far-field conditions from the beginning. Now, how near is the near-field? Since the “nearness” is expressed as a ratio of λ/2πr, we have a frequency-dependent term, that is, the lower portions of the spectrum can be in an extreme near-field condition, while the upper portions where λ is shorter will approach or even pass the near-far transition condition, that is, r = λ/2π.

This is discussed in Section 2.4 along with the experimentation on ESD radiation. Two situations may exist: 1. The discharge does not occur on the conductive housing of the equipment itself, but rather it occurs nearby. In this case, the discussion on absorption and reflection applies. Furniture discharge will be most threatening because this is where magnetic field predominates and the shielding reflection term will be minimal. 2. The discharge occurs right on the housing (direct ESD). In this case the previous approach on near-field and reflection losses is more questionable. What is impinging the metal barrier is not a field but already a current. This current then penetrates the metal barrier, is attenuated, and what is left on the

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Chapter 5 Design for ESD Immunity Exponential decrease of I (Absorption)

Ein

Ereflect I

I

Internal reflection

Eout

Eout

(b) Direct

(a) Indirect

Figure 5.18 Model of a shield barrier against ESD. (a) The classical behavior of a shield illuminated by an electromagnetic field. (b) What happens with direct ESD—the incident vector is already a current.

other side reradiates as shown in Figure 5.18. So, the strict definition of shielding effectiveness, being a ratio of two fields, does not apply here. A better measure would be to use the transfer impedance of the shield, which would convert the current on the discharge side to a voltage on the inner side (14). This voltage in turn excites a radiation mechanism inside the shield. One could also express this mechanism as the ratio of the reradiated field to the ESD current, that is, E volts/m/Iamp This ratio would have the dimension of a radiation impedance in ohms/meters. Another way of considering a shield effectiveness against an ESD is shown in Figure 5.19. A reference ESD event is created by substituting a straight wire to the shield, measuring the induced effect on a victim loop at given, close distance, then replacing the wire by the actual shield to compare the results. Notice that with this concept, a magnetic reflection actually takes place since the incident pulse terminates into a short circuit (the shield). In any case, this direct ESD mechanism suggests that there is practically no first reflection term and that the only chance of a shield to perform well is to have either: An excellent conductivity, as close as possible to copper A sufficient thickness to represent at least a few skin depths Table 5.2 shows, in this respect, the absorption loss of several metals, at several thicknesses, for the 30- to 300-MHz region.

175

7 13 22

30 MHz 100 MHz 300 MHz

70 130 220

0.1 700 >1000 >1000

1 5.2 9.5 17

0.01 52 95 170

0.1

1 520 950 >1000

Aluminum

4 7 12

0.01 40 72 125

0.1

Zinc

400 720 >1000

1 3 5 9

0.01 28 50 88

0.1

Steel∗

280 500 880

1

3 6 10

31 58 98

Nickel∗ σr = 0.2 .01 0.1

7 13 22

Copper Paint (nonhomogeneous metal) σr = 0.04 0.05 mm (2 mil)

a The shielding effectiveness against ESD will be at least equal to this plus some reflection. For steel and nickel, the values shown take into account the fall-off of their magnetic permeability above ≈ few MHz.

0.01

Thickness (mm)

Copper

Table 5.2 Absorption Loss in dB of Several Metalsa

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Chapter 5 Design for ESD Immunity

R

R

2

1

E E

IESD

Figure 5.19 Another conceptual view of a shield reflection with an ESD. As a base for comparison, we assume that 1 a discharge path exists, but without an integral shield, while 2 has an intergral, seamless shield. In 2 , since the source dimensions and charateristics have not changed, everything is as if the right-hand half of radiation in sketch 1 was folded back, thanks to the quasi-perfect perfect barrier. Thus, a significant part of the power is actually refelected. The shielding effectiveness SE of the shield could express as the ratio of the field at point R under condition 1 (artificially created), to the field at same point R when the shield is in place.

With homogeneous barriers, the SE against an ESD would at least equal these values. For steel and nickel, it was considered that their μr is falling to 1 above a few megahertz. Values above 150 dB are calculated, but not measurable. However, housings are not made like continuous metal cubes. They have slots, seams, apertures and the like, which will inevitably leak As in a chain, a shield is only as good as its weakest link. It is important to know its weak points for establishing some realistic objectives, knowing that: • •

At low frequencies, what counts is the nature of the metal that is used: thickness, conductivity, permeability. At high frequencies, where any solid metal would provide hundreds of decibels or shielding, they are never seen because seams and discontinuities completely spoil the metal barrier. ESD belongs to this case.

A slot in a shield can be compared to a slot antenna, which, except for a 90◦ rotation, behaves like a dipole. Figure 5.20 shows the attenuation leakage caused by long seams or slots, assuming worst-case polarization. It is assumed that the slot has practically no depth (i.e., the thickness of metal is smaller than

5.4. ESD Protection by Box Shielding and Envelope Design l/2

Current flow

E

ΔV

≡

= Radiation

177

h

Figure 5.20 Radiation caused by a discontinuity in the shield.

the slot length and height), so no waveguide attenuation is occurring. The model is simple but conservative in the sense that it assumes an improvement ratio of 1/F (20 dB/decade) below the resonancy of the slot. Depending on the height of the slot, actual apertures may behave differently and give better attenuation (Fig. 5.21)

3

300

1 GHz 100

90

90

80

80

70

70 =h

60

=h

50

60

cm

50

cm

0c

40

m/ h= =1 0 c 1 mm m =h =3 0c m =h =1 m

=h

30 20 10 0 1 MHz

=3

=3

40

=1

3

10 MHz

30

100 MHz

30

Shielding effectiveness in dB

Shielding effectiveness in dB

1 MHz 100

Frequency 10 MHz 30 100 MHz

20 10 300

0 1 GHz

Frequency

Figure 5.21 Shielding effectiveness corresponding to slot leakage for different lengths l. Figures valid for a victim distance behind the slot > l. The driving dimension is l, the larger one, with h playing a lesser role.

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Application Example

Using this worst-case model we see that for an ESD field pulse with 1-ns rise time, corresponding to a reciprocal bandwidth 1/πtr = 300 MHz, a 10-cm slot shows an attenuation of 15 dB. In other words, regardless of how good the metal of this enclosure is, it will behave grossly as a 15-dB barrier around this frequency. Taking again the example of Section 2.6, where a bulk voltage of 600 V was induced in the exposed cable loop, a 15-dB attenuation (a 5.5 times ratio) would reduce the induced voltage to 110 V. ESD being a broad spectrum, reasoning on a single frequency seems an oversimplification. As already discussed in Section 2.6, the final voltage in the victim circuit results from a cascade of frequency-dependent mechanisms, slot leakage being one of them. But this approximation based on reciprocal bandwidth is very acceptable, as demonstrated by a more complete solution of this example in Appendix F. This being said, not all seams and slots are equally critical in a given housing. After all, cathode ray tube (CRT) or thin film transistors (TFT) displays have a huge opening caused by the screen, which does not necessarily make them more vulnerable to ESD. So when chasing shield openings, one must remember that holes and seams are mostly critical in areas that: 1. Are likely to receive an ESD. 2. Have sensitive components or wiring just behind. An ESD-hardened box does not have to be a 120-dB Faraday cage. A large slot should not become a designer’s hangup, if it is far from any critical circuit.

5.4.2. How to Maintain Shield Integrity with Metal Housings A metal housing already has the advantage of being a naturally efficient shielding barrier. All the efforts of the designer should be aimed at not spoiling this barrier with excessive leakages: •

•

All metal parts should be bonded together. Figure 5.22 shows how a floated item is a candidate for reradiation. Instead of being part of the continuous barrier, a floated metallic piece may become a capacitive coupler to the electronics inside. Notice that it is not the grounding (earthing) of such a part that is crucial; it is its equipotentiality with the other sides of the envelope. For cover seams, slots, and the like, how frequently they should be bonded is a matter of design objective. Figure 5.21 showed that a 10-cm leakage is worth about 15 dB of shielding against a 1-ns pulse. If the goal is closer to 20 or 30 dB, seams or slots should be broken down to 5 or 3 cm. For permanent or semipermanent closures, this means frequent screws or welding points or an EMC-conductive gasket. For covers, hatches, and the like, it means flexible contacts or electrical gaskets.

5.4. ESD Protection by Box Shielding and Envelope Design

179

Electronics VESD

Figure 5.22 ESD coupling via floating metal parts. Such parts encourage capacitive coupling, especially near the edges and protruding areas. If they were connected (equipotential) to the rest of the casing, they would not cause capacitive coupling.

The following is an organization of these solutions in an orderly sequence. As efficiency increases, cost increases as well. •

If only minimal shielding effectiveness is needed (0–20 dB range), the simplest technique is to have frequent bonding points and, for covers, short flexible straps made of flat braid or copper foil as shown in Figure 5.23. This solution is bonding only the hinged side, but if no sensitive items are located near the opposite side, it can be sufficient. For the opposite side, a wise precaution is to use a grounded lock or fastener. The λ/10 rule (bond every tenth of a wavelength) in Figure 5.23 implies that, for a 1-ns rise

< λ/10

Figure 5.23 Braided jumpers screwed on paint-free spots.

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Chapter 5 Design for ESD Immunity

•

time of the ESD, the distance between jumpers should be less than 0.1 m (since 1 ns corresponds to a bandwidth of about 300 MHz, i.e., a wavelength of 1 m). Keeping this 0.1-m bond interval, and assuming that no sensitive circuits are located closer than 0.1 m from this seam, a shielding attenuation of 15 dB can be expected. If more attenuation is needed, or if sensitive circuits are closer from the seam, bonding points spacing must be reduced. For instance, a 20-dB shielding objective requires that this distance between straps be only 5 cm, which may not be very practical. If bonding at the hinged side only leaves an excessive length of ungasketed seams, additional bonding points are necessary. In this case, the techniques of Figure 5.24 can be used. Figure 5.24(a) shows a few soft springs Mainframe

Cover + +

Contact plate must rest on a paint-free area (a) Captive copper springs are located along cover edges. When closed, they mate with abutting frame edge. Contact plates can be nickel or tin plated or made from adhesive conductive tape

Tinned plate (paint free) riveted or soldered

Fingerstock riveted, soldered, or glued, using conductive adhesive backing

Painted frame and cover

Low pressure

Medium pressure (25 to 250 g/cm)

(b) Partial bonding by knife-edge of regular finger-stock

Figure 5.24 Solutions to maintain shield continuity with painted metal boxes.

5.4. ESD Protection by Box Shielding and Envelope Design

181

scattered along the cover edges. For durable performance, the spring contact riveting must be corrosion-free, which may render this solution more difficult to apply than it would seem. A variation of this is shown in Figure 5.24(b), using sections of spring contacts called finger-stocks. Several types are available, such as low pressure, knife edge, and medium pressure. They require an adequate control of pressure by manufacturing tolerances, but they are extremely dependable. The third technique, shown in Figure 5.25 is an interesting alternative, taking minimal surface preparation. The grounding buttons or “sticky pads,” which are fairly

Figure 5.25 - More solutions to maintain shield continuity with painted metal box. (Courtesy of Chomerics Division of Parker Hannifin Corp.)

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•

• •

compliant to gap variations thanks to their spring loading, are mounted simply by press-fit or self-threading studs. For a higher grade of shielding (20–40 dB), a continuous conductive bonding of seams is necessary since a 40-dB attenuation at 300 MHz (λ/2 = 50 cm) would require screws or rivets every 0.5 cm! These continuous conductive joints are available in several forms and stiffnesses (Fig. 5.26). The hollow conductive elastomer gasket is less expensive to use because its elasticity compensates for large-joint unevenness and warpage. The price for this is a lesser contact pressure, hence higher resistivity. Therefore, it is best used as a solution for the low end of this SE range. Here again, good-quality mating surface can be made by applying copper or aluminum tapes, which create a good conductive area for local shielding or contact points. Surface resistance can be as low as a few ohms/square, with through resistances of 5–10 m for a 1-inch2 contact. Then a piece of masking tape is pressed over the stripe and the surfaces can be painted, after which the masking tape is peeled off. Metal braid, mesh-type gaskets provide higher shielding, at the upper side of the required SE range. Finally, if even more hardening is necessary, the ultimate solution is shown in Figure 5.27. It is the most efficient since 100% of the seam becomes a very good conductive joint. Besides its cost, it adds the need for a strong locking mechanism to ensure good, even pressure on all spring blades. This method is applicable to both rotating (hinged) or slide-mating surfaces. It is extremely rare that such extreme solution be needed just for ESD requirements.

Extrusion mounting Strip Metal mesh on elastomer core

Metal mesh (monel, copper, or aluminium)

Conductive elastomer extrusion (hollow tube)

Figure 5.26 Compressible conductive gaskets.

Rubber gasket and adhesive backing

5.4. ESD Protection by Box Shielding and Envelope Design

183

Plated area or riveted strips

Figure 5.27 Ultimate solution for hardening greater than 40 dB.

Independently of bonding, a reduction of the slot leakage can be obtained, at pratically no cost, by designing the cover edges so that they always offer a generous overlap, as in Figure 5.28. This acts by providing an attenuation known as waveguide beyond cutoff.

5.4.3. How to Make Shield Barriers for Plastic Housings Plastic housings provide no shielding whatsoever. Therefore, unless the PCBs and internal wiring can withstand the ESD threat (in that case an I-ESD) by themselves, the plastic must be made conductive. Several metallizing processes exist, which are summarized in Table 5.3 along with their average 2008 cost.

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Chapter 5 Design for ESD Immunity

(a)

(c)

(b)

(d)

Figure 5.28 Design of cover edges for improved EMI and ESD shielding.

Table 5.3 Average Cost Range of Conductive Treatments on Plastics Cost in $/m2

10

20

30

50

100

200

Surf. Res., /sq Copper paint (50 μm thick)

0.2

Nickel paint (50 μm thick)

0.3–0.8

Graphite paint (50 μm thick)

10–300

Silver coating 0.06 (13–25 μm thick) Hot zinc spray

0.05

Electroplating

0.1

Electroless plating (1 μm thick)

0.1

a

For conductive paints, figures are for product only, w/o application costs (labor, equipment etc.). For paints, significant variances exist depending on the number of layers, granular or smooth finish of the plastic surface, volume concentration of base metal etc. c For platings, nickel is assumed. Compiled 2008 figures from several sources (Parker/Chomerics, MAP, Acheson). b

Since, as discussed in Section 5.5.1, conductive coatings exhibit a rather mediocre absorption loss, they work mostly by reflection. Based on reflection loss only, Figure 5.29 shows the shielding effectiveness (SE) of thin coatings for a 30 cm distance from the source. If a 30- to 40-dB SE range is desired, especially against low-impedance sources such as furniture/ machine ESD, a conductive process with 1 /square or less must be selected. Another conductive process, the particles-loaded plastic has not been mentioned. This process gives to the plastic a volumic conductivity by inclusion of thin

5.4. ESD Protection by Box Shielding and Envelope Design 80

80

Arc sprayed zinc

Shielding effectiveness, dB

70

70 Electroless copper

60

1 Ω/sq.

50

60 50

Domain of conductive paints

40

40 Electroless nickel 30

30

10 Ω/sq.

20 10 0 1 MHz

185

20 10

3

10 MHz30

100 MHz 300

1 GHz

3

0 10 GHz

Frequency

Figure 5.29 Shielding effectivenesses of some conductive coatings.

filaments or particles, which gives absorption instead of reflection loss. This definite advantage, though, has downfalls: The lack of surface conductivity complicates the bonding of metallic components to the box skin, and concerning ESD, it allows direct discharges, with multiple, cascaded arcing through the plastic barrier. With a close look at the box design, some features of plastic housing can be turned into an advantage against ESD, and pitfalls can be avoided, which are summarized in Figure 5.30. Of course, for cosmetic and mechanical abrasion reasons, it is generally preferrable to have the conductive film on the box inner side.This may also prevent any possibility of direct discharge, such as the equipment may be submitted essentially to I-ESD, while keeping the benefit of a shielded envelope. One exception is electroless or electroplating, for which the nickel or chrome plating is an aesthetic and hard surface that can be on the outer side. In this case, D-ESD will apply. Some problems, though, are specific to metallized plastics: 1. If a conductive coating is relied upon to provide an overall shield, it must provide electrical continuity at the mating surfaces: top cover-to-base, side panels, and the like. Since, with a plastic product, a continuous gasketing is sometimes too expensive, an alternative is to use tight tolerances for the mating faces, by designing a cross section that provides naturally some contact pressure (Fig. 5.31), making sure the conductive coating extends: a. Deep enough over tongue-and-groove side to make a positive contact. b. Yet not beyond the groove centerline because it would then permit direct ESD arcing in some areas that were not reachable before.

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1.5 – 2.5 cm

Poor

Better

(a) A tongue-and-groove design of plastic edges will provide a longer path against ESD reradiation or a longer creepage against ESD arcing. Plastic

6 mm (1/4'') will arc above 6 kV Metal part or conductors

30 mm (1 1/4'') won't arc below 30 kV

(b) Acting on wall thickness + separation distance to nearest conductive part inside to increase gap breakdown voltage. Ventilation

ZAP

Metal parts or components

ZAP

Plastic Plastic (c) Avoid long protruding screws inside: they act as capacitive coupling tips, or even as secondary are sources. For ventilation, prefer slots with slanted, or labyrinth shapes.

Figure 5.30 Plastic covers design for better ESD immunity. Internal metallic parts reachable by an arc can be protected by artificially increasing the path length.

5.4. ESD Protection by Box Shielding and Envelope Design

187

1

1

2

2

Avoid burring at the penetration of selftapping screws

Figure 5.31 Abutting parts with metallized plastics. Provide at least one screw every 10 cm.

2. Use a paint or coating process that has good resistance to abrasion, tolerating a reasonable number of closures and frictions of the mating edges. Certain coatings have a poor adhesion to their plastic substrate and poor abrasion resistance (11). 3. If, on the basis of its plastic enclosure, a product has been declared a “class II” isolation with respect to electrical safety categories (e.g., IEC Standard 435), one should verify that the metallization does not turn it into a “class I” isolation device. Except for these particular aspects, all that has been said for metal housings (slots, seams, bonding, etc.) applies to metallized plastic as well. Here, too, surface conductivity can be improved locally by using copper or aluminum tapes.

5.4.4. Treatment of Shield Openings Besides the joints and seams, several large holes may exist in the housing for: • • • • •

Displays Cooling Cable penetrations Fluid penetrations Components shafts and the like

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These apertures create shield discontinuities with the same leaky properties as seams. In strict terms of EMI, they should be treated to provide SE performance equal to or better than the one required for the whole box. However, ESD bears some specific aspects. It is rather unlikely that people will discharge frequently near a display window or a cooling aperture. Yet, if the packaging is such that (a) likely discharge points exist near these functional apertures and (b) vulnerable circuits are located right behind, then, apertures should be treated with wire mesh, conductive glass, and the like or a dependable grounding path must be provided for the discharge current to flow on the box skin, not reaching the inner parts. Switches, potentiometers shafts, and the like can be treated, if necessary, by grounding fingers or conductive bushing as shown in Figure 5.32. Switch locks pose a special problem since they are, by their very nature, designated targets for the tip of a hand-held key, which acts as a discharge enhancer inside a key socket that is poorly grounded, if at all. Therefore, the key slot ends up making an arc duct to the electrical parts of the lock. To make things worse, the lock is probably the first thing on which the user will discharge. Special antistatic locks have been developed, like the one in Figure 5.33 in which the rotating barrel makes a good electrical contact with the main body, which in turn has a large contact area with the mounting panel. Light-emitting diodes and all sorts of indicator lights, as shown in Section 2.2, are another Achille’s heel in the housing. Although feasible in ATTENTION !

Cover

ESD

IESD

Equipment chassis or test ground plane Solutions: • Connect the switch neck to the metal (or metallized plastic) cover, using a small spring clip or mesh washer. • Use a plastic toggle • Ground the switch neck to the PCB ground, using a short bracket (less preferred option)

Figure 5.32 ESD penetration via switches metallic toggle.

5.4. ESD Protection by Box Shielding and Envelope Design

189

Figure 5.33 Example of antistatic switch lock. (Courtesy of Illinois Lock Co.)

Panel mount

PCB mount

Figure 5.34 LED protection by an insulating lens. This CLIPTITE from Visual Com. Co. can withstand 16 kV.

sophisticated military equipment, for instance, shielding a LED or small light bulb is cumbersome. A simpler approach consist in merely increasing the breakdown voltage by adding an insulating, transparent lens that can resist to 15 kV or more, depending on the ESD constraints (Fig. 5.34). Cable penetrations will be addressed in Section 5.5, since the cable shield (if any) termination at the housing entry is a key factor in ESD immunity.

5.4.5. Nonmetallized Plastic Boxes Section 5.4.3 covered the topic of conductive plastics, that is, merely turning a plastic skin into a conductive one, then treating it more or less like a metal

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enclosure. However, an electronic equipment does not necessary have to be put in a conductive shell to resist ESD. Carefully designed PCBs and well-decoupled I/O ports can allow a product to function trouble free under at least all but the highest ESD threats, like severity levels 1, 2, and 3 of IEC. The key to the success, in this case, is to make sure that only I-ESD is feasible, and no direct arcing can reach a critical part inside. This implies: •

•

Using exclusively discharge-proof, nonconductive shafts, toggles, indicators, and the like with a sufficient dielectric strength to resist against a D-ESD. Keeping away from the openings (cooling, seams, assembly joints, etc.) any active component, bare wire/trace, or internal metallic part that could be reached by arc. This applies to obvious parts such as magnetic or laser heads, discrete transistors, ICs, metal cans, and the like, but also to passive elements such as internal brackets, screws, and the like. Use a minimum 1 mm/kV as a clearance rule. The creeping capability of an ESD arc is amazing, and even reasonably tight-fit, abutting joints can still allow an arc sneaking inside the box. If such clearance is impossible to ensure for the highest ESD voltages, use a labyrinth design for the openings, as shown in Figure 5.35. More details on arcing distances between metal parts are given in Appendix C.

With non-metallized platice housings, the option remains to use compartment shielding over some selected areas of the PCB (see Section 5.2.4). Summary of ESD Protection Measures at Mechanical Packaging and Box Level •

•

• •

For metal housings: • Bond together every metal part (floating items are candidates for reradiation) • Avoid long seams and slots: a 10-cm empty seam is leaky at upper frequencies of ESD. Break them into smaller slots or use conductive gaskets and waveguide beyond cutoff effect. For plastic housings: • Apply conductive coating with ≤ 1/sq surface resistance, then treat like a metal housing. • Avoid long screws protruding inside. • Try to take advantage of air gap and plastic thickness (works for you at no cost). Respect shield integrity at cable entry points. Internal parts location: • Locate more sensitive subassemblies and wiring deep inside, far from housing surface and openings. • locate less sensitive elements outboard from the above, acting as passive barriers.

5.5. ESD Protection of External Cables and I/O Ports

191

5.5. ESD PROTECTION OF EXTERNAL CABLES AND I/O PORTS External cabling is a greater problem. Due to their direct illumination during ESD, cables become unintentional, but efficient antennas, converting the radiated field into induced voltages and currents. Figure 5.35 shows a summary of what happens to external cables during an ESD event. To combat the effects of this ESD coupling, two approaches are available, which depend on the nature of the external cables and of the equipment enclosure. If the external cables are shielded (maybe for other EMC reasons, and probably not just against ESD), they will perform efficiently against ESD, provided some precautions are taken, the same as those used for good RF shielding results. If the system external cables are not normally planned to be shielded, and the equipment box is eventually plastic, there is no sense in shielding them for meeting an ESD immunity level. In this case, the ESD-induced pulses could penetrate the equipment by the external cable conductors, and they must be filtered, or eventually clamped, at the cable entry port.

ESD

2

A

B

1 1

2

1

C

INDUCTION

Field radiated around discharge zone illuminates the cables, inducing CM and DM currents.

2

CONDUCTION

Part of the direct discharge current returns to local ground by interconnect cables (CM currents if exposed wires, or transfer-impedance coupled noise if shielded cables).

REMARK: if units A, B, C, etc... are from different types, the system will be as weak as the unit having the weakest ESD level.

Figure 5.35 Contributions of external cables to ESD coupling.

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Chapter 5 Design for ESD Immunity

5.5.1. External Cable Shielding Although all cables are potential ESD coupling vectors, flat cables are at the top of the list because they are generally untwisted, unshielded, and terminate on plastic connectors right on PCB inputs. They also offer a larger, more even stray capacitance to ground than multipair cables, for instance, where wire pairs are convoluting randomly into the bundle. In a well-documented set of experiments, Palmgreen (15) has measured the voltage induced in flat cables by an ESD applied to the cabinet where these cables were connected. The highlights of her study are described hereafter. The test setup comprised a peripheral cabinet connected by a cable to the control cabinet. The sensing line in the cable was terminated in its characteristic impedance at the peripheral cabinet end. The receive end was connected to the 50- input of a Tektronix storage oscilloscope. This latter was shielded by placing it inside the cabinet. Both cabinets were grounded through the green wires of the local ac power ground. Figure 5.36 shows the details of the setup. The capacitor Cd , is charged by a 10-kV source, then discharged through resistor Rd to the peripheral cabinet, via a ball air gap that is adjusted for arcing once or twice per second (at least 22 charging time constants in all cases). The oscilloscope records the noise voltage induced in the signal conductors by the discharge. This 3 M, company-internal, ESD test with 400 pF/100 was used to compare four families of ribbon cables. As expected, the electromagnetic field of the discharge coupling directly into the unshielded cable 3365, produced noise voltages that were off-scale, even with oscilloscope input attenuators. The ground plane of 3460 (50 conductors wide = 2.63 inches or 6.67 cm) reduced significantly the ESD-induced voltage, but levels of 150 V on an edge conductor and 40 V on a center conductor are still more than enough to cause false data signals and eventually circuit damage. The double-side shielded 3517 cable exhibited a greatly reduced voltage with 3 V on the edge conductor and 0.4 V on the center conductor of a 50-wire cable. The experimental cable, with an improved shield, demonstrated even lower noise voltage with only 0.4 V on the edge conductor and 0.2 V on the center. Both the shielded and ground-plane versions showed a difference in noise levels on edge and central conductors, thus demonstrating the effect of shield construction. The voltage is maximum at the edge, decreasing proportionally with distance when moving toward the center. This edge-to-center difference can be attributed to the sharp bend in the shield where it is wrapped around the cable edge. The magnetic field produced in the shield by the discharge is concentrated at this sharp angle such that more field is present in the internal shield-to-wires space. When the distance between the two cabinets was increased, the noise pickup in the cable also increased (Fig. 5.37) until cable length reaches 4 m, corresponding to λ/2 for the air discharge risetime. The dependence of longitudinal shield transfer impedance on total length between the cabinets was responsible for this.

193

5.5. ESD Protection of External Cables and I/O Ports Metallic “target” box

Shielded cabinet

ESD simulator

Oscilloscope

100 Ω R = Z0

400 pF

Filter HV source 5 to 15 kV

Flat cable under test Connector under test 3365

Dielectric

Cable (L = 2 m)

Conductors

Dielectric

3469

Voltage induced by 10 kV ESD (volts) on conductor Edge

Center

> 500

> 500

3469 ground plane

150

40

3517 two-side shield

3.0

0.4

EXP : full shield

0.4

0.2

3365 unshielded

Ground plane 3517

Jacket Cable

EXP

Shield NOTE : For shielded versions, the shield was perfectly grounded to cabinet

Figure 5.36 Test setup used in Ref. 15 to measure ESD-induced noise into flat cables. Table indicates the noise pickup by 2 m of various flat cable types, for 10-kV ESD.

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Chapter 5 Design for ESD Immunity

(Shield is perfectly grounded to boxes, both ends) Type cable # 3517 Edge conductors

10

Induced voltage

8 15 kV 6 10 kV 4 5 kV 2 0

0

1

2

3

4

5

6

7

6

7

Cable length (m) Center conductors 1 15 kV Induced voltage

0.8 10 kV 0.6 5 kV

0.4 0.2 0

0

1

2 3 4 5 Cable length (m)

Figure 5.37 Flat cables experiment: Noise voltage as a function of cable length and discharge voltage. (Source: Study by 3M/USA.)

The ESD current flowing over the shield causes an increasing IR drop and Zt I along the shield as the cable becomes longer, producing a greater voltage to be coupled with the signal conductors. Conversely, increasing the shield conductivity, through the use of more conductive materials, decreased the cable’s ESD sensitivity. Even with identical construction, except for the number of conductors, the cable with more conductors (i.e., a wider, more conductive shield) exhibited less ESD noise pickup than the narrower cable. The benefits of a well-shielded cable are never realized if the shield is improperly terminated. Three requirements must be met in a connector for proper shield termination: 1. A very low-impedance path to ground 2. A 360◦ metallic hiding of the conductors exposed at the termination

5.5. ESD Protection of External Cables and I/O Ports

195

3. A high enough conductivity of the connector body to remain an equipotential surface

1.25 V

0.6 V

18 16 14 12 10 8 6 4 2 0

Voltage induced on middle connector in volts

2.0 V

Shield clamped directly to cabinet with 360° contact

16 V

22 20

Shield soldered to connector, 360° contact between connector and cabinet

4 2 0

?

Drain wire ground

18 16 14 12 10 8 6

Shield not connected to cabinet

Voltage induced on middle connector in volts

22 20

Shield soldered to connector, but connector in contact with cabinet through jack screws only

The results from testing several variations of shield termination at the cabinet end of the 3517 cable are shown in Figure 5.38. First, the shield was brought very close to the connector, then cut off, as might be done sometimes with the idea of “opening ground loops.” The voltage on the center conductor of 3517 jumped to more than 500 V. Using a big gage drain wire to ground the shield to the cabinet reduced the ESD pickup to 16 V on the center conductor. When the shield was soldered to the SCOTCHFLEX sub-D metal shell connector, with insulation displacement (3 M product), and a solid contact achieved between the connector and cabinet, the noise voltage went down to only 1.25 V. In this same configuration, but with the contact between the cabinet and connector occuring only at the jack screws as might occur after aging or cosmetic painting, the noise voltage increased to 2 V. The lowest noise pickup, 400 mV, was obtained with the shield clamped directly to the cabinet with 360◦ contact using 3 M angle clamps. The increase in ESD susceptibility when the shield was grounded at only one end, or connected through a drain wire, is due to the field concentration at the gap in the shield. This intense field couples an increased voltage into the unprotected portion of the exposed cable. The nontermination of the shield provided neither a low-impedance path to ground nor a hiding of the conductors. Terminating the shield through a heavy-gage drain wire (braid strap) can reduce the impedance to ground but not adequatly hiding the exposed wires. From these tests, we can conclude that to provide optimal ESD immunity, noise-sensitive circuitry should use the central conductors of a shielded flat cable. Care should be taken to minimize the shield resistance by (1) keeping the length of the cable as short as possible, (2) using cables with highly conductive shields, and (3) providing low resistance, 360o shield connections to the equipment frame.

Figure 5.38 Flat cables experiment: effect of cable shield termination on ESD-coupled voltage.

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Chapter 5 Design for ESD Immunity

Unshielded and ground-plane cables, such as 3365 and 3469, provide little or no ESD protection. One of the most remarkable aspects of Palmgreen’s findings is that, just as for coaxial cables, or for any shielded envelope, until the shield is integrally bonded to the frame, what is seen is not the quality of the shield itself but to what extent it is ruined by the more or less detrimental bonding impedance. We could say that unless the shield is integrally bonded, the shield transfer impedance Zt is overruled by its termination impedance (pigtail or else), which for the nanosecond rise times of concern can be several orders of magnitude larger than Zt . In fact, reasoning on transfer impedance of shielded flat cable could be misleading if one adheres strictly to Shelkunoff’s definition of Zt . Since, in flat cables, the shield is not part of the intentional signal path, we should instead speak of the differential transfer impedance Zt d, that is, the ratio of the differential voltage appearing between two wires of a multiconductor cable to the current flowing on the protective shield (discussion and practical data on Zt d can be found in Refs.11 and 16). In the case of ESD, the empirical recipes about cable shields (that is, thou will ground the shield at one end only to avoid ground loops), which can be justified at audio or low frequencies, become irrelevant. To reduce ESD pickup, a cable shield must be bonded to each housing that it penetrates. The argument that a floated shield will not allow the ESD current to flow and, therefore, will avoid coupling, does not stand a more thorough analysis, nor the conclusions of practical experiments. The floated end of the shield reaches several hundred volts of common-mode voltage and will reinject some of it by capacitive couping (more precisely, transfer admittance) onto the inner wiring. If a system is vulnerable to low-frequency ambient noise (such as ground potential differences between cabinets) and must also run trouble-free in possible ESD conditions, the dilemma is the following (typical of analog or instrumentation links): 1. If the protective shield is grounded at one end (generally the receiver end), the shield will not create a parasitic low-frequency ground loop, yet will perform as a Faraday shield against a low-frequency electric field that may be there all the time. However, it will leave the system unprotected (maybe even make things worse) during a casual ESD event. 2. If the protective shield is grounded at both ends, it will protect against ESD a few times a day or week but may create a permanent low-frequency ground loop problem. With such low frequency constraint choosing between the two evils is a matter of quantitative approach to decide which one can be tolerated. A more engineered solution is to immunize the system against both threats: Optimize against low-frequency, permanent threat by keeping the 0-V reference (PCB ground) isolated and float the shield from the chassis, dc-wise, but restore an HF ground connection of the shield via a few nanofarad ceramic capacitors (preferrably leadless).

5.5. ESD Protection of External Cables and I/O Ports

197

Optimize against high-frequency, ESD, and RF threats by having a good-quality cable shield bonded at both ends to machine frames. The low-frequency common-mode noise will be dealt with by common-mode baluns, signal transformers, differential drivers/receivers, and the like. Assuming its grounding can be done reasonably well, the type of cable shield relied upon for ESD immunity must be selected carefully, looking at qualitative construction details of Figure 5.39. One relevant figure of merit is the shield transfer impedance, Zt . If a cable exposed to ESD is of the coaxial type, the noise appears due to the ESD-induced current coupling via the transfer impedance of the braid. (Details of this mechanism can be found in Ref. 17 and in several works by Vance (18). We show simply in Figure 5.40 some typical values of Zt . This important parameter is defined as: Zt (/m) =

Vi (per meter length) Ishield (external)

(a) The optical coverage of the braid (area of copper/total area) is too small and is leaky at high frequency. (a) Poor

(b) The metallized film does not make contact at the closure. The long seam will be leaky when it approaches λ/2 of the highest ESD spectrum. In addition, the drain wire cannot make a dependable high-frequency bonding of the shield.

Drain wire (b) Poor

(c) The metallic continuity is ensured. However, since there is no outer metal surface, a 360° shield bonding cannot be made and the drain wire is still there. Drain wire (c) Better (d) Labeled "best" because the homogenous shield wrap or thick braid (optical coverage>90%) provide a good shield integrity and permit perfect shield bonding at the ends. (d) Best

Figure 5.39 General cable shield aspects regarding ESD immunity.

(5.4)

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Chapter 5 Design for ESD Immunity

10 Transfer impedance Zt in Ω / m

1

RG-17/U alum. screen

0.1

RG-58/U single braid 0.01 RG-55/U double braid 0.001

100 μ 10 k

Coaxial semirigid

2 braids 1 μmetal 100 k

1 MHz

2 braids 1 μmetal 10 M

100 M

1G

Figure 5.40 Values of the transfer impedance for typical coaxial cables, normalized to 1 m length.

where Vi is the voltage appearing inside the coaxial cable, between the center conductor and shield and ishield is the shield current, caused by the external coupling. Illustrative Example (Fig. 5.41)

An 8-kV personnel ESD, with 330- source resistance, is applied to a desk terminal. Using a current probe, it has been found that about half of the ESD current was returning to ground via the coaxial shield and the other machine. The noise coupled inside the coaxial can be derived from the transfer impedance, using the following, simple calculation: •

•

Portion of ESD current flowing along the coaxial cable shield: • 50% of 8000 V/330 = 12 A, with rise time tr = 10 ns (slowed down by the total discharge loop inductance) • Second corner frequency = 1/πtr ≈ 30 MHz • Zt at 30 MHz for RG58 (per Fig. 5.43): −10 dB/m = 0.3 /m Vi inside the shield = (0.3 /m) × 2 m × 12 A = 7 V (not a damaging voltage but can cause logic errors

5.5. ESD Protection of External Cables and I/O Ports

199

ESD

2 meters of RG 58 coax

IESD

Figure 5.41 Numerical example: ESD coupling onto a coaxial video cable.

Remedies

Use cable with lower Zt (reinforced braid), which can reduce Vi to less than 0.7 V. Add an overall shield to the RG58 shield, and ground this second shield at box entries. Add ferrite toroid (at least two passes through the window); by artificially increasing the external loop impedance, this can reduce the induced voltage by three times (10 dB). Finally, when a system, installed with unshielded cables suffers from ESD problems, instead of replacing all cables with shielded ones, which can be a long-term answer, a field fix can be arranged by using a zip-on shielded jacket over the whole bundle (Fig. 5.42), making sure the shield terminations are made by integral collars or clamps. By default, very short straps or pieces of braid can be used, provided they always stay close to the unprotected segment of cable. Grounding by wire must be avoided. Since it provides the transition between the cable shield and the machine envelope, the bonding of cable shields to machine frame interacts with the box shield integrity addressed in a former section. A most direct bonding of the cable shield to the outer skin of the equipment box will prevent the ESD currents carried by the shield from reradiating inside (Fig. 5.43). A quantitative example of this, reminiscent of the 3 M experiment, is seen in Figure 5.44 with the drastic improvement when a good shield-to-box metallic contact is achieved. Several ways of achieving this continuity are shown in Figures 5.45–5.48. Ferrite Toroids, ‘‘the Poor Man’s Shield’’ A ferrite toroid over an external cable cannot, by any means, match the 40 to 60-dB attenuation of an actual, well-braided cable shield. However, although this heavy, ugly bulge on the cable looks more like a desperate last minute fix, it provides a 6- to 10-dB reduction of the ESD coupling to the cable. This may be sufficient in some cases, with a solution that is inexpensive and easy to add on an existing cable without any hardware adjustment.

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Shielding performance Frequency in MHz .01 100

.10

1.0

10

100

1000 100

80

80

60

60 SHX2 = 0.4 mm thickness

40

40

20

20

.01

.10

1.0 10 Frequency in MHz

100

Attenuation in dB

Attenuation in dB

SHX4 = 0.7 mm thickness

1000

Attenuation shown as the difference between RF induced on an unshielded cable and the same equipped with Zippertubing.

Figure 5.42 Shielded zip-on jacket. The shield is a knitted wire mesh with a continuous grounding flat braid inside. Sturdy mounting clamps allow an integral bonding. (Courtesy of Zippertubing Co.)

5.5.2. ESD Hardening of I/O Ports In many applications, external cables are unshielded, and must remain so. Therefore, whether the box is metallic or not, the penetration of ESD-contaminated wires inside the device is a serious threat, which must be controlled at the point of entry. Filters or transient voltage suppressors (TVS) should be placed at the connector receptacle itself, or the nearest PCB area.

5.5. ESD Protection of External Cables and I/O Ports

Equipment shield

201

Equipment shield

Shield on cable

Current flow

Current flow

Preferred method of grounding

Figure 5.43 Grounding of cable shield versus ESD excitation. On the left, grounding the shield through a connector pin allows ESD-induced current to enter the equipment, where it reradiates.

(1) Shield carried through same pin as ground Wire (for example, RS 232 pin #01) ESD run fail level: 1800 V (A) External field picked up by stripped section of the cable (B) ESD current reradiation inside (C) Common impedance coupling by ground wire polluted from ESD (D) Heavy crosstalk in connector due to ESD current carried by ground pin

(2) Shield bonded to chassis via a dedicated short strap, using a jack screw ESD run/fail level: 4000 V Couplings (B), (C) and (D) reduced. Coupling (A) remains.

(3) Metallic connector shell 360° shield clamp, part of connector ESD run/fail level: 10,000 + V

Figure 5.44 Practical case of shield termination influence on ESD susceptibility.

202

Chapter 5 Design for ESD Immunity Flat cable

Metal shield

Side plate

Strain relief grips

Dimples for positioning “D” shroud Metal to metal contact via cable shield to enclosure Metal “D” shroud (a) by shielded connector

Figure 5.45 Proper bonding of flat cable shield via the metallic connector strain relief. (Courtesy of Alpha Wire.)

Figure 5.46 Direct bonding of flat cable shields via L clamps on cabinet frame. (Courtesy of 3M.)

5.5. ESD Protection of External Cables and I/O Ports Cable clamp Strain-relief bar

Cable

Captive screw

Saddle washer

Nut Flange gripper

Conductors Braid

Fillister head screw

Figure 5.47 Nickel-plated connector backshell with integral braid retention. (AMP Inc.)

Clamp PVC Jacket

(a)

Shield

(b)

(a) and (b) are correct ways to terminate a shielded cable at box entry (360 contact) when no feed-through connector is available (applies to shielded harness and power cords)

(c) If aesthetic or accessibility reasons prevent a straight panel-thru mounting, a doghouse can be built to recreate a shield integrity internally. At installation the metal bushing is clamped over the cable shield first, then the cable is pulled through the hole and the bushing is secured from inside the cabinet. (c)

Figure 5.48 Shielded cables through-grounding, without connectors.

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Chapter 5 Design for ESD Immunity

When an I/O port receives unshielded cables, two cases have to be considered: •

•

No direct discharge (contact or arc) can access the terminal pins, or screws, as the like. Therefore, only induced pulses, whose duration does not exceed a few nanoseconds can penetrate the device. A filter with a good attenuation above ≈ 30 MHz is generally sufficient. The terminals are exposed to both induction coupling as above and incidental direct discharges, where the full ESD pulse waveform could be injected into interface circuits. In this case, filtering is needed for error-free response to the short pulses, and TVS are a must for a no-damage criteria.

These two issues are examined next.

5.5.2.1. Filtering Short ESD-Induced Pulses

The simplest filtering is made by low-value ceramic capacitors, preferably the leadless (SMT) style. If leaded, they must be trimmed to the shortest possible length (Fig. 5.49). A 800-pF disk capacitor with just 2 × 2mm lead length starts loosing its efficiency at 100 MHz to become practically useless above 300 MHz (Fig. 5.50). Filtered connectors for panel mounting or PCB mounting (Fig 5.55) are very efficient above a few tens of megahertz, attenuating the bulk of the ESD frequency spectrum. For the more expensive types, each pin is constructed as a Pi or T filter, giving a substantial attenuation in the VHF range (30–300 MHz). Cheaper models use miniature SMT capacitors mounted in the receptacle housing. They exist for most connector styles (Sub-D, Micro-D, USB, IEEE-1394, Ethernet/RJ45, etc.). For PCB mounting, if the size, weight, or cost of filtered connectors are prohibitive, economical substitutes can be made with surface-mount capacitors or planar arrays, close from the connector footprint (Fig. 5.51). Each incoming trace is decoupled to the PCB 0-V reference, or better to the chassis, if there is a chassis-connected copper land, with maximum precautions to avoid parasitic inductances (Fig. 5.52). However, this is only a one-pole (20 dB per decade) attenuation slope (see discussion on filter attenuation below). The result is that if the cutoff frequency requirement imposed by the necessary I/O signal bandwidth is too high, say 50 MHz, for instance, it will provide barely a 6 times (16 dB) reduction at 300 MHz. This may not be sufficient for an error-free objective against a 10–100 V induced ESD spike. Steeper attenuations are obtained at PCB level with inexpensive T filters made of three-lead ceramic capacitors and small ferrite beads.Three-lead capacitor technology, sometimes nicknamed the “poor-man’s feedtrough,” is a simplified equivalent of the coaxial concept, which reduces parasitic inductance effects. Such components are available in leaded or surface-mount versions. Since, in general, a filtering of I/O ports is needed anyway against RF emissions and susceptibility, the matter is to also optimize this filtering against short

5.5. ESD Protection of External Cables and I/O Ports

205

220, 470 or 820 pF

PCB I/O traces

I/O traces interruped (a) Ordinary ceramic disk

(b) Three-terminal ceramic disk

Copper land grounded to chassis

Common ground land

(c) Regular SMT

Interrupted traces

(d) Three-terminal feedthrough SMT

Figure 5.49 Simple capacitor filtering with ceramic capacitors near PCB I/O connector. The common ground must be a wide copper land, or ground plane. (a) Ordinary ceramic disk, (b) three-terminal ceramic disk, (c) regular SMT, and (d) three-terminal feed through SMT.

ESD pulses. Before deciding which type of filter is appropriate, a brief reminder on filter attenuation is in order. The basic schemes for the filter action appears in Figure 5.53 : An unwanted signal appears in a circuit having a source and load resistances Rs and RL, where a capacitor (left) or a ferrite (right) can be added. In this circuit: •

The filter capacitor is a shunting device: To attenuate a signal at frequency Fx , the capacitor impedance ( 2πF1x C ) must be lower than Rs //RL . The cutoff frequency (start of the attenuation curve) is Fco =

1 2πC·Rs //RL

(5.5)

206

Chapter 5 Design for ESD Immunity Feedthrough 820 pF

dB Atten. in 50 Ω 50 820 pF disc leads 2 mm Ltotal ≈ 5 nH

40 30

820 pF surf. mount Ltotal = 1,2 nH

20 10 0

F 1 MHz

3

10 MHz

30

100

300

1 GHz 3 GHz

Figure 5.50 Attenuations with single capacitor filtering (given for a 50-/50- test configuration).

D connector mounting flange Ceramic array 1

6

Detail of MLC stack

PCB 0V Ceramic capacitor (short leads) between 0 V and frame ground "Frame ground" copper land on the PCB, not connected to 0-V

Figure 5.51 Instead of individual capacitors, planar multilayer capacitor array can filter all the lines at once, If the designer wishes its PCB 0 V being isolated from chassis, a discrete 10-nF ceramic can be inserted in between.

Attenuation is given by 2πFx C(Rs RL ) A(dB) = 20 log 1 + Rs + RL ) •

(5.5a)

The ferrite (or inductor) provides series loss: To attenuate a signal at frequency Fx , ferrite impedance Zf must be greater than Rs + RL . The

5.5. ESD Protection of External Cables and I/O Ports

1

4

2

5

3

6

207

Chassis

BAD Too much parasitic inductance, shared in common to chassis ground.

Too long grounding traces for pins 1, 2, 3. Dissymmetry with 4, 5, 6.

0V BETTER Shorter, and identical capacitors grounding connections. Common ground ring.

Figure 5.52 With individual decoupling capacitors, frequent layout mistakes are made, which create parasitic inductances and dissymetries, spoiling the filter efficiency above tens of MHz.

cutoff frequency (start of the attenuation curve) is the one for which Zf = Rs + RL . Attenuation is given by A(dB) = 20 log 1 +

Zf Rs + RL

(5.6)

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Chapter 5 Design for ESD Immunity

For a single, short pulse like ESD, we must remember that the attenuation of a filter is not the one found for a sinewave. A single pulse has a spectrum that exists also in the low-frequency region, below the filter cutoff frequency. This region is not attenuated and is responsible for the residual pulse. Provided that the pulse duration Td meets the condition 1/(πTd ) > Fco , the attenuation of a linear filter can be approximated by 1 A=1+ (5.7) (2Td B10 where, Td = pulse duration at 50% amplitude B10 = 10 dB bandwidth of the filter This 10-dB bandwidth depends on n, the number of stages, and can be derived as follows (19): For n = 1 (single capacitor or inductor) B10 = 3Fco n = 2 (capacitor and inductor combination) B10 = 1.8Fco n = 3 (Pi or T or combination) B10 = 1.4Fco Example Assume a configuration with Rs = 100 , RL = 1000 (thus Rparallel = 90 ). •

A single 100-pF capacitor filter will provide a cutoff frequency [Eq. (5.5)]: Fco =

1 = 18 MHz 2π·90·100·106 ·100·10−12

Against a 100-MHz sinewave interference, its attenuation is [Eq.(5.5a)] A = 1 + 2π

(100 × 106 × 100 × 10−12 ) = 6.6 equivalent to 16.5 dB 90

However, against a 3-ns ESD-induced pulse, the reduction [Eq. (5.7)] will be A=

1 = 3, equivalent to 10 dB 2 × 3 × 10−9 × 3Fco

5.5. ESD Protection of External Cables and I/O Ports • •

209

A ferrite with Zf = 600 at 100 MHz, in this same Rs /RL configuration would bring no attenuation, since Zf < Rs + RL . Considering that the Rs , RL . configuration is hybrid (low Rs , high RL ), ferrite + capacitor combination,with capacitor looking toward the 1000- side will achieve a better attenuation. The new Fco being approximately 10 MHz, the new attenuation with n = 2 will be A = 10, that is, 20 dB.

The amount of capacitance must be compatible with the bandwidth necessary to useful signals carried on each line. Capacitors will be preferrably mounted in a common-mode arrangement, decoupling each trace to chassis ground (Fig. 5.54). In the case of differential or isolated inputs, if a capacitor C is decoupling each line to chassis, the incoming differential pair will see C/2. To get the full benefit from these decoupling devices, these simple rules apply: • •

•

•

•

Compute the maximum capacitance tolerable without signal distorsion. Connect all the ground terminals of the capacitors (or arrays) to a copper land surrounding the connector area. Even with PCB 0-V reference grounded to chassis, this land should be preferably distinct from the 0-V plane, and connected with a short tab to the nearest chassis point. As a result, the ESD currents diverted by the filter will sink to the frame ground, while causing the least possible disturbance on the board. Keep these capacitor tolerances tight, if used on true differential lines. This will prevent the risk of common-mode conversion by capacitive unbalance, not only for ESD but for all RF emission or immunity aspects. Tight tolerances will also limit the deterioration of circuit balance for the useful signal. Check for the surge voltage withstanding capability of the capacitors. In some environments, they must survive temporary kilovolt surges, exactly as for the class Y capacitors used in ac main filters. This is especially true with isolated inputs or PCBs with floating signal reference; select COG/NPO ceramic dielectric. Make sure that all I/O lines have been decoupled in the same zone. One single line (even a dormant one) left unfiltered can couple with the others.

For computing the maximum value of tolerable common mode capacitive filtering, Figure 5.54 shows that, to avoid degrading a useful signal having a necessary bandwidth Fmax , we must keep: 2Xc RT

(5.8)

210

Chapter 5 Design for ESD Immunity Impedance range for good EMC ferrites Z (Ω) 1000 RS

3-dB borderline for ferrite insertion loss in 100 Ω – 100 Ω

100

30

3-dB borderline for capacitive insertion loss in 100 Ω – 100 Ω RS

10

RL

pF

30

0p

F

Impedance range of SMT decoupling capacitors for typ. signal lines

RL 1

1

3

10

30

100

300

FMHz 1000

Major spectral domain for induced ESD pulses

Figure 5.53 Comparison of decoupling capacitors vs. ferrite impedance ranges.

where Xc = impedance of one capacitor at frequency Fmax RT = total parallel impedance of victim R load //R source , or R load //Z 0 (for a long line) Z0 = characteristic impedance of the incoming wire pair For a good pulse integrity (distorsion barely perceptibe), this can be translated as: {1/(2πFmax (C/2)} ≥ 3RT

(5.8a)

that is, Cmax = 100/(Fmax RT ),

for C in nF and F in MHz

or, Cmax = 0.3tr /RT with tr rise time of useful signal, in ns and C in nF. This condition is shown on Table 5.4, calculated for some typical digital data pulses.

5.5. ESD Protection of External Cables and I/O Ports

211

Lf

Lf

0V Self-inductance of wiring

Decoupling capacitors style

Feedthru, or filter-connector, or surface mount ceramic disk very short leads

∗ If floating 0 V (needed to open low frequency ground loops with analog links): The capacitors still maintain a galvanic isolation from earth at low frequency (for instance: 300 pF ≡ 0,5 MΩ @ 1 KHz). But will sink HF current to chassis : (For instance : 300 pF ≡ 5 Ω @ 100 MHz). ∗ If 0V grounded to chassis (typical case for digital electronics) : The capacitors, teamed with Lf, will deroute HF currents to ground. Useful signal:

OK

C

Z0 Characteristic impedance

RC C

Too much capacitance

Figure 5.54 Configuration of common-mode capacitors for VHF and ESD decoupling. Table 5.4 Maximum Common-Mode Capacitor Values for VHF and ESD Decoupling Useful Signal

Low-Speed Interface (typ.)

CMOS TTL

HC/AC

Fast LVDS

Rise time tr Bandwidth Za Cmax for good pulse integrity Cmax for marginal pulse shape

0.5–1 μs 300 kHz 120 2200 pF

50–100 ns 3 MHz 3–500 150 pF

7 ns 50 MHz 100 20 pF

3.5–1.5 ns 100–230 MHz 50 15 pF

6800 pF

430 pF

60 pF

33 pF

a

Z-differential impedance = Rload //Rsource , or Rload //Z0 .

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Chapter 5 Design for ESD Immunity

Table 5.5 Comparison of Capacitor vs. Ferrite for ESD and Short Pulses Decoupling (Rs , RL = source and load side)a Capacitors

Ferrites

• Efficient

• Modest attenuation, generally 6–16 dB

attenuation with highimpedance circuits (Rs , RL ≥ 100 ). Up to 40 dB with SMT parts

• Can affect symmetry with balanced dif-

in typ. applications. Work best in low-impedance circuits (Rs and RL ≤ 100 ) • No impact on line symmetry

ferential inputs • Values restricted to what the useful sig-

nal can tolerate across the line. Generally 30–300 pF for digital inputs

• Do not affect useful signal, if CM

mounted • Easy to install, no or minimum

Hardware changes a With hybrid configurations where Rs < 100 and RL 100 , best results are obtained with ferrites plus capacitor, the ferrite looking toward the signal source, generally line side, and capacitor looking toward the load (victim’s input).

Table 5.5 and companion Figure 5.53 can help in deciding which capacitive filter, ferrite or both is the optimal choice. The 100-pF/100- rule-of-thumb (technically justified), often used by EMC practitioners for standard EMI reduction above 30 MHz, suits ESD as well. It means that a 100-pF capacitor on the high-impedance side, that is, looking toward an analog or digital input, combined with a 100- series resistance (or a ferrite with ≥ 100- impedance) will solve most RF immunity, emission, and ESD problems. This results from the following, simple observation: •

No matter the actual load (victim’s side) impedance, provided it is ≥ 100 , and

•

No matter the actual source (line side) impedance, the 100-pF/100- team will always provide at least, • • • •

10-dB attenuation 20-dB attenuation 30-dB attenuation 10-dB amplitude ≤ 3 ns

at 50 MHz at 150 MHz at 500 MHz (actually, 24-dB insertion loss) reduction against an isolated pulse with duration

Some guidance for the choice between a ferrite or a capacitive decoupling is given by Figure 5.53. The curves show that for the larger portion of the frequency domain occupied by a short ESD pulse, that is above 30 MHz :

5.5. ESD Protection of External Cables and I/O Ports

Filtered connector (C, L, π or T) C

π

L structure

T structure

Filter type

AMP electrical specification number

Capacitance range

CA

108 -1139

4000 pf to 10,000 pf

CC

108 -1132

1300 pf to 2500 pf

CD

108 -1135

600 pf to 1000 pf

CE

108 -1134

400 pf to 600 pf

CF

108 -1133

240 pf to 360 pf

60

Insertion loss in db

50 40 CA

30

CC CD CE F C

20 10

1 MHz

10 MHz

100 MHz

1GHz

Figure 5.55 Filtered connectors for signal lines, and male/female filter adapter. (Source: Spectrum Control Inc. and AMP Amplimite Series.)

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Chapter 5 Design for ESD Immunity

Idiff. mode(Signal)

ICM (Noise)

ICM ∑IdM = 0

ICM

One ferrite per wire (or trace) affects ICM and Idm

PC board trace interrupted

SMT version

ICM

One ferrite over the two (or "n") wires affects ICM only

Perforated ferrite plate for connector

Figure 5.56 Typical applications of small ferrite beads on I/O interfaces. • •

Ferrites with impedance Zf > 100 will work best if both Rs and RL are << 100 . Capacitors with impedance < 100 will work best if both Rs and RL are > > 100 .

In summary, capacitor-based filtering is efficient for noise-free protection of dc or low-frequency analog inputs, and moderate speed I/O data lines, say no more than 5 Mb/s, that is about 25 MHz of spectral bandwidth. For faster rates, two- or three-stage filters are necessary, but they, too, reach a practical limit for digital speeds exceeding 100 Mb/s, where the allowed capacitance, each line to chassis, is limited to 5 pF (×2). However, for functional as well as EMI reasons, such data rates are carried on shielded twisted pairs (STP) with good balance, Txmit and Receive Baluns, and differential inputs, which somewhat exonerates the designer from specific I/O filtering against short ESD pulses. For quick ESD hardening, or when deep changes in PCBs or hardware cannot be made, add-on components are available: •

The flexible insert filter of Figure 5.57 is manually fitted into an existing socket, turning an ordinary connector into a capacitive filter. Small tabs on the membrane edges allow a peripheral grounding to the metallic receptacle, which must be directly bonded to the chassis plate (best) or PCB ground plane.

5.5. ESD Protection of External Cables and I/O Ports

215

Filter insert for 9-Pin D-subs

Standard capacitances Capacitance (pF) @ 1 kHZ

Voltage rating*

100 470 1000 1500 2000 4700 10,000

200VDC 200VDC 200VDC 200VDC 100VDC 50VDC 50VDC

Filter water features: Low-cost, high performance alternative Available in all standard and high density D-Sub configurations Also available for MILC-38999 and MIL-C-26482 and other connectors Fits completely and unobtrusively inside mated connectors

Equivalent circuit for each pin

discrete capacitor connector shell

Figure 5.57 Flexible membrane capacitive filter array. (Courtesy of μM-Microelectronics Mfg.) •

The male–female filter adapter is a quick fix version of the standard filter connector in Figure 5.54, which can be inserted between the two parts of an existing connector, without any hardware change. As for the membrane type, the existing receptacle should have a grounded, metallic shell.

5.5.2.2. Transient Voltage Suppressors (TVS) against Direct Discharges on I/O Terminals

Direct ESD can inject the full energy of a discharge into those circuits that are wired to accessible parts of the equipment (see Section 2.2). The inputs of these circuits, especially ICs, have a normal ESD immunity, generally in the 2- to 4-kV range (see Section 5.1). So, unless special ESD-hardened ICs have been selected, they must be protected by fast TVS. Zener diodes and Zener-based devices have a sharp breakdown knee in their voltage/current curve, while metal oxide varistors

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Chapter 5 Design for ESD Immunity

have a smoother avalanche transition, with clamping voltage typically two or three times their break voltage. Varistors or Zener diodes have significant intrinsic capacitance (typically a few hundred picofarads) providing filtering of the short pulses at no additional cost. However, if the protected line is a high-speed digital link or an RF input, this intrinsic capacitance would bring too much distortion. Special TVS modules are available with very low capacitance, such as 5 pF for high-speed IEEE1394, or even less for high-speed, high-definition picture processing. A few manufacturers have developed interesting combinations of TVS + filter + single or balanced terminating resistors in one integrated package, capable of protecting 2–10 lines (Fig. 5.58). Such combinations provide

Low-capacitance transient suppressor with low capacitance diodes

+Vcc P. up DATA +

Combined low-capacitance TVS and EMI filter for high-speed differential signals

DATA − P. down GND

Figure 5.58 TVS modules for high-speed signals. The lower sketch combines HF noise filtering with full ESD protection. (Source: ST Microelectronics.)

5.5. ESD Protection of External Cables and I/O Ports

217

in a single device the ESD error-free filtering and the damage protection, yet preserving impedance matching for signal integrity. Similar modules also exist for protecting microphone and headset/loudspeaker interfaces from D-ESD damage. Other TVS (by SMT or Littelfuse Inc.) are based on crowbar principle, where a thyristor is triggered, shorting the line to ground when its voltage exceeds the supply dc voltage. Just like for the flexible filter insert of Figure 5.57, flexible TVS membrane that fit into connector receptacles are available for quick fix or retrofit. A cheap D-ESD protection can also be made with gas tubes or air gaps. They are robust devices, but their firing accuracy and response time for a nanosecond pulse front is mediocre, so they should be kept for the less fragile applications. A rough overvoltage suppressor can be made using PCB traces (Fig. 5.59d) to form a 0.1- to 0.2-mm gap, firing approximately at 1–2 kV. Needless to say, these devices should never be used on low-impedance dc lines: the arc would not extinguish since it remains fed by the dc source. 5.5.2.3. Accessible Pins of Unused Connectors

A problem arises when, depending on the equipment configuration and the type or number of interconnected units, some connector receptacles could be left without cables. Since it is very likely that the inner wiring of the electronics has been installed, these unemployed connectors are an invitation to serious ESD problems if they are accessible. If a bare pin is approached by a finger at less than 1 cm or so, a direct discharge can be conveyed straight into sensitive components. Although some test specifications are exempting these connectors from a contact or air-discharge requirement (see Chapter 4), it is recommended that such an event be considered seriously, at least as a no-damage criteria. Several solutions exist (Fig. 5.59): • • • • •

•

•

Do not provide the inner wiring when the corresponding option is not installed on this version of the equipment. Mount the receptacle in a recessed area so that a would-be charged finger or handheld tool will zap the housing or connector edge first. Provide a metal cap or blinder on unused connectors. Provide a plastic cap or blinder, with a breakdown voltage greater than 20 kV. Protect the corresponding lines with transient voltage suppressors, which might not have been needed if the bare receptacle was not exposed to ESD. Use a simple mechanical shorting device, with a small spring blade that grounds all the pins to the metallic receptacle rim when the connector is not there. If possible, prefer female contacts for accessible connector receptacles.

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Chapter 5 Design for ESD Immunity

Internal wiring to PCB

(a) Grounded "Crowbar" Row

(b)

Receptacle

Plug

Male

Female contact

Detail, side view

Grounding tab (c)

ESD - Sensitive input trace 0.2 to 0.3 mm or: Ground trace or plane (d)

Figure 5.59 ESD protection of unused connectors. To prevent the risk of a finger or tool arcing to a bare contact, solution (a) put the socket in a recessed zone, such as contacts, are practically unreachable without arcing to the case first. Solution (b) is adding a 20-kV resistant plastic cap fitted on the unusued receptacle. Crowbar solution (c) is based on spring contacts, grounding the connector pins when not in use. Finally, the PCB spark gap (d) provides a coarse protection for surges exceeding 1–2 kV.

5.5.2.4. Optoelectronics as an ESD Barrier

Optoelectronics often viewed as the panacea against EMI, would seem to be an ideal solution against ESD as well. Although it must not be rejected a priori, it may give disappointing results: •

Optical isolators (OI) have parasitic input-to-output capacitances that can represent, once mounted, 1–5 pF. For ESD rise time in the nanosecond range, this capacitance is by-passing the isolation barrier by less than 1 k impedance. Because of this parasitic capacitance as well, the OI can be activated by dV /dt on the order of 10 V/μs for the cheaper parts to few

5.5. ESD Protection of External Cables and I/O Ports

•

219

kilovots/microseconds for the best ones. Even after losing some amplitude across the various coupling paths, ESD transient reaching PCB inputs easily exceed 10 V/ns, hence, triggering most OI except the high immunity brands. These have generally an optically transparent, miniature Faraday shield between the light source and the detector. Fiber optics (FO) are certainly a better solution. But the designer is not exempted from carefully shielding and/or decoupling the detector end of the FO link. Photodiodes or phototransistors are high-impedance devices, generally followed by a sensitive, high-gain amplifier that is easily disturbed by capacitive coupling on its input.

5.5.2.5. Preventing ESD Back-Door Entry by the Power Cord

Often overlooked in their contribution to ESD coupling are the power cords. Since they connect to the transformer or other bulky components, they seem above suspicion. However, as it penetrates the machine enclosure, a power cord may carry to the inside the transients externally induced by an ESD. In this case, the solution resides in filtering/decoupling the power cord right at its point of entry. Since power cords are generally filtered anyway, this seems a superfluous recommendation; but RFI filters are generally optimized to meet conducted specifications below 30 MHz and may be inefficient at the 100-MHz (or more) frequencies of the ESD spectrum. In this case, the filter can be improved by additional ferrites, or mounted in such a way that its input-to-output isolation is still substantial for ESD rise times. Another solution, not mutually exclusive, is to use a shielded power cord, which will both avoid ESD reentry and also improve the drain path to ground.

5.5.3. I/O Cable Entries ESD Protection with Plastic Products If a product has a total plastic enclosure, with no conductive treatment, and the designer is confident that the other EMC requirements (radiated emission limits, etc.) are met, it would be regrettable to be forced to a metallization just for ESD. At least it is worth trying a design pass without it. So we are left with I/O cables that are either shielded, with no chassis for connecting the shield, or unshielded. For shielded cables, although an all-plastic box make their use questionable, several possibilities exist (Fig. 5.60): •

•

Connect the shield(s) to the PCB 0-V reference. This is the less desirable option because ESD currents drained by the shield will spread across the signal reference. Connect the shield to an artificial ground (Fig. 5.60, bottom). This artificial ground is a piece of metal foil or conductive coating, with at least a 50-cm2

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Chapter 5 Design for ESD Immunity

How to connect

Cable shields / connectors CM decoupling capacitors Filter - Connectors.

• Lack of any better: to the PC board 0 V plane

Problem: we spread ESD currents in a functionnal reference (but this 0 V plane has low Z ≡ this may work).

0V 0V

0V

• Better Gather all these connections in the same PCB area (Cf. the advantage of regrouping all I/0s), on a copper island connected to the 0 V plane via a bottleneck.

• Even better: Mettalize (conductive paint, copper tape, etc...) a limited area of the bottom cover; will act as an artificial ground to collect shields/capacitors currents, and relay them capacitively to local ground plane (floor, desk, etc...).

PC board shields and decoupling capcitors connection

I/O signal traces

PC board

Attention: do not extend this land far under the board or in "touchable" zones.

Figure 5.60 Treatment of external cable entries with nonconductive plastic boxes.

area (with 100 cm2 being preferred), laid in the plastic housing, bottom side. Placed near the entry point of the I/O cables, this foil will collect the shield currents (instead of the 0-V plane) and spread them to ground via the foil stray capacitance. Ideally, the cable shields should physically connect to this foil with a 360◦ joint. Since this is seldom practical, the cable shields can be terminated by a metallic connector housing, or clamp, on the PCB, then bonded to the artificial ground by a wide strap or bracket. The shield connection on the board should be a dedicated copper land, preferably not the 0-V plane.

5.6. ESD Immunity by Software and Noise Inhibition Techniques

221

With unshielded cables, the principle is to clean up the wires of their ESD-induced noise before it can contaminate the PCB. So HF decoupling will be used (see Section 5.2), with the decoupling capacitors connected following the same rules as cable shields above: •

•

Connect the decoupling capacitors to the PCB 0-V plane. This, too, is the less desirable option because it contaminates the signal reference (Fig. 5.60, top). Connect the capacitors to an artificial ground made by a metal foil. This ground foil should be located in the I/O ports area, not extending too far underneath the board.

5.6. ESD IMMUNITY BY SOFTWARE AND NOISE INHIBITION TECHNIQUES Electrostatic discharge is generally an isolated, elusive event that at the worst does not happen more than 10 or 20 times a day, during a few weeks per year. Therefore, software/firmware error detection and correction can be simpler and less expensive than adding components. The following few guidelines [some of them inspired by the excellent analysis by Boxleitner (20)] can help to implement this kind of “intelligent filtering.” However, one must remember that: 1. Nothing is free and the added instructions for “catch-all” error recovery increase the program size. Memory space (bytes) can double, and execution time (cycles) can be multiplied by 1.5. 2. A lot of software traps are, indeed, camouflages simply patching a more general vulnerability to all kinds of electromagnetic disturbances, not just ESD. Nondamaging, low-level ESD-induced pulses can cause severe errors and machine lockup if they appear on critical processor/controller lines, where they could corrupt or freeze a program execution. These include oscillator inputs, reset, interrupt request, or also chip resident programming or manufacturing customization/debugger inputs. Several techniques, not particularly devised for ESD error protection, can be used as defensive software: •

•

Software “deglitchers” (voting or polling techniques) can be used to confirm the status of an input by using multiple readings. For instance, with a keyboard, the depressing of a key should be validated by three successive readings at 10-ms intervals (21). Error detection methods such as: • Parity check, which detects errors, but without correction • Cyclic redundancy code (CRC) check, which can detect and correct errors • HDLC, digital filtering, autocorrelation, and credibility check can be used for checking input/output data

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Chapter 5 Design for ESD Immunity •

•

Program run-away can be detected by checking the time duration of routines. By filling unused memory spaces by a “Stop” or “No operation” instruction, nonintentional executions can be avoided, the watchdog will detect an abnormal halt, and initiate a reset. Regular, periodic programmed refresh, even without special aberration detection (e.g., the refreshing of the displayed data).

Some defensive sofware tools are generally embedded in the microprocessor itself. The I/O management, which connects the processor to sensors, actuators, or communication peripherals, can periodically refresh the I/O port register to prevent any illicit change of state. For analog input management, a regular check against a min–max range, based on the history of the previous strain of measurements, will ignore any instantaneous value, which is obviously out of scale or could not have jumped to such a value so fast. Many of these techniques are associated with some dedicated hardware circuit or safeguard, like the Watchdog, for instance, which is built in the IC, with a specific timer. The CPU generates a periodic signal as long as everything is okay. If not, a recovery is initiated (“dead-man’s” detection technique). If the main program is stuck in a frozzen state, the Watchdog will activate the RESET and restart the processor. Of course, if the Watchdog signal itself is triggered by an ESD, the scheme is defeated since an unnecessary restart will occur. On some machines, this reset is practically undetected by the user, hence tolerable. On some others, the reset suspends the regular operation during such a time that it can be a nuisance for the user. For this reason, some ESD test plans require that up to a certain ESD voltage, the EUT should make no error at all, even recoverable; the reason being that such low-voltage ESD occurrences can be very frequent in some environments. A leading idea for ESD hardening with firmware is mistrust (20): One should never assume that the state of an I/O port, register, memory address, and the like has not changed since the last time it has been legitimately used. If an undesired change in the status of a line can trigger a wrong sequence, the status of this line should be periodically refreshed, or checked and restored. Restoring should be used only for serious cases, like when the sequence of events would end in a lockup, requiring operator action, or even an impossibility to restart without a crash power-off. Concerning data lines in general: •

•

No design should authorize a circuit to disable itself for an undefined period. For instance, if a keyboard can be disabled or put in a “wait” mode, some routine should check periodically and refresh this status, to make sure it has not been incidental. Critical inputs, especially those that can trigger an irreversible sequence, should be checked twice, at microsecond intervals (it is very unlikely that an actual ESD event, which does not last more than a few tens of nanoseconds, occurs twice during this checking window).

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223

Make an “And” gating of critical signals with an undisturbed clock line. For instance, a RAM can be inherently protected against an illegal “Write” through an extended addressing mode. But if an ESD induces a same pulse in both the “Read/Write”and the “Enable” inputs, the protection is defeated.

Fault-tolerant architecture and “graceful recovery” schemes require that the designer knows all kinds of output states that can legally exist. Many error recovery schemes have been devised to this effect, which can be found in specialized literature. To conclude this section, and as said at the beginning, solving ESD problems by software tricks is an easy ticket, but it is basically “cheating.” Some other severe, high-frequency threats may exist that the software cannot handle. They are essentially the exposure to strong RF fields (10 V/m or more) and electrical fast transients (EFT pulses with kilovolt peaks). In both cases, the interference will be either quasi-continuous (with RF fields) or so recurrent (EFT has several bursts/second of 50 individual pulses) that the sofware recovery simply cannot work. More exactly, the sofware will keep trying to restart a machine that keeps making errors over errors. Therefore, software defense has to be kept as the last barrier for rarely occurring isolated events and does not exonerate the designer to apply all hardware protection techniques described in this chapter.

5.7. ESD IMMUNITY WITH MINIATURE, PORTABLE DEVICES An increasing number of small, handheld or pocket-size devices are carried by a huge number of people. Just to name a few of these “nomads,” consider a list that is extended every month: Cellular phones and related accessories (headsets, earsets) Low-power wireless (Bluetooth, etc.) devices such as wireless mouses, USB transceivers, and the like USB keys Miniature FM radios, music players/recorders Palm-size personal agendas/assistants RFID (radio frequency identification), some devices being body-implanted Body-connected devices: cardiac pacemakers, hearing aids, insuline dispensers Smart car keys Smart cards GPS road maps

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Regarding ESD, all of these share in common some remarkable features: •

• •

•

They are light, plastic-encased devices, packed with complex electronics, often combining audio input/output, RF transceiver, high-speed digital processing, optical sensors, and image processing with small LCD or O-LED displays. Some incorporate one or more small RF antennas. They are constantly touched, carried, or manipulated by people, which means that they are in proximity of notorious electrostatic carriers: human skin and clothes, and eventually car seats/upholstery. They often have accessible, subminiature I/O connectors.

Therefore, they appear as first-class targets for severe indirect and direct ESD. Fortunately, several factors concur in tempering these pessimistic expectations. For one thing, their size, generally not more than the palm of a hand and often much less, speaks in favor of very small exposed circuit loops and stray capacitance, with trace lengths seldom exceeding a few centimeters. Then, for obvious reasons, designers had to take serious precautions to guarantee all at once low RF emissions, high RF immunity, and mutual compatibility of many internal functions packed into such small spaces. For instance, the PCB, generally a single miniature board, not only is the host for the active circuitry but it also acts as the supporting structure for integral or compartmented shields because the device’s plastic housing is just a physical shell without shielding properties. This PCB is a multilayer type, with the ground plane frequently interconnected with ICs internal ground planes (see Section 5.2.3). The first layer (component face) has ground copper lands for wave soldering of small metallic covers with solder tabs on the four sides. The plastic shells of the box can be assembled together by a seamless process (e.g., ultrasonic welding), such as the final casing is totally hermetic to arc discharge. Miniature connector receptacles have a metallic housing grounded to the PCB, making it impossible to approach a charged finger without arcing on the metal edge first. For reducing the risk of a charged cable to discharge on sensitive pins at plug-in, the miniature connectors can have a peripheral ground ring or sleeve that makes contact first. Miniature RF antennas are now patch antennas that are not touchable. If a risk of air discharge remains at 15 kV, subminiature TVS with very low parasitic capacitance and VSWR can be mounted on the antenna feeder trace. The same technique is applicable to sensitive microphone inputs. Thanks to these advantges and along with many other tricks of the trade, some of them being proprietary, most of these nomad devices have a remarkable immunity. USB keys can resist more than 10 kV/m of RF field up to 1 GHz, with burst duration of 100 ns, which is a more intense exposure than any closer ESD. Cellular phones do resist to the IEC 8-kV contact and 15-kV air discharges. Contactless car keys are generally damage free (or code erase free) up to 25 kV, per ISO 10605.

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5.8. SYSTEM ESD IMMUNITY Propagation of ESD impulse currents in a multiple-unit system is very dependent on the common-mode (CM) impedance(s) of the system cabinets and cables network with respect to local ground planes (i.e., not just floor, but also walls, ceilling, concrete rebars, etc.). Depending on the actual system configuration: • •

Number of extensions connected I/O ports used and the like

and on the installation variations: • • • •

Nonconductive desk Metal desk Nonconductive floor Raised metal floor and the like

An infinite number of CM impedance combinations exist for the ESD current to spread from the victim unit to the companion units (Fig. 5.35). For instance, the whole system ESD susceptibility can deviate significantly from the individual susceptibility of its components. Even though it is recommended that each individual unit be tested with its I/O cables installed and terminated “in a representative manner,” one can predict that its behavior will be different in a complex network (22). If the unit is tested with all its cables laying 5 or 10 cm over a metal plane, this is (legitimately) considered as a worst case since the low CM impedance of the cables will invite a larger share of the current to flow, for the same ESD initialization voltage (remember: ESD, especially the personnel type, is a current source). The share of the total ESD current will be greater for the cables and less for the box itself. When this same unit is used in a small system configuration (i.e., not all I/O cables are present) and the cables are mounted high above ground, the box will take a bigger share of the ESD current and some failure modes related to apertures leakage and PCB trace pickup may become predominant. All these aspects result in some frustration observed in the system ESD performance, compared to the individual performances of its units. These variations may appear both in terms of different ESD susceptibility tresholds as well as type of malfunctions. Futhermore, higher ESD amplitudes do not necessarily mean the worst threat for unit and system performance since current waveforms exhibit either: 1. A constant rise time (hence, bandwidth): This would result in constant bandwidth, with a spectral density in amperes/megahertz increasing with test voltage. 2. A constant ampere/nanosecond slope: This would result in a constant amperes/megahertz spectral density in the higher portion of the spectrum, above f2 = 1/πtr .

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Therefore, when a unit is designed (and/or hardened) to meet a given ESD severity criteria, it must be checked, during design and test that: •

•

The level that has been achieved for the maximum system configuration (all possible cables, features, and peripherals installed) is still met for the minimum size or, eventually, a stand-alone configuration. This immunity does not rely exclusively on a drastic treatment of the I/O cables and interfaces. A good ESD performance built upon an intensive use of well-shielded cables and capacitive decoupling of I/O ports may deteriorate when the unit is not equipped with all these cables, or some unit(s) at the other end presents a higher CM impedance to ground than what was used as a test vehicle.

5.9. ESD CONTROL AT INSTALLATION LEVEL The installation environment is probably the aspect on which the designer has the least control. Furthermore, since equipments are generally specified for certain environmental conditions, it would be foul-play to change the environment because an electronic equipment does not meet the challenge! However, life seldom provides clear situations like this. Many times the environment was unknown or poorly defined at the time of initial equipment design. Moreover, salesmen might have overdone it and sold equipment for an environment where it should not have been installed. So, if everything else fails, or at least to provide temporary relief waiting for a more engineered solution, the following can be done : • • •

• • •

Maintain relative humidity above 50% or use an ionized air blower. Install a grounded metallic rail that everyone will touch when approaching the system. Use antistatic spray. Antistatic properties remain for about 2–4 months, depending on traffic. This treatment does not bleed-off existing charges, but avoid static generation around people and furniture, when moving. Use seat pads in nearby chairs having breather-type fabrics. Ground the chairs (or carts) by using conductive wheels. Avoid carpet around system perimeter, use carpet with grounded woven metal thread inside or cover the carpet with antistatic slightly conductive mats.

Floor conductivity has been a concern for a long time in the electronics industry and industrial buildings in general. For instance, electrical resistance is required to meet NFPA Bulletin 56A issued by the U.S. National Fire Protection Association or, in Europe, DIN Std n◦ 51953 and 53482 (Concentric electrode test). The NFPA standard recommends a 25,000- to 1-M resistance of the installed floor, between two electrodes placed 1 m apart. The measurement is

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made via two cylindrical electrodes with a 6.35-cm (2.5 inch) diameter, weighing 2.25 kg (5 lb) each. The resistance is determined by a current reading from a 500-V source or directly with an ohmmeter having a nominal source voltage of 500 V. Another test often quoted is the “standard pedestrian,” where a person walks lifting or shuffling his shoes. The repeatability is mediocre but gives an indication on electrostatic dissipation properties. A carpet is generally considered as satisfactory if the residual voltage is <2 kV within 2 seconds after a person charged to 5 kV has walked on the specimen. The parameters usually given for antistatic flooring are: 1. Surface resistivity ( /square) (Fig. 5.61) relates to the propensity to static charging and retention. It does not necessarily mean that this carpet can “ground” an already charged person or furniture. 2. Transverse resistivity (-cm) relates to volume resistivity, that is, the charge sink to ground. Antistatic floors can give disappointing results if not installed properly, or treated later with certain cleaning solutions, or so-called spot-free impregnations. For instance, the anti-static carpet in Figure 5.62 applied with a very insulating glue, may not generate static charges, per se, but cannot sink to ground the charges brought into the room by someone coming from another, untreated area, such as the corridor. For this reason, antistatic (in fact static-disspative) carpets incorporating a small percent of metal or carbon fibers in the yarn should be electrically connected to the room safety ground conductor (since this latter is grounded). All the same, floor tiles and desk overlays using an internal carbon filler (Rs ≈ 105 –107 /sq) should be grounded via an electrode that permanently contacts this layer.

Surface resist. Ω/sq.

1013 Insulating floor (silicon waxed floor, vinyl tiles nylon carpet, etc.)

1011 Wool carpet 109

Typical computer room antistatic carpet

107

Rel. humidity 10%

30%

50%

Figure 5.61 Floor surface resistivity versus RH.

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Initial voltage

Final voltage

7.6 kV

Anti-static carpet (R>107 Ω)

50% point 2.2 kV

2.1 kV 1.4 kV 0.6 sec

Concrete slab

Insulating glue (R>1011 Ω)

Figure 5.62 Typical property (charge decay) of antistatic carpet. On the right, such carpet is rendered useless by insulating glue, turning the carpet into the charged armature of a capacitor.

REFERENCES 1. Lin, D. Effect of VLSI Scaling on ESD Current Capability. Journal of Electrostatics, July, 1997. 2. Beebe, S. Characterization of ESD Protection Circuits. SemiConductor Research, Tech. Report 94CY707, March, 1998. 3. Sicard, E., and Bendhia, S. Advanced CMOS Cell Design. McGraw-Hill, New York, 2006. 4. Sicard, E., Bendhia, S., Baffreau, S., and Ramdani, M. EMC of Integrated Circuits. Springer, New York, 2006. 5. Malinaric, P. J. Transient Suppressors with Varistor Composite Material. IEEE/EMC Trans., Nov., 1985. p. 191– 200 6. Val, C. High Performance Surface-Mount VHSIC Packages. 4th Microcircuits Conference, Kob´e, 1986. 7. Ming-Dou, K., Cheng-Cheng, Y., and Pi-Chia, S. On-Chip ESD Detection. IEEE/EMC Trans., Feb., 2008, p. 13–21. 8. Montrose, M. Printed Circuits Board Design for EMC Compliance, 2nd ed. IEEE Press, New York, 2000. 9. Hubbing, T. PCB EMC Design. IEEE/EMC Symposium, Boston, 2003, p. 34–36. 10. Sarto, M. S. Electromagnetic Shielding of Thermoformed Plastics. IEEE/EMC Trans., Nov., 2004, p. 588– 596. 11. White, D. R. J., and Mardiguian, M. Electromagnetic Shielding, Vol. 3 EMC Handbook Series, 1988, ICT, Gainesville, VA. 12. Schutz, R. B. Shielding Theory and Practice. IEEE/EMC Trans., Aug., 1988, p. 187– 200. 13. Ott, H. Noise Reduction Techniques in Electronic Systems, 2nd Ed. Wiley Interscience, 1988. 14. Faught, A. Shield Evaluation Using Transfer Impedance Technique. IEEE/EMC Symposium, Santa Clara, CA p. 38–44, 1982. 15. Palmgreen, C. Shielded Flat Cables for EMI/ESD Reduction. IEEE/EMC Symposium, Boulder, 1981. 16. Mardiguian, M. Controlling Radiated Emissions by Design, 2nd ed., Kluwer, Boston, 2001. 17. Vance, E. Coupling to Shielded Cables. Wiley, 1978. 18. Tsaliovitch, A. Cables Shields for EMC . Kluwer Academic, Amsterdam, 1999.

References

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19. Charoy, A. Compatibilit´e ElectroMagn´etique. Dunod, Paris, 2000. 20. Boxleitner, W. ESD and Electronic Equipment. IEEE Press, New York, 1999. 21. Carlton, R., Racino, G., and Suchyta, J. Improving Transient Immunity of μ Controllers. FreeScale App. Note #2764, June, 2005. 22. King, M. Mastering ESD System Response. EMC Technology Magazine, 1988, March, p. 53, May, p. 39.

Chapter

6

ESD Cases Studies T

his chapter reports some ESD “war stories” experienced mostly by the author himself or by his associates at an EMC consulting firm in the United States. There were periods when the consultants’ telephone was ringing several times a day just for ESD calls. Assisting a customer who has an ESD problem is seldom a boring, “deja vu” experience. Of all the EMI manifestations, ESD is probably the one whose symptoms can be the most varied and deceptive and whose diagnosis can be the most elusive. Needless to say, ESD is also a privileged playground for Murphy to exercise his laws with demonic ability. The following “tales from the trenches” have been selected because they share several similarities: • •

•

In general, the plaintiffs were knowledgeable engineers who had tried all common-sense fixes (plus a few others) before calling a consultant. The outcome of these fixes (whether or not they helped) usually was not documented, or at least not quantitatively. When they were, it was in the form of a verbal legacy passed on by each of the frustrated raiders to his next partner. The go/no-go levels reached with each fix, the manufacturer, type and part number of the suppression components, and whether the fixes were cumulative or if each successive fix was taken away before a new one was tried could not be determined. The type of simulator used was sometimes not even documented. The whole saga was summarized as: “We have tried everything, and nothing worked.” Sometimes, the client had already called a consultant who tried several pieces of the usual EMC arsenal, including in one case a complete overhaul of the building ground network, ground rods, and the like, which, although it certainly improved the safety of the facility and the wealth of the building contractor, did not do much for the ESD immunity of the system.

Electrostatic Discharge, Third Edition, by Michel Mardiguian Copyright © 2009 the Institute of Electrical and Electronics Engineers, Inc.

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6.1. Case 1: The Reradiating Ground Strap •

•

231

In several instances, many of the unsuccessful fixes were, in fact, appropriate. But they were tried in random sequences so that the engineers could not compile and interpret the gradual changes they might otherwise have noticed, thereby not learning from their mistakes. Finally, there was unanimous consent about what the consultant had to do: He should fix in 48 hours what 3 successive task forces (appointed by 4 consecutive division managers) had failed to solve in 8 months.

6.1. CASE 1: THE RERADIATING GROUND STRAP The case of the reradiating ground strap started as an easy one. The EUT was a process control mainframe housed in a steel cabinet. The CPU was failing at a 5-kV discharge on the control panel, while an immunity of at least 12 kV was desired. A short discussion over the phone revealed that the operator panel front was not grounded. However, bonding it by a few short strap to the main cover did not improve the threshold by more than 1 kV. A trip to the customer’s site revealed that the problem had three facets, as shown in Figure 6.1. •

The flat cable [Fig. 6.1(a)] from the operator display to the microprocessor was running alongside the cover hinge slot and the cover ground strap. During an ESD, the sheet metal edge and ground strap were a preferred sink path for the discharge current to ground. The high current density

Signal connector

Operator panel PCB

IESD

DC supply connector

I/O terminal board

c

a

b

Power supply

Figure 6.1 Case study 1. Packaging of the machine showing the (a) flat cable routing, (b) dc supply wiring, and (c) I/O cable shield pigtails.

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•

•

created locally a strong magnetic field that coupled to the ribbon cable conductors. To make things worse, the 0-V return wire of the display board was made with a heavy-gage wire, part of the dc supply pair [Fig. 6.1(b)], but running far from the flat cable. Although a signal return wire was also provided within the flat cable, a large ground loop existed between the signal wires and the 0-V dc return. On the opposite side, the I/O signal cables were entering the cabinet through a simple hole. The shields [Fig. 6.1(c)] of each pair were terminated by long grounding wires, collected by a grounding post far inside the frame. The design of all PC boards was quite clean, so as soon as the first two problems were corrected, the level went up to 12 kV. A change in the I/O cable shields grounding was recommended to bring the level even higher.

6.2. CASE 2: ESD HARDENING OF A PRINTER A typewriter had to be hardened to withstand at least 8 kV. Since the users could have either metallic or nonconductive desktops, the criteria had to be met with both configurations. Initially, the EUT failed at approximately 4 kV, using the IEC-801 test method. A first significant fix raised the ESD susceptibility around 8 kV (i.e., no margin) by adding a thin sheet metal plane underneath the PC board, connected to the 0-V reference near the edge connector, using a short, flat strap jumper. This plane acted as a low-impedance Faraday shield. The next fix, which brought a tangible improvement, was a proper bonding and grounding of the printing head carrier, which was practically floating, HF-wise. Copper tape straps helped to bond together the front and rear halves of the carrier, and a bronze clip provided a sliding ground to the rail. This provided also a proper ground attachment for a braid added to the two cables coming from the main PC board to the carrier. Included in the fix was a good continuity between the elements of the paper tractor and carrier rail frame, via several short copper straps (Fig. 6.2). At this point, the susceptibility had raised to 12 kV with the typewriter placed directly upon the large table ground plane. When the unit was placed upon a wooden box, thus elevated approximately 10 inches above the ground plane, susceptibility dropped to about 7 kV. Two additional fixes upgraded the susceptibility to 12 kV as well. The most significant of these was the placement of screen foil underneath the keyboard, connected to the general grounding of the carrier rail supporting frame. The other fix involved the power supply cables that ran from the rear of the unit to the PCB. These cables, which fed the dc supplies to the electronics, motors, and solenoids, were harnessed together in a single, tight bundle. The overall EUT susceptibility threshold, in all configurations, held to12 kV giving a comfortable margin.

6.3. Case 3: The Data Terminal with Floating Tray

233

Front and back of carrier assembly bonded together Sliding contact on carrier rail

Safety wire

All metal parts of bottom plate continuously bonded together

Faraday shield underneath the keyboard Carrier cable, shielded. Shield grounded to bottom plate and to carrier assembly

Figure 6.2 Case study 2.

6.3. CASE 3: THE DATA TERMINAL WITH FLOATING TRAY This one was a more challenging mission. A significant amount of hardening had already been attempted by the designers, with some success. The unit was withstanding 7 kV, failing around 8 kV, but a 20-kV immunity was desired. As in most ESD hardening problems, the last kilovolt steps of the ladder are the most difficult to climb. After several investigations, including a careful tracking of the former iteration results, good or bad , attention was focused on two major failure candidates: •

•

A conductive coating had been applied inside the covers, but a decorative paint overcoat had been sprayed on the outer sides. No special attention was paid to the edges, and they were covered with insulating paint so that no continuity existed along the edge seams (Fig. 6.3). Even worse, this was the entry zone for the data bus cable. Restoring the metallization over the abutting edges, changing the mediocre cable shield (aluminum flash over mylar wrap) for a more homogeneous one, and bonding this shield to the box’s conductive skin via the connector shell brought the “run” level in this zone up to 20 kV. The other susceptible point was a metallic tray that the user would touch frequently. This tray was originally floating, but a former attempt to ground it via a jumper wire was fruitless, which can be explained by Figure 6.4 (a): a strong capacitive coupling between the tray and a bundle of sensor wires passing nearby. The high impedance of the jumper wire could not

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Metallized coating

Before

After

Figure 6.3 Case study 3. Enlarged view of the problem caused by the nonconductive paint sprayed over the metallic coating at the edges.

VESD

(a) ZW

10 pF Tray

RL

ESD 10pF ≈ 100 Ω for Δt = 1 ns

Sense ampl. inputs

Tray RL

Sense wires 10 cm of wire ≅ 100 Ω for 1 ns

Metallized paint

VESD

(b) ZW

ZB

RL

Tray

Z beads ≅ 300 to 500 Ω

Figure 6.4 Case study 3. (a) Couplig path before the fix and (b) after the tray was more efficiently grounded, and ferrite beads added.

6.4. Case 4: The Safety Wire “Antenna”

235

efficiently compete with the tray-to-cable capacitance, at such high frequencies as ESD. Considering the 1-ns rise time, we can grossly estimate the impedances involved: • The 10-cm grounding wire presents a dynamic impedance L/dt = 10 nH/10−9 s = 100 . • The tray-to-cable capacitance (≈ 10 pF) has a dynamic impedance dt/C = 1 ns/10−11 F = 100 . Therefore a significant share of the discharge current still coupled into the sensor harness instead of being diverted by the grounding wire. By grounding the tray via a short, wide strap, and putting ferrite beads over the sensing wires, the situation was reversed, most of the current sinking to ground by the strap and the conductive coating. This, too, raised to 20 kV the ESD threshold level on the tray.

6.4. CASE 4: THE SAFETY WIRE ‘‘ANTENNA’’ This unit had a data interface connector accessible by the user. This connector was one of the discharge points, and the EUT was failing at very low levels. Figure 6.5(a) shows that this connector, indeed, was grounded but not for ESD reasons. It was a safety ground, installed for complying with the standard that required a protective grounding of the I/O connector to the machine grounding terminal. Therefore, a green wire (green/yellow for Europe) had been drawn from the socket to the ac main cord grounding post. Moreover, the machine had a plastic case, and conductive paint had been used, but it was the graphite kind, with a rather high surface resistance. As a result, a fraction of ESD current was flowing to ground via the green wire, which in turn reradiated into the nearby electronics. The fix consisted of upgrading the conductivity of the coating by sticking a wide 3M adhesive copper foil (with length-to-width ratio not exceeding 5 to 1, ESD

ESD

Added metal foil (length/width: 5 to 1)

Conductive paint

IESD

ESD current Flow

PH N (a) Poor

Figure 6.5 Case study 4.

Safety wire grounding post Plastic case (b) Better

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so that it acted as a ground plane) on top of the coating from the connector area to the power cord grounding post. Then, since this tape was not an acceptable substitute for safety, the wire itself had been kept, but rerouted tightly against the copper foil. As a result: • •

Most of the ESD current (high frequency) was now flowing into the foil. The rest of the ESD current, which still came by the safety wire, was not causing reradiation because the “antenna” was laid on a ground plane.

6.5. CASE 5: THE TOUCHY WATCHDOG The equipment in this case was a control unit for industrial process. It consisted of two PC boards mounted side by side in a box. Although originally a metal casing had been designed, the client wanted to meet the challenge of 8-kV ESD with a plastic housing instead. In this case, of course, the test was done by indirect ESD. Initially, the unit was failing at 3–4 kV on practically all sides. An examination of the PCB drawings revealed about 12 undesirable trace loops, all of which were patiently eliminated using 3 M copper tape to fill the voids or heavy-up the grounds. After this, the whole card sustained 8 kV successfully, except in one very critical zone, reluctant to show any improvement. The irritating aspect was that no critical, functional circuit existed in this area. In discussing the problem with the designer, the culprit was finally caught: To save volatile data during transient power loss, a power-sensing circuit had been designed, which was recognizing a “power-loss condition” every time the bulk, unregulated dc voltage dropped by more than 10%. The time constant had to be fast enough so that, once a power loss was declared, there was still 10 ms left (about the time during which a voltage regulator still can make up for failing power mains) before the 5 Vdc actually dropped below 4.5 V. During that time, using a “watchdog” procedure, a STORE signal was sent and volatile data were saved into a nonvolatile memory. When power was restored, a RECALL signal was sent to the nonvolatile random-access memory (RAM) and the microprocessor resumed its previously interrupted operation. Unfortunately, the circuit was on the card edge and had no ground plane underneath. During an ESD, induced glitches would foul-up the power loss and store/write commands, creating false SAVE routines. The solution was to run the sense traces close to a ground land on the PCB and to decouple them close to a ground land on the PCB and to slow down the circuit slightly so that it would not respond to glitches of a few nanoseconds, yet would still match the 100-ns window of the STORE signal.

6.6. CASE 6: THE TRIGGER-HAPPY AIR BAG INITIATOR This case represents a not-so-rare situation where an ESD upset manifests only when another, unrelated, extraneous event exists. The production of a new model

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237

of car had just started, but few air bag incidents were reported on the first production cars. In one case, the vehicle was parked, engine running at idle, the driver simply wiping the dashboard with a cloth, when the air bag triggered unexpectedly. The sudden blast of an air bag, especially when the driver or passenger was not normally seated and belted, is a painful experience: The life-saving device turns into a deafening, brutal punch. It had been a dry, cold winter day, so an ESD was immediately suspected, and a solution urgently needed since the delivery of the vehicles to the car sales shops was ready to start. In order to investigate quickly and efficiently the problem, a complete car harnessing, with all the connectors, modules, and sensors was laid out on a workbench and powered-up by a battery. The air bag EED initiators were in place, with dummy charges. All arc-reachable points were patiently tested, including those where the gun had to be cranked up to 30 kV to get an arc creeping to hidden connector pins. No firing ever occurred. Since the entire product engineering was on emergency mode, a full support of all concerned parties was available and several investigations were run in parallel. After a few days, some interesting clues emerged from the reports coming into the “war room”: •

•

First, it was found that an improper assembly-line routine resulted in one wire of the air bag harness being sometimes pinched under the front seat steel armature. The random grounding of this wire did not result in a short circuit and could go unnoticed, but it caused a differential pair, balanced link to become a single-ended one, with a substantial degradation of its common-mode rejection. Then, the re-creation of the event with the actual driver revealed that, at the moment of the incident, the car heating was turned-on, full “warm.” Looking at the location of the air bag control electronic module, it appeared that it was near the foot of the steering column, close to the outlet of the forced hot air. The temperature inside the module was not pushing the components out of their limits, but the noise margin of the digital gates and the accelerometer comparators was seriously reduced.

When those two adverse conditions were artificially re-created, the EED instantly triggered for ESD levels as low as 5–6 kV. One immediate corrective action was to review the assembly procedure and add an insulation test on this branch of the air bag harness; later, a relocation of the airbag control module was scheduled.

6.7. CONCLUSION: TROUBLESHOOTING HINTS Armed with the explanation of ESD coupling mechanisms given throughout this book, the reader should be able to identify most of the ESD failure modes and apply the proper fixes. To help quantifying the improvements, and to avoid false routes, the following guidelines have proven to be useful:

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• •

•

Always grade the progress brought by a modification in terms of the new run/fail levels, or in terms of the new error-per-pulse ratio (see Section 4.6). Try to visualize the ESD current paths and how they are modified by the bonding/grounding changes. This often gives a clue to the validity of a fix. To monitor either the ground currents or the common-mode current induced in cables, an RF current probe is a priceless tool. Being a totally floated sensor, it is not affected itself by ESD, and it does not modify the victim circuit. As an absolute rule, never remove a fix when, although it seemed to make sense, it did not bring any significant improvement. ESD can couple into the victim by many parallel paths, and until ALL of them have been reduced, a change may not be seen. For instance, figure an equipment where, as shown in Figure 6.6, the pulses caused by an ESD are received simultaneously on the victim circuit by three different paths: • 3 V are induced directly on PCB traces. • 5 V are picked-up by external signal cables. • 2 V come in via the power supply.

If the victim sensitivity is ≈1 V for a few nanosecond pulse, each one of these paths alone is sufficient to upset the circuit. Therefore, if someone has a bright idea and tries filtering the I/O cables, he may reduce this contribution to 0.5 V and not notice any tangible progress because the other two paths are still there, unaffected. He might then conclude that his fix was useless, take it away and try something else. Dozen of fixes can be tried selectively this way, following a foggy, verbal legacy that “two changes should never be added on top of each other,” and never work. Had the engineer left his first fix in place, then tried a fix on the PCB traces that reduce the noise to 0.2 V, he would have noticed a small improvement, but not the expected amount. Finally, if the third coupling is also reduced, say down to 0.1 V, a sudden improvement will show up because 1 order of magnitude hardening has just been achieved. To summarize the outcome of the few reported field experiences: •

Lesson learned 1: When investigating ESD problems, never remove a fix that should have worked and that did not. Try another one, then another

ESD induces 3 V in PCB traces ESD induces 5 V via I/O cables ESD induces 2 V via power supply

Figure 6.6 Conceptual view of the simultaneous effects of more than one ESD coupling path.

6.7. Conclusion: Troubleshooting Hints

•

239

one, and accumulate them until final success. Then, and only then, remove sequentially some fixes to identify which one—maybe—was useless. Lesson learned 2: Even if it is the root cause, an EMC problem may sometimes manifest only when it is accompanied by another environmental event. When it seems impossible to re-create the problem by the “forced crash” method, look out for a possible joint effect of temperature, vibration, power supply undervoltage or overvoltage, earth or ground voltage gradient, and the like.

Appendix

A

ESD Protection by Design of Chips and Microcircuits The drastic reduction in area and thickness of the active elements that continuously occur in semiconductor technology makes each new IC family more prone to ESD damage than the former one. Technologies achieving more than 1000 gates/mm2 and speed-power products much less than a picojoule, with propagation delays inferior to 30 ps, are reaching a gate oxide barrier that is so thin that its theoretical breakdown voltage is in the 15- to 20-V range. Designers of integrated circuits, hybrids, and microelectronics in general can build in a certain level of ESD hardening through layout precautions and integrated protection networks. This hardening will make the wafers, chips, and encapsulated modules safer to handle and will relieve the end user of some of the cost and burden of basic protection. Eventually, if required by especially harsh applications, complementary hardening can be added at PCB or equipment level. The following guidelines are in no way a treatise on the subject, which is amply covered by the abundant literature available throughout the IC community. And whatever the hard-bound volume that would give minute details of on-chip ESD protection networks, it would soon be outdated by the ceaseless progress in the IC technology and manufacturing processes. Construction details that were successful for one technology are not necessarily transferable to the next one. We have tried to mention only the basic protection principles that will probably remain true, whatever the integration scale. Some of the following have been inspired by the remarkable analysis of Beebe (1), Sicard et al. (2), the Military Handbook DOD 263 (3), plus some Application Notes by Texas Instruments or National Semiconductor (4–6).

Electrostatic Discharge, Third Edition, by Michel Mardiguian Copyright © 2009 the Institute of Electrical and Electronics Engineers, Inc.

240

A.1. Functions Provided by On-Chip ESD Protection Strategy

241

A.1. FUNCTIONS PROVIDED BY ON-CHIP ESD PROTECTION STRATEGY These functions are multiple, challenging, and often contradictory, therefore trade-offs have to be made. The protection techniques must: •

• • • • • •

•

Provide a low-resistance shunting path for preventing the discharge current from reaching the sensitive parts inside the chip (risk of damage by joule effect), yet appear as a high impedance for normal signals. Keep the transient voltage at the stressed pin below the gate oxide damage level of 1 kV/ μm. Be fast acting (<1 ns) and self-resettable. Be able to withstand repeated discharges with both polarities, without significant changes in their protection level and reliability. If damaged, appear as a nonexisting device, thus maintaining the functionality of the IC. Keep their protection characteristics whether the IC is powered or not. Keep their high-impedance off-state when the IC is not powered. This is an important aspect in certain bus-type applications where one subscriber card can be temporarily off, while the rest of the system is active. A protection that would set itself in a conduction state when a signal is coming in, while Vcc is turned off, could disturb an entire bus or local area network (LAN). Preserve the signal integrity and all the functional features such as: • • • • •

•

•

Input resistance and capacitance Slew rate, signal-to-noise, and distorsion (SINAD), sensitivity threshold for analog inputs Fan-out, VIL max, VOL max, VIH min, and VOH min, noise margin Transient current demand at switching, leakage current Input symmetry with differential drivers/receivers such as LVDS, IEEE1394

Do not create, or aggravate, because of nonlinearity, some undesired, non-ESD, EMI problems such as RF detection/demodulation (7), skew, and the like. Do not interfere with voltage translators used for transition between the low-voltage core circuits and the higher voltage I/O circuits of the IC.

The above list represents 10 constraints for a protection network, with some of them not easy to reconcile. In addition to these primary considerations, the design should reduce the risk of ESD overstress and damage by applying certain precautions regarding layout, clearances, and current densities. It should also, if possible, ensure, or participate in, latch-up protection.

242

Appendix A

ESD Protection by Design of Chips and Microcircuits

A.2. PRINCIPAL COMPONENTS USED FOR ON-CHIP ESD PROTECTION Most of the following considerations address not only protection performance, but also the ESD survival of the protection device itself.

Resistors On-chip series resistors are used, with values ranging from 50 to 2000 depending on the application. Polysilicon resistors, embedded in the Si02 can withstand high voltages, but at the expense of a mediocre current handling capability (poor thermal dissipation). On the contrary, diffused N− well resistors have better current handling, but mediocre voltage withstanding, with breakdown occurring between N− well and P− substrate. For input protection, 200–400 resistances are generally used. For output protection, lesser values are used, if at all, because they rapidly affect the fan-out capability, and the Vout LOW (VOL), Vout HIGH (VOH) (hence the noise margin). These resistors are often invoked as current-limiting components; however, the HBM model with its 1500- source resistance is basically a current source, and it is obvious that 200–400 hardly cause a current reduction. In fact, resistances can only be current limiters for the MM (machine model) or CDM cases; they essentially serve as voltage dividers between the first clamp at the input pad and the internal core circuits, in case of cascaded protections. They can also slightly increase the ESD pulse rise time, giving more time for a protection diode to react.

Diodes Diffused diodes are arranged in several rows of multiple contacts (10–20) for better current handling. They generally have reverse breakdown voltages in the 25to 60-V range. When forward-biased by a positive pulse with Vin > Vcc + V d, the upper diode D1 will derive the input current into the V + line (Fig. A.1). When driven by a negative pulse (Vin < Vss − V d), lower diode D2 will allow the current to close out by the Vss /D2 /input lead loop. When the IC is not connected, D2 performs by its reverse breakdown. Few disadvantages of the diode solution are associated with its parasitic capacitance and its slow reaction time. In reverse breakdown mode, its clamp voltage can be higher that what the smallest, submicron technologies can withstand. Also, with smaller and smaller technologies, the dynamic resistance of the diode (typically 20 for a 15 × 15 μm junction area) is too high for an adequate protection of the most sensitive chip circuits: in 0.12- μm technology rules, the thin gate oxide cannot stand more than 12 V. Increasing the diode area would be feasible, but at the expense of a capacitance increase, which is rapidly playing against the I/O circuits speed.

A.2. Principal Components Used for On-Chip ESD Protection VDD

VDD

R

Pad

243

R

To gate

To gate

VSS

VSS

(a) Diodes

(d) Transistors

Distributed

R

VDD

To gate To gate R (b) Distributed diodes

VSS VSS (e) Transistor Bilateral Devices

R To gate VDD R To gate Arc gap VSS

VSS (c) Zener diodes

(f) Spark gap and diodes I ΔI Rdyn. =

ΔV ΔI

ΔV

V ON "Set" voltage

Trig.

Figure A.1 Some basic input protection networks. The spark-gap (f) is made by toothed metallization patterns, and usually put up front to evacuate the bulk of the incident energy. Lower sketch shows the “crowbar” behavior of a MOS transistor above its avalanche point.

244

Appendix A

ESD Protection by Design of Chips and Microcircuits

Transistors as Crowbar Devices With MOS transistors used as triggered short-circuit switches, the interest lies in the fact that these devices already exist in the standard chip-processing library. In normal operation, the protection MOS is off. With an ESD pulse, the drain–substrate junction is driven into reverse breakdown and turns the device into a snap-back or crowbar mode (sometimes viewed as the solid-state equivalent of a gas discharge tube), whereas the protection behaves temporarily as a short, making it more efficient and less prone to thermal damage. This snap-back is attributed to the turn-on of the lateral parasitic bipolar transistor formed by the drain/channel/source (1). Another advantage is that the two CMOSs perform equally well against positive or negative pulses, hence making a bidirectional protection. The output protection, based on a similar scheme, consists in simply using the regular output CMOS transistor pair to act as crowbar protection, when needed.

Zener Diodes Instead of regular diodes, zener diodes can also be integrated in the I/O area of a chip. They have the advantage of a more precise breakdown voltage, which allows an optimized coordination with other protection components such as resistance + crowbar scheme. Such a combination is used in ICs intended for environments with severe ESD and EFT (electrical fast transients).

A.3. TYPICAL ESD PROTECTION NETWORKS Various assemblies of the resistor, diode, and transistor components are used. The protection afforded by these specific circuits is limited to a maximum current/voltage/pulsewidth combination. ESD pulses beyond these limits can degrade the protected IC, or the protection network itself. It can also result in a noncatastrophic fatigue of the IC or its protection, affecting its lifetime, a problem known as “latent failures” or “walking wounded,” since the loss of protection circuit may not be apparent after an ESD. Protection networks are designed to face all realistic discharge configurations, but not to complicate and encumber the layout with improbable occurrences. For instance, although it would not be a totally impossible event, an ESD between two adjacent pins is generally not covered by protection networks. It is assumed, and confirmed by the tests, that in such cases, the discharge will still find a path further inside the device and meet a line-to-ground protection network. Referring to the HBM test, sometimes referred to as “human skin model” or “bare-hand model,” which is less severe (100 pF/1500 ), and thanks to the protective networks integrated by IC manufacturers, typical failure thresholds have been raised from 2 kV (i.e., a 1.3-A short-circuit current) in the early 1980s to about 6 kV (4 A) in the late 1990s.

A.4. Some Design Precautions to Improve ESD Immunity of ICs

245

Typically, an ESD test will stress: • • •

All pins vs. all power and ground pins. Power supply pins vs. ground pins. In addition, I/O pins dedicated to external functions (hence susceptible to being connected to long external cables) may be stressed vs. other I/O pins.

Figures A.2–A.5 show some examples of ESD protection networks used by current IC manufacturers. As technologies and fabrication techniques evolve, design philosophies and circuitry are evolving too, bringing more refinements in protection networks. Many elements of these networks are using parasitic transistors and diodes created as a by-product of the process.

A.4. SOME DESIGN PRECAUTIONS TO IMPROVE ESD IMMUNITY OF ICS The following is a brief sample of techniques commonly used by IC manufacturers: 1. Avoid as much as possible cross-unders beneath metal leads connected to I/O pins. When cross-unders are diffused during the N+ (emitter) diffusion process, the oxide over the diffusion will be thinner, reducing the breakdown voltage in this area. Deep N diffusion should be used for cross unders, if the process has such a phase. 2. Protection circuits should be analyzed to see if the layout permits the protection diodes to be defective or blown without causing the IC to become inoperative. 3. Linear IC capacitors should be paralleled by a PN junction with sufficiently low breakdown voltage. 4. Avoid high-energy density spots in a PN junction depletion region, under ESD conditions. Use parallel elements and multifingered contacts, or enlarge the junction. For instance,

VCC

≈ 120 Ω

≈ 120 Ω

Input Poly - Si

Failure

Poly - Si

Figure A.2 Standard HCMOS input protection network. Typical cumulative figures for ESD/HBM failures are: 2050 V (1% defects) to 2700 V (50% defects). More recent processes tend to abandon the poly-Si resistors for the less fragile diffused resistors.

246

Appendix A

ESD Protection by Design of Chips and Microcircuits VCC

To gates

Input pin

VCC

D1

D3

Output pin D2

D1 and D± are parasitic diodes

Figure A.3 High-speed CMOS input and output protection used by Texas Instruments and providing a typical ESD/HBM immunity of 4500 V. The input diode becomes forward-biased for positive pulses exceeding Vcc + 0.5 V. For negative pulses, the base of the diffused transistor becomes more positive than the input line, turning the transistor ON.

VCC

IN

ALVC

OUT

Figure A.4 ESD protection circuit in advance low-voltage CMOS (ALVC) used by Texas Instruments.

Substrate resist. IN

OUT LVTTL

Figure A.5 Example of cascaded input protection in bipolar low-voltage IC, using a combination of crowbar transistors and a limiting resistor. The output transistors are powerful enough, so no additional protection components are needed.

A.5. The Latch-Up Problem

247

a. When scaling down by a k factor, going down from√1 to 0.1 μm, it is possible to apply a lesser scaling factor, such as k for the chip periphery where I/O pads and protection components are located. b. While keeping the benefits of downscaling for the chip core, the I/O pads and protection components can be arranged in a double ring, with staggered pads such as the occupied real estate is optimized. c. The effective dissipation area and contact area of the protection networks can be artificially improved by using slotted traces, multifingered shapes, and multiple contacts for diodes. 5. Avoid pin layout that put critical pins in corners since they are more prone to occasional contact. 6. Avoid as much as possible metallization crossovers because these areas are separated by thinner dielectric layers. In addition, crossovers often impose metallurgical requirements with conflicting constraints and cause ESD weak spots. Although the protection efficiency of these techniques can be tested through the standard HBM, MM, and CDM tests (see Chapter 3), the transmission line pulse (TLP), a more recent design and validation tool can be used: A calibrated square pulse is injected into the tested device via an RF-quality jig, using precision-etched stripline. By varying the pulse amplitude and duration, more insight is obtained for critical failure parameters of each IC pin, including I ,V curves and mismatch. It has also the advantage of capturing many critical parameters without overstressing the device. It is also easily simulated by sofware tools such as SPICE, and its results are correlatable to those of a real HBM or CDM pulse with equivalent (current × time) area.

A.5. THE LATCH-UP PROBLEM Although it is not unique to CMOS circuits, one example of a latch-up situation is shown in Figure A.6. Most CMOS devices have one PNP and one NPN lateral parasitic bipolar transistor, resulting from the embedded ESD protection diodes. Being sufficiently close, they form a parasitic silicon-controlled rectifier (SCR). When one of the PN juction is forward biased, such as with an overvoltage exceeding (Vcc + 0.5 V), it supplies enough current to drive the other transistor into saturation. Provided that the product of the two gains is >1, and that the current exceeds the SCR hold current, this onset of a quasi-short circuit between Vcc and ground can last indefinitely after the pulse is gone. It may end up in IC destruction, if the current is not limited. Such inadvertent firing can be prevented by: • •

Guard rings alternatively connected to Vcc and ground. Increasing the separation between the PN diode and the N− well of the active device, thus reducing the gain of the lateral NPN parasitic transistor.

248

Appendix A

ESD Protection by Design of Chips and Microcircuits Input

VCC

P channel output

P+

P+

VCC

Output Ground

N+

P

N channel output

Ground

N+

N+

P well N substrate

VCC P channel gate output

VCC N substrate resistance

N channel and P channel outputs are connected together P well resistance

N channel gate output

Figure A.6 (Top) Cross section of a typical CMOS inverter showing the parasitic bipolar transistors. (Bottom) These parasitic transistors are naturally configured as a SCR.

A.6. COMPARING STRESSES OF HUMAN BODY, MACHINE, AND CHARGED DEVICE MODELS, AND IEC 61,000-4-2 DISCHARGE Although the HBM test criteria is the most frequently invoked in the vendors electrical characteristics of ICs, others test models are progressively introduced (see Chapter 3), corresponding to other-than-human events. Some manufacturers have also undertaken the challenge of offering a full IEC test level 4 compliance at the IC level, thus making life easier for the equipment designer, who is released from the need of additional protection components. The latter is especially true for bus drivers/receivers intended for telecommunications and data transmission in severe environments. The following calculations are comparing the respective stresses of the above-mentionned test models, as seen by the protection components integrated

Comparing Stresses of Human Body

249

Table A.1 Comparison between Respective Parameters for HBM, MM, CDM, and IEC Test Pulses ESD Test

Cd

Discharge Network

Zdyn

RC or Ringing Frequency

Minimum Requirement

HBM MM CDM IEC

100 pF 200 pF 10 pF 150 pF

1500 15 + 0.5 μH 1 + 30 nH 330

1500 56 65 500 a

150 ns 15 MHz 300 MHz 50 ns

2 kV (1.33 A) 400 V (7 A) 500 V (8 A) 2 kV (4 A)b

a This

impedance is due to the RLC circuit of the IEC, whose resistance Rd , combined with the self-inductance of the simulator 2-m ground strap is just above the critical damping. b This current correspond to the second hump of the hand/metal discharge IEC waveform, that is, the energetic portion of the pulse (see Chapter 4). The initail ultrashort 7.5 spike has been neglected for this comparison.

into the chip. TableA. 1 shows the basic parameters for comparing four standard ESD test pulses. The third column gives the discharge network impedance for each model. For the CDM, a 1- default resistor has been entered since no other resistor than the test jig wiring and contacts is specified, the discharge resistance being simply that of the device under test, pin-to-pin. The fourth column gives the total impedance of the discharging network, in short-circuit condition. For the HBM and the IEC, the source resistance Rd is such that it forces a unipolar, overdamped pulse. For the MM and CDM, the L,C values are causing a ringing pulse with a corresponding dynamic impedance Zd , such that the pulser is a voltage source for all loads < Zd . The last column is indicative of a minimum voltage requirement for each test, along with the corresponding short-circuit current. In principle, with a single pulse, it is the energy that is important for a parametric degradation or hard failure. Power is not a relevant figure because it only relates to the instantaneous peak power. For instance, let us assume a CMOS input protected by a 300- series resistance. For an HBM test with 2 kV, the peak current will be 2000 = 1.1 A 1500 + 300 P (peak) = Ri2 = 300i 2 = 360 W

Ip =

Energy = P t average = 360(0.5RC) = 360(0.5 × 150 ns) = 27 μJ With one ESD pulse/second, the average power is W × F = 27 μW, which is extremely low because the duty cycle is also extremely low. Yet, 27 μJ is about 10 times what an IC-embedded component can tolerate. The next comparison, in TableA. 2, is an attempt to evaluate the respective energy threats of the four types of ESD pulses, whose amplitudes have been choosen as having approximately the same risk of occurrence (a relatively common risk, in that case). It was assumed that the full pulse current was delivered

250

Appendix A

ESD Protection by Design of Chips and Microcircuits

Table A.2 Comparison of Energies Delivered by Four Standard ESD Tests for Moderate Severity Level HBM/2 kV

MM/400 V

CDM/500 V

IEC (hand/metal)/2 kV

10 /300 Ipeak 1.3 A/1.1 A W 1.3 μJ/33 μJ

10 /300 7 A/1.27 A 8.5 μJ/15 μJ

10 /300 7.9 A/1.66 A 1.2 μJ/1.2 μJ

10 /300 4 A/3 A 4 μJ/130 μJ

HBM, 2 kV

M.M., 400 V 7A

1.1 A

1.3 A RC 150 ns

180 ns

50%

CDM, 500 V 7.7 A

1.1 A 25 ns

60 ns

3 ns

1.4 A 3 ns

30 ns Into 10 Ω load

Into 300 Ω

Into 10 Ω load

Into 300 Ω

Into 10 Ω load

Into 300 Ω

IEC 61000-4-2 (2 kV) 3A

4A

90 ns

60 ns Into 10 Ω load

Into 300 Ω

Figure A.7 Discharge current waveforms for the scenarios of TableA. 2.

into two sorts of protection components: a 300- series resistor or a 10- shunt resistor, typical of the ON resistance of a clamping diode. Notice that depending on the load, high Z or low Z, the same test may behave as a voltage or a current source. Such extreme load variation also has an impact on the pulse duration, hence on the energy delivered. (See Fig. A.7.) The bottom line of the comparison is that for a 300- protection resistor, the IEC is by far the biggest threat, followed by the HBM. With the 10- load, it is the machine model that causes the highest energy, followed by the IEC. One should notice, however, that the CDM discharge into 10 delivers the highest current of all. Although the duration of this current is extremely short, its impulsive nature corresponds to the highest dI/dt derivative, creating a thermal shock that can be more damaging than the other tests.

REFERENCES 1. Beebe, S. G. Characterization, Modeling and Design of ESD Protection Circuits. SemiConductor Research Corp. T.R., 94SJ116, 1998.

References

251

2. Sicard, E., and Bendhia, S. Advanced CMOS Cell Design. McGraw-Hill, New York, 2006. 3. Military Handbook DOD-263. ESD Control Hand Book for Protection of Electrical & Electronic Equipment. 4. Design Considerations for Logic Products. Texas Instruments Application Notes, 1998. 5. National Semiconductor. Application Note AN248. 6. Diep, T., and Durvury, C. ElectroStatic Discharge. T. I. Application Report SSYA 010, Jan., 2001. 7. Chun, J-H., and Murmann, B. Analysis & Measurements of Signal Distorsion Due to ESD Protection Circuits. IEEE Journal on Solid State Circuits, Oct., 2006.

Appendix

B

Prediction of ESD Damage Level for a Semiconductor Junction Using some of the simple models of device failure given in Reference 1 of Chapter 1, the human body voltage at which a semiconductor junction may be damaged can be estimated. The following calculation is more accurate than the quick triangular pulse fit, used in some calculations of Chapter 2. We will use as an exemple Figure B.1 and B.2. The emitter–base junction being the smallest physical area, and being connected directly to the package leads, it is assumed that it will be a prime candidate for failure. The following constants will be used: A, cross section offered to the current path = 10−6 cm2 Rb , internal resistance near the emitter–base junction = 25 VRbd reverse breakdown voltage = 10 V Human body parameters will be chosen similar to the HBM model of MIL. Std 883: RH (through human skin) = 1500 CH = 100 pF The discharge time constant of the human-to-device contact can be estimated. Neglecting the other contact resistances in series in the path (such as

Electrostatic Discharge, Third Edition, by Michel Mardiguian Copyright © 2009 the Institute of Electrical and Electronics Engineers, Inc.

252

Appendix B Prediction of ESD Damage Level for a Semiconductor Junction

253

.1

.3

1

3

10

30 100 300 1000 100,000

10,000

10,000

1,000

1,000

100 .01 .03

.1

.3

100 30 100 300 1000

1 3 10 Time in μs

Average power density in kW/cm2

Average power density in kW/cm2

Time in μs .01 .03 100,000

Figure B.1 Average power density across a reverse-biased emitter–base junction (NPN transistor) causing a failure of ≥5% of devices (Ref. 1 of Chapter 1).

RH CH

IESD

e

I

b Ip

RB VRBD

.38Ip τc

5 × τc

Figure B.2 Simplified equivalent circuit for damage threshold approximation.

chip-to-leads, lead-to-finger, lead-to-ground, etc.), since they represent no more than a few ohms, the time constant is τ = (Rb + RH )CH = (25 + 1500)100 × 10−12 = 152 ns If we consider that the full pulse width is reached at 5 × Tc , or 760 ns, we are able to determine the maximum permissible power averaged over 760 ns. From the graph in Figure B.1, in the microsecond range, the maximum power density that a reverse-biased silicon PN junction can handle is about 2000 kW/cm2 for 0.76 0.76 μS, corresponding to 1.5 J/cm2 . Since A = 106 cm2 , the average tolerable power is Pav = (2000kW/cm2 ) × 10−6 = 2 W

254

Appendix B Prediction of ESD Damage Level for a Semiconductor Junction

On the other hand, the power created by the ESD current through the device is P = VRbd i + Rb i 2

(B.1)

with i = Ipe−t/τ The first term represents the power in the reverse-biased barrier, and the second term is the power dissipated in the internal device resistance, near the emitter–base junction. Replacing i by its expression yields P = VRbd Ipe−t/τ + Rb (Ipe−t/τ )2

(B.2)

Averaging the expression from t = 0 to t = 5τ, the following is obtained: 5τ 5τ 1 1 Vrbd Ip e−t/τ d t + Rb Ip e−2t/τ d t (B.3) Pav = 5τ 0 5τ 0 RB Ip 2 Vrbd Pav = Ip (1 − e−5 ) + (1 − e−10 ) 5 10 1 1 ≈ (VRbd Ip) + (Rb I 2 p) 5 10 Since Ip(Vesd − VRbd )/(RH + Rb ) ≈ Vesd (1500 + 25). Replacing Pav by the 2-W limit calculated before, and Ip by its expression, yields 10 Vesd 25 Vesd 2 2= + 5 1525 10 1525 Solving this quadratic equation for (Vesd ), ignoring the imaginary root, we get Vesd = 885 V or

Ip = 885/1525 = 0.58 A∗

Therefore, this device is vulnerable if handled by a person charged above 885 V. A more accurate calculation could be carried out by considering that Vrbd itself varies with current and temperature, both of which vary during the ESD pulse duration.

∗ The simplifed equation using the triangular approximation for an exponentially decaying pulse would have given Ip = 0.7 A and Vesd = 1060 V, a 20% optimistic result.

Appendix

C

Spark-Over Voltages Air gaps have been used for a long time against lightning surges or other kinds of transient overvoltages. Their response is much too slow for making accurate, dependable ESD protection, except in some specific cases where only a bulk breakdown device would be sufficient. However, the understanding of high-voltage arcing mechanism is useful for some testing and box design aspects, where clearances and arc creeping can lead to some peculiar ESD vulnerability of electronic equipment, as explained in Chapters 4 and 5. The voltage at which a given air gap will arc depends on the shape of the electrodes, the micrometric roughness of their surfaces, the air pressure and temperature, and eventually their speed of approach if one electrode is mobile. Provided that (a) the voltage is dc or at a frequency low enough to allow a complete deionization of the channel between two consecutive arcs and (b) the gap itself is dry and dust free, spark-over voltages are given by the law established by Paschen in 1889, from which the curves in Figures C.1 and C.2 are derived. They show that in the range of 0.3–3 atmosphere (1 atm = 1016 mbar, or 15 psi), the breakdown voltage is about proportional to the exact pressure and gap length. Little more accurate than the gross 10-kV/cm rule-of-thumb for sharp edges, a coarse approximation for millimeter to few centimeter gaps can be used: (1) •

For flat, or large radii spherical electrodes: √ V (kV) = 3pd + 1.3 d

•

For sharp, needle electrodes: V (kV ) = pd + 0.7

where d = gap length, mm p = atmospheric pressure, atm This simple law can give acceptable estimates within the gap range indicated. Unfortunately, it suffers from many limitations, making it unreliable, as soon Electrostatic Discharge, Third Edition, by Michel Mardiguian Copyright © 2009 the Institute of Electrical and Electronics Engineers, Inc.

255

256

Appendix C Spark-Over Voltages

1.5

4.5

0.1

Air pressure in PSI 15

45

1 Air pressure in kg/cm2

150 10

100

100 A

50

50

30

B1

20

20

10

10

5

5

3

3

B2

2

2

1

1

.5

0.5

.3

0.3

Sea level atmospheric pressure, 20°C Air pressure in kg/cm2 1

0.1 1.5

4.5

15

Sparkover voltage in kV

Sparkover voltage in kV

30

10 45

150

Air pressure in PSI

Figure C.1 Spark-over voltage versus air pressure for (A) smooth spherical electrodes, with diameter ≥ gap distance, for a 1-cm gap. (B1) needle gap, 1 cm; (B2) needle gap, 1 mm.

as some conditions are changed, as often is the case with natural or re-created ESD (2): •

•

When the speed of approach becomes significant, the air gap can with stand much greater voltages before it breaks, with values exceeding 10 kV/mm (2, 3). When the electrodes get very close, say in the submillimeter range, two mechanisms are interacting (2): • The normal gaseous discharge whereas gas electrons are freed and accelerated by the strong E field, getting enough energy to collide with other molecules, creating more ions (ionization) and starting an avalanche. • The surface discharge, where the microscopic surface irregularities start melting, due to the high current concentration, adding metal molecules into the plasma.

References

257

Gap spacing in mm 1

2

3

5

10

20

30

50

100

50

50

A

30

30

20

20 B

10

10

5

5

3

3

2

2

1

1

2

3

5 10 20 Gap spacing in mm

30

50

Breakdown voltage in kV

Breakdown voltage in kV

100

100

1 100

Figure C.2 Spark-over voltage versus gap spacing at normal atmospheric pressure: (A) smooth spherical electrodes, with diameter ≥ gap distance. (B) needle gap.

The breakdown voltage is also inversely proportional to the absolute temperature. Certain synthetic gases have higher arcing voltages than air. Sulfur hexafluoride (SF6 ) and Freon 12 (CCI2 F2 ) have a dielectric rigidity about 2.5 times higher than air, for similar conditions. This is why such gases, enclosed in a sealed bulb at high pressure, are used in high-voltage relays and switches with minimum arcing and multiple reclosures (showering arc) problems. Finally, when the air pressure becomes very low (<0.01 atm), heading toward vacuum conditions, the air breakdown voltage ceases to fall off and, below about 6 × 10−3 atm, starts increasing again.

REFERENCES 1. Jonassen, N. Ions. Compliance Engineering Magazine. No. 3, 1999. 2. Bonisch, Kalkner, and Pommerenke, D. Broadband Measurements of ESD Risetimes vs Discharges Mechanisms. Journal of Electro Statics, Oct. 2002. 3. Shinobu, I., Junji, O., and Takashi, I. Breakdown Voltages in Very Small Gap Discharges. Zurich EMC Symposium, 1999.

Appendix

D

Fatigue Phenomena During Repeated ESD Testing Chapter 2 mentioned the problem of the “walking wounded” or latent failures, that is, devices that still function after repeated ESDs but whose life span has been severely reduced. All the specifications dealing with device testing and QC acknowledge this fact by requesting that all samples that have been submitted to testing not be used for production. However, what about the hundreds of ICs that have been stressed when a complete system is tested to ESD? One could argue that this is a second-order problem because these parts are not directly zapped, being subjected to much lesser voltages as a result of induction coupling with low energy. This is not totally true: •

•

A direct ESD can sometimes strike directly a component, with its full amplitude and duration, via a connector pin, an exposed LED or switch, a keyboard, and the like. Even with purely indirect discharges, the repetitive nature of an intensive ESD can impose on some exposed modules, thousands of transients reaching hundreds of volts range. We must keep in mind, too, that unlike module testing, which is generally made at 20◦ C, the ambient inside the EUT during a machine test can be at 50–55◦ C, with junction temperatures approaching 85◦ C. This creates at least three aggravating conditions: • •

The breakdown voltages decrease when temperature increases. All fatigue phenomena accelerate exponentially with temperature, per Arrhenius∗ theory.

∗ The Arrhenius law (1889) describes the speed of variation of a chemical interaction as a function of temperature.

Electrostatic Discharge, Third Edition, by Michel Mardiguian Copyright © 2009 the Institute of Electrical and Electronics Engineers, Inc.

258

Appendix D Fatigue Phenomena During Repeated ESD Testing •

259

All electromigration phenomena also increase with temperature. They tend to grow ramifications between conductors, which locally increase the field gradient, and the problem becomes self-aggravating. They also create aluminum pile-up at some places and thinning at others, until current densities of 108 –109 are reached where cracks and melting occur.

So far, none of these aspects has been considered during equipment testing. It may very well be that this problem is a false one, but it would be certainly worthwhile to consider it, to ascertain wether an EUT sample that has endured several cycles of complete ESD checks can be shipped without a reduced reliability.

Appendix

E

Prediction of ESD-Induced Noise by Fast Frequency-Domain Calculations This appendix describes what a frequency-domain analysis can do compared to a simple, straightforward time-domain calculation. Readers not familiar with the basic concept and practice of spectral density, graphical convolution, and the like may find the following futile or useless. But a complete analysis of the cascade of frequency-dependent mechanisms involved with ESD coupling can be very useful for understanding the critical factors and optimize the hardware solutions. In this respect, this appendix is a theoretical companion to appendix F, where actual test results are presented. In order to complement the numerical example of Section 2.6 where an ESD was coupled into a short segment of flat cable, the same example (Fig. E.1) will now be conducted using frequency domain such that all the mechanisms involved will be more visible. The following calculation steps, inspired by the EMI methodology and procedures of White and Mardiguian (1), are generally using the simplified graphical Fourier spectrum envelopes, instead of the exact plots of the Fourier functions: 1. Convert the ESD current pulse into a spectral density plot, which translates the A/μs time-domain waveform into the A/MHz of a spectral envelope. 2. Apply the current-to H -field radiation coefficient (Ampere’s law) to express the corresponding H field at a distance d. 3. The result of step 1 combined with step 2 is a new spectral envelope, showing the magnetic field spectral density, in (A/m)/MHz vs. frequency. Electrostatic Discharge, Third Edition, by Michel Mardiguian Copyright © 2009 the Institute of Electrical and Electronics Engineers, Inc.

260

Appendix E Prediction of ESD-Induced Noise

261

PCB #1

Ov Ref. Grnd to chassis

25 cm

IESD

PCB #2

4 cm 8 cm

Figure E.1 Coupling example of a D-ESD illuminating a nearby cable.

4. Apply the H -field-to-loop conversion factor, which is a frequency-dependent term giving the volts induced in a given loop area. 5. The result of step 3 multiplied by step 4 is the spectral envelope of loop voltage, in V/MHz, across the entire frequency spectrum. This cascade of frequency-related mechanisms is conceptually shown in Figure E.2, for an 8-kV hand/metal, IEC-type discharge. Instead of performing the Fourier transform of the complex ESD pulse, the waveform has been broken down into its two components. For each one, a T → F conversion has been made, using the formulas of Appendex H for exponential waveforms: 1. The long pulse Ipeak amplitude = 16 A, Fall time constant Tc (0.37height) = 50 ns, reciprocal frequency F1 = 1/πTc = 6.4 MHz. 10–90% rise time ≈ 10 ns, reciprocal frequency F2 = 1/πtr = 32 MHz. Initial spectral density, for F < 6.4 MHz: 20 log ATc = 20 log(16A × 0.05 μs) = −2 dBV/MHz 2. The very narrow initial spike Ipeak = 30 A. Fall time constant Tc (0.37height) = 1.3 ns, reciprocal frequency F1 = 1/πTc = 250 MHz.

262

Appendix E

dBA/MHz

Prediction of ESD-Induced Noise

2

Unipolar Pulse 1 Tc

1 −20 dB

t 2

(a) −40 dB F2

F1

−40 dB F

F′2

dBA/m/A Ampere’s law (b) F dBV/(A/m) K field-to-loop (c)

+20 dB λ/2

3λ/2 F

dBV/MHz

(e)

F SE dB 40 20 0

F

dB Volts/MHz: (e) − S.E. Oscill. Pulse

F

Figure E.2 Conceptual view of the spectral envelope and transfer function method. The SE curve is the shielding effectiveness of metal barrier with a slot, reaching 0 dB when slot length = λ/2.

Appendix E Prediction of ESD-Induced Noise

263

Rise time ≈ pulse width at 50% heigth = 1 ns, reciprocal frequency F2 = 1/πtr = 320 MHz. For simplifying the calculations, since F1 and F2 are very close, a unique frequency of 300 MHz will be used, above which the spectrum will roll-off at a −40 dB/decade slope. Initial spectral density, for F < 300 MHz: 20 log ATc = 20 log(30A × 0.0013 μs) = −28 dBV/MHz. The spectra of pulse 1 and 2 are overlaid on a same plot (a), revealing two frequency regions: First, below 50 MHz where the spectrum of long pulse (1) overshadowes (2), such this latter can be neglected. Second, above 50 MHz where spectrum (2) is the dominant one and (1) can be neglected. Curve b in Figure E.2 is simply Ampere’s law expressed in (A/m)/A, giving the H -field at distance d for a unity current. For a distance d

(cm) = 8 + H =

4 = 10 cm = 0.1 m 2

I = (1.6A/m)/A 2π0.1

or

4 dB[(A/m)/A]

The long-wire model of Ampere’s law has no time (hence no frequency) dependency and can be used as long as the length of effective radiating segment, and the distance to target are < λ, condition that can be accepted here up to approximately 750 MHz. If this was not true, more complex modeling, using the method of moments, would have to be used. Curve d of Figure E.2 shows conceptually the field-to-loop coupling, in volts induced per amperes/meter of incident magnetic field. This curve shows an increase with F , which is a +20 dB/decade slope, since it relates to the derivative of the flux (μ0 H S) over the time. The nomogram of Figure E.3 gives directly this coupling in dBV per A/m, for several loop lengths l. When we reach the frequency corresponding to l = λ/2, that is, l(m) = 150/F (MHz), the conductor behaves as a tuned dipole, and from then on the induced voltage is clamped on a horizontal asymptote. Actually, as frequency keeps increasing, the induced voltage is running through a succession of maxima at every (2n+1)λ and nulls every 2n(λ/2), but the maxima keep a constant amplitude. This holds until the loop height h also reaches λ/2. Above this point, the effective capture area shrinks as frequency increases, shown by the −20-dB/dec (or 1/F ) slope. Finally, the decibel sum of the current spectrum curve (a) + current-to-field conversion (b) +H -field-to-loop coupling (d), produces the total loop voltage spectral density (e) in dBV/MHz induced into the loop. It shows clearly the predominance of the 300-MHz region because this is where coupling is maximum, while the ESD current spectrum still exhibits a high, nondecreasing amplitude. Above 300 MHz, the antenna efficiency of the 25 × 4 cm loop progressively

264

Appendix E

Prediction of ESD-Induced Noise dB Volt/A/m

1 MHz

3

10 MHz

30

100 MHz 300

1 GHz

3

10 GHz

3

2

18 dB

0

1

−10 dB −20 dB

A

−30 dB

B

−40 dB

C

−50 dB

D

1 MHz

3

10 MHz

30

100 MHz 300 Frequency

1 GHz

3

10 GHz

In region 1 (l < λ/2): K dBV/A/m = –62 + 20 log (l cm × h cm) + 20 logFMHz In region 2 (where l l > λ/2): K = 18 dB + 20 log hcm In region 3 (where l and h are > λ/2): K = 95 – 20 log FMHz, for any value of"h" Curve A: l = 30 cm Curve B: l = 10 cm Curve C: l = 3 cm Curve D: l = 1 cm All curves made for h = 1 cm. For other values of h, add 20 log h(cm).

Figure E.3 H-field-to-loop coupling vs. frequency, for uniform illumination of a loop with dimensions l × h.

ceases to increase, while the current spectrum—hence the field—rolls off like 1/F 2 (−40 dB/decade). What remains to be done is to integrate the V/MHz spectral density (e) across successive frequency intervals, like half-decades, such as V/MHz × (Fn − Fn−1 ) = Volts represented by the (Fn − Fn−1 ) interval The entire process is displayed in Figure E.4 in graphical form, and in Table E.1 in tabular form, giving a total induced (open) voltage of 540 V, fairly close to the 600 V of the coarse time-domain result of the Section 2.6 example. Note the following:

Appendix E Prediction of ESD-Induced Noise

30

265

IAmp 1

2

Tc = 50 ns 10 (a)

0 −10 −20 −30

20

40

tns

60

−2 dBA/MHz −16

1

2

−28

−40 −50

3

30

F1 10

100

300

1000

FMHz

+4 dBA/m/Amp

(b)

FMHz (c) 0

−2 dBA/m/MHz

−10 −20

−12 −24

−30 −40 (d)

10

FMHz

100

K field-to-loop dBV/A/m

28 18

20 10 0 (e) 0

+4

dB Volt/MHz

−10 −20

1000

100

1 10

2 30

100

300

Figure E.4 Detailed graphical process for the ESD-to-cable coupling example. (a) Spectral density of waveforms 1 and 2; (b) current-to-H -field conversion, for a 10.5-cm distance; (c) H -field spectrum density resulting of (a) + (b); (d) Field-to-loop coupling factor for a 25 × 4 cm loop; (e) final voltage spectrum, resulting of (c) + (d).

266

of partial voltages integration, 0 → 1000 MHz: 540 V.

1.2 V

0.03 V

−6 −4 −12

−22 −20

−42 −40

−2 −28 +4

6 MHz

−30

−2 −28 +4

1 MHz

−2 −28 +4

0.1 MHz

3V

−4

−2 −4

−6 −28 +4

10 MHz

12 V

−4

+8 −4

−16 −28 +4

30 MHz

20 V

−11

+18 −6

−36 −28 +4

100 MHz

180 V

−1

+28 +4

−56 −28 +4

300 MHz

Field-to-Cable Broadband Prediction by Frequency

Detailed Calculation Steps of Frequency-Domain Coupling Prediction

(A) Spectral Density (dB A/MHz) Long pulse (1) Short pulse (2) (B) H-field from 1 A wire @ 0.1 m distance (dB A/m/A) (D) K field-to-loop (dBV/A/m) (E) Final induced voltage density (dBV/MHz) = A+B+D Density @ midband for partial integration (F) Integral in frequency interval: Volts x F (MHz)

Table E.1

325 V

−6.5

+26 −6

−36 +4

550 MHz

+14 −26

−48 +4

1000 MHz

Appendix E Prediction of ESD-Induced Noise •

•

267

The highest voltage spectrum is essentially due to the short initial pulse (2); translated back into time domain, this spectrum concentrated around 300 MHz corresponds to a damped oscillatory signal, with a 3-ns period and a 50% pulse width ≈ 1 ns. The longer pulse (1) is playing a minor role for the voltage induced on this short piece of cable: Its contribution stretches from a few megahertz to about 50 MHz, totaling ≈ 35 V.

These values represent the common-mode (CM) voltage appearing in series in the loop. Since the PCBs signal references (0 V) are grounded at both ends, the CM noise rejection is extremely poor, assuming the link is single ended (nondifferential). In addition, since CMOSs have a high input impedance, the full CM voltage will appear at the input end [see Section 2.5, Eq. (2.7)] of the victim circuit. Hopefully, CMOS logic ICs, like all current technologies, have overvoltage protection diodes that will clamp the 600-V pulse amplitude seen by the chip to ≤ 20 V. Thus, we are left with a nondamaging 20-V/1-ns pulse, which is still capable of causing logic errors. However, the H-CMOS with 4-ns rise time offers a bandwidth limitation, compared to the spectral occupancy of the H -field-induced pulse. Therefore, an attenuation due to bandwidth (BW) rejection can be accounted for: BW rejection ≈ [1 + (pulse BW/logic BW)2 ]1/2 ≈ [1 + (logic time constant/pulse width)2 ]1/2 √ = [1 + (4 ns/1 ns)2 ] = 4 So, functionally speaking, the 20-V pulse will be finally perceived as 20 V/4, or 5 V. This is still way above the 0.7-V noise margin of the H-CMOS, and a further seven times reduction factor (17 dB) will be needed. An interesting follow-up exercise is shown next, assuming that the cable is inside a metal enclosure presenting a 10-cm aperture leakage in the vicinity of the discharge.

ESD Coupling after Reduction by Shield Aperture In the example of Section 2.6, a bulk voltage of 600 V was induced in the exposed cable loop. Then, in Section 5.4.1 dealing with box shielding, a 15-dB attenuation (a 5.5 times ratio) was expected from the metal enclosure with a 10-cm slot. However, this slot attenuation had been computed at 300 MHz only. ESD being a broad spectrum, reasoning on a single frequency is an oversimplification: Actually, the final voltage in the victim circuit results from a cascade of frequency-dependent mechanisms, slot leakage being one of them. This same 10-cm slot leakage example can now be recalculated by using the same spectrum intervals as in Table E.1, and factoring in each interval the average value of the slot leakage for this frequency band, using the graph already

268

Appendix E

Table E.2

Prediction of ESD-Induced Noise

Attenuation of Shield with a 10-cm Slot, Applied to Flat Cable Example

Frequency Voltage-Induced Average Attenuation New Induced Interval (MHz) without Shield (V) of a 10-cm Slot (dB) Voltage (V) 1–10 10–30 30–100 100–300 300–1000 Total ≈

4.2 12 20 180 325 540

50 (or 300 times) 35 (or 55 times) 25 (18 times) 15 (5.5 times) 5 (1.8 times)

0.014 0.2 10V 32 180 220

Global Attenuation

2.5 (or 8 dB)

presented in Figure 5.20 for slot attenuation. The results are listed in Table E.2. The global attenuation is 20 log(570/235) or 8 dB. The quick approximation of 15 dB obtained in Section 5.4.1 was optimistic by 7 dB because it neglected the broadband nature of the phenomenon. This whole frequency analysis is interesting in several ways: •

•

•

It shows that, without any enclosure shielding, the ESD radiation coupling is privileging strongly the higher frequency content of the spectrum, that is, the portion corresponding to the sharp, 1-ns precursor. This domination of the high-frequency part is furthermore exacerbated when a metal barrier with a slot is inserted between the source and the victim loop (see Fig. E.2, lower curves). We now have a double-derivative mechanism, whereas the field-to-loop coupling, a first derivative, is cumulating with the slot leakage, another derivative function, leading to a sharp response of the system. It shows in which frequency regions the design (or fixing) solutions should be optimized. For instance, floating the PCB 0 V reference ground plane from the chassis on one (or both) boards, a viable solution against Low frequency LF ground loops would be useless here. The PCB-to-chassis parasitic capacitance (typically 30–100 pF) would shunt the common mode isolation from the chassis above approximately 10 MHz, while the biggest coupling contribution is made by the 100- to 500-MHz portion of the spectrum. In contrast, ferrites and ceramic capacitor filters would work at their best and could provide the 17-dB reduction needed.

REFERENCE 1. White, D., and Mardiguian, M. EMI Control Methodology & Procedures. ICT, Gainesville, 1989.

Appendix

F

More Experiments on ESD Coupling to Boxes A follow-up of the ESD experiments described in Chapter 2 was carried on 2008 by the author, using more recent instrumentation and a faster IEC 61000-4-2 simulator. To avoid spurious ESD couplings interfering with measurements results—a frequent issue when one tries to capture ESD effects with an oscilloscope—the experiments were conducted in a shielded room with the oscilloscope located outside. The essential features of the set-up are summarized hereafter.

Figure F.1 Test box with cover removed, showing the 4.2-cm Moebius loop and its feed-through connection on the rear plate, leading to the shielded room connector panel. •

A 20 × 20 × 20 cm box, made of 5-sided welded steel sheet, with a rigid cover is used as a discharge target (Fig. F.1). A calibrated Moebius loop

Electrostatic Discharge, Third Edition, by Michel Mardiguian Copyright © 2009 the Institute of Electrical and Electronics Engineers, Inc.

269

270

Appendix F

•

•

More Experiments on ESD Coupling to Boxes

(An H-field loop shielded against an E-field) is mounted inside, with a N feed-through allowing a direct output of the received signal through the room connector panel without any interconnecting cable. This reduce the risk of the ESD current polluting the measurements via too many connectors and cable shields transfer impedances. The internal face of the box opposite to the cover was covered with a thick, 5-mm ferrite mat to attenuate the self resonances of the box that could obscure the readings. The cover is a 2-mm thick steel plate, pressed via 100% fingerstocks and spring-loaded latches on the periphery of the box edges. Some alternate cover plates with calibrated leakages are used for some experiments. The discharge current returning to the ESD gun ground post is measured via a miniature current probe (Tek. CT-6), having a flat response from 100 kHz to 2 GHz and up. Thus, the probe read-out is practically a mirror image of the current without any derivation effect (Fig F.2).

Figure F.2 Direct discharge on box edge. The ESD simulator is a Schloder model 30000.

•

In addition to direct discharges, I-ESD was also made on a 0.40 × 0.25 m vertical coupling plate (VCP) standing at 5 cm from the open box edge, that is 12 cm from the Moebius loop center.

DATA ON THE INSTRUMENTATION USED Tektronix Digital Sampling Oscilloscope, DPO 7254, 2.5 GHz/20 GigaSamples/s

Purpose of the Validation Tests

271

Schl¨oder ESD Simulator SESD-3000, with 150 pF/330 head Moebius loops: #1 4.2-cm diameter, antenna factor: 2.5 dB A/m/V, from 75-750 MHz (model similar to the one described in Chapter 4 Ref. 23) #2 2.2-cm diameter, antenna factor: 8 dB A/m/V, from 150–2500 MHz Tektronix CT-6 current probe, Zt = 5 (or 5V/A) in 50- load, 200 kHz → 2 GHz

PURPOSE OF THE VALIDATION TESTS (a) Collect more data on the actual ESD radiated coupling to circuits located inside a metallic enclosure with various, artificially made shielding alterations. (b) Confirm that with the IEC-type pulse, the precursor current spike is confined to the discharge tip/target zone, and does not return by the simulator ground cable. (c) Verify if the ESD on a VCP, virtually isolated by high value resistotrs, is mostly exciting an E-field, and little H-field, in the near region. Get a measure of the E-field/H-field sharing when the VCP is more directly grounded to the reference plane without series resistor. Note: There was no intent to measure the actual H-field generated by the discharge: an abundant data base is available (see Chapter 2), and the confined geometry of the small size shielded room, plus a reduced size VCP would have impaired the results anyway. Instead, we were interested in comparing different coupling configurations.

Summary of the experiments and results All tests were made at a 5-kV level and contact discharge (pointed tip). Some findings are almost self-explanatory on the following series of oscilloscope screens. Comments and discussion are added when necessary. Figure 3:

Calibration and reference level with plain cover closed. Largest signal (Chan. 1, 6.5V/div, peak amplitude 9A) is the current returning to the gun. The current probe is closely tracking the main current pulse, but as expected, the 19A precursor spike is missing. The narrow 2-ns hump barely emerging from the rise front is a radiated effect of the precursor current on the last segment of the generator ground wire, near the current probe.

272

Appendix F

More Experiments on ESD Coupling to Boxes

The small signal from the H-field loop (Chan. 2, 10 mV/div) indicates what will be the spurious noise, floor level of the experiment, hence a baseline for the dynamic range.

Figure F.3

Figure F.4:

Cover removed, discharge on box edge. Largest signal, Chan. 1 (6.5V/div) is the current returning to the gun. The small signal, Chan.2 (500 mV/div) is the Moebius loop output. The ratio of this signal to the noise baseline of Figure. F.3 gives the dynamic range of this set-up: 1.8V/(5.10−3 V) = 360(or 51 dB) This value corresponds also to the overall shielding of the closed box for such wideband pulse. The ringing of this signal is caused by the high frequency limitation (≈ 800 MHz) of the 4.2-cm diameter loop, whose self-resonance is excited by the tail end of the spectrum. Not shown, an additional checking was made of the possible parasitic pick-up by the N connector through the shielded room wall, by replacing the Moebius loop by a 50 coaxial load. No signal was detected above the 2 mV sensitivity threshold of the oscilloscope.

Purpose of the Validation Tests

273

Figure F.4

Figure F.5:

Cover closed. An artificial leakage is created underneath the cover edge, by putting a triple thickness of paper (total 200 μm) over 10-cm length of the fingerstock gasket. Channel 2 reading (50 mV/div) centered on the 0V trace, shows a damped sinewave with 200 mV maximum amplitude. The 0.7 ns period of the oscillation correspond quite well to the self resonance of a 10 cm slot antenna (1.5 GHz) reradiating inside the box. Based on this voltage, the new shielding effectiveness of the leaky box can be recalculated, by comparing Fig. F.5 with Fig. F.4 (no cover): SE = 20 log(1.8V/0.2V) = 19dB Compared to the 51 dB of the tightly closed box, the loss of shielding is huge, in spite of the fact that the 10 cm leakage has a minuscule height.

274

Appendix F

More Experiments on ESD Coupling to Boxes

Figure F.5

Figure F.6:

The thickness of the leakage is furthermore reduced by using a thinner, one-layer plastic tape (50 μm). The loop voltage gets down to 50 mV. This can be attributed to the reduction in height of the leaky seam, and to the beginning of a waveguide through-loss, thanks to the depht of the cover-to-box edge overlap.

Figure F.6

Purpose of the Validation Tests

275

Figure F.7:

The plain cover has been replaced by a plate with a 100 mm × 2 mm slot. When discharging near the center of the slot, the loop voltage reads 1 V, giving by comparison with Fig. F.4 a new shielding effectiveness: SE = 20 log(1.8V/1V) ≈ 5dB Notice that, although the height of the slot is very small, its lenght impose a significant leakage for the higher portion of the spectrum (see calculation example, Appendix E).

Figure F.7

Figure F.8:

A new cover is installed, with just a small hole in the center, obtured by a screw, washer and nut. The screw is protruding about 10 mm inside and the screw head and fillets were intentionally painted to interrupt the peripheral contact with the cover. When discharging on the screw head, the result is impressive, with the loop reading 4V peak. Strictly speaking, when compared with the 1.8V reading of Ref. Test. F.4, this look like a negative shielding attenuation, i.e., a gain! However, we must remember that test F.4 consisted in a discharge on the edge of a limited size cubicle, without a complete illumination of the target inside.

276

Appendix F

More Experiments on ESD Coupling to Boxes

Figure F.8

Here, in contrast, discharge occurs at center, on a perpendicular stub plunging inside, equivalent to a short monopole. This monopole is base-driven by the ESD in a peculiar manner: The thin insulated gap created by the layer of paint on the screw fillets is broken by the gun tip voltage. The small arc was clearly seen and heard, and this secondary low voltage arc has probably a faster rise time than the calibrated 1 ns of the gun (see Chapter 4, Honda Ref. 7 and Section 4.1.3.2). As a result, more energy of the discharge is shifted toward a higher frequency end of the pulse spectrum. The oscillating signal delivered by the loop inside would correspond to ≈ 5 GHz, i.e., the resonant frequency for a λ/4 dipole with 1.5 cm length. In any event, the bottom line of this specific test is that a single screw protruding inside with no or poor electrical contact can totally ruin (SE = 0 dB) the effectiveness of a decently shielded, 50-dB metallic housing. Figure F.9:

For the next series of tests done with an indirect discharge on a VCP (Fig. F.9), the 4.2-cm Moebius loop was replaced by a 2.2-cm model, with a flat response up to 2.5 GHz, hence less prone to resonance in the ESD upper frequency domain. The most relevant tests were made without the box, the loop being directly exposed to the VCP field, as would be the case with a plastic box EUT.

Purpose of the Validation Tests

277

Figure F.9

Figure F.10:

The VCP is directly grounded to the ref. plane by a 0.30-m cable. It was expected that the main current pulse would return to the source by this conductor, then by the gun grounding strap. Effectively, the main pulse in the ground path (current probe, Chan. 1) remains at ≈ 10A, without the narrow precursor spike. The H-field probe (Chan. 2) delivers a 1-V peak, narrow bipolar puse corresponding to the early discharge spike. The lower amplitude (≈ 0.5 V), longer pulse that follows correspond to the slower (12 ns) risetime of the main discharge, hence producing less voltage output.

Figure F.10

278

Appendix F

More Experiments on ESD Coupling to Boxes

Figure F.11:

The VCP is now grounded through 25k , hence virtually isolated like in the IEC set-up. Surprisingly, although the main discharge current sinking from the VCP to ground, then returning to the gun should be significantly reduced by the 25 k (to be compared with the 330 of gun output resistance), there is only a small decrease: 9 A instead of 10 A. This can be explained by the fact that the VCP is now raising abruptly to the gun tip voltage; the capacitive coupling from this “hot” plate to the shielded room wall is estimated at 20 pF. For a 1-ns voltage step, a 20 pF capacitive impedance is practically a short, compared to the 330 of gun resistance, and this capacitive current is adding to the smaller VCP return current. The loop read-out shows the same, short bipolar pulse as Figure F.10, with slightly more amplitude (1.3 V). The longer pulse of Figure F.10 is significantly reduced (0.2V), corresponding to a lesser H-field, as expeced (see discussion Section 4.4.3).

Figure F.11

Appendix

G

Examples of Simple SPICE Modeling of ESD Coupling Effects The disposal of a simple, easy-to-use simulation software that can process quickly time-domain as well as frequency-domain analysis on a personal computer, has been a blessing for the EMC engineers. SPICE can be used to perform EMC analysis for applications well beyond its initial purpose of integrated circuit simulation. To name a few, SPICE lends itself perfectly to: • • • • •

Crosstalk prediction Common-to-differential mode conversion with balanced or unbalanced cable link Ground loop coupling or field-to-cable coupling with shielded cables, through their Zt CM and DM filtering of switch mode power supplies Shielding effectiveness of a metal box with apertures

Of course, ESD is no exception, and we present here a few simple applications of ESD coupling prediction using SPICE.

G.1. SIMULATED ESD GENERATOR Figure G.1 shows the generation of the handheld metal contact ESD waveform by a circuit re-creating the ESD gun. Several equivalent circuits have been devised for modeling the IEC waveform. Although they generally merge the two subcircuits—main body discharge A and hand/metal contact discharge B —in Electrostatic Discharge, Third Edition, by Michel Mardiguian Copyright © 2009 the Institute of Electrical and Electronics Engineers, Inc.

279

280

v 30.0

Appendix G

Examples of Simple SPICE Modeling of ESD Coupling Effects v(10) v(10) + v(14)

v(14)

150 pF 1.5μ

25.0

A+B

6 pF 100 nH

A

270 Ω

⊥Ω

160 Ω B

20.0

8 kV

B 15.0 10.0 A 5.0 0.0 −5.0 0.0

5.0

10.0

15.0

20.0

25.0 30.0 Time ns

35.0

40.0

45.0

50.0

Figure G.1 ESD generator current for 8-kV discharge, as seen in a 1- load.

parallel, as they do when discharging on a calibration target, we have chosen to keep them distinct. This allows evaluating separately the currents and waveforms corresponding to A and B since their respective currents do not always follow the same paths when discharging on a real EUT. The summation curve A + B corresponds to what is seen on a 1- calibration target. Components have been adjusted to provide an ≈ 0.7-ns rise time for the initial spike, the worst-case (fastest) tolerance of the IEC template. This may result in a 1.4 times aggravating factor compared to simple approximation based on 1 ns. The caption circuit will be designated in the forthcoming coupling analysis as an “ESD generator” module.

G.2. DIRECT ESD ON ACCESSIBLE CONNECTOR PIN This simulation covers the direct application of an 8-kV ESD to a touchable connector pin, unprotected. The victim’s resistance is taken as 300 , plus a small length of wiring or PCB trace. Figure G.2 shows a 2.6-kV/110-ns received pulse, seen at the 300- input, which can be damaging, given that the associated 8-A current is substantially higher than with a 2-kV HBM test (approximately 1.3 A). In Figure G.3, an EMI “T” filter (2 ferrites plus 100-pF capacitor) circuit has been added in front of the victim circuit. The time scale has been stretched

G.2. Direct ESD on Accessible Connector Pin kV 2.6

v (22)

281

v (16)

2.4 2.2 2.0 1.8 1.6 1.4 1.2 0.1 0.8 0.6 0.4 0.2 0.0 0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Time μs

Figure G.2 Effect of a 8-kV direct contact ESD on a connector pin, terminated on a 300- load.

kV 4.5

v (22) victim’s voltage

v (16) connector pin voltage

4.0 3.5 3.0 2.5 2.0 1.5

V16

1.0 0.5

V22

0.0 −0.5 −1.0 0.0

10.0

20.0

30.0

40.0 Time ns

50.0

60.0

70.0

Figure G.3 Same ESD injection as Figure G.2, but with a T filter.

to show the actual pin voltage (V16 ) versus victim’s voltage (V22 ). The filter has eliminated the narrow initial pulse, but the 2.6-kV, destructive pulse is unchanged because the filter has an ≈ 15-MHz cut-off frequency, leaving the bulk of the long pulse unaffected. Figure G.4 has the same configuration as Figure G.3, but a 7-V clamping diode, with a low Ron added in front of the filter. The victim’s voltage in now

282

Appendix G

Examples of Simple SPICE Modeling of ESD Coupling Effects

V 24.0

v(22)

v(16)

22.0 20.0

Pin voltage

18.0 16.0 14.0 12.0 10.0 Victim’s input 8.0 6.0 4.0 2.0 0.0 0.0

0.1

0.2

0.3 Time μs

0.4

0.5

Figure G.4 Same as Figure G.3, but with a 7-V, bidirectional clamping diode added.

clamped at 8 V, except for the first 10 ns, where it reaches 14 V. The IC is safe, yet, an error is likely to occur if not corrected by software or firmware.

G.3. MAGNETIC FIELD, INDUCTION COUPLING INTO A PCB LOOP Here, we estimate the effect of a D-ESD at approximately 12 cm from a 5-cm ×2-cm PCB loop, terminated into 300 . Figure G.5 shows the resulting pulse in front of an unprotected 300- input. The 40-V/1-ns pulse is not damaging but could cause a logic error. Notice the 8-V inverted pulse caused by the falling front of the initial ESD spike, followed by a longer 1.5-V pulse due to the main body discharge current. In Figure G.6, the same circuit is now protected by a T filter. The voltage drops down to 8 V (a 5 times reduction), with a ringing due to the self-resonance of the filter L,C elements. The first four periods of the oscillatory pulse are enough to cause logic errors. Figure G.7 is the same configuration as (b), with a 5-V clamping diode added before the filter. Once clamped, the residual voltage is further attenuated by the filter, which appears less efficient than in (b) because of the clipping of the diode.

G.3. Magnetic Field, Induction Coupling into a PCB Loop

283

v (22)

v 40.0 35.0 IESD

50nH

30.0

300.Ω

30Ω

25.0 20.0 15.0 10.0 5.0 0.0 –5.0 –10.0 0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0 8.0

9.0

10.0

11.0

Time (ns)

Figure G.5 Induced ESD effects by H field into a 10-cm2 PCB loop at 12 cm from the discharge current path.

v 9.0

v(22)

8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 –1.0 –2.0 –3.0 –4.0 0.0

10.0

20.0

30.0

40.0

Time (ns)

50.0

60.0

70.0

Figure G.6 Same as Figure G.5, with a T filter.

284

Appendix G

Examples of Simple SPICE Modeling of ESD Coupling Effects

v 2.5

v(22)

2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

Time (ns)

Figure G.7 Same as Figure G.6, plus a 5-V, bidirectional clamping diode.

Nevertheless, the first two periods could still cause an error, unless inhibited by software or firmware. To conclude, in Figures G.5–G.7, we see that even though a zener plus a third-order filter reduces substantially the induced effect (here 40 V/2.4 V = 17 times), this is not enough to guarantee an error-free state. Assuming that no more filtering can be added because of the necessary signal bandwidth, the PCB loop must be reduced by 4 times or some shielding must be provided.

G.4. INDIRECT ESD (VERTICAL COUPLING PLATE) EFFECTS ON A PCB TRACE We now investigate the effects of an 8-kV indirect ESD applied on a vertical coupling plate (VCP). The victim is a 15-cm-wide, 20-cm-high unshielded PCB located at 10 cm from the discharge, with an estimated 5 pF of total VCP-to-PCB coupling capacitance. The VCP is isolated from the ground reference (floor, metal desktop, etc.) by a 470-k resistor, for replicating an ESD test setup, the only VCP-to-ground leakage path being a 10-pF stray capacitance. Figure G.8 shows the VCP and PCB (0 V ground plane) at the early instants of the discharge, with the PCB grounded to the reference plane (floor, or equipment base plate). We see that the VCP rises quickly (8 ns) to the gun tip voltage.

G.4. Indirect ESD (Vertical Coupling Plate) Effects on a PCB Trace kV 9.0

v(30) PCB to gnd voltage

285

v(15) VCP voltage

8.0 7.0

VCP

6.0 5.0 4.0 3.0 2.0

PCB

1.0 0.0 −1.0 −2.0 0.0

5.0

10.0

15.0 20.0 Time (ns)

25.0

30.0

35.0

Figure G.8 8-kV indirect ESD, showing the VCP voltage (V15 ) and grounded PCB voltage (V30 ).

The PCB, although grounded, jumps to more than 1 kV for a few nanoseconds because of the capacitive current running through the grounding wire impedance. This capacitive current is seen in Figure G.9, which gives the voltage in a 1- current mirror inserted in the PCB grounding conductor. One must realize that some of this current is directly flowing in sensitive zones of the PCB, and will be merciless for any small flaw in the signal reference plane. In Figure G.10, the same PCB is now floating, with a total 30-pF PCB-to-ground capacitance. The floating PCB tends to follow the VCP voltage, reaching 4 kV in the first nanoseconds, then slowly falls off, thanks to a finite insulation resistance. In spite of this presumably floating PCB, the ground current closing by the PCB is still significant (Fig. G.11), since the 30-pF stray capacitance is virtually a short for a 1-ns front. Next, as a follow-up of the former analysis, we look at the effects of this capacitive coupling on the PCB; more precisely, the effect of the current drained from the VCP, for various PCB trace layouts. It would be a gross estimate to assume that the whole current seen in Figures G.9 and G.11 is crossing a given zone on the PCB, therefore: 1. The 5 pF (VCP-to-PCB) should be seen as a total capacitance, which we can split into any arbitrary number of small capacitors in parallel, each

286

Appendix G

Examples of Simple SPICE Modeling of ESD Coupling Effects

V

v(31)

30.0

25.0

20.0

15.0

10.0

5.0

0.0

−5.0 0.0

5.0

10.0

15.0 Time (ns)

20.0

25.0

30.0

Figure G.9 ESD current returning by the PCB-to-ground path, seen by a 1- shunt. kV

v(15)

v(30)

9.0 8.0 7.0 6.0

VCP

5.0 4.0 3.0 PCB

2.0 1.0 0.0 −1.0 −2.0 −3.0 0.0

5.0

10.0

15.0 Time (ns)

20.0

25.0

30.0

Figure G.10 Same as Figure G.8, but with the PCB floating.

G.4. Indirect ESD (Vertical Coupling Plate) Effects on a PCB Trace V 25.0

287

v(32)

20.0

15.0

10.0

5.0

0.0

−5.0

−10.0 0.0

5.0

10.0 15.0 Time ns

20.0

25.0

Figure G.11 ESD current returning via the floating PCB (30 pF).

one draining a certain share of the bulk current into the facing section of the PCB floor plan. 2. Assuming that the PCB is mounted upright in a nonmetallic housing (remember that we are in an Indirect(I)ESD scenario), the PCB-to-ground stray capacitance itself can be modeled by breaking it into a number of small capacitors in parallel. 3. The VCP-to-PCB capacitance has been assumed to be of the same order as the VCP-to-ground capacitance, such as a significant share of the capacitive current is captured by the PCB. This leads naturally to worst-case results. The PCB is assumed to be a multilayer board, or at least a single-layer, double-sided board with one face almost entirely filled-in with copper. The copper foil on the 0-V side is a quasi-perfect plane, except for one zone with a 2.5-cm slot, perpendicular to the general direction of current. Two victim circuits are exposed to this ESD threat, with their trace running in the vertical direction:

288

Appendix G

Examples of Simple SPICE Modeling of ESD Coupling Effects

Circuit A is a 15-cm trace, not crossing over the ground plane slot. Circuit B is a 15-cm trace, crossing over the ground plane slot. Both circuits are terminated in a 300- load impedance, with a 30- source impedance. The various elements are modeled as follows: •

•

PCB ground plane impedance, given that it is not an infinite plane: • Copper foil resistance: 1 m/sq • Copper foil partial self-inductance: 0.05 nH/cm • 2.5 cm slot inductance: 2.75 nH Signal traces impedance: • dc resistance: 30 m/cm • self-inductance: 5 nH/cm • trace capacitance: 1 pF/cm

This configuration is shown in Figure G.12. In a first scenario, the discharge occurs with the VCP facing the 0-V ground plane (solder side) of the PCB. The results are shown in the following series of plots. Figure G.13: The VCP is looking at the PCB ground plane. Voltage on the 300- end of trace A (not crossing over the slot) is a train of decaying narrow

VCP

B

PC ESD Gener.

Trace A Trace B

Slot

PCB Grounded 470 k

Figure G.12 I-ESD coupling geometry for PCB example. The VCP is shown facing the PCB ground plane.

G.4. Indirect ESD (Vertical Coupling Plate) Effects on a PCB Trace

289

v(50) – v(41)

V 1.4 1.2 1.0 0.8

Vtrace, w/o filter

0.6 0.4 0.2 0.0 −0.2 −0.4 −0.6 −0.8 −1.0 −1.2 0.0

2.0

4.0

6.0

8.0

10.0

12.0

14.0

Time ns

Figure G.13 I- ESD coupling with the VCP facing the PCB ground plane (solder side). Voltage seen on a 15-cm trace not crossing over the slot without filtering, then with 50-pF filter added (dotted line).

pulses (< 1 ns), starting from 1.4 V. A simple 50-pF filtering across the 300- load (dotted line) reduces it to less than 0.3 V. Figure G.14 is the same configuration, but the trace is crossing over the slot. The voltage at the 300- end has increased 10 times, due to the longitudinal ground noise caused by the slot inductance. The first 15 periods of the decaying oscillation are prone to create logic errors, which are neither clamped or filtered. With a simple 50-pF filter added (dotted line), the noise is reduced to a short (< 1 ns) 1-V pulse, which can probably be ignored by any logic with > 3-ns rise time, the rest dropping below 0.7 V. In a second scenario, the discharge occurs with the VCP facing the component and traces side of the PCB. The traces are directly capturing the capacitive coupling from the VCP, without the masking effect of the ground plane. The result is shown in Figure G.15, for the trace crossing over the slot. The induced voltage (300 V) is catastrophic, with such an amplitude that no filter can reasonably bring it down to a no-error level (this would require about 54-dB attenuation). The results are about the same for a trace not crossing over the slot since we are now facing a problem of direct capacitive injection into a nonmasked trace.

290

Appendix G

Examples of Simple SPICE Modeling of ESD Coupling Effects

V 12.0

v(50) – v(30)

10.0 8.0 6.0

Trace B, no filter Trace B, with filter

4.0 2.0 0.0 −2.0 −4.0 −6.0 −8.0 −10.0 0.0

5.0

10.0

15.0 20.0 Time ns

25.0

30.0

Figure G.14 ESD coupling with the VCP facing the PCB ground plane (solder side). Voltage seen on a 15-cm trace crossing over the slot without filtering, then with 50-pF filter added (dotted line).

Even if we factor in some internal clamping of the device at 30–60 V, several protections must be added such as: Guard ring or wide ground traces surrounding the sensitive trace to deviate the E-field lines, reducing the capacitive injection to the trace itself. Transient suppressors to clamp the voltage around 5 V, complemented by a three-stage filter. A more efficient solution (more expensive too) would be to use a multilayer board with unetched copper planes on both external layers, or to metallize the inner face of the equipment plastic housing to create a Faraday shield, which would capture most of the capacitive current, at whatever side the VCP is looking.

G.5. Few Remarks on Simplifying Assumptions Used in These SPICE Simulations V 300.0

291

v(50) – v(30)

250.0

200.0

150.0

100.0

50.0

0.0 −50.0 −100.0 0.0

5.0

10.0

15.0 20.0 Time ns

25.0

30.0

Figure G.15 I- ESD coupling with the VCP facing the PCB traces (component side). Voltage seen on a 15-cm trace crossing over the slot without filtering.

G.5. FEW REMARKS ON SIMPLIFYING ASSUMPTIONS USED IN THESE SPICE SIMULATIONS G.5.1. Filters For discrete filters, we have taken into account the inevitable parasitic elements, assuming the devices are good quality, surface-mount types. For capacitors, an ESR+ESL equivalent to 0.1 has been added. Miniature ferrites were simulated by a parallel combination of L (30–300 nH), R (300–600 ), and Cp (1–2 pF), depending on the exact characteristics of the filter.

G.5.2. Lumped vs. Distributed Parameters Given the nanosecond rise times, when conductor lengths exceed ≈ 15 cm, lumped-element approximations are replaced by distributed (or transmission line) configurations.

292

Appendix G

Examples of Simple SPICE Modeling of ESD Coupling Effects

G.6. FEW GENERAL CONCLUSIONS FROM SPICE MODELING WITH 8-KV ESD •

•

•

Direct discharge on connector pins, with an IEC-type generator is an extremely severe test; immunity requires robust protection to achieve no damage. A no-error response is almost impossible, except for dc or low-speed (< 1 MHz) interfaces. Magnetic coupling from direct contact discharge on chassis is not destructive but difficult to competely filter if signal bandwidth> few megahertz. Loop size reduction, shielding or software traps may be required. I-ESD on coupling plate is a serious threat when the discharge plate is looking toward the trace and component side of ordinary PCBs. Even with presumably floating PCBs, several amperes can flow through the signal reference.

Appendix

H

Time-to-Frequency Conversion for a Single Transient An isolated pulse (voltage, current, E or H field, etc.) that has no repetition period can be translated into the frequency domain as a broadband spectrum where individual harmonics do not exist since the Fourier series is being replaced by the Fourier integral (Fig. H.1). Given that the area of the time-domain waveform could be sized in volts × second or amperes × second, it translates into the frequency domain as a spectral density, which is expressed in V/Hz or A/Hz, and submultiples as μV/MHz or μA/MHz.

Electrostatic Discharge, Third Edition, by Michel Mardiguian Copyright © 2009 the Institute of Electrical and Electronics Engineers, Inc.

293

294

Appendix H

Time-to-Frequency Conversion for a Single Transient

Time Domain Damped oscillatory (arc discharge and filter switching transient)

Overdamped unidirectional (arc discharge

Frequency Domain

Spectrum Equations 1 8T1 An = 126 + 20 log10 AT1 Fn < 0.5 F1 <

F1

A1

F n = F1 =

A2 AN T1 TD

40 dB/dec. Frequency (Fn)

20 dB/dec.

A

and relay switching transient)

T1

0.37A

TE

AN

F1

F2

40 dB/dec.

TO

Frequency (Fn)

1

4T1 2∗ An = 126 + 20 log10 AT1 −10 log10 [4d (1 - d) 1 F n > 2 F1 > 2T1 A An = 96 + 20 log10 −40 log10 Fn T1 1 Fn < F 1 < pTE An = 120 + 20 log10 ATE 1 Fn > F 1 > pTE An = 110 + 20 log10 A–20 log10 Fn 1 Fn > F 2 > pT1 An = 100 + 20 log10 A −40 log10 Fn T1

A = volts or amperes (peak)

F = frequency in MHz

L = inductance in mH

T = Time in ms

R = resistance in Ω

C = capacitance in mF

AN = dB mV/MHz or dB mA/MHz *Damping Ratio (d) = nA1 − nA2– = 2p

R 2

C/L

1 Note: TE = time for A to drop to a value of e A = 1.45 T50%

Figure H.1 Time to frequency conversion of single transients.

Index

A

C

Absorption loss, 171–185 Airbags, ESD sensitivity, 106 Aluminum, 44, 60, 68, 115, 139, 171, 178, 182, 187, 233, 259 American National Standards Institute (ANSI), 85 Analog devices, 74–75 Antistatic control techniques, 14, 19, 40, 44, 81–86, 88 floor, 226, 227 spray, 226 Aperture leakage, 225 Arc, 2, 13, 20, 50, 55, 160, 185, 188, 190, 204, 217, 276 discharge, 84, 92–96, 163, 204, 224, 255 inductance, 34 Arrays, planar capacitors, 160 Atoms, 1–2 Attenuation filter, see Filtering. Attenuation shield, see Shielding. Automobile ESD environment, 7 ESD testing, 81, 85, 105–107, 120, 129 Avalanche, 164, 243, 256

Cables configuration for testing, 120, 121, 130, 139 external contribution of, 191 penetration, 122, 201–204, 219–221 Calibration, ESD generator, 100, 101 Capacitance, 5, 24–28, 52, 54, 55, 60, 75, 78, 84–86, 152, 235, 242 parasitic, 78, 160, 268, 285 Capacitance, to infinity, 5 Capacitor, see Filters. Carpets, 4, 5, 6, 8, 14, 16, 18, 19, 22, 125, 128, 226, 227, 228 Carriers, ESD, 11, 161, 162, 224 Case studies, 231–239 Charged device model (CDM), 40 Chips, 6, 39–42, 45, 50, 85, 114, 145, 149, 150–153, 155, 161, 221, 240–250, 253, 267 Common mode (CM) capacitors, 209 ferrites, 168, 214 impedance, 225 rejection, 146 voltage, 77, 196 CMOS (complementary metal-oxide semiconductor), 44, 45, 46, 49, 150, 157, 267 Conductive coating, 160, 173, 184–185, 187, 190, 219, 233–236 paint, 13, 69, 123, 173, 175, 184, 185, 220, 234, 235 tape, 180, 184, 187, 220, 232, 236

B Body, see Human body. Bonding, 142, 156, 161, 167, 179–180, 182, 183, 185, 187, 196, 197, 199, 200, 202 Breakdown, 48, 152, 256, 257

Electrostatic Discharge, Third Edition, by Michel Mardiguian Copyright © 2009 the Institute of Electrical and Electronics Engineers, Inc.

295

296

Index

Connectors, 123, 159–160, 202, 203, 217–218, 280–282 filtered, 204, 213, 215 Copper, metallization, on IC, 44 shielding applications, 179, 180, 182, 184, 185, 187, 232 shielding properties, 171, 173–175 Coupling, 54–70, 116, 118–119, 158–159, 260–268, 282–291 Crowbar, 224 Current probe, 16, 19, 20, 53, 83, 143, 145, 146, 198, 238, 270, 271, 277

rate, 129–137 ESD (electrostatic discharge), furniture, 11, 14, 15, 18–23, 24, 28–30, 31, 35, 36, 40, 41, 53, 55, 63, 70, 72, 78–79, 83, 85, 89, 91, 92, 97, 98, 99, 109–112, 114, 118, 128, 129, 173, 184, 226, 227 human, 5, 9, 11, 12, 15–18, 20, 23–28, 30, 31, 32–35, 36, 37, 40, 44–45, 47, 49, 55, 64, 71, 72, 78–79, 81–83, 90, 92, 95, 99, 109–112, 122, 127–129, 134, 153, 173, 198, 225 object, 18–23, 78–79

D

F

Damage, ESD, 41, 45–48, 150, 165, 217, 240, 252–254 Dashboard, indirect ESD, 59, 237 Data, terminal, 53, 233–235 Decoupling, 153, 154 Diagnostics, 89–146 Diode, protection, 151, 152, 156, 216, 242, 246 Direct contact, see Discharge. Discharge, air, 55, 84, 97–98, 100, 128, 217, 255 direct contact, 6, 39–41, 51, 55, 84, 92–96 124, 174,185, 224, 258, 270, 280–282 hand-metal, 26, 31, 36, 51, 74, 96, 97, 103–105 109, 133, 249, 250, 261, 279 indirect, 53 network, 81, 90, 95, 97, 98, 101, 103 precursor, see Precursor DOD Std. 1686, 50, 81, 86, 87

Factory, ESD protection at, 43 Failure, ESD-related latent, 39, 49, 80, 244, 258; see also Walking wounded. phenomenon, 6, 14 15, 39, 40, 44, 45, 47, 244, 245, 247, 249 statistics, 48, 49 testing, 80, 82, 83, 87, 106, 112, 122, 124–126, 130, 133, 136, 138, 141, 150, 225 Faraday shield, see Shield. Fatigue, 244, 258–259 Ferrites, 168–169, 199, 206–208 Field effect transistor (FET), 45 Field, electric (E), 58, 59, 60–64, 103, 119, 143, 158–159, 170, 172, 270 magnetic (H), 55–58, 59, 60–64, 109, 119, 143, 145, 158–159, 170, 172, 260, 261, 263, 270, 272 near, 172 Filters, 200, 204, 205, 206–212, 291 Finger-stocks, 180, 181 Floor, 6–8, 14, 19, 22, 42 84, 115–117, 125, 127–128, 134, 220, 225, 226–227, 272, 284, 287 Forced crash, 140–143 Fourier, 26, 260–261, 293 Frequency domain analysis, 75–78, 260–268, 279 Furniture, ESD, induced effects, 72, 78, 173, 184, 226, 227

E Electromigration, 259 Electrons, 1–4, 256 Electrostatic, charging, 1, 2, 4, 5, 9–13, 71, 162 voltages, 5, 6, 8, 14–18, 29, 36, 60 EED (electroexplosive devices), 82, 105, 236–237 Embedded, protections, 151–152, 222, 240–250 Errors, 70–78, 125–137, 221–222

Index phenomenon, 11 statistics, 14, 18–23 testing, 97, 98, 109–112, 118 waveform, 28–30, 31, 35–36

G Gap, air, 33, 40, 79, 92–93, 94, 96, 103, 112, 190, 192, 217, 255, 256 Gaskets, 166, 167, 170, 178, 182, 185, 190, 273 Ground, guard/ ring, 152, 159, 161, 207, 224, 247, 290 plane and traces (PCB), 158, 159, 161, 205, 218, 219, 224 reference plane (GRP), 114–115, 119 strap, 40, 42, 60–61, 97–99, 111, 114, 115, 118, 120, 121, 139, 167, 179, 180, 195, 199, 201, 220, 231–232, 235, 249, 277 Grounding, 2, 40, 51, 52, 160, 162, 163, 188, 217, 226, 232 system safety, 51, 225, 235 Grounding buttons, 181–182

H Hand/metal discharge, 18, 26, 31, 36, 51, 74, 75, 96, 97, 103, 104, 105, 109, 133, 249, 250, 261, 279 HCMOS (high-speed CMOS), 47, 70, 76, 77, 245 Human body capacitance, 5, 24–27 model (HBM), 40, 44, 83 resistance, 24–27 Human ESD damage to components, 40, 41, 44–48 induced effects, 52–56, 58–60, 64, 70, 71, 72, 74, 78, 79, 173, 198 phenomenon, 5, 9, 11, 12 statistics, 15–18 testing, 81–83, 90, 92, 95, 99, 109–112, 128, 134 waveform, 24, 27, 30–34, 36 Humidity, relative, 6–9 High voltage (HV) relays, 84, 91, 95–96, 101, 102, 108–109, 111, 113, 114, 257

297

I IEC (International Electrotechnical Commission), 84–85, 87, 95–105, 112 Immunity, 84–86, 148–228, 241–250 Impedance, 40, 69–70 barrier, 172, 174 circuit, 72–73 common impedance coupling, 70 personnel and furniture, 27, 30 transfer, see Cable shield. wave, 61, 63, 64, 67, 171, 172, 173 Induced, noise, see Noise. voltage, see Voltage. Inductance, see Self-inductance. Installation, ESD control, 226 Integrated circuit (IC), 40, 42, 150–153, 161 Integrated transistor, see Transistor Ions, 2, 256 Ionization, 31, 34, 55, 93, 107, 255, 256

J Joule effect, 44, 241

K Keyboard, 121, 153, 154, 162–169, 221, 222, 232, 233, 258. See also Membrane switches. Key, hand-held, 50, 74, 77, 134

L Latch-up, 44, 150, 247–248 Leakage, 58, 67, 169, 176, 177, 178, 182, 188, 190, 225, 267, 268, 274, 275 Lock, antistatic, 188, 189 Logic, 60, 70–73, 76, 77, 131, 132, 136, 157, 161, 198, 267, 282, 289 transistor-transistor (TTL), 44, 47, 70 Low voltage differential system (LVDS), 211, 241

M Machine model (MM), 42, 49, 83, 114, 150, 242, 247, 250 Membrane switches, 143, 162–165, 214–217

298

Index

Metallic cabinet, 58, 67–69, 139 Metallization, 44–46, 67, 69, 160, 167, 169–190, 197, 219, 233–234, 243, 247, 290 Microcircuits, standards and specifications (for ESD), 82–83 MIL-Handbook, 50, 86, 87, 240, 263 MIL-Std., 50, 81–83, 86, 87, 112, 215, 252 Modules, 6, 31, 40- 42, 47, 50, 59, 70–71, 73, 77, 81, 106, 107, 112, 149, 151, 216–27, 237, 240, 258, 280 MOS (metal-oxide-semiconductor), 44–47, 49, 70, 71, 73, 76, 150–152, 157, 211, 243, 244, 247–249, 267

vertical coupling (VCP), 60, 116–119, 122–13, 158, 270, 271, 277–278, 284–291 Polarity, 4, 45, 71–73, 92, 99, 113, 124, 141 Precursor, 31, 34, 36–37, 57, 74, 78, 92, 97, 104, 268, 271, 277 Printed circuit board (PCB), 6, 42, 50–51, 58–60, 64–68, 76–78, 103, 138, 145, 196, 209, 225, 268, 282–284 ground plane, see Ground. hardening, protection, 157–161, 166, 167, 188, 190, 204–206, 214, 217–221, 224 Probability, 14–18, 22, 109, 110, 122, 127, 129, 132–133, 162

N NFPA (National Fire Protection Association), 226 Network, see Discharge network. Nickel, 69, 170, 171, 175, 176, 180, 184, 185, 203 NMOS, 47 Noise, 74, 76, 160, 192, 194, 195, 196–198, 238, 241 factor, 44 immunity/margin, 70, 148, 221–223, 237, 242 induced, 71, 72, 75, 159, 193, 221, 260–268, 289 inhibition, 221–223

O Optical, fiber, 121, 142, 219 isolators (OI), 218–219

P Packaging, 40, 49, 58, 86, 148, 161–169, 188, 190, 232 Personnel ESD, see Human body. Planar capacitor arrays, 160, 204, 206 Plane back-, 76 horizontal coupling (HCP), 60, 116–119, 120, 123, 154, 158 PCB ground, see Printed circuit board. test reference, see Ground reference plane (GRP).

R Radiation, 28, 56, 62, 66, 78, 104, 140, 163, 167, 173, 174, 176, 177, 178, 186, 190, 201, 236, 260, 268 Recombination, 1, 2, 5, 13, 53 Recovery, 136, 143, 221–223 Reflection, 170–177, 184, 185 Relays, 84, 91, 94–96, 98, 101, 102, 104, 107, 108–109, 111, 113, 114, 220, 257, 294 Resistance, 2, 4, 6, 9, 43, 63, 64, 117, 152, 154, 155, 167, 182, 190, 205, 242, 250, 252, 254 discharge, 20, 40, 55, 81–83, 90, 95, 97–99, 101, 103, 109, 173, 249, 278 floor, 226, 227 furniture, 28 human body, 24,–27, 64 Resistors, integrated on chips, 44, 150, 242, 244, 246, 250 Risetime, ESD pulse, 16, 20, 24–26, 31, 34, 37, 51, 52, 56, 74, 82, 85, 90–92, 96–97, 99–101, 104, 115, 198, 218, 225, 261, 263, 280 logic circuit, 70, 76–78, 131, 161, 210, 211, 267, 289

S SAE, 13, 81, 85–86, 106, 153 Safety wire, 51, 115, 233, 235–236 Schottky, 47, 152

Index Self-inductance, 24, 27, 28, 99, 211, 249, 288 Self-recombination, 13 Severity level, 84, 106, 108, 190, 226, 250 Shield, cable, 191, 192–195, 226 termination, 194, 195, 196, 199, 201 transfer impedance, 197, 198 Shielding, 43, 58, 60, 67–68, 75, 89, 101, 104, 119, 122, 142, 143, 145, 157–159, 165, 178–183, 187, 224, 267–268, 269–273, 275–278 basic theory, 168–178 conductive coating/paint, 183–185, 233, 235 Silicon-controlled rectifier (SCR), 44, 73, 247–248 Silver, 156, 171, 173, 184 Simulators, ESD, 81, 83, 89, 90–146, 193, 230, 249, 269–271 Skin effect, 58, 69 Slot, leakage, see Leakage Software, 26, 121–122, 124, 136, 140, 142, 148, 149, 221–223, 279, 282, 284, 292 Sparkover voltages, 255–257 Specifications, 14, 25, 47–48, 75, 80–88, 96, 100, 101, 112, 114, 116, 119, 122, 124, 125, 164, 169, 213, 217, 219, 258 Spectrum, frequency, 26–29, 58, 60, 61, 64, 66, 67, 70, 74, 75, 109, 110, 140, 153, 161, 169, 173, 178, 197, 204, 208, 219, 225, 260, 261, 263–268, 272, 275, 276, 293–294 Spring tinsel, see Tinsel devices. Static electricity, ix–x, 1 Static eliminator bar, 164 Statistics, ESD, 13–22, 129, 133 Steel, 58, 69, 97, 144, 165, 171 175, 176, 231, 237, 269, 270 Strain relief, 202, 203, 222 Surface mount technology (SMT), 157, 205

299

T Testing, 40, 44, 82, 89–146, 226, 258–259 criteria, 82–86 design and development, 83–84, 89–109, 110, 135–143 device, 82, 83, 84 set-up, 114–121 system, 120–121 Threshold, damage, 44, 45, 47, 124, 125, 131, 244 Time-to-frequency conversion, 293–294 Tinsel grounding devices, 162, 163 Transient protections, 153–154 Transient suppression devices (TVS), 164, 200, 204, 215–217, 224 Transistor, integrated, diffused, 244, 246, 248, 253 Triboelectric, 2, 3–4, 5, 71 Troubleshooting, 119, 237–239 TTL (transistor-transistor logic), 44, 157, 211

U ULSI (ultra large-scale integration), 45

V Vane, simulator, 111–112 Varistors, 151, 152, 156, 216 Victim response, 26–28, 54–78, 70–75 VLSI (very large-scale integration), 45 Voltage, charging, 1–2, 4–6, 9–13, 25–30, 90, 108, 162, 192 induced, 56–57, 64–68, 70–74, 76–77, 101, 105, 109, 159, 178, 191, 192–193, 195, 199, 204, 238, 263–264, 266–268, 289

W Walking wounded, 49, 244, 258 Wave impedance, see Impedance. Waveform, personnel ESD, see Human body. furniture ESD, see Furniture.