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PROCEEDINGS OF THE THIRD INTERNATIONAL SYMPOSIUM ON ULTRA LARGE SCALE INTEGRATION SCIENCE AND TECHNOLOGY
ULSI SCIENCE AND TECHNOLOGY/ 1991 Edited by George K. Celler AT&T Bell Laboratories Murray Hill, New Jersey
John M. Andrews Naval Research Laboratory Washington, D.C.
C
COULD INC. Assistant Editors Wayne Bailey
Paul Nicollian
Sam Broydo
Carl Osburn
Jonathan Chapple-Sokol
Dan Peters
Linda Ephrath
Mark Pinto
Steve Fonash
Gary Ray
Wayne Greene
Arnold Reisman
Bob Kostelak
Dennis Schmidt
Hisham Massoud
Geraldine Schwartz
Ed Middlesworth
Jimmie Wortman
Ken Monnig
I.-W. Wu
Shyam Murarka
ELECTRONICS AND DIELECTRIC SCIENCE AND TECHNOLOGY DIVISIONS Proceedings Volume 91-11 THE ELECTROCHEMICAL SOCIETY, INC., 10 South Main St., Pennington, NJ 08534-2896
Copyright 1991 by The Electrochemical Society, Incorporated
Papers contained herein may not be reprinted and may not be digested by publications other than those of The Electrochemical Society in excess of 1/6 of the material presented.
Library of Congress Catalog Number: 91-75851 Printed in the United States of America
PREFACE This ECS Softbound Symposium Volume contains the papers presented at the Third International Symposium on Ultra Large Scale Integration (ULSI) Science and Technology, held May 5-10, 1991, in Washington, DC. The symposium was cosponsored by the Electronics and the Dielectrics Science and Technology Divisions of the Electrochemical Society, Inc. The total number of papers submitted was much larger than could be accommodated in a five day symposium. The final program consisted of 20 invited reviews and 73 contributed papers. The symposium continues to be international in character, with 27 papers from outside the United States, namely 16 from Japan, 10 from Europe, and one from India. One half of the accepted papers represents work done in industry, with the other half submitted by universities and non-profit research facilities in the US and abroad. The Symposiuim was intended to provide a forum for reviewing the recent important developments in the rapidly changing field of ULSI technology. In the two years since the last ULSI Symposium, the density and complexity of integrated circuits have roughly doubled. Full scale production of 16 Mbit DRAMs is about to begin, and 64 and 256 Mbit memory chips are being designed. Scaling of non-memory circuits is proceeding at a similar pace. Processing structures with deep submicron dimensions is becoming critically important. These issues are reflected in the contents of the present volume. One of the highlights of this year's ULSI Symposium was the award address by Dr. V. J. Kapoor, titled "Review of Thin Oxynitride Dielectrics for Memory Device Technology" Dr. Kapoor received the 1991 Thomas D. Callinan Award, sponsored by the Dielectrics Science and Technology Division. I This proceedings volume is divided into thirteen sections: Device Structure and Technology, Submicron Device and Process Modeling, Submicron Feature Patterning: Lithography, Submicron Feature Patterning: Etching, Shallow Junctions and Ohmic Contacts, Thin Gates, Process-Induced Damage and Contamination, Rapid Thermal Processing, Planarization Techniques, Interconnect and Packaging, Wafer Cleaning and Oxidation, Thin Film Deposition, and Miscellaneous Processing Issues. Each of the first ten sections is introduced by invited reviews. Their authors, who set the tone for the meeting, deserve special thanks. They are: K.-Y. Chiu D. J. Dumin R. C. Frye R. M. Geffken R. W. Hill L. D. Hutcheson D.-L. Kwong M. E. Law T. P. Ma K. Maex M. Miyake S. C. McNevin K. A. Monnig
Hewlett Packard Clemson University AT&T Bell Laboratories IBM IBM Raynet The Univ. of Texas Univ. of Florida Yale Univ. IMEC NTT AT&T Bell Laboratories SEMATECH
iii
M. M. Moslehi 0. Nalamasu M. R. Pinto K. Shimohigashi C. H. Ting J. J. Wortman
Texas Instruments AT&T Bell Laboratories AT&T Bell Laboratories Hitachi Intel North Carolina State Univ.
The symposium would not be possible without the hard work and assistance of many people. We would like to thank Howard Huff, Chairman of the Electronics Division, and Geraldine Schwartz, who chairs the Dielectrics Science and Technology Division, for their support and encouragement. We also greatly appreciate the assistance of the Electrochemical Society Office staff, in particular: V. H. Branneky and Roque J. Calvo, Executive Secretary and Assistant Executive Secretary of the Society, Sarah A. Kilfoyle, Director of Publications, and Brian Rounsavill, Meetings and Programs Manager. Members of the ULSI Subcommittee of the Electronics Division provided extensive assistance in the planning of the symposium. We want to especially acknowledge all of the Session Chairmen and Vice-chairmen, since they did most of the work on paper selection and manuscript reviewing for publication in this volume. They are: Wayne Bailey Sam Broydo Jonathan Chapple-Sokol Linda Ephrath Steve Fonash Wayne Greene Bob Kostelak Hisham Massoud Ed Middlesworth Ken Monnig Shyam Murarka Paul Nicollian Carl Osburn Dan Peters Mark Pinto Gary Ray Arnold Reisman Dennis Schmidt Geraldine Schwartz Jimmie Wortman I.-W. Wu
Texas Instruments OPS, Inc. IBM IBM Pennsylvania State Univ. Hewlett Packard AT&T Bell Laboratories Duke University Hewlett Packard SEMATECH Rensselaer Polytechnic Inst. Texas Instruments MCNC Hewlett Packard AT&T Bell Laboratories Hewlett Packard MCNC consultant IBM North Carolina State Univ. Xerox PARC
We would also like to thank all of the authors for making this symposium possible by sharing their latest results and putting considerable effort into the preparation of the camera-ready manuscripts. John Andrews George Celler May 1991
iv
TABLE OF CONTENTS Preface
iii DEVICE STRUCTURE AND TECHNOLOGY
*Device Design and Process Optimization of Sub-Half Micron CMOS Technology, K.-Y. Chiu, D. Peters, and M. Kakumu
1
*Advanced Deep-Submicron BICMOS Technology, K. Shimohigashi
5
A P+ Poly-Si Gate with Nitrogen-Doped Poly-Si Layer for Deep Submicron PMOSFETS, S. Nakayama
9
Super SILO/RTN: Quasi-Recessed Field Oxide and 80 nm Bird's Beak Using a SILO/RTN Process, P. Molle and S. Deleonibus
17
Advanced Processes to Increase the Effective Storage Area of Stacked DRAM Cells, P. C. Fazan, H. C. Chan, Y. C. Liu, A. Ditali, C. H. Dennison, H. E. Rhodes, V. Mathews, and T. A. Lowrey
26
SUB-MICRON DEVICE AND PROCESS MODELING *Point Defect Based Modeling of Dopant Diffusion in Silicon, M. E. Law
34
*Simulation of ULSI Device Effects, M. R. Pinto
43
Non-Equilibrium Diffusion Process Modeling Based on Three-Dimensional Regulated Point-Defect Injection and in-situ TEM Observation, T. K. Okada, S. Onga, H. Kawaguchi, S. Kambayashi, I. Mizushima, J. Matsunaga, and K. Yamabe
52
*Invited
V
Simulation of Metal "Cone" Formation in a Tri-Layer Liftoff Process, M. D. Kellam, W. B. Rogers, R. W. Sayer, and R. C. Chapman
61
Use of Simulation for Rapid Design Prototyping, G. Chin and M. E. Law
78
SUBMICRON FEATURE PATTERNING: LITHOGRAPHY *X-Ray Lithography at IBM, R. W. Hill and J. R. Maldonado
88
*An Adaptive Neural Network for Computation of ProximityEffect Corrections, R. C. Frye, E. A. Rietman, and K. D. Cummings
101
*The Chemistry and Process Characteristics of Chemically Amplified Positive Resist Materials, 0. Nalamasu and A. E. Novembre
110
A 0.4 pum CMOS Test Circuit Completely Processed with 8-Level X-Ray Lithography, D. Friedrich, W. Windbracke, H. Bernt, G. Zwicker, P. Staudt-Fischbach, H. J. Schliwinski, P. Hemicker, P. Lange, and M. Pelka
120
A 0.5 Micrometer CMOS Process Based on a 248 nm Excimer Laser Stepper, M. D. Kellam, S. Goodwin-Johansson, S. Jones, B. Dudley, and C. Peters
131
Deep UV Lithography of Monolayer Films with Selective Electroless Metallization, J. M. Calvert, M.-S. Chen, C. S. Dulcey, J. H. Georger, M. C. Peckerar, J. M. Schnur, and P. E. Schoen
145
Silylated Acid Hardened Resist Processing for Submicron Deep UV Lithography, E. K. Pavelchek, J. F. Bohland, P. W. Freeman, S. K. Jones, and B. W. Dudley
155
Pitch and Line Width Measurements in Scanning Probe Metrology, J. E. Griffith, M. J. Vasile, G. L. Miller, E. R. Wagner, E. A. Fitzgerald, D. A. Grigg, and P. E. Russell
164
*Invited
vi
Extending a 0.35 NA h-Line Stepper to 0.8 Micrometer (1.6 Micrometer Pitch) CMOS Technology Using Trilayer Templates and Halo LDD Devices, K. W. Markus, S. Goodwin-Johannson, W. B. Rogers, and W. C. Donaldson
174
A Charge-Reducing Process Using a Charge Transfer Complex in Electron Beam Lithography, K. Yano, T. Maruyama, and K. Kobayashi
183
Characterization of a New Submicron I-Line Photoresist, L. N. Nguyen, J. R. Johnson, G. J. Stagaman, and W. Y. Hata
190
A Comprehensive Performance Evaluation of I-Line Resists for Submicron CMOS Technology, G. J. Stagaman, N. S. Thane, J. R. Johnson, L. N. Nguyen, and W. Y. Hata
199
SUBMICRON FEATURE PATTERNING: ETCHING *Time Modulated Plasma Etching, S. C. McNevin
206
Super-ECR Plasma Etching Technology for 64Mbit DRAM, S. Samukawa
216
Highly Controllable SiO2 Etching Technology by Vapor HF/H2 0 System, S. Onishi, K. Matsuda, and K. Sakiyama
226
Anisotropic Etching Process of n+-Polysilicon with Chlorine and Nitrogen Mixed ECR Plasma, T. Matsuura, H. Uetake, T. Ohmi, J. Murota, and S. Ono
236
Low Temperature Etching of Organic Photoresist with an Electron Cyclotron Resonance System, W. Varhue, J. Burroughs, and W. Mylnko
244
SHALLOW JUNCTIONS AND OHMIC CONTACTS *Silicided Shallow Junctions for ULSI, K. Maex, L. P. Hobbs, and W. Eichhammer
254
*Invited
vii
*Formation of Shallow Boron-Doped Layers Using Preamorphization and its Application to MOSFET Fabrication,M. Miyake
266
Ohmic Contact Formation to Shallow Junctions by Selective Titanium Silicide Chemical Vapor Deposition, K. Saito, T. Amazawa, and Y. Arita
276
Defect Annealing in Ultra-Shallow Junctions for Scaled Sub-Micron CMOS Technology, S. Chevacharoenkul, C. M. Osburn, and G. E. McGuire
285
Ultra-Shallow Junction Formation by Diffusion from Polycrystalline SixGel-x Alloys, D. T. Rider, M. C. Oztuirk, and 1. J. Wortman
296
Enhanced Silicide Formation Using Selective Epi Growth on Source/Drain for Deep Submicron CMOS, L. K. Wang, D. Moy, J. A. Ott, and T. S. Kuan
305
Optimization and Characterization of LPCVD TiB2 for ULSI Applications, C. S. Choi, G. A. Ruggles, C. M. Osburn, and G. C. Xing
310
Ideal Metal/Silicon Contact Formation by Clean-Nitrogen-Seal Processing,H. Kuwabara, M. Otsuki, and T. Ohmi
321
Junction Formation for Scaled Sub-Micron CMOS Technology, C. M. Osburn, S. Chevacharoenkul, and G. E. McGuire
330
Stability of TiB2 as a Diffusion Barrier on Silicon, C. S. Choi, C. C. Xing, G. A. Ruggles, C. M. Osburn, A. S. Shah, and J. D. Hunn
343
THIN GATES *Polarity Effects Associated with Wearout and Breakdown in Thin Silicon Oxide Films, D. J. Dumin, J. R. Cooper, K. J. Dickerson, N. B. Heilemann, and P. A. McAllister *Invited
viii
353
*UltrathinMOS
Gate Dielectrics Fabricated by RTP and RTP-CVD, D. L. Kwong, G. Q. Lo, and W. Ting
363
Integrity of Lightly Nitrided Oxide as the Gate Dielectric for 0.5 pm CMOS Devices, D.-G. Lin, J. A. Yasaitis, and C. H. Chiacchia
374
Reliability of Thermally Grown Thin SiO 2 for ULSI Applications, Y. L. Chiou, G. Li, C. H. Sow, J. P. Gambino, and P. J. Tsang
382
Breakdown Characteristics of 0 2 -Diluted and RTO Thin Si0 2 Films, L. Fonseca and F. Campabadal
391
Effects of Si Wafer Surface Micro-Roughness on Electrical Properties of Very Thin Gate Oxide Films, M. Morita, A. Teramoto, K. Makihara, T. Ohmi, Y. Nakazato, A. Uchiyama, and T. Abe
400
Dielectric Breakdown Strength Analysis of SiO 2 Using a Stepped-Field Testing Method, E. A. Sprangle, J. M. Andrews, and M. C. Peckerar
409
Top-Oxidation Effects on the Reliability of Oxide-Nitride-Oxide (ONO) Stacked Film, K. Yoneda, T. Ishida, Y. Todokoro, and M. Inoue
421
Thin Gate Oxide Integrity in Fluorinated MOS Structures, W. M. Greene, T. E. Kopley, and 0. S. Nakagawa
431
Electrical and Structural Properties of Ultrathin Si0 2 Gate Dielectrics Prepared Under Various Conditions, P. Lange, L. Schmidt, M. Pelka, P. Hemicker, H. Bernt, and W. Windbracke
445
Correlation of Metal Impurity Content of ULSI Chemicals and Defect-Related Breakdown of Gate Oxides, M. Meuris, M. Heyns, W. Kuiper, S. Verhaverbeke, and A. Philipossian
454
*Invited
ix
PROCESS-INDUCED DAMAGE AND CONTAMINATION
*Process-Induced Ionizing Radiation Effects in MOS Devices, T. P. Ma
464
Charge Sharing "Antenna" Effects for Gate Oxide Damage During Plasma Processing, S. Fang, A. M. McCarthy, and J. P. McVittie
473
Effects of Process-Induced Damage on 115 A Thin Gate Oxides and Their Removal by Low Temperature Passivation, S. Kar, A. Pandey, A. Raychaudhuri, and S. Ashok
483
Radiation-Induced Neutral Electron Trap Generation in Electrically Biased IGFET Gate Insulators, M. Walters and A. Reisman
493
RAPID THERMAL PROCESSING *Advanced Equipment and Sensor Technologies for Rapid Thermal Processing, M. M. Moslehi, H. Najm, L. Velo, R. Yeakley, J. Kuehne, B. Dostalik, D. Yin, and C. J. Davis
503
*Review of Process and Equipment Issues in RTP, J. J. Wortman, J. R. Hauser, M. C. Oztiirk, and F. Y. Sorrell
528
Principles of Wafer Temperature Measurement Using in situ Ellipsometry, H. Z. Massoud, R. K. Sampson, K. A. Conrad, Y.-Z. Hu, and E. A. Irene
541
Factors Affecting the Economic Performance of Cluster-Based Fabs, S. C. Wood and K. C. Saraswat
551
Single-Wafer Rapid Thermal CVD Technology for Fabrication of MOS and Bipolar Devices, A. Kermani, F. Wong, and K. E. Johnsgard
566
Simultaneous Measurement of Wafer Temperature and Native Oxide Thickness Using in situ Ellipsometry, R. K. Sampson and H. Z. Massoud
574
*Invited
x
A Cylindrical Tube Based Rapid Thermal Processor, D. T.
Chapman, J. M. Melzak, M. J. Fordham, J. J. Wortman, M. C. Oztiirk, and F. Y. Sorrell
582
PLANARIZATION TECHNIQUES
*Dielectric PlanarizationProcess for ULSI, C. H. Ting
592
*Overview of Planarization by Mechanical Polishing of Interlevel Dielectrics, S. Sivaram, R. Leggett, A. Maury, K. Monnig, and R. Tolles
606
Advanced Dielectric Techniques for the Fabrication of 16 Megabit DRAM Generation Devices, B. Ahlburn, R. Nowak, M. Galiano, and J. Olsen
617
Excimer Laser Assisted Planarizationfor ULSI Metallization, G. S. Sandhu, C. Yu, and T. T. Doan
627
Effect of Barrier Material on Excimer Laser Planarization of AICu, H. Chu, E. Ong, S.-Q. Wang, and 1. Raaijmakers
635
Application of a Spin-On-Glass Planarization Process to Submicron Triple Metal Technology, S. Morimoto, S. Queller, R. Gasser, and J. Kronschnabel
642
Oxide-Filled Trench Isolation Planarized Using Chemical/Mechanical Polishing, J. M. Pierce, P. Renteln, W. R. Burger, and S. T. Ahn
650
THOMAS D. CALLINAN AWARD ADDRESS Review of Thin Oxynitride Dielectrics for Memory Device Technology, V. J. Kapoor
657
*Invited
Xi
INTERCONNECT AND PACKAGING
*An Overview of Polyimide Use in Integrated Circuits and Packaging,R. M. Geffken
667
*Materialsand Packaging for Optical Interconnects: Status and Challenges, L. D. Hutcheson
678
Properties of PECVD 0 2/TEOS Silicon Dioxide, W. J. Patrick, G. C. Schwartz, J. D. Chapple-Sokol, K. Olson, and R. Carruthers
692
Electrochemical Effects of HF on Polyphenylquinoxaline Polymer Used in the Fabrication of PPQICu on Si Multilayer Interconnection Modules, F. Templier, J. Torr6s, A. Halimaoui, J. Palleau, and J. C. Oberlin
712
Gap-Fill with PECVD Silicon Dioxide Using Deposition/Sputter-Etch Cycles, G. C. Schwartz and P. Johns
720
Magnetron-Enhanced Etching of Double-Level Tungsten Interconnect, R. Hsu, C. Y. Fu, and B. Law
730
Selective Electroless Metal Deposition for Via Hole Filling and Conductor Pattern Formation in VLSI Multilevel Interconnection Structures, V. M. Dubin
739
WAFER CLEANING AND OXIDATION Novel Method for Prevention of Particle Deposition in Wet LSI Processes, A. Saito, K. Ohta, Y. Takahara, and H. Oka Low-Temperature in-situ Native Oxide Removal Using Anhydrous Hydrogen Fluoride, P. P. Apte, K. C. Saraswat, M. M. Moslehi, and R. Yeakley Low Temperature Oxidation of Silicon in an Electron Cyclotron Resonance Plasma, D. A. Carl and D. W. Hess *Invited
xii
749
755 765
Characterization of Stress Distribution in Submicron Isolation Structures by Micro-Raman Spectroscopy and Correlation with Transmission Electron Microscopy, I. De Wolf, J. Vanhellemont, A. Romano-Rodriguez, H. Norstr6m, and H. E. Maes
775
THIN FILM DEPOSITION A Manufacturable in-situ Doped Polysilicon Process for 16-64M Bit DRAM Technology, D. E. Bailey
785
Diffusion Behaviour of Dopants in Polycrystalline Silicon Electrode for Ultra High Speed Bipolar Devices, H. Yamaguchi and N. Owada
793
A New Polysilicon Texturization Technique Using Excimer Laser Processing, V. K. Mathews and C. Yu
800
As-Deposited Rugged Polysilicon for 16 and 64 Mbit DRAM Cells, V. K. Mathews, P. C. Fazan, and A. Ditali
810
Experimental Verification of a Fundamental Model for Multiwafer LPCVD of Polysilicon, T. A. Badgwell, T. F. Edgar, I. Trachttenberg, and J. K. Elliott
820
Low-Temperature Silicon Epitaxy without Substrate Heating by Ultraclean ECR-Plasma-Enhanced CVD, K. Fukuda, J. Murota, S. Ono, T. Matsuura, H. Uetake, and T. Ohmi
834
LPCVD of Silicon Dioxide Below 500 °C by Pyrolysis of Diethylsilane in Oxygen: A Safe Alternative to Silane, J. D. Patterson and M. M. Oztuirk
841
Optimization of Process Conditions for Selective Deposition of Polycrystalline SiGel-x Alloys in a Rapid Thermal Processor,M. Sanganeria, M. C. Ozturk, G. Harris, D. M. Maher, D. Batchelor, J. J. Wortman, B. Zhang, and Y. L. Zhong
851
xiii
MISCELLANEOUS PROCESSING ISSUES UV Annealing Passivation Effect on Sodium (Na+) Contamination, M. Itsumi, H. Yoshino, S. Nakayama, H. Akiya, and S. Muramoto
861
Variation of Surface and Interfacial SiO 2 Layers During Thermal Process, L. Ling and F. Shimura
870
Enhanced Degradation in Germanium Implanted PMOSFETs, L. P. Hobbs, A. von Schwerin, and K. Maex
880
xiv
FACTS ABOUT THE ELECTROCHEMICAL SOCIETY, INC. The Electrochemical Society, Inc., is a nonprofit, scientific, educational, international, individual membership organization founded for the advancement of the theory and practice of electrochemistry, electrothermics, electronics, and allied subjects. The Society was founded in Philadelphia in 1902 and incorporated in 1930. There are currently over 5000 scientists and engineers from more than 40 countries who hold individual membership; the Society is also supported by more than 100 corporations through Benefactor, Patron, and Sustaining Memberships. The technical activities of the Society are carried on by Divisions and Groups. Local Sections of the Society have been organized in a number of cities and regions. Major international meetings of the Society are held in the Spring and Fall
of each year. At these meetings, the Divisions and Groups hold general sessions and sponsor symposia on specialized subjects. The Society has an active publications program which includes the following. JOURNAL OF THE ELECTROCHEMICAL SOCIETY The JOURNAL is a monthly publication containing technical papers covering basic research and technology of interest in the areas of concern to the Society. Papers submitted for publication are subjected to careful evaluation and review by authorities in the field before acceptance, and high standards are maintained for the technical content of the JOURNAL. EXTENDED ABSTRACTS - Extended abstracts of the technical papers presented at the Spring and Fall Meetings of the Society are published in serialized softbound volumes. PROCEEDINGS
VOLUMES
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Papers
presented
in
symposia at Society and Topical Meetings are published from time to time as serialized softbound Proceedings Volumes. These provide up-to-date views of specialized topics and frequently offer comprehensive treatment of rapidly developing areas. MONOGRAPH VOLUMES - The Society has, for a number of years, sponsored the publication of hardbound Monograph Volumes, which provide authoritative accounts of specific topics in electrochemistry, solid state science and related disciplines.
Xv
DEVICE DESIGN AND PROCESS OPTIMIZATION OF SUB-HALF MICRON CMOS TECHNOLOGY Kuang-Yi Chiu, Dan Peters and Masakazu Kakumu Silicon Process Lab Circuit Technology R&D Hewlett Packard Company 3500 Deer Creek Road, Palo Alto, CA 94304
The device structure and process design optimization for realizing high performance and reliable sub-half micrometer CMOS devices will be discussed. As MOS device dimensions are scaling down to below 0.5 micrometer, optimization between performance and reliability becomes a must in choosing the right device structure, device design, and power-supply voltage. This paper addresses the trade-off between performance and reliability at both room temperature and low temperature operation, and solutions appropriate for fabricating ULSI circuits with sub-half micrometer CMOS devices. INTRODUCTION The two major technological driving forces that continue to propel the IC industry are the ability to scale feature sizes to enhance circuit packing density and the ability to further improve device performance by maintaining a constant powersupply voltage from the 64K DRAM to 4M DRAM technology generations. With the increase in scale of integration and the decrease of device dimensions to below 0.5 micron, the constant voltage scaling scenario, which the VLSI industry has employed in the past decade, is now encountering many physical limitations, especially the difficulties in maintaining the reliability of gate insulators and the hot carrier degradation of devices. The other limitation imposed on sub-half micron ULSI circuits is the significant increase in current density needed, which will cause electromigration problems in submicrometer interconnect line and contact holes. To overcome these fundamental limits encountered by the scaling into the sub-half micron regime, a comprehensive study in device design, process technology, and its operation environments are needed in order to make the best use of further scaled CMOS devices. In this paper, the relationship between device, structure, power-
I
supply voltage, device operation temperature, and fabrication process is examined especially for sub-half micron CMOS technology generations. DEVICE DESIGN OPTIMIZATION For many VLSI technology generations, power-supply voltage has been maintained at 5 volts for actual CMOS VLSIs in order to achieve higher circuit performance and maintain TML compatibility. This constant voltage scaling has been achieved with many device structure modifications, such as double diffused drain (DDD) and lightly doped drain (LDD) etc.. However, as MOS device geometries are scaling down to 0.5 um or below, reliability problems caused by hot carrier injection, oxide breakdown, gate-induced leakage and overall power dissipation concerns have made the reduction of power-supply voltage a necessity. However, the drive to continue increasing circuit performance places other demands on device design. The most important issue in the sub-half micron CMOS device design is an appropriate choice of a power-supply voltage to address the fundamental trade-off between performance and reliability of CMOS circuits. It has been observed that a higher power-supply voltage cannot always provide high-speed operation for circuits with below 0.5 um geometries, because higher electric field and impurity concentration could cause mobility degradation, increase in parasitic capacitance, and many other degradation effects. Optimization of device design with appropriate choice of power-supply voltage is critical for developing sub-half micron CMOS technology. Fig. 1 summarizes results obtained for an optimized power-supply voltage and process/device parameters selected by simulation for 0.2 um, 0.3 um and 0.5 um CMOS devices at both room temperature [11 and low temperature [2]. Physical Dimension of Poly Length Power-Supply Voltage M Gate Oxide Thickness inm) Threshold Voltage of nMOSFET M Threshold Voltage of pMOSFET M 3 Surface Impurity Concentration (cm- ) 3
Bulk Impurity Concentration (cm- ) Transconductance (mS/mm) of nMOSFET Transconductance (mS/mrn of pMOSFET Delay time with F1O II (ps/stage) Delay time with F/O = 3 (pa/stage)
0.2 lam
0.5 grm
1.4 (2.4) 6.5 (8.0) 0.18 10.53) 0.20 0.55) 5.3E16/5.3E16
2-0 (3.2) 10.5 (11.5) 0.21 (0.56) 0.22 (0.58) 2.3E16/2.3E16
2.8E17 InMOS13.3E17 (pMOS) 542 (298) 303 (169) 21.8 (37.4) 56.3 (79.3)
1.3E1719.gE16 286 (202) 155 (104) 30.5 (49.7) 75.0 (106.4)
5.8E1614.9E16 197(145) 106(72.2) 38.2 (70.9) 93.2 (156.8)
Delay time with F/O = 3. At 2mm (ps/stags) Power Density (s.u)
SNote:
0.3 pm
1.0 (1.7) 4.5 (5.0) 0.15 4D.39) 0.16 43.42) 2.0E17 CnMOSI2.1E17 (pMOS)
Off current criterion for RT -0.2gm
82.7 (120.7)
114.4 (173.4)
0.92 (1.23)
0.99 (1.15)
158.5 (276.2) 1(1)
Is lOpA/ pm
Fig. 1. A simulated optimum power-supply voltage and process/device parameters for sub-half micron CMOS at room [1] and 77 K [2] temperatures. Room temperature dates In parentheses.
2
It should be noticed that for a chosen optimum power-supply voltage at each technology generation, other process parameters such as gate oxide thickness, impurity concentrations and source/drain junction structure are changed to achieve the highest circuit performance and maintain its circuit reliability. PROCESS DESIGN OPTIMIZATION With the progress that has been achieved in lithography techniques, optical lithography will provide the manufacturing capability for continual down scaling. However, as we crossed into the sub-half micron era, conventional device structure and fabrication techniques reached their physical limitations. Therefore, it is necessary to develop new structures or use new materials to overcome key performance and reliability limitations, such as the parasitic resistance and capacitance, the sub-half micron contact etch and fill and interconnect RC delays, etc.. Fig. 2 shows the CMOS/VLSI process evolution that has happened from 1.8 to 0.5 micron generation and predicts what will be needed in the sub-half micron generations. Technology
Generation 1.8 urn
Isolation
Gate rnter.l
Material Well
Technology
dielectrics
Junction Structure
N or P well
LOCOS
N-polyloxide
N+/P+
Contact and [interconnect Via structure metal Wetetched tapered contact
Al-Si
Power Supply Voltage
5.0 V
N-polyloxide polycde
5.0 a Dry etched LOCOS DDD Al-Si 1.2 urn N or P well slopedcontact n-LDD Dry etched 5.0 v 0.8 urn Twinwell/ EPI ModifiedLOCOS N-polyloxide SALUCIDE sloped contact AI-SI Cu/TiW Vertical contact n& pLDD I EPf Twin well Modified LOCOS N-polyfoxede 0.5 urn TiN/Al-Cu/TiN 3.3 / 5.0 v SALICIDE with W plug Retrode grade Shallowtrench N and PFrameless cent GOLD/N+/P0.35 urn well I EPI Poly/oxide SALICIDE Via with W plug TiN/AI-Cu/TiN 2.5 13.3 v Shallowand ITUNAI-Cu/TiN Retrode grade 0.25 um N &P poly/ON(GOLDNI/P- Stackedcontacl wellI EPI Deep trench ?7?????? SALICIDE??fl withW plug or Cu/TiN??? Retrode grade Shallowand Cu/TiN???? or 0.15 urn Ref.retaT??/ welVEPIor SO0 Deep trench Hi-Tc sup.???? Fig. 2.
CMOS VLSIIULSI process technology trend
Some of the emerging technologies such as isolation, LDD with shallow junction structure, self-aligned silicide, local interconnect and self-aligned contact structures for sub-half micron ULSI will need significant improvement to comply with the device down scaling. Multilevel interconnect technology will perhaps undergo the 3
most significant changes in the sub-half micron era. All sections of interconnect technology require major improvement in the future that includes: Metal material structure, dielectric deposition and global planarization, non-enclosed contacts as well as the etch and fill of sub-half micron contacts. CONCLUSION As technology drives toward sub-half micron generation and beyond, many device structural changes are required in order to continue improving circuit performance and density, and to maintain reliability goals. Trade-off between performance and reliability needs to be understood for selecting an optimum powersupply voltage and the associated device structure and its process technology to fabricate a high performance and reliable ULSI circuit. REFERENCES 1. M. Kakumu, M. Kinugawa and K. Hashimoto, IEEE Trans. on Electron Devices, vol. Ed- 37, p. 1334, 1990. 2. M. Kakumu, D. Peters, H.Y. Liu and K.Y. Chiu, in IEDM Tech. Dig., paper no. 9.1, December, 1990.
ADVANCED DEEP-SUBMICRON BICMOS TECHNOLOGY Katsuhiro Shimohigashi, Central Research Laboratory, Hitachi Ltd. 1-280 Higashi-Koigakubo, Kokubunji Tokyo 185, Japan This paper will overview the deep-submicron BiCMOS tehchnology in the 1990's from the process, device, and circuit point of views. Critical design issues, such as the MOS-bipolar performance optimization, the isolation technology, the metal layer design, and the process modulalrity, are described and the future device development direction will be shown. In addition, our experimental half-a-micron BiCMOS technology will be presented, as an example. INTRODUCTION Since the introduction of BiCMOS technology to Large-Scale Integrated circuits, it has been used for a variety of products throughout the 1980', with the device feature size of 3.0-1.0 Jim. Although BiCMOS technology has the advantage compared to CMOS and bipolar technologies as shown in Fig. 1[11, scaling down to the deep-submicron range is said to be rather difficult, because both bipolar and MOS devices should be scaled simultaneously. The purpose of this paper is to describe the deep-submicron BiCMOS technology in the 1990's, showing our experimental half-a-micron BiCMOS technology as an example. INTEGRATION TREND Figure 2 shows the trend of the integration density versus the device feature size [2]. The density has been increasing four times in every three years, which is just as same as the MOS memory density trend. In the middle of the 1990's, one hundred million devices will be integrated on a single chip with the device feature size of 0.3tim. Its impact is so large that the middle to large computers could be integrated on a chip. DEEP-SUBMICRON BICMOS DEVICE DIRECTION Although, there are two types of device structures, costoriented CMOS based one and performance-oriented bipolar based one, the discussion hereafter will mostly deal with the performance 5
oriented BiCMOS technology. There are a number of issues for realizing the deep-submicron BiCMOS. These include, 1) the optimum design between bipolar and MOS device parameters, 2) high performance bipolar and MOS structures, 3) the isolation technology, 4) the number of metal layers and materials, 5) low voltage device and circuit designs, 6) the device and metal reliability, and 7) the modular process design.
108 Z
0
1o
7
'2
Slo6 aO5
m
i I I
3
I
I
2 1.3
I
I
I
0.8
0.5
0.3
Device Feature Size (gim) Fig. 1 Performance Comparison.
Fig. 2
Device Integration Density vs. Device Feature Size.
The optimum design between the bipolar and MOS performance is the key to the device design, as shown in Fig. 3. The fT of the bipolar device should be increased linearly to the scaling factor K to achieve the best performance of the BiCMOS gate circuit [3].In the deep submicron regime, the fT of larger than 20GHz will be necessary, leading to the necessity of the self-aligned bipolar structure. As the supply voltage will be reduced lower than 5V, MOS devices should also be designed carefully. Although the current capability enhancement by the drain engineering and the channel doping profile control is most important, the reduction of the source/drain resistance and capacitance should be considered at the same time. The silicidation technology will become important. For applying to the very high-speed ECL circuits, the reduction of the collector-substrate capacitance Ccs of the bipolar device is critical. The trench isolation technique should be used. 6
Although the required number of metal layers will depend on a particular application, at least three layers will be necessary for realizing complex digital functions in the 1990's. As will be apparent from the above discussion, the application of BiCMOS technology is expected to be quite wide, the costperformance or the process complexity versus the performance should better be traded-off in each application. The process modular design will become the most important leverage to realize the versatility of BiCMOS technology. Figure 4 shows a design device structure[3]. S50
-P---BMOS
(3 ..•20 0~
St10 K1
-
U2
I
0 0.3
I 0.5
0.8
I
I
1.3
2
Device Feature Size (grm) Fig. 3
ample of the half-a-micron BiCMOS
-
POLARE-
l
3
Fig. 4
fT versus Device Feature Size.
Cross-sectional View of 0.5 jPm BiCMOS Structure.
LOW VOLTAGE DEVICE AND CIRCUIT The low voltage BiCMOS gate development has been paid much attention in these days[4] and it will greatly affect the device structure. The conventional BiCMOS gate(Fig. 5(a)) can not be used with the supply voltage of less than 3.5-4.OV because of the combined voltage drop, Vth +VBE, as shown in Fig. 6. For the low voltage operation, the BiNMOS gate(Fig. 5(b)) and the complementary BiCMOS gate (Fig. 5.(c)) are likely to be the candidates. The CBiCMOS gate has an advantage of the lower voltage operation down to 2-2.5V. However, an additional PNP bipolar device is required, resulting in the increase in the process complexity. Therefore the coupling between the process and circuit design will become much more important in the future BiCMOS technology development.
7
(a)BiCMOS
(b)BiNMOS
(c)CMeMOS
R
{3 02
V
0
•
U
"1 ADDITIONAL 0 NO ISOLATION
NO PROCESS
.
.
S
.
2 V 3
.
4V
.
V)5
Supply Voltage Vs (V)
FOR BIPOLAR
Fig. 6
Fig. 5 BiCMOS Gate Circuits.
Gate Delay Time vs. Supply Voltage.
CONCLUSIONS We have reviewed the design issues for the advanced deepsubmicron BiCMOS technology and showed a future device development direction, showing our experimental half-a-micron BiCMOS technology as an example.
REFERENCES [1] [2] [3] [41
M. Kubo, "Perspective to Bi-CMOS VLSIs", Symp. on VLSI Circuits, pp89-90, May, 1987. K. Miyata, "BiCMOS technology overview", in '87 IEDM Short Course "BiCMOS Technology", A. Watanabe et al, "Future BiCMOS technology for scaled H. J. Shin, "Full-swing logic circuits in a complementary BiCMOS technology", Symp. on VLSI Circuits, pp89-90, June
1990.
8
A P+ POLY-Si GATE WITH NITROGEN-DOPED POLY-Si LAYER FOR DEEP SUBMICRON PMOSFETS Satoshi Nakayama 3-1,
NTT LSI Laboratories, Morinosato Wakamiya, Atugi-si, Kanagawa, 243-01, Japan
thin A new P+ polysilicon gate with a very layer at the polypolysilicon nitrogen-doped silicon gate/SiO2 interface is proposed for deep submicron PMOSFETs. This nitrogen-doped silicon boron penetration layer effectively suppresses through the ultra-thin oxide into the silicon A thin nitrogen-doped silicon layer substrate. of about (5 nm) with a nitrogen concentration 1x10 2 1 cm- 3 gives a process margin of about 50'C during heat-treatment after the formation of the gate electrode. This suppression of boron decrease in boron penetration is due to a diffusivity in the nitrogen-doped silicon layer. INTRODUCTION have been Over recent years, P+ polysilicon gates in suggested to fabricate surface-channel PMOS devices surfacedeep submicron regions[l,2]. This is because buried channel PMOS devices are superior to conventional in respect to both short channel channel PMOS devices characteristics and turn off characteristics. However, P+ polysilicon gates are disadvantaged by unstable threshold voltages. This is due to penetration of boron from the into the channel region through the gate oxide boron-doped polysilicon gate. This penetration of boron wet 02 ambient conditions is accelerated by annealing in or H2 ambient conditions, or by fluorine incorpolating into implantation[3,4,5]. the gate electrode, a result of BF 2 The issue of boron penetration becomes more serious as gate a new oxide thickness is reduced. This paper proposes supresses boron polysilicon gate that effectivily penetration through the ultra-thin gate oxide. SAMPLE PREPARATION and The new polysilicon gate consists of a boron-doped a nitrogen-doped double layer. The nitrogen-doped silicon
9
layer was deposited onto the gate oxide at about 510 O by LPCVD (low chemical
2 z
"
pressure vapor
deposition) with
a
Si 2 H 6 -NH 3 gas system. Then, without any breakin processing, the boron-doped silicon
layer was deposited onto the nitrogendoped silicon layer at the same of temperature 510*C with a
Si
2 H6
-
o
z
9
8 z w
•
R m 1io7
010-
I0-
z
P,4 , (atm) Fig.I
Dependence of depositon rate and
B2 H6 gas system[6]. nitrogen concentration in nitrogen-doped silicon on NH3 partial pressure. the Figure 1 shows dependence of deposition rate and nitrogen concentration on the partial pressure of NH3 . Here, nitrogen concentration(CN) was determined by secondory ion mass spectroscopy (SIMS). Deposition rate decreases slightly with NH3 partial pressure increases. Also, nitrogen concentration is in almost direct proportion to increases in NH3 partial pressure. The characteristics of MOS diodes fabricated on P-type substrates (5 Pcm) with the new polysilicon gate were evaluated. The total thickness of the polysilicon gate was 300 nm and boron concentration of the boron-doped polysilicon layer was 2x10 2 0 cm- 3 . The thickness of the nitrogen-doped silicon layer in the polysilicon gate was about 5 nm estimated by deposition rate and deposition time. The thickness of the gate oxide determined by ellipsometory was 3.4-3.8 nm. MOS diodes were annealed to electrically activate boron atoms after definition of the polysilicon gate. During this heat-treatment, boron atoms diffuse into the nitrogen-doped silicon layer and the gate oxide. RESULTS AND DISCUSSION Effects of the nitrogen-doped silicon layer The flatband voltage (VFB) of the MOS diode with the new polysilicon gate was determined by its high-freqency C-V characteristics. Figure 2 shows typical highfrequency C-V curves of MOS capacitors whose structure is shown in the inset. For samples annealed in dry N2 ambient 10
conditions, the VFB of capacitors with nitrogendoped silicon layers of CN=O is
the This
almost
value.
boron
that
indicates
wet 02 increases
L-.. "a boronC"
50
•
-um
T0x-3.7nm ea ixl- 4cm 12
dry N2 . (AVFB)
,
(cm-3)
10 x14. ,
0 -1
compared These
0
j
0
GATE VOLTAGE (V)
annealed
with capacitors shifts
Anneal: 850eC,30rin Niog,,-do4 wet 02 Ply-Sl layer
- -----. dry N2
the same as
theoretical
penetration can be ignored if annealing at 850'C in dry N2 even when CN=O. dry Annealing at 8506C in N2 is, therefore, assumed not to cause any boron penetration regardless of CN of nitrogen-doped silicon layers. On the other hand, the VFB of capacitors annealed in in
100
VFB
Fig.2
Typical high-frequency C-V curves of the p+ polysilicon gate MOS capacitors. MOS capacitor structure is shown in inset.
are ascribed
to boron penetration into the substrate, The AVFB resulting from boron 0,5 penetration by annealing in wet 02 is shown in Fig. 3 0.4as a function of CN. Here, AVFB is the 0.3difference in VFB
Anneal: 850°C, 30min wet 02
>
between capacitor dry N 2 in annealed with and capacitor
the same CN annealed in wet 02. The AVFB decreases with
increasing CN UP to 3 21 cm-
of
beyond which
it
about lxl0 CN,
levels result that
off. This demonstrates the
nitrogen-
• > <
0
To Nitrogen doped layer
5nm
0.1 0.0
20
0 10
21
1021
22
1022
NITROGEN CONCENTRATION (cm-') Fig.3 Dependence of flatband voltage shift on nitrogen concentration of nitrogen-doped silicon layers.
doped silicon layer is effective at blocking the penetration of boron. Electrical properties of nitrogen-doped silicon The resistivity increases with dependence of
of the nitrogen-doped silicon layer increasing CN as shown in Table 1. The resistivity on CN should affect the 11
characteristics of MOS diodes. As shown in Figure 2, capacitance in the accumulation region of capacitors with nitrogen-doped silicon layers of CNAO is smaller than that of capacitors with nitrogen-doped silicon layers of CN=OAlso, the VFB of capacitors with nitrogendoped silicon layers of CN*O annealed in dry N2 shifts in the
Table 1 Resistivity of nitrogen-doped polysilicon film. Nitrogen-doped polySi film is implanted with boron atoms 0 and annealed at iOO0C. Boron concentration in nitrogen-doped poly20 3 Silicon is about 2X10 cm- .
NITROGEN RESISTIVITY CONCENTRATION (cm- 3 ) (n cm) 9.0x1020
2 1.5x10 1 2.8x10 2 1 2 4.0x10 1
4.2x10-1 1.2 3 4.0x10 3.4x10 5 InnV Ivy
Cox -4 direction when compared with the 0.2-9 theoretical Li_ value. The VFB ,. and maximum capacitance TN 50. E N(Cmax) are shown • 0.0 U-) in Figure 4 as a 2 4 Diode Area I x IO cmr function of CN in the nitrogendoped silicon i fli layer. The VFB -0.2 u.-A. 0 2 decreases with 0 100 102 1Q021 increasing CN. NITROGEN CONCENTRATION (cm-3 ) Here, the samples were annealed at Fig.4 Dejpendence of the VFB and Cmax of samples, 8500C in dry N2 , with nit:rogen-doped silicon layers, on nitrogen concentra tion in nitrogen-doped silicon layers, and the effects boron penetration influence through the boron without of can gate oxidi e. penetration therefore be ignored. The dependence of VFB on gate oxide thickness is independent of nitrogen concentration and VFB extrapolated on Tox=0 for CN 0 O is smaller than that for CN=O as shown in Figure 5. These results indicate that the difference in the work function between the P+ gate and the substrate decreases with increasing CN. This is evidence that the decrease of VFB results from a change in the Fermi level of the nitrogen-doped silicon. The Cmax is almost constant up to 1x10 2 1 cm- 3 of CN and then decreases. This decrease of in Cmax is ascribed to the formation of a depletion layer the polysilicon gate as a result of decreasing carrier concentration in the nitrogen-doped silicon layer. Increasing gate oxide thickness also retards boron penetration and decreases maximum capacitance. Figure 6 I
12
shows the dependence of AVFB, due to boron penetration, on apparent gate oxide thickness (Tox') determined by the maximum capacitance. The AVFB is about 0.2 V even at 5.6 nm of Tox when changing gate oxide thickness, whereas LVFB is about 0.1 V at 4.4 nm of T40SC when increasing CN in the nitrogen-doped silicon layer. These results show that a thin nitrogen-doped silicon layer is more effective at suppressing boron penetration than increasing gate oxide thickness. Figure 6 also shows that samples with nitrogen-doped silicon layers tolerate heat-treatment temperatures up to 50'C higher than samples without nitrogen-doped silicon layers. Explanations for boron penetration retardation There are two possible explanations for this retardation of boron penetration. It is due, either to a decrease of boron diffusivity in the nitrogen-doped silicon layer, or to a change in the segregation coefficient of boron at the nitrogen-doped silicon and SiO2 interface. The diffusion coefficient of boron into nitrogendoped polysilicon from
0.3
Anneal: 850°C, 30min
0.2 0.1 >
0.0 -0.1 -0.2
im
[
-_n
I
I
I
10
v%0
I
I
I
20 30 40 50
GATE OXIDE THICKNESS (nm) Fig.5 Dependence of MOS capacitor flatband voltages on gate oxide thickness.
-o- without N-doped layer -*- with N-doped layer
05 >
-,-
i.
IM0. Anneal
without N-doped layer 800C Anneal
0.4
= 0.3 > .=:3
0.2
0.1 nAt %/.%2
3.5
4.0
5.0 TO (nm)
6.0
Fig.6 Dependence of flatband voltage shift on apparent gate oxide thickness (Tax) determined by maximum capacitance. Open circles represent changing gate oxide thickness of capacitors without nitrogen-doped silicon layer, while closed circles represent changing nitrogen concentration in nitrogen-doped silicon layer of capacitors with the same gate oxide thickness. Open triangle shows the sample annealed at 800 *C without nitrogen-doped silicon layer. All samples were annealed in wet 02 atmosphere.
13
, ý21
'E '0
(IJ E
Q LU
z
8 z w
z
0
C.)
0 uD
0.5
IV0.0
IUv
DEPTH (nm)
DEPTH (prm)
Fig.8
A profile
concentration Fig.7 Profile concentration in
polysilicon doped
and
of boron boron doped
polysilicon, polysilicon
nitrogen-
polysilicon
in
of
boron
boron-doped
nitrogen-doped and silicon oxide
annealed at 9001C for I hour.
annealed
at 900°C for 30 min.
the boron-doped polysilicon was examined by SIMS. Figure 7 shows the distribution of boron concentration in the nitrogen-doped polysilicon after diffusing the boron from the boron-doped polysilicon for 30 min at 900TC. The diffusion coefficient of boron in the nitrogen-doped polysilicon was determined by fitting the SIMS data to the error calculated with the complementary boron profile function deduced from Fick's law, assuming the constant concentration source. Figure 8 also illustrates boron poly profiles in boron-doped poly silicon, nitrogen-doped silicon and silicon dioxide after annealing for 1 hour at 900C. The segregation coefficient of boron has been defined as the ratio between boron concentration in the nitrogen-doped silicon layer and the silicon dioxide adjacent to the interface as shown in Figure 8. The diffusion coefficient (DB) and segregation coefficient (MB) determined by figures 7 and 8 are shown in Figure 9 as a function of nitrogen concentration in the nitrogen-doped polysilicon. The DB decreases with increasing of CN up On the to about 2-3x10 2 1 cm- 3 , then increases slightly. 21 1x10 other hand, the MB is almost constant up to a CN of cm-3 and then increases. These results indicate that any not retardation of boron penetration shown in Figure 3 is due to a change in the segregation coefficient, but rather 14
to
a
decrease
boron
of
diffusivity
-43
in the nitrogendoped silcon layer. It
should
be
noted, in Figure 9, that the minimum
10.
10 qn lnneol Temp. 900°¢
-
0
diffusivity in 10ý14 1,0 nitrogen-doped polysilicon 8 0 z coincides with the o boron diffusivity I i ln s ing le n Single -silicon [4]. '1 -0.I According to xray20 21 22 diffractometer 0 10 10 10 C/ 3 measurements, the NITROGEN CONCENTRATION (cm- ) grain size of Fig.9 Dependence of boron diffusivity and nitrogen-doped boron segregation coefficient on nitrogen polysilicon is concentration in nitrogen-doped polysilicon. smaller than that of the boron-doped polysilicon. These results suggest that the decrease of boron diffusivity in nitrogen-doped polysilicon is due to boron diffusion retardation along the grain boundaries. CONCLUSION A new P+ polysilicon gate with a very thin nitrogendoped polysilicon layer was proposed for deep submicron PMOSFETs. The nitrogen-doped silicon layer effectively suppresses boron penetration through a thin oxide. A very thin nitrogen-doped silicon layer (5 nm) with a nitrogen 2 1 3 concentration of about ix10 cmgives an additional processing margin of 50'C during heat-treatment after the formation of the gate electrode. Retardation of boron penetration is due to a decrease in boron diffusivity in the nitrogen-doped silicon layer. ACKNOWLEDGMENT The author would like to acknowledge the continued encouragement of T. Sakai, and would also like to thank Y. Sakakibara and M. Tabe for their many helpful contributions during the course of discussion.
15
REFERENCES [1]N. Kasai, N.Endo, H.Kitajima, IEDM Tech. Dig., p.367(1987) [2]B. Davari, et al., IEDM Tech. Dig., p.56(1988) C. Wong, Y. Taur, C. -H. Hsu, Digest of [3]J. Y. -C. Sun, the Intl. Symposium on LSI Technology, p.17(1985) IEDM [4]J. M. Sung, C. Y. Lu, M. L. Chen, S. J. Hillenius, Tech. Dig., p.447(1989) [53F. K. Baker, et al., IEDM Tech. Dig., p.443(1989) I. Kawashima, J. Murota, J. Electrochem. [6]S. Nakayama, Soc., Vol.133(8), p.1721(1986) Pergamon [7]H. F. Wolf, Silicon Semiconductor Data, p.141, Press, Oxford(1969)
16
SUPERSILO/RTN: QUASI-RECESSED FIELD OXIDE AND 80 nm BIRD'S BEAK USING A SILO/RTN PROCESS
P. Molle and S. Deleonibus CENG/LETI-SMSC 85X 38041 GRENOBLE CEDEX
SUPERSILO/RTN is a new isolation technique based on a SILO/RTN process and subsequent deposition, oxidation and etch-back steps. The process parameters are explored in order to provide a defectfree, quasi-recessed field oxide and a bird's beak length as short as 80nm. CMOS device performance shows the compability of the process with 0.8igm design rules and high supply voltage. Low junction leakage currents and high gate oxide breakdown fields are obtained.
INTRODUCTION Because of the presence of the bird's beak, LOCOS technology is no longer suitable for submicron circuits. SILO/RTN (Sealed Interface Local Oxidation by Rapid Thermal Nitridation) is a new isolation technique which uses a Rapid Thermal Nitride and a trilayer of Nitride/Oxide/Nitride to limit the lateral diffusion of oxidant species under the nitride mask [1]. The SiLO/RTN process can provide a defect-free structure with a bird's beak length as short as 0.15 lam, for high performance submicron CMOS (0.6 lam design rules) compatible with 13V supply voltage [2], [3]. We present here an optimization of the former SILO/RTN, called SUPERSILO, which can provide a quasi-recessed field oxide with 80 nm bird's beak length, for a lpm as-grown field oxide. The main steps of this process are given on Figure 1 and the important points are: 1. using a SILO/RTN process in order to limit the bird's beak growth; 2. growing a very high field oxide thickness so that more than 50% of the desired final field oxide thickness remains under the silicon surface; 3. consuming the field oxide overthickness during the masking layer (Oxide2/Nitride2) removal and by using an etching process with an oxide/nitride selectivity higher than 1; 4. Using a polysilicon film, oxidized during field oxidation, in order to limit preferential etching effects at the edge of the nitride mask. All the process parameters are explored in order to obtain a field isolation compatible with a 0.81rm CMOS, double level metalization 16K SRAM in wich the intermetal dielectric is achieved with a borosilicate glass (BSG) planarization using total etch-back of Spin On Glass (SOG) (4].
17
EXPERIMENTAL DETAILS SUPERSILO isolation is achieved within a 3*1016 cm- 3 doped twin-wells process flow. RTN is performed in a RTP equipment (ADDAX RRA) under atmospheric pressure in ammonia ambient. The RTN layer is only 20A thick and its composition has been determined by XPS, Auger and Nuclear Analysis: quasistoechiometric silicon nitride is obtained with an oxygen ratio below 10%. The SUPERSILO flow-chart, given on Figure 1, includes: Nitridel / Oxidel / Nitride2 / Oxide2 deposition, patterning, resist hardening, etching of the mask, boron P+ field implant, 1st oxidation (0.3 or 0.5 im at 9501C), poly deposition(0.05 or 0.1 g-m), 2nd oxidation(from 60 to 330 mn at 9500C) and etch back. Nitridel/oxidel/Nitride2 thicknesses are determined, and are respectively lOOA/300A/500A. The oxidation mask and field oxide are simultaneously etched back in a mixed dry-wet planarization scheme. The dry etching is performed in a high pressure low gap RIE reactor (ALCATEL RGV 220) using a CHF3/C 2 F 6 /Ar/0 2 chemistry. This process can provide an oxide etch rate 1.5 times higher than the nitride etch rate and the etching is stoped after complete elimination of Nitride2. Buffer Oxide, Nitridel and RTN are removed using alternated wet solutions [5]. On CMOS devices the 17nm gate oxide film is grown after a 45nm sacrificial oxide and subsequent removal.
I) RTN / NITRIDEI
I OXIDEI I NITRIDE2 / OXIDR2
I___________________
IoxEDE
NITRIDR2 OXIDEII
2) PATTERNING,ErlIENG, P. FIELD IMPLANT AND IST OXIDATION
ox ydatiON INST L
i
3) POLYSELICONDEPOSITION AND 2ND OXIDATION
4) E'CH RACK
FINAL OXION
Figure 1: SUPERSILO isolation sequence 18
RESULTS Physical
characterization
The total oxide thickness obtained on field areas
after the 2nd oxidation
depends on oxidation (1st and 2nd) time and polysilicon film thickness. We report on Figure 2 the total oxide thickness as a function of the 2nd oxidation time for two 1st oxidation thicknesses (0.3 lim and 0.5 gim) and 2 polysilicon thicknesses (0.05 grm and 0.1jim). 1.3iim final oxide thicknesses can be reached with this technique on field areas.
I-
OXIDATION TIME (nm)
Figure 2: Total field oxide thickness as a function of second oxidation time Figure 3 shows SEM micrographs of a SUPERSILO structure after the 2nd oxidation, the Oxide2 thickness is 0.1l m, the oxide thickness grown on field areas after 1st oxidation is 0.511m, the polysilicon thickness is 0.14im and the 2nd oxidation time is 5h. We can observe that a bird's beak length close to 0.21gjm can be obtained for a 1.15jim as grown field oxide.
Figure 3: SEM micrograph of a SUPERSILO structure after second oxidation 19
If both, SILO/RTN and etching processes are fixed, we can assume that the planarization of the field oxide only depends on Oxide2 thickness and second oxidation time. This is the reason why three Oxide2 thicknesses (0.1 gim, 0.2 lim and 0.3 jim) have been explored. In order to obtain a constant final oxide thickness, the 2nd oxidation time has been increased with the increase of oxide2 thickness. We report on Figure 4 oxide thicknesses measured on field areas after each etch step. We can see that, the thicker the oxide2 the more important is the consumption of field oxide during etch-back. Figure 5 shows the ratio of recessed oxide in the final oxide thickness. This ratio increases with oxide2 thickness and can reach 80% of the O.72gm final oxide, for a 0.5iim oxide2 thickness. Resulting profiles are given on Figure 6. We can observe, in all cases, a good step coverage and a bird's beak length shorter than 0.1[tm after etch-back. Wright etch has been performed after complete removal of the dielectrics films: no oxidation induced defect has been observed. 2ND OXIDATION TIME (h) 6 1
5 1,41 1,3 1,2 1,11,
,
7 1
S 1,0 0,9 U 0,8 ' 0,7 . 0,6
FIER ND OXIDATION
FIER DRY STEP AFTER WET STEP
S0,5 • 0
0,4 0,3 0,2 0,1 0,0 U,1
0,2
0,3
OXIDE2 THICKNESS (prm)
Figure 4: Oxide thickness on field areas
5 0,91i
2nd OXIDATION TIME (h) 6 I
7
=L 0,1
S0,7 0,; U
SILICON SURFACE 0,3 0,:
0
0,: 0, UE
U,&
Us,3
OXIDE 2 THICKNESS (pim)
Figure 5: Recessed field oxide thickness as a function of oxide2 thickness 20
a)
b)
C)
Figure 6: SEM micrographs of a SUPERSILO isolation, after etch-back. Oxide2 = a) O.1jam; b) 0.2gm; c) 0.3gm Magnification = 230000
Electrical
results
CMOS devices have been performed with a SUPERSILO isolation process. Active devices: The narrow channel effects are 50mV/-200mV are obtained between 25x25 and transistors. The effective channel width is found to actual etched critical dimension of the active area mask This confirms that the bird's beak is 0.08gm long.
given on Figure 7. Delta Vt of 0.6xl0(WxL) NMOS/PMOS be 0.16gm smaller than the on NMOS and PMOS devices.
Ids = f(Vgs) characteristics of 0.7/0.8gm gate length N/P devices are given on Figure 8. The subthreshold slopes are respectively 90 and 85mV/dec and no double subthreshold regime is observed as in badly isolated transistors [6]. For larger geometries, no short channel effect is observed and punch-through is controlled by drain avalanche breakdown at 12,5V/-13V for NiP devices.
21
ii
2 VTN(V)
Rý
. .-
ft
.
.V
S........... -1 ............ ............
VP( V)_ U,0
0,2
0,4
0,6
0,8
1,0
1,2
1,4
1,6
1,8
2,0
Wd (g±m) Figure 7: Narrow channel effects, Vt=f(W).
IDS
IDS
VGS
NMOS
VGS
PMOS
Figure 8: Ids=f(Vgs) for 0.7/0.8 gim a)NMOS/b)PMOS gate lengths. Parasitic devices: Vgoff values (measured for a leakage of 1OpA/micron of device width) are reported on Figure 9 as a function of N+/N+ (NMOS) or P+/P+ (PMOS) spacing. NMOS and PMOS poly, metal, metal2 gate field transistors are controlled on devices with minimum N+/N+, P+/P+ spacing of 1.2lam and Vgoft larger than 14V. This is possible with a charge free process using a thick BSG, total etch-back SOG and BSG trilayer deposition to achieve a charge free intermetal dielectric, allowing no subthreshold inversion of field devices [4]. Punch-through voltage (BVDSS) is reported on Figure 10, BVDSS of poly gate devices is the limitation to high voltage sustaining: 12V/-11.5V are the obtained values for N/P devices. 22
20 2 19 ..................................................... .....................................................' ........................... - !
17
4".17
16
9
.16
F
15
.15. -14i ................. ........................... $..........................'•............................-1 4
1s----14 ....... .................... 13
0,
.13
12
. -1 2
............... .......
11F
-
1,0
-11 in 1,2
-10 1,4
N+/N+
1,6
1,8
2,0
(or P+/P+) SPACING (jim)
Figure 9: Poly gate field transistors Vgoff versus N+/N+ or P+/P+ spacing. .1
1
S.......................... t .................... ..................
14
U
13
..................
.........
14
:.13
.12
12
--
11 C8 0 10 CZ
----
- -
-- o-
"--0--
9
0---"... -- 6 --
8'7 .......................
---
-..--
i 'is
- .11 _
_
-10
_
PoLYGATEFID NMOS POLY GATEFIELD PMOS MErAL1GATE FIELDNMOS MErALI OATEPIIlD PMO 4.......................... MErAL2 GATE m DNmm METAL2 GATE FIORD PMOSI
-
0 0,
a 7
6 .6
1,0
N+/N+
Figure 10: Poly, metal, P+/P+ spacing.
1,6
1,4
1,2
1,8
2,0
(OR P+/P+) SPACING (pro)
metal2 gate field transistors BVDSS versus N+/N+ or
Desio ruLue: Contact to active edge minimum distance design rule is compared between SUPERSILO, SILO/RTN and conventional LOCOS processes. Bird's beak lengths are respectively 0.08gm, 0.15gm and 0.45gm with bird's beak angles of 800, 600 and 450. Because of the recessed shape of SUPERSILO, overlapped to field oxide contacts are allowed, whereas a minimum distance of 0.4Rm is necessary in conventional LOCOS (Figure 11). 23
Log (Ileak)
Log (lleak)
-./
difftusion
N+
I
. ...
P+ diffusion
•...................... ,,s+........ =--1-1so 1-1...
-8 ---
SILO/RTN
-*-SUPERSILO
.9
-9
-10-
-10
•
.J
.
,
.P
.11
-0,5 Contact
0,0
0,5
/Active
edge
1,0
1,5
distance
2,0
-0,5
0,0
Contact /Active
(micron)
0,5
1,0
edge
distance
1,5
2,0
(micron)
Figure 11: Contact to active distance disign rule control for LOCOS, SILO/RTN and SUPERSILO Junctions and cate oxide integrity:junction leakage at 1OV/-10V and avalanche breakdown are given, for N+/P-well and P+/N-well in Tablel for 16cm perimeter and 160000[Lm2 surface diodes. Figure 12 shows gate oxide breakdown field distribution for a population of 750 tested capacitors. We can see that the RTN and planarization process steps are compatible with larger than 10MV/cm breakdown fields. LEAKAGE
BREAKDOWN
N+/P
< 10 pA/cm
13.5 V
P+/N
< 20 pA/cm
14 V
TABLE: N+/P AND P+/N breakdown (at 100nA)
junction leakage (measured at 10V and avalanche
I0
12.0
10.0 4
8
12
Ebd MV /cm
Figure 12: Cumulated failures of gate oxide breakdown field(Tox = 17 nm) 24
The SUPERSILO process has been applied to the manufacturing of 0.8tim design rules CMOS 16K SRAM. Address access time of 9 ns is obtained at 4.5V with an active current of 45 mA and a stand-by current less than 10nA at 5.5V.
CONCLUSION A SILO/RTN process has been used in order to obtain a bird's beak free field oxide. A quasi-recessed field oxide has been achieved by subsequent deposition, oxidation and etch-back steps. By optimization of the masking layer thicknesses a 80 nm bird's beak length, with 800 angle, for lIm as-grown field oxide , can be achieved with a 70% planarization ratio. Double level metal CMOS have been characterized and good parametric results have been demonstrated on active and field devices. Because of the high planarization level of the field process, high improvement of contact to active edge distance is obtained as respect to SILO/RTN and strandard LOCOS. High density CMOS devices have been processed with low standby current. REFERENCES [1] P. Molle, S. Deleonibus and F. Martin, Journal of the Electrochem. Soc., to be published [2] S. Deleonibus, P. Molle, J. Lajzerowicz, B. Guillaumot, Ph. Laporte and A. Bergemont, ESSDERC'89, 1989 [3] A. Bergemont, S. Deleonibus, G. Guegan, B. Guillaumot, M. Laurens, F. Martin, Proceedings IEDM'89, Washington, Dec 1989, pp. 591-594 [4] S. Deleonibus, C. Arena, M. Heitzmann, J. Lajzerowicz, F. Martin and F. Vinet, proceedings VMIC'89, Santa Clara, June 1989, p. 507. [5] S. Deleonibus, P. Molle , L. Tosti and M.C. Tacussel, Journal of the Electrochem. Soc., to be published. [6] K. Y. Chui et al. IEEE Trans. on Electron Devices, Vol E.D. 2, n0 4, 1982.
25
ADVANCED PROCESSES TO INCREASE THE EFFECTIVE STORAGE AREA OF STACKED DRAM CELLS P.C. Fazan, H.C. Chan, Y.C. Liu, A. Ditali, C.H. Dennison, H.E. Rhodes, V. Mathews, and T.A. Lowrey
Micron Technology Inc., 2805 E. Columbia Road Boise, ID 83706-9698
ABSTRACT STacked Capacitor (STC) cells have been widely studied for high density Dynamic Random Access Memories (DRAMs) because of their high cell capacitance and simple process flow. Advanced STC structures are needed to achieve the cell capacitance required for 64 Mbit DRAMs and beyond. In this paper we introduce a new threedimensional STC cell, named the Stacked-V Cell (SVC). By taking advantage of the bottom side of the polysilicon storage node, the SVC can attain up to 70% more capacitance than the standard STC without degrading device reliability. No extra masking steps are required. The SVC integrates a fully self-aligned storage node contact. It does not require the storage node to precisely overlap the node contact, and does not add topography. The SVC is a very promising structure for the manufacture of 64 Mbit DRAMs. INTRODUCTION The development of multimegabit Dynamic Random Access Memories (DRAMs) requires the use of three-dimensional (3D) storage capacitors to maintain a sufficiently high stored charge on a small restricted cell area. Commercially available 4 Mbit DRAMs are manufactured with both stacked and trench storage structures, but STacked Capacitor (STC) cells with a storage node over the bit line appear to be the structures of choice for high density DRAMs beyond 16 Mbit [1-3]. The major advantages of STC structures are their ease of fabrication, immunity against soft errors, and insensitivity to various leakage mechanisms. Advanced STC structures that have been introduced for 64 Mbit DRAMs include fins [4], double stacked [5], cylindrical stacked [2,6,7], spread stacked [8], box [9], ring [10], and double plate [11] stacked cells. However, these cell structures create a severe topography and add process complexity when compared to conventional STC designs. Some of these structures add as many as two extra masking steps, require additional layers to be deposited, or use contacts that are not self-aligned. Textured STacked Capacitors (TSTC) have recently been shown [12-16] to drastically reduce process complexity and topography while maintaining a high cell capacitance. In this paper we introduce a simple new 3D STC cell named the Stacked-V Cell (SVC) that does not add topography. It utilizes the bottom side of the polysilicon storage node to achieve up to 70% more capacitance. We propose the SVC as a very promising storage structure for 64 Mbit DRAMs. 26
CONCEPT OF THE V-CAPACITOR STRUCTURE Figures 1 and 2 depict schematic views of the fabrication process used for standard [1] and V-capacitor structures. For the V-shaped structure, the storage node is formed by a thin polysilicon membrane. A thin Oxidized/Nitride (O/N) dielectric and the top polysilicon plate completely surround the V. This structure uses both sides of the polysilicon storage node to considerably increase the amount of charge stored on a given cell area. The V-capacitor structure can be manufactured without additional photo masks while preserving fully self-aligned storage node contacts in both directions. This structure does not require the storage node to precisely overlap the node contact. Thus the Stacked-V Cell (SVC) structures, when compared to the structures mentioned earlier [4-11], allow the manufacture of a significantly smaller cell for a given photolithographic resolution. Additional layers are not required, and the only added process step is a wet etch. a) Storage Node,-, ,
Storage Node
b)
Conta
1
C
(
Figure 1: Schematic views of the standard buried bit line stacked capacitor during fabrication: a) top view, b) bit line formation and isolation dielectric deposition, c) self-aligned contact formation, d) poly storage electrode deposition and patterning, and e) O/N cell dielectric and poly plate deposition. This figure shows that the storage electrode does not need to overlap the storage node contact, which results in improved manufacturability.
27
a)
Contact
Undercut Edge
Gained A~rea Undercut dg C
t Figure 2: Schematicviewsof V-capacitors during fabrication: a) top
view, b) bit line formation and isolation/sacrificial dielectric deposition, c) self-aligned contact formation, d) poly storage electrode
deposition and patterning, e) sacrificial dielectric wet etching, and f) O/N storage dielectric and poly plate deposition. This figure illustrates that the storage electrode does not need to overlap the
storage node contact, which results inimproved manufacturability. FABRICATION AND CHARACTERIZATION SVC structures are built with a 4 Mbit DRAM process technology that includes a buried bit line with a total of four polysilicon layers. Figures 3-5 show SEM views of a V-capacitor during and after fabrication. A 150-nm thick sacrificial dielectric film is deposited by LPCVD after bit line definition and bit line spacer formation. Oxide (nitride) is used when the insulator covering the bit line is nitride (oxide), so the sacrificial layer can be selectively etched away later. Next, a self-aligned storage node contact is formed. Then the bottom capacitor electrode, consisting of a 100nm thick LPCVD polysilicon film, is deposited at 620 0C, doped by phosphorus diffusion at 8600C, and dry etched to form the storage nodes as in standard structures. The sacrificial dielectric (oxide in this work) is then partially wet etched to form a thin polysilicon storage membrane (Figure 2e and 4). Next, a 10-nm thick Si3N4 layer is deposited by LPCVD at 7800C and slightly oxidized by a wet oxidation process at 28
9070C to form a highly reliable O/N composite storage dielectric [3,17]. The oxidation conditions used grow a 20-nm thick SiO2 layer on bare control Si wafers. TEM analysis shows that this corresponds to a 2-3-nm thick SiO 2 layer on top of the Si3 N film. Finally, the top 200-nm thick polysilicon electrode is deposited at 6200 C, doped by phosphorus diffusion at 8800C, and patterened by wet etching to form the top capacitor plates (Figures 2f and 5).
Figure 3: Top-down SEM picture of V-capacitors afterthe sacrificial dielectric etch during fabrication.
Figure 4: Bird's-eye SEM view of V-capacitors after an eight minute sacrificial dielectric etch in an 8:(5:1) DI H20: (NH4 F: HF) solution.
29
GOULD INC.
Figure 5: SEM cross section of a final V-capacitor. The dielectric etch time in this sample was 15 minutes.
Capacitance-voltage (C-V) measurements are used to determine the relative capacitance as a function of the sacrificial dielectric etch time. Ramped currentvoltage (I-V) curves are used to measure the devices leakage current and their destructive breakdown voltage distribution. Constant voltage time dependent dielectric breakdown (TDDB) measurements performed on simplified sub-array structures are used to determine capacitor lifetime at high electric field. All these measurements are performed at room temperature on simplified sub-array structures with an area of 0.005mm 2. The I-V and TDDB data are obtained by applying a positive voltage on the top capacitor electrode. RESULTS Figure 6 illustrates the measured relative cell capacitance as a function of the sacrificial dielectric etch time (oxide in this case). An 8:(5:1) DI H20:(NH4 F:HF) solution is used in this work. The capacitance saturation observed for etch times exceeding ten minutes can be explained by the insufficient phosphorous diffusion to the backside of the polysilicon top plate that forms the V-shaped structure. Nevertheless, a 45% increase in cell capacitance can easily be achieved. Calculations show that a 70% increase in capacitance can be expected if the backside of the storage polysilicon membrane is efficiently processed. This can be achieved by the addition of an anneal step (no reflow step has been used in this study), or by depositing an insitu doped polysilicon top electrode. 30
15 1.4 CL
1.3 CU
12 1.1 1.0
0
5
15
10
Etch Time (min)
Figure 6: Relative capacitance as a function of sacrificial oxide etch time in a 8:(5:1) DI H20:(NHF:HF) solution.
Figure 7 shows typical positive I-V characteristics for the same test structures as in Figure 6. Only a slight increase in leakage current is observed at high voltage. The same trends are observed for negative bias applied on the top polysilicon plate. 1E-03
1E-06 C
a) n
0
1 E-09
1E-12 0
3
6
9
12
Voltage (V) Figure 7: I-V characteristics of control and V-capacitors with the sacrificial dielectric etched for different times in a 8:(5:1) DI H20:(NHF:HF) solution.
The destructive breakdown voltage distributions of control and V-capacitors are shown in Figure 8 for a positive bias applied on the top polysilicon plate. A very uniform breakdown is observed for both groups. 31
100.
80 ,
a)
b)
i(
V-Capacitor (15-min etch) 251C Positive Stress
60 40. 20'
0-
0
5
Voltage (V)
10
15
Voltage (V)
Figure 8: Destructive breakdown voltage distributions for a) control, and b) V-capacitors.
When compared to control samples, the breakdown voltage distribution of the V-capacitors is shifted slightly towards lower values. This corresponds to the shift of the I-V curves observed in Figure 7 and could be due to a slight cell dielectric thinning on the backside of the V structure, or to the capacitor area increase. TDDB is measured by stressing the capacitors with a constant positive voltage on the top plate. The time to 50% failure (T.0) extracted from cumulative percent failure versus stress time plots is presented in Figure 9 for control and V-capacitors. There is no drastic reduction in capacitor reliability. All structures have a T.,value higher than 1000 years when extrapolated to operating conditions. 25^
251C Positive Stress .0-
15 min.
Control ••m
-- 2.0-
C)
8mn
LO
"ý" 1.0E
A
i-
'
0.0 8.0
9.0
10.0
11.0
Voltage (V) Figure 9: Mean time to breakdown To versus stress bias for control and V-capacitors etched for different times in a 8:(5:1) DI H20:(NH 4F:HF) solution.
32
CONCLUSION This paper introduces a simple new 3D stacked capacitor structure named the Stacked-V Cell (SVC) that does not add topography or process complexity when compared to standard structures. The SVC structures can attain up to 70% more capacitance than the standard STacked Capacitor (STC) structures by utilizing the bottom side of the polysilicon
storage node. Electrical measurements show this capacitance increase can be achieved without degrading device reliability. The Stacked-V Cell capacitor is a very promising storage structure for 64 Mbit DRAMs. ACKNOWLEDGMENTS The authors would like to thank Paul Paduano, Brian Benard, David Becker, and Brett Rolfson for preparation of the samples; Danny Young for the SEM analysis; and Brenda Jameson and Larry Cromar for the preparation of this manuscript. REFERENCES [1] S. Kimura et al., IEEE Trans. Electron Devices ED-37, 737 (1990). [2] F. Kawamoto et al., Symp. on VLSI Tech., 13 (1990). [3] P.C. Fazan et al., Ext. Abst. Electrochem. Soc. Meeting 90-2, 453 (1990). [4] T. Ema et al., IEDM Tech. Dig., 592 (1988). [5] T. Kisu et al., Ext. Abst. 20th SSDM, 581 (1988). [6] W. Wakamiya et al., Symp. on VLSI Tech., 69 (1989). [7] T. Kure et al., IEEE Trans. Electron Devices ED-38, 255 (1991). [8] S. Inoue et al., IEDM Tech. Dig., 31 (1989). [9] S. Inoue et al., Ext. Abst. 21th SSDM, 141 (1989). [10] N. Shinmura et al., Ext. Abst. 22nd SSDM, 833 (1990). [11] H. Adma et al., IEDM Tech. Dig., 651 (1990). [12] P.C. Fazan et al., IEEE Electron Device Lett. EDL-1 1, 279 (1990). [13] M. Sakao et al., IEDM Tech. Dig., 655 (1990). [14] M. Yoshimaru et al., IEDM Tech. Dig., 659 (1990). [15] P.C. Fazan et al., IEDM Tech. Dig., 663 (1990). [16] Y. Hayashide et al., Jap. J. Apple. Phys. 12, L2345 (1990). [17] Y. Ohji et al., Int. Rel. Phys. Symp., 55 (1987).
33
POINT DEFECT BASED MODELING OF DOPANT DIFFUSION IN SILICON Mark E. Law University of Florida, 339 Larsen Hall, Gainesville, FL 32611 Physically based models of dopant diffusion are necessary for predictive simulation in multiple dimensions. Most advanced diffusion models are based on point-defectdopant interactions. There has been a large amount of work performed on the theory of these interactions, but relatively less work has been done on parameterization. For predictive simulation, a consistent set of parameters must be developed and applied to various process conditions, including oxidation and implantation damage. The prospects of developing a consistent set of parameters will be described.
INTRODUCTION Accurate predictive process simulation is difficult, because technology changes so rapidly. Submicron devices demand two-, if not three-, dimensional simulations to predict the device dimensions near corners and mask edges. A key portion of this job is predicting the doping profiles both vertically and laterally near mask edges. To perform predictive process simulation in multiple dimensions, it is necessary to have physically based accurate models that can be extended for new technologies and combinations of technologies. There has been considerable work [1-5] on the theory of dopant diffusion in silicon. These theories have used interactions of dopants with point defects, vacancies and interstitials, to explain dopant diffusion. For predictive modeling, as well for comparing of the various theoretical treatments, it is necessary to extract parameters for the defect models from simple experiments. The models and parameters should then be tested in different conditions to verify their global applicability.
POINT DEFECTr. DOPANT THEORY Mathiot and Pfister [1] derived the equations for defects and impurities by assuming that impurities diffuse only through interaction with point defects. Recent work [5] has extended this treatment to more directly account for the charge states of the defects and dopant-defect pairs, making two assumptions: (1) the donor impurity diffuses only when it is associated with a defect, and (2) the pairs and individual species are in local equilibrium with each other. The last assumption requires that the chemical reactions forming pairs are fast compared to the other processes, and that transients in the formation of these pairs can be neglected. It is 34
difficult to establish the accuracy of the latter assumption except by comparison to short annealing-time experiments to determine if the transient is required. The continuity equation for a donor which only diffuses through an interstitial mechanism can be written: DCA = V
D*CI CVlog{•_CJnl]
(1)
where C is the concentration, and the subscripts A, A+, I, I* refer to the total donors, substitutional donors, interstitials, and equilibrium interstitials, D* is the concentration dependent diffusivity, and n / ni is the electron concentration divided by the intrinsic carrier concentration. It is important to remember that CI* is a function of both temperature and the Fermi level. The equations for acceptors or dopants which diffuse via a vacancy mechanism can be written in a similar fashion. The interstitial continuity equation can be derived using the same assumptions as used in the derivation of the dopant equation: t(CI+CAI) = V{DICI at ~
V
+ JIl - R
(2)
CI
where JAI is the sum of all dopant-interstitial fluxes and R is the sum of the various recombination terms. In general R would have to include interstitial interaction with vacancies, as well as interaction with extended substrate defects (stacking faults) and precipitates. Because parameters are not available for all the possible terms, R usually just includes a simple interstitial-vacancy recombination term as well as a trap term [6]. The vacancy equation is similar. The theory of dopant diffusion has been developed and applied to several different problems, including phosphorus kink and tail. However, a consistent parameter set for the equations does not exist. For example, oxidation experiments [6, 7] are best fit by an interstitial diffusivity several orders of magnitude lower than that found in gettering experiments [8-10]. The remainder of this paper addresses the need of an appropriate parameter set for dopant and defect equations. OXIDATION EXPERIMENTS AND MODELS Oxidation of silicon is known to produce silicon interstitials and enhance dopant diffusion, and is therefore a good tool for extracting defect parameters. Experiments which make use of lightly doped marker layers simplify Equations 1 and 2 by eliminating the uncertainities in the Fermi level and electric field effects. This simplifies the parameter space considerably and provides a reference for which experiments and modeling in other doping regimes must agree. The surface boundary conditions must also be analyzed. The boundary conditions for interstitials are [11]:
35
DIVC 1 - KI(CI-CI) =
(3 (3)
where KI is the surface recombination velocity, and g, is the injection flux. The interstitial injection flux, gI, can be written [111: g1 = VoxeVm
(4)
where Vox is the oxide growth velocity, Vm is the lattice concentration of silicon, 5.1022 cm- 3 , and 0 is the percentage of consumed silicon lattice atoms that are reinjected into the crystal as interstitials. The surface recombination velocity, KI, also can depend on the surface growth rate. Obviously, the kinetics at growing and inert surfaces should not be expected to be the same. An empirical relationship for surface recombination is used [12]: K,
= Kimax(laf + Kimin v~
(5)
where VAx is the initial oxide growth velocity for a bare silicon wafer, KImax is the surface recombination velocity maximum at a growing interface, Kimin is the velocity at the inert interface, and (xI is the decay dependence. The boundary conditions for the vacancies are similar, except that gv is zero. Using a large variety of experimental data from gettering measurements [8-10], oxidation studies of phosphorus [6, 7, 13-15], membrane experiments [7], lateral oxidation enhancement studies [6], and oxidation retarded diffusion studies of antimony [13, 16-18] parameters for the equations 1-5 were extracted [12]. This extraction procedure assumed the interstitial diffusivity and equilibrium concentration were given by the gettering studies of Boit [10]. The vacancy-diffusivity equilibrium concentration product used the estimate of Tan [9]. The rest of the parameters were extracted from optimization of simulation results in comparison to experimental data. Table 1 shows the parameters that result from the optimization procedure. In general, the parameters are more accurate at higher temperatures due to the abundance of data at 1100'C. Because there is less data at lower temperatures, the parameters are less reliable in that temperature range. The trap reaction rate, KT, is assumed to be diffusion limited. The bulk recombination rate between interstitials and vacancies, KR, was extracted at 1100'C and then extended to other temperatures assuming it was diffusion limited with a barrier to recombination of 0.77eV.
36
Preexponential 2
Activation
Preexponential
Activation
1.03.106 cm /s
3.22eV
Kimin
1.204.10-3 Cm/s
0.44eV
3
1.58eV
KImax
8.18.105 cm/s
1.95eV
Dv
6.34.103 cm /s
3.29eV
(I
0.91
0.051eV
CV*
4.77.1018 cm- 3
0.71eV
O
1.97
0.55eV
3.99eV
KVmin
1.12.104 cm/s
2.48eV
CET* 4.77-1023 cma
1.57eV
KVmax
2.93.1016 cm/s
5.36eV
6
3.22eV
cav
1.79.10-7
-1.91eV
DI CI*
KR
3.11.1019 cm2
6
1.40 cm /s 3
KT
1.10.10-2 cm /s
Table 1 - Parameters for Oxidation Enhanced Diffusion of intrinsic layers Figure 1 shows the result of SUPREM-IV [19] simulations of oxidation-enhanced diffusion at 1100'C as well as experimental results from various researchers. An important result is indicated on Figure 1. The initial oxide thickness is a critical unknown in modeling oxidationenhanced diffusion at short times. Because vox is a parameter in the
5
ý
, , ý , '
I
I
III II
I
I
I
t
-
151 4.5 61
4 .
ion
3.5 --
3 2.5 2 1.5 I
-I 1
I
10
WHIP1
I
1000 100 Time in Minutes
V
104
Figure 1 - Enhancement of Phosphorus during dry oxidation at 1100'C 37
surface recombination and injection terms, the resulting interstitial supersaturation is very different for initial oxides of different thicknesses. This may help explain discrepancies in the results of oxidation-enhanced diffusion experiments from different sources. Figure 2 compares the simulation result with the membrane experiments of Ahn [7]. In these experiments, Ahn oxidized one surface of
5 4.5 4 3.5 U-
3 2.5 2 1.5 1
1
10
100 1000 Time in Minutes Figure 2 - Interstitial Supersaturation at the side opposite the oxidizing edge of a membrane. a membrane and measured the enhancement of phosphorus diffusivity on the other side. This experiment is a good test of the interstitial diffusivity because it allows the measurement of the delay between oxidation injection on one side and enhancement on the other side. This figure indicates that the traps are effective in slowing the effective rate of interstitial diffusion. The simulations used a diffusivity from a gettering experiment [10] which was several orders of magnitude larger than that estimated by Ahn. Figure 3 shows the result for two-dimensional experiments. Griffin [6] calculated the lateral decay length of interstitials by examining enhancement under a variety of widths of pad oxides. Also shown are the simulated results using the parameters in Table 1. These experiments are especially sensitive to the surface recombination velocity which controls the lateral decay length of the defect profile.
38
25
:=L
.m
4
I
hi
hr
1
I
[In
I
I
20 15 900oC
S10
0
5
Simulation 0
n3 0
I
10
Griffin [61 I
II I
I
I
I
I
I'1I
I
1000
100
I
I
104
Time in Minutes Figure 3 - Lateral decay length of the interstitial supersaturation. DIFFUSION ENHANCEMENTS BY IMPLANTATION-DAMAGE Implantation damage creates point and extended defects. The point defects can enhance dopant diffusion, and lead to anomalous behavior. The difficulty in modeling implantation damage enhancement is caused by the many separate effects that occur, including solid phase epitaxial regrowth, extended defect annealing and growth, as well as dopant precipitation and clustering, and high concentration and electric field effects. Recent experimental work [20, 21] has investigated the effect of low dose Si implants on lightly doped marker layers. These experiments indicate that boron and phosphorus experience large diffusivity enhancements. Figure 4 shows the enhancement of phosphorus difusivity as a function of temperature and time for a 1.0.10 14 /cm 2 silicon implant. This type of experiment simplifies the modeling by eliminating extended defects, solid phase epitaxial regrowth, and high concentration effects. The challenge for modeling lays in modeling the point defects which are created by implantation self-consistently with those created by oxidation. There are, however, substantial difficulties in modeling these results. First, the initial defect profile must be known. There is no way to directly measure the profiles of point defects. However, there are several ways to calculate the profiles [22-24]. Unfortunately, even for the simple experiment described above, the point-defect concentrations can differ by an order of magnitude. A second problem is that a simple application of 39
10 3
1 02
1 0.1
1
T0 Time (min)
102
Figure 4 - Phosphorus Damage Enhancement After a Silicon Implant Equations 1-5 and the parameters in Table 4.1 predicts substantially more diffusion enhancement than is actually seen. The key to modeling the phosphorus diffusivity enhancement shown in Figure 4 is to consider the total number of dopant defect pairs. Dopantdefect pairs are formed through the reaction: A+ X "AX
(6)
where A is the dopant species and X is the defect, either a charged interstitial or vacancy. In the derivation of Equation 1, the reaction in Equation 6 was assumed to be at equilibrium. With the large excess of defects caused by implantation, it is necessary to use the total concentration of unpaired dopant in the left side of the reaction shown in Equation 6. During implantation-damage conditions, the dopant is almost entirely paired. This approach to modeling damage enhancement was first used by Packan and Griffin [25]. Park [26] used this approach to model phosphorus enhancement caused by silicon implant damage and extracted a binding energy of 1.35eV for the 800'C and 900'C anneals. This binding energy did yield good models of the higher-temperature annealing steps. The time decay of the transient-enhanced diffusion is modeled incorrectly for the higher temperature anneals which suggests that there is a mechanism that is not accounted for. In particular, the enhancement last for too long a time period and predicts a larger enhancement than is actually measured. 40
CHALLENGES There are several remaining challenges to predictive modeling of The first is the determination of the effects of high dopant diffusion. concentrations of dopants on defects and the dopant-defect pairs. Miyake [27, 28] demonstrated that the enhancement of boron diffusivity during oxidation is a strong function of the Fermi level. This indicates that interstitials may have charge states similar to vacancies [29]; This may account for differences in the oxidation-enhanced diffusion. Second, for higher implant doses extended defects begin to play an important role. It is not clear how they affect diffusion of dopant or defects. Kim [30] concluded that the extended defects were important for high concentration boron diffusion. Further work must be performed to investigate the role of extended defects on dopant diffusion. Finally, new computational techniques must be investigated. The computer time required to compute the most advanced dopant-defect models of diffusion is very large. Further investigation into time discretization, spatial discretization, and sparse linear-solution techniques must be done. Fortunately, since the device simulation equations are similar, much of this can be adapted from prior work on device simulations. CONCLUSIONS The effort to build physics-based models of dopant-defect interactions is well underway. There is a growing consensus on the equations and relationships that must be used. Progress is being made on characterizing the parameters for these new models. Oxidation enhanced and retarded diffusion is modeled in both one and two dimensions. The next major challenge will be to produce accurate models for interaction of dopants and defects, both point and extended, created from implantation damage. ACKNOWLEDGEMENTS I would like to acknowledge the support of the Florida SEMATECH Center of Excellence. I would also like to thank my students Jay John, Sung-Won Ko, Chih-Chuan Lin, Paul Novell, and especially Heemyong Park for the work on damage modeling. Discussions with Paul Packan, Peter Griffin, and Jim Plummer have been most helpful. REFERENCES 1. D. Mathiot and J. C. Pfister, J. Apple. Phys., 55(10), p. 3518, (1984). 2. F. F. Morehead and R. F. Lever, Appl. Phys. Lett., 48(2), p. 151, (1986). 41
3. B. J. Mulvaney and W. B. Richardson, Appl. Phys. Lett., 51(18), p. 1439, (1987). 4. M. Orlowski, Appl. Phys. Lett., 53(14), p. 1323, (1988). 5. M. E. Law and J. R. Pfiester, IEEE Trans. on Elec. Dev., 38(2), p. 278, (1991). 6. P. B. Griffin and J. D. Plummer, International Electron Devices Meeting, Los Angeles, p. 522, 1986. 7. S. T. Ahn, P. B. Griffin, J. D. Shott, J. D. Plummer and W. A. Tiller, J. Apple. Phys., 62(12), p. 4745, (1987). 8. G. B. Bronner and J. D. Plummer, J. Apple. Phys., 61(12), p. 5286, (1987). 9. T. Y. Tan and U. Gbsele, J. Apple. Phys., 37(1), p. 1, (1985). 10. C. Boit, F. Lau and R. Sittig, Appl. Phys. A., 50, p. 197, (1990). 11. S. M. Hu, J. Apple. Phys., 57, p. 1069, (1985). 12. M. E. Law, IEEE Trans. on CAD., To be Published, Aug., (1991). 13. D. A. Antoniadis and I. Moskowitz, J. Appl. Phys., 53(10), p. 6788 - 6796, (1982). 14. K. Taniguchi, D. A. Antoniadis and Y. Matsushita, Appl. Phys. Lett., 42(11), p. 961, (1983). 15. P. A. Packan and J. D. Plummer, J. Apple. Phys., 68(8), (1990). 16. S. Mizuo and H. Higuchi, Jpn. J. Apple. Phys., 20, p. 739, (1981). 17. E. Guerrero, W. Jungling, H. Potzl, U. Gosele, L. Mader, M. Grasserbauer and G. Stingeder, J. Electrochem. Soc., , p. 2182, (1986). 18. P. Packan, Private Communication. 19. M. E. Law, C. S. Rafferty and R. W. Dutton, 1988. 20. P. A. Packan and J. D. Plummer, Appl. Phys. Lett., 56, p. 1787, (1990). 21. H. Park and M. E. Law, Appl. Phys. Lett., 58(7), p. 732, (1991). 22. G. Hobler and S. Selberherr, IEEE Trans. on CAD., 7(2), p. 174, (1988). 23. T. L. Crandle, W. B. Richardson and B. J. Mulvaney, International Electron Devices Meeting, San Fransisco, 1988. 24. M. D. Giles, IEEE Trans. on CAD., 5(4), (1986). 25. P. B. Griffin and P. A. Packan, Private Communication. 26. H. Park, M.S. Thesis, University of Florida, 1991. 27. M. Miyake, J. Apple. Phys., 58(2), p. 711, (1985). 28. M. Miyake, J. Appl. Phys., 57(6), p. 1861, (1985). 29. M. D. Giles, IEEE Trans. on CAD., 8(4), p. 460, (1989). 30. Y. Kim, H. Z. Massoud and R. B. Fair, J. Electronic Materials., 18(2), p. 143, (1989).
42
SIMULATION OF ULSI DEVICE EFFECTS Mark R. Pinto AT&T Bell Laboratories, Murray Hill, New Jersey 07974 Device simulators are critical to the development of VLSI technology, yielding nearly optimization without costly, time-consuming experiments. As structures are scaled to ULSI dimensions, the corresponding technical complexity and new physical operating regimes necessitate more advanced analytical treatment. This paper describes critical ULSI-scale device effects and outlines requirements to achieve predictive simulation into the deep submicron regime. INTRODUCTION Device simulation has become an essential component of the VLSI technology development process [1]. The use of fundamental physical models, e.g. Boltzmann-based carrier transport, together with sophisticated numerical techniques has yielded predictive tools which provide critical insight into device scaling as well as novel operational phenomena and structural concepts. The enormous costs associated with fabrication together with the ever aggressive schedules for higher performance systems further exaggerates the need for such physicallybased models in the future. However scaling into the ULSI regime (<0.25ptm) necessitates the treatment of several new classes of effects in order to achieve desired functionality and predictivity. It is clear that simulation must also interface more directly into the manufacturing environment. As part of an overall technology CAD (TCAD) system, device simulators have already been demonstrated to improve transistor performance of real technology through design centering and optimization [2]. To achieve these results however, a simulator must be run many times without manual intervention, thus placing even stricter demands on accuracy, automation, turnaround and robustness. Given that actual simulation capability must also be extended as discussed below, optimization thereby magnifies the challenges device simulation faces in ULSI regimes. At 0.51.tn levels of integration, practical device simulation tools are almost universally based on partial differential equation (PDE) formulations, most notably the drift-diffusion (DD) system [3]. PDE-based approaches have numerous advantages including their accuracy (physical and numerical), flexibility, computational efficiency and robustness, as well as their ability to obtain smooth terminal characteristics and accurate small-signal response. As a result, what follows is an attempt to extend PDE-based approaches to treat ULSI device effects with the goal of maintaining physically-based models, applicable to general (nonplanar)
43
geometries, which can effectively treat multiple carrier species under arbitrary bias and make maximum use of vectorization/parallelism. Three classes of challenges are considered - extrinsic device effects, enhanced physical models and 3D simulation - based on results obtained from the internal AT&T device simulator PADRE. EXTRINSIC DEVICE EFFECTS Figure 1 illustrates a cross section of an inverter in a small-geometry CMOS technology. Until recently, device simulation focused on intrinsic elements, e.g. the nMOSFET. To achieve the highest performance, it becomes increasingly necessary to optimize extrinsic elements - i.e., the outlined trench isolation. These structures are typically large and highly nonplanar with potentially complex modes of operation that cannot be fit or simplified. The trend towards such structures may continue to a point where it is difficult to even distinguish between intrinsic and extrinsic elements.
S
Figure 1
I I
Inverter cross-section in a scaled CMOS technology.
The latchup phenomenon in CMOS is an excellent example of an extrinsic effect. In order to minimize the distance between FETs, simulation can play a critical role in studying tradeoffs between performance and process complexity. Using sophisticated curve tracing algorithms and adaptive grid generation [4,5], triggering and holding points can be quickly and accurately estimated thereby permitting reliable process and design rules assessments a priori. By reducing numerical interaction to the setting of simple error tolerances, the latchup simulation procedure is completely automatic and is thus suitable for optimization systems. As examples, figure 2 shows results of different types of latchup simulations in a twin-tub CMOS technology. Figure 2a shows a full response map for a trigger current as a function of the spacings of both the n- and p-channel
44
transistors to the tub boundaries. A strong asymmetric dependence is detected (note the logarithmic scale) which can have a significant impact on the selection of design rules. Figure 2b shows the holding voltage as a function of the total NMOS-to-PMOS spacing (varied symmetrically) for different thicknesses of epi material on a low resistivity substrate. From plots such as this, tradeoffs in cost and performance can be fully analyzed without requiring time consuming, split-lot experiments. 6.0 0 t.-a" -0
5.0
-t
4.0 3.0 2.0 1.0 0.0 0-=. 5m
Figure 2
..
.0 7
. . .. . . 11.0 13.0~ 1=.0 p* to n* spadng (ýtm)
.0 9'
. 1 l.U
Simulated trigger currents and holding voltages for CMOS latchup cross-sections as a function of NMOS-PMOS spacings and different epitaxial layer thicknesses.
One of the difficulties in performing latchup simulations - the need to generate efficient grids - is clearly demonstrated by figure 3 which shows the electrostatic potential distribution in a trench CMOS cross-section at two different bias conditions during a dc triggering simulation [5]. In the off-state (no current between neighboring n+ and p+ source/drains), there is a large potential barrier between the well and substrate which must be resolved by the grid. However at conditions where significant currents are flowing, the barrier first pushes out due to the Kirk effect and then is greatly reduced. A boundary layer exists between the heavily injected regions in the tub and the tub contact in the state shown due to the reverse bias (2V) between the source/drain and the well contact. By using reliable discretization error estimates, the grid can be locally refined and unrefined automatically, saving a tremendous amount of grid points while guaranteeing an accurate result.
45
F
Figure 3
Potential in a trench CM (a) off-state (b) latched state. ENHANCED PHYSICAL MODELS
There are a variety of new physical effects that must be accounted for in ULSI devices. Of particular relevance in small MOSFETs are hot carrier degradation and velocity overshoot which necessitate nonequilibrium treatments of carrier heating. Figure 4a shows simulations of the intrinsic cutoff frequency f, for small geometry nMOSFETs a T = 300K as a function of effective channel length, using the conventional DD model and two higher order transport models - energy transport (ET) and Monte Carlo (MC); PADRE was used to produce the DD and ET results while the MC simulations were performed by BEBOP [7]. The DD model limits the maximum channel velocity through a local velocity-field relation, whereas more complex nonequilibrium models properly exhibit velocity overshoot effects [6,7]. As a result, the MOSFET speed would be underestimated at Leff=O. 2 51.tm by 12% using the conventional DD model, while at Leff=O.l1 Wf the difference is over 25% for this structure. The ET model derives from considering an additional moment of the Boltzmann equation (the "hydrodynamic model") and then further assuming the energy to be directly proportional to carrier temperature [8]. Following [9], the ET system incorporates two PDEs for each carrier (as opposed to one for DD) of the form
n= 1 v.J-U at q V-S
=J'E-
(1)
3k Tn - To 2 =w
3 k a(n T) 2 at
(2)
where n is the carrier (electron) density, Tn is the local electron temperature, U is
46
the recombination rate and E is the electric field. The current density J and energy flux S are defined as J = qt [nE+A--V(nT)]
S
=-_.= 2 k qTn
25
(3)
cký
(4)
Tq
which includes a heat conduction term, evaluated by applying the WiedmannFranz law (the coefficient x is discussed briefly below), to account for higher order moment effects. By assigning proper carrier temperature dependencies to the mobility g and energy relaxation time r,, ET should be suitable for treating nonequilibrium effects such as velocity overshoot at only a small incremental cost over DD while preserving all other desirable properties using primarily the same numerical methodology. 20 3
PADREBEBOP
nMOSFETf, 0 0
WC E,
A
DD
80.0
•
80.0
Z
40.0
AS
0.0 0ý0
0.0
0.1 0.2 0.3 0.4 0.5 086 EFFECTIVECHANNELLENGTH(Wo,)
Figure 4
0.1
0.2
0.3 0.4 Distance (Wn)
0.5
0.6
Simulations of small MOSFETs using drift-diffusion (DD), energy transport (ET) and Monte Carlo (MC) models. Overshoot is noticeable at Lff< 0.25 nm. Excellent agreement is observed between MC and ET.
In contrast, the MC method can be viewed as a means to solve the Boltzmann equation directly without resorting to a finite number of moments or relaxation times. As such, MC is more fundamental than moment methods (DD and ET), allowing accurate computation of entire distribution functions not just average quantities (J, Tn, etc.). However, even implemented in a fully vector/parallel environment [7], MC is extremely expensive and yields results typically having nonnegligible statistical uncertainty. As such, MC is not viewed as a primary mode of analysis for ULSI device design and is used only when necessary, for instance to properly assign temperature dependencies to coefficients in
47
the ET model using homogeneous, resistive slabs [10]. The primary difficulty in applying the ET to silicon devices is in the selection of a proper heat coefficient K which can strongly affect the local solution in regions with abrupt energy/field transitions. For some devices, the optimal K can have both structural and bias condition dependencies, arising from nonMaxwellian carrier distributions which would be better treated by a two temperature ET model [10]. Fortunately however we have found that MOSFETs are relatively insensitive to this parameter, and excellent agreement can be achieved with MC for a number of different types of impurity profiles (including LDDs) using c=0.7. Figure 4 demonstrates the accuracy of ET by comparison to MC, both in terms of ac parameters (ft) and internal velocity/density profiles. Silicon-based bipolar technology in the ULSI realm also requires multidimensional analysis in order to accurately estimate critical parasitic components. Furthermore, to obtain performance increases commensurate with scaling linewidths, Sil-xGe, HBTs have been explored as a means of relieving critical scaling barriers of homojunction devices [11]. Figure 5 shows a comparison of simulated 2D homojunction and HBT characteristics with equivalent electrical base widths. The offset in the valence band of the npn is a function of the Ge fraction x in the base so that as x increases, the current gain improves and becomes less dependent on base doping. n+ implant
0.0
0.2
0.4
0.5
0.8
1.0
1.2
1.4
1.6
Vet, VCE(VOI:8)
Figure 5
A Sil-.Gex HET [11] simulated in 2D and compared to an equivalent electrical base-width homojunction silicon bipolar transistor.
In order to model the Sil-,Gex HBTs, simulators must be able to incorporate abrupt band offsets and accurate alloy parameterizations of model coefficients e.g. mobility, lifetime and band-gap narrowing. Even for strictly Si homojunction devices, there remain numerous uncertainties involving minority carrier transport especially in structures with polysilicon emitters. The situation is obviously more
48
complex for Sil-xGex devices as alloy (x) dependencies must be developed for all relevant parameters. Furthermore these parameters depend heavily on material quality, growth conditions and thicknesses. In fact, most Sit-xGex HBT results published to date do not achieve anywhere near the potential suggested by figure 5b, mainly due to poor lifetimes in the epitaxial materials and/or at interfaces; even as material quality improves, it will still be difficult to obtain accurate parameterizations due to the inherent differences between bulk material and the thin, strained layers required for transistor bases. Finally it should be noted that the full hydrodynamic model, rather than the electron temperature assumption made in deriving ET, may be required for ultra small HBTs, especially for material systems which produce significant offsets in the majority carrier band edge [12]. THREE-DIMENSIONAL SIMULATION The ULSI regime will also usher in the use of real 3D simulation as part of the technological design process. Through the 1980s, 2D device simulation has been the workhorse as most 3D effects of relevance (e.g., narrow width) have been weak and can usually be estimated as perturbations or with relatively unsophisticated 3D techniques. The need for real 3D capability - and hence the difficulty in the analysis - arises out of the accurate characterization of phenomena that are more inherently 3D, for instance distributed current flow, alpha particles or sidewall inversion. Figure 6 illustrates a challenging 3D effect related to CMOS latchup. 2D device simulators can only handle pnpn layouts where the four contacts are colinear whereas real circuit layouts maybe folded; see figure 6a. (Note however that the fact that contacts may be square and hence have edge effects is a much simpler effect and can be accounted for with in 2D using an appropriate series resistance [13]). As a result, the effects of emitter debiasing and field assisted transport which normally occur in the well [14] may be significantly reduced, leading to higher trigger currents. Figure 6b shows a contour plot of the (log) electron density at triggering where triggering was caused by holes injected into the p+ source/drain (lower left-hand comer corresponding to light square) in the n-substrate. The electron injection at the n+ source/drain (upper left-hand comer, corresponding to dark square) is preferential toward the side of the contact furthest from the p-tub contact (upper right-hand comer), demonstrating a clearly 3D current distribution for both electrons and holes. As a result, the trigger current as induced in the p+ source/drain is almost twice that of a corresponding 2D layout. A real 3D design tool requires new mathematical techniques in order to meet the same demands met by current state-of-the-art 2D device simulators. At present, the widespread use of 3D simulation is hampered by low throughput due
49
p
Figure 6
n
3D effects in CMOS latchup (a) 2D (top) and 3D (bottom) layouts of CMOS structures (b) electron concentration contours (log scale, dark=high) for the 3D layout near triggering.
primarily to unadequate numerical algorithms. One major problem arises in the discretization of the device equations in 3D and the associated grid. Due to stability problems involving the continuity equation for elements with large angles, general tetrahedral generation is not currently possible unless generally applicable discretization techniques are concurrently developed. The alternative has been to use more restrictive element types (e.g. prisms or octrees) which consume substantially more points. A second problem which adversely affects throughput is the fact that direct solutions to the linear systems arising from the discretizations are not feasible, yet robust iterative solvers - particularly for vector/parallel environments - are not generally available due to the nature of the device PDEs, exaggerated by the typically poor grid aspect ratios required to model inversion layers for instance [10]. Clearly significantly more work in these areas, as well as in interfaces and visualization, will be required before 3D device simulation becomes routine. CONCLUSIONS ULSI-scale devices will require more sophisticated device simulation tools in order to address needs in primarily three areas: extrinsic phenomena, enhanced physical models and three-dimensional effects. From a physical standpoint, primary limitations at present would seem to exist in ULSI bipolar modeling and hot carrier degradation, although much of the difficulty stems from the lack of adequate experimental characterization of fundamental properties. Practical 3D simulation for general (particularly extrinsic) structures still faces algorithmic difficulties which reduce throughput or limit accuracy, making many exhaustive
50
studies infeasible. The primary limitation on the accuracy of device simulation in the ULSI regime however is expected to remain the same as at present: the lack of comprehensive and predictive process models. ACKNOWLEDGEMENTS The contributions of W. M. Coughran, Jr., C. A. King, C. S. Rafferty, E. Sangiorgi, R. K. Smith and F. Venturi to this work are gratefully acknowledged. REFERENCES R. W. Dutton and M. R. Pinto, Proc. IEEE, 74, 1730 (1986). K. Singhal, C. C. McAndrew, S. R. Nassif and V. Visvanathan, AT&T Tech. J., 68, 77 (1989). [3] W. van Roosbroeck, Bell Syst. Tech. J., 29, 560 (1950). [4] W. M. Coughran, Jr., M. R. Pinto and R. K. Smith, IEEE Trans. CAD of ICs, 7, 307 (1988). [5] W. M. Coughran, Jr., M. R. Pinto and R. K. Smith, IEEE Trans. CAD of ICs, to appear (1991). [6] G. A. Sai-Halasz, M. R. Wordeman, D. P. Kern, S. Rishton and E. Ganin, IEEE Electron Dev. Lett., 9, 464 (1988). [7] F. Venturi, R. K. Smith, E. Sangiorgi, M. R. Pinto and B. Riccb IEEE Trans. CAD of ICs, 8, 360 (1989). [8] K. Blotekjaer, IEEE Trans. Electron Dev., ED-17, 38 (1970). [9] R. Stratton, Phys. Rev., 126, 2002 (1962). [10] M. R. Pinto, W. M. Coughran, Jr., C. S. Rafferty, E. Sangiorgi and R. K. Smith, in Computational Electronics, K. Hess, J. Leburton and U. Ravaioli, eds., Kluwer, 3 (1990). [11] C. A. King, J. L. Hoyt and J. F. Gibbons, IEEE Trans. Electron Dev., 36, 2093 (1989). [12] Y. K. Chen, A. F. J. Levi, R. N. Nottenburg, P. H. Beton and M. B. Panish, Appl. Phys. Lett., 17, 1789 (1989). [13] I. Getreu, Modeling the Bipolar Transistor,Tektronix (1979). [14] M. R. Pinto and R. W. Dutton, IEEE Electron Dev. Lett., EDL-6, 100 (1985). [1] [2]
51
NON-EQUILIBRIUM DIFFUSION PROCESS MODELING BASED ON THREE-DIMENSIONAL REGULATED POINT-DEFECT INJECTION AND IN-SITU TEM OBSERVATION T.K.Okada, S.Onga, H.Kawaguchi, S.Kambayashi, I.Mizushima, J.Matsunaga, and K.Yamabe ULSI Research Center, Toshiba Corporation Kawasaki, 210 Japan Three new sophisticated experiments have been conducted for precise estimation of Si interstitial and vacancy diffusion coefficients and to understand quantitatively kinetics of impurity diffusion. The first is impurity profile monitoring under well-regulated injection flux of point defects in three-dimensional spaces. The second is in-situ TEM regrowth observation of damaged region caused by ion implantation, and the third is silicidation examination for checking of type of point defects. A prototype precise diffusion model of point defects and impurity atoms has been also proposed. Moreover, details of a three-dimensional process simulator which has been used for analysis and better understanding of experimental results has been also presented. INTRODUCTION Process simulation systems continue to be developed which can predict impurity redistributions in conjunction with final device structures, in advance of process operations[1-4]. Many improvements have been made in each individual process simulator, for instance, imprementation of point-defect diffusion model, renewing of impurity redistribution modeling, registration of exact segregation coefficients, etc.,J5,6]. However, more attention should be paid for to process model or process parameters than before, otherwise they could have less margin in definite requirements and/or could alter completely device characteristics. On this view point, three new sophisticated experiments have been conducted for precise estimation of Si interstitial and vacancy diffusion coefficients and to understand quantitatively kinetics of impurity diffusion: The first is impurity profile monitoring under well-regulated injection flux of point-defects in three-dimensional space, the second is in-situ TEM regfowth observation of damaged region caused by ion implantation, and the third is silicidation examination for checking of type of point-defects. In this paper, a prototype precise diffusion model of point defect and impurity atom has been proposed, moreover detailes of three-dimensional process simulator which have been used for analysis and better-understanding of experimental resuls has been also presented. EXPERIMENTS AND CAD TOOL Impurity Redistribution under Injection of Point-Defect We have conducted experiments for precise estimation of impurity diffusivity as a function of point-defect concentration and also have conducted for measurements of both interstitial and vacancy diffusion coefficients. Figure 1 shows a general concept of
52
T
Y ... ...
V
..
00 deofec Poonfl Si epi.
layer
8 doped layer
0
0
n-Si sub. 1
nf
onnmnle
trenorrl elnrent "lhi-1 A structure for diffusion examination under non-equilibrium condition.
Fig.2 Typical plain view of diffusion mask of PSG films.
a sample structure. The test samples were fabricated on N-type 9-11 Qcm (100) silicon substrates. Boron ion-implantation were carried out with acceleration voltage of 40 keV and a dose of lx1014 /cm 2. Low-temperature silicon epitaxial films were made on the substrates at 900 'C for formation of boron-buried monitor regions. The film thicknesses ranged from 4.5 gtm to 10 .tm. After Si 3N4 and SiO 2 film depositions with patters of various size of window areas, PSG films were deposited as sources of point-defect injections. The buried regions were studied for various concentrations of point-defects in non-equilibrium process conditions. Figure 2 shows a typical plain view of diffusion mask of PSG films, in which shadowed regions are injection area of point-defects. The adoption of epitaxial process made boron monitor regions deeply underneath the substrate and could eliminate surface recombination effects of interstitials. Silicidation for Checking of Point-Defect Type PSG flames were used for sources of interstitial injection. Redistributions of boron buried layers were measured as functions of interstitial concentrations as mentioned in the previous section. In this section, we conducted to make sure which one of the point-defects affect the redistribution of boron impurity. A Ni silicidation process was picked for checking of the type of point defects. The test samples were fabricated on P-type 9-11 i2cm (100) silicon substrates. Boron and arsenic ion-implantations were carried out on each individual region with the same acceleration voltage of 40 keV and a dose of 8xl0 15 /cm 2 . Ni films were deposited on the implanted layers. After formation of silicidation at 850 'C and 1 hour, impurity profile changes were checked by SIMS data. In-Situ TEM Observation During annealing after ion implantation of impurities, point-defects are injected from the damaged region into the silicon substrate in conjunction with regrowth the amorphous region. The quantitative understanding for kinetics of impurity diffusion
53
caused oy interstuals was conducted as described above. In this section, the precise growth-rate was examined using a direct in-situ TEM observation. An experimental set-up for in-situ TEM observation is shown in Fig. 3. 2000 A polycrystalline silicon films were deposited on silicon wafers covered with thermally grown SiO 2 layers. Amorphous silicon film were made by silicon ion-implantation with a series conditions of 2.5xl0t 5 /cm 2 at Du Kev and 5.Axlvu /cm at L20 keV. Regrowth characteristics were studied in real time at 550-7500 C using a VTR systems.
Fig.3 An experimental set-up for in-situ TEM observation.
Three-Dimensional Process Simulator A new three-dimensional process simulator was developed for analysis and better understandings of experimental results. The discretization scheme of the basic diffusion equation in the three-dimensional process simulator is described in an Appendix. In the impurity diffusion equation, the diffusivity(D) is defined to be D=Di
+ (l-F) C
F --
}
where Ceq is point defect concentration in equilibrium, Cv is the vacancy concentration, and C, is the interstitial concentration. Simulations with this model are compared to experiments to determine important parameters. The essential points of experiments mentioned should be the result in one dimensional junction depth Source on whole surface measurements under well-regulated S
injection flux of point-defects in
8-17.0'
three-dimensional space. Typical simulated results are illustrated in Fig.4 in which point-defects are clearly seen well-regulaied by a change of the diffusion source window area. Moreover, the concentration of point-defects can be understood to be unuformly distributed
-
around at a place of the monitor layer. After the estimation of precise diffusivities of interstitials and vacancies, these values are implemented the simulator. The final goal of this simulator is to predict precisely impurity redistributions in 1/4 .tm-level scaled devices,
:
1.0 x I.Oprm2 source 07-
•-eoN
15Se-.
--
N
1,
N
_ 0
t ".
-0,00 4.00 8.00 X (MICRON)
N000
400 800 12.00160 20.00 X (MICRON)
Fig.4 Typical simulated results of point-defect concentration for two deferent source structure.
54
EXPERIMENTAL RESULTS AND DISCUSSION Non-Equilibrium Diffusion Experiments One of the typical experimental results is presented in Fig. 5 for various window sizes. Angle-lapped surfaces are shown in the figure after the annealing of 16 hours at 850 'C. PSG films have been deposited for the point defect injection sources. The beveled sample angle was 34'. Arrows indicate junctions of monitor regions. It sould be noticed that the junction depths decrease markedly with decreasing window area, reflecting
regulation
of
point-defect
Window area ratio
injection from the surface. Figure 6(a) and 6(b) show in-depth profiles of monitor regions underneath the substrates as a parameter of diffusion source area size.
/
/1.6
-
.
I I
I,' Pdm•y* P lam'
I
*
200#.
C/C• >> 1, as shown in Fig.7. Moreover, the Si interstitial diffusion coefficients calculated are plotted in Fig.8, compared with those values in literature which are distributed in depth elsewhere[7,8]. 00
0
1/4
1/9
.
From these results, point-defect
diffusivity(D), recombination rate(kR), impurity diffusion coefficient have been measured precisely in several temperatures ranged down to 750 'C adjusting coefficients in the three dimensional process simulator. Boron diffusivity has been first observed to be fairly proportional to the point defect concentra-
Fig.5 Angle-lapped surfaces after the annealing at 850 *C. Angle of beveled sample was 34'. Arrows indicate junctions of monitor regions.
000.5,0, mAr mo(b)
*X
t012
•
•
--
'a.
•00
,I
1/5
1/49
~II 750% , Ar l
* U
51--
L
IolJ
6.0 101.
4.0
101,
/•.• •"•
c•2.0
010 '0 0
I 1
3 2 2345
4
5
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I(,.)
8 9 19
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II ;0 ;81112
M
O(3• fl tA
0.0
•
I
i
•
0.2
0.1
i
03
r
Fig.6 Impurity profile changes of monitor regions in 850 'C Ar anneal. (a) In-depth of buried layer underneath masking region (area size=0). (b) Indepth of buried layer underneath diffusion window area (area size=l).
Fig.7 Experimental result of boron diffusion coefficient as a function of diffusion source area "r".
55
T (*C) 110 120
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Boo
900
100
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Griffinet al.
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9 i04/T(K)
Fig.8
Silicon
diffusion
coefficient
obtained by the 3-D experiments.
Silicidation and In-Situ'TEM Experiments Ni silicidation experiments were conducted to
determine which one of the noint-defectg
inter~ti-
tial or vacancy, affect mainly to redistribution of ksntn
-uul
ninu4+y MtIIUlL•Y.
o
;A QJun*a1U; lk cat
-l
wasb
31 mi
15sec
tanlx _'; A k~,,t
etOUUL
at
850'C for 30 minites. It was found that there were no change in the boron junction depth before and after the silicidation process where Ni silicide was put on the doping layer. In contrast for the arsenic, there was quite large change of arsenic junction depth where Ni silicide was put on the doping layer. From these results, boron impurities can be concluded to be diffused with the help of interstitials. An in-situ TEM observation was used for estimation of temperature dependence of the regrowthl rate. Fore experimental convenience, a 32min 15sec seedless regrowth mode was adopted. Temperature has been observed by a calibrated thermocouple. The regrowth rate of amorphous region was Fig.9 VTR photographs at 600 0C. observed in real-time video. Figure 9 shows (Top) 30'15" regrowth. (Middle) observed VTR photographs as a function of 31'15" regrowth. (Bottom) 32'15". regrowth time. Using these photographs, the temperature dependence of the regrowth rate has been reploted as shown in fig. 10. These data are now compiled in the three-dimensional process simulator for future studies of scaled devices, such as a study of redistribution of implanted impurities taking into account of both injection of interstitials and the movement of the interface of the damaged region during regrowth.
56
R99rvWlh1barpture ('C) 640
.. 0
.0
630
620
610
590
600
0
-
0
1.09 1.10 1.11
12
1.13 1.14
1.15 1.16
103/T (K)
Fig.10 Regrowth rate as a various regrowth temperature using in-situ TEM observation. SUMMARY Non-equilibrium point-defect diffusion process modeling has been analyzed, based on new results supported with a three-dimensional process simulation system. Si interstitial and vacancy concentration have been sophisticatedly varied in an expanded region up to a non-equilibrium regime, and a prototype diffusion model of point defect and impurity atom has been proposed. ACKNOWLEDGMENTS The author are deeply indebted to Drs. Masahiro Kashiwagi and Kenji Natori who spent these several years sharing their insights into the field of process modeling. The author are also grateful for the epitaxial growth experiments by Mr. Saito. REFERENCES [1]
C.P.Ho, J.D.Plummer, S.E.Hansen and R.W.Dutton, IEEE trans. electron, devices, ED-30 no.11 (1983) 1438.
[2]
A.Gerodolle, S.Martin and A.Marroco, NASECODE4 p.287, Dublin(1985).
[3]
D.Collard and K.Taniguchi, IEEE trans. electron, devices, ED-33 no.10 (1986) 1454.
[4]
R.B.Fair, IEEE trans. electron. devices, ED-35 no.3 (1988) 285.
[5]
B.J.Mulvaney and W.B.Richardson, Appl. Phys. Lett., 51 no.18 (1987) 1439.
[6]
M.Orlowski, Appl. Phys. Lett., 55 no.17 (1989) 1762.
[7]
T.Y.Tan, Appl. Phys., A37 (1985) 1.
[8]
K.Taniguchi and D.A.Antoniadis, Appl. Phys. Lett., 46 no.10 (1985) 944. APPENDIX
A new three-dimensional process simulator was developed for analysis and better understanding of experimental results. In this section, some of the details of the
57
simulator, such as grid generation, discretization scheme of basic diffusion equation, timing control are introduced. Grid Generation The grid for ythe computation must be made especially fine when calculations are to be made for the creep of impurities at ion-implantation at the coener of the mask, the boundary of Si/SiO 2 in LOCOS process, and the redistribution of impurities. The simulator provides the following three generation schemes for the grid: (i) Starting from a given grid spacing, in a geometrical series can be generated; (ii) all grid spacings are set in a geometrical series; (iii) grid points are located with uniform spacings. Figure 1I shows an example of the input. The scheme (i) is used in this example. On both the X- and Y-axis, a uniform spacing of 500 is up to ninth grid point.
VGRIOS MIDX-9,MIDYV9,DX (I )0=.05,DY (I) -0.05,DZ (1) =0.025. VEND ¥SUBSTR IORN= 100, CONCa2.5E 154, I ELM= I VEND PROCESS IPRC(I)=IMASK 1I, (I) AMSK(IH I) =0,.5,0. 5, ICAS(I) =I.PHYI (I) ,4E2,PHY (I ) 6Ei, IPRC(2)=2,MASK(2)IsAMSK(1,2)=0.5,0.5, leAS (2) = PHY [2 - PHY2 (2)= I00 . TIMEQ(21=1.0. IPRC(3)=I, ICAS(3)=I.PHYI(31-0.4E2,PHY2(3)-6.E l, IPflC(4)=2, ICAS(4)3,PIYVI (,)=I .,PHY2(4)x=1000 .TIME(4)s0.3166e66 VEND
Fig. 11 Example of input data.
Output Part The outputs of the three dimensional process simulator are essentially the impurity distribution ans the device geometry. The impurity distributions are produced separately as outputs for B(boron), As(arsenic), P(phosphorus), vacancy and interstitial. Likewise the size, the two-dimensional distribution of SiO2 film thickness, twodimensional distribution of B-As junction can be produced as outputs. Discretization of Diffusion Equation The impurity diffusion in the three dimensional space can be represented as follows using Fick's second law and and the diffusion constant with the dependence on the concentration. Denoting the diffusion constant by D, time by t, the concentration by C, electrically activated impurity concentration by N and the electric potential by V, we obtain
58
a D- a[o1 +a [ Da[ 1 D DaxDy a+-y-0W + aLDWaD z DNý!-1 DN 0 f A DNŽ kT Lax L ax I ay L ay I az I azII ac at
ax
1+
1D-
_
Expanding the equation into Taylor series and considering only the contributions from the nearest grid points, by retaining only a(DaN/ax)/ax, where ij,k, and Ax, Ay, Az are defined as in Fig. 12, and using the suffix n to denote the time, we obtain
a
aXL
1
DŽ ax I
_
Nk
NiTn, nki
.Di~lj,_____j_
'i+l,j,k
2
-
D k+Di
i,jJk
ij,k+
Axi
In other words
2
i-j
k
N-i-Jk -
ISL rA
II.
1
2
Source oaeo y
the diffusionneqatilon
VJAV
+Axil i
AxiI
is converted into a linear differencial equation using seven points in space. Letting the number of grid points in xdirection be MX, y-direction be MY and z-direction be MZ, a system of MXxMYxMZ equations is formed. Regarding the coefficients as a square __4a
Ax
i,k
&,Zk-I
2I1J,k)
Z AY, AX,
hx,.1 , AYI1 ,
&L,
UUII
is obtained by the ICCG method.
Fig.12 Definition of coordinates.
Timing Control of Oxide Film Growth The next step is to calculate the growth of oxide film. Let the thickness of the oxide film be xo, the time of oxidation be t, the constant with the dimension of time be c, the parabolic growth constant be B and the linear growth constant be B/A. Then by Grove-Deal's formula 2 A (1+4B (t+,t)/A )-1 2 Solving this, t+- = xo(xo+A)/B
Letting the oxide film thickness at t+At be xo+Ax, it follows from the above equation, that At = Ax(2xo+Ax+A)/B 59
At a point (MX-1, MY-i) in the field, the distance from the SiO2/Si interface to the next lower grid plane is calculated. The increment of the oxide film thicknesses calculated by multiplying the distance by 1/0.44; Ax increment and then At in the above equation are calculated. In the LOCOS process, a phenomenon exists where the oxide film invades from the end of the mask below the mask to form birds beak. In the cases of annealing in the non-oxidizing atmosphere, however, there is no calculation available for the oxide film thickness. Thus, t+At is determined using the constant At determined by the set values in the program.
60
SIMULATION OF METAL "CONE" FORMATION IN A TRI-LAYER LIFTOFF PROCESS Mark D. Kellam, W. Boyd Rogers, Ron W. Sayer, and Richard C. Chapman The MCNC Center for Microelectronics P.O. Box 12889, Research Triangle Park, NC 27706-2889 A process designed to fill the via between two levels of metal with a lifted-off metal plug produces an unusual via defect. Isolated, submicrometer vias form a cone shaped structure that may be thicker or thinner than the nominal deposited metal thickness, depending on the size of the via. A Monte Carlo evaporation simulator was constructed based on the hypothesis that the cones are formed by incorporation of gas evolved from the sidewalls of the tri-layer structure. The simulator includes a simple model for surface diffusion of the metal and the local evolution of a contaminant gas species. The simulated metal plug profiles match the shape of the cones and the measured size and proximity dependance of the via cone formation. The role of the out-diffused gas molecules in the formation of the cone-shaped structures has been verified by the detection of excess oxygen in the via cones using wavelength dispersive x-ray spectroscopy in an SEM.
INTRODUCTION Considerable interest has been shown in the use of lifted off metal plugs in vias between multiple levels of metal interconnect. The primary advantage of the plug is to maintain perfect planarity of the via surface. The via planarization allows vias between several levels of metal to be stacked on top of etch other, dramatically improving interconnect density. Another advantage of the plug is improved step coverage of the interconnect metal on the via wall.This paper will describe a tri-layer liftoff process that can be used to fabricate the three levels of interconnect metal and to form planarized metal "plugs" in the vias between metal levels [1,2,3,4,5]. The tri-layer structure is constructed of a thick organic planarizing layer, a thin inorganic etch template, and a thin imaging layer. The process to be discussed in this paper uses 0.8 micrometer thick Shipley SAL110-PLI for the planarizing layer, 50 nm of evaporated silicon for the etch template, and 0.6 micrometers of Shipley SNR 248 deep UV resist for the imaging layer [6]. The process sequence is illustrated in
61
Figure 1. The patterned resist is used as an etch mask for a CF 4 reactive ion etch of the thin silicon. The silicon 'template' is then used to mask an oxygen reactive ion etch of the organic planarizing layer. The oxygen etch is designed to be partly isotropic, so that the silicon template is slightly undercut. The metal is directionally evaporated so that the lip of the template breaks the metal continuity over the edge of the tri-layer structure. The metal is then lifted off by placing the wafers in a solvent that attacks the organic underlayer. The use of the silicon template in this process has the advantage of simplicity, but suffers from an unusual problem when the open areas in the template are large distances from other opened areas. The metal growing on the edge of the template shelf has a large lateral growth component that reduces the sidewall angle of the plug and eventually causes the open area to close prematurely. The metal in the etched areas of the template is "pinched" off by the shadowing created by this lateral metal growth. SEM photographs of the resulting "cone" shaped structures also show that the thickness of the material deposited in the holes can be thicker than the nominal deposited metal thickness (Figure 2). These tall cones occur when the via hole is isolated from other vias or is at the
2) RIE etch silicon in CF4
1) Expose + Develop Resist Resist
Resist I
silicon
PMGI 3) RIE etch PMGI in 02
silicon
PMGI
silnmetal
Evatmea E silicon PMGI
PMGI
5) Liftoff metal in solvent metal
Figure 1. Tri-Layer Liftoff Process
62
Figure 2. SEM image of Via Cones after Metal Liftoff Note: Plugs on left have greater taper angle and thickness boundaries of via arrays. In via arrays, the effect is most pronounced on corner vias. The cone formation is via size dependant. Large vias with small aspect ratio holes do not form cones even if they are isolated from other structures. Small via plugs have a cone shaped structure that has a height less than the thickness of the deposited metal while slightly larger vias have a cone height that is thicker than the deposited metal. SEM observations of the small isolated vias before the metal is lifted off show that the via hole has been almost covered with metal (Figure 3). Similar cone shaped structures have been observed by other laboratories that have experimented with tri-layer liftoff of via plugs [7] A Monte Carlo deposition simulator was built to test various models for the formation of these via cone structures. The simulator includes the effects of surface diffusion and the local effusion of a contaminant gas that may be incorporated into the growing film.
63
Figure 3. SEM image of Via Cones before Metal Liftoff Note: Isolated Via is almost covered by metal EVAPORATION MODEL The evaporation simulator is similar to other Monte Carlo deposition simulators reported [8,9,10,11,12,13). Particles are launched at the substrate surface from positions above the substrate that are determined by a random number generator. The angle of the trajectory is randomly varied between fixed limit angles that correspond to the geometry of the source and the evaporator. The particles travel to the surface until they contact a surface particle after which bonding or diffusion occurs (Figure 4). Films formed by this technique without surface diffusion exhibit a fractal surface geometry and very low bulk density. Figure 5 shows the outline of the surface of such a film.
64
Prninm
uniform fliqtrihiitiiinn
of Point Deposition Sources
Random Uniform Distribution of Deposition Angles between Fixed Limiting Angle Template m
Substrate Figure 4. Simulation of the Evaporation
Figure 5. Simulated Evaporation without Surface Diffusion
65
A simple surface diffusion model has been implemented to enable the simulator to create films of high density and to more accurately generate the surface profiles found in actual depositions. After the deposited atom strikes the surface, the path formed by available bonding sites is traced in memory. The atom is then moved along the path and each site is tested to determine the number of nearest neighbor atoms available for bonding (Figure 6). A statistical weighting function is applied to determine the probability of bonding at a particular site based on the nearest neighbor population. Because of this statistical method of determining the atoms' final bonding site, the film does not grow in a completely epitaxial manner.The bonding probability was designed to be exponentially increasing with the number of nearest neighbors and a pre-exponential factor was adjusted to yield films with a bulk void density of less than 5% A random number is generated to determine whether or not the diffusing atom will stop at a particular site. The average surface diffusion distance under these conditions was about 10 atomic spacings. This diffusion length does not correspond to physically observable diffusion lengths because of the two-dimensionality of the simulator and because of
0
0
0
0
0
0
New Atom 0 0) 0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
Figure 6. Representation of the Metal Surface Including Matrix Elements that Represent the Number of Occupied Nearest Neighbor Grid Sites 66
the scale of the evaporated particles. The two dimensional simulation reduces the number of degrees of freedom of the surface and the number of high coordination number bonding sites. Films growing in three dimensions will have higher density and shorter diffusion lengths. The ratio of the simulated atom size to the film thickness in these simulations is roughly a factor of 40 larger than that found in actual depositions. This scale factor will have an impact on the film density, and on those parameters such as the diffusion length that are adjusted based on the film density. A fast algorithm was developed to perform the simulations, which involved the deposition of roughly 5 x 105 particles. Two matrices were created with the number of elements equal to the number of lattice sites to be simulated. One matrix contains characters corresponding to metal atoms, contaminant atoms, and atoms that form the walls and top of the tri-layer structure. Another matrix of integers contains the number of occupied nearest neighbor sites for each lattice position. The particle, following its trajectory to the surface, needs to test only its present lattice site to determine whether the surface has been intercepted. This method was found to be ten times faster than an early algorithm that tested all nearest neighbor positions at each position along the path of the incoming particle. The two methods produce identical structures. Once the atom strikes the surface, the surface diffusion algorithm is implemented. After using the nearest neighbor matrix to do the calculations needed for the surface diffusion,the integer matrix elements surrounding the particle's final resting place are incremented by one. In this way the nearest neighbor matrix grows with the surface in the most efficient manner. Simulations of the evaporation and surface diffusion of 5 x 105 particles used about three hours of execution time on a Convex C-220 mainframe. SIDEWALL OUT-GASSING The observation that cone shaped vias form only if the via is isolated from other vias led to the conjecture that the organic underlayer was acting as a source of contaminating gas. The silicon template prevents the gas from escaping the underlayer except through the holes opened in the template to form the vias. After a long time under vacuum, the amount of gas remaining in a region of the underlayer would depend on the density of openings in the region. The first theory of the cone formation involved
67
gas phase scattering of the incoming metal atoms by the contaminant. Simple calculations showed that gas pressure required to cause significant scattering of the metal atoms would be so large that the evaporation chamber could not be pumped down to the observed base pressure of 1 x 10-6 Torr. An alternative explanation of the cone growth involved the sticking of the contaminant gas to the surface of the metal structure. In the via holes that have significant out-gassing, the bulk material in the hole grows as a result of a co-deposition of metal from the metal source and of gas from the sidewalls. Calculations that follow will show that this mechanism requires a much lower local contaminant gas pressure to modify the shape of the deposited plug, and is consistent with low base pressures in the evaporation chamber. The simulator was built primarily to determine whether the conical shapes observed could be grown by this co-deposition phenomenon. The effusion of a contaminant gas, such as water vapor, from the sidewall of the organic underlayer was accomplished by adding a source of such atoms to the simulation (Figure 4). The initial position and trajectory angles of the particles are generated in a similar fashion to those created during the metal deposition simulation. These particles follow rules that allow bonding only with a deposited metal atom. There is no accumulation of the gas species on uncoated walls of the liftoff template or on a metal surface that is completely coated with the contaminant. The bonding probability of a contaminant atom with a metal atom is assumed to be unity and no surface diffusion of the contaminant is allowed. After contact with the metal atom the contaminant atom is moved at most one lattice spacing to maximize the number of metal bonds. The reduction in the surface mobility of the contaminant species is reasonable if the contaminant is water or oxygen. The result of this condition is an increase in the surface roughness of the plug walls that are exposed to the contaminant flux. If the flux of contaminating atoms is to significantly modify the profile of the deposited metal,the flux of molecules evolved from the organic sidewalls must be at least the same order of magnitude as the metal atom flux at the surface. This flux may be related to the density of molecules and their thermal velocity by FCONTAMINATION =
nV
=
n
=
FMETAL
where n is the density of the contaminant molecules and V is their average velocity.
68
The flux required to evaporate a 1 micrometer thick aluminum film in 10 minutes is: FMErAL =
I x l020 Al atoms 2
m sec
Assuming the contaminant is water in thermal equilibrium at room temperature and that the sticking coefficient of the water to the metal is unity, the density of water molecules in the gas phase is: n = 2 X 1017 water molecules/m3 This corresponds to a local water partial pressure of 5.6 X 10-5 Torr and an effective water vapor leak rate of 8 x 10-10 sccm per via. If every via contributed this leak rate, then 20 wafers, each having 20 chips that contain 1 million 1.0 micrometer vias would lead to a total leak rate of 0.8 sccm. This leak rate is large enough to represent a problem in the evaporator pumpdown. After a normal pumpdown cycle the stored water in the planarizing material will be exhausted in regions that are densely populated with vias. The number of vias at the edges of dense patterns or isolated vias is orders of magnitude smaller than the total via number and the total leak rate is reduced to a level that would not be noticed in the evaporator pumpdown. SIMULATION RESULTS Figure 7 shows the profile of a 1.5 micrometer wide simulated via plug after the deposition of 1.0 micrometers of metal with and without side wall out-gassing. The evaporation source angle limits were set to ± 3 degrees about the normal to the wafer surface. With out-gassing, the plug metal is tapered by the rapid lateral growth of the metal deposited on the template edge, forming a "cone" shaped profile. Before the closing of the hole defined by the metal deposited on the template surface, the thickness of the line grows at almost twice the rate of the metal on the template because of the incorporation of the contaminant into the bulk of the film. The final height of the cone in this case is about 1.75 times the thickness of the deposited metal. The dependance of the "cone" formation on the via size can be understood in terms of the out-gassing theory. For vias with high aspect ratios, the cone height grows at roughly twice the metal deposition rate, but the closure of the hole by the lateral metal growth limits the height to
69
OUTGASSING ON 400 nm metal
1.511
I
1.0-\ OUTGASSING OFF 800 nm metal
t
-d 1.51
1.011
Figure 7 Simulation of Normal and Cone Shaped Via Plug
70
which the cone may grow. The final cone height should increase with the size of the via until the impact of the sidewall is reduced by the increased distance of the deposited metal from the sidewall. A very large metal plug will have a slightly increased thickness near the edge of the plug, but normal metal thickness in its center. Since the lateral growth of the metal on the template is caused by outgassing from the opposite sidewall, the edge of a large metal plug will exhibit only the normal amount of lateral growth. A very small width plug will tend to close off more rapidly than a larger one because of the close proximity of the edges of the template. The metal deposited in such a small via will have the conical shape, but a smaller than nominal height. These two extremes are illustrated in Figure 8. The darkened regions of metal Figure 9 shows the simulated profile of the impurity concentration in a 1.5 micrometer via cone. The concentration is uniform inside the cone and graded in the metal deposited on the silicon template.The oxygen content of the metal was measured using wavelength dispersive spectroscopy in a JOEL 840 SEM with Kevex supporting hardware. Figure 10 compares the x-ray spectrum of an isolated cone shaped via with a normal shaped via found in the interior of a via array on the same die. These spectra show that the cone shaped vias have an abnormally high oxygen content, while the normal OUTGASSING ON 800nm meta]
13
Figure 8. Simulation of Large and Small Vias with Sidewall Out-Gassing
71
Figure 9. Contamination Profile in Via Cone vias have little or none. A small carbon signal is found in both spectra, but this is not due to carbon in the bulk of the metal. The increase of the carbon signal with exposure time to the SEM electron beam indicates that this carbon is a surface contamination induced by the electron beam. Comparison of the oxygen and aluminum density maps in Figure 11 with the SEM photograph of the same location (Figure 12) shows that the via plugs on the edges of the pattern are aluminum deficient and oxygen rich. This correlates with the increased via plug slope that is found only on the edge and corner plugs. This result is consistent with the simulation modeling and verifies the out-gassing theory of the cone formation. The sidewall out-gassing mechanism should also modify the character of long isolated metal wires formed by the same tri-layer liftoff process. Electrical testing shows isolated 0.5 micrometer wires have a resistivity a factor of 5 larger than the bulk values measured on the same wafer. This resistivity increase is likely caused by an increase in the oxygen content in the bulk metal of the wire.
72
111.57
millimeter
139.573
Figure 10. Wavelength Dispersive X-ray Spectra of Normal and "Coned" Vias
Altuminum Spectrum
Oxygen Spectrum
Figure 11. WDS Spectrum Maps of Normal and "Coned" Vias
73
Figure 12. SEM image of Vias Mapped using WDS
DISCUSSION The metal cone formation described in the previous section will have a severe impact on the yield of tri-layer liftoff processes for both the via plug and interconnect metal. The additional bias caused by the lateral shadowing of the deposited features limits the pitch of the metal and increases the minimum size of the metal borders around the via opening. The increased slope of the via plug will increase the number of via failures from poor step coverage and the increased oxygen content of the plugs will increase the via resistance or cause open circuits. The increase in RC delays observed in metal interconnect would certainly cause circuit timing failures. Several experiments are in progress to correct the via cone problem. Increasing the deposition rate of the metal will reduce the amount of oxygen contamination but this solution is limited by the size of the deposition power supply. One solution appears to be the replacement of the silicon template with a material that is gas permeable. Using such a material should prevent the cone formation by allowing the trapped moisture to escape through the template during the evaporation pumpdown. Several commercially available tri-layer template materials
74
and a chemically modified photoresist are being evaluated for this purpose [14,15]. These materials tend to suffer from linewidth loss during the oxygen RIE step that etches the release layer. A process that has the excellent bias characteristics of the silicon template, and freedom from the via cone formation has been developed. The release layer material was replaced with a pre-imidized polyimide that can be heated to 250 C without losing its solubility in liftoff solvent. The etched structures with the silicon template in place were heated to 250 C in the evaporation system by quartz lamps just prior to the metal deposition. Figure 13 shows that 1.0 micrometer via plugs in the corner of a large array did not form cones when this process was used.
Not Baked
Baked
Figure 13. Via plugs deposited after in-situ bake at 250 C
CONCLUSION Tri-layer metal liftoff processes can cause "cone" shaped metal plugs and high resistance metal wires. These structures may be formed because of incorporation of gas, that evolves from the release layer sidewall, into the deposited metal. A ballistic deposition simulator has been built and used to verify this model of the "cone" structure formation. The model is also supported by the detection of large concentrations of oxygen in the isolated via that have a conical shape. This processing
75
problem may be solved by heating the wafers to 250 C in the evaporation system just prior to the metal deposition, or by using a vapor permeable etch template.
REFERENCES
[1]
L.B. Rothman. "Process for Forming Passivated Metal Interconnection System with a Planar Surface." Journal Electrochem. Soc., 130 (5), p1131, (1983).
[2]
S.K. Jones, S.M. Bobbio, B.W. Dudley, and E.K. Pavelchek. "Submicron Metallization Utilizing a Versatile Trilayer Resist/Liftoff process." Proc. SPIE 1086 ,555, (1989).
[3]
S.K. Jones, R.C. Chapman, Yueh-Se Ho, and S.M. Bobbio. "Pattern Replication with a NOVOLAC/Silicon Polymer/Polyester Trilayer Structure." Proc. Kodak Microelectronics Seminar, San Diego, California, 63, (1986).
[4]
B.J. Lin. SPSE 31st Ann. Conf., Washington DC., 1978 and B.J. Lin. "Multilayer Resist Systems." Introduction to Microlithography (L.F. Thompson, C.G. Wilson, and M.J. Bowden. ed.), ACS Symposium Series 219, American Chemical Society, ch. 6, (1983).
[5]
T.P. Shaughnessy, E.P. Stonebraker, and J.V. Brandt, " The Implementation of a Multilayer Imaging Chemistry into a VLSI CMOS Process ." Proc. Kodak Microelectronics Seminar, San Diego, California , 78, (1984).
[6]
Shipley Co., 2300 Washington St., Newton Ma. 02162
[7]
G. C. Schwartz, J. Electrochem. Soc., 138 (2), 621 (1991).
76
[8]
M.J. Brett, K.L. Westra, and T. Smy, IEDM, 336, (1988).
[91
A.R. Neureuther, C.H. Ching, and C. Liu, IEEE Trans. Electron Devices ED-27, 1449, (1980).
[10]
H.P. Bader and M.A. Lardon, J. Vac. Sci. technol. A3, 2167, (1985).
[11]
I.A. Blech, Thin Solid Films 6, 113, (1970).
[12]
J.B. Bindell and T.C. Tisone, Thin Solid Films 23, 31, (1974).
[13]
I.A. Blech and H.A. Vander Plas, J. Apple. Phys. 54, 3489, (1983).
[14]
for instance: IC1 from Futurrex 44-50 Clinton St., Newton, NJ, 07860
[15]
S.M. Bobbio, F.M. Tranjan, T.D. DuBois, S.K. Jones, R.G. Frieser, T. Nivedan, S. Ashburn, Proc. of the 8th International Symposium on Photopolymers, SPE, Ellenville, NY, p 303, (October 1988).
77
USE OF SIMULATION FOR RAPID DESIGN PROTOTYPING G. Chin Stanford University, Stanford, CA 94305 M. E. Law University of Florida, Gainesville, FL 32611
A system allowing circuit designers to rigorously evaluate the effects of technology on layout is presented. This system is created from a set of publicly available process and device simulators, a layout viewer, graphics, and a common user interface. Issues in tool integration are discussed from the aspect of data representations and command languages. An example using the tool to design a dRAM cell is presented. INTRODUCTION The high cost of VLSI fabrication along with short design cycles necessary to remain competitive motivate the use of simulation to accurately predict final electrical characteristics. In the past, use of simulators has generally been partitioned at the circuit level with designers using functional, logic, and circuit simulation tools and technologists using process and device simulation tools. However, we are at the age where the designer must have the ability to directly access the technology tofully understand the impact of layout on performance. We will describe such a system for the designer using the development of a dRAM cell as an illustration. THE DESIGN SYSTEM The design system, shown in Figure 1, extends the U. C. Berkeley tool SIMPLIPX[1]. SIMPL-IPX allows the user to visualize layout (CIF format) and a 2-dimensional cross section (a cutline across the layout) simultaneously. Menu buttons provide the user access to the topography simulator SAMPLE[2, 3], an analytic process SIMPL-2[4], and utilities for resistance and capacitance extraction of planar topologies. In addition, the capability of viewing one dimensional doping profiles within the cross section is provided. The existing system has been enhanced to support thermal process simulation and device analysis. These external stand-alone simulators interact with SIMPL-IPX through a Foreign Tool Interface shown in the dotted region of Figure 1. Each of the items within this interface will be discussed in the following sections. The overall goal of this interface is to provide data transparency across the tools and to hide tool-dependent idiosyncrasies from the user. A set of widely used physically-based publically-available tools was linked to
78
IGnrTool •
Laot
Denter,~c
SIMtP-IPX
EnhancedenIMrLtor
Figure 1 -
Block Diagram of Design System
extended SIMPL-IPX. SUPREM-IV[51 supports diffusion modeling using advanced pointdefect models, implantation modeling including angled implants, and oxidation modeling using stress-dependent visco-elastic models for oxide flow - in one and two dimensions. Device analysis is supported by the 2D tool PISCES-IIB[6] and the 3D tool STRIDE[7]. Field dependent (transverse and longitudinal) mobility models in PISCES allow accurate prediction of submicron device behavior. STRIDE provides efficient 3D device simulation by using parallel computing and an iterative fast solver to reduce total simulation time. ISSUES IN TOOL INTEGRATION Although a great deal of effort has been spent within the TCAD community to develop robust physically-based accurate modeling tools, the user base is small. To intelligently use a process simulator, one should possess a broad knowledge of diffusion modeling, discritization theory, process technology, simulator syntax, and equipment limitations. Potential beneficiaries of TCAD such as circuit designers become overwhelmed at these prerequisites to using TCAD tools and use crude approximations instead. In order to convert these people, the use of TCAD at a higher level of abstraction must be provided such as that shown in Figure 2. The diagram is broken up into tasks(ovals) such as wafer fabrication and electrical tests. The corresponding process in the virtual fab. (TCAD domain) is related to the actual tasks by a set of horizontal arrows. The boxes in the middle consist of common input specifications that help maintain consistency between the domains. In addition, the output of each task (e.g. doping profiles from simulations and from actual wafers) can be compared to determine the relative predictive capability of the simulators.
79
CAD
I
Reality
logy bChrp-
I
Figure 2 -Abstract
View of the Production Process
In order to provide an abstract view of TCAD the following must occur: 1) A common user-interface must guide the user through the tasks necessary to simulate the fabrication and evaluation of devices - the user should not have to know which particular tools are being used. 2) An expert system must provide tool-specific information necessary to properly invoke tools based on abstract tasks to be performed. This can include retrieving stored information on the manufacturing process. 3) Transparent flow of data within the system. This should also allow the user to stop in the middle of a task and display wafer state. Each of these will be addressed in the next sections. Common User-Interface SIMPL-IPX provides a common interface to the designer. Menu buttons provide submenus that express operations in terms of tasks. For example, the top level menu allows the designer a choice of process simulation, device simulation, and layout and cross section browsing. The process submenu provides menu buttons for all of the major process steps such as diffusion, oxidation, deposition, etching, pattern transfer, and implantation. Within each of these process steps, the user can indirectly select the tool to be used based on a speed/ accuracy tradeoff. A scripting capability allows designers to automatically sequence tasks and subtasks. User input when necessary is expressed as either a question, extracted from a
80
set of default parameters, or is queried from the userin terms of a familiar piece of equipment. For example, bias information for device simulation is obtained from the user via a virtual HP4145 front panel. Automatic Input Deck Generation Automated input deck generation removes the possibility of syntax errors from users manually inputting data to the simulators. It also provides a template for modification by the expert user. The key to proper input for grid-based simulation tools is the computation of initial grid. For input to SUPREM-IV a triangular mesh is generated using a set of heuristics that are based on many man-years of experience with the tool. Fine grid is placed near the surface in order to discretize implants (conserve dose). In addition, grid lines with fine spacing are placed in the vicinity of critical implant mask edges where the effect of lateral diffusion may have a strong effect on device behavior. Finally grid is placed deep in the substrate to model point defect diffusion into the bulk. Grid used by thermal simulation may be inadequate for device simulation since an excessive number of grid points are present in the bulk to model the thick substrate necessary to model point defect diffusion. In some cases mobility models require more grid points near the surface than available from process simulation. Initial grid to PISCES-lIB is based on geometric considerations as well as heuristics. The geometric boundary of the device structure is meshed using a triangulator based on TRIGEN[8]. Doping is interpolated onto this grid from process simulation and the mesh is subsequently refined based on gradients in doping. For known device structures (e.g. MOS), special heuristics can be used to guide grid generation. For example, particular mobility models require a special grid spacing within the inversion and depletion regions to maintain accuracy. Modelingof subthreshold characteristics requires fine grid around the source/drain junctions in the direction of the channel. The initial grid to STRIDE is a set of rectangular boxes using an algorithm similar to that used to generate initial grid for SUPREM-IV. Thus a set of tools and heuristics provide adequate initial mesh for many applications. Another aspect of automatic input deck generation is the choice of solutions methods and physical models. Device simulation time can be dramatically reduced for majority carrier devices such as MOS if the one-carrier continuity equation is solved. Short channel MOS devices require special mobility models that accurately predict the effect of transverse and longitudinal electric fields. Bipolar devices require the use of band gap narrow models to simulate emitter efficiency. These rules can be used to generate correct input decks for many simulation cases. Data Transparency Transfer of information between different simulators is not a trivial task due to the
various data requirements. For example, device simulators use impurity concentrations of various charge states as input while process simulation provides as output impurity con-
81
centrations. These concentrations must be converted into the proper acceptor and donor concentrations. Interpolation of these values is also present between grid-based simulators since grid used for process simulation is not necessarily accurate enough or efficient to use for device simulation. Translation (and possible interpolation) between N different tools results in O(N 2 ) translators unless a uniform data representation for wafer state is generated. A more difficult problem than interpolation is in coupling simulators that perform similar types of analysis with widely different data structures. Considerintegrating a thermal simulator with a topography simulator. Topography simulators such as SAMPLE use stringbased models(ID grid embedded in 2D space) to describe surface movement and deformation associated with deposition, etching, and lithography. Thermal simulators such as SUPREMIV use a mesh-based scheme to describe doping concentration and topography across the wafer. Boundary motion is much simpler using strings than grid since no constraint is placed in the vertical direction - resulting in a more accuracy for the same computational cost. Boundary motion using grids requires that either movement on the order of an element's width be allowed (to allow the addition or refinement of elements that preserve a good shape for further numerical analysis) or the use of advance techniques to adaptively refine stretched elements. In addition, checks for overlapping elements is necessary for simulation of nonplanar surfaces (e.g. depositing into a trench). Limitations of the purely string approach are that the diffusion equation cannot be solved within the regions because there is no internal grid to the region. Since the mesh based scheme is a superset of the string (e.g. the boundary of a mesh can be thought of as a string) algorithms on improving grid algorithms to follow boundary movement are investigated. Two new schemes are investigated. Both require the use of a triangulator to mesh regular polygons. In the utility based approach, a utility was created to import an string from SAMPLE, convert it to a polygon, mesh the polygon to create a grid, and merge the new grid into the existing grid (Fig. 3). For the etching case, the original node removal algorithm currently in SUPREM-IV (remove elements inside the etched region and snap the surface grid points onto the new surface string) was used to minimize interpolation error within the substrate layer. Another reason for the choice is that interpolation schemes should be chosen by the client application which has knowledge of grid and numerical requirements - not by the utilities. The second approach places the triangulator within the SUPREM-IV program itself and accepts strings as input. Polygons are not necessary since for deposition since they can be constructed from the original surface are already present within the SUPREM-IV data structure. The cost of merging grids is dramatically reduced since grid points necessary for the deposited structure can be dynamically allocated from the SUPREM-IV internal heap. Etching is more robust by regridding the entire structure (global regridding) rather than the use of local regrid scheme (element removal and local regrid). The grid generator has been modified to maintain as many as the original grid points as possible by not remeshing
82
Figure 3 -Utility
Based Approach to Coupling SAMPLE with SUPREM-IV
rectangular regions (the initial SUPREM-IV mesh is composed of right triangles). Figure 4 compares the two grids for a trench etch. Differences in doping across the elements in the vicinity of the trench is on the order of (6%), which is tolerable considering the accuracy of the models used. EXAMPLE
-
ANALYSIS OF A dRAM CELL
To show the use of the system for device prototyping, analysis of a dRAM cell will be performed. This cell, taken from [91, has the layout shown in Figure 5. For device structures without a corresponding layout the system provides a capability to specify arbitrary device structures in a CIF format using a layout editor. Attributes such as analytic functions to describe doping concentrations are attached to the layout. An interactive interface to SUPREM-IV allows the use to enter in the processing steps necessary to fabricate the device. As an alternative, an existing process sequence could be submitted to the system through process editors such as PDA[10]. Based on this process information, input decks for are SUPREM-IV automatically generated, including grid definition, not requiring knowledge of SUPREM-IV syntax from the user. These input decks are submitted to SUPREM-IV and the results displayed in the cross sectional window. Due to the computational requirements of defected assisted diffusion on large meshes, the option of submitting the automatically generated input files in batch mode is allowed. An analytic simulator is run to allow the user a qualitative view of the sequence to ensure that the results that are seen are expected (e.g. minimize input error from the user). In addition, ID simulation can be performed at various points in the layout to improve response time at the
83
SUPREM-IV SUUF.9114
SUPREM-IV SUUF.9114
W
5.w
600
7.00
4&W
M0
0.0
LUJ
Figure 4 - GridsProduced Using Local and Global Remeshing cost of accuracy in the second dimension. The completed dRAM cell is shown in Figure 5. The trench capacitor oxide was formed by using a sacrificial oxidation and removal to smooth the comers at the bottom of the trench followed by a stress-dependent oxidation. Sacrificial oxidation reduces leakage current due to high electric fields that build up around sharp comers. SAMPLE was used to perform the anisotropic trench etch, the deposition of the capacitor plate and deposition of the gate and contact regions. The resulting structure is transferred to PISCES by first extracting the boundary of the cell and meshing this boundary. Doping is interpolated onto this new mesh. Simulated DC capacitance is 37fF. Another interesting effect of advanced process physics on device performance is in investigation of the effect ofpoint defect diffusion on parasitic current along the trench sidewall[1 1]. For this dRAM cell [12], the injection of interstitials during n-well oxidation results in increased spreading of the retrograde n-well implant. This spreading of the n-well results in a lower effective substrate doping for the parasitic trench transistor and hence a lower threshold voltage. Figure 6 shows a picture of the device structure as well as the subthreshold characteristics of the parasitic trench sidewall MOS with and without use of point-defect diffusion models. Both of these dRAM examples show the usefulness of advanced TCAD systems for rapid device analysis. They can qualitatively predict trends that can be fixed before actual silicon.
84
NPU
SELECT COMMAND ECONT
NIB
I@ACwV N18 NIB
EJbfrr1
23
NiB P15 *POLT
ETRNC
P17
EU
P18
El
P19 m!i
BIPOLAR
MOITI
Figure 5 -
GENERAL
PA1AICS
RT
R
ABORT
Layout and Cross of dRAM cell from SIMPL-IPX
Parastic Gate/Drain Figure 6 -
EDI
Forward Bias
Effect of point defect diffusion on conduction current of parasitic trench sidewall MOS. 85
CONCLUSION Integrated TCAD systems provide the flexibility for performing rapid device prototyping for use by device and circuit designers. Use of the system to examine dRAM cell design has been demonstrated. ACKNOWLEDGMENTS Support for G. Chin is provided by SRC. Support for M. E. Law is provided by the Florida SEMATECH Center of Excellence. The authors would like to thank Peter Griffin for technical discussions. REFERENCES [1]
E. W. Scheckler, A. S. Wong, R. H. Wang, G. Chin, J. R. Camagna, K. K. H. toh, K. H. Tadros, R. A. Ferguson, A. R. Neureuther and R. W. Dutton, "A Utility-Based Integrated Process Simulation System," in Proc. 1990 Symposium on VLSI Technology, Honolulu, Hawaii, pp. 97-98, 1990.
[2]
W. G. Oldham, S. N. Nandgankar, A. R. Neureuther and M. O'Toole, "A General Simulator for VLSI Lithography and Etching Processes : Part I - Application to Projection Lithography,"IEEE Trans.ElectronDevices, vol. ED-26, pp. 1455-1459, April, 1979.
[3]
W. G. Oldham, A. R. Neureuther, C. Sung, J. L. Reynolds and S. N. Nandgonkar, "A General Simulator for VLSI Lithography and Etching Processes: Part II - Application to Deposition and Etching," IEEE Trans. Electron Devices, vol. ED-27, pp. 1455-1459, August, 1980.
[4]
K. Lee and A. R. Neureuther, "SIMPL-2:(SIMulated Profiles from the LayoutVersion 2)," IEEE Trans. Computer-AidedDesign, vol. CAD-7, pp. 160-167, February, 1988.
[5)
M. E. Law and R. W. Dutton, "Verification of Analytic Point Defect Models Using SUPREM-IV," IEEE Trans. Computer-Aided Design, vol. CAD-7, pp. 181-190, February, 1988.
[6]
C. S. Rafferty, M. R. Pinto and R. W. Dutton, "Iterative Methods in Semiconductor Device Simulation," IEEE Trans. Electron Devices, vol. ED-32, pp. 2018-2027, October 1985.
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[7]
G. Chin, K. Wu and R. W. Dutton, "A STRIDE towards practical 3D device simulation - Computational and visualation considerations," in Proc. NUPAD 3, Honolulu, Hawaii, pp. 21-22, 1990.
[8]
R. E. Bank, "PLTMG: A software packagefor solving elliptic partialdifferential equations,"Philadelphia: SIAM, 1990.
[91
S. Nakajima, K. Minegishi, K. Miura, T. More, M. Kimizuka and T. Mano, "A submicrometer megabit dRAM process technology using trench capacitors.," IEEE Jour. Solid-State Circuits, vol. SC-20, pp. 130-136, 1985.
[101
J. S. Wenstrand, H. Iwai and R. W. Dutton, "A Manufacturing Oriented Environment for Synthesis of Fabrication Processes," in Proc. ICCAD, Santa Clara, CA, pp. 376379, 1989.
(111
Peter Griffin, private communication. 1991.
[121
P. Cottrell, S. Warley, S. Voldman, W. Leipold and C. Long, "N-Well design for trench dRAM arrays," in Proc. IEDM, San Francisco, pp. 584-587, 1988.
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X-RAY LITHOGRAPHY AT IBM Robert W. I lill IBM General Technology Division Ilopewell Junction, N.Y. 12533 and, Juan R. Maldonado IBM Federal Sector Division Manassas, Virginia Mailing address: IBM General Technology Division Rt 52, 300/40E Ilopewell Junction, N.Y., 12533
This paper describes the feasibility studies being conducted at IBM to use x-ray lithography for production of high density silicon chips. The system approach to x-ray lithography adopted at IBM considering the interaction of all the components will be presented in this paper. The following areas will be described: x-ray sources, mask, resist, exposure tools, the resolution limits of x-ray lithography, prototype devices fabricated with x-ray lithography, and process advantages. In addition, the status of the Advanced Lithography Facility which houses the electron storage ring x-ray source procured by IBM from Oxford Instruments, will be presented.
INTRODUCTION The purpose of this paper is to describe the work at IBM to study the feasibility of x-ray lithography (XRL) for the manufacture of submicron silicon chips, and to present the worldwide status of the most important components of XRL systems utilizing synchrotron storage rings.. The work at IBM is being performed at several locations including, Yorktown Heights, N.Y.; Burlington, VT.; Manassas, VA.; and East Fishkill, N.Y.. Several Universities are also supported by IBM in areas that include mask studies, modelling, radiation damage, and mask/wafer alignment techniques. IBM is also working with several companies under a DARPA contract. Furthermore, IBM and Motorola are collaborating in an 18 month study program on XRL with several Motorola employees temporarily assigned to IBM facilities. The XRI. work started at IBM in 1970 with an internal memo authored by Ralph Feder while working in Fast Fishkill, N.Y., which predated the first external publication 2 on XRL by the MIT group. Shortly after, Feder was transferred with the project from East Fishkill to the Research D)ivision, Yorktown Ilights, N.Y.. The years from 1970-1980
88
provided the background work in XRL. The initial experiments, and feasibility studies were performed with electron bombardment x-ray sources_1. 4 ',,. However, it was soon recognized that due both to the lack of x-ray sensitive resists, and stringent level/level overlay accuracy requirements, more powerful and collimated sources were needed to meet the throughput and pattern placement accuracy requirements of submicron device fabrication. In 1975, the first XRL experiments using synchrotron storage rings were reported from work at DESSY in Germany ', and ACO1 in France. This was followed with work in Germany' at the Fraunhofer Institute, and in Japan"0 , at the KEK facility in Tsukuba established in 1983. After a period of continuous XRL work utilizing conventional sources, the decision was made at IBM in 1980 to explore the feasibility of XRL utilizing a synchrotron storage ring". Soon afterwards, a systematic approach to XRL was started"2 using as the x-ray source, a port on the VUV storage ring at the Brookhaven National Laboratory (IINI). This approach considered the interaction of all key system components: source, mask, beamline, stepper, resists, etc., necessary to fabricate submicron (0.5 pm) devices. Four level NMOS and eleven level CMOS devices were successfully fabricated'l."4. The success obtained at BNL together with the predicted "1 advantages of XRL over other lithographic technologies led to the concept and implementation of the Advanced Lithography Facility (ALF) at East Fishkill, N.Y.. Several of the major components of the XRL system will be described below together with their interrelationships.
X-RA Y SOURCE In this section the status of the storage rings presently in operation or planned for XRL applications will be reviewed. There are two kinds of XRL storage rings; one utilizes conventional magnets operating at room temperature, and the other utilizes superconducting magnets to produce a smaller electron bending radius in order to reduce the size of the machine. The latter has been named "compact" storage ring, and its largest dimension may be of the order of a few meters. The electrons are injected into the ring .by means of a linear accelerator, or with a microtron. Injection can be accomplished at full energy (about 700 Mev), or by utilizing low energy injection ramping techniques from 50 Mev to full energy. Low energy injection is less expensive, but requires a more sophisticated electronic control system. Compact storage rings have been built in Germany', and Japan", and more recently in England by Oxford Instruments" for IBM. This compact storage ring (IIELIOS) utilizing superconducting magnets is designed to operate at an energy of 700 Mev with an average current of 135 mA, and it is presently installed in ALF. IIELIOS will be capable of delivering about 100 mW/cm 2 of x-rays between 8- 10 A incident on the resist with a properly designed beamline. This x-ray flux is considerably higher than any other conventional point source including electron bombardment"," and plasma (gas20 ,' or laser 22-27) x-ray sources. These point sources produce several orders of magnitude less output, and therefore are not suitable for a high throughput production system like the one to be evaluated in ALF. Nevertheless, these alternative sources offer the advantage of
89
"granularity" and
ease of installation with comparatively lower initial cost, and their future performance and development should be watched closely M. 2.
EXPOSURE SYSTEM The exposure system, or beamlines and steppers, are designed to work together with the x-ray source in order to optimize the resolution, and throughput of the x-ray lithography system. The exposure system used with synchrotron based semiconductor lithography systems consist of a stepper and a beam line to transfer x-rays in a useable form to the stepper. Specially designed mechanical fixturing is used to hold patterned masks and semiconductor wafers coated with resist in the path or "field" of radiation. -The mechanical systems for moving and holding the mask/semiconductor wafer combination are referred to as either the "stepper" or "aligner". They vary from relatively simple systems that expose one field at a time for research purposes to highly automated systems that rapidly unload wafers and masks from their holders or cassettes with very sophisticated alignment and control systems for positioning the mask with respect to the wafer. Some of these systems are capable of aligning and exposing multiple fields per wafer and can handle wafer sizes from 100 millimeters to 200 millimeters. Aligner manufacturers have started to work on the development of the elements of highly sophisticated manufacturing systems. Most of the installed systems are of the research type at the present time; some aligners have been purchased from Karl SUSS GMBH in Germany. Advanced work is being pursued on more elaborate types of aligners at NTT, Matsushita, Canon, and Sumitomo Heavy Industries. The beam line is a long evacuated pipe or chamber several meters long with its own control and vacuum system. It is isolated from the synchrotron by front end valves, one of which is usually a fast acting "shutter" that will close to protect the vacuum inside the storage ring very quickly. Closing times for this valve of 100 to 200 milliseconds are typical when a leak is detected. The beamline also contains one or more chambers containing the x-ray optics. The optics installed in these chambers is used to expand the beam and translate it into a useable form for the aligner. The optics consists of single or multiple mirrors which oscillate or translate the beam to scan one axis of the exposure field. In some systems a fixed mirror is utilized in the first mirror box to filter out the high energy spectrum from the storage ring, expand the beam in one axis, and to provide.a few degrees of tilt to the beam line (deflecting the beam downwards from the horizontal position for safety reasons). The latter is important since the radiation generated from electrons hitting the walls of the ring is not in the direct line of sight of a tilted beam line. An oscillating or translating mirror is then is used to expand the other axis of the field and to scan the beam onto the mask. Multiple mirrors are utilized to minimize scanning losses due to a curved beam shape. Two such parallel mirror systems have been reported by NTT10. Canon uses a fixed cylindrical mirror in the beamline to expand the beam to a 30 X 30 millimeter field on the mask. 90
Gold is the most common coating material for the mirrors, however NTT has reported some work using Pt mirrors ",. The surface finish is very important and the most advanced polishing and etching techniques arc used in the fabrication of the mirror. A membrane window is used to separate the vacuum in the beam line from the stepper and mask/wafer. This window is usually a thin beryllium foil (less than twenty five microns thick), Kapton foils have also been reported however they show some lifetime problems. In some beam lines, an acoustic delay line consisting of a series of baffles is placed before the beryllium window. Its purpose is to decrease the propagation time of incoming gas in case of window breakage, and to allow sufficient time for the fast action valve to close. All of the beam line components including several ion pumps and valves located along its length are computer controlled and arc interfaced to the storage ring operational and safety systems. In some installations a small computer is used for beamline control to be interfaced to a larger computer that controls the ring facility. The beam lines used today are generally of the research type and have been constructed by their users. They are built on an individual basis and are tailored to their applications. In Japan, there are lithography beamlines at KEK, NTT, SORTEC, and others. There are also beamlines at BESSY9 , Berlin; the Super ACO 32 storage ring in France; China 33; and in the U.S., at the University of Wisconsin 4, and at IBM as described below. The mask wafer aligner for a storage ring x-ray lithography system is operated with the semiconductor wafer mounted in a vertical position on some form of a vacuum chuck held in close proximity to the precisely aligned patterned mask. The stepper contains mechanical devices to load the mask and wafer from a clean room environment or SMIF boxes. Manual single wafer loading/unloading, or cassette loading/unloading may be utilized in research types of tools to handle the mask and wafers. The wafer size may range from 100 to 200 millimeters in diameter. To move the wafer to the next exposure field and to position the wafer with respect to the mask, the steppers use two main types of coarse drives for their vertical XY tables. Some are using DC linear motors for the XY table; NTT is using an air bearing lead screw that they have developed for both the X and Y axes30 . Most companies use flexure plates for the fine positioning of the wafer. Piezo electric actuators are often used to position the mask. One of the most critical components of the x-ray stepper is the alignment system. Alignment systems for x-ray lithography aligners are of two types. Both types process the combined signals obtained from the alignment marks on the mask and the wafer. These marks are frequently gratings or linear zone plates. NTT and Matsushita have combined the gratings with optical heterodyne interferometric techniques 11 and Sumitomo Juki 36 is using a dual chromatic focus technique utilizing the same lens at two
91
wavelengths. A similar alignment system utilizing a dual focus lens at two orthogonal states of light polarization was originally utilized in x-ray lithography systems at Bell Laboratories. 11The SUSS stepper utilizes mechanically actuated microscope objectives to align the mask and the wafer. In order to provide heat transfer from the mask/wafer during x-ray exposure, a heat conducting environment is required. Several types of environments have been utilized: air or nitrogen at atmospheric pressure, helium at atmospheric pressure and also at low pressure. Helium offers little attenuation to the wavelengths of interest, and has a short mean free path capable of effective heat transfer down to pressures of about 20 torrs. Because of throughput considerations, an environment of helium at atmospheric pressure is preferred. Work has been reported in all of the above environments by IBM and others. Air at atmospheric pressure is used by NTT 30 and helium at low pressure by Canon. Variations of these environments are used by others. There are two projects in the US which are addressing development steppers. There is a DARPA contract with SVGL (formerly Perkin Elmer) to produce a development exposure system which will be installed at the University of Wisconsin. This has suffered schedule delays because of the sale of the responsible Perkin Elmer division to SVGL. IBM has contracted for and is working with Karl SUSS GMBH (a German based company) on a development stepper for their facility in East Fishkill. Neither of these projects has the alignment capabilities necessary to do .25 micron ground rules and will require improvements. The IBM work will be described below. Presently, there are two kinds of bearnines installed by IBM at BNL. One of therp labeled U6, (originally installed by the Research Division) includes an oscillating mirror which cuts off the unwanted high energy radiation, and scans the fan of radiation from the storage ring onto the mask/wafer assembly. An IBM built stepper 11which operates in relatively high pressure helium gas (20 torr) was used in U6 for the fabrication of 0.5 prm devices with II x-ray exposed levels39. The other beamline' labeled U2, (presently in use) has a fixed mirror which shifts the beam from the horizontal plane, and cuts-off the high energy x-rays from the ring. The mirror provides a fixed quasi-circular segment of radiation onto the movable mask/wafer assembly of the SUSS stepper4 l operating in an atmospheric helium gas environment. Work in mirror evaluation and design is being performed in collaboration with CXRL at the University of Wisconsin. Both beamlines have a Be window to separate the low pressure environment from the exposure chamber, and acoustic delay lines in conjunction with fast acting valves to protect the ultra high vacuum in the event of window failure. The beamlines to be installed in ALF may be of either fixed or scanning mirror depending of the requirements of the stepper. I lowever, a scanning mirror may provide a faster throughput system, since the possibility of mask/wafer misalignment during motion is eliminated.
92
X-ray steppers capable of meeting 0.5 pm device ground rules are presently commercially available for conventional and storage ring XRL sources 4-41 . For 0.25 micron ground rules, the alignment system must be able to align the mask to the wafer with a total 30 error of less than 0.05 micron. None of the systems reported in the literature has achieved this level of performance. The best performance (about 0. 1 jtm, 3a) has been reported by NTT using an optical heterodyne system, and by IBM using the SUSS stepper installed at IBM/BNL beamline". High throughput steppers with 0.25 Pm capability are currently under development, and will be needed in the near future for XRL pilot lines in ALF. MASKS An x-ray mask consists of an x-ray transparent substrate with a thin absorber pattern. The x-ray mask substrate must meet very stringent requirements, and many materials (ie. silicon nitride, B-doped Si, Ge-B-doped Si among others) have been considered for it in the past 20 years. The x-ray masks presently being used 4- at IBM consist of a boron doped silicon membrane approximately 2.5 pum thick, and an e-beam written electroplated gold pattern. The boron doped silicon substrates are obtained by conventional diffusion techniques on silicon wafers. The wafers are bonded to a support pyrex ring to provide stability. Work on mask ring behavior in a stepper has been reported' and work on modellinge is presently being performed in collaboration with the National Institute of Standards and Technology (NIST) to help establish a standard mount to be used in commercial steppers. In addition, studies on mask contrast enhancement and mask replication are being performed in collaboration with the CXRL at the University of Wisconsin"'. The IBM mask technology was developed at Yorktown, and transferred to the IBM Advanced Mask Facility (AM F), Burlington, VT. which supplies a large number of mask substrates to IBM and other users. The boron doped silicon substrates fabricated by the AMF are relatively strong, offer low mask distortion and excellent radiation hardness, however, they lack optical transparency for conventional alignment systems. In the IBM mask optically transparent alignment windows using a polyimide substrate"0 are located away from the silicon membrane area to allow room for the alignment microscope objectives. In order to decrease alignment errors it is advantageous to perform in-field alignment. For this reason, work in developing mask substrate materials with suitable transparency is currently being pursued"t .- 2 in the U.S., Japan, and Europe. For a material to be adequate for x-ray mask substrate it must meet the mask lifetime requirements. (Usually equivalent of three months of continuous use under proper conditions, which translates to about 540 kJ/cm 2 of incident x-ray flux on the mask for a 35 mi/cm 2 resist exposed in I second). Therefore, the material must be chemically and mechanically stable under x-ray irradiation (radiation hard). More work is required to achieve the radiation damage test goals for mask substrate materials. In particular, Bdoped Si mask substrates have been subjected 11to 54 kJ/cm 2 of incident x-ray radiation without measurable distortion. This is about a factor of ten below the set goal of 540 93
kJ/cm 2. Radiation damage tests are very costly and time consuming, and a special high flux density beamline has been constructed in CXRL at Wisconsin to accelerate the tests. Two kinds of deposition techniques for absorber materials are being considered: additive and subtractive processes. The additive process consists of electroplating gold on a 4 plating base through a resist pattern" . The subtractive process involves etching a metal (eg. W or Ta) using a resist mask" - 16. Subtractive processes utilizing W may offer mask repair advantages, and are presently considered as a replacement for gold. However, the additive process offers better linewidth tolerances since it only includes resist errors. The subtractive process includes resist and metal etching errors. In addition, for the substractive process, electron backscattering from a heavy substrate must be properly corrected during e-beam writing of the x-ray mask. RESIST MATERIALS The high flux from storage ring x-ray sources allows efficient exposure of relatively thick single layers of conventional resists3 1 . However, in order to further improve the system throughput and to reduce radiation damage during x-ray exposure of certain metal levels s8-6 more sensitive resists are desired. Work in resist materials"-" is presently being conducted with the goal to obtain high sensitivity (< 100 mJ/cm 2) resist materials capable of simple single level processing while preserving the lithographic properties. The status of the x-ray resist work at IBM has been reported elsewhere'7-1.
SYSTEM CONSIDERATIONS All the components described above and a few others (inspection and repair tools, safety issues, processing, etc.) must be integrated to obtain an x-ray lithography system capable of successful operation in a production environment. It can be shown' that the preferred wavelength range for x-ray lithography using single levels of conventional resist materials is 7-10 A. HELIOS will provide effective x-ray flux in that wavelength range. On the other hand, wavelengths longer than 10 A should not be completely ruled out, since their use may introduce less radiation damage to the oxide films, due to the higher attenuation of the x-ray flux by the upper device layers. A softer spectrum may be advantageous in some applications where annealing at elevated temperatures to eliminate radiation damage may not be possible. Studies on x-ray induced radiation damage are being performed at several IBM locations in collaboration with the University of North Carolina, Penn State, and the CXRL at the University of Wisconsin. Other issues which have been or will be considered in the design and operation of exposure systems for ALF include: .
Field size (Mask strength, and stability, etc.)
94
* *
Field Uniformity (Mirrors, Be window, source characteristics, etc) Overlay Errors (Final Device) *
Mask distortion (intrinsic and operational) Mask Writing Errors. Alignment System Errors
*
Run-out errors Penumbral errors
*
Wafer processing errors Errors due to mask and wafer mounting
* * • •
Personnel safety Radiation Damage Mask inspection and repair tools and techniques"' Source Divergence Effects
The last issue has been shown1 0 to play an important role for the extendibility of x-ray lithography below 0.25 pum. This is because coherence effects "1 may narrow the processing window for the simultaneous replication of several different features of different sizes below 0.25 prm, however, increasing the source size or its divergence helps in extending the process window for a given resist material 72
SUMMARY None of the remaining problems in XRL are fundamental, and evolutionary improvements of the state of the art in tool and metrology development will lead to their solution in the very near future. Metrology requires special attention, however, since measurement tools are required to evaluate any submicron technology. Work in improving mask pattern writers is in process, because pattern placement in IX x-ray mask fabrication for 0.25 pm devices is limited by the accuracy of present day e-beam tools. The possibility of replicating IX x-ray masks from NX optical reticles using optical lithography tools should be explored because x-ray masks offer an ideal flat substrate for optical projection lithography. Studies of process induced wafer distortion and magnification correction techniques are also needed. The resolution capabilities of XRL have been shown7 3 to be much better than 0.1 ym for simple patterns. More work is required to optimize some parameters like source divergence for replications of features below 0.15 um for complex patterns. However, it could be easily envisioned that proximity XRL once it is established in production may be extended to 0.1 pm and below similarly to the way optical lithography has been extended below I pm in the last few years. For the replication of features below 0.15 ym, projection XRI. systems are being proposed elsewhere' 4 - ' as an alternative to proximity printing. lHowever, considerable research and development work will be needed before they can be implemented into a production environment. Nevertheless, we are following their development very closely since x-ray 95
projection systems may also find applications in the fabrication of IX proximity x-ray masks from NX reticles. In conclusion, after 20 years of continuous work, x-ray lithography is beginning the development phase. The testing ground to study the feasibility of XRL for the fabrication of silicon chips for IBM has been selected at the Advanced Lithography Facility in East Fishkill, N.Y.. All the required components have been designed and fabricated considering their interrelations using an integrated system approach. Work is being done with the U.S. government, selected universities and pursuing collaboration with other semiconductor companies towards the goal of demonstrating the feasibility of XRL in the manufacturing of submicron silicon chips before the end of the 20th century. The insertion point of x-ray lithography will depend however, on economics. The latter will depend on the complex phase shifting mask technology, and top surface imaging (or multilayer resist process) presently being proposed to extend optical lithography to the 0.25 jm regime.
A CKNO WLEDGEMENTS The authors would like to thank the East Fishkill, Yorktown, Burlington, and Manassas IBM XRL teams for their contributions. Research was carried out, in part, at the National Synchrotron Light Source, Brookhaven National Laboratory, which is sponsored by the U.S. Department of Energy, Division of Materials Science and Division of Chemical Sciences under contract number DE-AC02-76C1-100016. Government funding has also being provided by NRL under the National X-ray Lithography Program.
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29. Maldonado, X ray Lithography, Where it is Now, and Where it is Going, Journal of Electronic Materials, Vol. 19, No. 7, 1990. 30. S.Ishihara, M.Kanai, A.Une, and M.Suzuki: 'An X-ray Stepper for SOR lithography, NTT Review, Vol.2, No.4, p.93, July 1990 31. Kaneko T., Y.Saitoh, S. Itabashi, and H. Yoshihara: 'SOR Lithography Beam Line', NTT Review, Vol.2, No.4, pp. 87-89, July 1990 32. Rousseaux F., A. M. ttaghiri-Gosnet, C. Khan Malek, B. Kebabi, 11. Launois, and J. Durand, X-Ray Lithography at the Super-Aco storage ring of Orsay (France), Microelectronic Engineering 11 (1990) 229-232 33. Oian, S. G. Li, Z. Liu, Q. Chen, D. Jiang, W. Liu, Y. Kan, and Y. Su, J.Vac. Sci. Technol. B 8 (6), Nov./Dec. 1990, p1524. 34. Baszler, M. Hansen, and F. Cerrina, Absolute flux measurements for x-ray lithography beamlines, p1529. 35. M. Suzuki and A. Une: 'An optical-heterodyne aligment technique for quarter-micron x ray lithography." J.Vac. Sci. Technol. B7(6) Nov/Dec (1989) 1971 36. Sumitomo XRL system brochure. 37. A.D. White :Simple bifocus element for microscope objectives", Applied Optics, Vol. 16, No.3, p.54 9, March 1977 38. Bobroff, N., R. Tibbets, J. Wilczinski, and A. Wilson, Optical Alignment Microscope for Xray Lithography, J.Vac. Sci. Technol. B 4 (1) Jan/Feb 1986, pp 285-289. 39. Wang, L.K., C. I1. llsu, D. Seeger, J. Silverman, D. Zicherman, C. K. lu, R. Acosta, R. Viswanathan, J. Warlaumont, A. Wilson, "O.Sm CMOS devices and circuits fabricated using synchrotron x-ray lithography', Digest 1989 Symposium on VLSI technology, Kyoto, Japan. 40. Rippstein, R.P., D.L.Katcoff, and J.M.Oberschmidt, Design of an X-ray Lithography Beam Line, SPIE Proc. 1089, 252 (1989) 41. Cullman, E. and K. Cooper, 'Experimental Results with a Scanning Stepper for Synchrotron-based X-ray Lithography, 1. Vac. Sci. Technol., B 6 (6), Nov.-Dec. 1988. 42. McIntosh, R.R., et al., X-ray Step and Repeat Lithography System for Submicron VLSI, SPIE 632, 156-163 (1986). 43. Kuono, E. et al., An X-ray stepper for Synchrotron Radiation Lithography, J. Vac. Sci. Technol., B 6 (6), Nov.-Dec. 1988. 44. Rippstein, R., and A. Flamholz, X-ray stepper exposure system: Performance and status, h.Vac. Sci. Technol., B 8 (6), Nov./Dec. 1990, p2002. 45. Acosta R., JR. Maldonado, L. Towart, and J. Warlaumont, B-Si Substrates for X-ray Lithography, Proc. SPIE 484, 1984. 46. C. Uzoh, J.R. Maldonado, R. Acosta, S.S. Dana, I. Babich and 0. Vladimirsky, Mechanical Characterization of Membranes for X-ray Lithography Masks, J. Vac. Sci Technol., B 6 (6) Nov/Dec 1988. 47. Wilson, A.D., C. Lapadula, J.P. Silvennan, R. Viswanathan, I1. Voelker, and R. Fair, Control of Fixturing-Induced Distortion in X-Ray Masks, J. Vac. Sci. Technol., B 7 (6), Nov/Dec.1989, pp 1705-1708. 48. Chen, A., S. Lalapet, and J.R. Maldonado, Elastic Deformation of X-ray Lithography Masks under External loading, to be published.
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49. White, V., J. Wallace, F. Cerrina, Y. Vladimirsky, Y. Su, J. R. Maldonado, Contrast amplification of high resolution x-ray masks, J. Vac. Sci. Technol. B 8 (6), Nov/Dec. 1990. 50. Acosta R., J.R. Maldonado, N. Bobroff, J. Paraszczak, A.D. Wilson, and Y. Vladimirsky, Microelectron. Eng. 84, edited by A. Hleuberger, and Beniken, (Academic Press, London 1985) pp 291-96. 51.
Vladimirsky, Y., J.R. Maldonado, 0. Vladimirsky, A. Starikov, R. Fuentes, D. Guarnieri, S.W. Whitehair, and J. Cuomo, Optical Properties of X-ray Lithography Masks, J. Vac. Sci. Technol. B 8 (6), Nov/Dec 1990.
52. Maldonado, J.R., Y. Vladimirsky, 0. Vladimirsky, I. Babich, R. Fuentes, D. Guamineri, S.W. Whitchair, and 1. Cuomo, Light Scattering Properties of X-ray Lithography Mask Substrates, J. Vac. Sci. Technol. B 8 (6), Nov/Dec 1990. 53. Acosta, R.E., X-ray mask distortion due to radiation damage, Microelectronic Engineering 13 (1991) 259-262, Elsevier. 54. Shih-Liang Chiu and R.E. Acosta, Electrodeposition of Low Stress Gold for X-ray Mask, J. Vac. Sci. Technol. B 8 (6), Nov/Dec 1990, pp 1589-1594. 55. Suzuki, K., and Shimuzu, Y., X-Ray Mask Technology: Low Stress Tungsten Deposition and Sub-half micron Absorber Fabrication by Single Layer Resist, Microelectronic Engineering 13, (1991), Elsevier. 56. Xu, Z., et al., A XPS Study on Ion Beam Assisted Deposition of Tungsten Using WF(6), J. Vac. Sci. Technol. B 7 (6), Nov/Dec 1989. 57. Lane, J.G., JR. Maldonado, A.N. Cleland, R.P. Ilaelbich, J.P. Silverman, and J.M. Warlaumont, Conventional novolak resists for storage ring x-ray lithography, J.Vac. Sci. Technol. B 1 (4), Oct-Dec. 1983, pp 1072-1075. 58. Maldonado, J.R., A. Reisman, 11. Lezec, C.K. Williams, and S.S. Iyer, X-ray Damage Considerations in MOSFET Devices, J. Electrochem. Soc., Vol 133, No. 3, (1986). 59. Reisman, A., C.i. Merz, J.R. Maldonado, and W. Molzen, Jr., Low Energy X-ray and Electron Damage to IGFET Gate Insulators, J. Electrochem. Soc., Vol 131, 1414 (1984). 60. Maldonado, J.R., A. Reisman, 1I. Lezec, B. Bumble, C.K. Williams, and S.S. Iyer, Thin Film Structure to Reduce Radiation Damage in X-ray Lithography, J. Vac Sci. Technol. B 5 (1), Jan/Feb 1987. 61.
Reisman A., C.K. Williams, and I.R. Maldonado, Generation and Annealing ot Defects in Silicon Dioxide, J. Apple. Phys, 62 (3), Aug. 1, 1987, pp 868-874.
62. Trang, D.D., E. IHackbarth, and J.R. Maldonado, The Effects of X-rays on p-n Junction Leakage Currents, IEEE Transactions on Electron Devices, Vol. 36, No 1I, Nov. 1989, pp 2587-91. 63. Reisman, A., and C.i. Merz, I. Electrochem. Soc. Vol 130, 1384, (1983). 64. 11su, C.I., L. K. Wang, J. Y-C Sun, M. R. Wordeman and T. I. Ning, Hlot electron induced instability in 0.5ym CMOS patterned using synchrotron x-ray lithography, Proceeding 1989 International Reliability Physics Symposium, Phoenix, AZ. 65. Wilson, C.G., 'Organic Resist Materials' in Introduction to Microlithography, Edited by L.J. Thompson, C.G. Wilson, and MI. Bowden. 66. Sachdev, If., W. Bruns, R. Kong, W. Montgomery, W. Moreau, K. Welsh, R. Kvitek, and W. Conley, Ultrasensitive Chemically Amplified Resist Systems, Microelectronic Engineering 13, (1991), Elsevier.
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67. W. Conley, Proc. SPIE Conf., San Jose, March 1991, to be published. 68. Maldonado, J.R., X-ray lithography system development at IBM: Overview and status, Proc. SPIE Conf., San Jose, March 1991, to be published. 69. Wagner, A., and J.P. Levin, The kinetics of Ion beam Deposition, J. Vac. Sci. Technol., B 7 (6), Nov/Dec.1989. 70. Vladimirsky, Y., and J.R. Maldonado, Illumination Effects on Image Formation in X-ray Proximity Printing, Microelectronic Engineering 13, (1991), Elsevier. 71.
Lin, B.J., Proc. SPIE Vol 1263, (1990), p80.
72. Oertel, H.K., M. Weiss, H.L. Iluber, Y. Vladimirsky, and J.R. Maldonado, Modelling of Illumination Effects on Resist Profiles in X-ray Lithography, paper presented at SPIE 91, March 1991, to be published. 73. Early, M.L. Schattengburg, and H. Smith, Absence of Resolution degradation in XRL for A from 4.5 rm to 0.83 nm, Proc. of Microcircuit Engineering 89, Cambridge, England, 26-28 Sept. 1989. 74. Hawryluk, A. N. Ceglio, and D. Gaines, Reflection Mask Technology for X-ray Projection Lithography, J. Vac. Sci. Technol., B 7 (6), Nov/Dec. 1989. 75. Kinoshita, H. et al., "Soft X-ray Reduction Lithography Using Multilayer Mirrors", J. Vac. Sci. Technol., B 7 (6), Nov/Dec.1989.
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AN ADAPTIVE NEURAL NETWORK FOR COMPUTATION OF PROXIMITY-EFFECT CORRECTIONS Robert C. Frye, Edward A. Rietman and Kevin D. Cummings* AT&T Bell Laboratories, Murray Hill, New Jersey 07974 We have used a neural network to compute corrections for images written by electron beams to eliminate the proximity effects caused by electron scattering. Optimal local changes in the incident beam dose, found iteratively, require a prohibitively long time to compute for realistic pattern sizes. We have instead trained a neural network to perform equivalent corrections, resulting in a significant decrease in computation time. We have examined hardware implementations of the networks for this application using both analog and digital electronic networks. Although analog hardware is potentially faster, the digital network has the advantage of being more flexible. Both networks had an acceptably small error of 0.5% compared to the results of the iterative computation. Additionally, we verified that the neural network correctly generalized the solution of the problem to include patterns not contained in its training set. We have experimentally verified this approach on a Cambridge Instruments EBMF 10.5 exposure system. INTRODUCTION Scattering imposes limitations on the minimum feature sizes that can be reliably obtained with electron beam lithography. Linewidth corrections can be used to control the dimensions of isolated features (i.e. intraproximity, Sewell, 1978), but meet with little success when dealing with the same features in a practical context, where they are surrounded by other features (i.e. interproximity). Local corrections have been proposed using a self-consistent method of computation for the desired incident dose pattern (Parikh, 1978). Such techniques require inversion of large matrices and prohibitive amounts of computation time. Lynch et aW.,1982, have proposed an analytical method for proximity corrections based on a solution of a set of approximate equations, resulting in a considerable improvement in speed. The method that we present here, using a neural network, combines the computational simplicity of the method of Lynch et al. with the accuracy of the self-consistent methods. The first step in this method is to determine the scattered energy profile of the electron beam which depends on the substrate structure, beam size and electron energy. This is then used to compute spatial variations in the dosage that result when a particular image is scattered. This can be used to iteratively compute an optimal corrected image for the input pattern. The goal of the correction is to adjust the written image so that the incident pattern of dose after scattering *
Present address: Motorola Inc. Phoenix Corporate Research Laboratories, 2100 East Elliot Rd. Tempe, AZ 85284.
101
approximates the desired one as closely as possible. We have used this iterative method on a test image to form a training set for a neural network. The architecture of this network was chosen to incorporate the basic mathematical structure as the analytical method of Lynch et aL, but relies on an adaptive procedure to determine its characteristic parameters. The advantage of this method is that the neural network "learns" to perform a correction that closely approximates the optimal one. The advantage of the network over the iterative computation, however, is that it is much faster. CALCULATING PROXIMITY CORRECTED PATTERNS We determined the radial distribution of scattered dose from a single pixel by using a Monte-Carlo simulation for a variety of substrates and electron beam energies (Cummings, 1989). As an example problem, we first looked at resist on a heavy metal substrate. (These are of interest in the fabrication of masks for x-ray lithography.) For a 20 KeV electron beam this distribution, or "proximity function," could be approximated by the analytical expression
f(r) = f
1
7)=1~+v+ý) [
e -(,/U)2 ve-("r) a 2 ++--2
+e-(//r-22
2.2
2ý2
a
2
where a=0.0381gm, y=0.045gm, 1=0.36gim, v=3.49 and =6.42. The unscattered image is represented by an array of pixels, I0(x,y). For a beam with a proximity function f(r) like the one given above, the image after scattering will be lo(x-m,y-n) f((m2 +n2 )A),
1.s(x, y)= mr-
n=--
which is the discrete convolution of the original image with the lineshape f(r). The approach suggested by analogy with signal processing is to deconvolve the image by an inverse filtering operation. This method cannot be used, however, because it is impossible to generate negative amounts of electron exposure. Restricting the beam to positive exposures makes the problem inherently nonlinear, and we must rely instead on an iterative, rather than analytical, solution. Figure 1 shows the pattern that we used to generate a training set for the neural network. This pattern was chosen to include examples of the kinds of features that are difficult to resolve because of proximity effects. The feature in the upper left is a variable gap, ranging from 0.87511m down to 0.125gtm in steps of 0.125gm. The group of rectangles in the top center are 0.5 gim wide with different spacings, ranging from 1Igm down to 0.25 gim. At the bottom are a variety of square windows and isolated squares, the smallest of which is 0.25 jim. Finally, the feature on the right is a proximity tester. It has a 0.25 pim gap that runs down a variable width feature. This tests the ability to compensate exposure for a gap that is near both large and small neighboring features. The full pattern was 180 x 180 pixels, for a total of 32,400 pixels. Pixel size was 0.125 jim square. For the purposes of computation and display, the incident dose was normalized to fall within a relative range from 0 to 255. Based on an idealized model of the resist, a target exposure for an exposed pixel was 128, corresponding to a 16% overdose to allow for processing tolerance. The target dose for unexposed pixels was 102
IIIII •1!1111 180
pk*
E
mL...___
Figure 1. Training pattern zero. The initial exposure pattern for the iterative calculation used a relative value of 128 for exposed pixels and 0 for unexposed ones. The scattered intensity distribution was computed from the incident dose using the discrete two-dimensional convolution with the summation truncated to a finite range, r 0 . For the example proximity function 95% of the scattered intensity is contained within a radius of 1.125 gim (9 pixels) and this value was used for r 0 . The scattered intensity distribution was computed and compared with the desired pattern of 128 for exposed and 0 for unexposed pixels. The difference between the resulting scattered and desired distributions is the error. This error was subtracted from the dose pattern to be used for the next iteration. However, since negative doses are not allowed, negative regions in the correction were truncated to zero for the corrected dose. Using this algorithm, a pixel that receives a dosage that is too small will have a negative error, and on the next iteration its intensity will be increased. Unexposed pixels (i.e. regions where resist is to be removed) will always have some dosage scattered into them from adjacent features, and will consequently always show a positive error. Because the written dose in these regions is always zero, rather than negative, it is impossible for the iterative solution to completely eliminate the error in the final scattered distribution. However, the overall exposure pattern and the resulting definition in the resist is considerably improved. Moreover, since all exposed features receive a uniform dose after correction, it is possible to choose a resist with the optimal contrast properties for the pattern. Figure 2 shows histograms of the dose received by pixels in the test image before and after the iterative correction. In an uncorrected image, the input dose for every exposed pixel is a uniform value, 116% in this example. After scattering, pixels which are nominally exposed will receive a range of doses as indicated in the figure. Some of the incident dose is scattered into adjacent pixels which are nominally unexposed, so they too have a distribution of exposures. For this particular test image, the tails of these two distributions overlap. Some nominally unexposed pixels receive a larger dose than nominally exposed pixels. Even a resist with infinite contrast could not properly resolve such an image.
103
L0 -LJ
X a 0r Lý C,
wl a)
RELATIVE DOSE M%)
Figure 2. Histograms showing the dose received by pixels in the test image before (above) and after (below) the iterative correction. The dotted lines show the distribution of the input image, solid lines are the distributions after scattering. The effect of the correction is to pre-bias the input dose distribution so that after scattering, nominally exposed pixels receive a more uniform dose. Because negative exposure levels are not possible, we are still left with unwanted exposure in the surrounding areas, but the distributions of dose for nominally exposed and unexposed pixels no longer overlap. The correction opens up a "process window", and it is then possible to resolve the image with a finite contrast. The corrected distribution shown in the lower part of Figure 2 resulted after four iterations of the test image. Further iterations can make the distribution for exposed pixels more narrow, but this would result in only a small marginal increase in the process window. Although this iterative method is effective, it is also time consuming. Each iteration on the test pattern of 32,400 pixels required about 1 hour to run on a 386 based computer. Four iterations were required before the smallest features in the resist were properly resolved. The overall time corresponds to 0.44 seconds for each pixel. Even the expected order of magnitude speed increase from a large mainframe computer is not sufficient to correct the image from a full sized chip consisting of several billion pixels. The purpose of the neural network is to do these same 104
calculations, but in a much shorter time. THE NEURAL NETWORK ARCHITECTURE AND TRAINING Figure 3 shows the relationship between the image being corrected and the neural network.
Figure 3. Network configuration The correction for one pixel takes into account the image being written into a large number of the other surrounding pixels. Since the network must take into account all of the surrounding pixels that contribute appreciable scattered intensity to the central pixel being corrected, the size of the network was determined by the same maximum radius, r0 = 1.125txm, that characterized the scattering proximity function. This required that the pixel be computed from the center of a 19 x 19 pixel array (i.e. the central pixel and 9 pixels in each direction). This means that for this particular problem the neural network must have 361 inputs. This would be difficult to manage in an analog network if these inputs were general analog signals, but fortunately the input data, consisting of exposed and unexposed pixels, are binary. Furthermore the fixed relationship between each pixel and its neighbors makes it possible to load the input signals into an analog network using digital shift registers. The input in Figure 3 can be loaded as a digital block of 19 words each 19 bits long. Each time a new 19 bit word is shifted into the registers, the pixel to be computed shifts by one position. Figure 4 shows a schematic diagram of the analog network. The binary signals from the shift registers representing a portion of the image were connected to the buffer amplifiers through 10 KQ) resistors. Each was connected to only one summing node, corresponding to its radial distance from the center pixel. This stage converted the 19 x 19 binary representation of the image into 10 analog voltages that represented the radial distribution of the surrounding intensity. The summing amplifier at the output was connected to these 10 nodes by variable resistors. This resulted in an output that was a weighted sum of the radial components. 105
tcad -sigf 1
0 0 1
oatalo
Uinary o 11 inputs WrPY) 0 0 0 0
Figure 4. Schematic diagram of the analog network Functionally, this network does the operation 9
Volt =
w
, 1=0
where Wr are the weight coefficients set by the adjustable resistors and r are the average values of the pixel intensity at radius r. The form of this relationship is identical to the one proposed by Lynch et al. but uses an adaptive method, rather than an analytical one, to determine the coefficients wr. The prototype analog hardware network was built on a wire wrap board using 74HC164 8 bit CMOS static shift registers and LM324 quad operational amplifiers for the active devices. The resistors in the first layer were 10 KO) thin-film resistors in dual-in-line packages and had a tolerance of 1%. The ten adjustable resistors in the second layer of the network were 10 turn precision trimmers. Negative weights were made by inverting the sign of the voltage at the buffer amplifiers. The digital inputs to the network were generated by the computer (an AT&T 6386, 16MHz) which was interfaced to the network through a QuaTech PXB 721. A QuaTech ADM8-10 8 bit A/D converter was used to read the analog output of the network back into the computer for storage and analysis. For comparison, we also evaluated a digital hardware implementation of this network. It was implemented on a floating point array processor built by Eighteen Eight Laboratories using an AT&T DSP-32 chip operating at 8 MFLOPs peak rate. The mathematical operation performed by the network is equivalent to a twodimensional convolution of the input image with an adaptively learned floating point kernel. The adjustable weight values for both networks were determined using the delta rule of Widrow and Hoff (1960). For each pixel in the trial pattern of Figure 1 there was a corresponding desired output computed by the iterative method. Each pixel in 106
the test image, its surroundings and corresponding analog corrected value (computed by the iterative method) constituted a single learning trial, and the overall image contained 32,400 of them. We found that the weight values stabilized after two passes through the test image. NEURAL NETWORK PERFORMANCE The accuracy of both the analog and digital networks, compared to the iterative solution, was comparable. Both showed an average error for the test image of 0.5%, and a maximum error of 9% on any particular pixel. The maximum occurred in calculating the exposure level in the quarter-micron square feature, for which the network's response was consistently low. This was because the network was linear and the iterative method apparently resulted in some nonlinearity in these regions. It is likely that a larger, nonlinear network would eliminate this problem, but in this particular example the worst level of error was small enough to be well within the 16% overdose. The actual response of the neural network and ideal dose computed by the iterative method correspond almost exactly in most other places. The accuracy of the networks on images other than the one used to train them was comparable, averaging about 0.5% overall. As previously mentioned, the network corrects the image by performing a twodimensional convolution with an adaptively-learned kernel. This method itself is an efficient computational algorithm. The iterative method required 4 hours to compute the correction for the 32,400 pixel example. Equivalent results were obtained by convolution in about 6.5 minutes using the same computer. This corresponds to 0.012 seconds per pixel. Examination of the assembled code for the software network showed that the correction for each pixel required the execution of about 30 times fewer instructions than for the iterative method. The analog hardware generated corrections for the same example in 13.5 seconds. From one pixel to the next the computer measured the network's output, called the next 19 bits from an array that contained the image, and presented them as inputs from the computer to the network. These operations required a total of 356gpsec. The time that elapsed from clocking the inputs into the network until the analog computation was completed was about 18gtsec. Almost 95% of the computational time was used for input/output operations between the network and the computer. It was the time required for the 1/0, rather than the speed of the circuit, that limited the dynamic performance of this system. Clearly, with improved I/O hardware, the analog network could be made to compute these corrections much more quickly. The same algorithm, running on the digital floating point array processor performed the correction for this example problem in 4.5 seconds. The factor of three improvement over the analog hardware was primarily a result of the decreased time needed for I/O in the DSP-based network. The digital network was not appreciably more accurate than the analog one, indicating that the overall accuracy of operation was determined primarily by the network architecture rather than by limitations in the implementation. Table 1 shows a comparison of the speed of various methods that we used for for these corrections. These results have been normalized to indicate the correction time per unit area.
107
TABLE 1. Comparison of computational speed for various methods. METHOD
SPEED
Iteration Software network Analog hardware network Digital hardware network
6 years /mm' 2 100 days /mm 2 2 days /mm 2 /mm hours 18
EXPERIMENTAL VERIFICATION Recently, we have evaluated this method experimentally using a Cambridge Instruments EBMF 10.5 exposure system (Cummings, et al., 1990). The test image was 1 mm 2 and contained 11,165 Cambridge shapes and 6.7x10 7 pixels. The substrate was silicon with 0.5 gm of SAL6O1-ER7 resist exposed at 20 KeV beam energy. The range of the scattered electrons for these conditions is more than three times greater for these conditions than in the tests described above, requiring a network about ten times larger. The neural network computations were done using the digital floating point array processor, and required about 18 hours to correct the entire image. Input to the program was Cambridge source code, which was converted to a bit-mapped array, corrected by the neural network and then decomposed into new Cambridge source code. Figure 5 shows SEM micrographs comparing one of the test structures written with and without the neural network correction.
Figure 5. Comparison of a test structure written (a) without and (b) with neural network proximity-effect correctio This test structure consists of a 10 gim square pad next to a 1 gim wide line, separated by a gap of 0.5 tim. Note in the uncorrected pattern that the line widens in the region adjacent to the large pad, and the webs of resist extending into the gap. This is caused by excess dosage scattered into these regions from the large pad. In the corrected pattern, the dosage in these regions has been adjusted, resulting in a uniform exposure 108
after scattering and greatly improved pattern resolution. CONCLUSIONS The results of our trial experiments clearly demonstrate the computational benefits of a neural network for this particular application. The trained analog hardware network performed the corrections more than 1000 times faster than the iterative method using the same computer, and the digital processor was 3000 times faster. This technique is readily applicable to a variety of direct write exposure systems that have the capability to write with variable exposure times. Implementation of the network on more sophisticated computers with readily available coprocessors can directly lead to another order of magnitude improvement in speed, making it practical to correct full chip-sized images. We are presently developing the software for such a system. The performance of the analog network suggests that with appropriate modifications to improve the speed of 1/0 between the computer and the network, it would be possible to obtain even faster operation with an analog network. The added flexibility and availability of digital systems, however, is a considerable advantage, as is the relatively low cost of a general purpose digital coprocessor. ACKNOWLEDGMENTS We would like to thank S. Waaben and W. T. Lynch for useful discussions, suggestions and information, and J. Brereton who assisted in building the hardware and generating trial patterns for the initial evaluation. We also thank C. Biddick, C. Lockstampfor, S. Moccio and B. Vogel for technical support in the subsequent experimental verification. REFERENCES [1] [2] [3] [4] [5] [6]
H. Sewell, "Control of Pattern Dimensions in Electron Lithography," J. Vac. Sci. Technol. 15, 927 (1978). M. Parikh, "Self-Consistent Proximity Effect Correction Technique for Resist Exposure (SPECTRE)," J. Vac. Sci. Technol. 15, 931 (1978). W.T. Lynch, T. E. Smith and W. Fichtner, "An Algorithm for Proximity Effect Correction with E-Beam Exposure," Int'l. Conf. on Microlithography, Microcircuit Engineering pp 309-314, Grenoble (1982). K. D. Cummings "Determination of Proximity Parameters for Electron Beam Lithography," AT&T Bell Laboratories Internal Memorandum. B. Widrow and M. E. Hoff, "Adaptive Switching Circuits," IRE WESCON Convention Record, Part 4, 96-104 (1960). K. D. Cummings, R. C. Frye and E. A. Rietman, "Using a Neural Network to Proximity Correct Patterns Written with a Cambridge EBMF 10.5 Electron Beam Exposure System," Applied Phys. Lett. 57 1431 (1990).
109
THE CHEMISTRY AND PROCESS CHARACTERISTICS OF CHEMICALLY AMPLIFIED POSITIVE RESIST MATERIALS Omkaram Nalamasu and Anthony E. Novembre AT&T Bell Laboratories, Murray Hill, New Jersey 07974 Chemically amplified resists are a new class resist of materials that meet the low absorption and high sensitivity requirements of the new lithographic tools that in general have low brightness sources. This paper details the chemistry and process characteristics of a class of chemically amplified resist materials based on poly(t-butoxycarbonyloxystyrenesulfone) (PTBSS) copolymers with or without any added photo- (or radiation) acid generators. These resist systems exhibit sub-0.5 itm resolution, high contrast, sensitivity and good process latitude. INTRODUCTION In order to reap the full potential of new lithographic technologies necessary for sub-0.5 gim lithography, new resist materials and processes need to be developed. Several chemically amplified systems have been reported since the conception of chemical amplification for microlithographic applications [1-3] to meet the high sensitivity requirements of the new lithography tools. The inherent sensitivity characteristic to most chemically amplified systems emanates from the catalytic action of the photolytically generated acid during the post-exposure baking (PEB) step. The differential solubility introduced as a result of acid catalyzed reaction during the PEB can be utilized to make the resist develop in a negative or positive mode. The process flow (Table I) for these new materials is essentially similar to that for conventional positive resists although the post-exposure bake assumes a different role. We have recently introduced a class of chemically amplified positive acting resist formulations based upon a poly(t-butoxycarbonyloxystyrene-sulfone) (PTBSS) matrix polymer with (or without) several ionic and non-ionic acid generators for deep-UV [4, 5], and X-ray [6, 7] lithography applications (scheme I). The introduction of sulfur dioxide into the copolymer backbone not only improved the T. (glass transition temperature) and adhesion properties of the polymer but also improved the sensitivity to deep-UV, e-beam and x-ray wavelengths due to the C-S bond scission [7]. The C-S bond scission reduced the molecular weight of the polymer and generated sulfinic and sulfonic acid moieties that subsequently aided the photogenerated acid from the PAG in the deprotection of t-Boc groups during the PEB to improve the deep-UV sensitivity [8]. The quantum efficiency of the scission process is much more facile at x-ray wavelengths (4-20X) and consequently the copolymer itself (without any added PAG) acts as a very sensitive and high resolution single component positive resist [7].
110
The deep-UV resist formulations made with the onium salt photoacid generator triphenyl sulfonium hexafluoroarsenate (43SAsF6) exhibit sub-half micron resolution, excellent sensitivity and good process control with respect to process parameters such as prebake, exposure, PEB and development but suffer from three major deficiencies: 1) presence of a metal ion in the resist (As) that is perceived to be a device contaminant,
2) severe dependence of process performance on the elapsed time between exposure and PEB process steps (post-exposure time delay) and 3) large initial resist thickness loss during the pattern transfer into the substrate [4]. Preliminary lithographic characteristics of PTBSS copolymer with nitrobenzyl ester based, non-ionic, all-organic PAG materials was discussed recently for deep-UV lithography [5]. This paper details the chemistry and process development efforts to address these issues with the all-organic, metal-ion free resist materials for deep-UV, ebeam and x-ray lithographies. EXPERIMENTAL Materials Preparations Poly(t-butoxycarbonyloxystyrene-sulfone) copolymers were prepared by thermally and photo initiated solution polymerization methods. Copolymers of different compositions (t-Boc styrene (TBS):SO 2 ) and weight average molecular weights (Mu) were synthesized by adjusting the reactant and/or initiator feed ratio and by varying the polymerization reaction conditions, respectively. The organic PAG materials were prepared as previously reported [9]. Materials Characterization The molecular size and distribution of PTBSS copolymers were determined by high pressure size exclusion chromatography (HPSEC). Copolymer compositions were determined by x-ray fluorescence spectroscopy (XFS) and a variety of analytical techniques that include infra red (IR), 13 C and 1 H nuclear magnetic spectroscopy (NMR) spectroscopy, ultraviolent (UV) spectroscopy, and y-radiolysis were used to characterize and analyze the organic PAG materials, copolymers, resist solutions, as well as their photoproducts. Lithography The resist solution for deep-UV applications were prepared by dissolving the matrix copolymer, PTBSS (10-20 wt%) and 6 mole % of appropriate organic photoacid generator in a spinning solvent and were subsequently filtered 3 times through a stack of 1.0, 0.5 and 0.2 lim Teflon® filters. The resist solutions for x-ray and e-beam applications were prepared by simply dissolving copolymers in the spinning solvent. Resist films in the range of 0.4-1.1 g.tm were spun coated on the substrates by using spin speeds in the range of 2000-5000 rpm. A thin overcoat layer was applied on top of the resist for deep-UV applications [5]. The substrates were primed with HMDS 111
(hexamethyldisilazane) on wafer track or in a YES (Yield Engineering System, Inc.) oven prior to resist application. Film thicknesses were measured using a Sloane Dektak model HA or Tencor Alpha Step 200 profilometer and a Prometrix Spectra Map SM 200 interferometer. The resist and overcoat applied substrates were exposed to 248 nm radiation using a GCA Laserstep® prototype deep-UV exposure system with an NA--0.35 lens and 5X reduction optics. X-ray (X = 4-20 A centered @ 14 A) exposures were performed in helium on a Hampshire Instruments series 5000 point source proximity print stepper. The laser pulse rate was set at 0.3 Hz and the flux was measured to be between 0.3-0.6 mJ/cm 2 /pulse. An x-ray mask having a structure consisting of a 0.4 ptm gold absorber layer on top of a 1.0 pgm polysilicon membrane was used for patterning purposes. Electron-beam exposures were performed using a Cambridge EBMF model 10.5 vector scan system operating at 30 kV, 2.048 nm field size, 1.0 nA spot current and 0.0625 address. The resist films were post-exposure baked at 115'C/30 sec for deep-UV applications and at 120-1400C for 2.5-4.0 min. for x-ray and e-beam lithography. The delay time between exposure and PEB was varied from 1-30 mins. and its effects were characterized by linewidth measurements and image quality. The development was typically done in a 0.17 N TMAH (tetramethyl ammonium hydroxide) solution for 30 seconds. The minimum dose (D.) necessary to completely solubilize a 100 x 150 gm area was the reported sensitivity. A Hitachi model 570 or a Jeol model 35CFS was used to take photomicrographs of the developed images. RESULTS & DISCUSSION Effect of Copolymer Molecular Properties The molecular weight and composition of copolymer showed no noticeable effect on the sensitivity but affected resolution when tested in conjunction with onium salt or nitrobenzyl ester PAG materials in the deep-UV experiments [4, 10]. The resolution, however, was a function of copolymer molecular weight, degrading from < 0.5 gm when MK was 100,000 to 0.6 gm when MK was 540,000 g/mole. A copolymer of 200,000 Mw and 3:1 (TBS:SO 2 ) composition was used for optimization of the deep-UV process. In contrast, the resolution of copoloymers to x-ray lithography was independent of its molecular weight in the investigated 1-9 x 10- Mw range. The copolymer molecular composition, however, had a profound effect on the e-beam and x-ray response of these materials (Table II). Increasing the sulfur dioxide content of copolymer enhanced the sensitivity of both e-beam and x-ray exposures but the effect was much more pronounced for the x-ray exposures.
112
For example, increasing the sulfur dioxide molar content from 21.1% (3.75:1) TBS:S0 2 ) to 36.4% (1.75:1, TBS:SO2 ) dramatically enhanced the x-ray sensitivity (D.), from 40 to 10 mJ/cm 2 . The homopolymer, poly(t-butoxycarbonyloxystyrene) (PTBS), in contrast, exhibits no sensitivity even at x-ray doses exceeding 100 mJ/cm 2 . Similar results were obtained for e-beam exposures as well. The sensitivity improved from 100 gC/cm2 to 60 jtC/cm 2 over the same compositional range. The homopolymer did not demonstrate any thickness loss or aqueous base solubility even after exposure to 300 g±C/cm 2 . The homopolymer exhibited a 3% loss in thickness at a dose of 120 mJ/cm 2 during x-ray exposure and showed no further thickness loss after the PEB step indicating that the loss was due to partial t-Boc deprotection and that no acidic species were generated during exposure. No measurable thickness loss was observed in the nominally unexposed regions indicating that the PEB was done below the resist decomposition temperature. RESIST CHEMISTRY PTBSS undergoes t-Boc deprotection in the 155-180*C range to yield poly(hydroxystyrenesulfone) (PHSS). In the presence of acid, t-Boc deprotection is catalytically achieved at much lower temperatures. In deep-UV formulations, a PAG molecule that is capable of generating a strong acid upon photo excitation is added. This photogenerated acid then catalyzes deprotection during a PEB to generate PHSS. PTBSS is insoluble in aqueous base whereas PHSS is extremely soluble in base and thus generates positive tone images upon development. The copolymer itself also undergoes main chain scission albeit with low efficiency during deep-UV exposures. The sensitivity of 2.1:1 (TBS:SO2 ) copolymer as a single component resist was -1 J/cm2 . The homopolymer (PTBS), however shows no appreciable thickness loss even at doses exceeding 1.5 J/cm 2 . Introduction of sulfur dioxide in similar systems was shown to effect improved sensitivity for e-beam and deep-UV exposures [11]. PEB is one of the most critical parameters in chemically amplified resist systems. The loss of the protecting group (t-Boc) occurs during this step and is exposure dose dependent. Maximum thickness loss during the PEB is -35%-40% in these systems corresponding to the t-Boc group concentration. Essentially >95% deprotection is necessary to cause aqueous base solubility leading to the high contrast of the development mechanism [3]. PTBSS copolymer acts as a highly sensitive x-ray and moderately sensitive ebeam single component high resolution positive resist. Scheme II depicts proposed x-ray and e-beam induced chain scission and subsequent acid generation mechanisms. Exposure to these high energy radiation results in benzylic and sulfinyl radical moieties. The sulfinic radicals by means of hydrogen abstraction and other reactions form sulfinic and sulfonic acid moieties at chain terminii. Another source of acid may result from the reaction of sulfur dioxide, also, a possible chain scission product, with water to form sulfurous or sulfuric acid. 113
The t-Boc deprotection after PEB was monitored by IR spectra and evidence for main chain scission and acid formation was obtained from f-radiolysis, molecular weight determination and titration methods [7]. LITHOGRAPHIC PERFORMANCE Surface Inhibition Effects Irrespective of the use of metal-ion free or metal-ion containing PAG materials, PTBSS resist formulations exhibited a growth in surface residue with the introduction of a time delay between exposure and PEB steps in the deep-UV experiments [4, 51. This growth is purely a surface phenomenon and was found to be post-exposure delay time dependent. The organic PAG resist materials while solving the metal-ion issue, are far from ideal with respect to alleviating the time delay effects [5]. We have previously shown that the growth of surface inhibition layer (or "skin") was the result of incomplete deprotection of the t-Boc groups at the resist surface. Parts per billion (ppb) levels of basic contaminants such as HMDS (hexamethyldisilazane) in the processing environment profoundly deteriorated the post-exposure time delay latitude by neutralizing the photogenerated acid at the resist surface [5]. Since the origins of the surface inhibition problems were traced to acid deactivation by bases, it is conceivable that resist formulations that generate weaker acids should be less susceptible to these effects. Weaker acids, relative to acids generated from most common onium salts, produced from organic PAG formulations are indeed more tolerant to these surface inhibition effects, but the time delay latitude available is still not sufficient to define a robust and reproducible process. Several organic PAG materials that generate very weak acid materials are known [121 but require prohibitively high doses to cause full deblocking of protecting groups to generate positive tone images. E-beam and x-ray resist exposures, surprisingly, were not subject to any time delay induced surface inhibition effects in the investigated 30 min. time delay. The linewidth and image quality, within experimental error, were essentially independent of the time delay for, at least, pp to 30 mins. No effort was made to determine the effect of much longer time delays. One explanation that can rationalize the discrepancy between deep-UV and x-ray, e-beam exposures is that the sulfinic acid generated from the main chain scission during the e-beam and x-ray exposure of PTBSS is considerably weaker than the acids (lower pKa) generated from deep-UV PAGs. Also, if it is bound to the chain terminus, as the mechanism proposes, it will be non-volatile and relatively immobile. These weaker acids need much stronger thermal activation (PEB=140'C/2.5 mins.) to attain the high sensitivity achieved than is required for deep-UV exposures, but provide a resist system that is fairly insensitive to environmental effects and thermally induced migration effects. The amounts of acid produced in y-radiolysis and deep-UV systems were calculated to be in the 10-5 10-6 mmol range per wafer and are very similar. 114
Overcoat Development A family of overcoat materials that are acidic, water soluble, stable and transparent to 248 nm radiation were designed and synthesized. Application of thin layers of overcoat
materials over the resist isolated
the resist surface from the
environment by quenching the airborne basic contaminants. The resist surface became essentially insoluble in 5-10 rins. post-exposure delay without the overcoat due to environmental deactivation. No change in solubility was evident even after 1-2 hour time delay with the application of overcoat. Dramatic improvements in linewidth stability were also evident with the overcoat application [5]. Process Performance The optimized all-organic deep-UV resist formulations exhibit 0.30 gm resolution in 1 gm thick film at 20-30 mJ/cm 2 exposure dose (Fig. 1). The process with the overcoat exhibits no dependence on post-exposure time delay for at least up to 15 minutes. The sensitivity of the resist is both PEB parameter and PAG material dependent. The process capability of the resist is listed in Table III. PTBSS copolymers are highly sensitive x-ray resists but are only moderately sensitive e-beam resists even with very aggressive PEB conditions. Exposure to e-beam under very high vacuum conditions may deplete SO 2 , one of the two main sources of acid generation, thus accounting for its poor performance. Preliminary x-ray lithographic evaluation demonstrated 0.4 jim resolution in 2.1:1 (TBS:S0 2 ) copolymer at a dose of 25 mJ/cm 2 (Fig. 2). E-beam exposures of the same copolymer showed 0.25 jim resolution at a dose of 90 gC/cm2 @ 30 kV (Fig. 3). SUMMARY Copolymers of t-Boc styrene and sulfone are very sensitive x-ray (-10 mJ/cm 2 ) and moderately sensitive e-beam (90 jiC/cm 2 @ 30 kV) chemically amplified high resolution positive single layer resists. The sensitivity of the copolymers was a function of molecular composition and improved with increasing sulfur dioxide content. The sensitivity and resolution of the copolymer were independent of its molecular weight or polydispersity. The acid generation upon exposure to radiation was traced to C-S bond scission by molecular weight analysis and was confirmed by titration methods and lithographic analysis. These resist systems exhibited 0.25 jim resolution in e-beam exposures and 0.5 gim resolution in x-ray exposures. These materials are poor deep-UV resists and require >1 J/cm 2 doses. They are very sensitive to deep-UV radiation with the addition of an onium salt or nitrobenzyl ester (covalent) PAG molecule. Process optimization efforts were concentrated on metal-ion-free and non-ionic PAG resist formulations. These resists exhibit 0.3 Jim resolution in 1 jim resist film at a sensitivity of 20-30 mJ/cm 2 with good process latitude. 115
REFERENCES [1]
J. V. Crivello, in "Polymers in Electronics", ACS symposium Series 242, Davidson, T. Ed., ACS, Washington, D.C., 1984, pp. 3-10.
[21
H. Ito and C. G. Willson, ibid, pp. 11-23.
[3]
E. Riechmanis, F. M. Houlihan, 0. Nalamasu, T. X. Neenan, Chemistry of Materials,accepted for publication.
[41
0. Nalamasu, M. Cheng, J. M. Kometani, S. Vaidya, E. Reichmanis and L. F. Thompson, Proc. SPIE, 1262, 32 (1990).
[5]
0. Nalamasu, E. Reichmanis, M. Cheng, V. Pol, J. M. Kometani, F. M. Houlihan, T. X. Neenan, M. P. Bohrer, D. A. Nixon, L. F. Thompson, C. Takemoto, Proc. SPIE, 1466, in print.
[6]
A. E. Novembre, W. W. Tai, 0. Nalamasu, J. M. Kometani, F. M. Houlihan, T. X. Neenan and E. Reichmanis, ACS Polymer Prints, 31 (2), 379 (1990).
[7]
A. E. Novembre, W. W. Tai, J. M. Kometani, J. Hansen, 0. Nalamasu, G. N. Taylor, E. Reichmanis, L. F. Thompson, Proc.SPIE, 1466, in print.
[8]
R. G. Tarascon, E. Reichmanis, F. M. Houlihan, A. Shugard, L. F. Thompson, Polym. Eng. Sci. 29, 850, 1989.
[91 T. X. Neenan, F. M. Houlihan, E. Reichmanis, J. M. Kometani, B. J. Bachman, L. F. Thompson, Proc. SPIE, 1086, 1, 1989. [10]
J. M. Kometani, 0. Nalamasu, E. Reichmanis, R. S. Kanga, L. F. Thompson, S. Heffner, J. Vac. Sci. and Technol. B, 8 (6), 1428, 1990.
[11]
M. J. Bowden, E. A. Chandross, J. Electrochem. Soc., 122, 1370, 1975.
[12]
T. X. Neenan, F. M. Houlihan, E. Reichmanis, J. Kometani, B. J. Bachman, L. F. Thompson, Macromolecules,23, 145, 1990.
116
TABLE I. Process Flow for Chemically Amplified Resists. Spin Coat Prebake Exposure Post-Exposure Bake Development Rinse TABLE IL Effect of Copolymer Molecular Properties on Lithographic Performance. Molecular Molecular Composition Weight Molecular (TBS:SO 2 ) Weight Dispersity T9 g/mole
Sensitivity (D,) x-ray
e-beam
deep-UV
(mr/cm 2 ) (jtC/cm2 ) (mJ/cm 2 ) 1.75:1 2.1:1 2.8:1 3.75:1 1:0
3.53 4.74 2.14 2.50 1.07
2.70 1.88 1.89 1.98 1.60
168 165 159 151
10 20 30 40 > 120 b
nd 60 80 100 >300c
nd -1000a nd nd >1500
aPEB conditions were 140'C/2.5 mins. b showed 3% thickness loss during exposure and lost no further thickness during PEB. CWas insoluble even with 300 pC/cm 2 dose. nd = not determined TABLE Ill. Process Capabilities of Deep-UV Resist. Thickness Uniformity Resolution Sensitivity Linewidth Control Exposure Latitude Focus Latitude Thermal Stability
3a < 20X 0.30 gtm line/spaces (in 1 gim film) 0.40 ptm contact holes 20-30 mJ/cm 2 < 0.05 gim (for 0.5 gim feature) ±13% for 10% CD (0.5 jim feature) ±0.75 jim for 10% CD (0.5 pim feature) _>140 0 C 117
-(CH-CH
2
)_--(SO
2
-
-- (CH-CH2),-(SO2-CH-CH ),2
CH-CH2 ),j-
H
# c=O I
t-BOC
C=O I
I
o
OH
OH
POLY (HYDROXYSTYRENE-SULFONE)
0I
PHSS
H3 C-C-CH3
H 3 C-C-CH3
/
I
CH3
Ph3 S +ASF- ONIUMSALT PHOTOACID GENERATOR
CH3
N_2
._
NITROBENZYL
(POLY(t.BUTOXYCARBONYLOXYSTYRENE-SULFONE) PTBSS
Scheme I.
x
CH2 -O-SIt 0
y
ESTER PHOTOACID GENERATORS
Schematic representation of a chemical amplification scheme based on poly(t-butoxycarbonyloxystyrene-sulfone) with onium salt and nitrobenzyl ester photoacid generators.
H
H O
H
I 1 I1 _CC--S_ 0
H 0
1
0
H
1 1 -C--C*
H
H
II .S_
I I C=C
l
0
0 6-
+ so2
7, X-ra0y 0o
. (H*)
I
Scheme II.
o
I 0
0
I (OH2)2 C
CI (at 2 )3
I (OH C 2 )2
I
E-beam and x-ray induced chain scission and acid generation in PTBSS copolymers.
118
Figure 1.
SEM picture of 0.30 jim line/space pairs in I jim thick resist exposed (dose-- 30 mJ/cm) at 248 nm using a GCA laserstep prototype deep-UV stepper with a NA = 0.35 lens and 5X reduction optics.
0.3 /im
Figure 2.
SEM picture of coded 0.4 gim line/space pairs in I pm thick resist exposed using an X-ray dose of (X = 14A) 25 mJ/cm 2.
COOED 0.4 Am LINE/SPACE
Figure 3.
CODED 0.25 um LINE/SPACE
119
SEM picture of coded 0.25 jim linelspace pairs in 1 gim thick resist exposed using an edose of beam 90 tC/cm 2 @ 30 kV.
A 0.4 gim CMOS TEST CIRCUIT COMPLETELY PROCESSED WITH 8-LEVEL X-RAY LITHOGRAPHY D. Friedrich, W.Windbracke, H. Bernt, G. Zwicker, P. Staudt-Fischbach, H.J. Schliwinski, P. Hemicker, P. Lange, M.Pelka Fraunhofer-Institut fOr Mikrostrukturtechnik (IMT) Dillenburger Str. 53, 1000 Berlin 33 Federal Republic of Germany Sub-0.5 lim CMOS devices have been successfully fabricated by means of X-ray lithography at all levels. This paper reports about the X-ray lithography characterization, the CMOS technology including electrical device performance and the influence of radiation induced damages on the transistor behaviour. The overlay of subsequent lithography levels was determined • 180 nm, 3 a with respect to X-ray mask copies with a mask distortion of 150 nm maximum. A linewidths variation in the poly-Si gate level of ± 50 nm could be achieved. The electrical devices have been characterized by static and dynamic measurements. NMOS and PMOS transistors exhibit no severe short channel effects for gate lengths down to 0.35 Ilm with a supply voltage of VD = 5 V.A stage delay time of 120 ps was measured at a 33 stage 0.45 ýim CMOS ring oscillator. Radiation damages have been evaluated by comparison of X-ray and optically processed transistors and reveal no drastical differences. INTRODUCTION The quarter micron CMOS generation probably will require X-ray lithography as a tool for pattern transfer in industrial mass production. For this goal four components have to be available: X-ray source, stepper, masks and resist. In general, the advantages of X-ray lithography compared to the optical lithography are, in addition to the resolution capability, the high depth of focus and the large exposure field size (10 cm 2). Contrary to this, the most critical point of this method is the mask in terms of pattern placement accuracy and defect density. Due to the technique of 1:1 shadow printing, the mask overlay requirement for a 0.25 g±m process is less than 100 rim, 3 a which has to be adjusted by an advanced stress engineering technique in the mask technology and a high precision stepper alignment. At the IMT in Germany, a state of the art X-ray lithography process has been established for test device fabrication on a laboratory scale with low integration density. Based on former developments of 4 level PMOS and NMOS processes /1,2/ a partially scaled 0.4 Vm CMOS process with 8 X-ray lithography levels was developed. 120
The primarily intention of our work is the evaluation of all X-ray lithography components in a complete CMOS process with regard to overlay and linewidths control. Furthermore, the influence of radiation induced damages on the device behaviour under the specific process conditions have been investigated. The process technology exhibits all features to fulfill the device requirements for a basic 0.4 gm CMOS process. No special emphasis was laid on advanced drain engineering for reduction of hot carrier effects. X-RAY LITHOGRAPHY All exposures have been carried out with synchrotron radiation in the spectral range of 0.8 ... 1.5 nm at the Bessy storage ring in Berlin. The mask wafer alignment was performed with a first generation stepper MAX 1 from Suss with an alignment accuracy of 150 nm, 3 a /3/. The X-ray masks used are X-ray copies of e-beam written master masks. Within the exposure field they consist of a 2 g±m highly B-Ge doped stress compensated Si membrane with electroplated 0.8 jam Au absorbers /4/. A positive tone, 3 component resist Ray/PF with chemical amplification from Hoechst company was used at all lithography levels /5/. The Ray/PF resist exhibits a high sensitivity of < 50 mJ/cm 2 , a resolution capability down to 0.2 lam and sufficient etch stability /6/. At all levels, the exposure time was approximately 30 sec per stepfield. Special emphasis was laid on the overlay and CD control. The overlay values measured on box in box patterns of subsequent lithography levels are listed in Table 1. They include all contributing error types, mainly mask distortions, alignment errors and linewidths variations and reveal _ 180 nm, 3 a at all levels. The pattern placement accuracy of the X-ray copies, which is the most contributing part of the overlay budged, has been determined to 150 nm maximum. With reduced influence on the overlay, a total linewidths variation of ± 50 nm could be achieved. A typical overlay diagram of the contact to Poly-Si gate level is shown in Fig. 1 with a deviation of 180 nm, 3 a within a 3 cm x 3 cm stepfield. Table 1:
Overlay values of subsequent lithography levels
Overlay
Lithography Level
mean (nm)
max m (nm)
LOCOS/P-Well
90
170
Poly-SI / LOCOS
85
160
Contact / Poly-Si
12C
180
Metal / Contact
10!
156
First results with the new Suss stepper XRS 200, which reproducible perform an alignment accuracy of 80 nm, 3 a, reveal an improved overlay of 160 nm, 3 a. A further improvement is expected by using master masks in121
stead of work copies. With a maximal master mask distortion below 120 nm and the XRS 200 alignment accuracy an overlay of about 140 nm, 3 cr could be realized.
Fig. 1:
Overlay diagram of the contact / Poly - Si level. The stepfield size is 3 cm x 3 cm DEVICE TECHNOLOGY
The process technology of the partially scaled 0.4 pgm CMOS process was developed at the IMT for evaluation of the X-ray lithography under realistic process conditions. An overview of the essential process steps is given in Table 2. Special interest has to focus on some process features, which distinctly influence the device performance. In order to improve the short channel behaviour of NMOS and PMOS transistors n+ and p+ poly gate technique was used, resulting in surface channel transistors for both types of devices. An appropriate channel doping concentration was realized by a dual channel implant for the p-well and nwell definition, leading to a retrograde doping profile. With a thermal budged reduction the junction depth of the p-well could kept below 1 gim. This technique allows to minimize the n+ - p+ spacing between LOCOS isolated different wells on 4 lim, under the condition of sufficient latch up hardness. The requirement of punch through reduction for channel lengths in the sub-0.5 tim range implies surface channel concentrations of approximately 2 x 1017 cm- 3 . This condition has been led to a gate oxide thickness of dox = 10 nm for a threshold voltage adjustment of VT = 0.7 V. The junction depth of the source/drain regions is in the order of 0.15 jim and 0.2 jim for NMOS and PMOS transistors, respectively. CoSi2 was used for the reduction of parasitic resistances down to 4 L/VE in the active areas and on p+ - n+ poly Si lines. A cross-section SEM picture, as shown in Fig. 2, demonstrates clearly the dimensions of a subhalf-pm transistor. 1Z2
Table 2: Essential CMOS technology steps
Lithography level
Critical dimension (Vm)
Process parameters
1. P-Well
>1
2. LOCOS
0.6
3. N-Well
>1
4. Poly-Si
0.4
5. P+
>1
6. N+
>1
As implant for source/drain and n+ poly-Si Tempering: 9000C, 30 min CoSi2 process
7. Contact
0.5
8. Metal
0.8
TEOS SiO 2 for isolation: 600 nm TiN thickness: 100 nm Al thickness: 800 nm Post metallization anneal: 4500C, 20 min
Dual boron implant for retrograde pwell Phosphorous field implant 0.5 Aim field-oxide thickness: Dual phosphorous implant for retrograde n-well Gateoxide thickness: 10 nm Poly-Si thickness: 250 nm TEOS spacer: 60 nm BF2 implant for source/drain and p+ poly-Si
Fig. 2: Cross-section of a 0.4 g~m NMOS transistor. The junction depth is about 0.15 jim.
123
DEVICE CHARACTERIZATION For the device characterization, both dynamic and static measurements have been performed. The 0.4 g±m NMOS and PMOS transistors behave according to the technology used in terms of static device characteristics, as depicted in Fig. 3. Transfer and drain curves exhibit sufficient short channel performance with punch through stability up to VD = 5 V and minor influence of DIBL (drain induced barrier lowering) effects in the sub-0.5 gIm channel lengths range. The use of Co salicidation technique introduces no additional drain leakage current in the n+ and p+ junctions.
PMOS
NMOS a
10-1
C
10-1 10-1
L.. U
0 ._o C
10-1
Gate Voltage VG (V) E
b
C. C
.5 L._ o
Drain Voltage Vo (V) Fig. 3:
Transfer (a) and drain characteristics (b) for NMOS and PMOS transistors with leff = 0.35 gIm
A threshold voltage decrease caused by DIBL was not observable for effective channel lengths down to 0.3 Wi under the measurement condition of VD = 50 mV. The slight increase of the n-channel threshold voltage, as demonstrated in Fig. 4, indicates a rise of the channel concentration near the source/drain regions, due to boron redistribution during the reoxidation process M/. The basic device parameters are summarized in Table 3. 124
Table 3: Electrical device parameters for NMOS and PMOS transistors
Process parameter
NMOS
PMOS
Effective channel length left (pm) / W = 10ln
0.35
0.35
Threshold voltage VT (V) measured with VD = 50 mV
0.79
-0.73
Subthreshold slope (mV/Dec)
92
93
Transconductance Triode: gm max (mS/mm)
15
3.5
Transconductance Saturation: gm sat (mS/mm)
160
78
Junction depth (gim)
0.15
0.2
4
5
Sheet resistance CoSi2 Rs (9n)/I
0.8
-0,8
0.6
-0.6
U)
0.2
-0.4 V[s r 50mV
0.2 ¢I-
Vas = -50mV
NMOS I
I
0.4
I
PMOS
-0.2 I
0.8
I
I
12
If
I
16
If
I
I
I
2.0
I
04
Effective Channel Length
I
G8
I
12
I
16
I
I
2.0
egf (pm)
Fig. 4: Threshold voltage characteristic for NMOS and PMOS transistors 125
The dynamic device behaviour was examined with a 33 stage ring oscillator. A non velocity optimized inverter delay time of 120 ps/stage was achieved for a ring oscillator with left = 0.45 gim and a supply voltage of VD = 5 V. As clearly demonstrated in Fig. 5, a performance improvement with decreasing channel lengths has been obtained, which is scaled reciprocal proportional by the channel lengths. A fully processed ring oscillator is shown in Fig. 6, which also exhibits the overlay capability of the last lithography level.
o
Supply Voltage V., (V) a
b
Fig. 5:
Ring oscillator frequency (a) and stage delay time (b) for two different effective channel lengths
Fig. 6:
Microscope picture of a fully processed CMOS ring oscillator with left = 0.4 lim. The contact hole sizes are 0.5 gIm with 1 jim distance to the gate edge. 126
RADIATION DAMAGE The influence of X-ray induced radiation damages on the device characteristic was investigated by comparison of X-ray and optically processed sub-0.5 lgm NMOS and PMOS transistors. Both types of devices have been processed identically within the same lot and were only been splitted to perform the X-ray and optical lithography, respectively. For the realization of sub0.5 g±m channel lengths with optical lithography, the resist stuctures in the gate level have been shrunk by isotropic 02 plasma etch. In order to ensure the similarity of the transistors compared, the effective channel lengths, the surface concentrations of channel dopants and the gate oxide thicknesses have been determined electrically by transconductance and C-V measurements [8]. Within the gateoxide of dox = 10 nm the absorbed X-ray dose is about 2.5 Mrad, calculated by the simulation program XMAS. The mechanism of the X-ray damage is caused by the absorption of X-ray photons with energies higher than the SiO 2 bandgap of 8.8 eV, which are able to create electron hole pairs. Charge separation with subsequent hole trapping can occur, due to the internal field across the gate oxide, caused by the work function differences for n+ and p+ poly - Si, respectively. The internal electrical field strength for NMOS and PMOS transistors amount about ± 0.9 MV/cm, resulting in a different hole trapping characteristic. For NMOS transistors the holes move to the SiO 2 - Si interface according the direction of the field vector, where deep hole traps are mainly located. In contrast, for PMOS transistors an opposite field direction across the gate oxide governs a hole motion to the Si0 2 - poly Si interface, with reduced hole trapping efficiency. These effects can be observed by VT comparison between X-ray and optical NMOS and PMOS devices, as demonstrated in Fig. 7. N.V0*
(.VMr2)-l
v, (Y)
NMOS 07
-
PP40S
A r
0.6 -
Fig. 7:
A0 A
A . A0VT
iD i
E0 Opticol
X-Ray
T
3 .0 - 0 6
rnV
aW
2.0
,0,.1R
'
-03,5 Opk.OL
X-Ray
1.08 Optcal
X-Ray
Optical
X-Ray
Comparison of the threshold voltage VT and the interface state density Dit between X-ray and optical transistors. 127
,
Both, NMOS and PMOS transistors exhibit a negative VT shift of AVTp = 9 mV and AVTN = 51 mV, due to the different hole trapping efficiency, mentioned above. No significant difference in the interface trap density Dit could be observed in both cases, which can be explained by ADit annealing during the post metallization tempering at 4500C, 20 min. The influence of X-ray radiation on the long term stability was examined by hot carrier experiments. For this purpose, X-ray and optical transistors with sub-0.5 gim channel lengths have been stressed according to the following conditions:
Stress Condition
NMOS
PMOS
1000
1000
Stress drain voltage VD (V)
3
-3
Stress gate voltage VG (V)
VG : IBulk max
VG : IBulk max
Stress time t(s)
The reduced drain voltage of VD = 3V has been used with respect to the expected supply voltage for 0.25 g±m devices. In PMOS transistors, the degradation is mainly caused by electron injection into the gate oxide near the drain region, resulting in transconductance increase, due to channel shortening effects. With diminishing of the device geometry, localized damage effects exhibit enhanced impact on device parameters, according to the increase of the ratio of the damaged area to the total area. The most severe degradation for PMOS transistors take place under the condition of 'Gate max stress. However, in our experiments this condition could not be realized because of the reduced stress drain voltage. For NMOS transistors, the 'Bulk max stress reveals the highest degradation effect, mainly caused by hole injection with related Dit generation. The threshold voltage shifts AVT for X-ray and optical devices have been evaluated below AVT = 12 mV in all cases, with a tendency of slightly higher AVT values for X-ray transistors, as demonstrated in Fig. 8. An explanation of this minor effects is difficult because of uncertainties in channel lengths determination with an accuracy of about ± 20 nm. The stress induced differences of parameter shifts like transconductance Agm, interface state density ADit and linear drain current AID between X-ray and optical transistors are in the order of a few percents and, therefore, within the band width of process fluctuations and measurement accuracy.
128
.1
E:
MU r-
P - MOS Transistors
rnlsistrs
0
-0
- 10 Stress conditions
Stress conditions Vo - 3V 3
-20
- - --
T sec tt
L
m
vX-ray
-20 I-
t.
1000 SKc
*I
0.2 0.(3 U Etfective Char-et Length tW, {tn)
Fig. 8:
Vo: Is-
X- ray
vo I-
optical
- - - --
optical
0.
(12 0(3 O4 Elecive Chw e Length I.,
0.5 (t-)
Dependence of hot carrier induced VT shift (AVT = AVT (0) - VT stress) on effective channel lengths for NMOS and PMOS transistors CONCLUSION
In this paper we have demonstrated the capability of X-ray lithography for CMOS device making in the sub-0.5 pm range with low integration density. For this purpose all X-ray components like masks, stepper and resist could be successfully applied in an entire 0.4 gm CMOS process. The current overlay results with 180 nm maximum are suitable for processes with 0.5 gm design rules. Further reduction of the overlay error down to 140 nm maximum can be realized by the application of master masks and the XRS 200 (Suss) stepper alignment, which will meet the overlay demands for the 64 Mbit DRAM generation. The CMOS technology used could ensure an adequate device performance in terms of static and dynamic transistor behaviour. Radiation induced damages, evaluated on NMOS and PMOS transistors reveal a VT shift of AVTN = 51 mV and AVTp = 9 mV, respectively. Long term stability, examined by hot carrier experiments exhibit no severe differences between both types of devices. These results are no limitation in terms of X-ray induced device degradation and are related to an absorbed X-ray dose of about 2.5 Mrad within a gate oxide of dox < 10 nm. ACKNOWLEDGEMENTS We would like to thank our colleagues from the X-ray lithography group for mask-making, K. Tomkowiak for the X-ray exposures and A. Kloor for performing the electrical measurements. This research was financially supported by the Bundesministerium fur Forschung und Technologie (Federal Ministry of Research and Technology) of the Federal Republic of Germany.
129
REFERENCES [1]
G. Zwicker, W. Windbracke, H. Bernt and D. Friedrich, Fabrication of 0.5 pm n- and p- type metal-oxide-semiconductor test devices using X-ray lithography, J. Vac. Sci. Technol. B7, 1642 (1989)
[2]
D. Friedrich, H. Bernt, H.L. Huber, W. Windbracke and G. Zwicker, Fabrication of 0.5 g±m MOS test devices by application of X-ray lithography at all levels, Proc. SPIE Vol. 1089, 202 (1989)
[3]
H.L. Huber, U. Scheunemann, W. Rohrmoser and E. Cullmann, Application of X-ray steppers using optical alignment for synchrotron based X-ray lithography, Proc. Microelectron. Eng. 151 (1988)
[4]
W. Windbracke, H. Betz, H.L. Huber, W. Pilz and S. Pongratz, Critical dimension control in X-ray masks with electroplated gold absorbers, Proc. Microelectron. Eng., 73 (1986)
[5]
R.U. Ballhorn, R. Dammel and H.H. David, Performance optimization of the chemically ampified radiation resist RAY/PF, Proc. Microelectron. Eng. (1990)
[6]
W. Windbracke, H.L. Huber, P. Staudt and G. Zwicker, Fabrication of sub 0.5 gm pattern for MOS devices by means of X-ray lithography and plasma etching, Proc. Microelectron. Eng. 109 (1988)
[7]
M. Orlewski, C. Mazur6 and F. Lau, Submicron short channel effects due to gate reoxidation induced lateral interstitial diffusion, IEDM Tech. Dig., 632 (1987)
[8]
D. Friedrich, H. Bernt, L. Schmidt and W. Windbracke, Degradation behavior of 0.5 gm p-channel metal-oxide-semiconductor transistors fabricated by means of X-ray and optical lithography J. Vac. Sci. Technol. B8 (6), 1638 (1990)
130
A 0.5 MICROMETER CMOS PROCESS BASED ON A 248 NM EXCIMER LASER STEPPER Mark D. Kellam, Scott Goodwin-Johansson, Susan Jones, Bruce Dudley, and Charles Peters MCNC, Center for Microelectronics P.O. Box 12889, Research Triangle Park, NC 27706-2889
A 0.5 micrometer CMOS process with cobalt salicide and three levels of metal interconnect has been developed for implementation on the GCA ALS 200 Excimer Laser Stepper, which operates at a 248 nm wavelength. The process is designed to meet aggressive performance, density, and manufacturability requirements by using minimum mask level dimensions of 0.5 micrometers at the polysilicon gate, contact, first metal and first via levels. Device and process design strategies are presented. INTRODUCTION A 0.5 micrometer CMOS process with cobalt salicide and three levels of metal interconnect has been developed for implementation on the GCA ALS 2000 Excimer Laser Stepper, which operates at a 248 nm wavelength. The process is designed to meet aggressive performance, density, and manufacturability requirements by using minimum mask level dimensions of 0.5 micrometers at the polysilicon gate, contact, first metal and first via levels. The process requires 11 masks and 13 lithography operations including a third level of metal and passivation. The layout groundrules for the process reflect a 3 sigma inter-level overlay specification of 0.15 micrometers. The process is designed for reliable operation at a power supply voltage of 3.3 volts. The gate oxide thickness used in the process is 11 nm and nominal effective channel lengths of the devices are 0.32 micrometers. LITHOGRAPHY Current non-achromatic fused silica lens place tight constraints on the light sources of deep UV excimer laser steppers, such that tight bandwidth control is important. In the deep UV stepper used at our fabrication facility, a GCA ALS 200 Excimer Laser Stepper with a
131
numerical aperture of .35 and a 248 nm light source, a wavelength control system can lock the source wavelength to a user specified position. The key parameters affected by wavelength setting were 1) distortion, an image placement error, 2) ultimate resolution, 3) proximity effect, as defined by the difference in measured linewidths between isolated features and gratings of a nominal feature size, and 4) astigmatism, in which horizontal and vertical foci do not coincide, reducing depth of focus. These parameters were evaluated to determine the best absolute wavelength setting for achievement of optimum imaging performance, and compared to the laser wavelength determined during installation to yield almost the minimum distortion. Metrology methods used for the evaluation include electrical resistance (Prometrix Lithomap® EM1), scanning electron microscopy (Hitachi S6000 Metrology SEM), and an intrafield metrology system built into the stepper (GCA SMARTSETO). It was documented that proximity effect decreases, resolution improves, and absolute lens distortion increases with negative shifts in laser wavelength setting, with a slight differential in the setting required to minimize horizontal versus vertical proximity effect and astigmatism [1]. A negative wavelength offset of 2.3 A from the nominal stepper setup wavelength was determined to be the best operating wavelength for our applications. The effect of laser wavelength adjustment on 0.50 .Im nominal features in terms of proximity effect, astigmatism and total lens distortion is given in the graph of Figure 1. It should be noted that the lens distortion plotted in the figure represents an absolute value of maximum displacement across the field. Lens distortion was the only intrafield parameter measured by Smartset that could not be corrected by adjustments to the reticle platen of the stepper. As shown in the figure, a minimum in lens distortion and an acceptable level of astigmatism is achieved at a wavelength offset of 0.5 A. However, at this offset the proximity effect is nearly 0.2 im for the features of interest. This means that an isolated feature printed 0.2 micrometers smaller than a line that is part of a dense array. A wavelength offset of -2.3 A provided a more acceptable compromise for our design rules, although total lens distortion measured 0.2 ptm. For wafers exposed operating the stepper with the detuned laser, top down low voltage SEM measurements of photoresist lines yielded a proximity effect of 0.04 gm for vertically oriented 0.50 gm nominal lines. Astigmatism measured 0.02 pm for 0.50 pgm nominal lines. Electrical linewidth testing documented a linewidth uniformity of 0.05 ptm (3a) for <0.50 ptm nominal lines at the optimized wavelength. A minimum resolution of 0.30 gm was also observed, using no resist process enhancements other than an organic absorbing layer.
132
The difference in proximity effect and absolute resolution for the setup wavelength compared to an adjustment of -2.3 A is significant, as depicted in Figures 2, 3, and 4. Absolute resolution is increased by 0.1 pm with the negative wavelength adjustment, allowing resolution of 0.3 rni nominal features. The proximity effect is also improved throughout the range of nominally sized features investigated, with a factor of 4 reduction in proximity effect for 0.50 pm nominal features. Depth of field was approximated at slightly better than 2.0 gm to maintain a mean linewidth control of ±10% for the 0.50 gin nominal features. However, if across the die uniformity is taken into account, the depth of field is somewhat decreased. For the die exposed with optimum focus and exposure conditions, across the field 3y linewidth uniformity ranged from 0.02 ýlm for vertical grating lines to 0.05 ýim for horizontal isolated lines. .t
I
•,0.6
S0.5 E 0.4 0.3
g
0.2 0.1 0
-7
-6
-5
.4
.3
-2
-1
0
1
2
Wavelength Offset (A)
Figure 1. Graph of measured proximity effect, astigmatism and absolute lens distortion as a function of laser wavelength adjustment. The photoresist system used with the GCA Laserstep was Shipley Megaposit® SNR-248 deep-UV resist. A 0.6 micrometer thickness of resist was coated over a 0.1 micrometer thick anti-reflective underlayer, that has been developed for use at the polysilicon gate and contact levels to minimize substrate reflections and proximity effects. The antireflective layer is compatible with the resist system and provides a dramatic reduction in substrate reflectance effects. Figure 5 shows the comparison of resist lines patterned over polysilicon with and without the anti-reflective coating. The addition of the ARC significantly
133
0.4 *
0 wavelength offset
U
.2.3
0.3 A wavelength offset
0.2 0
0.1
""
0
0-0.1 a. -0.2
0
0.5
1
1.5
2
2.5
Mask Design (grm)
Figure 2. Graph of measured proximity effect over a range of nominal mask design linewidths for wavelength offsets of 0 and -2.3 A. The proximity effect is defined as the bias difference between isolated lines and those in a grating 0.4 S
0.3
0.2
&
Isolated space
a
grating line
A
Isolated line
0.1 S0
-0.1 S -0.2 -0.3 .fl A -0
4•
0
I
I
-a-
I
0.5
a
a -a-
1
a
I
a -a
1.5
a
a1
--a
2
a
2.5
Mask Design (jim)
Figure 3. Graph of linewidth bias from mask for equal line/space gratings and isolated features for a range of nominal mask design linewidths patterned with a laser wavelength offset of -2.3 A.
134
0.4 :
:
i
0.3
0.2 0.1
-0.1
I
*
isolated space
*
grating line
A
isolated line
3-0.2
-0.4
,
0
I
,
0.5
,
,
I
... ,,
I
.
1 1.5 Mask Design (gm)
.... 2
2.5
Figure 4. Graph of wafer linewidth bias from mask for equal line/space gratings and isolated features patterned with no laser wavelength offset.
with ARC Figure 5. Comparison of 0.5 g Photoresist Line over Polysilicon with and without anti-reflective coating reduced the line edge roughness caused by the grain structure of the polysilicon. The anti-reflective coating is reactive ion etched prior to the etch of the polysilicon or oxide film using the resist as a template. Lithography bias differences between polysilicon and diffusion contacts are reduced to less than 0.03 micrometers by the use of the thin anti-
135
reflective coating. The exposure and focus latitude of the contact level are improved by the use of the anti-reflective coating, but must still be considered unacceptable from a manufacturing point of view. The SNR248 resist is also used as the imaging film in a tri-layer liftoff process. The liftoff process is used to provide self-alignment of complementary implants, and for the patterning of the metal interconnect. The process sequence for the liftoff process involves spinning an oxygen plasma resistant coating on top of a planarizing release layer [2]The template material is reactive ion etched in CF4 using the resist mask, and then the release layer is etched using oxygen RIE. After evaporation, the metal is lifted off. DEVICE DESIGN The device design for this process was closely coupled to the characteristics of the lithography tool. The device designs were optimized by maximizing the drive current of the longest nominal channel length device while maintaining an acceptable subthreshold leakage and drain electric field of the 3 sigma shortest channel device. Circuit designers must insure that designs meet performance specifications given the slowest device parameters likely to occur in a process. Channel length variations are the most significant source of variation in device and circuit speed and it is reasonable to use the longest nominal channel length as a figure of merit for the overall performance of a process. Proximity effects have a dramatic effect on the overall circuit performance of the final design as measured by this figure of merit. The proximity effect observed in our experiments caused isolated polysilicon gate features to shrink in size relative to a grating structure formed by equal photoresist lines and spaces. The length of isolated gates must be increased by over-exposure in order to preserve the minimum Leff that meets the worst case subthreshold leakage and hot carrier immunity specifications. If the shortest allowed channel length is considered a fixed parameter, the proximity effect has the effect of increasing the channel length of the grating structures and reducing the speed of the longest channel length devices. This is particularly a problem for NAND and NOR gates because they contain multiple gates in series. These structures are intrinsically slow and the proximity effect slows them even more. Figure 6 shows the improvement in the longest channel length device obtained by the wavelength adjustment of the excimer laser. The reduction in proximity effect reduced the longest expected channel length by 0.16 micrometers and improved the slowest case process performance by almost 30%. Figures 7,8 and 9 show measured IV characteristics and subthreshold leakage currents for the nominal 0.5 micrometer mask dimension devices.
136
isolated line
grating
nized rtion
¶t.0
mized dmity rect
effect
Gate Length Figure 6. Reduction of Longest Channel length by Laser Wavelength Optimization of Proximity Effect. The longest channel length is the sum of the shortest channel length, the proximity effect, and the 3 a variation. The NMOS device design for the process is based on a conventional phosphorus LDD structure with a nominal Leff of 0.32 micrometers. The nominal NMOS threshold voltage is set to 0.65 volts using a BF2 threshold adjust implant. The PMOS device has a buried channel with a boron LDD below the oxide spacer. Control of short channel effects in the PMOS device is achieved by implanting an arsenic "halo" below the shallow boron LDD implant (Figure 10). The halo implant is shallower than the p+ junction implant so that it has little impact on the junction capacitance. A buried channel PMOS design optimized for current driveability and device leakage was found at a nominal PMOS threshold voltage of -1.0 volts. The sensitivity of
137
Id
va ..-ijuu/mv (Volts) Vgate = 0.0 to 3.3 volts Figure 7. IV Characteristic of 0.5 X 10 micrometer (mask) NMOS device Leff = 0.32 micrometers
Id (Or
IMA
Vdrain
.3300/div
(Volts)
Vgate = 0.0 to -3.3 volts
Figure 8. IV Characteristic of 0.5 X 10 micrometer (mask) PMOS device Leff = 0.32 micrometers
138
lE-2
IE-12
0
Vgate
3.3
Figure 9. Subthreshold Characteristic of 0.5 X 10 micrometer (mask) device Leff = 0.32 micrometers, Vdrain = 3.3 volts device parametrics to process variation were studied by a Monte Carlo simulation of 250 process variations and the resulting transistors. The process variations were simulated in PREDICT using normal distributions of the process parameters to approximate measured data.[3] The resulting device characteristics for a particular set of process values were then simulated using PISCES II.[4] The nominal device design was then modified to minimize the device properties' sensitivity to process variation. PROCESSSEQUENCE The process sequence begins with the definition of the isolation regions by a conventional LOCOS process with a scaled field oxide. The thin field oxide allows the use of the thinner pad and thicker nitride than normally used, without stress related damage. The absence of stress related crystal damage at the edge of the field oxide has been verified by electrical leakage studies and TEM micrographs (Figure 11). A highly selective RIE process was developed to allow endpoint of the nitride etch on the thin oxide.[5] The thin field oxide increases the metal 1 capacitance, but reduces the bias due to the birds beak to less than 0.12 micrometer. The RC delays associated with the first metal confine its use to local routing. The second and third metals will be used to route global signals. The step height of the field oxide drives the selectivity
139
Figure 10. Buried Channel PMOS with PLDD and "Halo" Implant requirement of the polysilicon gate etch because the poly overetch must remove the poly from the step. The lack of a large step at the isolation edge allows the use of conventional polysilicon etch processes with moderate selectivities to oxide. A retrograde nwell and NMOS punchthrough implant are performed using a liftoff process for complementary masking (Figure 12). The use of liftoff for complementary implant masking reduces the number of masks purchased by 2 and the number of lithography exposures by 3. An additional benefit to these cost reductions is the self-alignment of the complementary implants, that allows tighter groundrules and increased layout density. An 11 nm gate oxide is grown and covered by a thin deposit of CVD polysilicon, which protects the gate oxide from the resist used to mask the different NMOS and PMOS threshold adjust implants. A global BF2 implant is performed to set the PMOS threshold and the PMOS devices are masked with photoresist before the final NMOS threshold adjust implant. The remainder of the polysilicon is deposited and POC13 doped after stripping the resist. The polysilicon gates are then patterned and etched. The NMOS and PMOS LDD implants are performed using the liftoff process to achieve complementary masking. An oxide spacer is formed and the source drain implants are made using the another liftoff masking. The junctions are activated using a Rapid Thermal Anneal (RTA). A cobalt film is evaporated and annealed to form a cobalt salicide. The unreacted cobalt is removed with a sulfuric-peroxide etch, and the cobalt disilicide formed by an 800 degree RTA.
140
I
Figure 11. TEM micrograph of LOCOS Edge Contacts are etched through the passivation oxide using a conventional CHF 3 :0 2 RIE chemistry. Tables 1-3 list some of the technology and device parameters used in the process. The metal interconnect lines are formed of a titanium - titanium stack that is deposited without aluminuml4%copper breaking vacuum in the evaporator. This metallization structure has good electromigration resistance and a low density of metal hillocks. The process sequence for the metal and via interconnect levels are all identical and use the tri-layer liftoff to "entrench" the metal in a polyimide dielectric layer [6] .The tri-layer liftoff process described earlier is performed over a fully cured polyimide film. Following the RIE etching of the soluble release layer, the exposed portions of the fully cured polyimide are RIE etched. This film is insoluble in the liftoff solvent and surrounds the metal lines after the liftoff. The global planarization achieved by the entrenched metal process leads to good control of the via etch bias and reduces the metal pad size surrounding the via. The global planarization of the metal lines and via holes insures that the step coverage of the metal will be adequate. The use of the same process to fill the vias with lifted off metal plugs allows the stacking of an upper via directly over a lower one. These processes allow the use of extremely aggressive interconnect related design rules and high circuit layout density. The presence of the polyimide filler between the metal lines reduces the metal "halo" that is a 141
characteristic of liftoff metallization. The reduction in the metal "halo" reduces the additional wire capacitance and shorting density associated with the halo.
2) RIE etch silicon in CF4
1) Expose + Develop Resist Resist
Resist silicon PMGI
silicon
PMGI
3) RIE etch PMGI in 02
4) Implant n type
silicon
N
W
PMGI
metal
silicon PMG1
6) Liftoff metal in solvent metal
PMGI
8) Strip Metal
7) Implant p type metal
Figure 12. Self-aligned Complementary Implant Masking using Metal Liftoff and 1 lithography step
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Table 1:Technology Parameters Layer Gate Oxide Field Oxide Passivation LTO Polyimide (M1-M2) Polysilicon Xj (n diffusion) Xj (n diffusion)
Thickness (micrometers) 11.0 nm 0.20 microns (under poly) 0.39 microns (under metal 1) 0.20 microns 0.80 microns 0.25 microns 0.10 microns 0.12 microns
Table 2: Layout Groundrule Specifications Alignment tolerance (3 sigma) Minimum Size (Poly, Contact, Metal 1, Via 1) First Metal Pitch Second and Third Metal Pitch Lithography bias Lithography tolerance (3 sigma) Dry etch bias for nitride, poly Dry etch bias for contact Dry etch bias for via 1 Dry etch bias forvia2
0.15 Wn 0.50 Pm 1.1 Jim 1.6 jtm 0.1 gm 0.15 pim 0.05 + 0.1 pm 0.1 ± 0.1 jim 0.15 0.15 Wm 0.3 _0.16 Wm
Table 3: Electrical Parametrics Threshold Voltage (NMOS) Threshold Voltage (PMOS) NMOS Current Drive (Vg=Vd=3.3 Volts) PMOS Current Drive (Vg=Vd=-3.3 Volts) NMOS Sub-threshold Slope PMOS Sub-threshold Slope
0.65 Volts -1.00 Volts 350 jia/micrometer 220 ja/micrometer 90 mv/decade 120 mv/decade
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CONCLUSIONS A 0.5 micrometer CMOS process with cobalt salicide and three levels of metal interconnect has been developed for implementation on the GCA ALS 200 Excimer Laser Stepper, which operates at a 248 nm wavelength. Some tradeoffs were required between the various parameters when determining the precise laser wavelength adjustment to implement. The precise wavelength which provided minimum distortion was not the same as the setting which provided optimum resolution, or minimization of proximity effects and astigmatism. Given our specific design rules and process requirements, the best operating wavelength required an adjustment of -2.3 A from the wavelength which yielded the minimum lens distortion. This adjustment has a significant effect on the performance of circuits manufactured with this process. Further improvements in process and device latitude have been gained by the use of a thin anti-reflective coating under the photoresist at critical levels. The device design has been matched to the capabilities of the laser stepper. ACKNOWLEDGEMENTS The authors wish to acknowledge the technical contributions provided by Edward K. Pavelchek (Shipley Company, Resident Professional at MCNC), Peter Freeman (Digital Equipment Corporation, Resident Professional at MCNC) and Joe Williamson (Harris Corp.). The authors would also like to acknowledge the advice and other assistance provided by Dave Koester, Carl Osburn, W. Boyd Rogers, and Ron Sayer .
REFERENCES [1]
Susan K. Jones, Bruce W. Dudley, Charles R. Peters, Mark D. Kellam, Edward K. Pavelchek, Proc. SPIE 1464 (1991), in press.
[2]
D. Witman, et. al. , Proc. of the 15th Intern. Conf. on Lithography, Cambridge Eng., p549, (1989)
[3]
R.B Fair, IEDM Tech. Digest, 260, 1987
[41
M.R. Pinto, C.S. Rafferty, and R.W. Dutton, "PISCESII: Poisson and Continuity equation Solver," Stanford Electronics Tech. Rep., Sept. 1984.
[51
H. Stocker, J. Vac. Sci. Technology, A7(3), 1145, (1989)
[6]
L.B. Rothman, Journal Electrochem. Soc., 130 (5), p1131, (1983)
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DEEP UV LITHOGRAPHY OF MONOLAYER FILMS WITH SELECTIVE ELECTROLESS METALLIZATION Jeffrey M. Calvert*, Mu-San Chen*, Charles S. Dulcey, Jacque H. Georger**, Joel M. Schnur and Paul E. Schoen Center for Bio/Molecular Science & Engineering (Code 6090) Naval Research Laboratory, Washington, DC 20375-5000 and Martin C. Peckerar Nanoelectronics Processing Facility (Code 6804) Naval Research Laboratory, Washington, DC 20375-5000 To whom correspondence should be addressed Also at: Geo-Centers, Inc., Ft. Washington, MD 20744 A top surface imaging approach for the fabrication of submicron features on solid substrates has been developed. A monolayer film is exposed to patterned deep UV radiation, then selectively metallized using electroless deposition such that a thin metal layer (200-400 A) is deposited only in the unexposed areas. The film/metal assembly is a highly effective mask for reactive ion etching which can subsequently be stripped from the substrate after feature definition. Features with 0.25 prn line width in polysilicon and working transistor test structures have been produced using this process.
INTRODUCTION In considering the characteristics of an ideal imaging process for optical lithography, numerous factors must be taken into account [1]. The well-known Rayleigh criterion {1) states that the minimum resolution or feature width (W) is directly proportional to the exposure wavelength (W), a material specific k factor, and inversely proportional to the numerical aperture (NA) of the lens. W = kX/NA
(1{
Optical lithography is progressing from g-line (436 nm) to i-line (365 nm) to deep UV (248 nm and 193 rm) exposure tools in order to meet the continuing demand for greater circuit density, which requires increasingly smaller feature
145
sizes. A second measure of lithographic performance, the modulation transfer function (MTF), is maximized as both wavelength and imaging layer thickness decrease. However, the depth of focus (DOF) is also directly proportional to wavelength, as given in Eq. 12). Short wavelength sources and high NA lenses DOF = + A/2(NA) 2
121
which are desirable for fine feature printing can result in DOFs that are too small to produce a focussed image in a typical 1.0 - 1.5 pm thick photoresist. There are additional difficulties with changing to shorter wavelength. Many photoresists are highly absorbing below about 250 nm. Alternate resins have had to be developed based on a limited class of materials that have sufficient transparency in the deep LIV. In addition, standing wave effects are particularly serious with deep LIV lithography because ofthe higher reflectivity of silicon at these wavelengths, the higher aspect ratio structures typically required, and a more severe dependence of the exposure dose on photoresist thickness. The use of anti-reflection coatings to solve this problem adds to the complexity of the lithographic processing [2]. In the above analysis, the laws of optical physics lead to the conclusion that optimal performance will be obtained by the use of short wavelength irradiation and ultra-thin imaging layers. With a deep LTV sensitive top surface imaging (TSI) process, resolution and MTF are maximized. If the layer is sufficiently thin, resist transparency is not a problem and standing waves can not be supported. DOF is also not an issue, except that a planarizing layer is required for printing over topography; we will return to this point later. The photoresist systems currently under the most active investigation are the DNQ-novolaks, chemically amplified resists, and silicon-containing polymer systems [3,4]. With the latter, photooxidation throughout at least several hundred Angstroms of the resist produces an oxidized silicon material that is resistant to certain plasmas for pattern transfer. In both the DNQ and chemically amplified resists, post-exposure silylation is used to incorporate silicon containing species to depths of at about 1000 A into the photoresist. During 02 plasma etching, the silylated regions are converted to an SiO2-like material that serves as the actual etch barrier. Processes of this type include DESIRE, PRIME, CARL and SAHR [3,4]. In another process, a DNQ-novolak photoresist is exposed, then treated with a colloidal catalyst. After development, the catalyst is "lifted off' by dissolution of the outer -1000 A of the resist. Electroless deposition then produces a thin metal layer on the remaining catalyzed area. The metal serves as the primary etch mask [5]. Despite the fact that it is necessary to modify the outer several hundreds to thousands
146
of Angstroms of the photoresist, these and similar approaches have been referred to as TSI processes [6]. A more accurate characterization for these systems is as near-surface imaging processes. In a true TSI process, only the outermost monomolecular layer or layers undergo a radiation-induced transformation that leads to image formation. An example of this approach in which Langmuir-Blodgett (L-B) monolayer films of poly(methylmethacrylate) were employed as an electron beam resist has been reported [7]. Although the patterned monolayer was successfully used as a mask for wet etching chromium, these ultra-thin organic layers are not sufficiently robust to withstand the reactive ion etch (RIE) plasmas required for sub-micron feature definition in integrated circuit fabrication operations. Also, L-B film formation is extremely time-consuming and is not currently foreseen as a viable manufacturing technique. In another approach to TSI imaging, deep UV photooxidation of hydrophobic organic polymers, followed by exposure to vapors of inorganic halides produced oxides of the inorganic element in the outer regions of the polymer [8]. When developed with TiCl4, the vapor penetrated 50 - 100 A into the polymer and was converted to TiO2 which served as the etch barrier [9]. The refractory titanium dioxide gives higher etch selectivity than its silicon counterpart. However, difficulties with process control and background residue limit the attractiveness of this process in the same manner as with the silylated resists. We describe here an approach for high resolution optical lithography in which a deep UV sensitive, TSI process utilizes a monomolecular imaging film in conjunction with a thin metal layer that serves as an etch mask [10,11]. A monolayer film, attached to the desired substrate, is exposed with patterned deep UV radiation to produce alternating surface reactivity. No wet development step is employed. The film is then selectively metallized using electroless deposition such that a thin metal layer (about 200-400 A) is deposited only on the unexposed areas, creating a positive tone relief image. The ultra-thin film/metal assembly serves as a barrier against RIE which can be easily removed from the substrate after feature definition. The Ultra-Thin Film (UTF) metallization process is shown schematically in Fig. 1. FILM FORMATION Unlike the physisorbed L-B films that have been investigated elsewhere for lithographic applications, the monolayers used in this work are chemisorbed films that are strongly adhered to the substrate by covalent bonds. Chemisorbed films are easier to prepare and more robust than L-B films.
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Organosilane films, such as phenyltrichlorosilane (PTCS) or chloromethylphenyltrimethoxysilane (CMPTS), were typically deposited by dip coating from a non-aqueous solution (toluene, methanol) and can be deposited on any substrate with oxidized surface functionalities such as hydroxyl groups [10-12]. Organosilane films can also be formed by vapor deposition or spin coating. The film precursors react with the substrate in a manner similar to the photoresist primer HMDS to form a covalently bonded ultra-thin layer covering the surface. The typical thickness of these films is 5-10 A. The nature of the siloxane linkage is such that these materials can be attached to most relevant substrates in microelectronics, such as native and thermal silicon dioxide, polysilicon (poly-Si), silicon nitride, alumina, as well as many metals and polymers [10,11]. DEEP MONOLAYER FILM
EXPOSE
-
j
METAL
CATALYZE
PLATE
I
RIE
STRIP
Fig. 1 Schematic of UTF metallization process. EXPOSURE Patterning of the films was accomplished by the use of a variety of deep UV sources, including ArF (193 nm) and KrF (248 nm) lasers, low and high pressure mercury lamps, and both contact and projection printers. The principal photochemical mechanism in simple aromatic organosilanes such as PTCS upon exposure to deep UV radiation is photocleavage at the Si-C bond, which is believed to lead to the formation of surface silanol (Si-OH) groups. The initially hydrophobic film is converted to a highly hydrophilic surface in the exposed regions. Evidence for this mechanism has been obtained with UV, XPS and laser-induced desorption FTMS spectroscopies and contact angle goniometry [12]. Photochemical mechanisms other than Si-C bond cleavage are
148
observed in some of these materials. The photochemical cleavage mechanism is quite efficient at 193 run (ArF excimer laser), with some materials exhibiting dosages of -150 mJ/cm2 . The photocleavage is less efficient at 248 nm, with dosages currently near 1 J/cm . METALLIZATION The latent image in the organosilane film was then metallized using electroless deposition. In this step, a colloidal Pd/Sn catalyst (such as Cataposit 44 from Shipley Co.) adheres only to the unexposed regions of the film. XPS data has shown no evidence for Pd or Sn in irradiated regions of a PTCS film exposed to the colloidal catalyst. After an acceleration step (Shipley Accelerator 19), the catalyzed surface was immersed in an electroless plating bath. Plating occured selectively only in the catalyzed regions of the films, yielding a positive tone replica of the latent image in metal. Copper, nickelboron, cobalt-boron and permalloy are among the electroless deposits that have been produced with this technique. The metal most often employed has been electroless Ni-B (from Shipley Niposit 468), which provides a smooth, adherent, homogeneous plate on the ultra-thin film. Deposits ranging from about 2001000 A are typically employed. PATTERN TRANSFER The patterned, metallized wafers are then plasma etched to transfer the features into the underlying substrate. Initial studies used electroless copper as the RIE eteh mask. SF, CF4, and Freon 115 have been used as etch gases. Ultra-thin silane films, exposed on the GCA AWIS KrF laser-based projection stepper were plated with a 200 A thick electroless copper overcoat. The metal patterns were used to transfer 0.4 rnn features into poly-Si (Figs. 2 and 3). Exposures on an ArF laser-based contact printer produced features as small as 0.25 un, also with copper as the etch barrier (Fig. 4). Note the absence of background residue, or "grass" in the field. In subsequent studies, electroless Ni was primarily used as the etch mask. Nickel is known to have superior etch resistance to Cu because the nickel halide species formed during plama etching are much less volatile than those of copper. Etching studies have indicated that thin electroless Ni films exhibit etch selectivity of over 300:1 for photoresist [5]. We have found a 200 A electroless Ni layer to be essentially unaffected under conditions that yield an etch rate of 100 A/min for Si0 2 etch rate and 1000 A/min for poly-Si. These results show that electroless nickel is clearly a more robust etch barrier than a silylated resist, as well as being easier to remove. Removal of the metal mask is accomplished with a dilute nitric acid strip.
149
Fig. 2 Electron micrograph of microstructures fabricated by the UTF metallization process. The substrate was a silicon wafer with 4000 A of poly-Si and a top layer of 120 A of silicon dioxide. A CMPTS monolayer film was deposited onto the wafer and exposed with a GCA 1oX reduction 248 nm projection stepper (0.35 NA) at _1 J/cm 2 . The patterned film was catalyzed, accelerated, and subsequently plated with 200 A of electroless copper (Shipley Cuposit 328).
Fig. 3 Electron micrograph of partially etched patterns (0.5 pm. lines and 1.0 pm spaces) produced as described in Fig. 2. The wafer was etched with SF, to remove the outer SiO2 layer and about 1000 A of poly-Si. 150
Fig. 4 Electron micrograph of a transistor test structure with 0.3 Pro line width produced in poly-Si. A CMPTS monolayer film was imaged in a 193 nm contact printer (Karl Suss Co.), metallized with electroless copper, and etched by RIE down to the underlying oxide. The metal was then stripped by a nitric acid dip. DEVICE COMPATIBILITY Manufacturability concerns require an evaluation of device performance and factors which could affect device stability and yields. Such issues for the UTF metallization process include the ability of the metal film to withstand an RIE etch without pinholes and potential contamination of oxides and semiconductors by the metal resists or other process chemistry. In order to further test the manufacturability of the process, microelectronic test structures were fabricated. MOS capacitors are particularly useful structures for characterizing the effects of processing on device performance. Two types of experiments have been performed. In one experiment, a MOS capacitor was formed from a silicon wafer, a layer of silicon dioxide, and a top layer of poly-Si. The UTF metallization process was used to define the top poly-Si plate of the capacitor. This was accomplished by lithographically defining electroless copper patterns on the poly-Si as described above. RIE was used to transfer the patterns into the poly-Si and the metal was stripped with an acid dip. The electrical characteristics of the capacitors were then probed. No detectable changes in oxide breakdown field strength were found, and no hysteresis or carrier storage 151
lifetime degradation were observed even after thermal bias stress testing to 300 'C and +8 V. For the second (and much more stringent) test, a silicon wafer with a 350 A thick gate oxide was coated with an ultra-thin film and the electroless metal was plated homogeneously across the wafer. The metallized wafer was then exposed to an SF6 RIE of sufficient duration to completely remove the entire unprotected oxide. The electroless metal was stripped, then Al dots were evaporated onto the wafer and annealed. The MOS capacitors with Al as the top electrode were then probed electrically. These studies suggested that pinholes and contamination are not major problems in this process. The UTF metallization process has also been used to fabricate single level transistor test structures. The procedure employed was analogous to that described above for creating the poly-Si/SiO2 /Si MOS capacitors, except the shape of the feature was the structure shown in Fig. 4. After stripping the metal mask, sources and drains were produced by ion implantation. Electrical testing gave the expected current-voltage response characteristic of a transistor [11]. Step coverage of additively plated electroless copper over 4000 polysilicon serpentine lines has also been demonstrated.
A high
CONCLUSIONS The UTF metallization process is a true top surface imaging process that has demonstrated deep UV sensitivity, 0.25 pm feature resolution and superior plasma resistance when compared to organic polymer or silylated photoresists. As with silylation processes, the metallization process does not require a single material to serve as both the imaging layer and the plasma etch mask. Decoupling the two functions allows independent optimization of each. The use of a monomolecular imaging layer also presents some interesting questions in terms of quantitating typical lithographic parameters such as contrast and edge acuity, which are usually determined by measurements of the relief image in 1 pm of photoresist. Efforts are continuing to increase the photospeed of the imaging materials at both 193 and 248 nm as required for industrial applications. Preliminary results indicate that much more efficient photochemical mechanisms are available that should lead to photospeeds of<50 mJ/cm2 in the deep UV. Further testing of MOS capacitors to determine etch selectivity and pinhole density is in progress. Due to the DOF issues related to printing over topography, techniques are under invesigation to improve the compatibiity of the process with planarizing layers. We anticipate that a TSI process such as the UTF metallization process, perhaps in conjunction with phase shift masks [13], will make deep LV lithography a viable manufacturing technique for
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circuitry with 0.25 pm design rules and below. In addition to plasma hard resists for high resolution gate definition in integrated circuits, the UTF metallization process should be useful in many applications which require adherent patterns of electroless metallization. Such other applications include the replication of masks on quartz and other substrates as well as the definition of conductive pathways for interconnects and packaging applications [14]. Top surface imaging of monolayer films also promises to yield interesting results with alternate exposure sources, such as low energy electron beams and soft x-rays. Unlike other microlithographic processes that produce patterns of a polymer photoresist, deep UV surface imaging of chemisorbed monolayers (such as the organosilane films described here) creates patterns of molecules with specific chemical functionalities [12]. The ability to photochemically tailor the wettability properties of a surface has important ramifications for developing fundamental insights into adhesion and biocompatibility at the molecular level. The photochemistry of chemisorbed monolayer films, coupled with subsequent surface chemical treatments provides a pathway to define coplanar molecular assemblies of species such as chromophores, redox reagents, catalysts, optically-active and biologically-active species at the practical limits of lateral resolution. ACKNOWLEDGEMENTS The authors thank P. Pehrsson, R. Hershey, C. Anderson and the staff of the NRL Nanoelectronics Processing Facility for experimental assistance. Use of the GCA AWIS stepper at IBM-Manassas and the ArF laser contact printer at Karl Suss Co. is greatly appreciated. Helpful discussions with G. Calabrese (Shipley Co.) and G. Taylor (AT&T Bell Laboratories) are acknowledged. Funding was provided by the Manufacturing Technology Office of the Assistant Secretary of the Navy, DARPA, and the Office of Naval Technology. REFERENCES [1] W. Moreau, Semiconductor Lithography, Plenum Press, NY (1988), Ch. 8. [2] S. Sethi, R. Distasio, D. Ziger and J. Lamb, Optical/LaserMicrolithography XV, V. Pol, ed., SPIE Press Vol 1463, Paper 1463-03 (1991). [3] M.P.C. Watts, ed., Advances in Resist Technology and Processing VII, SPIE Press Vol. 1262 (1990).
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[4] H. Ito, ed., Advances in Resist Technology and ProcessingVIII, SPIE Press Vol. 1466, (1991). [5] G.S. Calabrese, L.N. Abali, J.F. Bohland, E.K. Pavelchek, P. Sricharoenchaikit, G. Vizvary, S.M. Bobbio and P. Smith in Advances in Resist Technology and ProcessingVIII, H. Ito., ed., SPIE Press Vol. 1466, Paper 1466-51 (1991). [6] B.L. Yang, J.M. Yang and KYN. Chiong, J. Vac. Sci. Tech., B7 1729 (1989). [7] S.W. Kuan, C.W. Frank, Y.H. Lee, T. Eimori, D.R. Allee, R.F. Pease, R. Browning, J. Vac. Sci. Tech., B7, 1729 (1989). [8] G.N. Taylor, L.E. Stillwagon and T. Venkatesan, J. Electrochem. Soc., 131, 1658 (1984). [9]
0. Nalamasu, F.A. Baiocchi, and G.N. Taylor, in Polymers in Microlithography, E. Reichmanis, S.A. MacDonald, and T. Iwayanagi, eds., ACS Symposium Series No. 412, ACS Press, Washington, DC (1989), pp. 189 - 209.
[10] Schnur, J.M., Peckerar, M.C., Marrian, C.R., Schoen, P.E., Calvert, J.M., Georger, J.H., U.S. patent application 07/022,439, allowed June 1988. [11] Schnur, J.M., Peckerar, M.C., Marrian, C.R., Schoen, P.E., Calvert, J'.M., Georger, J.H., U.S. patentapplication07/182,123, allowed August 1990. [12] Dulcey, C.S., Georger, J.H., Krauthamer, V., Stenger, D.A., Fare, T.L., Calvert, J.M., Science, in press. [13] M.D. Levenson, N.S. Viswanathan, R.A. Simpson, IEEE Trans. Elect. Dev., ED-29 1828 (1982). [14) Calvert, J.M., Dressick, W.J., Calabrese, G.S., Gulla, M., U.S. Patent application, submitted.
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SILYLATED ACID HARDENED RESIST PROCESSING FOR SUBMICRON DEEP UV LITHOGRAPHY E. K. Pavelchek, J. F. Bohland Shipley Company 455 Forest Street, Marlborough, Massachusetts 01752 P. W. Freeman Digital Equipment Corporation 77 Reed Road, Hudson, Massachusetts 01749 S. K. Jones, B. W. Dudley MCNC, Center for Microelectronics P.O. Box 12889, Research Triangle Park, North Carolina 27709
Selective silylation of Shipley XP-8928, a deep UV acid hardened resist, with TMSDEA and DMSDMA was investigated. RBS results indicated a 9-10 weight % incorporation of silicon, with a sharp front indicative of Case II diffusion. Silicon penetration was also monitored by resist swelling, by solvent stripping, and by cross section plasma staining, which correlate with RBS results. A linear time dependence of penetration was observed, consistent with Case 11 diffusion. The effects of temperature indicate an activation energy in the range of 10 kcal/mole. The effects of silylation pressure were consistent with Henry's Law. INTRODUCTION The future practice of lithography will continue to be limited by narrowing focal depths and increased aspect ratios. The high reflectivity of silicon and the higher refractive index of potential resist materials at 248 nm also underline the need for a surface imaging process, since they combine to worsen standing wave problems. Considerable work has now been done on surface silylation [1] as one such process, and one implementation is now commercially available as the DESIRE process [2]. A thick dyed resist is selectively silylated after exposure and then subsequently developed using an oxygen RIE. Use of RIE allows for extremely high aspect ratios. Acid hardening [31 approaches can also be used. SAHR (Silylated Acid Hardened Resist) [41 offers several advantages for such an approach: it is a positive process, it has high photospeed, and since all the cross-linked resist is etched during the develop process, resist stripping is simplified.
155
Shipley XP8928 is a blend of a novolak resin, a cross-linker and a photoacid generator. A schematic process flow is shown in Fig. 1. Exposure below 300 rn generates a photoacid. The depth of the exposure is limited by the high optical absorbance of the resist. Subsequent baking causes a cross-linking reaction between the resin and the cross-linker. The cross-linked areas inhibit the reaction of organosilane gases with the OH sites of the resin.
resist
resist ---
exposure of resist
cross-linking of resist by acid hardening bake
--
silylation of resist in unexposed areas
plasma etched image
Figure 1. Schematic diagram of SAHR process.
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EXPERIMENTAL XP-8928 was spin coated from a solvent (Shipley Thinner A) solution to thicknesses of 1.8 Kin. Exposures were performed on a GCA ALS 200 projection stepper with a KrF excimer laser source, and a 0.35 NA lens. An OAI model 466 dosimeter was used to measure exposure dose. Post exposure bakes were done on a hotplate for 60 seconds. Silylation treatments were performed in a single wafer, proximity heated silylation system [5]. Temperatures ranged from 30°C to 120"C and pressures from 10 to 240 torr. Agents reported here are TMSDEA and DMSDMA. The etching apparatus was a split cathode magnetron [6]. Oxygen plasmas with and without nitrogen or helium were used at power densities from 0.13 to 0.33 W/cm2 . This resulted in organic etch rates of up to 900 nm/min. Silicon uptake was monitored by thickness changes, RBS, cross section staining, and by solvent stripping. Thickness changes were measured optically by using a Nanospec Tm AFT and ellipsometry and mechanically by using a Dektak 3030. Although the refractive index of resist changes upon silylation, no corrections were made, presumably leading to slight underreporting of thickness. This error was not detectable via Dektak readings. RBS was performed with 2 MeV He ions. A simulation program was written which computed a backscattering spectrum based upon the assumptions of a sharp interface between silylated and unsilylated areas. A simplex algorithm was then applied to calculate the degree and depth of silylation. The silylated resist was found to be highly soluble in xylene; brief immersions (<Ssec) completely dissolved 2 gm of silylated material, while dissolving no measurable amount of unsilylated resist. Optical thickness measurements made after dissolution allowed calculation of the depth of silylation. This technique results in a more precise measurement of silicon penetration than swelling. The number being measured is typically three times larger, and it accurately shows small depths of silylation that fail to demonstrate swelling. These depths are confirmed by cross sectional staining; a technique which enables evaluation of the local patterns of silicon penetration [7,81. Cleaved samples were mounted in a holder so that the cleaved surface was flush with the flat holder top, and free of contact on the resist side by -0.2 rnm. This maintains a uniform sheath distance from the edge, and when placed on the magnetron cathode and subjected to an oxygen plasma, silicon containing regions are sharply delineated without top loss (shown in Fig. 2). Xylene stripping also delineates local patterning, but was not always as clearly seen in SEMs due to variation in cleave angle.
157
Figure 2. Plasma stained cross section showing penetration of silylation agent into 0.5 ptm gratings imaged onto XP-8928, 2 exposed to -20 mJ/cm @ 248 nm, 100 °C PEB. RESULTS Silylation was obtained above 60 °C with TMSDEA. Process times ranged from 30 to 240 sec for available pressures of TMSDEA. Silylation rates follow Henry's Law closely, and are generally constant with time. The apparent activation energy is -14 kcal/mole. (see Fig. 3,4) 1E
1
1.
1. -
z 0
-A-
w 0.
-
120 Degrees 15 Torr 120 Degrees 40 Torr 90 Degrees
H
0. 0. 0
50
100
SILYLATION TIME
150
200
(sec)
Figure 3. Effect of TMSDEA time upon silicon penetration for XP-8928 for various temperatures and pressures.
158
45 Torr
0
SILYLATION PRESSURE
(Torr)
Figure 4. Effect of temperature and pressure upon silicon penetration into XP-8928 (measured by cross section staining) by TMSDEA exposure for 30 seconds.
RBS analysis indicates that 9-10 weight % silicon is obtained in the silylated portions of the resist films. The concentration of silylated material is uniform, and drops abruptly at the limit of penetration, as shown in Fig. 5. One sample was analyzed by SIMS to confirm the absence of silicon below the interface. This sharp drop after a constant level is characteristic of Case H diffusion. Exposed films always show a small amount of surface silicon. It is believed that this is due to the large number of OH sites at the free surface where they can react. Cross-linking inhibits the further penetration by preventing the freedom of motion necessary for the reaction to proceed. Extensive silylation treatment will silylate exposed and cross-linked films to the same 10% silicon.
159
Z 0 0
100
150
200
250
300
350
400
CHANNEL NUMBER
Figure 5. Fitted RBS showing uniform 10 wt% silicon uptake for TMSDEA silylation at 110 °C for 2 min. Excellent bulk contrast in silylation depth is obtained with relatively light exposures. For high post exposure bakes (130 °C) only 3 mJ/cm 2 is sufficient to retard silylation. Resolution has been limited, however, by linearity problems in silylation where medium and small features are retarded in silylation depth. An example of this effect is shown in Fig. 6. This retardation is lessened by lowering the post-exposure bake, but effective-sp~eeds are considerably slower, -30 mJ/cm 2 .
Figure 6. Stained cross section showing overflow of silylated material and lesser penetration in smaller lines. Line sizes 1 pgm and 5ptm. Silylation has been performed as low as 21 'C using DMSDMA which is more reactive than TMSDEA. The additional vapor pressure available from DMSDMA allows for the use of higher silylation pressures and therefore reasonable rates of silylation at low temperatures. Typical process parameters are on the order of 60 sec at 100 torr 160
compared to 240 sec at 60 torr for TMSDEA. Silylation depths are again linear with time. The activation energy for silylation is -7 kcal/mole (see Fig. 7). Silylation results in a decrease in the refractive index of the resist of 0.034 for DMSDMA and 0.050 for TMSDEA. Contrast is somewhat lower compared to TMSDEA. Linearity is not changed. The etched features obtained so far have been limited by overflow of silylated material, by the limited amount of silylation in fine lines, and by the surface silicon. Etch selectivities relative to baked novolaks have ranged between 8:1 and 20:1. Because of the surface silicon, this selectivity is frequently reduced by 20 to 30%. Despite the linearity problems with silylation, it has been possible to create submicron patterns. Fig. 8 shows 0.6 lim lines in 1.8 g1m of resist. 18000,
16000-
E-
14000'
z 0
U
12000'
10000o
U) I.9
(0
8000,
nIJIIl•
40
45
50
55
TEMPERATURE
60
65
70
(C)
Figure 7. Effect of temperature on silylation with DMSDMA at 120 torr for 45 sec.
161
Figure 8. SEM of 1.2 Jim pitch grating in silylated XP-8928. Etch time 140 sec, exposure -8 mJ/cm 2 . SUMMARY Details of a positive tone, high speed (<30 mJ/cm 2), silylated acid hardened resist process using Shipley XP-8928 photoresist have been reported. Silylation with TMSDEA at temperatures above 60 °C and DMSDMA at temperatures as low as 21 TC has been demonstrated to yield case II diffusion characteristics that follow Henry's Law closely. Methods for analyzing silicon depth and contrast have been reported including a novel method of selectively dissolving the silylated material with xylene. Submicron resolution has been achieved, although limited by silylated material overflow and nonlinearity of diffusion depth with respect to geometry size. REFERENCES (1)
S.A. McDonald, H. Ito, H. Hiraoka, C.G. Willson in Proc. SPE (Society of Plastics Engineers, Inc., NY), 177 (1985).
(2)
F. Coopmans, B. Roland, Proc. SPIE, 631, 34 (1986). J.W. Thackeray, J.F. Bohland, E.K. Pavelchek, G.W. Orsula, A.W. McCullough, S.K. Jones, S.M. Bobbio Proc SPIE 1185, 2-11(1990)
(3) (4)
(a) J.W. Thackeray, G.W. Orsula, D. Canistro, E.K. Pavelchek, L.E. Bogan, Jr., A.K. Berry, K.A. Graziano, Proc. SPIE 1086, 34 (1989);
162
(b) J.W. Thackeray, G.W. Orsula, D. Canistro, A.K. Berry, J. Photopolymer Sci. Tech., 2(3), 429 (1989). (5)
Model 150, Genesis, 3066 Scott Blvd, Santa Clara, CA 95054
(6)
Stephen M. Bobbio & Yueh-Se Ho, "Shared Current Loop, Multiple Field
Apparatus and Process for Plasma Processing", U.S. Patent 4,738,761 (May, 1988). (7)
GR Misium, MA Douglas, CM Garza, CB Dobson, Proc SPIE 1262, 74(1990)
(8)
Peter W. Freeman, John F. Bohland, Edward K. Pavelchek, Susan K. Jones, Bruce W. Dudley, Stephen M. Bobbio, Proc. SPIE 1464, in press(1991).
163
PITCH AND LINE WIDTH MEASUREMENTS IN SCANNING PROBE METROLOGY J. E. Griffith, M. J. Vasile, G. L. Miller, E. R. Wagner, E. A. Fitzgerald AT&T Bell Laboratories Murray Hill, New Jersey 07974 D. A. Grigg and P. E. Russell North Carolina State University Raleigh, North Carolina 27695 The high resolution, three-dimensional data provided by scanning probe microscopes make them strong candidates for use in integrated circuit metrology. Pitch and line width measurements are affected, however, by the non-linear behavior of the piezoceramic actuators and of the probe tips. To correct these problems, we have developed a capacitance-based position monitor for the actuator and a method for reproducibly fabricating exceptionally sharp probe tips with a focussed ion beam. INTRODUCTION Scanning probe microscopes offer three-dimensional, non-destructive imaging of all solids in vacuum, air or fluids with resolution that can exceed 1 nm. These instruments are becoming useful tools in integrated circuit metrology where measurement requirements for critical dimensions often exceed the capabilities of optical and electron microscopes. Probe microscopes possess many advantages when making precision measurements [1]. The three-dimensional nature of the data allows surface profiles to be extracted without cleaving or otherwise altering the sample. Probe microscopes are compact and inherently stiff, so they tend to be immune to environmental perturbations that can affect other measurement tools. Probe microscopes are relatively inexpensive, especially those designed to operate in air. The application of probe microscopes to integrated circuit metrology is not completely straightforward, however. Practical measurements often require wide scans over structures with high aspect ratios. Such scans can present much greater challenges for a probe microscope than small, atomic resolution scans over an extremely flat sample. In particular, much greater care is required to assure scan linearity and to reduce distortions arising from the finite size of the tip. We describe here some new techniques we have developed to address these two problems. First, for high precision scans we describe a capacitance-based position monitor that measures the position of the piezoceramic scanner tube. Second, for scanning structures with high aspect ratio we describe a focussed ion beam technique for 164
producing exceptionally sharp probe tips. PITCH MEASUREMENT: A CAPACITANCE-BASED POSITION MONITOR In probe microscopy the position of the tip is controlled with piezoceramic actuators, often to better than 0.01 nm [2]. In the most popular configuration, the tip is mounted at the end of a hollow, radially polled Pb(Zr,Ti)0 3 tube with one, or perhaps both, of its electrodes segmented into four stripes parallel to the tube axis (Figure 1). Vertical motion of the tip occurs when the driving fields on all electrodes change in unison. By differentially driving opposing electrodes, the tube can be bent with a response that is proportional to 12 /r, where 1 is the length and r is the radius of the tube [3]. This bending generates the two lateral components of the tip's motion. Though a long, slender tube with thin walls offers the greatest range, the aspect ratio can not be too extreme because of the effect it has on the stiffness of the system. The resonant frequency of the first flexing mode of a tube with uniform wall thickness is inversely proportional to 12 /r [4]. The lowest resonance, which can be as low as a few kilohertz, constrains the bandwidth of the feedback loop that maintains the tip's vertical position relative to the surface. The bandwidth in turn sets the scan speed for a given topography, so the aspect ratio of the tube involves a compromise between range and scan speed. Commercial instruments now offer piezo tubes with high scan speeds and range greater than 100 .tm. Piezoceramics such as lead zirconate-titanate are used because they can be formed into tubes and because they have high sensitivity. These materials are, however, ferroelectrics, so they suffer from severe hysteresis [5,6]. In the scan, the out going trace does not follow the same path as the return trace. Furthermore, after a large change in position, a piezo tube can exhibit creep for over an hour. Most efforts to correct for the hysteresis have involved attempts to linearize the tube response either by numerically adjusting the potential across the electrodes or by controlling the charge delivered to the electrodes [7,8]. These methods are not suitable for metrology because they exhibit time dependent errors of a few percent that do not admit further correction. The nonlinear processes at work in the piezoceramics are too complicated to be accurately modeled. A more reliable method is to independently monitor the tube position. Yamada, Fujii and Nakayama [9] monitored the scans generated by a flexure stage with an optical interferometer. Though precise to within a few nanometers, the optical components in the system were cumbersome and expensive. Since the lateral range of the piezo tube is usually 100 gtm or less, we chose to monitor the scan with capacitors, which are simpler and cheaper but nearly as precise. The capacitor plates shown in Figure 1 were cleaved from polished silicon wafers. A second set, not shown, monitors the head position along the orthogonal axis. The area of the capacitors is 3 mm x 10 mm. When the head is at its center point, the gaps between the plates are approximately 50 gim, yielding a capacitance of 5 pf. The outer plates
165
Figure 1. Schematic diagram of a scanning probe microscope with a capacitancebased position monitor for the scan generator. The segmented outer electrode for the piezo tube is shown. The motor must bring the probe tip up to the sample without driving it into the surface. provide the reference points for the scan, so they are mounted on quartz tubes. The system for measuring the capacitance is derived from a technique developed by Miller, et al. [10]. The electronics for one set of capacitor plates is shown in block diagram form in Figure 2. Here an = 1.5 MHz RF oscillator is used to produce a 900 phase-shifted drive to the lower capacitor plate. The magnitude of the RF drive is arranged to be accurately proportional to the magnitude of the system output voltage by virtue of the action of the RF chopper. The resulting displacement current flowing through the capacitor plates is measured (by a synchronous detector) and compared with a stable reference value. Any difference between the two is integrated and fed back as the drive voltage, thereby providing the system output voltage. This output voltage is therefore constantly servoed to such a value as to provide a constant displacement current through the capacitor plates, which implies that the output voltage itself is proportional to the capacitor plate spacing. This scheme has four basic advantages: it is inherently linear in the gap x when the plates are parallel; the tuned amplifier and synchronous detector have no wide-range linearity requirement since they both operate at constant signal magnitude at all times; the signal-to-noise ratio itself is constant and consequently the position noise is independent of x; and the measurement plates can be mounted at the end of long cables. The wide-band noise in the monitor electronics is 1 mV, which translates to 0.1 nm/-H-z-z. Since the conversion factor for the capacitors is about 10 ýtm/V, the induced error in the position measurement is 10 nm. 166
SYNCHRONOUS DETECTOR ENCE UT
TPUT
RFCHOPPER
Figure 2. Block diagram of the electronics for the position monitor. Errors can arise from misalignment of the capacitor plates. If the two plates have a relative tilt of ax, the capacitance deviates from a purely hyperbolic dependence on the gap, so the monitor output, which is inversely proportional to the capacitance, is no longer linear. The expression for this case is easily derived if we note that the charge density on the plates is e.v, where e is the permittivity, V is the voltage drop ar across the plates, a is the tilt angle, and r is the perpendicular distance from the intersection of the two planes [11]. Integrating along the plates, which have width W, we obtain the capacitance, [1+Ltan(a)
1
2x Ltan(a) [
C= We a
L
2x
J
L which is valid when x>cz-L.
For small a, we have
>2
where the area A = WL. The error term in this case is a few percent of the total value. In addition, if the plates are not properly aligned with the axis of the tube, they will register an erroneous lateral motion with the tip moves vertically. Its presence is, however, easily detected because ghost images of tall objects will appear in plots of the capacitor output. The most effective way to deal with the error is to remove it 167
numerically. As described by Carr [3], the end of ,the tube tilts during lateral motion, causing the tip to swing relative to the reference plates. The size of the error is directly proportional to the distance between the tip and the end of the piezo tube, so it can be reduced by keeping that distance short. iThe 6 mm tip length in our microscope produces a swing of approximately 10 nm/V. If the capacitors are calibrated relative to a stage micrometer, the correction for the tip swing will be automatically included if the tip length is not changed afterward. The preformance of the system was checked by calibrating it with a twodimensional holographic grating. Over a 7 4im scan the capacitor output was linear to better than ±20 nm. The main error in the calibration actually arose from variations in the shape of the bumps in the grating. A convenient primary standard for widescan probe microscopes does not exist. LINE WIDTH MEASUREMENT: PROBE TIPS SHARPENED WITH A FOCUSSED ION BEAM The challenge in line width measurement occurs at the side walls of tall features because the width of a lithographically patterned object can not be known without measuring the shape of the sides, which are the least accessible part of the pattern. To make the problem even worse, side walls are often undercut. As in optical and electron microscopy, the ultimate limit to a probe microscope's ability to image a side wall is encountered in the interaction between the probe and the sample. In our case, no fundamental physical principles are involved; it is simply a question of tip size and shape. In most cases, the characteristic dimensions of the probe tip must be smaller than that of the features being scanned. Fortunately, the same processes used to fabricate the sample can often be used to sculpt the tip. The atomic resolution for which probe microscopes are famous can be misleading when considering the capabilities of such a microscope over a surface with steep topography. Atomic resolution arises from the configuration of a few atoms at the apex of a tip that may otherwise be quite blunt. A tip that can resolve atoms may be utterly incapable of discerning the shape of a quarter micron wide trench. When attempting to scan an object 1 .im deep, for instance, the tip shape must be known, and controlled, at least 1 pm from the apex. The finite width of the probe tip will induce errors, which can sometimes be numerically corrected. A scan requiring correction is shown in Figure 3 where a blunt probe tip encounters a moderately steep side wall. The point of closest approach, or proximal point, is indicated by the black dot. When the probe is scanning a flat region, the proximal point will coincide with the apex, but on a slope it wanders away from the apex. We describe the displacement of the proximal point from the apex with a shift vector, which must be determined if an accurate representation of the surface is to be extracted. This extraction is often called "deconvolution", which is unfortunate
168
terminology since convolution implies a linear process. The interaction of a probe tip " with any surface, flat or otherwise, is not linear [12].
Figure 3. Behavior of the proximal point when a blunt probe tip encounters an incline. The arrow indicates the shift vector. The problem of extracting the true surface from a scan has been discussed in several papers [13-15]. The extraction is not always possible. If, for instance, a blunt tip does not reach the bottom of a narrow trench, then only a lower bound for the depth is available. In Figure 3 the extraction is possible. Neither the tip nor the sample has a cusp at the proximal point, so the tangent planes of the two surfaces are parallel. The slope of the scan thus tells us the slope of the tip at the proximal point. For some tip shapes, the slope uniquely determines the shift vector. For instance, a parabaloidal tip allows such a determination, while a conical tip does not. Clearly, the shape of the probe tip must be accurately known. The probe shape can be measured with an electron microscope, but a better method is to use the probe microscope itself in conjunction with a known measurement structure. In Figure 4 we show how a trench or hole with vertical side walls can be used to determine the shape of the tip. As the tip drops into the hole, the proximal point stops at the lip and begins to generate a scan of the probe tip itself. With the tip shape in hand the most general way to perform the surface extraction would be to generate a look-up table associating a shift vector with each element in a small array of slopes. Alternatively one might fit the tip with a simple geometrical shape and then perform the extraction analytically. It is important that the tip characterization be performed after the data are collected. Under some circumstances the tip can be altered by the scanning; a tip that is sharp before a scan may not be so while the data are being taken.
169
Figure 4. A method for measuring the shape of the probe tip using the probe microscope and a known structure, in this case a hole. Because of the steep side walls, the image over the hole reveals the shape of the tip. Ideally one wants to have a tip so sharp that the correction to the scan is insignificant. Several papers on tip shaping techniques have been published most of them describing electrochemical etching procedures [16-20]. In some cases electrochemical etching produces tip radii as low as 10 nm, but such shapes are not easily reproduced. We have found that machining the probe with a Ga÷ focussed ion beam yields superior results [21]. The technique is shown in Figure 5. A 1.5 nA beam with 0.4 gtm with FWHM impinges on the probe along its axis. Several cuts with an annular raster produce a tip with radius of curvature as small as 4 nm. The probe typically widens to 0.2 pgm at a distance of 1 p.m from the apex. The dose required for the machining is roughly 10t 9 /cm 2 . Several tips can be prepared in an hour. Two SEM images of one of our Ir tips is shown in Figure 6. Focussed ion beam sharpening works with any stable material. When held vertical to the sample, the tip in Figure 6 can not directly scan a vertical side wall or a side wall that is undercut. At best is can establish an outer bound for the wall. That does not mean, however, that vertical side walls are inaccessible to probe microscopes. They have, in fact, been scanned by tips held at a small angle relative to the vertical. The disadvantage to this trick is that the side walls are not simultaneously accessible in all orientations. A better method is shown in Figure 7 where a probe with a flared bottom is used. Such a probe has not yet been successfully employed because a new feedback algorithm for this situation must be 170
I
41
1
0ks
Ga
I<9I
i
INITIAL CUT
FINAL CUT
Figure 5. Procedure for sharpening probe tips with a focussed ion beam. The beam is rastered across the apex in an annular pattern. developed. The present tunneling microscope designs pull up when they sense too much tunneling current. Clearly, that response would be inappropriate with a flared tip under an overhang. With modern digital feedback electronics, designing a more sophisticated three-dimensional algorithm should be possible. CONCLUSION We have shown how to correct those aspects of probe microscopes that affect the linearity of their behavior, which is the most critical problem in precision pitch and line width measurements. We have not discussed many other important issues in making practical measurements on lithographically patterned samples. An important advantage of probe microscopes is that they offer many choices among contrast mechanisms and ambient conditions. For integrated circuit metrology, where insulators are frequently encountered, scanning force microscopes will be especially important [22,23]. Though the scan speed of these instruments is relatively slow, their simplicity and small size will allow designs in which multiple probes operate in parallel. Probe microscopes are still very recent inventions. As they mature, we can expect their performance to steadily increase.
171
10Mm
3#m
Figure 6. Scanning electron microscope images of a focussed ion beam sharpened Ir tip.
Figure 7. A flared probe tip for scanning an undercut wall. 172
ACKNOWLEDGEMENT D. A. Grigg and P. E. Russell acknowledge the support of the National Science Foundation Presidential Young Investigator Award Program (DMR8657813) and of AT&T Bell Laboratories. REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23]
E. C. Teague, J. Vac. Sci. Technol., B7, 1898 (1989). Y. Kuk and P. J. Silverman, Rev. Sci. Instrum., 60, 165 (1989). R. G. Carr, J. Microscopy, 152, Pt.2, 379 (1988). T. Tiedje and A. Brown, J. Appl. Phys., 68, 649 (1990). 0. Nishikawa, M. Tomitori and A. Minakuchi, Surf. Sci. 181, J. E. Griffith, G. L. Miller, C. A. Green, D. A. Grigg, and P. E. Russell, J. Vac. Sci. Technol., B8, 2023 (1990). C. V. Newcomb and I. Flinn, Electron. Lett., 18, 442 (1982). H. Kaizuka, Rev. Sci. Instrum., 60, 3119 (1989). H. Yamada, T. Fujii, K. Nakayama, Japn. J. Appl. Phys., 28, 2402 (1989). 6G. L. Miller, R. A. Boie, P. L. Cowan, J. A. Golovchenko, R. W. Kerr, and D. A. H. Robinson, Rev. Sci. Instrum. 50, 1062 (1979). P. M. Morse and H. Feshback, Methods of Theoretical Physics, (McGraw-Hill, New York, 1953). J. E. Griffith and G. P. Kochanski, Annu. Rev. Mater. Sci., 20, 219 (1990). Ph. Niedermann and 0. Fischer, J. of Microscopy, 152, 93 (1988). G. Reiss, F. Schneider, J. Vancea, and H. Hoffmann, Appl. Phys. Lett., 57, 867 (1990). D. Keller, to be published. P. J. Bryant, H. S. Kim, Y. C. Zheng, and R. Yang, Rev. Sci. Instrum., 58, 1115 (1987). T. lijima and K. Yasuda, Jpn. J. Appl. Phys., 27, 1546 (1988). H. Lemke, T. G6ddenhenrich, H. P. Bochem, U. Hartmann, and C. Heiden, Rev. Sci. Instrum., 61, 2538 (1990). I. H. Musselman and P. E. Russell, J. Vac. Sci. Technol., A8, 3558 (1990). J. P. Ibe, P. P. Bey, Jr., S. L. Brandow, R. A. Brizzolara, N. A. Burnham, D. P. DiLella, K. P. Lee, C. R. K. Marrian, and R. J. Colton, J. Vac. Sci. Technol., A8, 3570 (1990). M. J. Vasile, D. A. Grigg, J. E. Griffith, E. A. Fitzgerald, and P. E. Russell, to be published. G. L. Miller, J. E. Griffith, E. R. Wagner and D. A. Grigg, Rev. Sci. Instrum., 62, 705 (1991). S. A. Joyce and J. E. Houston, Rev. Sci. Instrum., 62, 710 (1991).
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EXTENDING A 0.35 NA h-LINE STEPPER TO 0.8 MICROMETER (1.6 MICROMETER PITCH) CMOS TECHNOLOGY USING TRILAYER TEMPLATES AND HALO LDD DEVICES K.W. Markus, S. Goodwin-Johansson, W. B. Rogers and W. C. Donaldson MCNC Center for Microelectronics PO Box 12889 Research Triangle Park, NC 27709 A fully scaled 0.8 micron (1.6 Irm pitch) CMOS process which can be used to extend the usable life of equipment one generation beyond its intended life is described. The process utilizes a double spacer halo LDD device and a Si template trilayer resist process to produce 0.8 micron features over topography using a 0.35 NA h-line stepper. This process has been used to manufacture a 1.5 million transistor circuit, Bioscan. INTRODUCTION In an industry where the cost of a single piece of semiconductor manufacturing equipment may easily exceed the $1 million mark, it is prohibitively expensive to completely re-engineer a process line with each technological step. The time involved in re-capitalizing a line, developing and characterizing the new equipment and processes can also make each step forward prohibitive in both time and money. We have developed a method for extending the capability of a mid-NA h-line stepper, designed for 1.2 micron technology, to fabricate a fully scaled 0.8 micron CMOS process with effective channel lengths of 0.59 +/- 0.18 microns. This method can also be used to extend the usable range of high-NA g-line or i-line machines. The process provides considerable advances in feature size (0.8 micron contacts and vias, 0.8 micron lines/spaces poly and metal 1), packing density (factor of 2.1), and performance (table 1). Only 9 maskings are required to fabricate a double level metal circuit. The reduction in mask count is accomplished through the use of lift-off lithography for the well and source/drain levels, which provides self-alignment of the implants. A photoresist mask is used to define the well and n channel stop implant regions (or NMOS region for the source/drain levels). The dopant is implanted and then titanium is deposited. The photoresist has a retrograde profile which provides the break-point for the metal liftoff. After the titanium/photoresist stack is lifted-off in solvent, the p punch-through and channel stops are implanted (or PMOS region for the source/drain levels).
174
Table 1: 0.8 trm CMOS Device Parameters Gate length Gate oxide Poly line/space Metal 1 line/space Metal 2 line/space Contact Via 1 Metal 1 - contact head size Metal 2 - via head size Current drive (mA/ljm) Vt (V) Sub-Vt slope (worst case) (mV/decade) Mobility (cm 2 N-sec)
0.59 ± 0.18 urm 17.5 nm 0.8/0.8 ý±m 0.8/0.8 ýIm 1.0/1.0 i.Lm 0.8 gLm 0.8 ltm 1.8 jim 2.2 jim N 530 0.70 120 404
P 240 -0.65 110 166
Process Technology - The 0.8 micron CMOS process is a retrograde n well process which has evolved from MCNC's 1.2 micron CMOS process.[l]. The starting material is a thin epitaxial P layer on P+ wafers, which provides latchup immunity. A pad oxide is grown and nitride is deposited. The active layer is patterned and etched. The n well, channel stops and p-punch through regions are defined and implanted utilizing the self-aligned lithographic method mentioned above. A field oxide is grown and the nitride and pad oxide are stripped in a conventional ONO strip. A 175 A dry gate oxide is grown in HCI, and a common Vt adjust implant is performed. CVD polysilicon is deposited and doped in a POCI3 process. The poly layer is patterned and then etched in an RIE system. The device employed is a double sidewall spacer, halo implanted medium LDD device. After the NMOS and PMOS regions are defined, a CVD oxide layer is deposited. The trilayer template process is used to define the 0.8 micron contacts and etching is performed in an RIE system. Metalization is a laminated layering of Ti - AICu - Si - Ti, defined in a trilayer template defined liftoff process. A polyimide film is spun on the wafers to provide the intermetal dielectric layer, which is also employes the trilayer template to define the 0.8 micron vias. Etching is performed in an RIE system. Metal 2 is a laminated layering of Ti - AICu, defined in a liftoff process.
175
LITHOGRAPHY The process utilizes a GCA 5x, h-line stepper with an NA of 0.35. In order to utilize the h-line stepper for submicron technology, processes which improve resolution and focus response are necessary. For reasonably planar levels, such as active (nitride) or polysilicon, reducing the nominal resist thickness 30% is sufficient. Table 2: Polysilicon shorting failures for differing PR thicknesses Line/space 0.8 gm 0.7gm
(all values normalized to 0.964 meter length) 0.8 lam PR 1.0 gm PR 1.25 gam PR 6.73±1.80% 8.89±1.13% 7.65 ±0.975% 19.02±1.69% 12.61±1.17% 10.09±1.2%
Comb-serpentine structures etched on poly using different resist thicknesses indicate that while resist thickness does not seem to significantly affect 0.8 jim line/spaces, at 0.7 gm line/spacing a 20% reduction in resist thickness improves the shorting defect density by 33%, while a 36% reduction in resist thickness improves it 47% (table 2). Trilayer resist - For contact, metal 1 and via 1, where varying levels of topography exist, single layer resist processes are inadequate to resolve submicron features. Therefore we have developed a trilayer resist process for use at these levels. The trilayer process consists of a thin imaging resist layer and a hard mask layer deposited over a planarizing organic film (either PMGI or Probamide 285 soluble polyimide). Two types of materials are available for the hard mask layer; spin-on-glass (SOG) or evaporated films. Because of the optical transparency of SOG, underlying topography can cause severe reflective necking unless a dyed or anti-reflective layer is used (figure 1). In addition, the SOG is an insufficient etch barrier for subsequent contact RIE and wet chemical processing. We utilize an evaporated Si layer which is essentially optically opaque, eliminating the reflective necking problem (figure 2). The Si is not reactive in the subsequent etching processes required for contacts, vias, or the lift-off metal process. The Si templates are evaporated in a Balzers rf evaporator and increase the total raw process time only 1.4%. The Si layer also provides an etch barrier which improves contact and via biases. Using RIE technology, vias etched in polyimide with a single layer resist process exhibit biases of 0.4 - 0.5 microns. Use of the Si hard mask reduces the bias for a 0.8 micron via to 0.12 +/- 0.1 microns. Contact chain yield wafers for single layer resist and the trilayer Si template were run. For the Si template process the defect density was 5.6 E-7/contact while for the single layer resist process the defect density was 2.4 E-5/contact.
176
Figure 1 Reduced metal space (gap = 0.08 lim) caused by reflective necking
Figure 2 Reflective necking eliminated by Si template (gap = 0.6 lam)
Liftoff Metal Patterning- When the lift-off template for metal 1 is created using evaporated silicon, the impermeable nature of the Si film can influence the characteristics of isolated metal features. Outgassing from the organic release layer during metal evaporation is channeled into the isolated spaces where the metal is depositing, and is incorporated into the deposited metal film. This can reduce the conductivity of the isolated narrow metal lines (table 3) and create cone-shaped metal lines (figure 3). This affect can be seen on deposited metal regardless of the length of the lines, e.g. long metal lines or small deposited via-plugs. The occurrence of the coned metal plugs seen in vias has been successfully modeled by Kellam et al.[3] There are several methods that can be employed to eliminate the coning problem. First, the outgassing of the organic layer can be minimized, or eliminated, by the use of a pre-deposition bake with or without a heated metal deposition. Experiments have shown that the addition of 30 minutes bake time during evaporator pump down is sufficient to eliminate the worst case outgassing (figure 4). Secondly, the circuit designer can eliminate the occurrence of highly isolated narrow metal 1 lines through the use of "tiling", where small metal islands are fabricated adjacent to an isolated line, thereby eliminating the isolation. Non-isolated metal does not exhibit the effects of coning, since a much larger area is provided for the material to outgas. A software routine has been utilized to help automatically identify and eliminate largely isolated features where this affect can occur. Parasitic capacitance effects can be minimized by the appropriate choice of a
177
tiling algorithm, and with correct spacing between the tiles and the active metal. Finally, work is currently in progress on the incorporation of permeable \templates. This would allow the organic material to outgas through the entire patterned surface of the wafer.
Figure 3 0.8 gim metal line deposited with Si template
Figure 4 0.8 lIm metal line deposited with Si template and heated metal deposition
Table 3: Resistance of isolated and non-isolated lines Non-isolated line Isolated line Short 0.8 lam metal line 95 f 4220 Long 0.8 lm metal line 175 Q 834 Q
DEVICE TECHNOLOGY Device Design - The devices operate at 5 V by utilizing a double spacer medium dose LDD technology to provide hot electron reliability with minimized current loss. An unmasked arsenic halo implant is performed to improve the short channel behavior of the PMOS device without degrading the short channel performance of the NMOS device. A halo dose of 8 E12 reduces the process induced short channel AVt of the nominal channel length PMOS device by 170 mV, while increasing the long channel Vt by only 97 mV (figures 5,6).
178
0.35 0.30 0.25 S0.20 0.15 0.10 0.05 0.00
,
-le+12 Oe+0
•
,
•
-
•
1e+12 2e+12 3e+12 4e+12 5e+12 6e+12 7e+12 8e+12 9e+12
Halo Dose Figure 5 Short nominal Vt (at high Vd) minus long nominal Vt (at low Vd) as a function of halo dose [N
1
-05.6 -0.61 -0.63 -0.65
"> -0.67 -0.69 -0.71 -0.73 -0.75 . -1+12 0e+O
. . le+12 2e+12 30+12 4e+12 5e+12 6e+12 7e+12 8e+12 9e+12
Halo Dose Figure 6 Dependence of long channel PMOS Vt on halo dose The first spacer offsets the LDD implants from the gate edge, reducing their lateral extension into the channel and hence reducing the gate overlap capacitance. The first spacer also increases the effectiveness of the halo without resorting to large tilt angle implantation. The phosphorous LDD overtakes the arsenic halo, thereby minimizing its effect on the NMOS device. The second spacer offsets the source/drain implant. The P+ source/drain outdiffuses sufficiently to compensate the As halo, preventing any increase in the diffusion capacitance to the n-well. Reliability - The choice of which device parameter should be monitored as a measure of circuit performance degradation can lead to widely varying values of device lifetime.[4] Traditionally, the threshold voltage and transconductance at low drain biases have been monitored or the short
179
nominal device for shifts of 100 mV and 10%, respectively, to determine end-oflife. The short nominal device is the shortest channel length transistor that will result from normal process variation (lithography, poly etch, etc.). The linkage between these two device parameters and circuit degradation is not clear. The increase in the measured threshold voltage and the decrease in measured transconductance result in a decrease in current drive. However, due to the localized nature of hot carrier damage, a direct quantitative relationship between those device parameters and the current drive is very difficult to obtain. Thus a more direct measure of circuit degradation, due to the charge/discharge nature of digital CMOS circuits, is to monitor the drain current. The time required for an NMOS transistor to discharge the gate for the next stage to below the switching point (typically Vdd/2) will determine the speed of the circuit. Thus, monitoring the drain current degradation between Vdd and Vdd/2 should be an accurate measure of circuit performance degradation. The other device parameter of importance in determining device lifetime is the leakage current of the transistor when it is turned off by the gate.
[5] Lifetime Testing - Circuit designers typically design to ensure meeting performance specifications with a worst case fabrication run (long channel lengths). Thus the added performance in a best case fabrication run is not needed and can be sacrificed to hot carrier degradation. If the allowed circuit speed degradation is 10%, a bias point can be chosen that reflects the drain current degradation over the range of the output node voltage falling from the rail to the switching point. Thus the end-of-life criterion for reliable circuit operation is then 90% of the unstressed drain current at that bias point for the long nominal transistor. Whichever transistor under stress, short or longnominal, first degrades to that current level will determine the device lifetime. Lifetime testing on the halo LDD devices indicates that the long nominal device is the limiting device and that 5 V operation is reliable at a circuit performance level.
180
Circuit Fabrication - A double level metal circuit, Bioscan, has been fabricated using this process (figure 7). The chip is 7750 x 9050 microns and contains 1.5 million transistors at a density of 46.6 Jgm2 /transistor. The chip is
designed to operate at 50 Mhz at 5 volts, and has been tested up to 66 Mhz at 5 V. [5]
Figure 7: Bioscan Circuit CONCLUSION A fully scaled 0.8 micron (1.6 micron pitch) process which can be used to extend the usable life of equipment one generation beyond its intended life has been described. The process utilizes a double spacer halo LDD device and a Si template trilayer resist process to produce 0.8 micron features using a 0.35 NA h-line stepper. The trilayer process can also be utilized on I-line and high-NA g-line machines to extend their usable range. This process has been used to manufacture a 1.5 million transistor circuit, Bioscan.
ACKNOWLEDGEMENTS The authors would like to thank the personnel of the MCNC fabrication facility for their help in processing the many runs related to the development of this process. We would also like to thank Carlton Osburn and Mark Kellam for their helpful discussions.
181
REFERENCES [1] D. Sharma, S. H. Goodwin-Johansson, D-S. Wen, C-K. Kim and C. M. Osburn, "A 1 CMOS Technology with Low Temperature Processing" Proceedings of 1st ULSI Symposium, pg 49 May 1987 [2] P. Magill, to be published [3] M. Kellam, B. Rogers, R. Sayer, R. Chapman, "Simulation of Metal "Cone" Formation in a Tri-Layer Liftoff Process", This Conference [4] J. Winner, A. Loll, D. Schmitt-Landsiedel, M. Orlowski, F. Neppl, "Influence of Transistor Degradation on CMOS Performance and Input on Lifetime Criterion", 1988 IEDM [5] S. Goodwin-Johansson, to be published [61 W. Detloff, R. Singh, T. White, "50Mhz 1.5M Transistor ASIC for Biosequence Analysis", Proceedings of 1991 ISSCC
182
A CHARGE-REDUCING PROCESS USING A CHARGE TRANSFER COMPLEX IN ELECTRON BEAM LITHOGRAPHY Keiko Yano, Takashi Maruyama, and Koichi Kobayashi U-LSI Development Division, Fujitsu Limited 1015 Kamikodanaka, Nakahara-ku, Kawasaki 211, Japan A novel process that reduces charging in electron beam lithography was developed by using a TCNQ complex salt as the charge reducing film and a thermal cross-linkable EB positive working resist. The process is simple, and effectively reduces placement errors caused by charging. The charge reducing film was analyzed by using a scanning electron microscope. The structure of TCNQ complex crystals in the film relates to charge reduction. We optimized the conditions for film formation and grew 0.02 gm thick charge reducing film. Introduction Electron beam lithography is very useful for making micro patterns. Charging of the resist and substrate by the electron beam produces placement errors and mis-alignment in the lithography [1,2]. One way to prevent this is to apply a thin conductive film over the resist layer [1,3,4]. We uses a polymer that contains a TCNQ-complex salt [5] to reduce the charge formation [6,7,81. Materials and Processes To avoid charge formation during electron beam exposure, a polymer solution was used. This solution was prepared by Nitto Chemical Industry Co.,Ltd. and consists of a TCNQ-complex salt as shown in Fig. 1, a binding polymer and an organic solvent [6]. TCNQ complex salts are highly conductive with organic compounds and contains no metal [5,6,9,10]. The solution grows TCNQ complex crystals in the binding polymer and a conductive film is formed by spin coating.
NC-eCN
NCN CCN
NC
NC
C
N-octylisoquinolinium
.CN
TCNQO
C
CN
TCNQ°
Fig.l N-octylisoquinolinium-TCNQ complex salt 183
The film was formed over positive working EB resist CMR [11] and its effectiveness in charge reducing was tested. CMR is a thermal crosslinkable positive working resist. It consists of two types of polymers cross-linked in three dimensions by pre-baking at 140 °C or higher and becomes insoluble in almost all organic solvents after being cross-linked. When we use CMR and a charge reducing film with an organic solvent, there is no intermixing between layers. This process is shown in Fig. 2. The charge reducing film was removed during CMR resist development. This procedure adds only one step to the conventional resist process. CMR resist pattern cross sections with and without a 0.2 gIm charge reducing film after development were observed. Patterns were lines with 1.0 gtm period. There was no intermixing and no traces of layer after removal of charge reducing film. Effectiveness in Reducing Charge Formation 0.2 gim thick charge reducing film were coated on CMR resist, and placement error was investigated. Figure 3 shows the placement error caused by charging in chip corner with CMR resist and a 0.2 jim charge reducing film. The substrate is silicon wafer with an aluminum layer. Without charge reducing film, the placement error increases with resist thickness. When the charge-reducing film is added, almost no placement error occurs, even if the resist is quite thick. Figure 4 shows 1.5 gim thick CMR resist patterns with and without a 0.2 gim charge-reducing film on a quartz substrate. This process also improved the placement accuracy on insulator.
I
CMR resist coating and baking at 180"C Alsub
11111 IIll
Charge reducing film coating and baking at 70'C Resist only
Electron beam exposure
•
0.5 E •
Ca
-
,,/.With chargereducing film
-
p-.
0
Development
e
1.0
2.0
Resist thickness (,im)
Fig. 2 Steps in charge-reducing process.
Fig. 3 Placement error dependence on thickness of resist.
184
3.0
200grm Resist only
200g•m Using charge-reducing film
Fig. 4 Resist patterns on quartz substrate.
The Effect on Film Thickness The benefits of this process to ULSI lithography were investigated. The thickness of the resist and charge reducing film related to the resolution of micro patterns. As the patterns become smaller, thinner film should be needed. To study the dependence of the placement error on film thickness [81, we coated the CMR resist with charge reducing film of varying thickness. The effectiveness of the charge reduction was verifiable with films 0.05 p.m or thicker, but not with films less than 0.05 g.m thick. Film Analysis We used a scanning electron microscope to study the relationship between the effectiveness in charge reduction and the morphology of the film [8]. To observe the structure of the TCNQ complex salt in the film, the binding polymer was selectively removed with an organic solvent. Figure 5 shows the stacking of needle-like TCNQ crystals in 0.2 pgm film. Fig. 6 shows crystals formed in the 0.04 ptm film, which does not reduce charging. Crystals are small and isolated. It was found that the network of needlelike TCNQ crystals must form in the film to obtain sufficient charge reduction. Thus, growing more TCNQ crystals was needed for the thin film to be effective.
185
1.0 g~m
1.0 gzm
Fig. 5 A SEM photomicrograph of 0.2 gim thick charge reducing film.
Fig. 6 A SEM photomicrograph of 0.04 pm thick charge reducing film
Making Effective Thinner Film It was thought that two factors were important in growing the crystal network. One was time. Since crystals grow mainly during spin coating, it was assumed that if solvent evaporated slowly during film formation,,the time needed for crystal growth would increase. The other factor was the composition of materials in the film. This film is made of TCNQ complex and the binding polymer. So the concentration of TCNQ in the film increase, The crystal-network should be able to grow easily. The polymer solution was diluted in solvent and film less than 0.05 gim thick was formed by varying speed of spin coating. Larger crystals were observable in the film made at a low speed. In addition, we investigated the ratio by weight of the TCNQ complex salt to the binding polymer in the solution. Figure 7 shows TCNQ crystals in 0.02 gim film whose solution contained TCNQ complex salt 10 times as much as ordinary one. The network of crystals could be obtained even if the film was quite thin. Figure 8 shows placement error with CMR and 0.02 gm thick charge reducing film made from the new solution. The charge reduction can be obtained for the thin film.
186
1.0 gm Fig. 7 A SEM photomicrograph of 0.02 gim thick charge reducing film whose solution contained TCNQ complex salt 10 times as much as ordinary one.
1.0
0.5
-Resist
only
E With0.02 pm thick charge-reducing film made from the new solution
0
0
0 2.0 1.0 Resist thickness (pm)
1 3.0
Fig. 8 Placement error with CMR resist and 0.02 gm thick charge reducing film made from the new solution.
Figure 0.02 gm with 0.3 of resist
9 shows cross sections of CMR resist patterns with and without charge reducing film after development. The patterns show lines gim period. The charge reducing film does not affect the resolution micro patterns.
187
(a)
(b)
0.5 gIm
0.5 gim
Fig. 9 Cross sections of CMR resist after development for lines with 0.3 gtm period. (a) Resist only (b)Resist using 0.02 jim thick charge reducing film. Conclusion A novel process has been developed which uses a TCNQ complex salt foý the charge reducing film as top layer. Placement error data show that this process to be excellent for reducing charge formation. We observed the structure of the TCNQ complex salt in the film by SEM. The effectiveness Crystals of the of the film is related to the TCNQ crystal structure. complex must be interconnected in a network to obtain sufficient Optimizing film forming conditions enabled us to grow conductivity. TCNQ crystals in very thin film less than 0.02jtm thick without adversely affecting the resolution of sub-micro resist patterns. Acknowledgment Yoneda and We thank Nitto Chemical Industry Co.,Ltd., Messrs Watanabe of Fujitsu Laboratories Ltd., and Nippon Zeon Co., Ltd. for their help and advice References (1) Guenther 0. Langner Proc. Microcircuit Engineering 1979, P. 261. (2) Donald K. Atwood, Paohua Kuo, Sheila Vaidya, and Kevin D. Cummings
188
Proc. SPIE, San Jose, 1989 Vol. 1089, P. 358. (3) M. Kakuchi, M. Hikita, A. Sugita, K.Onose, and T. Tamamura J. Electrochem. Soc. 133, P. 1755 (1986). (4) H. Watanabe and Y Todokoro IEEE Trans. on Electron Devices, 36 No. 3, P. 474 (1989). (5) L. R. Melby, R. J. Harder, W. R. Hertler, R. E. Benson, and W. E. Mochel J. Am. Chem. Soc., 84, P. 3374 (1962). (6) T. Nakamura and K. Kikuchi Function and Materials, October, P. 32 (1989) [in Japanese]. (7) Y. Kawasaki, Y Yoneda, K. Saito, S. Fukuyama, and S. Shiba The47th fall meeting, Japan Soc. of Applied Physics and Related Societies, (1986) P. 310 [in Japanese]. (8) K. Yano, T. Maruyama, and K. Kobayashi Digest of Papers 1990, 3rd Microprocess Conference, P. 76. (9) Jerome H. Perlstein Angew. Chem., Int. ed. Engle., 16,P. 519 (1977). (10) L. B. Coleman, M. J. Cohen, D. J. Sandman, F. G. Yamagishi, A. F. Garito, and A. J. Heeger Solid-State Communications, 12, P. 1125 (1973). (11) T. Kitakohji, Y Yoneda, and K. Kitamura J. Electrochem. Soc., 126, No. 11, P. 118 (1979).
189
CHARACTERIZATION OF A NEW SUBMICRON I-LINE PHOTORESIST L. N. Nguyen, J. R. Johnson, G. J. Stagaman .and W. Y. Hata* Advanced Technology Development SGS-THOMSON MICROELECTRONICS, INC. 1310 Electronics Drive, MS 2200 Carrollton, Texas 75006 A new submicron I-line photoresist process was characterized and optimized using the vendor supplied process as a starting point. Quantitative outputs such as process window, focus latitude, exposure latitude, linearity, and wall slope were optimized using statistical experimental design. Qualitative outputs such as thermal stability, tapering, and necking were also optimized.
INTRODUCTION Deep submicron photolithography, <0.5 pm critical dimension, now appears possible with I-line illumination systems. However, key to the development of production worthy systems without unreasonable compromises for high numerical aperture (NA) and narrow depth of field are material and process improvements. Improved processes result in lower multiplicative factors in the equation: Minimum Feature = k*A/NA It is generally assumed that k equals 0.8 for production systems. However, some researchers suggest that these improvements may make it more appropriate to use a k factor equal to 0.7 [1]. The possibility of a k factor as low as 0.4 has been reported [2].
BACKGROUND One resist was chosen from several newer I-line photoresists suitable for submicron production [3]. Eventhough the vendor supplied process produced excellent results, additional optimization was required to maximize manufacturability and to be consistent with a lower k factor. In addition, controlled experiments often do not accurately represent the variation in results obtained during volume production. 190
The objective was to develop and fully characterize a process suitable for production with a 0.7 pm final CD. Although, higher resolution was desirable, it was felt that a wider process window at the target critical dimension was more important. In addition, several known, but heretofore unquantified production issues needed to be resolved.
APPROACH A typical process development methodology is described in Figure 1. One at a time experiments were used in place of a statistically defined screening experiment to identify the input variables of interest. Design of experiments and linear regression modeling allows one to anticipate the effect and interactions of changing input variables with a minimum of effort. However, once a model is developed it is not straightforward to tradeoff the effects on several output parameters. One way to optimize the process is to define an objective function which weighs several process conditions of interest. Finally, applied functional testing is required to identify any unanticipated and/or unquantified problems and opportunities. This may require problem solving techniques other than statistical design of experiments. Once a baseline process is defined characterization modeling is again required. All testing was performed using an ASM PAS2500/40 0.40NA, I-line stepper, and an SVG 8800 series coat and develop system. Critical dimensions were measured using a CD measurement SEM.
RESULTS AND DISCUSSION Process optimization began with the vendor recommended process. Characteristic performance parameters, such as resist thickness, film retention during softbake, dark field film loss, linearity, swing curve, and contrast, were obtained. The parameters chosen for process optimization were resist thickness (E,,i, Eax), PEB temperature (115, 120, 125 'C), developer type (A, B, C), and developing time (normalized time, normalized+IS, normalized+30 seconds), based upon the screening experiments. Output responses for optimization were: critical dimension uniformity, exposure latitude, focus latitude, wall slope, and tapering. A D-Optimal design with seven replications was chosen, for a total of 23 experiments. Models for all five responses were defined. Three separate developers were evaluated: Developer A(0.27 N), Developer B(0.25 N, with an additional surfactant), and Developer C(0.24 N). Develop times were scaled for the developers by selecting times for equivalent E.. The focus and exposure results for these three developers are shown in Figures 2 and 3. Developers A and B had comparable results. On the other hand, Developer C apparently had wetting 191
Figure 1. Typical process development methodology.
192
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194
.
problems; exposure latitude was only ±7%and a wide isofocal region could not be found. This developer was dropped from further optimization. An overall objective function was defined to weight the importance of optimizing each response. The scale and weighting of each response is shown in Table 1. Figure 4 is the response surface graph of the objective function. The objective function was maximized with: Emin resist thickness, Developer B, low temperature PEB, and short develop time. Listed in Table 2 are the optimal values of the objective function factors and responses. Short loop testing confirmed that this was a viable process. However, a problem still remained. It had been determined that a 1200C hot plate hardbake was necessary for plasma resistance [3]. A 1200C hardbake without resist flow was obtained with some sacrifice in performance. However, the 1200C hardbake produced inconsistent results when preceded by a 1150C PEB. It was found that increasing the post exposure bake (PEB) temperature greatly improved thermal stability. Examining the model revealed that the tradeoff between overall performance and PEB temperature was small. Increasing the PEB to 1200C improved the hardbake reliability, with little other detrimental effect. The process was recharacterized, using this new baseline as the center point. The optimized process is listed in Table 3.
CONCLUSIONS A process development, optimization, and characterization procedure was described. Statistical design of experiments was used to minimize the number of experimental results required to model the process. Optimized operating conditions were determined by defining an overall objective function, which weighted several output variables. Additional problem solving and figure of merit tests are still necessary to completely understand the process.
ACKNOWLEDGMENTS The authors would like to thank D. Wolf for her work on this project. The support of the resist vendor was outstanding, and greatly appreciated.
*Present address is: LSI Logic, Inc., Santa Clara, CA REFERENCES [1]
B. A. Katz, J. S. Greeneich, M. G. Bigelow, A. Katz, F. van Hout, and J. F. Coolsen, "High Numerical Aperature I-Line Stepper", Optical/LaserMicrolithography III, Victor Pol, Editor, Proc. SPIE 1264, p. 9 4 (1990) 195
[2]
A. R. Neurether, et al., Proc. Microcircuit Engineering,p.53 (1985)
[3]
G. J. Stagaman, N. S. Thane, J. R. Johnson, L. N. Nguyen, and W. Y. Hata, "A Comprehensive Performance Evaluation of I-line Resists for Submicron CMOS Technology", These Proceedings.
Table 1.
The response variable weighting for the overall objective function.
Response CD Uniformity Exp. Latitude Foc. Latitude Slope Tapering
Table 2.
0 Factor,
Priority
Scale
Weighting
B C C C A
0.01 10.0 160 100 0.10
-1,000 +5 +1 +1 -1,000
RS/1 output of the maximized objective function.
Response
1 Range
or Formula 1 Factors 2 PEB 3 DEV TIME 4 RESIST THICKNES 5 DEV TYPE 6 7 Responses 8 CD UNIFO 9 EXP LATITUDE 10 FOC LATITUDE 11 SLOYE 12 TAPERING 13 14 Formulas 15 OBJFUNCTION Converged
2 Initial
3 Optimal
Setting 115 TO 125 30 TO 60 10800,11400 A, B
120 45
Value 115 30 11400 B 0.034926 31.152 80.027 85.74 0.10914
MAX
177.46
to a tolerance of 0.000002
196
after 86 steps.
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Figure 4. Response surface graph of the objective function.
197
0
Table 3.
The optimized process for the new I-line resist.
Coat: Soft Bake: Expose(Eo): PEB: Develop: Hard Bake:
11,400
A
90'C, 45 seconds 75 mJ 120*C, 45 seconds Developer B, 60 sec double puddle 120'C, 60 seconds
198
A COMPREHENSIVE PERFORMANCE EVALUATION OF I-LINE RESISTS FOR SUBMICRON CMOS TECHNOLOGY G. J. Stagaman, N. S. Thane*, J. R. Johnson, L. N. Nguyen and W. Y. Hataf Advanced Technology Development SGS-THOMSON MICROELECTRONICS, INC. 1310 Electronics Drive, MS 2200 Carrollton, Texas 75006 Fourteen formulations of the latest commercially available I-line resists were evaluated as candidates for use in a production worthy submicron CMOS process. The evaluation consisted of several performance tests, some of which were: focus and exposure latitude, wall slope, minimum features, necking, exposure energy, develop time and adhesion. The results show that there is significant variation in performance between resists. The results of all tests are given for comparative purposes.
INTRODUCTION The use of I-line processes for submicron photolithography has rapidly increased, driven in part by the availability of high NA I-line steppers and the increase in the number of commercially available I-line photoresists. Several recent papers have compared the performance of I-line resists [1,2,3]. However, the number of resists examined represented a small fraction of the available products. We invited seven companies representing U.S., Japanese, and European resist vendors to participate in an evaluation of their latest I-line products. The objectives of this evaluation were to determine the relative strengths and weaknesses of each resist and to identify possible candidates for use in a production worthy submicron CMOS process. The vendors were challenged to bring their best resist, developer, and process for submicron imaging on both silicon and highly reflective substrates.
EXPERIMENTAL PROCEDURE The companies and resists included in the evaluation are listed in Table 1. The companies were randomly assigned a letter from A to G. A front end resist (used on all pre-metal levels) from company A will be referred to as resist A, while the back
199
Table 1.
Companies and I-line resists included in the evaluation.
Company
Front End Resist
Back End Resist
Olin-Hunt Shipley Hoechst Celanese Tokyo Ohka Dynachem KTI MacDermid
HiPR-6512 S3810 7110 DI 365i Nova 2030 895i 2015.5AN-24
HiPR-6517GH S3818-J1 7120 DI TSMRCRH-2 2030 AR 895k 2015 ANEZ-28
end resist will be referred to as A'. Each company provided samples of their resists, engineering support for one week and a recommended process for submicron imaging and development. For this evaluation no attempt was made to further optimize the process provided by each resist vendor. Resists A thru G were tested on flat silicon wafers and wafers with both reflective and nonreflective substrate topography. Resists A and E of this group contained reflection controlling dyes, while the other five did not. Resists formulated for patterning on highly reflective substrates (A' - G') were tested on aluminum coated wafers having both flat and underlying topography. All of these resists contained absorbing dyes. Wafers received an HMDS vapor prime and were coated with resist using an SVG 8600 track system. Resist thickness was chosen based on an energy to clear versus resist thickness plot, and usually corresponded to an energy maximum on the plot. Softbake, PEB, hardbake temperatures and times and vapor prime processes used were those recommended by each vendor. No additional processes, such as deepUV exposure, were used. The wafers were exposed with a standard resolution test pattern using an ASM PAS2500/40 stepper. Wafers were also exposed with in-house designed structures to test resist necking and notching over topography. Each resist was developed using the vendor recommended developer and track develop process. The performance tests included in the evaluation are defined in Table 2. All resists were also subjected to standard plasma oxide and metal etches to test their plasma resistance. All critical dimension measurements were made from high resolution, high voltage SEM photographs. RESULTS AND DISCUSSION The results of all tests are listed in Tables 3 and 4. It is interesting to note how resist performances diverge as the test conditions approach those of device wafers. When compared on flat silicon wafers all of the resists performed well. All demonstrated the ability to image lines/spaces (1/s) down to 0.50 pim in a linear fashion. 200
Table 2.
Performance tests used in the I-line resist evaluation.
TEST
Focus Latitude
DESCRIPTION
Change in focus required to shift the CD of a resist line by ±10% with a
Exposure Latitude
Dose To Clear Dose For CD
CD Linearity Minimum Feature
Necking
Maximum Slope Slope Latitude Develop Time
Swing Ratio
Hot Plate Flow
Adhesion (Develop)
0.05 um bias. Change in dose required to shift the CD of a resist line by ±10% with a 0.05 pm bias. Dose required to clear an open field of resist. Dose required to resolve 0.80 jm 1/s (on silicon) or 1.00 pm 1/s (on metal) at best focus with a 0.05 pm bias. Minimum feature imaged where a plot of reticle vs. wafer CD is linear (1.0 to 0.5 um 1/s). Size of minimum 1/s or contacts resolved with no resist residue, wall slope >830 , and <10% bias. Change in CD of a resist line as it crosses over a topography step of known height. The slope of the profile of a resist line at best focus and exposure.
Change in focus required to shift the feature wall slope by 20. Total developer dispense and puddle times for the manufacturer recommended process. Ratio of the energies at a maximum and minimum of the plot of dose to
clear as a function of resist thickness. Maximum temperature for a 60 sec. contact bake with no resist distortion observed on large or small geometries. All resist geometries examined for lifting. No lifting of the resist
should be observed.
201
Table 3.
Results of performance tests for all resists on Si wafers.
TEST Resist Thck. (pim) Focus Lat. (pim) Exposure Lat. (%) Dose to Clear (mJ/cm2 ) Dose for CD (mJ/cm2 ) CD Linearity (pm) Minimum Line (pum) Minimum Space (pum) Necking (pm) Max. Slope (degrees) Slope Lat. (pm) Develop Time (sec) Swing Ratio Hot Plate Flow (°C)
Table 4.
A 1.19 3.8 28 106 155 0.50 0.50 0.80 0.05 90 2.0 81 1.36 110
B 1.19 3.4 39 94 155 0.50 0.50 0.75 0.18 87 1.4 53 1.30 >120
RESIST C D 1.18 1.07 3.4 3.0 38 41 172 85 240 130 0.50 0.50 0.50 0.50 0.65 0.80 0.21 0.12 87 88 2.4 2.8 79 74 1.37 1.41 110 >120
E 1.08 4.0 35 60 110 0.50 0.50 0.85 0.14 89 2.6 30 1.25 110
F 1.19 3.4 44 108 170 0.50 0.50 0.80 0.20 84 1.6 64 1.42 110
Results of performance tests for all resists on Al coated wafers.
TEST Resist Thck. (pm) Focus Lat. (pm) Exposure Lat. (%) 2 Dose to Clear (mJ/cm ) 2 Dose for CD (mJ/cm ) CD Linearity (pm) Minimum Line (pm) Minimum Space (pam) Necking (pum) Max. Slope (degrees) Slope Lat. (pm) Develop Time (sec) Hot Plate Flow (°C) Adhesion (Develop) Plasma Etch
B'
C'
1.83 4.8 40 160 210 0.60 0.60 0.70 0.12 84 2.1 53 >120 Fail Fail
1.80 3.6 18 205 340 0.70 0.70 0.70 0.22 87 2.6 69 120 Pass Pass
202
RESIST E' D' 1.84 3.0 42 145 145 0.80 0.70 0.80 0.20 87 1.6 69 >120 Fail Pass
1.98 4.2 40 115 125 0.70 0.70 0.70 0.25 89 2.1 30 114 Fail Fail
F'
G'
1.81 4.8 39 140 175 0.70 0.60 0.70 0.25 88 1.1 79 >120 Pass Pass
1.80 4.8 43 155 245 0.60 0.60 0.70 0.16 86 2.1 30 114 Pass Fail
The focus and exposure latitudes were comparable, as were the profiles and swing ratios. Shown in Figure 1 are typical 0.8 pm resist lines obtained on Silicon wafers. It was noted that resist C had a pronounced standing wave effect that could not be reduced. Significant differences in photospeed between the resists were apparent. The dose required to clear and the dose for zero bias both varied by approximately a factor of two or greater. In addition, the develop process times were significantly different. The only resist from this group to fail the oxide etch test was resist G (reticulation). This resist was not included in any further testing. When tested on substrates other than silicon, or on wafers with topography, profound differences in resist performance appeared. Wafers with topography provided a test of each resist's ability to minimize reflective notching and necking. Shown in Figure 2 is a representative example of topography used for these tests. Resist A from the first group contained a dye and performed very well in the necking test. However, two other resists performed equivalently (D and E), and only one contained a dye (E). The least sensitive resist (C) did not contain a dye and did not do well on the necking test. All of the resists showed problems when coated on metal wafers. The photospeeds decreased and the minimum feature size increased due to the additional dye loading and thicker films used. Resist A' failed the Hot Plate Flow and Plasma Etch tests and was not evaluated further. The differences between the other resists also were magnified. Larger variations were seen in the exposure latitude, energy to hit CD and slope latitude. Three of the six resists tested on metal substrates failed the adhesion test by lifting during the develop process (B',D',E'). Lifting was observed for both large and small geometries. Three of the resists (B',E',G') failed the metal etch test (resist burning or reticulation). Two of the resists marginally passed the test (C',D'). Only one resist (F') had no trouble with resist reticulation or burning during the standard metal etch. CONCLUSIONS Significant performance differences between commercially available I-line resists were observed. All six resists tested on silicon wafers exhibited the capability to image 0.5 pm lines and spaces. However, a range of exposure energies from 240 mJ/cm2 (resist C) to 110 mJ/cm 2 (resist E) were required to resolve 0.80 pm 1/s. Develop times for the standard vendor processes varied from 30 seconds (resist E) to 81 seconds (resist A). Three resists (B',D',E') failed the metal substrate adhesion test, and three (B',E',G') also failed the metal plasma etch test. Many of these important differences between resists did not become apparent until the resists were evaluated on wafers other than flat silicon. Therefore, a resist evaluation should include substrates other than silicon and nonplanar topography, insuring that the resists are compared under conditions closer to a true production environment.
203
IX25,008
lym W012
Figure 1. 0.8pm resist lines and spaces. The left photo is resist C and the right is resist B.
Figure 2.
Typical topography used to test resist necking and notching.
204
ACKNOWLEDGMENTS The authors would like to thank D. Wolf for her effort on this project. Thanks also to the SEM laboratory, the Etch group, and all of the individual process engineers from the various resist companies for their support.
*Present address is: Sematech, Inc., Austin, TX tPresent address is: LSI Logic, Inc., Santa Clara, CA REFERENCES [1]
B. Katz and J. Greeneich, Proc. KTI MicroelectronicsSeminar, Interface '88, 1 (1988).
[2]
M. Cagan, D. Kyser, C. Lyons, G. Hefferon and S. Miura, Proc. KTI MicroelectronicsSeminar, Interface '90, 177 (1990).
[3]
J. Love, S. Sethi, C. Takemoto and P. Ackmann, ibid., 53 (1990).
205
TIME MODULATED PLASMA ETCHING S.C. McNevin AT&T Bell Laboratories Murray Hill, N.J. 07974 This paper will review the new approach of time modulated plasma etching/deposition. By the technically straightforward modulation of the electrical power, gas flows; and magnetic fields, the processing can be varied on a scale of every few atomic layers. Several examples will be described which demonstrate that periodically varying the plasma processing leads to large improvements in the etch rates, anisotropy, and film quality while eliminating unwanted deposition. In these examples, the modulated processing achieves results which are superior to the standard approach of constant processing conditions. INTRODUCTION This review will describe one of the recent approachs in achieving novel processing results by periodically modulating the plasma conditions. The standard technique is to maintain fairly constant control parameters (e.g. gas flow, power) during a process, perhaps having at most one or two step changes during the entire process. The new time modulated approach, in contrast, uses the rapid periodic modulation of these parameters to achieve novel, and in many cases much improved, results. One reason for the increasing interest in this technique is that time modulation is relatively simple technically. This review will be divided into two parts. In the first part, the practical time scale of process modulation is compared with typical etch/deposition rates to demonstrate that variation on the scale of several atomic levels is possible. In the second part, four examples of time modulated processing which have appeared in the literature are briefly described in order to illustrate the improvements which can result from such time modulation. PRACTICAL TIME SCALE OF PROCESS MODULATION The plasma processing results are determined by the electrical power, gas flows, and magnetic fields (if any). The x-axis in Figure 1 illustrates the time scale on which these three types of processing parameters can be practically varied. As shown in the figure, the modulation of the RF and/or microwave power is the fastest, followed by the gas modulation and then the magnetic field modulation. The electrical power input can be modulated on a fairly rapid time scale (<100 msec), limited only by the electrical response time of the circuit. The gas
206
modulation is limited either by the response time of the gas controller or the residence time of gases in the vacuum system, depending on which is slower. (This follows directly from the time dependent differential equation for conservation of mass in a flowing system.) Figure 2 illustrates the modulated pressure achieved by the author with a typical gas flow controller in a system with a vacuum residence time equal to 25 msec. As seen in the figure, this typical commercial controller has roughly a 200 msec response time. Thus gas modulation in a system with a fast residence time can be achieved on a -200 msec time scale. In systems with slower residence times, the gas modulation would be limited by the longer times required for pump out and would be correspondingly slower (-I sec). The magnetic field can be modulated either by mechanically rotating permanent magnets or using controllable electromagnets on a time scale of between 1-10 sec. Figure 1 compares these modulation times with the resulting periodicity of the process. For example, as shown by the dashed line in the figure, a processing rate of 1 um/min would require a 1 §pc modulation capability in order to change the processing conditions every 100 A of etching or deposition. As shown in Figure 1, slower etch/deposition rates require slower modulation to achieve the same periodic processing. Thus using technically straightforward processing modulation combined with realistic etch/deposition rates, it is possible to change processing every few atomic layers. SEVERAL EXAMPLES OF TIME MODULATED PLASMA PROCESSING This section briefly describes four examples of time modulated plasma processing which have appeared in the literature (1-4). The goal of this review is not to provide a complete survey of this rapidly increasing literature, but to use these examples to illustrate the potential of time modulated plasma processing. The first example, illustrated in Figure 3, is from the work of K. Suzuki et al. on the etching of Si in a microwave plasma (1). By rapidly alternating between an SF 6 isotropic etch (a), NHl surface nitride formation (b), and sputtering of the nitride from the ion bombarded surfaces (c), the resulting profile shown in (d) was obtained. Typical time scales for the (a)/(b)/(c) sequence were 10/2/3 seconds. This modulated approach permitted the fast etch rate obtainable with SF 6 without the unwanted isotropic attack on the sidewalls. In addition, the nitride sidewall protection grown in pure NH 3 was firmer than the sidewall obtained when NH 3 and SF 6 were both present, which was attributed to degradation due to F incorporation into the nitride sidewall in the unmodulated processing. This work included two interesting technical innovations which were the lock-in detection of end point to eliminate interference from the modulated processing, and a modulated gas by-pass to stabilize the gas flow. The second example is from the work of J.T. Verdeyen et al. on the modulation of rf power diging SiHl4 deposition (2). This rf power modulation has been varied from 10-10 Hz. The results were that the bandgap of the deposited 207
amorphous silicon and the amount of dust, measured by Mie scattering, were both lower for modulated discharges. This improvement in the bandgap is in the opposite direction from what would be expected based on thermal effects, since the cw operation would result in more sample heating and presumably better annealed samples. Figure 4 shows the observed inverse relationship between the peak negative ion flux (F-) measured in an analogous electronegative gas (F2 in He or pure CF 4 ) and the dust scattering during SiH deposition as a function of the rf modulation frequency. These results suggest that the formation of the dust is related to the formation of the negative ions, and that the extraction of these negative ions during the rf power off cycle leads to a reduction of the dust and a consequent improvement in the quality of the deposited films. It's not yet established if the negative ions cause the dust. In any event, the macrosized dust would be expected to charge negatively in the plasma and thus dust extraction during the rf cycle could be occurring no matter how the dust was formed. The third example is from the work of R.W. Boswell et al. on the modulation of the rf power during the etching of Si/SiO2 in an inductively coupled rf plasma reactor (3). Figure 5 shows the observed Si etch rate as a function of the power pulse duration with a constant 20% duty cycle. Several possible explanations were considered, but the model which appears to fit the data best postulates that the Si etching is dominated by atomic fluorine which persists for a period of time after the discharge has been turned off. The curve in Figure 5 is the theoretical curve for a 50 msec lifetime for atomic fluorine, which is consistent with the observed recombination time of F into F 2 on Pyrex. This model is also consistent with the observation that the anisotropic etching obtained with continuous operation changes into isotropic etching with high repetition rate pulsed operation. The dependence of the SiO etch rate on power modulation differs from that of Si, and consequently the selectvity can be improved from 6 with continuous operation to greater than 100 with high repetition rates. The fourth example is from the work of the author on the effects of gas modulation on the etching of Si/SiO in a parallel plate reactor (4). As illustrated in Figure 6, The Si etch rate is highly affected by the 02 gas flow timing while the SiO etching is unaffected. Consequently, the useof a modulated 0 process can nearly double the Si etch rate (from 600 to 1000 A/min) with more &hanan order of magnitude increase in the selectivity (from 3 to 50). The proposed model which appears to fit the observations involves the presence of hydrocarbon fragments from sputtered photoresist which reduce the SiO to Si and correspondingly decrease the selectivity. This carbonaceous material can be removed by oxygen before it causes this damage to the SiO Oxygen can unfortunately also react with the etching products (e.g. SiCI4 ) to Ftorm solid products which can deposit on the wafer. This unwanted deposition can be minimized while still preserving the beneficial oxidation of the unwanted hydrocarbon fragments by alternating the Cl 2 and 02 flows.
208
REFERENCES 1. K. Suzuki, K. Ninomiya, S. Nishimatsu, 0. Sadayuki, U.S. Patent #4,579,623 dated 4/1/86; K. Suzuki, K.Ninomiya, S. Nishimatsu, S Okuhiva, 0. Okada, Japanese Patent #60-126835 dated 1985. 2. J. Verdeyen, J. Beberman, L. Overzet, J. Vac. Sci. Technol. A8, 1851 (1990). 3. R.W. Boswell, D. Henry, Appl. Phys. Lett. 47, 1095 (1985). 4. S.C. McNevin, J. Vac. Sci. Technol. B8, 1185 (1990).
209
.4 W Z _-
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MODULATION TIME (sec)
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Figure 1: This illustrates the practical process modulation achievable for the electrical power, gas flows and magnetic fields (x-axis) with the corresponding scale of the process modulation (y-axis) for various etch/deposition rates. As illustrated by the dashed line in this figure, a processing rate of 1 ur/min would require a I sec modulation capability in order to change the processing conditions every 100 A of etching or deposition.
210
MKS GAS CONTROLLER
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Figure 2: This illustrates the pressure modulated by an MIKS gas controller as a function of time measured with a fast response baratron gauge and the vacuum residence time equal to 25 msec. This standard controller has roughly a 200 msec response time and operates reliably when time modulated over a long period of time.
211
Time Modulated Plasma Processing of Si (a) SF 6 Isotropic Etch
(b)
EELD
NH 3 Nitride Deposition
(c) Nitride Sputtering
(d) Predicted Geometry of Time Modulated Plasma Processing
Figure 3: This illustrates the time modulated etching of Si in a microwave plasma (1). Isotropic SF etching is combined with nitride deposition and sputtering to achieve a fast Si etch rate with acceptable anisotropy.
212
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Figure 4: This illustrates the inverse correlation between negative ion formation and dust scattering as a function of the modulation of the rf power during the plasma deposition of SiHl4 .(2) The reduction in the film quality associated with this dust can be eliminated by extracting either these negative ions and/or the negatively charged dust itself during the off cycle of the rf modulation.
213
3
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1000
PULSE DURATION (ms)
Figure 5: This illustrates the Si etch rate as a function of the ff power modulation in an inductively coupled rf reactor.(3) The theoretical curve is derived for a model where atomic fluorine persists for 50 msec after discharge termination. This power modulation leads to a greatly increased Si/SiO 2 selectivity.
214
z E
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AVERAGE Og PRESSURE (mtorr)
Figure 6: This illustrates the Si and SiO 2 etch rate as a function of the timing of 02 introduction in a CL2 rf plasma. (4) Modulating the 02 resulted in increased Si etch rates and much improved Si/SiO2 selectivity.
215
SUPER-ECR PLASMA ETCHING TECHNOLOGY FOR 64RBIT DRAM Seiji Samukawa VLSI Development Div., NEC Corporation 1120 Shimokuzawa Sagamihara, Kanagawa 229, Japan Extremely high selective, highly anisotropic, and high rate electron cyclotron resonance (ECR) plasma etching for n~poly-Si is achieved at the ECR position in a newly developed ECR plasma etching system. These characteristics are realized by the low ion energy, the high ion current density and the collimated ion flux at the ECR position. Moreover. an anisotropic Al-Si-Cu alloy film etching without the Cu residue problem is accomplished by using 400 kHz RF biased ECR position etching in C12 gas plasma. It is considered to be due to the combination of the dense ECR plasma generation and the efficient ion acceleration at the ECR position by using 400 kHz RF bias. INTRODUCTION Electron cyclotron resonance (ECR) plasma etching technology for submicron pattern fabrication has many advantages, such as low ion energy and high density plasma in low pressure [ 1. 2 ] . However, the FR plasma etching system has not been widely accepted in production lines because of poor uniformity, low etching 'rate and low anisotropy. The disadvantages of ECR plasma etching are caused by plasma transport from a discharge region and an etching region as a result of the divergent magnetic field gradient. The traveling plasma stream diameter is enlarged by the divergent magnetic field. The amount of ions and radicals decreases through the relaxation and recombination process that takes place during the plasma transport [3 ] . Therefore, ion current density becomes lower and nonuniform, and the ions take on various flight paths due to scattering. This paper reports on ECR position etching accomplished by a newly developed ECR plasma etching system [4, 5, 6] . It solves the above problems, and provides practical and accurate ECR plasma etching for n* poly-Si and Al-Si-Cu alloy film. These etching characteristics are obtained in large 6-in.-diam substrates. EXPERIMENTAL A schematic illustration of the ECR plasma etching system used in this study is shown in Fig. 1. Plasma chamber diameter is 260 mm. Silicon substrates of 6 or 8-inch diameters are automatically transported to substrate holder. Main magnetic and sub-magnetic coils are located around the periphery of the plasma chamber. In this experiment, a substrate is located at the ECR position (875 gauss position) in an ECR plasma. The etching characteristics at the KUR position are investigated using an n* poly-Si film and an Al-Si-Cu alloy film as etching materials. N÷ poly-Si gate electrode and stacked capacitor electrode etching are carried out without RF bias. Al-Si-Cu alloy film patterning are fabricated by supplying RF bias power. Optimum RF bias frequency to accelerate the ions efficiently at the ECR position is also examined . An n* poly-Si 216
(4000 A thick) film for the gate electrode and the stacked capacitor electrode are deposited on the thermal oxide. An Al-Si(1Z)-Cu(0.5Z) alloy film is sputtered on the thermal oxide. The etching gas used for the n* poly-Si and Al-Si-Cu is Cl2 only. RESULTS AND DISCUSSION A. Plasma characteristics at the ECR position Dependence of ion current density on magnetic field intensity is shown in Fig.2. Ion current density is measured with a Faraday cup using N2 and Cl2 gas plasma. Pressure is 5 X10-4 Torr. Microwave power is fixed at 1 kW. Results show that the ECR position has2 the maximum ion current density [4] . Ion current density is 15 mA/cm in the N2 plasma. On the other hand, the Cl 2 gas plasma obtains a much higher ion current density of more than 20 mA/cm'. In conventional ECR plasma etching system, as substrate is separated from the ECR position, plasma is transported from the KCR position to the substrate by the divergent magnetic field. The amount of ions decrease by relaxation and the recombination process during the plasma transport. Figure on etching rapidly at degree of Therefore,
3 shows dependence of the ion current density at the ECH position pressure. Microwave power is 1 kW. Ion current density increases pressure of less than 1 X10- Torr. This indicates that the ionization increases extremely at a 10-" Torr pressure level. the ion etching becomes dominant at this level.
Figure 4 shows the dependence of ion energy distribution on magnetic field intensity. An energy analyzer with four grids is used to measure ion energy distribution in the ECR plasma. The mean ion energy and the width of ion energy distribution decrease as they near the ECR position. The ECR position has the lowest ion energy and excellent uniform ion energy distribution [ 7] This result is considered to be due to the collimated ion flux. At the ECR position, the mean ion energy near the ECR position is about 16 eV and the half value width of ion energy distribution is about 3 eV. In conventional ECR plasma etching, the mean ion energy is more than 20 eV and the half value width of ion energy distribution is extended to more than 5 eV. Ions are accelerated by the negative potential between the plasma and the substrate. Negative potential is generated by the accelerated electrons by the magnetic field gradient. Therefore, the ion energy distribution at the ECR position is reduced compared with that in conventional ECR plasma etching because of the small magnetic field divergence. Ion energy distribution in the Cl2 gas plasma is investigated at the ECR position, as shown in Figure 5. The mean ion energy at the ECH position in the Cl2 gas plasma is about 14 eV. Figure 6 shows the dependence of ion energy distribution at the ECR position on the etching pressure. The mean ion energy decreases as the discharge pressure increases. When discharge pressure is 3 X10-1 Torr, the mean ion energy is about 12 eV. This seems to be due to the negative potential reduction caused by the decrease in the electron mean free path and the electron energy as the etching pressure increases. The ECR position in the ECR plasma has a high ion current density, a low ion energy and a collimated ion flight direction at the same time.
217
Figure 7 shows the ion current density distributions using the new = plasma etching system and with conventional EO plasma etching system at the KCR position. The ion current denseness uniformity in the new system is ±5% in a 200 mm diameter area. The uniform ion current density is due to a large quartz window for microwave introduction and a flat 875 equi-magnetic field plane caused by the sub-magnetic field to the substrate holder [4 ] Figure 8 shows the ion current density at the ECR position as a function of microwave power. The ion current density at the ECR position increases linearly with microwave power. Usually, it is impossible to achieve linear increasing of ion current density. The results indicate that the 875 gauss equi-magnetic field plane causes uniform and efficient microwave absorption at the ECR position [8] . B. N' poly-Si etching characteristics N* poly-Si etching characteristics at the ECH position are investigated using4 pure Cl 2 gas. The C12 flow rate is 20 sccL Rtching pressure is 5 X10- Torr. At the ECM position, the n÷ poly-Si etching rate is 3000 A/min and the etching selectivity ratio to SiO2 is about 100. The etching selectivity ratio to the photoresist is more than 20. Etching rate uniformity is +5 Z across a 6-inch-diameter substrate. Figure 9 shows the gate electrode poly-Si (a) and the stacked capacitored poly-Si (b) etching profiles. A highly anisotropic etching profile is realized after 100 % over-etching. EM position etching can satisfy a high etching selectivity ratio to SiO2 , a high etching rate, and excellent etching uniformity corresponding to the ion current density and ion energy at the ECR position [4, 5, 6] . In addition, as ICR position etching leads to higher selectivity ratios to photoresist, extremely precise control of pattern transfer is possible. Figure 10 shows the n* poly-Si etching rate and SiO2 etching rate as a function of etching pressure at the KCR position. Substrate temperature is VC. When etching pressure is 3 X10-' Torr, the etching fixed at 70 selectivity ratio to SiO2 is increased to 260. This is considered to he due to ion energy reduction, as shown in Fig.6. poly-Si as a function of Figure 11 shows the side etching widths of n* X1O-4 Torr, 5 XI- 4 Torr, and 3 X10-' substrate temperature at 1 'C, Torr. No side etching is observed below 90 'C, 70 'C, and 30 respectively. These results clearly show that sidewall reaction due to radicals is suppressed by lowering the substrate temperature. Moreover, the radical density on the substrate surface increases as the etching pressure increases. Therefore, the substrate temperature must he lower to reduce the side etching at higher pressure. poly-Si etching with The data indicate that highly selective n÷ extremely small side etching and high etching rate are achieved by keeping the substrate temperature of 30 'C. C.Effects
of applied RF bias at the ECR position
Applied RF bias frequency to accelerate ions at the ICR position efficiently and uniformly is investigated. To optimize the frequency of the RF
218
bias for ion acceleration, the etching rate and its uniformity across 6-inch diameter substrate are examined, as shown in Fig. 12. In this experiment, 3i0 2 film is used as etching material to observe the uniformity of only ion bombardment. Cl. flow rate is 20 sccu. Etching pressure is fixed at 5 X10-' Torr. It is seen that 400 kllz is the optimum frequency which satisfies both high etching rate and excellent uniformity. At frequency of 700 kldz or higher, the uniformity becomes poor due to local discharge between the grounded chamber-wall and the substrate holder. On the other hand, at frequency of less than 600 kllz. etching uniformity is excellent, and 400 kHz frequency has the highest etching rate. Below the 600 kHz, RF bias power is supplied to the KCR position without local discharge. Moreover, at frequency of 400 kHz, the ions cross the sheath quickly with respect to the oscillations and have maximum energy equal to the instantaneous applied field. From these results, the most suitable RF bias frequency for the ion acceleration at the ICR position is 400 kIz [ 91] . In addition, the supplied 400 kllz RF bias is effective in preventing the charge build-up damage to the gate oxide. Figure 13 shows SiOz (10 nm thick) breakdown frequency in the KOS capacitor with aluminum wirings after the RF biased KCR plasma irradiation. The 02 plasma is radiated to the NOS capacitor for 5 minutes. The RF bias frequency of 13.56 M and 400 kllz are applied to the (CR position. In case of using 400 klz RF bias, the gate oxide breakdown is eliminated perfectly because of keeping uniform 9C plasma. However, the applied 13.56 Mxlz RF bias causes the gate oxide breakdown due to the uneven KCR plasma irradiation generated by the local discharge [ 1 01 D.AI-Si-Cu alloy film etching characteristics By using the 400 kfz RF bias, and using simply Cl2 gas for the reactive etchant, an Al-Si-Cu alloy film etching is investigated, Cl 2 flow rate is 50 sccmL Etching pressure is 3 X10 3 Torr. Substrate temperature is kept at 100 "C. Microwave power is fixed at 200 W. Figure 14 shows the Al-Si-Cu etching rate uniformity for various 400 kHz RF bias powers. Excellent Al-Si-Cu etching rate is kept, even if the RF power increased, Etching rate is 5100 A/min with the 400 kHz RF bias power of 50 W. The etching divergency is ±5 Z across the 6 inch diameter substrate. A SEX photograph of the etched profile is shown in Fig.15. It should be noted that a highly anisotropic profile has been obtained, and no Cu residue etching is found despite Cl2 used for etchant gas. The simultaneous satisfaction of the various advantages described above are attributable to the physico-chemical etching mechanism that is specific to this RF biased ICR position etching, where effective extraction and acceleration of ions are taking place at the ECR position [91] CONCLUSION The mean ion energy and the half value width of ion energy distribution in an KCR plasma decrease as they near the ICR position. The ICR position has the lowest ion energy and the highest ion current density in an ICR plans. Extremely high selective etching for n'poly-Si is achieved at the FCR position in a newly developed KCR plasma etching system.
219
Moreover, a new position etching is only, without Cu accomplished by the at the ECR position
anisotropic etching technology using 400 kHz RF biased NCR presented. It can etch Al-Si-Cu film by using Cl2 gas residue problem. These etching characteristics are combination of the dense and uniform EC plasma generation by using a 400 kllz RF bias. ACKNOWLEDGMENTS
The author would like to thank Dr.H.Tsuya, Dr.O.Kudoh, Dr.K.Hamano, and Dr.A.Ishitani for their useful advice. REFEECES [1] K.Suzuki, S.Okudaira, N.Sakudo and I.Kanomata, Jpn. J. Appl. Phys., 16. 1979 (1977). [2) S. Eatsuo and N.Kiuchi, Jpn. J. Apple. Phys., 22. L210 (1983). [3] S. Samukawa, S.Mori and N.Sasaki, Jpn. J. Apple. Phys.. 29, 792 (1990). [4] S.Samukawa, Y.Suzuki and M.Sasaki, Appl. Phys. Lett., 57(4). 403 (1990). [ 5 S.Samukawa, . N.Sasaki and Y.Suzuki, J. Vac. Sci. Technol., B8(5), 1062 (1990). [6] S.Sauukawa, M.Sasaki and Y.Suzuki, J.Vac.Sci.Technol.,B8(6), 1192 (1990). S7] S. Samukawa, Y.Nakagawa and L Ikeda, Jpn. J. Apple. Phys., 30, 423 (1991). [ 8] S. Samukawa, S.Mori and MLSasaki, J. Vac. Sci. Technol., A9(1), 85 (1991). [9] S.Samukawa, T.Toyosato and K.Wani, Appl. Phys. Lett., 58(9), 896 (1991). [10] S.Samukawa, Jpn. J. Apple. Phys., 29, 980 (1990).
220
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Figure 8 Ion current density at the ECR position as a function of microwave power.
222
Figure 9 Gate electrode and stacked capacitored poly-Si etching profile. (a) Gate electrode (b) Stacked capacitor
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Figure 10 N* poly-Si etching rate and Si02 etching rate at the ECR position as a function of etching pressure.
223
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224
Figure 15 Anisotropically etched Al-Si-Cu pattern profile by using 400 kHz RF biased ECR position etching.
225
HIGHLY CONTROLLABLE SiO2 ETCHING TECHNOLOGY BY VAPOR HF/H20 SYSTEM Shigeo Onishi, Kenzo Matsuda and Keizo Sakiyama Sharp Corp., IC-Group, VLSI Development Laboratory 2613-1, Ichinomoto-cho, Tenri-city, Nara 632, Japan
Highly controllable Sit2 etching technology has been The etching developed by using vapor HF/H20 system. uniformity was better than the ordinal liquid HF system and indicated a value of 0.5% by using the azeotropic HF/H20 vapor from HF aqueous solution. The particles due to the reaction products (Sit2, H2SiF6 ) were decreased by changing HF/H20 mole ratio and raising miscibility, and can be completely suppressed by using the azeotropic HF/H20 vapor. INTRODUCTION In the fabrication process of ULSI devices, the contaminations around the silicon surface induce the degradation of the junction and the oxide properties 1), so the surface cleaning technology must be developed. Especially in the fine trench and contact holes with high aspect ratio, it is difficult to clean the surface regions, using the ordinal liquid-phase cleaning system has been developed, using HF/H20 2) 3) vapor, Cl radical 4) and so on. In the vapor HF systems, many researchers indicated that it was effective to suppress the native oxide growth 2), and recently Ohmi reported that it was possible to etch off the native oxide selectively 3). By the way, the etching process of the Sit2 film are considered as an useful application in the vapor HF system. There are three key issues on the etching applications. First is the etching uniformity, second is the etching repeatability, and third is the particles due to the reaction products. In our development, the excellent uniformity or repeatability were obtained in comparison with the usual liquid HF system. However, in order to employ the vapor HF system, the particle generation due to the reaction must be solved.
226
In this work, from the chemical viewpoint, a mechanism of the particle generation and a method to suppress the particles has been suggested in the vapor HFIH20 systems. EXPERIMENTAL Fig. I shows the schematic drawing of the three kinds of the etching chamber used in this experiment. In Fig.l(a), the HF/N2 and the H20/N2 vapor were separately introduced into the etching chamber at the room temperature in the atmospheric pressure. In Figl(b), the mixing box was fabricated in the chamber in order to mix HF and H20 vapor sufficiently. In Fig.l(c), the azeotropic HF/H20 vapor evaporated from the HF solution(HF content : 39 wt%) was introduced into the chamber with a mixing box. The sample was heated from the backside by irradiating the IR light from the tungsten halogen lamp. In this case, the light is transmitted through the quartz window coated with the the thin silicon film(O.1gm). The temperature was measured by the thermocouple attached to the sample. The etching rate of the thermal SiO2 film was evaluated by changing the HF concentration, the HF/H20 mole ratio and the sample temperature. Next, the thermal SiO2 film of 0.2gtm thickness was etched off with an over etch of about 50%. The number of the particles above 0.161gm in size was counted. The surface impurities were analyzed by SIMS and the bonding states were evaluated by XPS. H•r/Nz
H20/Nz
4.
__________
F/N2
costed
El/H20
HF/H20
I
Window
-_. .,____,-_
1120/112
with Si
Tungsten Halogen Lamp
(b)
(a) Fig.1 Schematic experiment.
drawing
of the
227
etching
(c) chamber used
in
this
RESULTS AND DISCUSSION 1) Mole ratio dependence of HF/H20 Fig.2 shows the etching rate at the various HF concentration as a function of the HF/H20 mole ratio, using the etching chamber in Fig.l(a). Basically, the etching rate was determined by the HF concentrations, and it increased in proportion to the HF concentration. Also, the etching rate had .a certain relationship with the water content above the critical concentration. The etching rate was increased in proportion to the water content at the HF/H20 mole ratio below 1. This behavior was obtained with the various HF concentrations. Fig.3 shows the particle distribution in a wafer after vapor HF/H20 treatment. The HF concentration is 10% and The HF/H20 mole ratio is 20. It was observed that the particles were mainly distributed around the introduction tube of the vapors. The particles didn't generate at the sample without the SiO2 film, so it is believed that the particles generated during the etching reaction of the Si02 films. HFIN2 1.5
HF concentration 01% 0 5% A 10% A 15%
S1.0
u-
0.5
H2O/N2 HF/H20 mole ratio = 50 at 25°C .1
1
10
100
HFIH20 Mole Ratio
1000
Etchina Uniformity-= + 2 %
Particle counts = 1,320 / wafer Fig.2 Etch rate at the various HF concentration as a function of Fig.3 Particle distribution in a wafer the HF/H20 mole ratio. by using the system in Fig.l(a)
228
Fig4 shows the particle counts as a function of the HF/H20 mole ratio. It also includes the HF concentration dependence of the particle counts. The particle counts weren't dependent on the HF concentration, but strongly depended on the HF/H20 mole ratio. A large amount of particles of above 10,000 counts/wafer were generated at the HF/H20 ratio below 1. When the water content was decreased and the HF/H20 mole ratio extended between 10 and 100, the particle counts abruptly decreased and the minimum value of about 80counts/wafer was obtained. However, when the water content decreased furthermore and approached around the critical concentration, the particle counts suddenly increased. In the case of the HF/H20 liquid-phase system, the particle counts were about 30 counts/wafer. Fig.5 shows the relative intensity of 1 H, 19 F, 160 atoms against 3 0Si on the vapor-etched sample. for vapor HF/H20 system, the intensity of 0, F atoms indicated a large value in comparison with the sample etched in HF/H20 solution. And the sample with a higher HF/H20 mole ratio indicated less 0 and F intensity. This tendency had a good correlation with the particle counts. On the other hand, H intensity indicated a reverse tendency,that is, the sample with the higher HF/H20 mole ratio had larger H intensity.when the water content approached the critical concentration, F intensity increased. Also, it was confirmed by XPS that F and 0 atoms were chemically bonded to Si atoms.
Se)OHF0
1000 A
A
atom
1.
F atom
1.0 ' 0.8
AAA
S1000
A H atom
S1.20
05% A 10% A 15%
00oA -10000
¶ A
concentration 1%
2 0.6 0.4
100
A
0.2 0IL
n _,_-_. . . .....
1
fJ.W
.1
1
10 100 1000 10000 HF/H20 Mole Ratio
S•
.1
• •
...... . ... • •A
d AA•
.... d AAA•
10 1u uuu 10uuu 0uu HF/H20 Mole Ratio
9 16 Fig.5 Relative intensity of 1H,1 F, 0 atoms against 30Si as a function of the HF/H-20 mole ratio.
Fig.4 Particle counts as a function of the HF/I-20 mole ratio,
229
2) A mechanism of particle generation Fig.6 shows the reaction mechanism between the SiO2 films and the HF/IH20 gas. SiH4 and H20 are produced by the reaction between HF and SiO2, and subsequently H2SiF6 are produced by the reaction between HF and SiF4. These reactions are principally reversible. Actually, the reaction seems to proceed.by the hydration mechanism as shown in Fig.6 (2),(3) 5). So, the etching process of S iO2 film suddenly proceeded at the water content above the critical concentration and the etching rate increased in proportion to the water content. However, with the existence of excess 1H20, the etching rate did not appreciably increase because of the reverse reaction in equation(l). H20
Si02÷Fr
SiF4 - 2H2O
(1)
H36 + EFi
(2)
2HY H20 Z± Sio2 • 2H30" ÷ 2HFz-
si+4r.
Z
H20
•
HzSiF6 H
Sir4 - 4Hz0 (3)
(4)
Fig.6 Reaction mechanism between the Si02 film and the HF/IH20 gas. The generation mechanism of the particles is considered as follows(Fig.7). On the Si02 film,SiF4 and 1120 are mainly produced by the reaction between HF and SiO2(equation(5)). In the vapor phase, SiF4 vapor react with H20 or HF to produce Si02 or H2SiF6(equation(6),(7)). These product (Si02,H2SiF6) are essentially non-volatile material and become particles or residues by depositing on the sample. Table.1 shows the summary of the particle count , the chemical equilibrium constant in the vapor phase reaction and 0 or F contents, when the HF/H20 mole ratio is 1 and 100. The partial pressure of SiF4 gas in the equilibrium constants(Ka and Kb) was estimated from the etching rate of the Si02 film. When the HF content increased and the HF/H20 mole ratio was 100, the particle counts largely decreased. In this case,the 230
HF
Lhase
HO
Vapor
T
SiF4 + 2H20
=X=i.SQ.
SiF4 + 2HF
;
SiF4
SiO2
SiO2
+
HI-2SFi
4HF(S)
(6)
surface
SiOU + 4HF
1
SiF4
+ 2H20
(7)
SijO2, H2S6 : Particles
Fig.7 Generation mechanism of the particles.
SiF4 +2H20==SiO Ka=
(PHF)
+4HF
(PSiF4) (PH20)
Kb=
2
HF/H20 mole ratio
1
Particle generation
20,000 1 x 10
Ka
1 (PSiF4) (PHF)2
100 100 3
much SiO2 0 relative intensity
JH.Sjf.i.
SiF4 + 2HF
4
1.0
2 x 10 7 less SiO2 0.25
-4
.5
Kb
8 x 10 much H2SiF6
F relative intensity
0.55
2 x 10 less H2SiF6 0.30
Table.1 Table of the particle counts, the chemical equilibrium constant and the F, 0 atoms intensity at the HF/H20 mole ratio of I and 100
231
equilibrium constants(Ka and Kb) become larger, so the chemical equilibrium states are largely shifted to the left direction(Le Chaterier's Law). So, it is difficult to produce SiO2 and H2SiF6 as non-volatile material. This phenomena caused the decrease of 0 and F atom intensity on the silicon surface and consequently the particle generation was suppressed. Also, considering that H atoms are stably terminated to the silicon surface, it seems to be reasonable to contain much H atom on the clean silicon surface. When the HF/H20 mole ratio approaches infinity, H20 concentration is determined by the reaction products, so the etching rate was not appreciably changed in this regions In this case, the amount of ionized HF2- species are less than that of HF amounts. So, the chemical equilibrium state was shifted to the right direction in equation (4)(Fig.6) and H2SiF6 were largely produced in the vapor phase So, the intensity of F atoms on Si surface increased and consequently the particles were generated. 3) Particle suppression by the enhancement of the miscibility As shown in Fig.4, the particle counts had a minimum value at the HF/H20 mole ratio of around 50, The improved chamber with a mixing box (Fig.l(b)) was used, then the etching uniformity and the particle counts were evaluated. Fig8 shows the particle distribution in a wafer by using two kinds of the equipments(Fig.l(a),(b)). When HF vapor and H20 vapor were separately introduced into the chamber, it was observed that the particle counts exceeded 1,000 counts/wafer and were concentrated around the introduction tube of the vapors. On the other hand,when these vapors were sufficiently mixed in the mixing box, the etching uniformity was improved to the value of 1% and the particles were largely decreased. Next, the azeotropic HF/H20 vapor evaporated from HF solution was introduced into the chamber, then the etching uniformity and the particle counts were evaluated The etching uniformity was improved and the value of 0.5% was obtained .Also, the particle counts were decreased by one order of magnitude and only the seven particles were observed. That is, it is believed that the sufficient mixture and the uniform dispersal are effective for suppressing the particle generation.
232
HF and H20 vacor
HF/N
mxe
y=o
HF/N2
H20/N2 HF/H20 mole ratio = 50 at 251C
HF/H20 mole ratio = 50 at 25°C
Etchina Uniformity = ± 2 %
Etchina Uniformity = + 1 %
Particle counts = 1.320 / wafer
Particle counts = 74 1 wafer
Fig.8 Particle distribution systems(Fig. 1(a),(b))
4)
Temperature
in
a
wafer
by
using
two
dependence
Fig.9 shows the wafer temperature dependence of the particle counts at the HF/H20 mole ratio of 0.5. The etching chamber shown in Fig.l(a) was used and the HF and H20 vapor were separately introduced into the chamber. It was observed that the particle counts largely decreased by raising the temperature from 25 0 C to 40 0 C.In this case, the etching rate decreased at the higher temperature, and the etching reaction didn't proceed at the temperature above 45 0 C. From the SIMS analysis(Fig.10), it was observed that the relative intensity of F and 0 atoms decreased by raising the sample temperature this tendency had a good correlation with the particle counts. The suppression effect of the particles at the higher temperature is considered as follows. In this case, it is considered that the sample was selectively heated by the lamp-heating method, so the temperature of the surrounding ambient wasn't raised so much. The reaction between SiO2 and HF is exothermic and the etching rate was decreased at the higher temperature because the chemical equilibrium in this reaction 233
shifted to the left direction on the sample(equation(5) in Fig.7) In the vapor phase, the temperature wasn't raised so much and the chemical equilibrium shifted to the left direction(equation(6),(7) in Fig.7) because of the less production of SiF4 from the sample. As a results,the generation of SiO2 and H2SiF6 could be suppressed in the vapor phase, and the particles largely decreased at the higher temperature. .Iz S
A H atom
0.4
o
a
0 atom atom
*F
0.3
a
*,0.8
0.6 •
0.2
S
.S 0.1
0.
0.4 =0.2 HF/H20
0.0 Tmetue )U Temperature( C)
00 VWV
i
Fig.9 Particle counts as a function of the wafer temperature.
U
mole ratia=0.5 •
Eli IU V
LU
.)U V U
A[ V Temperature
*U
( C)
U
OU
a V
Fig.10 Relative intensity of H, F, 0 atoms as a function of the wafer temperature.
CONCLUSIONS The following conclusions are summarized in this experiment. In the etching process of SiO2 film by HFJH20 vapor system, the reaction products such as H2SiF6 and Si02 were formed and consequently the particles were generated The particles decreased by changing HF/H20 mole ratio and wafer temperature for the purpose of shifting the chemical equilibrium state Especially, particle generation was largely affected by the HF/H20 mole ratio
and the adequate mole ratio regions existed for suppressing the particles. So, it becomes important to mix the HF and H20 gas fully and to keep good uniformity. Actually, the particle generation could
be perfectly suppressed by raising miscibility and controlling the temperature. 234
ACKNOWLEDGEMENT The authors would like to thank Mr. Ryuichirou Miyake for his support and helpful discussions. REFERENCES 1) J.P. Gambino, M.P. Monkowski, J.F. Shepard, and C.C. Parks, J. Electrochem. Soc., vol 137, No.3, pp 9 7 6 - 9 7 9 (1990) 2) T. Hara, S. Kamiyama, D. Burkman, J. Mehta, C.A. Peterson, D. Syverson, Extended abstract of ECS Fall Meeting (1987) 3) N. Miki, H. Kikuyama, M. Maeno, J. Morita and T. Ohmi, Tech. Dig. of IEDM 88, pp730-733 (1988) 4) T. Ito, R. Sugino, S. Watanabe, Y. Hara, and Y. Sato, Extended Abstract of ECS Fall Meeting. (1989) 5) N. Miki, M. Maeno, T. Ohmi, J. Electrochem. Soc., Vol.137, No.3, pp790-794(1990) 6) F.A. Lenfesty, T.D. Farr, J.C. Brosheer, Ind. Eng. Chem., vol.44, No.6, pp 1 4 4 8 - 1 4 5 0 (1952)
235
ANISOTROPIC ETCHING PROCESS OF n'-POLYSILICON WITH CHLORINE AND NITROGEN MIXED ECR PLASMA Takashi Matsuura, Hiroaki Uetake,* and Tadahiro Ohmi Department of Electronics, Faculty of Engineering, Tohoku University, Sendai 980, Japan. Junichi Murota and Shoichi Ono Research Institute of Electrical Communication, Tohoku University, Sendai 980, Japan. An anisotropic etching process of n+-polysilicon for ULSI fabrication has been Investigated by irradiating the chlorine and nitrogen mixed plasma using an ultraclean ECR etcher. With increasing nitrogen partial pressure, anisotropy increases drastically. From XPS analysis, it is considered that the SI-N bonds are formed on the side wall surface by N radicals competitively with Cl etching. The measurements of the light emission from the plasma show that the horizontal etch rate can be described as a radical reaction by an equation similar to Langmuir's adsorption Isotherm, whereas the vertical etching is affected by Ion incidence. INTRODUCTION Anisotropic etching of n+-polysilicon with high selectivity is increasingly important for ULSI fabrication. In our previous work [1, 21, an Induction period for S1O 2 etching has been found and perfectselective etching of undoped polysilicon with respect to S10 2 with high anisotropy has been achieved using an ultraclean C12 ECR plasma under a damage-suppressing condition. It has been also found that the anisotropy in pure Cl2 plasma etching for n+-polyslllcon is very low compared with that for undoped polysilicon, because of high reactivity of n÷-polysIlicon with radicals, and furthermore the anisotropy Is increased with the N2 addition under a highly selective condition [3, 4]. In the present work, an etching process of n+-polysilicon has been investigated, focusing on the effects of the N2 addition in a C1 plasma generated In an ultraclean ECR etcher. Based on the results of XPS analysis, it is suggested that the side wall of n+-polysilicon is protected against C1 radical attack by chemisorption of N. Estimating the radical concentration from the plasma light emission measurements, the etch rate In the C12 plasma with addition of N2 is expressed by an equation similar to Langmuir's adsorption isotherm. EXPERIMENTAL
An ultraclean ECR plasma apparatus shown In Fig. 1 [1,21 was used to obtain high selectivity In etching. High purity C12 and N2 gases *On leave from Seiko Instruments Inc., 236
Matsudo, Chiba 271,
Japan
IuLtra cLean gas supply system microwave supply C12 .N2
Fig. 1. Schematic diagram of the ultraclean plasma apparatus.
ECR
were premixed before introducing them into the plasma chamber. In the present work, the reactor pressure, measured with an MKS Baratron gauge, was fixed to 4 mTorr, and the wafer was electrically in floating condition. It should be noted that the typical energy of ions is known to be a few eV in this pressure region[5], and comparable to the energy of bonds concerned in etching. The samples etched usually were 450 nm thick phosphorus-doped n*polysilicon formed on thermally oxidized SI wafers. For XPS measurements, about 4 jim thick n÷-polysilicon was also used. Thermally grown and CVD SiO was used as a mask. The vertical etch rate of polysillcon was determined from the etching end point time by wafer voltage measurements[l], and the horizontal one from cross sectional SEM measurements. Plasma light emission near the wafer was measured with a Photal IMUC-7000 multichannel spectrometer. RESULTS AND DISCUSSION Figure 2 shows typical etch profiles for n*-polysilicon etched by a pure C12 plasma and a C12 plasma with addition of N where selectivity to S10 2 was higher than 160. It is found thai the N2 addition to C1 drastically improves etching anisotropy of n polysilicon, an4 anisotropic etching of 0.3 jim n -polysilicon patterns can be achieved by this method. In order to clarify the side wall protection chemistries with N2 addition, XPS analysis on the side wall surface after etching was performed using the area patterned with lines(-4jim) and spaces(-2jim). Two types of photoelectron collection as shown in Fig. 3, both before
237
(a)
(b)
0.3m Fig. 2. Etch profiles of n+-polysilicon on SIO etched with (a) the pure Cl 2 plasma (C12 =50 sccm) ani (b) the N2 added Cl2 plasma (C12 /N 2 =47 sccm/5 sccm). The total pressure-is 4 mTorr, the microwave power 700W. As mask material SiO2 has been used.
Parallel
20°<0<500
collection
perpendicular -41jm-l2Jm V H collection
$1
sking S102 Poly Si SnyiIA
Si substrate Fig. 3. Perpendicular and parallel collection of the photoelectrons in the XPS measurements on the area patterned by lines and spaces.
238
and after exposure of the sample to air after the N added C12 etching, are compared in Fig. 4. For the parallel collection, only the masking SIO surface at the top of the pattern and the gate oxide surface at ihe bottom of the pattern can be analyzed. On the other hand, for the perpendicular collection, the contribution from the side wall surface of n+-polysilicon can be obtained Instead of that from the bottom surface. By comparison of the measured spectra, the following results are obtained, although the absolute binding energy is shifted by the electrostatic charging effect during the XPS measurements: 1.
Adsorption of N atoms as well as Cl atoms is observed (see spectra a and8 in Fig. 4(c) and (b)).
2.
In Fig. 4(b), spectrum 6 shows Cl atoms adsorbed only on SIO because of the parallel collection. Spectrum a, in spite of the perpendicular collection, is very similar to 8 . Therefore, it is considered that the Cl adsorption on the side wall is little.
3.
The additional peaks (marked by arrows) are observed for the perpendicularly collected spectra(a) of Si (Fig. 4(a)) and N (Fig. 4(c)) before the exposure to air. These peaks are considered to originate from the N adsorption on the side wall of n+-polysilicon, because such peaks can not be seen for the parallel collection (R). This N adsorption Is believed to be the reason for suppression of Cl radical etching at the side wall.
4. The exposure of the sample to air causes desorption of the N atoms on n+-polysilicon (see disappearance of the marked peaks in Fig. 4 (a) and (c)) as well as the Cl atoms on SiO2 (Fig. 4(b)). In order to clarify the chemical nature of the adsorbed atoms, the plasma-irradiated n -polysilicon surface of the not-patterned area was also analyzed by XPS, since the peak was shallower and the binding energy of peak can be determined more clearly than that in the case for the patterned area. The following results were obtained: 5. The Si 4 + peak on the n -polysilicon surface exposed to the (C12 + N?) plasma appeared at an equivalent binding energy to the peak of Si In an SitN 4 film formed by LPCVD. It is considered that the Si-N bonds formed on the n+-polysllicon surface are similar to those in Si 3 N4 • 6.
The adsorbed N atoms on the n÷-polysilicon surface were removed by stopping the N addition In C12 plasma even when the shutter was closed which interrupted the direct incidence of ions. Also, exposure to air of the n -polysilicon surface after the (Cl + N2 ) plasma irradiation caused desorption of N atoms as well as ox.idation of the surface. Thus, the surface SI-N bonds can be easily replaced by other oxidized bonds such as Si-Cl and Si-O.
Figure 5 shows the effects of N2 addition on the vertical and horizontal etch rate of n+-polysllicon. With increasing N2 addition, the horizontal etch rate decreases and becomes negligibly small at N2 /(N 2 +C1 2 ) Z 10%, whereas the vertical etch rate decreases 239
(b)
(a
C12S
-11000 S Clon Si02
C
0 0
C
0q
10I
270
I
I
210
2t Binding Energy (eV)
Binding Energy (eV) (c) -J1000
N1S
N on S102
0 0
a
I
402 408 Binding Energy
3
396 Binding Energy (eV)
(eV)
Fig. 4. XPS spectra of (a) Si, (b) Cl, (c) N, and (d) 0 measured for the area patterned with lines and spaces, etched by the N2 added C12 plasma at 4 mTorr. Spectra for perpendicular (a, 7 ) and parallel (8, 5) collection of photoelectrons before (a. 8 ) and after (27, 5 ) exposure of the sample to air are compared. Dotted lines show the peak separation by the least square fit and the peaks marked by arrows can be assigned as the peaks which originate from the N adsorption on the side wall of n*-polysillcon.
240
b U
E LU)
3
u2
0
a-
+_ 0
t
0
10
20 N 2 I(N
2
30
40
+C1 2 )
(04)
50
Fig. 5. Added N2 concentration dependence of etching The total characteristics of n+-polysilicon. pressure is 4 mTorr and the microwave power is 700W. The dotted line is the result calculated from Eq. (1) with x=4 and y=4/3. drastically up to N2/(N 2 +C12 ) = 20% and then decreases gradually. Therefore, high anisotropy can be obtained for N2 / (N2 +C 2 ) 1 10. In order to analyze the radical reaction which is dominant on the side wall, the plasma light emission intensity has been measured. The results are shown in Fig. 6. The emission intensity of N increases with the added N2 concentration. The slope becomes steeper for N2 /(N2 +Cl ) Z 20%. The emission intensity of Cl decreases up to N /(N 2+Cl2 z 10%, and a slight decrease is observed for N2 /(N 2 +Cl ) z 10%. in tIe following discussion, the relationship between the etcA rates and the input N9 and Cl2 partial pressures is examined assuming that the measure emIssion intensities are proportional to the radical concentrations. If Cl and N are adsorbed competitively on the Si surface under a quasi-equilibrium condition, the adsorption and reaction can be described by an equation similar to Langmuir's adsorption isotherm R = A'CCIX /
(JlB'CNY)X
.
(1)
where R is the etch rate, and A and B constants depending on the reaction rate between Si and Cl and the surface coverage of N, respectively. Further, CCl and C3 are the concentrations of active Cl and N radicals, respectively, and x and y are constants depending on the surface reaction. Here, the following assumptions are made : 241
E0 -0
V) C .S C 0
•
w
0
10
20
N 2 /(N
2
30
+C12 )
40 (°/
50
)
Fig. 6. N2 concentration dependence of optical N2 added C12 plasma. The emission intensity from total pressure is 4 mTorr and the microwave power 700W. 1.
Si is etched as SiCI(x=l, 2, 3, and 4), surface as SINy(y=4/3, 4/2, and 4/1).
and N Is bonded on the
As an approximation, the adsorbed surface concentration of N is assumed to be large and that of C1 small. To evaluate R from Eq. (1), further assumptions are made as follows: 2.
CC1 and Cu are proportional to the measured emission intensities. that the SI-N bonds formed on the surface on XPS results Based 4. are similar to those in Si 3 N4 , it is assumed that y is 4/3. Using these assumptions, the constants A, B, and x in Eq. (1) were determined as R evaluated by Eq. (1) fits best the experimental data. The comparison-of the results obtained by Eq. (1) (dotted line) with the experimental data is shown in Fig. 5. The agreement is very good for the horizontal etch rate. On the other hand, the vertical etch proceeds even at N concentration higher than 20 %, and then the vertical etch rate could not be fitted by a single set of parameters over the whole N concentration region, although lower and higher This parts than about 20% addition of N could be fitted separately. indicates that due to the ion ?ncidence onto the surface, the adsorption and reaction characteristics in the vertical etching are different from those in the horizontal etching. It is possible that in spite of existence of chemisorbed N atoms the ion incidence causes vertical etching even for a high N2 concentrations. 3.
242
CONCLUSIONS The effects of the N addition to the Cl2 plasma in anisotropic etching process of n+-pofysilicon have been investigated under a highly selective condition using an ultraclean ECR etcher. The XPS analysis showed that the SI-N bonds are formed on the side wall surface by N radicals competitively with Cl etching. Using the light emission intensity from the plasma, the horizontal etch rate can be expressed as a radical reaction using an equation similar to Langmuir's adsorption isotherm, whereas the vertical etching is affected by the ion incidence. ACKNOWLEDGMENTS The authors would like to thank Prof. N. Mikoshiba for encouragements throughout this study. They also thank T. Kawashima and Y. Yamashita, Seiko Instruments Inc., for manufacturing the ultraclean ECR apparatus, S. Matsuo, NTT, for valuable advice about apparatus, and M. Onodera for resist patterning. This study was carried out in the Superclean Room of the Laboratory for Microelectronics, Research Institute of Electrical Communication, Tohoku University. REFERENCES [1]
T. Matsuura, H. Uetake, J. Murota, K. Fukuda, T. Ohmi, N. Mikoshiba, T. Kawashina, and Y. Yamashita, Ext. Abstr. of 21st Conf. on Solid State Devices and Materials, Tokyo, p. 149 (1989). [2] T. Matsuura, H. Uetake, T. Ohni, J. Murota, K. Fukuda, N. Mikoshiba, T. Kawashima, and Y. Yamashita, Appl. Phys. Lett. 56, 1339 (1990). [3] H. Uetake, T. Matsuura, T. Ohmi, J. Murota, K. Fukuda, and N. Mikoshiba, Appl. Phys. Lett. 57, 596 (1990). [4] T. Matsuura, H. Uetake, J. Murota, K. Fukuda, T. Ohmi, and N. Mikoshiba, Ext. Abstr. of 22nd Conf. on Solid State Devices and Materials, Sendai, p.199 (1990). [51 K. Nishloka, N. Fujiwara, M. Yoneda, and T. Kato, Microelectronic Engin. 9, 481 (1989).
243
LOW TEMPERATURE ETCHING OF ORGANIC PHOTORESIST WITH AN ELCTRON CYCLOTRON RESONANCE SYSTEM Walter Varhue and Jeffrey Burroughs Dept. of Electrical Engineering University of Vermont Burlington, VT. 05405 Walter Mylnko IBM Burlington Essex Junction, VT. An electron cyclotron resonance plasma was used at low substrate temperature (> -100 OC) to anisotropically etch a thick planarizing layer of organic photoresist in an 02 discharge. RF substrate biasing was used to increase the the etch rate. Etch rate was found to be affected by the ion power density impinging on the substrate. The plasma stream was found to contain approximately equal numbers of ions and reactive neutrals [0]. Four mechanisms were identified which contributed to lateral etching. Lateral etching was observed to decrease by the combined application of RF substrate bias and low substrate temperature. INTRODUCTION The fabrication of submicron size features in VLSI circuits is complicated by the fact that the depth of focus of the alignment tool can be less than the topography of the existing circuit structures [1]. This problem is solved by first applying a thick planarizing layer to the wafer and then proceding with either a multilayer resist or silylated resist process[1,21.
The planarizing layer is a spun on organic photoresist or polyimide. This layer is typically dry developed by an oxygen plasma. Anisotropic etching is required to transfer the top resist pattern to the lower resist layer. This investigation focuses on the improvement in anisotropy of this process by coupling two techniques which have been shown to be successful toward this end. The first is to use of an electron cyclotron resonance discharge. Limited ion scattering due to low pressure operation and high ion flux densities capable with an ECR system result in improved anisotropy over that of reactive ion etching (RIE) [3,4 and 5]. Significantly reducing the substrate temperature, referred to as cryogenic etching, has been shown to improve anisotropy without a reduction in selectivity or etch rate[6]. Dry etching in general is composed of spontaneous and ion assisted reactions. The spontaneous reaction which is temperature dependent causes undercutting of the sidewalls of etched trenches and can be controlled by temperature. The ion assisted vertical etch rate is insensitive to temperature over a wide range of operation. This investigation considers the anisotropic nature of the etching process as a function of RF substrate bias, reactor pressure and substrate temperature (between 0 to -100 oC).
244
EXPERIMENTAL
The etching study was performed in a custom built electron cyclotron resonance reactor. A sketch of the system is shown in Figure 1. The chamber is constructed with 8" Conflat flanges with all metal seals with the exception of the loading port which has a Viton o-ring.
The system is evacuated with a turbomolecular pump backed by a Roots blower and a rotory mechanical pump. The total chamber volume is 22 liters. MIOR
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Figure 1. Sketch of the ECR Reactor design. Microwave power at a frequency of 2.45 GHz is applied to the resonance chamber through a quartz window. The applicator has a gradual transition from a WR 284 guide to an 11 cm. diameter cylindrical guide segment. Two electromagnets are located around the resonance chamber and give a magnetic field of approximately 925 G near the window which then drops to the required ECR condition of 875 G at approximately 5 cm into the chamber. The resonance chamber is 23 cm long and is separated from the substrate chamber by a constricting orifice which is 9 cm in diameter. The wafer chuck is an 11 cm diameter, 1 cm thick Al disk. Cooling is provided by a cryogenic compressor made by Polycold Inc. Cu tubing mounted on the backside circulates an expanding mixture of freon and Ar. The chuck temperature can be operated as low as -110 °C. The Cu tubing is bonded to the Al chuck with Emerson-Cummings stycast epoxy, choosen for its good thermal conductivity and high electrical resistivity. The high electrical resistivity is needed to permit the application of RF biasing to the substrate.
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The samples etched were 3 cm by 3 cm squares of multilayer resist on single crystal silicon and were clamped into place behind a counter sunk retaining ring. To ensure good thermal contact to the chuck, the back of the wafer squares were covered with a thin coating of Dow Coming 704 grease. The retaining ring prevented plasma exposure to the grease as well as provided a thermal break between the plasma and the chuck. The etched pattern was a series of closely spaced lines with features as small as 0.3 gi. The planarizing layer was 1 gt thick Novolac resist. The mask was a 100 nm patterned plasma oxide layer. Characterization of the discharge included optical emmission spectroscopy to monitor the free radical oxygen concentration and Langmuir probes to measure the plasma density and electron temperature in both the resonance and substrate chamber. RESULTS AND DISCUSSION Etch Rate and Plasma Stream Characterization The measured etch rates without an external bias were unsatisfactorally low. Etch rates were a factor of six less than those obtained by D. A. Carl et. al.[5] using a similar technique. The reason for the lower etch rates is due to differences in reactor design. The chamber volume used in the present study is larger than that used in the previous study by a ratio of 11:4. This resulted in longer residence times, (0.2 - 0.9 sec.) and a pump speed limited maximum oxygen flow of 5.0 sccm at a pressure of 1 mTorr (0.013 Pa). A further disadvantage obtained from the larger resonance chamber diameter was that for the same input microwave power, the power flux in the resonance chamber was a factor of four lower. This resulted in lower plasma density and lower production rate of oxygen free radicals. Finally the distance from the limiting ring was 50% longer, resulting in additional attenuation of the beam reaching the substrate. RF substrate bias was added to improve the etch rate as is shown in Figure 2. Also shown is an increase in etching rate with decreasing chamber pressure. The ion flux to the substrate was determined by DC biasing the wafer chuck at - 65 V and measuring the collected current. The contribution of secondary electrons to the current is estmated to be less than 3 %. The ion flux as a function of pressure is shown in Figure 3 and is found to decrease strongly with increasing pressure. The plasma density in the resonance chamber was measured with a Langmuir probe by the method of Laframboise [7]. Over this range of pressures the plasma density is relatively constant. The large change in ion flux measured at the substratV can be explained as ion scattering by gas molecules in the chamber. Assuming a scattering model and calculating a cross section for the process, an ion-neutral cross section of value of 0.117 nm 2 is obtained. The cross section for the charge exchange reaction in oxygen is 0.15 nm 2 and could account for the measured value considering that the cross section for total removal from the beam should be less.[8] The concentration of oxygen free radicals was monitored by optical emission spectroscopy using a technique known as actinometry. The assumptions of actinometry are that for two excited states of similar energy, the activation cross sections have a similar threshold and shape. In this case the (844.5 nm) line of oxygen, obtained only through the direct excitation of atomic oxygen, is ratioed against the (750 nm) line of Ar.[9] A plot of this ratio as a function of microwave power was linear as expected. However this ratio as a function of pressure was not as straight forward as can be observed from Figure 4. 246
Variations in pressure were obtained by adjusting the throttle valve. This caused an increase in residence time of the gas in proportion with pressure. An increase in pressure should increase the number of collisions leading to the production of more atomic oxygen. However, the electron temperature as measured with the Langmuir probe, decreases with pressure, Figure 5. The electron mean free path decreases with pressure, and therefore the average energy obtained by the orbitting electron is less. The lower electron temperature results in a lower production rate of atomic oxygen in the plasma. The threshold for the electron impact dissociative reaction is (4.5 eV).[10]
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Figure 3. Ion current density versus reactor pressure with 500 W microwave power and 5.0 sccm flow rate.
An estimate of the atomic oxygen concentration can be obtained from OES data and the ideal gas law. The estimate places the atomic oxygen flux to the substrate at (1 - 3 X 10 16 atoms/cm 2 -s). This can be considered only as a rough estimate because it assumes equilibrium between the plasma stream and the gas in the substrate chamber, which is clearly not the case. This flux is similar in magnitude to the ion flux impinging on the substrate(1 -2 X 10 16 ions/cm 2-s). A plot of the yield per incident ion as a function of pressure and substrate bias is shown in figure 6. As expected, the yield increases with ion energy and for the most part with pressure as the surface coverage by atomic oxygen increases. The best fit for the experimental data occurred for etch rate versus total ion power density. The ion power was calculated as the average ion energy ( bias potential + plasma potential) times ion current density. This relationship is plotted in figure 7 for three different pressures. The close fit for the thr different pressures indicate that ion power density is the dominant factor controlling the etch rate for these conditions. Similar results 247
were obtained by Jurgensen et. al [11] for etching resists in an oxygen RIE process. The results also indicate that the rate saturates with increased power density as predicted by the model proposed by 0. Joubert et. al. [4] which identifies an equal dependence on both ion flux and atomic oxygen flux to the surface. Relative to RIE systems, the beam obtained in this study has a low ratio of atomic [0] to ionic [02+] flux. Such a ratio would indicate poorer etch rates yet the prospect for good etch anisotropies. The following section will address the observed etch profiles. 7-
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Etch Profiles The reactor operating conditions used to etch all patterns were 1.0 mTorr (0.013 Pa) pressure and 5.0 sccm total oxygen flow to the resonance chamber. The parameters varied were RF substrate bias ( -20, -80, and -100 V) and substrate temperature ( room temperature to -100 oC). The evolution of the observed etched patterns can be explained by four separate etching mechanisms. The first mechanism is the isotropic etching by neutral reactive species, in this case [0]. This mechanism results in classic undercutting as depicted in Figure 8 a. This mechanism depends on the flux of reactive [0] neutrals to the surface and substrate temperature. The second mechanism involves the enhanced etching by energetic ions and neutrals with off-angle trajectories striking the lower wall of the etch trench. The off angle nature of the ions comes from either high ion temperatures in the resonance chamber, scattering by gas molecules along the path from the resonance chamber to the substrate or acceleration along a diverging magnetic field line. Energetic neutrals result from charge exchange collisions with gas molecules. There is very little scattering in sheath between the plasma and the substrate because the gas density is low and the sheath thickness is much smaller than the mean free path as predicted from expressions found in reference [12] in contrast to 248
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Figure 7. Removal rate versus ion power density at 500 W microwave power and 5.0 sccm flow rate.
the situation in RIE systems. The lateral etching occurs lower in the etch trench than that observed in etching from thermal reactive neutrals due to collimation by the mask. A sketch of the expected profile from this mechanism is shown in Figure 8 b. This mechanism is expected to be dependent on reactor pressure, substrate temperature and substrate bias. The third mechanism is the result of electrons charging the inside walls of the etched trench. The electron charge most likely arrives on the walls during the positive swing of the RF bias cycle. The electron charge perturbs the electrostatic potential profile from one that is everywhere parallel to the substrate, to one that conforms to the etch trench. The incoming ions are accelerated laterally toward the trench walls, striking it near the bottom. Enhanced etching is expected near the bottom of the trench as depicted in Figure 8 c. The fourth proposed mechanism is the sputter errosion of the mask layer. For ions of energy sufficient to sputter the SiO 2 , the mask is first faceted and then its width is decreased. Once the underlying material is exposed to the plasma, ion enhanced etching occurs. Sputter erosion of the mask appears to be accelerated in cases where the mask cap has been undercut by lateral etching described in mechanism one. A sketch depicting this mechanism is shown in Figure 8 d. This mechanism is primarily dependent on substrate biasing, but is temperature dependent through its interaction with mechanism one. Scanning electron micrographs of the resulting etch profiles obtained with -20 V, -80 V and -100 V RF substrate bias are shown in Figures 9.a, b, and c respectively. The profiles shown in Figure 9 a. obtained with -20 V RF substrate bias are arranged in order of decreasing substrate temperature. The highest substrate temperature, at 9 oC, exhibits undercutting due to spontaneous reaction with thermal neutrals. As the substrate 249
temperature is decreased the undercutting is elliminated. The other mechnism which appears to be active at these reactor conditions is the the enhanced etching by off-angle particle trajectories. Lowering the substrate temperature reduces this effect but does not elinimate it. Results from etching with a 80 V RF substrate bias are shown in Figure 9 b. The greatest effect of the increased bias is to redirect the off-angle component of the incident ion towards a more perpendicular trajectory. The result is a sharper defined bottom edge. The shape of this edge improves further with lower substrate temperature. This indicates that perhaps a passivating layer forms on the trench wall which reduces the ion assisted etch rate from the off-angle ion trajectories. Another possible explanation is that etching by the neutral component of the off-angle particle flux has been reduced. Undercutting is not as evident in runs performed with -80 V RF substrate because the over hanging oxide cap has been removed by sputter errosion. Ion enhanced etching of the newly exposed material is evident in the run performed at -49 oC. At the lowest temperature of -97 oC where undercutting was eliminated, the mask remained intact, although faceted, and the best etch profile was observed.
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Figure 8. Lateral etching mechanisms; a. classic undercutting, b. off-angle ionic and neutral species, c. electro charging of resist layer, and d. mask sputter errosion. Etch profiles obtained with RF substrate biasing of -100 V are shown in Figure 9 c. Ellimination of the notching observed at the base occurs with a reduction in substrate temperature. Ion bombardment appears to be energetic enough in this case to result in mask errosion regardless of the underlying structure. The overall etch anisotropy has been quantified as the ratio of the highest lateral etch rate occurring any where on the trench sidewall, (a), versus the vertical etch rate, (b). A 250
Figure 9. Scanning electron micrographs of etch profiles organized according to substrate bias and temperature as follows: a. (-20 V) +9 C, -28 C, -49 C and -76 C. b. (-80 V) -8 C, -49 C -82 C and -97 C and c. (-100 V) -31 C, -58 C, -68 C and -80 C.
251
plot of this ratio as a function of temperature can be found in Figure 10. There is a gradual improvement in anisotropy with decreasing substrate temperature. Bias also is observered to significantly improve the resulting anisotropy. The beneficial effects of RF substrate biasing seem to saturate at about -80 V. Lower substrate biases should be tried to reduce the problems encountered with mask errosion.
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CONCLUSION The etch rate of organic photoresist is significantly influenced by the incident ion energy controlled by RF substrate biasing. The best fit of the experimental data occurred for etch rate versus ion power density. The plasma stream in this investigation is composed of approximately an equal number of reactive oxygen atoms and 02+ ions. Sidewall etching can result from a combination of at least four separate etch mechanisms. Lower substrate temperature can significantly reduce the rate of these etching mechanisms. Excellent etch anisotropy can be obtained by controlled use of both RF substrate bias and lower substrate temperature to reduce these lateral etching mechanisms.
252
ACKNOWLEDGEMENT We are grateful for the support received by International Business Machines of Essex Junction Vermont. REFERENCES [1]
S. Wolf and R. N. Tauber, Silicon Processing for the VLSI Era, Vol 1, Lattice Press, Sun Set Beach, Calif. (1987).
[2]
R. S. Hutton, R. L. Kostelak, 0. Nalamasu, A. Kornbilt, S. McNevin, and G. N. Taylor, J. Vac. Sci. Technol. B 8 (6) 1502 (1990).
[3]
T. H. Lin, M. Belser, and Y. Tzeng, IEEE Trans. on Plasma Sci., 16 (6) 631 (1988).
[4]
0. Joubert, J. Pelletier, and Y. Arnal, J. Apple. Phys. 65 (12) 5096 (1989).
[5]
D. A. Carl and D. W. Hess, J. Apple. Phys., 68 (4), 1859 (1990).
[6]
S. Tachi, K. Tsujimoto, H. Kawakami and S. Okudaira, Extended Abstracts of the 20th Conf. on Solid St. Devices and Mat., Tokyo, 553-556, (1988).
[7] [8]
J. G. Laframboise, Inst. for Aero. Stud., Univ. of Toronto, Rep. No. 100 (1966). R. F. Stebbings, B. R. Turner, and A. C. H. Smith, J. Chem. Phys., 38 2277 (1963).
[9]
W. K. Bischel, B. E. Perry and D. R. Crosley, Chem. Phys. Lett. 82,85 (1981).
[10] K. Masek, K. Rohlena, and L. Laska, Pure Appl. Chem, 54 1181 (1982). [11] C. W. Jurgensen and E. S. G. Shaqfeh, Polymer Eng. and Sci, 29 (13) 878 (1989). [12] K. Suzuki, K. Ninomiya, S. Nishimatsu and S. Okudaira, J. Vac. Sci. Technol. B3 (4) 1025 (1985).
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SILICIDED SHALLOW JUNCTIONS FOR ULSI K. Maex, L. P. Hobbs and W. Eichhammer Interuniversity Microelectronics Center (IMEC v.z.w.) Kapeldreef 75, 3001 Leuven, Belgium The scaling down of device lateral dimensions imposes severe restrictions on the depth of shallow junctions. The technological scheme for silicided shallow junction formation is a crucial part in the process flow, since more stringent boundary conditions appear as a consequence of scaling. In this work materials issues such as metal dopant compound formation and annihilation of implant end-of-range defects will be addressed. In addition the technology chosen for the formation of silicided shallow junctions, as well as process implementation will be discussed.
INTRODUCTION The formation of silicided shallow junctions for ULSI applications has been the subject of intensive research over the last years. Many materials aspects have been' investigated for the various silicides and based on this knowledge various formation technologies have been proposed. The interaction of silicides and doped Si has led to numerous reports and still many issues remain to be investigated. In this paper an overview will be given of the materials characterization of silicides specifically w.r.t. doped Si. The most promising technologies for the formation of silicided shallow junctions will also be discussed.
MATERIALS CHARACTERIZATION As a consequence of the trend to scale silicided shallow junctions, the formation of the doped Si and the overlaying silicide become inherently dependent on each other. In search of the silicide with optimal properties for implementation of silicided shallow
254
junctions in advanced MOS or bipolar processes, comparative studies of transistion metal silicides are mandatory. In addition to material properties such as self-alignment of the silicidation reaction w.r.t. oxide [1,2], chemical inertness, resistance to chemical etching solutions or to dry etching processes, stress generation by the silicide in the underlying Si [3] etc, the stability of high concentrations of dopants in Si adjacent to the silicide is an important issue. The various silicide formation technologies aim at a final structure consisting of a low-resistivity silicide on top of a highly doped Si substrate. The chemical stability of this high dopant concentration in the Si should be taken into account since chemical interactions between the three elements present viz. the dopant, the Si and the metal can occur during each subsequent high temperature treatment The occurence or absence of metal dopant compound formation is, therefore, a major parameter in establishing the attractiveness of the various silicides. Metal-dopant compound formation has been experimentally observed by SEM, SIMS, TEM and XRD for TiSi 2 and TaSi 2 on B and As doped Si [4-6]. From straightforward thermodynamic calculations, the driving force for metal-dopant compound formation can be estimated. The details of such calculations are found in ref [7,8]. Based on the interpretation of the thermodynamics involved, it can be concluded that CoSi2, MoSi2 and probably WSi 2 do not suffer from compound formation and the concomitant interface dopant depletion, when the layers are used on highly doped Si. Metal dopant compound formation has implications for the reaction kinetics of silicidation on doped Si [9], for shallow junctions and contact resistances of silicided preformed junctions as well as for the outdiffusion of dopants from an implanted silicide [101. Although many mechanisms contribute to the redistribution of dopants in the vicinity of the silicide/Si interface during a high temperature treatment, it has been shown that metal-dopant compound formation at the interface between the silicide and the doped Si has a large impact on the interface dopant level. The outdiffusion process from an implanted silicide is most prone to these effects, since the dopants are brought in close vicinity to the metal atoms, whereas in the case of silicidation of doped Si, higher temperatures are needed to allow the diffusion of dopant in the Si prior to reaction with the metal atoms. In fig. I SIMS profiles are shown for diffusion of B and As from various implanted silicides into the Si. The depth scale of the profiles starts at the
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silicide/Si interface. It is clear that outdiffusion of the dopants from CoSi2 and MoSi2 is
much easier than in the case of TiSi 2 and TaSi2. The dopant doses diffused from the implanted silicide into the underlaying Si are about an order of magnitude higher in the case where no metal dopant interaction was expected than in the case where the interaction does occur. This observation is in full agreement with the predictions based on the thermodynamic arguments and with the experimental observation of metal-dopant
compounds. Metal dopant compound formation can be limited if Si consumption, which occurs during silicide formation, is avoided, e.g. by using chemical vapor deposition for silicidation [11], and if no subsequent high temperature treatments are necessary.
FORMATION TECHNOLOGY Preformed junctions In the case of preformed junctions, the doped regions are defined in the Si prior to silicidation. This means that the junction depth is completely determined by the implant and annealing conditions. The formation of the shallow p+ junction poses the greatest challenge. The use of Ge to preamorphize the Si in combination with BF 2 has become a classical method by which to create these junctions [12]. Another method to minimize the junction depth is by using Sb instead of Ge [13,14]. Sb has the same preamorphizing effect as Ge, but its electrical activity yields a compensation of a part of the p+profile. To obtain the desired p-type concentration versus depth an optimization of both BF2 implant and Sb implant has to be achieved. A complete picture of the junction depth for a lxl0 15 cm-2 BF 2 implant at 20 keV in combination with a 3x10
13
cm-2 Sb
implant at various energies is presented in fig. 2a. The junction was annealed at 1 10OPC for 10s. The junction depth was determined from SIMS profiles, taking the intercept of the chemical B and Sb profiles. The junction depth can be tuned by adjusting the Sb implant energy, without decreasing the maximum net dopant concentration level. A reduction in junction depth from 130 nm, using a single BF 2 implant at 20 keV down to below 100 nm in combination with Sb can be achieved. Fig. 2b shows the leakage current and the contact resistance for these junctions. Whereas the contact resistance remains almost constant for all depicted cases, the leakage current increases for the
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shallowest junctions. No extended defects from the Sb implants were revealed by TEM. The origin of this increase in leakage current is presently under investigation. Subsequent to the shallow junction formation, the silicide is grown on top of the doped region. The thicker the silicide grown the lower is the sheet resistance of the area. The thickness of the silicide is, however, limited by the junction depth due to the Si consumption. A critical distance between the silicide and the junction region has to be taken into account in order to avoid high leakage currents of the diodes. This critical distance between the silicide/Si interface and the junction has been estimated experimentally by measuring the leakage current of p+-n junctions. In fig. 3 the leakage current is plotted as a function of the silicide sheet resistance as well as a function of the estimated distance between silicide/Si reaction front and metallurgical junction. The p+ junctions were formed by a 20 keV BF 2 implant with a dose of lxlO05 cm-2 , leading to a junction depth of about 0.09mm as measured by spreading resistance probe (SRP). After annealing at 11 00oC for 1Os, either 30 or 40 nm Ti was deposited to form a silicide. The calculation of the distance between the silicide and the junction depth was based on the sheet resistance of the silicide assuming a specific sheet resistivity of 15 mOhmcm. The dotted line represents the mean leakage current on a wafer which has not been silicided. The results from this figure suggest that a distance in the region of 50 nm must be maintained between the silicide and the junction.This in turn indicates that higher sheet resistances will have to be tolerated on silicided junctions in advanced technologies. In the optimization of preformed shallow junctions the shrinkage of extrinsic defects, viz. dislocation loops by the silicidation process could be beneficial for the electrical quality of the junction with a lower temperature budget. Annihilation of endof-range defects based on TEM investigations has been reported by Wen et al. [15,16] in the case of Ge preamorphized p+ junctions and by Maex et al. [17] in the case of As implanted junctions. The efficiency of this defect annihilation effect can only be fully evaluated by observation of diode leakage currents. In this way the homogeneity and reproducibility over large areas can be observed in contrast with TEM measurements which cover only a very small material volume. A study on diode leakage currents in the case of CoSi2 and TiSi2 formation is reported in ref [ 18]. A distinct improvement of the leakage current upon silicidation with Ti was observed. However a more detailed
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investigation indicates that the annihilation process is difficult to reproduce on large areas. In this case p+ junctions were formed with the same conditions as for fig.3, but with a 150 keV Ge preamorphization. About 40nm of Ti was deposited on the wafers for silicidation. In fig.4 the leakage curmnt density is plotted similar to fig.3. The dotted line in this case represents the mean leakage current from a wafer which has not been silicided, and where defects are observed by TEM to be present in the space charge region of the reverse biased diode. It is observed that the leakage current is greatly improved in the silicided wafer when the silicide sheet resistance is sufficiently high. This would suggest that if the leakage current density is to be further improved then the silicide front must be moved closer to the defects (i.e. use a thicker silicide). However, by doing so the leakage current will increase, as mentioned before, due to the proximity of the silicide front to the junction.
Outdiffused junctions Dopant outdiffusion is an attractive alternative to the direct implantation into silicon for the formation of shallow junctions [10, 19-23]. The main advantage of the outdiffusion process is that the implantation damage is confined within the silicide. The junction depth is controlled by the temperature treatment and the spiking of the junction by the silicide is avoided since the dopant diffusion front is parallel to the silicide/Si interface. Fig.5 shows SIMS profiles for B diffused from implanted CoSi2 during 30s at various temperatures. For the lowest diffusion temperature (at 9000C), no evidence for diffusion can be observed by SIMS, since the measured profiles before and after the temperature treatment are coincident. The doping profiles are so shallow after 9000C, that the measurement is masked by the CoSi2/Si interface roughness. However, a detailed investigation, using epitaxial silicides as a diffusion source [24] indicates that even with these low temperature treatments, some diffusion into the Si takes place. The estimated distance between the silicide and the junction is less than 50nm. It should be noted that the characteristics of the capping layer has a distinct influence on the outdiffused doping profile. In fig. 6 undensified TEOS, and densified TEOS capping layers are compared.The oxide layer during implantation, if present, was 20 nm thick.
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During the subsequent temperature treatment an oxide layer of 100nm thick was used. The interface between the capping layer and the silicide is an attractive place for the dopants. There is always an accumulation of dopants at this interface. This fact might explain why a different diffusion profile is obtained for differently treated capping layers. The difference in the profiles as measured with SIMS was reproduced in the electrically active profiles as measured by SRP. Table 1 gives an overview of the electrical characteristics viz. the diode leakage current density and the specific contact resistance for these outdiffused junctions. The implant was performed through a thin densified TEOS layer. The diodes were measured on lmm2 devices and the contact size was 4 x 4 mm2 . The procedure for contact resistance measurement was the same as in ref.10. It can be concluded that even for the lowest temperature treatments good diode leakage currents and good contact resistances are achieved. Even though the distance between the silicide/Si interface and the junction can be very small (<50nm), good diode leakage current densities are obtained. This is to be attributed to the conformal diffusion of the dopants w. r. t. the silicide dopant source. The increase of the contact resistance in case of B for the higher outdiffusion temperatures might be due to the redistribution of the dopants during the high temperature treatment.
JUNCTION DESIGN AND DEVICE IMPLEMENTATION For the implementation of a silicided shallow junction in a device, considerations have to be taken into account, which are dictated by the full technology. For instance, the inclusion of the preamorphizing impurities (as in the case of Ge) has been seen to enhance the degradation of PMOSFETS (251. Also, in a process using self-aligned silicides, a compromise will be required between junction depth, silicide thickness and spacer width to achieve optimal device performance. A detailed analysis of the dependence of the amount of shorts between gate and source/drain has led to the conclusion that the width of the spacer cannot be scaled down without limits [26]. In addition, the stability of the silicide on the poly-Si in a self-aligned technology has to be taken into account. Investigations have revealed a degraded thermal stability of the silicide/poly-Si runners for submicron widths [27-29].
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SUMMARY AND CONCLUSIONS
The formation of shallow silicided junctions has been discussed. For preformed junctions and even more so for outdiffused junctions, the chemical interaction between dopants and metals has important implications on the final dopant level in the Si at the silicide/Si interface. From the self-aligned silicides, only CoSi2 does not suffer from metal dopant compound formation. In the case of preformed shallow junctions, the implant and anneal conditions determine the overall junctions depth. Sb was shown to be an attractive alternative as a preamorphizing species instead of Ge. For the silicidation of preformed shallow junctions, a distance of about 50nm has to be taken into account in order to obtain low leakage currents for diodes. Moreover, the observed annihilation of implant end-of-range defects does not seem to be reliable enough to be advantageous in the formation of silicided shallow junctions. In the case of outdiffusion from implanted CoSi2, limited temperature treatments yield good leakage current densities for diodes and low specific contact resistances. The choice of a particular silicidation and shallow junction formation technology depends, however, to a large extent on the implementation in a full process.
REFERENCES 1. M.E. Alperin, T.C. Holloway, R.A. Haken, C.D. Gosmeyer, R.V. Karnaugh and W.D. Parmantie, IEEE Trans. Electron Devices, 32, 141 (1985). 2. L. Van den hove, R. Wolters, K. Maex, R. De Keersmaecker and G. Declerck, IEEE Trans. Electron Devices, 34, 554 (1987). 3. L. Van den hove, J. Vanhellemont, R. Wolters, W. Claassen, R. De Keersmaecker and G. Declerck, Proc. Int. Symp. on Materials for ULSI, Electrochemical Society, Pennington, NJ, Vol. 88-19, 165 (1988). 4. V. Probst, P. Lippens, L. van den hove, K. Maex, H. Schaber and R. De Keersmaecker, in Proceedings of the European Solid State Device Research Conference (ESSDERC) Bologna, Italy, edited by G. Soncini and P.U. Calzolari, 397 (1987). 5. V. Probst, H. Kabza and H. Goebel, in Proceedings of the European Solid State Device Research Conference (ESSDERC), Montpellier, France, edited by J.-P. Nougier and D. Gasquet (Les Editions de Physique, Les Ulis, 1988) Vol.49, p. C4-175 (1988).
260
6. V. Probst, H. Schaber, P. Lippens, L. Van den hove and R. De Keersmaecker, Apple. Phys. Lett. 52, 1803 (1988). 7. K. Maex, G. Ghosh, V. Probst, P. Lippens, L. Van den hove, L. Delaey and R.F. De Keersmaecker, J. Mat. res, 4, 1209 (1989). 8. K. Maex, G. Ghosh, L. Delay,
R.F. De Keersmaecker and V. Probst, J. Appl.
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261
23. C.M. Osbum, Q. Wang, M. Kellam, C. Canovai, P.L. Smith, G.E. McGuire, Z.G. Xiao and G.A. Rozgonyi, presented at the European Workshop on Refractory Metals and Silicides, Saltsj6baden, Sweden, March 1991, to be publ. in Appl. Surf. Sci. 24. W. Eichhammer, K. Maex, W. Vandervorst and K. Elst, presented at the European Workshop on Refractory Metals and Silicides, Saltsj6baden, Sweden, March 1991, to be published in Appl. Surf. Sci. 25. L. Hobbs and K. Maex, this Symp. 26. L. Hobbs and K. Maex, presented at the European Workshop on Refractory Metals and Silicides, Saltsj6baden, Sweden, March 1991, to be published in Appl. Surf. Sci. 27. Karen Maex, presented at the European Workshop on Refractory Metals and Silicides, Saltsj6baden, Sweden, March 1991, to be publ. in Appl. Surf. Sci. 28. H. Norstr6m, K. Maex and P. Vandenabeele J. Vac. Sc and Techn. B 8, 1223 (1990). 29. H. Norstr6m, K. Maex and P. Vandenabeele, Thin Solid Films, 196, 53 (1991)
Table I: Leakage current densities and specific contact resistance for samples with B and As outdiffusion from CoSi2. The outdiffusion conditions were varied from 900 to 1050 0 C
ARSENIC
BORON leakage current density2 nA/cm
specific contact resistance gfcm2
leakage current density nA/cm2
specific contact resistance 2 pncm
900 *C
30 s
0.9
0.92
N/A
N/A
950 0C
30 s
1.47
1.16
N/A
0.92
1000 *C
10s
0.67
4.03
2.8
1.28
1050 *C
10 s
0.90
2.5
0.72
11.8
262
E U 0 r e.)
0
Depth [Im,]
Depth [r-]
Figure 1: SIMS profiles in Si after diffusion of (a) B and (b) As from various diffusion sources upon furnace treatment. The origin of the depth axis is the silicide/Si interface.
140-
E
-30-
S120. S110100S 90. 40
60
80 100 120 ImpiN Enar In- keV
140
70
Sb Imp
90
Ito
130
t En-gy (keV)
Figure 2: (a) function depth versus Sb implant energy for samples in which a BF2 implant of lxl0 15 cm-2 at 20 key has been performed into Sb preimplanted substrates. The Sb dose was 3xl013cm- 2 . The dopants were activated at 11000C for 10s. Also included are the reference points of samples which received the BF2 implant only. (b) Diode leakage current density and specific contact resistance for samples treated with the same implant and anneal conditions as under (a). 263
Sheet Resistance (ohm/sq.) 3.08
3.33
3.63
4.0
4.44
5.0
0.040
0.045
0.050
0.055
0.060
\, '0
•10"7
lo 8o~
0.035
Junction Depth . TiSi2 thickness (Mm)
Figure 3: Leakage current density for samples with a varying distance between the actual 5 junction depth and the silicide/Si interface. The samples were implanted with lxlO0 cm0 2 BF 2 at 20 keV and annealed at 1 100 C for 10s. The thickness of the deposited Ti was between 30 and 40 nm for silicidation. The dotted line represents the leakage current density for non-silicided samples. Sheet Resistance (ohms/sq.) 3.08
3.33
3.64
4.0
510" o
o
0oo 00
o.
Oo
E 10
6
0
0
0 o0
0 0
0
S10-7
o ..
0.035 Junction
.
,
0 0
0- ,
0
0.050 0.040 0.045 Depth - TiSi2 thickness (gm)
Figure 4: Leakage current density of samples implanted with 1 x 1015 cm- 2 BF2 at 20 keV in to Si, preamorphized with lx10 1 5 cm-2 Ge at 20 keV. The annealing was performed at 1100oC for 1Os. The thickness of the deposited Ti was between 30 and 40 nm for silicidation. The dotted line represents the leakage current denisty for nonsilicided samples.
264
fig. prof'tles 5, 6layer :using analogous conditions for various samples to those
0 C 0 0
U C
U
Depth (nm)
Figure 5: SIMS profiles after outdiffusion of 1x10 16 cm-2 B out of a 13Onm thick CoSi2 at various temperatures for 30s. The capping layer during outdiffusion is an undensified TEOS layer. The origin of the depth scale is the silicide/Si interface.
1021
1019
1017 Undensified TEOS cap (Implantation before TEOS) _. .
Undensified TEOS cap (Implantation through TEOS) TEOS cap (800*C, 30min) (Implantation through densified TEOS)
____Densified
1815
-150
-50
50
150
250
Depth [nm]
265
Figure 6: SIMS profiles for samples prepared analogous to those of fig. 5, using various capping layer conditions Figure prepared capping of SIMS
FORMATION OF SHALLOW BORON-DOPED LAYERS USING PREAMORPHIZATION AND ITS APPLICATION TO MOSFET FABRICATION Masayasu Miyake NTT LSI Laboratories, Nippon Telegraph and Telephone Corporation 3-1, Morinosato Wakamiya, Atsugi-shi, Kanagawa, 243-01 Japan The channel preamorphization technique, a technique for forming shallow boron-doped layers for channel doping using preamorphization, is reviewed. Preamorphization does not affect MOS capacitor characteristics so long as the original amorphous/crystalline interface is sufficiently deep. Buriedchannel pMOSFETs with a shallow boron counter-doped layer using channel preamorphization are successfully fabricated. It is shown that channel preamorphization does not degrade carrier mobility and improves MOSFET characteristics in the subquartermicrometer gate-length region suppressing short-channel effects. INTRODUCTION Shallow boron-doped layers are indispensable for deep-submicrometer CMOS LSI,s as a source-drain (S/D) and as a channel-doped layer for pHOSFETs. It is well known that forming shallow boron-doped layers is not easy due to ion channeling during low-energy boron ion implantation [1, 2]. To form shallow p~n junctions for S/Ds without a channeling tail, preamorphization using Si or Ge ion implantation has been studied and applied to MOSFET fabrication [39]. Formation of shallower boron counter-doped layers in the channel region is also required for subquarter-micrometer buried-channel pMOSFET.s [10]. This paper reviews the channel preamorphization technique, a technique in which a shallow boron-doped layer is formed for channel doping using preamorphization [11, 12]. After briefly reviewing shallow p~n junction formation for S/D-s using preamorphization, the effects of preamorphization on channel-implanted boron depth profiles and characteristics of MOS capacitors fabricated in preamorphized Si substrates are described. Finally, characteristics of buried-channel pMOSFET-s with a shallow boron counter-doped layer and shallow S/D junctions fabricated using preamorphization are shown. SHALLOW p+n JUNCTION FORMATION USING PREAMORPHIZATION
FOR S/D
Figure 1 shows boron depth profiles for preamorphized p~n junctions measured by SIMS (8]. Ion implantation conditions are as follows: BF 2 ion 15 2 implantation at 15-keV energy and a 2x10 -cmdose after Si ion implantation at 20-keV energy and a 2xl0O15cm-2 dose. Annealing was done at 950°C for 15 a using rapid thermal annealing (RTA). As shown in Fig. 1, p~n junctions as shallow as 0.1 lum have been formed without a channeling tail. It has been shown that leakage current is sufficiently small when the original amorphous/crystalline (a/c) interface is shallower than the junction depth [7, 8].
266
.21
Po•ysMcon Gate Gate Ostde Fied Oxide
E Mdcto
LOOP
De~ft
Layer
Edge SI Substrale
O Fig. 2
DEPTH (pm)
Schematic cross section of
P
m
Fig. 1 Boron depth profiles for for preamorphized p~n junctions S/D.
CHANNEL PREANORPHIZATION Vith respect to preamorphization, it has been reported that small dislocation loops are induced at the original a/c interface and cause large leakage currents when they are located in the depletion region [7, 8]. For S/D applications, this problem can be overcome by confining the dislocation loops to the p+ region (8]. However, this approach cannot be applied to channel doping. As an alternative, we have attempted to solve this problem by making the dislocation loop depth deeper than the depletion layer depth; that is, by making the amorphous layer sufficiently deep that the channel and S/D depletion layers cannot reach the original a/c interface as shown in Fig. 2.
Boron depth profiles Figure 3 shows as-implanted boron depth profiles for channel doping measured by SIMS. The solid curve is for the preamorphized sample, and the dashed curve is for the nonpreamorphized one. Ion implantation was carried out through 150-A screen oxide. Si ion implantation for preamorphization was 15 2 performed at 150-key energy and a 2x10 -cmdose. Amorphous layer depth was estimated to be 0.3 j•m by cross-sectional TEN observation of samples without the screen oxide. After Si ion implantation, BF 2 was implanted at an energy 1 3 2 of 25 key and a dose of l.35x10 cu- . Channeling tails can be observed for the nonpreamorphized sample even when ion implantation is performed through 150-A oxide. For the preamorphized sample, the channeling tails are eliminated, and a shallow boron profile is obtained. Figure 4 shows the
267
2
z
.W, z 2
0
DEPTH (jm) depth
As-implanted boron Fig. 3 profiles for channel doping. 1-9
ed
"E
d
)s
E
z U
z
I--
z w
F3 4n 0
0.1
0
0
02
(a)
Preamorphized
Fig. 4
0.1 DEPTH (jmr)
DEPTH (pm)
(b) Nonpreamorphized
Profile broadening due to RTA at 950"C for 30 a.
268
02
profile broadening due to rapid thermal annealing at 950"C for 30 a. Figure 4(a) is for the preamorphized sample, and Fig. 4(b) is for the Dashed curves represent as-implanted profiles, and nonpreamorphized one. solid curves represent annealed profiles. It is clear that the boron profile
broadening is negligibly small for the preamorphized sample while the boron profile
is
substantially broadened by
the annealing
for the
nonpreamorphized
13
sample. The effective diffusion coefficient is estimated to be l.Ox1O2 cm /s for the nonpreamorphized sample. This value is much larger than the 5 2 intrinsic diffusion coefficient at 950"C (4.1x10-1 cm /s) (13]. That is, the profile broadening for the nonpreamorphized sample is due to transient enhanced diffusion arising from ion Implantation damage (14-20]. The effective diffusion coefficient for the preamorphized sample is estimated to 14 2 be 1.5x10cm /s, which is substantially smaller than that for the nonpreamorphized sample and is slightly larger than the intrinsic value. Thus, enhanced diffusion arising from ion implantation damage is suppressed for the preamorphized sample [20-22]. Figure 5 compares the annealed profile of a preamorphized sample with a nonpreamorphized sample. The solid curve shows the preamorphized sample, and the dashed curve the nonpreamorphized sample. It can be seen that an extremely shallow boron-doped layer is formed using preamorphization compared with the nonpreamorphized one. The extremely shallow boron-doped layer is made possible by suppressing transient enhanced diffusion arising from implantation damage in the annealing as well as suppressing the channeling tails in the ion implantation by preamorphization.
MOS capacitor characteristics To clarify the influence of channel preamorphization on MOS devices, characteristics of MOS capacitors fabricated in preamorphized and rapid thermal annealed Si substrates were investigated. CZ, n-type (100) Si wafers with l-Qcm resistivity were used. Phosphorus 16 3 concentration around the surface was adjusted to 8x10 cm- by phosphorus ion implantation and high-temperature drive-in diffusion. After growing 300-A oxide in dry 02 ambient, preamorphization was performed by Si ion implantation. The wafers were rapid thermal annealed at 950"C for 16 s in N2 ambient, and the 300-4 oxide was etched off followed by gate oxidation in dry 02 ambient to grow 200-4 gate oxide. Depositing Al as the gate material, Al gate MOS capacitors were fabricated using photolithography. Finally, the wafers were annealed in forming gas at 400"C. Figure 6 shows high-frequency C-V characteristics for a preamorphized capacitor. It is apparent from the figure that the preamorphized capacitor has normal C-V characteristics. The flat band voltage was the same as that for a nonpreamorphized capacitor. These results indicate that preamorphization can be used for channel doping without causing any unexpected threshold voltage shift. Pulsed C-V characteristics were measured to clarify the influence of the dislocation loops that are formed at the original a/c interface. In the pulsed C-V measurement, non-steady-state (i.e., deepdepletion C-V characteristics) are obtained. Figure 7 shows the pulsed C-V characteristics for the preamorphized and nonpreamorphized MOS capacitors. Figure 7(a) shows the preamorphized capacitor, and Fig. 7(b) the nonpreamorphized capacitor. The solid curves represent pulsed C-V characteristics, and the dashed curves represent the steady-state C-V characteristics. Depletion layer depth W is also shown. It can be seen that capacitance decreases until gate voltage reaches -7 V, beyond which point the capacitance becomes constant for the pulsed C-V characteristics of the
269
-r2
500
de
I0. C-)
,E
tox 200A z
500pmr0
2
z C-) 0
-1
0
3
V(V) DEPTH
(pm)
Fig. 5 Comparison of the annealed profile for a preamorphized sample (the solid curve) with that for a nonpreamorphized sample (the dashed curve) for channel doping.
Fig. 6 High-frequency (1-MHz) characteristics for preamorphized MOS capacitor.
• A^^
I000
1000 PREAMORPHrZED
0.1 100
02 0.3
C,
-
NON-PREAU0RPHM
0.1
I1_
a.
C-
0.2 0.3
100
C..)
-
PULSED
PULSED STEADY-STATE
STEADY-STATE In
I
In
1
-10
0
,
,
,
,
I
0
,
4
V MV)
V (V)
(b)
(a) Fig. 7 Pulsed C-V characteristics nonpreamorphized (b) MOS capacitors. shown.
I
-10
4
C-V a
for preamorphized (a) Depletion layer depth W is
270
and also
E
preamorphized capacitor. In the case of the nonpreamorphized capacitor, the capacitance decreases beyond -7 V. The depletion layer depth at which capacitance becomes constant is estimated to be 0.28 jMm. This value is nearly equal to the original amorphous layer depth. A plausible explanation for the results shown in Fig 7 is that when the dislocation loops near the original a/c interface come to be located in the depletion layer, the depletion layer does not extend any further, since a large number of minority carriers are generated with the dislocation loops acting as generation centers. From the results, it can be seen that the silicon layer shallower than the original a/c interface has good characteristics, although it has some problems beyond the interface. A C-t measurement revealed that minoritycarrier lifetime in the shallow region (roughly speaking, shallower than the original a/c interface) is the same as that for the nonpreamorphized sample. The surface-state density as a function of bandgap energy evaluated by quasistatic C-V measurement [23] is shown in Fig. 8. As shown in this figure, the surface-state density is sufficiently small for the preamorphized capacitor as well as for the nonpreamorphized capacitor. From these results, it is apparent that the preamorphization does not affect MOS capacitor characteristics so long as the a/c interface is sufficiently deep, which shows that channel preamorphization can be applied to channel doping in MOSFET fabrication. Application to HOSFET fabrication n÷ polysilicon gate MOSFET-s with a shallow boron counter-doped layer were fabricated using channel preamorphization. Shallow S/D junctions were
-
PRFAMORPF.ZED
ED 9" 'E
z
0
8E 'A
z
0
UI)
z
I C.B.
U.I
ENERGY (eV)
lZ
u.3
DEPTH (pm)
Fig. 8 Surface-state density as a function of bandgap energy.
Fig. 9 Net doping profile channel region.
271
in
the
Electron beam direct writing was used for also formed using preamorphization. all levels. Active regions were delineated by the conventional LOCOS process. Silicon ion implantation was performed through a 150-A temporary oxide to Rapid amorphize the surface followed by low-dose channel ion implantation. thermal annealing at 950°C for 15 s was done to activate implanted impurities. The net doping profile in the channel region of channel preamorphized MOSFET,s is shown in Fig. 9. Junction depth of the counter-doped layer is as shallow as 350 k. After etching off the temporary oxide, a 35-A gate oxide was grown Then, phosphorus-doped polysilicon was deposited in dry 02 ambient at 800"C. and subquarter-micrometer gate patterns were formed. Shallow S/D regions were The junction depth formed using preamorphization and RTA at 950*C for 15 s. of the S/D regions is as shallow as 800 A. Then, CVD Si02 was deposited followed by contact level lithography, and Al (2X Si) metallization was performed. Relatively deep (2000 A) p+ layers were formed in the S/D contact regions prior to metallization in order to prevent Al spiking. pMOSFETs with channel preamorphization have been successfully fabricated as shown in Fig. 10. Figure 10 shows the drain current IDS as a function of drain voltage VDS for a MOSFET with channel preamorphization. Gate length LG is 2 jum, and gate width is 20 /m. Threshold voltages are -0.60 V at VDS = 0.1 V and -0.52 V at VDS = -2 V. Threshold voltages for a MOSFET without channel preamorphization were -0.70 V at VDS = -0.1 V and -0.64 V at VDS = 2 V. The threshold voltages are lowered by about 0.1 V by channel preamorphization. This can be attributed to the shallower counter-doped boron profile of the channel-preamorphized MOSFET. Figure 11 compares the dependence of transconductance gm on VGS-VTH at VDS = -0.1 V for the channelpreamorphized MOSFET with that for the MOSFET without channel preamorphization, where VGS is gate voltage and VTH is threshold voltage. The solid curve is for the channel-preamorphized MOSFET, and the dashed curve for
WVU
-
,I'IIM.L rr.MUutMrIlJLW
U,
~50
Le -2 Pm Vos= -0.IV
0
-1.0
-2.0
VGS- VTH (V) Comparison of dependence Fig. 11 of transconductance gm on VGS-VTH at VDS = -0.1 V for a channelpreamorphized MOSFET with that for channel without MOSFET a Gate length is preamorphization. 2 pim.
Drain current as a Fig. 10 function of drain voltage for a channel with MOSFET Gate length is preamorphization. 2 gm, and gate width is 20 /pm. Gate voltages ranged from 0 to -2 V in 0 2-V inrmet
272
----------
-0.5
351 .1 X,-800A IO X
' IC. v=--. , Iv,."v
>0
SI N. oJ I
0
1.0
2.0
LG (PaM) Fig. 12 Dependence of threshold voltage on gate length. Open symbols are for channelpreamorphized MOSFETs, and solid symbols are for MOSFETs without channel preamorphization.
Fig. 13 Drain current as a function of drain voltage for a 0.2-.um gate-length MOSFET with channel preamorphization. Gate width is 20 /um. Gate voltages ranged from 0 to -2 V in 0.2-V increments.
the MOSFET without channel preamorphization. It can be seen that transconductance for the channel-preamorphized MOSFET is almost the same as that for the MOSFET without channel preamorphization. This result indicates that carrier mobility is not degraded by channel preamorphization. Figure 12 shows the dependence of threshold voltage on gate length for two different drain voltages, -0.1 and -2 V. Open symbols represent the channelpreamorphized MOSFETs, and solid symbols those without channel preamorphization. It is clear that short-channel effects are suppressed in the channel-preamorphized MOSFETs due to the shallower counter-doped boron profile compared with MOSFETs without channel preamorphization. Figure 13 shows the drain current as a function of drain voltage for a 0.2-Mum gatelength MOSFET with channel preamorphization. Figure 14 shows IDS-VGS characteristics for the 0.2-Mtm MOSFET at two different drain voltages, -0.1 and -2 V. As shown in these figures, 0.2-gum gate-length pMOSFETs with good subthreshold characteristics have been successfully fabricated by using channel preamorphization. Leakage characteristics of p+n junction diodes fabricated in the same channel-preamorphized substrates are shown in Fig. 15 along with those of a nonpreamorphized diode. The diode area is 100 gm x 100 Aim. Solid curves represent channel-preamorphized diodes, and the dashed curve represents a nonpreamorphized diode. Channel-preamorphized diodes with leakage characteristics as good as those without channel preamorphization were obtained as indicated by curve A. Not all channel-preamorphized diodes exhibited such good characteristics, however. Some diodes showed poor leakage characteristics as shown by curve B. This large leakage current probably
273
-
I0-8
---
CHANNEL- PREAMORPHIZED NONPREAMORPHIZED
8 10-9 I-
z
are
A
LU 10-11 1
Io-2
0
-1 -2 APPLIED VOLTAGE (V)
-
.6
VGS (V)
Fig. 15 Leakage characteristics of p~n junction diodes fabricated in channel-preamorphized (solid curves) and nonpreamorphized (dashed curve) substrates. Diode area is 100 pm x 100 pm.
Fig. 14 IDS-VGS characteristics for a 0.2-pm gate-length MOSFET with channel preamorphization.
derives from insufficient preamorphization depth and/or metal contamination during ion implantation for channel preamorphization. It is important, therefore, to make the preamorphization depth sufficiently deep and to eliminate metal contamination during ion implantation to suppress leakage current.
SUMMARY The channel preamorphization technique, a technique for forming shallow boron-doped layers for channel doping using preamorphization, was reviewed. Preamorphization does not affect MOS capacitor characteristics so long as the original a/c interface is sufficiently deep. Buried-channel pMOSFETs with a shallow boron counter-doped layer using channel preamorphization were successfully fabricated. It was shown that channel preamorphization does not degrade carrier mobility and improves MOSFET characteristics in the subquarter-micrometer gate-length region suppressing short-channel effects.
ACKNOWLEDGMENTS The author wishes to thank T. Sakai and T. Kobayashi for their advice and encouragement.
274
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[20] T. J. [21] S. in [22] S. 51, [23] M.
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0. Sedgwick, A. E. Michel, V. R. Deline, and S. A. Cohen, Appl. Phys., g3, 1452(1988) D. Brotherton, J. R. Ayres, J. B. Clegg, and B. J. Goldsmith, Mat. Res. Soc. Symp. Proc., 104, 161(1987) Solmi, R. Angelucci, F. Cambali, and M. Servidori, Appl. Phys. 331(1987) Kuhn, Solid-State Electron., 13, 873(1970)
275
Lett.,
OHMIC CONTACT FORMATION TO THE SHALLOW JUNCTIONS BY SELECTIVE TITANIUM SILICIDE CHEMICAL VAPOR DEPOSITION Kunio Saito, Takao Amazawa, and Yoshinobu Arita NTT LSI Laboratories Morinosato Wakamiya 3-1, Atsugi-shi, Kanagawa, 243-01 Japan
Selective titanium silicide chemical vapor deposition with an in-situ silane gas cleaning treatment and a silicon consumption control method are developed. The dependence of the source-gas flow rate on silicon consumption and film resistivity are clarified. Silicon consumption can be controlled by making a very small TiCI 4 /SiH 4 flow-rate ratio. By applying selective titanium silicide film to test devices with 0.1- /i m-deep shallow junctions, a low contact resistivity around 10-' • cm2 and a low junction leakage 2 current around 1011 A/mm are obtained.
INTRODUCTION Selective silicide chemical vapor deposition (CVD) is expected to be used in future deep submicron devices to reduce the contact resistivity of metal/silicon contacts or sheet resistance of silicon electrodes. Selective titanium silicide CVD has been studied by some researchers. [1, 21 However, difficult problems, such as the nucleation which resulted from the film growth started with islets and a large silicon substrate consumption, were unfortunately revealed. These problems have been studied further. V. Ulderem et al. reported deposition of a thin polysilicon layer prior to silicide deposition promoting the nucleation of titanium silicide. [3] D. Bensahel et al. reported titanium silicide deposition without silicon consumption using a TiCI 4 /SiH 4 system diluted in H2 and a fast-switching lamp system. [4] When a selective titanium silicide CVD process is applied to deep submicron devices with very shallow junctions, severe requirements such as both of small grains and small silicon consumption must be satisfied. We previously reported that the nucleation problem can be solved by using an in-situ SiH 4 gas cleaning treatment prior to titanium silicide deposition. The effect of the SiHl4 gas cleaning treatment on native oxide reduction was studied throughout the experiments; the nuclei density of titanium silicide were greatly increased by the cleaning treatment, and each silicon nuclei in-situ deposited on the silicon substrate after the cleaning 276
treatment grew epitaxially. [5, 6] This paper reports clear evidence of native oxide reduction by the in-situ SiH4 gas cleaning treatment. The paper also reports the silicon consumption depended on the ratio of the source-gas flow rate. Some electrical characteristics obtained from test devices with 0.1- 1rm-deep shallow junctions were also reported. EXPERIMENTS The silicon wafer was dipped in diluted HF and rinsed with pure water. Titanium silicide films were selectively deposited by the following process and conditions using the previously reported CVD apparatus [51 First, the in-situ SiH 4 gas cleaning treatment was performed at a temperature of about 720r- with a SiH4 gas flow rate of 10 SCCM and pressure of 0.5 mTorr. Sequentially, titanium silicide film was selectively deposited at a temperature of 720-7401C with a SiH 4 gas flow rate of 50 SCCM, partial SiH4 gas pressure of 19 mTorr, and TiCl 4 gas flow rate of 0.05-0.3 SCCM. The effect of the in-situ SiH4 gas cleaning treatment was confirmed using in-situ silicon deposition with a large deposition rate and depth profile measurement by secondary ion mass spectroscopy (SIMS) analysis. The quantity of silicon consumption was measured using a cross-sectional view of a scanning electron microscope (SEM). Titanium silicide film deposited under optimum condition was observed by a transmission electron microscope (TEM). (100) oriented p-type and n-type 1-10 0 - cm silicon wafers were used to obtain electrical characteristics. The device areas were isolated by oxide film formed by the LOCOS process. Shallow n/p junctions were formed by a low-energy As implant of 4 X 1015 cm-' dose. Shallow p7/n junctions were formed by a two-step implant including a low-energy silicon implant to preamorphize the silicon substrate and a low-energy BF2 implant of 2 X 10 1 5cm- 2 dose. [7] The wafers were annealed by a rapid thermal-annealing system. Both the n'/p and p÷/n junctions were formed about 0.1 /Am in depth. TiN film for barriers and AI(Cu) film for electrodes were sputtered and patterned. The contact resistances were measured using Kelvin resistors. RESULTS & DISCUSSION Effect of the in-situ Sil. gas cleaning treatment Wafers of p-type (100) silicon were cleaned by a modified RCA washing treatment Two types of wafers were prepared for this experiment. One was made through eliminating native oxide by dipping the wafers in diluted HF and rinsing them in pure water for 2 hours (specimen A). The other was made 277
through oxidization by dipping in diluted H2 0 2 after eliminating native oxide with diluted HF (specimen B). In-situ silicon film deposition was performed after the SiHl4 gas cleaning treatment to maintain the native oxide in the deposited silicon / substrate silicon interface. The in-situ SiH 4 gas cleaning treatment and in-situ silicon deposition were performed under the conditions shown in Table 1 and 2, respectively. Figure l(a) and (b) show the depth profiles of oxygen and carbon concentrations in the deposited silicon / substrate silicon structures; (a) and (b) show the profiles of specimens A and B, respectively, with and without the SiH4 gas cleaning treatment. It is clear from Fig. 1 that the native oxide is reduced by the SiH 4 gas cleaning treatment. The reduction of native oxide in specimen B is more effective than that in specimen A. The carbon is not reduced very much by the cleaning treatment. We think the two peaks of the carbon profile in Fig. l(b) were caused in the SIMS measurement by the surface roughness of the deposited silicon which originated from incomplete epitaxy. Considering the above results and the phenomena of titanium silicide deposition with and without the in-situ SiHl4 gas cleaning treatment, [5, 6] the oxygen on silicon has a strong influence on the titanium suicide growth when a TiCI 4 /SiH 4 gas system is used. conversely, it is clear that the carbon on silicon does not strongly influence the titanium silicide growth.
Table 1. The conditions of the in-situ SiH4 gas cleaning treatment Wafer temperature Sill,, gas flow rate SiH4 gas pressure Treatment time
about 750'C 10 SCCM 0.5 mTorr 1.5 min for specimen A 12.5 min for specimen B
Table 2. The conditions of the silicon deposition Wafer temperature : about 750rC SiH 4 gas flow rate : 20 SCCM Sill4 gas pressure 65 mTorr Deposition time L5 min Film thickness 0.35-0.4 /Lm
278
U 02 Go
0
z 02
z U z 0W
0 15 30 SPUTTERING TIME (min)
0 15 30 SPUTTERING TIME (min)
(a) Rinsed in pure water.
(b) Oxidized in diluted H.0 2 .
Fig. L Depth profiles of oxygen and carbon concentrations in the deposited silicon / substrate silicon structures with and without the in-situ Sil-14 gas cleaning treatment. The substrate silicon surfaces were rinsed in pure water for 2 hr (a) or oxidized in diluted H0a 5 (b). Specimens were sputtered about 0.5 ILm in depth for 30 min.
Si consumption The silicon substrate consumption was successfully controlled by a very small ratio of the TiCl/SiH4 gas flow rate. Figure 2 shows the TiCl 4 gas flow rate dependence of the titanium suicide film resistivity and the consumed silicon depth expressed as a percentage of the titanium silicide film thickness. The titanium silicide films grew with full selectivity under the conditions for the TiCl. gas flow rate over 0.05 SCCM at least. As seen in Fig. 2, the silicon consumption decreases with a decrease in the TiCl 4 gas flow rate, but the film resistivity increases. In contrast, the film resistivity becomes closer to the bulk value for increasing TiCl4 gas flow rate, but the silicon consumption simply increases. Using X-ray diffraction analysis, the C54 type of TiSi. was observed for a TiClI gas flow rate of 0.1-0.3 SCCM, and a mixture of C54 TiSi2 and 279
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S1001a720-740r
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"'
50 SCCM
Mo WZý
"-50aU
so-
'-1500
0
0.1
0.2
0.3
0
(SCCM) TiCI 4 GAS FLOW RATE
Fig. 2. The TiC14 gas flow rate dependence of titanium silicide film resistivity and the consumed silicon depth expressed as a percentage of the titanium silicide film thickness.
Ti5 Si 3 for a TiC14 gas flow rate below about 0.1 SCCM. Supposing that only titanium is supplied to the silicon substrate to make C54 type TiSi2 , the consumed silicon depth is calculated to about 90% of the titanium silicide film thickness. A relatively small silicon consumption shown in Fig. 2 indicates that part of the Si in the titanium silicide was supplied from the gas phase. A larger silicon consumption than about 90% means that the substrate silicon was consumed to make titanium suicide, and part of the substrate silicon evaporated with a byproduct form through the titanium silicide film. TEM observation of the titanium suicide film Figure 3 shows a cross-sectional TEM photograph of titanium silicide film deposited under the optimum conditions of which the consumed silicon depth corresponds to about 50% of the titanium sUicide film thickness. The film consists of small-size grains less than about 800 A along the silicon surface and less than about 400 A in the perpendicular direction. The film penetrates the underlying silicon to about 200 A in maximum depth. The titanium silicide grows with a nucleus form, as seen in Fig. 3. Considering the cause of the growth feature, a small quantity of oxygen or carbon remaining after the in-situ SiM4 gas cleaning treatment on the silicon substrate, as shown in Fig. 1, has the possibility to prevent uniform growth of titanium silicide. Another possibility for the nucleation is a high process temperature. 280
i Titanium silicide
I
0 0 0
Silicon substrate
Fig. 3. A cross-sectional TEM photograph of titanium silicide film deposited under the optimum conditions.
Selective titanium silicide film deposition in a deep submicron contact hole Figure 4 shows an SEM photograph of selectively deposited titanium silicide film on the bottom of a 0.2-g m-diameter contact hole which has an
Fig. 4. An SEM photograph of selectively deposited titanium silicide film on the bottom of a 0.2- I m-diameter contact hole (aspect ratio = 2.5). 281
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Fig. 5. The contact resistance as a function of contact hole size.
I
V
as depo. 400 450 500
ANNEALING TEMPERATURE (C)
Fig. 6. The contact resistance as a function of annealing temperature.
aspect ratio of 2.5. Using the selective CVD method, we can easily form titanium silicide film on the bottom of a deep submicron contact hole. Contact resistivity A selective titanium silicide film was deposited on the 0.1- IL m-deep shallow junctions under the optimum conditions. Figure 5 shows the contact resistance for n' and p÷ silicon as a function of contact hole size. The contact resistivities for n- and p' silicon are about 2 X 10-' and 6 X 10' Q - cm', respectively. Annealing caused little change in the contact resistance at 400-500r,, as shown in Fig. 6. In this experiment, optimization of impurity concentration at the titanium silicide / silicon interface was not performed. Thus, we think a lower contact resistivity might be obtained by the optimization. Junction leakage current for the shallow junctions Figure 7 shows the junction leakage currents for 0.1- IL m-deep shallow junctions as a function of annealing temperature. The device used in this measurement was on the same wafer with Kelvin resistors. The junction areas were 0.03 mm2 for the n÷/p junction and 0.2 mm" for the p÷/n junction. The contact areas were about half of the junction areas. The leakage currents of both the n-/p and p÷/n junctions are in the
282
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order of 10' A/mm 2 and were slightly changed by 400-500U annealing. This result shows that the selective titanium silicide CVD method can be used for ohmic contact formation to shallow junctions. CONCLUSION Clear evidence of the native oxide reduction by the in-situ SiH4 gas cleaning treatment was presented using in-situ silicon deposition and a depth profile measurement of SIMS. The silicon substrate consumption was successfully controlled to a relatively small value by a very small TiCI4 /SiH 4 flow-rate ratio that ranged from 0.001 to 0.005 when the SiH 4 gas flow was 50 SCCM at 720-740rC. The selective titanium silicide film deposited under optimum conditions was applied to test devices with 0.1- g m-deep shallow junctions. A low contact resistivity around 10' 0 • cm2 and a low junction leakage current around 10-" A/mm2 were obtained. The values were low enough to apply the selective titanium silicide film to devices with very shallow junctions.
283
ACKNOWLEDGEMENT We would like to thank Dr. T. Sakai for his encouragement throughout this work.
[1] A. 2080. [2) G. [3) V. [4] D.
REFERENCES Bouteville, A. Royer, and J. C. Remy: J. Electrochem. Soc. 134 (1987)
J. Reynolds, C. B. Cooper, and P. J. Gaczi, J. AppL Phys. 65 (1989) 3212. Ilderem and R. Reif: Appl. Phys. Lett. 53 (1988) 687. Bensahel and J. L. Regolini: Appl. Phys. Lett. 55 (1989) 1549. [5] K. Saito, T. Amazawa, and Y. Arita: Extended Abstracts of the 21st Conference on Solid State Devices and Materials, Tokyo (1989) 541. [6] K. Saito, T. Amazawa, and Y. Arita: Jap. J. Apple. Phys. 29 (1990) L185. M7l M. Miyake, S. Aoyama, S. Hirota, and T. Kobayashi: I. Electrochem. Soc. 135 (1988) 2872.
284
DEFECT ANNEALING IN ULTRA-SHALLOW JUNCTIONS FOR SCALED SUB-MICRON CMOS TECHNOLOGY S. Chevacharoenkul1, C.M. Osburnl, 2 , G.E. McGuire 1 1 MCNC, Center for Microelectronics P.O. Box 12889, Research Triangle Park, NC 27709 2 Department of Electrical and Computer Engineering North Carolina State University, Raleigh, NC 27695 Defect annealing in preamorphized and non-preamorphized Si substrates that have been implanted with low energy ions (Ge, Si, As, BF2) were examined as a function of 10 second rapid thermal annealing temperature (650-1050 °C) using transmission electron microscopy. The energy and dose of implantation were selected in accordance with a scaling rule based on minimization of the short channel effect. Such energies and doses result in the formation of amorphous layers which extend to the surface. It was found that lower annealing temperatures are required to remove the ion implantation damage when the junction depths are shallower. Factors affecting the damage removal were determined to be both the integrated recoils beyond the amorphous/crystalline (a/c) interface and the proximity of the a/c interface to the free surface. As the junction becomes deeper a higher temperature is needed to provide more vacancies for recombination with the interstitials dissolving from the loops. INTRODUCTION Ion channeling leading to a deeper-than-anticipated junction is a well known phenomenon in junction formation by ion implantation. Preamorphization of the Si surface with electrically non-active species such as Si, Ge and Sn was proposed to eliminate the channeling of the dopant [1-5]. However, the formation of end-of-range defects resulting from point defect agglomeration during the dopant activation can lead to high leakage current [6]. Their size- and spatial distributions were shown to depend on annealing temperature, as well as on the ion-energy and dose of implantation [7]. In general, defect annealing involves dissolution and recombination of interstitials and vacancies whose concentrations and diffusivities increase exponentially with temperature. Defect annealing is, therefore, expected to influence the kinetics of dopant diffusion which in turn determines the junction depth. It was the objective of this study to understand the relationship between the point defect production, annealing temperature, dopant diffusion and defect annealing in the formation of ultra-shallow junctions. EXPERIMENTAL PROCEDURE Details of the experimental procedure can be found in a companion article [8]. Only a summary is given here. Both p- and n-type Si (100) -10 ohm-cm substrates were RCA285
cleaned, and their top halves were masked with 1.5 micron thick photoresist films. Preamorphization of the lower halves with Ge or Si was done in a Varian 350 D Ion Implanter at 7 degree tilt. The photoresist films were later stripped by wet etching and the entire wafers were ion-implanted with As or BF2. Solid-phase epitaxial (SPE) regrowth of the amorphous region was accomplished by annealing at 450WC and 5500 C for 30 min each. Rapid thermal annealing (RTA) to electrically activate the dopants was done for each wafer at 650, 750, 850, 950 or 1050'C for 10 sec. After electrical measurements, wafers were divided for TEM and SIMS analyses. Both planar and cross-sectional views of each sample were studied in a transmission electron microscope operated at 300 kV. SIMS profiling conditions were optimized to ensure the minimum knock-on mixing.The complete SIMS results for the dopant profiles, as-implanted and after RTA, are given in the companion paper mentioned above. Table I. Process Description Technology
I12
Xj (nm):
200
Lkm
1/4 tim
150
70
40/5x10 14 30/5x 1014 20/2x10 15 10/5x1014
25/4x1014 20/4x 1014 15/1.5x10 1 5 8/4x10 14
450/30 550/30 1000/10
450/30 550/30 950/10
2
Ion: energy/ dose ( keV/cm- ) 85/lx10 15 Ge Si 50/5x1015 As 44/lx10 15 BF2 Annealing : temperature/time SPE (°C/min) 550/30 RTA (°C/see)
1050/10
RESULTS AND DISCUSSION Amorphization Depth Room temperature implantations using the conditions listed in Table I produce uniform amorphous layers to the depths shown in Table II. As seen in Fig. 1, the amorphous/crystalline (a/c) interface was abrupt. The amorphization depths obtained in this study were plotted along with those reported in the literature [9-25] in Fig. 2 A-C. The depth of the amorphous layer in nm produced by Si or Ge or As implants into Si substrate can be fitted to the equations : Da/c (Si)
=
6.22 + 2.05E + (1.76x10- 3 )E2 ,
and Do/c (Ge or As)
=
1.3E
286
E a 20
where E is the implant energy in keV. The amorphization depths obtained in our study are slightly less than those reported by others. Possibly the combination of room temperature implantation and the use of medium currents can induce substantial dynamical annealing. It should be noted that although data in the plots were not confined to one dose and that the use of a higher dose results in a larger depth of amorphization [7], the data do not appear to scatter significantly from the line given above. Table II. Amorphous Layer Thickness
ion
Ge Ge Ge Si Si As As As BF2 BF2 BF2
implantation conditions dose current (cm-2 ) 0iA) (keV)
a/c interface depth
energy
25 40 85 20 30 15 40 50 8 10 44.4
14
4x10 5x1014
lxi015 14
4x10 5x1014 1.5x1015 15
4x10 5x1015 14 4x10 5x10
14
lx1015
40 50 55 70 60 40 100 125 16 25 47
(nm) 34 50 98 32 43 26 62 75 11 14 38
Fig. 1. XTEM micrographs of (100) Si substrates implanted with (A) Ge,(B) Si, (C) As and (D) BF2 showing the amorphous layer thickness, uniform amorphization within the layer, and abrupt amorphous/crystalline interface.
287
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A
0
0 50 100 150 200 250 Implantation Energy (keV)
400
• 300
S250,
S150
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100 200 300 400 500
Fig. 2. Plots of the amorphous layer thickness as a function of energy for A) Ge, B) Si and C) As implants into (100) Si, including data from ref. [9-25].
Ua
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Implantation Energy (keV)
C
* this work * Prussin et al * Cerva&Kuster * Horiuchi et al 1 Narayan et al a Kown&Lee
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Damage Removal Damage removal which occurs during 10 second rapid thermal annealing at various temperatures in scaled Ge-preamorphized junctions (25 keV, 4x10 14 Ge) is shown in Fig.
3.During the SPE anneal at 550 TC for 30 minutes, the implantation damage which consists
of interstitials and vacancies interacts through the processes of annihilation and
agglomeration to form a band of many small interstitial loops at the amorphous/crystalline interface. The material above the boundary appears defect-free. However, one study [26] reported that this layer is vacancy-rich. Below the a/c interface the vacancies produced by implantation either recombine with interstitials, diffuse to the surface, recombine with other vacancies or remain as free vacancies. The existence of vacancies both above and below the ion-implanted Si before and after a low temperature annealing was detected using a positron annihilation technique [27]. Rapid thermal annealing up to 750 'C did not result in significant change in the defect structure formed during SPE regrowth. However, significant removal of the damage occurred at 850 0 C. The interstitial loops which survived at this temperature grew in size indicating these were loops with radii larger than a critical radius below which complete dissolution of loops occurred during the 10 second of anneal. A flux of atoms from the dissolved loops recombined with the undissolved loops and
caused them to grow. After 10 seconds 950 'C or 1050 'C, damage removal was almost complete and complete, respectively. Plan-view TEM micrographs of residual damage in the Ge preamorphized junctions after 10 second annealing at 1050 °C, 1000 'C or 950 'C for 85 keV, 40 keV, and 25 keV Ge, respectively, are shown in Fig. 4. Two important findings are seen in Fig. 4. First, as the implant energy increases, both the depth and areal loop density of defects increase. Second, higher annealing temperatures are required to remove all the defects produced by higher implantation energies. This later phenomena is presumeably a result of the greater damage depth from the surface which might act as a vacancy source or interstitial sink and/or greater damage density. This finding is also true for the non- Ge preamorphized Asimplant and BF2-implant junctions shown in Figures 5 and 6, respectively. A computer souce code : TRIM. CAS [28], which is a 3-dimensional Fortran Monte-Carlo program with cascades, was employed to calculate the ion ranges and Frenkel-pair defect production for the 85, 40 and 25 keV Ge implants as well as for a 20 keV Si implant into Si substrate. Ten thousand incident ions were used to compute distributions of interstitials and vacancies assuming a displacement energy of 15 eV. Fig. 7 shows the results. The distributions were normalized to the doses employed here (Table I). While the three implant conditions produce nearly the same Ge peak height of 1.5x1020 cm3, the peak heights of the interstitials are not the same. It should be added that the distributions of the vacancies are almost identical to those of the interstitials and that the concentration of interstitials at the a/c interface is about 1.7x10 22 cm- 3 for room temperature implants. The interstitials (damage) which must be removed during annealing can be estimated by integrating the area under the curve from the amorphization depth to the tail which is given in Table III. The implantation condition for the one micron technology produces 2.44 and 2.98 times more interstitials than those of the one-half and one-quarter micron technology, respectively. However, since damage removal involves diffusion of these interstitials and/or creation of vacancies, it is informative to examine the diffusivity of
289
Fig. 3. XTEM of Ge-preamorphized Si after 550 *C SPE regmwth (A). Plan-view TEM's after RTA at B) 750 OC, C) 850 OC, and D) 950 OC.
Fig. 4. Plan-view TEM's of Ge preamorphized Si after 10 sec RTA. A) 1050 *C (85 keV/lxlO05 cm' 2 ); B) 1000 0 C (40 keV/5xl0 14 cm-2 ); C) 950 OC (25 keV/4xl0 14 cnr 2 ).
290
Fig. 5. Plan-view TEM's of non-Ge preamorphized Arsenic implanted Si after 10 sec 0 2 0 RTA. A) 1050 0C (50 keV/5xl0 5 cm-2 ); B) 1000 C (25 keV2xl015 cm- ); C) 950 C (15 keV/1.5 keV/10 15 cm-2).
Si after 10 sec RTA at Fig. 6. Plan-view TEMs of non-Ge preamorphized BF2 implanted 2 14 2 A) 1050 TC (44.4 keV/1xl015 cm- ), B) 1000 *C (10 keV/5xl0 cmn ), and C) 950 'C (8 keV/4x 1014 cm-2).
291
Si at the three annealing temperatures as a measure of the concentration and mobility of the defects. The Si diffusivities at 950, 1000 and 1050 'C are 4.1x10- 18, 3.2x10- 17 and 1.8x1016 cm 2 /s , respectively [29], i.e., Si diffuses 5.6 and 44 times faster at 1050 "C than at 1000 'C and 950 'C, respectively. The differences in the integrated recoils among the three implants, i.e. only 2.44x and 2.89x, seem insignificant in comparision to the large differences in the diffusivity. From a diffusion view-point, annealing the 85 keV Ge implanted Si at 1050 'C should result in a damage-free junction, but experimental data indicate otherwise.This result leads to the conclusion that the total number of recoiled atoms beyond the a/c interface does not fully explain the damage removal behavior in the scaled junctions. Table IIn. Integrated Interstitials Beyond the a/c Interface for Ge implants Energy/dose (keV/cm-2 )
Interstitials (cm-2 )
85/ 1xl0 15 40/5x101 4 25/4x10 14
3.16x10 1.29x10 1.06x10
16 16 16
Another parameter which can affect damage removal is surface proximity of the a/c interface. The surface proximity effect on the damage removal was studied in two experiments. In the first, the amorphous depths were nearly equal but the integrated recoils were different ( Fig. 7b). In the second experiment , the integrated recoils were the same but the amorphous depths were different. Shown in Fig. 8 are plan-view TEM micrographs of Ge (25 keV/4xl014 cm-2) and Si (20 keV/4x 1014 cm- 2 ) preamorphized junctions which were annealed at 950 'C for 10 seconds. These two junctions had only a 2 nm difference in the amorphizartion depth (32 nm for Si versus 34 nm for Ge). It is seen that the remaining damage is very different for the two implants, i.e., nearly complete for the Gepreamorphization but considerable residual for Si implantation. This experiment indicates that equal proximity to the free surface does not produce equal damage removal. In the second experiment, a Si substrate was implanted with Ge at 85 keV and lx10 15 cm-2 dose and then 38 nm of the amorphized layer was etched away before performing an identical SPE and RTA anneal. The residual damage in the two samples is shown in Fig. 9. The loop size in the two micrographs is about the same but the areal density changes from 2.5x109 cm- 2 to 4.7x109 cm-2 in the etched and unetched samples, respectively. Moving the a/c interface 40 % closer to the surface results in a 47 % reduction in the residual damage. The enhanced damage removal induced by the reduction of a/c interface found here is in agreement with the work of Thornton and Hill [30] but in contradiction with that of Ganin and Marwick [31]. CONCLUSIONS In this study scaled shallow junctions were found to require lower annealing temperatures to remove the damage. This phenomenon is partially explained by the fact that fewer interstitial atoms are produced below the a/c interface when the ion -implantation energy is lower. For different implants possessing the same depth of amorphization, 292
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120
Fig. 7. TRIM concentration-depth profiles: A) interstitials (i) and germanium (g) for 25, 40 and 85 keV Ge implants; B) interstitials (i), 25 keV germanium (g) and 20 keV silicon (s). Hatched areas represent integrated recoils beyond amorphous/crystalline interface.
at 950 0 C. Fig. 8. Plan-view TEM of Ge (A) and Si (B) preamorphized Si after 10 sec RTA depth of identical The implant energies (25 keV Ge and 20 keV Si) were chosen to give amorphization. 293
damage removal depends on the number of interstitial atoms below the a/c interface. However, the numbers of interstitials alone could not completely explain the damage removal behavior. Etch-back experiments show that reducing the a/c interface depth results in an accelerated damage removal which leads to the conclusion that surface proximity also plays an important role in the removal of damage caused by ion implantation.
Fig. 9. Plan view TEM's of damage removal in 85 keV Ge implanted silicon after 10 sec at 1050 'C RTA: A) 38 nm of substrate removed by chemical etching prior to RTA; B) no etching ACKNOWLEDGMENTS The authors wish to express their appreciation to the following persons who have made contributions to this work : R. Chapman, R. Fair, J. J. Lee, M. Ma, M. Ray R.Stokell and T. Tan. They would also like to thank the staff of the MCNC Silicon Processing Facility for the sample preparation. REFERENCES [1] M. Y. Tsai and B. G. Streetman, J. Appl. Phys. 50, 183 (1979). [2] T.E. Seidel, IEEE Electron Device Lett. EDL-4, 353 (1983). [3] D. K. Sadana, W. Mazsara, J. J. Wortman, G. A. Rozgonyi, and W. K. Chu, J. Electrochem. Soc., 131, 934 (1984).
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[4] M.C. Ozturk, J.J. Wortman, C.M. Osburn, A. Ajmera, G. A. Rozgonyi, E. Frey, W.K. Chu, and C. Lee, IEEE Trans. Electron Devices, 35, 659 (1988). [5] S. D. Brotherton, J. R. Ayres, J.B. Clegg and J. P. Gower, J. Electronic Materials, 18, 173 (1989). [61 M. Miyake, S. Aoyarna, S. Hirota, and T. Kobayachi, J. Electrochem. Soc. 135, 2872 (1988). [7] K. S. Jones, and D. Venables, J. Apple. Phys. 69, 2931 (1991). [8] C. M. Osburn, S. Chevacharoenkul, and G. E. McGuire, in 1991 ULSI Science and Technology, J. M. Andrews and G. Celler, eds. Electrochem. Soc., 1991. [9] S. D. Brotherton, J. R. Ayres, J.B. Clegg and J. P. Gower, J. Electronic Materials, 18, 173 (1989). [10] S. Prussin and K. S. Jones, J. Elctrochem. Soc., 137, 1912 (1990). [11] M.C. Ozturk, J.J. Wortman, C.M. Osburn, A. Ajmera, G. A. Rozgonyi, E. Frey, W.K. Chu, and C. Lee, IEEE Trans. Electron Devices, 35, 659 (1988). [12] C. P. Wu, J. T. Mcginn, and L. R. Hewitt, J. Electronics Materials, 18, 721 (1989). [13] E. Myers, G. A. Rozgonyi, D. K. Sadana, J. J. Wortnan, and J. Narayan, in Rapid Thermal Processing,T. 0. Sedgwick, T. E. Seidel, B. -Y. Tsaur, eds., Mat. Res. Soc.Symp. Proc., 52, 107 (1986). [14] A. C. Ajmnera and G. A. Rozgonyi, Appl. Phys. Lett., 49, 1269 (1986). [15] M. Miyake, S. Aoyamna, S. Hirota, and T. Kobayachi, J. Electrochem. Soc. 135, 2872 (1988). [16] A. Tanaka, T. Yamnachi, A. Uchiyama, T. Iwabuchi, and S. Nishikawa, IEDM, 32, 785 (1989). [17] D. Brotherton, J. P. Gowers, N. D. Young, J. B. Clegg, and J. R. Ayres, J. Appl. Phys., 60, 3567 (1986). [18] D. M. Maher, R.V. Knoll, M.B. Ellington and D.C. Jacobson, in Rapid Thermal Processing,T. 0. Sedgewick, T. E. Seidel, B. -Y. Tsaur, eds., Mat. Res. Soc.Symp. Proc., 52, 94 (1986). [19] C. P. Wu, J. T. Mcginn, and L. R. Hewitt, J. Electronics Materials, 18, 721 (1989) [20] G. A. Ruggles, S. Hong, J. J. Wortman, M. C. Ozturk, E. R. Myers, L J. Hren, and R. F. Fair, in Processingand Characterizationof MaterialsUsing Ion Beams, L. E. Rehn, Greene, F. A. Smidt, eds., Mat. Res. Soc. Syrup. Proc., 128, 611 (1989). [21] S. Prussin, D. I. Margolese, and R. N. Tauber, J. Apple. Phys. 57, 180 (1985). [22] H. Cerva and K. -H. Kusters, J. Appl. Phys., 66, 4723 (1989). [23] M. Horiuchi, M.Tamura, and S. Aoki, J. Appl. Phys.,65, 2238 (1989). [24] J. Narayan and J. Fletcher, in Defects in Semiconductor, J. Narayan and T. Y. Tan, eds., Mat. Res. Soc. Symp. Proc., 2, 191 (1981). [251 S. J. Kown and J. D. Lee, J. Electrochem. Soc., 138, 867 (1991). [26] S. Solomi, R. Angelucci, F. Cembali, and M. Serviori, Appl. Phys. Lett. 51, 331 (1987). [27] P. Hautojarvi, P. Huttunen, J. Makinen, E. Punkka and A. Vehanen, in Defects in ElectronicMaterials,M. Stavola, S.J. Pearton and G. Davies, eds., Mat. Res. Soc. Syrup. Proc., 104, (1987). [28] J. P. Biersack and L. G. Haggrmark, Nucl. Instrum. Methods, 174, 257 (1980). [29] R. B. Fair, in Impurity Doping Processes in Silicon, F. F. F. Wang, ed., NorthHolland, New York, 1991. [30] J. Thornton and C. Hill, Semiconduct. Sci. Technol., 4, 53 (1989). [31] E. Ganin and A. Marwick, in Ion Beam ProcessingOf Advanced ElectronicMaterials, N. W. Cheung, A. D. Marwick, and J. B. Roberto, eds., Mat. Res. Soc. Symp. Proc., 147, 13 (1989).
295
ULTRA-SHALLOW JUNCTION FORMATION BY DIFFUSION FROM POLYCRYSTALLINE SixGel-x ALLOYS D.T. Grider, M.C. Oztiirk, and J.J. Wortman Department of Electrical and Computer Engineering North Carolina State University Raleigh, North Carolina 27695 ABSTRACT Selectively deposited, implanted polycrystalline SixGel-x has been investigated as a potential diffusion source for boron in the formation of ultra-shallow p÷-n junctions in silicon. Polycrystalline SixGel-x can be deposited on Si selectively with no deposition occuring on Si0 2 . In addition, the alloys exhibit a different etch chemistry than silicon so that if desired, SixGel-x may be selectively removed following dopant drive-in, making this technique directly comparable to ion-implantation without introducing substrate damage in Si. The alloys used in this study were deposited selectively on Si in a rapid thermal processor using dichlorosilane and germane as the reactant gases. After deposition, the alloys were doped with boron using ion-implantation and then annealed in a rapid thermal processor to diffuse boron into silicon. Shallow junctions were obtained with high peak surface concentrations and steeply sloped dopant profiles. Forward bias I-V and reverse bias I-V and I-1/T measurements indicated low leakage current densities and good ideality factors. I. INTRODUCTION Scaling trends continue to drive feature sizes of MOS devices smaller and smaller. Considerable effort has been directed to the issue of scaling vertical junction depths to keep pace with decreasing line widths [1 - 4]. Of all the existing techniques to form shallow junctions, low energy ion-implantation continues to be the most commonly used method to form these junctions today. In practice, shallow p+-n junctions are typically much more difficult to obtain than n÷-p junctions because of the channeling of boron during implantation, causing a spreading of the as-implanted profile. Several methods have been used to circumvent this problem, including implantation of BF2 [2], preamorphization with heavy ions such as Si or Ge [5]. During ion-implantation, damage is introduced in the silicon substrate which must be annealed out or, at a minimum, be kept out of the vicinity of the junction depletion region [5]. The removal of this implantation damage becomes more difficult as more stringent demands are placed on thermal budgets to maintain shallow dopant profiles. Using solid diffusion sources appears to be another viable technique to form shallow junctions in silicon. Polycrystalline silicon has been extensively studied for this purpose [6 - 8]. The technique offers rapid dopant diffusion in polycrystalline silicon through the grain boundaries so that the material acts as a constant dose diffusion source and prevents
296
substrate damage during ion-implantation. A disadvantage of the technique is that it is difficult to deposit polycrystalline silicon selectively with no deposition occuring on SiO 2 . In this paper we present results on an alternative diffusion source. We have used selectively deposited polycrystalline Si.Gel-x alloys doped using boron ion-implantation as a diffusion source to form ultra-shallow p+-n junctions in silicon. As with polycrystalline silicon, the SixGel-x alloys have rapid boron diffusion along grain boundaries so that the dopant quickly reaches the silicon surface. The advantages of polycrystalline SixGe1-x over polycrystalline Si are in the processing flexibilities SixGel-x offers in forming the junctions. We have shown previously that selective deposition of these films is much easier than that of silicon due to the formation of highly volatile GeO [9]. In addition, Cams, et.al. have shown that SixGel-x alloys have different etch properties than silicon [10]. This means that following junction formation, the diffusion source may be selectively removed making the process directly comparable to ion-implantation without introducing substrate damage in Si. In this work, we have studied the electrical properties of boron doped p+-n junctions formed by diffusion of boron into Si from selectively deposited and implanted polycrystalline SixGel-x alloys. Secondary ion-mass 'spectroscopy (SIMS) has been utilized to obtain as-implanted and annealed boron profiles in Si and SixGel-x. II. EXPERIMENTAL Ultra-shallow p+-n diodes were fabricated on Czochralski grown 0.2-0.45 Q-cm <100> silicon substrates and used to characterize the properties of the diffused junctions. A 3500 A thermal oxide was grown and patterned using conventional photolithography to define the active areas for the diodes. Selective SixGel-x alloys were deposited on the wafers in the active areas to a thickness of 2000 A using a cold-wall, lamp heated rapid thermal processor. A fixed Ge concentration of 30 % (SiO. 7Geo.3) was used in this study. The deposition conditions were optimized to obtain a smooth two-dimensional growth of Si 0 .7 GeO. 3 on Si. The details of the optimization procedures can be found elsewhere [ 11]. For comparison, monitors were fabricated without selective Sio.7GeO. 3 deposition in the active areas. To eliminate boron channeling in Si, the monitor wafers were preamorphized with Ge ions [5]. Boron implantation into SiO.7GeO. 3 was carried out at 10 keV with varying implant doses. For these samples , the implantation energy and dose were chosen to keep the as-implanted profile confined to the polycrystalline layer. A thin oxide was then deposited on all the samples at 450'C followed by rapid thermal annealing in a HeatpulseTM rapid thermal annealer at temperatures between 1000*C and 1100'C. Aluminum was evaporated and patterned on all the wafers. This was followed by a forming gas anneal at 400'C to complete the fabrication process. Samples were also prepared by depositing SixGel-x alloys on bare silicon wafers to monitor the diffused boron profiles by SIMS. III. RESULTS Dopant Profiles Anneal temperature, anneal time, and implant dose all contribute to determining dopant profiles and junction depths during diffusion. The effects of all of these parameters on boron diffusion into silicon from SiO.TGeO.3 has been investigated. Boron implant doses of
297
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Anneal Temperature (°C) Figure 2
Effective boron dose in silicon following RTA as a function of RTA temperature.
298
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Variation of Boron profiles with implant dose.
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Effective boron dose in silicon as a function of implant dose after a l0s,1 100°C RTA.
299
lxl0 15 cm-2 , 3x10 15 cm-2 , and lxl0 16 cm- 2 ; anneal temperatures of 1000TC, 1050'C, and 1 100'C; and anneal times between 10 s and 60 s were investigated. The progression of the boron profile with RTA temperature is shown in Figure 1. Each sample was implanted with lxl016 cm-2 boron at 10 keV and rapid thermal annealed for 10 seconds in an Argon ambient. As shown, the as-implanted profile is confined to the SiO. 7 GeO. 3 layer. Rapid diffusion of boron in the polycrystalline layer during RTA has resulted in a nearly uniform boron distribution in Si0.7GeO. 3 . At the interface between the polycrystalline SiO.7GeO.3 alloy and the crystalline silicon substrate the slope of the boron profile changes due to the decrease in diffusivity as the boron leaves the polycrystalline layer and enters the crystalline substrate. With this high dose implant, the junction depth can be varied over a wide range by small changes in the RTA temperature with junction depths varying between 600 A and 1600 A at a background concentration of lx10 16 cm-3 as the temperature is increased by only 50 0 C. The temperature dependence of the boron dose reaching the silicon for an implant dose of lxl0 16 cm-2 is shown in Figure 2. It is expected that almost all of the boron in silicon will be electrically active at these RTA temperatures. In addition to controlling the dopant profiles with RTA temperature, implant dose may also be used to control the junction depths as well as the peak surface concentration. This is illustrated in Figure 3 with boron profiles following RTA for three different implant doses. Each of the samples was annealed at I 100°C for 10 seconds in an Argon ambient. By simply varying the implant dose, the junction depth has been varied between 1300 A and 4000 A at a background concentration of lxl0 16 cm- 3 and the peak boron concentration has been controlled between 2x1019 cm- 3 , and 2x10 20 cm-3 for an anneal temperature of 1100'C. The amount of boron in silicon as a function of the implant dose is shown in Figure 4. Through proper choice of anneal conditions and implant dose, a wide degree of control over junction depth and boron concentration can be achieved. Electrical Properties To study the electrical properties of the junctions diffused from polycrystalline SiO.7GeO.3, p÷-n diodes were fabricated as described in Section II. Reverse bias I-V characteristics obtained from a 400 A deep, 400 gim x 400 ltim diffused junction before and after forming gas anneal are shown in Figure 5. The junction was formed by implanting boron into SiO.7Ge 0 .3 at 10 keV/3xl0 15 cm- 2 followed by RTA at 1050'C/10 s. The junction depth was determined by SIMS. Also shown for comparison is the reverse bias 14 IV characteristics of an implanted junction. This sample was first implanted with 3x10 cm- 2 Ge at 50 keV to preamorphize the silicon followed by boron implantation at 3x10 15 cm- 2 and 10 keV. RTA was performed at 1100'C for 10 seconds resulting in a much deeper junction of 0.2 gim. As shown, both IV profiles are quite similar before the forming gas anneal with comparable leakage currents and breakdown voltages. After the forming gas anneal, the leakage current of the diffused junction is greatly reduced while that of the implanted sample is only slightly reduced. The low leakage current of the diffused junction is supported by the forward I-V measurements which indicated an ideality factor of 1.05. The reduction in leakage current in the diffused sample following forming gas anneal can be understood by considering the junction under reverse bias. The diffused junction is expected to have many generation centers at the Si 0 .7Ge 0 .3/Si interface and in the 300
polycrystalline layer along the grain boundaries due to unsatisfied bonds. Carriers generated within a diffusion length of the depletion region will be swept across and add to the reverse bias leakage. During the forming gas anneal, some of these unsatisfied bonds will be compensated by the hydrogen atoms, thus reducing the number of generation centers and hence the leakage current. Another interesting feature in Figure 5 is the gradual increase in reverse leakage for the implanted sample that did not exist before the forming gas anneal. This can be attributed to the penetration of aluminum into silicon during the anneal. It should be noted that even though the implanted junction is much deeper than the diffused junction, a 0.2 gim junction should still be considered shallow and a diffusion barrier for Al must be used to avoid this problem. Aluminum penetration has been avoided in the diffused junctions because the effective junction depth is much greater than the actual junction depth due to the addition of the polycrystalline Sio.7Ge0.3 layer. As shown in Figure 5, both the diffused and implanted junctions exhibit a fairly high breakdown voltage of approximately 23 V.
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Reverse Bias (V) Figure 5. Comparison of reverse bias leakage profiles for implanted and diffused diodes. An interesting aspect of the reverse bias I-V characteristics of the diffused junction shown in Figure 5 is the kink at approximately - 8 V. This sudden increase in the reverse leakage was found in all of the diffused junctions. We believe that at this point, the junction depletion region at the periphery of the device has widened to include the SiO. 7 GeO. 3/Si
301
interface. Then, the interface and the polycrystalline material should both contribute generation centers in the depletion region causing the increase in reverse bias leakage. An effective means of verifying the above behavior is to plot the reverse bias leakage current as a function of inverse temperature. The leakage current of a pn-junction diode can be expressed in terms of two components : Igen due to generation of carriers within the depletion region and ldiff due to diffusion of carriers generated outside the depletion region. These current components can be expressed as [12]: (1)
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(3)
and has a strong temperature dependence. Combining Equations (1), (2) and (3), we obtain two different temperature dependencies for Igen and Idhff given below logI,a, a logI,,
a
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which can be used to determine the dominant leakage current mechanism of pn junction diode. The reverse bias leakage current of a diffused junction formed by implanting boron into SiO.7GeO.3 at 10 keV/lx10 16 cm- 2 is shown as a function of 1/T in Figure 6 for two reverse bias voltages of -5 V and -15 V. These voltages were chosen to bias the diode below and above the kink observed in the INV profile of Figure 5. The -5 V bias produces a curve which clearly illustrates generation dominated current at low temperatures with a slope of 0.59 and diffusion dominated current at high temperatures with a slope of 0.93. At a -15 V bias, however, generation current dominates throughout the entire temperature range with a slope of 0.55 at low temperatures and 0.65 at higher temperatures. The offset of the two curves also shows an increase in the magnitude of the generation component of leakage current. Even though this appears to be a problem, it should be noted that the kink occurs at voltages much higher than supply voltages considered for submicron MOS transistors. Furthermore, even with the kink at -8 V, an ultra-shallow - 400 A deep diffused junction exhibits a lower leakage than a much deeper (- 2000 A) implanted junction throughout the entire voltage range as shown in Figure 5.
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. IV. CONCLUSIONS In this paper, we have demonstrated the feasibility of forming high quality shallow p+n junctions by diffusion from selectively deposited, boron implanted polycrystalline SixGel.x alloys. This was confirmed by forward bias and reverse bias I-V and I-T measurements. We have shown that a wide degree of control can be achieved over the junction profiles by varying the implant dose and the RTA temperature. In the fabrication of submicron MOSFETs, we can utilize implanted polycrystalline SixGel-x as a diffusion source in two different ways to form shallow source/drain junctions: i) we can leave the selectively deposited Si0.7 Ge0.3 on the junctions after dopant drive-in to raise the junctions which was the subject of this study. Here, SixGeIx can serve as a sacrificial layer during silicide formation and eliminate silicon consumption below the gate level, ii) SixGel.x can be removed after dopant drive-in making the process directly comparable to ion-implantation. If desired, selective removal of SixGeIx can be also be followed by in-situ doped selective Si epitaxy to raise the junctions. V. ACKNOWLEDGEMENTS The authors would like to thank Barbara Neptune of MCNC for ion-implantation, Dieter Griffis and Jerry Hunter for SIMS analysis, and Joan O'Sullivan, Richard Kuehn, and Henry Taylor for assistance in sample preparation. This work has been partially supported by NSF Engineering Research Centers Program through the Center for Acvanced Materials Processing (Contract # CDR-8721505) and SRC Microstructures Science Program (Grant 90-SJ-081).
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VL REFERENCES C. M. Osburn, "Formation of silicided, ultra-shallow junctions using low thermal budget.processing", Journal of Electronic Materials, vol. 19, P. 67, 1990. 2. M. C. Ozturk, J. J. Wortman, and R. B. Fair, "Very shallow p+-n junction formation by low-energy BF2 ion-implantation into crystalline and germanium preamorphized silicon", Applied Physics Letters, vol. 52, p. 963, 1988. 3. P. G. Carey, T. W. Sigmon, R. L. Press, and T. S. Fahlen, "Ultra shallow high concentration boron profiles for CMOS processing", IEEE Electron Device Letters, vol. EDL-6, p. 291, 1985. 4. S. N. Hong, G. A. Ruggles, J. J. Wortman, E. R. Myers, and J. J. Hren, "Characterization of the ultra-shallow p+-n junction diodes fabricated by 500-eV boron ion-implantation", IEEE Transactions on Electron Devices, vol. 38, p. 28, 1991. 5. M. C. Oztfirk, J. J. Wortman, C. M. Osburn, A. Ajmera, G. A. Rozgonyi, E. Frey, W. K. Chu, and C. Lee, "Optimization of the germanium preamorphization conditions for shallow-junction formation", IEEE Transactions on Electron Devices, vol. 35, p. 659, 1988. 6. C. Hill and S. K. Jones, "Modelling diffusion in and from polysilicon layers", in MRS Symposia Proceedings, Vol. 182, p. 129, 1990 7. K. Park, S. Batra, S. Banerjee, and G. Lux, "Comparison of amorphous and polycrystalline silicon films as a solid diffusion source for advanced VLSI processes", in MRS Symposia Proceedings, Vol. 182, p. 159, 1990 8. B. Raicu, M. I. Current, W. A. Keenan, D. Mordo, R. Brennan, and R. Holzworth, "Supersaturated p-type polycrystalline films produced by rapid thermal annealing of high dose boron implants for interconnects and shallow junction diffusion sources", in MRS Symposia Proceedings, Vol. 182, p. 153, 1990 9. Y. Zhong, M. C. Oztiirk, D. T. Grider, J. J. Wortman, and M. A. Littlejohn, "Selective low pressure chemical vapor deposition of Si/Ge alloys in a rapid thermal processor using dichlorosilane and germane", Applied Physics Letters, vol. 57, p. 2092, 1990. 10. T. K. Cams, S. S. Rhee, G. K. Chang, and K. L. Wang, "The study and application of a selective etchant in GeSi/Si Heterostructures", in Proceedings of Techcon'90, p. 297, 1990 11. M. Sanganeria, M. C. Oztiirk, G. Harris, D. H. Maher, D. Batchelor, J. J. Wortman, B. Zhang, and Y. L. Zhong, "Optimization of Process Conditions for Selective Deposition of Polycrystalline Si/Ge Alloys in a Rapid Thermal Processor", To be published in proceedings of Third International Symposiun on ULSI, Science and Technology. 12. A. S. Grove, Physics and Technology of Semiconductor Devices. John Wiley & Sons, 1967. 1.
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ENHANCED SILICIDE FORMATION USING SELECTIVE EPI GROWTH ON SOURCE/DRAIN FOR DEEP SUBMICRON CMOS L.K. Wang, D. Moy, J. A. Ott and T. S. Kuan IBM Research Division T. J. Watson Research Center Yorktown Heights, NY 10598 Thin titanium silicide formation on very shallow junctions is often impeded due to retardation of phase transition and dopant effect. A selectively deposited epi can provide an undoped silicon buffer layer to eliminate these two effects. In this experiment, deep submicron CMOS devices are fabricated using selective epi on very shallow source/drain. The electrical characteristics of the fabricated devices will be presented. INTRODUCTION Shallow source/drain junctions are required to fabricate deep sub-micron CMOS devices. However such junctions may be too resistive without a layer of low-resistivity silicide [1]. The formation of low sheet resistance, ultra-thin titanium silicide on ultra-shallow junctions can be very difficult. Both the reduction of the thickness of the silicide film and the decrease in the linewidth of the titanium silicide of the polysilicon gates or diffusions can retard the transformation from the high resistivity C-49 phase to the low resistivity C-54 phase. As shown in Figure 1, the silicide sheet resistance increases very rapidly when the linewidth and thickness are reduced. To reduce the sheet resistance, thicker titanium has to be used which will consume more silicon in the junction region to form the silicide. This will introduce both the junction leakage as well as higher silicide to N + contact resistance due to the consumption of the highly doped region of the junctions [2]. Furthermore a highly doped n-type source-drain diffusion can additionally impede the silicide formation at lower formation temperatures. Figure 2 shows the effect of the n + junction implant dose on the sheet resistance of the silicide formed over the n + junctions. In order to form a low sheet resistance silicide on very shallow junctions without consuming silicon from the junctions, we use a selective silicon epi growth (SEG) process to deposit a layer of undoped silicon epi on the source/drain junctions of CMOS devices for thicker titanium silicide formation.
305
Figure 1 The effect of titanium thickness and linewidth on silicide sheet resistance over undoped silicon.
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PROCESS The selective silicon epi is deposited in a Applied Materials AMC-7810 cylindrical epitaxial reactor (Figure 3) at 850°C under reduced pressure [3,4,5]. The pre-deposition cleaning is accomplished by a short HCI-H 2 etch followed by a selective deposition of silicon facilitated by the use of SiC14 in H 2 carrier gas. A silicon epi layer, typically 30nm thick, is deposited to provide a 35nm thick titanium silicide. Thicker epitaxial silicon can be deposited if a thicker titanium silicide layer is desired.
306
Figure 3 Selective silicon epi deposition system.
In this experiment silicon epitaxial layer is grown selectively on CMOS devices with 800 nm arsenic N + junctions formed by a 1000°C RTA process. A 30nm thick Si 3 N4 is deposited and followed by RIE to form a sidewall for the selective epi process after the N + junction annealing. The P + junctions are formed after the epi deposition to reduce the drive-in of the boron junctions during the epi growth. A germanium amorphization implant followed by a BF 2 implant is used for the P + junction process. The annealing is attained by a 950°C RTA process with a junction depth of around 100 nm including the thickness of the selective epi. A 25nm thick titanium film is deposited to form a self-aligned titanium silicide layer with a two step RTA annealing process. The final diffusion sheet resistance is around 5 fl/El for both N+ and P+ junctions. The TEM micrographs of the devices with SEG raised source/drain are shown in Figure 4(a) and (b) 0.15pm Figure 4(a) Cross-sectional image of a n-FET with a 30-nm-thick, selective epi on the source and drain.
307
(b) SEG source/drain n-FET with a 0.3,um gate width.
The SEG-CMOS device characteristics are compared to the non-siuicide and non-epi control devices. The SEG devices show less junction leakage current and lower diffusion sheet resistance. The I-V characteristics of the SEG devices are essential the same as the control devices (Figures 5(a) and (b)). ID
(MA)
Figure 5(a) n-MOSFET I-V, (Leff=0.25pm, Vg=0 to 2.5 volts at 0.5 volt steps, Weff-- 9.Opm),
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(b) p4MOSFET I-V, (Leff=0.25pm, Vg=0 to -2.5 volts at -0.5 volt steps, Weff = 9.0pm).
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However the N + /P + diffusion sheet resistance of the SEG devices has been re-
duced to around 5 Q/O- from the 10-40 Q/O of the non-epi N + diffusion due to the elimination of the dopant effect during the silicidation process. There is no line width dependence on the sheet resistance in our measurement even for the narrowest N + diffusion at 0.5 pm. In summary, we have demonstrated a method to use selective epi growth to form low sheet resistance silicide over ultra shallow and narrow junctions and
polysilicon gate for deep sub-micron CMOS devices. REFERENCES [1] S. P. Muraka, D.B. Fraser, A. K. Sinha,and H. J. Levinstein, IEEE Trans. ED-27, (1980) p.1409. [2] Y. Taur, J. Y-C Sun, D. Moy, L.K. Wang, B. Davari, S.P. Klepner and C. Y. Ting, Trans. ED-34, (1987) p. 57 5 . [3] H.K. Park, J. Vac. Sci. Technol. A2 (1984) p. 26 4 . 14] B. Ginsberg, Ext. Abs. Electro. Chem. Soc. Fall Meeting (1987) p.991. [5] T.O. Sedgwick, Appl. Phys. Lett. 54, (1989) p.2689.
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OPTIMIZATION AND CHARACTERIZATION OF LPCVD TiB2 FOR ULSI APPLICATIONS C.S. Choi*, G.A. Ruggles*, C.M. Osburn*,+, and G.C. Xing** *Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27695 Department of Material Science and Engineering, North Carolina State University, Raleigh, NC 27695 +MCNC, Center for Microelectronics, P.O.Box 12889, Research Triangle Park, NC 27709 The chemical vapor deposition of TiB 2 from gaseous mixtures of TiCIL, B2H 6 and H2 onto various substrates was studied. Experimental depositions of films were carried out in a cold wall system over a broad range of temperatures, pressures and input gas flow rates. The as-deposited films are very fine grained polycrystalline or amorphous, and the films RTA-annealed above 900'C are crystalline TiB 2 . Below 550'C, surface reactions are the dominant factor for the kinetics of TiB 2 deposition, while mass transport is a limiting step for deposition above 550'C. At higher temperatures the deposition rate increases linearly with flow rate and total pressure, suggesting the deposition mechanism is reactant limited. The B/Ti ratio determined approaches the stoichiometric value of 2 in higher temperature films, while the presence of excess boron and chlorine was detected for low temperature films. Stoichiometric TiB 2 films were deposited over a wide range of input gas mixture. Depletion effects of input gas were observed at low flow rate and high pressure where the residence time of reactants is longer than 10 sec. INTRODUCTION Because of its interesting properties, titanium diboride has been investigated and commercially used for several applications such as: crucible materials for melting metals, thermocouple protection tubes in melting metal, abrasives, protective coatings, high temperature electrodes in nuclear fusion applications, and cathodes or containers in aluminum reduction cells. Nicolet has already pointed out titanium boride as an interesting potential material for mictoelectronic device fabrication [I]. The high conductivity and chemical inertness at high temperature leads TiB 2 to be considered as a potential candidate for a diffusion barrier or gate/diffusion cladding. The resistivity of bulk polycrystalline TiB2 (=101Q-cm) [2] and single crystal (6pQ-cm) [31 is lower than that of other potential barrier materials like silicides or nitrides and only slightly higher than that of tungsten. Shappirio et al. showed that ZrB2 is stable in contact to aluminum up to 600'C [4]. Feldman et al. used TiB2 as an electrode in polycrystalline silicon thin film solar cells [5]. Several different methods have been employed to produce TiB 2 thin films: i.e. sputtering [4, 6-10], reactive ion plating [11], laser induced vapor-phase synthesis [12], and reaction of Ti-B thin film couples [13]. Due to stringent ULSI requirements for low thermal budget, conformal step coverage, and high purity films, low pressure chemical vapor deposition is a good choice for producing high quality TiB 2 films.
310
Chemical vapor deposited polycrystalline TiB 2 films have been initially obtained from a source gas of TiCI4/BC13/H2. Peshev et al. deposited TiB2 films in the temperature range from 1000-1400'C [14]. A pyrolytic deposition of TiB 2 was performed at 1400 1600'C and at 3-5 Torr [15,16]. Models for the deposition process were developed based
on the experimental results of deposition rates and efficiencies, coupled with thermodynamic calculations for CVD TiB2 [17].
Pierson et. al. reported that the
atmospheric CVD at 900-950'C produced boron-rich titanium diboride even at a stoichiometric input gas [18]. A deposition study combined with a thermodynamic study suggested that equilibrium is approached under typical TiB2 CVD conditions, and that the deposited phases are far more sensitive to changes in system chemistry than they are to changes in temperature [19]. A glow discharge deposition was performed at temperatures from 480 to 6500 C, resulting in as-deposited resistivity ranging from about 200-450gi)-cm [20]. A chemical vapor deposition of titanium diboride using the reaction of TiCI4 with B2H6 in a hydrogen atmosphere in the temperature range of 600-900*C temperature was also reported [21]. The deposition rate of the B2 H6 reaction was considerably greater than that of the BC13 reaction, and it proceeded at a lower temperature; however, the deposition rate was negligible below 700'C, and above 1000'C the deposition tended to be powdery, probably the result of vapor phase nucleation. This work consists of experimental results for the mechanism of TiB 2 film deposition at various temperatures, pressures, gas mixtures, and flow rates, as well as analysis of TiB 2 films. EXPERIMENTAL TiB 2 films were prepared by chemical vapor deposition using TiC14 , B2H 6 and H2 source gases. A detailed description of the cold-wall CVD reactor and is given in a separate publication [22]. Titanium boride films were deposited on bare Si, or thermally oxidized silicon wafers. Chemical vapor deposition of TiB 2 for this work was done over a wide range of process temperatures (375'C - 750 0 C), pressures (0.5 Torr - 5 Torr), and total flow rates (69 -550sccm). The B/B+Ti ratio of the input gases was varied from Ti rich (B/B+Ti = 0) to B rich (B/B+Ti = 1). Only one parameter was varied for each set of experiments, while the others were held at a nominal value. The thicknesses and surface roughness of the TiB2 films were measured using a Dektak profilometer after etching through the film with a 30% H 202 solution at room temperature for 1-10 min to provide a step at the measurement point. The thickness of some samples was verified using Rutherford backscattering spectroscopy (RBS) and/or cross-sectional Transmission Electron Microscopy (TEM). The thickness of films deposited below 600*C was measured via angle lapping and cross sectioning SEM. The composition and phases of the films were determined by Auger Electron Spectroscopy (AES), X-ray Photon Spectroscopy (XPS), and X-ray diffraction. The optimized deposition conditions were achieved through a careful characterization of the as-deposited and annealed TiB 2 films. This optimization required measuring the following parameters; phases and crystallinity, stoichiometry, resistivity, impurity incorporation into the films, deposition rate and uniformity.
311
RESULTS AND DISCUSSION Film Chemistry X-ray diffraction was employed to identify the phases present in the as-deposited films. No X-ray diffraction lines of TiB 2 were observed at a deposition temperature up to 750'C, suggesting the presence of a very fine grained polycrystalline or amorphous phase for the as-deposited films. As shown in Fig. 1, the films RTA-annealed above 900'C gave patterns corresponding to the TiB2 structure, and the intensities of the TiB 2 peaks increased as the annealing temperature was increased. The X-ray data indicated that the average grain size in TiB 2 film grows with annealing temperature. Only the as-deposited sample showed a silicon substrate line, which is probably due to a stress build-up during film deposition. The grain-size growth and the resistivity reduction with annealing temperature are discussed in detail elsewhere [23]. In addition, XPS, coupled with depth profiling, was performed to find the phase(s) and chemical composition of the films. A typical result for a stoichiometric TiB 2 film deposited at 650'C and 5 Torr is shown in Fig: 2. No phase and composition change in the bulk film were noticed after rapid thermal anneal at 1150 0 C, 10 sec [24]. The film appears to be pure TiB 2 , with some oxygen present only at the surface, presumably due to surface oxidation. Examination of the B Is peak in detail revealed that only Ti-B bonding was present in the film, with the exception of the surface, where some B-O bonding is also present, revealing the formation of BxOy• The effect of deposition time on deposition rate. The dependence of the film thickness on the deposition time was examined in Fig. 3. The TiB 2 films were deposited on silicon, or thermal oxide substrates under a typical deposition condition: 600'C, 1 Torr, TiC14 = 25 sccm, and 10% B2 H 6 in H 2= 250 sccm (B/B+Ti= 0.67). The film thickness increased linearly with the growth time, and the deposition rate was independent of the substrate (Si vs. SiO 2 ). Some evidence of an incubation time (=20 sec) was observed. Since this time is very small compared to a typical deposition time (6 min), the growth rate was calculated simply by dividing the film thickness by the growth time in this work. The effect of temperature on the deposition. The effect of temperature on deposition rate of TiB 2 was studied as shown in Fig. 4. The depositions of TiB 2 were done at 3 Torr, B/B+Ti= 0.67 in the temperature range of 375 - 750 'C. This graph contains an Arrhenius plot of the logarithm of the deposition rate as a function of reciprocal temperature. As can be seen in this figure, two distinct regimes of deposition kinetics are evident. From standard CVD theory, the presence of the two regimes is defined by the type of controlling reaction rate; if the surface reaction is rate limiting, as is often the case at low temperature, the deposition rate will be a strong function of deposition temperature. If the rate limiting step is either reactant limited or diffusion controlled, the temperature dependence will be slight. As can be seen from the figure, below 550'C surface reactions are apparently the dominant factor for the kinetics of TiB 2 deposition, while mass transport is a limiting step for deposition above 550'C. Activation energies for deposition are 1.36 eV, and 0.31 eV for low and high temperature deposition, respectively. The reported value of the activatic n energies for TiB 2 deposition from BC13, TiCI4 , and H2 source were 1.74 eV and 0.17 eV [25].
312
Figure 5 shows the B/Ti and the Cl/Ti mole ratios as a function of deposition temperature. The B/Ti ratio of films was determined by AES coupled with depth profiling. A 3 KeV Ar beam was used for sputtering the film. The lack of a titanium diboride standard did not allow us to calibrate the B/Ti ratio precisely. Instead, the sensitivity factors of metallic titanium and metallic boron were adopted to quantify the ratio. AES analysis of the these films indicated the presence of excess boron throughout the bulk for films deposited at low temperatures. For example, the B/Ti ratio for a TiBx film deposited at 500'C was found to be 2.6 rather than the 2.0 value obtained for higher deposition temperatures. In addition, during wet etching, the films deposited at temperatures below 600'C, could not be completely removed. The residual layer, which was not completely etched in H 2 0 2 , is believed to result from concentration of a boron phase as the boron-rich titanium boride film is etched, ultimately resulting in a layer which resists further etching. Thus, thickness data were obtained from cross-sectional SEM after an angle lapping. As the deposition temperature increases, the B/Ti ratio approaches the stoichiometric value of 2, within the reasonable uncertainty of the AES sensitivity factors, and stays constant at higher temperatures. Pierson et al. also found boron-rich films deposited at 600'C or below and more stoichiometric films at higher temperature [21]. In addition to the problem of excess boron, a large Cl content was observed in low temperature films as well. At 6000 C and above the Cl was at the detection limit for EDS (2%). The decomposition of the chlorides at lower temperature is presumably not efficient, so that the films containing chlorine and excess boron are deposited. The benefit of higher temperature deposition in producing purer and more stoichiometric films is clear, and qualitatively in agreement with the thermodynamic calculations. The effect of input gas mixture on deposition. The deposition rate of titanium boride films was measured for the films deposited at 600-C, 3 Torr for 6 min. The B/B+Ti ratio of the input gas mixture was varied from 0.0 to 0.8 at a constant total flow rate of 550 sccm. In the temperature range 375 - 750'C, a violet colored film was deposited on the cold wall and the color changed to white when the chamber door was opened. The deposition on the wall was more pronounced in lower total pressure runs, in which the deposition efficiency is lower. It is believed that the observed films were titanium subchloride(s) because both TiCI3 [20, 25, 26] and TiCI 2 [21] are reported as stable substances below 440 and 475°C respectively. One interesting observation is the reaction between a Si substrate and the reactant gas in a CVD system containing only TiC14 (B/B+Ti=0),'since TiSi 2 could form. In this work, no discernible depositions were observed when 75 sccm of TiCI4 and 925 sccm of H 2 were introduced at either 375°C or 600'C, 3 Torr for 20 nin. Reynolds et al. also found no reaction at 627°C when TiCI4 was introduced over a Si wafer; however he did form TiSi 2 , and simultaneously etch Si above 827'C over the pressure range of I750mTorr [27]. Boutevitle et al. used a hydrogen reduction of TiCI4 in the temperature range of 700-1000'C and a total pressure of 0.75 Torr to form titanittm silicide selectively on Si [28]. The deposition rate and B/Ti atomic ratio determined via AES are plotted as a function of the B/B+Ti ratio in the reactant gas mixture in Fig. 6. The B/Ti ratio and the deposition rate were found to be dependent on the input gas ratio. No deposition is observed at an input gas mixture of B/B+Ti=0 (TiCI 4 only). On the other hand, the films deposited at B/B+Ti=0.8 were very nonuniform in composition and color. For this boronrich input gas mixture, the B/Ti ratio in the film increases from 2.4 to 9.9 along the
313
direction in which the input gases travel, indicating a depletion of TiCl 4 . The peak in deposition rate occurs close to an input gas ratio corresponding to stoichiometry (0.67). Such a peak in deposition rate from a fixed total flow system could be expected from a highly-efficient, or reactant-limited process. However, it is difficult to conclude whether there is a true maxima in the B/Ti ratio at B/B+Ti = 0.67 in the input gas, or if the data represent noise in the AES measurements. The films were found to have a constant, nearly-stoichiometric B/Ti ratio over a wide range of input gas mixture ratios ranging from 0.4 to 0.71. This result indicates that the window to deposit a single phase TiB 2 with very limited amount of secondary deposits (e.g. < 0.1 %) was wide. The effect of input gas flow rate on deposition. The deposition rate at 600°C increases linearly with total flow rate, from 70 to 550 sccm, as shown in Fig. 7. However the TiB2 thickness (deposition rate) also varies along the gas flow direction as shown in Fig. 8. For flow rates below 140 sccm, the thickness of the film decreases monotonously along the substrate in the direction of gas travel; at higher flow rates the film thickness maximum moves toward the center of the wafer. For the transport of gaseous species between the bulk gas and the deposition surface, it is usually assumed that a laminar boundary layer lies between the turbulent bulk gas flow and the deposition surface, and that the diffusion of gaseous species through the laminar boundary layer is a possible rate-limiting step. Typically two distinct types of mass transport limitations are associated with reactant flux into the reaction chamber, and the combination of these two establishes the mass transport limiting aspects of a reaction taking place in a given open tube system. The first depends entirely on the rate of introduction of gaseous reactant into the chamber. The second depends on the movement of this introduced mass to all portions of the reaction chamber, particularly the reaction site, and is governed by the system geometry. The average linear gas stream velocity is typically computed in a hot wall system to provide a normalization of the geometry [29]. However, it is practically very difficult to get a meaningful value of the linear gas stream velocity. in a cold wall system due to the complex reactor geometry. In this work, flow rates are used for analysis, instead of linear gas stream velocities. The residence time of the input gas in a reactor is defined as t = 60VP/f, where t = residence time (sec), V = volume of the reactor (1), f = flow rate (SLPM), P = pressure (Atm). At a low flow rate, the residence time of the reactant introduced into the reaction chamber may be long in comparison to chemical reaction or mass transfer rates. Hence the chemical system in the reactor may be expected to approach equilibrium. Once the system approaches equilibrium, the input gas flow rate becomes the mass transport rate. In other words, in this regime the deposition rate is determined entirely by the input gas flow rate, and therefore is proportional to the flow rate. In Fig. 7 the deposition rate is a linear function of the flow rate. On the other hand, as the reactants flow along the length of the reaction chamber, a portion of the reactant gas is consumed. The partial pressure of the reactant gas is thus lower near the outlet end of the reactor, and the deposition rate is reduced there if all other deposition parameters remain constant. The calculated residence time for the system used here is shown in Table I. As clan be seen in the table, the residence time increases as the flow rate decreases. When t ie flow rate or gas stream velocity is low, i.e. the residence time is long, depletion of input gases might be expected to occur. Indeed, as can be seen in
314
Table 1. The residence time at various input gas flow rates 600'C, 1 Torr, B/B+Ti--0.67 flow rate (sccm) residence time (sec)
68.8 21.9
103.1 14.7
137.5 11.0
275 5.5
550 2.8
Fig. 8, for total flow rates below 137.5 sccm the thickness of TiB 2 decreases along the direction of gas travel, indicating depletion of the input gas, while at high flow rates with short residence times, the thickness is maximum at the center of the wafer and decreases radially. The location of the maximum thickness is observed to shift from the wafer edge nearest the gas injector to that of the pumping port as the flow rate (linear gas stream velocity) increases. This is probably because that it takes longer for the input gas to approach the deposition temperature at high flow rate. The effect of pressure on deposition A series of experiments to study the dependence of pressure on deposition of TiB 2 were performed. The total pressure of the chamber was varied from 0.1 to 4 Torr by throttling the exhaust valve. The other deposition variables were fixed at 600'C, 250 sccm total flow rate having B/B+Ti = 0.67 and 6 min deposition time. Figure 9 shows the dependence of the deposition rate of TiB 2 films on the total pressure. No deposition was detected at 0.1 Torr, even using 4 point probe sheet resistance measurement, which should be sensitive to the presence of ultra thin film. A meaningful value of deposition rate could not be obtained at a pressure of 4 Torr due to poor thickness uniformity. As can be seen in the figure, the deposition rate linearly increases with the input partial pressure of TiCl4 and B 2 H6 . The film thickness variation on the wafer along the direction of gas flow is plotted in Fig. 10, where evidence of gas depletion is seen above 1 Torr. The location of the maximum in the film thickness shifts from the leading(input) to the trailing(exhaust) edge as the pressure decreases from 2 Torr to 0.5 Tort. For a horizontal CVD reactor, the boundary layer thickness, 5, can be determined using the equation: 8 = (Dr d / Re)1/ 2 ,where Dr is the diameter of the tube, d is the axial distance along the tube, and Re is the Reynolds number. Evidently Dr and d are independent of the pressure. The Reynolds number is calculated using the formula: Re=Dd x L / DA, where Dd is linear gas stream velocity, L is a characteristic length descriptive of the flow field which, for the case of gas flow in a tube, would be equal to the diameter of the tube, and DA is diffusion constant. Because L is independent of pressure and both the linear gas stream velocity and the diffusion constant are inversely proportional to the system pressure, the Reynolds number and consequently boundary layer thickness are independent of the pressure [30]. However the deposition rate increases linearly with the partial pressure of the reactants, which is proportional to total pressure in this experiment. The residence time of the input gas in the chamber and deposition efficiency are calculated in Table. II. The deposition efficiency is defined as a ratio of the mole amount of Ti deposited on the heated area to the mole amount of Ti in the input gas based on the input gas flow rate. The residence time of reactant and the deposition efficiency both increase with the pressure. The gas depletion effect discussed earlier in the flow rate experiments is observed again in these pressure experiments for long residence times.
315
Table II. The residence time and deposition efficiency at various pressures 600'C, 275sccm total flow, B/B+Ti=0.67 total pressure (orr) residence time (sec) deposition efficiency (%)
.5 2.8 0.75
1.0 5.5 8.1
1.5 8.2 13.5
2.0 11.0 18
At the total pressure of 2 Torr where the residence time is 11 sec, the input gas depletion effect is very pronounced, i.e. the film thickness on the wafer decreases along the direction of gas flow. A more uniform wafer, having the thickest film more symmetrically at the center, is obtained at the pressure of 1 Tort. It is very interesting to note the shift of the thickest film position from the front of the wafer at 2 Torr toward the back at 0.5 Torn, presumably caused by the low pressure gas taking longer (travelling farther) to achieve thermal equilibrium. CONCLUSIONS The as-deposited films are very fine grained polycrystalline or amorphous. However, the films RTA-annealed above 900'C gave patterns corresponding to the TiB 2 structure. Except for an oxidized layer at the surface, the films appear to be pure TiB 2 when analyzed via XPS. The film thickness increased linearly with the growth time, and the deposition rate was independent of the substrate (Si vs. Si0 2). Two distinct regimes of deposition kinetics were evident in different deposition temperature ranges. Below 600'C, surface reactions are found to be the dominant factor for the kinetics of TiB 2 deposition, while mass transport is the limiting step for deposition above 600'C. Activation energies for deposition were determined to be 1.36 eV, and 0.31 eV for low and high temperature deposition, respectively. The presence of excess boron and chlorine was detected throughout the bulk for low temperature films. As the deposition temperature increased, the B/Ti ratio approached the stoichiometric value of 2, and remained constant at higher temperatures; furthermore the Cl content was reduced. Over a wide range of input gas mixture ratios from 0.4 to 0.71, the films were found to have a constant, nearlystoichiometric B/Ti ratio. This result indicates that the window to deposit single phase TiB 2 is quite wide. The peak in deposition rate was found to occur close to an input gas ratio corresponding to stoichiometry (0.67), suggesting that the deposition mechanism was reactant limited. The deposition rate increased linearly with flow rate and pressure, indicating that the mechanism for deposition was equilibrium limited in the range of flow rate 70 - 550 seem. Input gas depletion effects were observed at low flow rates and high pressures where the residence time of reactants was longer than 10 sec. A surface reaction limited mechanism was not observed in these experiments, even at the maximum flow rate of 550sccm. The roughness of the films increased linearly with the thickness. To get stoichiometric and uniform films in the reactor used in this study, the optimized process condition was 600'C, 1 Torr, total flow rate of 550 sccm with an input gas mixture of B/B+Ti = 0.67. ACKNOWLEDGEMENTS This work has been supported by the Semiconductor Research Corporation (Contract #89-MP-132) and MCNC. The authors also gratefully acknowledge helpful discussion with A. Reisman, and J.J. Wortman of the Nanometer Engineering Laboratory
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of NCSU/MCNC and Stephen Bobbio at MCNC. They would like to thank C.U. Ro, A. S. Shah, Susan K. Hofmeister and J.D. Hunn for technical assistance. REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [91 [10] [11] [12] [13] [14] [15] [16] [17] [181 [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30]
M.-A. Nicolet, Thin Solid Films, 52, 415 (1978). G.V. Samsonov, B.A. Kovenskaya, and T.I. Serebryakova, Izv. Vyssh. Ucheb. Zaved. Fiz. 14, 19 (1971). A.D. McLeod, J.S. Haggerty, and D.R. Sadoway, J. American Ceramic Society, 67, No. 11 705 (1984). J.R. Shappirio, J.J. Finnegan, R.A. Lux, J. Vac. Sci. Technol. A3, 2255 (1985). C. Feldman, F.G. Satkiewicz and N.A. Blum, J. Less-Common Met., 82, 183 (1981). G. Ryan, S. Roberts, G.J. Slusser and E.D. Adams, Thin Solid Films, 153, 329 (1982). T, Shikama, Y. Sakai, M. Fukutomi and M. Okada, Thin Solid Films, 156, 287 (1988). T. Shikama, Y. Sakai, M. Fujitsuka, Y. Tamauchi, H. Shinno and M. Okada, Thin, 164, 95 (1988). T. Larsson, H.-O Blom, S. Berg, and M. Ostling, Thin Solid Films, 172, 133 (1989). H.-O Blom, T. Larsson, S. Berg, and M. Jostling, J. Vac. Sci. Technol. A 6 (3), May/Jun, 1693 (1988). T. Sato, M. Kudo, and T. Tachikawa, Denki Kagaku 55 No.7, 542 (1987). J.D. Casey and J.S. Haggerty, J. Materials Science, 22, 737 (1987). C. Feldman, F.G. Satkiewicz and G. Jones, J. Less-Common Met., 79, 221 (1981). P. Peshev and T. Niemyski, J. Less-Common Met., 10, 133 (1965). R.E. Gannon, R.C. Folweiler, and T. Vasilos, J. American Ceramic Society, 46, No.10 496 Sept. (1963). J.J Gebhart and R.F, Cree, J. American Ceramic Society 48, No.5 May , 262 (1965) T.M. Besmann and K.E. Spear, J. Electrochem. Soc., 124, 790 (1977). H.O. Pierson and A.W. Mullendore, Thin Solid Films, 95, 99 (1982). E. Randich and T.M. Gerlach, Thin Solid Films, 75, 271 (1981). L.W. William, Appl. Phys. Lett., 46 (1), 43 (1985). H.O. Pierson and A.W. Mullendore, Thin Solid Films, 72, 511 (1980). C.Choi, G.A. Ruggles, C.M. Osburn, P. Shea, and G.S. Xing, Proceeding of MRS symposium, Advanced metallization in microelectronics, Vol 181, 455 (1990) C.S. Choi, G.C. Xing, G.A. Ruggles, and C.M. Osburn, accepted by J. Appl. Phys. (1990). T.M. Besmann and K.E. Spear, J. Electrochem. Soc., 124, 790 (1977). R.J. H. Clark, The chemistry of Titanium and Vanadium, Elsevier, NY, 40 (1968). N. Nakanishi, S. Mori, and E. Kato, J. Electrochem. Soc., 137, No.], 322, (1990). G.J. Reynolds, C.B. Cooper III and P.J. Gaczi, J. Apple. Phys. 65, No.8, 3213, (1989). A. Bouteville, A. Royer, and J.C. Remy, J. Electrochem. Soc. 134, No. 8, 2080, (1987). A. Reisman and M. Berkenblit, J. Electrochem. Soc. 113, No. 2, 146 (1966). A. Reisman, private communication. 317
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Fig. 4. Deposition rate of titanium
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Fig. 6. Input gas ratio dependence of deposition rate and stoichiometry (B/Ti ratio) for TiB2 films. The films were deposited at 600'C, 3 Torr and the B/Ti ratio was measured by AES.
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Fig. 9. Deposition rate as a function of deposition pressure. The deposition rate increases linearly with pressure. The depositions were performed at B/B+Ti=0.67, 600'C.
320
IDEAL METAL/SILICON CONTACT FORMATION BY CLEAN-NITROGEN-SEAL PROCESSING H.
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M. Otsuki and T.
Ohmi
Department of Electronics. Faculty of Engineering, Tohoku University, Sendal 980 Japan Fax:(022)224-2549, Phone:(022)224-2649 ABSTRACT The formation of high quality metal/silicon contacts has been demonstrated by a clean-nitrogen gas seal processing. Al, Cu, and Ti thin films were deposited on either n-type or p-type Si substrates by a low energy bias sputtering process. The J-V characteristics of Schottky contacts and Ohmic contacts were evaluated. The experimental results show that the sum of the Schottky barrier height for n-type Si and p-type Si is equal to the bandgap of Si. The dependence of Schottky barrier heights on substrate orientation is also demonstrated. As a result, it is apparent that Schottky barrier height for ntype (lO0)Si is larger than that for n-type (lll)Si by about 0.02eV, and Schottky barrier height for p-type (lO0)Si is smaller than that for p-type (lll)Si by about 0.02eV. The exponential dependence of contact resistance on Schottky barrier height is made clear and very low contact resistance of 3x10-O Q.cm2 is achieved without any heat treatment. Thus the formation of ideal metal/silicon contacts has been verified. Introduction The formation of Ideal metal/silicon contacts and ideal SiO 2 /Si interfaces are most essential to achieve high performances in semiconductor devices. It is well known that native oxide grows very rapidly on Si surfaces and affects the crystallinity of epitaxially grown Si films or the electrical characteristics of metal/silicon contacts such as Schottky contacts and Ohmic contacts[l], [2]. Therefore, it is necessary to suppress the native oxide growth on Si wafer surfaces for highly reliable semiconductor manufacturing. It was reported that the native oxide growth occurs under the coexistence of oxygen and water[il], which results in the increase in the contact resistance as well as the increase in their nonuniformity and fluctuations. The
321
purpose of this paper is to realize ideal metal/silicon contact by isolating the bare Si wafer surface from the clean room air which contains oxygen and water. For this purpose, we have developed new wet cleaning equipment where ultrapure water and a diluted HF vessel are sealed by cleanAs a result, reduction in Al, Cu, Ti/n--Si N2 -gas[2]. contact resistances down to 3.3-3.8x10-7 Q.cm2 and the J-V -characteristics of Schottky diodes identical to those derived from the thermionic emission theory have been obtained without any post-metallization thermal annealing. Thus the effectiveness of the clean-nitrogen seal process has been demonstrated. Experimental (100) and (111) oriented Si wafers were used for the experiment. Patterning of contact holes was carried out by wet chemical etching to avoid damage generation by RIE. After cleaning in boiling H2 S04/H 2 0 2 solution and rinsing in ultrapure water, Si wafers were transported to clean-N2 -gas sealed wet cleaning station. Then, the wafers were chemically etched in diluted HF acid to remove native oxide, rinsed in ultrapure water having dissolved oxygen concentration of 20ppb, and dried by the N2 -gas blow. The Si wafers were transported to sputtering chambers also in N2 ambient. Then Al, Cu, or Tl film deposition was carried out by low-energy bias sputtering technology with in-situ surface cleaning[3],[4]. The metal/silicon contacts were characterized by measuring the J-V characteristics of the Schottky contacts and Ohmic contacts. Results and Discussion There have been several reports on native oxide in metal semiconductor contacts[2][5][6]. Reduction on native oxide growth has been demonstrated under clean-N2 -gas seal processing by Miyawaki et al.[2]. They have pointed out that suppression of native oxide growth is essential to improve electrical characteristics of metal/silicon contacts such as Schottky contacts and Ohmic contacts. Current transport mechanisms in atomically abrupt metal/semiconductor contacts have been reported by Shenai and Dutton[71. They obtained excellent agreements of experimental results with their new current transport theory in Al/n-GaAs system. This paper reports electrical characteristics of metal/Si contacts fabricated under the new clean-N2 -gas seal processing carried out in a different manner. In order to characterize metal/Si contacts with high reliability and high accuracy, all Schottky diodes described in the following were fabricated by the clean-N 2 -gas seal processing(N-process). Figure 1 shows the J-V 322
SS=A.6XI0-'S(0cm) 30.80
z
W
S0.75
z
0-
,
W
n-J10
03 C-,
0.70
BIAS VOLTAGE (VM
a
2
4
6
8
10
LENGTH (mm)
Fig. I
Fig.
J-V characteristics of Al/n-Si. Experimental result and theoretical curve are superimposed, area is The contact 2 4 1.6xlO- cm .
2.
barrier Schottky height of Al/n-Si(lO0) of function a as perimeter length.
characteristics of an Al/n-Si Schottky diode. The contact 2 4 area is 1.6xlO- cm and measurement temperature is 300K. The while the doted line shows measured J-V characteristics, derived from the thermionic ideal J-V characteristics emission theory is superimposed by a solid line. The Al/n-Si and an Schottky diode have nonideal J-V characteristics factor (n-value) of the Schottky diode is 1.05. ideality Figure 2 shows Schottky barrier height of Al/n-Si Schottky diodes calculated from the J-V characteristics as a function the of the perimeter length of the Schottky diodes, where 2 4 contact areas of the diodes are constant of 1.6x10- cm . From the figure, it is seen that the Schottky barrier height strongly depends on the perimeter length and decreases with increase in the perimeter length. Figures 1 and 2 point out that the leakage current flowing through the perimeter is dominant in reverse saturation currents of the Schottky diodes. In order to evaluate the real Schottky barrier the leakage current should be suppressed by a height, channel stopper or a guard ring. Figure 3 shows J-V characteristics of Al/n-Si and Al/pSi Schottky diodes at room temperature by a solid line and a dashed line, respectively. In the case of Al/n-Si contact, and the shows saturation density the reverse current obtained. is current-voltage characteristics rectifying is observed for the However, only Ohmic characteristics Al/p-Si contact (dashed line). This is because the barrier current height is very low and the reverse saturation
323
r 100
At/p-SI
S 10-
Al/p-Si T=77K
I0"' 10"1
'•10-'
.50
I0-
10 U
At/n -Si -0.3
Fig. 3.
-0.2
T=300K -0.1 0 0.1 BIAS VOLTAGE (V)
0.2
0.3
-
.
BIAS VOLTAGE (V)
J-V characteristics of Schottky diodes for Al/n-Si and Al/p-Si were measurements carried out at 300K.
Fig. 4. J-V characteristics of a Schottky diode on Al/p-Si at 77K.
density (J-) becomes very large. Since the barrier height for Al/n-SI is about 0.80eV, that for Al/p-SI would be 0.33eV assuming their sum equals to the bandgap of Si (1.13eV). Reduction in the barrier height by about 0.5eV results in the enhancement In the reverse saturation current density (J-) by nine orders of magnitude. As a result, the voltage drop at the series resistance of the substrate becomes dominant in the J-V characteristics in low voltage region. Figure 4 demonstrates the J-V characteristics of an Al/p-Si contact measured at 77K. It is clearly seen that the Al/p-SI contact has rectifier characteristics, demonstrating the existence of the Schottky barrier. However, carrier freeze-out occurs at this temperature, making accurate barrier height evaluation quite difficult. In order to characterize metal/silicon contacts in more reliable manner, a proper metal must be selected for experiment. Figure 5 shows Schottky barrier heights for Al/n-SI (30 Q-cm) contacts for four different contact areas formed by the clean-N 2 -gas seal process(N-process). Aluminum metallization is carried out by using RF-DC coupled mode bias sputtering technology[4]. The value D.- strongly depends on the contact area due to the leakage current flowing at the perimeter as is discussed in reference to Fig.2. On the other hand, in Cu/n-Si(30 Q.cm) contacts, the Schottky barrier height (D. is independent of the contact area over four orders of magnitude, as shown in Fig.6. Moreover, fluctuation of (bD, is less than 0.005eV. The Schottky barrier heights 4D,.- of the diodes fabricated in Nprocess are slightly smaller than those in C-process because of native oxide at the metal silicon interface.
324
00.84
r 0.82 j0.80
LU 0.78< 0.76 im'
10-5 Fig. 5.
AL/n-Si Schottky Diode I I I 10-1 10-2 18-3 10-4 CONTACT AREA (cm 2 )
Barrier heights of Al/n-Si Schottky diodes for four different contacts area formed by the clean-N.-gas seal process(N-process), where barrier heights are calculated from J-V characteristics at 300K. Cu/n-Si Schottky Diode 0 N-Process M C-Process
• 0.70 "ILU
M 0.69 rt" m0.68-
I
10-5
II
I
10-4
16--
10-2
CONTACT AREA (cm2 ) Fig. 6.
Barrier heights of Cu/n-Si Schottky diodes for four different contact areas and two different processings (N-process and C-process), where barrier heights are calculated from J-V characteristics at 300K.
Figures 7 (a) and (b) show the J-V characteristics of Cu/n-type and p-type Si Schottky diodes at 240K where the by solid lines. The theoretical curves are indicated Cu/n-Si contact. excellent agreement is obtained for the From Fig. 7 (a), the current density greater than 10-2A/cm2 tends to deviate from the in the forward direction of high curve due to the series resistance theoretical resistivity substrate (30 9.cm). Figure 7 (b) indicates the J-V characteristics of the Cu/p-Si Schottky diode where the 325
- 10
o
CU/p-Si T-240K
........
-, I -V zo-
-Theory -- Experiment (b)
0.3
BIAS VOLTAGE (V)
Fig.
7.
0.2
0.1 0 -0.1 BIAS VOLTAGE (V)
-0.2
-0.3
J-V characteristics of Schottky diodes for Cu/n-type S(a) and Cu/p-type Si(b) at 240K. Dots demonstrate measurement points and solid lines are calculated from the thermionic emission theory. T(K)
340 320
300
280
260
240
IV -E
S\O "to" X
10T 2.8
Fig.
8.
3!0
3.2
3.4 3.8 3.8 1/T(10-'/K)
4.0
4.2
Temperature dependence of the reverse saturation current density at a reverse bias of 0.1V (Jo), divided by T2 (Jo/T2); (a) Cu/n-Si, (b) Cu/p-Si. The slope of the results represents the barrier heights according to the following formula: Jo=A-T 2 exp(-q •0 /kT) ( A-
: Richardson Dushman constant)
resistivity of p-type substrate is also 30 Qocm. Due to the series resistance effect, experimental data for current density of the Cu/p-Si diode seem to immediately deviate from the theoretical curve in the forward direction and the reverse saturation current density is larger than that of the Cu/n-Si diode by a factor of 10. This resulted from the difference of Schottky barrier heights 4). and (D.. The Arrhenius plots of Jo/T 2 (Jo is the reverse saturation current density at a reverse bias voltage of 0.1V) are given in Figs. 8 (a) and (b), which yield barrier heights on n-Si
326
Ry
Meta./n-Si
10'
CA
10-
Fig.
3
-
9.
.
1
V
0
MV)
01
0.2
0.3
V (V)
J-V characteristics of Al, Cu, and TI diodes formed on n-SI and p-SI, at 300K.
Schottky
and p-Si of 0.668eV and 0.470eV, respectively. The sum of these values is 1.138eV and is very close to the energy gap of SI at 0 K (1.14eV), indicating that ideal metal/silicon contacts have been formed by this clean-nitrogen-gas seal processing. Figures 9 (a) and (b) show J-V characteristics of Schottky diodes using Al, Cu, or Ti as an electrode metal on n-type Si and p-type Si, respectively. For n-type Si, the reverse saturation current density increases in the order of Al, Cu, and TI. For p-type Si, on the contrary, the reverse saturation current density decreases in the order of Al, Cu, and Ti. Such behavior is qualitatively explained when we take into account the fact that the sum of the Schottky barrier heights of a metal for n-type SI and p-type Si is equal to the bandgap of Si. Table 1 summarizes the Schottky barrier heights calculated from J-V characteristics for three different electrode metals (Al, Cu, Ti), and two different Si orientation, (100) and (111). From the table, It is obvious that Schottky diodes on (l00)Si have larger (h,,-and smaller Ob. than on (lll)Si except for Cu/n-type SI. The result indicate that the band structures of SI differs on (100) and (111) orientations at the surface or at the metal/SI interface. However, the sum of (D,-- and (D, for each metal is very close to the bandgap of Si at 300K (1.13eV). This fact indicates that the metal/Si interfaces fabricated under clean-N2 -gas seal process realizes nearly ideal metal/silicon contacts. In the case of Cu/n(lll)Si contact, the Schottky barrier height is large by about 0.08eV against all expectation. We have not succeeded in explaining this result yet. In order to explain this result, the different calculation method for the Schottky barrier height are demanded.
327
Table 1. Schottky barrier heights of Al,Cu and Ti and p-type Si substrates for two different orientations.
on n-type substrate
BARRIER HEIGHT (eV) (111)Si
(100)Si A
Ti
I Cu
AL
Cu
Ti
0.837 0.680 0.551 0.821 0.727 0.528
(P
0.607 1.158
1.150
(P-+,b:
0.506 0.634 1.233
1.162
E
U
z I0-V I-
U) W 0)
Fig.
0 Cu/p-Si
I-
cu/n' Si
z 0 0) 10"1 TI/p'-Si
0.2
0.4
0.6
BARRIER IIEIGIrI
A(/rl' S
0.8
10. Contact resistance of various metals on n'and p--Si surfaces. the concentration carrier at the surface of n'-Si 19 or p+-Si is 4x1O cm-' 4xlOOcm-O, and respectively.
1.0
(eV)
Figure 10 shows the contact resistance as a function of n+-or p÷-Si. Carrier for height the Schottky barrier 0 or concentrations at the surface of n+-or p--Si are 4x10 8 (D.. of Al In the case of p-Si, 4xlO- cm-0 respectively. exponential For p-type Si, b--. is calculated by E. dependence of contact resistance on the Schottky barrier height is clearly demonstrated. However, contact resistance The contact (D,.-. of n-type Si seems independent on Qcm2 is measurement limit in this resistance of 3-4x10and the carrier concentration is very high so experiment, •bn is contact resistance and that the relation between not clear. 328
Conclusion The clean-nitrogen-gas seal processing combined with low energy bias sputtering metallization having in-situ cleaning function is most effective to realize ideal metal/silicon contacts. As a result, very low contact resistance of 3x10-1 Q•cm1 is obtained without any heat treatment. Through this study, it is pointed out that the Schottky barrier height is different on (100)Si and (111)Si surfaces. Thus the clean-N 2 -gas seal process conjunction with the low kinetic energy particle process is quite essential for the establishment of a highly reliable and very uniform metallization scheme for ULSI. ACKNOWLEDGEMENTS The authors wish to thank Mr. M. Saitoh for valuable discussions. performed in the Superclean Room Microelectronics, Research Institute Communication, Tohoku University.
Miyawaki and Mr. S. This study was of Laboratory for of Electrical
REFERENCES [1]M. Morita, T. Ohmi, E. Hasegawa, M. Kawakami, and M. Ohwada, J. Appl. Phys., 68, 1272(1990). [21M. Miyawaki, S. Yoshitake, and T. Ohmi, IEEE Electron Device Lett., EDLIl. 448(1990). [3]T.Ohmi, K. Hashimoto, M. Morita, and T. Shibata, IEEE IEDM, 53(1989). [41T. Ohmi, H. Kuwabara, S. Saitoh, and T. Shibata, J. Electrochem. Soc., 137, 1008(1990). [5]A. M. Cowley and S. M. Sze, J Appl. Phys., 36, pp. 32123220, 1965. [6]C. R. Crowell and G. I. Roberts, J. Appl. Phys., 40, pp. 3726-3730, 1969. [7]K. Shenal and R. W. Dutton, IEEE Trans. Electron Devices, ED-35, pp. 468-482, 1988.
329
JUNCTION FORMATION FOR SCALED SUB-MICRON CMOS TECHNOLOGY C.M. Osbu1"2, S. Chevacharoenkul1, and G.E. McGuire' 1
MCNC, Center for Microelectronics, P.O. Box 12889, Research Triangle Park, NC 27709 2
Department of Electrical and Computer Engineering North Carolina State University, Raleigh, NC 27695
The scaling of p+ and e junctions from 1 pm technology down to 0.25 gm technology has been examined. Dopant profiles and sheet resistances were measured as a function of rapid thermal annealing temperature over the range of 650-1050"C for 8 & 10 keV BF 2 , 8 & 10 keV B, and 10-50 keV As implanted single- and poly-crystalline silicon. For the shallowest junctions (<100 nm), preamorphization with either silicon or germanium did not result in shallower junctions. The enhanced diffusion associated with the preamorphization implant damage compensated for the reduction in channeling. Preamorphization did, however, give low sheet resistance junctions and high dopant activation at low (550"C) annealing temperatures. Considerable dopant motion (-50 mn) was observed in the tail region, near the junction, after 10 sec of annealing at a relatively low temperature (800"C). Annealing up to l00O0C resulted in very little additional change in the profiles: only at 1050"C did the high concentration, shoulder region of the profile start to move.
INTRODUCTION The ability to fabricate silicon devices with shallower junctions is a key element in the scaling to achieve smaller, higher performance semiconductor chips. Device scaling theory (1) requires that vertical scaling of film thicknesses, doping profiles, and junction depths follows the same geometrical reduction in dimensions as the scaling of lateral, pattern feature sizes. Other theory (2), where strict scaling is not employed, predicts that the minimum allowable channel length of a MOSFET device, as limited by the short-channel fall-off in threshold voltage, is proportional to the cube root of the product of junction depth, oxide thickness, and doping. Both analyses, however, anticipate that junction depths need to he reduced as device dimensions are decreased. Indeed, junction depths have been decreasing for the past decade as devices have become smaller. The present generation of semiconductor technology, in the 0.8 to 1 pm feature size range, employs junctions in the 200-300 nm range. Current product development is aimed at 0.5 to 0.8 pm technology, suitable for the fabrication of 4-16 Mb DRAMs for instance. This technology is expected to employ junctions that are 100 -200 nm deep. Advanced research, is focussed at pattern dimensions in the 0.1 to 0.5 prm
range, for 64 Mb to 1 Gb DRAM or > 5M transistor logic chips. This focus suggests that junction depths in the tens of nanometers will be needed in the relatively near future. The use of a lightly-doped-drain technology (3,4) or other, more sophisticated drain engineered structures (5) somewhat reduce the importance of the heavily-doped junction in controlling short channel effects, and slightly deeper junctions can often be tolerated. Nevertheless, scaling of these technologies to smaller dimensions also requires junction scaling. In fact, these drain-engineered structures typically require even more stringent control over junction depth and lateral junction motion in particular. Several studies have examined processes that might be employed to extend the state-of-the-art in junction formation. Of particular importance to this work is the earlier attention given to preamorphization (6-23), low energy ion implantation (20,22,24-5), and low thermal budget processing using rapid thermal annealing (7,8,11,13,14,16,18,20,22,25) to achieve shallow junctions. Preamorphization of the silicon 330
substrate prior to low energy implantation of dopant eliminates dopant tails due to channeling, maximizes the electrical activity of the implant at any fixed annealing temperature, and, under the right conditions, can minimize the amount of crystal damage associated with end-of-range ion-straggling that is left in the substrate. Although preamorphization is effective in reducing the depths ofjunctions that are a few tenths of a micrometer deep, recent work (22,25) suggests that ultra-shallow junctions may not benefit from this step. While the introduction of a shallow dopant profile is conceptually straightforward, maintaining such a shallow dopant profile is difficult, largely because of the subsequent enhanced diffusion that occurs during processing. The origin of this enhanced diffusion is the high point defect concentration created by implant damage. These point defects in excess of their equilibrium concentrations contribute to the enhanced diffusion for as long as it takes them to recombine to their equilibrium values. This paper attempts to extend the earlier work on shallow junction formation to even shallower junctions to test the scalability of these processes. Along with a companion paper (43), it attempts to identify those key issues associated with a straightforward reduction in junction depth. Of particular attention in this work is the doping profile measurement, high sheet resistance, and enhanced diffusion associated with ultra-shallow junction formation. EXPERIMENTAL The starting wafers used in this work were <100>-oriented, 0.5-10 fl-cm, p or n type. Prior to the implantation of dopants, the wafers received an RCA-type cleaning in NH 4 OH/HO,, HCI/HO,, and BHF. Blanket wafers or areas on a wafer were used for the physical characterization, e.g. SIMS, TEM, 4 point probe, and patterned areas were used for electrical leakage measurements. Patterned wafers were made using a thick, field oxide on which diode features were photolithographically defined and subsequently wet etched into the oxide. The implantation schedule was based on scaling from a I Jm CMOS process (27) which employed 5 2 germanium preamorphization (85 keV, 2 x 10 /cm ); in that process either n* or p* junctions were formed 2 2 by implantation of 5 x 101 As/cm at 50 keV or I x 10 15 B/cm at 10 keV, respectively. Wafers were given a very low temperature anneal (VLTA) at 450"C for 30 min as suggested by Rozgonyi et al (23) to reorder the amorphous/crystalline interface. The amorphous silicon was recrystallized by a 30 min 550"C furnace cycle, and the final junction anneal used an AG heatpusle rapid thermal annealer for 10 seconds at 1050"C. This process has been previously shown to result m low-leakage diodes having junction depths of about 200 run. As has been widely-reported previously and will be further shown here, the diffusion of dopant species is strongly dependent on their location with respect to the implantation damage and possibly also with respect to the wafer surface. Thus, in any diffusion study, it is critical to define the relative positions of dopant and implant damage, and the companion paper (26) gives extensive cross sectional TEMs to verify the position of the implantation-induced defects. The strategy employed in choosing the implantation energies and doses follows that originally described by Ozturk et al (18,22). The depth of the amorphization is chosen to be slightly greater than the as-implanted junction depth. For the amorphizing and doping species and doses used here, the depth of the amorphization was about twice the range of the amorphizing species, and the as-implanted junction depth was about three times the range of the dopant species. With this junction design, the amount of dopant motion by subsequent diffusion was intended to be equal to the depth of the implanted junction. By having the final junction depth twice as deep as the depth of amorphization, the electrical depletion region of the junction would be physically removed from the ion straggle damage band so that the damage would not be expected the contribute to diode leakage. With this process, dopant diffusion occurs from the region just above the original amorphous-crystalline interface to a region considerably below it. Dopants diffuse from the originally amorphous region through the band of defects and into undamaged silicon below. Table I lists some of the junction processes examined in this work. The processes labeled B, C, and D represent attempts to scale the I pim (A) process by factors of about 0.8, 0.5, and 0.25, respectively. Both the implantation doses and energies are scaled (approximately) by these factors. Due to the lower energy 331
limitations of the ion implanter used in this work, the shallowest p+ junctions were formed from BF 2 rather than boron, giving the additional complexity associated with the presence of fluorine. The implant doses were scaled in order to preserve the same doping concentrations in the shallower junctions. For arsenic, the dose was chosen to maintain the maximum concentration at about the electrical activity limit. Lower boron concentrations were used to reduce its diffusivity so that one common annealing cycle could be used to obtain nearly equal a* and p+ junction depths. In addition, the annealing temperatures are correspondingly reduced to scale the diffusion subsequent to implantation. The preamorphization species was one of the experimental variables examined in this study. Both silicon and germanium were used and compared to wafers receiving no preamorphization implant. The energies of the silicon and the germanium were chosen, as shown in Table I, to produce approximately equal preamorphization depths. Silicon preamorphization was performed with the Hycool end station of a Varian 350D ion implanter to minimize wafer heating. In addition, the silicon implants were restricted to only the shallowest of junction processes where the implant energy and dose were low. Table 1. Fabrication of Scaled Junctions Process
T1nm
Preamorph
P Junctions
N' Junctions R.
liI
X
,IR
X
(W2sq) (mQ)
(rnm)
(~sq)
(C) A-Ge (Ref) A-0
85 keV, 2E15 Ge none
1050 1050
50 keV, 5E15 50 keV, 5E15
55 55
180 180
10keV IEI5 B 10 keV, IEt5 B
140 190
200 320
B-Ge
70 keV, IEI5 Ge
1030
40 keV, 4E15
75
145
8 keV, 8114 B
180
180
C-Ge C-Si C-0
40 keV, 5E14 Ge 30 keV, 5E14 Si none
1000 1000 1000
20 keV, 2E15 20keV, 2E15 20 keV, 2E15
135 152 149
115 80 115
10 keV, 5E!4 BF, 10 keV, 5E14 BF, l0 keV, 5E14 BF,
428 513 505
105 95 105
D-Ge D-Si D-0
25 keV, 4E14 Ge 20 keV, 4214 Si none
950 950 950
15 keV, 1.5115 15keV, 1.5E15 15keV, 1.5E15
157 165 153
80 85 85
8 keV, 4E14 BF2 8 keV, 4E14 BF, 8keV, 4E14BF 2
509 739 546
95 95 90
16
17
2
2
'Junction depth measured at 10 /cm for A & B and at 10 /cm for C & D Selected junctions were clad with titanium silicide to reduce the junction sheet resistance. Since the silicide formation consumes silicon in the junction, the thickness of the silicide was scaled along with the junction depth. In the self-aligned silicide (SALICIDE) process, titanium was evaporated to a thickness of 10 to 30 run on wafers and was subsequently reacted for 120 sec at 650°C in nitrogen. After a selective etch to remove the unreacted titanium metal over oxide regions, the stoichiometric, high-conductivity, C54-phase was formed with an 850"C, 10 sec anneal. Secondary ion mass spectroscopy (SIMS) analyses were done with either the Perkin Elmer 6300 (quadrapole based) or the Cameca IMS-3f (magnetic sector) spectrometer. Depth analysis of ultra-shallow junctions, especially before they are broadened by diffusion, is an important challenge. In SIMS measurements, cascade and recoil mixing can significantly distort the doping profiles. For instance the 8 keV BF, implants, used in this study, impart about 1.8 keV to the boron atoms. Yet, SIMS profiling with 4 keV 02 j 2 keV 0) can transfer 1.9 keV to the boron, sufficient to knock it as far as its original range. In addition to this mixing effect, radiation enhanced diffusion can cause dopants to segregate at surface oxide layers. This effect can be especially important when an 02' beam is used for profiling or when an oxygen flood is used 332
to enhance ion yield. Transients in the sputter ion yield at the sample surface can occur over an appreciable portion of the overall doping profile, making the measurement of the profile peak or integrated dopant especially difficult. As a precursor to this work, the effect of operating conditions (beam energy, current, angle) on the resulting SIMS profiles was recently studied for both the Cameca IMS-3f (28) and the PHI 6300 (29) spectrometers in order to optimize the analysis to produce the shallowest profiles. Despite the optimization of the operating conditions, some profile broadening undoubtedly occurred when measuring the shallowest junctions. Even at the lowest energies and shallowest impact angle, the junction depth as measured at 7 3 101 /cm was larger than the extrapolation of the data to 0 keV beam energy. Very good agreement was obtained between the Cameca and the Physical Electronics instruments as shown in Fig 1. Also shown in Fig I ame simulations of the as-implanted doping profiles as computed with the PREDICT (30) process model. RESULTS AND DISCUSSION In addition to giving the experimental conditions, Table I summarizes two important junction characteristics, namely junction depth and sheet resistivity, obtained for the junctions studied here. Preamorphization and Sheet Resistance As has been widely reported (6-23), preamorphization is effective in reducing or eliminating the channeling of boron during ion implantation. Figure 2, for instance, compares as-implanted boron profiles for 8 keV, 4 x 1014 BF, doses with germanium, silicon, and no preamorphizing implants. The profiles are essentially identical, within the range of normal SIMS variations, for both silicon and germanium preimplants and are considerably deeper without preamorphization. In addition to eliminating the channeling, the preamorphization step increases the activation of boron after annealing, especially at low temperatures. Figures 3 and 4 compare the sheet resistivity of the different junctions with and without preamorphization for boron and arsenic implants. The boron-doped junctions, ranging from 0.2 pm down to below 100 nm, have lower sheet resistance when germanium is used for preamorphization, as shown in Fig 3. When the substrate is amorphized, much of the dopant is activated during the solid phase epitaxial regrowth step at 550"C; higher annealing temperatures have only a modest effect on further reducing the resistivity. In contrast, non-preamorphized regions are heavily damaged and require high temperatures to create vacancies so that dopants can become substitutional and to restore the defected silicon. The differences in Fig 3 between the measured and calculated sheet resistances is greatest at low temperatures where the carrier scattering off of extended damage is greatest in the calculations. Preamorphization of arsenic-doped junctions shown in Fig 4 does not have a significant impact on sheet resistance. Presumably, most of the implanted arsenic would be contained within the amorphous region without the need for Ge or Si preamorphization. It should be noted that the simulated sheet resistance values in Fig 4 are very sensitive to the arsenic dose in the 1-2 x 2 1015/cm range such that Predict simulations at only slightly higher doses than used here give quite good agreement to the experimental values. Figures 3 and 4 can also be used to illustrate one of the issues in temperature control of the rapid thermal annealing process. The sheet resistance of these shallow junctions is such a very weak function of annealing temperature that R, measurements are of little value as a monitor of the process temperature control. The annealing temperature dependence of the sheet resistance of both the p' and the n' junctions is unexpected in relation to values of the accepted solid solubilities of each dopant. The peak concentrations of the shallowest as-implanted dopant profiles using conditions D-Ge from Table I are expected to be about 2 2 8 x 102 As/cm and 2 x 1020 B/cm for the shallowest n' and p' junctions, respectively. This is considerably above the expected activity limit for low temperature (<700oC) anneals; nevertheless, high conductivity junctions are observed at these annealing temperatures. For the highest annealing temperature 3 employed here (1050*C), about 10 20 boronVcm is expected to be electrically active. Indeed, reasonably good agreement is found between simulated values of the sheet resistance and measured values after the 1050'C anneal. The fact that boron-doped junctions had about three times the sheet resistance of the arsenic junctions even though they had only one quarter the dose is explained by the fact that most of the arsenic is inactive. Nevertheless, the solid solubilities of both boron (31) and arsenic (32) are expected to 333
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Depth (nm) Fig 1. Comparison of Cameca IMS-3f and PHI 6300 SIMS profiles of ion-implanted boron (8 keV, 4 x 104/CM2 BF,) and arsenic (15 keV, 1.5 15 2 x 10 /cm ).
Fig 2. Boron depth profiles obtained with 10 2 keV, 5 x 1014 BF2 /cm implants with no preamorphization and with Ge (40 keV, 5 x 10'4) or Si (30 keV 5 x 1014) preamorphization before and after a 10 sec 1000"C RTA.
2000
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e
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Fig 3. Sheet resistance of boron implanted junctions as a function of annealing temperature for different 4 2 junction processes: a) 10 keV, 5 x 10 BF2cm , and b) 8 keV, 4 x 1014 BF2/CM 334
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8 Si Preamorphized -It- Non Preamorphized t- Predict
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Annealing Temperature (°C)
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b)
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Fig 4. Sheet resistance of arsenic implanted junctions as a function of annealing temperature for different 2 2 junction processes: a) 20 keV, 2 x 101 As/cm and b) 15 keV, 1.5 x l105 As/cm drop by over a factor of ten between 1050"C and the recrystallization temperature of 550"C used here. Yet, the sheet resistivity of junctions right after recrystallization at 550C was less than a factor of two higher than after the highest annealing temperature. In fact, for p+ junctions the sheet resistance is highest for intermediate temperature (750-950'C) rapid thermal anneals. Thus, the electrical activity of the dopant is considerably higher than what is predicted by the literature for low and intermediate annealing temperatures, indicating a supersaturation of electrically active dopants and a kinetic limitation of the clustering or precipitation of dopant atoms. The implant dose and energy dependencies of the sheet resistance are shown in Fig 5 for boron junctions from which several important observations can be made. The sheet resistivities of BF,-implanted, Ge-preamorphized Si are relatively independent of both implant energy and implant dose right after the 550°C recrystallization step; implants directly into crystalline silicon show a greater dependence on these 4 2 parameters. Predict simulations of the dopant profile in the low dose, 2 x 101 /cm , 550*C-annealed sample 2 reveal an expected peak boron concentration of 10 M/cm . Using the Antoniadis et al (33) value of the hole 2 mobility at this concentration (53 cm /V-sec) gives a calculated sheet resistance that agrees to within 3% of the experimentally-measured value. For deeper implants (60 keV), Queirolo and Polignano (34) report nearly this same mobility value, with lower implantation doses giving the highest mobility. Thus it is reasonable to assume that all the dopant is active in the low dose samples in this study. Sheet resistance and 4 2 Hall mobility measurements in other low-energy, high-dose (6 keV, 5 x 101 /c'm ) samples likewise found complete activation with only a low-temperature-anneal (35), although the mobility was only 25-35 2 cm /V-sec. After a 950'C RTA step, the junction conductances remain relatively independent of implant energy but scale nearly with the dose. One very striking result is that the low-dose, preamorphized samples, annealed at 950C, had considerably higher sheet resistance (-2x) than those merely recrystallized at 5500C. Thus the high temperature anneal must result in either a deactivation of dopant or a reduction of mobility. Earlier work (35) noted a maxima in the sheet resistance versus annealing temperature characteristics of higher-dose BF,-implanted Si; this behavior was explained by a deactivation of dopant at intermediate temperatures. 14
2
Only at the highest dose studied (6 x 10 /cm ) was the sheet resistance lower after the higher temperature RTA cycle. For this high implant dose, the dopant concentration is expected to exceed the boron 3 solubility limit of 9 x 10tg/cm at 950"C (31). Thus the lower resistance observed after high temperature annealing probably reflects a higher dopant activation. The product of the percent active dopant times mobility is highest for low dose implants and decreases rapidly with dose after the recrystallization step but 335
1400 8 keY BF2 4 X i0'
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U 550TC Annealed M
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o 0 950C RTA
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Fig 5. Sheet resistance of boron-implanted junctions as a function of implant dose at 8 keV or implant 2 4 energy at a dose of 4 x 101 /cm , with and without Ge preamorphization, for final annealing temperatures of 550C (30 min) and 950TC (10 sec). mobility is highest for low dose implants and decreases rapidly with dose after the recrystallization step but has a weaker dependence on the concentration after a 950"C RTA. A dose of 4 x 1014 was seen to be optimum in terms of maximizing both the active dopant-mobility product at both 550"C and 9500C. Higher doses gave only a slight decrease in sheet resistance at the higher dopant concentrations while low doses give considerably higher resistance after high temperature annealing. Figure 6 shows the corresponding dose and energy dependencies for shallow arsenic implants. Both figures show a remarkable similarity in the data either with or without Ge preamorphization. Similar to the boron case, the sheet resistance of 15 keV As implants was relatively independent of the dose after the 550'C SPE step, where it decreased only 10% for a 2x increase in dose. After an additional 950TC RTA 15 2 step, the resistance of the low-dose (10 /cm ) junction increased. Nevertheless, the final conductance of annealed junctions varied considerably sublinearly with dose. The junction conductance scaled nearly as the implant energy. The strong dependence of the sheet resistance on implant energy and the weak dependence on dose are both consistent with the dose being considerably over the electrical activity limit. Dopant Profiles and Diffusion Representative SIMS profiles of boron as a function of annealing temperature are shown in Fig 7 for 10 keV and 8 keV BF, implants into Ge pre-amorphized silicon while arsenic profiles for 20 and 15 keV implants are given in Fig 8. The figures show very little discernible boron diffusion up to 750'C. At 850'C the boron dopant tail diffuses considerably (30-50 rim) while little motion is observed near the peak. This behavior results in a concave dopant profile curve with a very pronounced tail. Surprisingly, higher annealing temperatures did not extend the diffusion in the tail region. Only at the highest annealing temperatures studied here (10 sec at 1000-1050TC) did the peak diffuse. Figure 9 portrays the p+ junction motion as a function of dopant concentration for the different 10 sec annealing temperatures of Fig 7. The junction motion was calculated from the difference in profile depths of the annealed and the implanted profile for each different concentration. Here the junction motion is greatest at the lowest dopant concentration and appears to be continuously increasing as the concentration decreases, at least up to 1000'C. This observation is seemingly at odds with the conventional understanding of concentration dependent diffusion phenomena where the diffusion coefficient increases with the doping concentration for boron. Above 1000*C, the dopant motion near the peak of the concentration becomes comparable to that in the tail region, and a more "normal" diffusion profile is seen. The data show three interesting trends: first the dopant
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is
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cm 2)
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Energy (keV)
Fig 6. Sheet resistance of arsenic-implanted junctions as a function of implant dose at 15 keV or implant 5 2 energy at a dose of 1.5 x 101 /cm , with and without Ge preamorphization. for final annealing temperatures of 550"C (30 min) and 950"C (10 sec). 21 ----
20
850*C 950*c
-\
....... ....... .
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E
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550oc 650oC
f
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I,
5 60 Depth (nm)
75
4 AS
80
90
100
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Fig 7. SIMS profiles of boron as a function of 10 sec annealing temperature for 10 keV, 5 x 1014 BF,/cm 2 2 implanted into 40 keV, 5 x 1014 Ge/cm preamorphized silicon (left) and 8 keV, 4 x 1014 BF,/cm implanted into 25 keV, 4 x 1014 Ge/cm2 (right) The samples were preannealed at 550*C prior to RTA.-
337
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Fig 8. SIMS profiles of arsenic as a function of 10 sec annealing temperature for 20 keV, 2 x l10" As/cm-2 2 implanted into 4-0 keV, 4 x 1014 Ge/cm preamorphized silicon (left) and 15 keV, 1.5 x 105 As/cm implanted into 25 keV, 5 x 1014 Ge/cm2 (right). The samples were preannealed at 550"C prior to RTA. motion is greatest in the tail region for all of the junctions; second the dopant motion can be scaled from the A-D series by scaling the implant energy, dose. and thermal cycle; and third the junction motion is considerably greater for the shallower junctions when the samples are preamorphized with either Ge of Si. This enhanced diffusion resulting from preamorphization greatly diminishes its benefit in providing a shallower junction. Indeed, with the implant conditions illustrated in Fig 2. preamorphization made no difference in doping profiles after 1000'C RTA. The arsenic motion, given in Fig 8. shows a lot of similarities to the boron motion even though the magnitude of the diffusion is smaller. At the lower annealing temperatures, for instance 850'C, the tail of the arsenic moves most rapidly. Only at the highest temperatures does the shoulder move accordingly. The final junction depth is relatively independent of annealing temperature. The arsenic data reveal one other important characteristic, namely less junction motion at some intermediate temperature rather than at lower temperature. The 950'C junction (15 keV As) is shallower than the 850"C one, and the 1000°C junction (20 keV) is shallower than the 850 or 950"C junctions. The non-preamorphized and Si-preamorphized sanmpies in the 20 keV As series also gave deeper profiles after 10 sec 950'C annealing than after 1000lC RTA. As shown by the relative temperature independence of the boron motion at the junction edge in Fig 9. it would appear that scaling the dose and energy are more effective in producing shallower junctions than further reducing the thermal budget. The big issue is the increasing dopant motion at decreasing concentration as if the diffusion increases as the concentration decreases. This seeming anomaly may be partially explained by the fact that the high dopant concentration occurs within the originally-amorphous layer and near the residual band of implantation damage where the diffusion is apparently slower. After only a modest amount of diffusion, the low concentration. dopant tail region is considerably deeper than the damage and experiences a more rapid diffusion. Also as will be described in more detail later (26), the rapid diffusion in the tail region occurs in the temperature range in which the implantation-induced defects are annihilated. The amount of junction motion appears to saturate once the damage is eliminated. The temperature dependence of the junction motion can better be seen in the data shown in Fig 10. Here the junction motion is given for all the shallow-implanted samples (8 & 10 keV BF, series), as meas7 2 ured at 10i T/cm . Extraction of the SIMS data at 1017 was somewhat difficult in several cases because of a combination of measurement noise, associated with profiling such shallow junctions, and the fact that some 338
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Junction Motion (nm)
o
Fig 9. Motion of boron as a function of concentration for 10 keV, 5 x 1014 BF,/cm 2 implanted into 40 keV, 5 x 1014 Ge/cm 2 preamorphized silicon. 0
10
20
30
40
50
60
70
80
Depth (nm)
Fig 11. Fluorine SIMS profiles in silicon (normalized to the Si SIMS signal) after 8 keV, 4 x 14 2 10 BE/cm implantation after 10 sec RTA at different temperatures.
Temperature ( C)
Temperature (°C)
X'.o 2
25
0.7
OB
09 I3/T
1.0
(oK-1)
0.7
0.8
0.9
10/-r (*K-')
Fig 10. Temperature dependence of boron (left) and arsenic (right) junction motion, as measured at 1017/cm2.
339
1.0
profiles exhibited considerable tailing, e.g. see Fig 7. In those cases, the 1017 junction depths were taken from extrapolation of the profile curves between 3 x 1017 associated with this process are believed to be less than 20% and do not qualitatively change the overall observations. Three calculated lines are also shown in the figures for reference: 1) 2 (DI)ia2 representing non-concentration-dependent Gaussian diffusion. 1
2) k(CssDt/ni) /2 representing a constant surface concentration diffusion, where the surface concentration, C ", is taken from the solid solubility values (48,49)), and k= 2.3 for boron and 2.29 for arsenic, respectively. 3) k(QoDt/ni)1/3 representing a constant-source diffusion with a concentration dependent D, where Qo is taken as the implant dose, and k=4.72 for boron and 2 for arsenic, respectively. Several important observations can be made from the data in Fig 10 which represent a composite of samples implanted at different energies and having different pre-amorphization conditions. First from the applications viewpoint, a boron junction motion of 40-70 nm was typical, indicating a possible limit to the future scalability of device junctions even using low thermal budget processing. Even at a very low RTA temperature, the junction motion was usually more than 10 nm. The boron junction motion was the least in the non-preamorphized samples (solid squares and open triangles in Fig 10). No obvious effect of the preamorphization was seen on the arsenic junctions. Somewhat surprisingly most of the boron data were bracketed by the concentration-dependent solutions of the diffusion equations for the constant-surfaceconcentration and the constant-source approximations. It is apparently not necessary to invoke mechanisms, such as ion-implantation-induced defect generation, to explain the magnitude of the observed diffusion. Clearly such an observation seems at odds with the preamorphization enhancement of diffusion and cannot readily be explained here. The arsenic motion was often greater than could be predicted on the basis of simple theory. Process simulations using Predict 1.5 (30) show a region of decreasing junction depth with increasing temperature. The magnitude of the effect is predicted to be greater for arsenic diffusion than for boron. Indeed, this is experimentally observed: arsenic motion is relatively low in the 950- 1000'C range, and no such effect could be confirmed for boron. The motion of the germanium used for preamorphization was also studied. After 10 sec 1050'C rapid thermal annealing, the germanium motion two orders of magnitude below the peak concentration was 2 less than 2 nrni. This corresponds to a diffusion coefficient less than 10.15 cm /sec or nearly an order of magnitude less than the literature value (36). Quite obviously there appears to be no enhancement of the germanium diffusion. The diffusivity of fluorine from the BF, can be taken from the data in Fig 11 where the fluorine diffuses out of the sample after high temperature annealing. Below 1050"C, where almost all of the fluorine has evaporated, the fluorine profiles are relatively parallel. Analysis of the motion of these curves toward the surface gives a fluorine diffusivity of Ilx0 exp(-4.2eV/kT). Only minor evidence was seen for a second fluorine peak 50-60 run deep, presumably decorating the end-of-range damage from the preamorphization. For BF, implants given a 10 sec 950'C RTA, the junction depth was found to be relatively indepen2 dent of both energy in the range of 8 to 13 keV implants and dose from 2-6 x 1014/cm . The measured 5 values are the same within the limits of the SIMS measurement. Likewise doses from t-2 x 101 /cm 2 of 15 KeV made no discernible difference in junction depth. However, variation of the implant energy from 10 to 20 keV did increase the junction depth by almost 20 run. Significant losses (up to 40%) of arsenic can occur during the junction formation process. The loss is most acute for the shallowest (lowest energy) implants.
SUMMARY Different processes for the formation of n' and p+ junctions from 200nm down to less than 50 rin deep have been studied, with an emphasis on sub 100 nm junctions. Preamorphization with either germanium or silicon is effective in reducing the channeling associated with the implantation of boron. 340
Furthermore, the solid-phase-epitaxial regrowth process leads to lower sheet resistances in preamorphized junctions, especially for low annealing temperatures. Higher annealing temperatures had only a minor effect of further reducing the sheet resistance of such junctions. Surprisingly, low dose implants of boron or arsenic into preamorphized silicon gave higher sheet resistance after a 10 sec 950"C RTA than they exhibited after the 550C SPE step. For boron the difference was 40%, suggesting that at most 60% of the dopant was active after 950'C annealing. For BF2 implants, the results further show that the fraction of active boron falls off rather dramatically as the dose, for an 8 keV implant, is increased from 2 to 6 4 2 xl01 /cm . Both boron and arsenic exhibited enhanced diffusion behavior. Boron motion was not observed below 750"C; however, a very rapid motion (-50 nm) of dopant in the tail region was observed at temperatures as low as 850"C for 10 sec RTA times. This enhanced diffusion was associated with the preamorphization implant. While the preamorphization of deep (100 nm) implants was effective in producing a shallower junction after annealing than non-preamorphized implants, the enhanced diffusion caused by preamorphization of shallower implants (<80 nm) was as large or greater than the advantage due to a reduction in channeling. After the rapid motion of the junction tail at low temperatures, annealing up to 1000°C had little further effect on the junction profile; only at 1050°C was there considerable diffusion. At this high temperature, the dopant motion was at the shoulder of the profile, while the tail (at the junction depth) was relatively stationary. Composite plots of the junction motion showed that even with low temperature RTA, it is not really possible to avoid 20-40 mn of motion of As and 30-60 nm of B diffusion. For the most 2 part, the junction motion data for boron were bounded by the constant-surface-concentration (Ax. - (Dt)t/ ) and the constant-source (Axj - (Dt)tf3) approximations for concentration dependent diffulsion. The observed arsenic motion was generally greater than could be explained by the latter diffusion.
ACKNOWLEDGEMENTS The authors would like to thank R.B. Fair for his helpful critique of the manuscript. In addition they are grateful to the staff of the MCNC silicon processing facility, particularly R. Stokell and J.-B. Yan, for the sample fabrication. Samples and data for the B series wafers were provided by M. Kellam and C. Herring. SIMS profiling was done at either the MCNC or the NCSU analytical facility by J J. Lee, J. Fulghum, M. Ray, D. Griffis, S. Corcoran, and J. Hunter. Diode leakage measurements were performed by J. Arppe. Rutherford backscattering analyses were made at UNC-Chapel Hill by B. Patnaik, N. Parikh, and M. Swanson. REFERENCES
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(36)
D.L. Kendall and D.B. DeVries, Semiconductor Silicon 1969, ed. R.R. Haberect and W.L. Kern, The Electrochemical Society, 414, (1969). 342
STABILITY OF TiB 2 AS A DIFFUSION BARRIER ON SILICON C.S. Choi*, G.C. Xing**, G.A. Ruggles*, C.M. Osburn*,+, A.S. Shah*, and J.D. Hunn++ *Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27695 **Department of Material Science and Engineering, North Carolina State University, Raleigh, NC 27695 +MCNC, Centerfor Microelectronics, P.O.Box 12889, Research Triangle Park, NC 27709 ++Department of Physics and Astronomy, University of North Carolina, Chapel Hill, NC 27599 The stability of low pressure chemical vapor deposited TiB2 films has been investigated for their potential use as diffusion barriers between Al or Cu metallurgy and the silicon substrate during post metal annealing at temperatures ranging from 450 - 650'C for A], and 500 - 800'C for Cu. Although no evidence of intermixing was observed via Rutherford backscattering spectroscopy (RBS) for TiB2/Si samples rapid thermal annealed (RTA) up to 1080'C, pyramid shape pits in the silicon, bounded by (111) planes were observed using transmission electron microscopy (TEM) for the samples annealed above 950'C. SIMS depth profiles of B in silicon originated from the TiB 2 solid source suggested enhanced diffusion after rapid thermal annealing. According to RBS spectra coupled with scanning electron microscopy (SEM) examination, AI/TiB 2 /Si (preannealed) stacks appeared to be stable up to 500°C for 30 min in forming gas. For the stacks with as-deposited (amorphous) TiB 2 films, plan-view SEM of Al/TiB 2/Si showed very limited reaction with A] up to 600'C, in good agreement with sheet resistance measurements. The as-deposited, amorphous TiB2 films were superior diffusion barriers compared to the annealed, polycrystalline TiB2 . No interaction took place between sputtered Cu and an underlying, amorphous TiB 2 film up to 7501C, 30 min in vacuum. Plan-view SEM, RBS, and sheet resistance measurements showed that the structure started to break down at 7750 C. INTRODUCTION To accommodate more devices per chip, device dimensions have been shrinking for the last 20 years. As feature sizes are scaled down according to scaling theory, both lateral scaling, as well as vertical scaling (reduced oxide thickness and shallow junction formation) are required to ensure proper device operation. The reduction in vertical dimension imposes severe constraints on the extent of permissible interaction between metal layers and the underlying semiconductor. Due to the concomitant reduction of junction depth and contact hole size, the interaction between the currently used contact metallurgy, Al, and the underlying semiconductor is a serious concern, because such interaction may lead to junction shorting or to compound formation with a resulting high contact resistance. The performance of Al metallization can be improved by adding small percentages of silicon -nd copper (or titanium), but the specific contact resistivity has been found to be inadequate for multilevel metallization for ULSI due to precipitated silicon. 343
High contact resistance to ultra-shallow junctions can severely limit overall device performance; thus, interaction between contact metallurgy and underlying Si should be carefully controlled. To this end, a diffusion barrier material is often included in the metallization scheme. There is a constant search for new metallization materials with improved contact characteristics as well as enhanced barrier properties which will permit each metal film to perform its intended function while maintaining its integrity during subsequent device processing and operation. Therefore, barrier layers are an increasingly important component in ULSI metallization. The primary requirements for a thin-film diffusion barrier would be to be "atomically opaque, and electronically transparent" [1]. However, the electronically transparentrequirement (low resistivity) is generally not of primary concern because the thickness of a diffusion barrier is typically only about 100 nm. Meeting the electrical requirement for a diffusion barrier is relatively easy; even poor electrical conductors (= I mK2-cm) are admissible for this purpose [2]. More important, however, is a low contact resistivity for a barrier layer used as an ohmic contact to silicon. Low contact resistance usually requires the thermal stability of the diffusion barrier (the atomically opaque requirement) between Si and overlying metal [3]. The barrier material must remain stable, maintaining the metal/barrier/silicon structure up to the temperature of post-metallization processing, which has tended to increase as more levels of metallization are employed, and as more annealing is required to remove radiation damage in oxides. Several types of materials have been employed as diffusion barriers, including noble and near noble metals [4,5], refractory metals [6], silicides [7], and nitrides. In particular, various titanium based compounds, i.e. TiSi2 [8], Ti-W [9,10], TiN [11] and even Ti [12-14] have been examined for diffusion barrier applications. Nitrides, borides, and carbides of refractory metals have also been suggested as possible candidates for passive diffusion barriers because they are chemically and thermodynamically stable interstitial compounds with low resistivities [1]. Titanium nitride is a commonly used material. It has extremely high thermal stability and resists silicon interdiffusion at temperatures up to 600'C for 20 hours [15]. The contact resistance is low and stable when used with a titanium silicide layer: barriers of AI/TiN/TiSi 2/Si fail only above 550 to 600'C due to reaction of aluminum with the barrier layer material, forming AIN and A13 Ti [16]. Significant intermixing has been observed to take place during 600'C annealing [17]. Similar to TiN, ZrN thin films have been found to be impermeable barriers to Si atoms up to 5500 C [18]. Titanium diboride is~an interesting potential candidate for ULSI metallization applications due to its high electrical conductivity and excellent chemical inertness at high temperatures. The resistivity of bulk polycrystalline TiB 2 (=-10 j.tf2-cm) is lower than that of other potential barrier materials, silicides, and nitrides, and only slightly higher than that of tungsten. These properties make TiB 2 a potential candidate for diffusion barrier applications. The study of titanium boride as a diffusion barrier has apparently been quite limited. Blom [19] et al. reported that reactive sputtered TiB 1 .6on silicon showed some weak X-ray diffraction lines corresponding to a TiSi 2 phase after a 800'C heat treatment, indicating that excess titanium in the boride film reacted with the underlying silicon substrate to form a titanium silicide layer. For TiB2 .3 no change in film composition was noticeable during heat treatment. The RBS spectra showed that A1/TiB 2/Si structures were stable after 610 0 C, 30 min heat treatments, and AES depth profiles indicated that the TiB2 /Si interface became less sharp during a 620'C, 30 min heat treatment, probably due to grain growth or a small amount of intermixing. For Al/TiB2/Ti/Si structure, the RBS spectra indicated that titanium silicide formation took place during a 610'C, 30 min heat treatment, but the barrier was not seriously affected. A stack of titanium boride/Si appeared 344
stable at 1092 0 C when examined via RBS, but TiB films reacted with the silicon substrate after a 890'C heat treatment [20]. In this work, the temperature stability of TiB 2 films has been investigated for their potential use as a diffusion barrier between Al or Cu metallurgy and the silicon substrate. As a part of the stability study, the diffusion of boron from TiB 2 into silicon was
examined.
EXPERIMENTAL The TiB 2 films were deposited by LPCVD on lf2-cm p-type or n-type Si substrates. The detailed process conditions were: 600'C, 1 Torr, 10% B 2 H6 in H2 = 250 seem, TiC14 =25 seem (B/B+Ti= 0.67). The experimental set-up and deposition procedures are described in more detail elsewhere [21]. TiB2 was the only phase deposited at the given conditions, and the composition of the deposited films was stoichiometric. The TiB 2 /Si stacks were annealed in a vacuum furnace for 30 minutes at temperatures up to 1000'C or rapid thermal annealed for 10 sec up to 1080'C to investigate the thermal stability. To determine the stability of TiB 2 to Al, a 165nm thick layer of Al (purity 99.999%) was evaporated onto the pre-annealed, polycrystalline TiB 2 (RTA 1080'C, 10 sec in Ar) or onto as-deposited, amorphous TiB 2 films. The thickness of Al was chosen such that the aluminum signal and the TiB2 signal would not overlap in the RBS spectrum. The stacked samples were furnace annealed in the temperature range of 450-650'C in forming gas for 30 min. The stability of TiB2 between Cu and Si was also investigated. A 150nm layer of Cu was sputtered or evaporated onto as-deposited (unannealed) TiB 2 on Si. The stacks were then annealed up to 800'C for 30 min in vacuum. The stability of the TiB2/Si and Al or Cu/TiB2/Si stacks was characterized using various surface and bulk film techniques, such as Rutherford Backscattering Spectroscopy (RBS), cross-sectional transmission electron microscopy (XTEM), electron diffraction, and X-ray diffraction (XRD). Planview SEM was employed to examine the surface of Al (or Cui), TiB2, and/or Si after removing each overlying layer one by one. Sheet resistance measurements of stacked samples after annealing were used to check the stability of TiB 2 electrically. Boron diffusion profiles in the silicon following 10 second isochronal anneals were obtained by Secondary Ion Mass Spectroscopy (SIMS) using the PHI 6300 after the TiB 2 films were stripped in 30% H20 2 . RESULTS
AND DISCUSSION
The barrier properties of RTA annealed TiB 2 films were examined by the use of Rutherford Back Scattering Spectroscopy (RBS). The RBS spectra, shown in Figure 1, showed no evidence of intermixing in TiB 2 /Si samples RTA-annealed up to 1080°C in argon for 10 sec. Samples annealed for 30 min in a vacuum furnace also appeared to be stable up to 1000°C. The slight difference seen in the spectra is due to the slight difference in TiB2 film thickness for each sample. Even though TiB 2 appeared to be stable with respect to Si according to RBS, cross-sectional TEM was employed to detect any local reaction at the interface of TiB 2 and Si, and the results are shown in Figure 2. In the asdeposited TiB2 sample, a locally strained area was observed at the interface of TiB 2 and Si, but no interaction was observed for samples annealed below or at 850'C. Pyramid shaped pits were observed at the Si interface for the samples annealed above 850'C. For the film annealed at 950'C, most of the pits were bounded by (111) planes, with a few having 345
rounded edges. However, the pits were larger and more clearly defined after annealing at 1080*C, and the strained areas were no longer visible. This indicates that the pits grew during high temperature annealing, and their growth was probably enhanced by the stress generated between films due to the difference in thermal expansion coefficient. Plan-view SEM was used to examine the surface of the underlying Si after removal of the TiB2 films for both the as-deposited sample and the annealed samples (See Figure 3). No pits were observed on the Si surface in the samples annealed below 850'C. The samples annealed at 1080'C contained well-defined rectangular pits, while the pits observed in the samples annealed at 950°C were irregular in shape. Apparently, annealing at 950'C for 10 sec was insufficient for the formation of well-defined pits. The presence of such pits may indicate that TiB2 reacted with Si during annealing to form a compound such as SiB 6 or titanium silicide. In fact, a series of SiB6 lines were observed in the X-ray diffraction pattern for this sample, while no titanium silicide lines were observed. Al/TiB 2/Si stacks were investigated for diffusion barrier applications. Some of the TiB2/Si stacks were pre-annealed using RTA at 1080'C for 10 sec prior to evaporation of aluminium. The grain size of TiB 2 after the RTA measured approximately 40nm. The effect of such annealing on the grain growth of TiB 2 has been discussed in detail elsewhere [221. According to the RBS spectrum of AI/TiB 2 /Si shown in Figure 4, the stacks annealed at 550 0 C for 30 min in forming gas appeared to be stable and evidence of failure was not observed until 600'C. However, for the samples annealed at 550'C, SEM revealed the presence of pin holes of =0.5 lim diameter on the surface of the Al layer (Figure 5c). Such pin holes were not evident on samples annealed at lower temperatures (Figure 5a,b). After the aluminum layer was stripped off, Energy Dispersive X-ray analysis (EDX) revealed that residues, containing a large amount of Al, were present on the TiB 2 surface. The formation of A13Ti was detected by X-ray diffraction, indicating that the Ti in TiB 2 reacted with Al to form AI3 Ti. As seen in Figure 5d, the samples annealed at 600'C were found to have large bumps on the film surface, and the films were not etched completely in aluminum etchant. The Al signal measured on the bump was stronger than that of the underlying Si. A weaker aluminum signal was detected on the surface between bumps, which was still stronger than that which was detected on residue on the samples annealed at 5500 C. This indicates that the reaction to form A13Ti was very pronounced in samples annealed at 600'C, a finding supported by the higher intensity of AI 3Ti peaks in the X-ray diffraction patterns. No evidence of Al/Si product formation was found in the X-ray diffraction patterns or the electron diffraction patterns, even for the 600'C annealed sample. Since diffusion in polycrystalline material is usually dominated by grain boundary diffusion below the Tammann temperature (typically one-half or two-thirds of the melting temperature of a solid), the stability study was repeated for the as-deposited, TiB 2 diffusion barrier, which was an amorphous, or extremely fine grained polycrystalline (= 3nm) phase. The aluminium surface of AI/TiB 2 /Si stacks annealed at various temperatures in forming gas for 30 min were examined using plan view SEM, and the results are shown in Figure 6. The sample annealed up to 600'C showed very limited reaction between aluminum and TiB 2 (Figure 6a - e); however, an extended interaction was observed on the Al surface for the samples annealed at 650'C, as seen in Figure 6f. Sheet resistance was also measured on these samples, because it is a very simple and sensitive technique to detect the presence of any reactions of the conducting films. Figure 7 shows sheet resistance of the stacks as a function of annealing temperature. No significant change in sheet resistance was observed for the samples annealed up to 600'C. For the sample annealed at 650°C, a significant increase in sheet resistance was observed, in good agreement with the SEM results. Thus, the as-deposited, amorphous TiB 2 films exhibited superior diffusion barrier properties between Al and Si as compared to the annealed, polycrystalline TiB2 films. 346
The stability of TiB 2 to sputtered Cu was investigated at various annealing temperatures. The as-deposited, amorphous TiB 2 films were used as a diffusion barrier in these experiments because of their superiority in the Al experiments. Initial RBS results revealed that no interaction took place between Cu and the underlying TiB 2 for samples annealed at 750'C in a vacuum furnace for 30 min, as shown in Figure 8. The structure, however, started to break down at 775'C. Plan view SEM was employed to examine the
Cu surface of Cu/TiB2/Si stacks annealed at various temperatures (Figure 9). The holes seen on the surface of annealed samples presumably resulted from release of Ar, trapped in the sputtered Cu film during annealing. Neglecting these artifacts of sputtering, no interaction was noticed on the Cu surface for samples annealed at temperatures up to 750'C (Figure 9a-c) At an annealing temperature of 800'C, a significant reaction was observed on the Cu surface under SEM examination, as evident in Figure 9d. However, within the signal to noise limit, X-ray diffraction failed to identify any new phases created by this reaction. In Figure 10, the sheet resistance of the Cu stacks is shown as a function of annealing temperature. The initial drop in resistance is associated with the annealing of defects and the release of trapped gases in the sputtered metallic films and the resistivity can be seen to reach its lowest value at 650'C. The sheet resistance dramatically increased above 750'C, in good agreement with both the RBS spectrum and SEM examination. Diffusion of boron into silicon from the solid-source TiB 2 layer was also studied, as this is an important consideration for contact applications, particularly to n-type Si. The SIMS depth profiles of boron shown in Figure 11 reveal a very high surface concentration, particularly when the TiB 2 was annealed for 10 sec at 1050'C. This layer probably reflects the formation of an SiB 6 layer as observed in XRD. After correcting the data to compensate for the SIMS instrumental broadening with no anneal [23], a junction depth of 0.11 gm was measured at 10 18 /cm 3 after a 10 sec 1050'C anneal. Using classical diffusion theory [24] for constant-source diffusion with a concentration dependent diffusivity, this junction depth corresponds to an effective diffusivity of 2.4 x 10-13 cm 2/sec, which is a factor of 3 greater than the conventionally accepted value of the boron diffusivity [25]. Because og this rapid boron diffusion, a shallow N+ junction could be compensated with boron from a TiB 2 top layer during a high temperature annealing, resulting in a low surface concentration of electrically active donors. The contact resistance of TiB2/N+ might then be expected to be very high. On the other hand, TiB 2 offers the potential of being a good solid diffusion source for P+ junction formation. Electrical characterization of these junctions is the subject of a future publication [26]. CONCLUSIONS The stability of LPCVD TiB 2 films has been investigated for their potential use as diffusion barriers between Al or Cu metallurgy and a silicon substrate during post metal annealing at temperatures ranging from 450 - 650'C for Al and 500 - 800'C for Cu. The RBS spectra showed no evidence of intermixing in TiB 2/Si samples annealed in RTA up to 1080'C in argon for 10 sec, and samples annealed for 30 min in a vacuum furnace also appeared to be stable up to 1000'C. Even though TiB 2 appeared to be stable with Si in RBS, pyramid shape pits, bounded by (111) planes, at the Si interface were observed using TEM for the samples anr ealed above 950'C. A series of SiB 6 lines were shown in X-ray diffraction patterns on this sample, but no crystalline silicide lines were observed. Therefore, the annealing temperature should be lower than 850'C to maintain the stability of TiB2/Si stacks. According to the RBS spectrum and SEM examination of AI/TiB 2 (pre-annealed)/Si stacks post-metal annealed at 500'C for 30 min in forming gas appeared to be stable, and 347
evidence of degradation was not observed until 550*C. In the sample annealed at 550 0 C, the formation of A13Ti was detected by X-ray diffraction analysis, and the reaction was very pronounced in samples annealed at 600'C. For the stacks with as-deposited (amorphous) TiB2 films, plan-view SEM of A1/TiB 2 /Si showed only a very limited reaction on the Al surface for 600*C annealed samples, and an extended interaction was observed for the samples annealed at 650'C. Sheet resistance measured at each annealing temperature was found to be in agreement with SEM observations. Consequently, the as-deposited, amorphous TiB 2 was found to be a superior diffusion barrier between Al and Si. No interaction took place between sputtered Cu and the underlying, amorphous TiB 2 film for vacuum anneals up to 750'C for 30 min, and the structure started to break down at 775°C based on RBS, plan-view SEM of the Cu surface, and sheet resistance measurements. The SIMS depth profiles of boron in silicon from the solid-source TiB 2 layer shows a very high surface concentration, with a junction depth of 0.11 l.tm measured after a 10 see 1050'C annealing. The diffusivity of boron was a factor of three greater than the conventionally accepted value of the boron diffusivity. ACKNOWLEDGEMENTS This work has been supported by the the NSF Engineering Research Center Program through the Center for Advanced Materials Processing (Grant CDR 8721505), the Semiconductor Research Corporation (Contract #89-MP-132), and MCNC. The authors gratefully acknowledge helpful discussion with J.J. Wortman and A. Reisman of the Nanometer Engineering Laboratory of NCSU/MCNC. They would also like to thank Nalin Parikh, Richard Chapman, J. B. Posthill, and P.L. Smith for technical assistance. REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
M-A. Nicolet, Thin Solid Films, 52, 415 (1978). M-A. Nicolet, in Tungsten and Other Refractory metals for VLSI Applications 11 , edited by E.K. Broadbent, 19, (Materials Research Society, Pennsylvania, 1987). M. Wittmer, Thin Solid Films, 107, 99 (1983). K. N. Tu, and J. W. Mayer, in Thin Films- Interdiffusion and reactions,edited by J. M. Poate, K. N. Tu, and J. W. Mayer, The Electrochemical Society, Princeton, 359 (1978). J. E. E. Baglin, and J. M. Poate, in Thin Films- Interdiffusion and reactions, edited by J. M. Poate, K. N. Tu, and J. W. Mayer, The Electrochemical Society, Princeton, 305 (1978). 0. Thomas, A. Charai, F. M. D'Heurle, T. G. Finstad, and R. V. Johsi, Thin Solid films, 171, 343 (1989). M. P. Lepselter,and J. M. Andrews, Ohmic Contacts to semiconductors, edited by B. Schwartz, 159 (The Electrochemical Society, Princeton, NJ, 1969). C. Y. Ting and M. Wittmer, J. Apple. Phys., 54, 937 (1982). C. Canali, G. Celotti, F. Fantini, and E. Zanoni, Thin Solid Films, 88, 9, (1982) C. Y. Ting and M. Wittmer, Thin solid films, 96, 327 (1982). N. Yokoyama, K. Himode, Y. Homma, J. Electrochem. Soc., 138, No. 1, 190 (1991). R. W. Bower, Appl. Phys. Lett., 23, 99 (1973). C. Y. Ting and B. L. Crowder, J. Electrochem. Soc., 129, 2590 (1982). R. K. Nahar, N. M. Devashrayee, and W. S. Khokle, J. Vac. Sci. Technol. B 6 (3), May/Jun, 880 (1988). 348
[15] [16] [17] [18] [19] [20] [21] [221 [231 [24] [25] [26]
M. Wittmer, and M. Melchior, Thin Solid Films, 93(3/4), 397 (1982). M. Wittmer, Journal of Vacuum Science and Technology, A3, 1797 (1985). C. Y. Ting, J. Vac. Sci. Technol., 21, 14 (1982). L. Krusin-Elbaum, M. Wittmer, C. Y. Ting, and J. J. Cuomo, Thin Solid Films, 104, 81 (1983). H.-O. Blom, T. Larsson, S. Berg, and M. Jostling, J. Vac. Sci. Technol. A 6 (3), May/Jun, 1693 (1988). J. G. Ryan, S. Roberts, G. J. Slusser, and E. D. Adams. Thin Solid Films, 153, 329 (1982). C. S. Choi, G. A. Ruggles, C. M. Osburn, and G. C. Xing, submitted to J. Electrochem. Soc. (1990) C. S. Choi, G.C. Xing, and G. A. Ruggles, C. M. Osburn, submitted to J. Appl. Phys. (1990). H. Jiang, C.M. Osbum, Z. -G. Xiao, G. Mcguire, and G.A. Rozgonyi, submitted to J. Electrochem. Soc. (1990). R. B. Fair, J. Electrochem., Soc., 122, 800 (1975). S.K. Ghandi, in VLSI FabricationPrinciples,130 (Wiley, New York, 1983). C. S. Choi, Q.F. Wang, C.M. Osburn, G.A. Ruggles, to be published.
I
000
Enr
I=
10
IsaW
Ener.gy (KV)
Fig. 2. Cross-sectional TEM showing the formation of pyramid shaped pits bound by (111) planes at the interface of TiB 2 and Si formed during 10 sec RTA in Ar above 950'C.
Fig. 1. RBS spectra of as-deposited TiB 2 film on Si, after 10 sec RTA anneal at 1080'C, 10 sec in Ar, or vaccum furnace anneal at 1000°C for 30 min.
349
4000 3000
C
..
550-C
1000 0 300
500
700
900
1100 1300 1500
Energy (KeV) Fig. 4. RBS spectra of Al/TiB 2 /Si after post-metal anneal at temperatures up to 600°C in forming gas for 30 min. The TiB2/Si stacks were preannealed using RTA at 1080'C for 10 sec prior to Al evaporation.
Fig. 3. Plan view SEM of pits on Si surface formed during 10 sec RTA in kUT UUUvV
.U
Fig. 5. Plan view SEM of the surface of AI/'iB2ISi samples after post-metal anneal at temperatures up to 600°C in forming gas for 30 min. The TiB 2 /Si stacks were preannealed using RTA at 1080*C for 10 sec prior to Al evaporation. 350
Fig. 6. Plan view SEM of the surface of AVl'iB2/Si samples after post-metal 0 anneal at temperatures up to 650 C in forming gas for 30 min. Asdeposited, amorphous TiB 2 films were used.
10 o As-deposited
6000 I
1
-
4000
o
750*C
-
775 =C
" 800°c
A 200D 0.1
o
0 300
1o0200
300 400 500 600 700 Temperature (*C)
600
900 1200 Energy (keV)
1500
Fig. 8. RBS spectra of Cu/TiB 2 /Si after post-metal anneal at temperatures up to 6000 C in forming gas for 30 min. The TiB 2 /Si stacks 0were preannealed using RTA at 1080 C for 10 sec prior to Al evaporation.
Fig. 7. Sheet resistance of A1/TiB 2 /Si stacks as a function of annealing temperature. Post-metal anneals were performed at temperatures up to 650 0 C in forming gas for 30 min. As-deposited, amorphous TiB 2 films were used.
351
Fig. 9. Plan view SEM of the copper surface of Cu/TiB 2 /Si stacks annealed in a vacuum furnace for 30 min at various temperatures. •55
*/0
10
U.
I
I
I0
C'
I
0.1
0
200
400 600 800 Temperature (°C)
1000 0
Fig. 10. Sheet resistance of Cu/TiB 2/Si stacks as a function of annealing temperature. Post-metal anneals were done at temperatures up to 650uC in forming gas for 30 min. The TiB 2 films in these stacks are amorphous.
50 100 Depth (am)
M50
Fig. 11. SIMS profile showing boron diffusion from TiB2 into p-type silicon. As- deposited at 6000 C, 3 Torr, B/B+Ti = 0.67 input gas mixture, and after 1050TC, 10 sec RTA.
352
POLARITY EFFECTS ASSOCIATED WITH WEAROUT AND BREAKDOWN IN THIN SILICON OXIDE FILMS* D. J. Dumin, J. R. Cooper**, K. J. Dickerson**, N. B. Heilemann**, P. A. McAllister** Center for Semiconductor Device Reliability Research Department of Electrical and Computer Engineering Clemson University Clemson, South Carolina 29634-0915
ABSTRACT The wearout and breakdown of thin silicon oxide films was studied as a function of the gate polarity. It was shown that the wearout of the films was independent of stress polarity. The breakdown, whether measured by ramp I-V breakdown voltage or by the charge-to-breakdown from either ramp IV or by TDDB, depended on the stress polarity. The wearout was determined by charge trapping throughout the oxide and by interface generation and charge trapping at both oxide interfaces. The breakdown process appeared to be initiated at the electron injecting contact. INTRODUCTION The wearout and breakdown of thin silicon oxide films has been extensively studied, particularly as dielectrics have become thinner and applications such as EEPROMs require operation at high voltages and fields. The ramp breakdown voltage has been shown to be a function of both the oxide thickness and the ramp rate.[1] During the high voltage stress leading to breakdown it has been shown that electrons were trapped in the oxide [2] and that interface traps were generated at the silicon-oxide interface.[31 It also has been shown that interface traps were generated at the polysilicon-oxide interface.[41 The polarity dependence of breakdown voltage has been measured and the higher breakdown voltages associated with positive stress voltages have been attributed to the reduced asperities at the silicon-oxide interface.t5] We have been studying thin oxide wearout and breakdown. In this paper we will describe the polarity dependence of wearout and breakdown caused by tunneling of electrons through the oxide. The differences between the polarity dependence of wearout and breakdown will be discussed. EXPERIMENTAL The capacitors used in this study were fabricated using a LOCOS process and n+ silicon gates. The silicon was 2 to 5 ohm cm p-type or 0.5 to I ohm cm n-type. The thin silicon oxide was systematically varied from 8 nm to 12 nm. The capacitor areas varied from
353
4 x 10-6 cm 2 to 1 x 10-3 cm 2 . The oxides described in this paper were grown in dry 02. Oxides grown in wet 02 have shown similar voltage dependences as described below. Both I-V and C-V techniques were used to characterize the films. The I-V characteristics were measured to breakdown using ramp voltage rates of 0.2 V/step, 0.2 sec/step. Slower sweep rates resulted in lower breakdown voltages, but approximately the same charge-to-breakdown (QBD). The capacitors were stressed at constant voltages and the QBD was obtained by integration of the tunneling current that flowed through the oxide. The time integral of the current through the oxide will be referred to as the fluence. The QBD measurements taken at constant stress voltages were compared with the QBD measured during the ramp I-V measurements. Both measurements were performed for both positive and negative gate polarities on the p-type and n-type substrates. Quasi-static C-V (QSCV) and high frequency C-V (HFCV) measurements were used to characterize the mid-gap interface trap density, the energy distribution of the interface traps, and the flat band voltage shifts caused by the constant voltage stressing. To avoid inaccuracies in interpretation of the interface trap distribution derived from the QSCV data, only the changes in the mid-gap density were used to characterize wearout.[6] It was observed that the shift in the flat band voltage after stress was a function of the stress polarity, the fluence during the stress, and the surface potential of the silicon-oxide interface after the stress. Thus, the stress induced shifts in the flat band voltage were not used for characterizing wearout. RESULTS A set of typical QSCV characteristics before and after constant fluence stressing have been shown in Figure 1. The energy distribution of interface traps associated with these QSCV characteristics have been shown in Figure 2. The interface trap distribution measured by the QSCV technique was accurate only near mid-gap.(6) Similar data were taken on the p-type and n-type wafers following both positive and negative gate voltage stressing. The range of stress voltages was from +5.5 V to +12 V and from -7 V to - 14 V. The range of fluences was from 0.000001 C/cm 2 to 12 C/cm 2 . The fluence dependence of the change in the mid-gap interface trap density derived from the QSCV data has been shown in Figure 3 for capacitors fabricated on p-type substrates and in Figure 4 for capacitors fabricated on n-type substrates. The number of interface traps generated by the stress was independent of stress polarity and substrate type. The interface trap generation rates in states / ev / C have been shown in Figure 5 for all of the data shown in Figure 3 and Figure 4. The interface trap generation rate dropped as the fluence increased and was proportional to the inverse square root of the fluence (fluence (-1/2)). At every stress voltage there was a field dependence to the trap generation rate. For capacitors stressed to a constant fluence, the interface trap generation rate increased as the stress voltage increased which was a reflection of the field dependence of the voltage acceleration factor.[7]
354
2e-11 0.%
Stress C
Voltage
4) 0
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-9.5 V -10.5 V
-
0 0L
--
l-l
cc
-11 V
c0e+
-
--4
-3
-2
-1
0
1
-12.5 V Initial
2
Gate Voltage (Volts) Figure 1 Quasi-static C-V characteristics measured on an oxide on p-type silicon as a function of stress voltage for a stress fluence of 3 C/cm 2 .
04 101
E 0
Stress Voltage Initial
0101
S-
0.
S.-
~Il
1
S--
1
0.0
0.2
0.4
0.6
0.8
1.0
Surface Potential (Volts) Figure 2 The interface trap distribution for the oxides described in Figure 1. 355
-9.5 V -10.5 V -11.0 V 12.5 V
C., SJ
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Fluence (C/cm2)
Figure 3 The change in the mid-gap interface trap density as a function of fluence for capacitors fabricated on p-type silicon. The polarity dependence associated with breakdown has been shown in Figure 6 where the QBD derived from ramp I-V measurements for capacitors fabricated on n-type substrates has been plotted as a function of the breakdown field. Two thicknesses of oxides have been described in Figure 6. In general, the QBD and the breakdown field were higher for positive gate voltages for either p-type or n-type substrates. In Figure 7 the QBD measured by constant voltage stress testing has been plotted as a function of the electric field for both positive and negative stress voltages. The QBD was higher for positive voltages than for negative voltages in agreement with measurements of others.[5]
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Fluence ( Coul / cm2) Figure 4 The change in the mid-gap interface trap density as a function of fluence for capacitors fabricated on n-type silicon. The stress induced flat band voltage shift was not used to characterize the oxide wearout. It was found that application of relatively small gate voltages at the end of the stress could alter the flat band voltage shift, QSCV characteristics have been shown in Figure 8 for capacitors fabricated on p-type capacitors stressed at -11 V to a fluence of 3 C/cm 2 (about 1/2 of the QBD at -12.5 V). The variable parameter in the data presented in Figure 8 was the application of small voltages after the stress. If the gate was held at positive gate voltages greater than +4 V for 20 sec after the -11 V stress, the stress induced shift in the flat band voltage shifted toward positive gate voltages. The flat band voltage shift was determined by the magnitude of this "holding" voltage and not by the stress itself. The fluences during the application of the holding voltage were between several orders of magnitude lower than the fluences during the stress. The number of interface traps generated by the stress was not significantly affected by the holding voltage. It was observed that the interface traps were partially populated by electrons introduced during the positive holding voltage. The charge injected into the stress induced traps did not decay over a period of several hours unless a negative bias was applied to the gate. The voltage dependence of the discharge of the electrons injected into these traps indicated that the traps responsible for the "holding voltage" dependence of the flat band voltage shift were located inside the silicon oxide and within 10A of the silicon-oxide interface.
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A capacitance above C. was measured in the accumulation region for some of the stressed capacitors and was caused by the discharging of the electrons trapped in the interface traps. The capacitance measured by the QSCV method was derived from the current using C = i / (dv/dt). If the QSCV characteristics of a negatively stressed capacitor were measured a second time, as shown in Figure 8 by the second QSCV measurement made after a holding voltage of +10V, then the QSCV characteristics showed a shift toward negative flat band voltages and only a small excess current in accumulation, indicating discharging of the electrons trapped during the positive holding voltage and a lower value of current being measured. Similar charging and discharging of interface traps by holes was measured when positive gate voltage stressing was followed by negative holding voltages. Similar "holding voltage" dependencies of the flat band voltage shifts were measured on capacitors fabricated on n-type material. It was important when measuring the QSCV characteristics to begin the QSCV measurement at the same polarity as the last polarity seen by the capacitor to account for the charges loosely bound onto the stress generated interface traps. If the
358
QSCV measurement was started at the opposite polarity, the QSCV measurement procedure could discharge the electrons from the traps.
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Figure 7 Charge-to-breakdown vs field for constant voltage stress measurements. DISCUSSION The interface trap generation rate in mid-gap states per Coulomb of fluence through the oxide was determined by integration of the QSCV characteristics. The stress voltages were varied from 15 VI to 114 VI and the fluences were varied from 10-6 C/cm 2 to 12 C/cm 2 . The number of mid-gap interface traps generated by the high voltage stress was independent of the stress polarity and substrate type and followed a (fluence)-0"5 dependence. The interface trap generation rate was high at low fluences and fell as the stress fluence rose. The decreasing trap generation rate has been attributed to the bond breaking process associated with the trap generation. The bonds that required the smallest energy for breaking were broken by the first electrons through the oxide. The probability of an electron breaking a bond and generating an interface trap became progressively smaller as more of the low energy bonds were broken. Dielectric breakdown was measured to occur when the mid-gap interface trap exceeded 1013 states/cm 2 /ev. The high density of generated interface traps could act as an asperity from which breakdown start. The breakdown of the oxides was found to be dependent on the polarity of the applied voltage. The higher QBD values associated with the constant positive gate voltage stressing were attributed to breakdown that occurred at asperities at the injecting interface and
360
more asperities were present at the silicon oxide - poly interface than at the silicon-oxide interface. Higher values of QBD and breakdown field for positive gate voltages were measured during ramp voltage breakdown measurements. As in the case of the constant voltage stressing, the polarity dependence of the QBD and breakdown voltage was associated with different numbers of asperities at the two interfaces. It was concluded that breakdown was initiated at the injecting interface. The breakdown itself occurred in a very small area of the capacitor and attempts to find and study the breakdown region after breakdown were unsuccessful.
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Figure 8 Quasi-static C-V characteristics of capacitors stressed with negative gate voltages followed by a 20 sec positive gate voltage. CONCLUSIONS The number of interface traps generated during high voltage stressing of thin silicon oxide films was independent of stress polarity and substrate type. The polarity independence of the interface trap generation argued against hot electrons or avalanche processes being responsible for the interface trap generation. The charge state of these traps was a strong function of the stress polarity and of any voltage applied to the capacitor after the stress. The electrons and holes that were trapped in these interface traps were stable at room temperature but were easily discharged during QSCV measurements. Other experiments have shown that these interface traps were not only at the silicon-oxide interface but were also distributed within the oxide near the interfaces. At every stress voltage there was a field dependence to the trap generation rate. The high voltage stress generated traps at
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both interfaces, but the breakdown was initiated at the injecting interface. Wearout of the silicon oxide was coupled to breakdown through the generation of interface traps and the local high fields and currents associated with interface traps. When the local density of interface traps exceeded a critical density, then the local tunneling current rose and initiated a destructive breakdown. ACKNOWLEDGEMENTS The authors would like to thank G. A. Brown of Texas Instruments, Inc. for providing the silicon oxide films described in this paper and for providing much insight into the wearout and breakdown mechanisms occurring in silicon oxide. REFERENCES [1] E. Harari, "Conduction and trapping of electrons in highly stressed ultrathin films of thermal SiO 2 ", Appl. Phys. Lett, vol. 30, p. 601, 1977. [2] E. Harari, "Dielectric breakdown in electrically stressed thin films of thermal SiO 2 ", J. Appl. Phys., vol. 49, p. 2478, 1978. [3] M. V. Fischetti, "Generation of positive charge in silicon dioxide during avalanche and tunnel electron injection", J. Apple.Phys., vol. 57, p. 2860, 1985. [4] Y. Nissan-Cohen, J. Shappir, and D. Frohman-Bentchkowshy, "Determination of SiO 2 trapped charge distribution by capacitance-voltage analysis of undoped polycrystalline silicon-oxide-silicon capacitors", Appl. Phys. Lett., vol. 44, p. 417, 1984. [5] Y. Hokari, "Stress Voltage Polarity Dependence of Thermally Brown Thin Gate Oxide Wearout", IEEE Trans. on Electron Devices, vol. 35, p. 1299, 1988. [6] E. H. Nicollian and J. R. Brews, "MOS (Metal Oxide Semiconductor) Physics and Technology, John Wiley & Sons, New York, 1982, p. 333. [7] J. W. McPherson and D. A. Baglee, "Acceleration Factors for Thin Gate Oxide Stressing", Proc. 23rd Annual IEEE Int. Rel. Phys. Symp., 1, 1985. *Supported by the Semiconductor Research Corporation "**Supportedby Texas Instruments Graduate Fellowship
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ULTRATHIN MOS GATE DIELECTRICS FABRICATED BY RTP AND RTP-CVD D. L. Kwong, G. Q. Lo, and W. Ting Microelectronics Research Center, Department of Electrical and Computer Engineering The University of Texas at Austin Austin, TX 78712 ABSTRACT A novel technique for the fabrication of ultrathin MOS gate dielectrics for ULSI applications has been developed using rapid thermal processing (RTP) and rapid thermal processing chemical vapor deposition (RTP-CVD). This technique is advantageous over other techniques due to its unique low thermal budget properties and processing flexibility while still maintaining the advantages of high temperature processing. In this paper, experiment results are presented for oxynitrides fabricated by in situ multiple rapid thermal reoxidation/nitridation (RTO/RTN) or by RTP of Si in N2 0, and fluorinated oxides prepared by RTP of Si in 0 2 +NF 3. In addition, ultrathin nitride and oxide/nitride stacked layers prepared by RTPCVD are discussed. The requirements of RTP and RTP-CVD as a viable manufacturing technology for UILSI MOS gate dielectrics are discussed with projections toward future trends. INTRODUCTION With the increasing demand for ultrathin MOS gate oxides in ultra-small dimension devices, a tight control over the oxidation process is necessary so as to avoid large deviations from the desired thickness of the gate oxides. This control is usually achieved by diluting the oxidizing specie or by reducing the thermal budget of the process. Reduction in thermal budget is obtained by a suitable combination of growth temperature and process duration. Recently, we have investigated the effect of gate oxide growth temperature on the performance and reliability of resulting MOSFETs [1]. The MOS devices (L=2 gm) used in this study were fabricated on (100) p-type 1-2 0-cm Si substrates using conventional polysilicon gate process. Thin (-11 nm) gate oxides were grown in dry 02 at different temperatures. Effective carrier mobility, defined as Iteff = Id[Vd°W/L°Cox{(V9-VT)], was obtained as a function of effective field (Eff) and the results for high field (Eff = 0.8 MV/cm) and low field (Eeff = 0.2 MV/cm) are plotted in Fig. 1 as a function of growth temperature. For both electrons and holes the Igeff is found to increase with the increase in growth temperature in high as well as low field region. Nevertheless, the percentage increase in mobility in high field region is significantly higher than the increase in low field region. The high field carrier mobility is mainly determined by phonon scattering and roughness scattering. Since the devices are operated at the same temperature, we attribute the changes in high field Peff to the variation in interface roughness and conclude that the interface becomes smoother with the increase in growth temperature. As revealed by the studies on MOS capacitors (not shown) there is no noticeable variation of fixed charge (low 1010 /cm 2 ) and interface state density (Dit) (l-2xl0 10 /eV-cm 2) caused by the changes in growth temperature. Therefore, we cannot attribute the changes in low field Iteff to the changes in Coulombic scattering in different sample. Since these changes are smaller than
363
those in high field geff, the interface roughness scattering is responsible for these changes, but the influence is weaker than that on high field P.•. Normalized transconductance degradation (AGm.j,./Gm._pj(0)) and AS are plotted in Fig. 2 as a function of growth temperature. It is observed that the degradation is considerably suppressed in MOSFETs with high growth temperature gate oxides. The plots of AGmPak/Gm__p,(0) versus AS and AGm..pk/Gmak( 0 ) versus AVT revealed an excellent correlation, implying that the Di, is responsible 1cr the on-state degradation. The need for low thermal budget for better thickness control coupled with the need for high temperature growth for better quality oxide, as revealed in this study, suggest that RTP is a promising approach for the growth of ultra-thin gate oxides. In addition to the requirement for a tight control over the oxidation process, gate dielectrics for future MOS technology should have such desirable properties as low defect density, high breakdown field, effective diffusion barrier against dopants, metals, and impurities, excellent interface with low trapped charge densities, minimum interface state density generation under stressing, and increased radiation resistance. For the conventional thermally grown silicon dioxide serious difficulties are encountered in meeting these stringent requirements, and much attention is currently focused on the ultrathin oxynitride or fluorinated gate dielectrics due to its demonstrated superior performance and reliability over thermal oxides. In this paper, a novel technique for fabricating MOS gate dielectrics for ULSI applications has been developed using RTP and RTP-CVD. This technique is advantageous over other techniques due to its unique low thermal budget properties and processing flexibility while still maintaining the advantages of high temperature processing. In this paper, experiment results are presented for oxynitrides fabricated by in situ multiple rapid thermal reoxidation/nitridation (RTO/RTN) or by RTP of Si in N2 0, and fluorinated oxides prepared by RTP of Si in 0 2 +NF 3 . In addition, ultrathin nitride and oxide/nitride stacked layers prepared by RTP-CVD are discussed. REOXIDIZED NITRIDED OXIDES Nitridation of Si0 2 is reported to improve the barrier properties of pure oxides against impurity diffusion [2,3], enhance the endurance to hot electron stress [4-6] and exposure to ionizing radiation [7]. In spite of these advantages, nitridation increases the oxide fixed charge density and introduces a large number of electron traps [8] due to the incorporation of hydrogen in the oxide [9]. Post-nitridation anneal in 02 is used to overcome the shortcomings of nitridation [9-17]. Reoxidation reduces electron trap and fixed charge densities [9] and increases the interface hardness [10-14]. We have investigated the effects of post-nitridation rapid thermal anneals in 02 (RTO) and in N2 (RTA) on the electrical properties of RTN oxides [12,14,15,17,18]. RTN of thin (-86 A) thermal SiO 2 grown on p-type (100) Si substrate at 875 0 C was performed at 1 atm in pure NH 3 . AES results showed N pileups at the surface and at the SiO2/Si interface following RTN. Some samples were then subjected to in-situ RTO or RTA. MOSFETs with channel lengths ranging from 0.8 gm to 10 pm were fabricated using CMOS twin well technology with SiO2 , RTN SiO2 and RTN/RTO SiO2 as gate oxides.
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The charge trapping properties of RTA and RTO gate oxides are studied using constant current stress. Following RTN, a positive AVfb caused by either the increase in electron trapping and/or suppression of positive charge generation [9,18] is observed. For light RTN oxide (1000 0 C, 10 s), RTO resulted in negative AVfb, becoming more negative with increasing RTO temperature. In contrast, for the heavy RTN sample (1000TC, 60 s), AVfb remained positive. RTO at 1100'C for 30 s was found to suppress AVfb dramatically. RTA resulted in a strong net positive charge build-up during the initial stress time, followed by a negative charge build-up. The reduction of AVfb in RTN SiO2 resulted from the electron traps reduction [9] and/or positive charge generation caused by donor-type ADit [19] or generated hole traps [20]. Although RTO sample exhibited a small AVfb, its AVg result showed a net negative charge build-up. This suggests a positive charge build-up, compensating the negative charge and resulting in a small AVfb, thereby. The Id-Vd characteristics of MOSFETs with control SiO2 and RTN/RTO SiO2 are shown in Fig. 3. It is observed that RTO samples have an improved Id compared to control samples in the high Vg region (Vg > 3 V). Both samples had comparable initial characteristics, i.e. Vt and subthreshold swing. The enhancement of Id in high Vg region was attributed to the improved geff and reduced field dependence at high normal field [15]. The effects of RTO on the behaviors of geff are demonstrated in Fig.4, where PIeff is plotted as a function of Vg-Vt. RTO degraded the maximum peff by 5% to 15% for the two RTO conditions. However, RTO samples exhibited a dramatic improvement (30%) of geff under high field, probably due to a large reduction of interface states which are distributed above the conduction band after RTN/RTO compared to the control SiO2 [15,16]. The hot-carrier immunity of MOSFETs has been studied using AGm,max under F-N injection (J=-4 mA/cm 2 ). In Fig.5, AGm,max/Gm,maxo is plotted as a function of stress time in MOSFETs for several different gate dielectrics. In our previous study [12], it was found that RTN oxides showed degraded interface endurance properties against hot-carrier stress. For samples with the same RTN conditions, light RTO resulted in a larger AGm,max than the control samples. In contrast, heavy RTO resulted in a significant suppression of AGm,max, even better than the control oxide samples. The advantages of using RTP over furnace processing are also shown in Fig.5, where AGm,max/Gm,maxO of MOSFETs with gate dielectrics prepared by a 900*C/30 min or 850'C/30 min nitridation followed by a 900PC/15 min reoxidation (d). ADit was measured using charge pumping technique and ADit/Dito correlates well with AGm,max/Gm,maxo under the same stress condition, as shown in Fig.6, suggesting AGm,max/Gm,maxo is an indirect probe of the SiO2/Si interface endurance. A qualitative model [121 has been proposed to describe the structural modifications in the dielectric film leading to the observed changes in the electrical characteristics. During RTN of oxide, the nitriding specie preferentially reacts with the interface defects such as Si dangling bonds and/or the Si-O-Si strained bonds to form Si-N related structure. Formation of mismatched Si-N bonds distorts and weakens the nearby Si-O network. As a result, there are more breakable bonds available at the interface, which are responsible for the observed deterioration of the interface endurance to stress. Subsequent RTO not only restores the distorted Si-O bonds but also oxidizes the substrate and pushes the Si-N structure away by interracial reoxidation. This SixNyOz/Si interface has better endurance to
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the hot carrier injection compared to the original SiO 2 /Si interface due to the presence of shorter Si-N bonds which relieve the compressive stress at the SiO2/Si interface. For future CMOS technology, p+-polysilicon gate was recommenend for surfacechannel p-MOSFETs. The p+-polysilicon is formed by B or BF 2 ion-implantation followed by thermal annealing. However, B tends to penetrate through thin gate SiO 2 into channel region during thermal drive-in, resulting in device instabilities. Furthermore, B penetration is aggravated when H-, OH- [21,22] or F- [23,24] are present. We have investigated the use of RTN/RTO oxides for p+-polysilicon gated p-MOSFETs [25]. B was introduced into S/D and polysilicon gate by BF 2 +-implantation at 50 keV with a dose of 5x1015 cm-2. RTA at 1000*C (for 20, 40, and 60 s) was used to activate and distribute the implanted B. Fig.7 illustrates the subthreshold swing S as a function of RTA drive-in time. Obviously, both control and RTN oxides samples show a significant increase of S values with prolonged RTA drive-in. An enhanced S degradation was observed for RTN oxide samples. However, this instability is drastically reduced in RTN/RTO samples. The n-MOSFETs these gate dielectrics show negligible variation of S values, indicating that the B penetration is primarily responsible for S degradation rather than RTN and RTO induced Dit. FLUORINATED GATE OXIDES Fluorinated gate oxide dielectrics have attracted considerable attention over the past few years [26-37]. The incorporation of small amounts of F (parts per million) into SiO2 was shown to improve the SiO2/Si interface hardness against hot-electron and radiation damages [30-37]. Several techniques have been proposed for the incorporation of F into MOS gate oxides. These include immersing Si wafers in an aqueous HF solution without DI water rinse prior to oxidation [30,31], ion implantation of F into polysilicon followed by a thermal drive-in [32-35], and high-energy F implantation into Si followed by thermal annealing and gate oxidation [36]. Furnace oxidation in 0 2 +NF 3 (diluted in N2 ) [37] was also demonstrated; however, thin gate dielectrics (.10 nm) may not easily be fabricated. We have applied RTP to the fabrication of thin (-10 nm), high quality fluorinated oxides in 0 2 +NF 3 (100 ppm diluted in N2 ) [26-28]. By using this method, F can be incorporated precisely and selectively into the oxides. The control SiO 2 was grown by RTO in dry 02 at 1050°C for 60 s. Two sets of samples were prepared using two different techniques for F incorporation. One set of samples received in-situ RTA in diluted NF3 with durations from 10 to 40 s at 9000 C prior to RTO (1050OC/60 s). For another set of samples, NF 3 was introduced into RTP chamber together with 02 and RTO was carried out at 1050*C for 60 s. The purge time for NF 3 varied from 10 to 60 s. An enhanced oxidation rate was observed due to the presence of F. Since F competes with 0 to form Si-F bonds and Si-dangling bonds via the cleavage of Si-Si bonds, the interracial reactivity was enhanced [38,39]. The sequence of NF 3 purging prior to or during RTO significantly affects the resulting F distributions. For samples which received RTA in NF 3 at 900*C for 20 s prior to oxidation, F piled up at the oxide surface. In contrast, F piled up at both the oxide surface and the Si/SiO2 interface in sample grown by RTO with an NF 3 purge during the first 10 s of oxidation. F distributions have dramatic impacts on the oxide electrical properties, as shown in Fig.8.
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In Fig. 9, Dit distribution is plotted against E-Emg for oxides with several NF 3 purge times. It is clear that the hot-electron hardness of resulting dielectrics depends strongly on the amount of F incorporated. Excessive fluorination may result in nonbridging oxygen centers [32] , accompanying a local strain relaxation which suppresses the defect migration. For a 10 s NF3 purge at 10501C, the F induced strain relaxation effect exceeded that of induced nonbridging oxygen centers. The charge trapping properties are shown in Fig. 10, where AVfb is plotted as a function of NF 3 purge time during RTO. The fluorinated oxide with 10 s NF3 purge shows a far less negative AVfb than the control oxide. However, prolonged NF3 purges result in a larger AVfb, indicating an increased hole trap density. The increased hole trap density strongly suggests the existence of defects such as oxygen deficiency of stretched Si-Si bonds due to F incorporation. OXYNITRIDES GROWN BY RTP IN N20 Another method to incorporate nitrogen at the SiO 2/Si interface to improve the dielectric performance and reliability is to oxidizing Si substrates in N20. The nitrogen distribution in N20 oxides is measured by SIMS, AES, and XPS, and is found to be similar to that in RTN/RTO oxides [46]. AES oxygen and nitrogen depth profiles taken from a 60 A oxide sample grown in N20 at 1200 OC indicate the nitrogen concentration is low at the oxide surface and in the bulk. It increases gradually toward the substrate and a peak concentration of 5% was reached at the Si/Si02 interface. The peak concentration decreases with decreasing growth temperatures, from 5 % at 1200 °C, 4% at 1100 °C, to slightly less than 2% at 1000 'C. This trend is also confirmed by XPS depth profiling. Samples oxidized in N2 0 at 1050, 1100 and 1150 *C to a thickness of 62±2 A were studied. The peak nitrogen intensities were also found to decrease with decreasing temperatures. The nitrogen ls electron binding energy as revealed by XPS was 398±0.2 eV for for all three samples. This binding energy is consistent with the value measured on a 80 A Si 3 N4 sample deposited by LPCVD. This demonstrates that the nitrogen atoms in N 20 oxides are bound only to Si. The chemical composition of the nitrogen-rich layer at the Si/SiO 2 interface of nitrided oxides is similar to that in reoxidized/nitrided oxides. It will be shown later that the presence of small amounts of nitrogen in N20 oxides has a dramatic influence on their electrical properties. SIMS depth profiling has also been performed and nitrogen distribution similar to AES profiles were obtained with very low concentrations of hydrogen in the oxide bulk or at the Si0 2/Si interface, although a much higher hydrogen concentration was seen at the oxide surface, which resulted from adsorbed moisture and hydrogen on the surface after its being exposed to air. Fig. 11 shows the oxide thickness as a function of oxidation time at various temperatures. The oxidation rate of oxides grown in N 20 is significantly lower than in 02. We attribute the reduced oxidation rate to the formation of a nitrogen-rich layer at the SiOvjSi interface. This property allows the extreme control of growing gate oxides with thicknesses in the deep sub- 100 A region. Fig. 12 illustrates AVg of MOS capacitors under constant current stressing. Although both control oxides and N 20 oxides exhibit initial hole trapping, the subsequent electron trap generation is significantly suppressed in N20 oxides. Unlike the nitridation of oxides in NH3, oxidation of Si in N 20 does not involve any H-containing species, resulting in a very low electron trapping density. The reduced electron trap generation in N2 0 oxides was attributed to the nitrogen passivation of strained Si-O bonds which, upon breaking, would form electron traps during a high-field stressing [40]. AVfb after constant current stressing was also investigated and the results are summarized in Fig. 13. Apparently, hole trapping
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near the Si/SiO2 interface was significantly suppressed in N20 oxides due to a decrease in the strain-bond density near the Si/SiO2 interface due to nitrogen incorporation [12]. The initial Ditm measured on fresh devices showed that both oxynitrides and control oxides exhibited Ditm in the range of 2.5 to 4xi0 10 eV-lcm- 2 . After stressing, however, a significantly lower ADinm was observed in oxynitride devices, especially under positive gate polarity. It is speculated that nitrogen incorporation at the Si/SiO2 interface reduces strained Si-O bond density by forming Si-N bonds, thus suppressing ADitm [12]. The resistance to B penetration was examined by measuring Vfb of BF 2 implanted polysilicon-gated devices as a function of annealing temperature. As shown in Fig. 10, the control oxide exhibited AVfb of - 5V when the annealing temperature was raised from 850 'C to 950 *C due to B penetration into the thin gate oxides. N2 0 oxides, on the other hand, exhibited much less AVfb (
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breakdown events [45]. The other possibility is that the in-situ nitride deposition provides an excellent protection for the oxide from contamination before polysilicon deposition. CONCLUSION A novel technique for the fabrication of ultrathin MOS gate dielectrics for ULSI applications has been developed using RTP and RTP-CVD. This technique is advantageous over other techniques due to its unique low thermal budget properties and processing flexibility while still maintaining the advantages of high temperature processing. In this paper, experiment results are presented for oxynitrides fabricated by in situ multiple rapid thermal reoxidation/nitridation (RTO/RTN) or by RTP of Si in N 20, and fluorinated oxides prepared by RTP of Si in 0 2+NF 3 . In addition, ultrathin nitride and oxide/nitride stacked layers prepared by RTP-CVD are discussed. The excellent performance and reliability of MOS devices with these films as gate dielectrics indicates that RTP and RTP-CVD are viable manufacturing technologies ULSI MOS gate dielectrics fabrication. ACKNOWLEDGEMENT This work was partially supported by SRC/SEMATECH, Texas Advanced Technology Program, and Texas Instruments. The authors are grateful to S. Lee and J. Kuehne for their contributions to this work. REFERENCES [1]. [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26]
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Y. Nishioka et al., IEEE Electron Device Leat., EDL-10, 1989, pp. 540-542 [341 P. J. Wright and K. C. Saraswat, IEEE Trans. Elec. Devices, ED-36, 879 (1989) [351 P. J. Wright et al., IEEE Electron Device Lett., EDL-10, 1989, pp. 347-348 [361 Y. Nishioka, T. Itoga, K. Ohyu, and T. P. Ma, 1990 IEEE Device Research Conf. [371 E. F. da Silva, Jr., Y. Wang, and T. P. Ma, IEDM Tech. Dig., 1987, pp. 848-849 [381 M. Morita, T. T. Ishihara, and M. Hirose, Appl. Phys. Leat., 45(12), 1312 (1984) [391 U. S. Kim et al., J. Electrochem. Soc., 137, 1990, pp.2291-2296 [401 S. K. Lai, J. Lee, and V. K. Dham, IEDM Tech. Dig., 1983, pp. 190-193 [411 T. Watanabe M. Ishikawa, and J. Kumagai, IEDM Tech. Dig., 1984, pp. 1 7 3 - 17 6 [421 K.K. Young C. Hu, and W. Oldham, IEEE Elec. Dev. Leat., EDIL-9, 616 (1988) [43] Z.A. Weinberg et al., Appl. Phys. Leat., 57, 1990, p. 1248 [441 M. Aminzadeh et al., IEEE Trans. Electron Devices, vol. ED-35, 1988, p. 459 [45] P. K. Roy et al., IEDM Tech.Dig., 1988, p. 714 [46] W. Ting, H. Hwang, J. Lee, and D. L. Kwong, Appl. Phys. Leat., 57, 2808 (1990)
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373
INTEGRITY OF LIGHTLY NITRIDED OXIDE AS THE GATE DIELECTRIC FOR 0.5 9±M CMOS DEVICES D. -G. Lin, J. A. Yasaitis, C. H. Chiacchia Analog Devices 804 Woburn Street, Wilmington, MA 01887 Light nitridation of gate oxide significantly improves dielectric breakdown characteristics as compared to heavy nitridation. It reduces charge trapping of the gate dielectric and enhances charge to breakdown Qbd of the dielectric. 0.5gtm CMOS devices with lightly nitrided oxides as the gate dielectric have been fabricated and exhibit excellent I-V characteristics and reliability. It was found that light nitridation of gate oxide still shows significant improvement (order of magnitude) in hot carrier induced degradation as compared to conventional oxides. Continuous scaling of CMOS devices imposes serious concerns on the integrity of the gate dielectric. Nitrided oxide (NO) has been proposed as an alternative gate dielectric material for submicron CMOS due to its high dielectric strength, high resistance to interface state generation and impurity penetration etc. A great body of literature exists on nitrided oxides [1]-[3]. However, most of the nitridations and reoxidations were done at high temperatures (e.g. much higher than 950'C ) which is not desirable in 0.5 gim or lower CMOS fabrication due to thermal budget constraints. In this paper, we will focus on the lightly nitrided oxides which were fabricated at lower temperatures. M.I.S. capacitors were used for charge trapping and dielectric breakdown evaluations and 0.5 gim CMOS devices were fabricated for device performance and reliability evaluations. M.I.S. capacitors were fabricated on p-type (100) silicon wafers. n- and pMOSFETs were also fabricated using 0.51im polysilicon gate technology. 108 A thermal oxide was grown in a dry oxygen ambient. Nitridation and reoxidation were performed in a lamp heated rapid thermal annealer. Figure 1 is the plot of charge to breakdown Qbd for gate oxide nitrided at various temperatures and times. Corrstant current stressing with electron injection from the gate ( negative gate voltage ) was used for Qbd evaluation. The injection current density was 100 mA/cm 2 . The area of the capacitor was 1 x 10-4 cm 2 . Fig. I shows that for 950 0 C and 1050 0C nitridations, Qbd decreases rapidly with nitridation time. For gate oxide nitrided at lower temperature, Qbd is not a strong function of nitridation time. This figure shows that heavy nitridation significantly degrades the gate dielectric breakdown characteristics. There exists an order of magnitude difference in Qbd between light and heavy nitridation, e.g. 850 0 C 60 seconds compared to 1050 0C 60 seconds. The nitrogen concentration at the oxide-silicon interface for 850 0C 60 seconds nitridation is -3% as determined by Auger analysis. This figure also shows that Qbd for light nitridation is comparable or better than conventional oxide. Nitridation introduces both nitrogen and hydrogen related species into the gate oxide. Hydrogen/nitrogen model [1] or two factor model [2] can be used to
374
Fig. 1 Charge to Breakdown of Gate Oxides Nitrided at Different Temperatures & Time 1 00
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375
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0~ ,L)gppppppppppppp.p-pppp-gggpg-gpggpgp3gpggugmguuuu w_ - . -3 4 b 1) Drain Voltage (Volt) 0.5 pnm CMOS devices were fabricated to evaluate the effect of light nitridation of gate oxide on device reliability and performance. Fig. 5 and Fig. 6 are the comparisons of I-V characteristics for devices with and without nitridation of gate oxide. The patterned gate length and width are 0.57 gm and 20 lpm respectively. Both devices with and without nitridation of gate oxide show good I-V characteristics with breakdown voltage greater than 5 Volts. It is noted that NMOS drain current has been improved and PMOS drain current is slightly reduced. Devices with ONO films show similar characteristics. For ONO films, the effect on NMOS and PMOS drain currents is less. This is due to the reduced effect of nitrogen after reoxidation. It has been reported [2] that nitridation will decrease the peak transconductance and increase the transconductance at high gate field. In this experiment, light nitridation of gate oxide shows smaller reduction in peak transconductance and still exhibits significant improvement in transconductance at high gate field. Fig. 7 shows substrate current for NMOS devices. Devices were stressed at Vdrain=5V. The nitridations and reoxidations for NO and ONO films were 850C NH3 60 sec and 950°C 02 60 sec respectively. Although NO devices have higher drain current, the substrate current is still smaller than devices with pure gate oxide. Lower substrate currents directly improve hot carrier reliability. For evaluation of device resistance to hot
378
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carrier induced degradation, devices with pure oxide, NO, and ONO films as gate dielectric were stressed at Vdrain=5V and Vgate -2 V which is the maximum substrate current stress condition. Extrapolated threshold voltage was measured after each stressing interval. Fig. 8 shows the threshold voltage shifts for oxide, NO, and ONO devices. It was found that NO and ONO devices are much more stable than pure gate oxide devices after stressing. After 10000 seconds stressing, there exists more than an order of magnitude improvement in threshold voltage shift for NO and ONO devices compared to pure gate oxide devices. The nitrogen concentration for NO device at the oxide-silicon interface is only -3%. Therefore it is demonstrated that light nitridation of gate oxide significantly improves the device resistance to hot carrier induced degradation. Threshold voltage shifts for lightly nitrided oxide devices stressed at various gate voltages were also measured. It was found that Vt shifts, for all gate voltages smaller or equal to drain voltages, were much smaller than the Vt shift of pure oxide device stressed at maximum substrate current. Most of the improvement in threshold stability comes from a reduction in oxide trapping rather than the difference in substrate currents noted above. In summary: (1) High temperature nitridation degrades gate dielectric integrity. Reoxidation improves the integrity. However higher temperature or longer reoxidation time does not further improve Qbd, but may slightly reduce Qbd. (2) By comparing to heavy nitridation, light nitridation has several advantages, e.g. reduced charge trapping, improved Qbd etc, and still exhibits high resistance to hot carrier degradation. (3) 0.5ýj= CMOS devices with lightly nitrided oxide as the gate dielectric have been fabricated with excellent device performance and reliability.
380
REFERENCES [1] A.T. Wu, V. Murali, J. Nulman, B. Triplett, D.B. Fraser and M. Garner, " Gate Bias Polarity Dependence of Charge Trapping and Time-Dependent Dielectric Breakdown in Nitrided and Reoxidized Nitrided Oxides", IEEE Electron Device Lett., EDL-10, No. 10, P.440 1989 [2] T. Hon, H. Iwasaki, and K. Tsuji, "Charge Trapping Properties of Ultrathin Nitrided Oxides prepared by Rapid Thermal Annealing", IEEE Tran. Electron Devices, vol. 35, No. 7, P. 904, 1988 [3] H. Momruse, S. Kitagawa, K. Yamabe, and H. Iwai, "Hot Carrier Related Phenomena for N- and P- MOSFETs with Nitrided gate Oxide by RTP", IEDM 1989, P267
381
RELIABILITY OF THERMALLY GROWN THIN SiO2 FOR ULSI APPLICATIONS Y. L. Chiou, G. Li and C. H. Sow Department of Electrical Engineering University of South Florida Tampa, Florida 33620 J. P. Gambino and P.J. Tsang IBM East Fishkill Facility Hopewell Junction, N. Y. 12533 ABSTRACT Dielectric breakdown was studied for gate oxides with thicknesses ranging from 3.5 to 25 nm, at electric fields greater than 10 MV/cm. Both constant voltage and constant current stress techniques were used which resulted in similar time-to-breakdown distributions. The oxide quality with respect to dielectric strength and current durability is generally better for thin oxides, which may be partly due to less charge buildup and less trap generation. The time-tobreakdown is shorter for devices that overlap the field oxide than for those that do not, suggesting that there are more gate oxide defects near the edge of the device. The time-to-breakdown also depends on the gate material and the substrate.
INTRODUCTION The reliability of Si0 2 film has been a subject of intensive study since the
invention of integrated circuits [1-4]. The evolution of smaller and smaller devices
requires shrinkage of lateral as well as vertical dimensions. The lateral dimensions
of the most advanced MOSFETs presently in manufacturing (4M DRAM) have gate lengths of about 0.7 microns and gate oxide thickness of about 10 inn. For 0.1 micron gate lengths, the gate oxide thickness required by scaling rules is about 2 nm [5]. Since the operating voltage does not scale down proportionally to the device dimensions, the thinner gate oxides will be subjected to increasingly severe electric field stress. This will accelerate the oxide breakdown processes and enhance the leakage current at the operating voltage. In addition, the electrical properties of thin gate oxides are increasingly sensitive to process contamination and defects as the thickness decreases. In this work, the reliability of gate oxides was systematically studied for oxide thicknesses in the range of 3.5 to 25 rn. Constant voltage and constant current stress techniques were utilized to study the time dependent dielectric breakdown (TDDB) at high field regions. Both aluminum gates and polysilicon gates have been investigated.
382
DEVICE STRUCTURES The device structures were conventional MOS capacitors with electrode areas ranging from 0.25 to l.lx10- 2 cm 2 . They were prepared on < 100>, 5 inch p-or n-type silicon substrates with resistivities on the order of 11-16 ohm-cm for p-type and 3-5 ohm-cm for n-type. The gate oxides were thermally grown in a dry 02 ambient at temperatures in the range of 750 to 900 C. Three different electrode materials have been used; Aluminum, arsenic-doped n' polysilicon and boron-doped p' polysilicon. The polysilicon gates were doped by ion implanting the appropriate impurity and then annealing at 900C for 30 min N 2. Wet etches were used for gate patterning to avoid RIE damage. Aluminum was deposited on the frontside and backside of the wafers using resistive evaporation. There was no post-metalization annealing in order to minimize reactions between Al and the gate oxide. RESULTS The TDDB was initially studied using aluminum gate MOS capacitors prepared on p-type silicon substrates without field oxide isolation. Both constant voltage and constant current stresses were used. In all measurements described below, the silicon substrate was biased in accumulation until catastrophic breakdown occurred in the oxides. Figure I shows the TDDB characteristics of 10 nm gate oxides under different levels of voltage stress. The time-to-breakdown distributions were expressed in a lognormal plot. As can be seen, the TDDB is voltage dependent. It takes a longer time to breakdown at lower voltages. The thickness dependence of the time-to-breakdown distribution is shown in Figure 2. It is difficult in practice to find a voltage at which a comparison can be made for the time-tobreakdown distribution of samples with different oxide thickness. For example, in Figure 2 at an average electric field of 12 MV/cm, the time-to-breakdown for a 25 nm gate oxide is on the order of a few seconds while for thinner oxides, much longer times are needed. Therefore, for 5 mu and 10 mu gate oxides, 15MV/cm was chosen. As can be seen even at a higher electric field stress, the time-to-breakdown for thinner oxides is longer than that of thicker oxides. The TDDB under a constant current stress was investigated using the same test structures. The time-to-breakdown distributions at different current levels are shown in Figure 3. The charge-to-breakdown (i.e. current x time) decreases slowly with increasing current, ranging from 0.084 coul/cm 2 for a 400 MA stress to 0.16 coul/cm 2 for a 5jA stress. Hence the time-to-breakdown is longer at lower currents for two reasons: It takes longer to achieve the critical charge and the critical charge is higher. The thickness dependence of the distribution is shown in Figure 4 for thicknesses ranging from 5 to 25 mu. As shown in the figure, the time-to-breakdown of 5 nm, 10 nm, and 15 mu gate oxides are better than that of 20 mu and 25 nm gate oxides. It was not clear why the 15 mu gate oxide is better than the 10 nm gate oxide. Further study is needed. A comparison was made between the distributions under a constant voltage stress and constant current stress for 10 mn gate oxides. The two plots in Figure 5 are the lognormal distribution of the time-to-breakdown at 50x106 amp and 15MV/cm. The two plots are similar. Since there is no difference in the
383
results using the two different stress techniques, in the following experiments only constant voltage stress will be used. Defect related breakdown was studied using large area Al gate MOS capacitors on p-type silicon substrates. Two different contact areas, 1.2 x 10-4 cm2 and 32 x 10' cm2 were selected for comparison. The time-to-breakdown distributions at a voltage of 14V were shown in Figure 6. As expected, the time-to-breakdown is shorter for a larger area due to the presence of defects in the oxide. The sensitivity to the device structure was evaluated using the same wafers. Devices with gate overlapping the field oxide isolation were compared to devices with gates that did not overlap the field oxide isolation. Figure 7 shows the time-to-breakdown distributions for 3.5 nm and 10 nm gate oxides. The applied voltages are indicated along with the plots. It is evident that devices with gates overlapping the field oxide break down at shorter times. The test structures with p4 or n÷ polysilicon gates on p-or n-type silicon substrates were used to evaluate the sensitivity of the oxide quality to the polysilicon gates processes. The effect of the device structure was again investigated using capacitors with n" poly gates on p-type silicon substrates. Devices with and without the gate overlapping the field oxide isolation are compared at the same stress voltage as shown in Figure 8. As with the Al gate devices, the poly gate overlapping structure, which has a contact area one fifth of that of underlapping structure, still breaks down at shorter time. In addition, the distribution has a wider spread than that of the Al gate devices. The time-to-breakdown distributions for n" poly gates on p-type substrates for 3.5 nm and 10 nm gate oxide are shown in Figure 9. For these devices, the gate does not overlap the field oxide. Again oxide quality is better for thinner oxides. In Figure 10, 10 nm gate oxides with n' or p4 poly gates on p-or n-type substrates are compared at the same stressed voltage of 14V. As can be seen, with the same type of substrate, p 4 poly gates are better than n' poly gates and for the same type of gate material, the oxide quality is better for p-type substrate. DISCUSSION AND CONCLUSION The dielectric breakdown of oxides at electric fields greater than l0MV/cm was studied for oxide thicknesses in the range of 3.5 to 25 rum using Al gate MOS capacitors. Both constant voltage and constant current stress techniques were used. Similar results were obtained. It was observed that the quality of oxides with respect to dielectric strength and current durability in general, is better for thinner oxides for a given stress. Thin gate oxides (< 6 rm) are expected to have less trap generation [6] and less charge buildup than thick oxides. There is less trap generation in thin oxides, because electrons that are injected into the SiO2 conduction band may not gain enough energy (-2.3ev) to create traps [6]. There is less charge trapping because electrons that are trapped within 3 nm of an interface can tunnel out. The oxide breakdown is sensitive to device structure, with earlier time dependent breakdown for devices with gates overlapping the field oxide compared
384
to those without overlap. A possible explanation is that particles and contaminants accumulate preferentially at the edges of the field oxide. Hence, the gate oxide near the edge of the field oxide would be of poorer quality than that in the center of the device. The time dependent breakdown also depends on the type of gate and the type of substrate. Contamination and defects in this starting substrate [8] can affect oxide breakdown, and may be the reason for the longer time-to-breakdown for devices on p-type substrates compared to those on n-type substrates. The longer time-tobreakdown for the polysilicon gate devices compared to the Al gate devices may be due to the difference in post-oxidation annealing. To activate the dopants, the polysilicon gate devices are annealed at 900C in N2, which will also anneal oxide traps and interface states, whereas the Al gate devices are not annealed at all. More current flow is expected at a given bias for unannealed devices, perhaps due to distortion of the cathode field by oxide charge [9]. The reason for the longer timeto-breakdown for devices with p-type gates compared to those with n-type gate is unclear. Note that Holland et al [10] observed the opposite effect; The time-tobreakdown is longer for devices with n-type gate. The difference may be due to differences in processing. Both the substrate effect and the gate effect require more study. ACKNOWLEDGEMENTS The authors would like to thank Doug Buchanan and John Aitken for helpful discussions and Shanta Kumar for processing the wafers. This work was supported in part by the Florida High Technology and Industry Council. [1] [2) [3] [4] [5]
[6] [7] [8] [9] [10]
REFERENCES C. Hu, IEDM Tech Dig., 368 (1985). I. C. Chen, S. Holland, and C. Hu, IEEE Elec. Dev. Lett., EDL-7, 164, (1986). Y. Hokari, IEEE Symp. on VLSI Tech, 41 (1988), Y. Hokari, IEEE Trans. Elec. Dev., ED-35, 1299 (1988) G. A. Sai-Halasz, M. R. Wordeman, D. P. Kern, E. Ganin, S. Rishton, D. S. Zicherman, H. Schmid, M. R. Polcari, H. Y. Ng., P. J. Restle, T. H. P. Chang and P. H. Dennard, IEEE Electron Device Letters, EDL8, 463, (1987). D. J. Dimaria and J. W. Stasiak, J. Apply Phys.,65, 2342, (1989) R. Moajjami, J. C. Lee, C. Hu, IEEE Trans. Elec. Dev., ED-36, 2462, (1988). W. Bergholz, W. Mohr, W. Drewes, and H. Wendt, Mat. Sci. Engr., B4, 359 (1989) R. Falster, J. Appl Phys. 66, 3355 (1989) S. Holland, I. C. Chen, C. Hu, IEEE Elec. Dev. Lett., EDL-8, 572 (1987)
385
9
ca U-
2) 0) 0) UD
a, -i
1
2
5
10
20
50
100
200
500
1000
Time (sec)
Figure 1 Voltage Dependence of TDDB for 1OOA Oxides (Al gate) 9
cc
LI a) 0)
0.01
0.03
0.1
0.3
1
3
10
30
Time (sec) Figure 2 Thickness Dependence of TDDB for P-type Al MOS Capacitors
386
100
98% 95
g? o u. 80
S70 60
• 50 40 .~30
20 10 5 29/. 0.001
0.01
0.1
10
1
100
1000
Time (sec) Figure 3 Current Dependence of TDDB for IOOA Oxides (Al gate) 9
cc LL
(D CM
(L
Q.)
0.1
0.2
0.5
1
2
5
10
20
Time (sec) Figure 4 Thickness Dependence under a Constant Current Stress
387
50
100
98% 95
90 LL 80 0)
S70 a 60 • 50 40
0)
30
.
• 20
E
S10
5 2%/ 0.1
0.2
0.5
1
2
5
Time (sec)
10
20
50
100
Figure 5 Comparision of TDDB under Constant Voltag and Constant Current Stress 9
cc UL a) 0)
C
0) C)
0.001
0.01
0.1
1
Time (sec)
10
Figure 6 The Effects of Contact Area to TDDB
388
100
1000
i0
Time (sec) Figure 7 Comparision of Al MOS Capacitors with and without Field Oxide Isolation for Different Thicknesses
98% 95-
.
Sunderlap
90
"U-80Q) 0)
1ooA oxide P-type N-Poly gate (1
70-
a) 60" 50-
4
2
4
2
device area= 1.21x 1Ucm
Overlap device area= 0.25x10 cm
a)
-5 20 E t1052% 0.001
overla
.. ..., . ....I / ...., . . .. . . ..., ...... 0.01
0.1
1
10
100
Time (sec) Figure 8 The Effects of Polysilicon Gate Processes to TDDB
389
1000
0.1
0.3
1
3
10 30 Time (sec)
100
300
Figure 9 Thickness Dependence of TDDB for n+ Poly Gate and Al Gate
98% 95
_ 90 u. 80 a)
0)70
o60 50 CL 40 30 CO
z 20 E 10 to
5 21% C
Time (sec) Figure 10 Comparision of TDDB for Poly Gate Test Structures
390
1000
BREAKDOWN CHARACTERISTICS OF O-DILUTED AND RTO THIN SiO2 FILMS L. Fonseca and F. Campabadal Centro Nacional de Microelectr6nica Universidad Aut6noma de Barcelona. 08193 Bellaterra. SPAIN. Two alternative techniques to low temperature conventional furnace processing for thin oxide films growth, RTO and O2-diluted oxidation, have been considered and extensively electrically characterized. Expected values of AI/SiO2 barrier reflected good oxide structural characteristics in both cases. Longer carrier lifetime for RTO oxides evidenced no substrate damage from aggressive thermal cycling. A lower density of defects was deduced for RTO oxides from TZDB tests. Slight differences in dielectric breakdown strengths turned out very important in TDDB experiences, specially for positive (substrate injection) stress polarity, RTO samples exhibiting larger Q, values.
INTRODUCTION Non degraded performance of ULSI circuits implies that the lateral dimensions reduction trend has to be accompanied of parallel diminishing vertical dimensions. As supply voltages have not followed the dimension scaling rate so far, work conditions for thin gate oxide have grown worse, making failure characterization of these films obliged. On the other hand, as shallower junctions are needed, reduce thermal budget is a must, and high temperature processes have to be avoided or shortened as much as possible. Controllability issues due to furnace large thermal inertia force thin oxide growth to be performed at lower temperatures (850°C) than thicker oxides. Low temperature oxide films however, are reported to present worse Si-Si0 2 interface quality [1]. A first attempt to moderately increase furnace temperature processing (-950°C), while keeping oxidation times still controllable, is to dilute oxidant atmosphere reducing oxidation rate. A second option is to turn to a relatively novel technique, Rapid Thermal Oxidation, that due to the small size of the oxidation chamber and its fast radiative heat source, conciliates the two key points of thin oxide growth, namely, high temperature (> 10000 C) and short time processing (typically a few tens of seconds), that are impossible to simultaneously achieve in furnace tubes.
391
EXPERIMENTAL Al-gated MOS capacitors were fabricated on 2", < 100 > oriented, 11cm, p-type Czochralsky grown silicon wafers. l6nm dry oxides were grown in a conventional diffusion furnace at 950'C in a Ar+ 10%0 2+2%HC1 atmosphere. On the other hand, an Addax R1000 by AET equipment was used to grow 16 nm RTO oxides at 1050°C, followed by a 30s RTA (rapid thermal annealing) in N2 at the same temperature. AI+ I %Si was deposited on top and bottom of the wafers, and after square gate definition by standard photolithographic procedures, all samples experienced a 20 min PMA at 435-C in hydrogenated ambient. Next, both destructive and non destructive electrical characterization tools were used in order to comparatively assess different aspects of electrical quality of these two kind of dielectric layers. NON DESTRUCTIVE ELECTRICAL CHARACTERIZATION In Fig. 1 thickness maps obtained for both oxides by C-V characterization of the fully processed capacitors are presented. RTO oxides are usually reported as less homogeneous due to problems of uniform heating [2]. In our case standard deviation for RTO samples (16A) was 5 times that of 0O-diluted oxides (3A).
160 40 ZO 40 30
Tý,M, ,,
RTO
J
•,•
MM
02-d diluted
Figure 1. Thickness wafer maps of RTO and 02-diluted oxides, RTO samples exhibiting a characteristic upward concavity and less homogeneity than furnace oxides.
No fixed positive charge in the vicinity of the Si-SiO2 interface could be inferred from the flatband voltages measured for both oxides. Interface states at midgap were also below detection of the two frequencies C-V method (!; 1.5e10 crmeV') in both cases.
392
In order to check if aggressive thermal cycling inherent to RTO technique, with temperature ramp rates as high as 300*C/s, damages the Si substrate, the pulsed Zerbst C-t method [3] was used and retention times were evaluated (figure 2). At this respect,
a damaged substrate is expected to offer more generation sites and thus exhibit worse storage time. However, RTO oxides showed three times higher carrier lifetime (- 140As) and an order lower (-I1cm'as') other parasitic relaxation currents. This fact makes RTO processes a good choice for DRAM applications.
Figure 2. Capacitance transients recorded for both types of samples, from the deep depletion to the equilibrium inversion value, being the area tested 2 2.3e-3em .
Inspection of I-V characteristics showed Fowler-Nordheim conduction over six decades of current prior to breakdown. Reasonable values of 3.0-3.1 eV for the Al-SiO2 barrier were obtained in both cases from the slopes of F-N plots, under the usual assumptions made in these calculations [4], indicating good structural characteristics for both oxides.
BREAKDOWN MEASUREMENTS Both time-zero and time-dependent stresses were performed on both type of oxides in order to characterize the electrical endurance of these films with such figures of merit as the breakdown field (E,) and the charge-to-breakdown (Q.).
393
Trne-Zero Breakdown experiences Using a HP4145B parameter analyzer, both types of samples were taken to destructive breakdown by performing staircase voltage ramp stresses at an approximately ramp rate of 4 V/s with the Si substrates biased in accumulation. It should be noted that all the fields appearing in this study are across the oxide and were calculated from the applied ones by taking into account the theoretical voltage distribution in MOS structures. 30-
30-
Am 3.
Area U (310)
I (RTO)
= 11.6 MV/em 25.
1.d. 1.7 7 MY/cm
MV/cm . -4 s.d. = 0.4 MV/cm
4) 10.
0
(b)
(a)
F'
15.
I
d
&
:•
•
5 7 6
A 4•
4"4
01
I
0-1
I Jl-,.. 21
41
112 34
6 67
Area I (O.-diluted)
km H (o,-dutd)
a
3.- 12.1 Wi/cm &.d. = 0.6 MV/cm
&.d.
I
11.0 MV/cm 3.2
iM/cm
M IW I1
1
1
|Z
h 1.. IJ
$2 131
1
a4?
p. 4? 4? S..
(d)
(c)
E (MV/cm)
E (MV/em)
Figure 3. Breakdown histograms of RTO (ab) and 0 2-diluted samples (c,d) for the two areas tested 2 2 (I:3.24e-4cm , ll:6.4e-5cm ).
In addition and regarding to the poor uniformity of RTO oxides the average thickness was not used in the calculation of breakdown fields. We used instead individual
394
thickness values for each sample considered and discarded those of less than 150A, the minimum thickness also observed for the O2 -diluted samples, in order to get a set of data suitable for comparison. The areas of the capacitors tested were 3.24e-4 cm2 and 6.4e-5 cm2. 50 capacitors of each type and area were used to construct the breakdown statistics. The breakdown histograms obtained for both types of oxides showing a good percentage of high field failures are presented in Fig. 3. From inspection of this figure it can be observed that although more 0O-diluted oxides broke down near the maximum breakdown field recorded (-13 MV/cm), RTO samples always showed tighter distributions. Average breakdown fields are summarized in Table I, RTO samples showing approximately 0.5 MV/cm higher dielectric strength. Analyzing failure data according to extreme value statistics [5], Weibull plots (Fig. 4) can be calculated from the cumulative failure functions (F). 2.0¸ 1.0 -.
0.0 -1.0
-2.0 -
R
-3.0 -4.0 -5.0
"I "I ",
F I""
E (MV/cm)
E (MV/cm)
Figure 4. Weibull plots of both areas RTO (a) and 0 2-di
As expected, the larger capacitors presented worse breakdown features showing more failures at low fields, although it must be pointed out that results for both areas converge in the high field region, indicating the quasi-intrinsic or non defective nature of these breakdown events. Furthermore, a defect density [51 also shown in Table I, can be extracted from the kink point appreciated in such a plot between the extrinsic (low field) and intrinsic (high field) regions, exhibiting RTO samples a lower density of defects. At this respect, different density of defects for different area values evidences a certain degree of defect clustering.
395
I Em (MV/cm) Defect density (cm 2)
Area II
RTO
Area I 11.5 ± 1.8
12.4
0O-diluted
11.0 ± 3.2
12.1 ± 0.6
RTO
1000
1800
O2-diluted
2600
8900
± 0.5
Table I. Average breakdown field and defect density obtained for both oxides. (Area I: 3.24e-4 cm2 ; Area R: 6.4e-5 cm2).
Wear-out tests TDDB experiences were carried out on 20 capacitors (3.24e-4cm2) of each type, by means of a constant F-N current (lmA/cm2) technique, for both gate and substrate injection. In spite of small size populations, results obtained were so distinct that can be considered significant. A first indication of better RTO quality was that less capacitors of this type were initially shorted for that current level injection. Higher Q" for RTO oxides was obtained (Table II) for both stress polarities, Q. for substrate injection being larger, as has been reported for conventional oxides [6]. Strikingly, this is not the case for our 0 2-diluted oxides. A possible explanation of this phenomenon is that the amount of the chlorine incorporated in the oxide, that is known to accumulate near the Si-SiO2 interface [7], is too high and has in fact weakened it. Anyway, Q. found for these samples was 2-3 times larger than the value of Q( that can be inferred from ref [6] for Al-gate, 950°C 0 2 +3%HCI samples of similar area. This fact makes Q. for RTO oxides even more respectable. Gate
Q. 2
(C/cm ) AV (V)
Substrate
RTO
1.35
± 0.80
4.00 ± 2.00
0 2-diluted
0.19 ± 0.10
0.10 ± 0.06
RTO
0.40 ± 0.10
4.50 ± 0.40
O2-diluted
0.35 ± 0.10
0.80 ± 0.40
Table U. TDDB results. AV' is the voltage difference between breakdown and turnaround points (Area I: 3.24e-4cm 2, lmA/cm2).
396
Initial trapping characteristics are presented in Fig. 5 for typical RTO and 0Qdiluted samples. In both cases a turnaround phenomenon can be appreciated as has been widely reported, the magnitude and position of the minimum being very repetitive for all samples tested. The diminishing portion of the characteristics has been described as indicative of positive trapping [8],[9] or electron detrapping from traps already present in the film [10]. According to this second interpretation, the obtained results indicate that as-grown traps are more numerous in RTO oxides than in 0 2-diluted oxides, provided similar initial occupation of these traps is assumed. The increasing part, on the other hand, reflects electron trap generation, RTO samples exhibiting lower trap generation rate.
5-
I
Figure 5. Typical trapping characteristics for RTO and 0 2-diluted samples (Area I) in the first 30 s of the stress, RTO oxides presenting larger initial electron detrapping and smaller electron trap generation rate.
Besides, this kind of samples presents higher voltage increment (AV), and thus more trap density, when breakdown occurs. This fact suggests that larger t. of RTO oxides is due both, to a smaller trap generation efficiency and to a larger capability to endure the effects of the traps generated. As RTO oxides were grown at higher temperatures than 0 2-diluted ones, less mechanical stress is expected in their bonding structure. Stronger bonds can explain both observations stated above, as it would be more difficult for an incident electron to break a bond and create a trap, and more trapped electrons would be necessary to build up local electric fields large enough to surpass bond strength.
397
Better breakdown features were also observed, as in TZDB stresses, for the smaller area capacitors (Table III), presenting in both cases a charge-to-breakdown about two times larger. Such great difference does not correlate however, with similar changes in the applied voltage increment (AV) that at most experienced 20% variations. This fact could be interpreted as an evidence of breakdown being triggered by a critical density of traps.
I Q.
Gate
Substrate
3.3 ± 1.4
9.0 + 3.5
O-diluted
0.34 ± 0.22
0.17 ± 0.14
RTO
0.53 ± 0.14
3.9
0.35 ± 0.10
0.91 ± 0.6
RTO
(C/cm?) AV(V)
IO-diluted
0.4
Table M. TDDB results. AV' is the voltage difference between breakdown and turnaround points 2
1
(Area II: 6.4e-.5cm , lmA/cm ).
CONCLUSIONS Two oxidation technologies, RTO and conventional 0 2-dilution, aimed to thin oxide film growth, have been compared by multi-purpose electrical characterization of the samples produced. C-V characterization revealed good interface quality for both types of oxides. Analysis of I-V characteristics showed F-N tunnelling conduction through an Al-SiO2 barrier of 3.0-3.1 eV, reflecting good structural properties in both cases. Superior storage time of RTO capacitors evidenced that no serious substrate damage was produced by aggressive thermal processing. In TZDB experiences RTO and O2-diluted yielded similar results again, although RTO oxides presented somewhat tighter breakdown distributions and then slightly higher average breakdown field, and fewer low-field breakdowns and hence a lower defect density. Finally, differences between both types of samples arose dramatically in TDDB experiences, where RTO oxides exhibited a ten times greater Q., revealing themselves as harder oxides than their conventional counterparts, being their main drawback a worse spatial thickness uniformity. ACKNOWLEDGMENTS This work has been partially supported by the Comisi6n Interministerial de Ciencia y Tecnologfa (CICYT) under project MIC88-340
398
REFERENCES
[1]
R. Razouk and B.E. Deal, J. Electrochem. Soc., 126, 1573 (1973)
[2]
M. Moslehi, S.C. Shatas, K.C. Saraswat and J.D. Meindl, IEEE Tran. Elec. Dev., 34, 1407 (1987) M. Zerbst, Z. Angew. Phys., 20, 30 (1966) Z. Weinberg, J. Apple. Phys., 53, 5052 (1982) D.R. Wolters and J.J. van der Schoot, Philips J. Res.,40, 115 (1985) J.J. van der Schoot and D.R. Wolters, in 1983 InsulatingFilms On Semiconductors, J.F. Verweij and D.R. Wolters, eds, INFOS Procc., 271 (1983) J.R. Monkowsky, T.E. Tressler and J.Stach, J. Electrochem. Soc., 125, 1867 (1978) N. Klein and P. Salomon, J. Apple. Phys., 47, 4364 (1976) I.C. Chen, S.E. Holland and C. Hu, IEEE Tran. Electron Devices, ED-32, 413 (1985) Y. Nissan-Cohen, J. Shappir and D. Frohman-Bentchkowsky, J. Apple. Phys., 60, 2024 (1986)
[3] [4] [5] [6]
[7] [8] [9] [10]
399
EFFECTS OF Si WAFER SURFACE MICRO-ROUGHNESS ON ELECTRICAL PROPERTIES OF VERY-THIN GATE OXIDE FILMS M. Morita, A. Teramoto, K. Makihara, T. Ohmi Department of Electronics, Faculty of Engineering, Tohoku University Sendai 980, Japan Y. Nakazato, A. Uchlyama Nagano Electronics Industrial Co., Ltd. Koshoku-shi, Nagano-ken 387, Japan and T. Abe Isobe R & D Center, Shin-Etsu Handotai Annaka-shi, Gunma-ken 379-01, Japan Electrical properties of very-thin oxide films are demonstrated to investigate the dependence on Si surface microroughness before oxidation. Good dielectric breakdown statistics are realized on the Si wafers with small surface microroughness. Scanning tunneling microscope (STM) observation suggests that the Si-SIO2 interface structure depends on Si surface microroughness before oxidation. Atomic force microscope (AFM) observation indicates that the microroughness of oxide surface also reflects the initial Si surface microroughness before oxidation. The current density through very-thin oxide films decreases with decreasing SI surface microroughness. INTRODUCTION The thickness of gate oxide film is thinned down with the shrinking of ultra large scale integrated (ULSI) devices. The microscopic uniformity of the oxide film thickness and the atomic flatness of the SI-SiO2 interface are essential to realize the high insulating performance of very-thin gate oxide films. It is, therefore, very important to control the Si surface microroughness right before oxidation and the resulting SI-SIO2 interface flatness. Some correlations between electrical properties and the Si-SIO interface microroughness or the initial Si surface microroughness right before oxidation have been reported so far[l][2][3]. Thermal oxidation is demonstrated generally to increase the microroughness of SI-SiO Interfacesfl]. Anneal of Si wafers In sufficiently low concentration of oxygen Is shown to cause etching and consequent roughening on Si surfaces[21. Cleaning procedure with the NH4 OH:H 2 02 :H2 0 solution having high NH4 0H content is demonstrated to increase the SI surface 400
Thus, some processes used to fabricate devices cause microroughness[3]. an increase of the microroughness of the Si surface and the Si-SiO2 interface. It is important to prepare the Si wafer having a microscopically flat surface and to establish the device fabrication processes which suppress roughening of Si surfaces and Si-SiO2 interfaces. The dielectric breakdown statistics are found to depend on the surface microroughness of polished FZ Si wafers[4]. However, the correlations between electrical properties and the surface microroughness of the polished Cz SI wafers have not been well understood. In this paper, we describe the effects of surface microroughness of Cz Si wafers on electrical properties of very-thin oxide films by using chemical-mechanical polishing techniques. Effects of oxidation on the microroughness of SI-SiO2 interfaces and SiO2 surfaces are also discussed. EXPERIMENTAL To clarify the microroughness effects, wafers having various levels of microscopic flatness (i.e. surface microroughness) were prepared by different chemical-mechanical polishing techniques[3]. The wafers were Cz, P-doped n-Si(100) with the resistivity of 8-12 Ohm-cm. The surface microroughness is usually defined as microroughness maximum (Rmax) and average (Ra). These levels of the wafer surface microroughness were evaluated by a scanning tunneling microscope. Figures 1 and 2 show typical STM profiles and microroughness maximum (Rmax) and average (Ra) values determined from their profiles of polished wafer surfaces, respectively. The error bar denotes each maximum fluctuation of Rmax and Ra in Fig. 2. The removal rate of Si in chemical-mechanical polishing for A, B, C and D Is high In that order. The STM profiles proved that the wafers with four levels of surface microroughness could be prepared, and revealed that the polishing technique C gives the smallest average value and fluctuation of Rmax and Ra. Field oxides with the thickness of approximate 200 nm were simultaneously grown at 1050 C in dry oxygen ambient for 5 hours. The dry oxidation is employed in order to suppress an increase of the microroughness of the Si surface after removing the field oxide. Very-thin gate oxide films were simultaneously grown at 900 C in dry oxygen. Al films were evaporated as metal electrodes in order to accurately determine the oxide thickness and the average oxide field from electrical measurements, because the depletion layer formation in polycrystalline Si electrodes induces the error of the above values for very-thin oxides. RESULTS AND DISCUSSION Figures 3 and 4 show dielectric breakdown characteristics of metaloxide-semiconductor (MOS) devices with approximately 3.7 nm-thick and 5.1 nm-thick oxides for specimens A, B, C, and D, respectively. The
401
thickness difference for the oxides simultaneously grown Is due to that the real oxidation time differs with the wafer location in the same oxidation furnace. The metal electrode voltage is positively biased with the applied field rate of 1 KV/cm-sec. Few or no breakdown events at the low field region Is found on specimen C, while some low-field breakdown events on specimen A. The breakdown events are concentrated on the intrinsic breakdown for specimen C. The breakdown at lower average fields than that of intrinsic breakdown is interpreted as a result of field enhancement due to microroughness at Si-SiO2 interfaces. These results indicate that good dielectric breakdown behavior can be obtained by reducing the surface microroughness of polished Si wafers. The microscopic roughness of Si-SIO2 interfaces was evaluated from STM profiles of the Si surface after the removal of S102 layers by diluted HF etching. Figures 5 and 6 show typical STM profiles and microroughness maximum (Rmax) and average (Ra) values determined from their profiles of wafer surfaces after removing Al electrodes and oxide layers (field and gate oxide layers) of MOS devices mentioned in Fig. 3, respectively. The surfaces after removal of thermal oxide films grown on wafers A, B, C, and D give the similar STM profile difference to polished wafer surfaces before oxidation. This indicates that the microroughness of Si-SiO2 interfaces is mainly governed by the surface microroughness of polished wafers. It is, therefore, necessary to reduce the surface microroughness of polished wafers in order to realize the Si-SiO structure with an atomically flat interface. Further, it is seen from Figs. 2 and 6 that the average values and the fluctuation of Rmax and Ra for Si surfaces after oxide removal are smaller than that for polished Si surfaces in the case of specimen A, while the microroughness of Si surfaces after the removal of the thermal oxides with the thickness of 50 nm or thinner is found hardly to differ from that of polished Si surfaces for all specimens. This suggests that the microroughness of Si-SiO2 interfaces is influenced by oxidation. Figure 7 shows current density-electric field characteristics of A1-SiOZ-Si MOS devices under positively biased metal electrodes, where the thicknesses of gate oxide films are approximately (a)3.7 nm and (b)5.1 nm, respectively. For 3.7 nm-thick oxides, the current density of specimen C is lower thin that of A and B. While the current densityfield characteristics of 5.1 nm-thick oxides for all specimen are nearly overlapped. These results indicate that the steady-state current density through oxide films depends on the microroughness of wafer surfaces before oxidation as the oxide thickness Is very thin. The current densities of 3.7 nm oxides at the given field are higher than that of 5.1 nm oxides. This result Indicates the current through 3.7 nm oxides is mainly dominated by electrons tunneling, while the current through 5.1 nm oxides by Fowler-Nordheim tunneling. Therefore, it is considered that the surface microroughness of polished Si wafer results in thinning of the effective insulator thickness for electrons tunneling. Figure 8 shows atomic force microscope (AFM) profiles of thermal oxide surfaces for specimens A and D, where the 5 nm-thick oxides were 402
grown at 900 C in dry oxygen ambient for 7 min, and the 200 nm thick oxides at 1050 C in dry oxygen for 5 hours. The Ra(Rmax) of the 5 nm oxide for A and D are 0.56 nm(2.75 nm) and 0.23 nm(l.29 nm), respectively. These Ra and Rmax for 5 nm oxides are almost that determined from STh profiles of polished wafer surfaces shown In Fig. 2. The same results were obtained for 10 nm and 20 nm-thick oxides grown at
900 C. It is seen that the surface microroughness of thin thermal oxides reflects that of polished wafer surfaces before oxidation. The Ra(Rmax) of the 200 nm oxide for A and D are 0.78 nm(3.59 nm) and 0.08 nm(0.68 nm), respectively. The Ra and Rmax of 200 nm oxide grown at 1050 C for A are slightly larger than that of 5 nm oxide grown at 900 C. While the Ra and Rmax of 200 nm oxide for D are smaller than that of 5 nm oxide. These results indicate that the oxide surface microroughness is dominated by oxidation temperature or oxide thickness along with polishing techniques. CONCLUSIONS We have demonstrated that electrical properties of very-thin oxide films depend on the microroughness of Si wafers prepared by chemicalmechanical polishing techniques. Good dielectric breakdown behavior can be obtained by reducing the surface microroughness of polished SI wafers. The current density through very-thin oxide films decreases with an decrease of the polished Si surface microroughness. It is suggested from STM observation that the microroughness of Si-SiO2 interfaces depends on that of polished Si surfaces before oxidation and is also influenced by oxidation. AFM observation indicates that the microroughness of oxide surfaces also reflects that of polished Si surfaces. ACKNOWLEDGMENT The authors wish to thank M. Katayama of Shin-Etsu Handotai for his help in the wafer preparation. This study was carried out at the Superclean Room of Laboratory for Microelectronics, Research Institute of Electrical Communication, Tohoku University. REFERENCES
[1] P.O.Harn and M.Henzler, J.Vac.Sci.Technol. A2, 574(1984). [2] M.Offenberg, M.Liehr, S.R.Kasi, and G.W.Rubloff, in Digest of Technical Papers,1990 VLSI Technology Symposium,Honolulu,1990, p.117. [3] T.Abe and M.Kimura, In Proceedings of The Sixth International Symposium on Silicon Materials Science and Technology, The Electrochemical Society, Pennington, 1990, p.105. 141 M.Miyashita, M.Itano, T.Imaoka, I.Kawanabe, and T.Ohmi, in Extended Abstract of the 179th Electrochemical Society Meeting, Washington D.C., 1991, p.709. 403
ohi TqI-FI-
F::;j
qI1:::IArFF
B
A
1)
C
Fig.1 STM profiles of wafer surfaces prepared by different chemical-mechanical polishing techniques.
1.0
10
POLISHED Si SURFACE
POLISHED Si SURFACE B -0.8
i00.4
-
0.2
2
A
B
C
A
0
B
C
D
(b)
(a)
Fig.2 Microroughness (a) maximum and (b) average values determined from STM profiles for polished wafer surfaces.
404
100
.A
I
.
I I
,
I
100
.
I I
I I I I
I
80
60
60
z
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0 I 2 3 4 5 6 7 8 9 10
1 12 13 141516
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0 1 2 3 4 5
100
.--t -I -.-- I
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E (MV/cm)
E (MV/cm)
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I
60 2:Z 0
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0 I 2 3 4 5 6 7 8 9 IOUl 1213141516
I 2 3 4 5 6 7 8 9 1011 12 13 141516
E (MV/cm)
E (MV/cm)
FIg.3 Dielectric breakdown histograms for specimens A, B,
405
C and D.
100 8 5.1n80
(C z
z
7l
W 40
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60 LL 20
0
1 2 3 4 5 6 7 8 910 11 12 13 141516
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E (MV/cm)
100 D 4.9nm 80
C)
60
U 7
LU
0
40
IL
20
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1516
E (MV/cm)
E (MV/cm)
Fig.4 Dielectric breakdown histograms for specimens A, B, C and D.
406
APT•n NYTnP RMmnV^I1
qIIRPArP
qi
A
B
C
D
Fig.5 STM profiles of wafer surfaces after removal of thermal oxide layer for specimens A, B, C and D.
10
I
Si SURFACE AFTER OXIDE REMOVAL
B x E
a
0.8
6
E 0.6
4
AFTER OXIDE REMOVAL
(0.4
IT
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2
0.2
t• V
A
B
c
0.0
D
(a)
A
B
C
0
(b)
Fig.6 Microroughness (a) maximum and (b) average values determined from STM profiles for wafer surfaces after removal of thermal oxide layer.
407
I
10-
to-,
10-.
B 3.8nm 7
/
\C
10-,
5,.Inm ... A A 5.0nm m B 5.1m
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----
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ao
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10-
F
10-' 10-
4
B
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6
8
E (MV/cm)
E (MV/cmn)
(b)
(a)
Fig.7 Current density-field characteristics of approximately (a)3.7nmand (b)5.lnm-thtck oxides for specimens A, B and C.
SiO2
SURFACE D
A
5 nmu
200 nm
Fig.8 AFM profiles of thermal oxide surfaces for specimens A and D.
408
DIELECTRIC BREAKDOWN STRENGTH ANALYSIS OF SiO2 USING A STEPPED-FIELD TESTING METHOD Eric A. Sprangle School of Electrical Engineering Cornell University Ithaca, New York 14850 John M. Andrews and Martin C. Peckerar Nanoelectronics Processing Facility Naval Research Laboratory 4555 Overlook Avenue Washington, DC 20375-5000
The ramped-field technique has been widely used for determining dielectric breakdown in thin insulating films. But this method does not control stress time, and it is difficult to define an irreversibly broken down capacitor based solely on observations of current during stressing. A more advanced stepped-field method is described, which provides well-defined stress times and guarantees catastrophic breakdown in all cases. MOS capacitors, formed by depositing Al dots on thermally grown SiO 2 , were used to determine oxide breakdown. The breakdown field was found to decrease logarithmically with the stressing time. A model is presented which relates the probability of breakdown to the stressing field strength and stressing time. Dielectric breakdown strength was also investigated as a function of annealing time and temperature. Annealing at 500 'C and above for 1 hr in H 2 caused the breakdown strength of the oxide to be sharply reduced due to a metallurgical reaction between Al and SiO 2 .
INTRODUCTION Traditionally, dielectric breakdown strength has been measured by applying a steadily increasing voltage across a thin insulating film, and measuring the leakage current. A sudden, large increase in current is assumed to indicate dielectric breakdown, at which point the electric field is recorded. Although this method is simple to implement, it is usually difficult to define conditions for catastrophic breakdown. Often, the sudden increase in leakage current is well-defined, but large currents may also be due to Fowler-Nordheim tunneling or Frenkel-Poole trap-assisted conduction. Dielectric breakdown defined by the ramped-field method may not always be irreversible, and a re-test might simply indicate modified device behavior [1]. Furthermore, oxides having a high trap density may be able to absorb significant amounts of electric charge before breaking down [2, 3]. Consequently, a constantly increasing field may have increased well past the true breakdown field by the time when breakdown conditions are recorded. In this case the measured breakdown field will appear to be higher
409
than the true breakdown field. The stepped-field method, proposed by Heimann [11 and described in this paper, avoids the shortcomings related to the ramped-field method.
DEVICE FABRICATION The metal-oxide-semiconductor (MOS) capacitors used in these experiments were fabricated on 50 mm, n-type silicon wafers with a resistivity of 2 ohm-cm. The wafers were cleaned using the standard RCA procedure, given a final rinse in deionized water, and spun dry. All wafers were oxidized at 1000 °C in dry oxygen in a horizontal oxidation furnace using a polycrystalline silicon tube. The oxide thickness was measured before Al deposition using a Gaertner ellipsometer. After oxide growth, the wafers were metallized with 4000 A of Al. The deposition was done in an Applied Materials radio frequency evaporating system. MOS capacitors were defined using a shadow mask that produced circular metal pads having a 3 2 diameter of 30 mils (A=4.56x10- cm ) and a separation of 1.14 mm. Each wafer contained approximately 900 MOS capacitors arranged in a 30x30 square array.
ELECTRICAL EVALUATION Dielectric breakdown was measured using a Keithley Model 617 programmable Electrometer and Voltage Source. The probe was stepped through the arrays using a Rucker and Kolls Model 690M Automatic Wafer Prober. The probe arms were specially designed by Quater Research and Development. Both the electrometer and the wafer prober were controlled by a Hewlett-Packard Series 9000 Model 360 desk top computer. All breakdown tests were performed at room temperature in open air. The stepped-field method, used to determine dielectric breakdown in these experiments, provides precisely-defined stressing conditions that are not available in the standard ramped-field method [1, 4]. Precisely controlled stressing time is important, because dielectrics exhibit time-dependent breakdown behavior. Thus, the breakdown field is reduced as the stressing time is increased [5]. Furthermore, MOS capacitors may exhibit a characteristic time delay in addition to the intrinsic time required for breakdown. This delay can be attributed to the charging of deep traps within the oxide. A space charge is formed when the traps are charged, which reduces further injection. Therefore the amount of charge required for oxide breakdown will only be reached after a characteristic injection period. The resulting time delay and reduction of local field may cause the measured breakdown field to appear to be higher than the actual field that the oxide could sustain for a similar period of time in the absence of trapped charge [2, 31. The stepped-field method avoids these problems by applying a constant electric field for a fixed period of time. After each stressing period, the E-field is reduced to a much lower test value in order to determine whether the leakage current has been significantly increased. If the MOS capacitor passes the test field leakage criterion, the electric field is then stepped to a higher stressing value. The stepped-field technique thus avoids the effect of delayed charge injection, especially important for CVD deposited oxides that may contain large trap
410
concentrations. A comparison of the two dielectric breakdown measurement methods is illustrated in Fig. 1.
STEPPED FIELD
RAMPED FIELD
0 uJ LL
TIME Fig. 1.
TIME
Comparison of traditional ramped-field method to stepped-field method.
In the stepped-field method, each capacitor was first tested at 1 MV/cm. (See Etet, as labeled in Fig. 1.) Capacitors that exhibited initial leakage currents >10-1° A were designated as shorted devices. If the capacitor is found to be shorted, the prober moves to the next capacitor and the test for the initial leakage current is repeated. If the capacitor passes the initial leakage test, it is then subjected to high-field stressing at a constant field Estres for a fixed stressing period tstress. After the stress field is applied, the leakage current is again 6 checked at the test field of 1 MV/cm. If the capacitor conducts a leakage current >2x10" A at the test field, it is designated "broken down." The following data are then recorded: the initial leakage current measured at 1 MV/cm prior to stressing, the leakage currents measured at the test field of 1 MV/cm just before and just after breakdown, and the electric field strength required to induce breakdown. A logic diagram of the testing routine is shown in Fig. 2. Dielectric breakdown conditions defined in this way are sufficient to guarantee that irreversible, catastrophic damage to the oxide has taken place [1, 4]. The statistical nature associated with the dielectric breakdown phenomenon requires a large number of capacitors to be broken down in order to provide reproducible data. Generally our experimental procedure was applied to 10x1O arrays of MOS capacitors on each wafer. However, to provide an adequate data base, a 30x30 array of MOS capacitors was chosen which covers most of the area of one wafer. The testing program was designed to reduce this larger 30x30 array into 9 10x10 nested arrays. In this way, 9 independent sets of 100 data points can be generated from each wafer. The prober was programmed to step across the wafer, contacting every third capacitor. Thus the 9 nested arrays are superimposed within the same overall area, and the effects of localized trends, such as varying oxide thickness, are minimized.
411
Fig. 2.
Flowchart of the stepped-field method for determining dielectric breakdown strength.
THE STATISTICAL NATURE OF FIELD-DEPENDENT DIELECTRIC BREAKDOWN Initial efforts were directed to discover the relationship between intrinsic and defectinduced breakdown by breaking down 900 MOS capacitors on one wafer. Extrinsic or defectinduced breakdown is defined as breakdown caused by a defect that formed, or contamination that was incorporated, during oxide growth. Intrinsic breakdown is defined as an inherent property of SiO 2 , which is related to the Si-O bond strength. Intrinsic breakdown occurs at considerable higher values of electric field than extrinsic or defect-induced breakdown. Evidently, the probability of observing defect-induced breakdown in a MOS capacitor is proportional to the area, assuming an oxide with a fixed defect density and with thickness
412
that is independent of position. Therefore capacitors with relatively small area must be utilized so that the defect-induced breakdown distribution does not overwhelm the intrinsic breakdown distribution [5]. It has been shown that the intrinsic breakdown field is proportional to the logarithm of the area of the conducting electrode [61. The stepped-field program was written so that the electric field begins at I MV/cm and steps toward breakdown in increments of 0.1 MV/cm. Baseline data was collected on an oxide that was 630 A thick, and was stressed for a period of 4 seconds at each successively increased field strength.
140
0
1l20 1C0
NUMBER OF DA STRESS TIME: 3 OXIDE THICKNE!
Ir
Defect Induced Distribution
043 23 n 0U
Fig. 3.
J 2
4
0 0 lU 1Z 14 BREAKDOWN FIELD (MV/cm)
10
10
&J
Histogram of breakdown fields illustrating a bimodal nature.
A histogram of the breakdown fields is shown in Fig. 3. From this histogram, it is clear that dielectric breakdown is a non-gaussian phenomenon that exhibits multimodal behavior. It has been shown that the Weibull distribution is appropriate for modelling the statistical nature of dielectric breakdown in oxides [5]. The data were fitted to the Weibull function: F(x)=l-exp[-exp(x)]
(1)
where F(x) is the cumulative distribution function, and x is a dimensionless parameter given by: x = (E-E___ ) S E.
413
(2)
The quantity Em is the modal breakdown field at which point x=0, and 1-e-1 or 63% of the MOS capacitors have broken down. The product SEo is the slope of the Weibull distributions shown in Figs. 4 and 5, and E0 is a characteristic electric field that is related to current injection into the oxide prior to breakdown [7]. The failure rate is given by:
fRx) =!LE = exp[x-exp(x)]
(3)
dx
LN (-LN(I-F)) -7 2D
-6
-5
-4
-3
i
i
i
ij
-2
-1
0
1
-2
3
SAMPLE SIZE 90oo STRESS TIME: 4 SEC
>
15
0
-
OXIDE THICKNESS: 630 Al Em =13.7 CORRELATION: 97.6%/
LL
z
F_. w5.15
10 CORRELATION: 97.4%/
0
0
00 o
.•.. I
< cla
0.5 1 2 5 10 20 50 90 99 CUMULATIVE PROBABILITY OF FAILURE (%) Fig. 4.
Weibull distributions of intrinsic and defect-induced dielectric breakdown illustrating bimodal behavior.
The maximum failure rate occurs when df/dx=0. This yields x=0 and corresponds to the modal value of the breakdown field Em. Two modes were separately fitted to similar Weibull distribution functions by truncating the ranked data, as illustrated in Fig. 4. The upper mode corresponds to the the intrinsic dielectric strength of the SiO 2, whereas the lower mode corresponds to dielectric breakdown associated with extrinsic defects. The correlation coefficient is above 97% for each of the distributions, indicating an excellent fit.
414
THE STATISTICAL NATURE OF TIME-DEPENDENT DIELECTRIC BREAKDOWN
Experimental efforts were next focused on the relationship between the intrinsic breakdown field and the stressing time. Defect-induced breakdowns were omitted from this investigation because of the limited data base and uncontrolled factors comprising their origin. The stepped-field method for breaking down dielectrics provides an accurate control of the stressing time. An analysis of the breakdown field as a function of stressing time was performed on the same wafer for periods of 1, 2,4, 10, 20, and 30 seconds. The data base contains 100 MOS capacitors for each of these stressing times.
co 0
0 a3
15
Fig. 5.
2) 33 40 ED 60 70 8D T 95 99 CUMULATIVE PROBABILITY OF FAILURE (%)
Weibull distributions of dielectric breakdown with varied stressing times.
After the data were collected, the defect-induced breakdowns were removed by truncating the ranked data, and the remaining points were compared with a Weibull distribution. By utilizing a simple independent variable transformation, a straight line could be fitted to the Weibull distribution and the correlation coefficient calculated. Data points were removed from the lower portion of the distribution until the correlation coefficient exceeded 97%. A plot of the breakdown fields fitted to a series of Weibull distribution functions is shown in Fig. 5.
415
The modal breakdown field Em for each Weibull distribution is defined at x=0 for each of the stressing times, and a plot of the characteristic breakdown field as a function of the stressing time is shown in Fig. 6. This plot indicates a logarithmic relationship between characteristic breakdown field and stressing time with a correlation coefficient of 99%.
E
z
2L -J
0 0
Fig. 6.
5
10 15 2 STRESSING TIME (SEC)
25
30
Modal breakdown field as a function of stressing time, fitted to a logarithmic function.
MATHEMATICAL MODEL RELATING PROBABILITY OF BREAKDOWN TO STRESSING FIELD AND STRESSING TIME Cumulative distributions of dielectric failures, plotted as a function of the logarithm of the stressing time, have been observed to undergo a parallel shift that is proportional to the electric stressing field [6, 8]. These observations have led Wolters and Verwey [9] to propose a model that incorporates the combined effect of electric field and stressing time: lni-In(1-F)]
-
ln(t)-In(tm) + E S SE.
(4)
where tm is the modal lifetime, or the stressing time at which the rate of dielectric breakdown events is maximum. With this model, we can predict dielectric breakdown behavior under conditions that may be impractical to measure experimentally, such as for very long stressing
416
times or relatively low stressing fields. vanishes, and we obtain: E
If we set E = Em, then the left hand side of Eq. 4
(5)
= Eo[ln(tm) - In(t)]
The data shown in Figs. 5 and 6 have been compared with this model, yielding empirical values: Eo= 1.42 MV/cm and tm = 1.91 x 104 sec. The fit is excellent for values of t << t.. The data in Fig. 5, however, suggest that the slope is also dependent on stressing time. This feature has not been explicitly incorporated in the model.
S15 -j
z 0
10
0
c
5
-j 0 0 0
Fig. 7.
100
400 500 200 300 ANNEALING TEMPERATURE (°C)
6W0
Modal breakdown field vs. annealing temperature.
BREAKDOWN FIELD VS. ANNEALING TIME AND ANNEALING TEMPERATURE The effect of annealing in H2 was investigated as a function time and temperature. When an AI-SiO 2 contact is annealed, the aluminum interacts chemically with the SiO 2 forming localized regions of A120 3 and releasing free interstitial Si. This process causes pitting of the oxide and forms regions of high electric field concentration. The oxide thickness is effectively reduced in these areas, thereby creating weak spots with an associated reduction in dielectric strength.
417
Four wafers were annealed for 1 hour at 457, 498, 525, and 550 *C. An additional wafer served as a control. The SiO 2 thickness ranged between 615 A and 715 A. The data were then fitted to Weibull distributions, and the modal breakdown fields were determined at x=0. The resulting plot of modal breakdown field as a function of annealing temperature is shown in Fig. 7. This figure indicates that the modal breakdown field is significantly reduced by annealing at temperatures of 500°C and above. The effects of annealing Al-SiO 2 -Si MOS capacitors for extended times at a fixed temperature of 450 °C in H 2 was also investigated. A wafer with 615 A of oxide was selected and annealed for 0, 0.5, 1, 2, 4, 8, and 12 hours (cumulative times). The data were fitted to Weibull distributions, and the modal breakdown fields were determined at x=0. These data indicate a monotonically decreasing relationship between modal breakdown field and annealing time only after an incubation period of 2-4 hours.
17 0
-OXIDE THICKNESS: 555 ANNEAL TEMP: 450 OC
16
_) -T-
z
0 3:
15 14 13 12
0
11 10 0
Fig. 8.
129
240 360 480 ANNEAL TIME (MINUTES)
600
72
Modal breakdown field vs. annealing time.
CONCLUSIONS The stepped-field method is a preferable technique for determining dielectric breakdown strength of thin insulating films, because: 1) it allows accurate control of the stressing time, 2) it guarantees catastrophic breakdown, and 3) it avoids ambiguities related to current transport mechanism. These features are not possible with the ramped-field method.
418
For accurate characterization of dielectrics, automation is essential to generate the large amount of data required for reliable statistical analysis. Dielectric breakdown strength of thermally-grown SiO 2 was found to be bimodal. An intrinsic distribution, associated with the Si-O bond strength, was characterized by a modal breakdown field of 13.7 MV/cm. A second, extrinsic distribution was observed to have a modal
breakdown field of 5.15 MV/cm. The extrinsic distribution is presumed to be caused by grown-in defects related to damage or contamination introduced during wafer production, substrate cleaning, or oxide growth. Modal breakdown fields were observed to be a logarithmic function of stressing time, which is most evident for short stressing periods between 1 and 30 sec. The time-dependent modal values of breakdown field were fitted to a model proposed by Wolters and Verwey, which related the intercept of the Weibull distributions at x=O to a characteristic field parameter E0 for the injection of charge into the dielectric prior to breakdown. Thermallygrown oxides in these observations were characterized by an E0 of 1.42MV/cm. The stepped-field method for dielectric breakdown was also applied to investigate the effects of hydrogen annealing on AI-SiO 2 -Si MOS capacitors. It was observed that the rate at 0 which Al attacks SiO 2 is significant at 500 °C and above. After annealing for 1 hr at 550 C, all MOS capacitors were shorted. However, at 450 °C and lower, degradation of SiO 2 by Al is negligible for annealing periods of 2 hrs. After annealing at 450 'C for extended periods of time up to 12 hrs in H 2 , the modal value for breakdown field decreased monatonically following an incubation period of approximately 2 hrs.
ACKNOWLEDGEMENTS We wish to acknowledge Del Griffanti at Hewlett-Packard for computer support, and Kelly Foster and Steve Labovitz for silicon oxidation and metallization. We would also like to thank Quater Research and Development for their help in designing and fabricating special probe arm assemblies.
REFERENCES [11
P. A. Heimann, "An Operational Definition for Breakdown of Thin Thermal Oxides of Silicon," IEEE Trans. Electron Devices ED-30, 1366 (1983).
[2]
D. J. DiMaria, ''he Properties of Electron and Hole Traps in Thermal Silicon Dioxide Layers Grown on Silicon," in The Physics of SiO2 and Its Interfaces, S. T. Pantelides, ed., p. 160, Pergamon Press, Elmsford, NY (1978).
[3]
C. G. Shirley, "High Field Phenomena in Thermal Si0 2 ," J. Electrochem. Soc. 132, 488 (1985).
419
[4]
J. M. Andrews and G. Smolinsky, "Dielectric Breakdown Strength of LPCVD SiO 2 Deposited at 500 'C," in Proc. 10th Int. Symp. on Chemical Vap. Dep. PV 87-8, G. W. Cullen, ed., p. 497, Electrochem. Soc., Pennington, NJ (1987).
[5]
D.R. Wolters and J. J. Van Der Schoot, "Dielectric Breakdown in MOS Devices. Part I: Defect-Related and Intrinsic Breakdown," Philips J. Res. 40, 115 (1985).
[61 Anolick, E. S., and Nelson, G. R., "Low Field Time Dependent Dielectric Integrity," in Proc. 17th Annual IEEE Reliability Physics, p. 8, IEEE, Piscataway, NJ (1979). [7]
R. H. Walden, "A Method for the Determination of High-Field Conduction Laws in Insulating Films in the Presence of Charge Trapping," 1. Apple Phys. 43, 1178 (1972).
18]
D. L. Crook, "Method of Determining Reliability Screens for Time Dependent Dielectric Breakdown," in Proc. 17th Annual IEEE Reliability Physics, p. 1, IEEE, Piscataway, NJ (1979).
[9]
D. R. Wolters and J. F. Verwey, "Breakdown and Wear-Out Phenomena," in Instabilities in Silicon Devices: Silicon Passivation and Related Instabilities, Vol. 1., G. Barbottin and A. Vapaille, eds., p 338, Elsevier Science Publishers B.V., New York, N.Y. (1986).
420
TOP-OXIDATION EFFECTS ON THE RELIABLITY OF OXIDE-NITRIDE-OXIDE (ONO) STACKED FILM
Kenji Yoneda, Tetsuo Ishida, YoshihiroTodokoro, Morio Inoue Kyoto Research Laboratory, Matsushita Electronics Corporation 19, Nishikujo-Kasugacho, Minami-ku, Kyoto 601 JAPAN
Effects of top-oxidation on the reliability of Oxide/Nitride/Oxide (ONO) stacked films have been investigated. The leakage current, electric field acceleration factor (13)and reliability of ONO stacked films are strongly affected by the top-oxide thickness and the oxidation methods.The optimum top-oxide thickness on the nitride film is 2 to 3nm. Leakage current and P3 are improved by the dry/TCA top-oxidation instead of dry oxidation. By using the dry/TCA top-oxidation, high J,1ow leakage current, low defect density and highly reliable ONO stacked films can be obtained. The dry/TCA top-oxidation of nitride is suitable to get a highly reliable and high performance ONO stacked film for high density DRAM and FPGA.
INTRODUCTION Highly reliable thin insulator films below 10nm are needed for cell capacitors of DRAM (dynamic random access memory) and gate insulator of other MOS devices. In particular, Oxide/Nitride/Oxide (ONO) and Oxide /Nitride (ON) stacked films are the most promising candidates for stacked cell capacitors of DRAM, inter-polysilicon insulators of EEPROM (electrically erasable and programmable read only memory) and anti-fuses of FPGA (field programmable gate array) . The ONO and ON stacked films have been reported to be highly reliable compared with thermally grown oxides for three dimensional structure capacitors and inter-polysilicon insulators [1][2] [3]. In particular, for inter-polysilicon insulator thermally grown oxide has poor dielectric strength and reliablity due to the surface roughness and grain structure of polysilicon film. Therefore, ONO or ON stacked films are suitable for inter-polysilicon insulators such as stacked capacitor of DRAM and control gate insulator of EEPROM. However, dielectric reliability and electrical characteristics of ONO stacked films are strongly affected by the top-oxidation condition of nitride film. For stacked capacitors of DRAM and anti-fuses of FPGA[4] , low defect density, large electric field acceleration factor 13and low leakage current are required. This paper describes the effects of top-oxidation on the reliability of ONO stacked films and improvement of the dielectric reliability of ONO stacked films by using dry/TCA top-oxidation. 421
EXPERIMENTAL Sample fabrication The sample fabrication flow of stacked capacitor with ONO stacked insulator used in this study is shown in Fig. 1. The 150mm diameter, (100) orientation,8-120cm, N-type silicon wafers were used. After LOCOS isolation , the 400nm thick LPCVD polysilicon deposition and subsequent phosphorus doping are done at 9501C for 20 minutes with POC13 as the bottom electrode. After removing the native oxide on the bottom polysilicon electrode by HF solution, the 1 lnm thick LPCVD silicon nitride film was deposited at 780'C using SiH 2Cl2 and NH 3 and subsequent top-oxidation was performed by the dry , pyrogenic steam and dry/TCA ( dry oxidation with 4wt%, CH3CCl3: trichloroethane) oxidation at 9000C. The 250nm thick LPCVD polysilicon was deposited on the ONO stacked film as the top electrode and phosphorus doping was carried out at 950°C for 15 minutes with POCI3 . After top electrode formation stacked capacitors were fabricated by using the conventional MOS capacitor fabrication technique. The schematic cross section of stacked capacitor and detail cross section of ONO stacked film are shown in Fig.2 (a) and (b), respectively. N-type Si(100) substrate
Al electrode
2ndpoly S! 250nm
LOCOS isolation 700nm 1st Polysilicon deposition 400nm
(Bottom electrode) Phosphorus doping 9501C
LPCVD SiaN4 deposition 11 nm Top-Oxidation of Si3N4 9f0,,C Dry / Pyrogenic / TCA(4wt%) 2nd Polysllicon deposition 250nm (Top electrode) Phosphorus doping 950eC CVD Si1O deposition
I
ONO Stacked Film Structure
Contact Opening
I p -oxide
Aluminum deposition
Nitride (Sil4) .. E
Bottom-oxide
(Native oxide)
Fig. 1 Process flow of ONO stacked capacitor
Fig.2 (a) Schematic cross section of ONO stacked capacitor (b) ONO stacked film structure 422
Measurements To measure the top oxide thickness Auger Electron Spectroscopy (AES) analysis is performed. For the electrical characteristics and reliability evaluation, high frequency-
CV,current-voltage (I-V), breakdown field measurement and constant voltage TDDB
(time dependent dielectric breakdown) measurements were done. For high frequency CV, current- voltage and trap measurements, samples with 1mm 2 gate area were used. Dielectric breakdown fields measurements were made on the samples with 10mm 2 gate area and 136 samples were used. Constant voltage TDDB were measured on the samples with lmm2 gate area and 136 samples were used for each stress conditions. The effective thickness was calculated from high frequency CV measurements. RESULTS AND DISCUSSION
Top-oxidation conditions and top-oxide thickness Table 1 shows the top-oxidation condition, effective thickness of the ONO stacked film (SiO2 compatible) measured by HF-CV technique, oxide thickness on the single crystalline silicon was measured by ellipsometer, and estimated thickness of the top oxide on the nitride by AES depth profile. The results of AES depth profile analysis (not shown) indicate that the top-oxide layer consists of SiNO and SiO2. Near the top-oxide and silicon nitride interface region, the SiON and SiO 2 mixing layer is observed. For the 900"C,30 minutes dry oxidation, the top-oxide thickness on the nitride is 0.8nm. Even with the increase of the oxidation time to 90 minutes, the increase of top-oxide thickness is very small (. lnmn). This small oxidation rate is caused by the low diffusion coefficient of 02 in the silicon nitride film. The oxide grown on single crystalline silicon using the 9001C, 30 minutes pyrogenic steam oxidation is very similar (32nm) to the dry oxidation done at 90 minutes (25nm). However, the top-oxide thickness with the pyrogenic steam condition is much greater (2.4nm) than the dry oxidation process. Furthermore, for the 90 minutes dry/TCA oxidation at 9001C top-oxide thickness is 2.5nm which is comparable with that under the pyrogenic steam oxidation. For the pyrogenic steam oxidation, oxide growth rate is increased by the OH diffusion. For the TCA oxidation, the OH and Cl enhances oxidation rate [5]. Table. 1 Top-oxidation condition vs. effective thickness and top-oxide thickness Top oxidation condition 9000C 900 0 C 900W C 9000 C 850' C
DryOx. Dry Ox. Pyro Ox. TCAOx. Pyro Ox.
30min. 90min. 30 min. 90rmin. 60 min.
Teff
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423
SiO 2 on Si Top Si02(nmn) (nm) AES I HF-CV 13 0.8 1.1 25 1.1 1.4 32 2.4 2.0 32 2.5 2.0 28 2.2 2.0
Leakage current of ONO film Figures 3 (a) and (b) show the current-voltage (I-V) characteristics of ONO stacked capacitors obtained by applying the positive and negative bias to the top electrode, respectively. In the positive bias case, drastic reduction of leakage current is observed for the dry/TCA and pyrogenic steam oxidation. For the dry oxidation, a large amount of leakage current was observed. Assuming that the Pool-Frenkel conduction is dominant as an electrical transport mechanism in a nitride film, hole injection from the top electrode is dominant for the positive bias. In the case of the dry oxidation, the topoxide is so thin (
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The bottom oxides have poor dielectric characteristics, since they are mainly grown during the wafer pushing sequence in the LPCVD nitride furnace process. Even though the bottom oxides are thicker than top-oxides, holes can easily flow through the bottom oxide due to the poor dielectric characteristics. The leakage current was strongly affected by top-oxide thickness and decreased with increasing the top-oxide thickness. From the view point of leakage current, the TCA and pyrogenic steam oxidation are an effective method of suppressing the leakage current of the ONO stacked film. Dielectric breakdown Figures 4 (a) and (b) show the dielectric breakdown histograms of ONO stacked capacitor for the dry (900°C,30min,top-oxide:0.8nm) and pyrogenic (900 0C,30min,topoxide:2.4nm) top-oxidation. Effective thickness of ONO stacked films for dry and pyrogenic oxidation are 7.3nm and 8.lnm,respectively. Hatched and dotted bars correspond to negative and positive bias, respectively. Most of dielectric breakdowns occur at high field (>8MV/cm) for both top-oxidation conditions. (a)
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Low field (14MV/cm) the MITF5o's for the dry/TCA and the pyrogenic top-oxidation are shorter than that for the dry oxidation.
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TIME TO BREAKDOWN (SEC) Fig.5 weibull-plot of constant voltage TDDB characteristics of ONO stacked capacitor for various top-oxidation conditions 426
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Fig.6 Time to 50% cumulative failures (MTTF5o) of ONO stacked films for various top-oxidation condition under the positive high fields (>14MV/cm) and medium high fields. The electric field acceleration factor P for the dry top-oxidation is 0.46 decade/V and does not depend on oxidation time. On the other hand, from Fig.6 (a) for the dry/TCA and pyrogenic top-oxidation, 13 becomes larger than that for the dry oxidation and are 0.65 and 0.58 decade/V, respectively. From Fig.6 (b), the 13 for the dry, pyrogenic and dry/TCA oxidation are 0.52, 0.93 and 1.14 decade/V, respectively. On the basis of this 0 value, MTTF5o's for the dry/lCA and pyrogenic top-oxidation at the operating voltage (2.5-4V) are estimated to be longer than that for the dry top-oxidation. Figure 7 shows MTTFso of the ONO stacked capacitor as a function of stress voltage for negative bias. The MTTF50 and 13are almost same for the all top-oxidation conditions P range from 0.5 to 0.6 decade/V. These results indicate that the MTTF5o for the positive bias and for the negative bias depends on the top-oxide and on the bottomoxide, respectively. From these results the dry/TCA top-oxidation is most suitable to get a high performance ONO stacked film with low leakage current, high reliability and large 13. The optimum top-oxide thickness is 2 to 3nm. The precise control and film quality control of bottom oxide is also important to form the highly reliable ONO stacked film. 427
Figure 8 shows the MTTF5o of the ONO stacked capacitors for pyrogenic steam topoxidation at 8501C and 900 0 C. The 3 value tends to be higher with increasing oxidation temperature. High temperature top-oxidation gives high 03and high reliability. However, the top-oxidation temperature becomes a trade-off between thermal budget and performance. Figure 9 shows the gate voltage variation (AVg) during current injection vs. injection current density of the ONO stacked film for various top-oxidation conditions. The behavior of AVg of the ONO stacked film is interpreted as follows. At the initial stage of current injection, holes are trapped at the SiO2/Si3N4 interface and increases the electric field across the film. At the next stage, electrons are trapped at the SiO2/Si3N4 interface. For the dry top-oxidation hole trapping is dominant. On the contrary, for the dry/TCA top-oxidation electron trapping is dominant. As shown in Fig.9, charge trapping behavior of the ONO stacked film varies depending on top-oxidation conditions. The 0 difference may be attributed to charge trapping difference mentioned above. The dielectric reliability of ONO stacked films strongly depend on the top-oxidation thickness and process method. Even if the topoxide thickness is equal, the dielectric reliability is dominated by the top-oxidation method. IN (V-') iN (V-') 8
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Fig.8 Time to 50% cumulative failures of ONO stacked films for different top-oxidation temperature under the positive fields 428
The dry/TCA and pyrogenic top-oxidation have higher 0 than the dry top-oxidation. This is due to the thickness difference of top-oxide. Moreover, the dry/TCA topoxidation has higher 0 than the pyrogenic top-oxidation. This result may come from the difference of top-SiO2 Si 3 N 4 interface structure caused by adding the C1 during oxidation. 15 1
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INJECTED CURRENT DENSITY (A/crf ) Fig.9 Gate voltage variation vs. injection current density for various top-oxidation conditions SUMMARY Effects of top-oxidation on the reliability of ONO stacked film has been discussed. and the reliability of the ONO The leakage current, electric field acceleration factor J0 stacked film are strongly affected by the top-oxidation conditions. (1)Dry/TCA and pyrogenic top-oxidation are effective to suppress the leakage current of ONO stacked films. This result can be explained by the difference of top-oxide thickness. For dry/TCA and pyrogenic top-oxidation, thick top-oxide can be obtained. (2) From view point of dielectric reliablity,the optimum top-oxide thickness is 2 to 3 nm. Control of the bottom oxide thickness and quality are also important in getting highly reliable ONO stacked films. Top-oxide thickness and oxidation condition (temperature and ambient) should be determined by the combination of leakage current, effective thickness, dielectric reliablity and thermal budget. (3) Leakage current and 03were improved by the dry/TCA and pyrogenic top-oxidation. In particular, using the dry/TCA top-oxidation, P is improved drastically and low leakage current, low defects density and highly reliable ONO stacked films can be obtained. This superior dielectric characteristics may come from the difference of top-SiO 2 /Si 3 N4 interface structure. 429
The dry/TCA top-oxidation of nitride is very useful to get a highly reliable ONO stacked film and a promising technique for realizing a high performance DRAM, EEPROM and FPGA.
ACKNOWLEDGMENT The authors wish to thank to Mr.H.Iwasa and Mr.H.Koide for their continuous support and encouragement. The authors thank to Pilot Production Department for their careful processing and Support Technology Department for their support of measurements and AES analysis. The authors wish to thank to Mr.Royce Richter of Matsushita Semiconductor Corporation of America for his useful discussion and language assistance.
REFERENCES [1]T.Watanabe, N.Goto, N.Yasuhira, T.Yanase, T.Tanaka and S.Shinozaki,1987 Proc. Int. Reliability Phys. Symp.,p50,1987 [2]Y.Ohji, T.Kusaka, I.Yoshida, A.Hiraiwa, K.Yagi and K.Mukai, 1987 Proc. Int. Reliability Phys. Symp.,p55,1987 [3]J.Yugami, T.Mine, S.Iijima and A.Hiraiwa, Extended abstracts of the 20th conference on SSDM, p. 173 , 1988 [4]S.Chiang, R.Wang, J.Chen, K.Hayes, J.McCollum, E.Hamdy and C.Hu, 1990 Proc. Int. Reliability Phys. Symp., p.186, 1990 [5]A.E.Kuiper,M.F.C.Willemsen,M.L.Mulder,J.B.Oude Elferink, F.H.P.M. Habraken and W.F.Van der Weg, J. Vac. Sci. Technol., B7, p.455, 1989
430
THIN GATE OXIDE INTEGRITY IN FLUORINATED MOS STRUCTURES W.M. Greene and T.E. Kopley Circuit Technology Research and Development Hewlett Packard 3500 DeerCreek Road Palo Alto, CA 94303 and O.S. Nakagawa Center for Electronic Materials and Processing The Pennsylvania State University University Park, PA 16802 oxide MOS (and chlorinated) Fluorinated capacitors and MOSFETs were studied by Fowlerdielectric time-depedendent Nordheim injection, hot carrier stress. and channel breakdown, Fluorinated and chlorinated oxides have more hole With interface traps. traps but have less initial stress the amount of interface states generated is oxides. The fluorinated oxides similar for all Hot carrier have thicker effected oxide thickness. stress on MOSFETs showed devices with fluorinated oxides, but no chlorine, had longer lifetimes at high stress voltages than devices with chlorinated voltages to operating Extrapolation oxides. predicted that chlorinated oxide devices will have Devices with both fluorine the better reliability. and chlorine incorporation have worse lifetimes, than both at stress and operating conditions, devices with chlorine incorporation only. INTRODUCTION Producing reliable thin dielectrics for CMOS applications involves gate oxide engineering to minimize degradation Incorporation of during device operation and stress. various amounts of F via implantation into the polysilicon Oxide charge gate has attracted significant interest. time dependent state generation, interface trapping, (TDDB), and channel hot electron breakdown dielectric degradation mechanisms that are desired trapping are all to be minimized. EXPERIMENTAL Test Structures -
431
Capacitors
Injection experiments were perfor~ied on polysilicon gate MOS capacitors of area 1 x 10' cm' and isolation edge of 4 x 10 cm. The polysilicon edge overlaps the field oxide by 1 m. The capacitors were fabricated on a substrate consisting of a epitiial layer of p-type silicon, doping concentration 8 x 10 cm- and thickness approximately 6 m, grown on a p-type silicon substrate. These capacitors were fabricated along with n-channel MOSFETs of drawn gate length down to 0.5 m, and therefore got both a threshold voltage adjust implant and a punchthrough control implant. These imp~jntsyive the substrate an effective doping of -1.5 x 10 cm . The isolation used is SWAMI.[1] The gate oxide is a dry thermal oxide grown at 850 0 C with a post oxidation anneal in N2 for 30 minutes. The oxide thickness is approximately 10 nm to 12 nm thick. Chlorine is incorporated into the oxide by flowing a carrier gas through a TCA bubbler for the final 10 minutes of oxidation. Fluorine is added to the oxide by implantation at 25 keY into the polysilicon gate and subsequent diffusion during later thermal process steps. Table 1 shows the oxide process and the resultant concentration of F or Cl as determined by SIMS. Note that fluorinated oxides all have the 10 minute TCA step. The gate material is 250 nm of LPCVD deposited polysilicon doped with POCL3 at 9000 C. The POCL3 doping occurs after the F implant, and dopes the polysilicon degenerate. Metal Oxide Semiconductor Field Effect Transistors N-channel MOSFETs with LDD source and drain were fabricated along with MOS capacitors. The measured FETs were all L=0.6 m and W=10 m drawn. Effective channel lengths were not measured on these structures, but should be Leff -0.4 m. The MOSFETs were subjected to the same fluorine and chlorine process steps as the MOS capacitors. Additional fluorinated MOSFETs from a different lot with oxide thickness 15 nm and no TCA step during the oxide growth were also measured. Te LDD structure of the MOSFETs consisted of a 4 x 1013 cm dose of phosphorus at 30 keV and 00 implant angle. A 1600 TEOS oxide was used as a spacer Aateri.al. The source and drain were implanted with 3 x 10 cm arsenic and annealed at 9000 C for 30 minutes. The devices had titanium salicidation and 7000 PSG deposited over them. After contact etching, a metal consisting of 1500 TiW diffusion barrier and 5000 aluminum doped with 4% copper was deposited and etched. A TEOS oxide of 5000 was used for passivation. 432
Electron Injection Electron injection experiments were performed on the MOS capacitors. The applied voltage used for injection was a constant 12 V which resulted in electron injection from the Si substrate. The injection current was varied by illuminating the capacitors with white light of varying intensity. This effectively produced injection of constant current as well as voltage. Without light, no FowlerNordheim current flowed at 12 V, which we attribute to the lack of minority carriers in the p-type substrate due to their small generation rate. The light produces electronhole pairs which produces current characteristic of FN tunneling. In thee expqjiments, the injection current was held at 1.5 x 10- A/cmF and the temperature was held at 250 C.
Both the flatband voltage, VFB, and the interface trap density at midgap, N. , were monitored as a function of electron fluence. -ach data point is taken from a different capacitor which was stressed for the desired time and then measured by high frequency CV at
1MHz and GV at
200 kHz. This frequency was chosen because it was the frequency of highest conductance on G vs. freq. curves with the capacitors biased to flatband conditions. Separate capacitors were used because relaxation effects associated with taking the devices off stress to do the measurements skewed the results. The curves shown in this paper are representative of all data obtained. The consistency of the data is due to the uniformity of the oxide across the wafer, measured by CV to be ± 0.2 nm. Time Dependent Dielectric Breakdown (TDDB) TDDB was performed on large area (0.032 cm2 ) capacitors that minimize isolation and diffusion edge components. The tests were performed at 8 MV/cm in accumulation at 1500 C. Hot carrier lifetime The hot carrier lifetime of MOSFETs was measured using a unique test structure that allowed the simultaneous DC stress of up to 20 FETs all at different Vds and Vgs. This allows one to extrapolate to operating conditions from a single stress measurement. The test structure consists of 20 FETs all of the same length and width connected with a common source, gate, and substrate. The common source is the key to the structure. It consists of a single Al interconnect of width 5 m which runs from the source probe pad to the end of the structure. Along its length are 433
attached the source diffusion of each FET. It is designed with enough series resistance between FETs (-2 ) so that each FET sees a different source resistance. The actual series resistance is easily measured using the last FET as a current source and all the other FETs on the source line as voltage probes. The combination of all the stress currents that flow from each transistor then produce a different source voltage drop for each FET. This in turn, produces different stress voltages, Vds and Vgs, on each FET. This structure will produce DC stress voltages constant in time only when the stress currents remain constant in time. One must be careful to monitor stress currents, and FET designs that have an intrinsically large shift in I with hot carrier stress will not work well. with is structure. Since the stress currents produce the source voltage drop that determines the stress voltages, and the stress currents are dependent on the stress voltages, finding the true stress voltages requires a self-consistent calculation using the measured IV curves of the stressed FETs and the measured series resistance noted above. Lifetime is defined as a 10 % change in the linear region Ids (@ Vds=. 1 V and Vgs=4 V) for each stress voltage. The set of lifetime, Vds pairs is fit to a straight line, which is extrapolated to Vd- at operation conditions to give a lifetime at operation conditions. Other parameters monitored include linear region transconductance, gm (@ Vds=.l V and Vgs=4V) and threshold voltage, VT. VT for these LDD devices changes very little and is not a good monitor of hot carrier degradation. RESULTS General observations The fluorinated oxides show trends in oxide thickness, I sat and VT as shown in Figs. 1 and 2. The larger the fluorine concentration, the larger the effective thickness of the oxide. This trend is mimicked in the device Idsat and the TDDB t5 n results. This could be due to variations in dielectric constant; or it may be a structural effect that occurs during subsequent thermal processes involving the fluorine's effect on the mobility and reactivity of the oxidant species. There is also a trend in VFB and V associated with F concentration. The differences in tliese characteristic voltages are too large to be due to differences in oxide thicknesses (or dielectric constants) alone. The positive 434
shift in these parameters could be due to differences in positive oxide charge, N , between the various oxides. More likely it is due to enhanced boron diffusion through the polysilicon gate in the presence of fluorine[2]. CV measurements show that the substrate doping concentration indeed changes for oxides implanted with BF2 . This explains the largest shifts in the oxides implanted with BFV, but not the shifts in oxides with different F implants. Oxides implanted with F only do not have the boron to change the substrate doping, which has been verified by CV measurements. In these devices, F compensation of the P dopant in the polysilicon is possible. The compensation would change the work function difference between the p-type silicon substrate and the ntype polysilicon gate. This effect has been observed in devices with F implanted directly into the substrate of MOS capacitors[3]. The same effect could occur in polysilicon if the polysilicon is only marginally degenerately doped. Injection experiments Fig. 3 shows the flatband voltage shift vs. electron fluence for various F implantation doses. The initial shifts are negative with a reversal of sign near 0.2 C/cm . This implies some sort of hole generation and trapping for low fluence which is then compensated at longer injection times by electron trapping. This is consistent with previous work of Nishioka et al.[4] who studied FN injection of ultra-dry oxides. Their fluence at which sign reversal of voltage shift occurs is near 0.1 C/cm . This may be due to differences in the quantity of hole traps and/or the electron trapping cross-section between our oxides and theirs. Again looking at the low fluence regime, one sees that the higher the F dose, the greater the V B shift. (The same trend was seen in chlorinated oxides. - The effective positive oxide charges (assuming the charge resides at the Si-SiO2 interface) responsible for the observed VJB shifts are noted in the figure. The calculated values are approximately an order of magnitude greater than the measured changes in interface trap density at the same fluence which gives us confidence that the shifts are mostly due to oxide charges. It is possible that the fluorinated oxides have, besides the hole generation mechanism seen in non-fluorinated oxides, another hole generation and trapping mechanism that is influenced by the presence of fluorine and chlorine. Two separate and noninteracting mechanisms with different cross-sections and saturation values could be detected by observing the characteristic charging of these sites. Unfortunately, 435
these characteristics are masked by electron trapping and trap generation. At larger electron fluences, the VFB shifts reverse their earlier trend and eventually changed sign. The plots of VFB vs. fluence show that the shifts do not saturate. (Measurements up to the charge to breakdown, Qbd 1 C/cm, of the oxides were performed and showed no saturation.) This is because electron traps are being generated during the injection. Our oxide electric field is -11 MV/cm, which is far above the threshold field needed for electron trap creation.[5,6] Another oxide parameter of interest is the interface trap density, Nit. The measured interface trap density as a function o• fluence is qualitatively the same for Cl and F impregnated oxides. Figs. 4 and 5 plot midgap Nit vs. fluence for chlorinated and fluorinated oxides. The initial N. for both Cl and F oxides shows a consistent trend: thelVigher the halogen concentration the smaller the initial Ni. The Cl oxides, however, show negligible difference in N. generation with Cl concentration. F oxides show a larger initial difference in N-t, but the amount of Nit generated seems independent of F concentration. All curves show a notable kink near 0.1 C/cm fluence. These curves are qualitatively different from previously reported interface trap generation by FN tunneling.[4,5,7] A correlation of interest would be between the oxides' hole trapping qualities and interface state generation. For instance, if the mechanism of interface trap creation due to trapped hole annihilation occurs in these oxides , one would expect to see more interface trap generation with oxides of larger hole trapping (those with more F and Cl as shown above). Unfortunately, the characteristic energy of these types of interface states lie in the upper portion of the bandgap, and the midgap N.t does not monitor them. Experiments are continuing to proe N. in the upper levels of the bandgap. Compensation of anyltrapped holes occurs above 0.2 C/cm2 as shown in Fig. 3, 2but N.it generation eerto decreases markedly after only 0.1 C/cm . The shape of the N.t curves seem correct though, as one would intuitively tAink that hole annihilation would occur at the start of injection and give a larger Nit generation rate there.
Hot carrier stress Hot carrier lifetime in hours as a function of I/Vds at 436
stress are shown in Figs. 6 and 7. Fig. 6 data comes from MOSFETs processed as described above. Note that devices with the F implant show worse lifetimes than the control devices that have the TCA oxide only. Also the slope of the curves are different, as the TCA oxide has higher slope and will have an even higher lifetime at operation conditions. The lifetime extracted for 10% change in the parameter shows the same difference in slope between the two types oxides although the absolute lifetimes are much closer in value between the two types of oxide devices. Using this lifetime to compare devices still shows nonfluorinated oxides to have the best reliability. g
These results are in contrast to previously reported work on hot carrier stress in fluorinated oxides.[9,10] The work of Kasai et al. (10] showed that non-fluorinated oxides have a smaller slope in lifetime vs. i/Vds than fluorinated oxides. Since our device processing sequence is much different, and our gate oxide recipe includes TCA oxides, a direct comparison is difficult. Another parameter these authors note is the slope of the degradation vs. stress time curves. Our slopes for this curve are much smaller than reported by Kasai et al. and references therein, being -0.17-0.2 for TCA oxide devices and -0.19-0.22 for fluorinated oxides. Then slopes quoted above are for devices stressed up to 10 seconds, but it is well known that degradation does not follow a pure logarithm formal], but that the slope of the degradation vs. stress time decreases with increasing stress time. The initial slopes in our degradation experiments are actually higher than the ones quoted above for long stress time. The initial slopes are -0.33-0.35 for TCA oxide devices and -0.27-0.29 for fluorinated oxide devices for stress times up to 1000 seconds. Other workers have noted, though, that the beneficial effects of fluorine in gate oxides can be masked by the presence of chlorine.[ 12] We have therefore also measured MOSFETs that contain fluorine, but no chlorine. These devices were processed similarly to the devices described above, but had 150 gate oxides and concomitant VT implant differences. Most important, the fluorinated oxide devices had no chlorine in their oxides. Results on measurements on these devices are presented in Fig. 7. Note that the fluorinated oxide devices show a longer lifetime than the devices with the control oxides that have only chlorine. Again, as in Fig. 6, the nonfluorinated oxide devices show a larger slope in the 437
lifetime vs. i/Vds curve. Extrapolated for operating conditions (Vd - 4.0 V) the non-fluorinated oxides will have a longer lifetime. Again, using 10% change in gm as a definition of lifetime gives the same trend. These results are intriguing though, and further study is continuing. The results on the 150 devices may point to a gate oxide thickness dependence, not just an effect of chlorine on hot carrier hardness of fluorinated oxides. Measurements of lifetime vs. substrate current, which were not possible with our test structures used in these studies, will be done on packaged devices allowing better statistics and give substrate current also. CONCLUSIONS MOS capacitors and MOSFETs with various amounts and combinations of fluorine (and chlorine) incorporated into their gate oxides have been studied using Fowler-Nordheim (FN) injection, time-dependent dielectric breakdown (TDDB), and channel hot carrier stress. The FN injection showed chlorinated and fluorinated oxides to have more hole traps than oxides with neither chlorine nor fluorine. In addition, fluorinated oxides had less initial interface traps, but the same amount of interface trap generation as non-fluorinated oxides. The fluorinated oxides had thicker effective oxide thicknesses as measured by TDDB and electrical characteristics. Channel hot carrier stress on MOSFETs showed devices with fluorinated oxides, but no chlorine, had longer lifetimes at high stress voltages than devices with chlorinated oxides. Extrapolation to operating voltages predicts that the chlorinated oxide devices will have the better reliability. Devices with both fluorine and chlorine incorporation have worse lifetimes, both at stress and operating conditions, than devices with chlorine incorporation only. ACKNOWLEDGEMENTS The authors would like to thank the Silicon Process Laboratory at HP, Irene Leal for processing coverage, John Turner for SIMS analysis, Tom Dungan for help in hot carrier data analysis, and T.P. Ma for useful discussions. REFERENCES [1]. K.Y. Chiu, J.L.Moll, and J. Electron Devices ED-28, 1115 (1981).
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Manoliu,
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X.W. Wang, A. Balasinski, the
1990
IEEE
in Proceedings
and T.P. Ma, Interface
Semiconductor
IEEE
Baker,
Specialists
Conference. [4]. Y. Nishioka, Y. Ohji, I. Yoshida, Sugano, J. Apple. Phys. 67, 3903 (1990). [5].
D.J.
2342
(1989).
DiMaria and J.W.
Stasiak,
T. Nishida and S. [6]. IEEE IRPS, 310 (1991).
Thompson,
[7]. Phys.
S. Horiguchi, T. 58, 387 (1985).
Kobayashi,
[8].
S.K.
Lai,
J.
Apple. Phys.
K.
J.
Mukai,
Apple. Phys.
Proceedings of the
and K.
54,
2540
[9]. Y. Nishioka, K. Ohyu, Y. Ohji, Electron Device Lett. 10, 540 (1989). (10]. N. Kasai, P.J. Wright, and K.C. Electron Devices 37, 1426 (1990).
Saito,
T.P. Ma,
private communication.
439
J.
65, 29
th
Appl.
(1983). and T.P.
Ma,
IEEE
Saraswat, IEEE Trans.
(11]. K.M. Cham, J. tui, P. van Voorde, and Proceedings of the 25 IEEE IRPS, 191 (1987). [12).
and T.
H.S.
Fu,
Table 1. Summary of F and Cl concentrations as measured by SIMS mCl]
Film
IF]018
no TCA 1 min TCA 10 min TCA
<2 <2 <2
1 5 30
50 100 >100 >100
30 30 30 3
10 min TCA with: 5 1 2 2
x x x x
1014 /cm2 10 1 5 /cm2 1015/cm2 1015/cm2
F+ F+ F+ BF 2 +
440
ý35
a
J
3
2
1
15 Cm2 F implant dose (xlO
Figure 1. Effective oxide thickness as a function of fluorine implant dose as measure by IV, CV, and TDDB techniques.
40
70
39
38
-
<-- -1
0 60:
36
0ý5(
35 0
1
2
3
4
F implant dose (x 1015)
Figure 2. Threshold voltage and drain saturation current as a function of fluorine implant dose.
441
12u
* control 14 (5 xx 10 lcm l'cm-• F (2 o F
100 80 60 40
BF 2 (2 x 10
15
-2 2)
cm -2)
20 01 0
-20 -40 >z -60 0
'--v
--.''n
0. 0
0.2
0.1
0.3
0.4
Fluence (C/cm2 ) Figure 3. Flatband voltage shift as a function of electron fluence for various F implantation doses.
3
2 >1)
"0
1
n 00.0
0.1
0.2
0.3
0.4
Fluence (C/cm2)
Figure 4. Midgap interface state density as a function of electron fluence for oxides of varying chlorination.
442
3
2
2) N 2)
a) C)
S 1
&
control
0
"F(5
a)
14
10
cm)-2
F (2 x 10 cm BF2 (2 x 10 15 cm-2 )
-J
V
0 0.0
x
0.1
0.2
0.3
0.4
Fluence (C/cm2
Figure 5. Midgap interface state density as a function of electron fluence for oxides of varying fluorination.
o *
0 0
chlorine 15 chlorine+2 x 10 F
100
o) 0 o)
10 0.18
A 0.19
0.20
l/VDS Figure 6. Hot carrier lifetime (10% g.) as a function of I/Vds for fluorinated and chlorinated 120 A oxides.
443
1n(ncf I.
o
no ch?:ine
100 0
i n0 A
0.17
0.18
0.19
1/VDs Figure 7. Hot carrier lifetime (10% g.) as a function of l/Vds for fluorinated and non-fluorinated 150 A oxides.
444
ELECTRICAL AND STRUCTURAL PROPERTIES OF ULTRATHIN Si02 GATE DIELECTRICS PREPARED UNDER VARIOUS CONDITIONS P. Lange, L. Schmidt, M. Pelka*, P. Hemicker, H. Bemt, and W. Windbracke Fraunhofer-Institut for Mikrostrukturtechnik, Dillenburger Str. 53, 1000 Berlin 33, FRG We have fabricated ultrathin SiO 2 layers between 5 and 10 nm. Conventional thermal and rapid thermal oxide forming processes were applied as well as a low temperature chemical vapor deposition (CVD) process. With these dielectrics, single layers have been produced for structural investigations by infrared (IR) absorbance spectroscopy. The IR-spectra of the thermal oxides and the postannealed CVD-oxide revealed nearly the same vibrational properties. MOS devices such as capacitors and field effect transistors (FETs) have been fabricated with these dielectrics. Breakdown measurements revealed a reduced high field breakdown voltage with a broadened distribution for CVD layers as compared to the results obtained for thermal oxides. This effect was reduced with decreasing thickness. From transfer characteristics and charge pumping measurements on FETs, no considerable difference in the number of fixed oxide charge and interface trapped charge density was observed for all oxides. The device properties appear to be more strongly effected by substrate dopant concentrations and the oxide thickness than by the intrinsic properties of the oxide.
INTRODUCTION The upcoming generations of 16 Mbit DRAMs and beyond require gate dielectrical layers with an effective oxide thickness of 10 nm and below . This increases the demands regarding the structural and electrical properties of dielectrical layers. Ion-diffusion blocking properties and hot carrier resistance become more significant as miniaturization increases. Aside from new approaches with oxide-nitride-oxide (ONO) thin multilayer systems [1,2], silicon oxynitride layers [3] or fluorinated gate dielectrics [4,5], silicon dioxide still plays a major role in the application as gate dielectrica [6,7,8]. In addition, in such highly integrated devices, there is a growing need for low-temperature, short-time processes in order to keep doping profiles present address:
Fraunhofer Arbeitsgruppe fOr Integrierte Schaltungen, Artilleriestrale 12, D-8520 Erlangen, FRG 445
shallow. This is why current efforts are focussed on rapid thermal processing [9,10] and low-temperature processing [11,12] of dielectrics. In a previous study we reported on the structural conformalities between postannealed CVD-oxide layers and thermally grown oxides in the 140 nm thickness range [13]. This result was concluded from infrared (IR) absorbance and wet chemical etching experiments. The question remains if this result is also obtainable for ultrathin layers and if there is a relationship to the electrical performance of such layers. Thus, we conducted a study in which Si0 2 was processed by low temperature deposition and subsequent annealing by rapid thermal oxidation and via conventional thermal oxidation. Thin layers in the 5 to10 nm range were then investigated by infrared absorbance measurements. For electrical characterization, breakdown measurements were carried out on MOS capacitors. In addition, n-channel MOSFETs have been fabricated and the transfer characteristics have been measured. The threshold voltages and transconductances were determined and compared to values received from device simulation. The interface trapped charge density was calculated from charge pumping measurements. EXPERIMENTAL WAFER PROCESSING Single films and MOS devices have been fabricated on 4 inch, n-Si (100) wafers, using three different oxidation processes, as described below: (a) Furnace oxidation (OX) in 02 at 9000C (ASM) (b) Rapid thermal oxidation (RTO) at 10500C in a rapid optical annealer (Eaton). This device is initially equipped with N2 , Ar gas lines for short-time, high-temperature activation or annealing, but through the introduction of 02 gas into the system, rapid thermal oxidation is possible. (c) Low temperature oxide (LTO) deposition in a low pressure-CVD reactor (ASM) at 4300C by reaction of SiH 4 and 02. The annealing of the LTO layers was carried out in N2 atmosphere at 9000C and 10000C for 30 min. MOS capacitors with 5 to 10 nm dielectrics and poly-silicon gate material doped from a POC13 source were prepared. N-channel MOSFETs were fabricated using a four mask lithography process, as reported in detail in Ref. [14]. Unlike the procedure described therein, in this study the lithography was performed optically using a g-line full wafer exposure mask aligner. For p-well implantation and the adjustment of the threshold voltage, a double boron implantation was carried out at 200 keV with 3 • 1013 ions cm- 2 and 60 keV with 1 . 1013 ions cm- 2 . After the standard LOCOS process and a subsequent modified RCA clean without an HF-etch step, the oxide was formed with 7 nm thickness. Immediately following, the poly-Si gate material was deposited. Subsequent to patterning the poly-level, sidewall spacer technology was applied. Source/Drain and poly-Si doping was carried out by means of arsenic implantation at 80 keV and 1 . 1016 ions cm- 2 , followed by a reoxidation step 446
which also ensures the diffusion and activation of implantation areas. Contact hole and AI-metallization levels were fabricated in a standard procedure. STRUCTURAL CHARACTERIZATION
The evaluation of structural properties was performed using a Fourier transform infrared (FTIR) spectrometer (Digilab QS-200) equipped with a 300 angle of incidence and unpolarized light. In this configuration, the excitation of the Berreman mode [15], which is a longitudinal optical (LO) resonance, is possible. It provides information regarding the quality of oxides in addition to information received from transverse optical (TO) modes, particularly from the principle absorption band at - 1070 cm- 1 . Any mention of TO and LO modes in the following refers only to these two modes. The absorption spectra of RTO layers with different thickness values are shown in Fig. 1. These spectra reveal peak positions of 1071 and 1064 cm"1 for the TO mode and full widths of half maximum (FWHM) values of 74 and 83 cm- 1 for 10 and 5.5 nm thickness, respectively. The well resolved LO mode at 1251 cm- 1 is also displayed. These features do not show any deviation from spectra obtained from conventional thermal oxides which are not shown here. As the thickness decreases, there is a slight shift to lower wave numbers in the TO mode, as has also been observed by others [16] for conventional thermal oxidation.
C
-_=
.0 0
Wavenumber
Wavenumber
(cm-)
(cm-')
Fig. 2: IR-absorbance spectra of a deposited (a) and annealed (b) LTO layer of 7 nm thickness
Fig. 1: IR-absorbance spectra of RTO layers with 10 and 5.5 nm thickness 447
For the LTO layer, the spectra are shown in Fig. 2 for an as-deposited film (a) and a postannealed (10000C) film (b). The as-deposited film spectrum 1 1 exhibits a TO mode at 1055 cm- with a FWHM of 86 cm- , and an LO mode 1 at -1225 cm- 1 . After annealing, the TO mode shifts to 1071 cm- and shows a 1 1 FWHM of 83 cm- . The position of the LO mode changes to 1251 cm- . This indicates a rearrangement process and thus a reduction of disorder in the oxide. Recently, more details on this subject have been reported in Ref. [13]. Overall, the features of the annealed LTO layer reveal a striking similarity with those observed on thermally grown oxides. However, the IR spectra appear as a good tool for the evaluation of structural qualities of thin films, but the question remains if a similar behavior is obtainable in the electrical performance of such films. ELECTRICAL CHARACTERIZATION Breakdown Measurements Breakdown measurements have been carded out on MOS capacitors 2 by applying a voltage ramp up to a current density of 2 • 10-4 A/cm . This current density has been accepted as the breakdown limit, as reversible measurements are possible up to this point.
0= ==
L,
U>
S=
E
UJ
Breakdown Field [MV/cm]
Fig. 3: Cumulative failures vs. breakdown field for various oxides of 10 nm thickness: a) LTO with 10000C annealing, b) OX, c) RTO and d) LTO with 9000C annealing
Fig. 4: Cumulative failures vs. breakdown field for various oxides of 5 nm thickness: a) LTO with 10000C annealing, b) OX and c) RTO 448
The cumulative breakdown statistics are displayed in Figs. 3 and 4 for 10 and 5 nm layers, respectively. The RTO and OX layers do not show any differences in their characteristics, and a high field breakdown voltage of 8-9 MV/cm for both thickness values. The LTO layer in Fig. 3 (annealed at 10000C) shows a reduced high field breakdown voltage with a broader distribution. However, for the g000 C annealed LTO layer, considerably poorer breakdown statistics have been obtained, as shown in Fig. 3. An annealing temperature above the viscous flow point is obviously required to reduce the number of low field breakdowns. If the thickness is decreased down to 5 nm, as shown in Fig. 4, the LTO layer also shows a higher field strength as compared to the 10 nm case. This effect is most likely due to the increased possibility of reduced structural defects with a decreased layer thickness. These measurements have been carried out on capacitors without measuring pads, fabricated in a separate process flow. On test capacitors which were made simultaneously with the NMOSFET-process flow, we have observed high breakdown fields of 20 MV/cm and 23.5 MV/cm for the 10 and 7 nm thermal oxide layers. The LTO layer of 7 nm thickness again revealed a slightly reduced breakdown field of 22 MV/cm as compared to the aforementioned thermal oxides. The observed differences in the two types of measurements may be explained by the very different process flow. For example, the applied reoxidation is suspended to reduce edge damage effects from plasma etching. Also, the surface dopant concentration for the two devices differs by a factor of 100. Transfer characteristics The transfer characteristics of NMOSFETs with 2 jam gate length and 10 jim width are shown in Fig. 5 for the three oxide layers with a thickness of 7 nm. In order to obtain information on the intrinsic properties of the oxides, we did not focus on gate lengths under 2 g.Lm, although gate lengths down to 0.8 g±m were also fabricated. This was done to exclude any effects which are related to small device geometries. From these data, the threshold voltages Vt and transconductances gm (VDS = 50 mV) have been estimated and are listed in Table I. Table I: Comparison of threshold voltages Vt and transconductances gm obtained from measured transfer characteristics and device simulation for various dielectrics.
OX RTO LTO
Measurement Vt / mV gimrus 470+/- 5 45+/-3 450 +/- 20 46 +/-3 630 +/- 25 41 +/-2 449
Simulation (7.5 nm) Vt / mV gmI/S 440 42 500 37 650 29
W< S: M0
V gate [V]
Fig. 5: Drain current vs. gate voltage for OX (dotted line), RTO (dashed line) and LTO (solid line)
Conc. [El7cm-3]
Fig. 6: Calculated threshold voltage Vt vs. surface dopant concentration for thickness values of the gate dielectric of 5 to 10 nm
The measured values for Vt and gm are in good agreement for the thermal oxide (OX and RTO) gate dielectrica. Deviations from these values have been measured in the case of LTO-dielectrics. The question remains if this effect can be explained by the appearance of various oxide charges, interface trap densities or dopant concentrations. By C-V measurements and subsequent profiling, we obtained the oxide thickness and different dopant concentration profiles. The actual dopant concentration near the surface was extracted from the flatband evaluation [17]. For the thermal oxides, the concentration was determined to be 2 - 1017 cm-3 and 1.7 • 1017 cm-3 for the RTO and OX layers, respectively. For the LTO layer, the concentration was 3 • 1017 cm-3 . This high value may be explained by the additional temperature step at 1 000°C which was applied for LTO densification. Device simulation by MINIMOS was carried out for various dopant concentrations and oxide thickness values. Source/Drain concentrations were simulated with ICECREM. An example is shown in Fig. 6 for the threshold voltages Vt vs. substrate surface concentrations, whereby the set of curves is drawn for various oxide thickness values. A comparison of Vt, extracted for d = 7.5 nm and the above-mentioned concentrations, shows good agreement 450
with the measured values. The values for the simulated transconductance gm are smaller for the LTO layer than for the thermal layers. This tends to agree satisfactorily with the measured values. The difference in the gm values is explained by the different dopant concentrations at the surface. From these results can be concluded that shifts in Vt and gm are not primarily caused by aditional process induced oxide or surface trapped charges. However, an important technological problem appears. As can be seen in Fig. 6, a variation of 1 nm in the thickness of the oxide results in a threshold voltage deviation of -100 mV. If for any reason the absolute value of the oxide thickness differs from a given value, the impact on the threshold value is very great. Also, poor thickness uniformity across the wafer causes a deterioration in the statistical deviations of the threshold voltages. In Tab. I, we also observed larger variances in Vt in the cases of RTO and LTO layers as compared to the variance for an OX layer. This corresponds to the results obtained in ellipsometric thickness measurements with a fixed refractive index. We received variances of a = 0.3 nm for LTO and RTO layers, and a = 0.02 nm for the OX layer. Charge pumping measurements The results of charge pumping measurements on NMOSFETs with 2 gIm gate lengths are displayed in Fig. 7. The bandwidth for the variation of the pumping currents is indicated by the dotted lines for OX layers, dashed lines for RTO layer and solid lines for LTO layer. A threshold voltage shift of -150 mV is also observable therein for the LTO layer. The currents are in the same
uJ 4' (1
0. 0
Fig. 7: Statistical variation in the charge pumping currents Ic vs. offset voltage for OX, RTO and LTO dielectrics, as shown by doffed, dashed •n,4
V offset [V]
a nirt
respectively 451
Iin.
order of magnitude and the number of interface state traps has been estimated as Dit = 3 to 4 x 1010 eV cm- 2 . Within the statistical variations of the pumping currents it can be concluded that there is only a negligible difference in the number of interface states for the three dielectrica. These devices have been stressed to observe any different degradation effects. For this purpose, a voltage of 4.5 V was applied between gate and substrate, and a voltage of 1.8 V between source and drain. Subsequent charge pumping measurements showed an increase by a factor of 2 in the pumping current. But once again, no significant difference for the three oxide layers was observed. CONCLUSION The interface trapped charge densities as well as the number of fixed oxide charges show no significant deviations for the three oxide dielectrics. Therefore, bulk and interface structural properties are very similar at a microscopic level, and all three oxides are suitable for device application. In a macroscopic view, however, LTO seems to be less appropriate because the defect density is enhanced compared to thermally grown oxides. This is shown by the results of the breakdown measurements. Also in this context, thickness uniformities are worse for RTO and LTO than for OX layers, which causes variations in threshold voltages in FETs. For future application, attention has to be focussed mainly on the availability of excellent thickness uniformities and low defect densities. This is of increasing importance for application in 8 inch wafer technology. The essential properties which determine the device characteristics are the dopant concentration profiles in the surface region and the thickness, as well as the uniformity of the dielectric layer. For submicron application, device design and process flow have a much greater effect on the device performance than the intrinsic properties of the oxides. ACKNOWLEDGEMENT The authors would like to express their gratitude to F. Naumann who performed additional C-V and breakdown measurements. REFERENCES [1] S.-W. Lee, T.-Y. Chan, and A.T. Wu IEEE Electron Device Letters, 11, 294 (1990) (2] T. Hori, and H. Iwasaki IEDM Tech. Dig. p. 459 (1989) [3] V.J. Kapoor, R. S. Bailey, and R.A. Turi J. Electrochem. Soc., 137, 3589 (1990) 452
[4] G. Q. Lo, W. Ting, D.- L. Kwong, J. Kuehne, and C. W. Magee IEEE Electron Device Letters, 11, 511(1990) [5] K. P. MacWilliams, L. F. Halle, and T. C. Zietlow IEEE Electron Device Letters, 11,3 (1990) [6] Y. Okazaki, T. Kobayashi, M. Miyake, T. Matsuda, K. Sakuma, Y. Kawai, M. Takahashi, and K. Kanisawa IEEE Electron Device Letters, 11, 134 (1990)
[7] S. P. Tay, A. Kalnitsky, G. Kelly, J. P. Ellul, P. DeLalio, and E. A. Irene J. Electrochem. Soc., 137, 3579 (1990) [8] C. C. - H. Hsu, D. S. Wen, M. R. Wordeman, Y. Taar, and T. H. Ning IEDM Tech. Dig., p. 75 (1989) [9] H. Fukuda, A. Uchiyama, T. Hayashi, T. Iwabuchi, and S. Ohno Jap. J. Apple. Phys., 29, L 137 (1990) [10] S. T. Ang and J. J. Wortman J. Electrochem. Soc., 133, 2361 (1986) [11] L.K.Wang, D. S. Wen, A. A. Bright, T. N. Nguyen, and W. Chang IEDM Tech. Dig., p. 463 (1989) [12] G. Lucovsky, S. S. Kim, and J. T. Fitch J. Vac. Sci. Technol., B8, 822 (1990) [13] P. Lange, U. Schnakenberg, S. Ullerich, and H.-J. Schliwinski J. Appl. Phys., 68, 3532 (1990) [14] D. Fredrich, H. Bemt, H. L. Huber, W. Windbracke and G. Zwicker SPIE Vol. 1089, 202 (1989) [15] D. W. Berreman Phys. Rev., 130, 2193 (1963) [16] J. T. Fitch, C. H. Bjorkman, G. Lucovsky, F. H. Pollak, and X. Yin Apple. Surf. Sci., 39, 103 (1989) [17] B. Ricco, P. Olivo, T. N. Nguyen, T.-S. Kuan, and G. Ferriani IEEE Trans. Electron. Dev., 35, 432 (1988)
453
CORRELATION OF METAL IMPURITY CONTENT OF ULSI CHEMICALS AND DEFECT - RELATED BREAKDOWN OF GATE OXIDES M. Meuris, M. Heyns, W. Kiiper, S. Verhaverbeke IMEC vzw, Kapeldreef 75, B-3001 Heverlee, Belgium and A. Philipossian Digital Equipment Corporation, 77 Reed road, Hudson, MA 01749, USA In this study the performance of ULSI chemicals from different suppliers was investigated in a RCA-type cleaning. After an ammonia/peroxide clean, the metal impurity density on the silicon surface is proportional to the metal impurity content in the peroxide. After a hydrochloric/peroxide clean no such correlation exist and an equal amount of trace metal densities on the silicon surface is found for all different vendors. Breakdown statistics do not completely correlate with the metal impurity content of the chemicals, but it is observed that haze shows a much better correlation with the breakdown statistics.
INTRODUCTION In MOS technology metal contamination seriously degrades the yield by causing defect - related oxide breakdown. In this study an investigation is made between trace metals in chemicals, the metal concentration on silicon wafers treated in these chemicals and the gate oxide properties. ULSI grade chemicals of different suppliers were tested in a RCA-type cleaning sequence. The chemicals used in this study were H2 0 2, HC1, and NH 1 OH. In a previous study M. Heyns et al. [1] correlated roughness parameters to breakdown statistics. This effect is also included in our study.
EXPERIMENTAL The wafers in these tests were <100> silicon wafers n-type doped (resistivity between 1 and 10 Qcm) and 125mm in diameter, used for standard processing of devices. Initially, these wafers were labeled and put into conventional teflon carrier boxes. Just before the RCA-type clean the wafers underwent a 10 minute H 2SO,/H2O2 (5/1) clean at 90°C to remove organic contamination, followed by a DI-water rinse. Then a 20 second dip is performed in 2% aeqeous HF also followed by DI-water rinse. After the sulfuric acid/peroxide cleaning the wafers show a metal
454
contamination below 1011 at.cm- 2 for each metal under investigation. This drops to below 10'0 at.cm- 2 after the HF-dip. After this initial clean, the RCA-type cleaning was performed with ULSI chemicals from 4 different vendors. It has to be noted that because HCI from vendor C
was missing, we used HC1 from vendor B as a substitute. The RCA-type cleaning recipe was optimised in a seperate set of investigations [21. This cleaning was performed in quartz containers and consists of a 10 minute clean in a NH 1OH/H 2 0 2/H 2 O (0.25/1/5) mixture at 75 to 78°C, immediately followed by a'DI-water rinse, followed by a 10 minute clean in a HCII/H2 0 2 /H 2 0 (1/1/5) mixture at 75 to 78°C and again a DI-water rinse. In all cases the peroxide was mixed 2 to 3 minutes before reaching the final temperature of the cleaning solution, to prevent decomposition of the peroxide during the warming-up period. Wafers were dried by putting them vertically on the wet bench under the laminar flow for ten minutes. It was controlled that this drying procedure does not add any substantial contamination regarding particles or metals, compared with a conventional spin-dry procedure. However this drying procedure was more convenient and reproducible. The experiment consisted of 3 seperate runs. In each run the chemicals from the 4 different vendors were tested sequentially. The testing order of the different chemicals was changed in every run. After each NH 4OH/H 20 2 /H 2 0 clean 1 wafer was taken out of the carrier and the metal concentration on this silicon wafer was measured. After each RCA-type clean, 2 wafers were measured on metal contamination and 4 wafers were used to make capacitor structures. So after each run 16 wafers were loaded together in 1 furnace for making a 15 nm gate oxide. This oxide was grown in dry 02 ambient (no addition of chlorine) at a temperature of 900'C in a double walled furnace tube. Phosphorous doped polysilicon was put on top and capacitor structures etched in the polysilicon layer. Aluminum was sputtered and alloyed at the backside of the wafers. On these structures breakdown statistics were measured of capacitors with an area of 1.2 10-2 cm 2 and 3.85 10-1 cm 2 respectively.
Particle densities (for particles of 0.1 /im and 0.5 am in diameter) and haze (average total in ppm, standard definition of the equipment) were measured after the cleaning sequence with a Tencor Surfscan 4500. The particle densities of 0.5 gm in diameter varied for all tests from 0.2 to 1.5 particles/cm2 . This density is believed to have a negligible effect on our experiments. Trace metal content in chemicals The concentration of trace metals in the chemicals was measured with Total reflection X-Ray Fluorescence (TXRF) using a technique as described in ref. [3]. This method allows a relatively fast (approximately 20 minutes) determination of the metal impurity content of the chemical for a large number of metals. A 100 il droplet of each chemical was pipeted and dried on a clean Si substrate. When using
455
Table I: Metal impurity analysis in ppb of H20 2 for different vendors. - means below the detection limit of 0.1 ppb. Element
supplier A
supplier B
supplier C
supplier D
6.6
1.2
S K
1.7 7.4
-
-
-
Ca
4.0
1.4
5.0
22.0
Ti
2.4
-
0.5
-
Cr
3.2
0.6
3.0
0.6
Mn
0.2
-
0.6
0.1
Fe
0.2
3.0
7.3
2.7
Co
0.3
-
0.3
-
Ni Cu Zn
1.3 0.2 1.2
0.3 0.2 2.0
1.7 0.3 3.1
0.5
Ta
-
-
-
3.0
-
2.5
Table I1: Metal impurity analysis in ppb of NH40H for different vendors. - means below the detection limit of 0.3 ppb. Element Ca
supplier A 4.5
supplier B -
supplierC pir
supplierD upir
Fe
-
Cu Zn
1.2 0.5
0.3 0.2 0.5
0.4 0.5 0.4
0.4 0.2 0.4
a Si substrate only elements from Sulfur to Krypton and from Silver to Bismuth can be measured. The detection limit varies from 1 ppb (in weigth) for Sulfur to 0.1 ppb (in weight) for Zinc under the measurement conditions used. The DI water used in our test was contamination free down to the detection limit of 0.1 ppb. The reproducibility of these measurements was better then 10 %, except for Cl, which is a volatile species and can evaporate easily from the solution and for Zn, where the reproducibility was only a factor of 2. The detection limit for NH OH is about 0.3 ppb in our experimental conditions. One vendor delivered an analysis certificate of the supplied chemicals measured with Inductively Coupled Plasma Mass Spectrometry and Atomic Absorption Spectrometry. The difference with our analysis was less than 10 % for the elements which were listed above the detection limit of the vendor (typically 1 ppb). In Table 1, II and III the analysis of respectively H2 0 2 , NH.lOH and HC1 for the different vendors is shown. The metals, which are not present in detectable quantities in any of the 4 different chemicals, are not tabulated.
456
Table III- Metal impurity analysis in ppb of HC1 for different vendors. - means below the detection limit of 0.1 ppb. Element S K Ca Ti Cr Mn Fe Ni Cu Zn
supplier A 0.6 0.4 30.0 0.8 0.3 0.2 6.5 0.1 0.1 8.0
supplier B 2.3 0.2 22.5 1.6 2.0 0.3 19.9 1.6 0.5 2.2
supplier D 1.6 10.0 0.4 0.6 98.0 0.7 0.3 3.5
Metal concentration on silicon wafers The amount of metal concentration on the silicon surface was measured with Vapour Phase Decomposition (VPD)-TXRF [4]. In this technique a HF vapour is used to dissolve the native oxide. Afterwards a 50 1l droplet of a collection solution is used to collect the metals present on the Si surface. The droplet is dried and the TXRF signal measured. The detection limit with this technique is dependent on the wafer size and the collection efficiency. When using a water droplet the collection efficiency for Fe, Co, Ni and Zn is 50 to 60 %. For Cu the collection is only a few percent effective. An improvement of the collection efficiency is observed, when a mixture of 0.5%HF/1%H 2 0 2 /98.5%H 2 0 is used, as reported in [5]. We determined the collection efficiency on 5 different wafers, homogeneously contaminated at the level of 1011 to 1012 at.cm- 2 using a spin technique. In Table IV the collection efficiency of 5 important trace metals is tabulated. From Table IV it can be concluded that the reproducibility of this technique is quite good (around 10%) except for Cu, which is still difficult to collect. However, even in this case a detection limit of about 3 10' at.cm- 2 can be attained, with an accuracy of a factor 2 to 3. The background originating from the 50 pl droplet was 8 I0' for Ca, 2 10' for Fe and Zn and below the detection limit of 1 109 at.cm-2 for the other metals. Breakdown of gate oxides Wafers with polysilicon capacitor structures on 15 nm gate oxides were stressed up to 15 MV.cm-' in steps of 0.5 MV.cm- . From the breakdown statistical data, Weibull plots were generated to distinguish between defect-related and intrinsic breakdown events [6, 7]. The total number of intrinsic breakdowns (typically capacitors surviving a field of 12 MV.cm-1) were counted as "good" capacitors and
457
le-O le-0O le-O Sle-O 4J
C le-0 ý4 ý3 le-O
le-0 le-O le-0
0
3
6
9
12
15
18
Field [MV/cm]
Figure 1: I-V curve (solid line) of a good capacitor. Curve (a) represents the leakage current, curve (b) the tunneling current through the 15 mu gate oxide and curve (c) the spreading resistance of the silicon substrate.
458
Table IV: Collection efficiency of 5 different metals with VPD-TXRF. wafer Fe Co Ni Cu Zn 1 80% 80% 76% 9% 78% 2 77% 76% 72% 28% 74%
3
83%
84%
80%
15%
82%
4 5
84% 84%
83% 82%
80% 77%
111% 16%
81% 75%
this number, divided by the total number of measured capacitors, result in the yield percentage of gate-oxides after cleaning with chemicals from different vendors. Note that to obtain statistical significant results a capacitor area with a yield percentage around 50 % was chosen. In this way a clear difference between the vendors can be detected. Remark that in these measurements, the exact value of the intrinsic breakdown field is not well defined. Due to the high spreading resistance of the substrate the intrinsic breakdown field can be defined arbitrarily between 13 and 18 MV.cm-'. This is illustrated in Fig. 1. In this figure a typical I-V curve of a good capacitor is plotted for a 15 nm gate oxide. At low fields [curve (a)] the leakage current through the oxide is measured. At fields above 7 MV.cm-1 a tunneling current through the 15 nm oxide starts to flow [curve (b)]. This is observed by the large increase of the current. At fields typically larger than 12 MV.cm-' the spreading resistance of our substrate is dominating the I-V curve [curve (c)] and any further increase in the stressing voltage results in a large increase of the voltage drop over the substrate and only a minor increase of the oxide field. Therefore, in this investigations, capacitors surviving the field of 12 MV.cm-' are arbitrarily defined as "intrinsic".
RESULTS AND DISCUSSION As a starting point VPD-TXRF measurements were performed from the silicon wafers, coming out of the storage box, before any cleaning. It was observed that for the metals under investigation only Ca, Fe, Ni, Cu and Zn were present in detectable quantities. Sometimes (but irreproducible) Cr and Mn was measured up to levels of 5 10" at.cm-2. Because of the low concentration of these metals (both before and after cleaning) they will not be discussed further in this paper. The Cu concentration before cleaning was about 4 to 8 10' at.cm- . This Cu concentration did not significantly change during any step of the cleaning treatment. It has to be concluded that none of the cleaning solutions has a strong effect on Cu contamination and no removal of Cu with the conventional RCA cleaning procedure can be obtained. For the chemicals tested in this experiments also no addition was observed. In Table V the detected contamination on 5 different wafers immediately taken out of the storage box is summarized. The overall reproducibility of Ca, Ni
459
I
2UU 200
T >, 4.
S150
-H4
o0 4J
100
a0 4J
50 a• 50 U..
0
5
10 Ca conc.
15
20
25
[ppb]
Fe conc.
[ppb]
500
E5
Ann 4)
-H
U) r 4)
-a 0
V
0
0
4.)
0
z
0
Ni conc.
[ppb]
1
2
Zn conc.
3
[ppb]
Figure 2: Atom density on the silicon surface in 10i at.Cm-2 versus metal content in the H 2 0 2 in ppb for Ca, Fe, Ni and Zn (solid lines to guide the eye). (0) data points after NH 1 OH/H 2 0 2 mixture, (0) data points after HCL/H 2 0 2 mixture.
460
Table V: Atom concentration densities in 10 of the storage box
9
2
at.cm- for Si wafers immediately taken out
wafer
Ca
Fe
1 2 3
225 200 370
12 22 23
4 5
225 310
88 27
Ni
Zn 40 31 44
7 5
55 37
and Zn is typical for all VPD-TXRF measurements (about a factor of 2, especially once beneath the low 10'" at.cm-2 range). A large spread in the Fe contamination was observed (from 12 to 88 10' at.cm-2), due to differences in starting material. With VPD-TXRF also the metal concentration after NH,1OH/H 20 2 /H 2 0 (3 wafers for each vendor) and HC1/H 2 0 2 /H 2 0 (6 wafers for each vendor) cleaning was measured. Above 10" at.cm-2 the reproducibility of the experiment was about 20%. Under this limit the reproducibility degrades and is typically a factor of 2 to 3 at the 10i at.cm-2 level. In Fig. 2 the metal concentration of resp. Ca, Fe, Ni and Zn in the chemical oxide (in 10' at.cm-2 ) is plotted as a function of the metal content in the peroxide. For the ammonia/peroxide mixtures a remarkable correlation between metal content of the peroxide and metal contamination of the chemical oxide is observed. This correlation is almost linear and tends to go through the origin. Such a correlation was not observed for the metal content in NHOH or HCI. Ta was only detected on wafers cleaned with chemicals from vendor D (2 109 cm-2) and can be correlated with the 3 ppb Ta content of the peroxide D. Together with the observation of the cleanliness of the NHRjOH (see Table 11), the conclusion that metal deposition in NH4OH/H 20 2 mixtures is coming from the peroxide, is very plausible. Further it can be observed that the metal deposition problem is the largest for Fe. For 1 ppb metal content in the chemical, the deposition will be 300 10' for Fe, 100 10' for Zn, and 15 10' at.cm-2 for Ca and Ni. For Cr the deposition rate is even lower, because 2 peroxides contain up to 3 ppb of Cr, but no Cr is detected conclusively above the detection limit of 1 10' atc M-2. Therefore Fe and Zn have to be considered as the most critical contaminants in H2 0 2 . All these observations are consistent with the model suggested in [8] of precipitation of metalhydroxides on the chemical oxide. After the HC1/H 20 2/H 2 0 cleaning the result is completely different. In this case no correlation between metal content of the chemical bath and the concentration on the silicon wafer is found. Remembering table III, even a 100 ppb Fe content of the HCl of vendor D, results in only 50 109 at.cm-2 Fe concentration on the Si wafer. The Fe content in HC1/H 20 2 /11 2 0 baths in our experiment is varying from 1 ppb
461
W0 V
Haze
[ppm]
0.09 pjm < No.
of part.
< 0.2 pm
densities cm -2 Figure 3: Yield of capacitor structures as a function of haze and particle (0.1 Am in diameter) for different chemical suppliers. (0) 1.2 10-2 cm 2 capacitor area, (0) 3.85 10-2 cm 2 capacitor area. to 15 ppb and only a change of 20 to 50 10' Fe at.cm- 2 on the silicon surface is observed. The breakdown statistics were measured for the 3 different runs on 4 wafers each. 100 So, in total 12 wafers were measured for each chemical supplier. On each wafer 2 capacitors were measured. On 6 wafers the capacitor area was 1.2 10-2 cm large. 2 On the other 6 wafers it was 3.85 10-2 cm , resulting in breakdown statistics on 600 capacitors for each area. The yield (as defined in the previous section) varied dramatically over the different chemical suppliers (from 74 ± 8 % to 29 ± 24 % for the small capacitors and from 45 ± 4 % to 7 ± 9% for the larger capacitors). Such a large difference (about a factor of 3) cannot be easily correlated with the metal concentration on the silicon wafers. Indeed no large difference on the metal concentration after our cleaning procedure could be observed. In Fig. 3 the density of particles (0.1-0.2 Am in diameter) and the haze is plotted as function of the yield for the different chemical suppliers. The haze and small particles are a parameter for roughness on the wafer J9] and taking into account the relationship between the surface roughness and the breakdown statistics of gate oxides [1) it becomes clear that this observation cannot be a hazardous event. Further it is remarkable that with chemicals of supplier A, not only the best breakdown statistics are obtained, but also the smallest standard deviation for the yield is observed.
CONCLUSIONS In this experiment metal content of chemicals and metal contamination on the 462
silicon surfaces was correlated. A linear correlation between metal content of chemical oxides after ammonia/peroxide mixture cleanings and the metal content of the peroxide could be determined. After hydrochloric/peroxide cleaning no correlation between metal content of the chemical and metal concentration on the silicon surface could be detected. The metal contamination on silicon surfaces after a complete RCA-clean did not vary significantly, even when using chemicals from different suppliers and with different metal content. However, the breakdown statistics changes drastically from vendor to vendor. Measurements on haze and "light-scattering defects" of the silicon surfaces after cleaning indicates that this difference in gate oxide integrity between the chemicals from different vendors is correlated with the difference in surface roughening behaviour of these chemicals.
ACKNOWLEDGMENTS Digital Equipment Corporation is greatly acknowledged for financial support.
REFERENCES [1] M. Heyns, C. Hasenack, R. De Keersmaecker and R. Falster, published in Proceedings 1st Int. Symp. Cleaning Technol. Semicond. Dev. Manuf., ECS meeting, Florida, Oct 1989. [2] M. Meuris, M. Heyns, S. Verhaverbeke, L. Stockman, A. Philipossian, presented at the Mat. Res. Symp., Anaheim, CA, 29 April - 3 May 1991. (3] A. Prange, K. Kramer, and U. Reus, submitted to Spectroch. Acta. [41 P. Eichinger, Proceedings Syrmp. Anal. Techn. Semic. Mat. and Process charact., ECS meeting, Essderc 89 Berlin, Vol 90-11, p. 227. [5] T. Shimono, and M. Tsuji, Proceed. 1st Workshop ULSI Ultra clean Technol., Tokyo 1989, p. 49. [61 D.R. Wolters, in Insulating Films On Semiconductors, Eds. M. Schulz and G. Pensl, (Springer Berlin 1981), p. 180. [7] R. Falster, J. Appl. Phys. 66, 3355 (1989). [8] W. Kiiper, and K. Maex, Proceed. Techn. Conf. on defect control and rel. yield manag., Semicon/Europa 1991, Ziirich, Switserland 1991, p. 1 3 5 . [9] S. Verhaverbeke, M. Meuris, and M. Heyns, Internal Report (IMEC 1990).
463
PROCESS-INDUCED IONIZING RADIATION EFFECTS IN MOS DEVICES T.P.Ma Yale University Center for Microelectronic Materials & Structures, and Department of Electrical Engineering New Haven, CT 06520-2157
Ionizing radiation damage in MOS devices caused by various ULSI wafer processing steps will be reviewed, along with the current understanding of the possible mechanisms. The capabilities and limitations of several annealing techniques will also be discussed.
INTRODUCTION To meet the ever more stringent requirements of dimensional control, increasing use of processing techniques involving highly energetic photons or particles is expected in ULSI wafer fabrication. Some of these processes could cause radiation damage to the devices and circuits being fabricated, resulting in degraded performance and reliability, and/or reduced yield. Depending on the processing sequence and the details of the processing parameters, some of these steps present a more serious problem than the others in terms of the resultant radiation damage. The most commonly observed ionizing radiation effects in a MOS device include: (a) a buildup of positive charge in the oxide; (b) an increase in the interface traps; and (3) an increase in the neutral electron/hole traps in the oxide. These electronic defects are known to cause changes in the MOS transistor parameters, such as a shift in the threshold voltage, a reduction in the transconductance, an increase in the subthreshold swing, and an increase in the source-drain leakage current; they could also cause significant degradation of the device stability and its operating lifetime. Mechanisms of Ionizing Radiation Effects Qualitatively, the ionizing radiation effects arise from the energy transfer of the incident radiation to the Si-O network, causing bond breakage, bond deformation, creation of defects, and generation of electrons and holes. The resulting deformed or broken bonds and the trapping of charge manifest themselves in the change of the electronic properties described above. A detailed description of the ionizing radiation effects can be found in a recently published book [1]. A very brief summary is given below. Figure 1 illustrates the possible 464
processes by which the electronic defects (represented by the three shaded boxes) are generated. Due to the incident radiation, electrons and holes are created in the oxide, or injected into the oxide by internal photoemission from the contacts. These carriers will either recombine or transport through the oxide, and some of them will be trapped, causing oxide charge. Since holes in the oxide have a much lower mobility and a much higher trapping probability than electrons, the radiation-induced oxide charge usually caries a positive sign. Along with the electron-hole generation process, chemical bonds in the oxide may be broken. Some of these bonds may reform when the electrons and holes recombine, while others may remain broken and give rise to bonding defects. These defects may then act as oxide traps or interface traps. Some of the defects generated in the strained region near the SiO 2 /Si interface may migrate toward the interface under the influence of the strain gradient and form interface traps. Chemical impurities, such as H or OH groups, may be released from their original bonding sites and become mobile in the oxide. These impurities may also migrate to the Si0 2 /Si interface, where they undergo reactions to form interface traps.
Fig.1. Mechanisms of ionizing radiation effects in MOS structures. The various processes
and their inter-relationships are shown in the block diagram, and discussed in the text.
465
PROCESS-INDUCED IONIZING RADIATION EFFECTS This section briefly describes the ionizing radiation effects caused by a number of wafer processing steps. E-beam and X-ray Lithography E-beam or X-ray lithography offers the advantage of higher resolution than the conventional optical lithography. In both the focused electron beam and the X-ray exposure systems, the silicon wafer will have received an accumulated radiation dose of well over 1 Mrad(Si) after each exposure. The generation of oxide charge, interface traps, and oxide traps in MOS devices by energetic electrons and X-rays is well recognized [2]. While most of the radiation-induced positive charge could be annealed out at 400 0C in forming gas, it has beeh found that the neutral traps are not completely removed even after annealing at 500 OC [3-5]. From the photo I-V measurements, it was suggested that the radiation-induced neutral traps are uniformally distributed spatially [5], as long as the incident radiation is absorbed uniformly through the oxide. The significance of the radiation-induced neutral traps and their impacts on the VLSI technology have been summarized [41, and the design constraints for the operating parameters in order to limit the hot electron injection in VLSI devices have been discussed [6]. Effects of repeated E-beam radiation-thermal annealing cycles on the long-term stability of MOS devices have also been reported [7]. In principle, it is possible to place a blocking layer over the gate oxide during X-ray or E-beam lithography to prevent the penetration of the incident radiation into the oxide. In practice, however, there are difficulties in its implementation [8] due to the secondary X-rays generated by the bombardment of the electron beam, which penetrate deeper than the electrons. The radiation effects resulting from the secondary X-rays generated by the bombarding electron beam were also reported by others [9]. RIE and Other Plasma Processes Plasma processes, including plasma etching, resist removal, RIE (reactive ion etching), and plasma-enhanced chemical vapor deposition (PECVD), are gaining increasing importance in processing high density circuits. Since a typical processing plasma contains various energetic species, it is expected that some radiation effects will occur. In a gaseous discharge, free electrons gain energy from an imposed electric field and lose this energy through collisions with gas molecules and solid objects, leading to the formation of a variety of new active species, including metastables, atoms, free radicals, ions, and photons.
466
Since the discharge initiates from the free electrons in the system, and because of their small mass, the electrons have the highest peak kinetic energy among all the energetic species. For a RF plasma the highest electron energy (in eV) would correspond to the applied RF voltage. The high energy end of the photons, i.e., the soft X-rays and VUV, are generated by the electrons impinging upon a solid object (e.g. the electrode plates, the chamber walls, or the sample). UV photons are also emitted by de-excitation of gas molecules in the plasma. Therefore, the peak photon energy should track that of the electron energy. The ions, being charged particles, can gain kinetic energy in the presence of an electric field. Because of their much higher masses compared to electrons, the kinetic energies of the ions are generally much lower than the peak energy of the electrons. The molecules and other neutral species do not gain kinetic energy from the electric field, and therefore have the lowest energies in comparison. In discussing the ionizing radiation effects in Si0 2 , we must examine the penetration depths of the various energetic species in the plasma. Because of their high energies and negligible momenta, the X-ray photons have the highest penetration depth among all the energetic species in the plasma. Based on the absorption coefficients in Al, Si, and Si0 2 as a function of photon energy [101, a penetration depth of approximately 0.5 pm in these materials is expected for a photon energy of 500 eV. The electrons, in contrast, have a much shallower penetration [11], because of the momentum conservation requirement. The ions and neutrals, having even larger masses and smaller kinetic energy, would have the least penetration depths. In a typical processing plasma, the penetration depths for various ions are less than 10 nm. If the oxide is covered with a gate electrode, then only X-rays in a typical processing plasma will be able to penetrate into the oxide and create radiation damage. It is, therefore, not surprising that the resulting radiation effects should be similar to those observed after X-ray lithography discussed in the previous subsection: generation of oxide charge, interface traps, and neutral oxide traps. All of these electronic defects have been observed experimentally [12,13]. The only significant difference is in the spatial distribution of the neutral traps along the thickness direction of the oxide, due to the more limited penetration depth of the soft x-rays generated in the plasma environment [13]. Again, the radiation induced neutral traps are more difficult to anneal out than the oxide charge and the interface traps [12]. While the ions in the processing plasma may not cause significant ionizing radiation effects to the gate oxide due to their limited penetration depths, they may nonetheless cause a potentially more troublesome reliability problem; i.e., the release of mobile ionic charge in Si0 2 . This phenomenon could occur when the surface of the Si0 2 is directly exposed to the processing plasma [14]. A model involving ion-insulator interactions has been proposed to explain the results [15]. The mobile ionic species, once they are introduced into the Si0 2 , are extremely difficult to remove, and therefore precaution must be taken to prevent their occurence. It should be noted that, according to the model proposed in [15], the necessary conditions for this effect to happen are: (1) the oxide sur467
face must be directly exposed to the plasma; (2) the oxide surface must initially contain immobile impurities, such as Na bonded to the SiO 2 network; and (3) the incoming ions must possess sufficient ionization potential so that electronic transitions from the SiO 2 surface can take place to neutralize the ions. Therefore, it should be possible to avoid this effect by designing a plasma process that does not satisfy one or more of the above listed conditions. Although their kinetic energies are relatively low, the ions in a processing plasma are capable of causing displacement damage to the exposed wafer surface [13,16,17]. However, since this paper is intended to focus on issues related to ionizing radiation effects, we will not address other forms of plasma damage here. Another reliability problem associated with plasma processes is the dielectric breakdown phenomenon [18,191, which has been attributed to the excessive charging of the gate. Again, since this is not due to ionizing radiation effects, it will not be covered beyond this paragraph. Sputtering and E-Gun Deposition The radiation damage due to sputter etching and deposition has been studied in detail [14]. In many ways, the sputtering environment is similar to that of RIE and some other plasma processes, with the exception that an inert gas (typically Ar) is used for sputtering. Therefore, its ionizing radiation effects are expected to be qualitatively similar to those from other plasma processes discussed in the previous section. In E-Gun deposition, an electron beam of energy range 10-50 keV is used to bombard the source material, causing heating and evaporation of the material in a vacuum environment. The E-beam bombardment creates X-rays and reflected and secondary electrons, which can cause radiation damage to the substrate on which the materials is being deposited. Again, due to the larger penetration depth of the X-rays compared to the electrons, it is usually the former that produce most of the radiation effects. Generations of oxide charge, interface traps, and oxide traps have all been observed experimentally 120,21]. ANNEALING OF PROCESS-INDUCED RADIATION EFFECTS It is generally accepted [1] that the radiation-induced oxide charge, interface traps, and oxide traps are associated with the microscopic structural and bonding defects in Si02 or at the Si0 2 /Si interface. To remove the radiation damage requires some mechanisms by which bond reformation or some other chemical reactions can take place to make the defect sites electronically inactive. In general, some sort of energy is a necessary input to promote such annealing mechanisms.
468
Thermal Annealing The most widely used technique is thermal annealing, in which thermal energy serves to initiate and sustain the various annealing mechanisms. The fact that the radiation-induced positive charge and interface traps in Al-gate MOS devices could be largely annealed out at 400 °C or below was recognized long ago [22]. Since then, a good amount of more detailed work has been done to investigate the annealing process, and data on the time dependence and temperature dependence of the annealing behavior have appeared in numerous publications [23-25]. The important role of hydrogen in the defect annealing process in Si0 2 is now widely recognized [26-31]. During thermal annealing, hydrogen species could undergo chemical reactions to form chemical bonds with certain defects, and make them electrically inactive. Therefore, one would expect the annealing mechanism to be very different with or without the participation of hydrogen. Since the hydrogen species could come from within the Si0 2 itself, or from inward diffusion from external sources, it is very difficult to separate out the two annealing mechanisms. The problem is compounded if the annealing ambient and the hydrogen content in the oxide are not strictly controlled. This is part of the reason why the results reported vary widely from one laboratory to another. Compared to the radiation-induced oxide charge and interface traps, the radiationinduced neutral traps in the oxide are much more difficult to anneal out [3,4,12], and remain a major concern. In recent years, many applications of rapid thermal processes have been demonstrated, but little work has been reported on the annealing of process-induced radiation damage. Because of its relatively low thermal budget, rapid thermal annealing may prove to be a powerful technique for this application. Hydrogen-Assisted Thermal Annealing The role of hydrogen in oxidation, annealing, and defect generation in thermal SiO 2 has been extensively discussed [26,27-29]. It is generally believed that hydrogen enhances the annealing efficiency by passivating the electronically active bonding defects. In the case that hydrogen must be introduced in the annealing ambient, forming gas (a few percent H2 mixed in an inert gas) is most widely used, although pure hydrogen is also occasionally used. To be effective, the active hydrogen species must be diffused into Si0 2 to react with the defects. Therefore, the thermal energy in the hydrogen-assisted annealing process serves three purposes: (1) it promotes the generation of active hydrogen species, most likely atomic hydrogen ; (2) it enhances the diffusion of same; and (3) it drives the defect reaction processes. Depending on the structure of the device being annealed and the annealing parameters, one or the other of the three may be the limiting factor in the overall annealing process. If the oxide is covered with aluminum, as in the Al-gate technology, it has been found that the annealing is equally effective whether or not the ambient contains hydrogen 469
[27,31]. It is believed that, during thermal annealing, the aluminum reacts with minute amounts of H2 0 on the oxide surface to release the active hydrogen species, which then diffuse into SiO 2 and annihilate the bonding defects [27]. In contrast, for polysilicon gate devices, the annealing process goes faster in forming gas than in an inert atmosphere [31], but is generally less effective than that for Al-gate devices even with forming gas [4,33], due to the fact that it is difficult for hydrogen to diffuse through the polysilicon gate at the annealing temperatures (• 500 oC). There has been evidence that, if the polysilicon gate is covered with a layer of aluminum, the defect annihilation rate is enhanced [4], presumably due to the production of active hydrogen species at the AI-polysilicon interface in a way similar to that at the Al-SiO2 interface. These hydrogen species then diffuse into SiO 2 through grain boundaries of the polysilicon. That the lack of active hydrogen species could hinder the defect annealing process in SiO 2 is also evidenced in experiments involving MNOS (Metal/Nitride/Oxide/Si) structures. It was found that, compared to the MOS structure, it is much more difficult to anneal out the oxide charge and interface traps in a MNOS structure [29], presumably due to the blocking of hydrogen by the nitride layer. Strong evidence suggesting that atomic hydrogen may be the active species involved in the defect annealing process has been presented [30]. Detailed studies of the annealing kinetics in Al-gate MOS capacitors [33] also brought out the importance of atomic hydrogen in the annealing of interface traps. Recognizing the importance of hydrogen in the thermal annealing process, attempts have been made to more effectively introduce the active hydrogen species into the oxide. One way is the use of atomic hydrogen generated in a plasma environment [30]. Another method is to perform the thermal annealing in a high pressure environment containing hydrogen [34]. Using a specially designed high-pressure system, the authors found that radiation-induced charged and neutral centers in Si-gate devices could be effectively removed by annealing in 50 atm of forming gas at 400 °C for 30 minutes for radiation doses as high as 5 x 10' rads (Si0 2 ). In contrast, temperatures as high as 600 °C are required to achieve similar results if the thermal annealing was done in 1 atm pressure. In addition to the thermal annealing and its variations, a very different annealing technique, called RF plasr6a annealing, has demonstrated its effectiveness [10,35-38], which is briefly described below. RF Plasma Annealing The RF annealing apparatus and the experimental details can be found in a number of publications [10,35,38]. Basically, the annealing apparatus is similar to a parallel-plate RIE system but with some important differences. The most significant difference is that in the annealing system the sample experiences no dc self-biasing effect. This can be accomplished by having two equal area parallel-plate electrodes with a wide spacing (Ž 8 in) between them, and the sample is positioned in the center between the two electrodes. 470
Other important considerations are that the pressure must be sufficiently low (< 10/pm), the wafer surface must be perpendicular to the RF field, and both sides of the wafer must be exposed to the plasma. Departure from these conditions has been found to result in unsatisfactory results. Complete removal of radiation-induced oxide charge, interface traps, and neutral traps has been demonstrated using this technique at a modest RF power (0.2 to 0.6 W/cm 2 ) [35,38]. It has been shown that, although the wafer temperature does rise during RF plasma annealing, thermal annealing is not the dominating mechanism [10,35,36]. Three essential components for the annealing have been identified [10,35,38], which are (1) plasma interactions with Si0 2 ; (2) RF field; and (3) induced wafer temperature. The primary role of the plasma is to serve as an excitation source for the generation of the electron-hole pairs in the oxide. The RF field controls the motion of these radiationinduced free carriers, and modifies the defect-reaction coordinates such that a more favorable annealing reaction can be achieved. Furthermore, the RF field, along with the plasma-wafer interactions, induces a moderate heating of the wafer, which also contributes to the annealing. The plasma-induced excess carriers could participate in two possible annealing processes. The first process involves the neutralization of the positive oxide charge centers through electron capture. The second process involves the more complicated recombinationenhanced defect reactions (REDR) mechanism [39,40], which could lead to the annihilation of the bonding defects in SiO 2 . Experimentally, it has been demonstrated that the occurence of the REDR mechanism helps to significantly reduce the temperature required for certain defect annealing processes [10]. As pointed out previously, the energetic gas plasma, if it acts alone, is a source of radiation damage. It is only through the proper cooperative interactions of all three essential components that effective annealing is possible. An experimental simulation has been performed in which an X-ray beam was used in place of the RF plasma, and the three essential components for an effective anneal- (1) the X-ray radiation; (2) the RF field; and (3) the induced wafer temperature- could be independently controlled. From a systematic investigation of their individual and combined effects, it was concluded that the cooperative interactions of all three components were necessary to achieve good annealing results. A factor of three reduction in the activation energy accociated with this annealing process was found when compared with the pure thermal annealing process. This is consistent with the recombination-enhanced annealing mechanism. A detailed description of this experiment and its results can be found elsewhere [10,38]. ACKNOWLEDGEMENT The author would like to acknowledge the contributions of his former graduate student, Dr. M.R. Chin, and the support of SRC.
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REFERENCES [1] T.P.Ma and Paul V. Dressendorfer, co-editors, Ionizing Radiation Effects in MOS Devices & Circuits, (John Wiley & Sons), (1989). [2] A. Reisman, et.a] J. Electrochem. Soc. 131, 1404 (1984). [3] J.M. Aitken, D.R. Young, and K. Pan, J. Appl. Phys. 49, 3386 (1978). [4] J.M. Aitken, IEEE J. Solid State Cir. SC-14(2), 294 (1979). [5] W. Schmitz and D.R. Young, J. Appl. Phys. 54(11), 6443 (1983). [6] T.H. Ning, et.al., IEEE Trans. Electron Dev. ED-26(4), 346 (1979). [7] M. Shimaya, et.al, J. Electrochem. Soc. 130, 945 (1983). [8] M. Shimaya, et.al, J. Electrochem. Soc. 131, 1391 (1984). [9] K. Nakamae, et.al, J. Apple. Phys. 52(3), 1306 (1981). [10] T-P. Ma and M.R. Chin, J. Apple. Phys. 51(10), 5458 (1980). [11] T.E. Everhart and P.H. Hoff, J. Appl. Phys. 42, 5837 (1971). [12] D.J. DiMaria, et.al, J. Appl. Phys. 50(6), 4015 (1979). [13] L.M. Ephrath and D.J. DiMaria, Sol. State Technol. p. 182, April 1981. [14] D.V. McCaugham and R.A. Kushner, Proc. of the IEEE 62, 1236 (1974). [15] D.V. McCaugham, et.al, Phys. Rev. Lett. 30, 614 (1973). [16] S.W. Pang, Sol. State Technol. 27, 249 (1984). [17] T.P. Chow, et.al, J. Electrochem. Soc. 131, 156 (1984). [18] T. Watanabe and Y. Yoshida, Sol. St. Technol. p. 263, April (1984). [19] K.H Ryden, et.al, J. Electrochem. Soc., 134, 3113 (1987). [20] T.H. Ning, J. Apple. Phys. 49(7), 4077 (1978). [21] M. Hamasaki, Sol. St. Electron. 26, 299 (1983). [22] K.H. Zaininger and A.G. Holmes-Siedle, RCA Rev. 28, 208 (1967). [23] V. Danchenko, et.al, J. Apple. Phys. 39, 2417 (1968). [24] P.S. Winokur and H.E. Boesch, Jr., IEEE Trans. Nucl. Sci. NS-28, 4088 (1981). [25] D.B. Brown, et.a], IEEE Trans. Nucl. Sci. NS-30, 4059 (1983). [26] A.G. Revesz, J. Electrochem. Soc. 126, 122 (1979). [27] P. Balk, Paper # 111, Electrochem. Soc. Meeting, Oct. 10-14, (1965). [28] P.L. Castro and B.E. Deal, J. Electrochem. Soc. 118, 280 (1971). [29] B.E. Deal, et.al, J. Electrochem. Soc. 116, 997 (1969). [30] N.M. Johnson, et.al, J. Vac. Sci. Technol. 19(3), 390 (1981). [31] M.L. Reed, et.al, Apph Phys. Lett., 47, 400 (1985). [32] T.W. Hickmott, J. Appl. Phys. 48, 723 (1977). [33] M.L. Reed, Ph.D dissertation, Stanford University, (1987). [34] A. Reisman and C.J. Merz, J. Electrochem. Soc. 130, 1384 (1983). [35] T.P. Ma and W.H. Ma, IEEE J. Solid State Circuits SC-13, 445 (1978). [36] T.P. Ma and M.R. Chin, Appl. Phys. Lett. 36, 81 (1980). [37] M.R. Chin and T.P. Ma, Appl. Phys. Lett. 40, 490 (1982). [38] M.R. Chin, Ph.D Dissertation, Yale University, December (1981). [39] L.C. Kimerling, Sol. St. Electron. 21, 1391 (1978). [40] J.D. Weeks, et.al, Phys. Rev. B12(8), 3286 (1975).
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CHARGE SHARING "ANTENNA" EFFECTS FOR GATE OXIDE DAMAGE DURING PLASMA PROCESSING S. Fang, A. M. McCarthy*, and J. P. McVittie Center for Integrated Systems, Stanford University, Stanford, CA 94305 *Lawrence Livermore National Laboratory, L-271, Livermore, CA 94550
In this work, small area capacitors with various sized polysilicon gate antennas and different field-to-gate oxide thickness ratios have been used. The objective is to characterize the role of device structure on thin oxide yield, and the nonuniform charge build-up phenomena during plasma processing. For a given field-to-gate oxide thickness ratio (tf/tg), the yield initially decreases with increasing field-to-gate area ratio (A f/Ag) and then saturates. The yield at saturation increases linearly with decreasing thickness ratio. The low yield region is concentrated at the wafer center and expands with increasing Af/Ag, or tf/tg. A structure dependent field enhancement factor is proposed using a model based on charge sharing between the gate and field capacitors. With surface charge density measurements, this simple model can successfully explain the above results. In addition, the nonuniform charge build-up phenomena is seen in the surface charge density profile and the wafer maps of damaged capacitors. Key words and phrases: charge sharing, antenna, plasma damage, oxide charging, plasma etching, plasma stripping, oxide breakdown
INTRODUCTION Plasma processes use glow discharges to lower process temperature and to obtain directional ion bombardment By their nature, discharges always result in some surface charging and are usually accompanied with some rf current flowing through the wafer. Normally the surface charging is not significant, however under some conditions which are not well understood, charging can be excessive and thin oxide degradation results [1] [2] [3]. Part of the difficulty in understanding this problem is that the observed damage depends on plasma conditions, the device structure, and oxide quality. In this paper, 473
Figure 1: The antenna structure of MOS capacitors: tf ranges from 0.75 pm to 1.7 Pm, t, ranges from 6 nm to 12 nm.
we focus on the role of the device structure [415][6]. In particular, antenna capacitor structures [7] have been used to study thin oxide integrity. These structures consist of small area thin oxide capacitors connected to large area field oxide (or antennas) capacitors as shown in Figure 1. The surface charge that deposits on the polysilicon antennas is measured with an electrically erasable-programmable read-only memory (EEPROM) device [8]. We will show that the experimental breakdown results and the surface charge density are consistent with a capacitor charge sharing model.
EXPERIMENT Antenna Capacitors Polysilicon gate MOS capacitors on 5 ohms-cm <100> n-type Si wafers were used in this study. Figure 1 shows the antenna test structure. The thin gate oxide was grown in dry 0 2 at 85 0 0C. For part of the wafer lot the gate oxide was held at 12 am, and the field oxide thickness (tf) ranged from 0.75 pm to 1.7 pm. For the other wafers the field oxide was held at 1.7 um , and the thin gate oxide thickness (tg) ranged from 6 am to 12 am. Polysilicon was deposited at 650°C and doped with POCI 3 at 900 0C. Polysilicon etching and photoresist stripping were used to achieve the antenna structure. The antenna-to-gate area ratio was varied from 16 to 1000 and 180 to 11,000 for gate oxide areas of 20 x 20 and 6 x 6 pm2 , respectively. To etch the polysilicon, a 474
13.56 MHz parallel plate configuration was used in the plasma mode (wafer on grounded electrode) with a SF6/C2FsCl mixture. The photoresist was subsequently removed in a single wafer 02 plasma stripper in which rf power was capacitively coupled to the plasma at the top of a quartz chamber while the wafer was supported on quartz pins at the bottom. Alternatively, control wafers were fabricated using only a wet chemical process for polysilicon etching and photoresist stripping. To characterize gate oxide damage from plasma processing, ramp voltage breakdown measurements were used. The breakdown voltage was defined as the point at the current exceeding 1I#A. Typically, 200 capacitors were tested for each antenna structure (Af/A•j,tJ/tg) used. Surface Charge Measurements The threshold voltage shift of a special EEPROM device [9] was measured to determine the surface charge density profile on the wafer during the 02 plasma. The EEPROM transistor used in these experiments was an N channel device with two polysilicon gates: a control gate and a floating gate which incorporates a thin dielectric over the source region. The control gate was connected to a large area metal electrode which enhanced the transistor sensitivity to surface charge. To study the plasma-induced wafer charging, initialized EEPROM wafers were exposed to the 02 plasma for three minutes. The resulting threshold voltage shift was measured after the plasma exposure.
RESULTS Role of Device Structure In this section, gate oxide integrity is compared by ramp voltage measurements for antenna capacitors with different structure parameters such as tf, t,, Af , and A,. Note that for plasma processing, both the polysilicon etch and resist strip steps were found to cause damage with the damage mainly arising from stripping. For the results from antenna structures to be reported here, the combined effect of etch and strip was examined. Control wafers prepared without any plasma processing show purely intrinsic breakdown. We use the term intrinsic breakdown for any capacitors with a breakdown field of about 13 MV/cm. The breakdown field below 12 MV/cm is referred to as a defective breakdown. For plasma etching and stripping combined, Fig. 2 shows a typical cumulative failure percentage versus breakdown voltage plot. Both defective and intrinsic breakdown were observed for a gate oxide area 20 x 20 pm 2 with tfl/tg = 142 and Af/A, = 16, 160, 1000. If we define the yield as the percentage of capacitors with intrinsic breakdown from across the entire wafer area , we can plot the yield versus area ratio as shown in Fig. 3 for a gate oxide area of 6 x 6 pm 2 and tf/t9 = 142, 236. For a given 475
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Figure 3: The yield versus area ratio. The yield is the percentage of capacitors with intrinsic breakdown in a ramp voltage test. 476
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Thickness ratio
Figure 4: The yield at saturation versus thickness ratio. thickness ratio, the yield initially decreases with increasing area ratios and then saturates at a value which decreases with increasing thickness ratio. This yield dependence on tf/tg is further shown in Fig. 4 where the saturated yield plotted against tf/tg for a gate oxide area 6 x 6 ym 2 increases linearly with decreasing thickness ratio. Tsunokuni et al. [10] also observed the dependence of plasma induced gate oxide damage on area ratio and gate oxide thickness with antenna capacitors. However, our experiments reveal that the damage to thin oxides depends not only on the oxide area ratio and the gate oxide thickness, but also on the field oxide thickness. The dependence of yield on Af/Ag in Fig. 3 differentiates the charge damage from the radiation damage because the polysilicon electrodes of different sizes (Af) serve as antennas to collect charge. The role of field oxide thickness may be explained as follows: The equivalent circuit of the antenna structure has a field and a gate capacitor in parallel. As the field oxide thickness increases, the field capacitance decreases so that more charge flows to the thin oxide gate resulting in higher fields and more damage.
Phenomena of Nonuniform Charge Build-up To study the nonuniform charging in an 02 plasma, wafer maps were made of antenna capacitors wafers using ramp voltage testing and of EEPROM wafers using surface charge density measurements.
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-4 -3 -2 -1 0 1 2 3 4 5 Distance from wafer center (cm)
Figure 5: A negative charge build-up profile calculated from Vth shift measured using EEPROM for RF-powered stripper with RF power = 500 Watts. For ramp voltage testing, we define the local yield as the percentage of capacitors with intrinsic breakdown, in a ring bounded by r-0.5 cm and r+0.5 cm. For these plasma processing steps, we see that the low local yield region with a yield < 50 % is concentrated at the wafer center and expands with increasing A1 /A, or tf/bt resembling a bill's eye. Furthermore, there exists a critical radius, r,, which defines the edge of this low local yield region. This same bull's-eye pattern is further observed in surface charge measurements using the EEPROM charge monitors as shown in Fig. 5 where negative surface charge density is shown across a wafer diameter. We calculate the amount of charge density deposited on the surface metal pad as Q,=
C
xVg
(1)
where C is the equivalent capacitance of the EEPROM, A is the area of the surface metal pad, and V, is the upper control gate potential which depends on the threshold voltage shift after plasma treatment. Tsunokuni et al. [10] and Kawamoto [11] have seen similar nonuniformity in the 02 plasma with flat band voltage shift of metal-Si3N 4 -SiO 2-Si(MNOS) capacitors. With
EEPROM results and SPICE simulation, Namura [12] relates the charging nonuniformity 478
FA 4
62 1 102
142
tfltg(Af/Ag > 2000) Af/A9 (tf/tg-142)
62
142 11000
102 360
1 2361 236
Table 1: A summary of the field enhancement factor FA and corresponding antenna structure used in this study.
I I I Gate oxide breakdown
0
114 -o
0. -o
FA, r,
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5
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Distance from wafer center: r (cm) Figure 6: The distribution of oxide field EG during plasma treatment due to nonuniform surface charging for different FA values calculated based on eq. (4).
479
to the spatial nonuniformity of plasma potential. However, the origin of nonuniform charging is still not clear. Further research is needed to achieve a better understanding.
MODEL OF CHARGE SHARING The bull's-eye pattern is seen in both the wafer maps of antenna capacitor breakdown measurements and surface charge densities measured by EEPROM. The similarity between the yield and surface charge uniformity measurements implies a correlation. In this section, the yield of antenna capacitors is related to the surface charge density by a simple charge sharing model. The equivalent circuit of an antenna capacitor test structure has a field and a gate capacitor in parallel. For a first order approximation, the current through the gate oxide is negligible. Assuming that the plasma locally deposits a surface charge density, Q., on the wafer, a model based on charge sharing between the gate and field capacitors is as follows. After redistribution of the deposited surface charge, the voltage across the field and the gate capacitor is given by: V = q XX tf = xtg
(2)
where e is the permittivity of Si0 2, and qf, aa are the final charge densities on the field and gate capacitor, respectively. The conservation of charge gives (Af+Ag) xQ.=Af xqf+A, xqg
(3)
Eq. (2) and Eq. (3) yields the electric field in the thin gate oxide during plasma processing as (4) EG = qq X l1+ I' + Aj/Ag ef 1 + tgA//t (Ag where the last term is called the field enhancement factor FA. For a given tf/tg, FA initially increases with increasing Af/A. and then saturates at t11t2. Note that the general feature of this model is also valid if the plasma acts as a current source. We apply this model to explain the phenomena observed. With the Q, described in Fig. 5, the EG below the intrinsic breakdown field (- 1.3 x 107 V/cm) can be calculated for different values of FA as shown in Fig. 6. The critical radius, r, , defines the edge of the low local yield region. The antenna structure parameters (Af/Ag, tfltg) corresponding to the FA of Fig. 6 are shown in Table 1. With this model the r, increases and the yield decreases as FA increases because of an increase in Af/Ag for a given tf/tg= 142, or an increase in tf/tg for Af/Ag _Ž2000. This effect is observed in Fig. 3 and Fig. 4.
480
CONCLUSIONS In summary, we have investigated the role of "antenna" structure parameters on oxide breakdown integrity yield during plasma processing. Our results reveal that the oxide yield depends on both the area ratio (Af/Ag) and the thickness ratio (tf/tg). For a given tfIt, the yield initially decreases with increasing Af/A, and then saturates. The yield at saturation increases linearly with decreasing thickness ratio. In addition, wafer maps are made of defective breakdown capacitors. The location of damaged capacitors is concentrated at the wafer center and expands with increasing Af /A9 , and tj/t . A model based on charge sharing between the gate and field capacitors gives the electric field EG in the thin gate oxide during plasma processing. The EG is proportional to a structure dependent field enhancement factor FA and the surface charge density Q,. With surface charge density measurements, the distribution of oxide field EG during plasma treatment for different FA values can be calculated based on Eq. (4) and this simple model is consistent with our results.
ACKNOWLEDGEMENTS The authors would like to thank Prof. K.C. Saraswat and Dr. L-W. Wu for their helpful discussions, and WJ. Snoeys, S.S. Agarwal for providing the antenna mask. This research was supported by SRC and DARPA.
References [1] T. Watanabe and Y. Yoshida, Solid State Technol., 27, 263(1984). [2] K. H. Ryden, H. Norstrom, C. Nender, and S. Berg, J. Electrochem. Soc., 134, 3113(1987). [3] G. K. Herb et al., Proc. 13th Annual Tegal Seminar, 31(1987). [4] I.-W. Wu, et al., J. Electrochem. Soc., 136, 1638(1989). [5] W. M. Green, J. B. Kruger, and G. KooL, to be published in J. Vac. Sci. Technol. B, April 1991. [6] C. T. Gabriel, to be published in J. Vac. Sci. Technol. B, April 1991. [7] F. Shone, et. al., VLSI Sym. Tech. Dig. , 73(1989). [8] Y. Yoshida, R. Shirota, and K. Azumi, Proc. 9th Symp. Dry Process, 110(1985).
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[9] A. McCarthy and W. Lukaszek, Proc. IEEE Conf. on microelectronics test structures, Edinburgh, Scotland, March 1989. [10] K. Tsunokuni, et. al., Ext. Abstr. 19th Conf. Sol. Stat. Dev. and Mat'ls, Tokyo, 195(1987). [11] Y. Kawamoto, Proc. 7th Symp. Dry Process, 132(1985). [12] T. Namura and H. Uchida, Proc. l1th Symp. Dry Process, 74(1989).
482
EFFECTS OF PROCESS-INDUCED DAMAGE ON 115 A THIN GATE OXIDES AND THEIR REMOVAL BY LOW TEMPERATURE PASSIVATION S. Kar, A. Pandey, and A. Raychaudhuri Department of Electrical Engineering, Indian Institute of Technology, Kanpur-208016, India and S. Ashok Department of Engineering Science & Mechanics, The Pennsylvania State University, University Park, PA 16802, USA
After thermal oxidation, the oxidized silicon substrates were exposed to Si ion beams. Metallization was then carried out to complete the KOS structures. Comprehensive small signal admittance measurements were made. The admittance data were analyzed by the standard approach used for the silicon/silicon dioxide interface states. The results for ion-beam-exposed samples exhibited many anomalies. In these samples, the trap density obtained from the ac conductance was much smaller than that obtained from the static capacitance. Secondly, very high and very low state capture cross-sections were obtained. Thirdly, G /w versus w profiles exhibited multiple peaks. These and other anomalies are caused by the induction of a high density of defects in the bulk silicon and the oxide and the formation of a high resistivity layer in the silicon subsurface. These results underscore the need for a different circuit model to analyze the admittance data of processdamaged MOS structures. INTRODUCTION Among the important features of ultra large scale integration, are the use of very thin gate oxides, and an ever-increasing exposure of devices to ion and other high-energy particle beams. Ion implantation, ion-beam-assisted etching and deposition are standard processes today. Emerging applications include ion beam lithography and ion beam annealing. In the early years of ion beam processing, it was possible to anneal out almost all the ion beam damage. This task is getting to be difficult in future for a number of reasons, an important one being limitations on annealing and processing temperatures to avoid dilution of profiles, wafer warpage, and cross-diffusions. The present study was undertaken to monitor and understand the characteristics of electronic defects in ion-beam-exposed metal-oxide-semiconductor (MOS) structures with thin gate oxides. The gate oxide is considered to be most prone to radiation damage. The emphasis in this study was laid on understanding completely unpassivated devices, so that all the signatures of the radiation-induced electronic traps could be catalogued, which in turn
483
can facilitate the development of an effective low temperature damage passivation technique. This catalogue should also be useful in process fault diagnosis. EXPERIMENTAL DETAILS The MOS structures were prepared in the following manner. P-type silicon wafers were oxidized in dry oxygen (containing HCI) at 950 0C to reach an oxide thickness of 115 A. Post-oxidation annealing was carried out at 950 0C in N2 for 15 min. Subsequently, the oxidized silicon wafers were exposed to 16 keV Si ions in a Varian 350D ion implanter at 300 K, such that the peak of the total target displacements was located at the silicon-oxide interface. Si ions were chosen 1 to deemphasjze the chemical effects. The ion dosage was varied from 1010/cm to 10 1/cm . Following implantation, Al front (1.0 mm dia dots) and Au back contacts were evaporated in an oil-free ion-pumped Varian VT-112 UHV system using filament sources. Most of the samples were characterized electrically without any sort of damage passivation or annealing. The electrical characterization was carried out using the Hewlett Packard 4061S semiconductor/component test system, equipped with 4192A impedance analyzer, 4140B pA meter/DC voltage source, 7475 graphics plotter, and the 310M controller. Direct current-voltage, quasistatic capacitancevoltage, and sinusoidal small signal capacitance-voltage, conductancevoltage, conductance-frequency measurements were made. The sinusoidal frequency was varied between 80 Hz and 3 MHz. Static capacitancevoltage measurements [1] were made using a Keithley 595 meter. Ellipsometric data were obtained using a Rudolph Research A7905 automatic ellipsometer. RESULTS AND DISCUSSIONS Many interesting new features were observed in the admittance characteristics of the unpassivated ion-beam-exposed M0S structures. One of these related to the experimental data obtained on interface state parameters. These parameters were obtained using the standard MOS admittance techniques [2-4]. In the case of the standard technique, it is assumed that all the traps, that contribute to the observed ac admittance, are located at the silicon/oxide interface. Figure 1 presents the interface state density distributions obtained from the static capacitance-voltage (C-V) characteristics [2], indicated by solid lines, as well as from the conductance-frequency (G-f) characteristics [3], indicated by broken lines, for samples with different ion dosages. For many ion-beam-exposed MOS structures, multiple peaks were observed in the Gp/w versus f (G is the parallel conductance, and w is the small signal angular frequency) profiles. It may be mentioned that for regular MOS structures only one such peak is seen. Figure 2 depicts the Gp /W versus f profiles for sample A12 for different bias values. Two peaks can be seen in each profile, and accordingly, two state density distributions were obtained for this sample from the ac conductance data, as indicated by A and B in Fig. 1. Figure 3 contains the profiles of the hole capture cross-section versus the silicon bandgap energy, for
484
the same samples as in Fig. 1. It may be noted that for sample A12, there are two profiles A and B, for the reason already mentioned.
FIG. 1: Experimental interface state density as a function of the bandgap energy, measured from the valence band edge, for samples, exposed to different ion dosages. The solid lines represent values obtained from the static capacitance data, and the broken lines, data obtained from the ac conductance data.
BANDGAP
ENERGY
leVI
SMALL SIGNAL
FREQUENCY
[Hz]
FIG. 2: Experimental parallel conductance/angular frequency [Gp/W] as a function of the sinusoidal small signal frequency, for sample A12, for two applied bias values.
485
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ua
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: tpetiiueiiai_ nole capture cross-section as a function of the bandgap energy, measured from the valence band edge, for samples, exposed to different ion dosages. For the profile B of sample A12, the right hand scale applies, while for the rest, the left hand scale.
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The profiles of Fig. I indicate that, with increasing ion dosage, the value of interface state density, obtained from the ac conductance, becomes progrssively smaller than that obtained from the static capacitance. It may be mentioned that if the defect states are located only at the interface, then in principle the same value of state density should be obtained from both static capacitance as well as ac conductance, as is the case for the control (unexposed) sample AO0, cf. Fig. 1. The profiles of Fig. 3 indicate unusually high and unusually low capture cross-sections for the ion-beam-exposed samples, while typical values are obtained for the control sample AO0. The source of these anomalies lies in the fact that in unpassivated ion-beam-exposed MOS structures, there is significant contribution to the ac admittance from traps located, away from the interface, in the oxide and in the silicon sub-surface layer. In the case of ion-beam exposed MOS structures, the bulk silicon traps may be created mainly by the atomic displacements, while the interface and the oxide traps may be created both by the atomic displacements and ionizations by ions/recoil atoms as well as attendant x-rays [5-7]. For the charging or discharging of oxide traps, the free carriers have to be transported from the silicon surface, most probably by tunneling through the oxide potential barrier [8]. The charging or discharging of the oxide, the interface, and the bulk silicon traps (all assumed to be multi-level) is illustrated in the energy band and the equivalent circuit diagrams of Fig. 4. It is assumed that only states located at or near the Fermi level take part in charging or discharging, i.e. the states whose energy levels intersect the silicon band-bending, as represented by the rectangular boxes in 486
Fig. 4a. In principle, the contribution to the static capacitance will come from all these states, although with varying weightages, since all the states should be able to follow the static signal. Figure 5a represents the reduction of the equivalent circuit in Fig. 4b at static frequencies. It may be noted that, as all states can follow the static signal, there is no loss involved, hence, the circuit of Fig. 5a is purely capacitive.
Ebt,==---EE
FIG. 4: (a) Energy band diagram of the MOS structure, for a given bias, illustrating the charging or discharging of the oxide traps (levels Eotl and Eot 2 ), the interface traps (level Eit), and the bulk traps (Ebtl and Ebt2). (b) Equivalent circuit representation of the MOS structure of Fig. 4a. Cox is the oxide capacitance. C 1 ' C and Cs 3 are capacitances of diterent sections of the surface space charge layer. If there is no contribution from the shallow dopants, these are then dielectric capacitors. Cbtl and Rbtl, and Cbt2 and Rbt2 represent the bulk trap impedances. Cit and Rit represent the interface state impedance. Cot, and Rot,, and Cot2 and Rot 2 represent the oxide trap impedances.
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SILICON 0
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X,2
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OXIDE 33 1ý4
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INTERFACE IA 'r I -R it Rbt Rb~at W
C(b)d
CC
Cs2
Cot
COX
Cs 3
CA-Cotl.CWA
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Cs2
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Co,1 FIG. 5: (a) Represents the reduction of the equivalent circuit in Fig. 4b under the static condition. (b) Represents the reduction of the equivalent circuit in Fig. 4b at an intermediate frequency, such that the time constant of the bulk trap level Ebt2 at x - x 2 is 11w.
Rbt2 Cbt2 C51. Cb
Cs2
C5 3
Cox
In the case of ac conductance, comes mainly
from states,
whose
the contribution to the conductance
time constant
is
about 1/w.
This means
that, for a given bias, i.e. a given silicon band-bending, and a given signal frequency, the contribution to the conductance will come only 487
from states of one energy level and located in one or a few atomic planes. Figure 5b represents the reduction of the equivalent circuit in Fig. 4b at an intermediate frequency, such that the time constant of the bulk trap level Ebt2 at x - x 2 is 1/t, for the given bias. It may be noted that the traps located at the Fermi level in Fig. 4a to the right of x 2 cannot follow the intermediate signal, hence their equivalent series RC branches in Fig. 4b can be open-circuited, while the traps located at the Fermi level to the left of x 2 can follow the intermediate signal very well, hence the resistances in their equivalent series RC brances can be short-circuited. The very high and very low values obtained for the hole capture cross-sections can be interpreted in the following way. The source for the very low values of the cross-section may be the oxide traps, while for the very high values may be the bulk silicon traps. Since electrons/holes have to tunnel to the oxide traps, the free carrier density at the oxide trap is reduced by the tunneling probability. Since the standard MOS conductance technique has been used for data analysis, the value of the carrier density used for calculating the cross-section is what obtains at the interface, hence, orders of magnitude lower cross-section may have been obtained than the actual. On the other hand, for the bulk silicon traps, the actual free carrier density is orders of magnitude higher than that at the interface, hence, use of the standard procedure may lead to much higher values of the cross-section than the actual. Two factors may be responsible for the discrepancy observed in the state density profiles of Fig. 1. Kramers-Kronig relations holds for the interface states alone [3]. When bulk silicon and oxide states are also present in a significant manner, [G/w]max is no longer related to the total trap capacitance, as obtained from the static capacitance. This happens, because, contribution to the conductance at given bias and frequency always comes from states in one or a few atomic planes, while that to the static capacitance at a given bias will come from states in many atomic planes. Secondly, different equivalent circuits have to be used for the analysis of the static and the conductance data to obtain the actual state densities, as Figs. 5a and 5b indicate. The surface potential at a given bias is experimentally obtained by integrating the static capacitance-voltage characteristic [2]. For a regular MOS structure, the surface potential can also be obtained from the high frequency C-V characteristic, although with lower accuracy. For the ion-beam-exposed samples, it was found that the surface potential difference obtained from the high frequency C-V plot, for a certain bias range, was much larger than that obtained from the static C-V plot. The reason for this anomaly may lie in the fact that the high frequency C-V plot for these samples does not represent the space charge capacitance arising out of the shallow dopants. The atomic displacements in the silicon sub-surface generate bandgap states throughout this region, which trap free carriers donated by the dopants. This deactivation of the dopants leads to the formation of a high resistivity or an intrinsic 488
layer [9,10], and therefore, the high frequency C-V plot in an ion-beamexposed MOS structure may not have any relation to the theoretical space charge capacitance of shallow dopants. Another manifestation of an intrinsic layer in the silicon subsurface was the interesting observation of very low frequency dispersion of the accumulation capacitance. Figure 6 presents the measured static as well as sinusoidal signal capacitance-voltage charyateristics of sample A12, which was exposed to an ion dosage of 10 2/cm . For a standard MOS structure, the MOS capacitance approaches the oxide capacitance, and this capacitance does not exhibit any frequency dispersion at low frequencies. The following interpretation is possible for the frequency dispersion observed in the accumulation region in Fig. 6. The existence of the intrinsic layer results in the formation of a pi junction in series with the accumulation space charge layer, which is very thin. As the gate metal is an array of 1.0 mm dia circular dots, and the back contact area is orders of magnitude larger, the silicon subsurface region has to be represented by a distributed network, as illustrated in Fig. 7. Under the static condition, the lateral resistance elements R. 'a can be short-circuited, and the pi junction capacitance elements ake then in parallel. The sum capacitance SC4 p is much larger than the oxide capacitance, and so is the accumulation layer capacitance Cs, hence under the static condition, the MOS accumulation capacitance, Caccs, approaches the oxide capacitance. Static C-V measurements with different step delay times indicate the time constant R.C. to be in the range of 0.1-10.0 s, depending upon the ion dosage. At frequencies higher than the inverse of this time, the lateral series elements Ri 's can be open-circuited, which results in Cox Cs, and C being in series. As Ci is smaller than Cox, especially for very thit oxides, the MOS accumulation capacitance, C I becomes smaller than the oxide capacitance even at 80 Hz. At stilfcg hher frequencies, Caccss decreases further because of the series resistance R in the i layer. A value for this resistance was obtained from the impednce measurement on the impedance analyzer HP 4192A at 100 kHz under the accumulation condition. This measured total series resistance Rs was found to increase with the ion dosage, cf. Table I. Ellipsometric measurements indicated a change in the intermediate parameters 6 and 0 with the ion dosage, cf. Table I, which provides supporting evidence for the presence of a damaged layer at the silicon surface. Table I shows that the static MOS capacitance in accumulation Caccs increases significantly at high ion dosages beyond the value measured for the control sample. This increase could be partly explained by sputtering of the very thin oxide during the ion beam exposure. However, annealing was found to restore Ca c to the value measured for the cy troll sample. Also, calculations indicate that even at the dosage of 10 /cm , only a few A of the oxide could be etched at the most. The most likely interpretation of the oxide capacitance increase is the increase in the oxide dielectric constant due to space charge effects, caused by atomic displacements in the oxide. At high ion dosages, atomic displacements and replacements can give rise to significant non-
489
stiochiometry in the oxide [11], which in turn leads to silicon-rich oxide islands. These silicon-rich oxide regions, i.e. SiOx regions, where x is <2.0, can be expected to have bandgaps lower than that of SiO2 , and may act as traps for electrons and holes, as illustrated in Fig. 8. Charging/discharging of these traps can result in a higher dielectric constant.
h.
FIG.6: Capacitance-voltage characteristics of sample A12, measured at various frequencies
#m. Z
APPLIED BIAS IV]
GATE METAL Cc,
OXIDE INTRINSIC LAYER BULK GAP STATES Ri
R.
_p
. s
J;s.j
Ic-i.Ici.
_v
BACK CONTACT
_P
I-c T"o
F' T
P-silicen
R.
FIG. 7: Equivalent circuit representation of an MOS structure in accumulation, having an intrinsic layer in the silicon sub-surface. Cox is the oxide capacitance, Cs is the surface accumulation capacitance, R is the series resistance of t~e neutral region of the intrinsic layer, Ri is the lateral resistance element of the neutral intrinsic layer, and Ci is the capacitance element of thX pi junction.
490
TABLE 1: Experimental Data Related the Silicon Subsurface. Sample
AOO A12 A13 A14 A15
Dose 2 [c [em-2]
R s [S]
C accs [nF/cm
0 1012 1013 1014 1015
76 137 127 595 729
301 306 314 365 473
to Formation of Intrinsic
I
Layer
Caccs/Caeess ac2
6 [deg]
[deg]
0.97 0.72 0.72 0.68 0.56
148.3 146.1 147.1 149.5 148.6
11.50 11.63 12.00 13.46 20.92
in
FIG. 8: Energy band diagram structure in of an MOS containing accumulation, silicon-rich oxide, i.e. SiOx with x < 2.0, islands in the Si0 2 matrix. The SiOx regions can be expected to have lower bandgap than that of Si0 2 .
The above features appear to be reliable signatures of ion-beaminduced damage, and can be utilized to monitor the residual radiation damage, and in process fault diagnosis of ULSI circuits. These results models for also underscore the need for developing new circuit representing process-damaged MOS structures, and a new technique for analyzing the small signal admittance data. thermal annealing and ion beam Both the low temperature For ion dosages up to hydjogenation showed encouraging results. 0 10 /cm , post-metallization thermal annealing in pure H2 at 350 C was found to be effective in greatly reducing the defect state density and in removing the low frequency accumulation the series resistance, capacitance dispersion, and in restoring the oxide dielectric constant to its standard value. Ion beam hydrogenation [Kaufman source, 650 eV ion energy, substrate temperature 250 C] was found to be effective in reftcini the state density even when the ion dosage was as high as 10 /cm , but the hydrogen ion beam causes significant etching of the oxide.
491
CONCLUSIONS In ion-beam-exposed KOS structures, defect states are present not only at the silicon-oxide interface, but also in the silicon sub-surface and the oxide, due to atomic displacements and ionizations by ions, recoil atoms, and x-rays. The presence of oxide and bulk-silicon defect states leads to the discrepancy between the gap state capacitance obtained from the static MOS capacitance and that obtained from the ac MOS conductance, and to the appearance of multiple peaks in the G /w versus f profiles. The radiation-damage-induced bulk silicon states compensate the dopants, leading to the formation of an i layer, which in turn causes dispersion of the HOS accumulation capacitance even at low frequencies. At high ion dosages, atomic displacements and replacements in the oxide lead to non-stoichiometry, resulting in space charge effects. The latter causes an increase in the oxide dielectric constant. Initial results indicated low temperature thermal annealing as well as ion beam hydrogenation to be effective in removing ion-beam-induced damage. ACKNOWLEDGEMENTS This work was carried out with support from the National Science Foundation, Washington, D.C., the Department of Electronics, New Delhi, and the Department of Science and Technology, New Delhi. The authors would like to thank K. Srikanth for assistance in ion implantation and H. P. Vyas for assistance in oxidation. REFERENCES [1] K. Ziegler and E. Klausmann, Appl. Phys. Lett., 26, 400(1975). [2] C. N. Berglund, IEEE Trans. Electron Devices, ED-13, 701(1966). [3] E. H. Nicollian and A. Goetzberger, Bell Syst. Tech. J., 46, 1055(1967). [4] S. Kar and S. Varma, J. Appl. Phys., 58, 4256(1985). [5] J. F. Gibbons, Proc. IEEE, 60, 1062(1972). [6] J. F. Ziegler, Ed. Ion Implantation Science and Technology, Academic Press(San Diego, 1988).
[7] D. L. Griscom, J. Appl.
Phys.,
58,
2524(1985).
[8] E. H. Nicollian and J. R. Brews, MOS(Metal Oxide Semiconductor) Physics and Technology, Wiley(New York, 1981). [9] W. R. Fahrner, C. P. Schneider, and E. F. Gorey, Phys. Status Solidi, 95, 343(1986).
[10] H. C. Chien and S. Ashok, J. Appl. Phys., [11] M. Offenburg and P.
Balk, Appl.
Surf.
492
60,
Sci.,
2886(1986).
30,
265(1987).
RADIATION-INDUCED NEUTRAL ELECTRON TRAP GENERATION IN ELECTRICALLY BIASED IGFET GATE INSULATORS M. Walters' and A. Reisman"'
2
'Center for Microelectronics, MCNC Research Triangle Park, NC 27709-2889 2
Department of Electrical and Computer Engineering North Carolina State University, Raleigh, NC 27695-7911 Optically assisted electron injection was employed for the first time to quantify both neutral electron trap and fixed positive charge concentrations in the gate oxides of electrically biased n-channel Insulated Gate Field Effect Transistors (IGFETs) exposed to 10 keV X-rays. Most surprisingly, the results showed that neutral electron trap generation is dependent upon the gate bias, and the oxide thickness in a similar manner to positive charge build-up during irradiation. This suggests a possible association between the two defect types. One possible model describing such a link, in which the E'., trapped hole center transforms into a dipolar neutral electron/hole trapping site via electron annihilation is presented. INTRODUCTION Integrated circuits of insulated gate field effect devices may be exposed to ionizing radiation during fabrication, or while operating in a hostile environment. Capacitancevoltage measurements (which are sensitive only to net quantities of coulombically charged defects) do not identify all the defect types that are formed in oxides exposed to ionizing radiation. Specifically, radiation-induced neutral electron traps in SiO 2 not detectable by C-V measurements, have been identified using electron injection techniques [1-3]. These neutral electron traps represent a reliability concern due to possible hot electron trapping during device operation, or when used in an ionizing radiation environment. The structure of neutral electron traps, and how they are formed remains unknown. No electron spin resonance signal has been detected which can be attributed to these neutral electron traps. It has been suggested that neutral electron traps may be dipolar in nature, with the separation between the poles related to their trapping cross-section [2]. The present study is the first known work to investigate neutral electron trap generation under electrically biased irradiation conditions. It will be shown that fixed positive charge and neutral electron trap concentrations are both dependent upon electrical biasing conditions during irradiation and the oxide thickness in a similar fashion. This result is very surprising, and possibly indicates that the generation mechanism of neutral electron traps is in some manner dependent upon the presence of fixed positive charge at an intermediate stage. One possible model describing such a link 493
will be presented. EXPERIMENTAL PROCEDURE Fixed positive charge and neutral electron traps in the gate oxide of polysilicongated IGFETs were determined using an optically assisted electron injection technique as described previously [1,4]. The gate insulators were grown at 800'C in an 02 - 4.5% HCl ambient atmosphere. The devices were irradiated at room temperature under various gate bias conditions with 10 keV X-rays at a dose rate of 180 krad(Si)/min. Electron injection was performed prior to irradiation to measure "intrinsic" defect levels, and then on different devices on the same die following irradiation to measure radiation-induced "extrinsic" defect levels. Zero voltage shifts were observed prior to irradiation following the injection to annihilate fixed positive charge, while small quantities of intrinsic neutral electron traps with cross sections of about 10-16 cm 2 were detectable prior to irradiation. Devices with 35 nm thick gate oxides exhibited threshold voltage shifts of about 0.06 volts following the injection sequence to label the "intrinsic" large neutral electron traps. RESULTS Gate Bias Dependence Figure 1 shows the post-injection, post-irradiation threshold voltage shifts associated with fixed positive charge and filled (labeled) neutral electron traps as a function of the applied gate bias during irradiation. Such a dependency of the radiationinduced positive charge build-up has been explained in the literature in terms of hole transport phenomena [5,6]. When the applied gate bias is near zero, most of the electronhole pairs generated by the radiation in the oxide bulk recombine, and only holes which are generated in or very near the trapping region of the oxide can be trapped to form fixed positive charge. Under positive gate bias, however, electrons generated in the oxide bulk rapidly drift toward the gate electrode, while the radiation-induced holes transport much more slowly toward the Si/SiO2 interface. As a result, under bias, a significant number of holes which were generated in the oxide bulk do not recombine and can contribute to positive charge build-up by being trapped in the neutral hole traps which reside near the Si/SiO 2 interface. Under an applied negative gate bias hole motion is toward the gate electrode, and so only the holes generated near the Si/SiO 2 interfacial trapping region become trapped there. Figure 1 shows that the number of neutral electron traps which are "labeled" following irradiation is also dependent upon gate biasing during irradiation, in a similar fashion as fixed positive charge. This result is quite surprising, since it is unclear why the generation of a neutral defect should be influenced by an applied electric field. Such a dependence on the gate bias could be speculated upon if trapped positive charge were somehow "required" for subsequent neutral electron trap generation to occur. 494
'4.V
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•
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1.0 0)
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7
1
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-3.0
-2.0
.1.
I.
- .0 0.0 1.0 Gate Bias (MV/cm)
I.
I
2.0
3.0
Figure 1: Gate Bias Dependence
Oxide Thickness Dependence Previous reports [1,7] using identical oxides have shown that the AVr vs to. behavior under conditions of zero gate biasing during irradiation is accurately described by the defect distribution model shown in Figure 2, and that the number of intrinsic hole traps in the defect region of unirradiated devices is constant (independent of the oxide thickness when the oxide thickness is larger than about 10 nm) while following irradiation, the sum of residual hole traps and fixed positive charges formed by filling hole traps is equal to this constant. In terms of the positive charge build-up as a consequence of irradiation, its oxide thickness dependence can be understood as follows. Under conditions of zero gate bias during irradiation, only those holes created in or very near the trapping region become trapped, the remainder being annihilated by recombination with generated electrons. Thus, when the gate electrode lies in Region (1), above the trapping region (Region 2) of Figure 2a, the number of trapped positive
charges, ND, is independent of the oxide thickness. This results from the fact that uniform electron-hole pair creation throughout the oxide leads to the same number of holes being created in the vicinity of the trapping region, independent of the thickness.
495
(1)
(a)
S102
tox -
-h2 I
A -
(3) Si
S102
(b)
tox{
t
z.
R eg:::::::::::::::n:.
Si Figure 2: Defect Distribution Model
Mathematically, Fig. 2a can be described as follows. In Fig. 2a, if A is the distance of the positive charge centroid above the Si/SiO 2 interface, then the threshold shift dependence when the gate electrode lies in Region (1) becomes[1]: A
•1
-- N,,O Qt,,_-A)
(1)
where N°O is the constant number of trapped positive charges, (t., - A) is the centroid of the distribution, e- is the charge on an electron (or hole), e is the SiO 2 dielectric constant, and S0 is the permittivity of free space. Region (3) of Figure 2a represents a region near the Si/SiO 2 interface which remains free of positive charge. It is believed that in this region trapped holes within a tunneling distance of this interface will be annihilated by a recombination process involving electron tunneling from the Si substrate [1,5]. Figure 2b represents the case for thin gate oxides, where the top gate electrode encroaches upon the trapping region. The number of trapped positive charges decreases with decreasing oxide thickness because of the decreased trapping region width. Taking into account the additional decrease due to tunneling phenomena within a distance h I from either oxide interface [1], the threshold voltage shift expression for this case can be 496
written as: AV(2)-
e
N
eco 2(h 2 - h1 )
t
(Q -2h_1)
Ox
(2) 2
where ND refers to the constant charged defect density when the top electrode lies above the defect region (tox _ h 2+h 1), h 1 is the distance between the substrate and the bottom of the defect region, and h 2 is the distance between the substrate and the top of the defect region when the latter is not encroached upon by the top electrode (see Fig. 2a and 2b). In Eq. 2 a simplifying assumption has been made that the positive charge is uniformly distributed in Region (2), such that the centroid is just half the oxide thickness. For oxide thicknesses less that 2h 1,all trapped positive charge is annihilated by electrons tunneling into the oxide and AVr = 0. Equations 1 and 2 apply when only the holes created within or very close to the trapping region become trapped to form fixed positive charge. Under positive bias during irradiation, holes created throughout the oxide bulk can also contribute to hole trapping because they are able to migrate without being annihilated into the trapping region. Since the number of holes created in the bulk is assumed to be linearly dependent on the oxide thickness, it follows that the number of trapped holes also be linearly dependent on the thickness, i.e., ND = b(Q, -2h 1 )
(3)
where the quantity (tox - 2h 1) is the thickness of the oxide region from which hole transport makes a contribution to the trapped positive charge density. The parameter b in the above equation is the fraction of the volume density of holes created throughout the oxide which become trapped to form fixed positive charge. Thus, the threshold shift expression when the top electrode lies in Region (1), above the defect region, can be written: (4) _ h ) (toX _-A) e -[&o Under positive gate bias, the expression for AV42) for thin oxides where the top electrode encroaches upon the trapping region can be written as: e-2) [b (to -_2h1)] (5) (assuming a uniform trapped charged distribution in the thin oxides). A log-log plot of the threshold voltage shifts associated with fixed positive charge as a function of the gate oxide thickness for different gate bias conditions are shown in Figure 3. The curves in Fig. 3 are the best fit of the appropriate equations (1,2,4 or 5) to the data. Under conditions of zero or negative gate biasing, where hole transport from the bulk oxide outside the defect region does not contribute to positive charge build-up
497
slope -+ 2
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i
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60
Gate Oxide Thickness (nm) Figure 3: Oxide thickness dependence of positive charge build-up
5.0000
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(0X 20 O0
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A 0 MV/cm
0--
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A Dose - 1 Mrad(Si)
U
5
10
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Gate Oxide Thickness (nm) Figure 4: Oxide thickness dependence of neutral electron trap generation
498
within the defect region, the log-log slopes at large t,,, are observed to approach unity, consistent with the linear relationship between AVT and t., given by Eq. (2). Under positive gate biasing, where enhanced hole transport from the oxide region outside of the
defect region does contribute to positive charge build-up within the defect region, the log-log slope is observed to approach 2 at large to,, consistent with the quadratic relationship between AVT and to. given by Eq. (4). Figure 4 shows the corresponding AVT vs tox curves for the voltage shifts associated with injection labeled (filled) radiation-induced neutral electron traps. Very surprisingly, as a function of the applied field during irradiation, these voltage shifts are observed to exhibit a similar dependency on the oxide thickness to the shifts associated with radiation-induced fixed positive charge. The values of the defect distribution parameters that were obtained by fitting the data to the equations specified by the model suggest that radiation-induced neutral electron traps are spatially distributed in approximately the same location in the oxide as are trapped holes (fixed positive charge). Nearly the same values were obtained for the distance of the centroid above the Si/SiO2 interface (A) for a given gate bias condition for both fixed positive charge and neutral electron traps. This further indicates that there might be a vital heretofore unreconized connection between fixed positive charge and neutral electron traps. Total Dose Dependence While the experimental results show similar behavior for radiation-induced neutral electron trap generation and positive charge build-up, it is apparent from the magnitude of the voltage shifts associated with the two defect types that for a given dose, the defect densities can be quite different. Figure 5 shows the radiation dose dependence of fixed positive charge and the generated neutral electron traps. The saturation of fixed positive charge at Mrad dose levels can be explained in terms of increased electron-hole recombination [8] and electron annihilation of trapped positive charge [3,9] as positive charge build-up reaches a maximum. When the trapped hole space charge field balances the field at the gate electrode, a critical trapped hole density is reached where electronhole recombination is enhanced and additional hole trapping events are balanced by electron annihilation. Fig. 5 indicates that neutral electron trap generation markedly increases at approximately the dose level where the shift associated with fixed positive charge is curtailed. In fact, the fixed positive charge curves are concave relative to the dose axis while the neutral electron trap curves are convex relative to the axis. This suggests that if there is a link between radiation-induced fixed positive charge and the neutral electron traps which are generated, then this connection arises from electron annihilation of trapped positive charge, rather than from the hole trapping event itself.
499
St• 'I)
>
2.5
S2.0 0 1.5 L-
1.0
0.5 0.0 IxlO4
ix10
5
1xlO
6
1x10
7
1x10
8
Dose in Rad(Si) Figure 5: Total dose dependence A POSSIBLE NEUTRAL ELECTRON TRAP GENERATION MODEL Recently, Lelis, et.al. [101 have proposed a trapped hole annihilation process which can lead to a dipolar structure. Previously, Aitken, et.al.[21 had speculated that the neutral electron trap is dipolar in nature. The results of the present study indicate that neutral electron traps may be generated from fixed positive charge by the electron annihilation of the latter. A neutral electron trap generation model based on a mechanism involving a fixed positive charge precursor is presented in Fig. 6. Figures 6A and 6B represent the accepted picture of positive charge buildup that has emerged from the literature. The pre-existing neutral hole Irap is portrayed as an oxygen vacancy type of defect; essentially a weak Si:Si covalent bond. A radiation-generated hole can become trapped at such a site (Fig. 6B), leaving one trivalently bonded Si atom with a dangling orbital containing one unpaired electron. Electron annihilation of trapped positive charge depicted by Figs. 6B--6C is the process proposed by Lelis, et.al.[10] In this process, an electron is attracted toward the positively charged silicon atom. This electron could reside on this atom only temporarily, since this configuration could consist of two unpaired spins in parallel alignment. In a very short time either the original Si:Si bond reforms, or the electron from one of the Si atoms decays to a ground state by joining the unpaired electron on the other Si atom, as depicted by Fig. 6C. Either of these events neutralizes the trapped hole and removes the unpaired spin. If the bond does not reform, 500
(A)
(B)
Fixed Positive Charge (E' Center)
radiation-induc ed hole trapping
Neutral Hole Trap (weak SI:Si bond)
electron annihilation
Neutral Electron/Hole Trap (Dipolar - Amphoteric)
electron redistribution
bond relorma'ion
r
.4----
Neutral Hole Trap (weak S5:SI bond)
Se-
Unstable State (not observed)
electron trapping
(C) /I'•\
k1U
Figure 6: A possible neutral electron trap generation model Fixed Negative Charge
501
but the two electrons localize around one of the Si atoms, then one of the Si atoms becomes negatively charged and the other becomes positively charged. This results in an amphoteric electrically neutral dipolar structure, (capable of either electron or hole capture), which is the type of structure proposed by Aitken, et.al.[2] for the neutral electron trap defect. The captured electron structure (fixed negative charge) shown in Fig. 6D is very similar to the structure identified by Kamigaki, et.al.[12] as the trapped electron structure in amorphous silicon nitride. It is this electron trapping event that gives rise to the threshold voltage shifts associated with filled neutral electron traps following electron injection. CONCLUSIONS A possible neutral electron trap generation model was developed, based on the observations of the present study and the positive charge annihilation process proposed by Lelis, et.al. [10]. In this model, fixed positive charge (the trapped hole E', center) is capable of transforming, via annihilation by an electron, into a dipolar defect which is electrically neutral at a distance removed from the defect, has no unpaired spin, and is capable of electron or hole capture. According to the model, when such a neutral trap captures an electron, a negatively charged defect (fixed negative charge) that contains an unpaired spin results. The 'detection of such fixed negative charge by electron spin resonance, and the subsequent identification of the structure associated with this defect, might provide sufficient evidence to either verify or refute the speculated neutral electron trap generation model presented here. REFERENCES [1]
M. Walters and A. Reisman, J. Apple. Phys., 67, 2992 (1990).
[2]
J.M. Aitken, D.R. Young, and K. Pan, J. AppI. Phys., 49, 3386 (1978).
[3]
A. Reisman and C.J. Merz, J. Electrochem. Soc., 130, 1384 (1983).
[4]
T.H. Ning and H.N. Yu, J. AppI. Phys., 45,5373 (1974).
[5]
N.S. Saks, M.G. Ancona, and J.A. Modolo, IEEE Trans. Nucl. Sci., NS-31, 1249 (1984).
[6]
N. Shiono, M. Shimaya, and K. Sano, Jap. J. Appl. Phys., 22, 1430 (1983).
[7]
L. Lipkin, A. Reisman, and C.K. Williams, Appl. Phys. Lett., 57, 2237 (1991).
[8]
H.E. Boesch, Jr., andJ.M. McGarrity, IEEE Trans. Nucl. Sci., NS-23, 1520 (1976).
[9]
R.B. Klein, N.S. Saks, and Z. Shanfield, IEEE Trans. Nucl. Sci., 37, 1690 (1990).
[10] A.J. Lelis, T.R. Oldham, H.E. Boesch, Jr., and F.B. McLean, IEEE Trans. Nucl. Sci., 36, 1808 (1989). [11] Y. Kamigaki, S. Minami, and H. Kato, J. Apple. Phys., 68, 2211 (1990).
502
ADVANCED EQUIPMENT AND SENSOR TECHNOLOGIES FOR RAPID THERMAL PROCESSINGt Mehrdad M. Moslehi, Habib Najm, Lino Velo, Richard Yeakley, John Kuehne, Bill Dostalik, David Yin, and Cecil J. Davis Semiconductor Process and Design Center Texas Instruments, Dallas, Texas 75265
ABSTRACT Advanced rapid thermal processing equipment and sensors have been developed for in-situ fabrication of semiconductor devices. Highperformance multi-zone heating lamp modules with cylindrical symmetry have been applied to various processes including rapid thermal oxidation, chemical-vapor deposition of tungsten and amorphous/polycrystalline silicon, silicide formation, as well as hightemperature rapid thermal annealing. Concurrent use of multi-zone heating lamps and multi-point temperature sensors provides a capability for real-time wafer temperature control and process uniformity optimization. Specific design features and experimental results will be presented on the multi-zone lamp modules, in-situ sensors for process monitoring and control, and single-wafer thermal processing applications. RAPID THERMAL PROCESSING FOR SEMICONDUCTOR MANUFACTURING The continuing trend for enhanced performance requirements of microelectronic systems has been a significant driver involved in semiconductor technology scaling. Advanced microprocessor chips are now using well over 1 million transistors per chip and this chip integration density is expected to exceed 100 million transistors by the end of this decade. Moreover, future generations of memory chips will pack 1 billion memory bits at the turn of the century. These enormous device integration levels place stringent demands on device fabrication technologies, semiconductor processing equipment, and process control methodology in order to meet the overall manufacturing yield, cycle time, and throughput requirements. Semiconductor technology scaling also affects wafer size. Currently, the state-of-the-art chip factories are set up for 200-mm wafer processing. The wafer size (diameter) is expected to grow to 250 mm and beyond (i.e., 275 mm and 300 mm) with future technology generations. Single-wafer processing (SWP) is an alternative to batch equipment for various det Invited Paper
503
vice fabrication processes. As the wafer size increases beyond 150 mm, advanced SWP equipment will be preferred over the batch equipment for many applications. The factors in favor of SWP include compatibility with multi-chamber cluster equipment for vacuum-integrated processing, improved fabrication cycle time, and enhanced fabrication process repeatability. A major argument against SWP has been its inferior processing throughput compared with the batch equipment. However, many applications can afford somewhat lower fabrication throughput in return for enhanced capabilities for integrated processing and improved manufacturing process control. Rapid thermal processing (RTP) has been used as a versatile SWP technique for various thermal processing applications [1]. Examples of RTP applications include junction annealing, silicide formation, epitaxy, chemical-vapor deposition (CVD), as well as rapid thermal oxidation (RTO) and nitridation (RTN) processes. However, various problems associated with wafer temperature measurement and dynamic temperature/process uniformity control have hindered the widespread use of RTP in semiconductor device manufacturing factories. This paper presents'some effective solutions to these problems. Multi-zone wafer heating lamps have been developed which provide cylindrical optical symmetry and independently controlled zones for real-time wafer temperature uniformity control. Moreover, numerous in-situ process monitoring sensors have been developed to meet the RTP-related process monitoring and control requirements. Some process applications of advanced load-locked singlewafer RTP techniques and associated sensors will be described. These include RTO, CVD of tungsten, as well as CVD of polysilicon and amorphous silicon. HIGH-PERFORMANCE MULTI-ZONE RTP LAMP MODULES The known RTP systems mostly employ single-zone tungsten-halogen or arc lamp modules for wafer heating. The lamp module is usually designed to provide relatively uniform steady-state wafer heating over a narrow range of wafer temperatures. The conventional RTP lamp modules provide real-time lamp power control capability for only a single zone. This has been known to impose major limitations in terms of dynamic (transient and steady-state) wafer temperature uniformity and slip dislocation control [2]. For a given optical flux distribution on a semiconductor wafer, temperature uniformity can be affected by various additional parameters such as gas flow rates and process pressure. Moreover, the transient heat-up and cool-down temperature uniformity of a wafer can be quite different from the steady-state uniformity [2]. These observations imply that the conventional single-zone lamp RTP systems may not be able to meet the stringent wafer temperature and process uniformity requirements over an extended domain of process parameters. Recent developments in the area, of RTP equipment have addressed these requirements. One approach has been to use a crossed lamp configuration which employs two parallel crossed banks of linear tungsten-halogen lamps above and below the wafer [3]. This technique is certainly superior to the conventional single-zone RTP designs; however, due to lack of cylin504
-7
Figure 1: Schematic illustration of a Texas Instruments' single-wafer (TI-AVP) reactor with a multi-zone lamp heating module.
drical symmetry, only a limited real-time wafer temperature uniformity control can be achieved [3]. This limitation is due to the circular shape of semiconductor wafers and linear/crossed configuration of the lamps. The approach to be described here has been to design and develop advanced multizone (2-zone, 3-zone, and 4-zone) lamp systems with overall cylindrical symmetry. Figure 1 shows a schematic (cut-away) illustration of Texas Instruments' advanced automated vacuum processor (to be called TI-AVP) using a 3-zone lamp module. The 3-zone lamp module employs a single center lamp, a first ring of 12 lamps, and an outer ring of 24 lamps (total number of tungsten-halogen lamps: 37). The combination of the point-source lamps in each ring simulates a continuous optical flux ring. All the zones are concentric with the central axis of the reactor process chamber and the center of the semiconductor wafer. The multi-zone lamp module heats the semiconductor wafer via, its backside during face-down wafer processing. Each lamp zone can be controlled independently in real time via its dedicated remote and computer-controlled power supply. Tire lamp design provides multiple hollow light-pipe holes through the illuminator housing and associated reflector assembly for multi-point real-time wafer temperature measurements. The 4-zone lamp module has a single lamp at the center, an inner middle ring of 7 lamps, an outer middle ring of 14 lamps, and an outer ring of 28 lamps (a total
505
54/0.935/1.250:900 sccm H2/0.5 Torr U)
WU
,
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o-,..°°.-...
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.- ------
.
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-
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550-
60 sec 90 sec 180 sec 240 sec 300 sec
I .*
n-
S500 0.0
0.5
1.0
1.5
2.0
2.5
3.0
DISTANCE FROM CENTER (INCHES)
Figure 2: Measured radial temperature profiles on a 150-mm wafer heated in a TIAVP reactor using the 3-zone lamp module. The profiles were obtained with the lamp zone power levels optimized for the best uniformity after 300 sec heating. Various curves show the evolution of radial profile after 60-300 sec into the heating cycle.
of 50 point-source tungsten-halogen lamps). Again, the 4-zone lamp module provides complete cylindrical symmetry. As a result, both the 3-zone and 4-zone lamp modules include capabilities for real-time wafer temperature uniformity control. This feature is very important due to the fact that various RTP fabrication processes are performed over an extended process parameter domain (e.g., 0.25-760 Torr pressure for LPCVD and RTO processes). Recent modeling results have shown that the process pressure and gas flow rates can have significant effects on wafer temperature uniformity, particularly near the wafer edge [4]. Figure 2 shows radial (center-to-top profile perpendicular to the wafer major flat) .emperature profile measurements performed on a 150-mm wafer with 4 bonded thermocouples in a TI-AVP reactor with a 3-zone lamp module. The lamp zone power levels were manually tuned to provide nearly optimum wafer heating 300 sec after turning the lamp zones on. The measurements shown in Fig. 2 were performed while the thermocouple-bonded wafer was in a 0.5 Torr hydrogen ambient (900 sccm flow rate). For this open-loop test, it can be seen that the radial wafer temperature nonuniformity is less than -1*C after 300 sec (the zone power ratios were optimized for good uniformity after 300 sec). The measured data also indicate that the op506
timum zone power ratios depend on the wafer temperature and heating time. The optimum zone power ratios for 300-sec uniformity did not provide optimum temperature uniformity at the initial stage of wafer heating (for instance, see the 60-sec curve which shows the center is somewhat cooler than the edge). These data clearly indicate the advantages of using a multi-zone lamp module (with cylindrical symmetry) along with reliable multi-point wafer temperature sensors. The capabilities of the TI multi-zone RTP lamp systems have been demonstrated for uniform wafer processing and real-time process uniformity control. The improved uniformity performance of the TI-AVP systems with the multi-zone lamp modules have been further confirmed via fabrication processes such as tungsten CVD. MULTI-POINT RTP TEMPERATURE SENSORS RTP applications present stringent requirements for accurate and repeatable realtime control of wafer temperature. Measurement of wafer temperature in RTP reactors is typically done using a noninvasive technique. The most commonly used non-contact, in-situ, temperature measurement technique in semiconductor processing is optical pyrometry. The advantages of optical pyrometry for RTP include, most importantly, its noninvasive nature and relatively fast measurement speed. Both of these requirements are critical for proper control of transient heat-up and cool-down temperature ramps and accurate/repeatable temperature control. The fundamental disadvantage with conventional pyrometry, however, is the dependence of the temperature measurement on the wafer surface and bulk conditions, namely surface roughness and emissivity. Surface roughness is typically wafer dependent, while emissivity depends on a range of parameters, including temperature and chamber reflectivity, as well as wafer doping characteristics and surface optical condition [51-[7I. Further, the direct reflection of heating lamp light from the wafer surface must be eliminated from the pyrometer measurement. Similarly, the heating of any optical chamber windows through which the wafer radiance is monitored, and any ensuing changes in the window index of refraction, must be corrected for in the measured radiance. Without proper compensation, these factors can result in large temperature measurement errors. The above sources of measurement error are very significant, and have not all been fully addressed in conventional pyrometry. Frequent calibrations against thermocouple instrumented wafers have allowed somewhat improved temperature control for a specific process/reactor, but are not satisfactory in general. Efforts are underway to allow proper correction for each of the above. As will be described here, pre-process measurement of wafer reflectance and backside roughness may be used to correct for wafer-to-wafer changes in surface optical conditions. The use of preprocess wafer reflectance measurements has been reported for improved pyrometry 507
PYROMETEl
Figure 3: Schematic diagram of 2-point temperature measurement and control on a 3-zone lamp-heated RTP reactor. measurements [8]. Real-time, in-situ, wafer emissivity measurement is being developed to allow correction for emissivity changes. Schemes for elimination of direct lamp light measurement have been used on commercial systems*, and techniques that allow independent window temperature measurement, in the far Infrared, are being developed. Aside from the above issues affecting pyrometry measurement accuracy and repeatability, wafer temperature uniformity is a key requirement to prevent slip dislocations in high-temperature RTP (2]. Multi-point fiber-optic pyrometry applications are being developed to allow real-time monitoring and control of wafer temperature using multi-zone lamp heat sources. The temperature sensor technology developed in this work based on multi-point fiber-optic pyrometric temperature measurement/control, and real-time, in-situ, emissivity monitoring is presented below. Concurrent work is underway on backside roughness measurement, lamp interference elimination, and window temperature measurement. Detailed data on these techniques will be published elsewhere. Figure 3 is a schematic diagram of a typical 2-point temperature measurement and Texas Instruments, Dallas, TX # Accufiber, Beaverton, OR. 508
cr
o'
DET
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COOLING WATER SUPPLY
Figure 4: Detail of a water-cooled light pipe, filter, and pyrometer assembly.
PID control on the 3-zone lamp-heated single-wafer TI-AVP reactors. The wafer is processed face-down to minimize particulate deposition on the device side. A 3-zone, 37 kW, tungsten-halogen lamp source provides radiant heating to the wafer backside. A quartz window provides a vacuum seal, and allows for optical access to the wafer. Two pyrometers are arranged, as shown, at two radial positions, each looking at the wafer backside through a 3.3 ptm interference filter, and a suitable light pipe. The light pipe is water cooled to prevent excessive heating due to reflection and radiation from the hot wafer. The pyrometer/light pipe assembly detail is shown in Fig. 4. The light pipe material used for 3.3 pm transmission is either a sapphire rod or a fluoride fiber bundle. The temperature of the water-cooled light-pipe tip, facing the wafer, is maintained at less than 80'C for a wafer temperature up to around 800"C. The temperature readout from each pyrometer is relayed to the process equipment, as shown in Fig. 3, with the process computer providing a temperature set-point to the PID control equipment. Any corrections for surface roughness, emissivity, lamp interference, or window temperature, (hardware not shown in the diagram), are then used to modify the pyrometer temperature reading, supply it to internal hardware PID controllers, and generate necessary power control outputs to be relayed to the lamp power supplies, as shown. The real-time, in-situ, emissivity measurement system is shown in Fig. 5. This technique involves the use of a chopped CO laser beam, at 5.4 um, to probe the wafer 509
REFLECTED
CO LASER
TWFAM
DETECTOR
INCIDENT BEAM DETECTOR
CHALCOGENIDE FIBER BUNDLE
REACTOR WINDOV
WAFER
Figure 5: Schematic of a 5.4 Im laser-based emissivity and temperature measurement system, using chalcogenide IR fiber.
backside surface during processing. This wavelength was chosen to eliminate, the measurement of reflected lamp light, since the quartz jackets of the tungsten-halogen lamp bulbs provide a necessary cutoff of direct filament light at above 3.5 gtm. The incident laser beam power is measured using a ZnSe beam splitter and an infrared (IR) detector, as shown in Fig. 5. The light transmitted through the beam splitter is then focused onto a 600 im (diameter) single chalcogenide fiber, and transmitted to the probe tip at the wafer end. Light that leaves the fiber tip and is transmitted through the chamber window, arrives at the wafer. The chamber window is typically fused quartz which has a small thermal expansion coefficient. The window material where the 5.4 Im beam is incident, however, needs to be chosen to allow maximum transmission at this wavelength. A thin (1 mm) sapphire section is ideal, given the inertness of sapphire, however, the joining of sapphire to quartz, under these temperature conditions, is not trivial, and is still under development. The light arriving at the wafer surface is partly reflected, absorbed, or transmitted. Since the transmitted portion is essentially eliminated above 600°-700*C, it is neglected here. Additional optical hardware can be arranged to measure the transmitted portion if the operating temperature is sufficiently low. However, the transmission measurements are not required at all if the semiconductor substrates are heavily doped (e.g., P-/P+ epi material used for CMOS/BiCMOS technologies). Therefore, with the transmission 510
neglected, the reflected light is collected via a fiber bundle arrangement at the probe tip, and relayed back to a suitable detector. Spectral wafer emissivity can be extracted based on measurements of the reflected and the incident beam power levels. The reflected beam detector is also used to measure the light emitted by the heated wafer at the 5.4 /Am wavelength, such that radiance and emissivity are measured simultaneously, allowing precise calculation of wafer temperature. It is essential to note that the surface roughness of the wafer backside affects the measurement of the reflected light, since the scattering profile of the reflected light generally depends on the RMS surface roughness. The reflection from a typical wafer backside at 5.4 /tm contains a strong specular component, with a smaller but significant diffuse component. The diffuse component is not measured by the reflection bundle, consequently, a pre-process surface roughness measurement is necessary to provide a ratio of expected diffuse-to-specular reflection (see the following section). Measurements with a non-fiber version of this system were demonstrated to provide ±15% agreement with predicted theoretical results, at 600'C, for a specific set of control wafers [9]. Most of the observed difference may be attributed to possible modeling errors as well as uncertainties in the test wafer surface film characteristics. The present fiber-optic version of the real-time emissivity/temperature measurement system is under development. WAFER SURFACE REFLECTANCE/ROUGHNESS SENSOR A novel in-situ sensor to determine surface roughness, reflectance, and spectral emissivity of silicon wafers with various surface films has been developed. The sensor has been designed for implementation in the vacuum load-lock chambers of SWP reactors. Operation of this in-situ sensor is based on the relation between the surface roughness and the specular and scattered reflection properties of semiconductor wafers for an incident monochromatic electromagnetic wave. Reflection parameters corresponding to the specular and scattered signals are evaluated and the correlation between surface roughness and these parameters is presented. Reflection parameters were obtained for various wafers with films deposited on both the front and backside of silicon substrates including W, TiN, TiSi 2 , SiO 2 and polysilicon films, as well as P- and P+ bare silicon wafers. Significant Optical Parameters of Semiconductor Wafers The optical reflection and transmission properties of semiconductor wafers have important effects on various process variables such as wafer temperature, dynamics of wafer heating/cooling, and fabrication process uniformity in RTP. For instance, knowledge of these properties is required to evaluate substrate emissivity and temperature. Reflection and transmission parameters depend not only on the intrinsic properties of the surface films, but also on the roughness and irregularities present on
511
the wafer surface. Surface roughness may be due to the wafer backside or a polycrystalline film present on the wafer (front-side or backside). Reflection and transmission of wafers with a smooth surface will be essentially specular or coherent. In wafers with a rough surface film (or a rough backside), only a fraction of the reflected signal will be specular; the remaining fraction will be scattered within a space cone angle around the specular direction. The latter will increase as the surface roughness increases (or the light wavelength decreases). Surface roughness can also have an effect on the substrate emissivity and should be taken into consideration in any real-time pyrometry-based temperature sensor. In-situ pre-process/post-process measurement of the surface scattering characteristics and reflection properties of a wafer can be used to monitor its surface roughness and spectral emissivity. An important application of this technique is that measurement of these properties can be used in the real-time determination of the emissivity and temperature of a silicon substrate at different steps during a process flow. Another important application relates to measurements of CVD films on silicon wafers. For instance, it has been shown that surface roughness of LPCVD W films is directly proportional to the film thickness [10]. Thus, an in-situ noninvasive sensor that can evaluate surface roughness and spectral reflectance of semiconductor wafers, can be used as a tool to monitor thickness and quality of LPCVD W (and other polycrystalline films). This can be done both for process control as well as process prognosis/diagnosis purposes. Scattering Sensor: Principle of Operation When an electromagnetic wave impinges on a surface, a fraction of the wave is reflected and the remainder is absorbed and/or transmitted. In turn, a fraction of the reflected signal will be reflected along the specular direction and a portion will be scatter reflected within a confined space angle, 4 o. The scatter reflected signal intensity and the space angle will depend on the surface irregularities or roughness and the signal wavelentgh. If the surface irregularities are much smaller than the signal wavelength, the amount of scattered signal will be very small and the surface will act as a smooth surface. As the wavelength of the signal is reduced, the scatter reflected signal ratio will increase. For a rough surface, the scatter reflected signal, the surface roughness and the signal wavelength can be related by a gaussian distribution as follows [101: R, = R.e 1-',
(1)
where R, and R, are the power reflection coefficient (reflectance) of a rough surface and a polished surface, respectively; ar is the root- mean- square (RMS) surface roughness, no is the index of refraction of the medium where the reflection occurs, (no = 1 for air/vacuum), and A0 is the signal wavelength in air/vacuum. Measurement of the surface reflectance characteristics for a given signal wavelength thus provides a technique to evaluate the RMS surface roughness and spectral emissivity. A sensor 512
was developed to measure the reflected as well as transmitted specular and scattered signals on semiconductor wafers. A simplified version of this in-situ sensor performs only specular and scattered reflectance measurements. A 1.3 Jim laser was used as the source of electromagnetic power. This value is adequate to measure surface roughness values on the order of 10's to 1000's of angstroms, typically found on backsides of silicon wafers and on wafers with different polycrystalline films (such as CVD tungsten) deposited to various thicknesses. Based on the independent measurements of specular and scattered signals, the following coefficients can be defined: Pso, PF,
e4f Scatter Reflected Laser Power Total Reflected Power
Sc,
=
SP,
=- gf
deL Specolar Reflected Laser power
sc
t=
def Scatter Transmtotted Laser Power
-set
ct Spt
=
Total Reflected Power (2)
Total Traostitted Power t
def Specular Transmitted Laser Power -t Total Traonsitted Power
The total reflected and transmitted signal powers (reflectance and transmittance values) can be expressed in terms of these coefficients as follow:
Pact +Ppt
=/
1
Pep,
where Ptne is the incident laser power. The total reflection coefficient, R, and the reflection scattering and specular parameters, Sc, and Sp, = 1 - Sc, respectively, can be used to characterize the surface roughness and spectral emissivity of a silicon substrate, particularly in the case where signal transmission is zero or small (such as in heavily doped P+ wafers). Furthermore, these parameters should vary with the type and thickness of deposited films, and can be evaluated for stacks of films on silicon substrates. The polished side of a silicon wafer is usually expected to show a much smaller value of scattering coefficient (Sc,) than the rough backside. Experimental Results A group of test wafers with different films deposited on the front-sides and backsides was fabricated. The process split chart for various test wafers is shown in Table 1. As indicated in the table, up to two films were deposited on each side. The deposited films include polysilicon, SiO 2, TiSi 2, and TiN. In all cases, the film indicated as #2 was deposited on top of film #1. Additional tests were performed on P+ and P- bare silicon wafers, W-coated wafers and an aluminum-coated sapphire mirror. These additional substrates were labeled as indicated in Table 2. Figure 6 513
Table 1: Split chart of front-side and backside surface films for the test silicon wafers.
shows the reflection coefficient, R, for the front or polished side and the back or rough side of the silicon substrates. As expected, in all cases, R is greater for the polished side than for the rough side. Figure 7 shows the scattering parameter, Sc,, for the backside and the specular parameter, Sp,, for the frontside of the substrates. As can be seen the scattering and specular parameters are sensitive to a change in film type and thickness. These types of reflectance and scattering parameter measurements can be done in situ (preprocess and post-process) in order to fully characterize the optical properties of semiconductor wafers for real-time emissivity compensation and precise multi-point wafer temperature measurements. Tests have also been performed on CVD tungsten films.
Table 2: Additional test wafers used for scattering sensor measurements. Substrate: Number I Type 26 P27
P+
28 29
W-on-silicon Mirror
514
]
TOTAL REFLECTION PARAMETER
WAFER #
Figure 6: Measured total reflectance vs test wafer number for the polished device sides and rough backsides of various test wafers. The results indicate the potential of this scattering sensor for CVD tungsten surface reflectance, roughness, and thickness uniformity characterizations. Thus, measurement of the total reflectivity, as well as the scattering and specular parameters can be correlated to surface roughness and spectral emissivity of silicon substrates with various surface films. These parameters were found to depend on the type and thickness of films on both the frontside and backside of these substrates. The variation of these parameters indicates that the emissivity of these substrates will vary depending on the substrate conditions. METAL SHEET RESISTANCE & PROCESS END-POINT SENSOR Wafer-to-wafer repeatability of CVD processes, particularly CVD metal processes is of primary concern in ULSI manufacturing. Due to the nature of such processes, to date there has been no widely accepted noninvasive real-time technique to monitor the deposition of metal films in situ during wafer processing. In this section, a sensor device is described which has been demonstrated to perform this function with a high degree of accuracy and reliability. A variation of the well-known four-point probe technique commonly used to measure metal film sheet resistances ex situ has been employed to measure the mean sheet 515
REFLECTED SCATTERING AND SPECULAR PARAMETERS
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(Rough)
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Figure 7: Measured scattering and specular parameters vs test wafer number for the polished device sides and rough backsides of various test wafers. resistance of blanket metal films across the entire wafer during metal CVD. These measurements are used to determine the deposition process end-point, thus improving wafer-to-wafer repeatability compared to standard timed process end-points. This method is especially useful if variability exists in the initial nucleation layers (e.g., TiN or TiW) from wafer to wafer. This method differs from four-point probe measurements in that the driving current is passed between the same probe points across which the voltage drop is measured. Hence, the name "two-point probe." As the current is passing through the voltage measurement probes, there is an inherent contact potential between the probe and the measurement surface. This technique is viable only if this contact potential is repeatable enough to be accounted for in the conversion algorithm. Extensive experimentation indicates that this is indeed the case. Experimental Results A linear relationship between the mean (room temperature) sheet resistance and the voltage drop across the blanket metal film has been empirically derived for a steady current flow: V, = AxR~h + B, 516
(4)
0
Response at 450 C
Vp
0.08
0.12
0.16
0.2 Re (O,n)
0.24
0.28
Figure 8: Two-point probe voltage at 4500C vs the mean room-temperature tungsten sheet resistance. where V, is the measured probe voltage, RAh is the mean room-temperature sheet resistance, and A and B are coefficients derived through standard linear regression. Excellent agreement with experimental results has been achieved for CVD-W films, with correlation coefficients of R 2 = 0.999. This agreement continues to hold even at elevated temperatures. An example of this is given in Fig. 8. The probe voltage at 4500C is plotted versus the mean roomtemperature sheet resistance. The temperature was measured with a thermocouple in contact with the wafer surface. The mean sheet resistances were measured with a Prometrix Omnimap set for 49-point measurements. Six wafers were used with CVDW films ranging from 80 mfl/O to 280 ml2/fl. Each wafer was cycled through a lampbased TI-AVP system three times, and twelve measurements were taken in each of the three cycles. The graph implies that much of the variability for a particular wafer may be due to a lack of repeatability with the lift-pin thermocouple measurements. Several plots similar to Fig. 8 have been made at different temperatures, revealing a relationship between the linear coefficients, (A and B), and temperature. Figure 9 shows this relationship over a temperature span from 3900 to 430'C. Clearly, it also follows a linear relationship. This is to be expected, as metal resistances are known to change linearly with temperature, but such relationships are only well known for most metals over lower temperature regimes. A similiar relation is found to exist for 517
Coefficient (V/0,Lu) 0.78
0.77
0.76
0.76
0.74
390
400
410
420
430
Temperature (0C)
Figure 9: Linear coefficient for the two-point probe response vs tungsten deposition temperature. the contact potential, B, although the temperature effect on B is less dramatic. Thus, the response of the probe may be characterized over a range of temperatures. The original linear relationship is then modified: V, = A(T)xRh + B(T),
(5)
where A(T) and B(T) are now linear functions of temperature. This underscores the importance of accurate temperature measurement for taking full advantage of this technique. However, initial results indicate that the sensor provides a much more repeatable end-point than a timed CVD process end-point even with a rather unreliable lift-pin thermocouple used for closed-loop PID temperature control. One significant problem encountered in practice was related to the effect of contacting metal pins with the wafer edge surface during the deposition process. There is a shadowing effect if the 0.8-mm diameter probe is kept in contact with the wafer edge during the entire process. The probe acts as a heat sink at that location inhibiting tungsten nucleation, and also acts as a physical shadow. To overcome this effect, the probe is retracted from contact with the wafer when measurements are not being taken, especially at the beginning of the process when nucleation is taking place. Measurements may then be taken at various points during the process, indicating when the desired process end-point is near. At this time, the probes are finally 518
extended to measure the exact CVD process end-point, with negligible disturbance to the wafer. The initial experiments utilizing this technique for CVD process end-pointing have been successful, resulting in improved wafer-to-wafer repeatability by a factor of four over the conventional timed end-pointing technique. The effect on more stable processes should also be significant, although somewhat less dramatic. Again, this sensor has proven to be especially useful if the nucleation layers are less repeatable than may be desirable, or for experimental CVD processes (including other metal processes besides tungsten). It is also effective for process prognosis/diagnosis providing real-time information about the deposition rate. PROCESS APPLICATIONS OF ADVANCED RTP: RTO AND LPCVD The RTP equipment and sensor technologies described in this paper have been employed for numerous CMOS-related device fabrication processes. These include rapid thermal oxidation (RTO) for CMOS gate dielectrics, rapid thermal annealing (RTA) of ion-implanted wafers, silicidation, low-pressure chemical-vapor deposition (LPCVD) processes for tungsten, amorphous and polycrystalline silicon, lowtemperature in-situ surface cleaning, and single-wafer epitaxy. The following sections present some examples related to process uniformity and kinetics using advanced multi-zone RTP systems. Tungsten LPCVD The TI-AVP reactor with a 3-zone lamp module has been employed for uniform LPCVD tungsten processing. Figure 10 shows two CVD tungsten sheet resistance uniformity maps measured on 150-mm wafers. These processes were performed on wafers with thin sputtered TiW layers (on oxide-coated Si) using 900 sccm of H 2 and 40 sccsn of WF 6 for 60 sec. The deposition pressures were either 376 mTorr or 8 Torr. With some manual tuning, the one-sigma sheet resistance nonuniformities were 3.7% and 4.5% for the low-pressure and high-pressure processes, respectively. These nonuniformities can be improved by further optimization of the lamp power ratios. The above-mentioned depositions included an initial pre-heating cycle for 3 min in hydrogen (at the desired process pressure) before the WF, flow was initiated. The pre-heating cycle was used in order to allow wafer temperature stability during these open-loop runs. These depositions did not result in any backside tungsten deposition. These tungsten deposition results were obtained without the use of a SiC-coated graphite heat-shield ring. Subsequent experiments have indicated that the use of a heat-shield ring provides further flexibility for dynamic wafer temperature uniformity control in the multi-zone RTP reactors.
519
LPCVD TUNGSTEN USING 3.Z ,NE/37 KW AVP ILLUMINATOR X.HIG-IPRESSURE (I TORR) PROCESS
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Rapid Thermal Oxidation for CMOS Gate Dielectrics Rapid thermal oxidation of silicon based on RTP has proven effective for growth of high-quality sub-100 A gate dielectrics [111. Growth of thin (75-150 A) gate oxides usually require RTO temperatures in the range of 1000'-1100'C. The hightemperature RTO processes demand stringent closed-loop wafer temperature and uniformity control to meet process repeatability and slip dislocation density specifications. Conventional RTP techniques with single-zone lamp heat sources have known limitations in terms of dynamic process uniformity control and generation of slip dislocation lines caused by wafer temperature nonuniformities [2]. As a result, this work was conducted based on a load-locked TI-AVP reactor using a 91-lamp heat source developed by G-Squared Semiconductor. The lamp assembly consists of 91 individually controllable tungsten-halogen lamps in an array. In this system, the lamps are computer controlled in eleven radial zones. The outer three zones are outside the radius of the 150-mm wafer and heat a SiC-coated graphite annular heatshield ring which is situated just above the plane of the wafer. This ring serves as an adjustable source of radiation for the wafer edge. The wafer sits on three pins which are rotated through a magnetic coupling to the outside of the process chamber. The rotation affords good circular symmetry of wafer heating if the support pins 520
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Figure 11: Measured radial thickness profile for an oxide layer grown on a 150-mm wafer. The measured profile yields a one-sigma radial thickness nonuniformity of 0.6%. are carefully designed to avoid heat transfer with the wafer. The radial temperature profile is fully controllable by adjustment of the intensity of the radial lamp zones. To characterize the temperature uniformity, oxides were grown in dry 02. Figure 11 shows ellipsometric measurement of oxide thickness along the radius of a wafer. A one-sigma radial oxide thickness nonuniformity of 0.6% was obtained by lamp zone tuning. The overall temperature is governed by a PID controller receiving feedback from an optical pyrometer looking at the center of the wafer. The system has provision for additional pyrometers which will look at the outer zones of the wafer and adjust the lamp zones for real-time temperature uniformity control. Polysilicon- gate metal-oxide- semiconductor (MOS) capacitors were fabricated with 90 A gate oxides grown in the RTO TI-AVP system (with a G-Squared lamp module) at 1000°C. Ramped-voltage breakdown tests were run on capacitors with an area of 0.02 cm 2 . Figure 12 is a normal cumulative probability plot of breakdowns. When these devices were fabricated, the lamp zones had not been tuned for optimum across-the-wafer temperature uniformity. The spread in breakdown voltages above seven volts can be correlated to the oxide thickness variation. The early breakdowns are attributed to particle contamination which had not yet been minimized in the RIO TI-AVP equipment. The average breakdown field of the non-defective distribu521
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Figure 12: The cumulative breakdown distribution plot for MOS capacitors with 90 RTO gate oxides.
A
tion is over 10 MV/cm. Quasi-static and high-frequency C-V and bias-temperature stress tests for these oxides all gave electrical properties equivalent to control batch furnace oxides.
Single-Wafer LPCVD for Amorphous and Polycrystalline Silicon The single-wafer TI-AVP reactor used for the LPCVD of amorphous and polycrystalline silicon was fitted with a G-Squared multi-zone lamp module for heating wafers. The lamps were controlled by a very versatile system that allowed tuning of lamp power to any area of the wafer. In addition, wafer rotation was employed during depositions to further enhance temperature and process uniformities. The gas distribution system of the reactor consisted of mass-flow controllers for SiH 2 Cl2 , SiH 4 , HC1, HF, 112, and a mixture of H 2 and GeH4. The HF and GeH 4 gases were used for removal of native oxide layers prior to silicon depositions. The reaction gases were introduced into the chamber through a reflective water-cooled showerhead located beneath the wafer which is held in a face-down manner. Spent gases were removed downward around the periphery of the wafer. A purge flow of H2 was maintained on the back of the wafer at a high enough rate to prevent the reactive gases from reaching the backside. 522
SILICON DEPOSITION KINETICS USING SILANE (p=15 Torr, 500 sccm SIH4, 10/15 sim H2) 1000 z
uJ I-
z 0 0
a. U1 1.04
1.12
1.08
1.16
1000/[T(°K)] Figure 13: LPCVD Si deposition rate vs inverse temperature at 15 Tort. The ability to carefully control temperature across the wafers was of great help in maintaining thickness control of amorphous or polysilicon depositions, but it was discovered that other factors such as pressure, backside purge, and showerhead hole patterns also affected thickness uniformity significantly. A series of depositions were performed at a pressure of 15 Torr, 500 sccm SiH 4 flow, 10 slm process H2 flow, and 15 slm purge H2 flow. The deposition time was fixed at 5 minutes and runs were 0 made at 5900, 6200, 6500, and 680 C. Results of the deposition rate are shown in Fig. 13. For the region of the curve between 6500 and 680°C the observed activation energy is 0.54 eV, and for the region between 5900 and 620°C it is 1.07 eV. Runs were also made under various conditions to study the conformality of depoof sitions made over patterns opened in 13000 A TEOS oxide deposited on 1000 thermal oxide. An example of the results obtained is shown in Fig. 14. Figure 14(a) shows a cross section of a wafer that received a deposition of about 2000 A of amorphous silicon at 590°C, 15 Torr, 500 sccm SiR 4 , and 10 slm H2 . The backside wafer H2 purge flow rate was 15 slm. Excellent conformality (100%) is shown for an opening about 0.7 Am wide. Figure 14(b) shows the complete filling of a 1.2 pm wide opening with a 6000 A deposition. There is some taper on the sides of the trench, but there is no evidence of voids between the two sidewalls.
A
As can be seen in these photographs, there is evidence of some roughness/pits on the surface of the deposited layer. Figure 15 shows the effect of introducing a 523
8214-01
30 Sees 80
(a)
(b)
Figure 14: Cross-sectional SEM micrographs of patterned wafers after LPCVD Si processes performed at 590'C (with SEM contrast enhancement etch). 524
one-minute nucleation deposition at 520'C prior to the deposition of the remaining portion of the layer. The wafer shown in Fig. 15(a) did not have the initial 60 sec nucleation step, while the one shown in Fig. 15(b) did. Although the surface is still not entirely smooth, definite improvement can be seen. The "etch" label indicated on the photographs refers to an etch that was used on the wafers to highlight the interface between the oxide and the silicon. To test the possibility of using GeH 4 to remove the native oxide prior to amorphous Si deposition, or as a low-temperature pre-epitaxial native oxide clean-up, a series of runs were made on wafers that had been prepared as follows: (i) Growth of 1000 A of thermal oxide; (ii) deposition of 3000 A polysilicon; (iii) growth of approximately 15 A chemical oxide using a mixture of H202 and H2S04 at 60CC; (iv) in-situ cleaning at temperatures of 6500, 7000, and 7500C, pressures of 8 and 20 Torr, and 0.5% GeH 4/99.5% H2 flows of 30 and 90 sccm (also, with a chamber H2 flow of 10 slm); (v) deposition of a second LPCVD Si layer, approximately 3000 A thick. The wafers were then put into a plasma etch reactor for selective silicon etch. A system utilizing a laser and a detector capable of recognizing changes in interference was available on the reactor. The detector was able to distinguish whether or not the oxide between the two poly layers was still present. An easily discernible change in the signal obtained indicated the presence or absence of the thin chemical native oxide grown in step (iii) above. At a temperature of 7500C, a pressure of 20 Torr, and a GeH 4 /H 2 flow of 90 sccm, no oxide was observed at the interface of the two silicon layers. The test was repeated with the same results. Evidently, the specified conditions were very near the threshold where etching of the native oxide was initiated. Runs made at lower temperatures, lower pressures, and lower GeH4/H2 flows did not indicate the complete removal of the native oxide (although partial removal was observed). SUMMARY In summary, advanced single-wafer RTP equipment and sensor technologies have been developed for semiconductor device manufacturing applications. The use of multi-zone cylindrically symmetrical lamp modules along with improved fiber-optic multi-point temperature sensors provide excellent capabilities for real-time dynamic RTP uniformity and process control. Additional in-situ sensors were shown to enhance real-time RTP control and process end-point detection. These new advancements are considered essential for use of single-wafer RTP techniques as viable and superior alternatives to batch processing in semiconductor factories. ACKNOWLEDGEMENT This work was supported in part by the U.S. Air Force and DARPA under the Microelectronics Manufacturing Science and Technology (MMST) contract number 525
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X30,000
IPM W015
Figure 15: SEM micrographs of wafers exposed to (a) one-step, and (b) two-step amorphous silicon LPCVD processes. 526
F33615-88-C-5448. The authors are grateful to Sam Gibbs, Robert Matthews, Brent Jones, Dwain Jakubik, Marlin Launius, Steven Henck, Fred Vaughan, Helen Simon, and Blondell Lewis for their experimental assistance.
References [1[ Rapid Thermal and Related Processing Techniques, R. Singh and M. M. Moslehi, Editors, Proc. SPIE 1393, (1991). [2] M. M. Moslehi, IEEE Trans. on Semiconductor Mfg., 2, 130 (1989). [3[ R. S. Gyurcsik, T. J. Riley, and F. Y. Sorrell, IEEE Trans. on Semiconductor Mfg., 4 (1), 9 (1991). [4] S. Campbell, K. Knutson, K. Ahn, J. Leighton, and B. Liu, IEDM Tech. Dig., 921 (1990).
[51 F. Sorrel, SRC workshop on temperature meas., Santa Fe, New Mexico, Feb. (1990). [6[ J. Nulman, B. Cohen, W. Blonigan, S. Antonio, R. Meinecke, and A. Gat, MRS Symp. Proc., 146, 461 (1989). [7] T. Sato, Jpn. J. Apple. Phys., 6, 339 (1967). [8] J. Gelpey and J. Liao, SRC workshop on temperature meas., Santa Fe, New Mexico, Feb. (1990). [9] M. Moslehi, R. Chapman, M. Wong, A. Paranjpe, H. Najm, J. Kuehne, R. Yeakley, and C. Davis, IEEE Trans. on Electron Devices (submitted for publication), (Dec. 1991). [10] T. Kamins, D. Bradbury, T. Cass, S. Laderman, and G. Reid, J. Electrochem. Soc., 131, 2555 (1986). [11] M. M. Moslehi, S. C. Shatas, K. C. Saraswat, and J. D. Meindl, IEEE Trans. on Electron Devices, ED-34 (6), 1407 (1987).
527
REVIEW OF PROCESS AND EQUIPMENT ISSUES IN RTP J.J. Wortman*, J.R. Hauser*, M.C. Ozturk* and F.Y. Sorrell** *Department of Electrical and Computer Engineering Box 7911, Raleigh, NC 27695-7911 "**Departmentof Mechanical and Aerospace Engineering Box 7960, Raleigh, NC 27695-7911 Rapid thermal processors are currently being considered for a variety of silicon processing applications. A number of potential design approaches are discussed along with their potential use in rapid thermal processes. Temperature measurement is discussed and equipment design issues that are of concern in rapid thermal processors are considered.
INTRODUCTION Rapid thermal processing (RTP) is currently being considered for a variety of single wafer applications from simple annealing to low pressure chemical vapor deposition. An extensive review (with over 500 references) of the subject has been given by Singh [1] for work prior to 1987. Annealing is by far the most common use of RTP tools today. The primary requirement placed on an RTP system used for annealing is that the wafer be heated, annealed and cooled in such a way that the wafer temperature is kept uniform. Temperature measurement and control over the environment are important, but not as important as wafer uniformity so long as repeatability is possible. For example, the annealing of radiation damage from an ion implanted wafer is far less demanding than growing a thin gate oxide for an MOS transistor. Consequently, early RTP annealers used simple quartz chambers heated with quartz halogen lamps with minimal control of temperature. Early annealers utilized thermocouples mounted into semiconductor chips placed near the wafer to monitor and control the temperature. As more confidence was gained in the use of RTP systems new concepts for wafer heating were forthcoming which included the use of single tube arc lamps and heated carbon radiators. The carbon radiator isolated by a shutter proved to be difficult to control and was abandoned. Wilson, et al. [2] has given an overview of processing equipment covering advances to 1986. Hill, et al. has considered the use of RTP systems along with some of the theory of RTP systems [3]. A more recent review by Roozeboum and Parebk [4] highlights the basic principles of RTP systems and emphasizes temperature control. Ozturk, et al. [5] have also addressed manufacturability issues in RTP systems with an emphasis on chemical vapor deposition. The following is a summary of some basic issues related to equipment and to temperature measurement which is an inseparable issue from equipment in RTP use.
528
Temperature measurement has evolved over the years from the use of thermocouples to the use of pyrometers including multicolor pyrometers and multiple pyrometers. The pyrometers are usually calibrated by monitoring a test wafer with an imbedded thermocouple. To properly utilize a pyrometer one must first know the emissivity of the surface of the sample being viewed. Secondly, one must know or at least be able to account for the loss of radiation in the optics including the losses and radiation from the windows of the RTP chamber. Third, and finally, one must either have a pyrometer whose spectral range is outside of the lamp spectra or in some method account for the direct radiation from the lamp or lamps. These problems are compounded by the fact that the radiation inside a processor reflects from almost all directions. In fact, most of the working chambers are designed so that maximum reflection is achieved to help with the uniformity problems. Consider first the emissivity problem. The emissivity of Si has been measured [6], and is shown in Figure 1. As shown even for pure intrinsic Si the emissivity is a strong function of both wavelength and temperature. It is obvious from Figure 1 that the problem of emissivity correction is very difficult at low temperatures. The problem becomes much more complex when one deposits layers of different materials on the wafer. See Figure 2, for example, where polysilicon is deposited on an SiO% layer which has been grown on Si [5]. As shown, the theoretical emissivity is a strong function of not only the thickness of the polysilicon but also the Si0 2 thickness. Chamber reflectance also has a similar and significant effect, as shown in Figure 3 for data taken in our laboratories on the emissivity as a function of polycrystalline thickness which is deposited on 1000 A of SiOC. The curves are for the theoretical model and the circles are actual data points. Note that chamber reflectance actually improves the situation. At first glance, it might be thought that if one uses more than one pyrometer with different wavelengths then the problem can be solved. However, it has been shown that this is not the case unless there is an accurate emissivity model. If one has 0.8
z!600 IC
S520 S470
0.6
S0.4 0.2
II III
i
I
I
I
I420
0 0.5
1.0
5.0
100,
15.0
WAVELENGTH (tm)
Figure 1.
Emissivity of silicon as a function of wavelength at different temperatures.
529
1.0
0.8
0.6
0.4
0.2
0.0
0.1
0.2
0.3
0.4
0.5
0.6
POLYSILICON THICKNESS (gim)
Figure 2.
Calculated emissivity of a polysilicon/SiO 2Si three-layer structure as a function of polysilicon thickness for four different SiO2 thicknesses of 200, 500, 1000 and 4500 A.
an accurate model for the wavelength dependence of emissivity, say as a function of polysilicon thickness, then two color pyrometry will greatly help in determining the emissivity. This subject has been treated by DeWitt, et al. [7]. Ozturk has shown that the wavelength of the pyrometer can have a significant effect on the error in the temperature one can expect due to an error in the emissivity [5]. He has shown that the shorter the wavelength the less the error in a process that depends exponentially on temperature as is the case for most semiconductor processes.
0
0.1
0.2
0.3
0.4
0.5
FILM THICKNESS_ (,m)
Figure 3.
Effect of chamber reflectance on emissivity of a polysilicon/oxide/Si structure.
530
C-, 0~ o,-
U1 I-
POLY SILICON THICKNESS, MICRONS
Figure 4.
Temperature as a function of polysilicon thickness for polysilicon deposited on 1000 A of SiO2 on an RTP system operated at a constant power.
One cannot simply avoid the problem by operating the heater so that a constant power is supplied to the RTP system. Figure 4 shows how the temperature of a wafer will vary as polycrystalline silicon is deposited on 1000 A of silicon dioxide at constant incident power. Note the large swing in temperature that results from the emissivity changes as the polycrystalline silicon is deposited. In summary, it is very difficult to accurately measure and to model the changing emissivity for say a chemical vapor deposition process involving different layers of materials to be carried out in an RTP system. On the other hand, processes such as annealing and the growth of thin oxides, or the deposition of polycrystalline Si, or the growth of epitaxy is much less complicated and can usually be handled effectively by careful calibration using a thermocouple. Here the calibration must be made on a wafer which is exactly like the wafer to be produced but one that has a thermocouple mounted in it. It should be noted in passing that the best technology available today from commercial vendors is + 3YC for thermocouples mounted in Si. A common pitfall is that thermocouples are often mounted in Si wafers that have an oxide grown for protection. The surface roughness of the wafer has a significant influence on the emissivity of a wafer. It may be necessary to measure this roughness for each wafer and to use some sort of model or look-up table to handle these effects on emissivity. Several equipment manufacturers provide such a system with their processors.
531
Turning to the problem of absorption by the windows and radiation by the windows or walls of RTP systems and its affect on pyrometer readings, one finds that these are more manageable problems. One can simply employ a second pyrometer to measure the radiation from a heated chamber window. This has been done by several vendors in their equipment. The best solution, if possible, is to simply keep the windows cool. This is necessary if a chemical reaction is involved, otherwise there will be deposits on the window. Absorption in the windows can usually be accounted for through calibration since this is usually a constant. The question of overlap between the lamp spectra and the detector of the pyrometer is straight forward. The problem comes in when one considers the transmission of the radiation through the walls or windows of the RTP chamber. The lamp spectra is essentially fixed into one of two possibilities - that resulting from quartz halogen lamps or that resulting from arc lamps. This choice is made at the design level and is fixed thereafter. Arc lamps give high power densities at lower wavelengths and hence one can use detectors with shorter wavelengths without contaminating the pyrometer reading. "Trade-offs" are possible with the primary limitation, being the inability to use long wavelength detectors due to absorption in quartz windows. Practically it is not easy to seal a different window material to a quartz tube. A number of ideas are currently being considered to aid remote temperature measurement. Principal among these are the use of ellipsometry, laser reflectance to measure the emissivity, and a new concept being studied by the present authors which utilizes some of the direct radiation from the sample to reflect back onto the sample after being chopped to get a measure of the reflectance. Other techniques being studied are Raman scattering and measurement of thermal expansion using laser interferometry. There has been much progress to date. The first step already behind us being the understanding of the problem. There is every reason to believe that continued progress will be made. Meanwhile known recipes coupled with reproduceability are capable of making RTP a reality for most applications including CVD. The future requirement of CVD using RTP systems imposes the additional requirements of cold wafts (especially if in-situ processing is to become viable) and low pressure. These two requirements are somewhat contradictory in that to sustain a one atmosphere pressure differential across the window of an RTP system requires approximately a 0.5" window thickness for quartz in a flat plate configuration [5]. The result is that it becomes very difficult to keep the inside of the window cold since the window is heated to some extent by the direct lamp radiation, the reflected radiation and the radiation from the wafer itself. Even if the outside of the window is kept at or below room temperature the inside may become hot enough to crack a reactant gas and cause deposition on the window of an RTCVD system.
532
reflectors
FM
0000000
Quartz Tube
Figure 5.
Three generic lamp configurations for RTP systems.
There are a number of chamber design alternatives. Three generic designs are shown in Figure 5. The challenge is to heat the wafer in such a manner that it matches the non-uniform radiation from the wafer. The radiation from the wafer is greatest at the edges, and hence the need to supply more heat to the edges. Another challenge is to keep the wafer temperature uniform during heat up and cool down. If this is not done one can easily produce slip at elevated temperatures. Different manufacturers use different methods to produce a radiation intensity profile that will produce the uniformity needed. This ranges in rectangular systems from the creative use of reflectors and absorbers to controlling individual lamp intensities to rotating the wafer. Obviously a system that has symmetry with the wafer is desirable. To date no one has come up with circular lamps. However, there is one design on the market that utilizes a circular array of individual point lamps. We have developed thermal models for some of the configurations [8]. As a result we have found that almost any design approach can be made to work to some extent provided one carefully chooses the parameters such as reflector placement, lamp placement, lamp currents, etc. We believe the uniformity problem to be one of engineering and is solvable, especially if one does not have to use the same design for all applications. We expect to see significant improvements in equipment during the next few years.
533
PROCESS ISSUES Much work has been published related to RTCVD [9]. However, for brevity, work in our laboratories will be discussed as examples of RTCVD applications. We have used a LEISKT' rapid thermal processor designed to operate at reduced pressure. The system has a water cooled, stainless steel process chamber with quartz windows. The chamber is designed to accommodate wafers up to 6" diameter. The low pressure is maintained by a mechanical pump which can provide a base pressure of approximately 10 mTorr. The wafer is heated by two banks of tungsten halogen lamps located on each side of the process chamber with the upper bank rotated 90 degrees relative to the lower bank, allowing for intensity contouring in x- and y- directions to reduce temperature gradients across the wafer. There are 15 lamps (1.5 kW each), upper and lower bank combined, giving a total lamp power of 22.5 kW. Curved reflectors behind the lamps help to focus the lamp radiation on the wafer. The temperature is monitored by an optical pyrometer (3.5 - 4.1 Am) focused at the center of the wafer. Unfortunately, the existing chemical processes developed for conventional systems are not necessarily applicable to single-wafer manufacturing via cold-wall, lamp heated rapid thermal processors. We will discuss three processes below: polysilicon, silicon dioxide and silicon nitride. Polysilicon, silicon nitride and silicon dioxide were chosed because these are the most commonly used thin films in silicon based integrated cirucit fabrication technolgies. Other thin films of potential interest include Si and Si/Ge epitaxial layers, metals (e.g. tungsten, aluminum) and deposited silicides (e.g WSi 2 , TiSi2 ). As an example, polycrystalline silicon has a variety of applications in microelectronics. Polysilicon is normally deposited by pyrolysis of SiH 4 in hot-wall allquartz furnaces at reduced pressure and at temperatures around 600-650*C [10]. In this temperature range, a deposition rate of 100-200 A/min can be obtained. To meet the throughput requirements of single-wafer manufacturing, higher deposition rates are needed. The simplest way of achieving higher rates is to increase the deposition temperature [11]. Figure 6 shows the temperature dependence of polysilicon deposition rate obtained in our rapid thermal processor described above using 10.3% SI-I4 diluted in Ar as the source gas. , Depositions were performed on 4" wafers with 1000A thermally grown oxide. The oxide grown on the rough backside where the pyrometer measures the wafer radiation was completely etched in order to deposit poly-Si on Si. This was done in order to minimize the temperature measurement error due to significant changes in the optical properties of the rough wafer backside which would normally exist with a three layer polysilicon/oxide/silicon structure. Below approximately 780°C, the deposition appears to be surface-reaction limited with an apparent activation energy of 39.2 Kcal/ mole which is typical for polycrystalline silicon deposition from silane in conventional LPCVD furnaces [12][13]. A decrease in the activation energy is observed above 780*C which shows a transition from a surface reaction limited process to a mass transport limited process. The decrease in the
534
Temperature ('C) 9M0
800
7M0
600
10, mass tumsmort,
i0J
E
104 10
S104 o S103 O
102 •• *~102 0 0L JIn
1N
0.8
0.9
1.0
1.1
1.2
1000/T(°K) Figure 6.
Temperature dependance of the polysilicon deposition rate using 10.3% silane diluted in argon.
activation energy was accompanied by non-uniform deposition along the direction of the gas flow resulting from silane depletion. In this temperature range, a reliable calculation of the deposition rate is not possible since the deposition rate is a strong function of position. The data in Figure 6 show the deposition rate obtained at the center of the wafer. In summary, deposition rates as high as 3000 A/min can be obtained at temperatures below 780'C where the deposition is limited by surface reactions. The next question to be addressed is whether good quality films can be deposited at these elevated temperatures. The electrical and structural properties of the poly-Si films depend strongly on the deposition temperature and therefore, detailed investigations are necessary to evaluate the films deposited at this high temperature regime. One of the important properties of polysilicon which must be considered in evaluating the quality of the films is the surface roughness or the surface morphology, which is an important parameter in fine-line lithography. In addition, the breakdown voltages of oxides grown on polycrystalline silicon films are strongly influenced by the surface roughness [10]. We have studied the temperature dependence of the surface roughness and the details of the experimental results are published elsewhere [11]. Our results show that if the process conditions (temperature and total pressure) are optimized, smooth polycrystalline silicon films can be deposited at temperatures above 7000 C with an RMS surface roughness less than 100 A. This is comparable to the surface roughness of best poly-Si films deposited in conventional furnaces at much
535
lower temperatures and is much less than what one would expect from conventional processes at these elevated temperatures [14][15]. The major difference between the conventional poly-Si furnaces and the RTP systems are that the latter have cold-wall deposition chambers. This difference may strongly affect the quality of the films by minimizing the SiH 4 decomposition in the gas phase since SiH 4 can easily decompose above 400'C. Another possible explanation for the extra smooth films may be the smaller size of grains due to high levels of oxygen in the films found in cold-wall RTCVD reactors [16]. Our results [11] have also shown that poly-Si films deposited by RTCVD techniques at temperatures above 700'C can be heavily doped by ionimplantation for MOS gate applications and using RTA, sheet resistivities comparable to that of conventional poly-Si can be obtained [17][18]. These results are promising and show that good quality poly-Si can be deposited at temperatures high enough to provide the deposition rates suitable to the throughput requirements of single wafer manufacturing. Some processes are simply incompatible with cold-wall RTCVD chambers. A good example is the most commonly used LPCVD silicon nitride process which makes use of the reactive gases dichlorosilane (SiH 2CI2) and ammonia (NH3) as the reactive gases. The problem with this reaction is that one of its byproducts, ammonium chloride (NH4CI), deposits on the cooler areas in the chamber as a white powder and results in clogging of the exhaust flanges and pipes of conventional hot-wall furnaces. In a coldwall RTP chamber, this becomes a major particulate source because it deposits essentially everywhere including the quartz windows and the chamber walls. Therefore, the standard silicon nitride LPCVD process must be replaced with an alternative process which uses a chlorine free source gas such as silane. Johnson, et al. (191 studied RTCVD of Si 3N4 using SiH 4 and NH 3, and have shown that the technique can be used to deposit high quality Si 3N4 films. The disadvantage of the reaction is that at low pressures, radial non-uniformities resulting from gas depletion (bullseye effect) make the process unsuitable to batch processing with closely spaced wafers 1201. However, this problem is not expected to exist in a single-wafer machine and has been confirmed by SiN 4 depositions in our RTP system [19]. We have studied low-pressure RTCVD of Si3N4 using 10.3% SiH 4 diluted in Ar. Figure 7 shows the temperature dependence of Si3N4 obtained using an ammonia to silane ratio of 120:1. This ratio was chosen to obtain stoichiometric silicon nitride films. The activation energy of the process was found to be 47.2 Kcal/mole which is higher than the activation energy of the polysilicon deposition process. On the other hand, the deposition rate of Si3N4 is almost two orders of magnitude lower than the deposition rate of poly-Si. Because of the throughput requirements of single wafer manufacturing, this limits the applications of RTCVD silicon nitride to thin dielectric layers which may have applications in the fabrication of MNOS type memory structures and on gate electrodes as a diffusion barrier. However, thick nitride films may also be necessary in single wafer processes. Therefore, it will be necessary to study processes
536
TEMPERATURE ('C) in~
Z 0
1
850
825
800
775
750
Pressure: 8 Torr Gas :10.3% silane in Arý Ammonia:Silane Ratio = 120:1
•1 .1 0.87
0.92
0.97
(1000/-K)
Figure 7.
Temperature dependance of the silicon nitride deposition rate using 10.3% silane diluted in argon with an ammonia to silane ration of 120:1.
which could enhance the deposition rate of the silicon nitride. This may involve techniques which as photolysis or new source gases instead of silane. Our studies on the electrical properties of the RTCVD nitride have shown that its electrical properties are very similar to the properties of conventional nitride films deposited in conventional furnaces [19]. Another important material used in microelectronics is silicon dioxide (SiO2). In conventional LPCVD furnaces, SiO 2 is deposited by reacting SiH 4 with 02. The reaction takes place below 450'C and results in deposition rates on the order of 100 A/min [21]. Caged boats and special injectors are needed to assure uniform, stoichiometric films. Because of the slow deposition rate and the hardware requirements, the process is not suitable to single wafer manufacturing. One alternative process is the pyrolysis of tetraethylorthosilicate (Si(OC 2H 5)4), also known as TEOS. This process has several advantages over the conventional process such as better electrical properties and step-coverage [22]. In addition, higher deposition rates can be obtained. Until recently, a disadvantage of TEOS was that standard mass-flow controllers could not be used with TEOS mainly due to condensation problems. However, a suitable mass flow controller has recently become available. In this work, TEOS was provided by a SCHUMACHERTM system (Model STC 115), where the vapor is pulled off the top of the liquid into the vacuum without the need for a carrier gas as in bubbler systems. The details of the experimental procedures can be found in
537
Temperature (°C) 900
800
700
S
°u
u-E
0.8
1.0
0.9
1.1
1000IT(OK) Figure 8.
Temperature dependance of the silicon dioxide deposition rate using TEOS.
an earlier publication [23]. Figure 8 shows the temperature dependence of the SiO2 deposition rate at three different pressures. As shown, deposition rates as high as 1000 A/mnin are possible near 800°C. The activation energy calculated using the data shown in Figure 8 (in the lower temperature range) is 76 Kcal/mole. This is higher than the activation energies reported for films deposited in conventional furnaces using carrier gases [22]. As shown in Figure 8, the deposition rate tends to saturate at 800?C. Similar behavior has been observed in conventional furnaces at around 750'C. These differences in the deposition characteristics are believed to be caused by the differences in the TEOS systems (specifically, the absence of the carrier gas in our system) used in these studies. The saturation of the deposition rate at high temperatures is attributed to TEOS depletion and severely affects the thickness uniformity in LPCVD furnaces [22]. In the rapid thermal processor, if the gas depletion is not excessive, uniform depositions can be obtained by individual lamp control and contouring to optimize the radiation profile on the wafer. Nevertheless, as shown in Figure 8, high deposition rates can be achieved before significant depletion effects are observed. Following deposition, it may be necessary to densify the deposited film by annealing the wafer at a temperatures higher than used for deposition. We have used rapid thermal annealing for this purpose and have shown by standard capacitance-voltage measurements that the electrical properties of the deposited films can be improved by annealing, and thick films of sufficient quality for passivation purposes can be deposited [23]. These results show that the existing CVD processes must either be modified or replaced with new processes to meet the throughput requirements of single wafer
538
manufacturing and tool requirements of rapid thermal processing. Polysilcion, silicon nitride and silicon dioxide were chosen because these are the most commonly used thin films in silicon based integrated circuit fabrication technologies. Other thin films of potential interest include Si and Si/Ge epitaxial layers, metals (e.g. tungsten, aluminum)
and deposited silicides (e.g. WSi 2, TiSi2). ACKNOWLEDGMENTS This work has been partially supported by the NSF Engineering Research Centers Program through the Center for Advanced Electronic Materials Processing (Grant CDR8721505) and SRC Manufacturing Sciences Program (Grant 88-MP-132).
REFERENCES [1]
R. Singh, J. Apple. Phys. 63, R59 (1988).
[2]
S. R. Wilson, R. B. Gregory and W. M. Paulson, Mater. Res. Soc. Symp. Proc. 52, 181 (1986).
[3]
C. Hill, S. Jones and D. Doys, Rapid Thermal Annealing - Theory and Practice, Levy Ed. Plenum Press, New York (1989).
[4]
F. Roozeboonand N. Parekh, J. Vac. Sci. Technol. B8, 1249 (1990).
[5]
M. C. Ozturk, F. Y. Sorrell, J. J. Wortman, F. S. Johnson and D. T. Grider, IEEE Transactions on Semiconductor Manufacturing, to be published May 1991.
[6]
T. Sato, Jap. J. Appl. Phys. 6, 339 (1967).
[7]
D. P. DeWitt and G.D. Nutter, Theory and Practice of Radiation Thermometry, (John Wiley and Sons, Inc., New York, NY, 1988).
[8]
F. Y. Sorrell, C. P. Eakes, M. C. Ozturk and J. J. Wortman, Proc. SPIE Symposium Rapid Isothermal Processing, (1989).
[9]
See for example, D. Hodul, J. C. Gelpey, M. L. Green and T. E. Seidel, Eds. Rapid Thermal Annealing/Chemical Vapor Deposition and Integrated Processing, Mater. Res. Soc. Symp. Proc. Vol. 146 (1989).
[10]
T. Kamins, Kluwer Academic Publishers, (1988).
539
[11]
M. C. Ozturk, J. J. Wortman, Y. Zhong, X. Ren, R. M. Miller, F. S. Johnson and D. A. Abercrombie, Proceedings of the MRS Symposium on Rapid Thermal Annealing/Chemical Vapor Deposition and Integrated Processing, Vol. 146. p. 109, (1989).
[12]
G. Harbeke, L. Krausbauer, E. F. Steigmeir, A.E. Widmer, J. Kappert and G. Neugebauer, Journal of the Electrochemical Society, Vo. 131, p. 675, (1984).
[131
F. Hottier and R. Cadoret, Journal of Crystal Growth, Vol. 61, p. 245, (1983).
[14]
D. Foster, A. Learn and T. Kamins, Solid State Technology, p. 227, (1986).
[15]
G. Harbeke, L. Krausbauer, E. F. Steigmeier, A. E. Widmer, H. F. Kappert and G. Neugebauer, Applied Physics Letters, Vol. 42, p. 249, (1983).
[16]
V. Murali, A.T. Wu, L. Dass, M. R. Frost, D. B. Fraser, J. Liao and J. Crowley, Journal of Electronic Materials, Vol. 18(6), p. 731, (1989).
[17]
F. S. Becker, H. Oppolzer, I. Weitzel, H. Eichermuller and H. Schaber, Journal of Applied Physics, Vol. 56, p. 1223, (1984).
[18]
R. Chow and R. A. Powell, Journal of Vacuum Science and Technology, Vo. A3, p. 892, (1985).
[19]
F. S. Johnson, R. M. Miller, M. C. Ozturk and J. J. Wortman, in Proceedings of the MRS Symposium on Rapid Thermal Annealing/Chemical Vapor Deposition and Integrated Processing, Vol. 146, p. 345, (1989).
[20]
R. S. Rosier, Solid State Technology, Vol. 4-77, p. 63, (1977).
[21]
A. C. Adams, VLSI Technology, Sze ed. McGraw-Hill Book Company, (1983).
[22]
F. S. Becker, D. Pawlik, H. Anzinger and A. Spitzer, Journal of Vacuum Science and Technology, Vol. B 5, 1555, (1987).
540
PRINCIPLES OF WAFER TEMPERATURE MEASUREMENT USING IN SITU ELLIPSOMETRY Hisham Z. Massoud,1 Ronald K. Sampson,1 Kevin2 A. Conrad,1'2
Yao-Zhi Hu, 2 and Eugene A. Irene
'Department of Electrical Engineering, Duke University, Durham, N.C. 27706. 2
Department of Chemistry,
University of North Carolina, Chapel Hill, N.C. 27514. ABSTRACT The novel use of in situ automated ellipsometry in silicon wafer temperature measurement is introduced. This method is based on determining the ellipsometric parameters 0 and A from the measured photomultiplier output obtained by reflection from a silicon substrate at any temperature. From b and A, the index of refraction of the silicon substrate (fisi) is then calculated, and the temperature is determined from the strong and known temperature dependence of hisi. The complete knowledge of the optical models of film-free and film-covered silicon substrates at processing temperatures gives this non-contact method many advantages over pyrometers and thermocouples. The influence of experimental parameters such as the light wavelength, the precision of the optical components, the angle of incidence, background radiation, the presence of surface films, and the growth or deposition of surface films will be discussed. INTRODUCTION Temperature measurement and control in single-wafer rapidthermal processing (RTP) systems have suffered to date from the dependence of pyrometry on emissivity and the impracticality of using thermocouples [1-3]. Temperature measurement using in situ ellipsometry is a non-contact method that avoids all the limitations 541
encountered in using thermocouples. It also relies on the well known optical properties and accurate optical models of surfaces, films, and interfaces at all temperatures. It is independent of surface emissivity and, therefore, eliminates all uncertainties associated with optical pyrometry. Even though the measurement of the temperature of a silicon wafer is described in this paper, this technique can be used with all materials whose surfaces are flat, and whose index of refraction is a known strong function of temperature. The use of ellipsometry for temperature measurement has been reported for low-temperature applications in the 30-180'C range for a silicon wafer heated from behind by a plate heater [4], and up to 100°C for a silicon wafer exposed to an rf plasma [5]. In this work, we investigate the use of in situ ellipsometry in the measurement of temperatures of interest in integrated-circuit device processing up to 11000C. THE BASIC TECHNIQUE The process chamber used in this work is a double-walled stainless-steel high-vacuum chamber equipped with a load lack, a rapidthermal heating source using tungsten-halogen lamps, a high-precision ellipsometer with provision for high-accuracy alignment, a mass spectrometer, and a controlled process gas supply, as illustrated in Fig. 1. A typical form for the the intensity 1(0) measured by the photomultiplier as a function of the azimuth 0 of the transmitting axis of the analyzer is given by 1(0) = Io[1 +
a
2
cos(20) +
b2
sin(28)] ,
(1)
where 0 is measured counterclockwise from the plane of incidence looking into the light source, and 1o the average intensity of a full rotation of the analyzer. The coefficients a 2 and b2 represent all the polarization available from the measurement and are determined by a Fast Fourier Transform. The ellipsometric parameters 7P and A are determined from a 2 and b2 using the relationships 1 1--cos- (-a 2 ) , (2)
2
542
HEAT SOURCE
pH>\7TMONOCHROMATO R PHTMULTIPLIER Fig. 1. Schematic of ellipsometer/RTP chamber system.
and z
cos1 (
i1j2a
)
(3)
The obtained values of 0 and A are then used to calculate the index of refraction of the silicon substrate using standard ellipsometry software [6]. The temperature dependence of the index of refraction of silicon, nsi = nsi -i,;si, at 6328A was measured by van der Meulen and Hien up to 1100°C and is shown in Fig. 2 [7]. This temperature dependence is then used to determine the temperature. Background radiation is the radiation reaching the photomultiplier which does not result from the light source. It could be radiation from the wafer itself if the wafer is at a temperature higher than 725 0 C, radiation from the heat source transmitted through the wafer, or any radiation reaching the photomultiplier by reflection. This com543
ponent of the light intensity must be taken into account by measuring it with the light source turned off and subtracting it from the total intensity with the light source turned on before calculating a 2 and b2 . This is easily done by inserting a light chopper in the incident branch of the ellipsometer and synchronizing its operation with that of the encoder. 3
4.4
2 02
4.0
1
3.8
T( 0 C) Fig. 2. Temperature dependence of the refractive index of silicon [6]. MEASUREMENT ON A FILM-FREE SURFACE First, we discuss the temperature measurement on a film-free silicon substrate. From the fundamental ellipsometry equation of a bare film-free surface, the real (nsi) and imaginary (Ksi) components of the index of refraction are calculated from [8] tan2
2nsinsi 2
sin 0
and
-
sin 40 sin A (1 + sin 20 cos A) 2
tan2 sin 2
=
0
24 - sin 2 24 sin 2 A 2 (1 + sin 20 cos A)
q-cos 2
544
(4)
(5)
where 0 is the angle of incidence. It should be noted here that two values of T could be obtained from Fig. 2, namely, T, based on the value of ns, and T, based on the value of Ksi. From Eqs. (4) and (5), it can be seen that the calculated values of ns; and KS; depend on the angle of incidence 0, and the measured values of b and A. It is also well known that nsi and Ksi also depend on the wavelength A. of the light source. Many sources contribute to defining the resolution of this temperature measurement technique such as (i) the accuracy with which we know the angle of incidence 0, (ii) the resolution with which we measure the ellipsometric parameters 0 and A, i.e., the resolution of the optical components of the ellipsometer, (iii) the numerical errors introduced in determining nsi and KSi from ellipsometry calculations, (iv) the surface conditions, (v) the influence of background radiation, and (v) the presence, growth or deposition of surface films during the measurement. INFLUENCE OF NUMERCIAL ERRORS Numerical errors are introduced in calculating the index of refraction using the ellipsometry software and in determining the temperature by poynomial fits of the dependence of nsi and rsi on T. The numerical error encountered in determining T is the sum of several non-interacting sources: errors arising from empirical fits of the data, errors resulting from truncation and roundoff during execution, and errors resulting from random events. It was found that the systematic error resulted primarily from the empirical polynomial fits of nsi and Ksi to T and vice versa. The truncation and roundoff errors were primarily random or normally distributed in nature and encountered in the ellipsometry program excecution and the supporting host computer software [9]. Upon correction for the systematic numercial errors, the random numerical errors in determining T were reduced from 5VC to +0.3°C using n8 i and to ±2°C using Ksi. The random numerical error in T, was constant at all temperatures, while that in T,, decreased with T to ±0.8°C in the 800-1000'C range [9]. 545
INFLUENCE OF ANGLE OF INCIDENCE € AND 0 AND A MEASUREMENT In an investigation of the systematic and random errors in the estimation of 0 and A, the role of the polarizer and analyzer imp erfections, the azimuth errors, and the residual birefringrence in the quartz windows were studied for a film-free, lightly doped, isotropic silicon substrate [9]. Errors in determining T caused by errors in the angle of incidence 0, and the angular resolution of the optical components were simulated assuming that these error sources were equivalent to an effective angular resolution 6 in the values of the ellipsometric parameters 0 and A [9]. The simulation proceeded by assuming a value for 6, and then finding the worst combination of b+ 6 and A ± 6 that resulted in the maximum error in T. The results are shown in Figs. 3 and 4, as the maximum possible error in T2, and T ,, respectively. It was found that for an angular resolution of 0.01° in 0 and A, the maximum temperature measurement resolution in this method is better than 3.6°C for temperatures up to 1100'C. It can be easily seen that the maximum measurement error is lower using T,, at low temperatures and using TK at higher temperatures. This is evident in Fig. 2 from the slope of Ksi which is higher than that of ns1 in the high-temperature range. INFLUENCE OF THE WAVELENGTH A. Early experimental results indicate that the wavelength of a He-Ne laser is not the optimal wavelength for determining the temperature of a silicon wafer for temperatures up to 500'C. The pseudodielectric functions of silicon were measured up to 5000C in a spectroscopic ellipsometer and it was found that temperature measurement at 3.0 eV would have a better accuracy. The index of refraction of silicon was calculated from these functions at 3.0 eV or 4133A, and the maximum error in T, and T , were calculated. The results are shown in Figs. 5 and 6. It can be easily seen that the maximum errors in T are smaller at 4133A than at 6328A.
546
E
Wafer Temperature ( C)
Fig. 3. Maximum error in T. as a function of T at 6328A [9].
CA
0
200
400
600
0 Wafer Temperature ( C)
800
1000
Fig. 4. Maximum error in T, as a function of T at 6328A [9]. 547
.JU
A = 4133A 0• = 70d = oA
=.-o
20
6 = 0.075*
a
"0 E
6 = 0.05* 10 6 = 0.025* 6 = 0.01* ,
, , I
.,
*.
.
0
A1
.
.
0 0
10O0
200 300 0 Wafer Temperature ( C)
400
500
Fig. 5. Maximum error in Tr as a function of T at 4133A [9].
a-
0 I-
n Wafer Temperature (°C)
Fig. 6. Maximum error in TK as a function of T at 4133A [9]. 548
INFLUENCE OF SURFACE FILMS The influence of the native oxide of silicon as a source of error in
temperature was also studied, and it was found that the oxide thickness and the temperature of the silicon substrate could be determined simultaneously [10]. The temperature of silicon wafers covered with a native oxide can be determined accurately. It was shown that both T and X., could be calculated from a measured set of 4 and A. In addition, this behavior of 4 and A with respect to T and X.o, is not limited to the native oxide regime. By extending the analysis of 4 and A to accomodate thicker oxides, it was found that the temperature and oxide thickness are uniquely determined by 4 and A up to oxide thicknesses of about 2650A for the same range of temperatures. For the case of film growth or deposition, automated ellipsometry lends itself to the in situ monitoring of fast processes. If the optical constants of the film under study are characterized as a function of T, it would be then possible to predict and control the trajectory of the process in the 4-A plane. The use in situ ellipsometry has been proposed as a method for end-of-process detection and applied to the rapid-thermal oxidation process [11]. CONCLUSIONS In conclusion, we discussed the principles of wafer temperature measurement using in situ ellipsometry. This method is a non-contact technique independent of emissivity which offers many advantages over pyrometers and thermocouples. Being a fast technique, it has wide-ranging possibilities for in situ temperature measurement and process control in many thermal growth and deposition applications.
This work was supported by the NSF/ERC on Advanced Electronic Materials Processing at North Carolina State University. We acknowledge many helpful discussions and the support of Profs. N. Masnari, J. Wortman, and J. Hauser.
549
REFERENCES 1. See for example: J. Nulman, in Rapid Isothermal Processing, R. Singh, Ed., the International Society of Optical Engineering, Bellingham, MA, Vol. 1189, 72 (1990), and references therein. 2. S. A. Cohen, T. 0. Sedgwick, and J. L. Speidel, Mat. Res. Soc. Syrnp. Proc., Vol. 23, 321 (1984). 3. R. E. Sheets, Mat. Res. Soc. Symp. Proc., Vol. 52, 191 (1986). 4. T. Tomita, T. Kinosada, T. Yamashita, M. Shiota, and T. Sakurai, Jap. J. Appl. Phys., Vol. 25, L925 (1986). 5. G. M. W. Kroesen, G. S. Oehrlein, and T. D. Bestwick, J. Appl. Phys., Vol. 69, 3390 (1991). 6. F. L. McCrackin, NBS Tech. Note 479 (1969). 7. Y. J. van der Meulen and N. C. Hien, J. Opt. Soc. Am., Vol. 64, 804 (1974). 8. K. H. Zaininger and A. G. Revesz, RCA Review, Vol. 25, 85 (1964). 9. R. K. Sampson and H. Z. Massoud, to be published. 10. R. K. Sampson and H. Z. Massoud, this symposium. 11. C. T. Yu, K. H. Isaak, and R. E. Sheets, ECS Fall Meeting, Seattle, Wa, October 1990.
550
FACTORS AFFECTING THE ECONOMIC PERFORMANCE OF CLUSTER-BASED FABS Samuel C. Wood and Krishna C. Saraswat Stanford University, Center For Integrated Systems, Stanford, California 94305 Open-architecture cluster tools are playing an increasingly important role in semiconductor manufacturing over the next decade. A subset of perceived advantages of cluster-based fabs are economic performance advantages. Modeling and simulation of a hypothetical fab is used to identify the extent of these advantages and the features of the cluster-based fab that are most important in determining those advantages. Results suggest that clustertools offer significant throughput time (or cycle time) advantages without serious compromises to the fab capital cost or cost per wafer, relative to conventional semiconductor manufacturing. Cluster-based fabs seem particularly suited for low-volume, fast turnaround manufacturing. These advantages are shown to depend on such issues as equipment costs, cluster tool features, and innovative management of fab operations. INTRODUCTION Over the last decade, cluster tools have been playing a role of increasing importance in semiconductor manufacturing. Cluster tools typically consist of the following components: one or more loadlocks where lots of wafers enter the tool; two or more process modules where the processes are performed; and a wafer handler consisting of one or more robots to transport wafers between the different parts of the cluster tool. Cluster tools can be subdivided into two classes: closed architecture and open architecture [1]. Closed architecture tools are typically sold by one vendor as a discrete machine with a proprietary communications and mechanical interface architecture. Open architecture systems are more oriented toward modular designs, where a systems integrator may buy a wafer handler, loadlocks, and process modules from independent vendors and configure the system according to the needs of the final user [2]. Although there is still some controversy surrounding the benefits of cluster tools, the tools will probably become increasingly prevalent over the next decade. Futuristic visions of highly automated, flexible fabs oriented toward rapid product innovation and production often include the idea of cluster tools [e.g., 3]. In addition, major semiconductor manufacturers such as IBM and Texas Instruments have already committed to using substantial levels of cluster-based manufacturing, and other semiconductor manufacturers and Sematech are presently evaluating cluster tools for their facilities [4,5,6]. It is likely that a significant portion of the cluster tools in such future facilities will be open architecture. The fabs just mentioned already use or plan to use open architecture tools to varying degrees. Also, SEMI's Modular Equipment Standards Committee (MESC) is developing a set of mechanical and communications standards for cluster tools to facilitate the design of integratible process modules and wafer handlers [7]. Recently, MESC compatible modules and handlers have already begun to appear on the market [1]. Single wafer processing technology is currently at the point where the majority of the process steps in a typical process flow could theoretically be performed in cluster tools. This suggests the possibility of a hypothetical fab where almost all of the process steps are performed in cluster tools (the major exception being ion implantation). Lithography 551
operations could be performed in atmospheric-pressure cluster tools, while the other cluster tools would be held at vacuum. Much of the enthusiasm for cluster tools stems from the perceived advantages of such cluster-based fabs. These perceived advantages can be grouped into three general categories: technological, strategic, and performance. Technological advantages include die yield improvements due to decreased exposure to contamination, and superior process technologies made possible by transferring wafers between process chambers under vacuum. Possible strategic advantages include addressing markets where short product lead times or a diverse line of low volume process flows are critical competitive factors. Performance advantages can be expressed as improved economic characteristics of the fab such as throughput time (also called cycle time or manufacturing interval) and cost per wafer. The rest of this paper will be restricted to the performance class of advantages. It is true that technological and strategic advantages of cluster-based fabs are probably critical in determining the ultimate role of cluster-tools in semiconductor manufacturing, and work has at least begun in characterizing the advantages. [5, 8] and [3,9] respectively. However, there is an implicit requirement that these cluster-based tools also be at least comparable in economic terms to their conventional counterparts. This paper describes the modeling and simulation of a hypothetical cluster-based fab with the goal of beginning to qualify the general economic performance of cluster-based fabs, and the cost, process, and operations issues critical in determining that performance. THE MODEL Cluster tools, particularly open architecture tools, probably represent a technology that is far from mature. However, descriptions of emerging products as well as industrial and academic literature are already sufficient to make a reasonable description of a cluster-based fab. The model in this paper is a refined version of a model presented in a previous paper [10]. That paper details the model to a greater extent than this paper and also contains a more extended discussion of the model's underlying assumptions. To provide an understanding of the model, this paper must summarize that work before moving on to this paper's focus on the factors determining fab performance. Potential time and cost advantages come from a number of general attributes of the cluster-based technology. Detailed descriptions of these attributes have appeared previously, [10] and include rapid single wafer processing, flexibility in processing, extensive in situ process monitoring, and vacuum transfer of wafers reducing wafer cleaning requirements. One should note that these attributes suggest a cluster-based fab that not only differs from a conventional fab in terms of its physical equipment, but also in terms of other features such as the physical process flow, CIM system requirements, equipment control, and wafer transport. Figures 1 and 2 summarize the models of the model's two varieties of cluster tools. Since cluster tools lend themselves more easily to hermetically sealed wafer carriers, it is assumed that lots are transported between clusters in vacuum carriers. The vacuum cluster can simultaneously accommodate and process a lot of wafers from each loadlock. Each vacuum cluster has two or three process modules. The lithography cluster requires a longer setup time to initialize the stepper and vent the vacuum carrier. Since this setup is required for each new mask, the lithography cluster only accommodates one lot at a time. The average cost in both figures refers to purchase plus installation. While estimates of the
552
"*Average Cost: $1.3 million "*Independent Loadlocks * Can accomodate two lots simultaneously * Loadlock pumping and venting: 5 minutes total
"*Wafer transfer time: 45 seconds "*Operator tend time: 5 minutes, including loading
" Internal handler scheduling: FIFO - Required clean room area: 100 square feet Figure 1:
Schematic of vacuum cluster tool.
"*t•verageCos V.7.; rujnul "*Can accommodate one lot at a time
"*Initial
15 minutes for setup and wafer carrier venting
"*3 minutes for wafer carrier evacuating
"*Wafer transfer time: 15 seconds
"•Operator tend time: - Required clean room area: 150 square feet
Figure 2:
Schematic of lithography cluster tool. 553
future mature cost of such a young technology are inevitably controversial, the costs are roughly consistent with those given for contemporary equipment [11]. As a benchmark for comparison, a conventional fab is also modeled. Table 1 summarizes the equipment in the two fabs. The amount of equipment is chosen to balance the fab as well as possible. The cost of a cluster is calculated by adding the cost of the cluster's frame to the modules in the cluster. The numbers given in this model vary considerably from vendor to vendor, and represent a vision for the next few years rather than past experience, particularly in the case of time available. The conventional equipment costs are generally consistent with those in published studies [121. Table 2 summarizes the process flow in the two fabs. The process flow to be simulated is a 0.6 micron DRAM process developed to produce 16 Mbit DRAMs. The flow is based on an experimental (not a production) flow developed at Texas Instruments. The flow was further altered to protect the proprietary interests of TI, and to better reflect traditional technologies outside TI. The cluster-based flow was then generated by directly transferring small sets of conventional operations to their rapid single-wafer processor counterparts. In a very small number of cases, the flow itself was altered between the fabs. For example, a self-aligned well process which was advantageous only for the conventional fab was translated to an extra mask set (non self-aligned process) in the cluster flow. Also, some implants in the cluster-based flow were done at multiple energy levels which decreased diffusion times at the expense of longer implant times. Process data for the cluster-based flow came from interviews with engineers in relevant companies, as well as a survey of the academic and industrial literature, and experience at Stanford in developing and using its Rapid Thermal Multiprocessor [13]. One striking difference in the resulting flows is between the total number of process steps. This is mainly due to the reduction in the number of steps required for a given clean, the reduction of total required cleans, the replacement of ex situ measurement steps with in situ monitoring, and the integration of multiple conventional steps into single cluster module steps. Another striking difference is between the total process time per wafer. This is a result of the switch from slow batch processes to rapid single wafer processes. Table 3 is a comparison of some key features of the two fabs. This table is intended to illustrate some important qualitative differences between the two fabs. Previously mentioned work describes a similar table in more detail than there is room for here [10]. However, a few features in the table require explanation. An "equipment group" is a set of interchangeable equipment that can perform the same process step. "Pipelining" refers to the splitting of a lot of wafers and processing them through a sequence of equipment one wafer at a time. This is an important feature of cluster tools which results in a reduction in the time to perform a sequence of process steps [4]. The difference in the required class and cost per area of the clean room for the two fabs is due to the fact that wafers are assumed to be transferred in sealed carriers in the cluster-based fab, and traditional cassettes in the conventional fab. Finally, results described later in this paper suggests that smaller lot sizes are more appropriate for cluster-based fabs. The cluster-based lot size of 12 is a result of this conclusion. The capital and annual operating costs are broken down into their components in a previously mentioned paper [101. Although the fabs are smaller (as shown by the "approximate capacity" line in Table 3) than many conventional DRAM "mega-fabs," the costs of the two fabs may still appear to be low for their size. This is probably due to the fact that such sources of expense as fab design and engineering fees, and equipment and 554
Cos
Cost
I"
Number Pece(Sk) Cost (Sk
Faulmient Fam.i steppers spin/develop wet station fumaces single-wafer dry etch cvd chambers medium current ion implanters high current ion implanters sputterers ashers in line, ex situ metrology other in line process equipment other equipment
8 15 16 23 38 9 3 2 3 8 18 24
2500 500 643 437 674 901 1500 2800 2100 240 336 134
20000
7500 10280 10045 25616 8111 4500 5600 6300 1920 6051 3220 15100
Ibi
Avaflahh 97 93 91 96 91 84 86 85 85 98 87 98
CLUS• Averavt Equipment Family
Number
Cost er
otal
Piee (Sk) Cost (ik
T ime
Available
stepper modules spin/develop modules uv/bake modules
10 20 15
2500 500 100
25000 10000 1500
97 93 99
dry clean modules rtp (non-cvd) modules rtcvd modules etchbstrip modules sputter modules ash modules
49 26 27 24 5 11
333 310 377 406 545 260
16320 8055 10180 9755 2725 2860
90 90 90 90 90 90
4 2 4 1
1500 2800 493 45
6000 5600 1972 45 15000
86 85 91 88
49 10
165 280
1650 13720
100 100
medium current ion implanters high current ion implanters in line, ex situ metrology laser scribe other equipment vacuum cluster frames lithography cluster frames
Notes: 'Tune Available" includes time for conditional setups, but does not include scheduled maintenance such as changing chemicals, or equipment down times. A "cluster frame" is a combination of wafer handler and loadlocks. These figures are intended to reflect goals for fabs in the mid-1990s. Table 1: Equipment summary for the two baseline fabs. 555
CONVENTIONAL FAB proes family
oe capacity
1 wafer furnace thermal/cvd < 200 wafers other cvd ý5 6 wafers 1 wafer
scribe
"sputter
*dry etch wet processes ash *implant resist coat/dev/bake "pattern expose metroloy
1 wafer < 48 wafers 48 wafers 1 wafer 1 wafer 1 wafer 1 lot
total
average number proc doe of eps per wafer
50 Seca
1
total proes doe6 per wafer
0.8 mine
91.0 hrs 40 137 mine 7 " 3.8 hrs 5 163 sece 13.6 mine 22 422 Seca 154.8 mine 239 16 mine 63.3 hrs 21 53 mine 18.7 hrs 12 79 seca 15.9 mine 55 130 secs 119.3 mine 16 128 sees 34.1 mine 134 8.2 mine 18.2 lre 200.5 hre 552
total
fraction Of
proc@ sDe total lot per lot proes time
0.3 hrs 91.0 16.1 1.1 61.9 63.3 18.7 6.3 47.7 M3.6 18.2
hrs hre hrs hrs hrs hrs hrs hrs hre lre 338.2 hre
0.09% 26.91% 4.76% 0.33% 18.30% 18.72% 5.53% 1.86% 14,10% 4.02% 5.38% 100.00%
CLUSTER-BASED FAB
""rerals proem family 1 1 1 1 1 1 1 resist coat/dev/bake I I pattern/expose scribe rapid thermal/cvd sputter etch/strip clean ash
"implant
metrology
1
proem capacity wafer wafer wafer wafer wafer wafer wafer wafer wafer lot
total
amble of ase 1 42 4 31 47 16 12 52 17 16 231
proc tane per wafer 50 seam 283 secs 228 seas 209 seas 225 seca 145 sas 87 sees 137 seas 152 seas 16 mine
total proem dU per wafer 0.8 mine 198.2 mine 15.2 mine 108.0 mine 178.1 mine 38.7 mine 17.5 mine 118.3 mine 43.1 mine 260.0 mine 16.2 hre
fraction of total proese tea3 total lot per lot process tdme 0.14% 0.2 hre 39.7 hre 26.92% 2.03% 3.0 hre 14.64% 21.6 hrs 35.2lhrs 23.86% 5.22% 7.7 hlr 3.5 hlr 2.37% 16.07% 23.7 hre 5.83% 8.6 hlr 4.3 hre 2.92% 147.5 hre 100.00%1
* Single asterixed processes involve substantial conditional set up times, which are not necessarily the same from process run to process run.These conditional set up
times are not included in "process time." ** Conventional equipment in the "other cvd" category include batch and singlewafer processors, so "average process time per wafer is not really meaningful.
Other notes: A process step is a visit to a cluster module, wet bath, or conventional machine. Process times include regular equipment setups as well as time for stabilization of temperature, gas flows, etc. These stabilization times represent about a third of the process times for the cluster-based processes. Process times do not include equipment loading and unloading. The lot size is 24 wafers in the conventional fab and 12 wafers in the cluster-based fab. Table 2:
Process summary for the two baseline labs.
556
Capital Cost Process Flow Number of Equipment Groups Number of Equipment Pieces Pipelining? Approximate Capacity Minimum Operator Transfers
$153 million 0.6 pm DRAM 39 198 yes 4700 waf/mo 120 238 16 45 hours 10455 sq ft $16.6 million $700 per sq ft
$157 million 0.6 pim DRAM 63 182 no 6000 waf/mo 551
Total Number of Process Steps 552 Number of Measurement Steps 112 Minimum Cycle Time (1 wafer) 283 hours 12017 sq ft Clean Room Area Fab Operation Cost (per year) $17.7 million $2000 per sq ft Cost of Clean Room Cost of Process Consumables $100 per wafer (purchase and dispose) * 24 lot size *
$100 per wafer 12
Table 3: Comparison of key features between the two fabs. Asterixed bold-faced entries are exogenously determined (independent) parameters.
50004000cost per
wafer (dollars)
conventional
300020001000. 0
l
0
10
l
iI
20
30
40
median throughput time (days)
Figure 3:
Performance comparison of the fabs described in previous Tables. 557
process characterization are not included in the capital cost, and that sources of expense originating outside the fab such as allocated corporate overhead are not included in the operating cost. The operating cost does, however, include depreciation of the capital costs. SIMULATION Descriptions of the equipment, process flows, operators, costs, maintenance schedules, and transportation times were specified in eleven files for each simulation. The simulation software has been described in detail previously [14]. The main source of random variation in the fab is equipment failures. The software runs a monte carlo simulation for a specified number of lots and then produces six output files summarizing throughput times, costs, utilizations, and other performance metrics. Simulation results produced the performance relationships for the two fabs shown in Figure 3. Each point on the two curves represents a separate simulation at a specified fixed inventory level. (Intermediate curves used to generate curves such as this have been illustrated previously 110,15].) The points on the left portions of the curves represent light loadings (i.e., low work in process inventories). In this region, there is little congestion in the fab, and so wafer lots are unlikely to have to wait at machines while other lots are processed. This lack of congestion makes quick throughput times possible. On the other hand, lightly loaded fabs have low throughput rates (i.e., wafer starts) and low equipment utilizations, and so fixed costs such as fab depreciation are amortized over a relatively small number of wafers. This is why the cost per wafer is relatively high in the lightly loaded region. The points on the right portion of the curves represent high work in process inventories or heavy loadings. In this region, increased congestion results in slower throughput times, but also better throughput rates resulting in lower costs per wafer. In general then, the vertical asymptote represents a case where a small number of wafers rush through the fab unhindered. The horizontal asymptote represents a case where large numbers of wafers slowly travel through heavily utilized equipment, and spend most of their time waiting at occupied equipment Figure 3 represents a tradeoff between two key economic parameters that help determine the profit generated by the fab (and thus the fab's value). The cost per wafer is clearly critical since it determines the cost to produce the fab's product. The throughput time is also important, however, because it plays a significant role in determining the value of the wafer. Advantages of rapid throughput times have been described previously [15] and are summarized here: (1) A reduced throughput time can result in faster turnaround for circuit and process experiments and characterizations. This can result in faster innovation and earlier entry into product markets, which in turn can result in higher prices for the product on the wafers, and increased market share [16]. (2) A reduced throughput time on existing products improves responsiveness to customers and market variations, which can improve the demand and price for the product [16,17]. (3) Shorter throughput times reduce the time the wafer exposed to potential yield-reducing contamination, which could increase the number of working chips per wafer [181. As market constraints change, the optimal operating point on the curves in Figure 3 also change. For example, a fab producing ASICs for customers paying a premium for fast order turnaround may operate in the low throughput time regime. A fab ramping up yield and volume for a memory product may start in the low throughput time regime and move to higher throughput times as process understanding and yields improve. For the remainder of this paper, the cost per wafer and throughput time will be considered the two primary economic performance factors in determining the fab's value. This papers next section is aimed at identifying critical factors that determine the shape and position of this curve. 558
PERFORMANCE FACTORS Scale and Equipment Cost Figure 4 shows how the performance curves vary with the cost constraint on the conventional and cluster-based fabs. The smaller fabs have degraded performance for at least two reasons. First, smaller fabs are harder to balance, so more equipment is underutilized even when the fab is configured in an optimum way. Second, since there are less copies of machines in the smaller fabs, performance is more likely to suffer when equipment breakdowns occur. In fact, increasing the copies of equipment available for a specific process generally improves fab performance even in fabs without equipment failures [19]. An important conclusion of Figure 4 is that conventional and cluster-based fabs seem to scale similarly with capital investment. When fabs need to be small, either due to the capital constraints on the firm building the fab, or the size of the market the fab is addressing, the cluster-based fabs may be superior even in the low wafer cost operating regime. For the model assumptions, this cross-over point seems to be for fabs with a cost of around $100 million. The impact of the cluster cost assumptions on fab scaling is addressed in Figures 5 and 6. Figure 5 shows how the maximum throughput rate of the fab changes with the cost of the fab for different vacuum cluster cost assumptions. As stated before, the average cost of a vacuum cluster was roughly $1.3 million for the previous figures. At this cluster cost, cluster-based fabs with capacities less than about 2500 wafers/month are less expensive than their conventional counterparts with the same capacity. In other words, for fabs smaller than this threshold the two curves in Figure 3 would not intercept; the cluster-based fab would be superior at all wafer costs. The other two lines in Figure 5 show the effect of varying the average vacuum cluster cost between two extremes. For an average cluster cost of $0.5 million, the cluster-based fab is generally superior, and for an average cluster cost of $3 million, the cluster-based fab is generally inferior. Readers should note that this figure contains no information about throughput time. The capacity level of the fab simply determines the horizontal asymptote on the wafer cost versus throughput time relationship in Figure 3. This horizontal asymptote for each fab size is plotted in Figure 6. This figure essentially presents the information in Figure 5 in a different form. Rather than expressing the size of the fab in terms of its capacity, the size of the fab is expressed as its minimum achievable cost per wafer. There are a number of factors other than equipment cost which affect the curves in Figures 5 and 6. One of these factors is the process flow. When the total time a wafer requires of an equipment group is reduced, less copies of that equipment are required to achieve the same throughput rate. In other words, for a given fab capacity, reducing such process parameters as set up times or process times (particularly on slow or expensive equipment) would tend to make the curves in Figure 5 steeper, which is desirable. Another factor that determines the shape of the curve is how many different processes one equipment type can perform. This main impact of this type of versatility is on the lower portions of the curve in Figure 5. Increased process versatility is likely to both decrease the minimum achievable fab cost and capacity, and also decrease the fab cost for existing low capacities. This feature has resulted in an interest in developing highly versatile "multiprocessing" equipment for low cost, low volume "micro factories" [13].
559
CONVENTIONAL FAB 50 $68 million
40 cost per 3 wafer (dollars) 20
$70 million
10
$101 million $157 million
0.00
10.00 20.00 30.00 40.00 median throughput time (days)
CLUSTER-BASED FAB
$53 million 4000 cost per 3000-. wafer (dollars) 2000
$55 million
$95 million
1000 0
0.00
million
a$153
10.00
20.00 30.00
40.00
median throughput time (days) Figure 4: Families of performance curves for conventional and cluster-based fabs. Each curve represents a different tab. The curves are labeled with their capital costs. The capital cost of the tab is varied by altering the amount of equipment in the fabs.
560
5000 4000 capacity of fab 3000 (wafers per month) 2000
1000 0 0
50
100
150
200
cost of fab (millions of dollars) Figure 5: Capacity versus cost for different fabs. The thin curve corresponds to the conventional fab described in Tables 1-3. The bold curves correspond to the cluster-based fab described in the same tables, except with varying vacuum cluster costs. The curves are labeled with their corresponding average vacuum cluster costs.
'$3M
•AA
DUUU'
$1.31 minimum
cost per
wafer (dollars)
4000-
$500k
300020001000. conventional
0 0
50
100
150
200
cost of fab (millions of dollars) Figure 6: Minimum cost per wafer versus fab cost for the same fabs in Figure 5 above.
561
Cluster Characteristics Performance characteristics of the cluster tool are factors which may deceivingly appear to be of little consequence in determining the overall performance of the fab. Many of the cluster tool characteristics turn out to be surprisingly important however. Figure 7 shows a performance curve for similar fabs with different wafer transfer times. The wafer transfer time is the time that passes from a wafer being completed in one module until that wafer is ready to start processing in the next module. This time is not only determined by the speed of the robotic arm, but also by the cluster host control system and the pumping and venting of intermediate volumes. The 45 second curve is the same curve that represents the clusterbased fab in Figure 3. Even though the 15 second curve is for a less expensive fab, that fab outperforms the 45 second fab in all regions of the performance curve. (If the fab costs were equal, the difference would be even greater than in Figure 7.) Although the improvement in fab performance may not look that significant in Figure 7, initial estimates suggest that the transfer time improvement could increase the scale cross-over point in Figure 5 by at least several tens of millions of dollars (for the $1.3 millioincurve). Another important characteristic of the cluster tool is its ability to simultaneously process multiple lots residing in multiple loadlocks. This feature results in at least two advantages. One is that one lot can be processed while the other loadlock is pumped or vented. The second advantage is that different lots utilizing different parts of a given cluster tool can be processed at the same time, balancing the utilizations of each module in the cluster tool. Although rather subtle, initial work suggests that the second advantage is the more significant, particularly for smaller fabs and cluster tools with quick loadlock pump/vent times. Exploiting that advantage depends on a reasonably sophisticated scheduling techniques, which are identified further in the next subsection of this paper. Configuration and Operations Management The tasks of configuring and managing cluster-based fabs are likely to be considerably more difficult than the corresponding tasks for conventional fabs. One of these tasks is choosing the appropriate lot size for the fab. In a conventional fab, relatively little effort is devoted to the choice of lot size, since varying the lot size does not seem to dramatically impact the performance of the fab (at least favorably). Figure 8 shows the effect of varying the number of wafers per lot in the cluster-based fab. The 12 wafer curve is the same curve as the cluster-based curve in Figure 3. The other two curves are the results of changing the lot size in the fab which was optimized for a lot size of 12. Re-optimizing the fabs for the respective new lot sizes is expected to reduce the minimum cost per wafer an additional $70 for the lot size of 6 wafers, and $30 for the lot size of 24 wafers. As the plot suggests, the choice of lot size determines the cost per wafer versus throughput time tradeoff of the fab. In the low throughput time regime, smaller lot sizes are optimal, while larger lot sizes are optimal for fabs aimed at operating at minimal cost. This plot also suggests that lot size should be increased as fab production is ramped up. It should also be noted that increasing the lot size improves the appearance of the cluster-based fabs in Figures 5 and 6, since only minimum wafer cost is important in those figures. There are other new issues that the cluster-based fab manager must confront as well. One of these issues is the configuration of an open-architecture fab. The manager must presumably choose the number of each process module, and then how those modules are to be arranged into cluster tools. The traditional approach to balancing a conventional fab is to choose a number of copies of each piece of equipment so that the utilization of the 562
3000 2500 2000-
cost per wafer (dollars) 1500.
1000.
45 seconds
500-
15 seconds
0
_-
0
5
-
_-
-
10
15
20
_-
25
throughput time (days) Figure 7: Performance curves for fabs with different cluster wafer transfer times. The 45 second curve is for the $153 million lab described in the earlier data tables, while the IS second curve is for a similar $133 million lab running the same process flow.
%UUU *
2500.
6 2000. wafers
cost per wafer (dollars) 15 0 0.
1000. 500. 0
I
0
5
10
I I
15
"I
20
25
throughput time (days) Figure 8: Performance of cluster-based fab with different lot sizes. The fab was optimized for a lot size of 12 wafers. 563
equipment is equal across the fab. This approach does not work for cluster-based fabs because process modules may be kept idle while other parts of the cluster are occupied. In other words, a module utilized at 60% in a cluster-based fab could be a bottleneck even if there are other modules utilized at 70%. This often counterintuitive situation made the cluster-based fab configuration much more challenging than the equivalent procedure for the conventional fab. The optimal balance of modules depends on wafer transfer time, lot size, loadlock pump/vent times, and the fab scheduling policy. Once the fab is configured the manager must then choose how to choose which lots go to which of the potential clusters that could process the lot, [10] and how wafers in different lots competing for the wafer handler and process modules should be scheduled within the cluster. Making optimal choices in each of these areas can significantly affect the shape and position of the fab performance curves. CONCLUSION The modeling and simulation of cluster-based and conventional fabs running a modem process was used to investigate the potential performance characteristics of openarchitecture cluster-based fabs. In general, the cluster-based fabs seem to be comparable in their capital cost requirements and cost per wafer performance. However, the cluster-based fabs offer significant advantages in the area of throughput time which could dramatically improve the profit potential of the fab. Specific areas which were identified in determining the economic performance of cluster-based fabs include the size of the fab, the cost of the cluster tools, the process flows in the fab, the characteristics of the cluster tool itself, and fab configuration and management strategies. One area where cluster-based fabs offer particular advantages is for fabs with small cost or small production volume requirements. ACKNOWLEDGEMENTS Portions of this work were supported by the Semiconductor Research Corporation and by Texas Instruments. In particular, the authors are grateful to Graydon Larrabee at TI for his assistance. BIBLIOGRAPHY [1] [2] [3] [4] [5] [6] [7] [8]
N. Korolkoff. "Integrated Processing Part 11 -- Cluster Tool System." Solid State Technology, October, 1990. P. Burggraaf. "Integrated Processing: The 1990s Trend." Semiconductor International,Jueft, 1989. G. B. Larrabee. "The Intelligent Microelectronics Factory of the Future." InternationalSemiconductorManufacturingScience Symposium. San Francisco, California. May 20, 1991. A. S. Bergendahl, D. V. Horak, P. E. Bakeman, and D. J. Miller. "Cluster Tools, Part 2:16 Mbit DRAM Processing." SemiconductorInternational,September, 1990. T. K. McNab. "Cluster Tools, Part 3: Technical Issues." Semiconductor International,October 1990. W. Iversen. "Could This be the Factory of the Future for Low-Volume Chip Production?" Electronics,January, 1989. B. Newboe. "Cluster Tools: A Process Solution?" Electronics,July, 1990. R. S. Freund, ed., SPIE Proceedingson Multichamber and In-Situ Processingof Electronic Materials.October 10-11, Santa Clara, California. 564
[9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
W. E. Steinmueller. '"he Economics of Alternative Integrated Circuit Manufacturing Technology: A Framework and Appraisal." Center for Economic Policy Research working paper. Stanford University. April, 1991. S. C. Wood and K. C. Saraswat. "Modeling the Performance of Cluster-Based Fabs." InternationalSemiconductorManufacturingScience Symposium. San Francisco, California, May 20, 1991. T.K. McNab. "Cluster Tools, Part I: Emerging Processes." Semiconductor International,August, 1990. "16 Mb DRAM -- 8 in. Line Cost Merits." SemiconductorInternational,February, 1991. K. C. Saraswat, et al. "Rapid Thermal Microprocessing for Micro Factories." SPIE Symposium on MicroelectronicProcessing. Santa Clara, California, October, 1989. S. C. Wood, K. C. Saraswat, and J. M. Harrison. "Cost Performance Modeling of Semiconductor Fabs." SRC Techcon 90. San Jose, California, October 18, 1990. S. C. Wood, K. C. Saraswat, and J. M. Harrison. "The Economic Impact of Single Wafer Multiprocessors." SPIE Conference on Rapid Thermal andRelated ProcessingTechniques. Santa Clara, California, October 2-3, 1990. B. C. Cole. "Getting the the Market on Time." Electronics,April, 1989. G. Stalk, Jr. "Time -- The Next Source of Competitive Advantage." Harvard Business Review, July-August, 1988. L. M. Wein. "On the Relationship Between Yield and Cycle Time in Semiconductor Wafer Fabrication." Submitted to IEEE Transactionson Semiconductor Manufacturing in January, 1991. S. C. Wood, J. M. Harrison, K. C. Saraswat. "Performance Modeling of Multiprocessor Fabs." SRC IFM-IC Workshop, Bryan, Texas, November, 1989.
565
SINGLE-WAFER RAPID THERMAL CVD TECHNOLOGY FOR FABRICATION OF MOS AND BIPOLAR DEVICES Ahmad Kermani, Fred Wong and Kris E. Johnsgard RAPRO Technology Inc., Fremont, CA 94539 In fabrication of MOS, bipolar and BiCMOS integrated circuits, single-wafer rapid thermal chemical vapor deposition (RTCVD) can provide the foundation for a wide range of processes. In addition, a number of processing steps can be integrated to a central wafer handler to provide an applicationspecific tool. The applications include MOS gate dielectric, poly-emitter bipolar interface engineering, polysilicon deposition, and single or multi-layers of blanket or selective homo or hetero-epitaxy films. It is increasingly apparent, especially with the advanced generation technology employed for large substrates, that the level of control required can only be achieved when processing sequences are executed in a single-wafer mode under a controlled environment. A combination of low-temperature reduced-pressure wafer cleaning, dielectric, engineering and polysilicon deposition will satisfy the requirements of this emerging concept of integrated, environmentally controlled front-end processing for the MOS gate and poly-emitter bipolar applications. INTRODUCTION For fabrication of small geometry ICs, reduced thermal budget processing is mandatory to restrict dopant movement for maintaining shallow junctions. Furthermore, for stability reasons, strained layer SixGel-x HBT structures can not be subjected to high-temperature processing [1]. For low-thermal budget processing, RTCVD was introduced to provide an alternative to conventional long-time, slow-response batch furnace technology. In this approach, thermal energy is provided by radiative heating in a cold-wall environment. Due to small thermal mass of the system, rapid changes in wafer temperature, both up and down, is made possible. In parallel, various dry low-temperature wafer cleaning techniques have been developed [2,3,4,5]. The key is to effectively clean the wafer at low temperatures (below 6000C) and to maintain surface cleanliness between various processing steps. Dry-phase, anhydrous HF cleaning at room temperature supplemented by UV/ozone treatment has been used to effectively remove the surface native oxide and hydrocarbon residues [6, 7]. This technique has attracted a lot of attention due to its simplicity, ease of integration and low cost. Furthermore, it can be applied to fabrication of both MOS and bipolar devices. 566
INTEGRATED PROCESSING
For both the MOS gate electrode or the bipolar emitter contact applications, the polysilicon deposition immediately follows the most critical step in the process sequence, i.e. the gate oxidation in the MOS devices, and the preparation of the emitter contact in bipolars. Sequential processing of silicon wafers, gate oxidation followed by in-situ deposition of polysilicon electrode without exposing the wafers to atmospheric ambient, has been shown to improve the device yield [8]. The results of comparing the breakdown performance of in-situ and ex-situ deposited polysilicon electrodes for PMOS capacitors are shown in Figure 1. For these samples,
I
I
0
1
2
4
6
8
9
10
11
12
13
Breakdown Voltage, Volts
Figure 1. A comparison of intrinsic integrity of PMOS capacitors for insitu vs. ex-situ deposited poly-Si electrodes on 115 A of gate oxide. the breakdown voltage was measured after the capacitors were ramped to 90 percent of the breakdown level once. For bipolar devices with poly-emitter technology, control of the polysilicon / silicon substrate interface is the key parameter for performance repeatability. Conventionally, a thin oxide layer is chemically grown on the silicon substrate prior to polysilicon deposition. Chemical oxide films are silicon-rich and have a rough surface morphology. Due to the delay between their growth and polysilicon deposition, control of the oxide thickness is poor. Both native and chemical oxide films are thermally 567
and chemically unstable and break down during the polysilicon deposition and emitter drive-in steps [9]. Ronsheim, et. al, [10] have reported on the correlation between the polysilicon / silicon interfacial oxygen content and the bipolar transistor performance. As expected, the transistor gain increases by the increasing amount of interfacial oxide thickness. The increase in the emitter resistance, however, becomes very severe at higher interfacial oxygen content. Tejwani, et. al, [11] have reported on the feasibility of improving the transistor gain without sacrificing the device speed, as evidenced by the value of the emitter resistance. An alternative approach to interfacial oxide growth and polysilicon deposition employs a bipolar poly-emitter integrated processing tool to clean, form and cap the interface [12]. Using the emitter resistance as a figure of merit, the effect of various wafer transfer media on poly-emitter interface characteristics is shown in Figure 2. The comparison is between hot and cold (1000C) conventional furnaces and single-wafer RTCVD. The RTCVD sample received an in-situ hydrogen clean prior to polysilicon deposition. This cleaning step completely removed the interfacial oxide, resulting in the lowest emitter resistance value. Depending on the device application, a controlled ultra-thin interfacial oxide film can be grown prior to the polysilicon deposition. For optimum performance, the thickness of the interfacial oxide must be controlled to balance the benefits of the higher transistor gain and the increase in the emitter resistance.
I
2.0e+15
4.0e+15
6.0e+15
8.00+15
1.0e+16
1.2e+11
Implant Dose, 1/cm2
Figure 2. The effect of wafer transfer media on the emitter resistance, "cold" furnace conditions are 6250 and 1000C, respectively.
"standard"and
568
MOS Gate Dielectric Engineering One application of RTCVD is in engineering of sub 10 nm MOS gate dielectrics. It has been demonstrated that the annealed-nitrided oxides (ANO) films have superior electrical and diffusion barrier properties to pure oxides [13]. The immunity and electrical integrity of optimized ANO films to hot carriers, after injection of 0.5 C/cm 2 of charge, is shown in Figure 3. 80 A thick oxide films were first grown at 1050oC in dry oxygen. Samples were then nitrided in diluted ammonia ambient and sequentially annealed in oxygen and argon. Hole trapping is observed in pure oxide films, while severe electron trapping is evident in the nitrided oxides. Properly engineered ANO films, however, exhibit excellent immunity against injected charge. Electron trapping behavior of the nitrided oxide films can be correlated to the nitridation conditions. Higher partial pressure of ammonia and nitridation temperature results in larger shifts in the flat band voltage. This is primarily due to higher concentration of nitrogen at the oxide/silicon interface and larger concentration of hydrogen related species in the oxide film [13]. The post nitridation anneal in oxygen
0.30 Q injected
0.25
Pure N143 @ 1050 C
0.5 CICm2
@ 10 ma/Cm2
S0.20 •
0.15
V a•
0.10
0.05 0.00
*
DuN@-V
-00o5 0.10
-0.10
RTO
NO Conditions
ONOA
Figure 3. Hot carrier immunity of optimized ANO structures after injection of 0.5 C/cm 2 of charge at 10 mA/cm 2 . and argon is mandatory to remove the nitrogen and hydrogen species from the bulk of the oxide and silicon/oxide interface. The balance between the sequential oxygen and argon anneal is to minimize the oxide growth at the interface and to remove the electron trap sites.
569
Bipolar Poly-emitter Interface Engemeering The interfacial oxide must be thicker than 10 A to be thermally and chemically stable and, thin enough not block dopant atoms, approximately less than 30 A. Furthermore, for best transistor performance, the interracial oxide must have a near-SiO2 stoichiometry. For this range of oxide thickness, the oxidation kinetics must be greatly reduced. This can be achieved by reducing the oxidation temperature, pressure and by lowering the partial pressure of oxygen. Using SIMS, the oxidation kinetics of ultrathin oxide films expressed as total integrated dose of oxygen is shown in Figure 4. For these samples, upon completion of the oxidation step, polysilicon caps were in-situ deposited.
^17 1
-
-SRI
_~DIdute 0205ti
p_
10}15.
I900E
M/ia
AU JLV
0
5
10
15
2)
(Oxidation time)0.5, SecO5
Figure 4. The oxidation kinetics of ultra-thin interfacial oxide films expressed as total integrated dose of oxygen, using SIMS. Polvsilicon deposition - RTCVD of polysilicon films is considered to be a complementary process for both integrated MOS gate and bipolar polyemitter applications. Polysilicon films in production must have good thickness uniformity, smooth surface morphology, uniform grain size distribution and proper grain orientation. The throughput of a single-wafer system must be comparable to that of a conventional LPCVD tube furnace. This can be accomplished by increasing the deposition rate of polysilicon. The deposition kinetics of polysilicon at 5 torr pressure and 2% SiH4/H2 chemistry is shown in Figure 5. At higher pressures, homogeneous gas
570
phase nucleation may result in severe particle problems. While increasing the temperature will increase film growth rate, it will also produce larger polysilicon grains and rough surface morphology. These effects are undesirable and can be prevented by a two step deposition process. An initial deposition at 5800 to 6300C grows a fine grain nucleating layer while subsequent deposition at 6800 to 7800C completes the stack. At the lower temperatures, the deposition rate is 100 to 200 A/min. It rises to 1000 to 2000 A/nain in the higher temperature 'range. Based on TEM plan view results, the average grain size for the two-step deposited films is approximately 1.5 to 2 times larger than the conventional LPCVD polysilicon films.
SIH4
I
= =
1000==
100
10.8.0
=
.
Ea z1.77V
-
8.S
9.0
9.5
10.0
10.5
11.0
11.5
12.0 12.5 13.0
1/T ( *10,000 ), K-1
Figure 5. The growth kinetics of polysilicon at 5 torr pressure for silane/hydrogen and dichlorosilane/hydrogen chemistries. SUMMARY The applications of single-wafer RTCVD for fabrication of MOS and bipolar devices are discussed. For front-end processing, the MOS gate dielectric engineering and bipolar poly-emitter interface engineering are the most immediate applications. The same reactor technology may be used for gate oxidation and poly-emitter interfacial oxide growth. An integrated, environmentally controlled processing system that incorporates cleaning, oxidation, and RTCVD polysilicon modules would satisfy the processing requirements of both MOS and bipolar technologies.
571
ACKNOWLEDGEMENTS The authors would like to thank Steve Tignor, Xiaolan Wu and Steve Baldwin of Unisys Corporation, Memory and Packaging Operation for their sincere cooperation in providing the bipolar poly-emitter results and helpful discussions. REFERENCES [1]
Ted Kamins, et. al., IEEE Electron Device Letters, 10 (11), pp. 503-505, 1989.
[2]
Nobuhiro Mild et. al, IEEE Transactions on Electron Devices, 37 (1), pp. 107-111, 1990.
[3]
G. P. Burns, Appl. Phys. letter 53 (15), pp. 1423-1425, 1988.
[4]
S. S. Iyer, M. Arienzo and E. de Fresart, Appl. Phys. Lett. 57 (9), pp. 893-894,1990.
[5]
Yasuo Takahashi, H. Ishii and K. Fujinaga, Appl. Phys. Lett. 57 (6), pp. 599-600, 1990.
[6]
M. Offenberg, M. Liehr, G. W. Rubloff and K. Holloway, Appl. Phys. Lett. 57 (12), pp. 1254-1256, 1990.
[7]
S.R. Kasi and M. Liehr, Appl. Phys. Lett. 57 (20), pp. 2095-2097, 1990.
[8]
P. Pan and Ahmad Kermani in Rapid Thermal Annealing/Chemical Vapor Deposition and Integrated Processing, edited by D. Hodul, J. Gelpey, M. Green and T. Siedel (Material Research Society Proceedings 146, Pittsburg, PA 1989) pp. 51-53.
[9]
A. Sakai, T. Tatsumi and T. Niino, Semiconductor Silicon 1990, Proceedings of the Sixth International Symposium on Silicon Materials Science and Technology, Edited by H. R. Huff, K. G. Barraclough and J. Chikawa (Electrochemical Society Pennington, NJ 1990) pp 251-260.
[10]
Paul A. Ronsheim, Brian Cunnigham and Mark D. Dupuis, J. Appl. Phys., f9 (1), pp. 495-497 (1990).
[11]
Manu J. Tejwani, Paul A, Ronsheim and Subodh K. Kulkarni, The 178th Electrochemical Society Meeting, News Briefs, Seattle, WA 1990).
572
[12]
Ahmad Kermani and Fred Wong, Solid State Technology, 42, pp. 4143, 1990.
[13]
Peter J. Wright, Ahmad Kermani and Krishna Saraswat, IEEE Transactions on Electron Devices 37 (8), pp. 1837-1839, 1990.
573
SIMULTANEOUS MEASUREMENT OF WAFER TEMPERATURE AND NATIVE OXIDE THICKNESS USING IN SITU ELLIPSOMETRY Ronald K. Sampson and Hisham Z. Massoud Department of Electrical Engineering, Duke University, Durham, N.C. 27706. ABSTRACT The influence of a native oxide layer on the temperature measurement of a silicon wafer using in situ ellipsometry was investigated. This measurement technique is based on determining the index of refraction of silicon (nisi) using ellipsometry, and then inferring the temperature from the known dependence of fisj on T. It was found that for native oxide thicknesses up to 30A and for wafer temperatures up to 11000C, both the oxide thickness and the wafer temperature could be calculated simultaneously either by iterative numerical routines, graphical methods, or polynomial fits. This process can also be applied for oxide thicknesses larger than native oxides. The use of this technique in the monitoring of temperature and growing oxides is discussed. INTRODUCTION It has been shown that the temperature T of a bare silicon wafer can be measured in situ using ellipsometry to within 3.60C for temperatures up to 11000C using an ellipsometer resolving 0.010 in ¢ and A [1]. This is achieved by measuring the ellipsometric parameters 0 and A, calculating the refractive index of silicon, fisi = n - in, and then determining T from the known temperature dependence of n and n. This process also has been shown to offer several advantages over standard techniques such as optical pyrometry and the use of thermocouples, because measurements using ellipsometry are fast, direct, independent of wafer emissivity and non-contact. As a result, 574
ellipsometry is well suited for temperature measurement in a rapid thermal processing (RTP) environment. However, this technique has been limited in application to filmfree wafer surfaces. This restriction is impractical for most thermal processes, since often the objective is to monitor the temperature in situ during film growth or deposition. As a result, the effect of the presence of a native oxide layer on the measured wafer temperature has been investigated and a resulting algorithm developed that enables simultaneous determination of both temperature and oxide thickness from a single ellipsometry measurement. Furthermore, it has been determined that this algorithm applies for thicker oxides, such that this technique can be applied to monitor both temperature and oxide growth in situ during processing. DEVELOPMENT OF THE MEASUREMENT PROCESS A typical RTP chamber equipped with an rotating analyzer ellipsometer (RAE) for temperature and oxide thickness measurement is used in this study. The chamber consists of a radiative heat source, gas inlets, vacuum chamber and optical ports for the RAE. The components of the RAE include a light source, polarizer, sample, rotating analyzer, monochromator and photomultipher. For this investigation, a helium-neon laser (A0 = 6328A) and an angle of incidence q = 700 were used. The silicon wafer sample is assumed to be optically flat, lightly doped and defect free. The refractive index of the native oxide was set as n,. = 1.46474 + 1.22142e-5.T, where T is in °C [2]. Temperature and Oxide Thickness Dependence of 0 and A The temperature and native oxide thickness dependence of the ellipsometric parameters V)and A was obtained using the following sequence of steps. First, both the real and imaginary components of the refractive index of the silicon substrate as a function of temperature were obtained by fitting polynomials to the data of van der Meulen and Hien [2] in the form M
n =
: ai. T' i=0 575
(1)
and N
bj. Tj,
=
(2)
j=0
where the polynomials were generated using a least squares algorithm [3], and the coefficients a, and bj were tabulated for M = 3 and N = 6 [4]. Second, 0 and A were calculated as functions of nsi, the refractive index of the oxide n.., the angle of incidence 0, and the wavelength A0 . The relationship between these parameters and the ellipsometric parameters 0 and A is transcendental [5], such that 0 and A were calculated for temperatures up to 1100'C and oxide thicknesses up to 30A using McCrackin's ellipsometry program [6]. The resulting curves plotted in Fig. 1 illustrate the dependence of 0 with varying temperature and native oxide thickness, where lines of constant oxide thickness are plotted every 5A. From Fig. 1, L is observed to be monotonically increasing with both increasing Xo, and T for the full ranges of temperatures and oxide thicknesses investigated. Similarly, the curves in Fig. 2 illustrate the dependence of A with varying temperature and oxide thickness. However, A is observed to decrease monotonically with both increasing Xo,, and T. It is these opposite trends that result in the unique determination of both X,,, and T from a single measured set of 0 and A. Determination of T and X,, from 0 and A can now be described as follows: For a given measured set (01, A 1), there is a temperature interval T 1 _
4, I,
a' 4,
0
Wofer Temperature ('C)
Fig. 1. Temperature dependence of the ellipsometric parameter V) for native oxide thicknesses up to 30A.
U, 4, 4,
a' 4,
0
Wafer Temperature ('C)
Fig. 2. Temperature dependence of the ellipsometric parameter A for native oxide thicknesses up to 30A. 577
Mapping of T and X.., Into 4 and A An alternative to the iterative approach is to examine the behavior of 4 vs. A as a function of the wafer temperature and oxide thickness, as illustrated in Fig. 3, where lines of constant thickness are plotted every 5k and isotherms are plotted every 220'C. It is evident *that, for a given measured pair of the ellipsometric parameters (01, A 1 ), there is only one corresponding wafer temperature and oxide thickness. That is, there is a unique one-to-one mapping of T and Xo, into 0 and A. As a result, it is possible to fit the curves in Fig. 3 using a similar least squares approach as mentioned earlier to obtain polynomials of the form M,N
T= E
aij.)'.
A
(3)
A
(4)
i,j=O
and
M,N
X. = :bj i,j=O
where the coefficients aij and bij were obtained and tabulated for M = N = 7 [4]. Seventh order polynomials in both 4, and A were needed in order to insure a maximum numerical error of less than 10 C and 0.5A in T and X,, for the range of parameters shown in Fig. 3. Therefore, once 4 and A are known, the temperature and native oxide thickness can be calculated using Eqs. 3 and 4. 4 and A Behavior For Thicker Oxides
After further investigation, it was determined that this process is not limited to the native oxide regime. Instead, the upper bound of oxide thickness is reached only when 4 and A have completed a full cycle. This cycle corresponds to approximately 2750k, as illustrated in Fig. 4. In this plot, two isotherms are represented by the outer and inner rings, where T = 0°C and 11000C, respectively. Lines of constant oxide thickness are plotted every 100A, for 0 < Xo, < 2700k. For comparison, the shaded region represents the area described by Fig. 3. 578
Ao- 6328
1 0 - 700
175
T -
O*C
1. 0'<
T= 1100I C
170
10
12 -0 (Degrees)
14
16
Fig. 3. Variation of 0 vs A for temperatures between O°C and 1100* C, and oxide thicknesses up to 30A.
@2 @2 0' @2
a
4, (Degrees)
Fig. 4. Variation of 0 vs A for temperatures between 0 0 C and 1100°C, and oxide thicknesses up to 2700A. 579
It is clear from Fig. 4 that both the wafer temperature and oxide thickness are still uniquely defined up to approximately 2750k, but the ability to accurately resolve T and Xox appears to be limited in certain regions. More specifically, it becomes increasingly difficult to resolve the temperature and oxide thickness 00C and 11000C, and oxide thicknesses up to 2700k. for oxides in the neighborhood of 7001100A and 1800-2000A. However, ellipsometers in general are more sensitive to changes in the optical characteristics of the wafer in these regions, which tends to somewhat counter this resolution limitation [7]. In other words, the ellipsometer is able to more accurately resolve ' and A in these regions. ELLIPSOMETRY AS A PROCESS MONITOR Because this process provides a relatively simple and versatile technique for temperature and oxide thickness measurement, ellipsometry has potential applications where continuous real-time measurements are required. More specifically, ellipsometry can be used to monitor oxide (and thin film) growth kinetics and temperature in a rapid thermal processing environment. Because two physical parameters can be monitored simultaneously with a single ellipsometer, a footprint in effect can be obtained that describes a particular process by plotting either both the oxide thickness and wafer temperature, or the ellipsometric parameters 0 and A, on a real-time basis. This footprint can then be used as a basis for standardizing and differentiating between particular processes. In addition, RAEs are capable of completing several measurements per second [9]. This capability is important because it provides the ability to monitor large thermal gradients typically encountered in a RTP environment. However, in order to maintain a reasonable resolution in the absolute values of the measured data taken using ellipsometry, it is important that the index of the film be well defined, the optical components including the wafer are aligned properly, and that the region of the wafer that will be used for the optical measurement be damage free [1,4]. Provided these criteria are met, ellipsometry can also be used effectively in a closed loop configuration to provide feedback for temperature and oxide growth control. 580
CONCLUSIONS It has been shown that both the temperature and native oxide thickness are uniquely determined by a single measured pair of the ellipsometric parameters 0 and A. As a result, an algorithm has been developed that uses fitted polynomials to calculate both the temperature and native oxide thickness of a wafer from the measured values for 0 and A for temepratures up to 1100"C and oxide thicknesses up to 30A. It has also been shown that this algorithm applies to oxide thicknesses up to approximately 2750A, although there may be some measurement resolution limitations, particularly for oxide thicknesses between 700-1100A and 1800-2000k. Finally, because these measurements can be carried out several times per second, ellipsometry can be used as a process monitor in either open or closed loop configurations in a rapid thermal processing environment.
ACKNOWLEDGMENTS This work was supported by the NSF/ERC for Advanced Electronic Materials at North Carolina State University. The authors wish to thank Prof. E. A. Irene, Prof. Y.-Z. Hu, and Dr. K. A. Conrad for many helpful discussions.
REFERENCES 1. H. Z. Massoud, R. K. Sampson, K. A. Conrad, Y.-Z. Hu, and E. A. Irene, this conference. 2. Y. J. van der Meulen and N. C. Hien, J. Opt. Soc. Am., 64,
804 (1974). 3. G. Dahlquist and A. Bj6rck, Numerical Methods, Prentice-Hall Inc., Englewood Cliffs, N.J. (1974). 4. R. K. Sampson and H. Z. Massoud, to be published. 5. F. L. McCrackin, NBS Tech. Note 479 (1969). 6. K. H. Zaininger and A. G. Revesz, RCA Rev., 25, 85 (1964). 7. D. E. Aspnes, J. Opt. Soc. Am., 64, 639 (1974). 8. E. Schmidt, J. Opt. Soc. Am., 60, 490 (1970). 9. R. H. Muller, Surf. Sci., 56, 19 (1976). 581
A CYLINDRICAL TUBE BASED RAPID THERMAL PROCESSOR D. T. Chapman*, J. M. Melzak**, M. J. Fordhamt, J. J. Wortman**, M. C. Oztiirk**, and F. Y. Sorrellt North Carolina State University College of Engineering * Department of Materials Science and Engineering
Box 7907, Raleigh, NC 27695-7907
"**Department of Electrical and Computer Engineering Box 7911, Raleigh, NC 27695-7911 tDepartment of Mechanical and Aerospace Engineering Box 7910, Raleigh, NC 27695-7910 ABSTRACT A cylindrical tube based rapid thermal processor has been designed and fabricated for the purpose of rapid thermal chemical vapor deposition (RTCVD). This geometry is conducive to improved coldwalled operation. The reactor resembles a conventional LPCVD system, except that the heating is provided by tungsten-halogen lamps and the exterior of the quartz tube is air cooled. Thermal modeling has been used to simulate the radial temperature variation across the wafer.
INTRODUCTION Rapid thermal processors have been designed primarily for the purpose of annealing radiation damage and activating dopants in implanted wafers. They have also been used for glass reflow, silicide formation, and oxidation [1]. In general, these systems operate at atmospheric pressure with no special effort being made to ensure coldwalled behavior. The most common approach has been to utilize steel chambers with flat plate quartz windows (for coupling radiation from the lamps to the wafer) and perpendicular flat lamp banks (outside the chamber) both above and below the wafer. This configuration has two major drawbacks for low pressure operation. First, it is very difficult to achieve temperature uniformity across a wafer without complex lamp contouring and/or clever arranging of lamps, reflectors, and absorbers. This problem is compounded because the wafer radiates more thermal energy at its edge; thus, very nonuniform incident radiation is required to minimize temperature gradients in the wafer. Second, for large wafers and low chamber pressures, the quartz windows must be quite thick (- 0.5") to mechanically withstand the pressure differential. This required thickness causes additional problems: the windows absorb radiation from the direct lamp source, reflections within the chamber, and the hot wafer. Since the total absorption may be 582
significant, cooling of the inner surface of these windows may be impossible even if the outer surface is kept cold. The reasoning behind the cylindrical configuration and the associated design issues are discussed and thickness maps of rapid thermal silicon oxidation (RTO) and RTCVD polycrystalline silicon thin films are presented. SYSTEM DESCRIPTION System Design The NCSU cylindrical tube based rapid thermal processor is a multiprocess research tool for single wafer processing of 4" silicon wafers. The system was designed for process purity and ultra high vacuum applications, utilizing all oil-free pumps and capable of 10-9 Torr base pressure when baked. Any processing series combination of rapid thermal cleaning (RTC), RTO, RTCVD, and rapid thermal annealing (RTA) can be performed in a wide variety of ambients over a wide range of pressures (10-9 to 760 Torr) and temperatures (> 1200 °C). This processing flexibility permits novel research, particularly that dealing with multistep in-situ device processing. Throughout the design and construction phases, careful attention was paid to the ergonomics of system operation and maintenance, yielding a very stable yet flexible platform in which to conduct integrated processing research. This system has advantages over conventional flat plate reactors, which are a consequence of deliberate engineering design and natural symmetries. In the following discussion, individual parts of the system will be identified according to numbers in parentheses (X), which refer to the system schematic in Figure1. Chamber Design In reviewing potential chamber configurations, a standard LPCVD furnace tube with several modifications has been chosen. The tube (1) is constructed of quartz to maximize transmission of the incident radiation. In RTCVD, the chamber's sidewalls must be kept cold to prevent deposition from occurring on these surfaces. The circular cross-sectional geometry of the chamber permits the use of a minimum thickness quartz tube sidewall since the glass is always under compression. With a quartz thickness of 5mm, the chamber's interior sidewalls can easily be kept cool by passing a high volume of air over the tube's outer surface. Since the entire chamber is constructed of quartz, the lamp power can be effectively coupled to the wafer-, this allows the manipulation of lampwafer angles as well as lamp-reflector geometries to optimize temperature uniformity. An optical quality quartz viewport (2) is fused into the tube's end to facilitate pyrometric temperature measurement. Gas injection occurs through a fused quartz to metal seal (3), maintaining UHV integrity. Utilizing a quartz chamber of any substantial volume attached rigidly to a metal chamber or fitting generates several tricky mechanical support and constraint issues which are described in later sections. Another benefit derived from the use of a quartz tube reactor is the considerable documented experience with its use as a LPCVD reactor [2].
583
0
I• 0•
U,
UJ
U
z_
584
Furnace Design A lamp arrangement was selected in which 32 1500 Watt tungsten halogen lamps are arranged radially in a stainless steel shroud (4). The properties of such lamps can be found elsewhere [3]. The shroud is gold-plated for high reflectivity, is both water- and air-cooled, and houses the recessed ceramic lamp electrical connectors. The lamps are aligned parallel to the quartz tube and arranged radially around its surface at a distance of 4.75" from the wafer center and at a spacing of 0.93". Maximum process temperature is in excess of 1200'C. The wafer can be held parallel to, normal to, or at 45* or 70* from longitudinal axis of the tube. More will be discussed about this later. Power is supplied via a computer controlled phase angle SCR firing on the primary of a step down transformer and has an upper limit of 48kW. The lamps are individually fused and fired in parallel. Individual lamps can be removed from the circuit to aid in controlling the temperature profile in a wafer, depending on the angle of the substrate holder chosen. Temperature control is implemented using open-loop power v/s time control or closed loop pyrometer feedback power v/s time control. Pyrometer and openloop control are calibrated via a silicon wafer with a thermocouple mounted in the center. A real-time closed-loop emissivity-corrected pyrometry PDPI control routine has been implemented to optimize temperature profiles. Vacuum Design The processor has been designed for ultra high vacuum applications. With the exception of the quartz-to-metal chamber seal, all other seals are metal-to-metal with copper gaskets. The connection between the quartz tube and the metal vacuum flange is made by a differentially pumped double viton O-ring seal onto a water cooled stainless steel flange (5). This provides a positive sealing force even when the pressure within the chamber exceeds one atmosphere. All vacuum components and pumps are located on one side of the quartz tube, with only the 1/2" flexible gas inlet port on the opposite side. This greatly simplifies alignment of the stainless steel to quartz connection. Vibration damping is utilized wherever possible to minimize the vibration transmitted to the tube. The quartz chamber is essentially cantilevered off the end of the pumping column with adjustable mechanical supports along the tube to facilitate thermal expansion and contraction. The chamber is loadlocked for process purity (6) and wafer loading is performed by a magnetically coupled transport arm (7). The system employs a combination of oil-free pumps which enables flexibility in processing pressure. A Seiko-Seiki STPH-200C turbomolecular pump (8) serves the main process chamber as the UHV pump and is backed by a Danielson Tribodyn 500 (9) or an Edwards Drystar 40 mechanical pump (10). The Drystar 40 is the main process pump for RTCVD applications. An Alcatel Drytel 30 molecular drag pump (11) is used to pump the loadlock chamber. With this combination the system is capable of operation between 760 and 10.9 Torr. Many gases are available: N2 , Ar, H 2, 02, N2 0, NH 3, SiH 4IAr, SiH 4/IH2 , GeH 4 , B2 H 6, and SiCl2 H2 . Point-of-use process gas purification and mass flow control are employed on the inlet gas lines (12). Ultra pure oxygen and argon sources have been supplied by Air Products for oxidation and annealing studies. A Kintek moisture generator and Meeco analyzer are available to allow incorporation and
585
detection of trace amounts of water vapor (parts per billion) to be introduced into the gas stream for research purposes. Pressure measurement is accomplished by an array of ion gauges, convectron gauges, and capacitance manometers (13). Low process pressures for CVD (< 100 Torr) are controlled by a VAT closed-loop feedback butterfly valve (14); a near atmospheric exhaust pressure regulating system (15) is used for oxidation and annealing near atmospheric pressure. A Leybold Inficon Quadrex 200 residual gas analyzer is used for monitoring process purity and leak checking (16). THERMAL MODEL The cylindrical furnace was modelled to predict the distribution of the temperature in a wafer heated by lamp radiation and convectively cooled by process gases. Lamp radiation from the shroud was modelled via a ray-tracing approach. The resulting irradiance on the wafer surface was coupled to a finite-difference model of diffusion of heat in the wafer. Gas cooling was calculated by using the buoyant flow velocity produced by wafer heating of the gas (natural convection) to compute a convective heat transfer coefficient. Flow velocities were taken from a computation fluid dynamics (CFD) analysis of the flow in the furnace. Here the commercial CFD program FLUENT was used to compute the flow field [4]. The shroud model utilizes a ray-tracing approach to compute the irradiant distribution of power onto the wafer from direct and specularly reflected lamp illumination. Each lamp is treated as a blackbody line source of length equal to the active filament area. Effects of the quartz tube and lamp housing on the spectral distribution of emitted power are not considered. Therefore this model provides only information about relative irradiance with respect to reference irradiance at the wafer center. The lamp is divided into a number of segments determined iteratively using a convergence criterion. Rays are generated from each segment in even increments in local polar and azimuthal angles. All rays emanating from a segment originate at the segment center. The power Pr associated with any ray is simply the power from cylindrical segment length ds into solid angle increment dw: Pr= Tf4 rf cosO ds dw dw = cosO dO dcp (2) where Tf and rf are the temperature and radius of the filament, respectively. Each ray strikes either the wafer, the cylindrical wall, the annular furnace sidewalls, or escapes the furnace. Surface normal n at intersection point p(r,0,z) and incident ray direction i uniquely determine reflected ray direction r: 3
3
Xrkn knk W
(3)
W-I
ri = ii - 2jiknk k-I (4) Power assigned to the reflected ray is attenuated based on the reflectivity of the intersected surface. Optical paths through the quartz tube and resulting attenuations can
586
I
be accommodated via this method; however, they are not currently modelled. The wafer is divided into radial and azimuthal increments. These grids are utilized in the finite difference solution of the heat diffusion equation for the wafer. Any ray intersection with the wafer yields additional power to a particular grid element. Notice that radiation incident on the surface of the wafer edge is not modelled. Convergence checks using large numbers of rays are necessary to assure that all power from a particular ray lands in a single grid. The wafer is modelled as a homogeneous isotropic solid with temperaturedependent thermal properties, for which the general heat diffusion equation becomes: V. [kVT(i,t)] + g(i,t) = p C aT(it)
at (5) The wafer is assumed to be two-dimensional, implying opacity to radiation from the lamps. Boundary conditions of radiation and convection on the top and bottom surfaces of the wafer become an equivalent source term in equation (5): 4 l[I(r,T,t) + Q,(r,(p,t) + oaT (r,Cp,t)] (6) where I is the total irradiance from the lamps to the wafer, Eo"T4 is the radiant heat loss, Qc is the heat flux lost by convection to the process gas, and z is the wafer thickness. Because the model is two-dimensional, conduction from the edge of the wafer must be approximated. If the edge geometry is treated as the frustrum of a cone, and the edge temperature is assumed to vary only with (p, an approximation to radial heat flux results [5]: 4 eeoT(Rqp) "_kI
g(r,p,t)
=
r-R
sin 0,
(7)
A fully explicit finite difference technique is applied to equation (5) with boundary condition (7), using derivative estimates accurate on the order of Ar2 and AWp2 in the wafer grid. Transient solution steps have errors on the order of At, but the accuracy of the steady state results is independent of time step. The FLUENT CFD package is used to develop velocity profiles used in calculating the convective heat transfer coefficient, which is then used to calculate Qc in equation (6). This approach decouples the momentum and energy equations for fluid transport from the wafer heat diffusion equation and therefore is applicable only for steady-state solutions. Iteration is required between the calculated Q, and the finitedifference solution to equation (5) for a converged solution. Therefore the results presented here are only a first approximation to solution of the coupled systems. Rapid thermal oxidation was modelled at 1000'C and atmospheric pressure with the wafer in a vertical position. The quartz tube was modelled as an isothermal 75°C cylinder which was shortened to assist in convergence. Temperature profiles resulting from the application of lamp and convective heat flux to the wafer model are shown in Figure 2a. For low pressure processes, the heat loss due to convective heat transfer is much smaller than the radiative heat loss [6, 7]. In this case the only loss mechanism in equation (6) is the radiant heat loss. Consequently, the temperature contours shown in Figure 2b (RTCVD polysilicon) are not influenced by the gas flow in the furnace.
587
(a)
0 :5
(•) 0 0 (-~)
-5
x
" 5
"
.1 5
(b)
5
0 x (ca)
5
Figure 2. Thermal models of wafer surface temperature: (a) Rapid thermal oxidation at 1000'C and 760 Torr, and (b) RTCVD of polysilicon at 7001C and 5 Torr. Contours represent 20 C intervals. Maximum temperature contour is dashed; maximum temperature is 1064°C in (a) and 728'C in (b). 588
EXPERIMENTAL Rapid thermal oxidation of silicon was performed at 760 Torr in dry oxygen for different times, preceded by standard wet chemical cleaning. Wafer edge to lamp angles of 90', 450 and 0' were used. Oxygen flow rates were either 0 or 2 SLPM. Rapid thermal CVD of polysilicon was also performed with wafer edge to lamp angles of 900 and 00. The flow rate of 10% silane (in argon) was 0.3 SLPM, pressure was 5 Torr, and deposition time was 60 seconds. Rapid thermal CVD of silicon dioxide was performed in a LEISK flat plate reactor (with no lamp contouring) as a reference [8]. Film thickness was mapped using a Rudolph AutoEl Ellipsometer, measuring 100 points per wafer. Experimental data are correlated to thermal models. Maps for five wafers are shown in Figure 3. Thickness nonuniformity is calculated as the ratio of the standard deviation (of 100 measurements) to the average thickness. Thickness measurements are accurate to ± 2A. Wafer A was oriented vertically (900) with 56A of oxide grown at - 950'C and atmospheric pressure for 112 seconds. Oxygen flow was 2 SLPM. This wafer has the highest nonuniformity 15.7%. It exhibits the additive effects of worst case convective cooling, wafer-wafer holder conduction, and shadowing. Gas cooling effects, however, were minimized in this orientation. Thermal modeling of this case is shown in Figure 2a. Note the downward shift of the bullseye and the higher temperature at the edges, both of which are appear in the thickness map. Wafer B was also oriented vertically, and received deposition of 511A of polysilicon at - 650'C and 5 Torr for 60 seconds. Thickness nonuniformity is best at 5.9%. This wafer is affected primarily by wafer-to-wafer holder conduction and to a lesser extent by shadowing. Since convective and gas cooling mechanisms are ineffective in this pressure regime, this wafer was the most uniform as expected. Thermal modeling of this case is shown in Figure 2b. Note the centered bullseye and the higher temperature at the wafer edge, both of which correlate with the experimental film thickness map. Wafer C was oriented at 45'. Rapid thermal oxidation was performed at - 980TC and no oxygen flow, yielding a 53A film in 120 seconds. The thickness nonuniformity of this wafer was the lowest of the RTO wafers - only 6.4%. By orienting the wafer at 450 relative to both the lamps and the gas flow, the effective furnace radius is increased for the wafer's top and bottom edges along with reducing the gas cooling effects - both of which significantly improved the uniformity over wafer A. In addition, several of the side lamps were extinguished to extend the virtual furnace radius effect to the wafer side edges. Wafer D was oriented horizontally (00) and was deposited with 871A of polysilicon at 700'C and 5 Torr for 60 sec. The thickness nonuniformity of this wafer was worse than wafer B - 11.8%. Wafer D is affected by gas cooling and demonstrates a characteristic valley in the direction of gas flow. Rapid thermal CVD of silicon dioxide (wafer E) was performed as a reference in a LEISK flat plate reactor at 950'C for 60 seconds and 8 Torr. This reactor has two perpendicular lamp banks above and below the wafer, no lamp contouring was used [8]. Notice that the film is much thinner at the edge of the wafer. Nonuniformity of this wafer was 26.8%, over four times higher than the best case film grown in the cylindrical system.
589
TO "Kin
(a)
(b)
(c)
ax TO
41.6 107.6
Avg TO
56.1
Std Dev
8.8
Min TO
446.6
Max TO
562.6
Avg TO
511.0
Std Day
36.6
Kin TO
48.8
Max TO
66.6
Av TO
53.3
Std Den
3.4
PilnTO
(d)
612.0 1669.8
Max TO
071.4 0
Avg TO Std Dev
:
Kin TO
(e)
63.0
168.0
Man TO
515.8
Avg TO
374.6 3
Ltd
Den 1
180.3
Figure 3. Ellipsometric maps of film thickness: (a) Rapid thermal oxide oriented vertically, (b) RTCVD polysilicon oriented vertically, (c) Rapid thermal oxide oriented at 450 angle, (d) RTCVD polysilicon oriented horizontally, and (e) RTCVD oxide grown in Leisk system. 590
CONCLUSIONS A cylindrical tube based rapid thermal processor has been designed and fabricated with the goal of investigating its usefulness in research and manufacturing applications. Results indicate that the cylindrical configuration has the attributes of cold-
walled operation and a high temperature ceiling (> 1200'C); it has also been made ultraclean through the use of oil-free pumps. The wafer can be held in any position from horizontal to vertical. Temperature uniformity is a strong function of this orientation. By removing lamps, the temperature profile can be modified. In this manner, it is possible to achieve better uniformity than in simple flat plate reactors. Thermal models have been developed to simulate the RTP system. These models were used to verify experimental results obtained from rapid thermal oxidation and RTCVD of polysilicon. They also indicate that creative lamp holder and reflector design can lead to optimal uniformity control. ACKNOWLEDGEMENTS The authors would like to thank the following individuals for their assistance: Jim Futrell, John Clarke, and Joselito Sarreal - Microelectronics Center of North Carolina; William Kiether and Chris Beasley - NCSU/ECE; Arthur Illingworth, Jim Emerick, Rick Lamy, Tony Mason, Jeffrey Nifong, Doron Strassman, and Marvin Strickland of the NCSU Engineering Research Instrument Shop. This work has been partially supported by the NSF Engineering Research Centers Program through the Center for Advanced Electronic Materials Processing (Grant # CDR8721 505), the North Carolina SEMATECH Center Of Excellence (Contract # 88-MC-809), and SRC Manufacturing Science Program (Grant # 88-MP-132). REFERENCES IR. Singh, J. Apple. Phys. 63, R59 (1988), and references therein. 2S. Wolf, R.N. Tauber, Silicon Processingfor the VLSI Era, Lattice Press, Sunset Beach California, 1986. 3 F. Roozeboom, N. Parekh, "Rapid thermal processing systems: A review with emphasis on temperature control", J. Vac. Sci. Technol. B8 (6), Nov/Dec '90. 4 Creare.x, Inc., Etna Road, P.O. Box 71, Hanover, NH, 03755. 5 C. Hill, S. Jones, and D. Boys, Proc. NATO ASI series B Vol. 207, "Reduced Thermal Processing for ULSI" p. 143, 1988. 6 F. Y. Sorrell, C. P. Eakes, "Temperature uniformity in RTP furnaces", Rapid Isothermal Processing, Rajendra Singh, Editor, Proc. SPIE 1189, pp. 55-63, 1990. 7S. A. Campbell, K. H. Ahn, K. L. Knutson, B. T. H. Liu, and J. D. Leighton, "Steady State Thermal Uniformity and Gas Flow Patterns in a Rapid Thermal Processing Chamber", IEEE Trans. Semicond. Manufact., vol 4, p. 14, 1991. 8 F. S. Johnson, R. M. Miller, M. C. Oztiirk, J. J. Wortman, "Characterization of LPCVD silicon nitride in a rapid thermal processor", MRS Proc., Vol. 146.
591
DIELECTRIC PLANARIZATION PROCESS FOR ULSI Chiu H. Ting Intel Corporation 3065 Bowers Ave. Santa Clara, Calif. 95052-8126
This paper presents an overview of the recent progress and innovation in the area of dielectric planarization for ULSI. Since there is a tremendous amount of information published recently describing a variety of approaches, only the more commonly practiced approaches will be discussed. For example, recent advances in the AP-TEOS/0
3
deposition process have
demonstrated good gap filling capability for high aspect ratio submicron gaps. Progress in thermally reflowable spin-on polymer could provide significant improvement over the standard resist etchback planarization process. Materials and process improvements have made the non-etchback SOG planarization process possible. The chemical mechanical polishing process has demonstrated superb planarity over a wide range of surface topography and provided the feasibility of global planarization.
INTRODUCTION: As device dimensions are scaled into sub-micron region, the performance of ULSI chips are often limited by inter-connection capabilities. Multi-level metallization is required to provide the interconnection between the millions of devices on a chip. However, the topography generated by the accumulation of multiple deposition and etching cycles is detrimental to high resolution lithography and etching processes. Surface topography is also the cause of many reliability problems such as metal step coverage, electromigration and device integrity issues. Therefore, a planarized dielectric layer is a requirement for high performance multilevel interconnections. There is a tremendous amount of information published on this subject describing different approaches to improve the planarity of dielectric surface for subsequent processing [1], [2]. Recent progress of the more important approaches will be discussed below.
592
DIELECTRIC DEPOSITION: In order to planarize the deposited dielectric layer over severe topography, the deposited dielectric layer must be thicker than the required final film thickness since a significant portion will be removed by the planarizing process. Furthermore, the thick deposited dielectric layer must be free from defects. A common problem is the formation of voids or key holes in gaps with high aspect ratio as illustrated in Fig. 1. The CVD technology used to deposit gap filling dielectric layer was originally based on the oxidation of silane. Silane oxide, however, does not give very conformal coating over topography. The non-conformed silane oxide film often results in the formation of cusps and voids in gaps with aspect ratios of 0.5 or larger. The development of CVD TEOS/oxygen process has greatly improved the conformality of the deposited oxide. However, due to the temperature limitation of aluminum, PE-CVD TEOS/oxygen must be used instead of the high temperature thermal CVD TEOS/oxygen process. The oxide deposited by PE-CVD TEOS/Oxygen process still gives improved conformality over the silane oxide [3]. However its conformality is not ideal, typically less than 75% in small spaces. To improve the step coverage, the LPCVD of thermal TEOS/ozone was developed. Thermal TEOS/ozone film gives nearly 100% conformality and is therefore, capable of filling gaps with nearly vertical profile [4]. The dielectric films deposited by the thermal TEOS/ozone process tend to be rather porous and may absorb a significant amount of moisture [4]. Therefore it is common to use it in the dep/etch process so that the bulk thermal TEOS/ozone film is etched away leaving this film only in the gap filling area [5]. The step coverage capability and the dielectric quality of the TEOS/ozone films can be improved by increasing the deposition pressure. The deposited TEOS/ozone films at or near atmospheric pressure using high ozone concentration tend to be thicker at the inside corners of a gap, thus giving a rounded or "reflowed" profile over a step [6], [7]. This is opposite of the cusp formation over a step in standard CVD dielectric films. Furthermore, these AP-TEOS/ozone or SA-TEOS/ozone films tend to be denser and absorbs less moisture than TEOS/ozone films deposited at low pressure [8], [9]. The step coverage capability of the AP-TEOS/ozone dielectric films for a sub-micron gap with an aspect ratio of approximately 2 is illustrated in Fig. 2. However, AP-TEOS/ozone film deposited with high ozone/TEOS ratio tend to be surface sensitive [6] as well as pattern density sensitive. This would make the step coverage vary with different surfaces and pattern densities, as illustrated in Fig. 3. The capability of the AP-CVD TEOS/ozone deposition process to fill submicron high aspect ratio gaps or re-entrant profiles could provide significant simplifications to the planarization processes for future ULSI structures. However, the deposition mechanism as well as the film quality are not yet well understood. It would require careful study before these AP-TEOS/ozone films can be used with consistent reproducibility.
593
Void Formation
Fig. 1:
Void
Void formation in deposited oxide.
Fig. 2:
Deposited AlP TEOS/ozone film filling submicron gap with an aspect ratio of approximately 2. 594
Fig. 3:
Step coverage of AP-TEOS/ozone film over Al lines with different pattern density. 595
ETCHBACK PLANARIZATION PROCESS:
The resist spin-on and etchback process were developed to provide a low temperature planarization process [10]. This process is based on the planarization capability of photoresist which is coated in liquid form over topography surface by spinning the wafer at high speed. The nearly planar surface of the photoresist is transferred to the underlying dielectric film by using a dry etching process, such as plasma or reactive ion etch process, that etches the photoresist and the dielectric layer at nearly equal rates. The etching process is continued until all the photoresist is removed so that the smooth photoresist surface contour is transferred into the dielectric film. This process has been widely used to planarize dielectric layers over A] metallization. However, the degree of planarization depends not only on the resist coating thickness but also on underlying geometries. Good planarity is obtained only for small closely spaced patterns [11],[12]. The planarity degrades rapidly when the pattern width or gap width exceeds several microns. This problem is reduced by using an additional photolithography step to fill in the large gaps with dummy patterns so only small gap geometries remain before coating the second planarizing photoresist layer [13]. This increases the process complexity due to additional photolithography and design complexity since the dummy pattern must be designed to fit a specific pattern and process [14]. The surface planarity of the spin-on layer can be greatly improved if the spin-on polymer layer is thermal flowing rather than thermal setting such as that of novolac resins used in common photoresists. By using a thermal flowing polymer for the spin-on layer, sufficient planarization can be achieved over geometrics as large as several hundred microns as compared to only a few micron when standard positive photoresist layer is used [16]. This is illustrated in Fig. 4. Since the planarization capability of this new thermal flowing polymer exceeds the largest pattern geometry the dummy photoresist pattern and second planarization photoresist coating may no longer be needed, thus greatly simplifying the etchback planarization process. Final planarity of the dielectric surface is also critically dependent on the etchback process. The commonly used 6ne to one etch rate between the polymer film and the dielectric film, as determined by test wafers, does not provide good planarization due to local loading effect. The local loading effect causes the polymer etch rate to change as more dielectric surface is exposed during the etching process [15]. This must be compensated in order to get good surface planarity. The etchback process using the new thermal flowing resin against SiON dielectric was optimized in a hexode RIE system. An etch ratio of 1.2 to 1 was used planarize the surface topography for both small geometries as well as for large geometries [17]. The results are illustrated in Fig. 5.
596
0
s0
100
200
150
250
FEATURE DIMENSION (urn)
Fig. 4:
of PC2-1500 and Planarity photoresist AZ-1370 after 200"C bake for 2 minutes.
Fig. 5:
SEM cross section to show dielectric surface planarity over 200 um Al pattern after PC2-1500 etchback process 597
SPIN-ON GLASS:
The resist spin-on etchback process can be simplified if the spin-on material can be used either as a stand alone dielectric layer or in conjunction with CVD dielectric films. For this reason, a lot of efforts have been made to study the feasibility of using spin-on polymide film (PI) as the dielectric layer [181. Although PI has good dielectric characteristics as well as good thermal stability, its use as a stand alone dielectric layer for VLSI as not yet been accepted. This is because polyimide is an organic polymer and its properties differ significantly from the CVD oxide films. Many process compatibility issues also need to be resolved before PI can be used to replace CVD dielectric films. A more compatible material could be the spin-on glass (SOG) films [191, [20]. There are many different types of SOG materials such as silicates, doped silicates and a variety of polysiloxanes. They can be coated from liquid to give a spin-on film with good surface planarity. SOG films can be cured at relatively low temperature to give a silicon dioxide like film. However, the film properties depend on the starting material and the curing conditions as well 'as subsequent processing conditions [21]. In general the density of SOG layer is lower than the thermal oxide and it cracks easily for thick layers. It is, usually used in conjunction with other CVD dielectric layers. A partial etchback process is generally used to remove SOG from the via opening areas [22], [23] to avoid excessive moisture absorption in the process SOG films. The moisture content of a typical silicate SOG has been determined by Wolters et.al. [24] by using mass spectroscopy to measure the thermally desorbed gas in a UHV system. The primary contaminant is water as illustrated in Fig. 6. This is because the silicate SOG film cured at low temperature is rather porous and can absorb a large amount of moisture. The porosity of the film can be reduced if the SOG is densified at high temperature (ie. 900°C) which is not acceptable for aluminum. Another way to reduce the porosity is by using siloxane material, which have organic groups such as methyl or phenyl groups built on to the end of silicon-oxygen chain to relieve film stress and to reduce moisture absorption. With proper material choice, the moisture absorption of a siloxane film can be reduced to negligible amount. This is illustrated in Fig. 7, where the amount of thermally desorbed gases from a siloxane SOG film were measured in a UHV chamber [25]. The water content from a properly cured siloxane film as shown in Fig. 7 was found to be negligible and the water content of this SOG film was found to be very low even when the film was subject to Ar sputtering and then soaked in water. The water absorbed was found to be comparable to absorbed Ar gas due to the sputtering process. The integrity of organic containing the siloxane films is destroyed by oxygen plasma, such as those commonly used for organic resist strip. The Siloxane film with organic group partially removed by oxygen plasma is very porous, and it cracks easily and absorbs a large amount of water. Therefore, the oxygen plasma
598
-STE'-nz TharlW S4
I.,
U0
W80 000
000
35a
(o c) -1
600 B20
C02
II ii
..
.
10
I I
f 'I LI
20
o
6
60
0
100
U0
-28TIME(M..,)
Fig. 6:
Partial pressure of absorbed gases from a cured silicate SOG film (ref. 24).
OUTGASSING OF CURED SOG Intensity (arb. units)
a) C) Argon (Alter Sputter)
0
|00
200
b), c)
b)
Water (After Sputter)
a)
Water (Alter Cure)
300
400
Temperature (C) Fig. 7:
Water from as cured film.
Partial pressure of desorbed gases from a cured siloxane SOG film.
599
500
Water and Ar from cured SOG film after subject to Ar sputter etching and then soaked in water.
steps must be either eliminated if the siloxane film is to remain on the wafer surface such as that used in the non-etchback SOG planarization process. Otherwise the siloxane film must be protected from the oxygen plasma by a using dense capping layer over the SOG film. If the siloxane film can not be completely protected from the oxygen plasma, the moisture absorbed in the expose region can be removed by a high temperature baking step (ie. 450'C) immediately before subsequent processing. This is illustrated in Fig. 8 with proper care in the processing sequence, the non-etchback SOG process using siloxane film can give good surface planarity as well as via integrity. This has been demonstrated by high via chain yield, shown in Table I from data obtained by C. Ting et.al. [251 and shown in Fig. 9 from data obtained by R. Wolters et. al. [24]. TABLE 1 Comparison of via chain yield of a non-etchback SOG process using dehyration bake and in-situ Ar sputter clean to control wafer without any planarization process
SOG Wafer
Control Wafer Via Resistance (mo hm/via)
95 +/- 10
79 +- 5
Yield of via chain
78%
100%
Number of total vias
19.44K
19.44K
Number of via chains
18
18
Post-via annealing jn 450 °C, N2
30 min.
30 min.
600
I
a)
Fig. 8:
FTIR measurements of water content in cured siloxane SOG film: a) b)
D3
0.9s
c)
0.95 0.9 0.8 0.7
As cured film Film in (a) after oxygen plasma resist strip. Film in (b) immediately after 30 min. anneal at 450°C in dry N2.
0.5 0.1 0.3 0.2 0.1 0.05 0.01 0
2 String
4 resistance
6
B
>10
[Ohms/section)
Fig. 9:
Via string resistance fabricated With non-etchback siloxane SOG planarization process using in-situ pre-heat prior to sputter etching 601
DEP/ETCH PLANARIZATION PROCESS:
A physical etching process, such as sputter etching has an incident angle dependent etch rate. It generally has a lower etch rate for flat surfaces than sloped surfaces. Therefore, physical etching process can be used to remove sharp corners to give a smoother surface [26]. Using repeated etching and deposition cycles, planarized surface can be obtained over small dimensions. To reduce wafer handling for repeated dep/etch cycles, several equipment manufacturers have developed automated systems that combine etching and CVD deposition processes into a single system. By using different combinations of deposition and etching cycles one can obtain various degree of planarization in the final dielectric layer surface. The well known AMP-5000 system uses plasma TEOS for the main dielectric layer. However, plasma TEOS does not have sufficient step coverage for tight geometries. Therefore, it is used in conjunction with thermal TEOS/0 3 to provide the needed step coverage. Unfortunately thermal TEOS/0 3 has rather poor dielectric properties (i.e. high water content as mentioned previously) so an etchback process is used to remove most of the film leaving only pockets of thermal TEOS/0 3 in the gaps to provide a planarized surface. This dep/etch process used to planarized intermetal dielectric layers as reported by Pennington et.al. [5] is illustrated in Fig. 10. The ultimate deposition and etching process is to create a single process where the deposition and etching processes are carried out simultaneously. This is accomplished in the biased-sputtered quartz or BSQ process [27]. Although the BSQ process has been used extensively, it suffers from low throughput because much of the sputtered deposited film is etched away. This short coming can be improved by using more efficient plasma sources such as the electron cyclotron resonance (ECR) process. In the ECR process, the plasma is generated at microwave frequency in resonance with the electron motion so that dense plasma can be generated even at very low pressure. When compared to the BSQ, the ECR process is capable of higher deposition rate and less radiation damage. It is, therefore, more suitable for planarizing surface topography with high aspect ratios. Similar to the BSQ process, the degree of planarization obtained with biased ECR deposition changes with pattern sizes. This is illustrated in Fig. 11 [28]. CHEMICAL/MECHANICAL POLISHING: Truly global planarization can be obtained by using either mechanical lapping or chemical-mechanical polishing. Lapping is a purely mechanical process. It is difficult to control precisely and it may be too harsh for some applications. Chemical-mechanical polishing is a combination of chemical and mechanical processes [29]. The chemical part of the process can used to optimize process control or to obtain large differential polish rates for different materials [30] [31]. The chemical-mechanical polishing process has demonstrated the capability of providing planar surface over very large dimensions, thus giving the possibility of planarizing the entire wafer surface instead of localized smoothing.
602
THCVD Oxide PECVD Oxiae
Metal
a) Wafer Post tst Metal Patterning
d) THCVD Oxide Deposition
PECVD Oxide
THCVD Oxide
b) Initial PECVD Oxide Deposition
e) Oxide Etchback
PECVO Oxide
c) Argon Sputter
f) Final PECVD Oxide Deposition
Fig. 10:
of a dep/etch Schematic planarization process in AMP-5000 (ref. 5).
with ECR depositea dielectric layer with Dias (ref. 28) )fl
Fr'1. a
603
SUMMARY As device dimensions are scaled into submicron region, multiple layers of interconnection are needed to provide the packing density and operating speed. Planarization techniques are essential to eliminate severe surface topography generated by repeated deposition and etching cycles. Although various planarization techniques for metal layers are being developed, they are focused on contact and via hole fillings. Therefore, the dielectric planarization process must provide over-all surface planarization for the deposition and patterning of next metallization layer. This requires a CVD-dielectric deposition process which is able to fill submicron gap with high aspect ratios. The current deposition/etch process as well as the newly developed AP-TEOS/ozone process are being refined to give this capability. The newly developed spin-on polymer that can be thermally flowed to give long range planarization over severe surface topography that should be able to extend the usefulness of the well established spin-on photoresist and etchback process. By optimizing the SOG materials and processing sequence, a non-etchback SOG planarization process based on thick siloxane layer has been demonstrated. This should simplify the commonly used partial etchback SOG process and extend the usefulness of SOG planarization process into deep submicron. Improved instrumentation such as ECR and improved film property such as SA-CVD or AP-CVD TEOS/ozone film should be able to extend the usefulness of the dep/etch process. The renaissance of the old chemical-mechanical polishing technology gives the possibility of achieving true planarized surface across an entire chip or even across an entire wafer.
REFERENCES
1.
V. Comello, Semiconductor International, p. 60, Nov. (1990).
2.
Proceedings of VLSI-Multilevel Interconnection conf.(1986, 1987, 1988, 1989, & 1990).
3.
B.L. Chin, E.P. VandeVen, Solid State Tech., p.119, April, (1988).
4.
S. Nguyen, et.al., J. Electrochem. Soc., _37. p. 22 0 9 (1990).
5.
S. Pennington, et.al., Proceedings of V-MIC conf. p.335, (1989).
6.
Y. Nishimoto, et.al., Proceedings of V-MIC conf. p. 382, (1989).
7.
K. Fujino, et.al., J. Electrochem. Soc., 138, p.550 (1991).
8.
H. Kotani, et.al., Tech Digest IEDM, p. 66 9 (1989). 604
9.
P. Lee, et.al., Proceedings of V-MIC Conf., p. 396, (1990).
10.
A.C. Adams, C.P. Capio, J. Electrochem. Soc, 128, p. 423 (1981).
11.
R.H. Wilson, P.A. Piacente, J. Electrochem. Soc, 1M3. p. 981, (1986).
12.
LE. Stillwagon, et.al., J. Electrochem. Soc, 134, p.2030, (1987).
13.
DJ. Sheldon, et.al., IEEE Trans. Semicond. Manuf., _1.p.140, (1988).
14.
T.H. Daubenspeck, et.al., J. Electrochem. Soc, 138, p. 506, (1991).
15.
B. Vasques, R. Gardner, Proc. V-MIC, p.384, (1987).
16.
C.H. Ting, et.al., Proc. V-MIC, p. 491, (1989).
17.
P.L Pai, C. H. Ting, ECS Ext. Abst., 89-2, p.3 54 (1989).
18.
LB. Rothman, J. Electrochem. Soc, 127 p. 2216 (1980).
19.
F. Dupuis, et. al.,
20.
C.H. Ting, et.al., ECS Ext. Abst., 3.2, p.352, (1986).
21.
P.L Pai, et. al., J. Electrochem. Soc, 134. p.2829, (1987).
22.
J. Multani, et. al., Proc. V-MIC, p.292, (1986).
23.
D. Yen, G. Rao, Proc. V-MIC, p. 85, (1988).
24.
R. Wolters, et. al., Proc. V-MIC, p. 447 (1990).
25.
C.H. Ting, et.al., Proc. of ECS Multilayer Interconnection Symposium (1988).
26.
C.H. Ting, A.R. Neureuther, Solid State Technology p. 115, (Feb. 1982).
27.
C.Y. Ting, et. al., J. Vac. Sci. Tech. _15,p.1105, (1979).
28.
C. Chien, et. al, ECS Ext. Abst., 89-1, p. 260 (1989).
29.
T. Hamaguchi, et. al, Tech. Digest, IEDM, p. 688, (1985).
30.
IBM Technical Disclosure Bulletin, 29, No. 2, p. 577 (July 1986).
Symp. on VLSI Tech., p.52, (1985).
605
OVERVIEW OF PLANARIZATION BY MECHANICAL
POLISHING OF INTERLEVEL DIELECTRICS Srinivasan Sivaram, Robert Leggett, Alvaro Maury, Kenneth Monnig, and Robert Tolles SEMATECH Inc., 2706 Montopolis Dr., Austin, Tx 78745. ABSTRACT The need for extreme planarity in fine featured devices is presented. Lithographic requirements and the ability of various planarization techniques in meeting these requirements are reviewed. We show that chemical mechanical polishing is needed to obtain global planarity. Concepts behind material removal using a hertzian indentor are extended to the polishing process and the chemistry of glass polishing is presented. We also survey the state of the art in the polishing technology and highlight the areas which need improvement so that the process can be used in volume manufacturing. INTRODUCTION Lithography and etching of finely spaced, fine featured interconnect lines requires that the underlying dielectric be extremely planar. The planarity needs to be both local for stringer free etching and global over an entire stepper field for pattern resolution below 0.5 micron feature size. Whereas local planarity can be achieved by gap filling techniques, extreme planarity requirements on the global scale can be met, among the existing planarization techniques, only by processes involving chemical mechanical polish (CMP) (1). In this paper, we describe the need, the technology, and the limitations of chemical-mechanical polishing as a planarization tool. We review the scientific foundations of the art of glass polishing, as applied to thin films, and establish a framework for further experimentation. We provide an overview of the tools used in achieving the planarity and describe the problems one encounters in developing a stable, manufacturable process. NEED FOR GLOBAL PLANARITY The primary driver for extreme planarity, particularly at the interconnect level, is the desire to use optical lithography at less than 0.5 micron resolution. A key to this capability is the minimization of the exposure field depth. In Table I, depths of focus field of prospective exposure tools are listed. Part of these field depths is consumed by the substrate flatness and the device topology. Without planarization, a nominal 0.8um metallization will not be imaged by tools shown in the shaded region in Table I.
606
Many techniques including oxide reflow, resist etch back, spin-on-glass followed by an etch back, deposition-etch-deposition sequences, and electron cyclotron resonance oxide deposition have been used in semiconductor device processing to achieve planarity (2). The last two of the above mentioned techniques are used in filling narrow spaces with oxides and hence provide void free dielectric films. They are not expected to provide planarity at scales much larger than a micron. Reflow techniques, where thermal budgets allow their use, and techniques that use a low viscosity fluid to level the surface produce a rolling topography with a characteristic length of the order of 10 microns (3). However, CMP makes use of a stiff pad which bridges across topography and can planarize over ranges much greater than any of the above techniques. In comparing planarity, two figures of merit need be defined. The planarization range, R, is a relaxation distance at which the difference in height between the lowest and highest feature after planarization becomes equal to the original step height. The original step height is related to the range, R, by the side wall angle o. Figure 1 illustrates the two definitions. Gap fill techniques are characterized by extreme conformality and hence high side wall angles and low range. Local planarization techniques operate around 10 degree side wall angle and about 10 microns range. Global planarization applies to ranges greater than 1 mm (4). The capabilities of the different planarization techniques are summarized in Figure 2. Each of these techniques finds its application in specific situations. For commonly used step-and-repeat imaging systems, an image field is often about 15mm on a side. Hence, the true lithographic requirement on the planarization process is often defined over such a large distance. If one assumes that the depth of focus requirement was about 0.75 microns over the entire stepper field (from Table I), then it is seen that CMP is the only technique that can satisfy the requirements. OVERVIEW OF GLASS POLISHING Where as the art of polishing glass is ancient and is seen in various walks of life, the science of glass polishing is not well known outside of the very confined field of lens manufacture. An excellent review of glass polishing can be found in Reference 5. Mechanistically, removal rate, dr/dt, of a glass surface during polishing follows the Preston equation (6): dr/dt = Kp (ds/dt)
(1).
where p is the applied pressure, and ds/dt is the relative velocity between the glass surface and the pad. K, the proportionality constant, is termed Preston coefficient. The units of K, area/force, relate it to the mechanical properties of the glass. At the fine
607
polishing situations that are normally encountered in planarization, Preston coefficient is related to the Young's modulus and the hardness of the glass. It is only a weak function of the applied pressure and the relative velocity (7). During a brittle grinding situation macroscopic chunks of material are removed from the glass surface, whereas polishing is characterized by near surface interactions and removal of molecular clusters of material. Near surface interactions during polishing are very strongly influenced by the presence of water. Experimenters have shown that removal rate is negligible when the water in the slurry is replaced by organic solvents (8). The process of polishing is thought to occur according to the sequence described in figure 3: a. Formation of hydrogen bonding between the solvated oxide surface and the solvent in the slurry. The solvated oxide surface pertains to both the surface of the wafer and the surface of the slurry particles. b. Formation of hydrogen bonding between the solvated surfaces on the wafer and on the slurry particles. c. Formation of molecular bonding between the surfaces. d. Removal of the bonded wafer surface as the slurry particle moves away. The net reaction can be described as: =Si-O-Si= + H20 <--> 2=Si-OH
(2).
Polishing occurs when the depolymerization reaction proceeds faster than the polymerization reaction. The cleavage of the Si-O-Si below the wafer oxide surface is controlled by the diffusion of water through the oxide. The role of the slurry particle is to impart a chemical "tooth" to the polishing process. The strength of the bond between the slurry particle surface and the wafer surface determines the effective kinetic coefficient of friction between the two surfaces during polishing. Thus the chemical nature of the oxide dispersed in the slurry is crucial to the final oxide removal rate (9). Figure 4 shows the polishing rates for silicon dioxide using different slurry chemistries. Plotted on the x-axis is a measure of the single bond strength, normalized to the isoelectric pH (IEP) of the oxide. It is seen that cerium oxide results in the highest removal rate, followed by Zr and Ti oxides. However, for the planarization process, the choice of the slurry chemistry must be made not only based on the removal rate, but also on the planarity obtained, and the ability to distribute the particles effectively in a stable colloidal distribution.
608
TECHNOLOGY OF POLISHING A cross sectional view of a wafer with interconnect structures undergoing polishing is depicted in Figure 5. The wafer is pressed against a polishing pad saturated with an abrasive slurry solution. The polishing pad and the wafer surface are actively rotated against each other. This process preferentially polishes protruding topography. The key to the global planarization capability is that the polishing pad be sufficiently stiff to bridge the die level topography (10). The overall polishing interface, however, needs to conform to the net wafer contour to obtain die to die polishing uniformity. The chemistry of the polishing process was discussed in an earlier section. The most popular slurry used for dielectric polishing consists of colloidal silica in an aqueous KOH solution (11,12). The silica particles are flame produced and extremely uniform in size at a few hundred angstroms. Polishing pads most often used are either polyurethane impregnated Dacron felts or cast, filled polyurethane (13). Typical polishing machinery needs to actively control the down force, pad and wafer rotation rates, slurry feed rate, and polish temperature. In general, the commercially available tools tend to polish one or two wafers simultaneously (14). Typical dielectric polishing tools do not offer the process control needed for large batch processing. Status of the polishing process: Achievement of planarity with the polishing process is relatively simple. However, obtaining simultaneously, stable, high removal rates and uniformity across the wafer is more challenging. Removal rate falls off with age of the pad, causing process control problems. Table II summarizes the effects of various polishing parameters on some of the output parameters including removal rate, slope in removal rate, uniformity within wafer, planarity, and particles left behind on the wafer. It should be noted that these are general trends and the importance of the influence of each parameter is dependent on the specific conditions of the polish. i. Rate drop off: Figure 6 shows a typical polish rate curve as a function of the life of the pad. The removal rate continuously drops off after some initial instability. This drop off with pad life is due to plastic deformation of the pad surface and the resultant glazing. Pad glazing appears to result in two phenomena: a. the net area of contact between the pad and the wafer increases and hence the effective polishing pressure drops, b. the channels available for slurry transport to the interior of the wafer are blocked. Both of these result in rate reduction. However, it is hypothesized that the latter is a stronger phenomenon. Various means have been used in correcting for the drop off during device processing. Increasing polishing pressure has other negatives including loss of planarity
609
and higher drop off slope. "Pad conditioning" is considered the most likely solution to this problem. The conditioning process consists of some method of dressing the pad often through an abrasive process, so that the removal rate is raised back to its original higher level. Most of the work in the pad conditioning area is still in the developmental stage (15).
ii. Pattern sensitivity in removal rate: It has also been observed that an isolated small elevated feature on an otherwise flat topography polishes much faster than a dense array of elevated features. Large high areas polish the slowest. Hence, differing densities of features within a die can result in degraded planarity due to different removal rates (4). Such a pattern sensitivity in polishing degrades within-die uniformity and if uncontrolled might expose underlying layers in one portion of the wafer while leaving large under-polished regions in other parts. Figure 7 shows the amount of oxide removed on top of varying line widths in a test pattern. It is clear that wider the line, the slower the polishing rate over it. Localized polishing pressure variations and the above mentioned slurry distribution problems lead to pattern sensitivity of removal. The general guidelines in using CMP for ILD planarization are: a. isolated elevated features polish very fast and should be avoided, if exposed underlying layers are a concern; b. large spaces of the order of 500 microns do not cause problems for polishing (3), c. isolated lines will show enhanced removal close to the edges, and d. large elevated featureless plateaux will show removal rate inversely varying as their areas. iii. Other manufacturability concerns: a. Within wafer removal rate variations: Within wafer uniformity is thought to be dictated by two major factors during CMP: a. Slurry access as a function of distance from the wafer edge, which often results in bull's eye type patterns, and b. distribution of pressure through the wafer holding mechanism. Since polishing pad aging results in poor slurry distribution, it follows that uniformity degrades with increasing pad life. Slurry access problems are often counteracted by increasing or decreasing the relative velocity between the pad and the wafer, as a function of wafer radius. Proper adjustments of the two speeds can be effective in arriving at an acceptable removal rate uniformity (16). b. Post-polishing cleans: Most of the polyurethane and slurry debris left on the wafer after polishing can
610
be removed by rinsing in water. However, since particle requirements in VLSI processing are stringent, cleaning processes are more elaborate. Particle levels on the wafer tend to stabilize at a lower value as the pad ages, as shown in Figure 8. In this
case, the top surface of the oxide has been etched away using a dilute HF solution, and spray cleaned in deionized water. In order to get very low levels of particles, scrubbing using felt brushes, ultrasonic cleans, and polishing with water (but no slurry) on a different pad have been suggested. The choice would depend on individual requirements and compatibility to the oxide type. c. Measurement of extreme planarity: Since CMP produces side wall angles much smaller than a degree, measurement of planarity is not feasible using the commonly used techniques such as scanning electron microscopy. Many novel methods have been attempted, including interferometry, measurement of phase lag (16), and electrical techniques. Of these techniques, profilometry, and oxide thickness measurements are the two that have become popular due to ease of use and the availability of commercial equipment. CONCLUSIONS In this work, we have reviewed the current status of chemical-mechanical polish for achieving planarity of interlevel dielectrics. The need for the extreme planarity that can be achieved with CMP was illustrated. We presented concepts from the science of glass polishing that can be applied to the technology of CMP for planarization. It is clear from the status of the technology, that there is significant amount of developmental effort still needed before CMP can become a mainstream processing tool. Many manufacturability issues .still need to be addressed, including process stability, and metrology. However, the technology offers unique capabilities not matched by any other planarization method.
ACKNOWLEDGMlENTS The authors would like to express their appreciation for the excellent discussions that they had with Lee Cook of Galileo Optics and Norm Brown of Lawrence Livermore Laboratories. REFERENCES 1. B. Davari, et. al., Technical digest, IEEE-IEDM, 1989. 2. V. Comello, Semiconductor International, 13 (1990), p60. 3. M.E. Thomas, S. Sekigahama, P. Renteln, and J.M. Pierce, Proc. of IEEE-VMIC, 611
1990, p438. 4. T.H. Daubenspeck, J.K. DeBrosse, C.W. Koburger, M. Armacost, and J.R. abernathy, J. electrochem. Soc, 138 (1991), p506. 5. L.M. Cook, J. Non-crystalline Sol., 120 (1990) p152. 6. F. Preston, J. Soc. Glass Tech., 11 (1927), p 2 14 . 7. N. Brown, document MISC4476 (Lawrence Livermore Laboratory, CA, 1987). 8. T. Izumitani in "Treatise on Materials science and technology, Vol 17", Ed. by M. Tomazawa and R.H. Doremus, Academic Press (1979), p115. 9. W. Silvernail, Paper WBI-1, Techn. Digest, Topical meeting on Optical fabrication and technology, Optical Society of America, 1982. 10. P. Renteln, M.E. Thomas, and J.M. Pierce, Proc. of IEEE-VMIC, 1990, p57. 11. Rodel Inc., Rodel Surfacetech Review, Vol 1, Issue 7, 1989: 9495 East San Salvador Dr., Scottsdale, Az 85258. 12. Cabot corporation, Cab-O-Sil Division, PO Box 188, Tuscola, 11. 61953. 13. Rodel Inc., Rodel Surfacetech review, Vol 1, Issue 1, Dec 1986. 14. Westech Systems Inc., 3502 East Atlanta Ave, Phoenix, Ar. 85040. 15. Private communication, Westech systems. 16. J.J. Colacino and T.A. Bartush, Sol. State Technol, Aug 1973, p 30. 17. E. L. Church, and P.Z. Takacs, Optical Engineering, 24 (1985), 296; Wyco Corp, 1955 E. Sixth St., Tucson, Az 85719.
R
Resolution Wavelength .370
.240
S190
.8
1 .5
1 .3
DEPTH of FOCUS 2.2 0.7 .24
2.7 3.4
1.1 1.3
Plaonrizotion Reloyotion Distance. R The distance R traveled over 0 step whereupon the original step height topogrophy, or depth of field,
.38 .47
T, returns
R = T ctnl Set T= .8u, R=.8 ctn, 0 Sidewall Angle
Figure 1: Metrics of planarization
612
POLiIt4ING 8203 RESIST& ES
S....
SOG &/or E8
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REFLOW
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R
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10000 .03
GLOBAL
Figure 2: Comparison of planarization processes
H 0
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Wafer surface
Figure 3. Sequence of chemical reactions during polishing
613
Effect of slurry chemistry on polishing
0.3
0.4
0.5 0.6 0.7 0.8 RG-1/[Ioglisngle bond strnth-ab9(7-IEP)]
0.9
Figure 4. Polishing rate vs slurry type
Figure 5: Cross sectional view of a wafer undergoing polishing
614
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11 RESULTS IN
INCREASE IN RATE
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00
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FIgure 8: Post-clean particle levels on a polished wafer Particles shown are larger than 0.5 microns
616
ADVANCED DIELECTRIC TECHNIQUES FOR THE FABRICATION
OF 16 MEGABIT DRAM GENERATION DEVICES B. Ahlburn Texas Instruments - DMOS IV, 13353 Floyd Rd. Dallas, TX 72265 R. Nowak, M. Galiano, and J. Olsen Applied Materials, 3050 Bowers Av. Santa Clara, CA 95054
Submicron gap filling and dielectric planarization schemes are applied to a 16 Megabit DRAM device. PECVD and SACVD TEOS oxide films are used for void free filling of gaps as small as 0.5 um at metal 1 and metal 2 levels. Thin layers of PECVD TEOS oxide are found to be important for reduction of nucleation sensitivity, loading effects, and moisture intake of the 0 3 -TEOS SACVD films. The sacrificial B 2 0 3 planarization scheme is used over metal-1 providing long range surface planarity. Electrical testing of completed 16 Megabit DRAMs indicates that these materials and processes meet or exceed requirements for the 16 Megabit device.
INTRODUCTION The requirements for the inter-metal isolation films used in the 16 Megabit generation devices exceed the capabilities of traditional films and fabrication techniques. The need for void-free gap filling of spaces as small as 0.5 pm at both metal-1 and metal-2 levels and for a high degree of dielectric planarity prior to metal-2 deposition make the multi-step conventional SOG [1] and depositionetchback [2, 3] schemes lengthy and unreliable. The degree of planarity using a single SOG coating and etchback is insufficient for certain topographies as illustrated in Figure 1. Reliability problems related to the use of the SOG are due to cracking, moisture absorption, outgassing, and limited planarity. For example, problems with nucleation of tungsten film in the vias may occur if the SOG film is not removed from the via vicinity in the etchback step. Stringent gap filling requirements have emerged for the passivation layers; metal-2 lines must be isolated by a low dielectric constant material which provides protection from rupture or displacement induced by the LOC packaging process. Consequently, metal-2 void-free gap filling and smoothing of the top chip surface are very desirable. Typical passivation films do not meet these requirements (see Figure 2). 617
In this paper we focus on practical applications of the Sub-Atmospheric (600 Torr) CVD TEOS-0 3 (SA-TEOS) oxide deposition process and the B2 0 3 planarization scheme to 16 Megabit DRAM. The use on device of the SA-TEOS oxide film, which has exceptional gap filling properties [4], is discussed. The B2 0 3 planarization process [5,6] is used to provide very long range planarization of the intermetal dielectric.
Figure 1. Insufficient of
the
planarization dielectric
over
metal-1 iti the guard-band area,
using
single-coat
SOG-etchback process.
Figure 2. "Keyhole" voids in a conventional dual-layer deposited
passivation over
metal-2.
film The
PECVD oxide and nitride films are deposited using the conventional SiH 4 -based chemistries.
618
FILLING OF SUBMICRON GAPS BY OXIDE DEPOSITION The SA-TEOS oxide film deposited at 600 Torr was used for filling of the submicron spaces. Void-free gap filling was obtained for a 0.5/arm wide 1.0/jm deep trench with vertical sidewalls. Similarly, void-free gap filling was demonstrated over 0.8 Yim high tungsten leads (metal-i) for spaces as small as 0.65 'Um. This was achieved despite the relatively large grain of the tungsten which resulted in irregular and sometimes re-entrant metal profiles. Figure 3 shows the result of sequential deposition of the PECVD TEOS (PETEOS) oxide layer followed by the SACVD film over metal-2 leads. Various thicknesses of the initial PECVD film (2000 A - 4000 A) were used to minimize the SACVD film thickness and to test its gap filling ability. The SACVD film had no problem with filling 0.5 jm gaps left after 4000 A PECVD deposition. Figure 3 also illustrates self-smoothing of the underlying topography which occurs in wider gaps resulting in a positive gap profile. This thickness dependent smoothing ability of the SA-TEOS oxide enables one to avoid forbidden gaps formation. Consequently, the profile after deposition of at least 4000 A of the SA-TEOS film is relatively easy to fill by either oxide or nitride PECVD films.
Figure 3. Dual-layer
passivation
(oxide-
nitride) of metal-2. "Keyholes" and "forbidden gaps" have been avoided as a result of the positively tapered profile of the SA-TEOS oxide film. The complete passivation structure consists of PE-TEOS oxide (4000 A) followed by SA-TEOS oxide (4000 A) followed by PE-CVD
nitride (1 um). 619
PROCESS INTEGRATION Loading effects and surface sensitivity It was found that the SA-TEOS oxide film thickness depends on the type of the underlying material and on the density of the underlying interconnect pattern. This is illustrated in Figures 4 (a) and (b), which show the difference in oxide thickness between areas of the wafer having different metal pattern density. The large surface area of the rough tungsten metal aggravates this effect. The surface and pattern sensitivity were found to depend on the 0 3 /TEOS ratio in the SACVD process, with high ratios producing the most surface/pattern sensitivity. A thin in-situ nucleation layer of the PE-TEOS oxide was found to be a solution to the loading effect (Figures 4 (c) and (d)). Identical film thickness is obtained for both pattern densities using this deposition method. The efficiency of the gap filling by the SA-TEOS oxide also increased. The SA-TEOS sidewall coverage in the gaps was found to be higher than 100% and resulted in complete filling of 1.0,pm spaces using films as thin as 0.45,pm. This minimizes the amount of the SA-TEOS needed to fill gaps. Like the atmospheric pressure 0 3 -TEOS process [7,8], the deposition rates of the SA-TEOS oxide vary from one type of substrate material to the next; the 2000 A&min-1 deposition rate observed on bare silicon substrates is reduced to ca. 1650 A min"1 on PE-TEOS oxide coated substrates. Furthurmore, the rate remains constant at 1650 A min-' throughout the entire deposition process, even after the initial nucleation of the SA-TEOS oxide. This phenomenon of substrate dependency is not well understood. However, it was found [9] that the proper treatment of the PECVD oxide surface or the use of the nucleation layer prior to SA-TEOS deposition eliminates the dependence of the deposition rate on the substrate type. Prevention of moisture absorption Like all porous SiO 2 films [10,11], SA-TEOS oxide films absorb water vapor from ambient air. This results in stress instability (Figure 5) as well as other deleterious effects. Water absorption can be mitigated by employing in-situ deposition of thin PE-TEOS oxide layer onto the SACVD oxide film. Figure 6 illustrates the effectiveness of the PE-TEOS oxide layer in protecting the underlying SA-TEOS oxide from moisture absorption during exposure to ambient water vapor. Curve (a) in Figure 6 reveals the quantity of water absorbed by the unprotected SATEOS oxide during extended exposure to air. Curve (b) indicates that the in-situ "cap" of PE-TEOS oxide produces a composite film which is substantially drier, even after the same exposure to ambient air. The SOG film contains an amount of moisture which is intermediate between the two CVD films (a) and (b). Thus, incorporation of moisture into the device can be minimized provided that the SATEOS film is capped. In the event of the exposure of the SA-TEOS film to ambient 620
Figure 4. Deposition rate of SA-TEOS oxide is a function of the underlying material type as well as the
density of the underlying interconnect pattern, giving rise to substantial differences in film thickness from one area of a die to another ((a) and (b)). If the metal pattern is coated with PE-TEOS oxide prior to SA-TEOS oxide deposition, this effect is diminished ((c) and (d)).
SA-TEOS oxide deposited directly onto metal-1 interconnects: a) Area with dense metal pattern
b) Area with less-dense metal pattern
SA-TEOS oxide preceeded by 1500Min-situ deposition of PE-TEOS oxide onto metal-1 interconnects: c) Area with dense metal pattern
d) Area with less-dense metal pattern
621
air, a short bake prior to the subsequent PE-TEOS deposition can drive the moisture out. Using these methods, no degradation of device performance was observed on our 16 Megabit devices. Mn
30I
250-
200
2
4 FILM
6 AGE
a
10
12
(hr.)
Figure 5 (above). Film stress in SA-TEOS oxide films during the first twelve hours of exposure to ambient air after deposition.
WEM Tit (kit) Figure 6 (above right). 0 Water effusion from oxide films during 450 C anneal. All have been exposed to ambient air for several days prior to annealing. Films (a) and (b) are SA-TEOS oxides (4000 A). Film (a) is unprotected. Film (b) is protected by a 1000 A layer of PE-TEOS oxide which was deposited in-situ after the SA-TEOS deposition. Film (c) is a baked and cured SOG 0
311P. The anneal cycle was a 2 minute ramp from room temp to 300 C, a four minute 0
0
hold at 3001C, a two minute ramp to 450 C, and a four minute hold at 450 C. Water effusion was measured using a duPont model 903H Moisture Evolution Analyzer.
DIELECTRIC PLANARIZATION Planarization of the oxide over metal-1 using a single SOG coating and etchback is marginal for the 16 Megabit device, which requires medium-to-long range dielectric planarity beneath metal-2. We have used the B2 0 3 planarization process [5,6] as an alternative to the SOG-etchback scheme. A comparison of results is shown in Figure 7. In the SOG case the degree of planarity is limited by the SOG thickness (3000 A) and selectivity of the etchback step. In the B2 0 3 scheme, planarity is limited by the boron oxide film thickness (1.3 um in this case). Very long range planarization was obtained using a single in-situ B2 0 3 deposition and etchback. In fact, considerable difficulty was encountered when aligning the metal-2 pattern, due to the planarity of the oxide surface. 622
C
en~ 0 4) C
C
.0
C.
4)
-o C)
.0 L~0
bb Uo
4) C C C
I 623
N 4)
C-
"
C
G,
DEVICE PERFORMANCE Table I summarizes electrical performance of completed 16 Megabit DRAMs built using three different intermetal dielectric schemes. The "Baseline" process is similar to most single-spin SOG-etchback planarization schemes: it uses PE-TEOS oxides and a partial SOG etchback such that SOG remains in the gaps between adjacent metal lines and on the tops of large features. Scheme "1' follows the same flow as the "Baseline", except that the first PE-TEOS layer is replaced with in-situ deposition of a thin PE-TEOS nucleation layer, SA-TEOS oxide, and a PE-TEOS cap layer. Just prior to SOG coating, the PE-TEOS protective cap is removed; then the baseline process flow is resumed. Once completed, the SA-TEOS oxide remains in the gaps between adjacent metal lines as well as on all horizontal surfaces, and SOG remains only in the largest gaps and atop large features. Scheme "2" does not use SOG. Gap filling is achieved using a thin PE-TEOS nucleation layer followed by SA-TEOS oxide, followed in turn by a blanket reactive ion etchback which removes most of the SA-TEOS oxide from the horizontal surfaces and leaves most of it in the gaps. Planarization is achieved using in-situ deposition and flow of sacrificial B2 0 3 , which is removed entirely during the following etchback step. The entire sequence of process steps is performed under vacuum. Leakage currents are generally lower through and across the dielectrics produced using schemes "1"and "2", compared with the "Baseline" case. Via integrity was comparable in all three cases. Transistor characteristics - including sensitive metal gate thick field transistors - were unaffected by the alternative schemes. This indicates that so long as proper precautions are taken when integrating these alternative materials and processes into the device flow, device performance is not degraded and may even be improved. The metal-1 integrity results confirm that the 03 used in the SACVD processes does not harm the underlying tungsten metal-1 material. It is noteworthy that in schemes "1" and "2", tungsten metal-2 is deposited into vias in which substantial amounts of SA-TEOS oxide are exposed on the sidewalls. Good via resistances are achieved nonetheless. When SOG materials are exposed on the via sidewalls, however, tungsten deposition fails due to poor local nucleation in these areas. Two Protective Overcoat (Final Passivation) schemes were used on these devices. The baseline scheme is illustrated in Figure 2; the alternative is shown in Figure 3. The alternative scheme is designed to provide a smooth, positively tapered surface profile onto which the PECVD nitride can be deposited, and at the same time to prevent the PECVD nitride from reaching the gaps between closely spaced metal-2 lines. No shifts or degradations were found when comparing electrical test parameters between the two schemes. 624
TABLE I. 16 MBit DRAM Electrical Test Parameters
INTERMETAL DIELECTRIC SCHEME
TEST PARAMETER
Baseline
1
2
BULK LEAKAGE:
mean(sigma)
mean(sigma)
mean(sigma)
-
M1 Block-to-M2 Block (pA)
14.3(3.6)
2.6(0.9)
4.4(5.2)
-
M1 Une-to-M2 Block (pA)
12.6(3.2)
9.2(0.4)
9.0(0.0)
129(114)
63(14)
38(8)
109(119)
33(16)
20(11)
2515(0)
1307(2)
763(0)
- single via (ohm)
0.61(.12)
0.61 (.08)
0.49(.04)
- via string (ohm)
2.87(.11)
2.91(.16)
2.79(.11)
0.20(.01)
0.19(.01)
0.20(.01)
0.26(.04)
0.28(.04)
0.28(.04)
SURFACE LEAKAGE: Between Interdigitated M2 Leads (pA) - Between Interdigitated M2 Leads with Lateral tabs (pA) -
- Between M2 Leads
Lying over a Passive Array (pA) VIA RESISTANCE (0.6 urn vias)
METAL-1 INTEGRITY: - Pad structure -
sheet resistance (ohm/sq) Serpentine structure sheet resistance (ohm/sq)
In the "Baseline" intermetal dielectric scheme, PE-TEOS oxide and SOG are used for gap filing; SOG is the planarizing agent. In the alternative scheme "1", PE-TEOS and SA-TEOS oxides are used for gap filling; SOG is the planarizing agent. In alternative scheme "2", PE-TEOS and SATEOS oxides are used for gap fIlling; boron oxide is used as a sacrificial planarizing agent. "MW"and "M2" refer to metal-1 and metal-2, respectively.
625
CONCLUSIONS Two new films and processes were used to build 16 Megabit DRAM devices, specifically: the PECVD-SACVD TEOS oxide sandwich film and the sacrificial B2 0 3 planarization. The SACVD TEOS film was used as a part of the dielectric insulation for both intermetal dielectric and protective overcoat. The results were compared to the conventional SOG-etchback process. Extensive electrical tests performed on 16 Megabit DRAMs indicated no degradation of any of the measured parameters as compared to the parent lot. Furthermore, some parameters improved. REFERENCES C. Chiang and D.B. Fraser, Proceedings of the VMIC Conference, Santa Clara 1989, p. 39 7 . [2] S. Pennington, S. Luce, and D. Hallock, Proceedings of the VMIC Conference, Santa Clara 1989, p.3 55 . [3] J.M. Perchard, H.E. Smith, R. O'Connor, J.C. Olsen, and K. Law, SPIE Proceedings, 1188, 75 (1989). [4] P. Lee, M. Galiano, P. Keswick, J. Wong, B. Shin, and D. Wang, Proceedings of the VMIC Conference, Santa Clara 1990, p. 18 7 . [5] J. Marks, K. Law, and D. Wang, Proceedings of the VMIC Conference, Santa Clara 1989, p. 89 . [6] J. Marks, K. Law, and D. Wang, SPIE Proceedings, 1188, 69 (1989). [7] K. Fujino, Y. Nishimoto, N. Tokumasu, and K. Maeda, Proceedings of the VMIC Conference, Santa Clara 1990, p.187. [8] K. Fujino, Y. Nishimoto, N. Tokumasu, and K. Maeda, J. Electrochem. Soc., 137, 2883 (1990). [9] P. Lee and R. Robertson, unpublished results. [10] M. Shimbo and T. Matsuo, J. Electrochem. Soc., 130, 135 (1983). [11] N. Nagasima, H. Suzuki, K. Tanaka, and S. Nishida, J. Electrochem.°Soc., 121, 434 (1974). [1]
626
EXCIMER LASER ASSISTED PLANARIZATION FOR ULSI METALLIZATION G.S. Sandhu, C. Yu, and T.T. Doan Micron Technology, Inc., 2805 East Columbia Road, Boise, ID 83706 Laser planarization is a promising technology for ULSI metallization because of its ability to fill high aspect ratio, submicron contact/vias. We have performed a comprehensive study on the effect of metal layer thickness, contact geometry, barrier layers and sputtering conditions on the process window for laser planarization. We used a XeCI excimer laser to planarize AISiCu thin films of thickness ranging from 0.5 gm to 1 Vm on a topography substrate, and to fill both micron and submicron sized contacts of aspect ratios ranging from 1 to 2. Under optimized process conditions, we achieved process windows as large as 20-30% which is significantly larger than the previously reported values (8% or less), and is adequate for this technology to be used in a manufacturing environment. Full electrical evaluations including leakage current, breakdown voltage, metal continuity/shorts, contact resistance, and I-V characteristics of the laser processed devices did not show any deleterious effects of exposure to laser energy.
INTRODUCTION Laser planarization is one of the most promising planar technologies for filling high aspect ratio, submicron contact/vias required for ULSI metallization (1-4). Laser planarization relies on a very short laser pulse to rapidly melt a metal layer. The mass transport of the metal during the molten period results in a planarized metal surface due to the high surface tension and low viscosity of molten metals. Laser planarization has the advantage of being a low thermal budget and effective technique for contact/via filling and surface planarization. Full integration of this technology into manufacturing process flow however, requires the technique to have a sufficiently large process window where, the process window is defined as the difference between minimum laser fluence required to achieve complete filling of the contacts and the maximum fluence before the onset of optical ablation. The flow of metal into a contact/via during laser planarization is governed by the surface tension and viscosity of the metal in its molten state. In addition, the 'resistance' to the flow of metal depends on the interactions at the metal/substrate interface as well as substrate topography. We have performed a comprehensive study on the effect of metal layer thickness, contact geometry, barrier layers and sputtering conditions on the process window for laser planarization. In order to preserve the junction integrity, a barrier metal scheme specific to the laser planarization process has been developed.
627
EXPERIMENTAL A XeCl excimer laser of energy - 500 mJ/pulse was used to planarize AlSiCu thin films of thickness ranging from 0.5 gim to 1 gim on topography substrates, and to fill both micron and submicron contacts of aspect ratios from 1.0 to 2.0. All the test structures were fabricated on 150 mm diameter p-type Si wafers deposited with BPSG and patterned by standard lithography and etch processes. The diffusion barrier and interconnect layer were deposited sequentially in a multi-module DC magnetron sputtering system without breaking the vacuum. For barrier layers, 500 A reactive TiN/500 A Ti were used in this study. The contact/via step coverage before and after laser planarizatio-n was examined by cross-sectional SEM. In addition, various film properties including surface morphology, Ar incorporation, barrier layer and Al alloy inter-diffusion before and after laser processing were investigated by SEM, AES, SIMS, and RBS. Electrical characterizations were carried out on laser planarized DRAM device wafers.
RESULT AND DISCUSSIONS Contact filling/planarization The SEM micrographs of contact vias before and after laser planarization are shown in Figure 1. The laser planarized devices showed completely filled contact/vias. For a given substrate topography, both the minimum laser fluence required to planarize the surface (Fp) and the maximum fluence before the onset of optical ablation (Fa) are lowered with the decrease in metal film thickness[5]. The influence of metal thickness
1 gm = 1 inch (a) (b) Fig. 1 SEM cross-sections of via (a) before and, (b) after laser planarization. 628
l•,q,,/
]0 80
800 nm
E3 600 nm A 500 nm
~60 S40 '-
0
20 as-deposited u
2.5
..
3.0
3.5 Optical
4.0 fluence
4.5
5.0
(J/cm2)
Fig. 2 Contact filling versus laser fluence for AlSiCu films at various thicknesses for contacts 0.9 by 1.4 gmn. on the effectiveness of via filling is shown in figure 2. For a similar contact/via geometry, better contact filling can be achieved at a much lower laser fluence for thinner films. For a given optical fluence, thinner films, because of their lower heat capacity, are heated to higher temperatures giving rise to a longer molten time, which therefore results in better contact filling. However, below certain metal thickness, this advantage is counter balanced by depletion of the metal around contacts during flow giving rise to partially filled contacts. In order to determine the effect of contact/via geometry on the contact filling process, contact filling percentage was determined for both sloped and vertical contacts of various diameters and aspect ratios. Figure 3 shows that for a given contact depth, a smaller diameter contact hole (higher aspect ratio) requires a higher laser fluence for complete filling. For smaller diameters, the surface tension forces act to close off the top of the via. Additional laser energy is therefore required to completely fill the vias[5]. Figure 4 shows contact filling for 1:1.6 aspect ratio contacts with several different as-deposited metal step coverages. In general, the contact filling is significantly greater with improved as-deposited metal step coverage and profile obtained at higher sputtering temperatures and sputtering with bias voltages. For certain sputtering conditions, the as-deposited metal film bridged the top of the contact hole. This resulted in better contact flow and protected the junction integrity since the junction did not get
629
120
Aspect ratio 100-
80C)
600
40-
on
I
3 Optical
4 Fluence
5
(J/cm2)
Fig. 3 Contact filling versus laser fluence for various contact aspect ratios. Contacts with smaller aspect ratios were completely filled at lower fluence. 120
100
80
60 Cu
40 0
U) 20
0
0
1
2 3 4 Optical Fluence (J/cm2)
5
Fig. 4 Effect of initial step coverage on the efficiency of contact filling during laser planarization. Better starting step coverage leads to a larger process window. 630
exposed to the incident laser beam during planarization. defined by the expression; Process Window
=
Clearly, the process window, as
Fa - Ff Fa + Ff
where, Ff is the minimum optical fluence required for complete filling and Fa is the optical fluence at the onset of optical ablation, is significantly widened by improving the initial step coverage. Under optimized process conditions, we have achieved process windows as large as 20-30% for lx1 gim contacts, which is significantly larger than the previously reported values (8% or less)[6]. The nature of the interface between Al and barrier layer has strong consequences on the flow of Al during laser reflow. The wetting properties of the layer being reflowed on the barrier layer can influence the degree of contact filling significantly. We were able to obtain better filling when Ti was in contact with Al at the bottom compared to TiN. In addition, it was observed that exposing TiN to air before Al deposition resulted in ablation at lower optical fluence. Figure 5 shows the optical micrograph of Al films after exposure to a laser pulse. The lasing conditions were selected so as to be close to the onset of optical ablation limit. Clearly, the magnitude of ablation increased significantly when the wafers coated with TiN were exposed to ambient before the deposition of Al film. Large amounts of ablation could result from gas adatoms trapped at the interface of Al and TiN films. These pockets of gas presumably expand rapidly during lasing and cause ablation.
(a)
(b)
Fig. 5 Optical micrograph of the Al films after laser planarization for (a) in-situ deposition (b) after exposing TiN to ambient for 2 hours before depositing Al. 631
and reliability
Electrical measurements
characterization
The laser processed devices were tested for electrical reliability under extreme As shown in figure 6, the laser processed wafers showed 26x environment. improvement in wafer level electromigration lifetime. The enhanced reliability results from better contact filling as well as change in the grain size of the Al films after laser planarization. It is known that a larger grain size of Al films in general leads to better electromigration lifetime.
70
~
e--
6
In 50 m- I I30
'_
""
FS50
T
jI
10
T
- L'S
.1-
/I--
ý
;I
I
,
1/6
,
I
ii1 H I 1
t4
I I Tll
i I 7-1F'
ri
1
E
z• SI.0
rli
LI
1".$1
-2
INeC.
Time (sec)
Fig. 6 Cumulative % failures versus time for a current density of 1.1x10 for a wafer level EM test. The AlSiCu films were 1 gIm in thickness.
7
amps/cm
2
There are several possible mechanisms which can contribute to the deterioration of the device characteristics after laser planarization. These include the breakdown of barrier layer between molten Al and Si which can result in Al spiking into the junction. In addition, the thermal shock received by the devices can lead to stress related problems. Consequently, a comprehensive electrical characterization of laser processed device wafers was undertaken. The I-V characteristics of n+-source diode from test structures on product wafers showed no deleterious effects on junction leakage after laser planarization as shown in Figure 7. The curves for lased and unlased dice on the same wafers showed exact overlap for this set of measurements. Similar behavior was observed for MOSFET transistor characteristics.
632
(mA)
2.000/div
V1
( V)
Fig. 7 IV characteristics of n+-source diode for laser processed and control wafers. Both the curves showed exact overlap for this set of measurements.
80e-
El
Leakage Current
0
Breakdown Voltage
60'E
a)
40-
20-
0-
IotA
IotB
IotC
IotD
Control
Fig. 8 Source to substrate leakage current and gate dielectric breakdown voltage before (Control) and after (lots A to D) laser planarization. 633
Figure 8 compares the source to substrate leakage current and gate breakdown voltage of laser processed wafers with control wafers and shows that junction and gate oxide integrity were preserved after laser planarization. In conclusion, we have achieved production worthy process windows as large as 20-30% for the laser reflow of Al into contact/vias. Full electrical evaluation including leakage current, breakdown voltage, metal continuity/shorts, contact resistance, and I-V characteristics of the laser processed devices have shown excellent results. We have successfully utilized this process for planarizing metal layers deposited on shallow junction contacts on DRAM's and obtained high yields with improved reliability on the finished product device wafers. ACKNOWLEDGEMENTS We would like to thank S. Kim, D. Mccullough for their help with every aspect of this project and R. Cross, A. Ditali for EM measurements. Thanks are due also to M. Tuttle and T. Lowrey for their constant encouragement during the course of this work. The authors would like to thank S. Chen at XMR Inc. for useful discussions. REFERENCES [1] R. Mukai, N.Sasaki, and M. Nakano, IEEE Electron Device Lett., EDL-8(2), 76 (1987). 121 D.B. Tuckerman and R.L. Schmit, in Proc. 1985 VLSI Multilevel Interconnection Conf.(V-MIC), IEEE Cat. 85CH2197-2, pp. 24 (1985). [ 3 ] D.B. Tuckerman and A.H. Weisberg, IEEE Electron Dev. Lett. EDL-7, 1 (1986). [41 B. Woratschek, P. Carey, M. Stolz, and F. Bachmann, International IEEE VLSI Multilevel Interconnection Conference (VMIC), Santa Clara, CA (1989).i [5 ] C. Yu, T.T. Doan, S. Kim and G.S. Sandhu, presented at MRS'90 Fall meeting, Boston, MA. [6 ] R. Liu, K.P. Cheung, and W.Y.-C. Lai, in Proc. 1989 VLSI Multilevel Interconnection Conf.(V-MIC), IEEE Cat. 89TH0259-2, pp. 329 (1989).
634
EFFECT OF BARRIER MATERIAL ON EXCIMER LASER PLANARIZATION OF AICu Harren Chu and Edith Ong XMR Inc., Santa Clara, CA 95054 Shi-Qing Wang' and Ivo Raaijmakers 2 Philips R&D Center, Signetics Company, Sunnyvale, CA 94088
keywords: Laser Planarization, Aluminum, Barrier
ABSTRACT The effect of barrier material (Ti, TiW, TiN) on the XeCI(308nm) excimer laser planarization process of AlCu is investigated. We find that the underlying barrier materials play an important role. A Ti barrier tends to give better filling characteristics than TiW, which in turn, is better than TiN. In addition, the resulting metal surface after laser reflow is much smoother with a Ti underlayer. We believe that the high chemical reactivity between Ti and AlCu contributes to some of these effects. In addition, laser melting redistributes Cu dopants in different AlCu-barrier systems uniformly throughout the AlCu film. INTRODUCTION Metal interconnect technologies pose great challenges to the manufacturing of advanced ICs as device dimensions decrease. Although materials such as W, Cu, and Si have been used, Al and its alloys remain the main interconnect materials for VLSIIULSI circuits. Among the various aluminum metallization schemes under development is the use of an excimer laser to reflow and planarize sputtered aluminum films over contacts and vias. This technique is a solution to the poor step coverage of as- deposited aluminum films and has been demonstrated to completely fill submicron contacts and vias [1-3]. The effectiveness of the laser planarization process, however, is very much dependent on the intrinsic material characteristics of the metallization system. For instance, the dopant distribution within the metal film is important. Woratschek et. al. have shown that large Si nodules in AlSi films are local sites for early ablation [4]. Also the use of anti-reflective coatings has been found to increase the process window [5-7]. Here, we look at the effects of different underlying substrates on the laser planarization process of Al-i %Cu. We will l 2
Present address: Present address:
National Semiconductor, Santa Clara, CA 95052 Novellus Systems, San Jose, CA 95134 635
look at the fluence requirements, the degree of fill, the grain structure, the surface roughness, the sheet resistance, and the degree of intermixing for laser planarized AlCu film on Ti, TiN, TiW, and SiO2 substrates. The integrity of different barrier layers as a diffusion barrier for the laser planarization process has been investigated elsewhere and will not be part of this study [8]. EXPERIMENTAL A lure thick layer of densified (9200C) boro-phospho-silicate glass (BPSG) was deposited on 4" (100) oriented Si wafers. Contact holes with a minimum diameter of 1.0 urn were etched anisotropically in this glass layer until Si was exposed. Prior to barrier layer deposition, wafers were precleaned by a short etch in diluted BF to remove native oxide from exposed Si in the contact holes. Thereafter, different barrier layers were deposited. The TiW barrier was deposited using a TiW target having a nominal Ti content of 10 wt %.The actual Ti content in the deposited layer is slightly lower [9] and, in this case, was measured to be about 9 wt % for the present layers. The residual gas pressure before deposition was about i0e"7 torr and the substrates were not heated intentionally. TiN (Ti-rich and N-rich) and pure Ti barrier layers were deposited in a different system. Wafers were heated to about 200'C before and during deposition. The residual gas pressure was about Ie" torr. TiN layers were sputter deposited from an elemental Ti target in Ar-N2 mixtures. The stoichiometry of the TiN layers was varied by varying the N2/Ar ratio in the working gas. Pure Ar was used for deposition of pure Ti layers. The present procedure resulted in a N content of 45 at. % and 52 at. % for the Ti-rich and N-rich layers, respectively. An Al-lwt%Cu layer of approximate thickness lum was deposited onto the TiN and Ti barrier layers without breaking vacuum. TiW was exposed to atmosphere before AlCu deposition. The substrate temperature during AlCu deposition was about 200°C. In some cases, AICu was also deposited on bare BPSG substrates. The as-deposited metal was lased with the XMR model 7100 aluminum planarization system. This system uses a pulsed 45ns FWHM XeCl(308nm) excimer laser source. Details of the system have been described elsewhere [6]. The specular reflectance at 308nm of the as-deposited samples unpatterned ) was monitored using the Perkin-Elmer Lambda 5 UV/VIS Spectrophotometer. A Si(100) wafer, doped with boron to a resistivity of 14-45 ohm-cm, was used as the reference, The actual composition of the various layers was assessed with 2MeV He+ Rutherford backscattering, using a scattering angle of 170 degrees. Secondary ion mass spectrometry (SIMS) analysis was performed using a Cameca IMS4F. The impact energy of the primary beam was 5.5 KeV per incident Cs+ ion. Positive secondary ions were extracted from the 85umr2 central portion of the 250ur 2 rastered area. The Cu data were quantified using data from the analysis of NBS standard alloy 3004 while the remaining data have been normalized to Al. 636
04 02 0.0
RESULTS AND DISCUSSIONS
-0.2
Planarization
-0.4
The minimum fluence for planarization of the contact structures described above are tabulated in Table 1. Consistent
with our previous results, the fluency required for planarization decreases with increasing substrate temperature [6]. We found, however, that samples with a Ti bartier require the highest fluence for planarization at all substrate temperatures and allow substantially higher fluences before the onset of ablation at 400°C. This results in a larger net planarization process window for the Ti samples at 4000 C. A factor which may explain the higher fluences required for planarization and ablation of samples with a Ti barrier was found to be the significantly higher specular reflectance of AICu on Ti (Table 1). However, the surface roughness of the as-deposited AICu on Ti was similar to that of the other samples (Figure 1). At this point, it is not clear why the specular reflectance should be higher for the Ti samples. Attempts have been made to test for differences in surface concentration of Cu, but we did not detect a significant change in surface
Table 1:
-0.4Q)
0
E
SiO2 TiW TiN, N-rich TiN. Ti-rich
1
0.4 "45 -0.2
00 C' 51 -02 in -0.4 0
100
200
30
100
200
300
0.2 0"0 -02 -04 0
E
0,4ý -0.20'0 0.2 -0.4
"0 10
o 200
30o
Scan Length (um) Figure 1: Stylus profilometer traces for as-deposited AlCu on a) Si02, b) Ti, c) TiW, d) TiN (Ti-rich), and e) TiN (N-rich) substrates.
Fluence requirements for planarization of Al- 1%Cu Min F(J/cm2)*
Substrate Ti
8.
04 0.2 S0.0 -0.2-
Max F(J/cm2) *
Reflectance* 140% 79%
250C 4.5 3.4
400C 3.0 -
250C 7.3 7.3
400C 6.7 -
60%
3.4
2.4
6.1
4.3
41% 35%
3.9 3.4
2.7 3.0
5.2 6.1
3.3 4.3
Reflectance measurementis specularreflectance at 308nm, measuredatnormal incidence and with reference to silicon Min F = Minimum Fluence needed for plananzation Max F = Minimum Fluence for onset of ablation
637
Cu concentraton withn me mints Or " SIMS.
and
It is also not clear why samples with the Ti barrier exhibit more resistance to ablation at 400°C. During laser planarization, however, oxygen and nitrogen can outgas from the TiW and TiN barriers to blow off the AlCu film; whereas, it is less likely for such gases to evolve with Ti samples. Contact Fill For these contact structures, complete contact fill was found only for samples with Ti and TiW barriers. Figure 2 shows that at 4.5 J/cmn and 250C, the degree of fill for the contacts with a Ti barrier is better than that with a TiW barrier or with no barrier at all. TiN barriers (both Ti-rich and N-rich) perform worst with respect to contact fill. Figure 2: Cross-section SEM This is a result which is both surprising micrographs of Al-I%Cu contact fill, and encouraging since we would expect the Ti as-deposited and irradiated with 4.5 J/cm2 sample to have least fill. The absorptivity of at 250C: a) and b) AICu on SiO2; c) and AICu on Ti is lower than that of AICu on other d) AICu on Ti; e) and f) AICu on TiW; g) substrates as is shown before by the higher and h) AICu on TiN (Ti-rich); and i) and fluence required for the onset of planarization j) AlCu on TiN (N-rich). for AICu on Ti films. Also, since filling characteristics can be altered by a change in the metal profile [5], one may suspect different as-deposited metal profiles on the different barrier substrates to cause the observed difference of fill. As shown in Figure 2, the as-deposited profiles for AlCu on different substrates are similar. Lastly, many have postulated that prolonged melt duration helps filling as substrate heating has been found to improve contact fill [1, 10]. Here, we cannot explain the difference of fill based on a difference in melt duration. Apparently, there is another factor causing our observed trend in contact fill. We postulate this factor to be wettability. It is known that different interface energies exist between AlCu and various barrier metals, and that the interfacial energy will decrease as the nature and structure of the contacting phases become increasingly similar. It is also known that metallic liquid moistens solid metallic bodies better if intensive chemical reaction takes place between them [11]. Here, we have a very reactive Ti compound which readily forms a layer of Al-Ti alloy between the top Al and the Ti barrier; we have a thin oxide layer between the top Al and the TiW barrier; and we have an AIN layer between the top Al and the TiN barrier [12]. Based on the above criterions for good wetting and the characteristics 638
F5.5
S. I
S40 S-f
Ti, 400C
T,N, 400C . ? ., Ti 0 T-N
400C
T
r~fh
IC
a
2
.0
2
3
4
5
6
7
Fluence (J/cm2)
Figure 3: Plan view SEM of AlCu surface morphology with a) Ti, b) TiN, c) TiW, and d) SiO2 underlayers after irradiation at 3.9 J/cm2 at 250C.
Figure 4: Change in sheet resistance with Fluence.
of our AICu-barrier systems, we would expect A1Cu to adhere best to Ti, then to TiW, and lastly to TiN. This is consistent with our observed trend in fill. Morphology Consistent with the findings of others, we find that grain size increases with increasing fluence and substrate temperature [13]. We also find that the resultant metal morphology and surface roughness are significantly different for AICu on different substrates after laser planarization. Figure 3 shows that under a given processing condition, the crystallized AlCu grains are largest with underlying SiO2 layer and smallest with an underlying Ti layer. This probably results from the differences in the nucleation and crystallization of molten AlCu on different barrier layers. This result can also be related to differences in chemical reactivity of the substrates. Sheet resistance The sheet resistance was measured before and after laser melting with a four point probe. As shown in Figure 4, the sheet resistance increases with fluence and substrate temperature. Since TiAI3 is readily formed between Al and all substrate barriers (Ti, TiW, and TiN) [12] and since TiA13 is the primary compound which forms above 440C [14,15], we postulate that our increase in sheet resistance is due to this TiA13 formation. Intermixing Our SIMS data (Figure 5) indicate that Ti intermixes readily with the Al layer after laser melting. The degree of intermixing, however, is less severe for AlCu on TiW and TiN (not shown). This is again consistent with the predicted chemical reactivities of our AlCu-barrier systems. Similar data has been reported for TiW barrier [13]. Also in Figure
639
J
.. .. .. ... .•A ,
tj
40
1
S,
E
Approximate Depth tmicrons)
Approximate Depth (microns)
Figure 5: SIMS depth profiles of AI-l%CuJri/SiO2/Si: a) 5 minutes at 250C and b) processed at 3.4 J/cm2 at 250C. 5, we see that the initial Cu pile-up is redistributed uniformly throughout the AICu film after laser melt/crystallization. CONCLUSIONS We have demonstrated that the underlying barrier material plays an important role in the laser planarization of AlCu. Planarization and contact filling properties are best for AlCu on Ti, which is better than that on TiW, which is better than that on TiN. Grain size and surface roughness is largest for lased A1Cu on TiN, which is larger than that on TiW, followed by that on Ti. The resulting sheet resistance and interface mixing are also dependent on the barrier material used. These characteristics can be attributed to the chemical reactivity of the adjacent barrier material with AICu. ACKNOWLEDGEMENTS Special thanks to Dr. S. Chen for his support. REFERENCES [1]
R. Mukai, N. Sasaki and M. Nakano, MRS Symp. Proc. 74,229 (1987). also published in IEEE Electron Decv. Lett. EDL-8, 76 (1987). [2] R. Mukai, K. Kobayashi and M. Nakano, Proc 5th Int. IEEE VLSI Multilevel Interconnection Conf., p. 101, Santa Clara, CA. (1988). [3] D. Pramanik and S. Chen, Proc. IEDM, p. 673 (1989). [4] B. Woratschek, P. Carey, M. Stolz, and F. Bachmann, Proc. 6th Int. IEEE VLSI Multilevel Interconnection Conf., p. 309., Santa Clara, CA. (1989) [5] R. Liu, K.P. Cheung, W.Y.C. Lai and R. Heim, ibid, p. 329. [6] I.J. Raaijmakers, H. Chu, E. Ong, S-Q Wang and K. Ritz, MRS Symp. Proc. 181, 553(1990). [7] C. Yu, G.S. Sandhu, and T.T. Doan, "CVD W, TiW, Ti as Anti-Reflective Coatings for the Laser Planarization of Al-Alloy for ULSI Metallization", presented at the 1990 MRS Tungsten Workshop, to be published at MRS Conf. Proc., VLSI-6. 640
[8] C. Yu, T. Doan, S. Kim, Proc. 7th Int. IEEE VLSI Multilevel Interconnection Conf., p. 444, Santa Clara, CA (1990). [9] I.J.Raaijmakers, T. Setalvad, A.S. Bhanssali, Brad J. Burrow, Laszlo Gutai, and Ki-Rum Kim, J. Electron. Mater. 19, 1221 (1990). [10] R. Baseman and J. Andreshak, MRS Symp Proc. 158,267 (1990). [11] M. Humenik and W.D. Kingery, J. Amer. Cer. Soc. 36, 11, 362 (1955). [12] A.S. Bhansali, I.J. Raaijmakers, R. Sinclair, A.E. Morgan, B.J. Burrow, and M. Arst, MRS Symp Proc. 187, 15(1990) [13] E.K. Broadbent, K.N. Ritz, P. Maillot and E. Ong, Proc. 6th Int. IEEE VLSI Multilevel Interconnection Conf., p. 336, Santa Clara, CA (1989). [14] J. K. Howard, R.F. Lever, P.J. Smith, and P.S. Ho, Journal of Vacuum Science Technology, 13, 68 (1976). [15] R.W. Bower, Applied Physics Letters, 23, 99(1973).
641
APPLICATION OF A SPIN-ON-GLASS PLANARIZATION PROCESS TO SUBMICRON TRIPLE METAL TECHNOLOGY Seiichi Morimoto, Sarah Queller, Robert Gasser and Janice Kronschnabel Portland Technology Development Intel Corporation 5200 N.E. Elam Young Parkway Hillsboro, Oregon 97124
Various spin-on-glass (SOG) planarization processes have been used in the fabrication of semiconductor devices. Their purpose is to planarize topographies both above and below the metal interconnect layers. This paper describes a no etchback SOG process that is capable of planarizing submicron metal spaces without cracking. The use of an organic SOG along with appropriate post spin treatments produces a planarizing film with consistently low via resistances of 100-150 mohms. When exposed to an accelerated steam environment of 158'C and 5 atms., the film was found to be acceptable in terms of delamination, capacitance increases, and leakage currents. Planarity and lithography effects were evaluated for a triple layer metal process. The no etchback SOG process was demonstrated to be a viable planarization approach for a submicron multilevel metal process. A separate SOG process was developed to enhance the planarization of the BPSG surface beyond the partial planarization that is obtained with thermal glass flow cycles. Flat BPSG slopes of almost zero degrees were achieved with this sacrificial SOG planar etchback process. INTRODUCTION Spin-on-glass processes are relatively simple and economical and have been widely used to planarize both submetal and intermetal dielectrics. SOG has an advantage over traditional resist etchback planarization schemes in that its similarity to silicon dioxide allows it to remain as an integral part of the device. Although SOG alone is not a good insulator, it can be readily integrated with CVD films to yield stable insulating properties. SOG also has an advantage over fully planarizing processes in that it is a smoothing film and it produces less via depth differential than that produced by a fully planarizing film. This decrease in via depth differential improves the metal step coverage and reliability. For applications to double metal layer technologies with geometries above 1p.m, SOG planarization has typically been achieved by etching back the SOG so that it remains only in the metal spaces. A relatively thick ILD underlayer is required
642
between the metal and the SOG to prevent loss of planarization once the etch clears the tops of the metal lines. The etched back SOG is then capped with an ILD overlayer which acts as the bulk of the interlayer dielectric. This approach isolates the SOG from the via regions, eliminating via resistance problems associated with outgassing of the SOG film in the via holes. However, the feasibility of this etchback approach is questionable for submicron geometries: The 1lD underlayer required to preserve the planarity during the etchback is thick enough that it pinches off the submicron spaces. The use of SOG to planarize a triple metal process also presents a challenge with regard to achieving adequate planarity. Since SOG planarization is smoothing as opposed to fully planarizing, the metal 3 layer sees the cumulative effect of the planarization of both the premetal and the intermetal dielectrics. Improving the planarization of the glass layer prior to the first metal deposition will improve the planarity seen at the metal 3 layer. This paper describes a SOG planarization scheme that provides adequate planarization for a submicron triple metal process (Figure 1.)
M3 SýOG
-M2
. .
SOG
IpllBPSG
Figure 1: SOG Planarization Scheme
THE DEVELOPMENT OF A NO ETCHBACK SOG PROCESS As described above, a traditional SOG etchback process is not compatible with
643
submicron geometries. The approach taken here to solve this problem is to increase the process window by allowing the SOG to be left on top of the metal and eliminating the etchback step. When SOG is not etched back and is left on top of the metal, however, there are several major issues that must be resolved. 1) SOG outgassing must be eliminated in order to obtain low and stable via resistance when SOG exists in the via region. 2) The reliability aspects of leaving SOG over the entire wafer surface, such as delamination during the high temperature/humidity testing, must be resolved. 3) The integrity of the insulating material as measured by leakage and capacitance between the metal lines as well as between the metal layers must be ensured. 4) SOG cracking and filling problems must be eliminated in the submicron metal spaces. To resolve the issues described above, the following no etchback SOG process sequence was used. 1. Thin ILDI deposition, IOOA plasma oxide 2. SOG spin/bake, 4000A double spin of organic type SOG 3. SOG cure, plasma nitrogen at 400'C for I hour 4. Thick ILD deposition, 5000A plasma oxide 5. Via pattern and etch with chemical resist strip 6. Post via cure, nitrogen at 450'C for 1 hour 7. In-situ sputter etch prior to metal deposition Achieving low and stable via resistance with this process is dependent on eliminating the contamination of the metal film that can occur when SOG outgasses during the metal deposition. In the process described here, consistent via resistances of 100-150 mohm are obtained by curing the SOG at 400'C in a nitrogen plasma, using a chemical resist strip rather than a plasma strip, and including an in-situ sputter clean prior to metal deposition. With this sequence of process steps, the via resistances described above could be achieved with either high organic content SOG material or with inorganic silicate SOG. Via resistance test structures evaluated included a structure with vias placed on a wide metal plate where SOG thickness is maximum. Devices processed using the no etchback SOG planarization were tested in a high temperature and high humidity environment. After 90 hours in steam at 158'C and 5 atmospheres, there were no signs of either delamination or cracking. For devices passivated with oxynitride, the post stress increase in layer to layer capacitance measured 13% and the post stress increase in line to line capacitance measured 2% (Figure 2.) The leakage current measured between metal lines was
644
SOG filling and cracking were evaluated for 0.8ltm metal spaces for different types of SOGs. Inorganic SOG cracked in these small spaces, and its planarization capability is limited by the thinner coating required to avoid cracking. Methyl based organic SOGs with organic contents ranging 20% to 35% provide adequate planarity and show no cracking in the 0.8gm metal spaces. However, when the space left after the ILD underlayer deposition becomes less than 0.2gm, SOG filling is a problem. A definite sensitivity to filling problems was noted in metal spaces that take a 90 degree turn.
MI /M(2CAPACITANCE MI/MI CAPACITANCE C A P A C T A N C E
Il C R E A S E
SOG TYPE,
PASSIVATION
Figure 2: Capacitance Increase After Accelerated Temperature Humidity Stress
As mentioned earlier, the planarization will affect both the metal step coverage and the printing of critical dimension submicron lines. Figure 3 shows the slopes that are achieved versus SOG thickness for a triple layer metal process using the no etchback SOG scheme and assuming a flat surface below the first layer metal. This data was generated using a metal 1 layer thickness of 4000A and a metal 2 layer thickness of 8000A. Figure 3 also plots the topography induced resist thickness delta as a function of SOG thickness using either double or triple SOG spin. The data indicates that the slope that the metal 3 layer sees can be decreased, if necessary, by increasing the SOG thickness above 4000A. However, the resist thickness delta is not 645
much improved by increasing the SOG thickness above 4000A. It S
RITY T DELTA
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2000
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SOG THICKNESS,
i 6000
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Figure 3: Planarity and Resist Thickness Delta vs. SOG Thickness BPSGISOG PLANAR ETCHBACK PROCESS
Achieving a fully planar surface underneath the first layer metal will improve the planarization all the way through the metal 3 layer. It will also reduce the worst case via depth differential and thus improves the metal step coverage. A planar BPSG can be achieved by doing a sacrificial SOG etchback. The planar etchback produces a nearly flat BPSG surface over the polysilicon and oxide steps. The planar BPSG etchback process is described below: 1. BPSG reflow 2. SOG spin 3. SOG cure, steam at 650'C for 1 hour 4. wet etchback with SOG:BPSG selectivity < 1:1 SOG in this case is used as a sacrificial layer and is completely removed after the etchback. Using this approach, it was demonstrated that a BPSG slope approaching zero degrees can be obtained at a selectivity of 0.8 (Figure 4). Selectivity can be
646
adjusted by changing steam cure temperature or time as shown in Figures 5 and 6.
Figure 4:
SEM Micrograph of BPSG Profile After Planar Etchback CONCLUSION
The application of spin-on-glass planarization processes for both premetal and intermetal dielectrics were discussed. A no etchback SOG process was selected in order to fill submicron metal spaces without cracking and filling problems. Using an organic type of SOG with proper post spin treatment, consistent via resistances of 100-150 mohm were obtained. The reliability of the SOG film was tested in an accelerated steam environment and found acceptable in terms of delamination, capacitance increases and leakage currents. Planarity and lithography effects of the noetchback SOG planarization scheme were also evaluated for a triple layer metal process application. This SOG process was shown to be a viable approach for submicron triple layer metal technology. A BPSG planar etchback improves the intermetal dielectric planarization above the metals by providing a flat foundation underneath the first layer metal. The planar etchback involves using SOG as a sacrificial layer and was demonstrated to reduce the BPSG slope to nearly zero degrees.
647
200
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Figure 5: SOG:BPSG Selectivity and Etch Rates vs. SOG Cure Temperature •^^ 300
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SELECTIVITY SOG E.R. BPSG E.R.
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Figure 6: SOG:BPSG Selectivity and Etch Rates vs. SOG Cure Time 648
ACKNOWLEDGMENTS The authors would like to thank Bill Siu, Steve Chambers and Mark Bohr for their support and suggestions regarding this project. REFERENCES [1]
Y. Shacham-Diamond and R. Brener, 'The Characterization of the Residual Film Formed by Plasma Etching Polysiloxane Spin-On-Glass on Aluminum', J. Electrochem. Soc., vol. 137, p. 3183 (1990)
[2]
T. Tokunaga and N. Owada, 'Effects of Multichamber Processing on Reliability of Submicron Vias', Proc.SPIE - Int. Soc. Optical Eng., vol. 1188, p. 61 (1990)
[3]
Y. Shacham-Diamond and Y. Nachumovsky, 'Process Reliability Considerations of Planarization with Spin-On-Glass', J. Electrochem. Soc., vol. 137, p. 190 (1990)
[4]
S. Morimoto and S. Q. Grant, 'Manufacturable and Reliable Spin-On-Glass Planarization Process for 1p CMOS Double Layer Metal Technology', Proc. 5th Int. IEEE VLSf Multilevel interconnection Conference, p. 411 (1988)
649
OXIDE-FILLED TRENCH ISOLATION PLANARIZED USING CHEMICAL/NECHANICAL POLISHING 2 1 J. N. Pierce, P. Renteln, W. R. Burger and S. T. Ahn Fairchild Research Center, National Semiconductor Corporation Santa Clara, CA 95052
An oxide-filled shallow trench isolation process is described, which includes a chemical/mechanical polishing (CMP) step to planarize the CVD oxide used to fill the trenches. The stringent leveling requirements for this application are discussed, and a newly developed CMP process is demonstrated with a leveling length of several mm. The isolation process has been applied to both CMOS and bipolar devices with good results. INTRODUCTION Shallow trench isolation (STI) filled with CVD oxide is attractive for scaled ULSI, because the encroachment and stress problems associated with field oxide growth are largely avoided. Figure 1 shows a simplified STI process flow, a key requirement of which is planarization of the CVD oxide to expose the nitride mask while controlling the relative heights of the active areas and field areas. The final height of the field oxide must be higher than that of the active silicon under the nitride mask, but not high enough to produce a substantial step. A reasonable range for the step is 0-100 nm, which poses a severe challenge for the planarization process. Previous STI processes [1,2] have used planarizing resist over the CVD oxide and RIE etchback of the composite stack. Field areas wider than a few micrometers must be protected by a blocking resist layer patterned using an extra photomasking step, because planarizing resists lose leveling ability beyond this range. Chemical/mechanical polishing (CMP) has also been used in conjunction with resist etchback to improve process margins [2]. These processes are obviously complex and expensive, and accumulation of tolerances associated with the many steps makes it difficult to achieve the final tolerances required. In this work, an improved CMP process has been used alone to planarize STI, without resist etchback and without the use of an extra masking step. We have named this simplified process ISO-P. The improved CMP process which makes the ISO-P process feasible levels over much longer distances than those leveled by spin-on processes. In addition, exposure of the masking nitride results in a reduction of the polishing rate of oxide in nearby field areas to match that of the nitride. Thus the nitride mask tends to act as a polishing stop layer. 650
ILdL PERIPHERY
ARRAY
Fig. 1. ISO-P process cross-sections before and after CMP planarizatlon.
Fig. 2. Typical wafer layout showing need for long distance leveling.
Nevertheless, STI planarization using CMP alone requires an extremely long planarizing range or leveling length to avoid over polishing in low density regions of the circuit where elevated areas naturally polish faster. The key requirement is to remove all oxide from the masking nitride in dense areas without breaking through the nitride in low density areas. Since the oxide/nitride polishing rate ratio is only about 3/1, the stopping power of a 150 nm nitride layer is quite limited. Therefore most of the burden falls on the leveling ability of the CMP process. Figure 2 shows a typical memory wafer layout where the density varies from high to low to high over 5 mm, indicating the range of leveling required. One can conclude that a CMP process used for ISO-P isolation must have a leveling length approaching the size of a chip. A significantly greater leveling length is not desirable, however, because it results in nonuniform oxide removal rates across a wafer due to variations in wafer thickness. The leveling length of a CMP process for ISO-P isolation must therefore be optimized. PROCESS DETAILS The process used for this work followed the scheme shown in Fig. 1. A 20 nm layer of thermal SiOg was grown on the silicon substrate, followed by deposition of 150 nm of CVD Si 3 N4 . After masking and etching the active area pattern in the oxide/nitride stack, the silicon substrate was anisotropically etched using RIE to a depth 0 - 100 nm less than the desired final isolation oxide thickness. Trench depths in the range 0.5 - 1.0 um were used in this study. After removing the photoresist and cleaning the wafers chemically, 20 - 40 nm of thermal SiO2 was grown to seal the sidewalls of the trenches. At this point, channel stop implants were 651
Next, the trench fill oxide was deposited using made in some cases. CVD to a thickness approximately 50% greater than the trench depth. CMP planarization was carried out using a glass-impregnated polyurethane polishing pad with fumed colloidal silica slurry. Polishing was terminated when the nitride over the active silicon The pad, slurry and polishing areas was completely exposed. parameters were optimized to produce the leveling results discussed below. After planarization, the nitride/oxide stack was stripped, and the devices were completed using normal process steps. RESULTS Figure 3 shows the leveling characteristics of the CMP process used in this work. Previously reported results [3] are also shown for The parameter used in Fig. 3 to characterize leveling is comparison. the planarization rate, p, a useful quantitative measure of the For planarizing ability of CMP processes on wide patterns [3]. pattern widths of approximately I mm or more, CMP processes quickly smooth the sharp steps at pattern edges and begin eroding oxide from Nevertheless, planarization continues low areas as well as high ones. In this regime, because high areas are eroded faster than low ones. the remaining step height A is decreases exponentially with the mean amount, d, of oxide removed, and p is defined to be the slope of the As Fig. 3 indicates, p is high for narrow patterns ln(A) vs. d line. The current process shows useful and declines for wider ones. planarization out to 5 mm widths, which 1is in the range needed for at w - 5 mm implies that For example, p - 2 umULSI isolation. the residue] step height of a 5 mm wide pattern can be reduced by a 7.4 by polishing away I um of oxide. factor of e 5
1
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Fig. 3. Leveling characteristics of improved CMP process compared with process reported previously [3].
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652
Figure 4 shows SEM views of an ISO-P wafer after CMP planarization and before stripping the exposed nitride mask. A poly-Si layer has been added to improve contrast and delineate surface topography. High quality local planarization Is evident. Long distance planarizatlon Is shown in Figs. 5-6. Figure 5 shows surface profilometer scans of a memory wafer before and after planarizatlon. The 3 mm scans run from one array to the next across a low density region more than I mm wide. The initial step height was 1.2 um. As the expanded scale trace in Fig. 5C shows, the total remaining amplitude over a 3 mm span is less than 40 nm. At this scale, the bow in the wafer is significant, making it necessary to measure actual film thicknesses to evaluate leveling. Figure 6 shows the remaining nitride and field oxide thicknesses at a series of adjacent points along a 12 mm path crossing the low density
Fig. 4. SEM cross-sections of ISO-P structures after CMP planarization. A poly-Si layer was added to improve contrast. 653
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region of Fig. 5. The original 150 nm nitride mask has been reduced to 133 nm with a variation of 12 nm. The oxide variation is about 40 nm. This excellent planarization coupled with the 1/3 etch rate ratio between nitride and oxide means that a 150 nm nitride mask provides sufficient extra margin to accommodate global nonuniformities in oxide deposition and CMP. The ISO-P process has been used to isolate both MOS and bipolar devices. No significant degradation in device properties was observed which could be attributed to the CMP process, and the essentially zero encroachment of STI means that an increased fraction of silicon area is available for active devices. An example is shown in Fig. 7, where the transconductances of NMOS transistors are compared with those of LOCOS isolated controls. The effective widths of the ISO-P devices are approximately 0.7 um greater than those of the controls due to the reduced encroachment.
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Fig. 7. Transconductance of 2 um long NMOS transistors vs. drawn channel width. Increase in Weff is 0.7 um.
Z 0
NOMINAL CHANNEL WIDTH (um)
CONCLUSIONS
Planarization of shallow trench isolation using CMP alone has been demonstrated, without resist etchback and without the use of an extra masking step. A newly developed CMP process was shown to produce leveling lengths in the range of several mm, which are required to bridge regions of varying density on typical ULSI circuits. The isolation has been applied to CMOS and bipolar devices with good results, and the field oxide encroachment is essentially zero. 655
realization that there is a significant potential for MNOS devices to be compatible with very high speed integrated circuit performance. This paper reports the effects of varying silicon nitride film deposition conditions on the chemical nature, memory traps, and memory characteristics of MNOS devices. The deposition conditions investigated were the deposition temperature variations which gave rise to varying hydrogen concentrations in the film and post-deposition annealing conditions. Nitrous oxide (N20) gas was used at various deposition temperatures to introduce oxygen and hydrogen impurities simultaneously during the film deposition process. We report how the nonvolatile memory properties of the MNOS devices are altered by incorporating hydrogen and oxygen into silicon nitride.
EXPERIMENTAL All metal-nitride-oxide-silicon (MNOS) samples were fabricated on p-type or n-type 450mm thick polished silicon substrates with a resistivity of 1-9 ohmcm and (100) orientation. Prior to oxidation, all waters were cleaned using a standard cleaning procedure. The thermal oxidation of the silicon wafers was performed in a hot-wall low pressure chemical vapor deposition (LPCVD) reactor with an ambient of pure oxygen at a temperature of 750 0C under atmospheric pressure. The silicon dioxide (SiO2) films of the MNOS devices were thermally grown in two separate groups. In the first group, the as-grown oxide thickness was 90A, as measured by ellipsometry. These thick oxide samples were used to investigate charge trapping in the MNOS structures using the internal photoelectric-effect technique [5]. In the second group, the asgrown oxide film had a thickness of 20A. These thin oxide samples were used for flatband charge decay measurements to investigate nonvolatile memory properties of MNOS devices [2]. The wafers from both groups were given a 25 minute dry nitrogen anneal in the same LPCVD system. The oxidation and post-oxidation annealing conditions were chosen such that fixed oxide charge and average mobile ionic charge were minimized as determined by bias temperature stressing and C-V measurements [5]. Silicon nitride films were chemical vapor deposited on the oxidized silicon wafers by the reaction of dichlorosilane (SiH2CI2) with ammonia (NH3) in the same LPCVD hot-wall reactor at a low chamber pressure of 0.5 Torr. The silicon nitride films were deposited under two separate conditions. In the first deposition condition, films were deposited as a function of deposition temperature at 6500 C, 7000 C, 750'C, 8000C, and 8500C, with a constant ammonia to dichlorosilane gas ratio of 3.5:1. The temperatures were chosen so as to obtain a varying hydrogen content in the silicon nitride films. The gas ratio was chosen in order to obtain good film stoichiometry [3]. In the second deposition condition, nitrous oxide (N20) gas was introduced into the LPCVD
658
reactor together with ammonia and dichlorosilane gases in order to incorporate oxygen into the silicon nitride film. The oxygen-rich silicon nitride film [3] was deposited as a function of deposition temperatures at 650°C 7001C, 7500C, 8000C and 8500C, with a constant nitrous oxide gas flow rate of 40 sccm and a constant ammonia to dichlorosilane gas ratio of 3.5:1. These conditions were chosen to simultaneously introduce oxygen and hydrogen impurities into the films. The thickness of all the nitride films used in our investigation was 400 A, as determined by ellipsometry. RESULTS AND ANALYSIS Figure I shows the atomic percentage of nitrogen (N), silicon (S), hydrogen (H), and oxygen (0) as a function of deposition temperature with no N20 gas flow as shown in Figure 1(A); and with an N20 gas flow rate of 40 sccm as shown in Figure 1(B). As shown in Figure 1(A), no oxygen was present in the film, and the silicon concentrations essentially remained constant throughout the film. However, the nitrogen concentrations decreased as a function of decreasing deposition temperature. The hydrogen concentration 65
65
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(B)
DEPOSITION TEMPERATURE (- C)
FIGURE 1: (A) Atomic percentage of Nitrogen (N), Silicon (Si), and Hydrogen (H) as a function of deposition temperature for oxygen-free silicon nitride samples; (B) Atomic percentage of Nitrogen (N), Silicon (Si), Oxygen (0), and Hydrogen (H) as a function of deposition temperature for silicon nitride samples deposited with N20 gas flow rate of 40 sccm.
659
increased by about 4% as the temperature decreased from 8500 to 6500 C. The nitrogen to hydrogen (N-H) and silicon to hydrogen (Si-H) bonds also decreased by approximately 2%. As shown in Figure 1(B), the nitrogen and oxygen content of the film varies quite significantly as a function of deposition temperature, and their variations essentially complement each other. More oxygen is incorporated into the film, primarily at the expense of the nitrogen. This is quite obvious at a deposition temperature of 7000 C, where there is essentially an increase in oxygen for a corresponding decrease in nitrogen concentration. It also shows that the hydrogen concentration decreases by about 3% as a function of deposition temperature. The steepest decrease was 2.5% at 7000 C, where more oxygen is incorporated into the film. The data indicates that the addition of oxygen in the insulating film further decreases hydrogen content in the insulator.
E
0 0
z
W• 0 L, hi
)
Lo 0 hi
a-
C650
700
750 800 850 650 700 750 800 (a) Wb) DEPOSITION TEMPERATURE ('C)
850
FIGURE 2: Trapped electron density (upper curves) and its normalized centroid (lower curves) for silicon nitride films deposited as a function of deposition temperature. In Figure 2, the trapped electron density (upper curves) and its normalized centroid (lower curves) are plotted as a function of deposition temperature for N20 = 0 sccm (Figure 2a) and for N20 = 40 sccm (Figure 2b). The curves designated as B with solid circles are for as-deposited samples, while curves designated as A with solid squares are for nitrogen-annealed samples, and dashed curves designated as C with solid triangles are for
660
hydrogen-annealed samples. The curve B of Figure 2(a) clearly shows a linear decrease (essentially 25%) in trapped electron density with decreasing deposition temperature. After nitrogen annealing, however, there is a parallel
increase of approximately 7% in the trapped electron density as compared to
as-deposited samples due to a loss of hydrogen present in the silicon nitride film. In addition, the trapped electron density increased approximately 29% as a function of deposition temperature after nitrogen annealing. Comparing curves A and C indicates that, after hydrogen annealing, the trapped electron density drastically decreased by approximately 22% at 8500C and by 10% at 6500C. The normalized charge centroid essentially remained constant, indicating that there is no movement of the charge centroid as a function of the deposition temperature and nitrogen/hydrogen annealing. Figure 2(b) illustrates the trapped electron density and its centroid in silicon nitride with oxygen impurities. The overall results of the variation of trapped electron density are the same, as shown in Figure 2(a), with two major exceptions. First, the trapped electron density is smaller in the films with oxygen impurities. Second, the trapped electron density showed a drastic decrease for films deposited at 7000C for as-deposited and nitrogen-annealed samples. The normalized charge centroid decreases from 0.57 to 0.54 for asdeposited samples, 0.59 to 0.56 for nitrogen annealed samples, and 0.56 to 0.51 for hydrogen annealed samples. This indicates that the centroid of the trapped electrons moves toward the gate metal interface and away from the oxide-nitride interface as more oxygen is introduced into the film. The variation of the refractive index of the film with the deposition temperature at a constant ammonia to dichlorosilane gas ratio with no N20 gas flow and with an N20 gas flow rate of 40 sccm was also investigated. For films with no oxygen impurities, the index of refraction increased initially with deposition temperature up to 7500C and then it was essentially constant at 1.98 for deposition temperatures between 7500 and 8500C. The abrupt increase in the refractive index may be due to a decrease in the hydrogen concentration, as a major part of the decrease in the hydrogen concentration occurs between 6500C and 8500C. For films with oxygen impurities, the index of refraction decreased as a function of deposition temperature, and showed an especially drastic decrease at 7000C. The data indicates that the decrease in the index of refraction is mainly due to an increase of oxygen content in the film, and their variations essentially complement each other. Figure 3 shows the normalized decay rate (volts/decade/volt) for both written and erased states as a function of deposition temperature for films with no oxygen, as shown by solid triangles, and for films with an N20 gas flow rate of 40 sccm, shown by solid circles. Both the normalized written and erased
661
state decay rates decrease as the deposition temperature decreases, or, equivalently, the hydrogen content of the films increase. The MNOS device retention for erased state and written state improved significantly by 31% and 15% respectively. The behavior of MNOS device retention characteristics with oxygen impurity was similar to that of films with no oxygen. However, additional improvement in the retention was approximately 40%. 0.2 NH3: SiH 2 CL.= 3"5:1
A
K.Z
N2 0 - 0 sccm
N40'40sccm
0.0
>.
UJ
010 ERASED STATE f
650
[
I
750
I
I
850
DEPOSITION TEMPERATURE
(°C
I4
Z-0
"
-0.1
WRITTEN
FIGURE 3: Normalized decay rates determined from the retention measurement for the written and erased states of silicon nitride films as a function of deposition temperatures for the films deposited with N20 = 0 sccm (solid triangle curve) and for films deposited withN20= 40 sccm (solid circle curve).
STATE
The interface state density of metal-nitride-oxide-silicon (MNOS) devices was determined as a function of silicon nitride deposition temperature and postdeposition annealing conditions. The interface state density around the midgap of the oxide-silicon interface of the MNOS structures as a function of deposition temperature between 650 0 C to 8500 C increased from 1.1 to 8.2x101 1 cm- 2 eV- 1 , for as-deposited silicon nitride films; but decreased from 5.0 to 3.5x1 011 cm- 2 eV- 1 , for films annealed in nitrogen at 9000 C for an additional 60 minutes. The interface state density increase is due to an increase in the loss of hydrogen at the interracial region and also to an increase in the thermal stress caused by differences in thermal expansion coefficients of silicon nitride and silicon dioxide films at higher deposition temperatures. The interface state density is subject to two opposing influences; an increase by thermal stress, and a reduction by hydrogen compensation of these states. Thus, either low
662
temperature processing or subsequent hydrogen annealing after high processing temperatures is required. The interface state density of metal-oxynitride-oxide-silicon (MNOS) devices was also determined as a function of the tunnel oxide thickness and the amount of oxygen in the silicon nitride films. As more oxygen was introduced into the silicon nitride film, the lowest oxide-silicon interface state density increased from 3.0 to 3.5x10 11 cm- 2 eV- 1 for 90 A thick oxide MNOS devices, and decreased from 5.1 to 3.65x10 1 1 cm- 2 eV- 1 for 20 A thick oxide devices. The increase in interface state density for 90 A thick oxide devices may be due to an increase in the loss of hydrogen passivation at the interfacial regions as more oxygen is introduced into the film. The higher interface state density for the 20 A thick oxide samples may be due to additional contributions from the trapping states at or near the oxide-oxynitride interface. However, the decrease in the interface state density for increasing oxygen concentration for 20 A thick oxide MNOS devices may be due to passivation of trapping states by oxygen. The silicon dangling bonds responsible for these trapping states may be compensated by oxygen introduced during the deposition process. 9
z
z
N2 0=40 sccM
88
uL
S
B
7, 7 N;
A
FIGURE 4: Endurance characteristics of MNOS the devices where logarithm of the number of write/erase cycles for the MNOS device is plotted as a function of deposition temperature for oxygenfree samples (curve A) and for samples deposited with N20 nn•
650 700
750
800
850
flow r~tQ of
40 sccm (curve B).
DEPOSITION TEMPERATURE (C)
Figure 4 shows the logarithm of the number of write/erase cycles when the memory window collapsed as a function of deposition temperature for films with no oxygen (curve A), and for films with N20 gas flow rate of 40 sccm (curve B). The endurance for the device with no oxygen considerably improved from 2.0xl 06 cycles to 3.0x1 07 cycles as the deposition temperature decreased from 850 0C to 6500 C (curve A). The behavior of MNOS devices with an oxygen impurity was similar to that of films with no oxygen. However, the overall
663
endurance improved considerably to 2x10 8 cycles at 700 0C as more oxygen was introduced in the film of the MNOS devices. The results of the analysis of Figure 4 indicate that hydrogen as well as oxygen in the silicon nitride play an important part in the improvement of device performance. Figure 5 shows a schematic representation of the energetically localized distribution of electron trapping levels associated with chemical impurities/structural defects and silicon dangling bonds within the bandgap of the silicon nitride film of the MNOS device structure. This energy distribution of trapping states was deduced from the preliminary results of trap photodepopulation [6] and electron-spin resonance [7] experiments. Our preliminary results suggested that there are shallow as well as deep traps in the bandgap of the film. The deep memory traps associated with silicon dangling bonds and other structural defects are located between-2.7eV to 4.3eV
SHALLOW TRAPS
L3 C L
DEEP TRAPS
FIGURE 5: Potential energy-level diagram for localized electron trapping states due to silicon-dangling bonds and structural defects within the bandgap of the silicon nitride film. The passivation of the shallow traps are by hydrogen and oxygen.
664
below the conduction band edge. The shallow memory traps are associated with silicon dangling bonds up to 2.5eV below the conduction band edge which may be responsible for degradation of the memory properties of MNOS devices. These silicon dangling bonds [8] passivated by oxygen, which lie within 2.5eV below the conduction band edge, are approximatley 13% of the total trapped electron density in the film. Therefore, it is estimated that hydrogen and oxygen both tie up the silicon dangling bonds and passivate the shallow traps, which are responsible for the memory degradation of the devices. The passivation of the shallow traps allows carriers to become trapped in deep traps and thus yields better retention and endurance properties. An effective photoionization cross-section associated with deep electron traps was determined to be 4.9-18.9x10- 19 cm 2 over the photon energy range 2.06-3.1 eV for oxynitride films containing 7 to 17 atomic percent of oxygen [4]. At a fixed oxygen concentration, the photoionization cross-section decreased from 8.3x10-19 to 4.9x10- 19 cm 2 as the photon energy was lowered from 2.06 to 2.48 eV. However, the photoionization cross-section at a fixed photon energy within this range showed an average decrease of 18% for a 10% increase in the amount of oxygen content in the oxynitride film. The photoionization crosssection increased from 4.9x10- 19 to 18.9x10- 1 9 cm 2 as the photon energy was increased from 2.48 to 3.1eV. Over this higher photon energy range, a 28% decrease in photoionization cross-section was observed for the same 10% increase of oxygen content in the oxynitride films [4]. The scaling of a silicon nitride film in nonvolatile memories is limited by the requirement to trap a significant amount of charge as free carriers drift through the nitride. The film thickness was varied from 600 A to 100 A to investigate the scaling effect on the memory properties of the device. The thinner films showed a higher total trapped charge which was due to an increase in the total injected charge as the nitride thickness was scaled. This was due to a reduction in the field lowering at the injecting interface, allowing for more charge to be injected. All of the above results indicate that the MNOS devices with scaled film thicknesses are ideally suited for ULSI compatible 5 volts EEPROM (electrically eraseable programmable read only memory) applications. CONCLUSION The chemical composition, charge trap density, and charge decay as a function of gas composition and deposition temperature during film deposition support the results of various investigators [7,8], who identify silicon dangling bonds as a likely candidate for trapping sites in silicon nitride. Higher deposition temperatures increase the charge trap density, or, equivalently, the dangling bond density in silicon nitride by reducing the hydrogen content in the
665
films. Auger analysis has shown that oxygen replaces nitrogen in the films, and we have demonstrated that there is a definite correlation between increasing oxygen content in the films and a decrease in the charge trap density. The presence of oxygen in the films reduces the trap density by passivating dangling bonds, which in turn decreases both the charge decay rate and the current conduction. These dangling bonds can also be passivated by hydrogen atoms, again reducing the trap density and further improving the memory properties of the MNOS devices [9]. The practical implication of these results is that the useful memory lifetime of MNOS devices with enhanced endurance to repeated cycling may be realizable by selecting appropriate processing and annealing conditions.
REFERENCES 1.
C.T. Kirk, Jr., J. Apple. Phys., 50, 4190 (1979)
2.
W.D. Brown, R.V. Jones, and R.D. Nasby, Solid-State Elect., 28(9), 877 (1985)
3.
V.J. Kapoor, R.S. Bailey, and R.A. Turi, J. Electrochemical Soc. 137(11), 3589 (1990).
4.
D. Xu and V.J. Kapoor, J. Apple. Phys., 65(3), 1217 (1989)
5.
V.J. Kapoor and J.P. Delatore, J. Appi. Phys., 53, 5079 (1982)
6.
V.J. Kapoor and S.B. Bibyk, Thin Solid Films, 78, 193 (1979)
7.
S. Fujita and A. Sasaki, J. Electrochemical Soc., 132, 398 (1985)
8.
J. Robertson and M.J. Powell, Appl. Phys. Lett., 44(4), 415 (1984)
9.
J.A. Topich, IEEE Trans. Electron Devices, ED-31, 1908 (1984)
666
AN OVERVIEW OF POLYIMIDE USE IN INTEGRATED CIRCUITS AND PACKAGING R. M. Geffken IBM General Technology Division Essex Junction, Vermont 05452 During the past decade, packaging technology has relied increasingly on low dielectric constant polyimides to reduce parasitic capacitances that were limiting computer performance. The use of polyimides in integrated circuit (IC) applications has been relatively low. However, with the advent of ULSI integration, chip interconnects are also becoming major limiters of IC performance. Although the introduction of polyimides as insulators in ICs would have a marked performance benefit, the gating factor to their use will be the confidence level that reliability and quality goals can be achieved. INTRODUCTION Integrated circuit performance and density have been on a very steep learning curve over the past few decades. This has resulted in parasitic capacitances associated with the chip package being responsible for an ever-increasing part of machine performance limitations. About one-half of the IBM 3090's cycle time is attributed to propagation delays in its packaging [I]. POLYIMIDE USE IN PACKAGING The response of the packaging technical community has been to increase the use of polyimides, especially in high-performance applications, because of their low dielectric constant. Conventional multilayer ceramic (MLC) packaging substrates are primarily formed from aluminum oxide. Substituting a polyimide with a 3.5 dielectric constant has the potential to reduce signal propagation delays by 40 % over the base case, as well as aid in reducing crosstalk between adjacent signal wires [2]. Other electronic properties of polyimide materials, such as high breakdown voltages and low dissipation factors, are also compatible with their use in high-performance packaging. Polyimides also have a unique combination of other properties that make them quite suitable for use as a packaging insulator material. Their inherent planarization properties can be used to advantage in high-performance packaging applications where the need for a controlled precise impedance is affected by insulator thickness variability between signal wires and ground planes. Polyimides also have relatively smooth surfaces when compared to ceramic, so they are more compatible with definition of ever-decreasing 667
linewidths for metal signal wires. Finally, as a class of materials, polyimides have cure temperatures and thermal stability compatible with the thermal processing requirements of IC packages. The IBM packaging organization has used polyimide insulators for many years. Its metallized-ceramic polyimide (MCP) package has been used since the early 1980s. It consisted of a simple pinned alumina substrate with two levels of Cr-Cu-Cr wiring separated by a polyimide insulator. C.W. Ho et al. [3] of IBM modeled the performance characteristics of a thin-film module with lossy transmission lines to be used as the top packaging layer on an MLC substrate and proposed a polyimide-insulator copper-interconnect system for the thinfilm module. Jensen et al. [4] of Honeywell described a fabrication process and the superior electrical performance of a polyimide copper thin-film module on an MLC carrier with three interconnect layers. The potential for polyimide in high-performance packaging was further demonstrated by NEC with their SX supercomputer [2]. Five copper-based thin-film wiring layers and four polyimide insulator layers were used on a 100-mm-square ceramic substrate with internal wiring. The thin-film layers included two signal layers, two ground planes and a top metal layer. This configuration allowed high I/O pin counts on the substrate and close spacing of logic chips to further improve performance. The fabrication technology used for these early packaging embodiments of a polyimide-copper thin-film packaging system was primarily subtractive etch for both metal interconnects and insulator vias. This was accomplished by either wet-etch, reactive-ion-etch (RIE) or ion milling. Polyimide planarization over the conductors was accomplished by applying and partially curing multiple coats of material. For example, the degree of planarization of DuPont PI 2555 polyimide over a 10-pm-thick conductor is 20% after one coat and increases to 90% after six coats [4]. A staggered placement of vias between interconnection levels was used to avoid the unmanageable topography associated with stacked vias in this type of technology. Controlling via slopes and metal deposition parameters was critical for achieving reliable metal coverage. Polyimide-copper thin-film multilayer interconnects have continued to gain acceptance in the packaging community for a wide variety of applications. The industry is moving toward higher densities, with reduction in the width and thickness of metal interconnects, vias and insulators [1,5,6]. Applications still include thin-film layers on multilayer ceramics but have been extended to utilize these thin-film techniques to construct chip packaging on Si wafers. Matched thermal coefficient of expansion between chip and substrate and utilization of chip fabrication tooling and processing techniques are some advantages that silicon substrates have over ceramics [7,8,9]. Fabrication technology has also evolved. Techniques to completely fill vias with metal and allow via stacking have become the norm. This was driven by the need for higher density and the realization that copper thermal vias ex668
tending from the top to the bottom of a thin-film module could dissipate heat and compensate for polyimide's poor thermal conductance [10]. Several process sequences are used to form the copper-interconnect line and stud with a polyimide insulator. The most common is formation of the interconnect line, followed by polyimide insulator-apply, planarization, via-etch and then via-fill with copper [5]. Another method is polyimide application and cure, trench-etch and then metal-fill for each interconnect and stud level [9,11-]. A third technique is formation of the metal interconnect line and then the metal stud, followed by polyimide-apply and cure; and, then, planarization-etchback to expose the stud [6]. Both subtractive (wet-etch, ion milling) or additive (liftoff, plating) techniques are used for definition of the interconnect lines. Additive processes (liftoff, plating) are primarily used for the stud formation. Multiple apply techniques for planarization have now been augmented by etchback planarization processes. Each process sequence has unique polyimide material requirements as well as characteristic yield and reliability fail modes. POLYIMIDE USE IN INTEGRATED CIRCUITS Up to this juncture, use of polyimides in integrated circuit technology has not been widespread. Although many technical articles have described polyimide-insulator-based interconnection schemes [12], polyimide use in manufacturing is relatively rare. IBM is a notable exception; it has a 15-year manufacturing experience base with polyimide insulators for dynamic RAMs (DRAMs) as well as bipolar and FET logic [13,14,15]. In the early 1970s, IBM's manufacturing lines began using polyimide as a passive "soft overcoat" layer for final quartz passivation to prevent chip-handling damage. In 1977, polyimide was incorporated as an insulator and passivation for IBM's metal gated DRAM production. Although its low dielectric constant was appreciated, polyimide's planarization properties and its very effective use as part of a dual insulator were the primary reasons for its implementation. The insulation between the two levels of interconnect metal was sputtered quartz plus polyimide, and a dual masking sequence was used for the vias through these two insulators. This technique resulted in a dramatic reduction in metal-tometal interlevel shorts as both a yield detractor and reliability fail mode. The final passivation for the M2 metal was another polyimide film. Polyimide also proved to be very cost-effective when compared to the capital and space requirements for additional sputtered quartz tools. This technology was utilized for DRAM generations from 64K through 128K. In 1982, a second-generation interconnect technology evolved that was extended to 256K and 1-megabit metal gated DRAMs, bipolar logic and IBM's first CMOS logic products. A dual-insulator scheme was retained for the DRAM and CMOS logic processes, but plasma nitride replaced sputtered quartz. The bipolar process introduced an all-polyimide insulation process 669
which also proved to have a very low defect density for interlevel shorts. A third-generation shrink of this same technology is still in high-volume production today; it supplies a majority of IBM's high-function CMOS logic requirements. Chips incorporating polyimide insulation and passivation are being utilized across the entire spectrum of IBM's product lines from 3090 mainframes, AS/400 mid-range systems, RISC 6000 workstations and PS/2 personal computers. A three-level-metal cross section of the CMOS logic family is shown in Figure 1. Note the dual plasma nitride and polyimide insulator between MI and M2, and polyimide only between M2 and M3. Also, a staggered via structure is used to avoid severe topography. The final passivation for all three product generations has been a polyimide film with vias patterned by wet-etch. Viaetch of polyimide on other levels is accomplished by reactive-ion-etch for improved profile control. The metal definition process evolved from wet-subtractive-etch for the initial DRAM process to liftoff at all levels for the second- and third-generation processes. Commercially available Du Pont 2540 PMDA-ODA is used for the insulation between the M2 and M3 interconnects and for final passivation. However, it was unsuitable for use between the M I and M2 interconnect levels due
Figure 1.
Interconnect cross section for IBM's current generation of CMOS logic products. 670
to void formation in submicron high-aspect-ratio spaces. The problem appears to occur because there is substantial cross-linking and rigidization of this polymer formulation before there is appreciable solvent evolution. A polyimide was developed at IBM's San Jose, California, research laboratory which overcame these limitations. The polymer was qualified and has been in use in manufacturing with this logic process since 1987. It should also be noted that the insulator structure depicted in Figure 1 does not yield a hermetic seal of the interconnect wiring at the chip level. These chip technologies have been used with different packaging schemes, ranging from single-chip and multichip modules to wirebond with plastic encapsulants. Most packaging applications have also not provided a hermetic seal of the IC chip. Despite this, there have been no corrosion-related field returns of polyimidepassivated ICs during their 15 years of use. Several areas are considered to be key for controlling the corrosion susceptibility of polyimide-passivated IC chips. Strict quality-control procedures on polyimide materials, including chemical, physical and functional testing, are critical. Good communication with polyimide suppliers is also essential. Processes must be structured to yield good polyimide adhesion to all interfaces both initially and after exposure to high temperature and humidity environments. Scrupulous attention must also be given to eliminating process residuals that can contaminate interfaces. Another area of importance is minimizing chemical exposure to chlorine, which is the prime causative agent in aluminum corrosion. One of the reasons for IBM's successful reliability experience with polyimide may be that only wet-subtractive-etch and liftoff metal definition processes that limit exposure to chlorine have been used. Finally, a physical separation must be provided between the edge of the chip and the kerf region to avoid polyimide tearing and physical disruption of interfaces during wafer dicing. Another successful example of polyimide use in a manufacturing environment was reported by Siemens [16]. Their approach differed substantially from IBM in that they used RIE definition of metal interconnects. This would normally have resulted in exposure of the metal and the polyimide to high concentrations of chlorine during processing. However, Siemens capped each polyimide layer with nitride and,in this way, prevented its exposure to chlorine during RIE metal-etch. Their design rules also resulted in a complete hermetic seal of all polyimide layers with either the Al-based metallurgy or silicon nitride. This type of structure is quite difficult to work with because of the tendency of polyimide to outgas through isolated via structures during subsequent metallization processes. Siemens noted that special precautions were used to control outgassing during nitride deposition and other processes.
671
POLYIMIDES FOR IC ULSI APPLICATIONS IC technologists are beginning to face the same constraints that their packaging counterparts faced in an earlier timeframe. With increasing integration, the trend toward larger chips, and more levels of wiring, chip performance is increasingly being limited by interconnect technology. Indeed, it is estimated that 50% of the signal delay will be attributed to the wiring levels for the next generation of high-performance bipolar chips. Using a polyimide-based insulation scheme with a dielectric constant of 2.8 would allow a 15% improvement in chip performance. Coupling this polyimide-insulator with a copperinterconnect would yield a 23% improvement in performance over the base case of Al alloy interconnects and silicon dioxide insulation. Table I lists some of the desirable attributes of a polymer material for use in ULSI chip-interconnect applications. However, for specific applications, the critical polymer properties are highly dependent on the process flow and technology in which it is used. In some cases, planarization and the ability to fill high-aspect-ratio topography may be critical, while in others not a factor at all. Table 1.
Polyimide properties for ULSI applications.
"*Electrical
"*Adhesion
Properties - Dielectric Constant < 3 - Low Dissipation Factor - Low Leakage
-
Self-Adhesion Metal Adhesion Other Stable at Use Conditions
"*Mechanical
"*Thermal
"*Hermiticity
"*Planarization
Properties - High Tensile Strength - Elongation at Break > 20% - Stable at Process Temperatures
- Minimal Moisture Uptake
Properties - TG > 360 *C - Low TCE - Stable > 400 °C
- Local/Global
Any ULSI wiring process needs an insulating material with the lowest possible dielectric constant. The dielectric constant should be maintained at high frequencies and not degrade excessively when exposed to moisture. Figure 2 shows the dielectric constant variability of several polymer materials, as measured in both low and high humidity environments. In addition, a range of other electrical properties, including dissipation factor, leakage, and breakdown voltage, must be characterized and confirmed to be compatible with high-performance needs. 672
I
0
.5
Figure 2.
Dielectric constant variability for dry to humid conditions for various polymers.
Mechanical properties of the polymer are also an important factor. In general, high tensile strength and especially elongation before break are extremely desirable. The potential reliability implications of cracks in a material that is permeable to moisture necessitates that brittle polymers be avoided. Compatibility of the polymer mechanical properties with the other interconnect materials and processes can be checked by finite-element-analysis modeling. This can predict whether intrinsic stresses, thermal coefficients of expansion (TCE) and stress concentration points result in stresses that are near the polymer fracture strength. It is also essential that the metal-polymer system maintain these good mechanical properties during processing, Figure 3 illustrates the change in tensile strength and strain at break as a function of time at 400 °C for the PMDA-ODA system. Some embrittlement of the polymer is evident after a few hours at 400 'C. Substantial degradation in mechanical properties can occur, depending on the polymer and thermal-excursion time, temperature and environment. Since any advanced high-performance interconnect structure is likely to contain at least four wiring-stud and insulator levels, cumulative processing times at elevated temperatures can become significant and must be considered. 673
I UU,
K 23 -
80
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22:50 Co
C
20
20'
n
"0 Figure 3.
2
6 4 Time at 400*C (Hr)
8
Tensile strength and strain at break vs. time at 400°C for PMDA-ODA.
Polyimide manufacturing and material quality-control issues are also essential to guaranteeing good mechanical properties. It is true that the polyimide chemical structure determines the mechanical properties of the material to a considerable extent. However, the tensile strength and elongation of a polymer with relatively good mechanical properties (PMDA-ODA) is quite dependent on its molecular weight (Figure 4). The molecular weight is not an inherent material property; it is a function of the process used to manufacture the polymer. Obviously, low molecular-weight polymers need to be avoided. In experimental polymers, instances were observed in which the average molecular weight was high but the distribution was either bimodal or had a substantial low molecular-weight tail. These situations also resulted in mechanical-property degradation. Adhesion of the polyimide to itself, as well as all other relevant metal and inorganic interfaces, is as crucial as good mechanical properties. Again, the adhesion must not exhibit significant degradation after exposure to high humidity or the thermal excursions required in processing or applications. However, in this instance, inherent poor polymer adhesion to a particular interface need not be the property that eliminates a polymer from consideration. Since adhesion is basically an interface rather than a bulk property, a wide variety of coupling agents, primers or surface treatments can be used to enhance it. Indeed, the PMDA-ODA polyimide used within IBM for the past 15 years has relatively poor adhesion to a number of interfaces. However, as illustrated in Figure 5, the use of an adhesion promoter can significantly improve adhesion, even after exposure to elevated temperature and humidity environments. 674
200
:F ._o 100 Z 0
e-
20,000 40,000 60,000 Molecular Weight (Mw) Figure 4.
[I
Tensile strength and elongation vs. molecular weight for PMDA-ODA [17].
A
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Amino Silane/PMDA-ODA
0 '7 !0
0
o
. PMDA-ODA
S,
0
Figure 5.
I
I
I
10
20
30
Time at 115 0C/15 psi Steam (Hr)
40
Adhesion of PMDA-ODA and amino silane/PMDA-ODA to SiO 2 as a function of exposure to temperature and humidity. 675
It is certainly desirable in many applications to pick a polymer with a high glass-transition (Tg) temperature. Distortion of metal lines on top of low Tg polyimide has been observed after heating them above the glass-transition temperature. However, low Tg material may actually be useful in relieving some of the stresses built up by polyimide shrinkage during curing. Layered structures of both low and high Tg polymers might be advantageous in some applications. The specific insulator and metal definition processes are as important to the success of a metal polymer interconnect scheme as the choice of the correct polymer. Since polyimide can be permeable to various gases and solvents, it is absolutely essential to understand how each process affects the system. Concern for reliability is the one element that will probably retard the advent of polyimide copper interconnects on ULSI circuits. Quality standards for IC chips are getting ever-more stringent. Process yield and reliability fail modes of interconnect schemes that utilize inorganic nitride or oxide passivation and Al-based interconnects are well documented and understood. The use of polyimide insulators and copper line stud interconnects would require radically different processes, sector sequences and materials. These will undoubtedly have unique process-related yield and reliability fail modes that will need to be discovered and understood. Even if there was significant improvement in the hermeticity of polyimides, many reliability questions would remain. The process and material differences required for ULSI make the existing IC polyimide manufacturing database of limited relevance. To the extent that existing packaging technologies can be extended to ULSI dimensions, some of the reliability learning can be applicable. However, unlike packaging, ULSI interconnect cross sections would be on the order of tenths of micrometers squared and have little margin for error due to any oxidation or corrosion exposure. Spaces between interconnects would be similarly reduced and therefore susceptible to fail modes due to process residuals. There will need to be extreme scrutiny of both wearout and process-defect-related reliability fail modes before releasing any integrated polyimide-dielectric metal interconnect process into manufacturing.
SUMMARY The performance advantage offered by polyimide dielectrics has led to their wide acceptance in IC packaging applications. Use of polyimide dielectrics in ULSI IC interconnect processes also has the potential to provide significant performance leverage. However, there are many unanswered questions about the intrinsic wearout and process-defect-related reliability fail modes for a polyimide-insulator-based ULSI interconnect scheme. Since quality is an even stronger driver of IC technology than chip performance, it is very likely that IC manufacturers will move relatively cautiously to exploit polyimide in ULSI interconnects. 676
ACKNOWLEDGMENTS The author thanks W.T. Motsiff, Dr. D. Hofer and Dr. P. Farrar for their many incisive observations on polymer applications and properties and for their help with the material in this article. REFERENCES 1. C. Chaa, K. Scholz, J. Leibovitz, M. Cobarruviaz and C Chang, IEEE Trans. on CHMT, 12 (4), 180 (1989). 2.
T. Watari and H. Murano, IEEE Trans. on CHMT, 8 (4), 462 (1985).
3. C.W. Ho, D. A. Chance, C.H. Bajorek and R.E. Acosta, IBM J. Res. Develop., 26 (3), 286 (1982). 4.
R. J. Jensen, J. P. Cummings and H. Vora, IEEE Trans. on CHMT, 7 (4), 384 (1984).
5. S. Sasaki, T. Kon, T. Onsaki and Y Yasuba, IEEE Trans. on CHMT, 12 (4), 658 (1989). 6.
N. Iwasaki and S Yamaguchi, IEEE Trans. on CHMT, 13 (2), 440 (1990).
7. J. Bartlett, J.H. Segelken and N.J. Teneketges, IEEE Trans. on CHMT, 12 (4), 647 (1987). 8. K. Hagge, IEEE Trans. on CHMT, 12 (2), 170 (1989). 9. J. Mcdonald, H.T. Lin, H. Greub, R. Philhower and S Dabral, IEEE Trans. on CHMT, 12 (2), 195 (1989). 10. T.A. Lane, F.J. Belcourt and R Jensen, IEEE Trans. on CHMT, 12 (4), 577 (1987). 11. K.K. Chakrovorty, J.M. Cech, C.P. Chien, L.S. Lathrop, M. Tanielian and P L Young, J. Electrochem. Soc., 137 (3), 268 (1980). 12. T. Nishida, A. Saike, Y. Homma and K. Mukai, IEDM Proc., 552 (1982). 13. R.A. Larsen, IBM J. Res. Develop., 26 (3), 268 (1980). 14. R.M. Geffken, IEDM Tech. Digest, 542 (1983). 15. D.L. Bergeron, J.P. Kent and K.E. Morrett, IEEE/IRPS, 229 (1984). 16. H. Eggers, H. Fritzsche and A. Glasl, IEEE VMIC Conf., 163 (1985). 17. M Wallach, J. of Polymer Sci., 6 (A2) (1968). 677
MATERIALS AND PACKAGING FOR OPTICAL INTERCONNECTS:STATUS AND CHALLENGES L. D. Hutcheson Raynet Corporation 181 Constitution Dr., Menlo Park, California 94025 Conventional interconnect and switching technology is rapidly becoming a critical issue in the realization of systems using high speed silicon and GaAs based technologies. In recent years clock speeds and onchip density for VLSI/VHSIC technology has made packaging these high speed chips extremely difficult. A strong case can be made for using optical interconnects for on-chip/on-wafer, chip-to-chip and board-to-board high speed communications. In this paper integrated optoelectronic materials, electronics, optoelectronic devices, and packaging are presented. IOC's are examined from the standpoint of what it takes to fabricate the devices and what performance can be expected. INTRODUCTION The throughput of data and signal processors is being pushed to ever-increasing limits. The development of faster, more complex silicon integrated circuits (ICs) and the use of parallel processing are largely responsible for this improved performance. At the same time, it has been necessary to improve the electrical packaging and interconnect technology in order not to compromise the speed of the IC. In an attempt to develop even faster circuits, major research programs have been started in gallium arsenide (GaAs) and indium phosphide (InP) electronics. One of the goals of these programs is to develop circuits having gigahertz clock rates. One of the problems that must be faced when designing a processor to operate at these higher speeds is the extreme difficulty of transmitting data at gigabit/second (Gbit/s) rates. The performance of electrical interconnects is adversely affected by increases in capacitance and reflections due to impedance
678
mismatches. Multilevel board technology is being developed to address this problem for chip-to-chip interconnects at hundreds of megahertz. The interlevel vias, however, are electrical discontinuities
which become increasingly more troublesome as frequency increases. One solution may be the use of optical interconnects to transmit the data. The optical fiber, integrated optical waveguides and freespace all provide an excellent transmission medium, while optical sources and detectors have been demonstrated at operating frequencies above 10 GHz. In addition to the transmission medium, high speed optical interconnects also benefit from freedom of capacitive loading effects, immunity to mutual interference effects and the flexibility to utilize the third dimension allowing more efficient utilization of space [1]. Other potential benefits include reduced system power, increased fanout capability, decreased complexity, reduced pinout count, smaller volume, increased density, and new architectures not previously possible [2,3]. Integrated Optoelectronic Circuits (IOCs) are circuits that combine both optical and electronic functions and are being developed at a number of laboratories around the world for this application. In this paper the components that make up an IOC materials, electronics, optoelectronics, and packaging - are presented. The parameters that are important to a designer of interconnects (e.g., bandwidth, power, density and bit error rate) are described. Other operating characteristics, such as temperature sensitivity, are discussed to provide an appreciation of what must be considered when the optical interconnect is taken out of the laboratory and designed into a system. The present status of IOCs is described, as well as, a few examples are given for the expected performance of IOCs and their impact on the system. MATERIALS FOR OPTICAL INTERCONNECTS AND IOCs The materials that have received the greatest attention for this application are polymer waveguides and the III-V compound semiconductors (GaAs and InP) and their derivatives. Polymer waveguides are being used for routing signals and interconnecting optoelectronic devices such as lasers and detectors. GaAs and InP based semiconductor materials are being used for integrating optical components such as lasers and detectors on the same substrate as electronics.
679
Polymer
Waveguides
Optical waveguides made from polymers [4,5] are particularly attractive because of their use in printed-wiring-board (PWB) interconnections and multi-chip packaging interconnections [6]. The process for fabricating channel waveguides utilizes standard photolithographic processes used in semiconductor processing. Figure 1 shows a cross section of a typical channel waveguide [7]. The guides consist of a bottom "cladding" layer, a channelized guiding layer, and a top cladding layer. Each layer is exposed and developed before the next layer is applied. The cladding layers are spun onto 10 cm printed circuit boards (Rogers RT DUROIDTM) at approximately 1000 rpm. The higher index guiding layer is spun at 500 rpm ( due to its lower viscosity). Exposure can be accomplished using either mylar or glass emulsion photographic masks. After each exposure the uncured adhesive is rinsed off with acetone. As shown in Figure 1, waveguide dimensions are very large (125 ýtm x 250 pim). The refractive indices of the cladding (1.48) and guiding layer (1.54) at a wavelength of 820 nm yields a numerical aperture of the waveguide of 0.42. The process for fabrication is a direct extension of printed circuit card fabrication. Commercial mask aligner systems are used and because waveguide dimensions are large, standard mylar photographic masks are sufficient for patterning the waveguides. POLYMER WAVEGUIDE CROSS SECTION
Figure 1. Polymer Waveguide Using components
Cross
Section
(Ref. 7).
optical waveguide polymer technology numerous have been demonstrated some of which are straight-
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channel waveguides for simple signal transmission, right-angle bends, branches, and crossover waveguides [8]. As in all communication systems the performance requirements are driven by
Bit-Error-Rate
and optical power
margin specifications
in the
interchip links and by the package topography that restricts layout area or constrains the interconnections so as to meet various mechanical and thermal specifications of the system. Therefore, minimizing the loss of each of these components is extremely important. Typical loss values demonstrated at a wavelength of 830 nm [8] are 0.3 dB/cm for straight channel waveguides, 0.4 dB for right-angle corner bends (900 directional change), 0.15 dB for halfright-angle bends (450 directional change), 0.03 dB for right-angle crossovers, and 0.4 dB for right-angle lx2 splitters. III-V
Compound
Semiconductors
The requirements of the starting GaAs substrate are dependent on the electronics and the optoelectronics. The electronic technologies which are fabricated using selective ion implantation require uniform, high-resistivity substrates which maintain their properties after the implant anneal steps. The circuits which require epitaxial layers for optoelectronic devices are not as dependent on the electrical properties of the substrate, but do depend on the density of defects. Optoelectronic components, especially lasers, are very susceptible to defects in the substrate which propagate up through the active region. These defects have proven to be one of the major causes of short-lived lasers. There has been great strides in recent years for growing "zero-defect" GaAs substrates. It is possible that the success of integrated optoelectronics depends on having nearly zero-defect material. The reason is that the laser lifetime may not be long enough on the high defect standard LEC material [3]. Therefore, low defect density is a must. The requirements for the growth of the epitaxial layers on the substrate are also dependent on the type of component to be fabricated. The electronics technologies requiring epitaxial growth generally need low background carrier concentrations (around 1 x 1013 cm- 3 ) and the ability to control doping accurately. Lasers are not as dependent on electrical properties, but need high photoluminescence efficiency. Waveguide structures need low carrier concentration (low capacitance) and excellent morphology (low
681
scattering). Quantum-well lasers and modulation doped field effect transistor (MODFET) electronics also require extremely sharp interfaces (on the order of a few angstroms) between layers of GaAs and AlGaAs. There are two epitaxial growth techniques that can be considered for use in the production of integrated optoelectronic circuits: molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD). Liquid phase epitaxy (LPE) has been used for years to manufacture high quality lasers and light emitting diodes. The substrates used in LPE, however, are limited in size to approximately 2 in. 2 , which is not compatible with GaAs electronics. MBE [9] has been the standard technique for the development of MODFET structures. MBE can achieve the low background carrier concentrations, layer thicknesses, and sharp interfaces needed for low threshold lasers [10] and optoelectronic circuits [11]. MOCVD is the most common technique today and has the advantage that it can be used for simultaneous wafer growths and the growth rate is higher than for MBE. The layers can be made with very low defect levels. MOCVD is currently being used in production by a number of laser diode manufacturers. The major drawback to MOCVD is its background carrier concentration. Typical MOCVD layers have a background level of around 1 x 1015 cm" 3 . This is not acceptable for either MODFET electronics or waveguide structures. The major limitation appears to be in the purity of the starting metal organic sources. For integrated optoelectronic ICs to meet the needs of high speed processors, it is imperative that the IOCs be fabricated in a way that guarantees an adequate supply of chips. This will occur only if the IOCs are fabricated using a standard GaAs production process to which the extra steps for the optoelectronics have been added. It is very doubtful that a new GaAs electronics process will be developed solely for the purpose of allowing optoelectronic components to be integrated. Figure 2 shows the cross sections of the most common transistors fabricated in GaAs; Fig. 2(a) is the depletion-mode MESFET (metalsemiconductor field-effect transistor), Fig. 2(b) shows the enhancement-mode MESFET and Fig. 2(c) is the JFET (junction FET). Each of these technologies is fabricated using undoped, semiinsulating (108 ohm-cm) GaAs as a starting substrate 13]. The channel and contact regions are formed by selective ion
682
implantations which are activated using a high temperature annealing step. Until now, nearly all GaAs IOCs have been fabricated using depletion-mode MESFETs. Very few demonstrations, however, have used the process as it exists on a production line. The researchers have chosen instead to use a fabrication sequence which is more conducive to experimentation and which does not require the same restrictions on substrate size and uniformity. A detailed discussion of GaAs processing and high speed GaAs IC demonstrations will not be presented here. For the interested reader a review of the production process and state-of-the-art demonstrations for depletion-mode, enhancement-mode, JFETs and MODFET can be found in reference [3]. Source
Gate
Drain
Semi-insula t ing GaAs substrate
(a) Source
Gate
Drain
Semi-insulating GaAs subs t rate
(b) Source
Gate
P* Drain
Semi-insulating GaAs substrate (c) n-GaAs
Figure 2. Schematic (a) Depletion-mode
cross sections of GaAs field effect transistors: MESFET; (b) Self-aligned-gate enhancement-
mode MESFET; (c) Junction FET (Ref. 3)
INTEGRATED OPTOELECTRONIC DETECTORS AND RECEIVERS Semiconductor optical detectors are two-terminal devices that convert optical inputs into electrical carriers. By connecting the detector to an appropriate circuit, the electrical carriers are collected
683
and the signal is amplified to levels adequate to drive a digital IC. The detector and amplifier must be designed as a unit. The integration of the detector with the amplifier provides a significant improvement in bandwidth and sensitivity over a hybrid circuit [3]. The reason for the improvement is that the capacitance at the connection of the detector to the amplifier can be made as low as 0.2 pF for a monolithic circuit as opposed to > 0.5 pF for a discrete detector/amplifier pair. The significance of this can be seen in Figure 3 where the detected optical power versus bit rate for several values of input capacitance is plotted [12] for a BER = 10- 9 . The best experimental results for a hybrid receiver are shown in the figure as closed circles [13] and is consistent with a total capacitance between 0.6 and 0.8 pF. At 1 Gbit/s there is a 5 dBm increase in receiver sensitivity between a hybrid and an integrated receiver. Alternately, this three or fourfold decrease in capacitance would permit the detector/amplifier to be operated at nearly three or four times the bit rate with no degradation in accuracy. From this figure one can also see that the effect of capacitance is even more dramatic at higher bit rates. This is a strong argument for integration.
BIT RATE (Mb/s)
Figure 3. Plot of sensitivity at 10-9 BER versus bit rate as a function of node capacitance (Ref. 12) Detector/Amplifier
Demonstrations
The first and simplest detector/amplifiers reported were p-in/FETs fabricated at Bell Labs in InGaAs/InP [14]. Both the detector
684
and FET were fabricated in epitaxial layers grown by LPE. One such example is shown in Figure 4 where a transimpedance amplifier is integrated with a p-i-n detector [15]. The layers for the detector and amplifier were selectively grown in the two regions by a two-step MOCVD process. The FET layers were grown, forming a nearly planar surface for photolithography. The p-n junction was formed by a Zn diffusion into the lightly doped GaAs absorption region. The technique of selectively growing the p-i-n and FET layers allows for the independent optimization of both circuit segments. For example, high-transconductance FETs require thin (<0.5 gtm) n-type channels with high impurity concentration. The transimpedance amplifier consists of six GaAs MESFETs. The amplifier consists of two stages with a transimpedance of 1 k-ohm. The output impedance is 50 ohm, and the circuit had a 400 ps rise and fall time. A third example fabricated by Honeywell researchers is a GaAs receiver [16], consisting of a detector, amplifier, and a 1:4 GaAs demultiplexer operating at 1 GHz clock rates. The detector is an interdigitated back-to-back Schottky diode with 1 gim lines and 3 jtm spaces fabricated directly on the semi-insulating substrate. The circuit consists of depletion-mode MESFETs fabricated using selective ion implantation on 3 inch diameter substrates. This is truly a production compatible part. PIN PD Au/Zn/Au Au/AuGe
zn-DIFFUSED REGION
Figure 4.
FET At Si 3 N4 AU/Ti Au/AuGe INTERCONNECT
fn-GOAS H.R.-AIo.3 GO?7AS UNDOPED GaAS n--GOAS n -_GaAS SI-GOAS SUBSTRATE
Cross Section of a monolithic receiver (Ref. 15)
INTEGRATED OPTOELECTRONIC TRANSMITTERS The fabrication of semiconductor laser diodes requires crystal growth and processing steps similar to IC manufacturing in order to
685
define the electrical and optical cavity in the two dimensions perpendicular to the direction of light propagation. The length of the cavity is defined by partial mirrors which are formed by cleaving the semiconductor along parallel crystal planes. The integration of the laser diode with the associated electronics is much more difficult from a materials and processing standpoint than the integration of the detector with its associated electronics [3]. There are three major reasons for this: (1) lasers require a multilayered heterostructure up to 7 gim thick; (2) they need two high quality parallel mirrors separated by approximately 200 lim; and (3) a method is needed to achieve electrical and optical confinement in the lateral dimension. Optical
Transmitter
Demonstrations
The first monolithic laser/electronics demonstration was reported by researchers at Cal Tech [171. This component consisted of an AlGaAs laser which was integrated with a GaAs Gunn oscillator. Since that time, there have been numerous demonstrations of different laser and electronic devices in both GaAs and InP material systems. The demonstrations were limited to single lasers, grown by LPE, integrated with a single transistor. The laser mirrors were formed by cleaving. These parts demonstrated the feasibility of integrating lasers with electronics, but they were far from being practical. In more recent years, advances have been made in the areas of crystal growth, circuit design, and complexity which bring these components closer to production. As discussed in the earlier section on material growth both MBE and MOCVD are capable of being used for growth on 3 inch round substrates which are standard for current production of GaAs ICs. Demonstrations have also been reported which show an increase in the complexity of the electronics, an on-chip mirror and power monitor. Figure 5 shows an optoelectronic IC with the laser grown in a well etched in the semi-insulating substrate and has a multiquantum-well active region [18]. The back facet was formed by reactive ion etching and resulted in a laser threshold of 40 mA. The electronics were formed by selective ion implantation into the semiinsulating substrate. The circuit design uses input buffers as well as a differential drive. It was demonstrated at modulation rates up to 2 Gbit/s using nonreturn-to-zero format.
686
CULTS
MONITORI
GOAS SUBSTRATE Figure 5. Integrated optoelectronic laser transmitter with a quantum well laser and selective ion implantation (Ref. 18)
A more sophisticated and complex demonstration consisted of a transverse junction stripe (TJS) laser integrated with a 4:1 2 multiplexer [19]. The chip was approximately 1.8 x 1.8 mm . The 4:1 multiplexer (MUX) and its associated circuitry is formed by selective ion implantation and contains 36 NOR gates (approximately 150 Dmode MESFETs). The TJS laser was grown by LPE in an etched well and the rear facet was formed with an undercut mirror process. This particular chip was tested at speeds up to 160 MHz. PACKAGING TECHNIQUES Packaging optical interconnects presents some very unique and challenging aspects of realizing and implementing this technology. Using the optical domain for communicating between devices complicates the hardware packaging and reliability. Methods must be developed to allow high-speed silicon and GaAs digital electronics to be packaged with optoelectronic components, planar waveguides and fiber optics. Special packaging problems arise when optical interconnects are used with high-speed electronics. Coupling between optical components and waveguides requires critical alignment tolerances. In addition, thermal management is important so the optoelectronic devices do not drift. A technique that has been implemented at a number of laboratories [20,21,22] for aligning several fibers to a multiple 687
detector array is shown in Figure 6. As shown in Figure 6 V-grooves are etched in silicon [23] to provide an excellent alignment fixture since the spacing between the V-grooves can be delineated exactly to match the detector spacing. The exit end of the fiber is polished at an angle such that the light strikes the end of the fiber and is total internally reflected through the bottom of the fiber. Since the fiber used is multimode (50 jtm core diameter), the end of the fiber must be polished at 580 so that all the modes are total internally reflected. Pt,
fixtum
Figure
6.
Fiber
to
detector alignment technique V-grooves (Ref. 20)
utilizing
silicon
Another fiber to chip coupling technique [24] is shown in Figure 7 which allows vertical bonding of the fiber to the chip. A high aspect ratio hole is etched in the silicon substrate (this could be fabricated in GaAs as well) by using a frequency-doubled argon-ion laser at a wavelength of 257 nm for laser-assisted etching in a 5% aqueous solution of HF. The diameter of the hole is controlled (to first order) by the diameter of the laser beam. Once the hole has been etched, a p-n junction detector is fabricated in the hole using standard semiconductor device fabrication techniques. A single mode fiber is chemically etched down to its 9 gim diameter core by immersion in buffered solution of HF for approximately 2 hours. The etched fiber is then inserted into the detector well and attached to the chip using epoxy. This system was tested by coupling a He-Ne laser into the fiber. The measured responsivity was 0.13 A/W with a quantum efficiency of 25%. The advantage to using this technique is the flexibility to put the optical detectors at any position on the chip. Since this technique is not planar, as opposed to the technique described above, an unconventional packaging technique needs to be implemented. 688
licon
12 arm
Figure
7.
Schematic
cross section of a verical coupler (Ref. 24)
mounted
fiber
optic
A packaging technology based upon multichip integration as shown in Figure 8 has been developed at MIT Lincoln Laboratories [25]. Individual die or chips are imbedded in a potting compound and cast. By using standard photolithographic processes, defining connections between the chips becomes fairly routine. Choosing the potting compound is crucial to ensure chemical and thermal compatibility with photolithographic processing steps. A breadboard demonstration was built which consisted of a commercial GaAs shift register (HMD-11141), a mass-transported GaInAsP laser diode [261, a 6 dB attenuator, and an outer-conductor DC block. Using a clock rate of 1.4 Ghz to the input of the GaAs shift register, a chip risetime of 150 ps and a falltime of 120 ps was measured.
Figure
8.
Multichip
package of Silicon, 689
GaAs,
and Opto.
(Ref. 25)
SUMMARY As can be seen by the discussion presented in this paper, there are numerous researchers developing this technology. A lot of attention has been given to packaging high speed silicon VLSI devices with high speed GaAs integrated electronics, opto-electronics and optics. The optimum method for routing the optical signals has yet to be determined. Fiber optics for the board-to-board and local area network applications, polymer waveguides for chip-to-chip, and free-space holographic techniques for intrachip communications appear to have the most promise. The monolithic integration of optoelectronic components with electronics is making rapid progress. The results to date are encouraging for optics to' become an integral part of future high throughput computing systems. For the near term, we can expect several demonstrations of optical interconnects using hyprid components. As the packaging of electical and optical compnents becomes more common, we will learn which applications and which high speed circuits will benefit from this technology. REFERENCES 1. J.W. Goodman, F.J. Leonberger, S.Y. Kung and R.A. Athale, Proc. IEEE, 72, p. 850 (1984). 2. L.D. Hutcheson, P.R. Haugen and A. Husain, IEEE Spectrum, p. 30 March (1987). 3. L.D. Hutcheson, ed., Integrated Optical Circuits and Components:Design and Applications, Marcel Dekker, New York, (1987). 4. D.A. Christensen, Proc. SPIE, Vol. 836, p. 359 (1987). 5. H. Franke and J.D. Crow, Proc. SPIE, Vol. 651, p. 102 (1986). 6. R.J. Jensen, R.B. Douglas, J.M. Smeby and T.J. Morevec, VHSIC Packaging Conf., Houston (1987). 7. D.H. Hartman, G.R. Lalk, T.C. Banwell and I. Ladany, Proc. SPIE, Vol. 994, p.57 (1988). 8. C.T. Sullivan, Proc. SPIE, Vol. 994, p. 9 2 (1988). 9. A. Y. Cho, Thin Solid Films, 100, p. 291 (1983). 10. W.T. Tsang, Appl. Phys. Lett., 40, p. 217 (1982). 11. T. Sanada, J. Yamakaski, 0. Wada, T. Fujii, T. Sakurai and N. Sasaki, Appl. Phys. Lett., 44, p. 325 (1984).
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12. S.R. Forrest, J. Light. Tech., LT-3, p. 1248 (1985). 13. P.P. Smythe, P.J. Chidgey, M.C. Brian, B.R. White, R.C. Hooper and D.R. Smith, Tech. DigestlOth European Conf. Opt. Fibre Comm., Stuttgart, Germany, paper 11B-5 (1984). 14. R.F. Leheny, M.A. Nahary, M.A. Pollack, A.A. Bellman, E.D. Beebe, H.C. DeWinter and R.J. Martin, Elect. Lett., 16, p. 353 (1980). 15. M. Makiuchi, 0. Wada, S. Miura, H. Hamaguchi, H. Hachida, K. Nakai, H. Horimatsu and T. Sakurai, Tech. Digest of IEDM, p. 862 (1984). 16. S. Ray and M.B. Walton, Proc. IEEE Microwave and Millimeter IC Symposium, Baltimore (1986). 17. C.P. Lee, S. Margalit, I. Ury and A. Yariv, Appl. Phys. Lett., 32, p.574 (1986). 18. H. Nakano, S. Yamashita, T. Tanaka, N. Hirao and N. Naeda, J. Light. Tech., LT-4, p.574 (1986). 19. J. K. Carney, M. J. Helix and R.M. Kolbas, Tech. Digest GaAs IC Symposium, Phoenix, p. 48 (1983). 20. P.R. Haugen, S. Rychnovsky, L.D. Hutcheson, A. Husain, Optical Engineering, 25, p. 1076 (1986). 21. D.H. Hartman, M.K. Grace, and F.V. Richard, J. Light. Tech., LT-4, p. 73 (1986). 22. K.P. Jackson, A.J. Moll, E.B. Flint, and M.F. Cina, Proc. SPIE, Vol. 994, p. 40 (1988). 23. E.J. Murphy and T.C. Rice, J. Light. Tech., LT-1, p. 470 (1983). 24. P.R. Prucnal, E.R. Fossum and R.M. Osgood, Optics Letters, 11, p. 109 (1986). 25. D. Z. Tsang, D.L. Smythe, A. Chu and J.J. Lambert, Optical Engineering, 25, p. 1127 (1986). 26. Z.L. Liau, J.N. Walpole and D.Z. Tsang, IEEE J. Quant. Elect., OE-20, p. 855 (1984).
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PROPERTIES OF PECVD O2/TEOS SILICON DIOXIDE * William J. Patrick, Geraldine Cogin Schwartz, Jonathan D. Chapple-Sokol, Kurt Olson, Roy Carruthers IBM East Fishkill, Hopewell Junction, NY 12533
ABSTRACT SiO 2 films were deposited in a commercial single wafer parallel plate plasma deposition reactor using TEOS as the silicon source. Deposition conditions were varied to produce films with widely differing properties. Electrical and optical characterization were then used to investigate the as-deposited film quality. Moisture uptake at 62°C was also determined and related to the initial properties. The films were studied in an ongoing investigation of silicon dioxide interlevel dielectric films used in multilevel ULSI chip wiring.
INTRODUCTION The use of silicon dioxide as the interlevel dielectric in multilevel chip wiring technologies places many requirements upon the film properties. One of the requirements that immediately arises is that the deposition temperature be low enough to prevent thermal voiding in aluminum-based conductors, but not so low that the dielectric properties of the films are adversely affected by the poorer film properties typically observed when low temperature, high deposition rate processes are used. The high deposition rate requirement arises from the facts that interlevel dielectrics are typically quite thick, and most modern deposition systems are single wafer reactors. Dielectric layers a few micro-meters in thickness are not uncommon in bipolar chip wiring. Although the electrical properties of the films can be relaxed somewhat from those used in close proximity to the silicon device surface, a key parameter is the dielectric constant of the insulator. The dielectric constant directly affects chip wiring delays and thus directly influences the performance of the finished chip. Other key properties of the 'dielectric are the electrical leakage and breakdown characteristics which are related to chip reliability issues, as well as the stability of the physical characteristics of the films. Finally, the dielectric must protect the metal wiring from environmental influences such as moisture, which can be a factor in corrosion-induced failure of the chip. In the studies reported here, SiO films deposited in a single-wafer plasma reactor from 02, TEOS (tetraetl~oxy silane) mixtures, were investigated. Deposition parameters were varied over wide ranges, and the film dielectric properties were determined using MOS capacitor measurements of the dielectric constant and breakdown characteristics. Moisture (as -OH and H20) in the as-deposited films was determined using FTIR- spectrum analysis, and the stability of the moisture content was determined by exposing the films to a 62'
692
C, 100% relative humidity ambient. Other features observed in the infrared absorption spectrum are also reported.
EXPERIMENTAL The films were deposited in a commercial plasma single wafer reactor. The silicon source was TEOS liquid which was transported to the reaction chamber with a helium gas flow. The TEOS bubbler was equipped with a mass flow controller on the He inlet side, and a mass flow monitor on the outlet side. The difference in flows measured on both sides of the bubbler was proportional to the TEOS vapor flow (calibration supplied by the equipment manufacturer). A bypass line with its own mass flow controller allowed the total helium flow into the reactor to be kept constant, while the TEOS delivery could be varied by controlling the flow into the bubbler. The TEOS reservoir was kept at 39.6°C and the carrier gas varied to transport 12.6, 21.7, 29.5, and 36.6 sccm TEOS vapor in the majority of the depositions. Total helium flow was kept at 260 sccm by dilution with helium through the bypass line. Another series of runs was made at a TEOS flow of 46.8 sccm, but the TEOS reservoir had to be heated to 43.3°C to achieve this delivery rate. Deposition chamber pressure was held at a constant 8.7 Torr in all runs by throttling the chamber exhaust line. Oxygen flow was held constant at 231 sccm so the oxygen to TEOS flow ratios investigated were between 4.9 and 18.3. The 13.56 MHz rf power was applied to the electrode/gas distribution head and was held constant at 360 watts. The wafer rested on a grounded electrode spaced 0.48 cm below the rf driven electrode. This grounded electrode could be independently heated, so that the deposition temperature was varied from 300°C to 440'. The actual wafer temperature during deposition depended upon heat transfer between the wafer holder and the backside of the wafer. It is estimated that the actual wafer temperature was within 5 to 10°C of the holder temperature. Wafers were 125 mm in diameter and were polished on both sides to facilitate the IR transmission spectroscopy. 10 to 20 ohm-cm p-type wafers were used most often, but some of the electrical characterization techniques required 1 to 2 ohm-cm n-type wafers. Wafers were cleaned with the peroxide "FET" cleaning solutions [1]. Immediately prior to deposition, some wafers were immersed in isopropyl alcohol, deionized water spray rinsed and warm nitrogen spin dried. Reference made to a "standard" process in following sections of this paper corresponds to an oxygen to TEOS ratio of 6.3:1 and a deposition temperature of 390'C. Electrical characterization was carried out using aluminum capacitors formed by evaporation through a metal mask. A large electrode (0.168 square cm in area) was used for dielectric constant measurements, while equal numbers (45 each) of large and 0.0746 cm 2 electrodes arrayed over most of the wafer surface were used in the breakdown field strength determinations to improve the statistics of the measurements, to obtain information on area effects, and to yield information of the film properties over most of the surface area of the wafer. The dielectric constant was determined by averaging values of capacitance measured on 12 large capacitors near the wafer center. The largest source of error in these measurements was the oxide film thickness variation over the measured area. In samples with a large thickness gradient, the film
693
thickness had to be measured at each individual capacitor to give reliable dielectric constant values. About 500 nm of aluminum was evaporated for the capacitors and a blanket deposition of 200 nm was used on the wafer backside to provide the backside electrical contact. Usually, an e-gun evaporation source was used, but for oxide charge determination, a resistance source was substituted. The dielectric constant was determined by measuring the capacitance of the 0.168 cm 2 capacitors with a standard capacitance bridge at a bias voltage determined by measuring the C-V characteristics to ensure the silicon surface was in full accumulation. Measurements were carried out at 10 kHz, and were checked at 100 kHz and 1 MHz on a few wafers to determine that there were no unexpected frequency effects present. Breakdown characteristics were determined by stepping the applied voltage at a rate of approximately 0.02 MV/cm-sec. The voltage at which the first breakdown event occurred (evidenced typically by a current spike greater than 100 microamperes in the case of "self-healing" breakdowns) was used to calculate the breakdown field. Little information could be obtained from continuing to increase the applied voltage through multiple breakdown events until one happened to result in a shorted capacitor. In one instance a true voltage ramp (not stepped) of 10-1 MV/cm-sec was used to evaluate the reliability of the oxide more thoroughly. The index of refraction of the films was determined at the wafer center, using a prism coupler [2]. The infrared absorption analysis was carried out with an FTIR instrument on films 600 to 800 nm thick. Spectra were taken at 4 wavenumber resolution to suppress wafer interference fringes, between 5000 and 400 cm-1 at the wafer center. The -OH and H 0 content of the oxides were measured by estimating the intensities of the 3&50 and 3330 cm- bands and relating these to the corresponding concentrations according to the method given by Pliskin [3]. As with any quantitative IR absorption analysis, an estimation must be made of the transmittance in this spectral region in the absence of any impurity bands (the "baseline"). This is complicated in the case of thin films on silicon substrates since interference fringes exist in the spectrum which are of such a long period that they cannot be removed by loweiing the resolution. Estimation of the baseline was made by curve-fitting a cubic polynomial at both ends of the absorption bands. A visual estimation of the goodness of fit of this approach was made. Spectra which showed poor baseline fit and spectra of a few randomly chosen samples were analyzed by subtracting spectra of samples of thermal oxide of the same thickness which did not contain the absorption bands due to OH or H 20. In the case of the random samples with good baseline fit, the concentrations were the same to within 0.2 weight percent. To determine water pickup of the films, samples were kept in closed containers in an oven controlled at 62°C. Water reservoirs were placed inside the containers to keep the relative humidity at 100% and prevent contact between liquid water and the films.
694
RESULTS AND DISCUSSION A. Initial Studies
The dielectric constant of films produced in the reactor was very consistent
for the standard process. The average dielectric constant of the oxide deposited, using the standard process, on a total of 69 test wafers over a period of several months is 4.09 with a standard deviation of 0.05 (1.2%). The minimum value was 3.99 and the maximum 4.20, a spread of 5 %, and the average remained at 4.1 in samples taken less frequently thereafter. 41 of the original 69 wafers were annealed at 400'C for one hour in forming gas. After anneal the dielectric constant was 4.06 with a standard deviation of 0.03. This by itself was not a significant change in dielectric constant, but it was observed that all samples except one were slightly lower after the anneal. There was no significant difference due to wafer type or to sputter etching after deposition. The dielectric constant was reduced further to a value of 3.80 after an hour anneal at 1000°C in N, in a few samples. It is clear, therefore, that the dielectric constant of tde oxide films produced with the standard process is adequately reproducible for practical applications. An experiment was performed wherein the wafer holder temperature was varied from 300' to 440'C. The index of refraction was measured on the as-deposited wafers but the samples were put aside for a period of months before the measurements were continued. Upon resumption of the measurements, the index of refraction determinations were repeated and they were found to be quite different from the original values. Samples deposited at low temperatures showed a substantial increase, while those deposited at high temperature showed little or no change (fig.l). Dielectric constant measurements showed the low temperature samples had values approaching 5.0 (fig.2). The samples were then annealed at 400'C for 30 minutes in forming gas and remeasured. The results are also shown in figs. 1 and 2. The dielectric constant returned to considerably lower values and the index to its original values. P-etch rates were determined on companion samples, and these results are presented in fig. 3. An interesting thing to note is that although the P-etch rate dropped after the anneal at 400'C, it still shows that the oxide structure varied with deposition temperature. Since atmospheric water absorption was suspected to be the cause of the changes noted, it was decided to expand the investigation to include not only the wafer holder temperature, but also the 02 : TEOS ratio to produce films of widely varying properties, and purposely expose them to a warm, high humidity ambient. B. Deposition Temperature/0
2
: TEOS flow ratio Experiment
Film thicknesses were nominally 650 nm, although some 120 nm samples were evaluated as well. The observed deposition rates are shown in fig. 4. Lower deposition temperature resulted in a higher deposition rate, and decreasing the 02 : TEOS ratio also increased the rate. The variation in dielectric constant for these conditions is shown in fig. 5. Here we see that the dielectric constant shows an overall decrease as higher deposition temperatures are used. The 300°C samples also show a sharp increase at low 02 : TEOS ratios. We will
695
return to the interpretation of this behavior after the IR spectra are discussed. The observed index of refraction is shown in fig. 6 for the as-deposited samples. Low deposition temperatures give lower indices than high temperatures. In addition, there is a considerable dependence upon the 02: TEOS flow ratio. A typical IR spectrum is shown in fig. 7a covering the 5000 to 400 cm-1 range. The -OH band at 3650 cm-1 and H 0 band at 3330 cm- are shown in more detail in fig. 7b, Analysis of the -OI4 and H 0 absorption bands in the as-deposited samples is summarized in fig. 8. The 6H concentration increases as the deposition temperature is decreased and there is also an appreciable rise for flow ratios less than about 8. The H 0 content is plotted for the 3000 samples only, since no H20 was detecteA in samples deposited at higher temperatures. The uptake of water was determined by exposing the samples to 100% relative humidity at 62'C. The behavior of oxides deposited at the three deposition temperatures used was distinctly different. Figure 9a shows that the increase in OH content was relatively small in the 300' samples, but the H 0 increase was considerably greater (fig. 9b). In fig. 9c it can be seen that t&e total hydrogen content, computed from the values obtained in the IR analysis, increased in all the oxides deposited at 300'C. The films deposited at high 02 : TEOS ratios exhibited a smaller increase than those deposited at low ratios. The shape of the curves tended to be similar: an initial rapid rise was followed by a more gradual, diffusion-limited increase. As seen in fig. 10a, the increase in 01-1 for the oxides deposited at 390'C was confined to the low 0 : TEOS ratio samples, as was the H 0 increase shown in fig. 10b. The total hydrogen increase was therefore conAined to the low ratio samples (fig. 10c). Thus, samples prepared with the standard process also eventually picked up water. The only hydrogen increase in the 4400 samples was seen in the one deposited at an 0 : TEOS ratio of 4.9:1 and this was due to a small increase in both OH an(i H126 (fig. 11). As noted in the preceding section, the water pickup was completely reversible, since a 400' C anneal could be used to return the films to the original levels (or lower). Furthermore, samples left at 62°C in a dry container lost water (although not OH). The main Si-O stretching vibration in the vicinity of 1080 wavenumbers decreased slightly in fulf width at half maximum (FWHM) as the OH content rose, and the band maximum also shifted to slightly higher wavenumbers. This has been interpreted to indicate some strained Si-O bonds are destroyed by the incorporation of hydroxyl groups [4]. Some other features of interest observed in the spectra of the as-deposited oxides are illustrated in fig. 12. At high 0 : TEOS ratios, a narrow band (approximately 9 cm-1 FWHM) at 2340 cm , was observed, which indicates that CO was incorporated in these films. While this band was largest for films deposited at 300°C, it was detectable at all temperatures. In the spectra of films deposited using low 02 : TEOS ratios, a weak, fairly broad peak near 2260 cm-1 could be seen, as well as another band at 890 cm-1. These bands
696
suggest a degree of oxygen deficiency in the films, since they are associated with Si-FI and non-bridging oxygen, respectively [5]. C. Correlations Between Properties Figure 13 shows the index of refraction of the as-deposited samples plotted as a function of the total hydrogen content. At first glance there appears to be a definite correlation, but when the data are separated into deposition temperatures, the correlation exists only in the 300'C samples deposited at low 02 : TEOS ratios. The other data cluster as indicated in the figure. We therefore conclude that the index of refraction is a complicated function of many material properties. A definite correlation exists between the dielectric constant and the total hydrogen, as is seen in fig. 14. A linear relationship fits the data quite well (the square of the correlation coefficient is 0.91). The variances increase as the hydrogen content becomes small, probably because of a reduced accuracy of the IR analysis at low hydroxyl contents. The magnitude of the constant term in the regression (3.73) is surprisingly close to the dielectric constant observed after 1000°C nitrogen anneal (Section A. above). Dielectric breakdown The dielectric breakdown field strength was studied in films deposited with the standard process and on various types of substrates. In the figures which illustrate the breakdown characteristics of the films, the cumulative percent failed is plotted as a function of the applied field, E (MV/cm), at which the first event occurred. Table I identifies and describes all of the samples on which breakdown measurements were made and lists the values of the maximum breakdown field, Er,×, the average breakdown field, Ev, and the standard deviation. A breakdown distribution is often seen to consist of two regions: a high-field and a low-field one. The distinction between the regions is often hazy. An abrupt change in slope of the breakdown distribution may be taken as the dividing line, but it is often a subjective judgement. In fig. 15a, the low-field region is very sparsely populated. In figs. 15b and c, and in curve #10 of fig, 15d, the regimes are reasonably clear. Sometimes the distribution extends smoothly from the high field to low field regions, as seen in curve #11 in fig. 15d. The processes involved in the breakdown in the two regions are the same, but breakdown occurs at different rates [6]. The low-fiekl breakdowns are emphasized at low ramp rates of the applied voltage. Therefore, the results will differ at different ramp rates. They will also depend on the electrode area, but the differences may not be obvious if the distributions are very tight. Therefore, unless all measurements are made using the same test conditions, comparisons between different materials/processes may be difficult. We have hesitated to characterize the breakdown process. The high-field breakdowns have been called intrinsic, but that has a connotation that the mechanism is understood, and this does not seem to be so. The low-field or
697
rapid-rate breakdowns have been called defect related; they may be due to impurities or inclusions, or in the view of Av-ron and Shatzkes [6] regions of positive charge. PECVD Si0 2 films deposited in rapid sequence usually had very similar breakdown characteristics; however, in general, the characteristics of the films prepared in this study were much more variable than the dielectric constant. Some of the PECVD oxides deposited in these reactors have exceptionally high values of E a (> 9 MV/cm.) with a very tight distribution of events (fig. 15a). If the low-field region is a measure of defects, this indicates a very low defect level as well as a very high ultimate strength. However, films of approximately the same thickness, deposited under presumably identical conditions, on substrates that were prepared in the same way, were often quite different, as previously mentioned and illustrated in figs. 15a through d. The variability of the results obtained for what we considered to be identical oxides indicates that there may be process differences that have gone undetected. Since plasma deposition is an extraordinarily complex process, involving impact ionization of the feed gases (so that both gas and electron distributions are important), free radical and metastable molecule formation, species transport, surface (and possibly gas phase) reactions, etc., variability may not be altogether surprising. It is possible that breakdown strength is sensitive to small changes in the H content, due to the interaction (inferred from IR measurements) between OH groups and strained Si-O bonds. As seen in fig. 16, the breakdown behavior is influenced by changes in H content (produced by changing the deposition temperature). The films with a higher H content have higher values of E , but the low-field breakdowns were generally more numerous. Although an increase in H content increases the dielectric constant significantly, it also increases E and degrades, only slightly, the dielectric breakdown behavior characterize'm by low-field breakdowns. Also, wafer preparation may be exceedingly important and may not have been controlled properly. It has been reported that, for a material formed in a much simpler kinetic system, i.e., thermally-grown Si0 2, the breakdown behavior depends on surface preparation, cleanliness of the reactor, electrode preparation, etc. [8]. As previous results on other oxides imply, and as we confirm here, it may be very difficult, and possibly meaningless to specify a characteristic dielectric strength, even for a given material prepared in a given reactor according to a given recipe, although such a value is often given. Em, which is often reported as a measure of the quality of the insulator, is of little import in evaluating the usefulness or reliability of an insulator. It is the low-field breakdowns (uncovered using large electrodes, slow ramp rates and the first event criterion), that are the ones most important in evaluating the reliability of the insulator at use conditions. Although we have cast doubt on the reproducibility and absolute value of the results of dielectric breakdown measurements, we report some trends we have observed in series of films, deposited in rapid succession, as we intentionally
698
varied some of the deposition conditions or substrates, and after annealing the films, and by varying the applied voltage ramp rate used in the measurements. The effect of deposition temperature has been discussed above. As the deposition time was changed, i.e., as the film thickness was varied, and we often observed that for the thinner films, the breakdown curve was shifted to lower field values (lower E ax), and the distribution became broader with more numerous low-field breakdowns (fig. 17a). At other times the differences among them were less pronounced although the breakdown distribution for the thinnest film was significantly broader (fig. 17b). For these film thicknesses (250-800 nm) we cannot explain the high-field shifts when they occur. For very thin thermally-grown SiO 2, when the low-field breakdowns were studied they were reported to increase, decrease, or remain constant as the thickness increased [9]. The high-field breakdown was unaffected. When relatively and blanket AICu identical; the low surfaces of the two
thin (280 nm) films were deposited, in sequence, on silicon substrates (fig. 18), the high-field behavior was essentially field breakdowns probably reflected the difference in the substrates.
In one experiment, 2000A of oxide was deposited on an AICu grid (2000k thick) which covered the entire wafer and the electrodes were evaporated as usual. The breakdown characteristics of the oxide on this structure were somewhat degraded when compared to an oxide of the same thickness, deposited sequentially on a bare silicon wafer surface. We attributed the differences to the fact that the thickness of the oxide at the edges of the grid pattern was less than nominal. In addition, field concentration at the edges of the structure may enhance the tendency to break down. As illustrated in fig. 19, the breakdown curve of oxides deposited on n-type silicon was always shifted to lower fields than those deposited on p-type silicon; the electrodes were biased using the proper polarity for each type. This asymmetry has not been noted for thermally-grown SiO 2. Annealing the oxide films reproducibly shifted the entire distributions slightly to a lower field with no increase in the number of low-field breakdowns. The latter is not surprising, since no interaction between Al and SiO 2 is expected at 400'C after one hour. An interaction, leading to shorts, was reported by Chou and Eldridge [10]. after annealing at 500'C for an hour. We cannot explain the shift at the higher fields. Figure 20 illustrates the effect of changing the applied voltage ramp rate in the measurement. In this study, measurements made on four wafers were
combined; the electrode area was 0.018cm 2 . The high field regions are almost
unchanged as the rate is reduced, but, as expected, the number of low-field breakdowns increased at the lower rates. This figure shows that the reproducibility, performance and reliability of these oxides are very good. The charge in a typical oxide deposited in this system was 1.75 xl(O cm-2. This is considered to be an acceptable charge level for an interlevel dielectric. 699
Figure 21 shows a typical I-V curve. The high current at low field indicates the presence of positive charge. As the field is increased, the charge is eradicated. When the field is then decreased, two limiting curves, obtained for different electrodes, are shown. The one on the right indicates that the charge remained eradicated; the one on the left showed that the positive charge was enhanced.
CONCLUSIONS SiO 2 films deposited under various operating conditions can pick up water in appreciable amounts. The presence of OH and H2 0 results in an increase in the dielectric constant. However, films deposited using the standard conditions have relatively small amounts of OH and H 0 in the as-deposited state and show little tendency to pick up moisture luring exposure to warm, high humidity ambients. Even in oxides produced using the same, standard conditions, there is a variability in breakdown behavior. Despite these observations, these oxide films deposited at a high rate in a plasma reactor can be expected to perform well as interlevel dielectrics, once the proper deposition conditions are determined.
ACKNOWLEDGEMENTS P. Johns and T. Desormier deposited many of the films used in this study. We are grateful to M.Shatzkes and M. Av-ron for the illuminating discussions about breakdown measurements and to M. Av-ron who made the low-ramp-rate breakdown and the I-V measurements. D. Buchanan measured the oxide charge. Discussions with W. A. Pliskin about the IR spectra were particularly helpful. J. Marks and E. Yieh of Applied Materials Corporation, Santa Clara, California, prepared some of the films deposited at different temperatures. *
Combined papers, numbers 366 and 367.
REFERENCES [I] W. Kern & D. A. Puotinen, RCA Review 31, 187 (1970). [2] Metricon Corp. PC-2000. [3] W. A. Pliskin in Semiconductor Silicon 1973, eds. H. R. Huff and R. R. Burgess (Electrochemical Society, Princeton NJ) 506 (1973). [4] .J.A. Theil, D. V. Tsu, M. W. Watkins, S. S. Kim, and G. Lukovsky, J. Vac. Sci. Technol, 8, 1374 (1990). [5] W. Knolle, H. Maxwell Jr, & R. Benson, J Appl. Phys., 51 4385 (1980). [6] M. Shatzkes and M. Av-ron, Thin Solid Films, 91, 217, (1982). [7] Private communication [8] P. Solomon, J. Vac. Sci. Technol. 14, 1122, (1977). [9] P. Solomon, ibid. [10] N.J.Chou and J.M.Eldridge J. Electrochem. Soc., 117, 1287, (1970).
700
TABLE I. BREAK-DOWN STATISTICS FIGURE # CURVE ff DESCRIPTION ELECTRODE AREA (CM2) 0.168 A I 15 a 0.075 A 2 15 a 0.168 A 3 15 a 0.075 A 4 15 a 0.168 A 5 15 b 0.168 A 6 15 b 0.168 A 7 15 b 0.168 A 8 15 c 0.168 A 9 15 c 0.168 A 10 15 d 0.168 A II 15 d 0.168 300o CB 12 16 0.168 330'C B 13 16 0.168 360oC B 14 16 0.168 390'C " 15 16 0.168 415'C '• 16 16 0.168 440'C n 17 16 0.168 2540 A c 18 17 a 0.168 3990Ag c 19 17 a 0.168 7900 A c 20 17 a 0.168 2010 A c 21 17 b 0.168 4020 A c 22 17 b 0.168 5850 A c 23 17 b 0.168 8215 A c 24 17 b 0.168 P-Si D 25 18 0.074 P-Si 11 26 18 0.168 AlCu ' 27 18 0.074 AlCu " 28 18 0.168 P-Si B 29 19 0.168 N-Si R 30 19 0.018 1 V/sec.Y 31 20 0.018 0.02 V/sec." 32 20 0.018 0.0004 V/scc.` 33 20
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701
0.18 0.39 0.35 0.75 1.43 0.35 0.98 0.88 1.54 1.15 1.51 0.48 0.35 0.33 0.43 1.34 0.51 0.39 1.20 0.54 0.33 0.46 0.22 0.17 0.74 0.58 0.76 0.95
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703
Figure 7a: IR absorption spectrum over full range recorded in these studies.
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Figure It: Changes in H for 440' samples. Only samples deposited at the lowest 02 :TEOS ratio picked up moisture.
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710
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500
ELECTROCHEMICAL EFFECTS OF HF ON POLYPHENYLQUINOXALINE POLYMER USED IN THE FABRICATION OF PPQ/CU ON SI MULTILAYER INTERCONNECTION MODULES F. Templier, J. Torr~s, A. Halimaoui, J. Palleau and J.C. Oberlin France Telecom, CNET, BP 98, 38243 Meylan, France. Electrochemical behaviour of a PolyPhenylQuinoxaline (PPQ) polymer in hydrofluoric acid (HF) solutions have been investigated through the use of PPQ/metal/Si structures. When such a structure is dipped in HF solution spontaneous reactions occured. These reactions give rise to a dark coloration of the silicon substrate backside attributed to porous silicon formation. The reactions also lead to the polymer reduction which provokes its dark coloration in acidic solution. In order to investigate the mechanisms involved, voltammetric measurements have been performed using these structures. From these electrochemical investigations, two states of the PPQ have been evidenced. The first one is the standard state and corresponds to the as deposited PPQ. The second one is the reduced state resulting from the electrochemical reduction of the standard state. In non-acidic media, these two states exhibit the same yellow colour. When dipped in acidic media, the two phases are subjected to a protonation reaction. During this reaction an orange colour is obtained for the standard film and a dark-violet colour for the reduced PPQ. INTRODUCTION The increasing complexity of VLSI chips, characterized by a high clock frequency and a high number of input/output requires the development of multichip packages providing low signal delays and size reduction. Such systems involve the development of thin film multilayer interconnect modules built using integrated circuit technologies. Since the distance of the connexions becomes much longer, new materials (metal and dielectric) are needed for these technologies . The fabrication of these modules undertaken in our laboratory involves copper as a conducting material (very high conductivity) and a new polymer, PolyPhenylQuinoxaline (PPQ, from CEMOTA) as a dielectric. This material offers low dielectric constant (C < 3) and tg 5 < 10-3 . In our process, a 10 gin thick layer of PPQ is first spun on the silicon substrate (100 mm wafer). Patterns are then defined on the polymer using techniques such as photolitography and etching processes. Conducting lines and vias are obtained by copper deposition and using a lift-off process. The next interconnection level is made by repeating the same technological steps with 5 9tm thick layers. The lift layer used is polysiloxane (Spin On Glass, SOG), soluble in HF. During the process, HF was found diffusing rapidly across the PPQ which is slightly porous. HF solutions induce at least two kinds of effects. Both chemical and electrochemical reactions occur in the module. The chemical effects concerns the polymer itself and are responsible for the exfoliation phenomena occuring at both Cu/PPQ and Module/substrate interfaces. These chemical effects will be discussed elsewhere [1]. In this work, we present new results on electrochemical effects in PPQ. These effects are found to occur spontaneously (without biasing intentionally the system) when structures such as PPQ/Metal/Si are dipped in HF. To elucidate the mechanisms involved 712
and for a best control of the reactions, electrochemical measurements such as current/voltage plots have been performed using intentionally biased structures. Electrochemical reactions involving PPQ [2] and polymers such as diphenylquinoxaline [3,4], polyquinoxaline (5], polyimides (6] or other polymers (7,81 were already studied. However, to the authors knowledge all published electrochemical data on PPQ referred to the dissolved polymer in an organic solvent. EXPERIMENTAL Sample preparation PPQ in o-xylene/m-cresol solution is spun on silicon wafers at 3500 rpm. Both n and p doped silicon wafers were used. A yellow film with 2.5 ýLm thickness is obtained with a 13 % solution. Complete solvent removal is achieved in a first low temperature annealing. The polymer densification is performed at temperatures of 200 and 400 'C for 30 mn in nitrogen ambient. To improve the polymer adhesion, a 100 nm thick metallic layer (Cr or Pt) was deposited onto the silicon substrate prior to the polymer deposition. Electrochemical measurements The current/voltage data reported herein were taken using a standard three electrode arrangement. A platinum wire is used as an auxiliary electrode. The working electrode was biased through a PAR 273 potentiostat. All potentials are measured against a Saturated Calomel Electrode (SCE). In the electrochemical cell used, only the frontside (PPQ side) of the sample is exposed to the electrolytic solution, the backside being electrically connected to the potentiostat. Hydrochloric acid solutions were used in the case of aqueous media. When the experiments are carried out in organic media, we used acetonitrile as solvent and NH4CI as a supporting electrolyte. In some experiments the organic solvent was dehydrated using molecular sieves. Nitrogen was bubbled through the solution prior to each experiment. RESULTS AND DISCUSSION Spontaneous effects When a PPQ/Cr/p-type Si structure is dipped in concentrated (18 M) hydrofluoric acid (HF) we observed changes in the PPQ colour. In the first minute, the polymer became orange. After that it turned to dark violet. The orange coloration occurs even with a single PPQ film separated from the structure and dipped in HF. This orange coloration corresponds to a chemical reaction between the polymer and HF which has been studied in detail elsewhere [1]. The most surprising effect in our case is the change in colour of the backside structure. In fact, this backside which consist of pure silicon (grey colour) and which is in contact with the HF solution becomes dark. This phenomenon occurring at the backside is evidence of porous silicon formation. RBS and Auger measurements performed on this backside revealed only silicon and a small amount of oxygen. It is well known [9,10] that porous silicon is a material which can be obtained by electrochemical dissolution (anodic) of silicon in concentrated HF solution. We conclude that when our structure (PPQ/Cr/p-type Si) is dipped in HF solution, a current flow occurs between the back and the front side of the structure. This current flow is in such a way that electrochemical oxidation occurs at the backside and an electrochemical 713
reduction at the frontside. A possible explanation of such a behaviour is that the electrochemical potentials of the frontside/electrolyte and of the backside/electrolyte systems are so different that while the whole structure is dipped in a HF solution (which is conductive) a current can flow between the two faces through the solution, just like a battery. It is also known [10] that on n-type Si, porous silicon is formed only under illumination (electron-hole pairs generation). We performed some experiment using PPQ/Cr/n-type Si substrate. When such a structure is dipped in HF under illumination, its behaviour is similar to the one obtained with p-type silicon. However, when the same experiment is performed in the dark, there is no porous silicon formation at the backside and the PPQ colour is only orange (not dark- violet). These results are summarized in table I.
Colour
after 1 mn
Colour
after 3 mn
Frontside
Backside
Frontside
Backside
In dark
Orange
None
Orange
None
Illumination
Orange
None
Dk. Violet
Dk. Blue
In dark
Orange
None
Dk. Violet
Dk. Blue
Illumination
Orange
None
Dk. Violet
Dk. Blue
On Si (n):
On Si (p):
Table I: Colorations of PPQ/Cr/Si structures in HF solution.
The same experiments are performed in concentrated (12M) hydrochloric acid (HCI) solutions. In this case, for both structures (n and p type Si), no change in the backside colour is observed and only orange coloration of PPQ is obtained. If we assume that the dark violet colour of the PPQ is related to a current flow, an obvious explanation of the effect observed with HCl is that in this acid the electrochemical oxidation occurring at the backside leads to the formation of an anodic silicon dioxide film. Since this insoluble film is insulating, it stops the current flow and thus the electrochemical reactions which are responsible for PPQ dark coloration. In summary, when a PPQICr/Si structure is dipped in HF solution, a current flows
between the front and the back side through the HF solution. This current flow is related to an electrochemical oxidation at the backside and thus to a reduction reaction at the front side. During the former reaction, the PPQ is reduced. All these spontaneous effects are summarized in Table I. We believe that the orange colour corresponds to the protonated state of the PPQ. This protonation is a pure chemical effect since no current 714
flow is involved. The dark-violet colour may corresponds to the reduced state of the protonated PPQ. The stability of the dark-violet colour depends strongly upon the surrounding ambient. In air, the film recovers its initial yellow colour after only a few minutes. Similar instability has been already reported [51 . However, in non-oxygenated ambient (nitrogen or vacuum) the dark colour remains stable for 24 hours at least. Elastic Recoil Detection Analysis (ERDA) was performed on sample dipped in a HF+DCI solution (where D is a deuterium atom). As the dark colour is unstable in air, the measurements were performed on sample having recovered its yellow colour. A deuterium concentration of about 5.1018 cm- 3 is found in the film. Further ERDA measurements using dark-violet samples (i.e. stored in non-oxygenated ambient) are in progress. Meanwhile, we performed electrochemical measurements in order to have a better control of the reduction reaction occurring in the polymer. Voltammetric measurements AOUEOUS ACIDIC MEDIA: When the samples are loaded in the electrochemical cell, only the PPQ side of the structure is exposed to the solution. A good control of the potentials and thus of the reduction-oxidation (redox) reactions can be easily achieved. Owing to the fact that penalizing chemical effects (layer exfoliation) occur with samples exposed for a long time to HF solutions[l], the voltammetric measurements are performed in HC1 solutions. Fig. 1 shows I (V) characteristic performed on PPQ/Cr/Si samples in HCL. Before applying any potential, the PPQ becomes orange (chemical protonation). A reduction current starts increasing at about -0.5 V and gas bubbles are produced at the electrode. When the potential is held at more reducing values (-3 V), the current increases (curve a, fig. 1) and PPQ turns to dark-violet. When the potential is swept in the anodic direction, an oxidation current appears (curve b, fig. 1). If the potential is held at 3V, the oxidation current decreases (c in fig. I) and PPQ recovers its initial colour. A possible explanation of these effects is that at the rest potential there is no current flow and only chemical effect (protonation) occurs and thus the polymer remains orange. However,when the structure is biased in the negative direction the polymer is reduced and its colour changes to dark violet. The observed bubbles are related to hydrogen production from protons reduction. This reduced polymer is oxidized when the structure is biased at anodic potentials (positive). During this oxidation, the PPQ recovers its initial orange aspect. The PPQ colour can be cycled from dark-violet to orange by biasing the structure from cathodic to anodic potentials.
715
6 4
""'
2 0 -2 -4 -6 -8 A1n
-4
-2
0
2
Potential ( V ) Figure 1: 1 (V) plots for PPQ/Cr/Si in 12 M HCI solutions. Arrows show order and direction of sweep (0,IV.S-'). Surface = 2 cm 2. The same voltammetric cycles were performed using PPQ/Pt/Si structures and the obtained results are similar to the one obtained with PPQ/Cr/Si structures. This shows that the frontside coloration does not involve the metallic interlayer. These electrochemical results are consistent with the spontaneous effects described above. In some experiments, the dark-violet PPQ film is separated from the substrate. When this film is briefly dipped in pure water (pH 6-7) it turns to its initial yellow colour. If the film is now dipped again in acidic solution it recovers the dark-violet colour. During these experiments, no electrochemical effect can occur since the film is separated from the substrate. An explanation of such effects can be given if we assume that during the short dip in water the PPQ film (dark-violet) is only deprotonated but remains in a reduced state (yellow colour). If this reduced but non-protonated PPQ film is dipped in acidic solution it protonates again and becomes dark-violet. This experiment was repeated using a virgin PPQ film (non-reduced). The film is separated from the substrate in order to avoid electrochemical effects. In this case, the film can be cycled from orange colour (in acidic solution) to yellow (in water). These two former colours correspond exactly to those obtained with chemically protonated and deprotonated PPQ films [ 11. According as the polymer is reduced or non-reduced and protonated or nonprotonated its colour changes. These different states are summarized in table II.
716
Non-protonated
Protonated
Non-reduced
Yellow
Orange
Reduced
Yellow
Dk. Violet
Table II: Colour of PPQ vs. redox and acid/base state.
-4
-3
-2
2 3 -1 0 Potential ( V Figure 2: 1 (V) of PPQ/Cr/Si structures in dehydrated acetonitrile (A) and in acetonitrile+2% water (B). Potential sweep=0.1VS-1. Surface=2 cm 2 . ORGANIC MEDIA : Fig.2 shows current-voltage curves obtained from PPQ/Cr/Si structures. Curve A (sample a) refers to the dehydrated acetonitrile and curve B (sample b) to the acetonitrile with 2% of water. Before applying any potential, the PPQ exposed to the solution exhibits its standard yellow colour. In the cathodic direction higher current values are obtained with the hydrated solvent. When the potential is held at a more reducing value (-3V), no colour change is observed for the two samples. The polymer remains yellow for both samples. After this cathodic treatment if the samples are exposed to a concentrated HCI solution for about 20 mn a colour change occurs.Sample (a) becomes orange and sample (b) dark-violet. From the colour listed in table II, we can conclude that sample (a) has not been reduced. Sample (b) has been reduced without any colour change in the organic solvent but became dark-violet when it is protonated in concentrated HCI solution. These experiments shows clearly that water (protons) is needed for the electrochemical reduction of the PPQ. We believe that the overall reaction for the reduction of PPQ is as followed: 717
PPQ + n H+ + ne-
----->
[PPQ]nH
Considering results obtained in the reduction of PPQ [I I], We can assume that hydrogen is bonded at nitrogen sites of the PPQ (fig.3).
Figure 3: PolyPhenylQuinoxaline. Some additional experiments were performed using a molar (IM) aqueous solution of HCI instead of concentrated one. In this case, when the potential is held at more reducing values (-4V) we observe hydrogen bubble evolution but no change in the PPQ colour even when this cathodically treated film is dipped in concentrated HCI. This surprising result means that in 1 molar HCI the PPQ is not reduced. At this time, we have no evident explanation of such an effect. However, we can imagine that only a dissolved PPQ is electrochemically reduced. Since the reduction is obtained only in concentrated HCI and in acetonitrile one can conclude that the polymer is slightly soluble in these two media but remain insoluble in diluted (IM) HCI. We did not perform electrochemical measurements using PPQ dissolved in organic solutions [41. The mean reason is that the aim of this work is to investigate the electrochemical behaviour of thin PPQ films over silicon substrate, i.e when the polymer stands in the interconnection modules. CONCLUSION In conclusion, we have demonstrated that when a PPQ film over silicon substrate is dipped in HF solution, both electrochemical and chemical effects occur. The electrochemical reactions which involve current flow occur even in absence of external current supply. These results were found consistent with electrochemical measurements. Different PPQ colours which correspond to different redox and acid/base states of the PPQ have been also evidenced. We believe that in the reduced state the hydrogen is bonded to the nitrogen sites of the PPQ. This reduced state was found unstable in oxygenated ambient (air). From some electrochemical experiments performed in organic solvent we conclude that the PPQ reduction involves protons (H+). Meanwhile, other characterisation techniques such as Infrared and UV transmission must be used in order to determine the exact chemical structure of the different states of the PPQ. Since this polymer is used as a dielectric in our process, electrical measurements must be performed in order to determine if the electrical parameters such as the dielectric constant and the conductivity of the polymer are changed by the different observed effects.
718
REFERENCES [1] F. Templier, J. Torrts, J. Palleau and A. Halimaoui, to be presented at the MRS '91 Spring Meeting, Anaheim. [2] Z. Chi, L. Tongming and L. Fengcai, Kexue Tongbao, 20, 1697 (1988). [3] K. R. Barqawi and M. A. Atfah, ElectrochimicaActa, 4, 597 (1987). [41 R. Even and M. Petit, Technical report, 1990. [5] S. A. Jenekhe, Macromolecules, 24-1, 1 (1991). [6]
S. Mazur, P. S. Lugg and C. Yarnitzky, J. Electrochem. Soc., 134-2, 347 (1987).
[7]
N.S. Sariciftci, H. Kuzmany, H. Neugebauer and A. Neckel, Phys., 92-7, 4530 (1990).
[8]
G. Froyer, Y. Pelous, A. Siove, F. Genoud, M. Nechtschein and B. Villeret, Synt. Metals, 33, 381 (1989).
[9]
D.R. Turner, J. Electrochem. Soc., 105-7, 402 (1958).
[101
M.I.J. Beale, J.D. Benjamin, M.J. Uren, N.G. Chew and A.G. Cullis, Journalof Crystal Growth, 73, 622 (1985).
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P. Launay and J. Armand, C.R Acad. Sc. Paris,270-23, 1881 (1970).
719
GAP-FILL WITH PECVD SILICON DIOXIDE USING DEPOSITION/SPUTTER ETCH CYCLES Geraldine Cogin Schwartz and Pauline Johns IBM East Fishkill, Hopewell Junction, NY 12533
ABSTRACT The evolution of a process consisting of alternate cycles of PECVD deposition and sputter etching in Ar to fill narrow spaces between adjacent metallic conductors (gaps) with PECVD SiO has been studied. For a fixed process and metal thickness, as Afk (AR = height/width) increases, a low-density region is formed in the gap. At higher AR, physical voids are formed. The ability to fill the gaps with good quality oxide is a function of AR, side-wall angle and the thickness of the metal. Filaments of an unidentified material are detected within the gap. Higher AR spaces can be filled if more of the oxide is sputtered. However, decreasing the thickness of the PECVD film or using 02 instead of Ar has the opposite effect. The low density region in the gap etches at the same rate in a CF 4 plasma; therefore misalignment of vias is not a concern. The dielectric constant of the PECVD SiO 2 is unchanged by sputter etching; the high-field break-down strength of the oxide is reduced. However, after the structure is completed by the deposition of a thick PECVD layer, the effect of the dep/etch cycles on the break-down strength of the composite is not detectable.
INTRODUCTION The difficulty in filling high AR spaces between adjacent conductors by deposition of a film from extended sources is a consequence of shadowing by steps in the underlying structures to be covered by the deposited film. Shadowing results in thinner films on the side walls of a step than on an exposed horizontal surface and minimal coverage at the inside corners of the step [1,2,3,41. Therefore, as the deposition proceeds, the film eventually grows together at the top of a narrow space; this results in an enclosed void within the space. In CVD and PECVD, if TEOS replaces SiH as the Si-source gas in the deposition of SiO 2 the step coverage is improved. This has been attributed to enhanced surface migration of the reactants or of the precursor species along the surfaces [2] or to a decrease in the sticking coefficient of the arriving species [5]. Instead of improving the conformality, attempts have been made to make the TEOS/0 2 process for PECVD highly directional. [6,7,8,9]. However, the improvement in gap-fill has been illustrated only for relatively low AR spaces and thin conductors. 720
In order to fill higher AR spaces, between thicker conductors, processes using sequences of deposition (PECVD and/or CVD) and etch-back steps (RIE and/or sputter etching) in multi-chamber reactors have been developed [10,11,12]. In a somewhat different approach [13], the gap was filled partially with bias-sputtered SiO 2 ; fill was completed by depositing PECVD oxide in another reactor. Relatively high AR between thick conductors can be filled without voids by this process [14] but two separate reactors are used. We studied the PECVD deposition and sputter etch parts of the process described by Bader et al., [12]; we have abbreviated the name to dep/etch. It is a simpler process than the ones decribed in refs. 10 and 11, and less susceptible to contamination than that of ref. 13, which requires tranfer of the wafers between two independent systems. The principle of improved gap-fill by deposition and sputter etching is the same as that invoked in explaining planarization by bias-sputtering [15] i.e., the sputter etch rate depends of the angle of incidence of the impinging ions [16]; an inclined surface etches at a higher rate than a horizontal surface, and a surface parallel to the ions will not be etched. Therefore, the top corner of a step in the deposited film is etched at a higher rate than the film on the horizontal surfaces. The blocking film is thereby etched back so that the acceptance angle presented to the incoming reactants is larger, i.e., the shadowing reduced.
EXPERIMENTAL The dep/etch process we investigated consisted of alternate cycles of PECVD SiO, deposition, using TEOS and 02, and sputter etching in a magnetically-enhanced argon plasma plus a final thick PECVD SiO 2 film adequate to insulate successive wiring planes. The underlying structures were aluminum-alloy conductors formed by reactive ion etching, RIE. The deposition and etch conditions are given in Table I. The standard dep/etch sequence was: deposit 2500A/ etch 500A, although we varied both the thickness of the deposit and the amount sputter etched during the investigation. To examine the effect of taper angle, the underlying metal pattern was formed by lift-off so that the side-walls were 84-85'. In this case, the dep/etch sequence was +6000A/-1200A, but we were not successful in using it for the vertical-walled structures. The completed structure can be partially planarized by chemical-mechanical polishing (CMP) [17] or by resist-etch-back of the final thick PECVD oxide layer, but this step was usually omitted in the work reported here. Deposition and etching were done in separate chambers of a single-wafer multi-chamber reactor with vacuum-transfer between chambers. The chambers were cleaned after each step of the process. The deposition rate was about 7000-8000 A/min; the etch rate only about 300A/min. The experimental technique used to study the evolution of gap-fill as well as the final result was almost exclusively scanning electron microscopy, SEM. 721
Cross sections of the samples were dipped in a buffered-HF solution, BHF, (which also contained glycerine to minimize the attack of the metal lands) to detect regions of different densities within the oxide layer. Other cross-sections of the same samples were etched in an aluminum etch (but not in BHF) to make the photographs more distinct when examining the deposited (unetched) oxide. Thus it was possible to distinguish between low-density regions and physical voids within the gap and to evaluate the etch rates of the oxide in different areas, e g., the side wall vs. the horizontal surface. To investigate the effect of AR, at constant metal thickness, a line/space test-site of varying pitch was used. In order to determine whether the low-density oxide in the gap and the oxide of normal density surrounding it were etched by RIE at different rates, the samples were planarized by CMP, then etched in a CF 4 plasma until the fast-BHF-etching region in the gap was exposed to the etchant. Cross-sections of these samples were then examined with and without decoration in BHF. Cross-sectional transmission electron microscopy, TEM, was used to try to detect differences in density/material in the deposited oxide without the use of preferential etches. We also compared some of the electrical properties of PECVD oxides to those subjected to the dep/etch process, using MOS capacitors with large areas and with low ramp-rates for break-down measurements.
RESULTS and DISCUSSION As in sputter deposition, the higher the AR and the steeper the side-wall angle, the greater the difficulty of void-free filling [18,19, 20]. In the deposition of SiO 2 by PECVD a similar phenomenon is observed. For a given process sequence and metal thickness, as the gap is decreased, at some critical value of AR, a region which etches very rapidly in BHF is seen at the center of the gap. We interpret this as a region of low density or a porous region. At still higher values of AR, physical voids are formed. What had not been reported previously (but is not surprising) is that it is not only the AR itself, but the absolute depth of the gap as well, that determines how well it can be filled. The relationship between the metal thickness and the AR that could be filled without formation of porous regions is shown in fig. I. As in all depositions from an extended source, the side-wall coverage by the PECVD oxide depended on the gap width; the maximum coverage, of an isolated line, was about 60%. The thinner oxide on the side wall has an effect equivalent to a reduction of the AR as seen by the arriving reactants; this facilitates gap-fill. Not unexpectedly, vertical-walled spaces were harder to fill that those with sloping sides in the dep/etch process as well. Figure 2a shows SEMs of fractured cross sections of a series of samples of increasing AR after completion of a 5-step dep/etch process (2 dep/etch cycles + final oxide) and dipped in BHF after fracture. Low-density regions are observed in the higher AR spaces, as mentioned above; in addition, filaments are visible within all the gaps. Our interpretation of the SEM is that the filaments consist of a material that etches more slowly in BHF than the bulk of the oxide. The number of these filaments corresponds to the number of etch steps when the gap is narrow and the walls are vertical. Often a button of 722
material is seen at the corners of the metal stripes. Growth seams are visible within the gap; the interfaces between successive oxide layers are also highlighted. As the AR is increased by decreasing the spacing between conductors of a constant height, the growth seam within the gap widens slightly, enlarges at the base, and finally, successivly larger low-density regions are formed. In gaps of moderate AR, the low-density regions are buried well below the tops of the adjacent conductors. At high AR, they extend to the level of the conductors; we have had almost no samples with metal so thick and spaces so narrow that the low-density region extends beyond the top of the metal. When the cross sections are not decorated in BHF no filaments, buttons, growth seams, or interfaces between layers are visible (fig. 2b). If the AR is high enough, physical voids are formed; these are always smaller than the corresponding low-density region. The progress of the gap-fill process was followed by stopping it after each step and examining fractured cross sections of the resultant structure with and without decoration in BHF. Figure 3a shows the profile of an initial oxide, 2500A thick; after BHF decoration (fig. 3b) it can be seen that the oxide on the side wall was etched at a higher rate than that on the horizontal surface. After sputter etching 500A of oxide from the horizontal surface in Ar, the facet angle of 47' can be seen (fig. 3c). The thickness of the oxide on the side wall appears to be unchanged and none would be expected because of the normal incidence of the ions. We do not detect thickening (re-deposition) on the side-walls. However, when the same structure was decorated in BHF (fig. 3d), two distinct layers are visible along the side wall. In addition, the oxide at the top corner has been etched completely and the thickness of material midway along the wall appears to be greater than in the structure which had not been exposed to BHF. We have no explanation of this apparent contradiction. Figure 3e is the SEM of a sample after a second deposition of 2500A; the gap is filled to about half its depth and the top of the gap is more tapered than in the starting structure. After exposure to BHF (fig. 30, the first oxide layer is, of course, protected from the etch and the film thickness at the top corner is great enough so that it is not etched completely. Along the side-wall, what had appeared as the outer layer in fig. 3d, now seems to be a stubby filament covered by the second oxide. The oxide on the walls near the top of the gap has been thinned. One possible source of the slow-etching filamentary material might be metal sputteied from the underlying conductor, although no attack can be detected. No contaminants were detected by x-ray fluorescence analysis, XFSA, or near the side-wall when examined in cross section by TEM. The filaments were also formed if the the underlying structure was silicon or SiO 2 instead of aluminum-alloy. We then considered the possibility that the the filaments were formed by preferential sputtering of oxygen during etching, leaving silicon or silicon-rich oxide on the walls of the gaps. This would be consistent with a material which etched slowly in BHF. And a faintly denser region was detected near the side-wall in the TEM. However, filaments could not be etched in CF4, or in wet 723
silicon etches. To try to resolve this issue, 02 was substituted for Ar as the sputtering gas. As expected (21], the sputter etch rate decreased to about half its value in argon. As seen in the comparison of the SEMs in fig. 4, on the sample etched in 02, filaments could no longer be detected (decorated sample), but the buttons were still seen. The interfaces between successsive layers were still noticeable, however. The composition of the filaments and buttons has never been identified nor the apparent contradictions resolved. They are not seen in gaps filled by bias sputtered SiO2 or after PECVD of SiO2 which was not followed by sputter etching. The effect of these anomalous structures on the electrical characteristics of the oxide in the gap has still to be determined. For a given thickness of metal and initial oxide deposited, gaps of higher AR could be filled by increasing the amount of oxide sputter .etched, i.e., by increasing the sputter etch time, as illustrated in the graph of fig. 5. The maximum sputter-etch-back time was determined as the time it took to reach, but not attack, the top edges of the conductors forming the sides of the space. Thus, there appears to be a limit of AR to which this process can be extended which will also depend on the thickness of the underlying conductors. Since the sputter etch step was rate-limiting, the thickness of the oxide deposited initially was decreased to minimize the side-wall coverage, and thus, reduce the time required for adequate etch-back. However, this resulted in a much deeper space after etch-back and was self-defeating. The AR that could be filled by a given dcp/etch process was lower when 02 was substituted for Ar. This was attributed to the fact that the facet angle formed by sputter etching in 02 was 67', while, as mentioned previously, the facet angle formed by sputtering in Ar was 47'. Thus the acceptance angle for the arriving reactants was reduced when 02 was used. Because of overlay error in photolithography, the low-density regions between the conductors can be uncovered when the resist pattern for interlevel vias is exposed. Therefore, there is a concern that such vias might be over-etched (luring RIE. We demonstrated that the etch rate in a CF 4 plasma of the low-density material in the gap was the same as that of normal PECVD oxide, as seen in fig. 6. Therefore, mis-aligned vias would not be over-etched if the via im,qge included or abuttdd the region containing porous oxide. The dielectric constant of the interlevel oxide was not affected by the inclusion of sputter etch steps. However, oxides deposited using the dep/etch cycles consistently had lower high-field breakdown strengths, E , than PECVD oxides of approximately the same thickness although the numbers and distributions of low-field breakdowns were comparable. This result is illustrated in fig. 7. One of the causes of the shift to lower break-down strength could be inclusion of particulates, generated by sputter etching or introduced by flaking of poorly adherent deposits sputtered on to the chamber walls. But we found no correlation with chamber cleaning protocol. Another possiblility is is damage due to sputtering; however, this there is no independent evidence for this. The existence of interfaces has been noted, but we do not understand how 724
they would affect the processes responsible for breakdown. None of these, however, seem to be reasonable explanations for the reduction of the high-field breakdown strength while leaving unaffected breakdown events that might be attributed to defects, i.e., the low-field breakdowns. Over-coating the layers formed in the dep-etch cycles with PECVD SiO improves the breakdown characteristics. The structure used as an interlevef insulator included a final thick PECVD SiO 2 layer; it could not be broken down at 1000V. Therefore the degradation of the dielectric breakdown, which appears to be a consequence of sputter etching the PECVD film, is not a practical concern. TABLE I DEPOSITION
SPUTTER ETCH
Wafer-holder temperature = 390'C Input rf power = 350 watts Flow rate TEOS/He = 310 sccm Flow rate of 02 = 325 sccm Pressure = 9.0 Torr Electrode spacing = 185 mils
Input power = 300 watts Pressure = 17 mTorr Ar flow - 50 sccm Magnetic field = 60 Gauss
ACKNOWLEDGEMENTS We appreciate the help of R. Carruthers, B. Cunningham, T. Desormier, K. Olsen and M. A. Zaitz, of IBM East Fishkill and J. Marks and E. Yieh of Applied Materials.
REFERENCES [11CJ.Standley, R.E.Jones, and L.I.Maissel, Thin Solid Films, 5, 355, (1970). 12] R.M.Levin and K.Evans Lutterodt, J.Vac.Sci.Technol., B 1, 54, (1983). 131R.C.Ross and J.L.Vossen, Appl.Phys.Lett., 45,39 (1984). [41 A.C.Adams, Solid State Technology, 26-4, 135 (1983). 151 L.-Y.Cheng, J.P.McVittie, and J.P.Saraswat in ULSI Science and Technolgy 1989, C.M.Osbum and J.M.Andrews, eds., The Electrochemical Society, Pennington, NJ, PV 89-9, 586 (1989). 161J.J.Hsieh, D.E.Ibbotson, J.A.Mucha, and D.L.Flamm, 1989 Proc. IEEE VLSI Multilevel Interconnection Conf., p. 411. 171D.A.Webb, A.P.Lane, and T.E.Tang, in ULSI Science and Technolgy 1989, C.M.Osbum
and J.M.Andrews, eds., The Electrochemical Society, Pennington, NJ, PV 89-9, 571 (1989). 181D.E.Ibbotson, J.A.Mucha, J.J.llsieh, and D.L.Flamm, Flectrochem.Soc.Ext.Abstr. #131, PV 90-1 (1990).
191L.J.Olmer and C.A.Daverse, ibid., #132. [101 O.Spindler and B.Neureither, Thin Solid Films, 74, 67 (1989).
[111J.Marks, K.Law, D.Wang, 1989 Proc. IEEE VLSI Multilevel Interconnection Conf., p.89. 1121 M.E.Bader, R.P.HiaII, and G.Strasser, Solid State Technology, 33-5, 149 (1990),
[13] M.Abe, Y.Mase, T.Katsura, O.tirata, T.Yamamote, and S.Koguschi, 1989 Proc. IEEE VLSI Multilevel Interconnection Conf., p. 404.
1141 G.C.Schwartz, unpublished. 1151 C.Y.Ting, V.J.Vivalda, and H.G.Schaefer, J.Vac.Sci.Technol., 15, 1105 (1978). 725
1161 A.1).Stewart and M.W.Thompson, J.Mat.Sci., 4, 56 (1969). 1171 K.D.Beyer, W.L.Guthrie, S.R.Makarewicz, E.Mendel, W.J.Patrick, K.A.Perry, W.A.Pliskin, J. Riseman, P M.Schaible, and C.L.Standley, IJSPatent # 4,944,836 (1990). 1181 l.A.Blech, D.M.Fraser, and S.E.1aszko, J.Vac.Sci.Technol, 15, 13, (1978). 1191 lI.1'.Bader and M.A.lardon, J.Vac.Sci,Technol., B 4, 1192 (1986). 1201.. S.logan, M1..l1ait, TI.C..lones, G.R.Firth, and 1).B.Thompson, J.Vac.Sci.Technol, A 7, 1392 (1989). 121] R.lF.Jones, 11T.1Winters, and 1,.I.Maissel, .1.Vac.Sci.Technol., 5, 84 (1968). 0.9
FIGURE 1 0.8
ASPECT RATIO of GAPS FILLED with NO POROUS REGION vs. METAL. THICKNESS
S0.7 0•.6 0.5 1.5 13 1.1 09 0.7 0.eo.7 o. k (micr 1.3 m 1e5 Metal Thickness (micrometers)
(7 1,
PIIYS'.A ILVOI)', (NO 1il IOIF( ORA I ION) IN( RIASING AR; MI; IAI - 1.1 MIICRON
FIGURE 2 GAP-FILL INCREASING AR
(a) DECORATED in BHF
(b) NO BHF METAL ETCHED
726
j.I
z
I-
0
0
0
0 0.
727
FIGURE 4 COMPARISON of Ar and 02 as SPUTTER ETCH GAS
(a) Ar
(b) 0 2
FIGURE 5 AR of GAPS FILLED vs. SiO 2 SPUTTER ETCHED
1.1 Porous Reqion
1.0 t,
0.9 -
0.9
0.8
-Z
ý
No Porous Region
0.7 500
750 Amount Sputter Etched (A)
728
1000
FIGURE 6 RIE of POROUS REGION in GAP in CF 4 PLANARIZE, ETCH in CF4
FIGURE 7 BREAK-DOWN CURVES PECVD vs. DEP/ETCH O
K
0 0-4300A
x-398OA
x x x x x x x x x x x x x x x x ×
2X DEP-ETCH DEP ONLY
0 0 0 0 0
e
-
0 0 0 0 0 0 0 0 0 0
2
x x x x x x
0
0
0 0
0
0
0 0
0
I
0
°0 0 0
0 0x
0
I
I
5 FIELD STRENGTH - MV/CM
729
I
I
I
I 10
THE MAGNETRON-ENHANCED ETCHING OF DOUBLE-LEVEL TUNGSTEN INTERCONNECT R. Hsu, C. Y. Fu and B. Law Lawrence Livermore National Lab Livermore, CA 94550
We evaluated dc magnetron-sputtered tungsten (W) and molybdenum (Mo) for double-level interconnect. The combined C12 and NF 3 chemistry was chosen over either gas or SiC14 for magnetron-enhanced etching to achieve better etch selectivity and profile. Tungsten was picked over molybdenum for a more anisotropic etch profile. The etch rate of W depended strongly on sputtering conditions. A reasonably high etch rate at 400 nm/min was obtained with selectivity to resist at about 1.4 to 1. Adhesion layers of 30 nm of TiW or Ta added to either M1 or M2 could be etched by the same recipe with no undercutting. The vertical profile achieved was found to be independent of feature size and had a large operating window in rf power, temperature and overetch time. This process has been successfully applied to define patterns for a double-level interconnect structure.
INTRODUCTION The trend of shrinking features in ULSI design has gradually pushed the aluminum alloy interconnect to its theoretical limitations in terms of electromigration resistance and high temperature compatibility. Refractory metals like tungsten (W) or molybdenum (Mo) become favorable candidates due to their high-temperature stability, corrosion-resistance, and low contact resistance [1]. Although CVD gives better step coverage, the surface is very rough [2-5]. We chose sputtering deposition for the following reasons: (a) the film surface is smooth, (b) no toxic gas used, and (c) adhesion layer or multi-layer can easily be added without breaking vacuum. Adequate step coverage can be achieved for a somewhat planarized topography [1,6-9]. Photoresist patterning of W and Mo with plasma etching using chlorine and/or fluorine etchants usually has problems with profile control, low etch rate, or poor selectivity to resist [2-4]. The higher plasma density associated with magnetron-enhanced reactive ion etching (MIE) as well as better wafer temperature control have been shown to resolve these issues [5]. 730
The purpose of this paper is to study in a sytematic manner the important variables in both the deposition and etch processes that have significant effects on the plasma etch results. A comparison of W and Mo patterning by MIE with different levels of Cl- and F- containing gases follows in order to make the final choice of our double-layer interconnect.
EXPERIMENTAL
Silicon wafers, 4 inches in diameter, were thermally oxidized prior to the deposition of the material to be tested. The first and second level metals (M1 and M2) being evaluated included both W and Mo deposited by dc magnetron sputtering. The original sputtering recipe for W was 1.7 kW power, 63 mTorr pressure, 150 W rf bias power at 175 °C preheat temperature. The W film stress was unpredictable and varied between 600 MPa to 1.5 GPa with resistivity of 50 gohm-cm. The thickness of the films was 200 nm for M1, 500 nm of undoped glass for interlayer dielectric, and 500 nm for M2. The stress of W tends to become highly tensile if annealed above 800 °C [7]. To ensure film integrity during a subsequent 750 °C anneal, a 30 nm adhesion layer of TiW or Ta was also sputtered in-situ for both M1 and M2. One- and two-micron-deep UV photoresists with 30 minutes bake at 120 0C were used in M1 and M2 patterning, respectively. The MIE operating at 13.56 MHz was performed in an MRC ARIES etcher (Fig. 1). Uniform plasma was formed right above the wafer on the cathode by the careful alignment of the counter magnet with the internal magnet. The wafer was held down with three clamps to enhance wafer backside cooling with He at 10 Torr. Both the chamber wall and the cathode had independent temperature control with dual channel heat exchangers. The etch gases studied were SiC14 , C12, NF 3 , and different combinations of NF 3 and C12. Total gas flow and pressure were 40 sccm and 10 mTorr, respectively, in most of the studies. The W thickness was determined by profilometer measurement of step height, subtracting the oxide removed near the dot-mask defined pattern after MIE. The etch rate was then determined after taking into account the fraction of etch time consumed in oxide etch. In order to minimize the inaccuracy of etch rate calculation, the etch time must be estimated properly such that excessive oxide loss can be avoided. The uniformity was calculated based on the maximum and minimum values of five measurement points per wafer.
731
Fig. 1 Schematic of etch chamber for the MIE system. RESULTS AND DISCUSSION The etch rates achieved for W, Mo, SiO 2 and photoresist within the rf power range are summarized for different etchant gases in Table 1.. The following observations were made: Pure Cl etchants in general led to low etch rate and poor selectivity to both SiO 2 and resist. The Cl 2 gas was preferred over SiC14 because of potential SiC14 condensation problems. The NF 3 was chosen as the F source because it contains both F and N, and N might play an important role to passivate the sidewall and provide the end point signal [5]. With pure NF 3 etch, the etch profile is slightly positive for W and positive for Mo. This indicated that N alone did not provide enough sidewall protection until C1 was also added. NF 3 also led to polymer formation and thus resulted in incomplete etch with black residue left on the Mo surface. The combination of C12 and NF 3 at 500 W led to the best results in both selectivity and profile control. We observed a strong dependence of etch rate on the metal sputtering conditions. Most of the W etch rates in Table 1 were based on W prepared from the original sputtering recipe. As the F chemistry was evaluated, the sensitivity of etch rate to the sputter recipe was observed. This explained the range of etch rate listed for W under the 10 sccm and 20 sccm NF 3 columns. The original recipe generally led to a 732
higher etch rate. The optimized recipe was later developed to minimize the film stress. At 27 mTorr, 2.1 kW, 188 W bias and 123 OC, W stress became 500 MPa with resistivity of 18 gohm-cm. The reflectivity stayed at 45%. No pure NF 3 etch rate data for Mo could be obtained because of measurement uncertainties introduced by etch residue. At 20 sccm C12 and 20 sccm NF3 , the variation of W etch rate and its uniformity as a function of substrate preheat temperature (K), sputter pressure (mT), rf power (kW), and bias power (W) are shown in Fig. 2. Different sputtering conditions might lead to different film microstructures and thus cause etch rate variations. The range of temperatures used was low compared with the melting point and thus no difference in phase or grain structure was expected. The increase in etch rate vs temperature might be due to increased outgasing from the substrate holder fixture and possible impurity incorporation into the W film. Similarly, higher pressure might lead to higher degree of Ar incorporation into W. Lower density thus would lead to a higher etch rate. Similarly, increased bias might lead to more energetic bombardment resulting in purer film or higher density and lower etch rate. These arguments were in agreement with the resistivity variations. But further microstructural analysis is necessary before final conclusions can be drawn. The effect of NF 3 addition can be summarized for etch rate in Fig. 3 and for selectivity in Fig. 4. There was a synergistic effect for W etch rate so that mixed Cl and F got higher etch rate than that in either pure gas. But etch rate for oxide or resist with different amounts of added F stayed the same as in pure NF 3. Therefore the W selectivity to resist or oxide reached a maximum of 1.4 at 20 sccm C12 and 20 sccm NF3 . The Mo result were worse in terms of etch rate and selectivity. The optical emission spectra in Fig. 5 show a clear rise in the N signal at 337 nm for blanket W wafer vs oxide, but not as significant an increase for blanket Mo. The corresponding end point curve at 337 nm for patterned W interconnect showed an end point starting at 1 min and completing at 1:15. This rise in the N signal helped support the theory that N was consumed in passivating the newly exposed metal sidewall until oxide is exposed at the end of etch. The etch profile of Mo was found slightly positive while W was vertical. The cross sectional view under SEM showed a vertical W profile from 25 to 100% over etch and changing to slightly positive slope at 150% over etch (Fig. 6). Figure 7 shows the vertical wall and clean etch surface after 100% over etch. Such profile was independent of feature size from 3 to 0.6 micron. The thinner resist on top of the 0.6 micron line was due to developing prior to etch. The profile also remained vertical over a wide window of rf power
733
Table 1
Gas RFWatil W WM S102 Resist
The summary of MIE etch rate of W, Mo, SiO 2 and resist for different gases at the rf values shown.
All SiC14 1 K-2K 500-1K 300-600 500-1 K
1900-3500
3500
All C12 /+10cc NF3 /+20cc NF3 /+30cc PIF3 All NF3 500-1500 500 500 500 500 420-1800 2940-4950 2870-3920 2530 2190-4900 270-1300 1970 2380 2100 1600 170-900 1140 1120 1050 2730 1530-4300 3024 2860 1 1 90 900
44.5
-
4600
3400-
8
4400-
4
7.5
4200 3300
3.5
T
/
4000
-
3
U-ER 310
/
3600-
ETCH RT2
\U-ERI
_/
2
5 4.5
3000
250 300 350 400 450 500 550 600 650
4 n
20
40
60
80 PP•SS
TEMP
8
8 I -•= _1-ER =ErCH RT __
44006
i-
7/
5
4000 3800
4 3600 3 1.5
2
2.5
100 120 140
4800 4600-
7
1
5
ETCHR-
3200
0.5
6.5 \6--I-
3400
,5
3000
7
"
38003200
Z
N /
/
7-
7 6.5
K
-If
5 -50
0
50 100 150 200 250 300 350 1BIAS
Fig. 2 The W etch rate dependence on sputtering (a) temperature (K), (b) pressure (mTorr), (c) power (kW) and (d) bias power (W).
734
6 5.5
3400
3
7.5
0
10
10
NF3 ý.
20
-10
50
40
30
NF3 cc
50
40
30
20
10
0
Fig. 4 The W and Mo etch selectivity to resist and oxide as a function of added NF 3 to C12 at 40 sccm total flow.
Fig. 3 The etch rate of resist, W, Mo and oxide as a function of added NF 3 to C12 at 40 sccm total flow. IMTEMSITI (Q)
Sj02 MOLY TUNGSTEN
0.610
Z90
360
376
366
356
346
336
3Z6
316
386
(um) WAVELENGTH
(Y)
60
68
r
46 26 0 0:
0:20 68
S.
0:40
40 26
.
.
.
]
1:'
I
•
*
I
1:28
I
I r
'
,
I
I
I
:b4
Fig. 5 The emission spectra of (a)oxide, Mo and W, and (b) the associated W end-point curve at 337 nm, for 20 scem C12 and 20 sccm NF3 etch. 735
1 min 15 sec
2 mins
2 mins 30 sec
Fig. 6 Scanning electron micrographs showing that tungsten lines maintain vertical profiles at 25% and 100% over etch and become slightly positive at 150% over etch. I
A A A Al (a) 3 Micron
(b) 1 Micron
AAA (c) 0.8 Micron
(d) 0.6 Micron
Fig. 7 Tungsten lines maintaining vertical profile for features from 0.6 to 3 g.
736
(250-650 W) and cathode temperature (10-65 OC). Better selectivity could be obtained at higher temperature and lower power. Based on the better selectivity, the vertical profile, and the associated negligible CD loss, W was chosen as the Ml and M2 material over Mo. In addition, a lkW initiation step was added to ensure removal of resist residue or native oxide and prevent 'grass' formation. The 20 sccm C12 and 20 sccm NF 3 etch recipe was successfully implemented to define the double-layer pattern as shown in Fig. 8. Different adhesion layers were found to show little effect on etch time or profile.
Fig. 8 The top and cross-sectional views of the double-level W interconnect structures, showing clean etch and good step coverage.
737
CONCLUSIONS A viable MIE process for double-layer W interconnect with vertical profile, reasonable etch rate, and selectivity to oxide and resist has been developed. The combined NF3 and C12 chemistry was simple to run and yet provided adequate end point detectability. The best selectivity to resist was 1.4 using 20 sccm C12 and 20 sccm NF3 . The range of W sputtering conditions we used had a 30% effect on W etch rate. We believe that the selectivity could be nearly doubled if we choose not to minimize W film stress but to maximize the W etch rate instead. With an adhesion layer of 30 nm TiW, acceptable M1 to M2 contact resistance was achieved. Good etch profile was achieved independent of feature size, and with a very big process window in terms of rf power, temperature and over etch time. ACKNOWLEDGEMENT This work was performed under the auspices of the U. S. DOE by LLNL under contract no. W-7405-Eng-48. REFERENCES [1) M.E. Thomas, M.P. Hartnett, J.E. McKay, A.K. Kapoor and J.D. Chinn, in 1988 IEEE V-MIC Conf. Proc., 183 (1988) [21 D.S. Fischl and D.W. Hess, J. Electrochem. Soc., 134, 2265 (1987) [3] W.M. Greene, D.W. Hess and W.G. Oldfam, J. Vac. Sci. Tech., B6, 1570 (1988) [4]
D.W. Hess, Solid State Techno., 4/88, 97 (1988)
[5]
R. Rossen, Microelectronic Manufacturing Techology, 14, 17 (1991)
[6]
F. Hawley, A. Levi, G. Vasche, J.M. Caywood, B. Houck, J. Boyce and L. Tso, in 1988 IEEE V-MIC Conf Proc. 142 (1988)
[7] L. Dori, A. Megdanis, S.B. Brodsky, M. Arienzo and S.A. Cohen, Thin Solid Films, 1931194, 501 (1990) [8] L. Krusin-Elbaum, M.O. Aboelfotoh, T. Lin and K.Y. Aln, Thin Solid Films, 153, 349 (1987) [91 P. Collot, B. Agius, P. Estrache and M.C. Hugon, J. Vac. Sci. Tech., A6, 2319 (1988)
738
SELECTIVE ELECTROLESS METAL DEPOSITION FOR VIA HOLE KILLING AND CONDUCTOR PATTERN FORMATION IN VLSI MULTILEVEL INTERCONNECTION STRUCTURES Valery M. Dubin
Minsk Radioengineering Institute, Minsk, BSSR* The selective electroless Ni-Cu deposition process has been investigated for via hole filling and conductor pattern formation in VLSI multilevel interconnection structures. Cu was added to Al-Si in order to deposit Ni-Cu on AlSi-Cu lines without any activation step and obtain a good selectivity. It was observed that a 0.2 pm Ni-Cu overcoat on a 0.5 pm Al-Si-Cu lines increase corrosion resistance, suppress hillock formation and decrease resistance of interconnections. The Ni-Cu was deposited into via holes on Ni-Cu overcoats of Al-Si-Cu lines without any activation. Via holes in a 1.5 pm polyimide layer were filled by Ni-Cu to the top surface to give completely planarization of interconnections. Good contact resistance has been also obtained without any annealing by measuring the via chain resistance. For comparison selective electroless Ni deposition on Al-Si with Pd activation was also investigated. INTRODUCTION With the continued decrease in device dimensions and increase in scale of integration, modern VLSI (very large scale integration) chips often contain more than one million transistors. As a result, multiple layers of metallization are needed to provide interconnections for these devices. The surface topography created by multiple deposition and etching steps in fabricating the interconnection pattern presents a serious problem for subsequent processing. One of the most challenging issues is the step coverage at via holes because the via holes are not only small in size, but also have nearly vertical sidewalls. Therefore, a via hole filling process is indispensable to achieve a high reliability and a high density of multilevel interconnection structures. W,Pd,Ni,Co,Cu are used to fill the contact holes and via holes in dielectric layers, such as Si02, phosphosilicates glass, borophosphosilicate glass and polyimide [1].
739
The reliability of multilevel metallization also depends on conductor pattern formation process. Because of their favourable properties (low resistivity, good adhesion to SiO, good contact resistance to Si), aluminum and its alloys (Al-Si, Al-Cu, Al-Si-Cu) are widely used as interconnections in manufacturing VLSI circuits. Important problems encountered with aluminum metallization are electromigration, the growth of hillocks during heat treatment and corrosion. Besides, the aluminum surface oxidizes very easily and the contact resistance between the different levels of interconnection becomes very high. In order to improve the properties of aluminum interconnections formed by the conventional processes, the aluminum lines are overcoated with a more reliable material. Refrectory metals or refrectory metal silicides are widely used to improve the current carrying capability, increase corrosion resitance of Al patterns, suppress hillock formation on Al surface and obtain a low contact resistance between different levels of aluminum interconnections [ 2, 3 ]. Relatively few metal deposition processes exist for coating the aluminum films and fill the via holes. One very attractive approach is the selective electroless metal deposition. The electroless metal deposition is potentially a much simpler and less costly process in comparison with other metal deposition processes (vacuum evaporation, sputtering, chemical vapor deposition). The selective electroless metal deposition (with Ni,Co or Pd) has been studied for VLSI multilevel interconnection structures as an alternative to the selective CVD W process [ 1, 4 ]. In these previous studies Ni was selectively electroless deposited on Al after Pd activation. The present paper describes a proces for selective electroless Ni-Cu deposition without any activation step for via hole filling and conductor pattern formation. For comparison, the selective electroless Ni deposition on Al with Pd activation was also studied. EXPERIMENTAL Substrate Preparation. - The substrates used in this study are thermally oxidized 100 mm diam silicon wafers. A 0.5 pm thick Al-Si (1.0 weight % Si) layer and a 0.5 pm thick Al-Si-Cu (1.0 weight % Si and 0.5 weight % Cu) layer were deposited on the wafer surface by a convential sputtering process. The Al layer was patterned with standard photolithography and plasma etching process. The minimum pitch of the metal pattern used in this work is 1.5 um. These samples were then used to study electroless Ni-Cu and Ni deposition on Al, Al-Si and Al-Si-Cu conductor lines. The 740
dielectric layers used in this study were silicon dioxide and polyimide. A dielectric layer with a thickness of 0.80.85 um was deposited on the top of the conductor patterns by a low temperature CVD process. Polyimide (AD 9103) was spun at 6000 rpm onto the conductor patterns on SiO /Si wafers. The samples were subsequently cured by heating to 380 0C for 0.5 hour in a nitrogen-purged oven. A dielectric layer of 1.5-1.6 pm thick polyimide was formed. Via holes of 1.2 pm minimum size were formed in the dielectric layer using standard photolithography and plasma etching. These wafers were then used to investigate via hole filling using selective deposition of electroless Ni or Ni-Cu. For contact resistance measurements, a second Al-Si layer of 0.9-1.0 um thick was deposited on the wafers after via filling. The second Al layer was then patterned using standard processes. The via chain resistance was determined by standard electrical measurements. ComPosition of solution. - Aluminum surfaces are not catalytically active for Ni deposition. Therefore, palladium is often used for surface activation [ 1 3. The composition of a typical Pd activation solution used here is given in Table 1. Many different compositions of solutions for electroless Ni and Ni-Cu deposition have been tested. The compositions of Ni and Ni-Cu solutions giving the best results for conductor pattern formation and via hole filling are presented in Table 2 - Table 4. RESULTS AND DISCUSSION a.Conductor pattern formation. The selective electroless Ni deposition process with Pd activation was used to clad the aluminum lines. It was observed that the grain sizes of the Ni films range from 0.2 pm to 0.5 pm. However, undesired Ni deposition between Al and Al-Si lines was also found. Thus the dielectric surface (SiO ) between the aluminum lines was also activated by Pd deposition. Table 1. Composition of a Pd deposition solution Chemicals
Concentration (ml 11)
PdCl?
0.2 g
HCI
1
Glacial acetic acid
500
HF (50:1)
250
741
Table 2. Composition of a solution for electroless Ni deposition [ 5 ]. Chemicals
Concentration
NiCI, 6HO
0.13
NaHPO, HO
0.1
sodium citrate
0.37
(mol 1"1)
NHCI
0.93
NH40H
Adjust pH to 8.5-9
Table 3. Composition of a solution for electroless Ni-Cu deposition on Al lines ( 6 ]. Chemicals
Concentration (g 1-1)
NiSO4 7HO
50
CuSOL 5HO
0.8
NaHPO, HO
15
citrate
acid
50
NH4CHCOO 3HPO
40
NH40H
Adjust pH to 8.5-9
Table 4.
Composition of a solution for electroless
Ni-Cu deposition for via hole filling [ 7 ] Chemicals
Concentration (g 1"1)
NiCl, 6HO
25
NaHPO, HO
25
NaCHCO0
3HO
5
glycine
30
cystein
0.02
CuS04 5HO
0.25
NH4 OH
Adjust pH to 5.0-5.5
In order to discuss how the dielectric surface becomes activated we will simulate the experimental conditions during this deposition. The potential distribution between
742
the Al lines on a dielectric layer (SiO2 ) can be estimated using Poisson equation
S+ ax 2
_ 2 ay
_
-_I
e'-e
P (X)
(1)
where c0 is the permittivity in vacuum, e is the dielectric constant, p. is the fixed oxide charge density. The solution of equation ( 1 ) in this case is described in detail in Ref. 8. The calculated potential between Al lines is shown in Fig. 1 for various fixed charge values in the dielectric layer and for various values of Al line potentials.
1
0.5
i
CD
0
A V
0
0.5
1
(y 1 0-6 M) Fig. 1. Distribution of the electrical field between Al lines on a dielectric layer. a)-h=10"6 m, 1=10-6, p =10-4 q 6 m"2 V=5V; b)1-h=10" M, 1=10 6 M, p q M-=10" V=-5V; c)6 6 h=10" M, 1=10. M, p'=10"4 q m"2, V=0V'9; d) -h=10"9 m, 1=10-6 m, ps=10"4 q m"2 , V=-IV. The symbols denote: h - thickness of Al lines; 1 - distance between Al lines; p - the fixed charge in dielectric layer; V - potential of Al line. 743
It is commonly accepted that SiO has a positive fixed oxide charge. But it can be seen from Fig. 1, that if the potential of the Al lines is negative the potential between Al lines on the SiO2 can also be negative (Fig. lb and Fig. id). Thus positive Pd ions can be adsorbed on the SiO2 surface having negative potential and be reduced. This may occur in the aqueous solution used for Pd deposition. Because of Al dissolution, the Al lines have negative charge. The Al surface is not catalytically active for Ni deposition. Since a Cu surface is catalytic for Ni deposition with sodium hypophosphite as a reducing agent [5], this process can be simplified by using Al-Si-Cu alloys as catalytic surfaces for Ni deposition without any activation step. Figure 2 shows Ni-Cu deposition on Al-Si-Cu without activation step. Cu was added to the Ni solution in order to increase the corrosion resistance of the deposited film, decrease the grain sizes and obtain a more (also without Pd smooth surface [ 6 ]. In this case activation of Al surface) no Ni-Cu deposition between AlSi-Cu lines on dielectric surface was found. Hillock formation on Al-Si-Cu lines was observed after 510 0C annealing during 30 min in N2 atmosphere. Reduced hillock formation on the Al lines was obtained
Fig. 2.
Al-Si-Cu lines with Ni-Cu overcoats. 744
with a 0.1 pm thick Ni-Cu overcoat. With a 0.2 tim Ni-Cu layer on a 0.5 pm Al-Si-Cu line complete suppression of hillock formation was obtained even after 510 0C heat treatment for 120 min. Measurement of the resistance of Al-Si-Cu/Ni-Cu conductor lines show that after an annealing cycle to 450 OC for 30 min in N atmosphere the resistance of a 0.5 pm AlSi-Cu lines with a 0.2-0.3 pm Ni-Cu overcoat was reduced by a factor of more than 1.2-1.3. The decrease in resistance of the Al-Si-Cu/Ni-Cu system after annealing can be explained as due to recrystallization of Ni-Cu at this temperature [ 5 ]. The investigation of the corrosion resistance of AlSi-Cu/Ni-Cu conductor lines shows that the Ni-Cu overcoat improved the corrosion resistance of Al-Si-Cu conductor line. No corrosion was observed after a treatment of AlSi-Cu/Ni-Cu lines in 60 0C hot water for 200hr. It was found that under these conditions the aluminum was completely consumed in the presence of small amounts of halide contamination. b.Via hole filling. Via holes were patterned in dielectric layers such as CVD Sio2 or thick polyimide layer by standard photolitography and plasma etching processes. The use of the thick polyimide layers (the thickness is more than 1 pm) makes it possible to achieve planar surfaces, to improve the dielectric and mechanical properties of the polyimide layers and to increase the frequency range of VLSI circuits. In order to fill the via holes (the nominal sizes are from 1.5 pm to 5 pm) in thick polyimide layers (the thickness is about 1.5 pm), the selective electroless NiCu and Ni deposition was applied. After Pd activation and selective electroless Ni deposition into via holes it was observed that the deposited Ni is over 0.5 pm thick with the edge somewhat thicker than the middle. If the electroless Ni deposition into via holes is continued for a long time the Ni film grows also on the dielectric surface. If via holes are situated very close to each other accidental connections between the via holes are observed. The activation of the surface in the via holes can be avoided if the Ni-Cu overcoats of Al lines are used. This is because of the Ni-Cu surface being catalytic for electroless Ni deposition. Copper ions and surfactant (cystein) were added in the Ni solution to obtain very smooth Ni-Cu surfaces and to decrease the lateral growth of Ni-Cu pillars. It was observed that the rate of Ni-Cu deposition was 0.25-0.3 pm/min with pH=5-5.5 and tempera745
ture 90-95 0C. Via holes were filled to the top surface to give a completely planar surface (Fig. 3).
Fig.
3. Via holes filled by Ni-Cu.
In comparison with selective Ni deposition on Al surfaces into via holes after Pd activation, the thickness of Ni-Cu on Ni-Cu surfaces in the via holes is larger in the middle than at the edges of the via hole. Ni-Cu pillars were obtained when the electroless Ni-Cu deposition process was continued for a long time. No connections between pillars in via holes was found. c.Via chains. Via chains are formed by two Al layers. The first level of Al-Si-Cu pattern is connected to a second level of Al-Si pattern through a via hole, the second level of Al-Si pattern is connected to another first level of Al-Si-Cu pattern through a second via hole. A via chain pattern of any desired length can be formed by repeating this structure. In this work, the via holes were filled by selective electroless Ni and Ni-Cu deposition before the deposition of second Al layer. For selective electroless Ni deposition into via holes the palladium activation process of Al was applied. For selective electroless Ni-Cu deposition into via holes the overcoat of first level of Al-Si-Cu pattern was applied, the Ni-Cu was deposited into via holes without any activation process. 746
Figure 4 shows a wafer surface after the via holes Al-Si-Cu layer was 0.5 were filled with Ni-Cu. The first gm thick with a 0.2 gm thick Ni-Cu overcoat. The polyimide layer was 1.5 pm thick, the second Al-Si layer was 1 pm thick. As can be seen from Fig. 4, these vias were filled to the top surface to give a planar surface of interconnections.
Fig. 4. Two-level interconnection structure with via holes filled by Ni-Cu (the polyimide layer was removed) The resistance of the chains was measured by electrical probing; the measured resistance for via holes filled by Ni-Cu is very low before annealing. After annealing the resistance is insignificantly increased. This corresponds2 to a specific via resistance of less than 1 10.9 ( cm The before and after annealing (450 OC, 30 min, N,). measured resistance for via holes filled by Ni is very high before annealing, after a 450 °C nitrogen annealing cycle resistance value of less than 150 m R per via has been obtained.This corresponds 2 to a specific via resistivity of less than 1 10.8 R. cm . CONCLUSIONS Selective electroless Ni-Cu deposition process has been studied for via hole filling and conductor pattern formation in VLSI multilevel interconnection structures. Cu 747
was added to Al-Si in order to deposit Ni-Cu on Al-Si-Cu without any activation step and obtain a good selectivity. It was observed that Ni-Cu overcoats of Al-Si-Cu lines increase corrosion resistance, suppress hillock formation and decrease resistance of interconnections. The Ni-Cu was deposited into via holes on Ni-Cu overcoats of Al-Si-Cu lines without any activation step. Ni-Cu filled vias with a planar surfaces were obtained. Good contact resistance was measured also without annealing. ACKNOWLEDGMENTS Many discussions with J.Bottiger,
N.Karpe
and K.K.Larsen
are gratefully acknowledged. Thanks are due to V.Smolskij for assistance with respect to the potential distribution calculation. *Present address: Institute of Physics, Aarhus, DK-8000 Aarhus C, Denmark.
University
of
REFERENCES
[1) C.H.Ting and M.Paunovic, J.Electrochem.
Soc.,
136, 456
(1989).
[2) E.G.Colgan, Materials Science Reports,
5,
1 (1990).
[3] V.Smith, H.Norstrom, U.Wennstrom, A.Johansson, I.Engstrom and Z.Toth-Pal, J.Vac.Sci.Technol., 8, 499 (1990). [4] C.H.Ting, M.Paunovic, P.L.Pai and G.Chiu, J.Electrochem. Soc., 136, 462 (1989). [5] V.V.Sviridov, "Electroless metal deposition in an aqueous solutions", Buelorussia University, Minsk (1987). [6) I.Z.Prebish, in "Hard and wearproof electroless and electroplating coats", MHNTP, Moscow, p.85 (1984). [7]
Author
certificate
No
1110818
(USSR),
in
B.I.,
32
(1984).
[8] A.A.Samarskij, Moscow (1977).
"The theory
748
of circuits",
Science,
NOVEL METHOD FOR PREVENTION OF PARTICLE DEPOSITION IN WET LSI PROCESSES A.Saito, K.Ohta, Y.Takahara and H.Oka Production Engineering Research Lab. Hitachi, Ltd., 292 Yoshida-cho Totsuka-ku, Yokohama, 244 Japan ABSTRACT A novel method to prevent particle deposition by controlling the zeta potential of the particles has been developed. The repulsive force between a particle and a substrate is increased when the zeta potential becomes low. The zeta potential control is realized by adding organic solvent to the solution. 2-amino ethanol is found to be very effective for changing the zeta potential of hydrophobic particles and that of hydrophilic particles using nonionic surfactant together. The prevention of particle deposition is demonstrated for 0.2 - 1.0 pm-size polystyrene particles. INTRODUCTION As semiconductor devices are manufactured more finely, deposition of smaller particles deteriorates production yield and device performances. Simulation of particle deposition[l,2], which is based on a particle-diffusion model, indicates that small particles very easily adhere to Si wafers in wet LSI processes. As even 0.05 pm-size particles would affect the production yield of a 16M bit DRAM, it becomes very important to prevent particle deposition in wet processes. We have clarified that particle deposition depends on a balance between the van der Waals force and repulsive force of electrical double layers between a particle and a substrate[1,2]. The increase in the repulsive force induces the suppression of particle deposition. The repulsive force can be changed by controlling the zeta potential, which is related to the electrical double layer. The zeta potential of particles was changed with the pH of the solution[3] or by adding ionic surfactant to the solution. But when the ionic strength in the solution becomes too high, particles easily adhere to the Si wafer. Therefore we can't use such ionic materials. In this paper we investigated the effect of adding polarized materials such as organic solvent.
749
EXPERIMENTAL 0.2 -1.0 pm-size polystyrene particles (Dow chemical), 1 pm-size Si particles, SiO2 particles and Fe particles (Ko-jundo kagaku) were used as dispersed particles, and ntype Si wafers (Shin-etsu Kagaku) as deposited substrates. Organic solvents (alcohols, aldehydes, organic acids, amino-alcohols and fluoric-alcohols) were used as polarized materials. Each solvent was added to ultra clean water containing dispersed particles. The concentration of solvent was 0.00001 - 10%. Nonionic surfactant (Emulgen 120, Kao Corporation) was used for hydrophilic particles together witl organic solvent. The concentration of surfactant was 10-- mol/l. The zeta potential of the particles was measured by electrophoresis[4] using LASER ZEE TM Model 501 (Pen Kem). The particle deposition experiment was performed as follows. A Si wafer was dipped into ultra clean water including 5 x 10-3 mol/l NaCI with dispersed polystyrene particles. Since 0.2 -1.0 pm-size particles don't adhere to a Si wafer in ultra clean water stationarily, the experiment was made in such ionic strength. After dipping the wafer for 5 minutes, the wafer was dried by spinning. The number of particles deposited on the wafer was measured using an optical microscope. The same treatment was made after adding the organic solvent to the water. RESULTS AND DISCUSSION Si particles pre-cleaned by dilute HF showed zeta potential of -23,7mV, The zeta potential was changed
by
Table 1
Zeta potential change by adding organic solvent Additive
Zeta potential (mV)
adding
various organic solvents to water as shown in Table 1. Alcohols were especially effective. The zeta potential of the Si particles was changed from -23.7 mV to -47.3 mV by adding ethanol with 1% concentration. Si wafer and most of the particles show negative zeta potential, therefore the repulsive force increases
Ethanol
-4
7 .3
Acetaldehyde
-2
6 .7
Acetic acid
- 3 1 .1
Methyl
-3
5.5
acetate None
750
- 23.7
when the zeta potential becomes lower. Table 2 shows the zeta potential change various adding by Ethanol or alcohols. more was 2-propanol to change effective the zeta potential than 1-propanol or Ibutanol. The electron polarization in these molecules was thought the zeta to affect the But potential. is momentum dipole almost the same for as alcohols these The shown in Table 2. distribution of elecwas density tron obtained by ab-initio orbital molecular calculations in order to consider the mechanism of zeta potential The results change. are shown in Figure 1. are Hydrogen atoms omitted to be displayed.
Table 2 Additive
Zeta potential change by adding alcohol Zeta Potential
Dipole momentum
(mN)
Methanol
1.66
-40.5
Ethanol
1.68
-47.3
ProPaaul
1.66
-4 8.8
2-
1 .6 8
-- 4 6 .5
1 .6 8
-2 24. 1
1.63
-2
PrePanel 1Butanol 2-
1.4
Butanol 2 3 .7
None
-0. 74 -0.74
-0 74
"0.00"
49
+0.1
shear plane
-0.32
-0.49 0
-0.5
particle surface zeta potential -47.3mV
-28.8mV ep
n
-24. lmV
-46.5mV
banol2-propanol
Fig.1 Adosorption model of alcohols on particle
751
The value in this figure means elecCH for a neutral tron density. The value 0.8 4 N atom is zero and the value for a high negative. electron-density atom is C Figure I shows the adsorption model of alcohols onto a particle. The ethanol .74 or 2-propanol has a high electronH density atom on the shear plane (slip plane), which is the border between a moving particle and the liquid. This Fig.2 2-amino ethanol result is reasonable since the zeta potential is an electric potential in the shear plane. The calculation was applied to materials which have N or F atoms with high electron negativity. It was clarified that the N atom in 2-amino ethanol had a higher electrondensity (-0.84) than each atom in the ethanol(Figure 2). This means that 2-amino ethanol can be more effective. When the 2-amino ethanol was added, the zeta potential of the Si particles was measured to be -62.lmV, which was the lowest value obtained in this study. Various particles affect the production yield of semior Fe(material of conductor processes, such as Si, SIO producing apparatus). The zeta potentlai of those particles was measured when 2-amino ethanol was added(Table 3). The zeta potential of hydrophobic particles such as polystyrene or HF treated Si was changed by adding 2-amino ethanol. However the zeta potential of hydrophilic particles such as Si(not treated by HF) or Fe was scarcely changed. This Sio adsorbed on the particle is because 2-amino ethanol wasn't surface. Therefore we used nonionic surfactant in order to The experiadsorb 2-amino ethanol on the particle surface. mental results are shown in Table 3. The zeta potential of hydrophilic particles was changed by adding 2-amino ethanol and nonionic surfactant. Table 3
None
Zeta potential change for various particles (mV) Fe S i 02 S i Bare-Si* SPoIYstyrene -- 2 2 ,1 -3 7.8 -4 3.1 -2 3.2 -50.4
2-Amino ethana4 2-Amino ethanol+
-7
1.3 -
-6
2.1 I
Noninnic surfactant
-5
6.0
-7
0.1
-45.1 -7
2.3
I
* S1 treated by HF
752
-3
0,2
-5
7.6
The effect of 2-amino ethanol on particle deposition was evaluated experimentally. Figure 3 shows the relationin the solution and the ship between the ionic strength number of depositing particles in the case of 0.2 pm-size polystyrene particles. Particles adhered to the Si wafer at mol/l. But when 2-amino ethaabove 10 an Ionic strength nol was added(•O] moi/l), particles were able to adhere The relationthe between ship and size particle the number of deposat particles iting the ionic strength is 5 x 10 - mol/ shown in Figure 4. By adding 2-amino 5 mol/l), ethanol(10the number of deposparticles iting became less than one tenth.
M c
0
Ionic Strength (mol/1) Fig.3
Relation between ionic strength and depositing particles 2-Amino Ethanol
o:10-5mol/I
A:O
Ct
3
Ionic Strength 5xO- moW/ U
'A 0.51
0ý5 Particle Size (pm)
0
Fig.4
1
Prevention of particle deposition by zeta potential control 753
CONCLUSION The zeta potential of particles can be changed by adding organic solvent to water. Alcohols were especially effective for changing the zeta potential. The effect of zeta potential control by adding 2-amino ethanol was demonstrated in this experiment. The production yield of LSI would be improved by using "Zeta potential control methods".
REFERENCES l)A.Saito et al.:Extended Abstracts of the 21st Conference on Solid State Devices and Materials, p409-412 (1989) 2)A.Saito et al.: submitted to Japanese Journal of Applied Physics 3)I.Ali et al.:SEMICONDUCTOR INTERNATIONAL APRIL 1990, p92-95 4)A.Delgado et al.: Acta Polymerica,37, p361-364 (1986)
754
LOW-TEMPERATURE IN-SITU NATIVE OXIDE REMOVAL USING ANHYDROUS HYDROGEN FLUORIDE Pushkar P. Apte, Krishna C. Saraswat Center for Integrated Systems, Stanford University, Stanford, CA 94305 and Mehrdad M. Moslehi, Richard Yeakley Semiconductor Process and Design Center, Texas Instruments, Dallas, TX 75265
ABSTRACT A new low-temperature, gas-phase cleaning technique using Anhydrous Hydrogen Fluoride that removes native oxides and carbon in situ prior to film deposition has been demonstrated. The technique is simple and manufacturable, and it is selective in that it removes surface oxides grown by both air and wet chemical cleans, but leaves thermal oxides intact. The efficacy of the technique is shown by both physical analysis and the growth of specular epitaxial silicon. Keywords: Anhydrous Hydrogen Fluoride, in situ dry cleaning, lowtemperature cleaning, native-oxide removal, silicon epitaxy.
INTRODUCTION Advanced semiconductor technologies with sub-micron geometries impose stringent requirements on Ultra Large Scale Integrated (ULSI) device manufacturing. This is manifest in the increasingly exacting demands on the quality of films, on the tolerances for dopant diffusion and on selectivity of deposition/etch processes. The sensitivity of film quality to the atomic-level cleanliness of the surface immediately preceding film deposition underscores the need for effective in situ cleaning. Long process sequences and the need for precisely tailored dopant profiles combine to restrict the thermal budget of individual steps, which requires that both cleaning and deposition be done at low temperatures. The broad objective of ULSI-compatible cleaning research is then the search for an in situ, low-temperature, selective and manufacturable process. This work demonstrates a new dry cleaning technique using Anhydrous Hydrogen Fluoride (AHF) that meets all these challenges effectively, in that it is performed in situ, its operating temperature range is 325-750°C, and it selectively removes native oxide while leaving thermal oxide untouched. Furthermore, the technique is simple to implement and can remove oxides grown by both air and standard wet cleans, which enhances its adaptability to the manufacturing environment. 755
MOTIVATION The main sources of wafer contamination are impurities introduced by the equipment, the ambient, the reactive gases and the wet chemicals. The main contaminants of an exposed wafer surface include a thin layer of non-stoichiometric silicon oxide, metallic ions, organics and particulates. The traditional approach is to remove these ex situ using a series of wet chemical cleans and rinses. However, as processing moves into the ULSI domain, it is becoming increasingly evident that wet cleaning presents significant problems. One is that precise process control is difficult to achieve. Another is the incompatibility with modular equipment such as cluster tools and single wafer processors: incorporation of liquids in this environment is neither easy to implement, nor desirable. A corollary is that in situ wet cleaning is not generally feasible. Another significant problem is that aqueous chemicals may not penetrate sub-micron features due to surface tension. It may therefore be inferred that dry cleaning is of critical importance for ULSI technology. While the goal is to replace the entire wet cleaning sequence with dry processes, native oxide removal represents the most immediate challenge, since even a Si surface which has been stripped of oxide with an HF dip will regrow an ultrathin native oxide layer within a short time. The key factor for oxide growth is the partial pressure of H20 and 02 in the ambient. It has been shown that a critical value for the partial pressure exists for different temperatures [1, 2]; above which an oxide layer will form. This information can be used to maintain an oxide free surface in a vacuum system. The regrowth of a surface oxide layer during storage has also been studied by several workers. The results differ, since the rate and ultimate thickness of the regrown layer are a function of the ambient that the wafers are exposed to. For instance, growth of a monolayer of oxide has been reported to occur within one hour [3, 4]. On the other hand, wafer storage in a single wafer polycarbonate package immediately following an HF dip took a few days for a monolayer to form, with the growth rate increasing after a week [5]. Similar results were obtained in an ambient with moisture restricted to less than 0.1 ppm [6]. While the native oxide can be controlled using special facilities, the complete ex situ elimination of oxide contamination is difficult. Also, it is sometimes desirable .to leave a passivating oxide layer on the wafer to reduce other contamination during wafer transport and storage. Thus the development of an in situ native-oxide removal technique is imperative.
IN SITU DRY CLEANING TECHNIQUES These generally fall into three broad categories, namely use of Ultra High Vacuum (UHV) systems, energetic beam techniques and thermal-chemical techniques. Epitaxial growth of silicon at temperatures of 825°C has been demonstrated in a UHV system [7]. The basic idea in this approach is to hold the H2 0 and 02 in the ambient to levels below the critical levels determined by the previous studies [1, 2]. However, significant system complexity is introduced by the requirement of a base 756
pressure of 10'
Torr. Energetic beam techniques may be sub-divided into physi-
cal and chemical techniques. The former have been demonstrated using an Ar ion plasma [8, 9] at temperatures of 710-7500C. Physical sputtering is constrained by
the limited window within which the clean is effective: too little results in insufficient impurity removal, while too much causes lattice damage. Energetic beams have been also used to enhance the chemical reaction leading to oxide removal. For instance, photochemical cleaning using Ultraviolet(UV) light irradiation in an H2 ambient [10] has been shown to remove surface oxides. From a manufacturing perspective, UHV and energetic beam techniques suffer from the drawback that they increase system cost and complexity, since they typically require special hardware or custom-made chambers. Also, wafer throughput is usually very low, due to the long cycles required for system preparation and actual processing. Thermal-chemical techniques may be divided into high and low temperature techniques. High-temperature techniques use H 2 or HC1 for their cleaning action. Apart from the obvious drawback of a high thermal budget, additional problems such as faceting for HCl and oxide undercutting for H2 bake limit the use of these techniques in the ULSI domain. Low temperature gas-phase cleaning techniques that have been studied include GeH 4 , NF 3 and HF. GeH 4 cleaning has been found to be effective [11, 121 in removing native oxide, although further optimization is needed. The possibility of Ge incorporation into the subsequent film may limit the process domain of this technique. NF 3 seems to require a relatively high temperature (800°C) post-clean bake [13] to be effective. Also NF 3 is non-selective to the type of the oxide and etches quartz, which would degrade reliability in systems with quartz ele-
ments. Significant effort has been targeted at native oxide removal using the vaporphase cleaning action of HF at room temperature. It has been demonstrated that native oxide removal can be achieved without significant addition of metallic impurities [14, 15]. A regime for the selective removal of native oxides has been identified by Miki et al. [16]. However, it was found that this leads to passivation of the surface with fluorine. High temperature annealing (930°C, 1 hour) and bombardment with Ar ions was unsuccessful in removing the fluorine, and Xe lamp irradiation was needed. Vapor-phase HF cleaning will be discussed later, in the context of contrasting
it with this work.
EXPERIMENTAL APPROACH This work describes the use of a mixture of AHF and H2 for the selective removal of surface oxides in a low-temperature regime, with no moisture added. We do not see any corrosive action of the gas-phase reaction even though the chamber walls, quartz elements and plumbing have not undergone any special passivation treatment. Further, we demonstrate in our results that we do not have any fluorine passivation of the silicon surface. The work was done in a single wafer cold wall reactor, with rapid heating provided by tungsten-halogen lamps [11]. The first set of experiments consisted of testing 757
Table 1: Parameters for a typical AHF clean HF H2 50 sccm 150 sccm
Temperature 325°C
Time 200 sec
Pressure 300 mTorr
Table 2: Oxide etching observed for a typical AHF clean Oxide PSG TEOS Chemical Oxides Thermal Oxides
Extent of Etch (A) 80-100 25-40 3-4 NO ETCH
the etching rate of the AHF clean on wafers with blanket oxides. The types of oxides tested included oxides grown by wet chemical cleans, oxides deposited using tetra-ethyl ortho silicate (TEOS), phosphosilicate glass (PSG), and thermal oxides. The thicknesses were measured immediately before and after the pre-clean with a Prometrix Spectramap machine for all oxides except the thin chemical oxides, which were measured with an ellipsometer. In the second set of experiments, the AHF pre-clean was followed by in situ deposition of epitaxial silicon using SiH 2 Cl 2 and H2, at a temperature of 980'C and a pressure of 5 Torr. Parameters for a typical cleaning step are shown in Table 1. Some out-of-the-box wafers were processed, but all the in situ cleaning and deposition results presented are for wafers that had undergone a wet chemical clean (NH 4 OH:H 2 0 2 ), followed by a rinse and dry cycle, prior to being inserted into the chamber. The efficacy of the clean was evaluated by examining the substrate-film interface with Secondary Ion Mass Spectrometry (SIMS). A control sample that had not undergone any in situ cleaning, and had the Si film deposited under identical conditions as the wafers with the pre-clean, was used as a reference. The quality of the deposited layers was examined by optical microscopy, using polarized light.
RESULTS AND DISCUSSION The extent of etch due to a typical AHF clean on wafers with blanket oxides is shown in Table 2. The fact that the pre-clean has no effect on thermal oxides establishes the selectivity of the pre-clean unambiguously. A variety of temperatures, flows and times tested yielded similar results, indicating that the process window for selectivity is quite large. It should be noted that the chemical oxides grown by wet cleaning are typically only 10-12 A thick, and the relatively small (3-4 A) etch observed may be due to regrowth of native oxide between processing and measurement, 758
I
I.
10 C
I
III'
I
I
FILN
UTiEWAM
SUSSIUM1A
U.
Figure 1: SIMS profiles: (a) control wafer, and (b) pre-cleaned wafer since no in situ thickness measurement technique was available. Chemical oxide removal is demonstrated by specular epitaxy and the SIMS results since, as stated earlier, all presented results for in situ cleaning and film deposition are for wafers that had undergone a wet chemical clean prior to insertion in the chamber. The SIMS profiles for a control wafer that did not have the pre-clean and that of a wafer pre-cleaned according to conditions described in Table 1, are shown in Figures 1(a) and 1(b) respectively. The substrate-film interface is indicated by the impurity peaks. The effectiveness of the AHF pre-clean is underscored by three key features that emerge from a comparison of Figures 1(a) and l(b). Firstly, the oxygen peak is sharply reduced, indicating interracial oxide removal. Secondly, the interracial carbon peak also decreases sharply. This is a unique feature, which has not been demonstrated for most other low-temperature chemical native oxide removal techniques. And lastly, the absence of any significant fluorine at the interface implies that the technique does not face the problem of fluorine passivation. Figures 2(a) and 2(b) are optical micrographs of the films deposited on the control and pre-cleaned samples corresponding to Figures 1(a) and 1(b) respectively. The topography of the film on the control sample is extremely rough, while the pre-cleaned sample shows a smooth film surface. This is consistent with the preliminary observation in white 759
1
10 im
Lim
Figure 2: Optical micrographs of films on: (a) control wafer, and (b) pre-cleaned wafer light of a hazy film for the control sample, as opposed to the clear specular film on the pre-cleaned one. This also highlights the sensitive dependence of Si films on the presence of surface oxide and carbon on the starting substrate. Since moisture- activated 'vapor-phase' HF cleaning has been extensively studied, it forms a logical starting point in the search for possible mechanisms of the AHFbased cleaning described in this work. Recent work has described the vapor-phase cleaning action as being similar to that of aqueous HF, with a condensed surface film of HF/H 2 0 effecting the etch [171. The moisture for this condensed film may either be intentionally introduced or may simply be derived from that present in the background and in the carrier gases. As the etching is incumbent on the formation of the condensed film, the cleaning action in this regime is predicted to not work above 40'C and indeed, this is consistent with experimental observations. Also, selectivity in the vapor-phase regime is due to varying moisture contents of different oxides, which in turn leads to different incubation times for the condensed film. Since our work demonstrates cleaning at temperatures above 300'C, where the formation of a condensed film is highly unlikely, it follows that we are operating in a regime that is different from the vapor-phase one. Experiments are currently in progress to try and identify the mechanism of the technique described in this work. One interesting point is the role of temperature, and the SIMS results of some preliminary experiments are shown in Figure 3. The cleaning conditions were the same as those described in Table 1, with the exception 760
I
I
Figure 3: (a) Oxygen and (b) Carbon profiles for wafers cleaned at different temperatures
761
S
0
U
0
1000
500
1500
Temperature (C) Figure 4: Free Energy vs Temperature for standard HF etching reaction of temperature which, as shown in the figure, was varied for two of the samples. While the direction of the change of the interracial oxygen (Figure 3(a)) and carbon (Figure 3(b)) is the same, a clear trend is not observed, since the impurities increase in going from 3250C to 5750C and then decrease on increasing the temperature to 725°C. It should be noted though, that smooth specular epitaxy was observed on all these samples. While more data points are necessary before attempting an explanation, these initial results underscore some of'the directions that future work must take. For instance, the chemical reaction effecting the clean needs to be established precisely, because Figure 3 can be explained by one reaction moving into different regimes or by different reactions. The most commonly accepted reaction for HF etching is: 4HF + SiO 2 -+ 2H 2 0 + SiF 4 The variation of the driving force of this reaction with temperature is of interest. The plot of free energy vs temperature for this reaction is shown in Figure 4. The free energy curve indicates that thermodynamically, this reaction should be less favored as the temperature rises, which is not entirely consistent with what is observed in Figure 3. The discrepancy could be due to kinetics alone or due to the occurrence of a different reaction. In summary, while further work is needed to establish the precise mechanism of this cleaning technique, its effectiveness has been clearly shown in the epitaxial growth results presented. 762
CONCLUSIONS A new gas-phase technique has been removal of native oxide using AHF. It has therefore suitable for possible adaptation ment. Its efficacy has been demonstrated growth of silicon.
demonstrated for low-temperature, in situ been shown to be selective and simple, and to a semiconductor manufacturing environby physical analysis as well as the epitaxial
ACKNOWLEDGEMENTS This work was supported by the T.I./M.M.S.T. program and S.R.C. We would like to thank Cecil Davis of T. I. for his encouragement.
REFERENCES [1] G. Ghidini and F. W. Smith. J. Electrochem. Soc.:Solid-State Science and Technology, 131, 2924, 1984. [2] F. W. Smith and C. Ghidini. J. Electrochem. Soc.:Solid-State Science and Technology, 129, 1300, 1982. [3] G. Mende, J. Finster, D. Flamm, and D. Schulze. Surface Science, 128, 169, 1983. [4] P. A. M. van der Heide, M. J. Baan Hofman, and J. J. Ronde. Technol., A7, 1719, 1989. [5] D. Graf, M. Grundner, R. Schulz, and L. Muhlhoff. 5155, 1990.
J. Vac. Sci.
J. Apple. Phys., 68(10),
[6] M. Morita, T. Ohmi, E. Hasegawa, M. Kawakami, and K. Suma. Appl. Phys. Lett., 55(6), 562, 1989. [7] B. S. Meyerson, E. Ganin, D. A. Smith, and T. N. Nguyen. J. Electrochem. Soc.: Solid-State Science and Technology, 133(6), 1232, 1986. [8] W. R. Burger and R. Reif. J. Apple. Phys., 62(10), 4255, 1987. [9] I. Nagai, T. Takahagi, A. Ishitani, H. Kuroda, and M. Yoshikawa. J. Apple. Phys., 64(10), 5183, 1988. [10] A. Ishitani, Y. Ohshita, K. Tanigaki, K. Takada, and S. Itoh. J. Apple. Phys., 61(6), 2224, 1987. [11] M. M. Moslehi and C. Davis. J. Mat. Res., 5(6), 1159, 1990. 763
[12] Y. Takahasi, H. Ishii, and K. Fujinaga. Apple. Phys. Lett., 57(6), 599, 1990. [13] G. P. Burns. Apple. Phys, Lett., 53(15), 1423, 1988. [14] C. R. Cleavelin and Gary T. Duranko. Semiconductor International, page 95, November 1987. [15] Daniel J. Syverson and Gary T. Duranko. October 1988.
Solid State Technology, page 101,
[16] N. Miki, H. Kikuyama, I. Kawanabe, M. Miyashita, and T. Ohmi. IEEE Trans. Electron Devices, 37, 107, 1990. [17] C. R. Helms, B. E. Deal, and M. A. McNeilly. to be published in Proceedings Institute of Environmental Sciences, 1991.
764
LOW TEMPERATURE OXIDATION OF SILICON IN AN ELECTRON CYCLOTRON RESONANCE PLASMA D. A. Carl* and D. W. Hess Department of Chemical Engineering and M. A. Lieberman Department of Electrical Engineering and Computer Sciences University of California Berkeley, California 94720 Silicon dioxide was grown on single crystal silicon substrates immersed in low pressure electron cyclotron resonance (ECR) oxygencontaining discharges. Physicochemical and electrical properties of the films grown were correlated to plasma parameters, silicon substrate temperature, applied wafer dc bias, and post-processing metallization treatments. Although silicon oxide films could be grown at rates comparable to thermal (> 900 'C) oxides at temperatures below 500 °C under floating, cathodic, and anodic bias conditions, the ECR oxides with the best thickness uniformity and the best physical and electrical characteristics were grown with anodic (substrate holder positive) conditions. Physical and chemical properties of the anodic oxides were equivalent to those of thermal oxides. When polysilicon was used as the gate material, anodic oxides displayed analogous fixed charge and intrinsic breakdown levels to those of thermal oxides, although low field leakage was apparent in the ECR oxides. INTRODUCTION In order to enhance the low thermal oxidation rate of silicon at temperatures below 900 'C, various plasma techniques have been invoked. Silicon has been oxidized in microwave plasmas (- 15 Pa) with and without an applied bias [1-3], in inductively coupled (- 5 Pa) rf plasmas [4, 5], and in downstream afterglows of high pressure (- 130 Pa) microwave discharges [6, 7]. (The above references and approaches are not intended to be exhaustive; for further, more extensive information,
"Currentaddress:
IBM Corporation, General Technology Division, Burlington, VT 05452
765
the reader should consult available review articles [8-10). Although these methods offered improvements in oxidation rate, the rates in downstream configurations, where oxide damage was reduced relative to in-plasma techniques, were still low. Recently, electron cyclotron resonance (ECR) plasmas have been investigated as potential high ion flux, low ion energy discharge atmospheres wherein oxidation rates comparable to those obtained by thermal oxidation at temperatures > 900 'C can be achieved. Under floating (no external dc or rf bias) conditions in a 0.027 Pa oxygen ECR plasma, silicon oxide growth kinetics were studied as a function of temperature and magnetic field configuration [11-13]. Neither linear-parabolic nor power law kinetics accounted for the observed growth rates. 180 marker studies indicated that the reaction took place at the Si-SiO 2 interface, with a small amount of exchange of 0 with the SiO 2 during oxidant transport. Growth rates under these conditions were low (10 nm in 1 hour at 350 °C), and oxide etch rates in HF solutions were 1.1 to 1.5 times that of thermal oxides. Electrical properties were not reported. A distributed ECR (DECR) system has been used to anodize silicon under a variety of plasma contitions [14]. These systems operate at the same pressure and power levels as conventional ECR systems; however, due to the permanent magnets around the microwave cavity, ion energetics are different as a result of near-wafer magnetic field configurations. In this study, substrate temperature was not controlled; substrate temperature was estimated to be 197 °C. Oxidation rate was a function of wafer position with respect to the plasma stream, roughly tracking ion density or the estimated wafer temperature. Electrical properties of the as-grown oxides were not reported. After gate metallization anneal, the MOS structures had2 2 fixed oxide charge levels of 5 x 1011 cm and interface trap densities of 5 x 101 cmeV'. Mobile ionic charge in these oxides was - 7 x 10'° cm-2, and the mean breakdown field (MBDF) was 7.8 MV cmn'. Etch rates in aqueous HF solutions were not reported. In the present study we describe our investigations of the relationship between ECR plasma parameters, oxidation conditions, and resulting chemical and electrical properties of SiO 2 films. In all cases, we compare these properties to those of thermal oxides grown in dry oxygen at 900 °C. EXPERIMENTAL CONSIDERATIONS The ECR system used in this investigation is shown schematically in Fig. 1. In this configuration [15, 16], a 2.45 GHz CW microwave power supply/matching network was connected by a WR284 rectangular waveguide through a quartz window to the 7.8 cm diameter by 22 cm long stainless steel cylindrical vacuum chamber. No special microwave mode conversion was used. Two electromagnets driven in a
766
mirror configuration established the axial magnetic field required for cyclotron resonance. Single crystal (p-type and n-type 10-15 0 -cm, (100)) silicon wafers 75 mm in diameter were clamped onto an aluminum holder via a retention ring, with the holder 14 cm from the source chamber. The substrate holder contained resistive heating elements, a thermocouple for temperature measurement, and could be electrically floated or dc biased. A 3.2 mm thick quartz plate covered the metal portions of the sample holder and had a 50 mm diameter opening to the discharge centered 7 mm above the wafer. This approach assured that all net dc current flowed through the center 50 mm of the 75 mm wafers. The oxygen plasma was characterized by optical emission, actinometry (with the Ar 750.4 nm emission line as a reference), and Langmuir probes. Prior to oxidation, wafer were cleaned in a boiling sulfuric acid/hydrogen peroxide solution, rinsed in DI water, immersed in buffered oxide etch until hydrophobic, then rinsed in 16 M Q0-cm DI water. Oxidation was performed by first evacuating the ECR system to - 1 x 1 0 4 Pa and the silicon wafer was then heated to the desired temperature. When the desired flow rate and pressure of oxygen were established, microwave power was applied. Oxidations were carried out at pressures between 0.033 and 1.3 Pa and at temperatures between 250 and 450 'C. Oxide film thicknesses were measured by ellipsometry. MOS capacitor structures used either thermally evaporated aluminum or deposited n+ polysilicon as the gate electrode. Polysilicon was deposited from silane and phosphine at 50 Pa and 650 'C, and activated at 850 'C in dry nitrogen for 20 min. Capacitance-voltage (CV) at 1 MHz and current-voltage data were obtained prior to and after a 400 'C forming gas sinter for 30 min. Bias-temperature stress measurements were performed at + /-1 V and 200 'C for 5 min. RESULTS AND DISCUSSION Oxidation Results Figure 2 displays silicon oxide thickness versus time for various microwave powers and substrate temperatures under floating (zero applied) bias conditions. Also shown in Fig. 2 are the oxidation rate data for a dry oxygen thermal oxidation performed at 1 atmosphere pressure and 1000 *C. Clearly, when the power level is at least 400 W, ECR oxidation rates are equivalent to thermal oxidation rates performed at temperatures significantly higher. Furthermore, at 700 W, the ECR oxidation rate is independent of substrate temperature (apparent activation energy - 0). Although no difference in rates for n- or p-type Si was observed, (111) orientations showed approximately a 10% increase in rate over that of (100). This difference is above the standard deviation of our oxidation runs -.3%); at present, we can offer no explanation for this observation. The ECR rate data can be fit to both the Deal-Grove (DG) linear-parabolic [17] or the Wolters-Zegers-van 767
Duynhoven (WZD) ion space-charge limited [18] growth models. The resulting constants in these two rate expressions are given in Tables I and II [16]. The apparent activation energies for both the linear and parabolic rate coefficients fall between 0.06 and 0.1 eV. As the ion density increased with increasing power (from 2 x 1011 cm-3 at 300 W to 5 x 10l cm"3 at 700 W), the apparent activation energy decreased to zero. In addition, oxygen ion and oxygen atom emission intensities increased with microwave power. Oxygen ion emission intensity tracked the ion density as measured by Langmuir probe studies [16]. Oxidation rates are obviously controlled by different mechanisms than those ascribed to thermal oxidation processes. Under floating conditions, the oxidation rate was independent of temperature over the range of 250 to 400 'C up to - 80 min. of oxidation (which corresponds to - 30 nm of silicon dioxide). For these oxides, a parabolic rate law described the rate data, although an initial accelerated oxidation rate, which resulted in the virtual instantaneous formation of - 3 nm of oxide) was observed. The ECR oxides had similar chemical and electrical properties to those of thermal oxides until a thickness of 30 nm was reached. Thicker oxides had buffered oxide etch (BOE) rates that ranged from 1.5 to 3.0 times that of thermal oxides grown at 900 *C. When a dc bias is applied to the wafer holder, the wafer surface behaves like a large planar Langmuir probe [8, 19], so that current is drawn through the wafer and the growing oxide film. The current-voltage characteristic depends on plasma conditions through electron density and electron temperature [8, 19]. In our configuration, the ion density 1 cm from the wafer holder is not affected by the dc bias applied between values of -45 and +5 V. In addition, the ion density in the ECR source region is unperturbed by the wafer bias over this potential range. We can thus assume that the wafer holder can be independently biased over this range with no resulting change in electron density, electron temperature, or ion energy in the ECR discharge. Under cathodic biasing conditions (substrate holder negative), positive ions in the growing oxide are attracted to the silicon and electrons are injected from the silicon into the oxide. Oxidation rates were similar to those observed under floating potential; again, a maximum thickness was observed, with no growth observed after this value. The termination thickness depended upon the bias applied (- 40 rnm for -20 V, and - 5 nm for 35 V). The observation of a maximum thickness is analogous to reports of thermal oxidation results under cathodic bias conditions [20]. Thus, positively charged oxygen ions cannot account for the silicon oxidation observed. The cathodic oxidation results might be explained by electron-active oxidation [21, 22]. However, the questionable reproducibility of our cathodic oxidations and the poor quality of the oxides (BOE rates comparable to those grown under floating
768
conditions, refractive index 1.43 or lower and breakdown fields - 3 MV/cm) established that this bias regime would not generate device quality oxide layers. The ECR oxides with the best thickness uniformity and the best physical and electrical characteristics were grown under anodic (substrate holder positive) bias. Anodizations were performed under constant current and constant voltage conditions; both types of anodization yielded identical oxide properties. Thus, only constant current anodization will be discussed here. In constant current anodization, a positive bias relative to the floating potential was applied to the holder and the voltage varied to maintain a specific negative current. Figure 3 shows oxide thickness versus time for a constant anodization current of -20 mA cm"2 at 350 'C, Power (forward) = 500 W, and two pressures [23]. For these constant current conditions, no change in growth rate occurred between 250 and 400 *C. At pressures between 0.13 and 1.3 Pa, three growth regimes were evident: an initial parabolic region (< 10 nm); a linear (ohmic) growth region extending from 10 nm to 100 nm (equivalent to oxidation times of - 8 - 30 min.); and a region (> 100 nm) with growth rates below that of the linear regime where space charge effects appear to dominate. A parabolic rate law was used to analyze the initial regime in Fig. 3. The parabolic rate constants were 0.0008 and 0.0011 u m2 /hr for 0.26 and 1.3 Pa, respectively; these values are slightly higher than those measured for floating bias operation. The larger rate coefficients may be due to a higher near-surface concentration of negatively charged atomic oxygen under positive bias conditions, which is consistent with an increased electron flux from the plasma. As observed under floating conditions, an induction period occurs at the start of the anodization, where the negative current can be maintained without altering the applied potential, although the oxide thickness is changing. Such behavior has been reported in other studies [3]. The thickness of the oxide layer during the induction period was - 4 nm at 0.26 Pa, and - 0.1 nm at 1.3 Pa. In the linear regime, the oxide grew at a constant rate, and the applied voltage had to be increased to maintain constant current. The linear rate coefficients were 0.11 and 0.095,u m/hr at 0.26 and 1.3 Pa, respectively. These values are similar to those reported for an inductively coupled rf plasma oxidation study performed under analogous current densities [4]. For film thicknesses above 100 nm, oxide growth rates were no longer linear with time. Indeed, it has been shown that space-charge in a growing oxide can result in non-linear growth kinetics during constant current anodization [3,9,24]. The applied voltage in this regime scaled with oxide thickness to the 1.3 power [23]. The high growth rates of anodic ECR oxidation relative to those of thermal 769
oxidation at equivalent temperatures are believed to be due to the transport of 0across the growing oxide film by field-aided diffusion. Since it is unlikely that 0generated in the discharge has sufficient energy to overcome the plasma sheath potential and reach the substrate, we propose that atomic oxygen in the plasma adsorbs onto the growing oxide surface where it forms 0- via electron attachment from the large electron flux from the discharge. Physical and chemical properties of as-grown, anodic oxides 60 nm or less in thickness were identical to those of thermal oxides grown at temperatures of 850 TC or higher [23]. For instance, the refractive index of ECR oxides was 1.467. Etch rates in BOE and infrared, Auger, and X-ray photoelectron spectra were indistinguishable from those of thermal oxides. For films above 60 nm, the ECR oxides displayed BOE rates between 1.1 and 1.25 times that of the thermal oxide rate. Such differences may be due to film stress or to overall film degradation from the cumulative effect of passage of electron current with time. Oxide Electrical Properties Aluminum gates were used to evaluate as-grown ECR oxides. All films studied were 20-30 nm thick. All as-grown oxides had significant fixed charge (> 1 x 101 cm-2) and high levels of interface traps (> 1 x 1012 cm-2 eV"1 ) as estimated by Terman's method) compared to the thermal oxide controls. Oxides grown at floating potential exhibited a hysteresis of 400 mV (polarization direction). This "damage" is likely due to UV and electron flux from the plasma. Breakdown fields were - 4.5, - 8.5, and - 11 MV cm"1 for floating, + 5 V (anodic) and thermal oxides, respectively [23]. When polysilicon was used as the gate metal, the effects of plasma-induced radiation damage were reduced substantially. Due to the anneal step following polysilicon deposition, the fixed charge dropped to that of a control (thermal) oxide (4.7 x 1010 era2). Although interface states were still present (- 1 x 1011 cm' eV-1), the density was equivalent to that of our thermal oxide. No mobile charges were detected in bias-temperature stress studies. Intrinsic breakdown fields also improved, and were generally 10-12 MV cm"1 ; however, slight low field leakage was observed in these cases, probably a result of the interface state density and/or residual damage in the oxide.
CONCLUSIONS An ECR oxygen plasma has been used to grow silicon oxides at temperatures below 500 °C with physical, chemical, and electrical properties similar to those of
770
thermal oxides grown at temperatures above 900 'C. ECR oxidation rates, which were equivalent to thermal oxidation rates at temperatures above 900 'C in dry oxygen, were controlled by plasma flux conditions under substrate floating, positive (anodic), or negative (cathodic) bias configurations. Analysis of the growth kinetics during constant current anodization demonstrated that three distinct oxidation regions exist: initial parabolic growth; linear growth; and space-charge limited growth. The highest quality oxides obtained were grown under anodic conditions. ACKNOWLEDGMENTS This work was supported by National Science Foundation Grants No. ECS8517363 and No. ENG-8710988, Department of Energy Grant No. DEFG0387ER13727, and a contract from IBM Corporation, General Technology Division, Burlington, VT. REFERENCES 1.
J. R. Ligenza, J. Apple. Phys., 36, 2703 (1965).
2.
J. Kraitchman, J. Apple. Phys., 8, 4323 (1967).
3.
S. Taylor, W. Eccleston, and K. J. Barlow, J. Appl. Phys., 64, 6515 (1988).
4.
D. L. Pulfrey and J. J. H. Reche, Solid State Electron., 17, 627 (1974).
5.
A. K. Ray and A. Reisman, J. Electrochem. Soc., 126, 2460 (1981).
6.
C. Vinckier, P. Coeckelberghs, G. Stevens, M. Heyns, and S. DeJaegere, J. Apple. Phys., 62, 1450 (1987).
7.
Y. Yasuda, S. Zaima, T. Kaida, and Y. Koide, J. Apple. Phys., 67, 2603 (1990).
8.
J. F. O'Hanlon, in Oxides and Oxide Films, Vol. 5, ed. by A. K. Vijh, Marcel Dekker, Inc., New York, 1977, p. 105.
9.
S. Gourrier and M. Bacal, Plasma Chem. Plasma Proc., 1, 217 (1981).
10.
A. Reisman, in Semiconductor Silicon 198 , ed. by H. R. Huff, T. Abe, and B. Kolbesen, The Electrochem. Soc. Inc. Pennington, 1986, p. 364.
11.
S. Kimura, E. Marakami, K. Miyake, T. Warabisako,, H Skunami, and T. Tokuyama, J. Electrochem. Soc., 132, 1460 (1985).
771
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S. Kimura, E. Marakami, M. Miyake, T. Warabisako, E. Mitani, and H. Sunami, J. Apple. Phys., 63, 4655 (1990).
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S. Kimura, E. Murakami, K. Miyake, T. Warabisako, and H. Sunami, J. Electrochem. Soc., 135, 2009 (1988).
14.
G. T. Salbert, D. K. Reinhard, and J. Asmussen, J. Vac. Sci. Technol., A8, 2819 (1990).
15.
D. A. Carl, D. W. Hess, and M. A. Lieberman, J. Apple. Phys., 68, 1859 (1990).
16.
D. A. Carl, D. W. Hess, and M. A, Lieberman, J. Vac. Sci. Technol., A8, 2924 (1990).
17.
B. E. Deal and A. S. Grove, J. Apple. Phys., 36, 3770 (1965).
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D. R. Wolters and A. T. A. Zegers-van Duynhoven, J. Apple. Phys., 65, 5126 and 5134 (1989).
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P. Friedel, S. Gourrier, and P. Dimitriou. J. Electrochem. Soc., 128, 1857 (1981).
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P. J. Jorgensen, J. Chem. Phys., 37, 874 (1962).
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E. A. Irene and E. A. Lewis, Appl. Phys., Lett., 51, 767 (1987).
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E. M. Young, Appl. Phys. A, L7, 259 (1988).
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D. A. Carl, Ph.D. Thesis, University of California, Berkeley, 1991.
24.
N. Cabrera and N. F. Mott, Rept. Prog. Phys., 12, 163 (1948).
772
Table I.
Pfo0 ard
Deal-Grove Model Constants for ECR Oxidation at 0.13 Pa and Thermal Oxidation Comparison.
Temperature
700 W
B(u m2/hr)
A(u m)
B/A(ji m/hr)
T (hr)
0.0126
0.060
0.2096
0.03
400 W
623 K
0.00209
0.0179
0.117
0.07
400 W
723 K
0.00454
0.0259
0.175
0.04
Thermal Ox.
1273 K
0.0117
0.165
Thermal Ox.
1373 K
Table II.
0.027
0.090
0.071 0.30
0.037 0.08
Wolters - Zegers-van Duynhoven Constants for ECR Oxidation at 0.13 Pa and Thermal Oxidation Comparison.
Pfoard
Temperature
700 W
a
a
coA/h.-
c(A/h o)
0.714
0.399
865
9215
400 W
623 K
0.664
0.515
381
623
400 W
723 K
0.659
0.505
563
9722
1073 K
0.670
0.490
60
297
Thermal Ox. Thermal Ox. Thermal Ox.
1223 K 1273 K
0.630 0.620
773
0.590 0.600
312 544
5673 15195
Temperature Conol Langmir Probw-
Magnets _ Gas
Fig. 1.
Schematic of at electron cyclotron resonance plasma oxidation system.
2000
1000
1273 K Th-.1l
5
400 W
623 K
0
200
I00
100
s0
0
The. (ie.t.) Fig. 2.
Oxide thickness versus time for various temperatures and microwave poe- levels.
0.26 Pa -20 mA cm -2
1.3 Pa -20 mA cmr-2 /
100
.1
Near,
;E
Space Charge
Parabolic
Linear , Space Charge
.• Parabolic ab
10 0.1
1
10
100
Fig.
3.
1
10
100
lime (min)
Time (min)
Oxide thickness vs. oxidation time for constant current anodization for two system pressures.
774
CHARACTERIZATION OF STRESS DISTRIBUTION IN SUBMICRON ISOLATION STRUCTURES BY MICRO-RAMAN SPECTROSCOPY AND CORRELATION WITH TRANSMISSION ELECTRON MICROSCOPY I. De Wolfl, J. Vanhellemont1, A. Romano-Rodriguez1, 2 , H. Norstrtam 13 and H.E. Maes1 llnteruniversity Micro-Electronics Center (IMEC), Kapeldreef 75, B-3001 Leuven, Belgium; 2 Cdtedra de Electr6nica, University of Barcelona, Diagonal 645, E-08028 Barcelona, Spain; 3 Swedish Institute of Micro-Electronics, P.O. Box 1084, S-16421 Kista, Sweden Local stress in LOCOS and LOPOS structures is studied by Micro Raman spectroscopy and the results are correlated with XTEM analysis. The stress in the silicon substrate under the center of the structures is found to be compressive and to increase with decreasing line width, except for lines widths smaller than 4 gim. Large tensile stresses are concentrated at the bird's beak edge and are found to be correlated with the shape and length of the bird's beak. LOCOS structures show in the center larger stress and at the bird's beak edge smaller stress than LOPOS samples. INTRODUCTION A well known problem in VLSI technology is the concentration of large stresses near the edges of surface films. These stresses may deform the band structure and change the transport properties, resulting in a degradation of the circuit performance. MicroRaman spectroscopy has proved to be a powerful technique to measure such local stresses [1]. Scattering areas with dimensions of the order of the laser wavelength can be probed. This spatial resolution is superior to most conventionally stress measuring techniques, such as X-ray analysis, where the probed areas have dimensions in the millimeter range. Isolation of active components of silicon Integrated Circuits is commonly performed by LOCal Oxidation of Silicon (LOCOS). A drawback of this approach is the lateral encroachment of the field oxide underneath the Si 3N 4 edge, giving rise to the so called bird's beak (BB). As a consequence the available active surface area is reduced and so is the packing density. To reduce the size of the bird's beak, modified LOCOS techniques were explored, e.g. the LOPOS (Local Oxidation of Polysilicon Over Silicon) technique. Micro-Raman spectroscopy was used to study local stress in these structures and the results were compared with XTEM (cross sectional transmission electron microscopy). EXPERIMENTAL PROCEDURES The samples were fabricated on (001) silicon substrates. Experiments were performed on two LOPOS structures (LOP2 and LOP3) and three LOCOS structures (S#7, S#10 and S#1 1). A pad oxide, thickness 10 nm, was grown by thermal oxidation. This was followed by deposition of 50 nm poly-amorphous silicon (LOP2 and LOP3) or SiON (S#10 and S#1 1). Next a Si 3 N4 film was deposited by LPCVD (thickness 150 nm 775
(LOP2, LOP3 and S#7) or 100 nm (S#10 and S#11) and patterned using photolithography, resulting in long Si 3 N4 lines with different widths. Finally a 600 nm thick field oxide was grown by wet oxidation at different temperatures (LOP2 and S#1 1: 1000 "C, LOP3: 1050 "C, S#7 and S#10: 950 "C). Raman spectra were measured in back scattering configuration using the 457.9 nm or 488.0 nm argon laser line with maximal output power of 30 mW. The incoming light was polarized along the length of the lines, the scattered light was not analysed. The diameter of the probed region was smaller than 1 gm. The sample was moved with an XY translation stage in steps of minimum 0.1 jim. In this way the Raman signal of the silicon was obtained at different positions under and near the Si 3 N 4 lines. The Raman lines were fitted with a Lorentzian function, reducing the error on the peak position to values smaller than 0.05 cmt1. Laser plasma lines were used for calibration. MICRO-RAMAN SPECTROSCOPY Mono crystalline silicon (c-Si) has three active optical vibrations. For strain-free c-Si, these vibrations have the same frequency, ,o, at about 520 cm-1. In the case of back scattering from a (001) surface only the LO phonon can be observed. Strain lowers the symmetry of the crystal so that the degeneracy of the optical phonons is partly lifted and they shift to frequencies different from (00 . The phonon frequencies of strained silicon can be calculated using perturbation theory [2,3]. From this theory it follows that the frequencies of the optical phonons in the presence of strain, co, are related to the eigenvalues, k., of the following secular matrix
S
2rexy 2re•
peyy+q(ezz+Exx) 2rezy
2
reyz pezz+q(exx+Eyy)
(1)
by X =
2 -_(362 i=1, 2, 3 from which follows oi = oo + X•j20)o -ijare the components of the strain tensor e, which is related to the stress tensor -Cby Hooke's law: e = S %t where S is the compliance tensor. For c-Si, S has only three 1 12 different components: SiI = 7.68 10- Pa , S12 = -2.14 10-" Pa-1 and S44 = 12.7 10-12 Pa-t. p,q and rare deformation potential constants [1] with for c-Si: p = -1.43 o2 q 1.89 coo2 and r = -0.59w0) 2 . The Raman polarizability tensors will also change under the influence of strain. They can be calculated by a linear combination of the zero-strain polarizability tensors, corresponding to the linear combination between old and new eigenvectors. As a result, it is possible that in the presence of strain or stress more than one of the three c-Si Raman active optical vibrations can be observed.
STRESS MODEL In order to relate the observed shift of the Raman signal with stress in the material one needs a model that describes the stress profile in the silicon substrate underneath the Si 3 N4 lines. Vanhellemont et al. [41 proposed a stress model which they successfully used 776
to describe film edge induced dislocation generation in LOCOS structures. For simplicity the problem was reduced to two dimensions by assuming an idealized film structure consisting of a film edge perpendicular to the image plane and deposited on a semi-infinite substrate. They assumed plane stress in the silicon with a film edge force lying in the image plane (Fig. 1). This force can be decomposed in two components: f=fex
and
k=afez
with x < 0 for bending up of the film, ex and ez are unit vectors along the X axis and Z axis, respectively.
Fig.l: Cross-sectional view of a LOCOS structure with forces acting on the substrate.
Assuming plane stress, only three stress components are present in the silicon substrate under the structure. For a single line they are given by: 2f it
rx(x÷+ az) (x2+
z2)2
2
(x _-w)2-_ _
(2)
(x -w -az)
(3
0'=2f z2( (x +az) 711
2f
X 2+ z2)2
((
)2 + z2)2
x(x + xz)
(x - w)(x - w -
2
z ((x - W)2 +22
(x2 +
.C1
((x-w)2+z2)2}
z)] (4)
where w indicates the distance between the two bird's beak ends. In most samples we studied, the lines are oriented along a [110] direction. This means that the above given equations are in the axes system X = [1101, Y = [1101, Z = [00i]. The secular matrix is given in the crystallographic axes system [1001,[010],[001]. So we had to calculate the strains in the latter system corresponding with the stresses axx, azz and Txz given in the coordinate system shown in Fig. I and solve the secular matrix for eigenvalues and eigenvectors. From the eigenvectors XI, X2 and X.3, the following dependence of the frequency shift AO( 1, Ao02 and A" ( AO)i = i - WOO) of the three Raman peaks on oxx, (Yz and xz was obtained: 777
Aow = -3.65 1010 oY,- 1.93 10-'90 Ao)2 = -2.12 10-9 x, - 1.34 10-9 02z2 + C A" = -2.12 10-9 xx - 1.34 10-9 oC. - C
4(4.02
zz)
10-7 arx + 1.22 10-6
~~~~2080
(5) + 1.64 1011 t3
"2+16
2
0"T
Using the eigenvectors of the secular equation, the polarizability tensors in the presence of these stresses were calculated. The result implies that both the Raman signal corresponding with peak 2 and the one corresponding with peak 3 can be observed, with an intensity depending on the position across the line. Peak 1 is not visible. RESULTS AND DISCUSSION Fig. 2a shows the peak frequency of the Raman signal that was measured during a scan across a 3 jim wide Si 3 N4 line (LOP2), starting from the center of the line (0 gim) =1 C.) -i
.'4.4
0.0
0.5
1.0 1.5 Position (jim)
2.0
b)
Fig. 2: a) Raman frequency of silicon measured at different positions across a 3 Wim LOPOS structure (LOP2). b) XTEM picture of a similar 3 Wi LOPOS sample. 778
across the edge of the nitride mask (at 1.5 urm, indicated by a dashed line) towards the field oxide. The 457.9 nm laser line was used for excitation in order to probe only the uppermost substrate area, where stresses are expected to be higher. The contribution of the poly-Si to the Raman signal was checked by analysing the polarization direction of the scattered light. It was found to be negligible. An XTEM micrograph of the corresponding LOPOS geometry is shown in Fig. 2b. A polysilicon top layer was deposited on the sample to improve the contrast of the picture. In between measurements on LOPOS or LOCOS structures, the peak frequency of stress-free c-Si was measured on a reference sample. From 9 measurements a value of 520.0 cm 1 was obtained. The frequency of the Raman signal at the center of the 3 gxm line shown in Fig. 2a is higher than this reference value: 520.7 cm t . This indicates the presence of compressive stress in the top layer of the silicon substrate at this position. When approaching the BB, the frequency decreases and reaches a minimum value of 519.3 cm 1 , indicating the presence of tensile stress. It is important to notice that this minimum is not located at the edge of the Si 3 N 4 line, but at the BB's end, under the Si 3 N4 film. The Raman frequency increases again towards the edge of the nitride film and reaches the stress-free value underneath the field oxide. To study the influence of the Si 3 N4 line width on the Raman frequency, we repeated the measurement for line widths varying from 2 gin to 15 gm. The results are shown in Fig. 3. For broad lines (5 to 15 grm), the maximum shift is not reached at the center of the lines, but closer to the edge, indicating a relaxation of the compressive stress towards the center of the line, as predicted by the model. An accurate fit of the proposed model to the measurements was difficult because the theory predicts that peak 2 (at2) has a large intensity outside the
779
1.0
15
0,5 0.0 -0.5 10
0.5 0.0 0 -0.5
5
0.5 0.0 -0.5 1.0' 0.5 0.0 -0.5 1.0
3
0.5 0.0 -0.5 0.5 0.0 -0.5
-10
-5
0
5
10
Position (rtm) Fig. 3: Si Raman frequency shift from the value in the center under the field oxide line, at different positions LOPOS (LOP2) lines of varying width.
lines and is not visible in the center, while the reverse is true for peak 3 (o3). They both show a different dependence on stress. According to the model, both peaks should be visible at the edge of the BB. We never observed two different peaks in this area. The appearance of a significant increase of the width of the Raman signal at half maximum (FWHM) in this area could be due to the presence of two Raman peaks which are not resolved by the Raman instrument. However, a more probable explanation is that this effect is caused by the large variation of the stress within the laser beam diameter and within the probed depth. The former corresponds with the large variation of the Raman frequency in this area. To obtain information on the magnitude of these local stresses, we studied the Raman shift in the center of the lines (Acocenter) and the most negative shift (AComin) in the vicinity of the BB's edge. Both were calculated relative to the Raman shift measured in between the lines. Fig. 4 shows the mean values of A~min and Ac.enter obtained for
different line widths. Acocenter increases with decreasing line width, up to 4 Aim, but decreases for smaller lines. A0min is found to be independent of line width within the experimental error. According to the stress model, rxz is zero and azz is negligible compared to ox, at the center of the line for broad lines (> 4 Aim). ca, (Pa) is then linearly related to the Raman frequency shift: Ao = 2-L pS 12 + q(SlI + S12 )] Ox,
-1.93 10-9 o.x
(6)
Using this equation, OYx was calculated from AcOcenter. The values varied from about -0.09 GPa in the center of 15 jim lines to -0.4 GPa in the center of 4 Aim lines. Furthermore, at the center of these broad lines x = w/2 >> z so that oxx is mainly determined by the value of f and relatively independent of (x and z. Using the value of Oxx and Eq. 2, f was found to be about f = 500 N/in. This value corresponds well with f = 800 N/m estimated from computer simulations of the pile up configuration of 60" dislocations in similar structures [5]. For smaller lines -rxz and czz cannot be neglected and Eq.6 is no longer valid. We attribute the decrease of the Raman shift in the center of these lines to a combination of two effects: an increasing influence of the tensile stress at
S0.8
-0.4
S0.6
-0.3
0.4
-0.2 • -0.1
5
10
15
Line width (grm) 780
Fig. 4: Difference between the Raman frequency in the center of LOP2 lines (Amcenter,-) or most negative Raman frequency (ACOmin, -o-) around the BB's edge of the LOP2 lines and the "Raman frequency under the field oxide, as a function of widths of the Si 3 N4 lines. The right Y-axis denotes the stress at the center of the lines. These values are only valid for broad lines (15 to 4 im).
the BB's edge and the presence of a vertical force in the center of the lines due to the bending up of the Si 3 N 4 film, which increases with decreasing line width. For very narrow lines this vertical force becomes so large that it can cause breaking of the pad oxide and/or the nitride film, as was observed by XTEM [6]. According to the theoretical model, Awmin is strongly dependent of f, a and z but almost independent of the line width, w. We indeed found no significant dependence of Acomin on w (Fig. 4). So, while the stress in the silicon substrate underneath the center of the lines is highly influenced by the width w, the stress at the BB's edge does not change. TEM experiments showed that the shape and length of the BB in these LOPOS samples is independent of the width of the lines. This suggests that the stress at the BB's edge is mainly determined by the shape and length of the BB. The separation between the Si 3 N4 lines in all samples was equal to the width of the lines. Fig. 5 shows the difference between the silicon Raman shift measured in the center of the field oxide region in between the Si 3N4 lines of LOP2 and the stress free Si Raman frequency as a function of the spacing of the lines. Reduction of the line spacing results in an larger negative shift up to widths of 4 Am. For smaller lines the shift decreases. This behaviour is a mirror image of the dependence of the compressive stress at the center of the lines on line width, only the scale is much smaller. Assuming also here uniaxial stress for broad lines, the value of a,, is found to vary from about 0.017 GPa in the center between two 15 Am lines (spacing 15 jim) to 0.064 GPa between 4 Jim lines (spacing 4 Am). These tensile stresses are about a factor 10 smaller than the compressive stresses under the Si 3 N4 film. Tensile stress in the substrate underneath the field oxide is expected from the difference in thermal expansion coefficients of c-Si and SiO 2 [7]. A similar result was reported by Brunner et al. [8]. ,-,
;
0.05
-0.025
00
omo
-0.05
ýI >
Raman shift of stress
0.025
. 10
0.050 0.075
15 10 5 Line spacing (QiLm)
Fig. 5: Difference between Raman shift at the center of the field oxide region and the
'
freec-Si(520.0Rcm-) as a function of line spacing. The right Yaxis denotes the stress. These values are only valid for broad lines (15 to 4 Am).
The penetration depth of light increases with increasing wavelength. The Raman signal obtained with 457.9 nm arises from an integrated depth of about 0.3 Am. Light with wavelength 488.0 nm will give information about an integrated depth of about 0.6 pm. According to the theoretical model, the stress in the silicon substrate decreases with depth, and the dependence of stress and Raman frequency shift on depth (z) is larger at the BB's edge than in the center of the lines. Fig.6 shows the dependence of the Raman 781
frequency on the position across a 5 gtm LOPOS line (LOP2), measured with 457.9 nm and 488.0 nm excitation light wavelength. At 457.9 nm, Aommin and Aocentr are clearly larger than the shifts measured with 488.0 nm. Also, as predicted by the model, the influence of excitation light wavelength on Raman shift is larger at the BB than in the center of the line.
520.5 U
520.0 519.5 519.0 I
II
20
40 60 Position
80 100 (pgm/10)
I
120
Fig. 6: Influence of laser light wavelength used for Raman excitation on the Raman shift observed during a scan across a 5 gim LOPOS structure (LOP2). -o-: 488.0 nm; -- : 457.9 nm
520.6 520.4 520.2 520.0 519.8 80
100 120 140 160 Position (pgm/10)
180
Fig. 7: Raman frequency shift measured during a scan across a 5 gtm line of a LOPOS (LOP2) and a LOCOS (S#7) sample. The excitation wavelength is 488.0 nm. -o- : LOCOS; -- : LOPOS Fig. 7 compares the Raman shift observed during a scan across a conventional LOCOS (S#7) structure with a scan across a LOPOS (LOP2) structure. The width of the 782
scanned lines is 5 gtm. The measurements were performed with laser wavelength of 488 rnm. At the field oxide region, the Raman shift observed in both samples is about 520 cm1, corresponding with the Raman frequency of stress free c-Si. The negative deviation from the stress free value at the BB's edge, at about 0.5 gtm from the edge of the layer (indicated by vertical lines) is larger in the LOPOS structure than in the LOCOS structure, indicating smaller stresses near the LOCOS BB's end. This confirms the hypothesis that the large negative deviation of the Raman frequency at the BB's edge from the unstressed value is correlated with BB's length and shape. At the center of the lines, the Raman frequency is higher than 520 RcmI for both LOPOS and LOCOS structures. Assuming uniaxial stress in the silicon substrate at this position, the following stress values are obtained (Eq. 6): cxx,(LOPOS) = 0.29 GPa < rxx(LOCOS) 0.31 GPa. The only difference between both samples is the presence of a poly-Si layer (500 A) in the LOPOS structure. Poly-Si and single c-Si have about the same thermal expansion coefficient. However, poly-Si exhibits an intrinsic compressive stress of about -0.2 GPa [7]. This stress partly compensates for the tensile stress in the Si 3 N4 layer, resulting in a smaller compressive stress in the underlaying silicon substrate compared to the LOCOS sample. Fig. 8 shows the result of Raman measurements performed on LOPOS (LOP2) and modified LOCOS (S#10 and S#11) samples with wavelength 457.9 nm. Again the deviation from the stress free frequency at the BB is smaller in the LOCOS samples than in the LOPOS samples. This difference can be correlated with the length and shape of the BB: XTEM experiments showed that the BB is longer and less steep in the modified LOCOS sample than in the LOPOS sample. In the center of the lines, both structures show approximately the same positive Raman shift from the control value, indicating compressive stresses of equal magnitude in the substrate. This indicates that poly-Si is a better stress buffer than SiON.
44)
Fig. 8: Raman frequency dependence on position across 5 gm lines. The lines are indicated by the shaded area. LOPOS: LOP2; LOCOS [110]: S#10; LOCOS [1001: S#l 1, LOCOS [100] no Si 3N 4 : S# 1I after removal the the Si 3N 4 film. In the same figure, an experiment on a LOCOS structure with lines oriented in the [1001 direction (S#l I) is shown. We did not observe a significant influence of line orientation on Raman shift. Sample S# 1I was also studied after removal of the Si 3 N4 film by etching techniques. This resulted in a decrease of the Raman shift in the center of the 783
lines, indicating a reduction of the compressive stress in the substrate upon removal of the Si 3 N4 layer. The negative shift from the stress free value is not located at the BB, but is shifted outside the borders of the lines. Similar experiments were reported by Kobayashi et al. [9]. They also observed an increase of A(Ocenter with decreasing line width, but, in contrast with the results we obtained when the Si 3 N4 film was present, up to very small active area sizes (1.2 grn). The difference in Raman shift dependence on line width in samples with and without a Si 3 N4 layer can be understood by the presence or absence of the upward vertical force acting on the silicon surface below the center of the nitride line. The present results show that micro-Raman spectroscopy can give detailed quantitative information about local stresses in LOCOS/LOPOS structures. Despite the fact that a complete fit of a simple planar stress model to the Raman data was not possible, important information could be extracted. Further progress can be expected by refinement of the model by e.g. taking into account the presence of an additional upward vertical force or force distribution at the center of the lines or by use of finite element calculations. ACKNOWLEDGMENTS The authors thank Ph. J. Roussel for stimulating discussions on data handling and modelling. The Raman scattering experiments were performed on the equipment of the K.U.Leuven (MTM department). The authors acknowledge the Belgian Fund for Scientific Research (NFWO), the Spanish Ministry of Science and Education and the Swedish Board of Technical Development REFERENCES [1] [2] [3] [4] [5] [6]
[7] [8] [9]
E. Anastassakis, in 1985 PhysicalProblems in Microelectronics,J. Kassabov ed., Proc. of the 4th Int. School ISPPME, Varna, Bulgaria, 128 (1985) E. Anastassakis and E. Burstein. 1. Phys. Chem. Solids 32, 563 (1971) S. Ganesan, A.A. Maradudin, J. Oitmaa, J. Ann. Phys. (N.Y.) 56, 556 (1970) J. Vanhellemont, S. Amelinckx and C. Claeys, J. Appl. Phys. 61, 2170 (1987) J. Vanhellemont, C. Claeys, J. Van Landuyt and S. Amelinckx, In 1985 ProceedingsGADEST, H. Richter ed., 255 (1985) A. Romano-Rodrfguez, J. Vanhellemont, I. De Wolf, H. Norstr6m and H.E. Maes, to be published in 1991 Proceedingsof the "Vllth Oxford Conference on Electron Microscopy of Semiconducting Materials",Oxford (U.K.), March 25-28 (1991) S.M. Hu, in Proc. of the 2th Intern. Symp. on ProcessPhysics and Modeling in SemiconductorTechnology, The Electroch. Soc., 91-4 (1991) K. Brunner, G. Abstreiter, B.O. Kolbesen and H.W. Meul, In 1989 Proceedings INFOS, F. Koch and A. Spitzen ed., 116 (1989) K. Kobayashi, Y. Inoue, T. Nishimura, H. Arima, M. Hirayama and T. Matsukawa, Ext. Abstracts of the 19th Conf. on Solid State Devices and Materials, Tokyo, C-8-5, 323 (1987) 784
A MANUFACTURABLE IN-SITU DOPED POLYSILICON PROCESS FOR 16-64K BIT DRAM TECHNOLOGY Dane E. Bailey MOS Memory Products Texas Instruments Incorporated P.O. Box 655012, M/S 374 Dallas, Texas 75265 An in-situ doped polysilicon process using phosphine (PH3) and silane (SiH4) is described which meets the requirements for ULSI manufacturing technology. Utilizing experimental design, a process optimizing uniformity and load size was developed for a fully automated 150 mm vertical LPCVD reactor. Optimized conditions produce films which have thickness and resistivity variations of < 1.2% and < 2.0%, respectively, for a 75 wafer load size. Additionally, film conformality is > 95% and defect density is < 0.17 /cm 2 for defects > 0.3 microns. INTRODUCTION As DRAM technology moves into the 16-64M bit density regime, processing requirements become more demanding, especially for high aspect ratio trench technology utilizing up to three different polysilicon levels [1]. To achieve the low temperature processing and homogeneous doping requirements for such technology, in-situ doped polysilicon is the preferred technique. However, current in-situ doped polysilicon processes used in the industry require either special designed LPCVD reactors or caged boats [2,3,41 which preclude the use of advanced automation thereby producing unacceptable defect densities or vapor dopant sources [5] which add unwanted impurities such as Carbon. EXPERIMENTAL In-situ doped silicon films were deposited in a fully automated vertical LPCVD reactor, shown schematically in Fig. 1, using silane and phosphine-silane gas mixtures. Wafers were loaded into a single quartz boat with a capacity of eighty 150 mm wafers spaced 7.11 mm apart. Prior to film deposition, 80-100 nm of silicon dioxide was thermally grown on the wafers.
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Polysilicon film thickness measurements were made with a Nanospec using a refractive index of 2.8 after being annealed at 1000 C for 30 seconds in a Heatpulse RTA. Sheet resistance measurements were made with a Prometrix Omni Map. Defect densities were measured on as-deposited films using a WIS8500, which is capable of 0.2 micron minimum resolution on unpatterned films. RESULTS Experimental design was employed to optimize the effects of gas flow, pressure, and PH3/SiH4 ratio with regard to both thickness uniformity and resistivity uniformity across a 75 wafer load. For this investigation, gas flow, pressure and PH3/SiH4 ratio were varied between 100-300 sccm, 300-600 mTorr, and 0.0008-0.002, respectively, while temperature was held constant at 560 C. As shown in Fig. 2, thickness and resistivity variation is inversely proportional to total gas flow, while resistivity variation is proportional to pressure and PH3/SiH4 ratio. The effects of pressure and PH3/SiH4 ratio on thickness variation were negligible as determined by statistical analysis.
786
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Figure 2. Main effects of experimental design for in-situ doped polysilicon. A) Thickness and resistivity variation vs. B) Resistivity variation vs. phosphine silane flow. concentration. C) Resistivity variation vs. pressure. The resulting optimized process, as predicted by experimental design, has a one sigma variation in both film thickness and resistivity of 1.15% and 1.9%, respectively, A slight with a deposition rate of 22.2 angstroms/min. of +2 C on the top zone and -4 C on the temperature tilt bottom zone aided in the uniformity. The results are shown graphically in Fig. 3. 30 0.0
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TtAFER POSITION
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Figure 3. Thickness and resistivity results across 75 wafer Deposition load using predictions from experimental design. conditions are Temp = 560 C, Pressure = 300 mTorr, PH3/SiH4 = 0.0008, Top Flow = 300 sccm, Bottom Flow = 235 scciu. 787
In comparison with data reported by Meyerson et al. [6], it is obvious that deposition rate and uniformity are significantly improved as the PH3 content is decreased. Together with a reduction in deposition temperature, it is possible to achieve low resistivity, highly uniform films with acceptable deposition rates. Furthermore, the optimized process combined with the advanced wafer automation capabilities of a vertical LPCVD reactor, is capable of2 producing films with defect levels less than 0.17 defects/cm for defect sizes greater than or equal to 0.3 microns as shown in Fig. 4.
90
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CUMULATIVE THICKNESS (kA)
Figure 4. As-deposited particle levels for 3000 A in-situ doped polysilicon films. In separate experiments, temperature was varied from 550600 C while all other parameters were kept the same as those listed in Fig. 3. An Arrhenius plot of different in-situ doped polysilicon films is shown in Fig. 5. The activation energy, as calculated from Fig. 5 is 1.5 eV compared with 1.5 eV for TBP doped silicon [5] and 2.0 eV for high PH3/SiH4 concentrations as reported by Learn et al. [2] From TEM analysis of as-deposited films, the amorphous-polysilicon transition temperature for this experiment was determined to be 550 C as shown in Fig. 6. Additionally, the grain size for films deposited at 560 C, 570 C, and 600 C are 3000 A, 2000 A, and 300 A, respectively. Finally, as shown in Fig. 7, the resistivity of such films is proportional to the deposition temperature. 788
100
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INVERSE TEMPERATURE (1000/K) --
A
-B
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Deposition rate vs. temperature for various Figure 5. A) 0.0008 PH3/SiH4 (this report) E = 1.5 polysilicon films. C) 0.01 PH3/SiH4 (Learn et B) TBP (T.Tang) E = 1.5 eV. eV. al.)
E = 2.0 eV.
B)
A)
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Figure 6. SEM micrographs showing as-deposited grain size for B) A) 550 C - amorphous. various deposition temperatures. 560 C
- 3000 A.
C)
570 C -
2000 A.
D) 600 C -
300 A.
Data showing trends for poly grain size and film resistivity as a function of deposition temperature are consistent with data reported earlier [2]. 789
1.5
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540
650
560
570
580
690
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Figure 7. Resistivity vs. deposition temperature. All other deposition conditions are the same as those listed in Fig. 3. Conformal in-situ doped polysilicon films were deposited under the optimized conditions listed in Fig. 3 on wafers patterned and etched with deep trenches. Unlike previous reports using phosphine doped polysilicon for deep trench refill [71, no voids, defects, or seams were formed using the process described herein as confirmed by SEM analysis and by plasma assisted etch back of in-situ doped polysilicon refilled trench wafers. From SEM measurements as shown in Fig. 8, the step coverage is greater than 95% for optimized films. This again is in contrast to earlier findings where conformality was reported to be 60-80% [8].
790
I
-0.
0.5um
SEM micrograph showing > 95% step coverage of Figure 8. Trench size is 0.6 x 1.2 microns. 0.0008 PH3/SiH4 films. SUMMARY High aspect ratio trench technology requires that films not only be uniform and defect free, but also highly conformal This paper describes an in-situ doped polysilicon as well. is capable of attaining thickness and process which resistivity variations of 1.15% and 1.9%, respectively, over Also, due to being developed in a highly 75 wafer loads. automated vertical LPCVD reactor, this process achieves less than 0.17 defects/cm' for defects greater than or equal to 0.3 Furthermore, due to the low deposition temperature microns. and the low dopant concentration used, films are of sufficient conformality and resistivity to meet ULSI requirements.
791
ACKNOWLEDGEMENTS The author would like to thank R. Tyler for help in conducting the experiments and H. L. Tsai of the Material Science Laboratory for TEM analysis. REFERENCES [I] [2] [3] [4] [5] [6] [7] [8]
B. W. Shen, G. Chung, I. C. Chen, D. J. Coleman, P. S. Ying, R. McKee, M. Yashiro, C. W. Teng, IEDM Tech. Dig., 27 (1989). A. J. Learn and D. W. Foster, J. Appl. Phys. 61, 1898 (1987). L. D. Madsen and L. Weaver, J. Electrochem. Soc. 137, 2246 (1990). J. G. M. Mulder, P. Eppenga, M. Hendrix, J. E. Tong, J. Electrochem. Soc. 137, 273 (1990). T. Tang, IEDM Tech. Dig., 39 (1989). B. S. Meyerson and W. Olbricht, J. Electrochem. Soc. 131, 2361 (1984). K. Sawada, Symposium on VSLI Technology, 41 (1989). T. Morie and J. Murota, Jpn. J. Apple. Phys. 23, No. 7, L482 (1984).
792
DIFFUSION BEHAVIOUR OF DOPANTS IN POLYCRYSTALLINE SILICON ELECTRODE FOR ULTRA HIGH SPEED BIPOLAR DEVICES Hizuru Yamaguchi and Nobuo Owada Device Development Center, Hitachi Ltd., 2326 Imai, Ome, Tokyo 198, Japan
Dopant diffusion from poly-Si into Si-substrate can be suppressed under certain process conditions even by increasing heat treatment, because the strain field around grain boundaries stabilizes them in poly-Si to some extent. This suppression is released by increasing doping level more than stably stored level, or by releasing the strain field by poly-Si grain growth. This very unique dopant behaviour makes it possible to form very shallow junctions with poly-Si electrode insensitive to heat treatment. INTRODUCTION Recently, polycrystalline silicon(poly-Si) film is very widely used as a diffusion source and electrode for very shallow junction formation in the scaled MOS devices and in the advanced selfaligned bipolar devices, in which dopants in poly-Si film have been believed to diffuse very fast through the film down into single silicon substrate(Si-substrate) in any case. But, in the development of selfaligned bipolar devices with emitter and base poly-Si electrode, we have found out that the dopants in poly-Si film do not always diffuse into the substrate with the increase in heat treatment, and that the dopant diffusion into the substrate is saturated at the initial stage of drive-in annealing under certain process conditions. This paper reports the detailed study of this very unique diffusion phenomenon of dopants in this poly-Si/Si-substrate structure, observed in very shallow emitter/base junction formation process for an advanced self-aligned bipolar transistor.
EXPERIMENTS Fig. 1 shows the cross-sectional view of an advanced self-aligned bipolar transistor, in which emitter and active base is formed by arsenic and boron diffusion from poly-Si into Si-substrate respectively, and graft base is formed by diffusion of boron implanted
793
in the surface region of Si-substrate both into the substrate and into the poly-Si film deposited on it. This study focuses on diffusion behaviour of dopants in poly-Si/Si-substrate structure, simulating very shallow emitter/base junction formation in this self-aligned bipolar transistor. Poly-Si film is deposited on Si-substrate by thermal decomposition of SiH 4 at 643 0 C. just after removing native oxide with buffered HF. In simulating emitter formation, poly-Si film deposited on Si-substrate is implanted with arsenic at 80keV to the dose of 2X10 16 /cm 2 followed by drive-in annealing around 9000 C. In simulating active base formation, poly-Si film deposited on Sisubstrate is implanted with boron at 30keV to the dose of 2X10 14 /cm 2 followed by two drive-in annealing steps. In simulating graft base formation in Fig. 1, Si-substrate is implanted with boron at 10keV to the dose of 1X10 1 5/cm 2 followed by poly-Si deposition and drive-in annealing at 9500 C. Cross-sectional TEM is used in order to evaluate the crystalline structure of the poly-Si film, and dopant distribution in poly-Si/Si-substrate structure is measured by SIMS using a CAMECA 3f instrument.
base poly-Si
Fig.1
emitter oly-Si
Typical cross-sectional view of a self- aligned high speed bipolar transistor.
794
RESULTS AND DISCUSSIONS
Fig.2 summarizes the diffusion behaviour of arsenic from polySi into SI-substrate, simulating shallow emitter junction formation, under three annealing conditions listed in the figure. After the annealing at 85090 for 20 minutes, arsenic diffusion layer is already formed in Si-substrate, indicating that the arsenic diffuses very fast through the poly-Si film down into the substrate. On the other hand, the diffusion profile of arsenic in poly-Si/Si-substrate changes very little even by increasing the annealing temperature from 8500C to 900'C and the annealing time from 20 minutes to 40 minutes, indicating that the diffusion of arsenic from poly-Si into Si-substrate is saturated at the initial stage of drive-in annealing after dopant profile in poly-Si and in Si-substrate is balanced. Fig. 3 shows boron profiles diffusing from poly-Si into Sisubstrate under three annealing conditions listed in the figure, simulating active base formation. Even in this case, boron profile in poly-Si/Si-substrate structure does not change by increasing drive-in annealing from 90000 for 20 minutes up to 10000C for 40 minutes, indicating that the boron diffusion is also saturated after dopant profile in poly-Si and in Si-substrate is balanced. Fig.4 summarizes diffusion behaviour of boron, implanted in the surface region of Si-substrate, both into the poly-Si film deposited on it and into Si-substrate under three annealing conditions listed in the figure, simulating graft base formation. As is clearly shown in this figure, boron atoms implanted in the surface region of the substrate diffuse very fast up into the poly-Si film after 10 minutes annealing at 9500C. But, the diffusion of boron deep into the substrate does not advance even by increasing the annealing time from 10 minutes up to 60 minutes, indicating that the boron diffusion deep into the substrate is also saturated because of the existence of poly-Si film on it after dopant profile in poly-Si and in Si-substrate is balanced. Extensive studies have been done for the mechanism of the above mentioned dopant diffusion behaviour in poly-Si/Si-substrate structure. And It is deduced from these studies that the strain field in poly-Si film, caused by crystalline imperfection such as grain boundaries, stabilizes some amount of dopants and tends to store them in the poly-Si film, resulting in suppression of their diffusion into the substrate. So, in order to release this saturation of dopant diffusion, doping level should be increased more than the level stably stored in the poly-Si film, or strain field in poly-Si film should be released. Fig.5 and Fig.6 show the effects of increasing doping level, corresponding to Fig.3 and Fig.4 respectively. In Fig.3, the doping
795
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Depth( pm) Fig.4 Diffusion of boron implanted in the surface region of Si-substrate both into poly-Si and into Si-substrate. 2 (Implantation condition; B, 1OkeV, 1 El 5 atoms/cm )
797
level is increased from 2X10 14 /cm 2 to IX10 16 /cm 2 . and the boron diffusion into the substrate is advanced drastically under the same annealing condition. In Fig.6, the doping level implanted in the surface region of the substrate is increased from IX10 1 5 /cm 2 to lXl0 16 /cm 2 , and the boron diffusion into the substrate is also advanced drastically. The best way to release the strain field is to increase the grain size of poly-Si film, and we have confirmed that the arsenic diffusion from poly-Si into Si-substrate is advanced by raising the annealing temperature from 900FC up to 950 0 C together with the grain growth of poly-Si film. In this way, dopant diffusion in poly-Si/Si-substrate structure shows very unique behaviour that has never been observed in the conventional diffusion mechanism in single crystal silicon. And by making the best use of this saturation phenomenon of dopants, shallow junctions in advanced devices with poly-Si electrode can be made insensitive to heat treatment under very high repeatability. CONCLUSIONS Diffusion mechanism of dopants in poly-Si/Si-substrate structure is completely different from the well established diffusion mechnism in single silicon, and the saturation of dopant diffusion from poly-Si into Si-substrate occurs under certain process conditions. This saturation phenomenon is successfully explained by the mechanism that the strain field in poly-Si film caused by grain boundaries stabilizes some amount of dopants and stores them in the film. This very unique behaviour of dopants in this poly-Si/Sisubstrate structure makes it possible to form very shallow junctions with poly-Si electrode insensitive to heat treatment.
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Depth(p•m) of boron diffusion from poly-Si into Fig.6 Enhancement Si-substrate by increasing doping level corresponding to Fig.4. (Implantation condition; B, 1OkeV, 1 El 6 atoms/crr?) 799
A NEW POLYSILICON TEXTURIZATION TECHNIQUE USING EXCIMER LASER PROCESSING Viju K. Mathews and Chang Yu Micron Technology Inc. Boise, ID 83706
ABSTRACT A new texturization technique utilizing a XeCl excimer laser to modify the surface of polysilicon films has been investigated. A significant change in the surface roughness and optical reflectivity of the polysilicon films has been observed after processing. The change in the surface texture depends on the applied laser fluence and polysilicon deposition temperature. For laser fluences of 0.2 J/cm2 to 0.7 J/cm2, the reflectivity of the polysilicon film after laser processing varied from 10% - 180% (relative to silicon). Optimization of the deposition temperature and laser fluence to maximize the surface roughness of the polysilicon film, used as the capacitor storage node, can result in a significant increase in the effective surface area and cell capacitance.
INTRODUCTION As device dimensions in Dynamic Random Access Memories (DRAM's) continue to shrink, the need to achieve a higher stored charge for a given cell area becomes increasingly important. The utilization of advanced trenched (1] or stacked [2-4] cell structures results in a significant improvement over planar structures, but it also adds to the complexity of the process. "Texturization" or "roughening" of the polysilicon film, that forms the storage plate, has recently received a great deal of attention because of its effectiveness in increasing the cell capacitance for a fixed planar area. Several techniques including reactive ion etching [5], low temperature oxidation [6] and rugged polysilicon deposition [7-11] have been investigated to increase the surface roughness of the polysilicon film. In this paper,
a new texturization
800
technique involving the
surface modification of polysilicon films using an excimer laser is reported. Excimer laser processing relies on a high power, ultra - short laser pulse to achieve an enhanced degree of surface roughness. Compared with the existing texturization procedures, this technique is expected to offer a high throughput, better process control and wider process window at the cost of only introducing an additional process step. Structural and crystallographic modifications of polysilicon films using laser processing have been reported earlier in relation to graphoepitaxy (12-14]. For this application, laser energy was used to induce crystallization in polysilicon films deposited on a SiO2 substrate. The desired orientation, (100), in the recrystallized film was achieved by using gratings on the substrate. These investigations were directed at the development of SOI substrates. The parameters that were reported to be important in these studies included the laser power, beam diameter, scan speed and overlap, substrate temperature, atmosphere during crystallization, silicon film doping and the type of substrate. It was also observed that the process conditions that gave the best crystallographic orientations also resulted in a significant degree of surface roughness [15]. For the present application, the primary requirement is the development of a very rough surface texture on the polysilicon film. The crystallographic orientation is of secondary importance as related to the subsequent doping of the film.
EXPERIMENTAL The substrates used for this study were 150 mm, p-type (100) silicon wafers. An insulating layer of PECVD oxide was used between the substrate and the capacitor structures. The polysilicon films for the capacitor plates were deposited in a LPCVD reactor at a pressure of 80 mTorr. The storage plate was deposited at temperatures ranging from 550-625 C, and the top plate was deposited at 625 C. An 8 nm reoxidized nitride (ON) film was used as the cell dielectric. The texturization of the polysilicon film was carried out using a XeCl (308 nm wavelength) excimer laser with an energy of approximately 500 mJ/pulse and pulse duration of approximately 25 nsec. The laser fluence, defined as the laser energy per unit area (J/cm2), was controlled by varying the laser spot size. In this study, the spot size was typically varied from 6.7 to 8.0 mm. The surface texture of the polysilicon film before and after laser processing was examined by scanning electron microscopy. Reflectance at a wavelength of 480 nm was used to quantify the surface roughness of the films. Capacitance -
801
(a) As-deposited (555 C)
(d)
As-deposited (600 C)
(b)
Fluence = 0.656 J/cm2
(e)
Fluence = 0.656 J/cm2
(c)
Fluence = 0.757 J/cm2
(f)
Fluence = 0.757
Fig.
J/cm2
1. SEM micrographs of polysilicon films deposited at 555 and 600 C before and after laser processing.
802
voltage measurements on 6.5 e-5 cm2 evaluating the cell capacitance.
structures were used for
RESULTS AND DISCUSSIONS (A)
Undoped films
The surface texture of polysilicon films deposited at 555 and 600 C before and after laser processing is shown in Fig. 1. As seen in the micrographs, laser processing results in the generation of a surface texture consisting of small globules connected in a grain-like structure. It was observed that the size of the globules and the size of the grain-like structure increases with increasing laser fluence. For the highest fluence used in this study, the globules are quite large and the inter - connecting structure is almost absent, indicating a possible breakdown of the film as shown in Fig. ic. The general development of the structure after laser processing was similar for the other films deposited at 560, 565, 570, 575, and 590 C. It was also observed that that the 600 C film did not exhibit the breakdown (Fig. lf) seen in the other films at the highest fluence. An interesting observation for the polysilicon films deposited at different temperatures was the effect of laser processing on the reflectivity of the films. Reflectance measurement at 480 nm was used to quantify the surface roughness of the films. Results from other texturization experiments have indicated that the reflectance of the film is a good indicator of the surface roughness. As shown in Fig. 2, a good correlation is observed between the reflectance of the film and the cell capacitance. The change in the
120 A S.
AA *
110@ 100
., 90
80
1o
Fig.
2.
1.2
1.3
104
1.5
1.6
Effect of film reflectance on cell capacitance. 803
0 CONTROL A 0 o
150
0 A
S
A
0
v
[3
555 C
r]
A
560 C 565 C
N100-
570 C 575 C
0
590 C 600 C 50 A A A 0 0,5
A
A
0.6
0.8
0.7 LASER FLUENCY (J/cm2)
Fig.
3.
Effect of laser processing on film
reflectance.
0 Q
CONTROL
O
0.550
A
0.636 J/cm2
J/cm2
45
TI
S40
V
35 0
30
560
565
570
POLYSILICON DEPOSITION
Fig.
4.
575
Effect of polysilicon deposition
processing on cell capacitance.
804
625
TEMPERATURE (C)
temperature and laser
of the undoped films as a function of the laser reflectance shown in Fig. 3. There was an fluence during processing is increase in reflectance after laser processing for films depothe 555 to 575 C temperature range. In the case of sited in the higher temperature films (590,600 C), there was a decrease in the reflectance values. The silicon deposition temperature used for these tests corresponds to the amorphous to polycrystalline transition region [16,171. Films deposited under these conditions are expected to exhibit the changes in the surface roughness associated with this transition. However, for the initial set of experiments, we did not see a corresponding change in the reflectance of the films (control values in Fig. laser 3). Based on the reflectance results from these tests, fluences of 0.558 J/cm2 and 0.636 J/cm2 were used to further investigate the changes in the surface roughness of polysilicon films in terms of cell capacitance measurements. The polysilicon films for these tests were also deposited at various temperatures ranging from 560 to 625 C. The effect of the polysilicon deposition temperature and laser fluence on the cell capacitance is shown in Fig. 4. The change in the cell capacitance with deposition temperature observed for the as deposited films (control points) is a result of the amorphous transition , mentioned earlier, and the to polycrystalline
(a)
(b) (b)
(a)
1 pm (c) Fig.
5.
Surface texture of polysilicon films 560, (b) 568, and (c) 575 C. 805
deposited at (a)
*
0
1
100 n. 50 nm
10
0 0
0 0
0 0
£ 00 0
00 I. 0
0 0
1. 0C 0
0.3
0 2
0.6
0 5
0.4
0 7
LASER FLUENCE (J/c-2)
Fig.
6.
Effect film.
of
laser
processing
on a 625 C
polysilicon
associated changes in the surface texture. The variation in the surface texture of the as-deposited films from this group is shown in Fig. 5. An increase in cell capacitance with laser processing is only observed for the films deposited at 560 and 625C, the increase being higher for the 625C film. The changes in cell capacitance with laser fluence for polysilicon films deposited at 625 C are shown in Fig. 6. The highest gain in capacitance for a 50 nm film was 8 %. The thickness of the film is also seen to have an effect on the surface texture after laser processing as indicated by the data points for the 100 nm film. (B)
Doped films
The effect of laser processing on doped polysilicon film is shown in Fig. 7. The film was deposited at 625 C and thermally doped with phosphorus at 850C. The capacitance values in all cases were lower than that observed for the control. The thermal doping of polysilicon results in a small degree of texturization because of enhanced oxidation along the grain boundaries during phosophorus diffusion and the subsequent removal of the oxide. The decrease in capacitance with laser processing could be caused by a reduction in this surface 806
0
CONTROL
390
S38
37-
360.5
0.55
0.6
0.65
0.7
0.75
LASER FLUENCE (J/cm2)
Fig. 7.
Effect of laser processing on
doped 625 C polysilicon
film. roughness. Electrical tests to evaluate the capacitor structures, in terms of leakage current and reliability, were not conducted because of the modest gains in capacitance obtained for the process conditions used in this study. However, similar studies on as-deposited rugged polysilicon structures [11,18,19] have indicated that the small increase in leakage current observed for the rough polysilicon capacitors with a reoxidized nitride(ON) dielectric is negligible compared to the typical increases of several orders of magnitude observed when SiO2 is used instead of ON on a rough electrode. Reliability measurements (Time to 50% failure) on rough and smooth capacitors have indicated a lower lifetime for the rugged capacitors at high fields (8-12 MV/cm). However, because of their higher field acceleration coefficient, rugged capacitors are expected to exhibit a much higher lifetime value at the operating field of 3 MV/cm [11,19]. Rugged polysilicon electrodes have been observed to exhibit electron trapping as opposed to hole trapping for the smooth electrodes [18]. Similar observations have been reported in studies related to EEPROM's [20,21] and the results were attributed to the large localized current density at the tip of the asperities. This phenomena, which limits the endurance of EEPROM's [20] can actually be beneficial for DRAM
807
applications where it can relax the localized high fields and reduce excessive leakage currents [22].
electric
CONCLUSIONS A new texturization technique utilizing an excimer laser to enhance the surface roughness of polysilicon films has been investigated. A significant change in the surface roughness and optical reflectivity of the polysilicon film has been observed after laser processing. The polysilicon deposition and doping conditions as well as the laser fluence used during processing were found to be the important parameters for this texturization process.
ACKNOWLEDGEMENT The authors would like to thank M. Tuttle, A. Martin, T. Doan, P. C. Fazan, and H. C. Chan for discussions. The assistance from the process development, manufacturing, and the Y.E. SEM lab groups at Micron is also gratefully acknowleged.
REFERENCES N.C.C. Lu, IEEE Circ. Dev. Mag., Vol. 5, No. 1, 27(1989). T. Ema, S. Kawanago, T. Nishi, S. Yoshida, H. Nishibe, T. Yabu, Y. Kodama, T. Nakano and M. Taguchi, IEDM Tech. Dig., 592(1988). [3] W. Wakamiya, Y. Tanaka, H. Kimura, H. Miyatake and S. Satoh, Symposium VLSI Tech., 69(1989). [4] S. Inoue, A. Nitayama, K. Heida and F. Horiguichi, Ext. Abs. 21st Conf. on SSDM, 141(1989). [5] T. Mine, S. Iijima, J. Yugami, K. Ohga and T. Morimoto, Ext. Abs. 21st Conf. on SSDM, 137(1989). (6] P.C. Fazan, and R.R. Lee, IEEE Electron Dev. Lett., Vol. 11, No. 7, 279(1990). [7] M. Sakao, N. Kasai, T. Ishijima, E. Ikawa, K. Terada and T. Kikkawa, IEDM Tech. Dig., 655 (1990). [8] M. Yoshimaru, J. Miyano, N. Inoue, A. Sakamoto, S. You, H. Tamura and M. Ino, IEDM Tech. Dig., 659(1990). [9] Y. Hayoshide, H. Miyatake, J. Mitsuhashi, M. Hirayama, T. Higaki and H. Abe, Ext. Abs. 22nd Conf. on SSDM, 869 (1990). [10] H. Watanabe, N. Aoto, S. Adachi, T. Ishijima, E. Ikawa, [1] [2]
808
K. Terada, Appl. Phys. Lett., Vol. 58, No. 3, 251 (1991). A. Ditali and [11] V. K. Mathews, P. C. Fazan, G. S. Sandhu, H.R. Rhodes, Ext. Abs. 179th ECS Meeting, Vol. 91-1 , No. 375, 567(1991). [12] M.W. Geis, D.C. Flanders, D.A. Antoniadis and H.I. Smith, Apple. Phys. Lett., Vol. 35, 71(1979). [13] M.W. Geis, D.C. Flanders, D.A. Antoniadis and H.I. Smith, J. Vac. Sci. Tech., Vol. 16, 1640(1979). [14] M.W. Geis, D.C. Flanders, D.A. Antoniadis and H.I. Smith, IEDM Tech. Dig., 210(1980). [15] M.W. Geis, D.A. Antoniadis, D.J. Silversmith, R.W. Mountain and H. I. Smith, Appl. Phys. Lett., Vol. 37, No. 5, 454(1980). [16] P. Joubert, B. Loisel, Y. Chouan and L. Haji, J. Electrochem. Soc., Vol. 134, No. 10, 2541(1987). Proust and K. Zellama, J. Bisaro, J. Magarino, N. [17] R. Appl. Phys., Vol. 59, No. 4, 1167(1986). [18] H. C. Chan, V. K. Mathews and P. C. Fazan, submitted to Elec. Device Letters. H.C. Chan and A. Ditali, to be [19] P.C. Fazan, V.K. Mathews, submitted to Appl. Phys. Letters. [20] N. Mielke, A. Fazio and H.C. tiou, Proc. Int. Rel. Phys. Symp., 85(1987). [21] Y. Fong, A.T.T. Wu and C. Hu, IEEE Trans. Elec. Devices., Vol. 37, 583(1990). [22] T. Watanabe, N. Gato, N. Yasuhisa, T. Yamase, T. Tamnaka and S. Shinozaki, Int. Rel. Phys. Symp., 50(1989).
809
AS-DEPOSITED RUGGED POLYSILICON FOR 16 AND 64 MBIT DRAM CELLS Viju K. Mathews, Pierre C. Micron Technology Inc,
Fazan and Akram Ditali Boise, Idaho 83706
ABSTRACT The effect of processing conditions on the surface texture of polysilicon films has been investigated in this study. We observed an increase in the surface roughness and the corresponding cell capacitance for films deposited at temperatures ranging from 560-570 C when compared to the smooth films obtained at 625C. The as-deposited surface texture is very sensitive to the procedure used for doping the film. The dielectric deposition conditions were also observed to have a small effect on the measured capacitance. The stability of the "rugged" films to subsequent high temperature processing, the electrical properties, and reliabilty of the capacitor structures have also been evaluated.
INTRODUCTION The transition to higher generations of dynamic random access memories (DRAM) is associated with a corresponding decrease in the cell size. This has a direct effect on the surface area available for the storage capacitor. The minimum charge required for the reliable operation of a memory device is determined by several factors such as the soft error rate, sense amplifier sensitivity, 0-1 storage voltage difference and bit line capacitance [1]. This requirement has led to the development of several innovative cell designs utilizing trenched [2] or stacked structures [3-5]. These advanced 3-D structures increase the surface area available for the capacitor without significantly affecting the cell size. However, they usually tend to increase the complexity of the process. Another alternative is the use of materials with high dielectric constants like Tantalum pentoxide [6], Yittrium Oxide [7], and Lead Zirconate Titanate (PZT) [8]. These materials have yet to be used on a large scale because of several unresolved issues related to their processing, leakage current, and reliability. A recent development in the field of cell capacitors has been the application of techniques designed to "roughen" or "textu-
810
rize" the surface of the polysilicon film used as the storage node. This results in a larger surface area for the same planar area occupied by the film. One approach has been the deposition of smooth polysilicon films followed by texturization using reactive ion etching [9], low temperature oxidation [10], or laser processing [11]. The surface texture of polysilicon films can also be changed during deposition by varying the process conditions [12-17]. The main advantages offered by the as-deposited "rugged" polysilicon technique include the simplicity of the process as well as the use of fabrication procedures that are slight variations of well established polysilicon deposition techniques. In addition to this, the electrical characteristics and reliability of capacitor structures using polysilicon films has been widely investigated. In this paper we report on the changes in the surface texture and the corresponding increase in cell capacitance that can be achieved by varying the process conditions during the deposition of polysilicon films. The stability of the "rugged" film during doping, dielectric deposition and subsequent high temperature processing steps has also been investigated. Finally, the leakage characteristics and reliability of the rugged polysilicon capacitor structures are evaluated with respect to the smooth polysilicon capacitors.
EXPERIMENTAL P-Type, (100) wafers with 200 nm of densified TEOS oxide were used as the base for depositing the polysilicon films that formed the storage plate of the capacitor. The polysilicon films were deposited in a vertical LPCVD reactor at temperatures ranging from 550 to 625 C . The base operating pressure was 80 mTorr. The tube pressure was also varied from 80 to 1000 mTorr to study its effect on the film texture. An 8 nm thick re-oxidized nitride (ON) film was used as the cell dielectric. The top plate of the capacitor consisted of a 100 nm thick polysilicon film doped by phosphorus diffusion. The surface texture of the polysilicon films were evaluated using reflectance measurements, scanning electron microscopy, and scanning force microscopy. Their capacitance and leakage current characteristics were determined from capacitance - voltage (C-V) and current-voltage (I-V) measurements using 6.5e-5 cm2 structures. The capacitor lifetime at high electric fields was measured by constant voltage time dependent dielectric breakdown (TDDB) on 2.0e-2 cm2 structures. All measurements involved the application of both positive and negative voltages to the top capacitor electrode to simulate the actual operation of a multi-megabit memory cell. Some of the tests were also conducted at 125 C.
811
(a)
(d)
(b)
(e)
(c) Fig.
I Pm
(f)
1. Surface texture of polysilicon films deposited at (a) 555, (b)560, (c)565, (d)570, (e)575, and (f)625 C.
812
RESULTS AND DISCUSSION
The surface texture of the polysilicon films deposited at the various temperatures used in this study are shown in Fig. 1. The films are amorphous at 550 C and polycrystalline at 625 C. Within this range, the change in surface texture associated with the transition from the amorphous to the polycrystalline phase [13] is responsible for the appearance of the rough layers. For the 100 nm thick films used in this study, we observed a good correlation between the surface roughness of the film and its reflectance (Fig. 2). These measurements were at a wavelength of 480nm, but similar trends were observed at shorther wavelengths of 280 and 370 nm. The change in cell capacitance with the polysilicon deposition temperature is shown in Fig. 3. The maximum increase in capacitance observed in this study was 54%. The changes in capacitance with temperature correlate very well with the surface roughness observed in the SEM micrographs and the reflectance measurements. The surface texture of the polysilicon film was observed to be very sensitive to the doping procedure. As shown in the figure, thermal diffusion of phosphorus to dope the film gives a much lower increase in the capacitance compared to the optimized process. The slightly higher capacitance observed for the 625 C film compared to the 550 and 555 C films, after thermal diffusion, is due to the grain boundary enhanced dif-
1201 PHO0SPHORU0 DIFFUSI00
512
Ii0
•103
i
900
701 0.L 4054 5 0
560 50
580
050 600
620
620
560 500 560 590 600 610 620 630 SOtyTLCON DEPOOSTION 'r~IEMIIAlII( (C)
550
630
pOLYSILICON DEPOSITION TENOEOATURE (C)
Fig.
2.
Change in reflectance with polysilicon deposition temperature.
Fig.
813
3.
Effect of polysilicon deposition temperature on cell capacitance
1.5-
S N N
756 C ( 3:1) 765 C (10:1) 600 C (3:1)
1 *
1.4
~14 11
,
550
6o
POLYSILICON DEPOSITIONT-
Fig.
4.
G
0,
_D
-P-ERAT E (C)
Effect of dielectric deposition conditions on cell capacitance.
_Du "Du 7 8ED "Du 9 -a o
1-u
-•
630
POLYSILICONDEPOSITIONT-pERATURE (C)
Fig.
5.
Stability of the films to subsequent high temperature processing.
fusion in the high temperature film which results in a small amount of texturization. The figure also indicates the high sensitivity of the polysilicon surface roughness to the deposition temperature. This sensitivity can be reduced by otpimizing the
deposition
pressure.
Three different
silicon
nitride
films were used to study the stability of the polysilicon film to the dielectric deposition conditions. The variables included the deposition temperature and the ammonia to dicholorosilane ratios. Based on the results from the rugged polysilicon annealing tests, mentioned below, the temperature at which the nitride film is deposited is not expected to cause any significant change in the polysilicon surface texture. The small differences that were observed could be associated with the conformality of the nitride film as affected by the gas flow ratio and temperature or the variation in thickness of the nitride film. The stability of the films to subsequent processing was evaluated by annealing the final capacitor structures at 900 and 957C in a nitrogen ambient. As shown in Fig. 5, the annealing treatments do not affect the roughness of the polysilicon films. However, it was observed that capacitors formed on smooth polysilicon films (575 and 625 C) exhibited an excessive amount of leakage current after the thermal cycles. I-V curves for samples with different
814
polysilicon storage
I r%-3 IU
-
2500
CDB
CA
10-4
Positive 5D
:0
4 t -11 IV
0
3
6 9 Voltage (V)
12
4
10
Voltage (V)
(a)
(b)
10-3
10"•i
1250C Positive
DB
104-
C
0)
A
125°C
D C
106
Negative
A
0)
10OI
0
10-12U
Fig.
6.
3
6
9
12
15
0
3
6
9
Voltage (V)
Voltage (V)
(c)
(d)
12
15
Current-Voltage characteristics for polysilicon films at (a)25 C, + bias, (b)25 C, - bias, (c)125 C, + bias, and (d)125 C, - bias. The films were deposited at (A)625, (B)570, (C)565, and (D)560 C.
815
improvement of at least 3 orders of magnitude. Hence, the use of a rugged polysilicon electrode for storage capacitors provides a considerable increase in capacitance and also improves their reliability.
CONCLUSIONS The application of as-deposited rugged polysilicon films for the fabrication of cell capacitors in high density DRAM's has been reported in this paper. These films increase the cell capacitance for a given planar surface without increasing the process complexity. The stability of the films to subsequent high temperature processing coupled with the low leakage currents and high lifetime values exhibited by the capacitor structures makes them a highly attractive option for high density dynamic random access memories.
ACKNOWLEDGEMENTS The authors would like to thank Annette Martin and Mark Tuttle for discussions, Bill Black for the TDDB measurements, Brenda Jameson for assistance with the manuscript, and the process development, manufacturing and Y.E. Sem Lab groups at Micron for assistance with the experiments.
REFERENCES [1] [2] [3] (4] [5] [6] [7] [8]
A.L. Tasch and L.H. Parker, Proceedings of the IEEE, Vol. 77, No. 3, 374(1989). N.C.C. Lu, IEEE Circ. Dev. Mag., Vol. 5, No. 1, 27(1989). T. Ema, S. Kawanago, T. Nishi, S. Yoshida, H. Nishibe, T. Yabu, Y. Kodama, T. Nakano and M. Taguchi, IEDM Tech. Dig., 592(1988). W. Wakamiya, Y. Tanaka, H. Kimura, H. Miyatake and S. Satoh, Symposium VLSI Tech., 69(1989). S. Inoue, A. Nitayama, K. Heida and F. Horiguichi, Ext. Abs. 21st Conf. on SSDM, 141(1989). H. Shinriki, Y. Nishioka, Y. Ohji and K. Mukai, IEDM Tech. Dig., 684(1986). L. Manchanda and M. Gurvitch, IEEE Electron Dev. Lett., Vol. 9, No. 4, 180(1988). J. Carrano, C. Sudhama, J. Lee, A. Tasch and W. Miller, IEDM Tech. Dig., 255(1989).
818
[9] [10] [11] [12] [13] (14] [15] [16] [17] [18] [19] [20] [21]
Yugami, K. Ohga and T. Morimoto, T. Mine, S. Iijima, J. Ext. Abs. 21st Conf. on SSDM, 137(1989). P.C. Fazan and R.R. Lee, IEEE Electron Dev. Lett., Vol. 11, No. 7, 279(1990). V.K. Mathews and C. Yu, Ext. Abs. 179th ECS Meeting, Vol. 91-1, No. 374, 565(1991). P. Joubert, B. Loisel, Y. Chouan and L. Haji, J. Electrochem. Soc., Vol. 134, No. 10, 2541(1987). Zellama, J. Magarino, N. Proust and K. R. Bisaro, J. Appl. Phys., Vol 59, No. 4, 1167(1986). Ikawa, K. Terada and M. Sakao, N. Kasai, T. Ishijima, E. T. Kikkawa, IEDM Tech. Dig., 655 (1990). M. Yoshimaru, J. Miyano, N. Inoue, A. Sakamoto, S. You, H. Tamura and M. Ino, IEDM Tech. Dig., 659(1990). Y. Hayoshide, H. Miyatake, J. Mitsuhashi, M. Hirayama, T. Higaki and H. Abe, Ext. Abs. 22nd Conf. on SSDM, 869 (1990). Aoto, S. Adachi, T. Ishijima, E. Ikawa H. Watanabe, N. 251 and K. Terada, Appl. Phys. Lett., Vol. 58, No. 3, (1991). L. Faraone, IEEE Trans. Electron Dev., Vol. 33, No. 11, 1785(1986). Phys., Vol. 38, No. 7, 2951(1967). S. M. Sze, J. Appl. IEDM Tech. Dig., 663(1990). P. C. Fazan and A. Ditali, H. KitaA. Nishimura, S. Murata, S. Kuroda, 0. Enomoto, Phys. Symp., 158 gawa, and S. Hasegawa, Proc. Int. Rel. (1989).
819
EXPERIMENTAL VERIFICATION OF A FUNDAMENTAL MODEL FOR MULTIWAFER LPCVD OF POLYSILICON Thomas A. Badgwell, Thomas F. Edgar, Isaac Trachtenberg Department of Chemical Engineering, The University of Texas at Austin Austin, Texas 78712 J. Kiefer Elliott SEMATECH, Inc. Austin, Texas 78741
A fundamental model for multiwafer LPCVD of polysilicon has been developed and evaluated in terms of its ability to predict experimental data from two widely differing reactors. The model can predict the main features of polysilicon deposition in a small research reactor, even though the model parameters were estimated using data taken from a much larger industrial system. It is demonstrated that the assumption of thermal variations within the reactor can greatly improve model predictions.
INTRODUCTION The horizontal multiwafer Low Pressure Chemical Vapor Deposition (LPCVD) reactor, first introduced in the late seventies [1], is a critical component in the manufacture of integrated circuits. Although this type of reactor is widely used to deposit polysilicon, nitride and low temperature oxide films [2, 3], the transport phenomena and chemical reactions influencing these processes are not well understood. Recent attempts to model the multiwafer LPCVD reactor have shown promising results [4, 5, 6, 7], however an accurate fundamental model which can predict both growth rate and radial nonuniformity for a wide range of chemistries has yet to be developed. This paper presents an experimental evaluation of a fundamental model for 820
multiwafer LPCVD of polysilicon. This analysis demonstrates the capabilities of a relatively simple modeling approach, and suggests promising directions for future
research. UTCVD-P: A MODEL FOR POLYSILICON LPCVD Jensen, Graves and Roenigk have published the most comprehensive modeling work to date for this reactor [4, 5, 6, 7], using concepts from heterogeneous catalysis in their approach. Roenigk's multicomponent model [7] contained two one-dimensional species continuity equations, one for axial transport down the reactor tube and the other for radial transport into the region between each wafer pair. The two equations were coupled at the boundary between the annular and interwafer regions. The Stefan-Maxwell equations were used to relate mole fractions to molar fluxes [8]. An arbitrary number of gas and surface reactions were allowed in this approach. The modeling equations were solved by orthogonal collocation [9]. The derivation of any fundamental model must necessarily involve a trade-off between complexity and utility. The University of Texas Chemical Vapor Deposition of Polysilicon (UTCVD-P) model was developed specifically to investigate thermal variations within the reactor, and to assess the ability of a simplified model to predict experimental results for polysilicon deposition. Other important considerations, such as different chemical processes, a multicomponent gas phase and more complex geometry are not addressed by this model, although these extensions are included in a multicomponent LPCVD model (UTCVD-M) currently under development at The University of Texas. The UTCVD-P model developed here can be regarded as an extension of the Jensen and Graves model [4] to include axial and radial thermal variations, and the more recent kinetic expression published by Roenigk and Jensen [5]. The modeling assumptions include:
"* Multiwafer
hot wall LPCVD reactor, deposition section only
"* Steady-state ideal gas "* Binary gas phase system of silane and hydrogen "* Isobaric plug flow "* A single rate-limiting surface reaction, with the reaction Si) R = kjexp(-l8500/T)pj (mol m-sec + k3 p 1+ k
821
rate given by:
Miuttwater Hot-Wall Reactor Pressure Sonsor
3-Zone Furnace
Quartz Tube
5to205 Load Door
ooue
ae
Waer
Reactant Gases
Boat
UTCVD-P Represenlatlon
F-
K
reacantos vo '0 x0
I
AIl
0
I L
Figure 1: Multiwafer LPCVD Reactor and UTCVD-P Representation
"* Temperature
varies axially within the reactor as follows:
J T
"* Temperature
0.2 _ 0.8 Tp(()
(2)
varies radially across each wafer as follows: T.(ý, () = Te(C) + b(()(4' - 1)
b(C)
-
bo ~0.05 < C• 0.95 b, + b,(( - 0.05)2 C < 0.05
(3)
(4)
bo + bi(C - 0.95)' C > 0.95 Figure 1 shows a typical horizontal multiwafer LPCVD reactor and the corresponding geometry assumed by UTCVD-P. The reactor inlet and outlet sections are ignored by the model. The reactor is divided into two types of regions, the annular space surrounding the wafers, and the interwafer region between each pair of wafers. Isobaric plug flow is assumed for the gas phase, following Roenigk and Jensen [5]. This assumption is supported by direct experimental measurements performed
822
by Hitchman and co-workers [101, and allows the momentum balance to be dropped from consideration. Coltrin et al. [11] postulated that gas phase reactions are not important for this system below 630 degC, and that under these conditions the gas phase can be considered as a binary mixture of silane and hydrogen. We therefore assume a binary gas mixture undergoing a single rate-limiting surface decomposition. The kinetic rate expression used by UTCVD-P is taken from Roenigk and Jensen [5], although slightly different values for the rate constants have been computed in this investigation. The proposed functional forms for axial and radial thermal variations presented here are strictly empirical. They were chosen so as to fit patterns evident in experimental data. The quadratic axial variation function (2) is symmetric about the reactor midpoint, and falls off rapidly at both ends of the wafer load. The radial variation function (4) includes the built-in assumption that the total edge to center thermal drop is smallest at the reactor midpoint and increases toward the ends of the wafer boat. The temperature profile across a given wafer (3) is assumed to follow a quadratic profile and satisfies a symmetry condition at the wafer center. The three constants which define the thermal environment for the model must be estimated from experimental data. The UTCVD-P axial and radial model equations are identical to those derived by Jensen and Graves [4] with the exception of the inlet Danckwerts boundary condition [12]. The corrected form used here was also derived by Joshi [13]. The axial equation and boundary conditions are as follows: d
(VA-) d(
+ Re
- Pe(Dal + DaIz)g(x) = 0
d(C odxP (I +cXo)'Xo
l(6)
=0
(5) (6)
The axial dimension is scaled by the reactor length:
z L
(7)
The axial equation is affected by three dimensionless parameters: Pe = D--L
(8)
2Lr,(1 + a)R0o
(9)
vo(rt' - r,)clo 2Lr',Rl° Da 2 - vo(r2 r)co
10 (10)
823
The Peclet number Pe measures the strength of convection relative to diffusion. The Damkoehler numbers measure the strength of reaction on the tube and boat surfaces (Dal) and the wafers (Da 2) relative to convection. The dimensionless reaction rate is scaled by the rate at inlet conditions: (11)
R(x)
A dimensionless factor accounting for volumetric expansion and thermal effects also appears in the axial equation:
S=(1(1++)'X)'
(T) °.65
f/
12
The radial equation and boundary conditions are:
)_'X) +
i ( (_-_
1 g(X) = 0
=0
X1=Xb
(13) (14)
The radial dimension is scaled by wafer radius: r
(15)
The radial equation is affected by a single dimensionless parameter, the Thiele modulus 4, which measures the strength of reaction relative to radial diffusion: = AcoD
T)0
(16)
The effectiveness factor r measures the average reaction rate across a wafer relative to the rate at the wafer edge, and links the axial and radial equations together:
2 f, R(r)•r•dr RK,
(17)
As the effectiveness factor approaches one, the deposited film becomes more uniform. At a given position, the average film growth rate is computed as follows: G. = vi Rio g(x(C)) 7
824
(18)
The nonuniformity of the deposited film U. (standard deviation divided by mean) is determined by: U=
2 =
2
(o
1)
2
d
(19)
Nonuniformity increases as the effectiveness factor decreases from one. The model equations (5-6) and (13-14) were discretized by orthogonal collocation on finite elements [9], and the resulting nonlinear equations were solved by a HybridPowell method [14]. The steep thermal gradients of the assumed thermal profile required the use of a multiple element solution, rather than the single element approach used by Jensen and Graves [4]. The integrals in equations (17) and (19) were evaluated by Radau quadrature and the interpolated model solution was computed using Lagrange interpolation [15]. POLYSILICON DEPOSITION EXPERIMENTS Experimental data for polysilicon deposition have been collected from two reactors; an industrial scale system at SEMATECH and a research reactor at U.T. The SEMATECH system is a state-of-the-art horizontal BTU/BRUCE furnace, capable of processing up to 150 wafers in six boats of 25 wafers each. Table 1 describes the reactor geometry for the SEMATECH runs. Twenty-eight runs were performed with changes in temperature, inlet composition, total flowrate and pressure, following a Box-Behnken experimental design [16]. Although only the centerpoint runs are discussed here, a more detailed account of these experiments is available elsewhere [17]. The three centerpoint runs were performed at the following conditions; 615 degC, silane mole fraction 0.6 (in hydrogen), total flowrate 230 sccm, and pressure 325 mtorr. For each run, growth rate and film uniformity measurements were taken from monitor wafers at nine locations throughout the load. Monitor positions in the 150 wafer load were: 1, 13, 26, 51, 76, 101, 126, 138, and 150. A Prometrix FT-500 film thickness probe was used to measure the distribution of film thickness at 49 locations on each monitor wafer. Average growth rate was computed as the average of the 49 readings divided by the deposition time of one hour, and radial nonuniformity was computed as the standard deviation of the 49 measurements divided by the mean. The U.T. reactor system is a small research furnace, capable of processing up to 50 wafers in a single open boat. This reactor is about half the size of the SEMATECH system and runs four inch rather than six inch diameter wafers. Three runs were performed at the same process conditions; 615 degC, 322 mtorr, and a silane flowrate of 102 sccm. Table 1 describes the reactor geometry for the U.T. runs. A total of sixteen monitor wafers were measured for each run, providing a higher degree of detail for the axial variations in growth rate and radial nonuniformity. Monitor positions in the 50 wafer load were: 1, 4, 7, 10, 13, 19, 23, 25, 26, 28, 32, 38, 41, 44, 47 and 50. 825
Table 1: SEMATECH and U.T. Reactor Geometry Parameter
SEMATECH Reactor
U.T. Reactor
Reactor Length (m) TC 1 Location (m) TC 2 Location (i) TC 3 Location (i) TC 4 Location (m) TC 5 Location (W) First Wafer (m) Last Wafer (m) Injector 1 Location (m) Injector 2 Location (m)
2.286 0.572 0.793 1.13 1.51 1.61
1.186 0.330 0.483 0.635
0.744 1.47 1.14 1.36
0.466 0.703
Interwafer Spacing (m)
0.00479
0.00483
Tube Inner Radius (m) Wafer Radius (m)
0.160 0.075
0.075 0.050
Boat area/tube area
0.0732
0.0767
A Nanometrics Nanospec/AFT was used to measure the distribution of film thickness at 13 locations on each monitor wafer. Average growth rate was computed as the average of the 13 readings divided by the deposition time of 33 minutes, and radial nonuniformity was computed as the standard deviation of the 13 measurements divided by the mean.
MODEL COMPARISON WITH EXPERIMENTAL DATA Isothermal Case UTCVD-P model parameters were first estimated from the SEMATECH data for the case of an isothermal reactor. Optimal kinetic parameters kj, k2 , and k3 were estimated with a nonlinear parameter estimation package called GREG (General Regression) developed by Caracotsios [18]. The optimal isothermal parameter estimates, shown in Table 2, were found to be of the same magnitude as those reported by Roenigk and Jensen [5]. The intervals reported here are the higher posterior density (HPD) intervals for a 95% probability level. The intervals for our estimates are not symmetric because we estimated the logarithm of the parameters, rather than the parameters themselves. For the SEMATECH centerpoint conditions our estimated reaction rate is 1.6 x 10-moI Si/m 2sec, compared to 1.9 x 0l-mol Si/m 2 sec using the constants from Roenigk and Jensen. This discrepancy can be attributed to a number of factors, including the use of different data sets, models and estimation 826
Table 2: Optimal Isothermal Parameter Estimates Roenigk et al. Parameter {] Our Estimates
ki(molSi/m 2 secatm) k2(atm- 12) k 3 (atm -)
(2.2 < 3.7 < 6.4) x 10' (1.2 < 4.1 < 14) x 101 (0.8 < 1.5 < 2.7) x 10'
(1.2 < 1.6 < 2.0) x 10' (3.0 < 6.0 < 9.0) X 101 (6.0 < 7.0 <8.0) x 10'
[o i,0oo0
0 I,
2IfXOO C 24J01X
....
00.0
02
0.4
0.6
O,.
isotheral 1 UTCVD-P I
1.0
0imensionles AMist Posittion
Figure 2: Growth Rate for SEMATECH Reactor, Centerpoint Runs methods. Isothermal model predictions are compared with the SEMATECH data in Figures 2 and 3. While the experimental data consistently show a drop in the growth rate at the ends of the wafer load, predictions from UTCVD-P for the isothermal case show no such trend. Another problem is that the nonuniformity predictions are consistently low by several orders of magnitude. Although not shown here, isothermal predictions for the remaining SEMATECH runs show the same general trends.
Non-isothermal Case To improve the model predictions the empirical thermal profile described in equations (2) through (4) was added to UTCVD-P. Optimal kinetic parameters k1 , k 2, and k 3 and thermal parameters al, b0 , and b, were estimated with the GREG package [18], and are shown in Table 3. Although our point estimates do not agree exactly, the HPD intervals for our kinetic parameter estimates do overlap with those 827
15
-
1-
.......
. ... ... ... ..
9
. ... ..........
al 11M 0 MW
-
x 24000 z
2
3.'.............. ................. i................ ................. ............ ..'
lTotmal I US.... UTCVD-P I
o~"A'lt"• 0.0
0.2
~
0.4
~
.. 0.6
. 0.8
170
Dimensionless Axial Position
Figure 3: Radial Nonuniformity for SEMATECH Reactor, Centerpoint Runs
Table 3: Optimal Parameter Estimates with Thermal Profile Parameter kl(molSi/m 2 secatrm) k2 (atm-1 2 ) k3(atm-1) al(degC) bo(degC) bl(degC)
Our Estimates (0.4 < 2.0 < 10) x 109 (0.6 < 3.7 < 24) x 102 (0.2 < 1.1 < 3.9) x i0s (1.9 < 2.4 < 3.0) x 101 (0.7 < 1.1 < 1.8) (3.5 < 3.9 < 4.3) x 10'
from Roenigk and Jensen. The estimated thermal profile is shown in Figures 4 and 5. Figure 4 shows that the estimated drop-off in temperature at the front and back of the wafer load is about 15 degC. Figure 5 shows that the estimated temperature difference across the wafers is constant at about 1 degC throughout most of the load, increasing sharply to about 10 degC at the ends. UTCVD-P model predictions for the SEMATECH data set are shown in Figures 2 and 3. It is clear from Figures 2 and 3 that introducing the thermal profile greatly improves both growth rate and radial nonuniformity predictions. There are still some variations in the nonuniformity profile which are not predicted by the model. More accurate prediction of radial nonuniformity will require a more detailed model of the reactor's thermal environment. Direct in-situ temperature measurements are necessary to confirm the existence of the large thermal variations predicted in Figures 4 and 5. A fundamental model of the radiative heat transfer between the tube and 828
630 630610
5de gc
ProfileTempf..
degC
Prof il
,
degC Temrp-. ProfMle , .51 T mp
E
600
590 .
0.0
............
0.2
..
.... ....... ........ ....
0.4
OimefsionI...
0.6
0.8
. ....
1.0
Axi.l Position
Figure 4: Average Temperature Profile for SEMATECH Reactor
E
2
Oimrnenionies Axial Position
Figure 5: Wafer Temperature Drop Profile (Edge Minus Center) for SEMATECH Reactor
829
120
Nibs is
"
S
0 -
30. 0.0
Rx 2 UTCVD-P 1
i+ 0.2
0.4 1mn .r..Il.Mn
0.6
OS.
1.0
Axil1 P..HioW
Figure 6: Growth Rate for U.T. Reactor the wafers may be required to accurately predict radial nonuniformity.
Comparison with U.T. Data To test the predictive capability of the model it was compared with experimental data from the U.T. reactor. Kinetic and thermal parameters estimated from the SEMATECH data were used to predict growth rate and radial nonuniformity for the U.T. reactor runs, with the results shown in Figures 6 and 7. The model provides a reasonable estimate of the growth rate profile, but does not correctly predict the observed radial nonuniformity. The most likely source of this error is the assumption that the two reactors have identical thermal environments. Nevertheless, this illustrates that it is possible to roughly predict the behavior of an LPCVD reactor using this relatively simple fundamental model. CONCLUSIONS The main features of polysilicon deposition in a multiwafer LPCVD reactor can be satisfactorily explained by a predictive steady-state model. Although most multiwafer LPCVD models assume an isothermal reactor, it has been shown that model predictions can be improved by the assumption of both radial and axial thermal variations, following a simple empirical profile. A 15 degC drop in wafer temperature at the front and back of the wafer load is required to explain the observed variations in growth rate in these regions. A 1 degC variation across the wafers is required to explain the observed film uniformity in the center of the reactor, increasing to a 10 830
1ý
F
Z2
O Run2 x
6
Fin3
-UTCVD-P
I
3
8
A
4 0.0
02
0,4
Q
06
0.8
*
I 1.0
Dlimensionless Axiol Position
Figure 7: Radial Nonuniformity for U.T. Reactor degC required variation across the end wafers. A more accurate prediction of radial nonuniformity, of primary importance in the manufacture of integrated circuits, may require a more detailed model of the reactor's thermal environment. Our future plans include collecting in-situ temperature measurements to verify the assumed thermal variations, and development of a more detailed multicomponent multiwafer LPCVD reactor model. Ultimately we plan to use these models in conjunction with a model-based control scheme to maximize productivity while satisfying product quality constraints. ACKNOWLEDGEMENTS The authors are grateful for the generous support provided by SEMATECH (contract 88-MC-505) and the Semiconductor Research Corporation in conducting this investigation.
831
LIST OF SYMBOLS Z L
TO Do Co T Pt kl, k 2 , k3 b(C) xo
g Cv Dal Gý Vsi P
= = = = = = = = = = = = = = = = = = = = = =
axial coordinate (m) reactor length (m) wafer radius (m) interwafer spacing (m) inlet temperature (K) 2 reaction rate at wafer edge (mol/m sec) inlet binary diffusivity (M2/ase) 3 inlet total concentration (mol/m ) temperature (K) tube temperature (degC) silane partial pressure (atm) kinetic constants temperature drop across wafer (degC) inlet fractional conversion of silane dimensionless axial coordinate inlet silane mole fraction dimensionless reaction rate Damkoehler number for tube and boat Thiele modulus average wafer growth rate (A//min) 3 polysilicon film molar volume (m /mol) mean film thickness
rI rt a R Rio vo oto xio pa P2 ai, bo, bi X Xb
Da2 'k
UW o
= = = = = = = = = = = = = = = = = = = = =
radial coordinate (m) reactor tube diameter (m) ratio of boat to tube inner surface area 2 reaction rate (mol/m asc) 2 reaction rate at inlet conditions (mol/m sec) inlet axial gas velocity (m/sec) ) inlet silane concentration (mot/m3 inlet mole fraction for component j wafer edge temperature (degC) wafer temperature (degC) hydrogen partial pressure (atm) thermal profile constants (degC) fractional conversion of silane fractional conversion of silane at wafer edge dimensionless radial coordinate effectiveness factor Peclet number Damkoehler number for wafers volume temperature factor radial nonuniformity (%) standard deviation of film thickness
References [1] R. S. Rosier. Solid State Technology, 20, 63, (1977). [21 H. H. Lee.
Fundamentals of Microelectronics Processing. McGraw-Hill, New
York, N.Y., (1990). [3] S. M. Sze. VLSI Technology. McGraw-Hill, New York, N.Y., (1988). [4] K. F. Jensen and D. B. Graves. J. Electrochem. Soc., 130, 1950, (1983). [5] K. F. Roenigk and K. F. Jensen. J. Electrochem. Soc., 132, 448, (1985). [6] K. F. Roenigk and K. F. Jensen. J. Electrochem. Soc., 134, 1777, (1987). [7] K. F. Roenigk. Analysis of Low Pressure Chemical Vapor Deposition Processes.
PhD thesis, University of Minnesota, (1987). [8] R. Bird, W. Stewart, and E. Lightfoot. Transport Phenomena. John Wiley and Sons, New York, N.Y., (1960). [9] Bruce A. Finlayson. Nonlinear Analysis in Chemical Engineering. McGraw-Hill, New York, N.Y., (1980). [10] M. L. Hitchman, J. Kane, and A. E. Widmer. Thin Solid Films, 59, 231, (1979).
832
[111 M. E. Coltrin, R. J. Kee, and G. H. Evans. (1989).
J. Electrochem. Soc., 136, 819,
[12] P. Danckwerts. Chem. Eng. Sci., 2, 1, (1953). [13] M. G. Joshi. J. Electrochem. Soc., 134, 3118, (1987). [14] J. J. More, B. S. Garbow, and K. E. Hillstrom. User Guide for Minpack-1. Technical Report ANL-80-74, Argonne National Laboratory, (1980). [15] J. Villadsen and M. L. Michelsen. Solution of Differential Equation Models by
Polynomial Approximation. Prentice-Hall, Englewood Cliffs, N.J., (1978). [16] E. P. Box and D. W. Behnken. Technometrics, 2, 455, (1960). [17] T. A. Badgwell, T. F. Edgar, I. Trachtenberg, and J. K. Elliott. Experimental Evaluation of a Fundamental Model for Multiwafer LPCVD of Polysilicon. Technical Report C91188, Semiconductor Research Corporation, (1991). [18] M. Caracotsios. Model ParametricSensitivity Analysis And Nonlinear Parameter Estimation. Theory and Applications. PhD thesis, University of Wisconsin-
Madison, (1986).
833
LOW-TEMPERATURE SILICON EPITAXY WITHOUT SUBSTRATE HEATING BY ULTRACLEAN ECR-PLASMA-ENIIANCED CVD Koichi Fukuda,+ Junichi Murota,# and Shoichi Ono Research Institute of Electrical Communication, Tohoku University, Sendal 980, Japan. Takashi Matsuura, Hiroaki Uetake,* and Tadahiro Ohmi Department of Electronics, Faculty of Engineering, Tohoku University, Sendai 980, Japan. Low-temperature Si epitaxy without substrate heating has been realized for the first time by Ar plasma-enhanced decomposition of SiH4 using an ultraclean ECR system. From Ar plasma pre-exposure experiments, it is concluded that ion energies lower than a few eV are favorable for epitaxy, in order to avoid plasma damages on the surface crystallinity. Furthermore, it is found that addition of H2 to the Ar plasma Is very effective to achieve St surface cleaning at very low temperatures. INTRODUCTION There have been sustained efforts to lower the Si epitaxial temperature for future ULSI. Although Si epitaxy at a deposition temperature as low as 1200C was performed by MBE, the sample was heated up to 12000C before deposition in order to obtain a clean surface[l]. Plasma enhancement can be used as an alternative to thermal reaction at low temperatures. Si epitaxial growth at temperatures of 2300C and 150 0 C was reported by a conventional plasma CVD method [2] and by a remote plasma-enhanced CVD method[13], respectively. However, so far, substrate heating by an electrical heater, etc., has been necessary to achieve Si epitaxy. In plasma processing for epitaxy, the condition of plasma (ex. energy of ions) must be optimized in order to suppress damage, because the quality of the deposited films depends on damage and the thermal recovery of damage is less at lower temperatures. Since energy of ions In the ECR system is comparatively low[4], ECR plasma processing is considered to be of great advantage to low temperature Si epitaxy. In the present work, low-temperature Si epitaxy without substrate heating has been realized for the first time by the ultraclean ECR plasma processing. Furthermore, effects of plasma damage and surface cleaning on epitaxy are investigated by plasma pre-exposure without substrate heating. +On leave from Alps Electric Co., Ltd., Furukawa, Miyagi 989-61, Japan *On leave from Seiko Instruments Inc., Matsudo, Chiba 271, Japan #To whom all correspondence should be addressed.
834
LuLtra
clean gas supply system I supply
:
transfer ,, chmberl
Fig. 1. Schematic diagram of ultraclean ECR plasma apparatus. SIl 4 gas was introduced into the deposition chamber. Ar and H2 gases were introduced into the plasma generating chamber.
EXPERIMENTAL The ultraclean ECR plasma apparatus used Is schematically shown turbo molecular pump (TMP) system was An oil-free in Fig. 1 [51. Torr was obtained. employed, and an ultimate vacuum of about 5xlO Si0 4 gas was supplied Into the deposition chamber, which was separated from the plasma generating chamber by a plate with a 100 mmo window. Ar and H2 gases were introduced into the plasma generating chamber. Plasma is carried to the wafer by a divergent magnetic field without s deposition conditions we chose using an ion extraction electrode. Torr, Ar pressure of 6 mTorr. an SIH4 partial pressure of 3x10 microwave (2.45 GHz) power of 700 W, and a deposition time of 40 minutes. The wafer susceptor was not heated at all, and the wafer was forced to the susceptor by an electrostatic chuck system under an electrically floating condition. To investigate the effects of plasma structure of deposited films, substrates were pre-exposure on the exposed to a pure Ar plasma and an Ar plasma with 10% H2 addition, just before the deposition of the films. 835
The substrates used were p-type Si wafers of 3-8 ohm-cm with mirror-polished (100) surfaces and with patterned thermal SiO2 films. The samples were cleaned in several cycles in a 4:1 solution of H2 SO4 and H20 2 , high-purity DI water, and 1% HF just before loading to the ECR amber. To investigate the surface cleaning by plasma preexposure, the samples were also treated in an H2 S0 4 -H2 0 2 solution to form a native oxide layer. The deposited film thickness was measured by a Tencor Alpha Step with a partial removal of the deposited films by chemical etching. The structure of the film surface was evaluated by electron diffraction. RESULTS AND DISCUSSION Si films were deposited nonselectively both on Si and SiO2 by the ultraclean ECR-plasma-enhanced CVD. Figure 2 shows typical electron diffraction patterns of the films deposited on Si and S1O 2 without plasma pre-exposure. The pattern of the film on Si shows Laue reflection spots which Indicate single crystallinity, whereas the pattern on S10 2 shows halo which indicates an amorphous film. Here, it should be noted that, without substrate heating, the temperature of the SI surface was 25 0 C at least just before the deposition, and the temperature was elevated up to approximately 200 0 C after 5 minutes of deposition, which was estimated by I-V characteristics of p-n diodes formed previously on the wafer surface. The temperature measurement method will be reported elsewhere. Since the optimum Ion energy for low-temperature Si epitaxy should exist, at which plasma damage Is minimized[6], the effects of plasma damage on the crystallinity of the deposited film were examined by Ar plasma pre-exposure. The results are shown in Fig. 3, where Ar
(a)
(b)
Fig. 2. Electron diffraction patterns for Si films deposited on (a) Si and (b) Si0 2 without plasma preexposure. Deposited film thickness was about 600 A. 836
(1))
(C)
kuj
Fig. 3. Electron diffraction patterns for Si films deposited after the pre-exposure of the sample for 150 seconds to Ar plasmas with a pressure of (a) 0.2 mTorr, (b) 2 mTorr, (c) 6 mTorr, and (d) 20 mTorr, and a microwave power of 700W.
pressure is varied to change the ion energy at pre-exposure under the For the higher Ar pressure (2-20 mTorr), same deposition condition. epitaxial growth is observed, whereas for a lower pressure(0.2 mTorr), amorphous film growth is observed. It is known that the typical peak energy of ions in the ECR system is a few 10 eV at 0.2 mTorr, and lower than a few eV at pressures higher than 2 mTorr[7]. Therefore, it is considered that high energy ion bombardment onto Si at 0.2 mTorr (of about a few 10 eV) causes damage of the surface crystallinity, whereas low energy ion bombardment at higher pressures (about a few eV) causes so little damage that epitaxial films can be grown on the substrate without heating. It was reported that epitaxial growth was 0 observed at a temperature as high as 630 C when a high ion energy condition at about 0.2 mTorr was chosen[8]. This shows that the thermal recovery of damage is more effective at higher temperatures. 837
ta)
ku/
Fig. 4. Electron diffraction patterns for SI films deposited on the substrates with native oxides after the pre-exposure of the sample for 15 seconds to (a) a pure Ar plasma and (b) a 10 % addition of H2 to the Ar plasma with a total pressure of 6 mTorr and a microwave power of 300W.
On the other hand, it is necessary for low temperature epitaxy that energy of ions is lowered down to a comparable order of magnitude to the bond energy (the SI-Si bond energy in bulk Si is 2.4 eV). Effective surface cleaning by plasma was investigated using the samples with a native oxide layer formed intentionally on the surface. The electron diffraction patterns of the deposited films pre-exposed to pure and H2 added Ar plasmas for 15 seconds are compared in Fig. 4. Although halo patterns are obtained by pure Ar plasma pre-exposure, epitaxial film growth is observed by pre-exposure to an Ar plasma with H2 addition. Similar patterns for the both conditions were obtained for the films deposited after the pre-exposure for a time as long as 150 seconds. Thus, the halo patterns for pure Ar plasma preexposure indicate, not the effects of damage, but an insufficient ability to remove a native oxide layer. On the other hand, hydrogen addition Is very effective to clean the surface, even in the presence of a native oxide layer. Figure 5 shows the cleaning pressure dependence of the crystallinity of the deposited films. Cleaning by Ar+IOH 2 plasma at the optimum pressure in the range of 2 and 6 mTorr for 15 seconds is sufficient to remove the native oxide and to obtain epitaxial growth. Amorphous and amorphous/polycrystal-like patterns are observed at 0.2 and 20 mTorr, respectively, which indicates Insufficient cleaning. SI surface cleaning by ECR H2 plasma for GaAs heteroepitaxy has been reported[9]. However, the typical cleaning condition was different, 0 that is, a cleaning temperature of 400 C, a gas pressure of 0.2 mTorr, and a cleaning time of 20-30 minutes. The present results show that a
838
(a)
tUI
1,,
k )i
kv I
Fig. 5. Electron diffraction patterns for SI films deposited on the substrates with native oxides after the pre-exposure of the sample for 15 seconds with a 10% addition of H2 to the Ar plasma at a total pressure of (a) 0.2 mTorr, (b) 2 mTorr, (c) 6 mTorr, and (d) 20 mTorr, and a microwave power of 300W.
clean Si surface can be obtained by the ultraclean ECR plasma exposure at a much lower temperature, at a much higher pressure with a significantly lower ion energy, and a much shorter cleaning time. different results may be due to the different cleaning These temperature. CONCLUSIONS Low-temperature Si epitaxy without substrate heating was realized condition, by the under a low-ion-energy, i.e. damage-suppressing ultraclean ECR plasma enhanced decomposition of SIH4 . Exposure to an Ar plasma with H2 addition even for a short period, is extremely effective to achieve a clean Si surface at very low temperatures without substrate heating. 839
ACKNOWLEDGMENTS The authors would like to thank Prof. N. Mikoshiba for encouragements throughout this study. They also thank T. Iawashima and Y. Yamashita, Seiko Instruments Inc., for manufacturing the ultraclean ECR apparatus, and S. Matsuo, NTT, for valuable advice about apparatus. This study was carried out in the Superclean Room of the Laboratory for Microelectronics, Research Institute of Electrical Communication, Tohoku University. REFERENCES [1] Y. Shlraki, Y. Katayama, K. L. I. Kobayashi, and K. F. Komatsubara, J. Crystal Growth, 45, 287 (1978). [2] T. Uematsu, S. Matsubara, M. Kondo, M. Tamura, and T. Saitoh, Jpn. J. Apple. Phys. 27, L493 (1988). [31 L. Breaux, B. Anthony, T. Hsu, S. Banerjee, and A. Tasch, Appl. Phys. Lett. 55, 1885 (1989). [4] S. Matsuo and M. Kiuchi, The Electrochemical Society, Fall Meeting, Detroit, Abs. 148, p233 (1982). [51 T. Matsuura, H. Uetake, T. Ohmi, J. Murota, K. Fukuda, N. Mikoshiba, T. Kawashima, and Y. Yamashita, Appl. Phys. Lett. 56, 1339 (1990). [6] T. Ohmi, T. Ichikawa, T. Shibata, K. Matsudo, and H. Iwabuchi, Appl. Phys. Lett. 53, 45 (1988). [71 K. Nishioka, N. Fujiwara, M, Yoneda, and T. Kato, Microelectronic Engin., 9, 481 (1989). [8] I. Nagai, T. Takahagi, A. Ishitani, H. Kuroda, and M. Yoshikawa, J. Appl. Phys. 64, 5183 (1988). (9] T. Shibata, Y. Nanishi, and M. Fujimoto, Jpn. J. Appl. Phys. 29, L1181 (1990).
840
LPCVD OF SILICON DIOXIDE BELOW 500 0C BY PYROLYSIS OF DIETHYLSILANE IN OXYGEN:
A SAFE ALTERNATIVE TO SILANE James D. Patterson and Mehmet C. Oztiurk North Carolina State University Department of Electrical Engineering, Box 7911, Raleigh NC 27695 Low pressure chemical vapor deposition (LPCVD) of Si0 2 in a horizontal LPCVD furnace using liquid diethylsilane and oxygen was studied. In this study, the driving force was to test the diethylsilane as a safe alternative to the pyrophoric silane in depositing silicon dioxide films at low temperatures. A temperature deposition window ranging from 425500'C was observed resulting in a maximum deposition rate of -275A/min. Electrical and structural characterizations of the films were performed before and after annealing the films in a cold-wall rapid thermal annealing (RTA) system in Ar, N2, and 02 ambients. Effects of the RTA conditions on the stoichiometry, etch rate, index of refraction, current conduction, fixed charge density, breakdown, and mobile ion density were determined. The results indicate that the oxides are high in quality suitable for microelectronics applications. INTRODUCTION Thermally grown SiO 2 is successfully used in silicon based integrated circuit technologies. When the high growth temperatures and consumption of silicon can not be tolerated, SiO2 is deposited by conventional low pressure chemical vapor deposition (LPCVD) techniques. A process which is widely used by industry is the silane VLTO (Very Low Temperature Oxide) reaction which utilizes the pyrolysis of SiH 4 in 02 [1]. The primary advantage of this process is its low temperature deposition window (350450'C). However, these oxides have traditionally yielded poorer electrical properties and conformality in comparison with thermally grown oxides[2,3]. The conformality of these oxides are typically worse than thermally grown oxides and high temperature deposited oxides (4]. In addition, SiH4 is pyrophoric and thus is a potentially explosive gas which requires expensive equipment to meet safety standards. The problems associated with the silane VLTO process has motivated the investigation of other silicon containing sources. Another commonly used low temperature SiO2 deposition source is the liquid source, TEOS (tetraethylorthosilicate) which deposits by pyrolytic decomposition[5-1 1). TEOS has been shown to yield better properties [6-9) than silane VLTO oxides, but the threshold deposition temperature (650'C) for this process is higher, and is beyond the melting point of aluminum. Since aluminum is the most widely used device interconnect material, this is a major disadvantage. Furthermore, successful control of the delivery of the TEOS vapor requires the use of heated mass flow controllers to avoid TEOS condensation on the cold surfaces [12]. Recently, a new SiO2 low temperature LPCVD process has been suggested that yields both, a deposition temperature window (425-500'C) below the melting point of aluminum 841
and good conformality[7,13]. This process involves the thermal decomposition of diethylsilane in oxygen. It has been proposed that the diethylsilane oxygen reaction proceeds as follows [14]: CH3 CH 2SiH 2 CH 2CH 3 + 202 -- SiO 2 + 2CH2 = CH 2 + 2H 2 0 Diethylsilane is a liquid source which is nonpyrophoric and noncorrosive. Delivery rate of the diethylsilane can be controlled by a conventional unheated mass flow controller because of its high vapor pressure at room temperature (200 Torr at 21'C) [13]. In this work, we have studied the process, electrical and structural properties of SiO 2 films deposited using diethylsilane. This work includes the study of both as-deposited and rapid thermal annealed films. The structural properties studied include deposition rates, across wafer uniformity, etch rates, stoichiometry, and conformality. The electrical properties studied were catastrophic breakdown field, current conduction mechanisms, fixed charge density, and mobile ion density. EXPERIMENTAL Depositions were carried out in a 3 zone Thermco RangerTM LPCVD furnace. The system consists of a hot wall resistance heated quartz reaction tube with a 4.5" inner diameter. A rotary vane vacuum pump was used to evacuate the system. Pressure was monitored with a capacitance manometer. Pumping speed was controlled with a feedback controlled throttle valve. The gas delivery system consisted of a liquid diethylsilane source bottle contained in a thermoelectric temperature controlled bubbler (Schumacher Model STC 115); a carrier gas for the diethylsilane was unnecessary since diethylsilane has a high vapor pressure. The flow rates of diethylsilane and purging nitrogen were controlled by the same N 2 calibrated Tylan FC260 mass flow controller. A diethylsilane flow conversion factor of 0. 17 was used [ 15]. The diethylsilane and oxygen were delivered to injectors at the door of the quartz tube via separate lines to avoid the possibility of reactions occuring in the lines. Source temperature was set to 23°C for all depositions in this study. To completely eliminate condensation of diethylsilane in the delivery lines, all lines were wrapped with heat tape and were kept slightly above the source temperature. Deposition rate was determined as a function of both temperature and pressure. Preceding all depositions, a standard RCA clean was carried out. In all experiments 4" silicon, prime grade, p-type, (100) orientation wafers were used as the oxide substrate. All depositions were performed with a flat zone furnace temperature profile. The deposition rate was determined by averaging oxide thicknesses over a 25 wafer boat. Depositions were carried out using both a caged boat and an open boat. A fixed deposition time of 15 minutes was used. Wafer spacing in the boat was kept at 1 cm and boat position was maintained at 24 inches downstream. We have found that wafer spacing and boat position affects the deposition rate greatly and must be kept constant to determine valid trends. Flow rates which gave stoichiometric SiO2 and minimized depletion effects were determined to be 100 sccm diethylsilane and 200 sccm oxygen. These gas flows were used in all studies and were suggested by J.C. Schumacher Co.[13,15]. Film thicknesses were determined with a Rudolph Research/Auto EL II ENG350 ellipsometer and a Nanometrics Nanospec/AFT Model 010-0180 film thickness gauge.
842
For the electrical characterization, MOS (metal oxide semiconductor) capacitors were prepared using 500±20A thick films. The capacitors were fabricated on as-deposited and rapid thermal annealed diethylsilane deposited SiO 2 films. Silicon, prime grade, p-type, 0.2-0.5 Q-cm, (100) orientation wafers were used as the substrate. Rapid thermal anneals were done in an AG Associates HeatpulseTM Model 210 rapid thermal annealer at atmospheric pressure for 15 seconds in Ar, N 2 , or 02 ambients at temperatures ranging from 950-11 000 C. Aluminum was evaporated onto the wafers for the gate material and patterned by photolithography and wet etching. All wafers were subjected to a 400'C forming gas anneal in H 2 for 30 minutes following capacitor fabrication. MOS capacitors fabricated with Si02 dielectrics grown by thermal oxidation in a dry 02 ambient at a temperature of 950'C using 4.5%HCl were fabricated for comparison. RESULTS Process and Structural Characterization The temperature dependance of the deposition rate is shown in Figure 1 which indicates a process window of 425-500'C. The lower deposition rates toward lower temperatures for the uncovered boat relative to the caged boat is believed to be due to lower residence time, i.e. the threshold thermal budget requirements for deposition is reached at higher temperatures for the uncovered boat case, possibly because the caged boat stagnates the reactants giving a longer residence time. Maximas in deposition rate are reached in the neighborhood of 475'C: 275A/min and 180A/min for the uncovered and caged boats respectively. As the deposition temperature increases from the maximas, the deposition rates decrease for both the uncovered and caged boats. This is believed to be due to an increased number of homogeneous gas phase reactions, i.e. at higher temperatures the creation of SiO2 particulates in the gas phase decreases the amount of reactants reaching the wafers. This is clearly evident at deposition temperatures above 500'C in which domination of homogeneous reactions results in copious amounts of SiO 2 particulates and no deposition on the wafers. The significant increased creation of the Si02 particulates above the maximum deposition rate suggest that depositions should be carried below the corresponding temperatures to yield the best quality oxides. The creation of the SiO 2 particles in the gas phase is also exhibited in the Sill4 VLTO [1,161 and TEOS[8] deposition processes. Across wafer uniformities were better for the caged boat case (±5% and ±8%for the caged boat and uncovered boat respectively at a deposition pressure of 750mTorr). A temperature dependance on the across wafer uniformity was not observed. The pressure dependance of the deposition rate at a temperature of 450'C was also studied. The results indicated a linear dependance of the deposition rate on pressure. A pressure window of 550-95OmTorr was obtained. Below 550 mTorr, deposition did not occur after 15 minutes of deposition time. Above 950 mTorr ignition of the reactants in the gas phase occurred creating copious amounts of SiO 2 particulates. Thus the implementation of a feedback controlled throttle valve was necessary to avoid "accidental" surpassing of the pressure threshold for homogeneous gas phase reactions. The index of refraction was evaluated using ellipsometry at a wavelength of 6328A. Values of the index of refraction for an as-deposited oxide (1.449_+0.001) were lower than a thermal oxide (1.462). However, RTA resulted in an increase of the index of refraction that approached a maximum of 1.459 at 1100°C in all three ambients. This behavior is expected, since the index of refraction generally increases with film density. 843
P
°u Cu
Deposition Temperature (°C) Figure 1 The deposition rate of SiO2 as a function of temperature using a caged boat and an uncovered boat: deposition pressure = 750mTorr. Etch rates of the oxides in 10% buffered oxide etch (10 parts 40% aqueous NH 4 F, 1 part 49% aqueous HF) and a 1%HF solution (1% HF by volume in deionized water) at room temperature for as-deposited and annealed samples were studied. Results for each condition are stated as averages for 10 trials. In Figure 2, wet etch rates are shown for oxides deposited at 450'C following 15 second RTAs in Ar, N 2 , and 02. Increased annealing temperature in all ambients resulted in a reduction of the etch rate, This is indicative of a densification of the deposited oxide. Ellipsometric thickness measurements showed this to be the case for the Ar and N2 anneals since a decrease in film thickness of 4% was observed. An increase in film thickness of 2% was observed for the 02 anneals indicating growth of a thermal oxide at the interface. Note that the etch rates following RTA are comparable to that of the thermal oxide and the anneals in 02 yielded the lowest etch rates. In addition, to the wet etching experiments, the etch rate of the oxides in a reactive ion etching (RIE) system is being studied using CHF 3 and 10% oxygen. This gas mixture is typically used for etching with high selectivity to Si0 2 over Si [17]. An Ion and Plasma Equipment Model 100OTP RIE system was used. The CHF3 and 02 flow rates were 20 and 2 sccm respectively. The power density used was 0.15W/cm 2 and the pressure was 50mTorr. The measurements gave an etch rate of 80 ±5 A/min for as-deposited oxides which was comparable to the etch rate of a thermally grown oxide used for comparison. The stoichiometry of the deposited oxides (425-500'C) has been evaluated by Rutherford Back Scattering (RBS). The results showed that the oxides deposited at 425'C 844
and 450 0 C were stoichiometric SiO 2. Deposition temperatures of 475 and 500"C resulted in depletion of oxygen in the films yielding a composition of SiO1. 8 5. 100
argon
-
10:1 BOE
nitrogen
-
as-deposited
""0
-
oxygen
Thermal Oxide 10 0 <- as-deposited
I Thermal Oxide
-0-------
argon
-0---C-
nitrogen.
1% HF
.1'
850
I,
900
oxygen
& i
950
1000
1050
1100
RTA Temperature (°C) Figure 2 Wet etch rates in 10:1 BOE and 1% HF before and after RTA (deposition temperature = 450'C, deposition pressure = 750 mTorr, RTA time = 15 s) A sidewall to top wall conformality of -80% was obtained when a 6000 A SiO 2 film was deposited over a 2g.tm deep Iýtm wide silicon trench. This could be possibly improved by decreasing the deposition pressure in the reaction chamber which should lead to a longer mean free path for the reactants and less depletion of reactants toward the bottom of the well. It should be noted that this conformality is superior to the 50-70% conformality of oxides deposited with the Silane VLTO process[4]and comparable to the conformality of TEOS oxides (-90%)[6-91. Electrical Characterization To determine breakdown voltages, leakage currents, and conduction mechanisms of the oxides, current-voltage and current-temperature data were taken. A Keithley Model 617 Electrometer, Keithley Model 230 voltmeter, and Temptronic Model TPO315A-1 temperature controller were used for the analysis. To determine repeatabilities, 10 curves for each annealing condition were taken and averaged.
845
Temperature (°C) 150
25
100
U-
10-6
Themial Oxide Z
10-8
in-
9
2.2
Electric Field = 7 MV/cm RTA : 100 'C1 10 s 2.4
2.6
2.8
RTA in 02
3.0
3.2
3.4
3.6
1000/T(K) Figure 3 Leakage current dependance on temperature for SiO2 deposited with diethylsilane for as-deposited and rapid thermal annealed samples (deposition temperature = 450'C, deposition pressure = 750 mTorr, RTA time = 15 s). Current conduction in insulators obeys one of three transport mechanisms : FowlerNordheim, Frenkel-Poole or Hopping [18]. Generally, deposited films have a large density of trap states and as a result of this, Frenkel-Poole conduction usually dominates the I-V characteristics. If this is the case a plot of ln(J) versus 4E yields a linear dependance. Likewise, if Fowler-Nordheim conduction dominates, a plot of JIE 2 versus 1/E yields a linear plot. Typically the IV data is plotted in both the Fowler-Nordheim and Frenkel-Poole plots and the plot that gives a linear dependance reveals the dominant conduction mechanism. In our case, both plots were equally linear for the electric field range studied; this was also verified to be the case with theoretical plots. Thus, a current-temperature plot will yield more valuable information, since Fowler-Nordheim mechanism is temperature independent and therefore any structure in the plot shows the presence of trap conduction. Figure 3 shows the temperature dependance of the leakage currents of the films with a 7MV/cm applied electric field. As expected, the thermal oxide does not exhibit any temperature dependance which is indicative of Fowler-Nordheim conduction. The asdeposited and N2 annealed samples indicated significant temperature dependance suggesting Frenkel-Poole and Hopping conduction as the dominant mechanisms. The lowest leakage currents and the most similar behavior to the thermal oxide are achieved when deposition is followed by a RTA in either Ar or 02; this indicates that annealing in 846
these ambients results in a reduction of the trap density in the oxide. It should be noted, however that a slight temperature dependance remains which is indicative of a FrenkelPoole or Hopping component of the leakage current. I L.U
.
11.5
"11.0 10.5
""
10.0
S9.5 9.0
RTA Temperature (CC) Figure 4 Catastrophic breakdown electric fields for as-deposited and rapid thermal annealed films (deposition temperature = 450'C, deposition pressure = 750mTorr, RTA time = 15 sec). The catastrophic breakdown fields for the oxides are shown in Figure 4 for asdeposited and annealed films. Ten measurements of the breakdown fields per each annealing condition were taken. Averages and error bars of one standard deviation are shown. Ar and N2 anneals yielded breakdown fields of -10.5MV/cm. Oxygen anneals gave slightly lower breakdown fields which were still comparable to the thermal oxide. The breakdown field obtained for the as-deposited oxide is -9.5MV/cm which is better than that typically observed for Silane VLTO and comparable to TEOS. Reported values for the breakdown fields of as deposited SiH4 VLTO oxides are 3-8MV/cm [1,8,19]and those for TEOS oxides are -3-lOMV/cm[6,8,19,20]. The density of charge defects which affect reliability and yield were studied . These were fixed charge, oxide trapped charge, and mobile ions. High frequency CV (capacitance voltage) analysis was performed at 1MHz on the MOS capacitors to determine the density of these defects. A Princeton Applied Research Model 410 CV Plotter and Temptronic TP36 CV Plot Thermochuck were used for the CV analysis. Figure 5 shows the fixed charge (Qf) for both as-deposited and rapid thermal annealed films. As shown, the as-deposited oxide has an order of magnitude higher fixed charge in comparison with the thermal oxide. An increase in RTA temperature for the Ar and N2 anneals is shown to be associated with a decrease in Qf. Anneals in Ar and N2 at I 100°C
847
yield the lowest Qf (6X1010/cm 2 ). On the other hand, anneals in an 02 ambient yield higher fixed charge with no dependance on annealing temperature. This may be due to 02 anneals causing the films to be oxygen rich which may in turn increase the number of unsaturated bonds. Retraces for all high frequency CV curves were done to determine the existence of oxide trapped charges. Hysteresis was not observed in any of the CV curves indicating a low density of oxide trapped charges.
Argon
--
UNitrogen
As-Deposited
/
S1012
•
Oxygen
10
Q, 102 [ -4--Thermal Oxide
1010
900
950
1000
1050
1100
1150
RTA Temperature (MC) Figure 5 Fixed charge density for SiO2 deposited with the diethylsilane oxygen reaction for various RTA ambients and temperatures (deposition temperature = 450'C, deposition pressure = 750mTorr, RTA time = 15 sec). A high frequency CV temperature-bias stress test was performed on the deposited oxides following MOS capacitor fabrication to determine mobile ionic charge density. The mobile ionic charge was calculated by determining the flat band voltage shift from high frequency CV curves generated following a 2001C temperature stress at both positive and negative 5 volt bias. The ionic charge in the diethylsilane oxides was determined to be .54X1010 /cm-2 . This shows excellent purity of the diethylsilane source as well as process cleanliness. CONCLUSIONS Deposition of stoichiometric SiO 2 by the pyrolysis of diethylsilane in oxygen using a LPCVD furnace has been demonstrated. The deposition temperature window for this reaction was determined to be 425-500"C which yields a maximum deposition rate of
848
275A•min. Excessive SiO2 particulate generation for this reaction was noted at pressures greater than 950mTorr for a deposition temperature of 450'C. Best case across wafer uniformities were shown to be ±5%. Wet etch rates of the oxides in 10% BOE, 1%HF, and RIE etch rates in CHF 3 + 10% 02 were comparable to etch rates of a thermal oxide control sample. The oxides were determined by RBS to be stoichiometric SiO 2 for deposition temperatures 5.450'C. Preliminary results from an experimental matrix studying the conformality of the oxides has shown that the diethylsilane oxides yield good conformality. The effects of RTA temperature on the electrical properties have been determined for anneals in Ar, N 2 , and 02 ambients. The results have shown that the leakage current density of the as-deposited oxides is higher than that of a thermal oxide at high temperatures and fields, and is due to defect conduction mechanisms. If deposition is followed by a RTA in Ar or 02 ambient, the leakage current becomes comparable to a thermal oxide and follows the Fowler-Nordheim conduction mechanism. Catastrophic breakdown fields of the as-deposited and annealed oxides were shown to be high and comparable to a thermal oxide. The order of breakdown strength relative to RTA ambient was: Ar-N 2>0 2 . Our results have shown that as-deposited oxides yield high fixed charge densities (1012 cm- 2 ) in comparison with thermal oxides (-1010/cm 2 ). However, if deposition is followed by a high temperature RTA in Ar or N2 a fixed charge density as low as 6X10 10 cm-2 can be obtained that are comparable to a thermal oxide. Hysteresis in the CV curves of the oxides were not observed indicating the absence of a high concentration of oxide traps. The mobile ionic charge in the oxides was determined to be <4Xl0 10/cm 2 which indicates high purity of the source material. In summary, based on the electrical properties of the oxides used in this study, an Ar RTA ambient appears to yield best overall electrical properties. These properties were shown to improve with increasing RTA temperature. ACKNOWLEDGEMENTS This work has been partially supported by the NSF Engineering Research Centers Program through the Center for Advanced Electronic Materials Processing (Grant CDR8721505) and SRC Manufacturing Sciences Program (Grant 90-MP-132). The authors are grateful to IC. Schumacher Co. for their contribution of the diethylsilane source material used in this study.
1. 2. 3. 4. 5.
REFERENCES N. Goldsmith and W. Kern, "The Deposition of Vitreous Silicon Dioxide Films From Silane", RCA Rev., p. 153, 1967. E. H. Nicollian and J. R. Brews, Deposited Silicon Dioxide, (John Wiley & Sons, New York, 1982), p. 743 C. Cobianu and C. Pavelescu, "D.C. Dielectric Breakdown in Si02 Films Prepared by Low Temperature Chemical Vapor Deposition", Thin Solid Films, vol. 143, p. 109, 1986. R. M. Levin and K. Evans-Lutterodt, "The Step Coverage of Undoped and Phosphorus-Doped SiO2 Glass Films", J. Vac. Sci. Technol. B, vol. 1, p. 54, 1983. A. Cuccia, G. Shrank, and G. Queirolo, "Semiconductor Silicon", in Proceedings of The Electrochemical Society Meeting, p. 506, 1969
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6.
7. 8.
9.
10.
11.
12. 13. 14. 15. 16. 16. 17.
18. 19. 20.
F. S. Becker, D. Pawlik, H. Schafer, and G. Staudigl, "Process and Film Characterization of Low Pressure Tetraethylorthosilicate Borophosphosilicate Glass", J. Vacuum Sci. Technol. B, vol. 4, p. 732, 1986. B. Gelernt, "Selecting An Organosilicon Source For LPCVD Oxide", Semicon. Intemat., vol. 3, p. 82, 1990. F. S. Becker, D. Pawlik, H. Anzinger, and A. Spitzer, "Low-Pressure Deposition of High Quality Silicon Dioxide Films By Pyrolysis of Tetraethylorthosilicate", J. Vacuum. Sci. Technol. B, vol. 5, p. 1555, 1987. A. Borghesi, B. Pivac, A. Sassella, S. Rojas, A. Modelli, and W. S. Wu, "Influence of Deposition Parameters on Fundamental Properties of Si02 Films Prepared by LPCVD From a Tetraethylorthosilicate Source", ICEM 1990 Proceedings, to be published, 1990. A. C. Adams and C. D. Capio, "The Deposition of Silicon Dioxide Films at Reduced Pressure", J. Electrochem. Soc.: Solid State Science and Technology, vol. 126, p. 1042, 1979. R. Miller, M. C. Ozturk, J. J. Wortman, F. S. Johnson, and D. T. Grider, "LPCVD of Silicon Dioxide By Pyrolysis Of TEOS In A Rapid Thermal Processor", Mat. Lett., vol. 8, p. 353, 1989. D. J. Ferran, PracticalConsiderations in the Delivery of Low PressureMaterialsto Reduced PressureProcesses.Vacuum General: Precision Instrumentation A. K. Hochberg and D. L. O'Meara, "The LPCVD Of Silicon Oxide Films Below 400'C From Liquid Sources", J. Electrochem. Soc., vol. 136, p. 1843, 1989. D. O'Meara, Discussion of Diethylsilane Oxygen Reaction. 1989, J.C. Schumacher Co. A. K. Hochberg and D. L. O'Meara, User's Guide For: Glass Deposition With LTO410 Source Material. 1990, J.C. Schumacher Co: E. H. Nicollian and J. R. Brews, Combined High-Low Frequency Capacitance Method, (John Wiley & Sons, 1982), p. 331 W. Kern and R. S. Rosier, "Advances in Deposition Processes for Passivation Films", J. Vac. Sci. Technol., vol. 14, p. 1082, 1977. L. M. Ephrath, "Selective Etching of Silicon Dioxide Using Reactive Ion Etching with CF4H2", J. Electrochem. Soc.:Solid State Science and Technology, vol. 126, p. 1419, 1979. S. M. Sze, "Current Transport and Maximum Dielectric Strength of Silicon Nitride Films", J. Apple. Phys., vol. 38, p. 2951, 1967. A. C. Adams, Dielecttic and Polysilicon Film Deposition, 2nd Ed., (McGraw-Hill, New York, 1988), p. 259 E. B. Gorokhov, E. A. Dem'yanov, I. G. Neizvestnyi, and I. G. Pokrovskaya, "Preparation of Uniform SiO2 Films by Pyrolysis of Tetraethoxysilane", Izvestiya Akademmii Nauk SSSR, Neorganicheskie, vol. 12, p. 270, 1976.
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OPTIMIZATION OF PROCESS CONDITIONS FOR SELECTIVE DEPOSITION OF POLYCRYSTALLINE SixGel.x ALLOYS IN A RAPID THERMAL PROCESSOR* M. Sanganeria*, M.C. Oztiurk*, G. Harris**, D. M. Maher**, D. Batchelor** J. J. Wortman*, B. Zhang** and Y. L. Zhong*. *North Carolina State University Department of Electrical and Computer Engineering Box 7911, Raleigh, NC 27695-7911
"**NorthCarolina State University Department of Materials Science and Engineering Box 7907, Raleigh, NC 27695-7907 ABSTRACT Polycrystalline SixGel-x alloys were deposited by rapid thermal chemical vapor deposition (RTCVD) using the reactive gases GeH4 and SiH 2 C12 in a H2 carrier gas. The depositions were performed at a total pressure of 2.5 Torr and at temperatures between 500'C and 800°C using GeH4 :SiH 2 C12 flow ratios ranging from 0.025 to 1.00. The effects of the deposition temperature and the flow ratio of the reactive gases on the surface morphology and deposition selectivity were studied by Auger Electron Spectroscopy (AES), Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM). The results showed that the deposition selectivity was a strong function of the amount of GeH 4 in the gas stream. Selective depositions were obtained for GeH4:SiH2C12 flow ratios greater than 0.2, irrespective of the deposition temperature. It was also shown that three dimensional growth could be eliminated by depositing below a critical temperature determined by the Ge content in the alloy. It is shown that the critical temperature for transition from two dimensional to three dimensional growth decreases as the germanium concentration in the film increases.
*
This work has been partially supported by NSF Engineering Research Centers Program through the Center for Advanced Materials Processing (Contract # CDR-8721505) and SRC Microstructures Sciences Program (Grant 90-$1-081).
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INTRODUCTION There has been a growing interest in epitaxial SixGel-x alloys since they have the potential of improving the performance of existing devices and possibly leading to new device structures through bandgap engineering. Recently, polycrystalline SixGel-x has been recognized as a diffusion source for the formation of ultra-shallow junctions in Si [1][2]. In these studies, the junctions were formed by drive-in of dopants into the silicon substrate from an implanted polycrystalline SixGel-x layer selectively deposited by rapid thermal chemical vapor deposition (RTCVD). In the present work, an attempt has been made to optimize the deposition parameters for the growth of selective and smooth polycrystalline SixGel-x alloys on Si. RTCVD, which is a variant of low pressure chemical vapor deposition (LPCVD), makes use of rapid changes in the process temperature to initiate and terminate chemical reactions instead of gas flows as in conventional LPCVD furnaces. Tho technique allows deposition of extremely thin layers with abrupt interfaces once only possible by molecular beam epitaxy (MBE). Also referred to as limited reaction processing (LRP), RTCVD is a promising technique for future single wafer manufacturing technologies. As the devices shrink to submicron dimensions, selective area deposition is becoming increasingly attractive as it leads to elimination of photolithographic steps. Selective growth of SixGel-x on Si has been used as a means of reducing the misfit dislocation density at the heterointerface arising from the lattice mismatch between the two material systems [3]. We have reported selective deposition of polycrystalline SixGel-x alloys in a previous publication [4]. In this work it was found that selectivity was dependent upon the amount of GeH4 in the gas stream. However, as more GeH4 is added to the gas stream, the concentration of Ge in the alloy and thus the lattice mismatch between the alloy and the substrate increases, favoring a three dimensional growth. This results in a rough surface morphology. Three dimensional growth is expected to dominate when the interfacial energy between the alloy and the substrate is greater than the sum of the alloy/ambient and substrate/ambient surface energies [5]. Therefore, it is necessary to optimize the deposition conditions so that smooth SixGel-x can be deposited selectively. In this work, we have employed Scanning Electron Microscopy (SEM) and CrossSectional Transmission Electron Microscopy (TEM) to study the selectivity and surface morphology of alloys deposited on silicon. Germanium content of the films were determined by Auger Electron Spectroscopy (AES). EXPERIMENTAL SixGel-x alloy depositions were performed in a rapid thermal processor. A detailed description of the deposition system used in this work can be found elsewhere [6]. Depositions were performed on 20 ohm-cm, <100> silicon wafers. Selective growth of SixGel-x alloys was studied using windows defined by wet etching in a 2000A thick SiO2 layer grown by thermal oxidation. Prior to deposition, the wafers underwent an RCA clean followed by a 10 second buffered HF dip. The films were deposited using SiH 2 CI2 and GeH4 in a H 2 carrier gas at a total pressure of 2.5 torr. The GeH4 used in this study was premixed with hydrogen to a dilution of 7.8%. Flow rate of GeH4 was kept constant at 5 sccm and SiH 2 C12 flow rate was adjusted to obtain a desired flow ratio. The operating
852
pressure was maintained at 2.5 torr by adding hydrogen to the gas stream. The depositions were performed at temperatures between 500*C and 800*C using GeH4:SiH 2 Cl2 flow ratios ranging from 0.025 to 1.00. RESULTS Figure 1 shows the effect of the GeH 4 :SiH 2Cl 2 flow ratio on the germanium content of the alloys as determined by AES for deposition temperatures ranging from 5000 C to 800'C. As shown, the amount of germanium in the alloy is a function of both the GeH4:SiH 2 C12 flow ratio and the deposition temperature. For gas flow ratios less than 0.2, the Ge content in the alloy is a strong function of the gas flow ratio and rapidly diminishes with increasing SiH2 Cl2 in the gas stream. As the ratio is increased above 0.1, the germanium content gradually increases with increasing gas flow ratio. For the entire GeH 4 :SiH 2 CI 2 gas flow ratios used in this study, the Ge content of the films increased with decreasing deposition temperature. This is easily understood if one compares the temperature dependance of pure Ge and pure Si deposition on Si. Pure Ge can be deposited using GeH4 at rates as high as 700A/min at temperature lower than 450'C[7]. On the other hand Si deposition is considerably slower below 600'C. As the GeH-I4 flow in the gas stream approaches that of SiH2 C12 , the germanium content of the alloy becomes less sensitive to the deposition temperature.
0
Q
E 0
I 0.0
Figure 1
0.2
0.4 0.6 0.8 1.0 Germane: DCS flow ratio
1.2
The effect of the GeH4:SiH2C12 flow ratio on the Ge content at different deposition temperatures.
853
0 0
40.
u
4C5
0
PC?
°•
854
4 800 lU - I 0 A
Temperature0 ( C) 600 700 I
500
I
I
DCS:GeH4 ratio
flow A
010
103
o02 S+ o
102
A 1011
0.9
1.0
1.1 1.2 1000/T(K)
1.3
1.4
Figure 3
Temperature dependance of the deposition rate for different GeH4:SiH2C12 flow ratios. Deposition selectivity was examined by both AES and SEM. As shown in Figure 1 selective depositions were obtained with GeH4 :SiH2 C12 gas flow ratios greater than 0.2 for all deposition temperatures. Figure 2 shows the SEM micrographs of films deposited at 650°C with four different flow ratios of 0.025, 0.05, 0.1 and 0.2. As shown in Figure 2.a, the deposition is completely non-selective with a flow ratio of 0.025. When the flow ratio is raised to 0.05, partially selective deposition is obtained. Nucleation on SiO2 is initiated by the formation of discrete SixGel-x islands. At flow ratio of 0.1, traces of alloy are present on the oxide (Figure 2.c). However, when the ratio is raised to 0.2, there is no evidence of nucleation on SiO 2 . This clearly indicates the effect of GeH4 as a selectivity enhancing agent. A similar observation was made at other deposition temperatures; i.e., it was concluded that transition from selective to non-selective deposition occurs between flow ratios of 0.1 to 0.2, independent of the deposition temperature. It has been proposed [61 that the reason for improved selectivity can be attributed to the generation of the highly volatile GeO via the reactions GeH 4 -4 Ge + 2H 2 Ge + SiO2 -* GeO2 + Si GeO2 + Ge --* 2GeO This is believed to lead to a competition between SiO 2 etching and alloy deposition processes. At higher germanium concentrations, SiO 2 etching is more effective. 855
Figure 3 shows the temperature dependance of the deposition rate for four different GeH 4 :SiH2CI2 flow ratios of 0.1, 0.2, 0.5 and 1 at a total pressure of 2.5 torr. The data indicates an enhanced deposition rate due to addition of GeH4 to the gas stream. As an example, using a GeH 4 :SiH2C12 flow ratio of 0. 1, the deposition rate at 800 0 C was found to be equal to approximately 4400A/min. AES indicated that the percentage of Ge in the alloy was 17%. This corresponds to a pure silicon deposition rate of approximately 371OA/min. On the other hand, pure silicon deposition rate at the same pressure and temperature was found to be approximately 550A/min. This corresponds to a rate of increase of more than 7x with the addition of GeH4. This is in agreement with previous results [8][9]. Higher deposition rates are advantageous in single wafer manufacturing where throughput is a major concern. As is evidenced in Figure 2, while higher Ge concentrations can improve selectivity, increased lattice mismatch can lead to a rough surface morphology. Figure 4 shows cross-sectional TEM micrographs obtained from films deposited at 600 0 C, 650 0 C, 700'C, 750'C and 800'C. The gas flow ratios were adjusted using the results from Figure I to obtain a Ge concentration of 30% in all five films. As shown, the film deposited at 600'C (Figure 4.e) has a very smooth surface morphology. However, the surface becomes rougher when the deposition temperature is raised to 650'C and 700'C (Figures 4.d and 4.c). Macroscopic islanding is distinctly visible in Figures 4.b and 4.a which were obtained from films deposited at 750'C and 800'C respectively. It is believed that at lower temperatures the surface mobility of the depositing species is reduced considerably resulting in very small surface migration lengths. Islanding is thus avoided at lower temperatures. It was observed that the critical temperature for transition from twodimensional to three-dimensional growth decreases as the germanium content of the film increases. Smooth films of alloys containing up to 40% Ge could be deposited at 600'C whereas at a deposition temperature of 650'C alloys containing more than 30% Ge become rough. For the alloys deposited at the same temperature, the film with higher germanium content will have more pronounced three dimensional growth behavior. Figure 5 shows the cross-sectional TEM micrographs of SiO.75GeO.25 obtained from films deposited at 600'C, 750'C and 800'C. Comparison of Figures 4.a and 5.a illustrates the fact that islanding is more pronounced in the film containing 30% Ge (Figure 4.a) than in the film containing a lower Ge concentration of 25% (Figure 5.a). This leads to the conclusion that smooth films of SixGel-x alloys can be obtained by deposition under the critical temperature determined by the germanium content of the alloy. Bean et. al. [10] have investigated the deposition of SixGel.x alloys over compositions ranging from pure Ge to pure Si for a wide range of temperatures using MBE. Our results are in general agreement with this earlier work. In the cross-sectional TEM micrographs presented in Figures 4 and 5, it is interesting to note that depositions at high temperatures e.g. 750'C and 800'C result in almost hemispherical large grains epitaxially aligned to the silicon substrate. The size of these grains decreases as deposition temperature is decreased. The grain structure will play a significant role if polycrystalline SixGet-x is used as a diffusion source to form ultrashallow junctions in Si. For this application, it is desirable to have small columnar grains to facilitate uniform and fast diffusion of dopant species through the grain boundaries. Therefore, the epitaxial alignment obtained at high temperatures must be avoided. It should
856
ft
A
ii
e
Figure 4
Cross-sectional TEM micrographs of SiO.7GeO.3 films deposited at five 0 different temperatures; a) 800 0 C, b) 750 0 C, c) 700'C, d) 650'C and e) 600 C.
857
a
0.2pu.
b
C
Figure 5 Cross-sectional TEM micrographs of SiO.75Geo.25 films deposited at three different temperatures; a) 800'C, b) 750°C, and c) 600'C. also be noted that these temperatures lead to three dimensional growth and thus rough surface morphologies. Figure 6 illustrates a summary of results obtained from selectivity and surface roughness studies in this work. The data points in this figure represent the samples investigated for surface roughness using SEM and TEM. It is clear that selective deposition of smooth films can only be obtained below 6500 C with the conditions used in this study. As shown in Figure 3, the deposition rate below 600°C is less than looA/min
858
which may be a serious constrain for single manufacturing technologies. It should, however, be noted that these results are likely to be influenced by the deposition environment. Contaminants such as water vapor and/or oxygen may play a key role in altering this window of deposition parameters. Changes in the total pressure may also contribute to changes in the observed results. nAiA
SSelective Deposition 0
4) 2 Cu I.. 4)
800-
0
E 4)
0
700-
Rough Surface Morphology 0 .
Z. 0 U, 0
600-
4)
500
.1
0.0
Smooth Surface Morphology 0.2
0.4
0.6
0.8
1.0
Germane:DCS Flow Ratio Figure 6
Optimum deposition parameters for the deposition of smooth, selective
SixGel-x alloys. CONCLUSIONS In summary, we have shown that smooth polycrystalline SixGel-x alloys can be deposited selectively by optimizing the deposition parameters. Selectivity is increased as germane in the gas stream is increased. Smooth films of alloys can be obtained by depositing below a critical temperature determined by the Ge concentration in the alloy. The critical temperature decreases as the germanium content of the film is increased. ACKNOWLEDGEMENTS The authors would like to thank Joan O'Sullivan and Richard Kuehn of NCSU Microelectronics Laboratory for their assistance in sample preparation. REFERENCES 1.
M. C. OztUrk, Y. Zhong, D. T. Grider, M. Sanganeria, J. J. Wortman, and M. A. Littlejohn, Proceedings of the 1990 SPIE Technical Symposium on Rapid Thermal and Related Processing Techniques, San Jose, CA, to be published. 859
2.
D. T. Gider, M. C. Oztiirk, and J. J. Wortman, this proceedings.
3.
D. B. Noble, J. L. Hoyt, C. A. King, J. F. Gibbons, T. I. Kamins, and M. P. Scott, Applied Physics Letters, vol. 56, p. 51, 1989.
4.
Y. Zhong, M. C. OztUrk, D. T. Grider, J. J. Wortman, and M. A. Littlejohn, Applied Physics Letters, vol. 57, p. 2092, 1990.
5,
S. M. Sze, VLSI technolgy. New York: McGraw-Hill Book Company, 1988
6.
M. C. Oztiirk, D. T. Grider, J. J. Wortman, M. A. Littlejohn, and Y. Zhong, Journal of Electronic Materials, vol. 19, p. 1129, 1990.
7.
D. T. Grider, M. C. Oztiirk, J. J. Wortman, M. A. Littlejohn, Y. Zhong, D. Bathchelor, and P. Russell, MRS Symposia Proceedings , Vol. 158, p. 147, 1989
8.
P. M. Garone, J. C. Sturm, P. V. Schwartz, S. A. Schwartz, and B. Wilkens, MRS Symposia Proceedings, Vol. 146, p. 4, 1989
9.
C. A. King, J. L. Hoyt, D. B. Noble, C. M. Gronet, 3. F. Gibbons, M. P. Scott, S. S. Laderman, T. I. Kamins, and J. Turner, MRS Symposia Proceedings, Vol. 146, p. 71, 1989
10.
J. C. Bean, T. T. Sheng, L. C. Feldman, A. T. Fiory, and R. T. Lynch, Applied Physics Letters, vol. 44, p. 102, 1983.
860
UV ANNEALING PASSIVATION EFFECT CONTAMINATION ON SODIUM (Na÷) Manabu Itsumi, Hideo Yoshino, Satoshi Nakayama NTT LSI Laboratories, Atsugi-Shi, Kanagawa 243-01 Hideo Akiya and Susumu Muramoto LSI Fabrication Division NTT Electronics Technology Corporation, Atsugi-Shi, Kanagawa 243-01 The passivating effect of UV annealing on sodiumcontaminated MOS devices was studied. MOS devices were intentionally contaminated with sodium after gate electrode formation. Each wafer with fabricated MOS devices was subjected to ultraviolet light at 180 C at an atmospheric UV radiation intensity was 650 mW/cm2 and pressure. wavelength is 220-320 nm. Sodium-induced threshold voltage shifts of active or parasitic MOS transistors return to uncontaminated levels through the UV annealing process. It is assumed that sodium ions (positive) in the oxides are neutralized with electrons excited by UV light. This passivation effect is enhanced at temperatures above 150' C. These results suggest that sodium ion (or atom) diffusion in the oxides is closely associated with this passivation mechanism. dependent A model is presented for this temperature passivation effect. INTRODUCTION Sodium contamination in oxides is known as a major factor in the degradation Not only the initial properties of MOS devices but also the of MOS devices." long-term reliability is greatly influenced by sodium contamination. 12) In order to remove sodium ions from fabrication processes, a good deal of work has been done. "I In addition, passivation effects due to phosphorus have been studied by many researchers. ý41 While investigating radiation hardened (or degraded) MOS devices, we have noted a passivation effect using 220-320 nm ultraviolet light. The UV light was irradiated on to a full wafer with fabricated MOS devices. This paper describes the remarkable passivation effect of this UV annealing on sodium ions in oxides. EXPERIMENTAL The devices evaluated in this study were parasitic MOS transistors, active MOS transistors, MOS capacitors and p-n junctions. They were contaminated with sodium after gate electrode formation. Photoresist was coated on Si wafers and ashing was performed to introduce sodium contamination from the photoresist to the MOS devices. A two-level aluminum interconnect was formed. Then, the devices were subjected to H2 /N. annealing for 30 min at 400" C. First, electrical properties (ID--VG curve, threshold voltage, and flatband 861
voltage) of these MOS devices were measured. Next, the devices were subjected to UV annealing for a given time period and were measured once more. The UV annealing was done with a radiation intensity of 650 mW/cmr at 180* C in the air. The UV wavelength was 220-320 nm. Temperature dependence of the passivation effect was examined using a weak UV light with a radiation intensity of 5.5 mW/cm 2 . Other conditions were the same as those described above. EXPERIMENTAL RESULTS The flatband voltage of the MOS capacitors subjected to the above contamination process is shown in Fig.l. A large negative shift indicates many positive charges. When these MOS capacitors are biased negatively at an elevated temperature (190' C), flatband voltage is reduced to the control level. Considering that temperature is 190 C and the electric field is weak (0.5 MV/cm), it is confirmed that the positive charges responsible for the negative shift are sodium ions. A cross-sectional view of a parasitic MOS transistor used in this study is shown in Fig.2(a). I.-V. characteristics of the parasitic MOS transistor with sodium contamination are given in Fig.2(b). The degraded I,-V. curve due to sodium ions is greatly improved with UV annealing for only 10 min. It is known that sodium ions in the oxides are located near the Si-SiO. interface and near the gate electrode-SiO2 interface and that the former is responsible for the negative flatband voltage shift. Considering these, it is assumed that UV annealing acts on the sodium ions near the Si-SiO. interface. The threshold voltage as a function of UV annealing time is given in Fig.3. A rapid improvement is obtained during the initial 3 minutes. No further improvement in
0 MOS CAPACITOR
CONTROL LEVEL
to× -10
-BT: 0
z
= 400 -20V,
-20
I
I
BEFORE
AFTER
-BT
Fig.1
nm
S =
mm2
SODIUM CONTAMINATED
-BT
-BT effect on flatband voltage of contaminated MOS capacitors
862
190"C,
20MIN
Al
Si
(
a
GATE
)
Cross-sectional drawing of a parasitic MOS transistor
100 H
H
10-0
z H
H H
(1)
C-,
10-,o
z H
H
10-1
8
6
4
2
0
GATE VOLTAGE V 0 (V) Fig.2
Gate voltage for
a
dependence
parasitic
863
MOS
of drain transistor
current
A PARASITIC M0S TRANSISTORS (n-CHANNEL) GATE ELECTRODE
Poly-Si
CHANNEL
0.8
LENGTH
CHANNEL WIDTH
51
OXIDE THICKNESS
u m
/u m
350 nm
a C')
H
6
-7
0 Hn 0I-
b
H
/lL
UV ANNEALING
W
0
w-)
mW/C
INTENSiTY 650
RADIATIONN
WAVELENGTH TEMPERATURE
:11
220-320 nm 180 C
0
--
~l Il
2
I
I
I
3
0
I
I
~I
0
UV ANNEALING TIME
I
I
20 (MIN)
Fig.3 UV annealing time dependence of threshold voltage for parasitic MOS transistors
864
n-CHANNEL ACTIVE MOS TRANSISTOR
60
GATE ELECTRODE
Poly-Si
CHANNEL
0.5 u m
LENGTH
GATE OXIDE THICKNESS
7 nm
FIELD OXIDE THICKNESS
300 nm
-
1 1Z
-
1
t
E
S40
0 Z
z
00 02
S20 Z
n
0
P
z O~'
00 z
H
0
10
20
30
UV ANNEALING TIME (MIN) on sodiumeffect Fig.4 UV annealing contaminated active MOS transistors
the threshold voltage is obtained for prolonged UV annealing time beyond 10 min. The figure indicates that 10 min UV annealing sufficiently affects sodium ion passivation (or neutralization). UV annealing effect on contaminated active MOS transistors is portrayed in Fig.4. The threshold voltage and subthreshold swing sharply recover at 10 min and that transconductance is constant. These results imply that Si-SiO2 interface states are not associated with sodium ions and that the threshold voltage recovery is due to the sodium ion passivation of the gate oxide areas and field oxide regions. Another demonstration of the passivation effect of the UV annealing is given in Fig.5. This shows a degraded MOS capacitor flatband voltage influenced by sodium contamination and a remarkably improved flatband voltage associated with the UV annealing. Here, it should be emphasized that the gate area is very large (1 mm 2 ) and the UV annealing acts on the oxides below the Poly-Si gates. 865
MOS CAPACITOR GATE ELECTRODE THICKNESS 1 mm2
GATE AREA
SiO.
Poly-Si 300 rim
THICKNESS 440 run
-5 WITH UV ANNEALING I..-
H
0
-10
0
H E<
WITHOUT
i
z f=
UV ANNEALING
J_
-15
A
B
C
D
SAMPLE PARAMETER
E
A B
CONTROL LIGHTLY CONTAMINATED
C D E
MOS CAPACITORS HEAVILY CONTAMINATED MOS CAPACITORS
Fig.5 UV annealing effect on sodiumcontaminated MOS capacitors
TEMPERATURE DEPENDENCE The temperature dependence of UV annealing is shown in Fig.6. Figure 6(a) illustrates a cross-sectional view of a junction diode used in this examination and Figure 6(b) shows reverse current-voltage characteristics. When the devices are contaminated with sodium ions, the reverse leakage current becomes large. The reverse leakage current is corrected with UV annealing. The recovery rate of the leakage current is measured as a function of temperature to study the role of temperature in the UV annealing. The temperature dependence of the leakage current recovery rate is indicated in Fig.6(c). The recovery rate is small at low temperatures and increases at temperatures above 150" C. 866
Vi
S=O. 2 mnm 100 SODIUM CONTAMINATED H
(a)
(b)
5 0
Z
UV
ýNNEAL
'D -
CC/2
n'-p JUNCTION
S0
,
1
!
,CONTROL
2
3
REVERSE VOLTAGE V,(V) UV ANNEALING RADIATION 2 INTENSITY 5. 5 mW/cm
15
0
(c)
z C-
10
N
C:,
I
5 5 0
0
I
I
100
200
TEMPERATURE
Fig.6
Temperature
dependence
867
I
300
(-C)
of UV passivation
effect
UV light with small radiation intensity (5.5 mW/cm') was employed to avoid excessively fast recovery with 650 mW/cm 2 radiation intensity. Recovery rate R is defined as,
R =- A.- (AIL/At) /IL,
where A is constant, 1L is leakage current and t is UV annealing time. A I , is the leakage current decrease with a radiation time period (A t) of 15 min. MECHANISM A most probable mechanism for the UV annealing effect is neutralizing sodium ions with electrons. This neutralization model is illustrated in Fig. 7. A UV wavelength of 220-320 nm corresponds to an energy of about 4 eV, which excites electrons of the Si gate (or Si substrate) conduction band to surpass the conduction band edge of the silicon dioxides next to the Si. It is assumed that some of these electrons are injected into the oxides and may be trapped by the positive space charges (sodium ions). There are many electrons in the conduction band for the n-type Poly-Si gates. UV light with about 4 eV energy can excite electrons from the Poly-Si conduction band edge to above the barrier height of 3.1 eV (between the Poly-Si gate and SOi conduction band edges). Conversely, with the p-type Si substrate, there are few electrons in the conduction band and electrons excited from the substrate to the Si02 conduction band edge need an energy of 4.2 eV, which is the sum of the Si forbidden gap (1.1 eV) and the barrier height (3.1 eV).
ELECTRONS
Fig.7 Schematic energy band diagram (neutralization process of positive ions Na÷
with
868
excited
electrons)
Thus, it is concluded that electron injection from the Si substrate is much more difficut to occur compared to that from the Poly-Si gates. It is assumed that electron injection from the gate is effective for the passivation of sodium ions near the gate-SiO. interface and ineffective for that of sodium ions relatively far from the gate-SiO2 interface (such as sodium ions near Si sub-SiO. interface). Experimental results that UV annealing is effective at temperatures above 150"C suggest that sodium ion (or atom) diffusion in the oxides is closely connected to the passivation mechanism. The diffusion length of sodium in the oxides is approximately 0.2Mzm for 15 min. at 180" C. Such considerations bring us to the idea that only sodium ions close to gates are neutralized at low temperatures and that sodium ions far from gates can also diffuse near the gates to be neutralized at high temperature. Sodium atoms neutralized near the gates can also diffuse elsewhere. As a result, it is assumed that positive charge concentration near the Si-SiO decreases. Neutralizing sodium ions near the Si-SiO2 interface through this mechanism is proposed to explain the remarkable recovery at temperatures above 150" C. CONCLUSION A notable passivation effect caused by UV annealing was studied with various MOS devices. A mechanism for the passivation process was presented in terms of a sodium ion neutralization with excited electrons. UV light with the energy of about 4 eV can give larger energy to electrons in n-type Poly-Si gates than the gate-SiO2 interface barrier height (3.1 eV). It is considered that some excited electrons are injected into the oxides and are trapped by sodium ions near the gate-Si0 2 interface. Experimental findings that UV annealing effect is small at low temperatures and large at temperatures above 150 C implies that sodium ion (or atom) diffusion in the oxides plays an important role in the passivation effect. These can be explained with a model that sodium ions relatively far from the gate can diffuse near the gates to be neutralized at elevated temperatures and that sodium atoms neutralized near the gate also diffuse elsewhere. As a result, it is interface also assumed that sodium ion concentration near the Si-SiO decreases. This UV annealing process is of practical use as well as being of scientific importance, and deserves further study. ACKNOWLEDGMENTS The authors are indebted to Takashi Morimoto for his useful suggestion, to Yoshiaki Mimura for his help in the UV annealing, and Dr. Eisuke Arai for his encouragement. REFERENCES [1] [2] [3] [4]
E.H.Snow, A.S.Grove, B.E.Deal and C.T.Sah, J. Appl. Phys. 36, 1664(1965). D.J.DiMaria, J.M.Aitken and D.R.Young, J. Apple. Phys. 47, 2740(1976). W.Kern and D.A.Puotinen, RCA Rev. 31, 187(1970). D.R.Kerr, J.S.Logan, P.J.Burkhardt and W.A.Pliskin, IBM J. 8, 376(1964).
869
VARIATION OF SURFACE AND INTERFACIAL SiO 2 LAYERS DURING THERMAL PROCESS L. Ling and F. Shimura Department of Materials Science and Engineering North Carolina State University Raleigh, North Carolina 27695-7916
ABSTRACT The variation of thermally grown surface SiO 2 films and interfacial SiO 2 layers in directly bonded wafer pairs during the thermal processes are investigated by means of SIMS and HR-TEM. The SIMS depth profiles for thermal SiO 2 films after heat treatment at 1000oC for 5 hours in 02 and N2 show that a surface SiO 2 film grows with oxygen supplied from the ambient, and the contribution of interstitial oxygen in both FZ silicon and CZ silicon is negligible. It is shown that the interfacial SiO2 layer in bonded FZ silicon wafer pairs disintegrates greatly during the bonding process at 12000C. The higher stability of interracial SiO2 layer in CZ silicon is demonstrated and is attributed to the higher concentration of interstitial oxygen which can increase the system free energy. Introduction Thin films of silicon oxide, usually denoted as SiOx with x around 2, have been intensively studied over many years because of their extreme importance to the microelectronics device technology. In particular, the trend toward shrinkage of the dimensions of MOS devices demands reduction in thickness and increase in stability of the gate oxide. The stability of thin interfacial oxide layers plays a key role for polysilicon emitter bipolar transistors and bonded silicon wafers for SOI or power device fabrications. Since the structure of the SiO 2 layer in the region close to the Si/SiO2 interface is complex and involve uncertainties, the stoichiometry and the structure of the Si0 2 may 870
vary locally during thermal processes particularly at high temperatures, e.g., 9000C or higher [1-5]. This may affect the properties and stability of the whole Si0 2 film more seriously for thinner films (e.g., <200A) than for thicker films (e.g., >250/k). By means of secondary ion mass spectroscopy (SIMS) and high-resolution transmission electron microscopy (HR-TEM), the present study concentrates on the observation of variation and disintegration phenomena of surface and interfacial SiO 2 layers formed in thermally oxidized and directly bonded float-zone grown (FZ) and Czochralski grown (CZ) silicon wafers. From the comparison between CZ and FZ silicon wafers, we conclude that oxygen out diffusion from the bulk region toward the SiO 2 layers [6] can be ignored during the thermal processes. Instead, we attribute the higher stability of interracial SiO 2 layer in CZ silicon wafer pairs to the system free energy which depends on the interfacial oxygen concentration in bonded silicon wafers.
Experimental
Procedure
Commercially available p<100> FZ and CZ silicon wafers were used in this study. They were 100 mm in diameter, 525 gm in thickness and with a resistivity of 10-20 ohm-cm. The concentrations of interstitial oxygen (0i) were measured by Fourier transform infrared (FTIR) spectroscopy. According to ASTM F12179[7], CZ and FZ wafers contained 1.6X1018 cm- 3 and < 2.5X1O15cm- 3 interstitial oxygen, respectively. The first set of these wafers were oxidized in an oxygen ambient to form thermal Si0 2 films with nominal thickness of 80 A at 900 'C. These oxidized wafers with thermal SiO 2 were followed by the heat treatment at 1000'C for 5 hours in either oxygen or nitrogen ambients. The second set of samples were prepared by direct Si/Si wafer bonding [8]. The pairs of as-cleaned CZ or FZ silicon wafers were contacted at room temperature without any specific force, and were followed by annealing at 1000'C or 1200'C for 2 hours in a nitrogen ambient. During the bonding anneal no external force was used to keep the wafers together. The SIMS depth profiles of 160 were obtained for thermally oxidized wafers by a CAMECA IMS-3f using Cs ions as the 871
primary beam. The thickness of the primary surface SiO 2 films was measured by ellipsometry, and was observed with crosssectional TEM after the secondary heat treatment. The interfacial oxide layers of bonded wafer pairs were investigated by HR-TEM using a JEOL 200CX for cross-sectional thin specimens prepared by standard procedures including polishing, dimpling and ion-milling.
Experimental
Results
and
Discussion
The effect of high temperature annealing on the thickness of surface Si0 2 - Two kinds of specimens listed in Table 1 underwent annealing processes in dry 02 or N 2 ambients at 1000 'C for 5 hrs. The cross-sectional HR-TEM results show that the effect of high temperature annealing in N 2 on the thickness of surface SiO 2 layer is too small to be perceptible by this technique for both CZ and FZ silicon wafers (see Tablel). The thickness of SiO2 increased greatly when the samples were annealed in a dry 02 ambient, as shown in Fig.l. This is reasonable because the oxygen ambient supplied the silicon wafers with the oxygen atoms which diffuse into the silicon bulk and form oxide. Based on above results, it is clear that the concentration of interstitial oxygen atoms in silicon bulk does not have significant effect on SiO 2 thickness growth. In contrast to the conclusion by T. Abe et al.[6], we suggest that the contribution of oxygen atom diffusion from CZ silicon bulk to a SiO 2 layer or from a SiO 2 layer to FZ silicon bulk to the change in the SiO 2 thickness is negligible during the thermal processes. The surface SiO 2 layers grew with oxygen atoms supplied by an 02 ambient. In addition, it is worthy to note that our conclusion is not contradictory with Ahn's consideration [4,5]. According to their consideration, the changes in oxide thickness are about 2.OA and 0.2A for CZ and FZ silicon, respectively, which are less than the sensitivity of both TEM and SIMS techniques and negligible. Variation of interfacial Si02 layer in directly bonded silicon wafer pairs - Figure 2 shows the local HR-TEM images of bonded CZ silicon wafer pairs; (a) bonded at 1000°C and (b) at 1200'C . The interfacial oxide layers shown in Fig.2 came from native oxide formed before bonding heat treatment, the same is true for Fig.3. We did not find any disintegration phenomenon of interfacial oxide 872
U 4)
0 DOept
..05
.1
.15
.2
Depti (Mlicromoter-e)
(H i o0ometers)
Fig. The SIMS depth profiles for the samples listed in Table 1; (a) FZ silicon wafers and (b) CZ silicon wafers.
layers which has been observed by other researchers[5,10]. In contrast to their results, the oxide layer bonded at 1200'C is more uniform than that bonded at 1000'C, as shown in Table 2. The HR-TEM images of interfacial oxide layers in bonded FZ silicon wafer pairs are shown in Fig.3; (a) bonded at 1000 0 C and (b) at 1200 0 C. The disintegration phenomenon of the oxide layers is very obvious in these samples, especially in the sample bonded at 1200'C. Across the disintegrated area, the silicon lattice is continuous from one wafer to another one. This result is consistent with that reported by other researchers[5,9]. In the sample bonded at 1000 0 C, few disintegrated areas, such as that shown in Fig.3(a), were observed, which are about 150A in length. The remaining layer is not uniform with about 10A fluctuation. Its average thickness is about 20A. The greatest disintegration phenomenon occured in FZ silicon wafer pairs bonded at 1200'C. The whole oxide layer disintegrated into several " white islands " during the bonding process. One of them is shown in Fig. 3(b), which is 60A in thickness and 245 A in length. The thickness of these islands is 873
TABLE 1. Thermally oxidized silicon wafers investigated in this study. Sample ID SiO. Thickness (A) Nominal Ellipsometry TEM FZ-80-R 80 77 70 FZ-80-N 70 FZ-80-O 1570 CZ-80-R CZ-80-N CZ-80-O Where R: reference samples. 0: annealed in 02.
80 -
77
-
75 75 1330
N: annealed in N2.
TABLE 2. The characteristics of interfacial SiO2 layer in directly bonded silicon wafer pairs. Sample ID Thickness (A) Quality Maximum Minimum FZ-B-1000 25 0 Disintegrated CZ-B-1000 30 20 Continuous FZ-B-1200 60 0 Disintegrated/Islands CZ-B-1200 25 25 Uniform/Continuous Where B: bonded wafer pairs. much larger than the average thickness of the oxide layer in the FZ pairs bonded at 1000'C. This result was also conformed by Ahn et al. [5) Comparing the morphology of the interracial oxide layers in CZ silicon wafer pairs with that in FZ pairs, it is clear that the stability of the oxide layer in CZ silicon pairs is much higher than that in FZ silicon pairs. This phenomenon is also consistent with that reported by Ahn et al. [5]. Although the interfacial oxide layer in CZ silicon pairs disintegrated in their experiment, the remaining layer is much longer than that in FZ silicon pairs. As we know, the biggest difference between CZ and FZ silicon wafers is their interstitial oxygen concentration. The concentration is larger than its solid solubility in CZ silicon wafers but less than the solubility in 874
Fig.2 The HR-TEM images showing interfacial oxide layers in CZ silicon wafer pairs bonded at (a) 1000°C and (b) 1200C.
Fig.3 The HR-TEM images showing disintegrated interracial oxide layers in FZ silicon wafer pairs bonded at (a) 1000*C and (b) 1200°C.
FZ silicon. Even though it is possible that the misorientation between two bonded wafers can affect the disintegration of the interfacial oxide layer[5]. The misorientation in our samples is less than 2.2' which is less than the critical angle ecrit estimated . Thus, we suggest that the concentration of interstitial oxygen also affects the morphology of the interfacial oxide layer besides the Si/SiO 2 interface energy[5].
875
Since the initial disintegration of the oxide layer begins with silicon holes formed in the oxide layer[5], based on the critical nucleation theory[1O], the free energy change due to a hole formation should be given by following equation: si s o gio+x 2 Xx S' sio(gigsio2)+27c'rXop - 2xT 2r AGTt - g5o 02)+irrX, xa 05Si 2 (g5 g 0 )+rX X Xx)si2(si AG=itr 2 X..X 1 O-2r 5 oJgo 0
(1 ()
si
0
where XSio 2 andXSio 2 are the concentrations of oxygen
and silicon
A
atoms in SiO 2 , per A atom in /Si0 2 interface an oxide layer.
respectively. Symbol gB stands for the free energy B material. r is the radius of a silicon hole, Y the Si energy per unit area and Xox the initial thickness of Therefore, the critical nucleation energy is: 2
2
Ox AE* =t 2o-XoAG,
(2)
where Gv is the volume free energy of the system due to a silicon hole formation, AGv, is given by S
os
AGv = s 0 2(gsi-
o
Si
, Si
and its change
Si
+ xSiO•gs" so gsio 2)
(3)
and 2a -X oAG, > 0
(4)
From Eqs.(l) and (2), it is obvious that this initial disintegration process is driven by two kinds of forces which come from Si/Si0 2 interface free energy and the volume free energy change AGv and is restrained by the initial thickness of oxide layers. Larger critical nucleation energy leads to a higher stability of an oxide layer. If the driving force coming from the volume free energy change is ignored, that is AGv = 0, Eqs.(l) and (2) degrade to those in Ahn's local model where only the interface energy was considered as a driving force[51. However, the Si/SiO2 interface energy is the same for both CZ and FZ silicon wafer pairs during a bonding process because the concentration of interstitial oxygen atoms along the interface is equal to the solid solubility of silicon [5]. Therefore, the different stability of the oxide layers in CZ and 876
FZ silicon wafer pairs is not associated with the interface energy. As a result, only the volume free energy change and the initial oxide layer thickness determine the stability of the oxide layer. It is evident that the thicker the oxide layer is, the higher the nucleation energy E* and the higher the stability of the oxide layer. If the thickness difference of the initial oxide layers between CZ and FZ silicon pairs is negiligible, which is much closer to the case of directly bonded wafers, the volume free energy change is the primary cause of the different stability. Because CZ and FZ silicon are a kind of solid solution with oxygen as interstitial atoms in silicon crystal lattice, the solid solution is in the minimum free energy state when the concentration of interstitial oxygen atoms is equal to the equilibrium solubility of oxygen in silicon[l 1]. Fig.(4) shows a schematic diagram of the volume free energy Gv vs Ci, where Ci is the concentration of interstitial oxygen atoms in silicon bulk. If silicon bulk is annealed at 1200'C, the solid solubility of t7 -3 C 1 =4.56X 10 c1 [12]. The oxygen oxygen interstitials is concentration is 1.6 X 1018 cm- 3 in our CZ silicon wafer pairs but less than 2.5XI016 cm- 3 in FZ silicon pairs. Thus, Ci(CZ) - C9 >> C?' - Ci(FZ)
(5)
I(5
Gvt
Ci(FZ) Ci(eq)
Ci(CZ)
Ci
Fig.4 The schematic diagram of Gv vs Ci. Ci(FZ) and Ci(CZ) are the concentration of interstitial oxygen atoms in FZ and CZ silicon, respectively. 877
and the volume free energy Gv in CZ silicon might be considered to be larger than that in FZ silicon. AG, may be negative or positive, which is up to the concentration of interstitial oxygen atoms. if AGv < 0, it is energy favorable for the nucleation of silicon in oxide layer. If AGv > 0, the nucleation still can take place as long as Eg.(4) is valid. The larger the AGv the harder the nucleation and the more stable the layer . For CZ and FZ silicon, Gv(Cz) > Gv(FZ), so AGv(CZ) > AGv(FZ) because of Eqs.(3) and (5). Therefore, the interracial oxide layer in CZ silicon wafer pairs is more stable than that in FZ silicon wafer pairs, which is consistent with the experiment results. In our experiment, the much higher stability of the interfacial oxide layer in CZ silicon pairs, which is caused by higher concentration of interstitial oxygen and a little bit thicker initial oxide layer, makes the layer continuous. The further disintegration and final spheroidization of the oxide layer, which is mainly driven by the interface energy, have been discussed by Ahn et al.[5] in great detail.
Conclusion The SIMS depth profiles for thermal SiO 2 films after heat treatment at 10000C for 5 hours in 02 and N2 showed that a surface SiO 2 film grows with oxygen supplied from the ambient and the contribution of interstitial oxygen in not only FZ silicon but also in CZ silicon is negligible. It has been shown that the interfacial SiO2 layer in bonded FZ silicon wafer pairs disintegrated greatly during a bonding process at 12000C. The higher stability of interfacial SiO 2 layer in CZ silicon was explained by the higher concentration of interstitial oxygen which can increase the system free energy.
ACKNOWLEDGEMENTS The authors thank Shin-etsu Handotai (SEH) for financial support to this study. They are grateful to Dr. T. Abe (SEH) for his supply of bonded wafers and many helpful discussions, and to Dr. D. Griffs (NCSU) for his assistance in SIMS measurements.
878
REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9] [10]
[11] [121
G. R. Wolstenholme, N. Jorgensen, F. Ashburn and G. R. Booker, J. Apple. Phys., 61,225(1987). H. Schaber, J. Bieger, T. F. Meister, K. Ehinger, and R. Kakoschke, Proc. IEDM , p170 (1987). M. Delfino, J. G. de Groot, K. N. Ritz, and P. Maillot, J. Electrochrem. Soc., 136,215(1989). K. -Y. Ahn, R. Stengle, T. Y. Tan, U. Goesele, and P. Smith, J. Apple. Phys., 65,561(1989). K. -Y. Ahn, R. Stengle, T. Y. Tan, U. Goesele, and P. Smith, Appl. Phys., A50,85(1990). T. Abe, A. Uchiyama, K. Yoshizawa, Y. Nakazato, M. Miyawaki, and T. Ohmi, Japan. J. Apple. Phys., 29,L2315(1990). ASTM Standards Vol.10.05, Section 10, 1984 (American Society for Testing and Materials). T. Abe, M. Nakano, Submitted to Proc. of 4th Intern. Symp. SO1 Tech. and Devices, Montreal, May 9 (1990). R. B. Black, S. D. Arthur, R. S. Gilmore, N. Lewis, E. L. Hall and R. D. Lillquist, J. Appl. Phys., 63, 2773 (1988). J. W. Christain, " The Theory of Transformations in Metals and Alloys", ed. by G. V. Raynor F. R. S. ( Pergam Press, Oxford) p415 (1965). K. Wang, "Solid State Physics", ed. by The People Education Press, China, p81 (1979). R. A. Craven, " Semiconductor Silicon", ed. by H. R. Huff, R. J. Kriegler and Y. Takeishi (Electrochemical Society, Pennington )p254 (1981).
879
ENHANCED DEGRADATION IN GERMANIUM IMPLANTED PMOSFETS L. P. Hobbs, A. von Schwerin & K. Maex. IMEC vzw, Kapeldreef 75, 3001 Leuven, Belgium. ABSTRACT The use of germanium amorphisation and boron implantation is an established technique in forming p+n- junctions for submicron PMOSFET processes. However little information is available on the influence of the germanium on the device degradation. In this work the influence of the germanium on the gate and substrate currents in a PMOSFET is investigated. It will be shown that the PMOSFET devices with germanium have degraded lifetime characteristics. A model is proposed which suggests that this degradation is due to an increased mean free path for the hole which is brought about by the decreased lattice strain in the germanium implanted device. INTRODUCTION Over the past number of years device degradation in MOSFET devices has been the subject of many investigations [1-51 as the topic becomes more important with todays ever shrinking device dimensions. Although most work has been conducted with NMOSFET [1-31 devices more studies are now being carried out to investigate the degradation in PMOSFET devices [4,51. Another topic that has been a major concern is the formation of shallow p+n- junctions [6,71 as such junctions are required in advanced MOS processes. A popular method to create these junctions has been to use germanium implantation to amorphise the silicon surface and by so doing to prevent the boron ion from channeling [7]. However little knowledge is available on the influence of germanium on the PMOSFET degradation. In a recent publication [3] Ng. et al have reported improved degradation results when germanium implantations have been used in NMOSFET devices. The purpose of this work was to investigate what influence the pre-amorphising germanium implants have on device degradation in PMOSFET devices. EXPERIMENTAL DESCRIPTION The starting material was 5 inch silicon wafers which had a resistivity of 15 K2cm. A LOCOS technique was used for device isolation and an anti-punch through implant of 1.4xl0 12 cm- 2 with phosphorus at 180keV was followed by a threshold adjust implant with boron of dose 1.7x1l012 cm- 2 and energy 20keV. A gate oxide of 15nm was grown at 900C and the deposited polysilicon was implanted with
880
phosphorus to yield a n+ gate. After polysilicon gate definition Ge was implanted with a dose and energy of lxlOl 5 cm- and 85keV into some of the wafers. Next all the wafers received a 1F2 implant of dose Ixl0 15 cm-2 and energy 20keV. A zero degree off-axis implant angle was employed. Spacers were subsequently formed using TEOS deposition and an anisotropic oxide etch. A second implant with BF 2 was then performed which had a dose and energy of lxl015 cm- 2 and 45keV. The junctions were then annealed using furnace annealing at 900C for various times. CoSi2 was formed on the junctions by reacting a deposited 20nm layer at 700C in N2.
Depth pgm
(b)
region
El
Ge/n
drain
n substrate
II
region Fig. 1 (a) SRP profile for a BF2 implant of dose and energy 1x101 5cm" 2 and 20keV into preamorphised silicon. The implant had an off-axis implant angle of zero degrees and the junction had been activated using a furnace anneal at 900C for 30 minutes. Also shown is the SIMS profile for
the amorphising germanium implant of dose and energy lxl015cm- 2 and 85keV. (b)Schematic representation of a PMOS device which has received an amorphising germanium implant. 881
After deposition of an inter-layer dielectric the contact holes were defined and the metalisation stage completed. The metalisation layer consisted of a bilayer of 100nm of TiW and lI.tm of Al/l%Si. MATERIAL AND ELECTRICAL CHARACTERISATION Both SIMS and SRP analyses were used to characterise the profiles of the various implants that were performed. This analysis revealed that there was no measurable difference in vertical junction depth between samples which did and did not receive a pre-amorphising implant. The reason for this lack of difference is thought to be due to the fact that the BF2 species acts as an efficient self-amorphising 15 species under these implant conditions [6].The SRP profile for the lxl0 cm-2 20keV BF2 implant, which has been activated using a furnace anneal of 30 minutes at 900C, can be seen in Fig. 1(a). Also shown here is the SIMS profile for the Ge implant. It is obvious that when germanium is used in such a pre-amorphisation scheme large concentrations of this.neutral ion will exist beyond the p+ region. As such the realisation of such a scheme in a MOS device will result in a device structure which is depicted schematically in Fig. l(b). The devices which have germanium in the channel exhibit similar junction leakage currents but higher substrate and gate currents, for the same bias conditions, than those devices in which there is no germanium. This increase in the gate and substrate currents can be observed in Fig. 2 (a) and (b) respectively, which display these characteristics as a function of gate current for a fixed drain voltage of -7.5V. (b)
(a)
IV Gs I(V)
I VGS I(V)
Fig. 2 (a) Gate Current and (b) substrate current versus gate voltage for devices with and without germanium implants. The gate length = l14m, junction depth = 1 10nm for both devices. VDS = 7.5V
882
The substrate current in a PMOS device is created from the impact ionization of channel holes near the drain with the created holes being swept into the drain and the electrons into the substrate where they give rise to the substrate current. In addition the gate current under the bias condition of VGS < VDS is composed of electrons which are injected into the gate from the substrate current [5]. Hence both the gate current and the substrate current in the PMOS device are a measure of the extent of the impact ionization that takes place near the reverse biased drain region. As such it is evident from Fig. 2 that a greater number of electron-hole pairs are generated by impact ionization near the drain of the device which has received the germanium implant. This fact is again illustrated in Fig. 3 where Isub/IDS is now plotted as a
function of the vertical junction depth ( as determined from SRP data) for similar bias conditions on all the devices. Here again it is observed that the devices which have germanium in the channel have an increased substrate current. Junction Activation Time (mins) 30
-5
+
40
50
60
.I.
10
- 010
-7 10
I r
110
1
I
125 120 115 Junction Depth (nm)
130
Fig. 3 Log-linear plot of tsub/tDS versus Junction Depth ( as measured by SRP ) and Junction Anneal Time for devices which (a) did and (b) did not receive a preamorphising Ge implant. Device gate length = tim. VDS = -4V & VGS = -2V.
In addition the behaviour of Isub/IDS with increasing junction depth is different for the two cases. This discrepancy can be explained as follows. The increase in Isub/IDS, for the devices with no germanium, with increasing junction depth is due to the fact that as the junction depth increases the effective channel length of the device will decrease. From [8) the maximum electric field in the channel of a device which has a gate oxide thickness Tox and junction depth of Xj can be expressed as follows
883
Em = VD - IVDsat .......... (1)
where 0 33 . 05 1 =0.22T x Xj. .......... (2)
and VDs1t
IVG-VtlEsatLeff
= IVG_-Vt + EsatLeff .
(3)
where Vt is the device threshold voltage, Esat is the channel field at which the carriers reach saturation velocity and Leff is the effective channel length. From (3) it can be seen that as the effective channel length decreases VDsat will also decrease and hence the maximum electric field increases. From [8] Isub may be expressed as -B IDSAEmI Em Isub= B e .......
(4)
The origins for A and B can be found in the expression for the ionization rate ct [8]. -B Em ax=A e
.......... (5)
Hence it is seen that an increase in junction depth brings about an increase in the maximum electric field which in turn will increase Isub/IDS. This increase in Isub/IDS is not observed in the devices which had received the germanium implant. In fact a slight decrease is observed with increasing junction depth ( Fig 3 ). This decrease is thought to be due to the fact that as the junction spreads more laterally into the channel then the size of the germanium/n region( recall Fig. l(b) ) is steadily reduced and hence the behaviour of the impact ionization approaches that of the standard device. The effect of the germanium on device lifetime is depicted in Fig. 4 where device degradation is plotted as a function of the gate length for devices with and without germanium in the channel ( Alsub/Isub was chosen as the parameter with which device degradation could be best compared as it was found to be most sensitive to changes in the channel ). The difference in the degradation between the two different types of devices can be attributed to the increased carrier injection into the gate oxide regions in the germanium implanted devices.
884
Device degradation in PMOS devices is known to be mainly due to electron injection into the oxide [5,9]. Hence the device with the higher substrate current will inject more electrons into the oxide and so enhance the device degradation. The decrease in the difference between the germanium device and standard device characteristic with decreasing gate length is due to the fact that as the gate length is reduced the increasing electric field begins to dominate and the effect of the germanium is somewhat masked.
0.9
S0.8 "
0.7
0.6
1.5
2.0 2.5 Gate Length (gm)
Fig. 4 Alsub/Isub versus Gate Length for devices which (a) did and (b) did not receive a germanium preamorphisation implant Stress time was 1 hour and stress conditions were VDS = -8V & VGS = 3.5V. Isub was taken as the maximum of the Isub versus VGS curve when VDS = -5V. Junction depth was I10nm. DISCUSSION The reason for the increase in substrate current and subsequent enhancement in device degradation in devices which have received germanium implants is not immediately evident. One possibility is that the mean free path of the carrier has been influenced by the inclusion of the germanium in the channel. In [3] Ng. et al argues that the suppression of the hot carrier degradation in NMOSFETs is due to a decreased mean free path of the hot electrons. If such a hypothesis were to be applied here then it could be concluded that in the PMOSFET device the inclusion of germanium leads to an increase in the mean free path of the hot hole. To investigate this possibility we return to equation (4) which when combined with (1) indicates that a log-lin plot of Isub/IDS(VD - VDsat) versus the inverse of (VD - VDsat ) will return a slope B1. Such curves are illustrated in Fig. 5 for devices with a junction depth of 1l0nm and 120nm. VDsat was determined using (3) assuming a value of 1.2x10 5 V/cm for Esat [10].
885
(a) 10
S10 S10*
10
Sto-~10
10 - 0.2
0.4
0.3
0.5
.0.6
(/V)
VD
VDsat
(b) 10 -3
Device with Ge Standard Device -u-
to 14 '5
t-~10
B = 2.8x10
10 -6; p
6
(V/cm)
10 -7
S10
6
-8
B = 3.2xl0 (Vjcm)
-9
lu
0.2
1
0.3
0.4 1 VD- VDsat
0.5
0.6
(/V)
Fig. 5 Log-linear ploys Of I sub/IDS* (VD - VDsat )) versus 1/ ( VD - Vbsat) for devices with and without germanium. Junctions depths were (a) I l0nm and (b) 120nm.
886
Using (2) B may be determined from the slope of the line is Fig. 5. A value of 3.2xlo 6 V/cm was returned for both cases in which no germanium had been used. This value for B is close to other published values [8,10]. When germanium preamorphisation was employed a somewhat lower value for B of 2.6x.0- V/cm was determined for the device with a junction depth of 110nm ( Fig. 5(a) ). When the junction depth was increased the value of B also increased to 2.8x10 6 V/cm (Fig. 5(b)). In [1] B was expressed as B
!L '.........(6) q2L
where (pi is the energy that a hole requires before it can create an electron-hole pair by impact ionization and X is the mean free path of the hole. Hence if pi is assumed to be the same in devices with and without germanium then the reason for the reduction in B in the germanium implanted devices is due to an increased X. Hence it can be easily calculated, using (6), that in the devices with a junction depth of 110nm ( Fig. 5(a) ) X has been increased by 23% in the germanium implanted device. When the junction depth is increased to 120nm the increase in X is reduced to 14%. The effect of this decreasing X , with increasing junction depth in the germanium implanted devices, was first observed in Fig. 3 and can be attributed to the decreasing influence of the germanium as the boron spreads more laterally into the channel beyond the germanium region. The increase in ?, in the Ge implanted devices could be due to the fact that germanium is expected to compensate the lattice strain that arises after high dose shallow implant/annealing of species such as boron [7]. This argument is supported by a recent work by Iwai et al. [11] in which they showed that increases in stress in the channel ( due to a nitrided gate in their case ) can produce lower hole mobilities in PMOSFETs and higher electron mobilities in NMOSFETs. CONCLUSION Devices which have been fabricated using Ge amorphising implants exhibit increased substrate and gate currents and subsequently degraded device lifetimes. The reason for this degradation is thought to be due to the fact that the germanium implant compensates for the lattice strain produced by the boron implant and so enhances the mean free path of the hole by as much as 23%.
887
ACKNOWLEDGEMENTS The authors would like to thank E. Simoen for useful discussions, B. Deweerdt for processing and W. Vandervorst for SRP and SIMS. K. Maex is a Research Associate of the Belgian Fund for Scientific Research.
REFERENCES [1] C. Hu, S. Tam, F. Hsu, P. Ko, T. Chan & K. Terrill, IEEE Trans. Electron Devices, vol. ED-32, p3 7 5 , February 1985 [2] F. Hsu & H. Grinolds, IEEE Electron Device Letters, vol. EDL-5, p71, March 1984. [3] K. Ng, C. Pai, W. Manisfield & G. Clarke, IEEE Electron Device Letters, vol. 11, p45, January 1990. [4] F. Matsouka, H. Hayashida, K. Hama, Y. Toyoshima, H. Iwai & K. Maeguchi, IEDM 1988, p. 18. [5] T. Ong, P. Ko & C. Hu, IEEE Trans. Electron Devices, vol. 37, p. 1658, July 1990. [6] L. Hobbs & K. Maex, Ext. Abs., Electrochemical Society Meeting, May 1990, ,vol 90-1, p. 6 9 3 . [7] D. K. Sadana, E. Myers, J. Liu, T. Finstead & G. Rozgonyi, Symposia Proceedings of the MaterialsResearch Society, Nov. 1983, vol 23, p. 303. [8] T. Ong, P. Ko and C. Hu, IEEE Electron Device Letters, vol EDL-8, p413, Sept 1987. [9] P. Heremans, R. Bellens, G Groeseneken and H. Maes, IEEE Trans Electron Devices, vol 35, p2194, Dec 1988. [10] C. A. Lee, R. A. Logan, R. L. Bardof, J. J. Kleimack and W. Wiegman, Phys. Rev. vol. 134, p. 761, 1964. [11] H. Iwai, H. Momose, S. Takagi, T. Morimoto, S. Kitagawa, S. Kambayashi, K. Yamabe & S. Onga, 1990 Synposium on VLSI Technology, Tech. Papers, Dig., p. 1 31.
888
AUTHOR INDEX Abe, T. .....................................................................................................
A00
Ahlbum , B.................................................................................................. Ahn, S. T ................................................................................................... Akiya, H ................................................................................................... Amazawa, T .............................................................................................. Andrews, J. M .............................................................................................. Apte, P. P.................................................................................................. Arita, Y...................................................................................................... Ashok, S.................................................................................................... Badgwell, T. A .......................................................................................... Bailey, D. E ................................................ Batchelor, D .............................................................................................. Bernt, H ............................................................................................... Bohland, J. F............................................................................................... Burger, W . R ...............................................................................................
617 650 861 276 409 755 276 483 820 785 851 120,445 155 650
Burroughs, J .................................................................................................
244
145 Calvert, J. M ............................................................................................... 391 Cam pabadal, F.......................................................................................... 765 Carl, D. A .................................................................................................. 692 Carruthers, R ............................................................................................. 26 Chan, H . C ............................................................................................... 582 Chapman, D. T ........................................................................................... 61 Chapman, R. C ........................................................................................ 692 Chapple-Sokol, J. D ................................................................................... 145 Chen, M .-S ................................................................................................. 285,330 Chevacharoenkul, S ............................................................................. 374 Chiacchia, C. H ........................................................................................ 78 Chin, G .................................................................................................... 382 Chiou, Y. L ................................................................................................. I Chiu, K.-Y ................................................................................................ 310,343 Choi, C. S ............................................................................................ ............................................. 635 Chu, H .................... ..... 541 Conrad, K. A.............................................................................................. 353 Cooper, J. R . ................................................................................................ 101 Cum m ings, K. D ........................................................................................... 503 Davis, C. J................................................................................................ 775 De Wolf, I ................................................................................................... 17 Deleonibus, S........................................................................................... 26 Dennison, C. H .........................................................................................
Dickerson, K.J............................................................................................
353
26,810 Ditali, A ............................................................................................... 627 Doan, T. T . .................................................................................................. 174 Donaldson, W . C ......................................................................................... 503 Dostalik, B................................................................................................ 739 Dubin, V. M ................................................................................................ 131,155 Dudley, B. W ....................................................................................... 145 Dulcey, C. S ................................................................................................
889
Dumin, D. J ................................................................................................. 353 Edgar, T. F . ................................................................................................ 820 Eichham mer, W .......................................................................................... 254 Elliott, J. K . ................................................................................................ 820 Fang, S................................................................................................... 473 Fazan, P. C............................................................................................. 26,810 Fitzgerald, E. A .......................................................................................... 164 Fonseca, L ................................................................................................. 391 Fordham , M . J . .......................................................................................... 582 Freeman, P. W ............................................................................................. 155 Friedrich, D ................................................................................................ 120 Frye, R. C .................................................................................................... 101 Fu, C. Y ...................................................................................................... 730 Fukuda,K .................................................................................................. 834 Galiano, M .................................................................................................. 617 Gambino, J. P............................................................................................. 382 Gasser, R .................................................................................................... 642 Geffken, R. M ............................................................................................. 667 Georger, J. H .............................................................................................. 145 Goodwin-Johannson, S.......................................................................... 131,174 Greene, W . M .............................................................................................. 431 Grider, D. T ................................................................................................. 296 Griffith, J. E ................................................................................................ 164 Grigg, D. A .................................................................................................. 164 Halimaoui, A . ............................................................................................ 712 Harris, G . ............................................................................................... 51 Hata, W . Y .......................................................................................... 190,199 Hauser, J. R ................................................................................................ 528 Heilemann, N . B ........................................................................................ 353 Hemicker, P ......................................................................................... 120,445 Hess, D. W ................................................................................................. 765 Heyns, M . .............................................................................................. 454 Hill, R. W ............................................................................................... 88 Hobbs, L. P ........................................................................................... 254,880 Hsu, R ........................................................................................................ 730 Hu, Y.-Z . .................................................................................................... 541 Hunn, J.D ................................................................................................. 343 Hutcheson, L. D ........................................................................................... 678 Inoue, MN................................................................................................ 421 Irene, E. A .................................................................................................. 541 Ishida, T ................................................................................................ 421 Itsum i, M . ................................................................................................... 861 Johns, P ................ ..... ............................................. 720 Johnsgard, K. E ........................................................................................... 566 Johnson, J. R .......................................................................................... 190,199 Jones, S. K............................................................................................ 131,155 Kakum u, M . ................................................................................................... 1 Kambayashi, S ......................................................................................... 52 Kapoor, V. J ................................................................................................ 657 Kar, S........................................................................................................ 483 Kawaguchi, E ........................................................................................... 52 890
Kellam, M . D......................................................................................... Kermani, A ...............................................................................................
61,131 566
Kobayashi, K .............................................................................................
183
Kopley, T. E.......................................................................................... Kronschnabel, J . ..........................................................................................
431 642
305 Kuan, T. S .................................................................................................. 503 Kuehne, J................................................................................................... 454 Kuper, W .................................................................................................. 321 Kuwabara, H .............................................................................................. 363 Kwong, D. L ................................................................................................ 120,445 Lange, P............................................................................................... 730 Law, B....................................................................................................... 34,78 Law, M . E ................................................................................................ 606 Leggett, R................................................................................................... 382 Li, G . .......................................................................................................... 374 Lin, D.-G .................................................................................................... 870 Ling, L . ....................................................................................................... . ........................... 26 Liu, Y................................................................. 363 Lo, G. Q ...................................................................................................... 26 Lowrey, T. A ............................................................................................. 464 M a, T. P . ..................................................................................................... 775 M aes, H. E . ................................................................................................. 254,880 Maex, K ............................................................................................... 851 M aher, D. M . .............................................................................................. 400 M akihara, K. ............................................................................................. 88 M aldonado, J. R ....................................................................................... 174 M arkus, K. W .............................................................................................. 183 M aruyama, T .............................................................................................. 541,574 M assoud, H. Z ..................................................................................... 26,800,810 M athews, V. K ................................................................................ 226 M atsuda, K ............................................................................................... 52 M atsunaga, J........................................................................................... 236,834 M atsuura, T .......................................................................................... 606 M aury, A.................................................................................................... 353 M cAllister, P. A ......................................................................................... 473 M cCarthy, A. M .................................................................................... 285, 330 M cGuire, G. E....................................................................................... 206 M cNevin, S. C............................................................................................. 473 M cVittie, J. M . ...................................................................................... 582 M elzak, J. M .................................................... 454 M euris, M ............................................................................................... 164 M iller, G. L ................................................................................................. 266 M iyake, M .................................................................................................. 52 M izushim a, I........................................................................................... 17 M olle, P ................................................................................................... 606 Monnig, K ................................................................................................... 642 M orim oto, S. ............................................................................................ 400 M orita, M . .................................................................................................. 503, 755 M oslehi, M . M ..................................................................................... 305 M oy, D ....................................................................................................... 861 M uramoto, S ...............................................................................................
891
M urota, J.............................................................................................. M yInko, W ..................................................................................................
236,834
Najm, H ....................................................................................................
503
244
Nakagawa, 0. S . ........................................................................................ 431 Nakayama, S ........................................................................................ 9,861 Nakazato, Y .............................................................................................. 400 Nalamasu, 0 .............................................................................................. 110 Nguyen, L. N........................................................................................ 190,199 Norstr6m , H ................................................................................................ 775 Novembre, A. E ........................................................................................... 110 Nowak, R ................................................................................................... 617 Oberlin, J. C ................................................................................................ 712 Ohmi, T.................................................................................. 236, 321,400,834 Ohta, K ..................................................................................................... 749 Oka, H . ...................................................................................................... 749 Okada, T. K............................................................................................. 52 Olsen, J . ...................................................................................................... 617 Olson, K ..................................................................................................... 692 Ong, E ....................................................................................................... 635 Onga, S ................................................................................................... 52 Onishi, S .................................................................................................... 226 Ono, S .................................................................................................. 236,834 Osburn, C. M .............. ........................................................ 285,310,330,343 Otsuki, M .................................................................................................... 321 Ott, J. A ...................................................................................................... 305 Owada, N .................................................................................................. 793 Oztiirk, M . C .................................................................... 296,528, 582,841,851 Palleau, J................................................................................................... 712 Pandey, A .................................................................................................. 483 Patrick, W . ) . .............................................................................................. 692 Patterson, J. D . ............................................................................................ 841 Pavelchek, E. K .......................................................................................... 155 Peckerar, M . C ...................................................................................... 145,409 Pelka, M .............................................................................................. 120,445 Peters, C ..................................................................................................... 131 Peters, D........................................................................................................ Philipossian, A .......................................................................................... 454 Pierce, J. M .................................................................................................. 650 Pinto, M . R ............................................................................................... 43 Queller, S . .................................................................................................. 642 Raaijm akers, I . ........................................................................................... 635 Raychaudhuri, A ....................................................................................... 483 Reism an, A . ................................................................................................ 493 Renteln, P .................................................................................................. 650 Rhodes, H. E........................................................................................... 26 Rietman, E. A .............................................................................................. 101 Rogers, W . B .......................................................................................... 61,174 Rom ano-Rodriguez, A ............................................................................... 775 Ruggles, G. A ........................................................................................ 310,343 Russell, P. E................................................................................................ 164 Saito, A ..................................................................................................... 749
892
276 Saito, K ...................................................................................................... 226 Sakiyama, K.............................................................................................. 541,574 Sampson, R. K ..................................................................................... 216 Samukawa, S .............................................................................................. 627 Sandhu, G. S . .............................................................................................. 851 Sanganeria, M ............................................................................................ 551,755 Saraswat, K. C .................................................................................... 61 Sayer, R. W ............................................................................................. Schliwinski, H. J ......................................................................................... 120 445 Schmidt, L ................................................................................................. 145 Schnur, J. M ................................................................................................ Schoen, P. E ................................................................................................. 145 692, 720 Schwartz, G. C.................................................................................... Shah, A. S ................................................................................................. 343 5 Shimohigashi, K ..................................................................................... 870 Shimura, F ................................................................................................. 606 Sivaram , S .................................................................................................. 528,582 Sorrell, F. Y . ........................................................................................ 382 Sow, C. H ................................................................................................... 409 Sprangle, E. A ............................................................................................. Stagam an, G. J ...................................................................................... 190,199 120 Staudt-Fischbach, P .................................................................................... 749 Takahara, Y . ............................................................................................. 712 Tem plier, F ............................................................................................... 400 Teramoto, A ............................................................................................... Thane, N . S ................................................................................................. 199 592 Ting, C. H ................................................................................................... ..... ............................................. 363 Ting, W ............................ 421 Todokoro, Y ................................................................................................ Tolles, R . .................................................................................................... 606 712 Torr6s, J.............................................. 820 Trachttenberg, I . ......................................................................................... Tsang, P. J................................................................................................... 382 400 Uchiyama, A ............................................................................................. Uetake, H ............................................................................................ 236,834 775 Vanhellem ont, J .......................................................................................... 244 Varhue, W .................................................................................................. 164 Vasile, M . J................................................................................................. Velo, L ....................................................................................................... 503 454 Verhaverbeke, S ........................................................................................ 880 von Schwerin, A ......................................................................................... 164 Wagner, E. R ............................................................................................... 493 Walters, M . ............................................................................................... 305 W ang, L. K .................................................................................................. 635 Wang, S.-Q .............................................................................................. W indbracke, W ................................................................................... 120,445 566 W ong, F . ..................................................................................................... 551 W ood, S. C................................................................................................ 296, 528, 582, 851 Wortman, J. J ..................................... Xing, G. C ............................................................................................. 310,343 52 Yamabe, K ...............................................................................................
893
Yam aguchi, H ............................................................................................. 793 Yano, K ...................................................................................................... 183 Yasaitis, J. A .............................................................................................. 374 Yeakley, R.......................................................................................... 503,755 Yin, D ........................................................................................................ 503 Yoneda, K .................................................................................................. 421 Yoshino, H ............................................................................................ 861 Yu, C .................................................................................................... 627, 800 Zhang, B .................................................................................................... 851 Zhong, Y. L . ................................................................................................ 851 Zwicker, G .................................................................................................. 120
894
SUBJECT INDEX Ab-Initio Molecular Orbital ........................................................................ Ablation, Optical .......................................................................................
751 631
AC Conductance .........................................................................................
487
427 Acceleration Factor, Electric Field .............................................................. 489 Accumulation Capacitance ......................................................................... 155 Acid-Hardened Resist ................................................................................. 767 Actinometry ................................................................................................ 312 Activation Energy ...................................................................................... 740 Activation Solution ..................................................................................... 105 Adaptive Learning ...................................................................................... 153,203 Adhesion ............................................................................................ 483 Adm ittance Characteristics, Small Signal .............................................. 236 Adsorption .................................................................................................. 121 Advanced Drain Engineering ....................................................................... 423 AES Analysis ......................................................................................... 400 AFM ........................................................................................................... 343,635 Al ........................................................................................................ 739 Al Cladding ............................................................................................... 216 Al-Si-Cu .................................................................................................... 409 AI-Si0 2 M etallurgical Reaction ............................................................. AI-SiO 2 -Si M OS Devices ........................................................................ 402 751 Alcohol ..................................................................................................... 121 Alignment Accuracy, W afer ........................................................................ 851 Alloys, SixGea_x .......................................................................................... 343,635 Aluminum ........................................................................................... 470 Aluminum Gate ....................................................................................... 880 Amorphization .......................................................................................... 285 Amorphization Depth ............................................................................... 308 Amorphization, Ge ..................................................................................... 313, 346 Amorphous .......................................................................................... 312 Amorphous Phase ...................................................................................... 813 Amorphous Silicon ...................................................................................... 755 Anhydrous .................................................................................................. 236,252 Anisotropy ........................................................................................... 528 Annealing ................................................................................................... 285 Annealing of Defects ................................................................................... Annealing Techniques for Process-Induced Radiation .................................... 464 794 Annealing, Drive-In ................................................................................... 470 Annealing, High Pressure Thermal .............................................................. 470 Annealing, RF Plasma ................................................................................. 469 Annealing, Thermal .................................................................................... 769 Anodization ................................................................................................ Antenna Effects, Charge Sharing ............................................................ 473 473 Antennas, Polysilicon Gate ..................................................................... 421 Anti-Fuse .................................................................................................... 133,146 Anti-Reflection Coatings ...................................................................... 592 AP-TEOS ....................................................................................................
895
AP-TEOS/Ozone .........................................................................................
593
715 Aqueous Acidic M edia ................................................................................. Ar .......................................................................................................... 18,835 133 ARC ........................................................................................................... 835 Argon .......................................................................................................... 148 Argon Fluoride ............................................................................................ 720 Aspect Ratio ............................................................................................... 132 Astigmatism ............................................................................................... 592 Atmospheric Pressure TEOS ......................................................................... Atomic Fluorine .......................................................................................... 208 400 Atomic Force M icroscope .............................................................................. 470 Atomic Hydrogen ........................................................................................ 18, 713 Auger Analysis ...................................................................................... 296 B ................................................................................................................ B Diffusivity ........................................................................................... 13 15 B Diffusivity in Single Crystal Si ............................................................ 9 B-Doped Polysilicon .......................................... B-Ge Doped Si Membrane ............................................................................ 121 B2 0 3 . . . . ........................................................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .617 Ballistic Deposition Simulation ................................................................ 61 Band Gap .................................................................................................... 327 Barrier ................................................................................................ 343,635 324 Barrier Height, Schottky ............................................................................ Barrier Layer, TiN ...................................................................................... 628 795 Base Profile ................................................................................................ 46 BEBOP ..................................................................................................... BF 2 . . . ..................................................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 296,880 152 Bias Stress .................................................................................................. 602 Bias-Sputtered-Quartz ............................................................................... BiCM OS Device, Low-Voltage .................................................................. 5 BiCMOS Technology, Half-M icron ............................................................ 5 BiNCM OS Technology ............................................................................... 5 153 Biocompatability ....................................................................................... 5,655 Bipolar ................................................................................................ 566 Bipolar Poly-Emitter ............................................................................ 17,139 Bird's Beak ............................................................................................ Bit Line, Buried ...................................................................................... 28 Boltzmann-Based Carrier Transport ......................................................... 43 Bond .......................................................................................................... 237 838 Bond Energy ................................................................................................ 870 Bonded W afer Pairs .................................................................................... 296 Boron .......................................................................................................... 13,347 Boron Diffusion ...................................................................................... Boron Diffusivity in Single Crystal Si ..................................................... 15 880 Boron Difluoride ......................................................................................... Boron Penetration, Suppression of .............................................................. 9 617 Boron Trioxide ........................................................................................... 266 Boron-Doped Layer ..................................................................................... Boron-Doped Polysilicon ............................................................................ 9 17 Borosilic3te Glass Planarization ..............................................................
896
Bottom -Oxide ............................................................................................. 421 313,346 Boundary Diffusion .............................................................................. 315 Boundary Layer ......................................................................................... 642 BPSG .......................................................................................................... 31 Breakdown ............................................................................................... 402 Breakdown Events ...................................................................................... Breakdown M easurem ents of SiO 2 .................................... . . . . . . . . . . . . . . . . . . . . . . . . . .. . 448 17,458 Breakdown of Gate Oxide ...................................................................... 353 Breakdown of Oxides .................................................................................. 454 Breakdown Statistics ............................................................................. 409 Breakdown Strength, Dielectric ............................................................ 396 Breakdown, Charge to ................................................................................. 423, 724 Breakdown, Dielectric ......................................................................... 360 Breakdown, Oxide ..................................................................................... 358 Breakdown, Ram p Voltage .......................................................................... 396 Breakdown, Time Dependent ....................................................................... 394 Breakdown, Time Zero ................................................................................ ... . ........ 394 Breakdown, TZBD ............................. 359 Breakdown-W earout Com parisons .............................................................. 17 BSG Planarization ................................................................................... 602 BSQ .......................................................................................................... 566 Budget, Thermal ...................................................................................... 486 Bulk Silicon Traps .................................................................................. 28 Buried Bit Line ......................................................................................... 137 Buried Channel .......................................................................................... ............... ............................................. 354 C-V Analysis ............................ 11,423 C-V Characteristics, High Frequency .................................................... 392 C-V Characterization ................................................................................. 801,811 C-V M easurement ................................................................................. 592,602 C/M Polishing ..................................................................................... C 2 F 6 . . . . . ..................................................... . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 12,84 Capacitance ........................................................................................... Capacitance, Cell .................................................................................... 30 803 Capacitance, DRAM Cell ............................................................................ 354 Capacitance-Voltage Analysis .................................................................... 392,423 Capacitance-Voltage Characteristics ................................................... 801,811 Capacitance-Voltage M easurem ent ...................................................... 810 Capacitor Cells, 16 and 64 M bit DRAM ........................................................ 421 Capacitor Insulator ..................................................................................... 810 Capacitor Structures, Reliability ................................................................ 26 Capacitor, Stacked .................................................................................. 28 Capacitors ............................................................................................... Capacitors, DRAM , Electrical Characteristics ............................................. 800 391 Capacitors, M OS ......................................................................................... 567 Capacitors, PM OS ....................................................................................... 209 Carbonaceous M aterial ................................................................................ 149 Catalyst ..................................................................................................... 30 Cell Capacitance ..................................................................................... 800, 803 Cell Capacitance, DRAM ..................................................................... 78 Cell Design, DRAM ..................................................................................
897
Cells, 16 and 64 Mbit DRAM Capacitor .......................................................
810
Cells, Leakage Current in DRAM ................................................................. 803 266 Channel Doping .......................................................................................... 137,881 Channel Length ................................................................................... 296,881 Channeling .......................................................................................... 449 Characteristics, Transfer ............................................................................. Characterization ....................................................................................... 310 190 Characterization of I-Line Photoresist ........................................................ 447 Characterization of SiO 2 Gates ................................................................... 473 Charge Build-Up During Plasma Processing ................................................. 661 Charge Centroid ......................................................................................... 431 Charge Injection .......................................................................................... 451 Charge Pumping .......................................................................................... 183 Charge Reduction ........................................................................................ 473 Charge Sharing Antenna Effects .................................................................. 375,396 Charge to Breakdown ........................................................................... 183 Charge Transfer Complex ............................................................................ ................... .. 377,428,803 Charge Trapping ........................................... 183 Charge-Reducing Process ............................................................................. 358,359 Charge-to-Breakdown ......................................................................... 183 Charging of Resist ....................................................................................... 311,344 Chem ical Inertness ............................................................................... 276,503,528,582,692 Chemical Vapor Deposition ............................................. 566 Chemical Vapor Deposition, Rapid Thermal ..................... 592, 602,606,650 Chem ical-M echanical Polishing ............................................. 110,146 Chem ically Amplified Resists ............................................................. 153 Chem isorbed Films .................................................................................... 570 Chem istry, Silane .......................................................................................
CH F3 .. .. ...................................................
... ...... ..... ..... .... ..... ...... ..... ..... . . . .
18
236,440,730 Chlorine ....................................................................................... 236,440 Cl ........................................................................................................ C12 . . . ...................................................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209,730 739 Cladding, Al ............................................................................................... 568 Clean, Hydrogen ........................................................................................ 834 Cleaning ..................................................................................................... Cluster Tool M odeling and Economics ........................................................... 551 Cluster-Based Fabs ..................................................................................... 551 1,655 CM OS ..................................................................................................... 374 CM OS Devices, 0.5 gm ................................................................................. 49 CM OS Latchup ......................................................................................... ............... ................................. 131 CM OS Process, 0.5 M icrometer ............... 120 CMOS Ring Oscillator ................................................................................. CMOS Technology, Scaled ....................................................................... 44 120 CM OS, 0.4 pIn Test Circuit ........................................................................... 174 CM OS, 0.8 pm ............................................................................................. 17, 199,305 CM OS, Sub-Micron ......................................................................... 607, 650,651 CM P ............................................................................................. 254 Co-Silicide ................................................................................................. 149 Cobalt ........................................................................................................ 122 Cobalt Disilicide ........................................................................................
898
131 Cobalt Salicide ........................................................................................... 310 Cold Wall System ....................................................................................... 149 Colloidal Pd/Sn Catalyst ........................................................................... 885 Compensate ................................................................................................ Complementary BiCMOS .......................................................................... 5 14 Complementary Error Function ................................................................. 681 Compound Semiconductors ........................................................................... 445 Condensed Matter, Electronic Structure ........................................................ 445 Condensed M atter, Optical Properties ......................................................... 31 Conduction ............................................................................................... 813 Conduction, Poole-Frenkel ........................................................................... 311,344 Conductivity ........................................................................................ 739 Conductor Pattern Formation ....................................................................... 359 Constant-Voltage Stressing ......................................................................... 148 Contact Printing .......................................................................................... 254,328 Contact Resistance......................................... 276 Contact, Ohmic .......................................................................................... 28 Contacts .................................................................................................. 151,861 Contamination ..................................................................................... 541, 574 Control of Temperature ........................................................................ 110 Copolymer Backbone ................................................................................... 112 Copolymer M olecular Properties .................................................................. 149 Copper ........................................................................................................ 667 Copper-Interconnect .................................................................................... 325 Copper-Silicon Contact ............................................................................... 745 Corrosion Resistance .................................................................................... CoSi 2 .. . ....................................................... .. ..... .... ..... .. ... ...... ..... ..... .... ..... ..122 551 Cost Modeling of Semiconductor Fabs .................................. 244 Cryogenic Etching ....................................................................................... 183 Crystal Growth, TCNQ ............................................................................... 795 Crystalline Imperfection ............................................................................. 343 Cu ............................................................................................................... 216 Cu Residue .................................................................................................. .... ....................................... 667 Cu-Interconnect ........................................... 325 Cu-Si Contact .............................................................................................. 712 Cu/PPQ ..................................................................................................... 414 Cumulative Probability of Failure ............................................................... 648 Cure Time of SOG ....................................................................................... 216 Current Density, Ion .................................................................................... Current Distribution, 3D .......................................................................... 49 813 Current, Leakage ......................................................................................... 423,811 Current-Voltage Characteristics .......................................................... 433 C-V ....................................................................................................... 276,503,528,532,534,582,692 CVD ................................................................... 650 CVD Oxide ................................................................................................. 720 CVD SiO 2 , Plasma-Enhanced ..................................................................... 566,851 CVD, Rapid Thermal .......................................................................... Cylindrical Tube Based Rapid Thermal Processor ........................................ 582 401 Czochralski Si W afers ................................................................................ 834 Damage ......................................................................................................
899
285 Dam age Rem oval ........................................................................................ 473 Damage, Gate Oxide ................................................................................... 34,39 Dam age, Implantation ............................................................................ 664 Dangling Bonds ........................................................................................... 78 Data Representations ............................................................................... 43 DD System ................................................................................................ Deactivation of Dopants ........................................................................ 488 5 Deep Subm icron ........................................................................................... 147 Deep UV .................................................................................................... 131 Deep UV Excimer Laser Stepper .................................................................. 110, 145,155 Deep UV Lithography .................................................................. 285 Defect Annealing ........................................................................................ 395 Defect Density ............................................................................................ Defect Distribution ..................................................................................... 495 Defect Generation .................................................................................. 465 384 Defect Related Breakdown .......................................................................... 483 Defect States .............................................................................................. 413 Defect-Induced Dielectric Breakdown ..................................................... 41 Defects, Extended .................................................................................... 34,84 Defects, Point.......................................................................................... 179 Degradation, Hot Carrier ............................................................................ 602 Dep/Etch Cycles ........................................................................................ 720 Dep/Etch Process ........................................................................................ 12 Depletion Layer ....................................................................................... 314 Depletion of Input Gases .............................................................................. 315 Deposition Efficiency .................................................................................. 312 Deposition Kinetics ..................................................................................... 801 Deposition of Polysilicon ............................................................................. 740 Deposition Solution ..................................................................................... 695 Deposition Temperature .............................................................................. 468 Deposition, E-Gun and Sputter ..................................................................... Deposition, In-Situ ..................................................................................... 567 810 Deposition, Polysilicon ............................................................................... 851 Deposition, Selective ................................................................................. 607 Deposition-Etch-Deposition Technique ........................................................ 206 Deposition/Etching, Plasma ....................................................................... Depth of Amorphization ............................................................................. 285 133 Depth of Field ............................................................................................ 120,132, 145,606 Depth of Focus ........................................................................ 871 Depth Profile, SIM S ................................................................................... 1 Design ........................................................................................................... 78 Design, DRAM Cell .................................................................................. 598 Desorbed Gas .............................................................................................. 208 Detection of End-Point ................................................................................ 398 Detrapping, Electron ................................................................................... 191 Developer ................................................................................................... 1 Device Design ................................................................................................ 881 Device Lifetime ............................................................ 624 Device Perform ance ................................................................................... 43 Device Scaling ......................................................................................... 78 Device Simulation ..................................................................................
900
Device Simulation Grid ...........................................................................
81
Device Simulators ................................................................................... 43 Devices, CM OS, 0.5 rm................................................................................ 374 Devices, M OS ...................................................................................... 363,464 124 DIBL .......................................................................................................... Dielectric ................................................................................................... 592 Dielectric Breakdown ...................................................... 374, 385, 401, 423, 724 Dielectric Breakdown Fields, Histogram of ................................................. 413 Dielectric Breakdown Histogram ................................................................ 425 Dielectric Breakdown of Gate Oxide ......................................................... 17 Dielectric Breakdown of Si02 ...................................... . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . . 697 Dielectric Breakdown Strength .............................................................. 409 Dielectric Breakdown, Ramped-Field M ethod ............................................. 409 Dielectric Breakdown, Stepped-Field Method .................... 409 Dielectric Constant .............................................................................. 692, 724 Dielectric Degradation ............................................................................... 418 Dielectric Deposition .................................................................................. 593 Dielectric Engineering ................................................................................. 569 Dielectric Integrity ..................................................................................... 374 Dielectric Properties of M aterials ............................................................ 445 Dielectric Reliability .......................................................................... 421,803 Dielectric Strength .............................................................................. 395,692 Dielectric, O /N ..................................................................................... 29,801 Dielectric, Reoxidized Nitride .................................................................... 801 Dielectrics, Gate ......................................................................................... 363 Dielectrics, Ultrathin SiO 2 Gate ................................................................. 445 Diethylsilane, Pyrolysis of ........................................................................ 841 Diffusion ................................................................................ 296, 313, 346,347 Diffusion Barrier ........................................................................................ 343 Diffusion Coefficients, Interstitial and Vacancy ...................................... 52 Diffusion M odel, Point-Defect ................................................................. 52 Diffusion of Oxygen ..................................................................................... 871 Diffusion Source for Boron ............................................................................ 296 Diffusion, Dopant .................................................................................... 34 Diffusion, Extrinsic .................................................................................. 41 Diffusion, Oxidation Enhanced ................................................................ 34 Diffusion, Transient Enhanced ................................................................. 34,39 Diffusivity of B in Single Crystal Si .......................................................... 15 Diluted Oxidation Technique ...................................................................... 391 Dipolar Structure ........................................................................................ 500 Disintegration of Oxide Layer ..................................................................... 871 Distortion ................................................................................................... 132 DM SDM A ................................................................................................. 155 Dopant Diffusion ................................................................................... 34,793 Dopant Profiles ........................................................................................... 336 Doped Polysilicon, Phosphorus .................................................................... 803 Doping Effects, Substrate ............................................................................. 357 Doping Profile, Retrograde ......................................................................... 122 Dosage ........................................................................................................ 148 Dose, Oxygen .............................................................................................. 568
901
Double Layer, Electrical ............................................................................. 749 Double Level M etallization ...................................................................... 17 Double-Level Interconnect ........................................................................... 730 Drain Current .............................................................................................. 379 Drain Engineering ....................................................................................... 121 Drain Induced Barrier Lowering ................................................................... 124 DRAM ................................................................................................. 422, 785 DRAM Analysis ....................................................................................... 83 DRAM Capacitors, Electrical Characteristics .............................................. 800 DRAM Cell Capacitance ...................................................................... 800,803 DRAM Cell Design .................................................................................. 78 DRAM Cells, 16 and 64 M bit ........................................................................ 810 DRAM Cells, Leakage Current ............................... 803 DRAM 's .................................................................................................. 26 DRAM , 16 M egabit ...................................................................................... 617 DRAM s, 64 M bit ....................................................................................... 33 Drift Diffusion System ............................................................................ 43 Drive-In Annealing ..................................................................................... 794 Dry Etching ............................................................................................. 18 Dry Etching Si/SiO2 ........................................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Dry Oxidation ............................................................................................ 423 Dummy Pattern ........................................................................................... 596 E-Beam Lithography .................................................................................. 466 E-Gun Deposition ........................................................................................ 468 ECL ........................................................................................................... 5 Economic Modeling of Semiconductor Fabs .................................................... 551 Econom ics of Cluster Tools ............................................................................ 551 ECR .......................................................................... 216, 236, 244, 602, 607,834 ECR Plasma ................................................................................................ 765 EEPROM ................................................................................................ 422 Effective Channel Length ............................................................................ 881 Eg Center .................................................................................................... 493 Elastic Recoil Detection Analysis ................................................................ 715 Electric Field .............................................................................................. 881 Electric Field Acceleration Factor ................................................................ 427 Electrical Characteristics of DRAM Capacitors ........................................... 800 Electrical Characterization of Si0 2 Gates .................................................... 448 Electrical Conductivity ........................................................................ 311,344 Electrical Double Layer ............................................................................... 749 Electrical Field Distribution ....................................................................... 741 Electrical Interconnects ................................................................................ 678 Electrical Properties of Gate Oxides ............................................................ 400 Electrical Properties of Interfaces ................................................................ 445 Electrical Properties of Surfaces .................................................................. 445 Electrical Properties of Thin Films .............................................................. 445 Electrochem ical Effects of HF...................................................................... 712 Electroless Deposition ................................................................................. 145 Electroless M etal Deposition ....................................................................... 739 Electroless Plating ...................................................................................... 149 Electromigration Failure ............................................................................ 632
902
101,183,466 Electron Beam Lithography .......................................................... 216,236,244,385,602 Electron Cyclotron Resonance ............................................ 765 Electron Cyclotron Resonance Plasma ........................................................... Electron Density .....................................................................................
Electron Injection ...........................................................................
49, 751
433,880,881
494 Electron Injection, Optically Assisted .......................................................... 500 Electron Spin ............................................................................................ 502 Electron Spin Resonance ............................................................................... Electron Storage Ring .............................................................................. 88 398 Electron Trapping and Detrapping ............................................................... Electron-Gun Deposition ........................................................................ 468 Electron-Hole Recombination .................................................................. 499 Electronic Structure of Condensed M atter...................................................... 445 445 Electronic Structure of Interfaces .................................................................. 445 Electronic Structure of Surfaces .................................................................... 445 Electronic Structure of Thin Films ................................................................ 467 Electrons ................................................................................................. 541,574 Ellipsometry ........................................................................................ Emissivity..................................................................................................528 529 Emissivity of Si .......................................................................................... 795 Em itter Profile ............................................................................................ 568 Emitter Resistance ..................................................................................... Emitter-Coupled Logic .............................................................................. 5 655 Encroachment .............................................................................................. 179 End-of-Life Test .......................................................................................... 208 End-Point Detection .................................................................................... 657 Endurance ................................................................................................... 216 Energy Distribution, Ion .............................................................................. Engineering, Dielectric ............................................................................... 569 570 Engineering, Interface .................................................................................. 880 Enhanced Degradation ................................................................................ 34 Enhanced Diffusion, Oxidation ................................................................ 34,39 Enhanced Diffusion, Transient ................................................................. Enhanced Physical Models ...................................................................... 46 305 Enhanced Silicide Formation ...................................................................... Enhancement of M iscibility ...................................................................... 230 305 Epi Growth, Selective ................................................................................ 306 Epitaxial Silicon ..................................................................................... 755,834 Epitaxy ............................................................................................... Equivalent Circuit Diagrams .................................................................. 486 715 ERDA ......................................................................................................... ESR ........................................................................................................... 502 607 Etch Back of Resist ..................................................................................... 250 Etch Mechanisms ........................................................................................ 248 Etch Profiles ............................................................................................... 648 Etch Rate and Selectivity of SOG:BPSG ...................................................... Etch-Back of Spin-On-Glass .................................................................... 17 596 Etchback Planarization ............................................................................... 236,244 Etching ................................................................................................ Etching Si/SiO2 .............................................. ..... ..... ...... ... ...... ..... ..... .... .... .208
903
Etching, Reactive Ion and Plasma ............................................................ 466 206 Etching/Deposition, Plasma ....................................................................... 752 Ethanol, 2-Amino ........................................................................................ 199 Evaluation of I-Line Photoresist .................................................................. 61 Evaporation M odeling .............................................................................. 800 Excimer Laser Processing .............................................................................. 131 Excimer Laser Stepper, 248 nm ..................................................................... 785 Experimental Design ................................................................................... Experimental Simulation of Radiation Effects ............................................. 471 446 Experimental Wafer Processing ................................................................... 193 Exposure ..................................................................................................... 120 Exposure Field Size ..................................................................................... 90 Exposure System ...................................................................................... 606 Exposure Tools ............................................................................................. 41 Extended Defects ...................................................................................... 44 Extrinsic Device Effects ............................................................................. 41 Extrinsic Diffusion .................................................................................. 440 F ................................................................................................................. 551 Factory Performance Simulation ................................................................. 32 Failure ..................................................................................................... 12 Fermi Level ............................................................................................. 402 Field Enhancement ...................................................................................... Field Oxide, Quasi-Recessed .................................................................. 17 722 Filaments ................................................ 312 Film ........................................................................................................... 801,811 Film Reflectance .................................................................................. ................. .................................. 153 Film s........ ..................... Films, Thin SiO2 .............................................. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391 770 Fixed Charge .............................................................................................. 493 Fixed Positive Charge ............................................................................ 11,569 Flatband Voltage ................................................................................... 376 Flatband Voltage Shift ............................................................................... 216 Flight Direction, Ion ................................................................................. 401 Float Zone Si W afers .................................................................................. 870 Float Zone Silicon ....................................................................................... 314 Flow Rate ................................................................................................... 434,440 Fluorine ............................................................................................... 208 Fluorine, Atomic ......................................................................................... 145,193 Focus ................................................................................................... 135 Focus Latitude ............................................................................................. 148 Fourier Transform Mass Spectrometry .......................................................... 393,402,409 Fowler-Nordheim Tunneling ......................................................... 422 FPGA ...................................................................................................... 870 Free Energy of System .................................................................................. 820 Fundamental M odel .................................................................................... 401 FZ Si Wafers ......................................................................................... 870 FZ Silicon ................................................................................................... 678 GaAs .......................................................................................................... 568 Gain, Transistor .......................................................................................... 678 Gallium Arsenide ........................................................................................
904
592,619 Gap Filling .......................................................................................... 720 Gap-Fill ..................................................................................................... 493 Gate Bias .................................................................................................... 881 Gate Current ............................................................................................... 374 Gate Dielectric Integrity ............................................................................. 363 Gate Dielectrics .......................................................................................... 363 Gate Dielectrics, Ultrathin MOS ................................................................ Gate Dielectrics, Ultrathin Si02 ................................... ......... .......... ........... 445 494 Gate Insulator ......................................................................................... 152,432,881 Gate Oxide ................................................................................... 17,458 Gate Oxide Breakdown .................................... Gate Oxide Damage, Plasma Processing ................................................. 473 454,483 Gate Oxides ......................................................................................... 400 Gate Oxides, Electrical Properties of .......................................................... Gate, Aluminum and Polysilicon .............................................................. 470 566 Gate, MOS .................................................................................................. Gates, Electrical Characterization of SiO2 .......................... ..... ..... ..... .... ..... 448 Gates, Structural Characterization of SiO 2 .......................... .... ...... ... .. .... ..... 447 880 Ge ............................................................................................................... 308 Ge Amorphization ...................................................................................... 254 Ge-Preamorphization ................................................................................. 500 Generation Mechanism .............................................................................. Generation of Defects ............................................................................ 465 851,880 Germanium .......................................................................................... 607 Glass Polishing ........................................................................................... 110 Glass Transition Temperature ...................................................................... 606 Global Planarity ......................................................................................... 15,793,798 Grain Boundary ............................................................................... 313,346 Grain Boundary Diffusion ..................................................................... 571 Grain Size ................................................................................................... 134 Grain Structure of Polysilicon ...................................................................... 149 Grass .......................................................................................................... 132 Gratings ...................................................................................................... Grid for Device and Process Simulation ...................................................... 81 45 Grid Points .............................................................................................. 723 Growth Seams ............................................................................................. 851 Growth, Three Dimensional ........................................................................ 838 H2 Addition ............................................................................................... H 20 2 .... ....................................................... .... ..... ..... ..... ..... ...... .... ..... ..... ...400 H 2 SiF 6 ... ...................................................... ..... .... .. ..... ..... ...... ...... ..... ..... .... 226 Half-M icron BiCMOS Technology .............................................................. 5 137 Halo Effect ................................................................................................ 174 Halo LLD Device ........................................................................................ 194 Hardbake ................................................................................................... 48 HBT, Sil.xGe ........................................................................................... 715 HCI ............................................................................................................ 306 HCI-H 2 Etch ............................................................................................... 503 Heating Lamps, M ulti-Zone ........................................................................ 155 Henry's Law ............................................................................................... 48 Hetero-Bipolar Transistor ....................................................................... 905
HF ....................................................................................................... 712,755 HF/H 2 0 Vapor .......................................................................................... 226 High Frequency C-V Characteristics ........................................................... 423 High Pressure Thermal Annealing ............................................................... 470 High Resolution Transmission Electron Microscopy ................. 870 High-Frequency C-V Characteristics ............................................................ 11 High-Performance ...................................................................................... 667 Hillock Formation ...................................................................................... 741 Histogram of Dielectric Breakdown ...................................................... 425,413 HM DS ........................................................................................................ 114 Hole ........................................................................................................... 425 Hole Capture Cross-Section ......................................................................... 484 Hole M ean Free Path ........................................................................... 880,885 Hole Transport ............................................................................................ 494 Hole Trapping ..................................................................................... 428,569 Hole Traps .................................................................................................. 493 Hot Carrier Degradation ..................................................................... 179,431 Hot Carrier Effects ...................................................................................... 121 Hot Electron Degradation ..................................................................... 437,438 Hot Electron Lifetime .................................................................................. 433 HR-TEM ..................................................................................................... 870 Hydration of Silicon Dioxide ...................................................................... 696 Hydrocarbon Fragments ............................................................................... 209 Hydrodynamic Model .............................................................................. 46 Hydrofluoric Acid ....................................................................................... 712 Hydrogen Annealing ................................................................................... 469 Hydrogen Clean ......................................................................................... 568 Hydrogen Fluoride ...................................................................................... 755 Hydrogen, Atomic ....................................................................................... 470 Hydrogenation ............................................................................................ 491 I-Line .................................................................................................. 190,199 I-V Characteristics ..................................................................................... 423 I-V Characteristics of NM OS Devices ......................................................... 378 I-V Measurements ....................................................................................... 811 Idealty Factor ............................................................................................. 323 IGFET ......................................................................................................... 493 Imaging ..................................................................................................... 145 Impact ........................................................................................................ 440 Impact Ionization ................................................................................. 881,885 Imperfection, Crystalline ........................................................................... 795 Implantation .............................................................................................. 794 Implantation Damage ............................................................................. 34,39 Impurities in Silicon Dioxide ....................................................................... 694 Impurity Content ......................................................................................... 454 Im purity Redistribution ............................................................................ 52 In Situ Dry Cleaning .................................................................................... 755 In-Situ Baking ............................................................................................ 600 In-Situ Deposition ...................................................................................... 567 In-Situ Doped Polysilicon ............................................................................ 785 In-Situ Fabrication ...................................................................................... 503
906
In-Situ M ultiprocessing ............................................................................... 582 Incident-Angle-Dependent Etch Rate ........................................................... 602 Incubation Tim e .......................................................................................... 312 Index of Refraction ...................................................................................... 694 Indium Phosphide ....................................................................................... 678 Inertness .............................................................................................. 311,344 Infrared Spectroscopy .................................................................................. 692 Injection ...................................................................................................... 881 Injection of Point-Defects ........................................................................... 52 InP .............................................................................................................. 678 Instability .................................................................................................. 861 Integrated Circuits ............................................................................... 667,671 Integrated Optoelectronic Circuits ............................................................... 679 Integrated Processing ............................................................................... 566 Integration, Tool ....................................................................................... 78 Integrity of Lightly Nitrided Oxide ............................................................ 374 Integrity, Intrinsic .......................................................................................
567
Inter-Polysilicon Insulator ........................................................................... 421 Interconnections, M ultilevel ........................................................................ 739 Interconnects ........................................................................................ 153, 730 Interface Engineering ................................................................................... 570 Interface Flatness ........................................................................................ 400 Interface State Changes, M idgap ................................................................. 376 Interface State Density ................................................................. 484, 662, 770 Interface States ........................................................................................... 436 Interface Structure .................................................................................. 429 Interface Traps ..................................................................................... 355,465 Interface, User ......................................................................................... 80 Interfaces, Electronic Structure ..................................................................... 445 Interracial Oxide ...................................................................................... 568 Interracial Si02 ............................................... ..... ..... ..... ..... ...... ..... .... ..... ...870 Interlevel Dielectrics, Polishing of .............................................................. 606 Intermediate Frequency .............................................................................. 488 Interstitial Diffusion .............................................................................. 52 Interstitial Oxygen ................................................................................ 870 Interstitial Surface Recombination ........................................................... 36 Intrinsic Breakdown .............................................................................. 402 Intrinsic Dielectric Breakdown .................................................................. 413 Intrinsic Integrity ........................................................................................ 567 Intrinsic Layer ............................................................................................ 489 IOC ............................................................................................................ 679 Ion Beam Hydrogenation ........................................................................ 491 Ion Bombardment ........................................................................................ 837 Ion Current Density .............................................................................. 247,216 Ion Energy ................................................................................................... 836 Ion Energy Distribution ................................................................................ 216 Ion Flight Direction .................................................................................... 216 Ion Implantation ......................................................................................... 285 Ion-Beam -Induced Damage ................................................................... 483,491 Ionization Rate ........................................................................................... 881
907
Ionizing Radiation Effects, Processed-Induced ......................................... 464 Ions ......................................................................................................... 467 Isolated Features ........................................................................................ 132 Isolation Technique ................................................................................... 17 Isolation, Trench .................................................................................... 5,650 Isotherm al .................................................................................................. 825 Isotropic Etch .............................................................................................. 207 JFET ............................................................................................................ 682 Junction Depth ..................................................................................... 308,881 Junction Diode ............................................................................................. 266 Junction Field Effect Transistor .................................................................... 682 Junction Formation, Shallow ................................................................. 285,296 Junction Leakage ....................................................................................... 17 Junction Profiling by SIM S ........................................................................... 332 Junction, Shallow ................................................................... 276, 793,305,880 Junctions, Shallow Silicided ........................................................................ 254 Kinetic Parameters .............................................................................. 825,826 Kinetics ...................................................................................................... 312 Krypton Fluoride ........................................................................................ 148 Lamps, M ulti-Zone Heating ........................................................................ 503 Langmuir .................................................................................................... 236 Langmuir Probe ........................................................................................... 768 Langm uir-Blodgett Film s ............................................................................ 147 Laser Planarization ............................................................................. 627,635 Laser Processing, Excimer ............................................................................. 800 Lasers .................................................................................................. 148,681 Latch Up Hardness ..................................................................................... 122 Latchup Simulations ................................................................................. 45 Lateral Diffusion of Oxidant Species ........................................................ 17 Latitude ..................................................................................................... 193 Lattice Strain ...................................................................................... 880,885 LDD ........................................................................................................... 137 LDD Device, Halo ...................................................................................... 174 Leakage .................................................................................................... 31 Leakage Current ...................................................................... 254,421,632,813 Leakage Current in DRAM Cells .................................................................. 803 Leakage Current in Oxides ..................................................................... 409 Lens Distortion ............................................................................................ 132 Leveling Length .......................................................................................... 650 Lifetim e ........................................................................................ 32,152,881 Lifetime, M inority Carrier ......................................................................... 393 Liftoff ..................................................................................................... 61 Liftoff M etal Patterning .............................................................................. 177 Liftoff Process ............................................................................................. 135 Lightly Doped Drain Device, Halo ............................................................. 174 Lightly Nitrided Oxide, Integrity of ........................................................... 374 Lightly-Doped Drain .................................................................................. 137 Linear Rate Coefficient ............................................................................... 769 Linewidth .................................................................................................. 132 Linewidth Control ...................................................................................... 121 Linewidth M easurements ............................................................................ 164 908
Lithographic Performance of PTBSS Resist .................................................. 114 Lithography ....................................................................................... 101,145 110,131 Lithography, Deep UV ....................................................................... Lithography, E-Beam and X-Ray ............................................................
466
Lithography, X-Ray ..................................................................................
110
Loading Effect ......................................................................................... 620 Local Loading Effect .................................................................................... 596 Local Oxidation of Silicon ........................................................................ 17 Local Planarization .................................................................................... 607 Lock-In Detection ............................................... 208 LOCOS .......................................................................................... 17,139,775
LOPOS .......................................................................................................
775
Low Density Region ..................................................................................... 722 Low Energy Electron Beam s.......................................................................... 153 Low Frequency Dispersion ....................................................................... 489 Low Pressure Chemical Vapor Deposition .................................................... 310 Low Pressure CVD Tube ............................................................................... 571 Low Temperature ................................................................................... 83ft Low Temperature Etching ........................................................................... 244 Low Temperature Oxidation of Silicon ......................................................... 765 Low Temperature Oxide .............................................................................. 841 Low Temperature Thermal Annealing .......................................................... 491 Low-Field Breakdown Events .................................................................. 402 Low-Tem perature Cleaning ......................................................................... 755 Low-Voltage BiCM OS Device .................................................................... 5 LPCVD .................................................................................... 10,310,785,820 LPCVD of SiO2 ............................................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .841 LPCVD Tube ............................................................................................... 571 LSI ............................................................................................................. 749 M agnetron-Enhanced RIE ............................................................................ 730 M ask Distortion ................................................................................... 121,122 M asks .................................................................................................. 152, 153 M ass Spectrometry ...................................................................................... 148 M aterials for Optical Interconnects .............................................................. 678 M aterials, Dielectric Properties .............................................................. 445 M aximum Electric Field .............................................................................. 881 M BE ........................................................................................................... 682 M ean Free Path .......................................................................................... 880 M ean Free Path of Hole ............................................................................... 885 Measurement of Temperature ................................................................ 541,574 M echanical Polishing, Planarization by ..................................................... 606 M echanical/Chem ical Polishing ............................................................... 650 M echanism of Particle Generation .............................................................. 229 M echanism s of Radiation Effects ............................................................ 464 M embrane Experim ents ............................................................................ 38 M embrane, Polysilicon ............................................................................ 27 M emories ................................................................................................. 26 Mercury Lamp ............................................................................................. 148 M ESFET ...................................................................................................... 682 739 M etal Deposition, Electroless ......................................................................
909
M etal Im purity Analysis ............................................................................. Metal Organic Chemical Vapor Deposition .................................................
456 682
M etal Patterning, Liftoff .............................................................................
177
M etal-Silicon Contact .................................................................................
321
627 M etallization ............................................................................................. M etallization Resistance ............................................................................ 745 M etallization, 0.8 lrm .................................................................................. 606 Metallurgical Reaction of Al with SiO2 .............................. . . . . . . . . . . . . . . . . . . . . . .. . .409 M etallurgical Stability .............................................................................. 343 Methodology, I-Line Process Development ................................................... 192 M etrology ........................................................................................... 132, 164 M icro-Pattern ............................................................................................. 183 M icro-Ram an Spectroscopy ......................................................................... 775 Stress .......................................................................................................... 775 M icro-Roughness of Si W afers ..................................................................... 400 M icrowave Plasma ............................................................................... 207,765 M idgap Interface State Changes .................................................................. 376 M ie Scattering ............................................................................................ 208 M inority Carrier Lifetime ........................................................................... 393 M iscibility Enhancement ............................................................................. 230
MNOS Devices ........................................................................................... Mo .............................................................................................................. M obility .................................................
657 730 885
M OCVD .................................................................................................... 682 Model .................................................................................................. 820,825 Modeling .................................................................................................... 582 Modeling of Cluster Tools ............................................................................ 551 M ODFET .................................................................................................... 681 M odulating Plasma Conditions .................................................................... 206 Modulation Transfer Function ...................................................................... 146 Moisture Absorption .................................................................................... 620 Moisture Content ......................................................................................... 598 M ole Ratio Dependence ............................................................................... 228 M olecular Beam Epitaxy ............................................................................. 682 Molybdenum ............................................................................................... 730 M onolayer Films ......................................................................................... 145 M onte Carlo M odel ................................................................................... 47 M onte Carlo Simulation .............................................................................. 139 M orphology, Surface ......................... ........... ................................. 570,851 M OS Capacitor ....................................................................... 151,266,391,409 M OS Capacitor Yield ............................................................................. 462 M OS Devices ................................................................................ 363,464,861 M OS Devices, AI-Si0 2 -Si ...................................................................... 402 MOS Devices, Radiation Effects in .............................................................. 464 M OS Diode ............................................................................................. 10 M OS Gate ................................................................................................... 566 M OS Gate Dielectrics, Ultrathin ................................................................. 363 M OS Structures ........................................................................................... 483 MOSFET .................................................................................................... 266 M ulti-Layer Resist ..................................................................................... 246
910
M ulti-Point Temperature Sensors ................................................................. M ulti-Zone Heating Lamps ........................................................................
503 503
M ultilevel Interconnections ......................................................................... 739 M ultiprocessing ........................................................................................... 582 820 M ultiwafer LPCVD ..................................................................................... N' Polysilicon .................................................................................... 216,236 N-Doped Silicon ....................................................................................... 9 N 2 . . . . . . ......................................................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 N 2 -Gas Seal Processing ............................................................................... 322 N 2 0, RTP of Si in ........................................................................................ 363 Na Ions ....................................................................................................... 861 Native Oxide ...................................................................................... 321,836 Native-Oxide Removal .............................................................................. 755 Near Surface Imaging ........................................... 146 Necking ...................................................................................................... 200 Neural Network Training ............................................................................ 105 Neural Networks ........................................................................................ 101 Neutral Electron Traps .......................................................................... 493 Neutral Traps ............................................................................................. 465 NF3 . . . . . ........................................................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .730 NH 3 ..................................................... . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .10,207 N H 4 Cl ........................................................................................................ 713 N H 4 OH .................................................................................................. 400 Ni-Cu Pillars ............................................................................................ 739 Nickel ........................................................................................................ 149 Nitrous Oxide ............................................................................................. 658 Nitridation ......................................................................................... 374,569 Nitride ................................................................................................... 28 Nitride Dielectric, Reoxidized .................................................................... 801 Nitride Formation, Surface ......................................................................... 207 Nitride Oxidation ...................................................................................... 421 Nitride Sidewall Protection ........................................................................ 208 Nitride, Oxidized ..................................................................................... 27 Nitride/Oxide/Nitride Trilayer ............................................................. 17 Nitrided Oxide ........................................................................................... 374 Nitrogen ..................................................................................................... 236 Nitrogen-Doped Silicon ............................................................................ 9 Nitrogen-Gas Seal Processing ..................................................................... 322 NM OS ................................................................................................. 137,655 NM OS Devices, I-V Characteristics ............................................................ 378 NM OS Transistors ....................................................................................... 120 NM OS-CM OS Spacings ........................................................................... 45 No Etchback SOG .............................................. 642 Non-Etchback ............................................................................................. 598 Non-Etchback SOG .................................................................................... 592 Non-Ionic Surfactant................................................................................... 752 Non-Isothermal .......................................................................................... 826 Notching .................................................................................................... 200 Novolak ..................................................................................................... 146 Nuclear Analysis ..................................................................................... 18
911
Nucleation .................................................................................................. Nucleation Layer ........................................................................................
571 620
O/N Dielectric ........................................................................................ 29 18,209 02 .......................................................................................................... 391 0 2 -Diluted Oxidation Technique ................................................................. 695 0 2 /TEOS Flow Ratio ................................................................................... 276 Ohmic Contact ............................................................................................ 801,811 ON Dielectric ...................................................................................... 421 ON Stacked Film ........................................................................................ 375 ONO .......................................................................................................... 421 ONO Stacked Film ..................................................................................... 631 Optical Ablation ........................................................................................ 730 Optical Emission ......................................................................................... 678 Optical Interconnects ................................................................................... 445 Optical Properties of Condensed M atter ....................................................... Optically Assisted Electron Injection ..................................................... 494 310 Optimization .............................................................................................. 191 Optimization of I-Line Photolithography ................................................... 717 Organic M edia ............................................................................................ 244 Organic Photoresist ................................................................................... 749 Organic Solvent .......................................................................................... 147 Organosilane .............................................................................................. 121 Overlay Control .......................................................................................... 120 Overlay of Lithography Levels ................................................................... Oxidant Species, Lateral Diffusion of ...................................................... 17 28, 765 Oxidation .............................................................................................. 34 Oxidation Enhanced Diffusion .................................................................. 421 Oxidation of Nitride .............................................................................. 423 Oxidation, Dry ...................................................................................... 391 Oxidation, 0 2 -Diluted Technique ................................................................ 421 Oxidation, Pyrogenic Steam ................................................................... 151 Oxide ......................................................................................................... 353, 360,409,473 Oxide Breakdown ................................................................... 435,465 Oxide Charge ..................................................................................... 473 Oxide Charging .................................................................................... Oxide Dielectric Constant ...................................................................... 489 871 Oxide Layer Disintegration ......................................................................... 409 Oxide Leakage Current ................................................................................ 607 Oxide Reflow .............................................................................................. 353,360 Oxide Reliability ................................................................................ 400 Oxide Surface Micro-Roughness ................................................................... 434,495 Oxide Thickness .................................................................................. 574 Oxide Thickness Measurement ..................................................................... 486 Oxide Traps ................................................................................................ 353,355,360 Oxide W earout ............................................................................. 473 Oxide Yield ........................................................................................... 568 Oxide, Interfacial ...................................................................................... 374 Oxide, Lightly Nitrided ............................................................................. 841 Oxide, Low Temperature ............................................................................. 321 Oxide, Native ............................................................................................
912
Oxidized Nitride ..................................................................................... Oxygen Diffusion ........................................................................................ Oxygen Dose .............................................................................................. Oxygen, Interstitial .................................................................................... Oxynitride .................................................................................................. Ozone ......................................................................................................... P + Gate.....................................................................................................
27 871 568 870 657 617 9
P-I Junction ................................................................................................. A89 Packaging ............................................................................................ 153,667 Packaging for Optical Interconnects ............................................................. 678 PADRE ................................................................................................... 46 PAG Resist Formulations ............................................................................. 110 Parabolic Rate Constant .............................................................................. 769 Parallel Plate Plasma Reactor .................................................................... 209 Parallel Processing ...................................................................................... 678 Parameters .......................................................................................... 825,826 Parasitic Resistance Reduction .................................................................... 122 Partial Differential Equation Formulation ............................................... 43 Partial Etchback ......................................................................................... 598 Particle Deposition ..................................................................................... 749 Particle Deposition, Prevention of ............................................................... 753 Passivation ................................................................................... 617,624,861 Pattern Formation, Conductor ...................................................................... 739 Patterning, Liftoff Metal ............................................................................. 177 Pd/Sn Catalyst ........................................................................................... 149 PDE Formulation ...................................................................................... 43 PE-CVD TEOS/Oxygen ............................................................................... 593 PEB ............................................................................................................ 110 PECVD ................................................................................................ 617,692 PECVD Si02 ................................................. .. ..... ..... ..... ...... .... ...... .... ..... .... 720 Penetration Depth ...................................................................................... 467 Performance of I-Line Photoresist ................................................................ 199 Permalloy ................................................................................................... 149 Phase ......................................................................................................... 312 Phase Shift Masks ...................................................................................... 152 Phosphorus-Doped Polysilicon ................................................................... 803 Photochemistry .......................................................................................... 153 Photocleavage ............................................................................................ 148 Photoionization Cross Section ...................................................................... 665 Photolytically Generated Acid ................................................................... 110 Photons ................................................................................................... 467 Photooxidation ........................................................................................... 147 Photoresist ............................................................................. 134,190,199,244 Photospeed ................................................................................................. 152 Piezoceramic Scanner .................................................................................. 164 Pillars, Ni-Cu ............................................................................................. 739 Pinholes ..................................................................................................... 151 PISCES ....................................................................................................... 139 Pitch Measurements .................................................................................... 164 Pits ............................................................................................................. 345
913
Placem ent Error ........................................................................................... 183 642 Planarity .................................................................................................... 606 Planarity, Global ....................................................................................... 592,617,635 Planarization ............................................................................... 606 Planarization by M echanical Polishing ....................................................... 17 Planarization of Borosilicate Glass .......................................................... 642 Planarization Process .................................................................................. 607 Planarization Range ........................................ 650,652 Planarization Rate .............................................................................. 146 Planarizing Layer ....................................................................................... 246, 765,834 Plasm a ......................................................................................... 206 Plasma Conditions, M odulating .................................................................. 473 Plasma Damage .......................................................................................... 466 Plasma Etching ........................................................................................... Plasma Etching Si/SiO 2 ..................................... . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . ... . . . . . 208 473 Plasm a Etching, Charge Build-Up During .................................................... 206 Plasm a Etching/Deposition ......................................................................... 473 Plasma Processing Gate Oxide Dam age ........................................................ 473 Plasma Processing, Charge Build-Up During ................................................ 206 Plasm a Processing, Time M odulated ............................................................. Plasm a Reactor, RF ............................................................................... 208 246 Plasm a Stream Characterization ................................................................ 473 Plasm a Stripping, Charge Build-Up During ........................................... 692 Plasma-Enhanced CVD ............................................................................... Plasma-Enhanced CVD Si02 ............. ............... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 176 PM GI .......................................................................................................... 137 PMOS ......................................................................................................... 567 PM OS Capacitors ........................................................................................ 120 PM OS Transistors ........................................................................................ 9,880 PM OSFETs .............................................................................................. 5 PNP Bipolar ............................................................................................. 49 pnpn Layouts ............................................................................................ POC13 . . . . ...................................................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 140 53 Point Defect Type ..................................................................................... 34,84 Point Defects ........................................................................................... Point-Defect Diffusion M odel .................................................................... 52 52 Point-Defects, Injectiqn of ....................................................................... 357 Polarity Independence of Wearout ............................................................... 607 Polishing of Glass ....................................................................................... 606 Polishing of Interlevel Dielectrics ............................................................... 652 Polishing Pad, Polyurethane ....................................................................... 606,650 Polishing, Chem ical-M echanical ........................................................ 606 Polishing, Planarization by M echanical ...................................................... 566 Poly-Em itter, Bipolar ............................................................................... 793 Polycrystalline Silicon ................................................................................ 296 Polycrystalline Silicon-Germ anium Alloys .................................................. 296 Polycrystalline SixGet.x Alloys ................................................................... 667,669 Polyim ide ............................................................................................ 741 Polyim ide Dielectric Layer ......................................................................... 680 Polym er Waveguides ..................................................................................
914
Polyphenylquinoxaline Polymer ..................................................................
712
528,567,570, 785,820 Polysilicon ....................................................................... 801,810 Polysilicon Deposition .........................................................................
Polysilicon Deposition Experiments .............................................................
824
Polysilicon Film .......................................................................................
17
Polysilicon Gate .......................................................................................... Polysilicon Gate Antennas ...........................................................................
470 473
820,821 Polysilicon LPCVD M odel .................................................................... Polysilicon Membrane .............................................................................. 27 803 Polysilicon Reflectance ............................................................................... Polysilicon Surface Roughness ..................................................................... 803 803 Polysilicon Texture ...................................................................................... 810 Polysilicon Texturization ...................................................................... 800 Polysilicon Texturization Technique ........................................................... 236 Polysilicon, n÷............................................................................................. 803 Polysilicon, Phosphorus-Doped ................................................................... 810 Polysilicon, Rugged ..................................................................................... 803 Polysilicon, Undoped .................................................................................. 712 Polysiloxane ............................................................................................... 750 Polystyrene Particle.................................................................................... 652 Polyurethane Polishing Pad ....................................................................... 424,813 Poole-Frenkel Conduction .................................................................... 722 Porous Region .............................................................................................. 712 Porous Silicon Formation ............................................................................. Positive Charge Annihilation ................................................................ 499 110 Positive Resist M aterials ............................................................................ 110 Post-Exposure Baking .................................................................................. 749 Potential, Zeta ........................................................................................... 249 Power Density ............................................................................................. 712 PPQ ........................................................................................................... 713 PPQ/Cr/Si .................................................................................................. 266, 285, 296,330 Preamorphization ................................................................... 254 Preamorphization, Ge and Sb ...................................................................... 139 PREDICT .................................................................................................... 315 Pressure ...................................................................................................... 753 Prevention of Particle Deposition ................................................................ 409 Probability for Breakdown .......................................................................... 176 Probamide 285 ............................................................................................. 164 Probe M icroscope ......................................................................................... 541,574 Process Control ..................................................................................... 432 Process Integration ...................................................................................... 551 Process Integration, Semiconductor .............................................................. 52 Process Modeling ....................................................................................... 5 Process M odularity ......................................................................................... Process Optimization of I-Line Photolithography ........................................ 191 52,78 Process Simulation .................................................................................. 81 Process Simulation Grid ............................................................................. Process Simulator, Three-Dimensional .................................................... 54 627 Process Window .......................................................................................... 464 Process-Induced Ionizing Radiation Effects .............................................. 800 Processing, Excimer Laser .............................................................................
915
Processing, Integrated ................................................................................. Processing, Single W afer ............................................................................. Processing, ULSI W afer ...............................................................................
566 503 464
Processing, Wafer ........................................................................................ 446 Profile ........................................................................................................ 201 Profile, Base and Emitter ............................................................................ 795 Profile, SIM S .............................................................................................. 871 Profiles, Dopant ......................................................................................... 336 Projection Printing ....................................................................................... 148 Projection Stepper ....................................................................................... 149 Proxim ity Effects ................................................................................. 101,132 PSG Films ............................................................................................... 53 PTBSS Resist............................ ..... . . . ............... ... ..................... 110 Pyramid Shaped Pits .................................................................................. 345 Pyrogenic Steam Oxidation .................................................................... 421 Pyrolysis of Diethylsilane .......................................................................... 841 Pyrolytic Decomposition ............................................................................. 841 Pyrometer ................................................................................................... 529 Q d ...................................................................................................... 375,396 Quantum-W ell Lasers ................................................................................. 681 Quasi-Recessed Field Oxide .................................................................... 17 Quasi-Stoichiometric Silicon Nitride ...................................................... 18 Radiation Dam age ................................................................................... 94 Radiation Effects in M OS Devices ........................................................ 464,467 Radiation Effects, Experimental Simulation ................................................ 471 Radiation Effects, Process-induced ............................................................... 464 Radiation, Ionizing ..................................................................................... 464 Radiation-Induced Damage,.......... .... . . ........ .......................... 120 Raman Spectroscopy .................................................................................... 775 Ram p Voltage Breakdown ........................................................................... 358 Ramped-Field Method for Dielectric Breakdown .................. 409 Rapid Therm al Annealing ....................................................... 266, 285, 307,330 Rapid Thermal Chemical Vapor Deposition.......................... .... 566,582 Rapid Thermal CVD ............................................................................ 582,851 Rapid Thermal Nitridation .................................................................... 17 Rapid Thermal Oxidation ............................................................. 391,503,582 Rapid Thermal Oxidation/Nitridation ....................................................... 363 Rapid Thermal Processing ...... ............... .......... 363,503,528,541,574 Rate of Planarization ........................................ :.................................. 650,652 RBS ............................................................................................................ 155 RBS Analysis .............................................................................................. 713 RC Delay .................................................................................................... 139 RCA Clean................ .................................... 454 Reactive Ion Etching ............................................................... 149, 308,466,730 Reactor, Single W afer ............................................................................... 693 Recombination, Electron-Hole ..................................................................... 499 Recom bination, Surface ........................................................................... 36 Recombination-Enhanced Annealing ............................................................ 471 Reflectance, Polysilicon .............................................................................. 803 Reflectance, Thin Film ......................................................................... 801,811
916
607 Reflow Techniques ..................................................................................... 382,493,813 Reliability .................................................................................. 353 Reliability of Thin Oxides .......................................................................... Reliability, Dielectric ......................................................................... 426,803 360 Reliability, Oxide ..................................................................................... Removal of Damage ................................................................................... 285 249 Removal Rate vs. Power Density ................................................................ 569 Reoxidation ............................................................................................... Reoxidized Nitride Dielectric............................... 801,811 375 Reoxidized Nitrided Oxide ......................................................................... Representations of Data .......................................................................... 78 207 Residence Time ........................................................................................... Resist ........................................................................................................ 246 Resist Chem istry ........................................................................................ 113 592,607 Resist Etchback .................................................................................... Resist M aterials, Chem ically Am plified .................................................... 110 183 Resist Process .............................................................................................. Resistance of M etallization ........................................................................ 741 254, 328 Resistance, Contact .............................................................................. 568 Resistance, Em itter .................................................................................... Resistivity, N-Doped Si .......................................................................... 12 Resolution .......................................... 132, 145, 191,200 541 Resolution of Temperature ........................................................................... 657 Retention .................................................................................................... 122 Retrograde Doping Profile ........................................................................... 470 RF Plasma Annealing ....................................... RF Plasma Reactor .................................................................................... 208 308,466,730 RIE .............................................................................................. 120 Ring Oscillator, CM OS ............................................................................... 800 Roughening Technique, for Polysilicon ......................................................... 803 Roughness of Polysilicon Surface ............................................................. 813 Roughness, Surface ..................................................................................... 266,285,307,330,541 RTA ....................................... RTCVD ...................................................................................................... 566 391,503 RTO ..................................................................................................... 363 RTO/RTN .................................................................................................. 363, 503, 528, 532, 574 RTP ................................................................................. 363 RTP-CVD .................................................................................................. Rugged Polysilicon ...................................................................................... 810 155,713 Rutherford Back Scattering .................................................................. Sacrificial Oxide ..................................................................................... 18 SACVD ...................................................................................................... 617 155 SAHR ....................................................................................................... 124 Salicidation .............................................................................................. 713 Saturated Calom el Electrode ....................................................................... Saturation ................................................................................................. 798 Sb-Preamorphization.................................................................................. 254 44 Scaled CM OS Technology ........................................................................ 43 Scaling of Devices ..................................................................................... Scanning Probe M etrology ............................................................................ 164 713 SCE ............................................................................................................
917
Schottky Barrier Height ............................................................................. 324 Schottky Contact ........................................................................................ 321 Sealed Interface Local Oxidation ............................................................. 17 Secondary Ion Mass Spectrometry ........................................................... 14,794 SEG ............................................................................................................ 305 Segregation Coefficient ............................................................................ 13 Selective Deposition ................................................................................. 851 Selective Epi Growth .................................................................................. 305 Selectivity ................................................................................................. 236 Selectivity and Etch Rate of SOG:BPSG ...................................................... 648 Self-Aligned .................................................................................................. 5 SEM Profiles ............................................................................................... 251 Semiconductor Fabs, Economic Modeling ....................................................... 551 Semiconductor Process Integration ................................................................ 551 Sensors, M ulti-Point Temperature ............................................................... 503 SF6 ............................................................................................................. 207 Shallow Boron-Doped Layer ....................................................................... 266 Shallow Junction .............................................................. 276,305,330,793,880 Shallow Junction Formation .................................................................. 285,296 Shallow Junctions, Silicided ........................................................................ 254 Sheet Resistance ........................................................................... 313,333,346 Shift, Threshold Voltage ........................................................................... 380 Short Channel Effects .......................................................................... 120,266 Si ........................................................................................................ 343,834 Si Emissivity .............................................................................................. 529 Si Membrane, Stress Compensated ............................................................... 121 Si Surface M icro-Roughness ........................................................................ 400 Si Template ................................................................................................ 176 Si Wafer Surface Roughness ........................................................................ 400 Si/Si0 2 Interface ....................................................................................... 400 SijxGex HBT ........................................................................................... 48 Si 2 H 6 ... .. .................................................... . .... ..... .. .... ....... .... ..... ...... ..... . . . . 10 Si 3 N 4............................................. .. .... .. ..... .... ....... ..... ...... .... ... 53,307,528,536 SiC14 .............................................. ..... ..... ...... .... ..... ..... .... ..... ..... . 209,306,730 Sidewall .................................................................................................... 239 Sidewall Protection .................................................................................... 208 Signal Processors ......................................................................................... 678 SiH4 ... .. ................................................... ...... ..... ..... ..... .... . .... ..... ..... .. . ... .835 Silane .................................................................................................. 835,841 Silane Chemistry ........................................................................................ 570 Silica Slurry ............................................................................................... 652 Silicate ..................................................................................................... 598 Silicidation .............................................................................................. 5,53 Silicide Formation, Enhanced ...................................................................... 305 Silicide, Ti and Co ...................................................................................... 254 Silicided Shallow Junctions ......................................................................... 254 Silicon ................................................................................................. 454,834 Silicon Dangling Bonds ................................................................................ 664 Silicon Dioxide .................................................................................... 692, 765 Silicon Dioxide Etching ............................................................................... 226
918
Silicon Dioxide Hydration ..........................................................................
696
Silicon Dioxide, Dielectric Breakdown ........................................................
409
Silicon Dioxide, Impurities ......................................................................... Silicon Epitaxy ...........................................................................................
694 755
Silicon Nitride ...........................................................................................
657
Silicon Oxidation ........................................................................................ 765 Silicon Tetrachloride .................................................................................. 730 Silicon, Amorphous ..................................................................................... 813 Silicon, N itrogen-Doped ............................................................................ 9 Silicon-Germanium Alloys .......................................................................... 296 Silicon-Rich Oxide ..................................................................................... 490 SILO ........................................................................................................ 17 SILO /RTN ................................................................................................ 17 Siloxane .................................................................................................... 598 Silylated Acid Hardened Resist .................................................................. 155 Silylation ............................................................................................ 146,155 SIM PL-IPX ............................................................................................... 79 SIM S ..................................................................................... 14, 440, 794,881 SIM S Depth Profile .................................................................................... 871 SIM S Junction Profiling ................................................................................ 332 Sim ulation of Factory Performance .............................................................. 551 Simulation of ULSI Device Effects ............................................................ 43 Sim ulation, Device and Process ................................................................ 78 Single Wafer Reactor .................................................................................. 693 Single W afer Thermal Processing ................................................................ 503 Si02 ............................................. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . 53,528,692,765 Si0 2 Breakdown M easurements .................................................................... 448 SiO 2 Etching ........................................................................................ 209,226 Si0 2 Films, Thin ......................................................................................... 391 SiO 2 Gate Dielectrics .................................................................................. 445 Si0 2 Gates, Electrical Characterization ...................................................... 448 Si0 2 Gates, Structural Characterization ...................................................... 447 Si0 2 , Dielectric Breakdown ........................................................................ 409 Si0 2 , Interfacial ........................................................................................ 870 Si02, LPCVD of .......................................................................................... 841 Si0 2 , PECVD ............................................................................................. 720 Si0 2 , Thermally-Grown .............................................................................. 409 Si0 2 , Trap Density in ............................................................................. 409 Si.Ge 1 _, Alloys .................................................................................... 296,851 Slurry, Silica .............................................................................................. 652 Small Signal Adm ittance Characteristics .............................................. 483 SM IF Box ................................................................................................. 91 Sodium Ions ................................................................................................. 861 Soft X-Rays ................................................................................................ 153 SOG ........................................................................................ 592, 598, 642, 712 SOG Cure Time ............................................................................................ 648 SOG, Etch-Back of ................................................................................... 17 SOG:BPSG Selectivity and Etch Rate .......................................................... 648 Solvent, Organic ......................................................................................... 749
91.9
Source/Drain Junctions, Shallow ..................................................................
305
Spin-On-Glass .......................................................... 592,598,607,617,642,712 Spin-On-Glass, Etch-Back of .................................................................. 17 592 Spin-ON-Polymer ....................................................................................... 730 Sputter ....................................................................................................... Sputter Deposition ................................................................................ 468 721 Sputter Etching ........................................................................................... 628 Sputtering ................................................................................................... 17 SRAM , 16K .............................................................................................. 881 SRP Analysis .............................................................................................. 343 Stability .................................................................................................... 26,421,422 Stacked Capacitor .......................................................................... 146 Standing Waves .......................................................................................... 487 Static Capacitance ...................................................................................... 33 STC ......................................................................................................... 421 Steam Oxidation, Pyrogenic ........................................................................ 152 Step Coverage ............................................................................................. Stepped-Field M ethod for Dielectric Breakdown ......................................... 409 402 STM Profiles ............................................................................................... 345 Stoichiometric ............................................................................................ 312 Stoichiometric Film .................................................................................... 885 Strain ......................................................................................................... 798 Strain Field ................................................................................................ 885 Stress ......................................................................................................... 354 Stress Induced Changes ................................................................................ 409 Stressing Field ............................................................................................ 409 Stressing Time ............................................................................................. 359 Stressing, Constant-Voltage ........................................................................ 447 Structural Characterization of SiO 2 Gates ................................................... I Sub-Half Micron ... ................................................................................... 178,305,305 Sub-M icron CMOS ......................................................................... 199 Submicron CMOS Process ............................................................................. 155 Submicron Deep UV Lithography ................................................................ 190,199 Submicron Photolithography ............................................................... 642 Submicron Triple M etal Technology .................................... Submicron, Deep ........................................................................................ 5 203 Substrate .................................................................................................... 379,881 Substrate Current ................................................................................. 620 Substrate Dependency ................................................................................. 357 Substrate Doping Effects .............................................................................. 606 Substrate Flatness ....................................................................................... 740 Substrate Preparation ................................................................................. SUPERSILO Isolation .............................................................................. 18 17 SuperSILO/RTN ....................................................................................... Suppression of Boron Penetration ................................................................ 9 834 Surface ....................................................................................................... 454,460 Surface Contamination ......................................................................... 146 Surface Imaging .......................................................................................... 114 Surface Inhibition Effects ............................................................................ 400 Surface M icro-Roughness ............................................................................
920
570, 851 Surface M orphology ............................................................................. 207 Surface Nitride Formation .......................................................................... Surface Potential Discrepancy ................................................................ 488 Surface Recombination, Interstitial ......................................................... 36 803 Surface Roughness of Polysilicon .................................................................. 400 Surface Roughness of Si Wafers ................................................................... 813 Surface Texture and Roughness ..................................................................... 445 Surfaces, Electrical Properties ..................................................................... 445 Surfaces, Electronic Structure ....................................................................... 33 SVC ......................................................................................................... 121 Synchrotron Radiation ................................................................................ Synchrotron Storage Ring ........................................................................ 88 870 System Free Energy ..................................................................................... 440 TCA ............................................................................................................ 421 TCA Oxidation ........................................................................................... 183 TCNQ .................................................. 32, 383, 396,414,421,431,811 TDDB .................................................................. 52,308 TEM ....................................................................................................... 870 TEM , High Resolution ................................................................................. 541,574 Temperature Control ............................................................................ 528, 541,574 Temperature M easurement ............................................................. 541 Tem perature Resolution ............................................................................... 503 Temperature Sensors, M ulti-Point ............................................................... 174 Tem plate, Trilayer .................................................................................... 528, 537,617,692,720,841 TEOS ........................................................................ 593 TEOS/Ozone .............................................................................................. 120 Test Circuit, 0.4 mim CM OS ......................................................................... 692 Tetraethoxy Silane ..................................................................................... 841 Tetraethylorthosilicate .............................................................................. 803 Texture, Polysilicon ..................................................................................... 813 Texture, Surface ......................................................................................... Texturization Technique, for Polysilicon ...................................................... 800 810 Texturization, Polysilicon ........................................................................... 110 469 A ermal Annealing ................................................................................. Therm al Annealing, High Pressure .......................................................... 470 491 Thermal Annealing, Low Temperature ........................................................ 152 Thermal Bias Stress .................................................................................. 122,428,566 Thermal Budget ............................................................................ 596 Thermal Flowing Polymer ........................................................................... 582 Thermal M odeling ...................................................................................... 503 Thermal Processing, Single W afer ............................................................... 592 Therm al Reflow .......................................................................................... Thermally-Grown SiO2 .................................... .. ..... .... ...... ..... .... ...... ... . . . 409 801, 811 Thin Film Reflectance .......................................................................... 445 Thin Film s, Electrical Properties ................................................................. Thin Films, Electronic Structure .............................................................. 445 483 Thin Gate Oxides ........................................................................................ Thin Gate Oxides, Electrical Properties of ................................................... 400 353 Thin Oxide Reliability ...............................................................................
921
Thin Oxide Yield ........................................................................................ Thin Oxides ................................................................................................
473 353
Thin SiO 2 Films .......................................................................................... 391 Three Dimensional Growth ......................................................................... 851 Three-Dimensional Process Simulator ....................................................... 54 Threshold Voltage Shift ...................................................................... 380,861 Ti-Silicide .................................................................................................. 254 TiB 2 . .. .................................................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310,343 TiC14 . . . . ....................................................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Time Dependent Breakdown ........................................................................ 396 Time Dependent Dielectric Breakdown ..................................... 32, 383, 414,421 431,433,434,811 Time Modulated Plasma Processing .............................................................. 206 Time Zero Breakdown ................................................................................. 394 TiN Barrier Layer ....................................................................................... 628 TiSi 2 . . . . ........................................................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 TiSi 2 Formation ........................................................................................... 305 Titanium Silicide ........................................................................................ 276 Titanium Silicide Formation ....................................................................... 305 TiW ............................................................................................................ 730 TM SDEA .................................................................................................... 155 Tool Integration ...................................................................................... 78 Top Surface Imaging .................................................................................... 145 Top-Oxide ............................................................................................. 421 Topography ................................................................................................ 203 Total Dose .................................................................................................. 499 Total Pressure ............................................................................................. 315 Transfer Characteristics .............................................................................. 449 Transfer Function ......................................................................................... 146 Transient Enhanced Diffusion .................................................................. 34,39 Transistor ............................................................................................ 152,432 Transistor Gain ........................................................................................... 568 Transmission Electron M icroscopy ........................................................... 52,308 Trap Density in SiO2 ...................................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 Trapped Electron Density ........................................................................... 660 Trapping, Charge ................................................................................. 377,803 Trapping, Electron ....................................................................................... 398 Trapping, Hole .................................................................................... 428,569 Traps .......................................................................................................... 486 Traps, Interface ........................................................................................... 355 Traps, Interface and Neutral ................................................................. 465 Trench Isolation ...................................................................................... 5,650 Tri-Layer Liftoff ......................................................................................... 135 Tri-Layer Resist ....................................................................................... 61 Trilayer Nitride/Oxide/Nitride ............................................................. 17 Trilayer Template ...................................................................................... 174 Triple Metal Technology, Submicron ............................................................ 642 Tungsten ..................................................................................................... 730 Tunneling .................................................................................................... 496 Tunneling, Fowler-Nordheim ...................................................................... 393
922
44 Twin-Tub CM OS Technology ..................................................................... 394 TZBD Breakdown ....................................................................................... 650,667,671 ULSI ............................................................................................. ULSI Device Effects, Simulation of .......................................................... 43
ULSI M OS Gate Dielectrics .........................................................................
363
ULSI Wafer Processing ............................................................................... 464 Ultra High Vacuum .............................................................................. 582 296 Ultra-Shallow Junction Formation ............................................................... Ultra-Thin Film ......................................................................................... 147 236,834 Ultraclean ........................................................................................... Ultrathin M OS Gate Dielectrics ................................................................. 363 445 Ultrathin SiO 2 Gate Dielectrics .................................................................. Undoped Polysilicon ................................................................................... 803 80 User Interface ........................................................................................... UTF ............................................................................................................ 147 150 UTF Metallization Process .......................................................................... UV ............................................................................................................. 147 131 UV Excimer Laser Stepper ........................................................................... 861 UV Light .................................................................................................. 110,145 UV Lithography ................................................................................. 26 V-Cell ..................................................................................................... V-Shaped Structure ................................................................................ 30 52 Vacancy Diffusion .................................................................................... Vapor HF/H 20 ........................................................................................... 226 785 Vertical Furnace ......................................................................................... 841 Very Low Temperature Oxide ..................................................................... 600 Via Chain .................................................................................................. Via Hole Filling ......................................................................................... 739 745 Via Resistivity ........................................................................................... 841 VLTO ........................................................................................................ 593 Void Formation ........................................................................................... 607 Void Free Dielectric Films ......................................................................... 722 Voids ......................................................................................................... 569 Voltage, Flatband ...................................................................................... 715 Voltammetric M easurements ...................................................................... 380 VtShift ...................................................................................................... 730 W ............................................................................................................... 121 Wafer Alignment Accuracy .......................................................................... Wafer Pairs, Bonded ................................................................................. 870 446 Wafer Processing, Experimental .................................................................. Wafer Processing, ULSI .......................................................................... 464 400 Wafer Surface Roughness ........................................................................... 694 Water Pickup ............................................................................................. Waveguide Structures ................................................................................. 681 353 Wearout of Oxides ...................................................................................... 355,360 Wearout, Oxide ................................................................................... .357 Wearout, Polarity Independence ............................................................... 414 Weibull Distribution ............................................................................... 426 W eibull Plot ........................................................................................... W et Process ................................................................................................. 749
923
X-Ray X-Ray X-Ray X-Ray
Irradiation .................................................................................. A93 Lithography ................................................................. 88,110, 120,466 Photoelectron Spectroscopy ............................................................... 237 Resist ............................................................................................. 94
X-Ray Source .......................................................................................... X-Rays ....................................................................................................... XPS ............................................................................................................ XPS Analysis ........................................................................................... Yield of M OS Capacitor .............................................................................. Yield, Thin Oxide ...................................................................................... Zero-Defect Substrates ................................................................................ Zeta Potential ............................................................................................ Zeta Potential Control ................................................................................
924
89 153 237 18 462 473 681 749 754
