SYMBOLIC ANALYSIS TECHNIQUES
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SYMBOLIC ANALYSIS TECHNIQUES Applications to Analog Design Automation Edited by Francisco V. Fernandez Centro Nacional de Microelectronica, Spain Angel Rodriguez-Vazquez Centro Nacional de Microelectronica, Spain Jose L. Huertas Centro Nacional de Microelectronica, Spain Georges G. E. Gielen Katholieke Universiteit Leuven, Belgium
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© 1998 by the Institute of Electrical and Electronics Engineers, Inc. 345 East 47th Street, New York, NY 10017-2394
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ISBN 0-7803-1075-6 IEEE Order Number: PC4283
Library of Congress Cataloging-in-Publication Data Symbolic analysis techniques: applications to analog design automation / edited by Francisco V. Fernandez ... ret al.]. p. em. Includes bibliographical references (p. ) and index. ISBN 0-7803-1075-6 1. Linear integrated circuits--Design and construction--Data processing. 2. Symbolic circuit analysis. I. Fernandez, Francisco V., 1965TK7874.S876 1997 621.3815--dc21 97-18498 CIP
To Eli, Belen, Concha and Patricia
Contents
Preface
xv
Acknowledgments
xix
Chapter 1 Introduction 1.1. Symbolic Analysis: Concept and Ground Rationale 1.1.1. Qualitative, Numerical, and Symbolic Analysis
1.2.
1 1
1
1.1.1.1. Qualitative Analysis
2
1.1.1.2. Numerical Analysis
2
1.1.1.3. Symbolic Analysis
2
1.1.2. Ground Rationale and Arena of Symbolic Analysis
3
Symbolic Analysis for Circuit Understanding
4
1.2.1. A Feedforward Compensated CMOS Amplifier
5
1.2.2. Cascode Transistors
6
1.2.3. CMOS Current Mirrors
7
1.3. Symbolic Analysis for Iterative Design Procedures
11
1.4. Symbolic Analyzers
12
1.4.1. Symbolic Analyzers: Inputs
12
vii
viii
Contents
1.4.2. Basic Outputs of Symbolic Analyzers
14
1.4.3. Processed Symbolic Analyzer Outputs
16
1.4.3.1. Symbolic Poles and Zeros
16
1.4.3.2. Sensitivity
17
1.5. Historical Notes
18
References
22
Chapter 2 Symbolic Analysis Techniques: A Review
27
2.1.
Introduction
27
2.2.
Definitions
28
2.3. Tree Enumeration Methods
29
2.3.1. Directed Tree Enumeration
29
2.3.2. Undirected Tree Enumeration
33
Flowgraph (Topological) Methods
36
2.4.1. The Mason Signal Flowgraph
36
2.4.2. The Coates Graph
42
2.5.
Parameter Extraction Methods
43
2.6.
Interpolation Methods
47
2.7.
Matrix-Based Methods
48
2.7.1. The Modified Nodal Analysis
48
2.7.2. Determinant-Based Solutions
54
2.7.3. Parameter Reduction Solutions
56
General Comparisons and Complexity Analysis
60
References
61
2.4.
2.8.
Chapter 3 Symbolic Analysis of Sampled-Data Systems 3.1.
3.2.
64
3.1.1. Signal Flowgraphs and Topological Analysis
64 64
3.1.2. Matrix Approach
65
Sedlar-Bekey Method
66
Introduction
3.3. Arnautovic-Lin Approach for Finding Input-Output Relationships of Sampled-Data Systems
73
3.3.1. The Arnautovic-Lin Approach Applied on a General Case of Sampled-Data System 3.4.
Solved Examples of Finding Input-Output Relationship
3.5. Conclusions References
76 79 84 84
ix
Contents
Chapter 4 Symbolic Analysis of Switched Analog Circuits
86
4.1.
Introduction
86
4.2.
Classification of Techniques for the Symbolic Analysis of SC Circuits
88
4.2.1. Modeling: of the SC Circuits
88
4.2.2. Classification of Symbolic Analysis Methods
91
Algebraic Methods
91
4.3.1. Formulation of the SC Circuit Equations
91
4.3.2. Solution of the SC Circuit Equations
94
4.4.
Circuit Transformation Methods
95
4.5.
Signal Flowgraph Methods
97
4.3.
4.6.
Parameter Extraction Methods
4.7.
Conclusions
100
Acknowledgments
100
References
100
Chapter 5 Hierarchical Symbolic Analysis of Large Analog Circuits 5.1.
5.2.
5.3.
102
Introduction
102
5.1.1. Circuit Level Hierarchy
102
5.1.2. Expression Level Hierarchy (Sequence of Expressions)
105
5.1.3. Parallel Processor Implementation Issues
107
5.1.4. Existing Hierarchical Methods
108
Hierarchical Direct Network Method
108
5.2.1. Terminal Block Analysis
109
5.2.2. Middle Block Analysis
111
5.2.3. Analysis of the Sequence of Expressions
114
Hierarchical Mason Signal Flowgraph Method
116
5.3.1. Analysis of the Partitions (Terminal Block Analysis)
117
5.3.1.1. MSFG Reduction Rules
117
5.3.1.2. Reduction Order
118
5.3.2. Middle Block Analysis
119
5.3.3. Discussion
120
5.3.3.1. Performance Measures 5.4.
99
123
5.3.4. Examples
125
Hierarchical Coates Graph Method
127
5.4.1. Terminal Block Analysis
127
5.4.2. Middle Block Analysis
128
x
Contents
5.5.
Comparisons of Hierarchical Methods
130
5.6.
Conclusions
132
References
139
Chapter 6 Symbolic Formula Approximation
141
6.1.
A Rationale for Expression Approximation
141
6.2.
The Concept of Symbolic Formula Approximation
144
6.3.
Simplification of Expanded Format Expressions
146
6.3.1. Nominal Value Approaches
147
6.3.2. Variation Range Approach
152
6.4.
6.5.
6.3.2.1. Range Concept and Basic Operators
152
6.3.2.2. Handling of Mismatches
154
6.3.2.3. Simplification Algorithm
155
6.3.2.4. Further Developments
156
6.3.2.5. Experimental Results
157
Simplification of Nested Format Expressions
159
6.4.1. Direct Pruning Approach
159
6.4.2. Simplification Criterion Requirements
161
6.4.3. The Lazy Expansion Approach
162
6.4.4. The Contribution Factor Approach
163
6.4.5. Expressions in SOE Format
167
Approximation-during-Generation Techniques
167
6.5.1. Term Generation
168
6.5.2. Error Criterion
170
6.5.3. Handling of Mismatches
171
6.5.4. Experimental Results
172
6.6.
Approximation-before-Generation Techniques
174
6.7.
Conclusions
176
References
176
Chapter 7 Symbolic Analysis of Weakly Nonlinear Analog Integrated Circuits
179
7.1.
Introduction
179
7.2.
Characteristics of Weakly Nonlinear Analog Integrated Circuits
181
7.2.1. One-Tone Definitions
182
7.2.2. Two-Tone Definitions
182
Power Series Description of Basic Weak Nonlinearities
183
7.3.
xi
Contents
7.3.1. Set of Basic Nonlinearities
183
7.3.2. Nonlinear Conductance and Transconductance
184
7.3.3. Nonlinear Capacitance
185
7.3.4. Two-Dimensional Transconductance
187
7.3.5. Three-Dimensional Transconductance
189
7.3.6. Weakly Nonlinear Transistor Models
190
7.3.6.1. Bipolar Transistor
190
7.3.6.2. MOS Transistor
193
7.4. A Calculation Method for Harmonics and Intermodulation Products 7.4.1.
First-Order Responses
193 195
7.4.2. Second-Order Responses
195
7.4.3. Higher-Order Responses
197
7.4.4. Interpretation of the Results
197
7.4.5. Factorization of Denominators
198
7.5. Simplified Symbolic Computation of Harmonics and Intennodulation Products
199
7.5.1. Elimination of Unimportant Nonlinearities
199
7.5.2. Generation of the Approximated Symbolic Subexpressions
200
7.6. Examples
200
7.7. Conclusions
207
References
Chapter 8 Structural Synthesis and Optimization of Analog Circuits 8.1. Introduction
8.2. Basic Definitions and Problem Formulation
209
211 211 212
8.2.1. Basic Definitions
212
8.2.2. Problem Formulation
214
8.3. Methodology of Structural Synthesis and Optimization
216
8.3.1. General Algorithms of Structural Synthesis and Optimization
216
8.3.2. Structure Optimization
217
8.3.3. Parameter Optimization
221
8.3.4. Structural Synthesis: Exhaustive Generation of All Structures
221
8.4. Symbolic Approach in Structure Synthesis and Parameter Optimization
224
8.5. Examples
225
8.6. Concluding Remarks
230
References
232
xii
Contents
Chapter 9 Automated Analog Design Using Compiled Symbolic Models
233
9.1.
Introduction
233
9.2.
Overview of Automated Analog Design Techniques
234
9.2.1. Specification Translation and Sizing of Analog Circuits
234
9.2.2. Knowledge-Based Versus Optimization-Based Automated Analog Design
237
9.2.2.1. The Knowledge-Based Approach
237
9.2.2.2. The Optimization-Based Approach
238
9.2.2.3. Comparison of Knowledge-Based and OptimizationBased Automated Analog Design 9.3.
Automated Analog Design as an Optimization Problem Based on Compiled Symbolic Models
9.4.
9.5.
239 240
9.3.1. Symbolic Design Equations
241
9.3.2. The Independent Optimization Variables
245
9.3.3. The Analog Design Optimization Formulation
247
Examples of Analog Design Systems Using Symbolic Models
249
9.4.1. The OPASYN Program
249
9.4.2. The OPTIMAN Program
249
9.4.3. The ASTRXlOBLX Tool
253
9.4.4. A Sigma-Delta Modulator Synthesis Tool
254
9.4.5. A Switched-Capacitor Filter Synthesis Tool
255
Conclusions
255
References
256
Chapter 10 Symbolic Signal Flow Graph Methods in Switched-Capacitor Design
258
10.1. Introduction
258
10.2. Analysis and Synthesis in Circuit Design
259
10.2.1. Flow of Information for Analysis
259
10.2.2. Formulation Method for Building Block Interpretation
260
10.2.3. Flow of Information for Synthesis
260
10.2.4. Equation Extractor for Dimensioning
261
10.3. SC Primitives and Identification Techniques
262
10.3.1. SFG Representation of SC Elements
262
10.3.2. Rule-Based Identification
262
10.4. SFG-Based Symbolic Analysis of SC Networks 10.4.1. Formulation Method
264 264
Contents
xiii
10.5. Step-by-Step SC Synthesis and Knowledge Capture
267
10.5.1. Step-by-Step Synthesis
269
10.5.2. Building Block Characterization
269
10.5.3. Dimensioning
272
10.6. Automatic Synthesis 10.6.1. Building Block Knowledge-Base 10.7. Conclusions References
Chapter 11 Symbolic Methods in Semiconductor Parameter Extraction
274 274 288 288
290
11.1. Introduction
290
11.2. Overview of Parameter Extraction
291
11.2.1. Approaches to Parameter Extraction
291
11.2.2. Parameter Extraction as an Optimization Problem
292
11.3. Integrated Parameter Extraction
293
11.3.1. Simulation-Based Parameter Extractor
293
11.3.2. Numerical Methods in Parameter Extraction
295
11.3.3. Symbolic Methods in Parameter Extraction
295
11.3.4. Integration of Numerical and Symbolic Extraction
298
11.4. Examples 11.4.1. Evaluation of Examples 11.5. Concluding Remarks References
Chapter 12 Statistical Delay Characterization of CMOS Digital Combinational Circuits
301 303 306 308
311
12.1. Introduction
311
12.2. Overview of Symbolic / Analytical Delay Modeling Techniques
314
12.2.1. General Assumptions
314
12.2.2. RC-Based Models
315
12.2.3. Macromodels
319
12.2.4. Direct Solution of Circuit Equations
319
12.3. Nominal Accuracy versus Statistical Accuracy
320
12.4. The Statistical Modeling Methodology
321
12.5. Device Models
323
12.5.1. MOS Transistor Model
323
12.5.2. Capacitor Model
328
xiv
Contents
12.5.3. Statistical Model
330
12.6. Analytical Delay Models
333
12.6.1. Circuit Decomposition
333
12.6.2. Waveform Representation
334
12.6.3. Charging and Discharging a Capacitor through an NMOS Transistor
335
12.6.4. Inverter
341
12.6.5. Serially Connected Transistors (NANDINOR Structure)
342
12.7. Examples
346
12.8. Conclusions
351
References
Chapter 13 Analog Testability and Fault Diagnosis Using Symbolic Analysis
352
354
13.1. Introduction
354
13.2. The Testability Concept
356
13.2.1. Testability Based on the Multi-frequency Approach
356
13.2.2. Algorithms for Testability Evaluation
357
13.2.2.1. Numerical Algorithm
358
13.2.2.2. Symbolic Algorithm
358
13.2.2.3. Further Developments
361
13.2.3. Testability of Nonlinear Circuits
366
13.3. Fault Diagnosis of Linear Analog Circuits
366
13.3.1. Symbolic Methods Based on Multifrequency Measurements
367
13.3.2. Symbolic Methods Based on Time-Domain Measurements
368
13.4. Fault Diagnosis of Nonlinear Circuits
370
13.4.1. PWL Models
371
13.4.2. Transient Analysis Models for Reactive Components
372
13.4.3. The Katzenelson-Type Algorithm
373
13.4.4. The Circuit Fault Diagnosis Application
374
13.4.5. The SAPDEC Program
375
13.5. Conclusions References
379 379
Index
383
About the Editors
389
Preface
As soon as powerful digital computers became available, electrical engineers started to develop programs to perform systematic analysis tasks in a fully automatic way. Today, all electrical engineering professionals and students use electrical simulators (such as HSPICE or ELDO). However, electrical simulators do not cover all the analysis tasks required for integrated circuit design. Essentially, they serve to verify the performance of previously sized circuits. However, designers must also be able to predict the behavior of unsized circuits by tracing relationships among performance figures and design parameters. These relationships may involve transfer functions, poles and zeroes, root loci, parametric Bode plots, harmonic distortion coefficients, and so forth. Traditionally, they have been derived manually. Tools used to derive them automatically are called symbolic analyzers. The first generation of symbolic analyzers appeared in the late 1960s, when basic analysis techniques were proposed. These tools did not spread to the designer community, partially due to their computational cost and because they did not fully fit the designer requirements. On the other hand, the lack of interest in custom analog ICs during the 1970s rendered symbolic analyzers secondary to electrical simulations. This scenario changed during the 1980s with increased economical interest in custom analog and mixed-signal ASICs. Symbolic analyzers were promptly recognized as helpful tools to relieve analog designers of the lengthy analyses needed to understand the operation of analog circuits. They also demonstrated useful-to-perform automatic modeling of analog modules, both for behavioral modeling and for design procedures that require repetitive calculations. This resulted in the emergence of a new generation of tools during the late 1980s. Main features of this new generation are approximation, expression post processing, and the extension to the analysis of weakly nonlinear circuits.
xv
xvi
Preface
This edited book is an overview of the basic analysis techniques behind this last generation's tools and some of their emerging applications. The book includes 13 chapters organized in two major areas: Techniques for symbolic analysis, in Chapters 2 to 7. Applications of symbolic analyzers, in Chapters 8 to 13. Chapter 2 presents an overview of conventional symbolic analysis techniques for those unfamiliar with this subject. Detailed algorithmic descriptions and illustrative examples are shown for topological methods (tree enumeration, Mason signal flowgraph, and Coates' graph) and matrix techniques (parameter extraction, numerical interpolation, determinant-based techniques, etc.). Techniques presented in Chapter 2 apply directly to continuous-time circuits described in the s-domain. Chapters 3 and 4 are devoted to sampled-data circuits described in the z-domain. Chapter 3 presents a method for symbolic analysis of sampled-data systems which consists of describing samplers as black nodes in order to apply Mason's formula. On the other hand, Chapter 4 overviews the use of matrix techniques for sampled-data circuits, with special emphasis on switched-capacitor circuits. Chapter 5 arises from the necessity for full-detail analysis of large circuits, for instance, RC-active filters with opamps described at the transistor level or by complex macromodels, and the intrinsic limitations of flat analysis. The chapter presents three different techniques (Coates' graph, signal flowgraph, and direct network approach) using hierarchy to solve these problems. Chapter 6 overviews the topic of symbolic formula simplification. Initially developed to enhance the interpretability of expressions and ease its computational manipulation, it has evolved to become a fundamental means to make large-circuit analysis feasible. All previous chapters deal with linear circuits. Chapter 7 introduces a technique based on the Volterra series method to extend symbolic analysis to weakly nonlinear characteristics of analog integrated circuits, like harmonic and intermodulation distortion. Nonlinearities are added to the linearized transistor models, and the weakly nonlinear behavior is obtained as high-order correction of the linear behavior. In the set of chapters dedicated to applications, Chapter 8 presents a method based on symbolic analysis to choose the optimum interconnection of a number of circuit primitives for a given functionality and then the optimum values for the circuit parameters. Chapter 9 explores the use of symbolic analysis in automatic sizing of analog cells. Symbolic equations are compiled in a symbolic model that describes the circuit behavior and is used inside an iterative optimization loop based on simulated annealing. The use of simulated annealing guarantees good design quality, the use of analytical equations confers high speed to the system, and the use of symbolic analysis provides openness. Chapter 10 discusses the application of a symbolic signal flowgraph technique for automatic analysis and design of discrete-time circuits. SC elementary building blocks are characterized by a signal flowgraph representation that can be used for either analysis of large SC building blocks or for synthesis. Chapter 11 introduces the application of symbolic techniques to the determination of semiconductor parameters. The extraction of model parameters requires iterative optimization techniques to minimize differences between measurement data and model behavior - a very time-consuming task using numerical simulators that can be largely alleviated using symbolic formulas. Chapter 12 shows the advantageous application of a combination of symbolic and iterative techniques to the determination of the statistical parameters of delays along signal paths in digital circuits - a very expensive method using conventional Monte Carlo and gradient-based techniques. Finally, Chapter 13 covers the use of symbolic techniques in analog fault diagnosis and testability evaluation. Testability,
Preface
xvii
conceived as a measure of the solvability of the fault diagnosis problem, is shown to be more exactly evaluated using symbolic rather than numericalmethods, due to the round-off error encountered in numerical techniques. Fault diagnosis techniques are introduced for linear circuits based on frequency and time-domain measurements as well as for nonlinear circuits based on the generation of devoted simulators. The views presented in the book have to be complemented with the references included at the end of the chapters; in particular, Chapter 1 includes a detailed list of references. We have intended to make it exhaustive; we apologize for all those references which may have been unintentionally forgotten.
Francisco V. Fernandez Angel Rodriguez-Vazquez Jose L. Huertas Georges G. E. Gielen
Acknowledgments
Elisenda Roca converted the material supplied by the authors to a common electronic format and edited the whole book. Thank you very much, Eli, for this huge work. Thanks very much to Prof. Edgar Sanchez-Sinencio of Texas A&M University for his encouragement to prepare this edited volume and to the IEEE Press editorial board and staff for their patience and support. We are also indebted to all our colleagues of the Instituto de Microelectr6nica de Sevilla-CNM, and of the Departement Elektrotechniek -KUL for contributing to create the appropriate atmosphere to undertake this project. Finally we would like to thank the anonymous reviewers for their constructive comments. Francisco V. Fernandez Angel Rodriguez- Vazquez Jose L. Huertas Georges G. E. Gielen
xix
1 Angel Bodrlquez-vazquez
Introduction
Francisco V. Fernandez Jose L. Huertas IMSE-CNM Sevilla, Spain
Circuit analysis is the cornerstone for electronic circuit engineering. On the one hand, it provides the keys to understanding the intricate mechanisms underneath the circuit operation. On the other hand, designers use analysis to obtain models of the circuit behavior-the basis on which this behavior can be predicted. Nodal and mesh analysis, signal flowgraphs, transfer functions, poles and zeros, root locus, power expansions, and so on, as well as associated mathematical apparatus are hence crucial for circuit designers. For basic building blocks consisting of a few transistors (such as current mirrors, elementary amplifiers, differential amplifiers, and the like) these analyses can be carried out by hand. However, detailed manual analysis of even the simplest circuits encountered in practical applications is a complicated, time-consuming, and error-prone task. In many cases, the only way to analyze circuits by hand is using shortcuts based on knowledge, which requires a lot of expertise, takes a long time, and does not guarantee accuracy of the final results. Symbolic analyzers are intended to palliate these difficulties and to relieve designers of systematic tasks, thus letting them concentrate on creative issues. This introductory chapter presents general concepts related to symbolic analysis and symbolic analyzers and briefly traces their history.
1.1. SYMBOLIC ANALYSIS: CONCEPT AND GROUND RATIONALE 1.1.1. Qualitative, Numerical, and Symbolic Analysis The term circuit analysis refers to the tracing of dependencies between the circuit behavior and the features of its individual components. There are three different types of
1
2
Chapter 1
Introduction
analyses depending on the nature of the behaviors and features involved: numerical, symbolic, and qualitative. Their concepts will be illustrated through the calculation of the transfer function of Fig. 1.1a as a function of the component values and the frequency. We will assume for these purposes that the operational amplifier (op-amp) is modeled as shown in Fig. 1.1b.
Vin o--~/\/ \ / - -......---../lll\/'-----...........- - - i
+
(b) Figure 1.1 (a) Second-order active filter; (b) op-amp small-signal model.
1.1.1.1. Qualitative Analysis Qualitative analysis defines conceptual relationships between output and input; for instance, the absolute value of the de gain of Fig. l.la increases with R2 increasing and R} decreasing; or the resonant frequency of the circuit poles decreases as the de gain of the op-amp increases. These general guidelines give background knowledge that assists designers to make well-founded decisions in choosing proper directions during the design procedure.
1.1.1.2. Numerical Analysis Here, the input amplitude, phase, frequency, and the parameters associated with the models of the circuit components are given as numbers, and the analysis returns numerical values for the output amplitude and phase. For instance, assuming R} = 1 kQ, R2 = 2 kQ, R3 =5 kQ, C 1 = 10 nF, C2 =20 nF, AO = 105, and a 1 kHz sinusoidal input with 1 V amplitude and 300 phase, numerical analysis using SPICE would return an amplitude of 0.860 V and a phase of 1430 for the output signal. Note that determination of the output amplitude and phase for either different input parameters or component values or both requires a new analysis instance.
1.1.1.3. Symbolic Analysis Unlike numerical analysis, symbolic analysis maintains the input frequency and all or part of the circuit parameters as symbols. We distinguish different types of symbolic analysis, depending on whether all or only some parameters are symbols [1], [2].
Sec. 1.1
Symbolic Analysis: Concept and Ground Rationale
3
1. Fully symbolic analysis, where all component parameters and the complex frequency are maintainedsymbols.In the case of Fig. 1.1,the following network function in Laplace domain results: Vo (5) ( 2 T (5) = V. (5) = - ( G) G3) / 5 [C) C 2 ( 1 + 1/A o) 1 + In
5
[C 2 (G) + G 2 + G3) (I + I/A O) + C)G3/AOl +
(1-1)
G2G3 (1 + IIAO) + G,G 31A O )
2. Semisymbolic analysis, where some of the component parameters are given numerical values; for instance,
2= [AA o+3) ( 9) + 1 x 0.5 x 10
000
o
(1-2)
which gives the resonant frequency of (1-1) as a function of the op-amp de gain for the component values given above. 3. Symbolic analysis in the complexfrequency, where all componentparametersare given numerical values and only the complex frequency remains a symbol. Most modern symbolic analyzers enable specifying each circuit parameter as either a number or a symbol, and hence realizing any of the three types of analyses described.I Also, the combination of numbers and symbols makes it possible to develop symbolic expressions where insignificant terms are discarded-a feature that emulates how experts analyze integratedcircuits (ICs) [3]-[5]. This leads us to define a further class of symbolic analysis: 4. Simplified symbolic analysis, where only significant terms appear in the final expression.For instance,simplified analysis of Fig. 1.1,assuming Ao» 1,results in T(s) =
=
(1-3)
1.1.2. Ground Rationale and Arena of Symbolic Analysis The previous example shows that symbolic analysis includes the features of qualitative and numerical analyses. On the one hand, a symbolic formula like (1-1), (1-2), or (1-3) provides direct insight to the qualitative influence of each circuit component over the circuit behavior, for instance, on the influence of the op-amp de gain over the resonant frequency. On the other hand, the outcome of a symbolic analysis is an analytical formula that captures the behavior in large regions of the design space, while the outcome of numerical analysis quantifies the behavior at an isolated point of this space. From a symbolic formula, which is calculated in one analysis instance, infinite numerical results are obtained by assigning values to the circuit components and the frequency. ) Most analyzers provide only formulas for transfer functions; only a few advanced tools are able to provide further elaborated pieces of information, like poles, zeros, resonant frequencies, etc.
4
Chapter 1
Introduction
From previous considerations, one might be tempted to draw the fallacious conclusion that symbolic tools supersede numerical simulators. However, this is far from the truth. On the one hand, numerical simulators cover a wider domain of applications. The basic arena of symbolic techniques are linear-or linearized 2-time-invariant circuits in frequency domain; either s-domain analysis of continuous-time circuits or z-domain analysis of sampled-data circuits [6]-[ 14]. Although some recent works are extending this arena to frequency-domain analysis of weakly nonlinear circuits [15], and transient analysis of linear circuits [16], symbolic techniques for transient and/or frequency domain analysis of general nonlinear circuits are not mature enough yet. On the other hand, numerical simulators are capable of coping with larger circuits than symbolic tools. While the former have evolved such that they are able to cope with complete chips, the basic instances for symbolic analysis are circuit building blocks of up to about 30 transistors (op-amps, comparators, etc.). Larger complexities require proper combination of macromodeling and hierarchical analysis [17], [18]. Symbolic and numerical tools should be viewed as complementary rather than competing tools. Essentially, numerical simulators serve to verify the performance of previously sized circuits, while symbolic analysis tools serve to assist in predicting the behavior of unsized circuits. P. M. Lin presented an excellent overview of the use of symbolic analysis in 1973, only a few years after the first works in the topic were published [2]. Most of Lin's ideas still remain today. However, the application of symbolic analysis to the design of analog integrated circuits has opened new scenarios. Figure 1.2 illustrates the expected role to be played by symbolic analysis tools in the design flow of Ie circuits. As the figure illustrates, applications of modern symbolic analysis tools can be basically grouped in two major areas: 1. Those associated with the generation of knowledge about the operation of circuits. 2. Those requiring repetitive evaluations of the formula describing the operation of circuits, as in iterative optimization procedures or statistical analysis. Detailed cases of these areas are presented in the different chapters of this book. Some illustrative examples will be presented in the next two sections.
1.2. SYMBOLIC ANALYSIS FOR CIRCUIT UNDERSTANDING In what follows, we will illustrate through selected examples the use of symbolic analysis and symbolic formulas to gain knowledge of the behavior of circuits. All the analyses involved in these examples can be completed by modern symbolic analyzers in less than 1 s, thus allowing interactive usage.
2
For instance, linearization is required to analyze circuits containing semiconductor devices; in general, for circuitscontainingnonlinearcomponents.
Sec. 1.2
5
Symbolic Analysis for Circuit Understanding
Unsized Circuit
SYMBOLIC ANALYZER Specifications Ao, GB,PM :::: A0-
gmn gdsn
+ gdsp
Sizes
Evaluations
2
I
Jlpc ox
~C'
3 ox
Optimization routines
(W) IB L p'2
W L
p p
Qualitative knowledge Dependencies among specifications and design parameters, sensitivities, etc.
Quantitative knowledge Sized circuit
Figure 1.2 Illustrating the role of symbolic analyzers in the IC design flow.
1.2.1. AFeedforward Compensated CMOS Amplifier There are many circumstances where the symbolic formulas reveal relationships among behaviors from which design choices can be made. Consider, for instance, the amplifier of Fig. 1.3a, and assume that we aim to increase its useful frequency range through proper choice of the value of the capacitor Cpz [19]. A symbolic analyzer with
6
Chapter 1
Introduction
B
(b)
(a)
Figure 1.3 (a) Active compensated cascode amplifier; (b) MOS transistor small-signal model.
embedded symbolic pole-zero extraction capability-for instance, ASAP [5]-obtains the following expressions for the dominant poles and zeros: gdsl gds2 gdsa
(1-4)
At a glance, and taking into account that gm of the transistors is typically much larger than one can conclude that PI is a dominant pole, and that the other two will most probably lie at far enough frequencies. Also, the designer can infer a design condition to obtain cancellation between the second pole and the zero, and thus increase the phase margin of the amplifier,
gds'
(1-5) This formula defines a hypersurface within the design space containing all the possible solutions to the compensation problem: one for each possible value of the real numbers Cpz' Cdb l , Cgd l , CII, and Cgd2 that fulfill (1-5).
1.2.2. Cascade Transistors The insight provided by symbolic formulas is also of unrivaled value to assess the influence of adding or deleting individual components from a circuit-an extended practice among analog Ie designers. It is based on the observation that the performance of practical circuits may become significantly enhanced by just adding or deleting a single component. This is shown in Fig. 1.4, where the incorporation of the cascode transistor of Fig. 1.4b may increase the output resistance by orders of magnitude. This is apparent by a glance at the
Sec. 1.2
7
Symbolic Analysis for Circuit Understanding
+
1 Zout = gds2
(c)
(a)
Figure 1.4 (a) Simple current mirror; (b) cascade current mirror; (c) MOS transistor small-signal model.
enclosed symbolic formulas for the output resistance, and taking into account that gm is typically much larger than gds. However, enhancement of a given performance figure occurs mostly with concurrent deterioration of other figures, and the quick evaluation of these enhancements and deteriorations becomes necessary. Because symbolic expressions display the topology modifications as terms added or deleted from analytical formulas, they are especially well suited for this task. This benefits largely from the incorporation of postprocessing tools over the symbolic analyzers, for instance, to obtain poles and zeros and graphic parametric plots from the symbolic formulas. An example of this follows.
1.2.3. CMOS Current Mirrors Consider the structures presented in Fig. 1.5 and assume they are loaded by a resistor RL in parallel with a capacitor CL. The current gain of Fig. 1.5a with the model of Fig. 1.5e is Io(s,x) ~( ) i S,X
=
(
2
)
GLgm2+s(CLgm2-Cgd2GL) -s C LCgd2 /
( (gdsl
+ gml) (G L + gds2) +
(1-6)
s(G L +gds2) (Cg s l +Cgs2+Cgd2+Cdbl) + s [(gdsl + gml) (C L + C gd2 + Cdb2) + gm2Cgd2] + s2 [(C L
+ Cgd2 + Cdb2 ) (C gs 1 + Cgs 2 + Cdb 1) + Cgd2 (C L + Cdb2 ) ]
)
which contains two poles and two zeros. Figure 1.6 presents the real (Fig. 1.6a) and imaginary (Fig. 1.6b) parts of the roots of (1-6) in logarithmic scale, as a function of the bias current. Note that the pole PI cancels out the zero zl in part of the current range. There is also a high-frequency pole, P2' that moves at higher frequencies when the bias current increases. Hence, we can conclude that this mirror is very fast. Unfortunately, its output impedance is low and its input impedance
8
Chapter 1
Introduction
(a)
(c) (d)
B
S (e) Figure 1.5 Current mirrors: (a) simple; (b) simple active; (c) cascode; (d) cascode with level shifter; (e) MOS transistor small-signal model.
is high [20], which may produce important errors when mirrors are cascaded, a situation commonly encountered in current mode analog circuits [21]. As designers, we conceive two alternative strategies to cope with these problems: (a) reduce voltage excursions at the input node and (b) increase the output impedance. The mirror in Fig. 1.5b realizes the first strategy. The amplifier introduces a negative feedback loop that maintains the input node at a relatively constant voltage and hence reduces the input impedance. The numerical simulation of the circuit behavior of Fig. 1.5b with a bias current of some tenths of microamps shows no abnormal behavior. This leads us to conclude that this circuit is acceptable. However, more global analysis of its poles and zeros reveals that this circuit is somewhat controversial. Figure 1.7 shows the real and imaginary parts of these roots when the amplifier is substituted by the macromodel
9
Sec. 1.2 Symbolic Analysis for Circuit Understanding
~
.3 ,. '-'
0
-
~
(a)
'" '"0I
-
.~
P2 ,
Z2
Zl
PI
.,
., '.
I I .
I "'. 1
"
"-,
.D
.j
1
i i
\
'.
\
cc I
0
, \
I I
,
I I
-10 10 _10 8 -106 _10 4 -102
0
104
106
108 1010 1012
102
104
106
108 1010 1012
Re(s) (rad/s) (log)
0
'-"
(b)
102
Z2Z1 P2P1
,.
~
0
~
ce . '" _ -o 0I
-
;S
cc I
0
_10 10_108 _10 6 _10 4 - 10 2
0
Im(s) (rad/s) (log)
Figure 1.6 Root location of the current gain of the simple current mirror in
Fig. 1.5a: (a) real part; (b) imaginary part.
.,
I -. I
"-... _... _... _... _...-
..
_. .. - .. _... _... -
(a) co I
o
_10 10 _10 8 -106 -104 -10 2
0
102
104
106
108 1010 1012
Re(s) (rad/s) (log)
P3
P2
(b) cc I
o
_10 10_108 -106 -104 _10 2
0
102
104
106
108
1010 1012
Im(s) (rad/s) (log) Figure 1.7 Root location of the current gain of the active current mirror in
Fig. 1.5b: (a) real part; (b) imaginary part.
10
Chapte r 1
Introduction
displayed with the figure . Unexpectedly , two complex poles appear in the right half of the s-plane for bias currents of up to 7 1lA. Actually, this instability appears in numeric al simulat ion with HSPICE [22] of this circuit for I bias =5 IlA. If this information were not available, this problem would remain undetected until the test stage. Cascode structures realize the second strategy cited earlier [23] . Figure 1.5c shows a cascode mirror encountered in many practical current-mode circu its [21]. Figure 1.8 show s that two real poles are canceled with two real zeros throughout the current range ; thus, the external behavior is determ ined by a zero in the right semi plane and a pair of conjugated complex pole s in the left semiplane of the s-plane. Thus. we can conclude that this circuit is slightly slower than the simple mirror . As a co unterpart, its output impedance is considerably larger. A main problem of this circuit lies in its small dynamic range whose limits are very sensitive to technological parameters. The circuit of Fig . 1.5d tries to solve this problem. Numeri cal simulation of this circu it for different circuit parameters and bias intensities leads to unstable conditions, whose limits are obscure . Once aga in, the symbol ic analyzer solves this problem by giving information about the bias cond itions for correct circuit operation. Figure 1.9 show s the real and imaginary parts of pole s and zeros for different bias current values . There is a pair of conjugated complex poles that move to the right half of the s-plane for a limited range of bias currents, mak ing the circuit unstable.
Z3
~1
~
~
-
'"
~ b :0 -
'-'
(a)
~
co I 0
_10 10 -108 -106 _10 4 _10 2
~1
v~
~ '-'
(b)
-
102
104
106
108
'.
1010 1012
Re(s) (rad/s) (log)
P3P4 z3zZZ1
pz
~
0
PI J J J J
-o
J
~ b :o-
J J J J
cc
J
I
0
J J
".
_10 1°_108 _10 6 -104 -10 2
0
102
104
106 108 1010 1012 Im(s) (radls) (log)
Figure 1.8 Root location of the current gain of the cascode current mirror in Fig. 1.Sc: (a) real part; (b) imaginary part.
Sec. 1.3
P3 Z2P2P IZ ,
---.
!::J)
o 1
0
~
(a)
,
:? -o
~
:, 1
"d'· . ' '.
, ,
.s" ::: '"
"
- - - - - - -
,..,
-v
I
., ,
I
0
~ 0
~
:?
-
-
~ ._ i' 0 .n
,
I
,
,
-10 6
r
-----_._---- - - - - -- -- - - - - -
/
I
_10 4
-10 2
P3
10
"l
!
_10 8
--- - - - - - - - - - - - - - - - - - - -
I
\'."'.,
cc
(b)
11
Symbolic Analysis for Iterative Design Procedures
0
102
104
106
108
Re(s ) (rad/s) (log)
PI Z' Z2
P2
I I \ \ \ \
-
\ \
\ \
cc
\
I
0
\
\
_10 8
_10 6
_10 4
_10 2
0
102
104
106
108
Im(s) (rad/s) (log)
Figure 1.9 Root location of the current gain of the cascode current mirror with level shifter in Fig. 1.5d: (a) real part; (b) imaginary part.
1.3. SYMBOLIC ANALYSIS FOR ITERATIVE DESIGN PROCEDURES Analog circ uits have very wide design spaces. On the one hand, each build ing block can be realized through many alternative schematics. On the other hand, each schematic can be sized in different ways to fulfill its requested performance specifications. Expert designers use heuristics based on their knowledge of the circuit operation to choose both circuit topologies and their design parameters. Alternatively, this knowledge can be captured in the form of computer-generated symbolic formulas, and topology selection as well as parameter optimization realized through the systematic eva luation of the formula . Chapters 8 to 10 discuss this in detail. Here, we will ju st mention some basic ideas . The basic idea underlying symbolic-based structure optimization is to generate a large number of alternative topologies through the combinatorial interconnection of elementary buildin g blocks using artificial intelligence [24], [25]. For each generated topology, the form ula associated to some performance criteria is derived automatically. Then , the performance criteria is optimized throu gh repetitive eva luations of the form ula, and a quality index is assigned to the topology based on the outcome of the optimiza tion procedure. Sim ilar proced ures can be used for the optimum dime nsioning of predefined analog building blocks through the repetitive evaluation of compiled symbolic expressions of their significa nt specification figures as functio ns of their design parameters . As long as the symbolic expressions can be generated automatically, designers may create and expand design databases in a very simple manner. Th is was proposed in Ref. [26], where the
12
Chapter 1
Introduction
authors claim significant advantages as compared to other alternative synthesis and optimization procedures. Similar to the optimization of circuit structures and parameters, there are many other applications that take advantage of the increased computer efficiency in the evaluation of compiled symbolic formula. For instance, there are fault diagnosis and testability analysis, semiconductor parameter extraction, behavioral simulation of basic building blocks, etc. all discussed in different chapters of this book.
1.4. SYMBOLIC ANALYZERS 1.4.1. Symbolic Analyzers: Inputs A symbolic analyzer is a program or set of programs to obtain symbolic formulas from electrical circuits, and to extract significant features from these formulas. Input and output differ among different programs, but typically have elements in common. 1. Description of the circuit topology in a SPICE-type language. Typical primitives include resistors, capacitors, inductors, independent sources, controlled sources, semiconductor devices, and functional blocks like op-amps, operational transconductance amplifiers (OTAs), etc. Table 1-1 shows a netlist to analyze the circuit of Fig. 1.3a using the program ASAP [5]. In particular, the area enclosed by the block labeled A corresponds to the description of the circuit topology. The enclosed numbers are intended to guide simplification. All modern analyzers use similar hardware description languages and include a similar set of primitives. 2. Indication of the models for the semiconductor devices and functional blocks. Most symbolic analyzers include encapsulated models for these entities, and the user may choose the most convenient for his/her purpose. For example, Fig. 1.10 shows the four levels that ASAP considers for the MOS transistors. The lines in the area labeled B in Table 1-1 specify a level-4 model for the PMOS and the NMOS. Again, the numbers are used for simplification. Most analyzers allow users to create macromodels of functional blocks other than those included in the program library. 3. Requested analyses and control parameters. For instance, the area labeled C in Table 1-1 contains a first line to request calculation of the symbolic transfer function from voltage at node 1 to voltage at node 3, a second line to order calculation of a simplified formula and its associated control parameters, another to request pole extraction, and a final line to request realization of parametric analysis varying the capacitor Cpz. 4. Design points. Most of the symbolic analyzers with simplification capability do evaluate the symbolic terms at a nominal design point-chosen as the more likely to happen in the sized circuit. This means that the validity of the simplified formulas is restricted to a neighborhood of this point. To avoid this, some analyzers include the possibility of considering design regions, instead of single points, for simplification [17].
Sec. 1.4
13
Symbolic Analyzers
Table 1-1 Input Netlist in ASAP for the Circuit in Figure 1.3a
II * active feed-forward compensation
I
~
rV~705-------------------------------------------
Vss 6 00 CII 72 2P II 7 2 1.5M Ml2166NMODl M2 3 4 2 2 PMOD2
A
Ma5277PMODA Cpz 43 4P CL 3 62P I2360.5M I3560.1M LVin
10AC
_
r------------------------------------------------
I.ACMODEL NMODI NMOS LEVEL=4 GM=15.5247E-3 GDS=21.7398E-6
:+ CGS= 12.8803P CGD= 1.6706P CDB=3.7918P : .ACMODEL PMOD2 PMOS LEVEL=4 GM=4.1129E-3 GDS=57.492E-6 I
1+ CGS=5.4284P CGD=0.6688P CDB=3.5084P I
B
I.ACMODEL PMODA PMOS LEVEL=4 GM=214.8596E-3 GDS=2.7679E-6 I
I+ CGS=0.1817P CGD=O.O170P CDB=0.0894P
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --
~-----------------------------------------------:~TF-V(3)-V(1)-
: .SIMPLIFY LEVEL=3 EPS=O.l I
"PZ: .VARY Cpz EXACT dec 30 l.e-13 I.e-IO POLES(1in),ZEROS(1in) I
C
I.END
Some symbolic analyzers also include strategies to simplify handling of matched devices, by representing them by the same symbolic parameter. Then, they include dedicated procedures to handle mismatches due to statistical variations in fabrication processes. Such mismatches play a dominant role in some small-signal circuit characteristics, mainly second-order ones. In these cases, large insight is gained if explicit mismatch parameters are introduced. For instance, to explicitly express mismatch between two nominally matched devices, i.e., two transistors M 1 and M 2, each symbolic parameter x i 2 of M 2 is determined from that corresponding to M 1, as follows: XiI = x i Q x i2
=
x i Q + ~xil2
(1-7)
where ~x i l' the delta variable, accounts for the dispersions between both device
parametersr'
14
Chapter 1
Introduction
GoB
G
level-l
s
level-3
G B 0-
B
s
level-2
level-4 Figure 1.10 MOS transistor small-signal models in symbolic analyzer ASAP.
Thus, such variables have some unpredictable value (either positive or negative) between some given extrema.
1.4.2. Basic Outputs of Symbolic Analyzers As to output, the primary ones are in the form of system functions, and have different formats depending on the nesting produced with respect to a complex frequency, s or z. or other symbolic parameters. The expanded format produces system functions given as a quotient of polynomials in s (or z) whose coefficients are symbolic polynomials in the circuit parameters, N
I/f;(x) = i =0 M
Ilg/x) j=o 3 An alternativeis to define
Xii
= x iO + ~xil
x i2
= x iO + dX i 2
This representation expresses nominal values and deviations around them more clearly, but incorporatesmore variable names, which means a higher computationalcost.
(1-8)
Sec. 1.4
15
Symbolic Analyzers
where p is either s or z. and the coefficients of p powers are sums of products of the . T symbolic parameters x = {xI' x 2' ... , x Q } . Generically, either Ii (x) or gj (x) in (1-8) can be written as T
hk (x) = hk l (x) + "n (x) + ... + hkT(x) ==
L
hk1(x)
(1-9)
1= I
where hkl (x) represents a product of symbols; that is, H(s,x) =
-gml gds2 + sC I g ds2 + sC I g m2 gdsl gds2
+ gm2 gds3 + gmb2 gds3 + gds2 gds3 + sC 1g ds3
(1-10)
In some analyzers, the coefficients f..I (x) and g.} (x) in (1-8) are at the same time nested functions in the symbolic parameters; that is, (1-11) which corresponds to the same expression in (1-10). As shown in (1-11), a nested format expression may contain hidden cancellations. Human interpretation of nested format expressions is more difficult than expanded ones, but their computational evaluation is more efficient. Thus, they become adequate or not depending on the application context. Their approximation exhibits many more difficulties than expanded expressions. However, they are unavoidable when analyzing very large circuits, because expansion of the resulting expressions exceeds any computer capability. Nested format expressions can also be expressed as a sequence of expressions (SOE) format, in which each subexpression is assigned a new variable name. Assuming that equal subexpressions share the same variable name they are more compact than nested format expressions, as in (1-11). Therefore, memory consumption is reduced and they are more efficient to evaluate. As an illustrative example, the expression in SOE format:
H I I = ky+ 1
H l2
=k+ 1
H l 3 = l+a
s H l 4 = l+GB.E H 21
= H 12H 13
H 31 = H 21 + ky H(s,x) =
(1-12)
16
Chapter 1
Introduction
results from the symbolic computation of the voltage gain of the noninverting amplifier of Fig. 1.11a where the op-amp has been implemented using the composite operational amplifier of Fig. 1.11b [27]. A two-pole model was used for the op-amps in Fig. 1.11b: A(s)
= __1_ _
( 1-13)
-.!..-( I + 00~)
GB
2
and y and E in (1-12) represent E
,
v·
+
C20A
00" = --..:. GB
>---.----0
R Y = -.!!. R
v()
(a)
( 1-14)
··...... ···
··· ··
.....
."
(b)
Figure 1.11 (a) Noninverting amplifier; (b) composite operational amplifier.
1.4.3. Processed Symbolic Analyzer Outputs In addition to the basic outputs already discussed, some symbolic analyzers provide further elaborated pieces of information either in symbolic form or in the form of parametric surfaces defined on designer-selected regions of the design parameter spaces. This encompasses techniques or tools, built around the core symbolic analyzers, that ease the interpretation of symbolic results or its manipulation and extract information from them. They have been already illustrated in previous examples and are typically tailored to analog integrated circuit design: simplification, handling of mismatches, power series expansion and distortion analysis, etc. Most of them are extensively covered in chapters of this book. In the next sections, we outline some others not covered specifically in any chapter.
1.4.3.1. Symbolic Poles and Zeros A natural transformation of exact or simplified symbolic system functions is to obtain the parametric dependencies of poles and zeros which, in a large measure, determine the circuit function. In Ref. [28], a technique was introduced for symbolic extraction of poles and zeros, based on numeric estimates of their positions, similar to those performed by expert analog designers, e.g., the pole-splitting technique. Numerical estimates of pole/ zero locations are used by the program to suggest possible approximations: root splitting, displacement to infinite, root clustering, etc. Analytical solutions are applied to the reduced
Sec. 1.4
17
Symbolic Analyzers
polynomials when no more approximations are applicable. This was illustrated by (1-4) for the cascode amplifier of Fig. 1.3. Another technique, reported in Ref. [29], calculates approximate symbolic network functions in alimited frequency range. Given a network function in factorized form,
H (s, x) =
(s - Z 1) (s - Z2)
(s - ZN)
(s-Pl) (s-P2)
(s-PM)
( 1-15)
For a frequency range such that ( 1-16) and assuming that the remaining roots are widely separated, (1-15) can be approximated as
s (s - z2) (-z3) ... (-zN) H (s, x) == - 2 - - - - - - - - - - -
(1-17)
s (s-P3) (s-P4) (-ps) ... (-PM) which are lower-order polynomials, and the poles and zeros within the considered frequency range can be approximately extracted.
1.4.3.2. Sensitivity Sensitivity analysis is extensively used in analog circuit design. Consider a certain behavior represented by a system function H(s, x). The normalized sensitivity of this function regarding a certain parameter, p, is defined as
_
J/ _ aHp Sp - dp
H-
a
( 1-18)
dIn (p) In (H)
Techniques to compute this sensitivity include the traditional network perturbation method [1] or the adjoint network [1]. For not too large circuits, sensitivity can also be calculated from the symbolic formula, by simply deriving it with respect to the circuit parameter P [30], [31]. We can particularize (1-18) if we express the system function as a quotient of symbolic polynomials in s: that is, N
I/!;(x)
= ;= 0
H(s,x) - N(s,x) - D(s,x)
( 1-19)
M
I!gj(X) j=O
The normalized sensitivity is, then,
!!..~(~)
SH = EaH =
Hap
P
=
Hap D
N
=
(!.-
aD)
aN _1. P Nap Dap
M
N
M
e ~ dNd!; .e ~ dDdgj = e ~ /d!; .t: ~ !dgj
N £..J af.dp ;=0
I
D £..J dg .ap j=o
J
N £..J ap D £..J ap ;=0
)=0
(1-20)
18
Chapter 1
Introduction
Here, we must distinguish if p is a symbolic parameter that appears more than once in the circuit or not. If that is the case, (1-20) must be evaluated; on the other hand, if it appears only once, (1-21 )
is the group of numerator terms that contain the symbol p. Thus, it is enough to order the terms according to if they contain the parameter p or not. Likewise, it may be performed for the denominator. The sensitivity of magnitude and phase may be obtained from the normalized sensitivity, SH. As a function of these, H (s, x) can be expressed as p
IH (s, x) Iej <1> (s, x)
( 1-22)
for which the sensitivity is Jl
~'p
=
d
I
dln(p) n
(IH(s,x )1 ej<1>(S,X») =
alna(p) In (!H(s,x)l) +Jalna(P)cj>(S,X) =
s~H1+Jcj>S:
through which the sensitivity of magnitude and phase are obtained from
Re( S:) = !Im(sH) P P
s~H1
( 1-23)
S;:
=
( 1-24)
S<1>
<J>
Similarly, the normalized sensitivities of poles and zeros can be determined [31]. On the other hand, Ref. [32] presents a technique to perform sensitivity analysis of nested symbolic formula.
1.5. HISTORICAL NOTES The first generation of symbolic analyzers appeared in the late 1960s, most of which were reported in conference papers [33]-[37]. One that acquired special renown due to its extensions and applications to practical design problems [38]-[44] was NASAP [45]. NASAP maintained only the complex frequency as a symbolic parameter. The first symbolic analyzer capable of supplying system functions with an arbitrary number of symbolic parameters was SNAP [46], which used signal flowgraph analysis techniques (see chapter 2). The ulterior development of the parameter extraction analysis technique resulted in NAPPE [47] in 1973, and was superior for applications involving only a small number of symbolic parameters, and much inferior, even unfeasible, for an increased number of symbolic terms. These first-generation programs did not have the analysis capacity and efficiency needed to cope with integrated circuit design problems. On the other hand, their CPU time
Sec. 1.5
Historical Notes
19
and memory requirements to analyze practical circuits transcended the performance limits of contemporary computers, making their efficient use unfeasible. Consequently, the interest in symbolic analysis declined considerably by the early 1970s, reflected in a scarcity of publications during the 1970s and 1980s. Renewed interest in symbolic analysis dates from the late 1980s and mainly links to the concurrent interest in mixed-mode application-specific integrated circuits (ASICs) and more specifically, to the need for increased designer efficiency in the implementation of the analog circuits found in these ASICs. It has also been largely favored by the dramatic evolution of computer performance since the 1970s, and by the bottleneck in the use of numerical simulations tools for knowledge acquisition. Many symbolic analyzers have evolved as members of this second generation [3], [11], [18], [25], [48]-[51]. Exact comparison of their performance is difficult due to the lack of standard benchmarks for test circuits and platforms. Also, in some cases, they are intended for different analysis tasks; for instance, some are oriented to z-domain analysis of discrete-time and/or analog sampled-data circuits and others to s-domain analysis of continuous-time circuits. A brief description of the analyzers listed in Table 1-2 follows. SCAPP [18], [52] has been implemented at Iowa State University, and relates to the development of a new methodology for symbolic analysis of large circuits. The program partitions the circuits hierarchically and symbolically analyzes each subcircuit separately, using a variation of the modified nodal analysis (MNA), called reduced MNA (RMNA), which significantly reduces the nodal matrices. Once the terminal blocks are analyzed, an inverse run of the partition process reconstructs the global system function. Because this analyzer uses an approach for large circuits based on hierarchical analysis, the system functions are given as a series of expressions rather than only one expression. Thus, the number of symbolic terms grows linearly, instead of exponentially, with the size of the circuit. Subsequently, a hierarchical signal flowgraph approach has also been added to the program [53]. SCYMBAL and SYBILIN [24], [25] are two simulators developed in CNET (Bagneux, France). The distinctive characteristic of SCYMBAL is that it was developed specifically for the circuit analysis of switched-capacitor (SC) circuits. It has the particularity of allowing not only continuous variables such as conductances, capacitors, etc. as symbolic parameters, but also Boolean variables such as clock phases. On the other hand, SYBILIN is a continuous-time analyzer, especially conceived for the analysis of microwave circuits. SC [51], [54] was developed at the University of Arizona and conceived for classroom use, and thus developed for personal computers. It has a set of postprocessing tools to ease interpretation of symbolic data: interactive numeric evaluation, numeric calculation of poles and zeros, and graphic representation. The types of elements that may form part of the circuit under study are limited to linear resistors, capacitors and inductors, independent sources, and four types of controlled sources: voltage-controlled voltage source (VCVS), voltage-controlled current source (VCCS), current-controlled voltage source (CCVS), and current-controlled current source (CCCS). SAPEC [50], [55], implemented at the University of Florence, is similar to SC. Like SC, it has a graphic interface and it is capable of analyzing circuits composed of the previously cited elements, plus mutual inductances, ideal transformers, and operational amplifiers. The application environment where it was developed establishes its implementation in LISP, greatly limiting its speed and portability. One of the main characteristics of SAPEC is the group of applications developed around it, such as
~
s::
no no no
no
no
no
expanded format
nested format
before generation
yes
yes
no no no no
no
yes
no
no
WS
C
Nonlinear analysis
Hierarchical analysis
P/Z extraction
Graphical interface
Platforms (WS == workstations)
Implementation language FORTRANI ADA
WS
no
no
no
no
C
WS
no
no
no
LISPI C++
PC
no
no
no
no
Element lumping
no
no
no
no
no
no
yes
s
Mismatchings
no
no
no
no
s
MNA
SAPEC
no no
zls
s
Analysis domain
MNA
GASCAP &SC
during generation
<
0.. 0..
2
E .><
~
.9
SFG
RMNA &SFG
SCYMBALI SYBILIN
Formulation
SCAPP
Table 1-2 Comparison of Symbolic Analyzers
C
WS &PC
no
no
no
no
no
no
yes
no
no
yes
s
MNA
SSPICE
LISPI C++
WS
no
no
no
no
no
yes
no
no
yes
yes
s&z
MNA
SYNAP
LISP/C
WS
no
no
no
weakly nonlinear
yes
yes
yes
no
no
yes
s&z
CMNA
ISAAC
C/C++
WS &PC
yes
yes
no
no
yes
yes
yes
no
yes
yes
s
SFG
ASAP
C
WS
no
yes
no
no
no
no
no
yes
no
no
s
Nodal analysis
SIFTER
C
WS
no
no
no
no
no
no
yes
yes
no
no
s
Tree enumeration
RAINIER
Sec. 1.5
Historical Notes
21
symbolic sensitivity analysis [30], transient analysis of electronic power circuits [56], calculation of testability index [57], and fault diagnosis [58]. SSPICE [59] was developed at the University of Michigan for both personal and large computers. It is capable of performing small-signal analysis of circuits that contain semiconductor devices: diodes, MOS transistors, bipolar transistors, JFET (field-effect) transistors, and gallium-arsenide transistors. It incorporates the capacity of simplifying symbolic expressions, although using a primitive technique to eliminate the least significant terms [60]. It is also capable of performing sensitivity analysis [61]. SYNAP [3] was developed at ETH in Zurich and CSEM in Neuchatel (Switzerland). Together with ISAAC [4] and ASAP [5], it was especially conceived for the modeling and design of analog integrated circuits and, more specifically, to be included on a CAD framework for automatic design of analog integrated circuits [62]-[64]. It not only incorporates encapsulated models for semiconductor devices and analog functional blocks, it can also handle mismatches. Its first version was programmed in LISP using MACSYMA [65], a general-purpose symbolic manipulation program, resulting in a highly inefficient implementation. Recently, it has been realized in a self-contained manner using C++. This new version is capable of analyzing linear continuous-time and sample-data circuits, and also incorporates a primitive de analysis capability. As to simplifications, it incorporates the concept of "lazy expansions," which enables performing approximations directly on the nested expressions [66]. ISAAC [4] was developed in the Katholieke Universiteit Leuven (KUL). Originally, it was implemented in LISP using a modification of the modified nodal analysis technique to formulate circuit equations. It was the first to include the capability to analyze continuous-time and sample-data circuits in a single program. It was also the first to incorporate the analysis of weakly nonlinear characteristics [15]. Like ASAP, SYNAP, and SSPICE, it can obtain simplified expressions. For this, it parts from exact expressions in expanded format and eliminates the least significant terms, while the accumulated sum of the eliminated terms does not exceed the mismatching between devices. ISAAC forms a fundamental part of the automatic design system ARIADNE [67], [68]. ASAP [5] was developed in a cooperative effort between the Spanish Microelectronics Center (CNM) and ANACAD Electrical Engineering Software. Like SSPICE, there are versions of ASAP for workstations and personal computers, with the difference that ASAP has a graphic interface for both types of platforms. It shares with ISAAC the capability of performing groupings of elements and, together with SYNAP, the explicit expression of mismatching. On the other hand, it incorporates the capability of calculating approximate poles and zeros symbolically. ASAP also incorporates new simplification criteria for symbolic expressions, which guarantee maximum precision for each simplification level, using variation ranges of each symbolic parameter instead of fixed numeric values. This approximation avoids multiple pathological errors that appeared in previous simplification criteria. Approximation with variation ranges has also been used to develop a reliable and precise criterion to simplify expressions resulting from hierarchical analysis and generally, any type of expression in nested format. CNM and KUL have jointly developed approximation-during-generation techniques that have been incorporated into their tools [69], [70] (see chapter 6 for a detailed description). SIFTER [71], [72] and RAINIER [73] .were both developed at the University of Washington at Seattle. Both addressed the simplified analysis of large analog circuits by means of the new simplification before- and during-generation approaches. SIFfER
22
Chapter 1
Introduction
follows a matrix-basedapproach, while RAINIER follows a topological approach based on spanning tree enumeration, similar to that in [69], [70]. Both will be discussed in greater detail in chapter 6.
References [1] L. O. Chua and P. M. Lin, Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques. Englewood Cliffs, NJ: Prentice-Hall, 1975. [2] P. M. Lin, "A survey of applications of symbolic network functions," IEEE Trans. Circuit Theory, vol. CT-20, no. 6, pp. 732-737, November 1973. [3] S. Seda, M. G. R. Degrauwe, and W. Fichtner, "A symbolic snalysis tool for analog circuit design automation," Proc. IEEE Int. Conf. Computer-Aided Design, Santa Clara, CA, pp. 488-491, 1988. [4] G. E. Gielen, H. Walscharts, and W. Sansen, "ISAAC: A symbolic simulator for analog integrated circuits," IEEE J. Solid-State Circuits, vol. 24, no. 6, pp. 1587-1597, December 1989. [5] F. V. Fernandez, A. Rodriguez-Vazquez, and J. L. Huertas, "Interactive ac modeling and characterization of analog circuits via symbolic analysis," Analog Integrated Circuits and Signal Processing, vol. 1, pp. 183-208, November 1991. [6] E. Wehrhahn, "Evaluation of transfer functions of ideal S.C. networks in z-domain using standard linear symbolic or semisymbolic network analysis programs," Electron. Lett., vol. 16, no. 21, pp. 801-802, October 1980. [7] A. Konczykowska and M. Bon, "SCYMBAL2: A portable computer program for efficient all-symbolic hierarchical analysis of large multiphase switched capacitor networks," Proc. European Conf. Circuit Theory Design, Stuttgart, pp. 375-378, 1983. [8] C. K. Pun and J. I. Sewell, "Symbolic analysis of ideal and non-ideal switched capacitor networks," Proc. Int. Symp. Circuits Syst., Kyoto, Japan, pp. 1165-1168, 1985. [9] J. F. Duque-Carrillo,J. J. Pefia-Bernal, and J. M. Vega-Fernandez, "ANSWICAP-A computer-aided method for symbolic transfer function determination on switched capacitor networks," Int. J. Electronics, vol. 61, no. 4, pp. 517-529, 1986. [10] Y. Cheng and P. M. Lin, "Symbolic analysis of general switched capacitor networksNew methods and implementation," Proc. IEEE Int. Symp. Circuits Syst., Philadelphia, pp. 55-59, 1987. [11] H. Walscharts, G. Gielen, and W. Sansen, "Symbolic simulation of analog circuits in s- and z-domain," Proc. IEEE Int. Symp. Circuits Syst., Portland, pp. 814-817, 1989. [12] B. Li and D. Gu, "SSCNAP: A program for symbolic analysis of switched capacitor circuits," IEEE Trans. Computer-Aided Design, vol. 11, no. 3, pp. 334-340, March 1992. [13] M. H. Martins, J. E. Franca, and A. S. Garcao, "A symbolic z-transfer function generator for the synthesis and analysis of multirate switched-capacitor circuits," Proc. IEEE Int. Symp. Circuits Syst., San Diego, CA, pp. 2573-2576, 1992. [14] Z. M. Arnautovic and P. M. Lin, "Symbolic analysis of mixed continuous and sampled-data systems," Proc. IEEE Int. Symp. Circuits Syst., Singapore, pp. 798-801, 1991.
References
23
[15] P. Wambacq, G. Gielen, and W. Sansen, "Symbolic simulation ofharrnonic distortion in analog integrated circuits with weak nonlinearities," Proc. IEEE Int. Symp. Circuits Syst., New Orleans, pp. 536-539, 1990. [16) B. A. Alspaugh and M. M. Hassoun, "A mixed symbolic and numeric method for closed-form transient analysis," Proc. European Con! CircuitTheory Design, Davos, Switzerland, pp. 1687-1692, 1993. (17] F. V. Fernandez, A. Rodnguez-Vazquez, J. D. Martin, and J. L. Huertas, "Formula approximation for flat and hierarchical symbolic analysis," Analog Integrated Circuits and Signal Processing, vol. 3, no. 1, pp. 43-58, January 1993. [18] M. M. Hassoun and P. M. Lin, "A new network approach to symbolic simulation of large-scale networks," Proc. IEEE Int. Symp. Circuits Syst., Portland, pp. 806-809, 1989. [19] W. Sansen and Z. Y. Chang, "Feedforward compensation techniques for high-frequency CMOS amplifiers," IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1590-1595, December 1990. [20] D. Nairn and C. A. T. Salama, "High-resolution, current-mode AID convertors using active current mirrors," Electron. Lett., vol. 24, pp. 1331-1332, October 1988. [21] C. Toumazou, F. J. Lidgey, and D. G. Haigh (Eds.), Analog IC Design: The Current Mode Approach. London: Peter Peregrinus, 1990. [22] HSPICE User's Manual. Campbell, CA: Meta-Software, 1993. [23] P. Allen and D. Holdberg, CMOS Analog Circuit Design. New York: Holt, Rinehart and Winston, 1987. (24] A. Konczykowska and M. Bon, "Automated design software for switched-capacitor IC's with symbolic simulator SCYMBAL," Proc. 25th ACM/IEEE Design Automation Conf., Anaheim, CA, pp. 363-368, 1988. [25] A. Konczykowska and M. Bon, "Symbolic simulation for efficient repetitive analysis and artificial intelligence techniques in C.A.D.," Proc. IEEE Int. Symp. CircuitsSyst., Portland, pp. 802-805, 1989. [26] G. E. Gielen and W. Sansen, Symbolic Analysis .for Automated Design of Analog Integrated Circuits. Boston: Kluwer Academic Publishers, 1991. [27] W. B. Mikhael and S. Michael, "Composite operational amplifiers: Generation and finite-gain applications," IEEE Trans. Circuits Syst., vol. CAS-34, pp. 449-460, May 1987. [28] F. V. Fernandez, A. Rodriguez-Vazquez, and J. L. Huertas, "A tool for symbolic analysis of analog integrated circuits including pole/zero extraction," Proc. European Conf. Circuit Theory Design, Copenhagen, pp. 752-761, 1991. [29] Jer-Jaw Hsu and C. Sechen, "Accurate extraction of simplified symbolic pole/zero expressions for large analog IC's," Proc. IEEE Int. Symp. CircuitsSyst., Seattle, WA, pp.2083-2087, 1995. (30] A. Liberatore and S. Manetti, "Network sensitivity analysis via symbolic formulation," Proc. IEEE Int. Symp. Circuits Syst., Portland, pp. 705-708, 1989. [31] Y. Cheng and R. Fujii, "SAUCES: A sensitivity analysis program for analog circuit design," Proc. IEEE Int. Symp. Circuits Syst., San Diego, pp. 1175-1178, 1992. [32] P. M. Lin, "Sensitivity analysis of large linear networks using symbolic programs," Proc. IEEE Int. Symp. Circuits Syst., San Diego, pp. 1145-1148, 1992. [33] W. R. Dunn and S. P. Chan, "Topological formulation of network functions without generation of k-trees," Proc. 6th Allerton Conf. Circuit Syst. Theory, 1968.
24
Chapter 1
Introduction
[34] A. Demari, "On-line computer active network analysis and design in symbolic form," Proc. 2nd Cornell Electrical Eng. Conf., pp. 94-106, August 1969. [35] P. M. Lin and G. E. Alderson, "Symbolic network functions by a single pathfinding algorithm," Proc. 7th Allerton Con! Circuits Syst., pp. 196-205, 1969. [36] T. F. Gatts and N. R. Malik, "Topological analysis program for linear active networks (TAPLAN)," Proc. 13th Midwest Symp. Circuit Theory, Minneapolis, MN, 1970. [37] R. S. Schwartz and R. E Bach, "A symbolic solution algorithm for design of linear networks," Proc. 13th Midwest Symp. Circuit Theory, Minneapolis, MN, 1970. [38] M. L. Wilson and L. P. McNamee, "Considerations for solving large scale circuit problems using NASAP-70," Proc. 13th Midwest Symp. Circuit Theory, Minneapolis, MN,1970. [39] K. Haag, "NASAP analysis of nonlinear de circuits," Proc. 7th Allerton Conf Circuits Syst., pp. 905-912, 1969. [40] T. J. Kobylarz, F. J. Burke, and J. G Ma, "The structure of a nonlinear circuit analysis program which utilizes the principles of NASAP," Proc. 12th Midwest Symp. Circuit Theory, Austin, TX, 1969. [41] G. J. Herskowitz and M. Sakaran, "Application of NASAP to the design of communication circuits," Proc. 12th Midwest Symp. Circuit Theory, Austin, TX, 1969. [42] C. H. Beck, R. L. Drake, and M. H. Kuo, "A NASAP module for direct design of linear dynamic circuits," Proc. 12th Midwest Symp. Circuit Theory, Austin, TX, 1969. [43] W. N. Carr and J. D Sefcik, "NASAP guided design of MOSFET linear amplifiers," Proc. 12th Midwest Symp. Circuit Theory, Austin, TX, 1969. [44] C. H. Beck, R. L. Drake, and M. H. Kuo, "A NASAP-hybrid optimization technique for network design using NASAP sensitivity evaluation," Proc. 13th Midwest Symp. Circuit Theory, Minneapolis, MN, 1970. [45] L. P. McNamee and H. Potash, A User's and Programmer's Manualfor NASAP, Rep. 68-38. Los Angeles: Univ. of California, 1968. [46] P. M. Lin and G. E. Alderson, SNAP-A Computer Program for Generating Symbolic Network Functions, Tech. Rep. TR-EE70-16. Lafayette, IN: School of Electrical Engineering, Purdue University, August 1970. [47] G. E. Alderson and P. M. Lin, "Computer generation of symbolic network functionsA new theory and implementation," IEEE Trans. Circuit Theory, vol. CT-20, no. J ~ pp. 48-56, January 1973. [48] W. Sansen, G. Gielen, and H. Walscharts, "A symbolic simulator for analog circuits," Proc. IEEE Int. Solid-State Circuit Conf, pp. 204-205, 1989. [49] F. V. Fernandez, A. Rodriguez-Vazquez, and J. L. Huertas, "ASAP: A program for the symbolic analysis of analog integrated circuits," Proc. EUROASIC Conf, Paris, pp. 80-85, 1990. -[50] A. Liberatore and S. Manetti, "SAPEC-A personal computer program for the symbolic analysis of electric circuits," Proc. IEEE Int. Symp. Circuits Syst., Espoo, Finland, pp. 897-900, 1988. [51] L. P. Huelsman, "Personal computer symbolic analysis programs for undergraduate engineering courses," Proc. IEEE Int. Symp. Circuits Syst., Portland, pp. 798-801, 1989. [52] M. M. Hassoun and P. M. Lin, "An efficient partitioning algorithm for large-scale circuits," Proc. IEEE Int. Symp. Circuits Syst., New Orleans, pp. 2405-2408, 1990.
References
25
[53] M. M. Hassoun and K. S. McCarville, "Symbolic analysis of large-scale networks using a hierarchical signal flowgraph approach," Analog Integrated Circuits and Signal Processing, vol. 3, no. 1, pp. 31-42, January 1993. [54] L. P. Huelsman and D. G. Dalton, "A computational approach to the development and reduction of large symbolic expressions," Proc. IEEE Int. Symp. Circuits Syst., Singapore, pp. 790-793,1991. [55] S. Manetti, "New approach to automatic symbolic analysts' of electric circuits," lEE Proc. Pt. G, vol. 138, no. 1, pp. 22-28, February 1991. [56] A. Liberatore, S. Manetti, and M. C. Piccirilli, "A symbolic approach to the time-domain analysis of nonlinear or switched networks," Proc. First Int. Workshop Symbolic Methods and Appl. Circuit Design, Paris, October 1991. [57] R. Cannassi et aI., "Analog network testability measurement: A symbolic formulation approach," IEEE Trans. Instrument. Measurement, vol. 40, no. 6, pp. 930-935, December 1991. [58] S. Manetti and M. C. Piccirilli, "Symbolic simulators for the fault diagnosis of nonlinear analog circuits," Analog Integrated Circuits and Signal Processing, vol. 3, no. 1, pp. 59-72, January 1993. [59] G. M. Wierzba et aI., "Sspice-A symbolic SPICE program for linear active circuits," Proc. 32nd Midwest Symp. Circuits Syst., pp. 1197-1201, 1989. [60] G. M. Wierzba, Sspice User Manual. Instructional Media Center, Michigan State University, East Lansing, 1991. [61] S. Chang and G. M. Wierzba, "Symbolic sensitivity analysis using Sspice," Proc. 34th Midwest Symposium Circuits Syst., pp. 1043-1046, 1991. [62] M. Degrauwe et aI., "Towards an analog system design environment," IEEE J. Solid-State Circuits, vol. 24, no. 3, pp. 659-671, June 1989. [63] M. Degrauwe et aI., "The ADAM analog design automation system," Proc. IEEE Int. Symp. Circuits Syst., New Orleans, pp. 820-822, 1990. [64] J. Jongsma et aI., "An open design tool for analog circuits," Proc. IEEE Int. Symp. Circuits Syst., Singapore, pp. 2000-2003, 1991. [65] MACSYMA Reference Manual, version 10. Cambridge, MA: MIT and Symbolics, 1984. [66] S. Seda, M. Degrauwe, and W. Fichtner, "Lazy-expansion symbolic expression approximation in SYNAP," Proc. IEEE Int. Con! Computer-Aided Design, pp. 310-317,1992. [67] K. Swings and W. Sansen, "ARIADNE: A constraint-based approach to computer-aided synthesis and modeling of analog integrated circuits," Analog Integrated Circuits and Signal Processing, vol. 3, pp. 197-215, 1993. [68] G. Gielen and W. Sansen, "Open analog synthesis system based on declarative models," Proc. Workshop Advances in Analog Circuit Design, Scheveningen, The Netherlands, 1992. [69] F. V. Fernandez, P. Wambacq, G. Gielen, A. Rodriguez-Vazquez, and W. Sansen, "Symbolic analysis of large analog integrated circuits by approximation during expression generation," Proc. IEEE Int. Symp. Circuits Syst., London, Great Britain, pp. 25-28, 1994. [70] P. Wambacq, F. V. Fernandez, G. Gielen, W. Sansen, and A. Rodriguez-Vazquez, "Efficient symbolic computation of approximated small-signal characteristics of analog integrated circuits," IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 327-330, March 1995.
26
Chapter 1
Introduction
[71] Jer-Jaw Hsu and C. Sechen, "Fully symbolic analysis of large analog integrated circuits," Proc. IEEE Custom Integrated Circuits Conf., San Diego, CA, pp. 21.4.1-21.4.4, 1994. [72] Jer-Jaw Hsu and C. Sechen, "DC small signal symbolic analysis of large analog integrated circuits," IEEE Trans. Circuits Systems-I, vol. 41, no. 12, pp. 817-828, December 1994. [73] Q. Yu and C. Sechen, "Approximate symbolic analysis of large analog integrated circuits," Proc. IEEE Int. Con! Computer-Aided Design, San Jose, CA, pp. 664-671, 1994.
2 Marwan M. Hassoun
Dept. Electrical Engineering and Computer Engineering
Symbolic Analysis Techniques: A Review
Iowa State University Ames, Iowa
2.1. INTRODUCTION This chapter presents an overview of the prominent symbolic analysis techniques that have been introduced over the past 30 years. These symbolic methods, in general, can be classified according to the basic mechanism used in the analysis engine. These classifications are as follows: 1. Tree enumeration methods (section 2.3) 2. Flowgraph (topological) methods (section 2.4) 3. Parameter extraction methods (section 2.5) 4. Interpolation methods (section 2.6) 5. Matrix-based methods (section 2.7)
i. Determinant-based solutions (section 2.7.2) ii. Parameter reduction solutions (section 2.7.3) A further classification highlights the fact that some of the methods, which already fall under one of these categories, can be applied hierarchically to partitioned representations of circuits. Hierarchical methods are based on the following two mechanisms: 1. Flowgraph (topological) methods 2. Parameter reduction methods
27
28
Chapter 2
Symbolic Analysis Techniques: A Review
This chapter will address the basic methods of symbolic analysis for flat (nonhierarchical) circuits, which, naturally, will cover the basics of the hierarchical methods. The discussion of the hierarchical implementations is postponed to a dedicated chapter (chapter 5) because of the significant algorithmic development beyond the basics presented herein. Traditional symbolic circuit analysis is limited to linear circuits I and is performed in the frequency domain where the results are in terms of the frequency variable s. The main goal of performing symbolic analysis on a circuit in the frequency domain is to obtain a symbolic transfer function of the form H ( X) s,
= N (s, X)
(2-1)
D (s, X)'
The expression is a function of the complex frequency variable s, and the variables through xn represent the variable circuit elements, where n is the number of variable circuit elements and naIl is the total number of circuit elements. The hierarchical approaches are based on a decomposed form of (2-1) [1 ]-[3]. This hierarchical representation is referred to as a sequence of expressions representation to distinguish it from the single expression representation of (2-1), and is addressed in a subsequent chapter. The major advantage of having a symbolic expression in single expression form is the insight that can be gained by observing the terms in both the numerator and the denominator. The effects of the different terms can, perhaps, be determined by inspection. This process is very valid for the cases where there are relatively few symbolic terms in the expression. The remaining sections of this chapter will explain through simple examples the basic workings of the five classifications of symbolic analysis techniques. Although the specific implementations may differ, the essentials to understanding the inner workings of the algorithms are presented herein.
xl
2.2. DEFINITIONS Before indulging in the explanation of the different methods covered by this class, some definitions of terms are in order. Definition 2. J-RLCg m circuit: a circuit that may contain only resistors, inductors, capaci-
tors, and voltage-controlled current sources with the gain denoted as gnr
Definition 2.2-term cancellations: the process in which two equal symbolic terms cancel out each other in the symbolic expression. This can happen in one of two ways: by having two equal terms with opposite signs added together, or by having two equal terms (regardless of their signs) divided by each other. For example, the equation
ab(ab+cd) -ab(cd-ej) ab(cd-gh)
(2-2)
where a, b, c, d, e.f, g, and h are symbolic terms, can be reduced by observing that the terms 1
Some symbolic analysis algorithms handle nonlinear circuits by linearizing them around a de operating point [33]. Therefore, the symbolic analysis itself is performedon a linear circuit.
Sec. 2.3
29
Tree Enumeration Methods
ab in the numerator and denominator cancel each other and the terms +cd and -cd cancel each other in the numerator. The result is ab+ ef cd-gh
(2-3)
Definition 2.3-cancellation-free: an expression in which no possible cancellations exist. Expression (2-3) is said to be a cancellation-free equation while (2-2) is not. Definition 2.4-cancellation-free algorithm: the process of term cancellation can occur during the execution of an algorithm where a cancellation-free equation is generated directly rather than generating an expression with possible term cancellations in it. Cancellation-free algorithms are more desirable because, otherwise, an overhead is needed to generate and keep the terms that are to be canceled later.
Definition 2.5-directed graph: a directed graph G = (~E) consists of a finite, nonempty set of vertices V and a set of edges E that are ordered pairs ei =(vi' ui ) of vertices; Vi is called the tail and ciated with it.
ui
is called the head of edge
ei .
Each edge
e E i
E has a weight Wi asso-
2.3. TREE ENUMERATION METHODS Tree enumeration methods can be classified into two categories: directed tree enumeration and undirected tree enumeration. Tree enumeration is the oldest symbolic analysis process and is the basis for old and new symbolic analysis programs. Several programs have been produced based on tree enumeration; see Refs. [4]-[8]. Direct implementations of these methods can only handle small circuits in the range of 15 nodes and 30 branches [9]. The main reason is the exponential growth in the number of symbolic terms generated. These methods can only handle one type of controlled sources, namely voltage-controlled current sources. So, only RLCg m circuits can be analyzed. Also, the methods do not produce any symbolic term cancellations for RLC circuits and produce only a few for RLCg m circuits. Recently, however, some solutions to these problems have been presented through the addition of other algorithms to the process. The circuit size and cancellation problems were solved by using approximation techniques during the generation of the symbolic terms. That is, insignificant terms, based on knowledge of their nominal values, are eliminated during the process and therefore avoid the large number of symbolic terms generated [7], [8]. This section will first present the directed tree enumeration method and then present the undirected tree enumeration method.
2.3.1. Directed Tree Enumeration The basic idea of the directed tree enumeration method is to construct an augmented circuit (a slightly modified version of the original circuit) and its associated directed graph (see definition 2.5) and then enumerate all the directed trees of the graph [10]. The admittance products of these trees are then used to find the nodal admittance matrix determinant and cofactors (which itself is never constructed) to produce the required symbolic transfer functions. For a circuit with n nodes, where the input is an excitation
30
Chapter 2
Symbolic Analysis Techniques: A Review
between nodes 1and n and the output is taken between nodes 2 and n; the transfer functions of the circuit can be written as Z.In
V()
I.In V() V.In
VI
= II = V
= II2 = V
dll d d I2 d d l2
2 = VI = d}}
(2-4)
(2-5)
(2-6)
where Ll is the determinant of the nodal admittance matrix Yn (dimension n - 1 x n - 1) and Llij is the ijth cofactor of Yn' It can be shown that a. simple method for obtaining d, d}}, d12' is to construct another circuit comprised of the original circuit with an extra admittance )'~\' in parallel with a voltage controlled current source i«; V2 n ) draped across the input terminals (nodes 1 and n). The determinant of J;; (the nodal admittance matrix for the new, slightly modified, circuit) can be written as (2-7) This simple trick allows the construction of the determinant expression of the original circuit and its two needed cofactors by constructing the expression for the new augmented circuit. Example 2.1 (presented later in this section) illustrates this process. The basic steps of the tree enumeration algorithm are (condensed from Ref. [11]): 1. Construct the augmented circuit from the original circuit by adding an admittance y's and a transconductance (g'm . V o ) in parallel between the input
2. 3.
4.
5.
node and the reference node. Construct a directed graph Gind associated with the augmented circuit. The stamps used to generate Gind are shown in Fig. 2.1a and b. Find all directed trees for Gind. A directed tree rooted at node i is a subgraph of Gind with node i having no incoming branches and every other node having exactly one incoming branch. Find the admittance product for each directed tree. An admittance product of a directed tree is simply a term that is the product of all the weights of the branches in that tree. Apply the following theorem: Theorem 2.1 [11]: For any RLCg m circuit, the determinant of the node admittance matrix (with any node as the reference node) is equal to the sum of all directed tree admittance products of Gind (with any node as the root). In other words,
/).' =
Ltree admittance products
(2-8)
Arranging (2-8) in the form of (2-7) results in the necessary determinant and
Sec. 2.3
31
Tree Enumeration Methods
i
~ j
(a)
p
•
+
gm Vpq
•q -gm
(b)
Figure 2.1 Element stamps for generating Gjnd: (a) for a conductance; (b) for a voltage-controlled current source.
cofactors of the original circuit, and the needed transfer functions are generated from (2-4), (2-5), and (2-6). EXAMPLE 2.1
A circuit and its augmented counterpart are shown in Fig. 2.2. The circuit is the small-signal model of a simple inverting CMOS amplifier shown with the coupling capacitance C; taken into account. Figure 2.3 shows the directed graph associated with the Cc
---)t---......t----.. . 2
11-1
go
o (b) v1
Cc
(a)
(c)
o
Figure 2.2 Circuit of example 2.1 and its augmented circuit: (a) an inverter; (b) its small-signal model; (c) its augmented circuit.
32
Chapter 2
Symbolic Analysis Techniques: A Review
sC c• g'm t - - - -. . .- - - - - I 2
sCc- g'm
Figure 2.3 Graph and directed trees of example 2.1.
augmented circuit constructed using the rules shown in Fig. 2.1. The figure also shows all the directed trees rooted at node 0 of the graph. Parallel branches heading in the same direction are combined into one branch with a weight equal to the sum of the weights of the individual parallel branches. Applying (2-8) and rearranging the terms results in fl' = (sC c - gm) (g'm + y's) + (sC c - g'm)
ts; + go)
+ (g'm + y's)
i»; + go)
(2-9) (2-10)
(2-11) (2-12) Note that (2-9), which is the direct result of the algorithm, is not cancellation-free. Some terms cancel out to result in the determinant of the original circuit and its two cofactors of interest. The final transfer functions can be readily obtained by substituting these results into (2-4), (2-5), and (2-6). For example, the voltage transfer function for the circuit just analyzed, from (2-6), is V21V1 = (sC c - gm) I (s C; - g().
Sec. 2.3
Tree Enumeration Methods
33
2.3.2. Undirected Tree Enumeration The undirected tree enumeration method is also referred to as the two-graph tree enumeration method. It is based on the construction of tw0 2 slightly different undirected graphs of the RLCg m circuit, a voltage graph G v and a current graph Gb and then enumeration of all trees that are common to both graphs and appropriate 2-trees common in both graphs (defined later) [12]. The goal is to obtain the determinant and necessary cofactors (8, 811' 8(2) of the nodal admittance matrix Yn to generate the transfer functions (2-4), (2-5), and (2-6). The two graphs of a circuit G v and GJ are identical for RLC circuits but differ for the case of RLCg m circuits. For an RLC circuit, the construction of G v or GJ (because they are identical) is done by replacing every circuit node by a graph node and replacing every circuit branch by a graph branch with weight equal to the admittance of the branch. There is a one-to-one correspondence between the circuit size and the graph size, and the construction of the graph is very simpler' For RLCg m circuits, which are of more interest here, the two graphs differ slightly. The construction of both G v and GJ starts by replacing each node in the circuit by a node in G v and GJ. Next, the R, L, and C elements are handled by replacing each one of those branches by a graph branch in both G v and Gb with the weight being the admittance of the branch. Now, the handling of gm branches is different for each graph. For the voltage graph G v , each controlled current source gm Vi} between nodes p and q is replaced by a branch between graph nodes i and} with admittance gm. For the voltage graph Gb each controlled current source gm Vi} between nodes p and q is replaced by a branch between graph nodes p and q with admittance gm. Example 2.2 illustrates the procedure.
EXAMPLE 2.2 Consider the circuit in Fig. 2.2b. Its two graphs, Gv and Gb are shown in Fig. 2.4.
Figure 2.4 The two graphs of Fig. 2.2b.
The determinant of the nodal admittance matrix Y n of a circuit can be given using the concept of two graphs.
~ =
L
f.; (ith common tree admittance product)
(2-13)
all common trees
where Ei is the sign of the ith common tree and is given by 2 It must be noted that a single graph implementation of the method was recently presented in Ref. [7]. 3 These graphs should not be confused with the signal flowgraph of a circuit, which is discussed in section 2.4.1.
34 f.i
=
Chapter 2
l
major of A I for the ith common tree
X
Symbolic Analysis Techniques: A Review
major of A V for the ith common tree )
= ±1
(2-14)
Al and A y are the incidence matrices for GI and G y , respectively [12].
It must be noted that for a tree in G y , call it T y, and a tree in Gb call it Tb to be common, each branch in T v due to circuit element b must have a corresponding branch due to b in TI . This is a very important point here. While for an RLC circuit, the two graphs are identical and a common treeto both graphs has the same topology, for an RLCg m this is not the case. The branch in G y due to a gm branch does not have the same topology as the branch due to gm in Gb as illustrated in Fig. 2.4. To further illustrate this concept, Fig. 2.5 shows the branch correspondence between the two graphs by giving each branch a label and a subscript. Now, enumerating all the trees in G y yields a.b., avcv' and bvcv. Enumerating all the trees in GI yields ab, and ajcj. The common trees to G y and GI are (avbv' ajb j) and (avcv' ajcj). Note that although a\-.c v and ajcj are common trees, they do not have the same topology. The determinant of the circuit for this example can readily be obtained from (2-13) and (2-14) as ~
= sC co g + sC cm g = sC c(go+m g )
(2-15)
which matches (2-10). The cofactors ~ll and ~12 needed to find the transfer functions in (2-4), (2-5), and (2-6) are found by enumerating a subset of the common 2-trees in both graphs. The definition of a 2-tree follows [9].
Definition 2.6-2-tree: a 2-tree of a connected, undirected graph is a pair of node-disjoint, connected, loopless subgraphs (each subgraph is possibly an isolated node), which together include all nodes of the graph. For a connected graph of n nodes, every 2-tree has (n - 2) branches. Also, any loopless set of (n - 2) branches, together with possibly one or two isolated nodes, form a 2-tree of the graph. Figure 2.6 shows an undirected graph G and all its 2-trees. The symbol for a 2-tree is Tij....pq..•' where the subscript (ij...,pq...) denotes all 2-trees with nodes ij... and nodes pq ... not spanned by the same subtree. So, for example, in Fig. 2.6, the 2-trees belonging to the set TO,1 are TO,124' T024 ,1' and T04,12' The weight of a 2-tree Wjj ...,pq... is given by the sum of the product of all branch weights of all spanning trees of Tij..,pq.... For example, WO,124 = ab, while WO,l
= ab + be + ac.
Figure 2.5 Corresponding branches in the two graphs.
Sec. 2.3
35
Tree Enumeration Methods
TO,124
TO12,4
T04,12
Figure 2.6 An undirected graph G and all its 2-trees.
The cofactor dll is produced by summing all common W1,o 2-tree weights and the cofactor dl2 is produced by summing all common W I2,O and W 1,2 2-tree weights. The signs for the terms in these cofactors are calculated similar to (2-14), and is an involved process. A detailed discussion of the process is available in [12]. Figures 2.7 and 2.8 show the common 2-trees needed for the circuit in Fig. 2.2b. The results for dll and dl2 readily match the results in (2-11) and (2-12).
ri\__
Iv
1"::\
TI,O
Figure 2.7 Common 2-trees T1,o, T12,O, and T1,2.
36
Chapter 2
T12,O
Symbolic Analysis Techniques: A Review
®
Figure 2.8 Common z-frees T12 ,O and T1,2.
2.4. FLOWGRAPH (TOPOLOGICAL) METHODS Two types of flowgraphs are used in symbolic analysis. The first is referred to as a Mason signal flowgraph and the second as a Coates graph. The Mason signal flowgraph is by far a more popular and well-known topological approach that has been used extensively in symbolic analysis, among other control applications. Both the Mason signal flowgraph and the Coates graph are used as the basis for hierarchical symbolic analysis. However, the Coates graph was introduced to symbolic analysis by Starzyk and Konczykowska [1] solely for the purpose of performing hierarchical symbolic analysis. This section will cover both approaches.
2.4.1. The Mason Signal Flowgraph The symbolic methods developed here are based on the idea formalized by Mason [13] in the 1950s.Formulation of the signal flowgraph (SFG) and then the evaluation of the gain formula associated with it (Mason's formula) is the basis for symbolic analysis using this method. This method is used in the publicly available programs NASAP [14], [15] and SNAP [16] in addition to more recent programs like ASAP [17] and MASSAP [3]. The method has the same circuit size limitations as the tree enumeration method due to the exponential growth in the number of symbolic terms. However, the signal flowgraph method allows all four types of controlled sources to be analyzed, which makes it a more popular method for symbolic analysis. The method is not cancellation-free, which contributes to the circuit size limitation mentioned earlier. An improved signal flowgraph method that avoids term cancellations was described in [18]. The analysis process of a circuit consists of two parts: the first is to construct the signal flowgraph for the given circuit, and the second is to perform the analysis on the signal flowgraph. Some definitions are needed before proceeding in the details of these two parts.
Sec. 2.4
Flowgraph (Topological) Methods
37
Definition 2.7-signal flowgraph: a signal flowgraph is a weighted directed graph representing a system of simultaneous linear equations. Each node (x;) in the signal flowgraph represents a circuit variable (node voltage, branch voltage, branch current, capacitor charge, inductor flux, etc.) and each branch weight (w;j) represents a coefficient relating x; to Xj. Every node in the signal flowgraph can be looked at as a summer. For a node xk with m incoming branches, (2-16) where i is the indices of all incoming branches from x; to xk.
Definition 2.B-path weight: the weight of a path from x; to Xj (P;j) is the product of all the branch weights in the path.
Definition 2.9-100p weight: the weight of a loop (L;) from x; to itself is the product of all the branch weights in that loop. This also holds for a loop with only one branch in it (self-loop).
Definition 2.1 O-nth-order loop: an nth-orderloop is a set of n loops that have no common nodes between them. The weight of an nth-order loop is the product of the weights of all n loops. See example 2.4 for an illustration of nth-order loops. Any transfer function x.fx., where x,' is referred to as the source node, can be found J I by the application of Mason's formula: (2-17) where
d
= 1-
(sum of all L;'s)
+ (sum of all second-order loop weights)
(2-18)
- (sum of all third-order loop weights)
+ ...
11k =11
with all loop contributions that are touching Pk eliminated
(2-19)
The construction and the use of these equations are best illustrated via a couple of examples. Example 2.3 shows how to systematically construct a compact SFG, and example 2.4 illustrates the concepts of nth-order loops.
EXAMPLE 2.3 Consider the circuit in Fig. 2.9. The formulation of the signal flowgraph for this circuit takes on the following steps:
38
Chapter 2
Ie
Symbolic Analysis Techniques: A Review
~
go Figure 2.9 Circuit for example 2.3 with its highlighted tree.
1. Find a tree and cotree of the circuit such that all current sources are in the cotree and all the voltage sources are in the tree. 2. Use Kirchhoff's current law (KCL), branch admittances, and tree branch voltages to find an expression for every cotree link current. In the case of a controlled source, simply use the branch relationship. For the present example, this yields (2-20) (2-21 ) 3. Use Kirchhoff's voltage law (KVL), branch impedances, and cotree link currents to find an expression for every tree branch voltage. In the case of a controlled source, simply use the branch relationship. For the present example, this yields
V
go
1 =V2=-(-I+I) go
C
(2-22)
4. Create the signal flowgraph by drawing a node for each current source, voltage source, tree branch voltage, and cotree link current. 5. Use (2-16) to draw the branches between the nodes that realize the linear equations developed in the previous steps. Figure 2.10 shows the result of executing these five steps on the example circuit. This formulation is referred to as the compact signal flowgraph. Any other variables that are linear combinations of the variables in the signal flowgraph (e.g., node voltages) can be added to the signal flowgraph by simply adding the extra node and implementing the linear relationship using signal flowgraph branches. A more detailed discussion of signal flowgraphs can be found in Refs. [11] and [9]. Now, applying (2-18) and (2-19) yields
p
2
sC =_c
g
o
The final transfer function is then produced by (2-17) and is
Sec. 2.4
Flowgraph (Topological) Methods
39
Figure 2.10 Signal flowgraph for example 2.3.
(2-23)
Several comments must be made about the previous steps for formulating a compact SFG. The procedure will never result in a self-loop, that is, a loop that starts and ends at the same SFG node, or parallel branches. While this does not affect the construction of the transfer function of (2-17), it does simplify the procedure for finding (2-18). Another comment is that if sources exist in the circuit (independent or dependent), then the independent and controlled voltage sources must never form a loop, and the independent and controlled current sources must never form a cutset. The reason for this is that a loop of voltage sources results in an undetermined loop current, and a cutset of current sources results in an undetermined cutset voltage. Also, these two conditions guarantee the existence of a tree that contains all the voltage sources, and a cotree that contains all the current sources. The simplest procedure to incorporate all types of controlled sources in the SFG formulation described in example 2.3 is to replace all controlled sources by independent sources, construct the compact SFG according to the given steps and then add the constraints of the controlled sources to the SFG. A more detailed discussion of these comments can be found in Ref. [11]. A major challenge of applying (2-18) is the listing of all paths from input to output node in the SPG in addition to the finding of all order loops. Many algorithms exist for path enumeration because of the widespread applications that require the process [19], [14], [16]. The finding of nth-order loops has much more limited applications. A simple algorithm to implement would be to split each node i in the SFG, one at a time, into two nodes i and i'. To find first -order loops, all paths from i to i' are found, the branches deleted, and the process repeated for the next node. Finding nth-order loops (where n > 1) can proceed by examining all permutations of the first-order loops. This is a brute force approach and more efficient algorithms do exist to find nth-order loops [11]. The discussion of specific algorithms for finding paths and nth-order loops is beyond the scope
40
Chapter 2
Symbolic Analysis Techniques: A Review
of this book. However, example 2.4 illustrates the concepts and shows the results for a more complicated SFG than the one presented in example 2.3.
EXAMPLE 2.4 Consider the SFG in Fig. 2.11 with node 1 as the input node and node 13 as the output node. There is only one forward path between nodes 1 and 13: p} = agklpu. WEIGHTS OF FIRST-ORDER
= gklidc
L2 = ef
L4
L7
L9 = qr
= klptsn SECOND-ORDER
L}L 2 L2L 3
Loops
L IL 7
L2L6
L}L6 L2L7
L2L 8
L3L s
L3L 8
L3L 9
L3L IO
L4L 9 LsL6
L4L}O LsL9
LSL}O
L6L 8
L6L}O
L8L9
L9L}O
L}L S
Loops
L}L 8 L2L9
L}L 9
LIL}O
L2L}O
The weight of a second-order loop is simply the product of both loop weights (e.g., the weight of L}L 2 = abef).
Figure 2.11 SFG of example 2.4.
Sec. 2.4
41
Flowgraph (Topological) Methods THIRD-ORDER
Loops
L1L2L6
L1L2L7
L 1L2L g
L1L2L9
L1LsL6
L1LsL9
L1LsL 1O
L1L6L g
L1L6L 1O
L1L2L 1O
L1L gL 9 L1L9L 1O L2L3L g L2L 6L g
L2L3L9 L2L 6L 1O
L2L3L 1O
L2L gL 9 L2L 9L 1O L3LsL9 L3L gL 9
L3LsL1O
L3L9L 1O L4L 9L 1O LSL 6L g
LsL6L 1O
LsL9L 1O The weight of a third-order loop is simply the product of both loop weights (e.g., the weight of L1L2L 6 = abefmns. FOURTH-ORDER
Loops
L1L 2L6L g L1L2L gL 9 LIL2L9LIO L1L SL6L g LILsL9LIO L2L 3L gL 9 L2L3L9LIO L3LsL9LIO The weight of a fourth-order loop is simply the product of both loop weights (e.g., the weight of L 1L2L6 Lg = abefmnop).
42
Chapter 2
Symbolic Analysis Techniques: A Review
Applying (2-18) yields L\. Notice that only two first-order loops and one second-order loop do not touch the only path between nodes 1 and 13. Applying (2-17),
= 1 - (L 2 + L 9 ) + (L 2L9 ) · Another solution process to find the final transfer function of a circuit is presented in Ref. [3]. It was proposed and used as part of a hierarchical symbolic signal flowgraph method and therefore is presented as part of chapter 5 (section 5.4). therefore, yields
~l
2.4.2. The Coates Graph The Coates graph representation of a simultaneous linear system of equations is a directed graph with each node representing one of the equations of the system. Each node (xi) in the Coates graph represents a circuit variable and each branch weight (wi}) represents a coefficient relating xi to xj- At node k, the weighted sum of all the nodes that have branches incoming to node k is O. In other words, (2-24 )
where i is the indices of all incoming branches from xi to xk. For the Coates graph, the transfer function is expressed as the ratio of the graph's I-connection, which is dependent on the input variable and the output variable selected, to the graph's O-connection, which is global to all the circuit's transfer functions (i.e., independent of the input/output (I/O) variables selected) [20]. A generalization of Coates l-connection and O-connection is referred to as a k-connection or a multiconnection [1]. The program FLOWUP [1], [21] is based on this topological method. To illustrate the concept of a k-connection, the symbolism of a directed graph presented in definition 2.5 is used. Definition 2. JJ [1]-Multiconnection or k-connection: a k-connection (multiconnection) of a directed graph G with n nodes is a subgraph Pj with n nodes, e node-disjoint directed edges, d isolated nodes, and I node-disjoint directed loops, where k = e + d. In other words, a k-connection has exactly e nontouching edges, d nodes with no incoming or outgoing branches, and an unlimited number of loops. The weight of a k-connection is given by
(2-25)
and the weight of a set of multiconnections P is given by
IPI
=
L sign PjE P
where
Pj
(2-26)
Sec. 2.5
43
Parameter Extraction Methods n+k+l
sign p = (-1)
p
ord (vI' ... , V k ) . ord (UI' ... , Uk) when the number of permutations ordering the set is even
-1
(2-27)
otherwise
(lp number of loops in multi connection p). The transfer function of a circuit with input variable vI and output variable v2 is, therefore,
H(s,v 3,v4 , ···) =
.vr
IP I-connection \P
I
21
(2-28)
Ovconnection
The I-connection vl _>v2 is the set of all I-connections that include a directed path (a set of directed edges) that connect graph nodes v I to "z-
EXAMPLE 2.5 As an example, consider the circuit in Fig. 2.I2a. To find V2 / /1' the I-connection vl_>v2 is needed. Only one such subgraph exists, Fig. 2.I2b. However, the O-connection set has two members, illustrated in Fig. 2.I2c, so
= =
IP l-connection, 1->\,21
\PO-connection\
(-sC 2 + gm )
(2-29)
(g2 + sC 2)
The Coates graph use in electrical engineering application is limited compared to its counterpart, the Mason signal flowgraph. The most automated mechanism for building the Coates graph for a circuit is an element stamp approach, which is fully illustrated in Ref. [1] and will not be addressed here. Of course, another approach would be to write the simultaneous linear equations for the system, assign a node to each variable, and construct the graph from there.
2.5. PARAMETER EXTRACTION METHODS This method is best suited when few parameters in a circuit are symbolic, while the rest of the parameters are in numeric form (s being one of the symbolic variables). The method was introduced in 1973 [22]. Other variations on the method were proposed later, in Refs. [23] and [24]. The advantage of the method is that it is directly related to the basic determinant properties of widely used equation formulation methods like the modified nodal method [25] and the tableau method [26]. As the name of the method implies, it provides a mechanism for extracting the symbolic parameters out of the matrix formulation, breaking the matrix solution problem into a numeric part and a symbolic part. The numeric part can then be solved using any number of standard techniques and then
44
Chapter 2
+ 91
V
Symbolic Analysis Techniques: A Review
c,
(a)
gm- S C2 (b)
o
(c)
cO
(d)
Figure 2.12 A circuit, its Coates graph, and its multiconnections: (a) example circuit [1]; (b) Coates graph; (c) 1-connections; (d) O-connections.
recombined with the extracted symbolic part. The method has the advantage of being able to handle larger circuits than the previously discussed fully symbolic methods if only a few parameters are represented symbolically. If the number of symbolic parameters in a circuit is high, the method will exhibit the same exponential growth in the number of symbolic terms generated and will have the same circuit size limitations as the other algorithms previously discussed. The method does not limit the type of matrix formulation used to analyze the circuit. However, the extraction rules depend on the pattern of the symbolic parameters in the matrix. Reference [27] uses the indefinite admittance matrix as the basis of the analysis and the rules depend on the appearance of symbolic parameters in four locations in the matrix: (i, i), (i, j), (j, i), and (j, j). Reference [23] uses the tableau equations and can handle a symbolic parameter that only appears once in the matrix. Sannuti and Puri [24] force the symbolic parameters to appear only on the diagonal, using a 2-graph method [12] to write the tableau equations. To illustrate the concept of parameter extraction, this section will
Sec. 2.5
45
Parameter Extraction Methods
concentrate on the indefinite admittance matrix (lAM) formulation and RLCg m circuits. Details of other formulations can be found in Refs. [9], [23], [24] and [18]. One of the basic properties of the lAM matrix is the symmetric nature of the entries sometimes referred to as quadrature entries [11], [9]. A symbolic variable a will always appear in four places in the matrix, +a in entries (i, k) and (j, m), and -a in entries (i, m) and (i, k), as shown in the following equation:
k
m
a
-a (2-30)
j
-a
a
where i -:;:. j and k -:;:. m . For the case of an admittance y between nodes i andj, then k = i and j = m. The basic process of extracting the parameter (the symbol) a can be performed by applying the following equation [11], [22]: cofactor of Yind = cofactor of (Yind , a=O) + (-ly+m a (cofactor of Ya )
(2-31)
where Ya is a matrix that does not contain a and is obtained by: 1. Adding row j to row i. 2. Adding column m to column k. 3. Deleting row j and column m. For the case where several symbols exist, this extraction process can be repeated, and would result in cofactor of Yin d =
L P (cofactor of j
Y}
(2-32)
where Pj is some product of symbolic parameters including the sign and lj is a matrix with the frequency variable s, possibly being the only symbolic variable. The cofactor of lj may be evaluated using any of the typical evaluation methods [11]. EXAMPLE 2.6 [11]
Consider the resistive circuit in Fig. 2.13. The goal of this example is to find the input impedance Zl4 using the parameter extraction method, where g m is the only symbolic variable in the circuit. In order to use . (2-4) and (2-7), a source admittance y's is added across the input terminals of the circuit to
46
Chapter 2
Symbolic Analysis Techniques: A Review
5 mhos
2
2mh
y's
0.1 mho
4 Figure 2.13 Circuit for the parameter extraction method.
create the augmented circuit (note that all numerical values are admittances rather than resistances). The lAM matrix is then written as
r'd= In
6+y' s
-5
-1
-y's
g m -5
15.1
-g m -10
-0.1
-gm -1
-10
gm + 13
-2
-y's
-0.1
-2
y's + 2.1
(2-33)
Applying (2-31) to extract y's results in
cofactor of lind = cofactor of
6 gm -5
-5
-1
0
15.1
- gm -10
-0.1
-gm -1
-10
gm + 13
-2
0
-0.1
-2
2.1
8.1
-3
+ y's . cofactor of gm - 5.1
-5.1 15.1
-gm -10
-gm- 3
-10
«; + 13
Applying (2-31) again to extract gmresults in
(2-34)
Sec.2.6
47
Interpolation Methods
6 -5 -1 0 - 5 15.1 -10 -0.1 = cofactor of 1 -10 13 -2 o -0.1 -2 2.1
lind
cofactor of
5 -5 0] [-2 -0.1 2.1
+ g m . cofactor of -3 5.1 -2.1
(2-35)
8.1 -5.1 -3J [
+ y's . cofactor of -5.1 15.1 -10 -3 -10 13 + y' g . cofactor of [5.1 -5.1] s m -5.1 5.1 After evaluating the cofactors numerically, the equation reduces to
lind
cofactor of
= 137.7 + 10.5gm + 96.3y's + 5.1y'sgm
(2-36)
From (2-4) and (2-7), this results in
96.3 + 5.lg m 137.7 + 10.5gm
(2-37)
2.6. INTERPOLATION METHODS This method is best suited when s is the only symbolic variable. The method requires the finding of the coefficient of the determinant's polynomial by evaluating it at different values of s. A serious disadvantage of this method is that, for circuits with over 20 nodes, using real values for s leads to ill-conditionedequations and results in inaccurate solutions [28]. Therefore, it is best to use complex values for s. This can be done by the manipulation of the nodal admittance matrix Yn to write it in the form: Yn = sA +B
(2-38)
where A and Bare n X n real matrices. The determinant of Yn , which is a function of s, can then be written as a polynomial of degree n or lower n
~(s) = £..J ~ k.s! = k o +kls+k2s2+k3s3+ ... +k n s" I _
(2-39)
; =0
The k;'s in these equations are numeric constants that are calculated by evaluating the polynomial at n + I different values of s and then solving the following set of linear equations:
48
Chapter 2
Symbolic Analysis Techniques: A Review
ko 1 So s2 0 ... s8
1 sl s2I ... sl kl =
(2-40)
An advantage of the mostly numeric nature of this method is that the fast Fourier transform can be used to find the coefficients, which greatly enhances the execution time of this method [9]. Singhal and Vlach [28] extended the method to handle several symbolic variables in addition to s. The program implementation [29] allows a maximum of five symbolic parameters in a circuit.
2.7. MATRIX-BASED METHODS The following two classes of methods are based on the idea of generating the fully symbolic circuit equations directly from the circuit description and then putting them into the following linear matrix form:
Ax = b where A is a symbolic matrix of dimension n
(2-41 )
x n, x is a vector of circuit variables of length
n, and b is a symbolic vector of constants of length n; n, of course, is the number of circuit
variables: currents, voltages, charges, or fluxes. The analysis proceeds by solving (2-41) for x. This is where this method's two subclasses, determinant-based methods and parameter reduction methods, differ. The generation of matrix (2-41) can be done using one of several classic numerically based techniques like nodal analysis and its modifications, hybrid analysis and sparse tableau analysis [11]. The most common symbolic formulation is the modified nodal analysis (MNA) and modifications to it, like reduced MNA formulations (RMNA) [30], compacted MNA formulations (CMNA) [31], and supernode analysis (SNA) [32]. The basic symbolic MNA formulation is, therefore, presented in the following section.
2.7.1. The Modified Nodal Analysis The initial step of MNA is to formulate the nodal admittance matrix Y [25] from the circuit. The circuit variables considered here are all the node-to-datum voltages, referred to simply as node voltages; there are n v of them. They are included in the variable vector V. So V has the dimensions of (n v xI). The vector J, also of dimension (n v x l ), represents the values of all independent current sources in the circuit. The ith entry of J represents a current source entering node i, The nodal linear system of equations can be represented in the following matrix form:
YV=J
(2-42)
Sec. 2.7
49
Matrix·Based Methods
Row i of Y represents the KCL equation at node i. Y is constructed by writing KCL equations at each node except for the datum node. The itb equation then would state that the sum of all currents leaving node i is equal to zero. The equations are then put into the matrix form of (2-42). The following example illustrates the process.
EXAMPLE 2.7 Consider the circuit in Fig. 2.14. Collecting the node voltages would produce the following
V:
(2-43)
Considering all the current sources in the circuit, the vector J becomes
(2-44)
Now, writing KCL equations at the three nondatum nodes produces
(2-45) (2-46) (2-47) Substituting VR = v I - v2 in these three equations and rearranging their variables results 3 in
L7
CD
i
11
R3
C6
R2
Figure 2.14 MNA example circuit.
50
Chapter 2
Symbolic Analysis Techniques: A Review
(2-48)
(2-49) (2-50) Now, realizing the form of (2-42) would yield the nodal admittance matrix of this circuit Y:
G2+G 3+ -G 3 1
1
y s 7
g -s sL 7
1 sL 7
-G 3 G3+GS+sC6
-sC6
- (gg + sC 6 )
-+sC sL 7 6
1
vI
JI
v2 =
J4
v3
0
(2-51 )
An automatic technique to construct the nodal admittance matrix is the element stamp method [25]. The method constitutes going through each branch of the circuit and adding its contribution to the nodal admittance matrix in the appropriate positions. It is a very nice and easy way to illustrate the impact of each element on the matrix. Figure 2.15 shows the element stamp for any conductance (G, sC, or l/sL), Fig. 2.16 shows the
y
J/y
i
j
j
iy
-;]
iy Y -Y -1
i y not a variable
i y a variable
i[ Y
J -Y
i[~] -1
j
Figure 2.15 Conductance branch element stamp.
J,
J
Figure 2.16 Current source element stamp.
Sec. 2.7
51
Matrix-Based Methods
element stamp for an independent current source, and Fig. 2.17 shows the element stamp for a voltage-controlled current source (VCCS). These are the only types of elements allowed by the nodal analysis. Resolving example 2.7 using the element stamps would produce exactly the same Y matrix, V vector, and J vector as in (2-51). i'
k
+ y
I
-8",] 8m
Figure 2.17 VCCS element stamp.
The modified nodal analysis technique introduced in Ref. [25] expands on nodal analysis in order to readily include independent voltage sources and the three other types of controlled sources: voltage-controlled voltage source (VCVS), current-controlled current source (CCCS), and current-controlled voltage source (CCVS). This is done by introducing some branch currents as variables into the system of equations, which in tum allows for the introduction of any branch current as an extra system variable. Each extra current variable introduced would need an extra equation to solve for it. The extra equations are obtained from the branch relationship (BR) equations for the branches whose currents are the extra variables. The effect on the nodal admittance matrix is the deletion of any contribution in it due to the branches whose currents have been declared as variables. This matrix is referred to as Yn . The addition of extra variables and a corresponding number of equations to the system results in the need to append extra rows and extra columns to Yn . The augmented Ym matrix is referred to as the MNA matrix. The new system of equations, in matrix form, is
[~ [~ [~] ;]
=
(2-52)
where 1 is a vector of size n; whose elements are the extra branch current variables introduced, E is the independent voltage source values, and C and D correspond to BR equations for the branches whose currents are in I. According to Ref. [25], the MNA current variables should include all branch currents of independent voltage sources, controlled voltage sources, and all controlling currents. However, with some extra manipulations for CCVS and CCCS, the number of extra current variables required by the MNA could be reduced, in turn reducing the size of the MNA matrix. Each of the new elements that the MNA allows over the nodal analysis is examined in the following steps. These elements, as mentioned earlier, are
1. Independent voltage source (Fig. 2.18). iv E I is the extra current variable and the extra equation is the BR provided by the independent voltage source, which is
52
Chapter 2
Symbolic Analysis Techniques: A Review
~v +
v
Figure 2.18 Voltage source element stamp.
=V
v.-v. J
I
(2-53)
So V becomes an entry in E. Also, iv will appear in the KCL equations at nodes i and j. The element stamp for an independent voltage source is illustrated in Fig. 2.18.
2. Voltage-controlled voltage source, VCVS (Fig. 2.19). iv E I is the extra current variable and the extra equation is the BR provided by the vevs, which is v.-v.
J
I
Because Vy
= vk -
= JlVY
(2-54)
vI' (2-54) becomes
vi - vj - Jlv k + Jlv I = 0
(2-55)
The element stamp for a vevs is illustrated in Fig. 2.19.
3. Current-controlled voltage source, CCVS (Fig. 2.20). The MNA proposed in Ref. [25] would require that both the dependent voltage source current iccvs and the controlling current i y be included as variables. However, that is unnecessary. Recognizing that ', = Y (v k - v/) would enable the elimination of iy from being an extra variable, therefore reducing the size of the MNA matrix. So, i v E I is the only extra current variable and the extra equation is the BR provided by the
cevs and the controlling branch, which is
k
+
v
i i[d k Iii] j
j
i." 1 -1
-1
-~
J.l Figure 2.19 VCVS element stamp.
Sec. 2.7
53
Matrix-Based Methods
k
Figure 2.20
eevs element stamp.
(2-56) Because iy
=Y (vk - vi), (2-56) becomes (2-57)
v;-vj-rYvk+rYv i = 0
The element stamp for a CCVS is illustrated in Fig. 2.20.
4. Current-controlled current source, CCCS (Fig. 2.21). The MNA proposed in Ref. [25] would require that the controlling current iy be included as variables. However, that is unnecessary. Recognizing that iy = Y (vk - vi) would enable the elimination of iy from being an extra variable, therefore introducing no extra variables to the MNA matrix. So the CCCS's current can be expressed as (2-58) and immediately entered in the MNA matrix in that form. The element stamp for a CCCS is illustrated in Fig. 2.21.
EXAMPLE 2.8 As an example of an MNA matrix formulation, consider the circuit of Fig. 2.22. The extra current variables are the branch current of the independent voltage source (branch 1) and the CCVS (branch 5). They are referred to as i 1 and i5, respectively. Using element stamps, the MNA system of equations becomes
i· I~
y
k
[PY
i j -JjY Figure 2.21
eees element stamp.
1
-py{jY
1
54
Chapter2
Symbolic Analysis Techniques: A Review
Lg
i
Jll
-Figure 2.22 Circuitof example 2.8.
(2-59) G2
-G 2
1
0
0
0
-G 4
-1 sL g
0
0
0
G 4 + sC7
-sC7
0
0
0
0
v3 . v 4 0
2
-G 2
G 2+G 3+G 4+
3
~9G2
-G4-~9G2
4
-~9G2
-1 sL + ~9G2
-sC7
0
0
0
0
1
0
0
0
-rSG 3
1
0 0
5
xl x2
g
sy g
G 6+sC7+
1
sy g
0
G IO 0
0 -1
0 0
-1
0 0
vI v2
Vs
iI is
0 0 0 1 11
0 VI
0
2.7.2. Determinant-Based Solutions Here, the basic idea is to apply an extension of Cramer's rule, symbolically, to find a transfer function from the formulated matrix (2-52). Cramer's rule leads to the fact that a transfer function can be obtained from (2-41) as follows: (2-60)
where for
IA (i) I is the determinant of A with column i replaced with the vector b, and similarly
IA U) I.
Sec. 2.7
55
Matrix-Based Methods
Several symbolic algorithms are based on the concept of using Cramer's rule and calculating the determinants of an MNA matrix. Most notably is the program ISAAC [31], which uses a recursive determinant-expansion algorithm to calculate the determinants of (2-60). Although there are many other algorithms to calculate the determinant of a matrix, like elimination algorithms and nested minors algorithms [33], recursive determinant-expansion algorithms were found the most suitable for sparse linear matrices [34]. These algorithms are cancellation-free, given that all the matrix entries are different, which is a very desirable property in symbolic analysis. The determinant of A is calculated by n
IAI
= ~ £..J (-1) i +l a I}..IM I}..1 J=
for (n > 1)
(2-61 )
I
for (n = 1)
= 1 where row i is an arbitrary row of matrix A, n
x n is the dimension of A, and IMijl is a minor
of A of dimension (n - 1) x (n - 1) with row i and column} removed.IMij\ is calculated by using (2-61) recursively. As an example, the determinant of a 3 x 3 matrix is calculated by this method as all
a
a
a
a
21 31
l2 22
Q 32
a l3 a a
23
= all
a a
22 32
a a
23
-a
33
a 12
a
21
a
31
a
23 33
+ a l3
a a
21
a
31
a
22 32
(2-62)
33
= QIIQ22Q33 -
alla32a23 - al2a2la33
+ QI2 a3l a23 + Ql3 a21 a32 -
al3Q3lQ22
Here, i was chosen to be, arbitrarily, row 1. The expression is cancellation-free here because all the matrix entries are unique. Note that for matrices with duplicated entries, the algorithm is not cancellation-free.
EXAMPLE 2.9 As an example, the transfer function v 3/v 1 for the circuit in Fig. 2.14 is to be calculated. Equation (2-51) shows its MNA formulation. Using (2-60) and the recursive application of (2-61) results in
56
Chapter 2
1
-G 3
11
G3+G5+sC6
14
-gg-sC6
0
G2+G 3+ y
S 7
-G 3
Symbolic Analysis Techniques: A Review
1 gg-d
7
~=~------------
VI
1 sL 7
-sC6
o (gs -
si;)
(-J4G3 -J I G 3 -JIGS -J I sC6 )
(2-63)
1 sC 6 + sL 7
+ (gs + sC6 ) (J4GZ + J4G3 +!i; + J I G 3
J
( 14 1 ) (gg+sC 6) -sC611+- + sC 6+- (11G3+11G5+11sC6+14G3) sL 7 sL 7
Close inspection of expression (2-63) will reveal that is not cancellation-free. This is due to the non-uniqueness of the matrix entries. For instance, in the numerator, the terms
ggG3J4 cancel out and the terms ggG3J 1 also cancel out. In the denominator, the terms s2C62J 1 cancel out.
2.7.3. Parameter Reduction Solutions These methods use basic linear algebra techniques, applied symbolically, to find the solution to (2-41). The goal here is to reduce the size of the system of equations by manipulating the entries of matrix A down to a 2 x 2 size. The two variables remaining in x are the ones for which the transfer function is to be calculated. The manipulation process, which in simple terms is solving for the two desired variables in terms of the others, is done using methods like Gaussian elimination [35]. This methodology is used in the symbolic analysis program SCAPP [2], which uses a successive application of a modified Gaussian elimination process to produce the transfer function of the solution. The process is applied to MNA matrices and the result is a reduced MNA matrix referred to as RMNA (YR). The process of reducing a circuit variable, whether a node voltage or branch current, is referred to as variable suppression. The modification process to the MNA is the suppression of all node voltages and current variables that are not input or output variables. They are referred to as internal variables. The system of equations that describes the circuit in terms of the external variables (circuit inputs and outputs) can be written as (2-64)
where Y Rn is the reduced nodal admittance submatrix, B R is the reduced contributions of the external currents to the KCL equations, CR and DR represent the reduced BR equations,
Sec. 2.7
57
Matrix-Based Methods
Ve is the vector of external node variables, and leis the vector of external current variables. The ith entry of the
Ie vector represents the external currents entering the circuit through
the ith node. The J R and the E R vectors represent the contributions of the independent current and voltage sources, respectively, internal to the circuit. The process of suppressing an internal node or an internal branch current, in mathematical terms, means solving for the variable in terms of the other system variables. A process to solve for a variable in terms of the other system variables can be done by using a single step of the Gaussian elimination method [35]. Each step of the Gaussian elimination method consists of reducing a system of n linear equations in n unknowns to a system of n - 1 linear equations in n - 1 unknowns by using one of the equations to eliminate one of the unknowns from the remaining n - 1 equations. The best way to illustrate the method is to consider an example.
EXAMPLE 2.10 Consider the following system of three linear equations and three unknowns: ( 1)
bllX l +b12x2+b13x3
(2)
b 2 l X 1 + b 22X 2
(3)
b 3l X l
+ b 23X 3
+ b 32X 2 + b 33X 3
= /1 = /2 = /3
(2-65)
The general matrix form for a linear system of equations can be written as
BX
=L
(2-66)
Therefore, equations (2-65) can be rewritten as follows: (1)
b l l b 12 b 13
Xl
(2)
b 2 1 b 22 b 23
X
(3)
b
X
31
b
32
b
33
2
(2-67)
3
Now, the process of eliminating equation x2 from the system requires the use of one of the three equations to do so. Without any loss of generality and in order to maintain a certain symmetry in the process, the second equation is chosen. The process is equivalent to eliminating the second row and second column of B and the second entry in both X and
L. First x2 must be eliminated from the first equation. This is done by multiplying the second equation by b 121 b 22 and subtracting it from the first equation. The next step is to eliminate x2 from the third equation. This is done by multiplying the second equation by
b 321 b22 and subtracting it from the third equation. The results are: (1)
(2-68) (2)
58
Chapter 2
Symbolic Analysis Techniques: A Review
What has happened here is that the second equation was used to express x2 in terms of xl and x2. In matrix form, the process of suppressingthe second row and second column of B and the second entry in both X and L to produce B R, XR, and L R, respectively, can be expressed as (2-69)
(2-70) where C2 is the second column of B with b22 removed, R 2 is the second row of B with b22 removed, B er is B with the second column and the second row removed, and L er is L with the second entry removed. XR is simply X with x2 removed because it has been suppressed by equations (2-69) and (2-70). The new system of linear equations can be written in general terms as (2-71 ) and, for this specific example, as
b l2
b l2 xI _
22
b 32
x3
b 33 - l)b 23 22
22
b 32
(2-72)
13 - l)I 2 22
The previous example can be generalized for any system of linear equations in the
form of (2-66), to be reduced to the form of (2-71 ) where the variable Xj is to be suppressed. The suppression equations become BR = B
er
LR = L
er
1 --C.R.
b .. JJ
(2-73)
J J
1 --C.I. b .. J J
(2-74)
JJ
where Cj is thejth column of B with bjj removed, Rj is the jth row of B with bjj removed, B er is B with the jth column and the jth row removed, and L er is L with the jth entry removed. XR is simply X with Xj removed because it has been suppressed by (2-73) and (2- 74).
The effect of (2-73) on each element of B, or, in other words, the effect of reducing the variable Xj on any element of B, can be expressed as
b
pqR
b .
= bpq -J!l.b. b .. Jq
p:t j
JJ
The effect on the members of L can be expressed as
and
(2-75)
Sec. 2.7
59
Matrix-Based Methods
b . = [ _J!l.[. PR P b .. }
[
(2-76)
}}
The matrix entry bjj is referred to as the pivot, the entry bpj is referred to as the column pivot, and the entry bjq is referred to as the row pivot. Each column pivot is unique for each row in B and each row pivot is unique for each column in B. A simple example will serve to illustrate and easily verify the formulation of the RMNA matrix.
EXAMPLE 2.11 Consider the circuit in Fig. 2.23. Nodes 1 and 3 are the external nodes. The assumption is that all current variables are to remain internal; in this case i2. It must be noted that it makes sense that node 3 is the input terminal while node 1 is the output terminal. Therefore, any excitations will come via terminal 3. Using element stamps, the MNA matrix for this circuit is expressed as vI
v2
v3
i2
1
GI
-G}
0
0
2
-G}
G} + sC 3
-sC3
3
0
-sC3
sC 3 + G4
0
xl
0
1
-1l 2
0
(2-77)
To produce the RMNA matrix in terms of vI and v3 only, all the other variables must be suppressed. The anticipated result is a (2 x 2) RMNA matrix. Notice that an attempt to reduce the current variable i2 first would cause a problem. The reason is that the pivot is zero. Therefore, it is deferred to the end. A discussion of the reasons can be found in Ref. [30].
Figure 2.23 Circuit of example 2.11.
--
60
Chapter 2
Symbolic Analysis Techniques: A Review
So, the first step is to suppress the internal node 2. The pivot is G t+sC3 . Performing (2-73), the MNA matrix of (2-77) yields
0
Gt
o
0
sC 3+G4 0 -
0
0
-fl2
-G t
1
G t + sC 3 -sC3
-sC3
IJ
1
v3
v}
=
~GI
;2
G tsC 3
G}sC 3
G}
G} + sC 3
G I + sC 3
G I + sC 3
3
G IsC3
G IsC3
G} + sC 3
G I + sC 3
G}
xl
G 1 + sC 3
- fl + 2
+G 4
sC 3 G 1 +sC3
(2-78)
sC 3 G I + sC 3 1
G} + sC 3
Notice what happened here: the suppression of node 2, which is one of the nodes of the branch whose current is a variable, produced a fill in the pivot position for row Xl. This now allows for the suppression of the internal current variable ;2. Equation (2-73) is applied again to the matrix of (2-78) and results in (2-79)
G 1sC3
G 1sC3
G I +sC3 G 1sC3
G I +sC3
G 1 +sC3
G
1sC3 -----+G 4 G 1 +sC3
+ (G 1 + sC 3 )
G 1 + sC 3 sC 3
G 1 + sC 3
After canceling some terms and some mathematical manipulation of the matrix of (2-79), the resulting RMNA system becomes
1[G 1
3 0
(2-80)
The transfer function is then readily available from the first equation, which corresponds to KCL at the output node.
2.8. GENERAL COMPARISONS AND COMPLEXITY ANALYSIS This chapter presented five basic symbolic analysis methods, with some specific algorithms illustrated further due to their prominent roles in symbolic analysis software implementations. It is very difficult to compare and declare one method as the clear choice
61
References
for performing symbolic analysis. The presentation in this chapter was aimed at introducing the general concepts of the algorithms rather than specific implementations. Each method has its advantages and disadvantages and is highly dependent on the realization choices. The computational efficiency of many of these methods has been improved through coupling with other techniques, most noteworthy are the circuit approximation techniques [36]-[39], [7]. Having said all that, an attempt will be made to compare the methods and present a general complexity analysis of each. The tree enumeration methods, both directed and undirected, have found their way into many software implementations, especially in recent times. The circuit size limitation that is characteristic of these methods has been resolved lately by the use of approximation techniques. The time complexity of the algorithms here is due to the need for finding all spanning trees common to two graphs and a subset of 2-trees. This process in itself exhibits exponential complexity, especially the 2-tree search process; however, some techniques have been proposed to make that process more efficient [7]. It must be noted that the graphs for this method are much simpler compared to the signal flowgraph of the circuit. The signal flow graph methods are also very popular in software implementations, namely Mason's SFG. The circuit size limitations that these methods exhibit have also been addressed in recent times, mainly through the use of hierarchical methods. The mapping of the circuit to its SFG is not a trivial mapping. The size of a SFG compared to its circuit is more than twofold. The largest computational complexity is for the enumeration of the n order loops needed to generate the transfer function. This process is exponential in nature. The parameter extraction method is most suitable when very few symbols exist in the circuit. In its fully symbolic form, it is very inefficient and has not been used in this capacity. Because most of the computation time of the algorithm, especially for larger circuits, is in the numerical part, its time complexity is as efficient as the implementation of the numerical portion. The interpolation method can handle very few symbolic terms. An implementation reported a maximum of five symbolic variables allowed. Its time complexity is also dependent on the efficiency of the numerical computational techniques implemented. Several recent implementations of matrix-based methods have been reported. These methods are characterized by a direct formulation of the circuit equations without the intermediate steps of forming graphs. The methods are, in general, symbolic implementations of well-established numerical analysis algorithms with modifications and enhancements for adaptation to the symbolic domain. The circuit size limitation has been addressed using hierarchical methods as well as approximation techniques. The time complexity of the algorithms is easier to characterize because of their direct formulation, which enables the complexity analysis to easily take into account properties of real circuits. Based on these properties, some implementations have reported polynomial bounds on the process.
References [1] J. A. Starzyk and A. Konczykowska, "Flowgraph analysis of large electronic networks," IEEE Trans. Circuits Syst., vol. CAS-33, pp. 302-315, March 1986. [2] M. M. Hassoun and P. M. Lin, "A new network approach to symbolic simulation of large-scale networks," Proc. J989 IEEE Int. Symp. Circuits Syst. ,Portland, pp. 806-809, May 1989.
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Chapter 2
Symbolic Analysis Techniques: A Review
[3] M. Hassoun and K. McCarville, "Symbolic analysis of large-scale networks using a hierarchical signal flowgraph approach," Int. J. Analog Integrated Circuits and Signal Processing, vol. 3, no. 1, pp. 31-42, January 1993. [4] D. A. Calahan, "Linear network analysis and realization digital computer programs, and instruction manual," University ofIll. Bull., vol. 62, February 1965. [5] J. O. McClanahan and S. P. Chan, "Computer analysis of general linear networks using digraphs," Int. J. Electron., no. 22, pp. 153-191, 1972. [6] T. F. Gatts and N. R. Malik, "Topological analysis program for linear active networks (TAPLAN)," Proc. J3th Midwest Symp. Circuit Theory, 1970. [7] P. Wambacq, F. V. Fernandez, G. Gielen, and W. Sansen, "Approximation during expression generation in symbolic analysis of analog integrated circuits," Alta Frequenza, vol. 5, no. 6, pp. 48-55, November 1993. [8] Q. Yu and C. Sechen, "Efficient approximation of symbolic network function using matroid intersection algorithms," IEEE Int. Symp. Circuits Syst., pp. 2088-2091, Seattle, Wa, May 1995. [9] P. M. Lin, Symbolic Network Analysis. Amsterdam: Elsevier Science, 1991. [10] W. K. Chen, "Topological analysis for active networks," IEEE Trans. Circuit Theory, vol. CT-12, pp. 85-91, 1965. [11] L. O. Chua and P. M. Lin, Computer Aided Analysis of Electronic CircuitsAlgorithms and Computational Techniques. Englewood Cliffs, NJ: Prentice-Hall, 1975. [12] W. Mayeda and S. Seshu, Topological Formulasfor Network Functions, Engineering Experimentation Station, University of Illinois, Bulletin 446, Urbana, 1957. [13] S. J. Mason, "Feedback theory-further properties of signal flow graphs," Proc. IRE, vol. 44, pp. 920-926, July 1956. [14] L. P. McNamee and H. Potash, A user's and programmer's manual for NASAP. University of California at Los Angeles, Rep. 63-38, August 1968. [15] H. Okrent and L. P. McNamee, NASAP-70 User's and Programmer's Manual. University of California at Los Angeles, Tech. Rep. ENG-7044, 1970. [16] P. M. Lin and G. E. Alderson, SNAP-A computer programfor generating symbolic networkfunctions. School ofEE, Purdue University, West Lafayette, IN, Rep. TR-EE 70-16, August 1970. [17] F. V. Fernandez, A. Rodriguez-Vazquez, and J. L. Huertas, "An advanced symbolic analyzer for the automatic generation of analog circuit design equations," Proc. IEEE Int. Symp. Circuits Syst., Singapore, pp. 810-813, June 1991. [18] R. R. Mielke, "A new signal flowgraph formulation of symbolic network functions," IEEE Trans. Circuits Syst., vol. CAS-25, pp. 334-340, June 1978. [19] A. V. Aho et al., The Design and Analysis of Computer Algorithms. Reading, MA: Addison-Wesley, 1974. [20] C. L. Coates, "Flow graph solutions of linear algebraic equations," IRE Trans. Circuit Theory, vol. CT-6, pp. 170-187, 1959. [21] A. Konczykowska and M. Bon, "Automated design software for switched-capacitor ICs with symbolic simulator SCYMBAL," Proc. Design Automation Conf, Anaheim, CA, pp. 363-368, 1988. [22] G. E. Alderson and P. M. Lin, "Computer generation of symbolic network functions-A new theory and implementation," IEEE Trans. Circuit Theory, vol. CT-20, pp. 48-56, January 1973.
References
63
[23] K. Singhal and J. Vlach, "Symbolic analysis of analog and digital circuits," IEEE Trans. Circuits Syst., vol. CAS-24, pp. 598-609, November 1977. [24] P. Sannuti and N. N. Puri, "Symbolic network analysis-An algebraic formulation," IEEE Trans. Circuits Syst., vol. CAS-27, pp. 679-687, August 1980. [25] C. Ho, A. E. Ruehli, and Brennan, "The modified nodal approach to network analysis," IEEE Trans. Circuits Syst., vol. CAS-25, pp. 504-509, June 1975. [26] G. D. Hachtel et aI., "The sparse tableau approach to network and design," IEEE Trans. Circuit Theory, vol. CT-18, pp. 101-113, January 1971. [27] G. E. Alderson and P. M. Lin, "Integrating topological and numerical methods for semi-symbolic network analysis," Proc. MidwestSymp. CircuitTheory, Minneapolis, MN,1970. [28] K. Singhal and J. Vlach, "Generation of immittance functions in symbolic form for lumped distributed active networks," IEEE Trans. Circuits Syst., vol. CAS-21, pp. 57-67, January 1974. [29] J. Vlach and K. Singhal, Computer Methodsfor Circuit Analysis and Design. New York: Van Nostrand Reinhold, 1983. [30] M. M. Hassoun and P. M. Lin, "A hierarchical network approach to symbolic analysis of large-scale networks," IEEE Trans. Circuits Syst. I, vol. 42, no. 4, pp. 201-211, March 1995. [31] G. Gielen, H. Walscharts, and W. Sansen, "ISAAC: A symbolic simulator for analog integrated circuits," IEEE J. Solid-State Circuits, vol. SC-24, pp. 1587-1597, December 1989. [32] R. Sommer, D. Ammennann, and E. Hennig, "More efficient algorithms for symbolic network analysis: supernodes and reduced loop analysis," Int. J. Analog Integrated Circuits and Signal Processing, vol. 3, no. 1, pp. 73-83, January 1993. [33] G. Gielen and W. Sansen, Symbolic Analysis for Automated Design of Analog Integrated Circuits. Boston, MA: Kluwer Academic, 1991. [34] P. Wang, "On the expansion of sparse symbolic determinants," Proc. Int. Con! System Sciences, Honolulu, 1977. [35] B. Noble and J. Daniel, Applied Linear Algebra, 2nd Ed. Englewood Cliffs, NJ: Prentice-Hall, 1977. [36] S.-M. Chang, J. F. MacKay, and G. M. Wierzba, "Matrix reduction and numerical approximation during computation techniques for symbolic analog circuit analysis," Proc. IEEE Int. Symp. Circuits Syst., San Diego, CA, pp. 1153-1156, May 1992. [37] F. V. Fernandez, A. Rodriguez-Vazquez, J. D. Martin, and J. L. Huertas, "Approximating nested format symbolic expressions," Alta Frequenza, vol. 5, no. 6, pp. 326-335, November 1993. [38] S. Seda, M. Degrauwe, and W. Fichtner, "Lazy-expansion symbolic expression approximation in SYNAP," Proc. 1992 Int. Con! Computer-Aided Design, Santa Clara, CA, pp. 310-317, 1992. [39] P. Wambacq, G. Gielen, and W. Sansen, "A cancellation free algorithm for the symbolic simulation of large analog circuits," Proc. IEEE Int. Symp. Circuits Syst., San Diego, CA, pp. 1157-1160, May 1992.
3 Zaga M. Arnautovic Bell-Northern Research Ltd. Ottawa, Ontario, Canada
Symbolic Analysis of Sampled-Data Systems
Pen-Min Lin School ofElectrical Engineering Purdue University West Lafayette, Indiana
3.1. INTRODUCTION Extending some of the methods used to generate symbolic network functions to the sampled-data systems is a difficult task. The problem lies in determination of the transfer function for sampled-data systems. This task is sometimes very difficult to accomplish, because a transfer function for the ideal sampler does not exist. However, for the case in which every signal within the system is sampled, i.e., there is a sampler in each path of system, the continuous-time procedure can be applied. The transfer function can be written by inspection using Mason's gain formula [1]. However, no transfer function of the sampled-data system can be found in the case when the input is applied to a continuous-time element before being sampled. Thus, the only way left to express the output of such a sampled-data system is to write several algebraic equations and, with a somewhat complicated procedure, try to find the relationship between the input and output of the sampled-data system. In general, the equations contain both sampled and unsampled forms of the same variable. The problem is then to perform analytical sampling of one such variable, solve for the sampled variable, and finally search for the right equations in which to substitute.
3.1.1. Signal Flowgraphs and Topological Analysis One of the first attempts to apply the signal flowgraph (SPG) technique and topological analysis to obtain the expression for the output of sampled-data system was made by Kuo [2]. His method is a combination of algebraic manipulation of equations and
64
Sec. 3.1
Introduction
65
the use of Mason's topological gain formula. The method consists of constructing an "equivalent" SFG of the system, and a "sampled" SFG. The sampled SFG contains only sampled signals to which Mason's gain formula can be applied. It is obtained by careful algebraic manipulations. In the next step of Kuo' s method, the samplers are deleted and artificial signal sources at the corresponding output nodes of samplers are added. A composition of the sampled and equivalent SFG, known as the composite SFG, is then determined. The samplers in the equivalent SFG are deleted and their corresponding artificial inputs are connected to the sampled SFG. At this point, Mason's gain formula can be applied to obtain any system variable and its sampled form. The major problem with this method is that it includes nonrigorous mathematical operations in the stage of obtaining the sampled SFG. In order to get the sampled SFG, cascading of samplers is often performed. The samplers cannot be cascaded, because impulse response of an impulse sampler is not defined [3]. Obtaining a sampled SFG from the pulse transformation of a set of equations may be possible for simple, small systems. However, for the most complex systems, it is not systematic enough. After the composite SFG is obtained, the number of nodes is twice as many as in the equivalent SFG. That requires the application of some kind of reduction algorithm. Therefore, the method for choosing the variables, systematic writing, and solving the equations of sampled-data systems was proposed in Ref. [4]. Another method for determining the output of sampled-data systems was proposed by Lendaris and Jury [5]. Their approach involved obtaining a general expression for the gain of a multisampled-loop system. They introduced the artificial signal source in place of the sampler, and then expressed the transfer function of the system as a combination of the transfer functions from input to the sampler and the sampler to output, with the sampler left open. At the same time, the signal source was restricted to be equal to the sampled form of the signal entering the sampler. But, it turned out that every attempt to generalize the gain formula for a multisampled-Ioop system with the number of loops greater than two gave a result that was too lengthy and complicated to apply.
3.1.2. Matrix Approach Another approach to finding the output of a sampled-data system is to use topological matrices. Some of those attempts are described in papers by Ash, Kim, Krane, and Vago. Both papers, [6] and [7], present methods based on: • the use of a signal flowgraph to obtain topological matrices, and • the use of the matrix algebra to calculate the output of the system. In his paper, Salehi [8] presents another algorithm based on the systematic node-by-node reduction of a special SFG. By his approach, the samplers are treated like subsystems with operator transmittances. The author has also introduced special types of nodes: • gray if they represent sampler inputs, • black if they represent sampler outputs, and • white otherwise.
66
Chapter 3
Symbolic Analysis of Sampled-Data Systems
The method is a generalization of Munro's algorithm for node reduction [9]. However, success of the reduction process depends on the node ordering. In general, matrices used to calculate input-output relationships in these methods are often very sparse. Therefore, to reduce computation time, it is necessary to use methods that exploit sparsity of a matrix. These methods are referred to as the sparse matrix methods. But, the use of the sparse matrix methods requires considerable software efforts to develop a viable program. The additional software routines include a special storage procedure, finding optimal node ordering, etc.
3.2. SEDLAR-BEKEY METHOD The signal flowgraph technique is a powerful tool in the analysis of the linear continuous-time systems. The algebra of signal flowgraphs is well developed, as well as systematic techniques for reduction that lead to the simplest possible graph. By applying Mason's gain formula, it is possible to obtain input-output relationships by inspection. As several authors have shown, the signal flowgraph technique can be applied in analyzing sampled-data systems. However, it is impossible to apply Mason's formula directly, except for the special case of systems when all signals are sampled. The difficulty lies in the presence of samplers that cannot be described by a transfer function. M. Sedlar and G. A. Bekey [10] have extended the signal flowgraph approach to the analysis of sampled-data systems by introducing a new symbol that represents the sampler. They have generalized signal flowgraph techniques, so that these techniques can be applied both to sampled-data systems and to continuous systems. The analysis of the linear continuous-time systems becomes a special case of the general signal flowgraph. By definition, a signal flowgraph is a network of nodes connected by oriented branches. The nodes describe system variables, while branches describe their interactions, and, in the case of linear continuous-time systems with constant coefficients, they are associated with operations of summations and multiplication in the frequency domain. In the case of sampled-data systems, the variables can be continuous or discrete. In addition to summing and multiplying, the operation of sampling exists and it becomes necessary to introduce a new symbol that will be associated with this operation. In order to distinguish between the two types of variables present in sampled-data systems, Sedlar and Bekey have proposed white node and black node symbols: • White node (indicated by an empty circle) denotes a continuous variable • Black node (represented by a filled circle) denotes a sampled variable and operation of sampling The black node is defined as follows: • It represents a discrete variable. • The value of the variable is the sampled form of the sum of all variables entering the node.
Sec. 3.2
67
Sedlar-Bekey Method
The authors have also, where necessary, extended some of the topological definitions from the theory of signal flowgraphs in order to take into account the black nodes. For example, the set of all nodes N consists of a set of white nodes Wand a set of black nodes B, such that
WuB=N
(3-1)
WnB=O
(3-2)
where the set N is divided into subsets of input and output variables: Nin = {Xj I Xj represents an input variable}, and Nout = {Xj I Xj represents an output variable} A path is a sequence of branches {Q, b, C, ... } such that the initial node of each branch is a terminal node of the preceding branch, where the nodes belong to the set N. A finite path is a path of k < 00 branches. A loop is the finite path in which initial and terminal nodes coincide. A segment a[xm,xn ] is defined as a path between x m E N in U Band x m E N out u B such that all other nodes of segment a belong to the set Wand no node is met more than once. A Type 1 path or loop is the path or loop containing only white nodes. A Type 2 path or loop is the path or loop containing at least one black node. A Type 1 path is elementary if it does not meet the same node more than once. A Type 1 loop is elementary if, except for initial and terminal nodes, all other nodes are distinct. A Type 2 path or loop is elementary if it contains distinct segments such that no black node is met more than once. The white node can be met more than once, but it must belong to the different segments. Topological connections between paths and loops are defined as follows: • A Type 1 loop is connected with a path or another Type 1 loop if they have a node in common. • A Type 2 loop is connected with another Type 2 loop or path if they have a black node in common. As an illustration of these definitions, the system whose block diagram is given in Fig. 3.1 is considered. The system has two samplers, 5 I and 52' in two of three feedback loops. The input to the system is normalized to unity by introducing a branch with the transmittance H(s), which represents the Laplace transform of the input, because in linear sampled-data systems, in general, it is not possible to separate the input variable in the expression for the output. The pulse transform of the output of a sampled-data system is not always a product of the transfer function of the system and the pulse transform of the input. The operation symbolized by the sampler cannot be represented by the transfer function. By normalizing the input to the system to unity, the overall transfer function is referred to as a unit input, so that the transfer function and output become equal. The H1(s) and H 2(s) are Laplace transforms of continuous-time transfer functions of subsystems of the system whose block diagram is given. For simplicity, H(s), H1(s), and H 2(s) are denoted by H, HI' and H2 . Hd* denotes z-transfonn, HJz), of the discrete-time transfer function of the subsystem.
68
Chapter 3
Symbolic Analysis of Sampled-Data Systems
~H
Figure 3.1 Block diagram of the system.
The signal flowgraph of the system shown in Fig. 3.1 is given in Fig. 3.2. Both samplers in the block diagram of the system are replaced with black nodes in the signal flowgraph. All the other nodes in the block diagram are white nodes. Applying the given definitions of paths and loops, the following elementary paths exist: • Type 1 ( I)
III
(3-3)
= [1,2,3,4,5]
-1
H
3
4
5 y
)-------~
Figure 3.2 Signal flowgraph of the system.
Sec. 3.2
69
Sedlar-Bekey Method
• Type 2 (2)
III
(2)
= [1, 2, 3, 6, 2, 3, 4, 5]
~2
= [1,2,3,4,7,2,3,4,5]
(2) ~3
= [1,2,3,6,2,3,4,7,2,3,4,5]
(2) ~4
= [1,2,3,4,7,2,3,6,2,3,4,5]
(3-4)
The following elementary loops exist: • Type 1 ( I) \)1
= [2,3,4,2]
(3-5)
• Type 2 (2)
\)1
= [6,2,3,6]
(2) \)2
= [7, 2,3,4,7]
(2)
\)3
(3-6)
= [6,2,3,4,7,2,3,6]
Sedlar and Bekey have defined the path and loop transmittance as: a path transmittance, P(J,l), is the product of the transmittances of the branches that appear in the path. The transmittances are taken in the order in which the branches appear, and the presence of a black node denotes that the sampled form of the preceding product should be taken. The operation of sampling is denoted by a * sign. a loop transmittance, L(u), is defined in the same manner as path transmittance. However, if there is any black node in the loop, then a black node should be taken as the initial node. As an illustration of definitions of path and loop transmittances, we consider Fig. 3.2 again. The following are the path transmittances: • Type 1 (3-7)
70
Chapter 3
Symbolic Analysis of Sampled-Data Systems
• Type 2
(3-8)
(HH I ) *Hd* (H IH2 ) *H IH2 (HH IH 2 ) * (HI) *Hd*H IH2 The following are the loop transmittances: • Type 1 (3-9)
• Type 2
L I( 2) -- -H 1*H d*
L~2) = -(H tH2) *
(3-10)
L~2) = H/ (H 1H2)*H 1* The first determinant of the graph is defined as ~ (1) = 1- ~ L.(l) + ~ L.(l) L~l)
£..J
~
£..J
I
I
(1).
_
}
~ L.(I) L.(I) Lk(l) + ...
£..J
I
(3-11)
J
.
~
(1)
(1)
where £..JL; IS the sum of the loop transmittances of all Type 1 loops, and £..JL; Lj is the sum of the products of loop transmittances of all nonconnected Type 1 loops taken two at a time. The next terms represent the sum of the products of the all nonconnected Type 1 loops taken three at a time, four at a time, and so forth. The second determinant of the graph is established as ~ (2) = 1 _ ~ L~2)
£..J
I
+ ~ L~2) L~2)
£..J
I
}
_
~ L~2) L~2) L
£..J
I
}
k(2)
+ ...
(3-12)
with the same interpretation for the terms as in the definition for the first determinant, but this time referring to the Type 2 loops. To define the input-output relation between any two nodes in the signal flowgraph, Sedlar and Bekey have shown that it can be written in the form [10]
~.( I) I
~
(2)
£..JP;~; ;
Y = 6 (I) ® -~-(-2)-
(3-13)
where P;is the path transmittance of Type 1 or Type 2 path Jl;, connecting input and output
Sec. 3.2
71
Sedlar"Bekey Method
nodes, ~ (2) is the second determinant of the graph, and ~/2) is the subdetenninant of the path Jl j
•
The subdetenninant ~i(2) is obtained by omitting from the determinant all loop transmittances that are connected with path Jl j • The symbol ® represents the operation of multiplication of each segment
.
. .
transmittance appeanng In
(~pA(2»)/ (2)b ~ itij ~ Y ~i(1)/ ~ (I) . I
If any of the transmittances appear in the sampled form, the multiplication must first be performed on the corresponding continuous variables and the result is then sampled. The expression ~ (J) is the first determinant of the graph and ~i( I) is the subdetenninant of related segment 0' i ' which is part of the path J.l i • The subdetenninant ~i( I) is obtained from ~ ( I) by omitting all terms containing loop transmittances of the loops u ( I) connected with segment
(jj .
In the case of all white nodes, Eq. (3-13) reduces to the well-known Mason's formula, because ~ (2) =
(3-14)
~~2) = I
In the case of all black nodes, (3-13) reduces, again, to Mason's formula, because ~ (I)
= (3-15)
~~I) = I
The first determinant for the signal flowgraph given in Fig. 3.2 is (3-16) The second determinant is:
~(2) = I +HJ*H/+ (H 1H2 ) * - H d* (H 1H2 ) *H 1* + HI *H d* (H 1H2 ) * = 1 +H1*Hd* + (H 1H2)*
The substitution of these expressions into
(LPi~i(2»)/~ I
(2)
results in
(3-17)
72
Chapter 3
Symbolic Analysis of Sampled-Data Systems
5
~ r.s:" ~ II
(HH
;=1 ~ (2)
1H 2
)
~ (2)
~ (2)
(HH 1) *H d*H 1H2 [I + (H 1H2 ) *] ~ (2)
(HH IH 2)*H IH 2 [ 1 +HI*Hd*]
(3-18)
~ (2)
+ +
(HH I) *H d* (H IH 2 ) *H IH 2
~ (2)
(HH 1H2 ) *HI *H d*H I H2
~ (2)
= HH 1H2 -
(HH I) *Hd*H 1H2 + (HH 1H2 ) *H}H 2 (2)
~
We should note that several terms in (3-18) have been canceled in the final expression for the output. In the next equation, we determine the respective ~i( I) for every segrnent o i appearing in the output. All possible different segments and their corresponding ~/ I)s are (I)
=I
al
= HH 1H2
L\~l)
(I) 0"2
=HH 1
~~I) = I
= H 1H2
~j I) = I
= HI
~~I) = I
= Hd
~5
( I)
a3
( I)
0"4
( })
0"5
( })
(3-19)
= 1 + H}H 2
Thus, the final expression for the output is HH IH2 y=--I +H 1H2
(HH1L)*H d* (H 1H2L) + (HH 1H2L)*H 1H2L
1+ (H}L) *H d* + (H}H 2L) *
(3-20)
where (3-21)
Sec. 3.3
Arnautovic-Lin Approach for Finding Input-Output Relationships of Sampled-Data Systems
73
A computer program capable of generating input-output relationships of mixed continuous and sampled-data systems in the symbolic form based on Sedlar-Bekey method has been developed at Purdue University, West Lafayette, IN (U.S.A.), and is described in Refs. [11] and [12].
3.3. ARNAUTOVIC-LIN APPROACH FOR FINDING INPUT-OUTPUT RELATIONSHIPS OF SAMPLED-DATA SYSTEMS We can see that applying Sedlar and Bekey's method for finding input-output relationships of sampled-data systems has generated several redundant terms: Moreover, in the case of systems with large numbers of nodes, the identification of all paths and loops is a nontrivial task. Because our branch transmittances are given in the form of symbolic variables, and computer handling of symbols is often intractable, avoiding finding the redundant terms is a very important issue. In an effort to avoid redundant terms, the following method is proposed [1 1]. Consider the signal flowgraph in Fig. 3.2 again. Denote the signal flowgraph in Fig. 3.2 as G, and from this signal flowgraph create two new signal flowgraphs using the procedure described next. First, form another signal flowgraph denoted as G I by splitting all black nodes and replacing them by two new nodes. One node is a source node, which has all original outgoing branches. The other node is a new sink node, which has all original incoming branches. The signal flowgraph obtained by splitting all black nodes is given in Fig. 3.3. Because signal flowgraph G} contains only continuous variables, Mason's rule can be applied, and transmittance between every input node and every output node can be found. The continuous determinant for signal flowgraph G} is denoted as ~
GI
(3-22)
= 1 +H 1H2
The transmittances between every source node and sink node In the signal flowgraph G 1 are determined as follows: -1
H
1
------t~ } - - - - - - . < > - - - - - - . . < J------~5
6
-H; 7
1
7
-1 6 Figure 3.3 Signal flowgraph G1 .
74
Chapter 3
HH IH2
GI
T I5 =
GI HH I T I6 = GT
fi
GI HI T76 =-(;1
Ii
HH 1H2
GI
GI H IH2 T75 =-Gl
Ii GI
GI Hd*H I T66 = --G-I-
Ii
T l7 =
Hd*HIH2
GI
T65 =
fi GI
Symbolic Analysis of Sampled-Data Systems
Ii GI
Ii
Hd*H 1H2
GI
T67 =
(3-23)
GI H 1H2 T77 =-Gl
Ii GI
Ii
Now, signal flowgraph G 2 is formed. Signal flowgraph G 2 contains original input and output nodes and all black nodes. The branch transmittances between nodes will be the corresponding branch transmittances from signal flowgraph G I . Signal flowgraph G 2 is given in Fig. 3.4. Because signal flowgraph G 2 contains only black nodes and original source and sink nodes, Mason's rule can be applied again. In order to find the transmittance between nodes 1 and 5, all possible paths and loops will be identified first. The following are all possible paths in signal flowgraph G2 :
pG2 _ I
pG2 2
-
Gl
T I5 =
HH 1H2 Ii
GI
= (TGI)*(TGI) = _(HHI]*H 16
G2 = (
P3
GI)* GI =
T I7
Ii G I
65
T75
Ii
GI
1
(GI)*( T TGI)* TGl __
I7
76
*. H 1H2 Ii G I
_(HH IH2]* . H IH2
65
rH/( Ii
p~2 = (T~61 )*( T~71 )*T~51 = (::11 P5G2 =
d
(3-24)
Gl
:~2 r:~2
(HHIH2]*(!2]*Hd*HIH2 Ii G I
fiG I
Ii G I
5
Figure 3.4 Signal flowgraph G2 .
Sec. 3.3
Arnautovic-Lin Approach for Finding Input-Output Relationships of Sampled-Data Systems
75
(3-25)
The determinant for signal flowgraph G2 is
~
G2
.
= 1 +H/
+
H1
1 2 ( ~GI ]* + (H~GIH I
* (H H]* H]* H d'---cT (m 1
~
]* -H/ (H~GIH]*( ~GIH ]* I
I
1 2'
1
(3-26)
1 2
~
(3-27)
Thus, transmittance between the original source and sink nodes obtained by applying Mason's rule is
The final result is
(3-29)
76
Chapter 3
Symbolic Analysis of Sampled-Data Systems
We can see that the transmittance between the original source node 1 and sink node 5 (given in (3-29) and obtained by the method of splitting black nodes and the transmittance found by applying Sedlar and Bekey's method and given in (3-20» are the same.
3.3.1. The Arnautovic-Lin Approach Applied on aGeneral Case of Sampled-Data System Let us, now, show that the method of splitting of black nodes and creating two signal tlowgraphs in order to find the transmittance between an input and output node can be applied in a case of a general sampled-data system. Any sampled-data system can be represented with a system of linear equations [6], which can be written in the form: Ax = Bx* +h
(3-30)
where A and B are square matrices whose order is equal to the number of variables, x is a column vector of variables, and x* is obtained from x by replacing each variable by its sampled form. Due to input normalization, h is a column vector whose elements are either 1 or o. Premultiplying both sides of (3-30) with A -I it follows that x = A-1Bx* +A-1h
(3-31)
It has been shown [6] that matrix A characterizes a continuous part of a system and that elements of the matrix A
-I
are (3-32)
where 1); is the transfer function from the node j to the node i of the signal flowgraph describing original sampled-data system, but with the samplers open. If we take the signal flowgraph of a sampled-data system and represent each sampler or discrete variable with a black node, then creating signal flowgraph G 1 by splitting a black node into two nodes, the one having only incoming branches, and the other having only outgoing branches, is equivalent to open-circuiting all samplers in the system. Mason's rule can be applied and all transmittances can be found. Every transfer function from node j to node i in that signal flowgraph can then be written in the form
~p ..~?1 Too = £..J Jt Jt Jt
(3-33)
~GI
where Pj; denotes any possible path transmittance from node j to node i, ~ G I denotes the determinant of the signal flowgraph G I or determinant defined on only the continuous part of the sampled-data system, and ~j~ I is the subdetenninant of the related path Pj;' Further, it has been shown [6] that components of the vector A
-I
hare
Sec.3.3
Arnautovic-Lin Approach for Finding Input-Output Relationships of Sampled-Data Systems
la J -I h
=
r;
77
(3-34)
or they are equal to the transfer function from the normalized input to each nodej. It follows that elements of A - I h are different from zero if and only if there are continuous paths from the input to the corresponding node j. In that case, the transmittance between input node, denoted as I, and any node j is given as
T
-
Ij -
L
GI
Pl'~l' J
~
GI
J
(3-35)
where P Ij is any possible path from the input node to nodej. If we go back to (3-31) and apply the operation of starring, it will follow that x*
= (A -1)* B x* + (-1)* A h
(3-36)
Because Eq. (3-36) involves only sampled variables, it can be solved in terms ofx*:
[I - (A-I B)*J x* = (A -I h)* x* = [1-(A-1B )*rl(A-1h)*
(3-37)
Because all the variables in Eq. (3-37) are in the starred form, then the equation can be represented by a sampled graph and solved by Mason's rule. of vector x* are then given as The components x.* I (3-38)
"t* i
G2
G2
G2
where P; ,d; ,and d are defined on a sampled graph. Substituting (3-38) into (3-31), it follows that (3-39) Eq. (3-39) has been derived by Ash, Kim, and Krane [6], who also provided its topological interpretation. They have shown that matrix B characterizes the presence of samplers or black nodes in the signal flowgraph of the sampled-data system. The elements
la-I b )ij of the matrix A
(a 1) b -
_
ij -
TJI..
{0
j
j
-I B
for an arbitrary i are
= discrete variable = continuous variable
(3-40)
At the same time, applying the operation of starring on Eqs. (3-34) and (3-40), it follows that
78
Chapter 3 (
Symbolic Analysis of Sampled-Data Systems
J
a -I h j * = T 1j *
(3-41 )
and ( a
-1 )
b
*
{T. *
=
ij
J
j = black node
i
o
= white node
j
(3-42)
The product A -I Bx* is a vector with components that according to the properties of the matrix A -I B , can be written in the form
P tJ. G2
- - L T .x * -- L - - T .
x.I -
n
nt n
n n G2
(3-43)
nt
tJ.
n
where n represents any node of the sampled graph corresponding to discrete variables of the original system or black nodes of the original signal flowgraph and i represents any component of the vector. According Eqs. (3-31), (3-34), and (3-43), any component xi of the vector x, with X o representing the output node as well, can be written in the form p G2 tJ. G2
x =~ () £..J n
Any path
n
T
n
tJ.
G2
no
+T
(3-44)
10
p:2 from this equation is of the form pG2 n
= T IJ.*T.jk:*Tkl *... Tpn *
(3-45)
G'J
and the product Pn ... Tno can be written in the form pG2 n Tno
= T Ij'*Tjk'*Tkl'* ... Tpn'*Tno
_(TGI)*( T GI)* (T GI)* TGI
-
jk
lj
...
pn
(3-46)
no
The product corresponds to the transmittance of the path that is going through distinct black nodes and connecting input and output nodes. Similarly, any loop of the sampled graph will meet the nodes representing only discrete variables in the original system or the black nodes in the original signal flow graph. The loop transmittance will have the form G2
Li
--
T ij *Tjk *Tkl'" * Tpq*Tqi *
(3-47)
The determinant of the sampled signal flowgraph is defined as d G2 = 1- ~ L?2 + ~ L?2 L?2 _ ~ L?2 L?2 LkG2 + ...
£..J
I
£..J
I
J
£..J
I
J
(3-48)
where products of two or more loops exist only if these loops are nontouching, which in turn corresponds to loops that do not have a black node in common.
Sec. 3.4
Solved Examples of Finding Input-Output Relationship
79
Let us now give a topological explanation to the result given in Eq. (3-44). Assuming that input was normalized, finding an expression for any node xi is equivalent to finding the transfer function from the input node (xl) to that particular node. Obviously, any node xi of the vector x, so also output node X o and at the same time transfer function from input to output node, can be found by finding all possible paths and their transmittances, from input through each black node and from that black node to output. In addition, the direct path and its transmittance, from the input to the output, has to be found. This means that when forming signal flowgraph G 2 by leaving only black nodes and input and output nodes of the original signal flowgraph, we are able to find direct path transmittance and all path transmittances from input, through each black node to output, by applying only Mason's rule.
3.4. SOLVED EXAMPLES OF FINDING INPUT-OUTPUT RELATIONSHIP To illustrate the method just described of splitting black nodes and creating two signal flowgraphs in order to find the transfer function between any two nodes of the sampled-data system, we present two solved examples of finding the input-output relationship in this section. More solved examples may be found in [11].
EXAMPLE 3.1 For the sampled-data system whose block diagram is shown in Fig. 3.5, find the transfer function between the given input and output. The signal flowgraph of the system given in Fig. 3.5 is shown in Fig. 3.6. The signal flowgraph obtained after splitting black nodes 3, 4, and 8 is shown in Fig. 3.7. Applying Mason's rule, we can find all possible paths and their path transmittances between input node 1 and output node 7. Also, we have to find all paths between input node 1 to nodes 3, 4, and 8 and from nodes 3, 4, and 8 to output. All possible paths between nodes 3,4, and 8 themselves have to be found as well. Analyzing the signal flowgraph given in Fig. 3.7, we can conclude that there is no path between input node 1 and output node 7. Path transmittances from input node 1 to nodes 3, 4, and 8 can be found applying Mason's rule. There is only one such path connecting node 1 to node 3 and there are no paths between node 1 to nodes 4 and 8. The path transmittance from node I to node 3 is given as
Figure 3.5 Block diagram of sampled-data system in example 3.1.
80
Chapter 3
Symbolic Analysis of Sampled-Data Systems
Figure 3.6 Signal flowgraph of the system given in Fig. 3.5.
2 ,.---~ ~~
3 3' HI .-t
0
4
~O
4' t---
5
6
~ }---~~ ~----~
7
Figure 3.7 Signal flowgraph with only white nodes.
(3-49)
Path transmittances from nodes 3, 4, and 8 to output node 7 are T4 ' 7 = H 2
T S ' 7 = -H4H2
(3-50)
Path transmittances between nodes 3, 4, and 8 are given as T 3 ' 4 = HI T4 ' 3 = -H2H3 T4,s = H 2
T S'3
(3-51 )
= H4H2H3
Ts,s = -H 4H2
As the next step, a signal flowgraph with only black nodes and input and output nodes should be formed, and this flowgraph is given in Fig. 3.8. All possible path transmittances between nodes 1 and 7 are PI P2
= (T I3)*(T3' 4 ) * T 4 ' 7 = H*(H I)*H 2 = (T I3) * (T3' 4 ) * (T4 ,s) *Ts' 7 = -H* (HI) * (H 2 ) *H 4H2
(3-52)
Sec. 3.4
Solved Examples of Finding Input-Output Relationship
81
Figure 3.8 Signal flowgraph with only black nodes.
There are three possible loops, and they are L I = (Ts,s)*
= -(H4H2 ) *
L 2 = (T3' 4) * (T4 ' 3) * = -(H I)*(H 2H3)* L 3 = (T3' 4 ) * (T4 ,s) * (T S' 3) * = (HI)
(3-53)
* (H 2 ) * (H4H2H3 ) *
Loops L] and L 2 do not touch each other, i.e., they do not have a black node in common, so the determinant of the graph can be given as
d
= 1 + (H4H2 ) * + (HI) * (H2H3 ) * -(HI)
* (H 2 ) * (H4H2H3 ) *
(3-54)
+ (H 4H2) * (H I ) * (H 2H3) * Finally, the transmittance between nodes 1 and 7 can be found as _ H*(H I)*H 2[1 T 17 -
+ (H 4H2)*] -H*(H I)*(H 2)*H4H2 d
(3-55)
EXAMPLE 3.2 For the sampled-data system whose block diagram is given in Fig. 3.9, find the transfer function between the given input and output. The signal flowgraph of the system given in Fig. 3.9 is shown in Fig. 3.10. The signal flowgraph obtained after splitting black nodes 3, 9, and lOis shown in Fig. 3.11. Applying Mason's rule, we can find all possible paths and their path transmittances between input node 1 to output node 8. Also, we have to find all paths between input node 1 to nodes 3, 9, and 10 and from nodes 3, 9, and 10 to output node 8, as well as all possible paths between nodes 3, 9, and 10 themselves. Analyzing the signal flowgraph shown in Fig. 3.11, we can conclude that there is no path between input node 1 and output node 8. Path transmittances from input node 1 to nodes 3, 9, and 10 can be found by applying Mason's rule, and there exists only one path from node 1 to node 3. Its transmittance is given as (3-56)
82
Chapter 3
Symbolic Analysis of Sampled-Data Systems
Figure 3.9 Block diagram of sampled-data system in example 3.2.
-1 Figure 3.10 Signal flowgraph of the system given in Fig. 3.9.
-1 Figure 3.11 Signal flowgraph with only white nodes.
Path transmittances from nodes 3, 9, and 10 to output node 8 are
T3' 8 = H IH2H3 T9' 8
= -Hd*H IH2H3
T I O' 8 = -H4H3 Path transmittances between nodes 3, 9 and 10 are given as:
(3-57)
Sec. 3.4
83
Solved Examples of Finding Input-Output Relationship
= HI T3' IO = H 1H2H3 T 3'3 = -H 1H2H3 T3' 9
T9' 3 = Hd*H 1H2H3 T 9'IO
= -Hd*H 1H2H3
T 9'9 = -Hd*H 1
As the next step, a signal flowgraph with only black nodes and input and output nodes should be formed, and it is shown in Fig. 3.12. All possible path transmittances between nodes 1 and 8 are PI = (T I3)*T3'8 = H*H 1H2H3
P2 = (T 13) * (T3' l o) *T 10'8 = -H* (H 1H2H3) *H4H 3 P3
= (TI3)*(T3'9)*(T9'IO)*TIO'8 = H* (HI) *Hd* (H 1H 2H 3) *H4H3
(3-59)
P4 = (T I3)* (T3'9)*T9'8 = -H* (HI)*Hd*HIH2H3 There are six possible loops, and they are
L1
= (T3'3)* = -(H 1H2H3)*
L2 = (T9'9)* = -Hd*H 1* L 3 = (T10'IO)* = -(H4H 3) *
L4
(3-60)
= (T3'9) * (T9'3) * = Hl*Hd*(HIH2H3)*
Ls = (T 3'9) * (T9'IO)*(T10'3)* = -HI*Hd*(HIH2H3)*(H4H3)* L 6 = (T 3'IO) * (T 10'3) * = (H 1H2H3) * (H 4H3) *
The determinant of the graph is given as
T9'9 T9'8 Figure 3.12 Signal flowgraph with only black nodes.
84
Chapter 3
Symbolic Analysis of Sampled-Data Systems
The transmittance between nodes I and 8 can be found as (3-62)
3.5. CONCLUSIONS Several authors have studied the ways to derive the transfer function of sampled-data systems, and different methods for finding the input-output relationship in symbolic form have been proposed. The advantages of expressing the input-output relationship in the symbolic form include better insight into the system, improved error control compared to numerical analysis, and easier sensitivity analysis. The method of describing samplers as black nodes and then splitting them in order to apply Mason's rule to the two obtained signal flowgraphs belongs to a group of topological methods, and it is based on the signal tlowgraph technique. Following are several of the method's advantages: • The procedure is easy to apply. In the case of more complex sampled-data systems, to find all paths and loops by applying Sedlar and Bekey's method is not an easy task. The complete computer program written as implementation of their method and described in [11] substantiates this assertion. The method described in this chapter gives us a more methodical way of achieving that goal. • The method enables us to use existing programs for finding the transfer function of continuous systems in two steps: Step 1 finds transmittances in the signal flowgraph G I (continuous graph) where all samplers are left open and all nodes represent the continuous variables. Step 2 finds final the expression for the output of the sampled-data system in signal flowgraph G2 (sampled graph) where all nodes, except input and output, represent sampled variables. • The method has the potential for avoiding redundant terms if the existing programs can be used for dividing a complex signal flowgraph of a sampled-data system into several unconnected signal flowgraphs. Application of this method can be in circuit design, in particular, the design of sampled-data systems (combinations of continuous and discrete subsystems).
References [1] S. J. Mason, "Feedback theory-Some properties of signal flow graphs," Proc. IRE, vol. 44, pp. 1144-1156, September 1953. [2] B. C. Kuo, Analysis and Synthesis of Sanzpled-Data Control Systems. Englewood Cliffs, NJ: Prentice-Hall, 1963. [3] R. K. Cavin, D. L. Chenowith, and C. L. Phillips, "The z transform of an impulse function," IEEE Trans. Autonzat. Contr., p. 113, 1967.
References
85
[4] G. Cook, "A systematic procedure for writing and solving equations of sampled-data system," Int. J. Contr., vol. 13, no. 3, pp. 491-496, 1971. [5] G. G. Lendaris and E. I. Jury, "Input-output relationships for muItiIoop sampled systems," Trans. Amer. Inst. ElectricalEngineers (Appl. Ind.), pp. 375-385, January 1960. [6] R. Ash, W. H. Kim; and G. M. Krane, "A general flow graph technique for the solution of multiloop sampled systems," Trans. ASME-J. Basic Engineering, pp. 360-365, June 1960. [7] I. Vago, "The calculation of transfer matrices of linear systems with continuous and sampled-data signals by signal flow graphs," Circuit Theory Appl., vol. 11, pp. 355-362, 1983. [8] S. V. Salehi, "Signal flow graph reduction of sampled-data systems," Int. J. Contr., vol. 34, no. 1, pp. 71-94, 1981. [9] N. Munro, "Composite system studies using the connection matrix," Int. J. Contr., vol. 26,no.6,pp. 831-839,1977. [10] M. Sedlar and G. A. Bekey, "Signal flow graphs of sampled-data systems: a new formulation," IEEE Trans. Automat. Contr., vol. AC-12, pp. 154-161, April 1967. [11] Z. Arnautovic, Automatic Generation of Transfer Functions of Sampled-Data Systems in Symbolic Form. Purdue University, School of Electrical Engineering, West Lafayette, IN, M.S. thesis, December 1989. [12] Z. Arnautovic and P. M. Lin, "Symbolic analysis of mixed continuous and sampled-data systems," Proc. IEEE Int. Symp. Circuits Syst., Singapore, pp. 798-801,1991.
4 Georges Gielen *
Departement Elektrotechniek, ESAT-MICAS Katholieke Universiteit Leuven Heverlee, Belgium
Symbolic Analysis of Switched Analog Circuits
4.1. INTRODUCTION An important class of analog integrated circuits frequently used for signal-processing operations in industrial practice today are switched-capacitor (SC) circuits [1]. They are used not only to implement filters, decimators, and interpolators, but also to implement the integrators in L\-L converters. These circuits operate by alternately charging and discharging capacitors at a high clock frequency, which emulates the behavior of equivalent resistors when looking at the voltage-current behavior at lower frequencies (Fig. 4.1). In addition, capacitors are easy to fabricate in a MOS technology. In this way, the switched-capacitor equivalent of active RC filters can easily be generated on chip, while avoiding the problem of the large manufacturing tolerances in VLSI technology (20% or more) on the values of integrated Rs and Cs, and therefore also on the values of the resulting RC time constants. Indeed, in SC circuits the time constants are determined by the ratio of two capacitors (a switched capacitor and an integrating capacitor). These ratios can be fabricated with a very high accuracy (1% or even 0.1 %), especially when the layouts of the capacitors are generated with careful consideration to improving the matching. This means in practice that the capacitors are laid out in capacitor banks of equally sized unit capacitors. In addition, SC circuits were thoroughly studied in the 1980s. Their theoretical foundations are therefore well known, and several CAD tools for simulating and synthesizing SC circuits have been developed as well. The limitation of SC circuits is that their operating frequency range is restricted, because the capacitors have to
* Research associate of the Belgian National Fund of Scientific Research. 86
Sec. 4.1
87
Introduction
Yin
Vout
Figure 4.1 Principle schematic of a switched-capacitor integrator.
be switched at frequencies higher than the maximum signal frequency, and because all op-amps have to settle within a time frame of the order of a clock cycle. This means that SC circuits cannot be used for really high frequency applications. Second, SC circuits are clocked, in several cases by more than two nonoverlapping clocks. All these clock signals also have to be generated and distributed on chip, or derived from one master clock. In recent years, there has also been a growing interest in another class of switched analog circuits, called switched-current (SI) circuits [2]. The basic principle of these circuits is that they sample the driving voltage generated by an input current on the gate of a transistor in diode configuration, after which this voltage is switched such that it drives the output current into the next stage (Fig. 4.2). In this way, filters can be realized in a kind of open-loop configuration. Drawbacks of this technique are the lower dynamic range and higher distortion levels, although this has been improved in recent years with the use of better SI basic current cells. This chapter describes techniques for the symbolic analysis of sampled-data analog circuits, including both SC and SI analog circuits. Historically, most effort has been spent on programs for the analysis of SC circuits, but these techniques should be relatively easily expandable to SI currents as well. Due to the switching performed in these circuits, the
Ii
ut
Figure 4.2 Principle schematic of a simple switched-current memory cell.
88
Chapter 4
Symbolic Analysis of Switched Analog Circuits
circuits are periodically time-varying and therefore they required the development of special symbolic analysis techniques, although the basic symbolic methods described in chapter 2 in this book are often used as internal routines in these methods. The basic differences are mainly in the modeling of the circuit and the setup of the formulation, be it as a matrix of equations or as a graph. From the user point of view, the most important differences are that the resulting expressions are generated in the z-domain and that multiple input-output transfer functions are possible depending on the clock phases at which the input and output signals are considered (as requested by the user). For example, for two-phase circuits, the following transfer functions can be considered:
(4-1)
But combinations of these H I I (z)
transfer functions are important as well,
such
as
+ H I 2 (z) or H 21 (z) + H 22 (z) [1]. The techniques described in this chapter are
dedicated to SC circuits. The general symbolic analysis of sampled-data circuits has been described in chapter 3 in this book. The application of these symbolic analysis techniques to the synthesis of SC filters will be described in chapter 10. Section 4.2 will first describe the modeling used for SC circuits and will then give a classification of the different techniques used for the symbolic analysis of these circuits. Section 4.3 will then provide a more detailed overview of matrix-based techniques. Circuit transformation methods are described in section 4.4. Section 4.5 will focus on graph-based techniques, while section 4.6 will highlight parameter extraction methods. Examples are provided throughout these sections. Conclusions are then drawn in section 4.7.
4.2. CLASSIFICATION OF TECHNIQUES FOR THE SYMBOLIC ANALYSIS OF SC CIRCUITS Because switched-current circuits have been emerging only recently, most work on symbolic analysis of sampled-data analog circuits has been carried out for switched-capacitor circuits. This section will give a classification of the existing techniques for the symbolic analysis of SC circuits, consisting of linear, time-invariant capacitors, op-amps, and switches, the latter being controlled according to some given clocking scheme. The result of the analysis are transfer functions in the z-domain, where Z is the complex frequency variable for time-discrete circuits.
4.2.1. Modeling of the SC Circuits SC circuits are periodically time-varying circuits. The number of clock phases, or switch states, of the circuit depends on the actual clocking scheme of the clocks controlling the switches, and can be two or more. A clock phase is defined as a periodically returning time interval in which the clocks of a time-discrete circuit have a certain logical level. For example, in the case of two exactly synchronous complementary clocks, there are two phases. In general, overlap periods and nonoverlap periods should be considered as separate phases. So, for two complementary clocks with short nonoverlapping periods, one
Sec. 4.2
89
Classification of Techniques for the Symbolic Analysis of SC Circuits
can, in general, distinguish four clock phases. Note that multirate clocking is also allowed, which means that the number of phases has to be determined over one period of the clock with the lowest frequency. The methods used in the analysis of SC circuits depend basically on the models selected for the switches, the switched capacitors, and the op-amps. In most cases, the op-amps are modeled as a voltage-dependent voltage source, with either a large finite or, in the ideal op-amp case, an infinite gain, an infinite input impedance, and a zero output impedance. The capacitors are usually considered as linear, lossless, and time-invariant. In certain methods, the switched capacitors are replaced by equivalent circuits without switches. In other methods, the switches are modeled on their own. The ideal model of a switch is to replace it by an open circuit (infinite resistance) when the switch is open (off) and by a short circuit (zero resistance) when the switch is closed (on). Each switch is controlled by a periodic clock signal. This ideal switch model allows the symbolic analysis of SC circuits in the z-domain. The resulting transfer functions are then rational functions, where the coefficients of z in the numerator and denominator polynomials are sums of products of the capacitors and (when the op-amps are not considered as ideal) the gains of the op-amps:
(4-2)
On the other hand, when the switch model includes a finite resistance in its closed and/or open state, then it is not possible to find simple symbolic expressions for the transfer functions of the circuit. The analysis must then consider the transient behavior of the circuit, due to the RC time constants and the resulting finite settling within the available clock phases. Such analysis involves the evaluation of state transition matrices for each state of the switches in the circuit, Le., for each clock phase. The state transition matrix is equal to the exponential exp(At.) of the state space matrix A for phase i with a time duration of t; . The symbolic expressions of the transfer functions depend explicitly on all these state transition matrices. Hence, the analysis of such circuits should be restricted to the generation of semisymbolic expressions with the frequency variable z as the only symbolic parameter. The same holds when the finite gain-bandwidth of the op-amps is considered, which also causes a finite settling in the available clock phases.
,
EXAMPLE 4.1 Consider, for example, the simple RC circuit of Fig. 4.3. The switch is opened and closed with a clock period T. Assume that the capacitor initially is charged to an initial voltage
vo = v (0). If we close the switch at time t = T /2, then the voltage source E is connected across the resistor R to the capacitor C, which will therefore be charged (or
Figure 4.3 Simple example RC circuit.
f
c
90
Chapter 4
discharged) in the time interval
Symbolic Analysis of Switched Analog Circuits
~ ~ t < T from the value "o up to the value of E
according
to O~t<
T
(4-3)
where u (t - tx) is the unit step function with a unit step from 0 to 1 at time tx ' The current flowing through the resistor R in this same time interval is
Os r c T
(4-4)
Clearly, both voltages and currents in this example have transient behavior that depends on the circuit time constant RC relative to half the clock period T12, and requires an evaluation of the scalar transition factor exp (-T12RC). In circuits with many capacitors and resistors, it is necessary to evaluate a state transition matrix that is equal to the exponential exp (A T) of the state space matrix A. On the other hand, if we assume that R ~ 0 (which corresponds to an ideal switch and voltage source model if R models the switch resistance and/or the driving source resistance in this example), then the voltage across the capacitor changes instantaneously from va to E at the time point t = T12 when the switch is closed: v(t) =
"o" (E-Vo)u(t-D
O~t
(4-5)
This requires an infinite current through the resistor at the switching moment t = T12, and the current is zero at all other moments: O~t<
T
(4-6)
where 0 (t - t x) is the Dirac impulse function at time point tx' The integral of the current between t = T 12 and t == T is equal to the electrical charge flown to the capacitor, resulting in the capacitor voltage becoming equal to E. The advantage of considering R = 0 is that the evaluation of the transient behavior is avoided. All currents flow and all voltages change instantaneously at the switching moments (i.e., the moments when at least one clock switches state), and all voltages remain constant and all currents are zero in between, i.e., throughout a clock phase. The equations that describe such idealized SC circuits will be described in section 4.3. Clearly, the errors introduced by this simplification can be neglected in practice only when the time interval available for the signals to settle (due to RC time constants and/or finite gain-bandwidths) is small compared to the switching period. Note that it is also assumed in example 4.1 that E remains constant during the phase when the switch is closed. So it is often assumed that the input signal of the SC circuit is stepwise constant and only changes at switching instants. In practice, this corresponds to a sample-and-hold function applied to the input signal before it drives the SC circuit.
Sec. 4.3
Algebraic Methods
91
4.2.2. Classification of Symbolic Analysis Methods The symbolic analysis methods for SC circuits presented in the literature can basically be classified as follows. The first proposed SC dedicated symbolic simulators could only produce partially symbolic transfer functions, where the complex frequency variable z is the only parameter represented as a symbol. These methods include Refs. [3]-[6]. They will not be discussed further in this chapter. Their operation is all based on a matrix formulation of the SC circuit equations. A much more difficult problem is to obtain symbolic expressions for SC circuits where, besides z, some or all network elements are also kept as symbols. The methods to resolve this problem can be classified into four categories, depending on how they formulate and solve equations: 1. Algebraic methods. These methods use a matrix formulation of the z-domain circuit equations and solve them symbolically, for instance, by calculating the determinants [7], [8]. 2. Circuit transformation methods. These methods transform the switched z-domain circuit into an equivalent unswitched circuit, which can then be analyzed by traditional s-domain symbolic analysis programs [9]-[ 11]. 3. Signal ftowgraph methods. These methods construct a signal flowgraph representation of the z-domain circuit equations, which is then solved, for instance, using Mason IS rule [11]-[ 15]. 4. Parameter extraction methods. These methods also use a matrix formulation of the z-domain circuit equations, but solve them using the technique of parameter extraction, which internally takes advantage of powerful numerical solution techniques [10], [16]. These different methods will now be explained in more detail in the following four sections.
4.3. ALGEBRAIC METHODS In the algebraic methods, the z-domain equations of the SC circuit are described in matrix format. These circuit equations are a combination of the circuit equations for each phase of the circuit, including the relations between the values of the variables during the different clock phases.
4.3.1. Formulation of the SC Circuit Equations F9r an ideal time-discrete circuit, z-domain equations can be constructed in a way similar to time-continuous circuits. Several different formulations of the equations can be used for this, such as the tableau formulation, the MNA formulation, or any other formulation. For symbolic analysis, however, it is important that the size of the matrices is reduced as much as possible and that the set of equations is therefore restricted to the strict minimum necessary to calculate the requested transfer function. Note that the same is true for the numerical simulation of SC circuits, such as that used in the program SWAP [17].
92
Chapter 4
Symbolic Analysis of Switched Analog Circuits
The minimum matrix size for SC circuits is then determined by the number of state variables (integration capacitors) and outputs. This minimum set of equations is given by the charge conservation equations at the virtual ground nodes of all integrating op-amps at all phases. These charge conservation equations for phase j equate the charges stored on the capacitors connected to each virtual ground node to the charges stored on those capacitors in the previous phase j - 1. Because the charge on a capacitor is equal to the capacitance times the voltage difference across the capacitor, these matrix equations therefore relate the values of the voltages V during phases j and j - 1:
A.V.-B.V. 1 = E. )) )))
j
= 2, ... , K
(4-7)
where E.) denotes the vector of input voltage sources and K is the number of phases. The same is true for phase 1, where the voltages, however, are related to the voltages of the previous phase, which in this case is phase K. Thus, the equations show an additional delay factor of
-1
z : (4-8)
This formulation is used for instance in SSCNAP in combination with a parameter extraction method to derive the transfer function [16]. In general, when the circuit would contain elements other than voltage sources, capacitors, and ideal op-amps (e.g., an op-amp modeled as a voltage-controlled voltage source with finite gain), additional branch relations would be required and a more general formulation like modified nodal analysis (MNA) has to be used. Fortunately, even the MNA equations can be compacted using row and column compactions. Such a compacted formulation, called CMNA, is used in the program ISAAC [8], which can symbolically analyze both continuous-time and discrete-time analog circuits. The resulting z-domain CMNA equations can be denoted as [7] Al
0
-E 2 A 2 0
0
-E K
-I
BI
0
0
VI
QI
0
0
B2
0
V2
Q2
AK
0
0
-Elz
B K . VK
=
QK FI
CI
0
0
D1
0
0
ql
0
C2
0
0
D2
0
q2
F2
0
0
CK
0
0
DK
qK
FK
(4-9)
where Vk is the vector of node voltages and qk is the vector of additional branch charges at every phase k (k ranging from 1 to K with K being the number of phases in the circuit). Q k is the charge source vector and F k is the voltage source vector at every phase k. The direct construction of this z-domain CMNA matrix from the circuit description is not straightforward. Fortunately, it can easily be constructed by combining the s-domain CMNA matrices of each phase of the circuit. Indeed, in each clock phase, all switches are in a certain state, either closed or open, and can therefore be replaced by either a perfect
Sec. 4.3
93
Algebraic Methods
short or a perfect open (using the ideal switch model). The resulting circuit in that phase is therefore a normal continuous-time circuit that can be described by a traditional set of s-domain equations, such as MNA or CMNA. The overall z-domain CMNA matrix is then constructed as follows [7]. First, the s-domain CMNA matrices of the ideal circuit (with zero time constants) in all phases are constructed. This can be done directly from the circuit description by using the appropriate CMNA stamps for each element. The submatrices A k' B k' Ck' D k' Qk and F k are then formally retrieved from the s-domain CMNA matrices and vectors of phase k by putting s equal to 1. The matrices E k' on the other hand, are obtained from the matrices E; of the noncompacted MNA of phase k by performingthe CMNA row compactionscorresponding to phase k and the CMNA column compactions corresponding to the phase prior to phase k. This formulation is now illustrated in the following example. EXAMPLE 4.2
The z-domain CMNA equations for the Fleischer-Laker biquad of Fig. 4.4 with two complementary clocks can be derived as -1
-(C+E) -D Ez -(B + F)
E B
0 D 0
B
-E -B
Dz
-1
A
-D 0
-1
- (G + L) V in 1 + (H + L) Z
V out I V
int l
V out2 V
=
-(K+L)Vinl+(K+L)z
-1
V in2 V in2
(4-10)
LVinl-LVin2
int2
KVin I - KVin2 c
E F
D B
Vin
G
Vout
K
Figure 4.4 Switched-capacitor biquad of Fleischer and Laker.
94
Chapter 4
Symbolic Analysis of Switched Analog Circuits
where A, ... , L denote the symbols for the capacitors in this circuit, Vint is the output of the first integrator, and VO U f is the output of the second integrator. The indices 1 and 2 denote the voltage at phase 1 and phase 2, respectively. These four equations are the charge conservation equations at the two virtual ground nodes of both op-amps at phases 1 and 2. In this case, the CMNA equations basically come down to Eqs. (4-7) and (4-8). As the conventional MNA method requires 98 equations for this simple example, it is clear why matrix compactions have to be used, both for the symbolic and the numerical simulation of SC circuits.
4.3.2. Solution of the SC Circuit Equations Once the set of z-domain equations has been set up in matrix format, the next step is to symbolically solve this set of equations. In order to find a transfer function from an input at phase p to an output at phase q, Cramer's rule can be used, which requires the calculation of some determinants. Any of the determinant calculation methods mentioned in chapter 2 in this book can be used. In the ISAAC symbolic analyzer, determinants are calculated through a recursive symbolic Laplace expansion along the row or column with the largest number of zero elements (the most sparse row or column), while throughout this expansion process, calculated minors are stored for possible reuse later on [8]. If we assume that the most sparse row or column is row i, then the Laplace expansion of the determinant of the n x n matrix A along that row is given by n
L
(-1)
i+j
a··IM ..1 IJ IJ
(4-11)
j = 1, aij;tO
If, on the other hand, the most sparse row or column is column j, then the Laplace expansion along that column is given by: n
L
(-1)
i+j
a··IM·.1 IJ IJ
(4-12)
i = 1, aij;tO
IMi·1
where the summation is extended over the nonzero elements aU only, and the minors are the determinant of the (n - 1) x (n - 1) matrix obtained from the original matrix Abj removing row i and column j. These minors are recursively calculated with the same formulas and, after elaborating all term cancellations, they are stored for possible reuse later on in the determinant calculation. EXAMPLE 4.3
The z-domain transfer functions for the Fleischer and Laker biquad of Fig. 4.4 are now calculated. The clocking scheme contains two complementary clocks, so there are two phases in this circuit. If the input is sampled at phase 1and then held constant under phase 2 (with a preceding sample-and-hold circuit) and the output is considered at phase 1, then the transfer function becomes
Sec. 4.4
95
Circuit Transformation Methods
(4-13)
.., (DK-AL-AH+DJ) +z(AG-2DK+AL-D/-DJ) +z-D(/+K)
H I I (Z) =
2
(AE-BD) +z(-AC-AE+2BD+DF) +z (-I)D(B+F)
A more compact expression is obtained by setting B = D = 1. This means that all symbols must now be interpreted as capacitor ratios (relative to the corresponding integration capacitor, either B or D). The transfer function now becomes 2
H II () z
- (K-AL-AH+J) +z(AG-2K+AL-/-J) +z (/+K)
-
2
(4-14)
(AE-l) +z(-AC-AE+2+F) +z (-1) (I +F)
If, on the other hand, the input is considered in phase 2 and the output is observed under phase I, then the transfer function becomes H
21
() -
z -
(AEK-AL-AH+J) +z(-AEK+AL-J) 2
(4-15)
(AE-I) +z(-AC-AE+2+F) +z (-1) (I +F)
If we now look at the output node of the first op-amp under the same conditions, then the transfer function becomes
(4-16)
Hil
2
(z) =
O+z(-EFK+E/+CK-G) +z (FG+EFK-CK-E/-C/+G) ') (AE-I) +z(-AC-AE+2+F) +z-(-I) (I +F)
And similar expressions can be derived for other transfer functions or network functions of interest. Note that it is also possible to analyze each phase of the SC circuit separately. Because at each phase the circuit reduces to a continuous-time circuit, finite switch on-resistances and op-amp gain-bandwidths can now easily be taken into account, resulting in s-domain network functions that can be generated by ISAAC for each phase separateI y.
4.4. CIRCUIT TRANSFORMATION METHODS A second class of methods starts from the periodically time-varying switched-capacitor circuit and transforms this into an equivalent time-invariant analog circuit (EAC), which has no switches and can be analyzed by any of the traditional s-domain symbolic analysis programs discussed in chapter 2, after which s can be replaced again by the inverse function of z. One procedure for generating the equivalent circuit for two-phase SC circuits was presented in Ref. [9]. In this method, every capacitor is replaced by an equivalent circuit resulting in the overall EAC. Depending on the transformation used, the equivalent circuit consists of different elements; for example, four inductors and two resistors in the one case, and one inductor and three controlled sources in the other case mentioned in Ref. [9]. The first transformation corresponds to the following variable transformation in the equations of the two-phase SC circuit:
96
Chapter 4
Symbolic Analysis of Switched Analog Circuits
(4-17) where V, I , and Q are the voltage across, the current through, and the charge stored on the capacitor in the odd (subscript 0) or even (subscript e) phase, respectively, and the prime indicates a transformed variable. The conductors model the coupling between the variables of the two clock phases. The back-substitution is then z = s,2. The second transformation corresponds to the following variable transformation: (4-18) where the transformed variables are indicated by the double prime. The back-substitution is now simply z = S". 2 An alternative method that uses the transformation z = s for transforming two-phase SC circuits into an equivalent analog circuit is presented in Ref. [10]. The derivation of the method is based on voltage ratio matrices, but finally requires the symbolic analysis of an EAC consisting of capacitors, conductances, voltage-controlled voltage sources, and voltage-controlled current sources. In Ref. [10], the method is used in combination with the parameter extraction method for the analysis of the EAC. A generalization of the equivalent circuit method to K-phase SC circuits can be obtained by considering a subcircuit for each phase k (k = 1, ... , K) of the circuit, which is derived from the original circuit by replacing every capacitor Cj by a conductance G. = C., in parallel with a voltage-controlled current source with transconductance value }
}
C.} but controlled by the voltage across the capacitor in the previous phase k - 1, Le., by
r
Vj (k _ 1 In addition, for the first phase, a delay z-1 has to be added to the controlling
voltage Vj K (see Eq. (4-8)). This delay is modeled with an additional voltage-controlled current source loaded with a capacitor of value 1, resulting in a delay of .:'. In Ref. [11], the method is used in combination with a signal flowgraph analysis technique. EXAMPLE 4.4
This method is now illustrated for the simple two-phase SC integrator of Fig. 4.1. The EAC, shown in Fig. 4.5, consists of the subcircuits corresponding to phases 1 and 2, respectively, as well as the additional equivalent s-1 delay model. Note that in Fig. 4.5, Vc
. denotes the voltage across "capacitor" C. in phase j . After solving the equations for
i')
l
this EAC from the input voltage under phase 1 to the output under phase 2 and formally back-substituting s by z, the following transfer function is indeed obtained:
V out, 2 Vin,l
C1 - C2 (1 -
z")
(4-19)
A problem with this method is that the number of circuit elements and circuit nodes in the EAC increases with the number of phases in the circuit. And it is well known that the CPU time and memory requirements of a full symbolic analysis drastically increase with the circuit size. Fortunately, in many cases, the resulting EAC can still be simplified to
Sec. 4.5
97
Signal Flowgraph Methods
(a) phase 1 CI
Vin __
C2,0<:--····
---i
Vout
<.:: 2,1
Vout
" ~/
CIVCl.I
I,
"
,
.'
,I
I'
{cJPh~'se to model delay I' I
"
'
'.
I'"
CI
'~q;J
<...
C2,2
Vout
CIVCl.2
Figure 4.5 Equivalent analog circuit for the two-phase SC integrator of Fig. 4.1, consisting of a subcircuit for (a) phase 1, (b) phase 2, and (c) the extra phase modeling the delay.
some extent without altering the result. For example, a capacitor that is connected across a voltage source or that is shorted by a switch can be deleted from the EAC, thereby reducing the complexity of the EAC.
4.5. SIGNAL FLOWGRAPH METHODS In these methods, the SC circuit is represented as some graph, from which the transfer function can be derived with any of the graph formulas presented in chapter 2. The graph can be a set of undirected conjugate graphs, a directed graph, or a signal flowgraph (a Mason or a Coates graph). A signal flowgraph (SFG) is particularly interesting because the SFG on its own already provides in-depth information about the discrete-time behavior of the circuit to the user. In the SCYMBAL tool [11], the Coates graph is used. First, the periodically time-varying SC circuit is replaced by an equivalent time-invariant circuit, which connects subcircuits for each of the phases of the SC circuit as described in the previous section. The
98
Chapter 4
Symbolic Analysis of Switched Analog Circuits
transfer functions are then obtained from the Coates graph of this equivalent circuit by using the following topological formula. The determinant of a Coates flowgraph G is equal to
det (G) = (-I) w~>ign (T) T
n
val (t)
(4-20)
t. I
where n is the number of nodes in G, and the sum extends over all O-connections T = (t 1, ••• , t n ) of the graph. The method has the same limitation in circuit size as all direct topological methods, unless hierarchical decomposition techniques are used [13]. An extra feature of the SCYMBAL tool is that not only the capacitors or the frequency variable can be represented as a symbol, but also the switching timing functions. These are symbolically represented by Boolean variables that determine whether the switch is open or closed in a given phase. For two-phase circuits, for instance, a symbolic toggle switch can be described by one Boolean variable. This variable will be 0 if the first switch is, for example, of e-type and the second switch of a-type. In the other case, when the first switch is of a-type and the second switch of e-type, the variable is 1. This feature is important when different timing schemes or different topological structures for the circuit under design are considered. The SCYMBAL program has been accompanied by several postprocessing modules (e.g., pole/zero analysis), where the symbolic equations are evaluated numerically [14]. For certain applications requiring the repetitive numerical evaluation of circuit characteristics (e.g., frequency analysis of SC circuits), the one-time generation of the symbolic equations followed by a repetitive numerical evaluation is shown to be more efficient than a repeated direct numerical analysis. In addition, Ref. [14] also presents an entirely symbolic application of SCYMBAL. New SC circuit structures (composed from a given set of elements) are exhaustively generated by a PROLOG program and each resulting structure is analyzed symbolically in order to decide whether it is a valid structure that meets all requirements. In this way, new structures have been found with sometimes better properties than the structures that were used before the experiment. A method to directly generate the signal flowgraph of a two-phase SC circuit by inspection is presented in Ref. [12]. Once the signal flowgraph is known, Mason's rule is used to derive the desired transfer function. The method is particularly targeted to hand analysis of medium-size circuits. The circuit must conform to the requirement that every capacitor is connected to at least one source switch and to one sink switch. This limitation should be met by parasitic-insensitive SC circuits. An alternative approach to generate the signal flowgraph of an SC circuit is presented in Ref. [15]. Rule-based techniques are employed to capture the symbolic SFG from an arbitrary circuit schematic and timing diagrams. The principle is illustrated in Fig. 4.6. The technique has been applied to a large variety of SC circuits, including multirate circuits. SC circuits generally consist of the interconnection of elementary blocks comprising switches, capacitor, and op-amps. A library of frequently employed SC elementary blocks has been included in the program's knowledge base (SC-KB), in which, for each block, the corresponding signal flowgraph representation has been coded with respect to the associated timing diagram. Next, a rule-based program has been developed that, starting from a given SC circuit schematic and the timing diagram, recognizes elementary blocks in this schematic and then generates the corresponding SFG. The rules consist of structural rules for identifying the circuit elements constituting a block as well as
Sec. 4.6
99
Parameter Extraction Methods
~--4
SC knowledge base
symbolic transfer function Figure 4.6 Principle of rule-based generation of the signal flowgraph of an SC circuit, followed by a derivation of the SC transfer function.
evaluation rules to calculate parameters needed to construct the resulting SFG (e.g., delays, SFG weight factors, etc.). Once the SFG is known, the symbolic z-domain transfer function can be generated automatically, and several other performance indicators (like the capacitance spread or the nominal frequency response and its variability) can be generated from the transfer function by numerically instantiating the symbols. More details on this technique, including examples of rules, as well as some symbolic analysis examples, can be found in chapter lOin this book.
4.6. PARAMETER EXTRACTION METHODS The last class of methods also uses a matrix formulation of the z-domain circuit equations, but solves them using some form of parameter extraction (see chapter 2 for a basic explanation of this technique), which internally takes advantage of powerful numerical solution techniques. These methods are especially suited for the analysis of large SC circuits where only a few circuit elements (typically a maximum of 10) are represented as symbols. In Ref. [10], a first method is presented that uses the indefinite admittance matrix (lAM) description of a two-phase SC circuit in combination with the parameter extraction method. The lAM of the SC circuit is constructed using the four-port equivalent circuits of all capacitors (resulting from the two phases). This lAM is then contracted by adding and
100
Chapter 4
Symbolic Analysis of Switched Analog Circuits
deleting rows and columns, while keeping the zero-sum property, after which the parameter extraction method is executed to calculate the cofactor. The second method presented in Ref. [10] uses voltage ratios of an associated resistive network to derive an equivalent analog circuit without switches (based on the transformation
2
z =
s), which is then solved with the parameter extraction method. This
second method was reported to be more advantageous than the first method when the number of switches is much smaller than the number of capacitors [10]. An improved method for K-phase circuits was later presented in the program SSCNAP [16]. This program can generate partially or totally symbolic z-domain transfer functions and large-change or small-change sensitivities, but the circuit may contain at most only 10 symbolic elements [16]. In addition, poles and their sensitivities can be derived numerically as well. The formulation is based on Eqs. (4-7) and (4-8). Valid symbol combinations are detected and the coefficients are calculated using the fast Fourier transform (FFT) method in polynomial interpolation. For the large-change sensitivities, perturbation theory is used to calculate the transfer function in terms of the value increments of the symbolic elements.
4.7. CONCLUSIONS In this chapter, methods have been discussed for the symbolic and semisymbolic analysis of switched analog circuits. Historically, these are mainly switched-capacitor circuits, although more recently, switched-current circuits are gaining importance. The switching in these circuits makes them time-varying and necessitates the use of special techniques to obtain the z-domain transfer functions. After discussing the modeling of the different circuit elements (especially the switches and the op-amps), it is clear that z-domain equations can only be derived for "ideal" circuits without internal time constants. The different symbolic analysis techniques for switched circuits have then been classified and described in detail. The basic step is to transform the periodically time-varying circuit into an equivalent time-invariant representation of the overall circuit by combining the schematics, the equations, or the individual graphs for the different phases of the circuit. This equivalent circuit can then be analyzed by any of the traditional symbolic analysis methods (algebraic or topological). Finally, parameter extraction techniques are preferred when the number of symbolic elements is rather limited (maximum 10). Several symbolic analysis examples have been provided to illustrate the different techniques.
Acknowledgments The author acknowledges Erich Wehrhahn and Herman Walscharts for their contributions.
References [1] R. Schaumann, M. Ghausi, and K. Laker, Design ofAnalog Filters. Englewood Cliffs, NJ: Prentice Hall, 1990. [2] C. Toumazou, F. Lidgey, and D. Haigh (eds.), Analogue Ie Design: The Current-Mode Approach. London: Peter Peregrinus, 1990.
References
101
[3] C. Kurth and G. Moschytz, "Two-port analysis of switched-capacitor networks using four-port equivalent circuits in the z-domain," IEEE Trans. Circuits Syst., vol. CAS-26, pp. 166-180, March 1979. [4] Y. Kuo, M. Liou, and W. Kasinska, "An equivalent circuit approach to the computer-aided analysis of switched-capacitor circuits," IEEE Trans. Circuits Syst., vol. CAS-26, pp. 708-714, September 1979. [5] J. Vlach, K. Singhal, and M. Vlach, "Computer oriented formulation of equation and analysis of switched-capacitor networks," IEEE Trans. Circuits Syst., vol. CAS-31, pp. 753-765, September 1984. [6] C. Pun and J. Sewell, "Symbolic analysis of ideal and nonideal switched capacitor networks," Proc. IEEE Int. Symp. Circuits Syst., Kyoto, Japan, pp. 1165-1168, 1985. [7] H. Walscharts, G. Gielen, and W. Sansen, "Symbolic simulation of analog circuits in s- and z-domain," Proc. IEEE Int. Symp. Circuits Syst., Portland, pp. 814-817, 1989. [8] G. Gielen, H. Walscharts, and W. Sansen, "ISAAC: A symbolic simulator for analog integrated circuits," IEEE J. Solid-State Circuits, vol. SC-24, no. 6, pp. 1587-1597, December 1989. [9] E. Wehrhahn, "Evaluation of transfer functions of ideal SC networks in z domain using standard linear symbolic or semisymbolic networks," Electron. Lett., vol. 16, pp. 801-802, 1980. [10] Y. Cheng and P. Lin, "Symbolic analysis of general switched-capacitor networksNew methods and implementation," Proc. IEEE Int. Symp. Circuits Syst., Philadelphia, pp. 55-59, 1987. [11] A. Konczykowska and M. Bon, "Topological analysis of switched-capacitor networks," Electron. Lett., vol. 16, pp. 89-90, 1980. [12] G. Moschytz and J. Mulawka, "New methods of direct closed form analysis of switched-capacitor networks," Proc. IEEE Int. Symp. Circuits Syst., pp. 369-372, 1986. [13] A. Konczykowska and M. Bon, "SCYMBAL 2: A portable computer program for efficient all symbolic hierarchical analysis of large multi phase switched capacitor networks," Proc. European Conf. Circuit Theory Design, Stuttgart, Germany, 1983. [14] A. Konczykowska and M. Bon, "Automated design software for switched-capacitor IC's with symbolic simulator SCYMBAL," Proc. Design Automation Conf., Anaheim, CA, pp. 363-368,1988. [15] M. Fino, J. Franca, and A. Steiger-Garcao, "Automatic symbolic analysis of switched-capacitor filtering networks using signal flow graphs," IEEE Trans. Computer-Aided Design, vol. 14, no. 7, pp. 858-867, July 1995. [16] B. Li and D. Gu, "SSCNAP: A program for symbolic analysis of switched capacitor circuits," IEEE Trans. Computer-Aided Design, vol. 11, no. 3, pp. 334-340, March 1992. [17] SWAP 2.2 Reference Manual. Silvar Lisco, Heverlee, Belgium, Document M-037-2, 1983.
5 Marwan M. Hassoun
Dept. Electrical Engineering and Computer Engineering Iowa State University Ames, Iowa
Hierarchical Symbolic Analysis of Large Analog Circuits
5.1. INTRODUCTION This chapter presents hierarchical methods for symbolic analysis of large analog circuits. The two main limitations for performing symbolic analysis on a large circuit are classic: computer execution time and memory requirements. All the symbolic analysis techniques presented in chapter 2 are polynomial in time and exponential in memory requirements. Those methods, therefore, are limited to relatively small circuits in the range of 15 nodes and 30 branches due to the time and memory restrictions [1]. Hierarchical symbolic analysis techniques solve both problems by introducing some classical divide-and-conquer techniques and nested expressions techniques. Hierarchical symbolic analysis can be performed on two independent levels: the circuit level and the output symbolic expression level. A hierarchical algorithm that is aimed at analyzing large circuits will usually incorporate both levels of hierarchy. The two processes are completely independent of each other and the advantages of the analysis on each level can be assessed separately. All currently existing programs that perform hierarchical analysis, FLOWUP [2], SCAPP [3], and MAS SAP [4], incorporate hierarchical analysis on both the circuit and the expression levels.
5.1.1. Circuit Level Hierarchy On the circuit level, the idea is to partiuon the circuit, or its appropriate representation, into a number of smaller subcircuits, as shown in Fig. 5.1. The binary tree shown in Fig. 5.1 b is the representation of the partitioned circuit of Fig. 5.1 a. Symbolic analysis is then performed on the different subcircuits, producing a symbolic solution for
102
Sec. 5.1
103
Introduction
(a)
• •
•
C9
•
• •
•••• •• • • • • (b) Figure 5.1 A partitioned circuit and its equivalent tree representation: (a) a hierarchical circuit; (b) binary tree model.
each. This process is referred to as the terminal block analysis. Each terminal block is represented by a leaf in the partitioning tree shown in Fig. 5.1 b. The next step is to combine the symbolic solutions for the subcircuits in order to find the symbolic solution for the entire circuit. In the case of a frequency-domain analysis, which is the main application of symbolic analysis, the goal is to combine the transfer functions of all the subblocks and generate the transfer function for the final circuit. The process of combining symbolic solutions of subcircuits is referred to as middle block analysis. Each nonleaf vertex in the tree of Fig. 5.1 b refers to a middle block.
104
Chapter 5
Hierarchical Symbolic Analysis of Large Analog Circuits
It is appropriate at this point to introduce a terminology set that is used in describing a partitioned circuit. Figure 5.1 a can represent a physical circuit or its flowgraph representation. The following is a set of variables that represent a partitioned circuit:
N, = set of nodes (variables) in partition (block) B i . ENi
=set of external variables in partition Bi .
IN i = set of internal variables partition B i . TN = set of tearing variables. V = set of input and output variables. V is always a subset of TN (V c TN). In order to illustrate these concepts, Fig. 5.1a and b are considered. Nodes n,I E V and no E V represent the input and output node variables of the circuit, respectively. The circuit, of course, may have several of each. All input and output node variables are considered external nodes and may be voltage or current variables. Nodes na, nb' nc' through n/ are all tearing nodes (E TN). Nodes na and n c are external nodes to block B I
v;
(n a , n b E EN 1); however, na is an internal node to block Bp + 1 E IN + I)' while nc is p an external node to block Bp + 1 E EN + I). Block Bp + 1 is B U B . An important I 2 p
'».
observation is that an external node on one hierarchical level of the analysis may become an internal node on another level. Eventually, at B main level, all tearing nodes other than those in V become internal nodes to B main . For the purpose of simplifying the discussion and without any loss of generality, the partitioning tree of Fig. 5.1 b is assumed to always be a binary tree. That is, middle block analysis is always performed on two subcircuits at a time. All possible combinations can be broken down to a binary combination process. The process can be further illustrated as follows. main (circuit) { /* Main routine */ root = partition (circuit); /*Partition circuit and return the root vertex*/ analyze (root) /*Recursively perform the symbolic analysis */ } /* End of main */ analyze(parent) /* Recursively Manage the terminal and Middle block analyses */ { if (left_child) { /* If there is a left child then a right one must exist */ analyze(left_child) ; analyze(right_child) ; middle(parent); /* Perform middle block analysis */ } else { /* A leaf has been reached */ terminal(parent); /* Perform terminal block analysis */ } }
Sec. 5.1
Introduction
105
The two processes middle() and tenninal() refer to middle block analysis and terminal block analysis, respectively. This concept of hierarchical analysis is also referred to as upward hierarchical analysis [5]. While other orderings of the analysis process can be found-almost as many as there are traversal paths for a binary tree [6]-this traversal is the most intuitive in terms of implementation and explanation of the hierarchical analysis concept. While terminal block analysis can be performed using any of the basic methodologies highlighted in chapter 2, it is imperative to use a method that would adapt to the hierarchical combination step that is the middle block analysis. This is the main reason for the choices made for the algorithms described later in this chapter. The justification for using circuit level hierarchical analysis is the increased execution speed for large circuits. This can be seen by considering a circuit that is to be symbolically analyzed by an algorithm exhibiting a quadratic time complexity O(n 2), which would be considered a good solution, where n is a measure of the size of the circuit (number of nodes, number of branches, or both). The time it takes to analyze the circuit is then proportional to
(5-1) If the circuit is partitioned into p partitions, as shown in Fig. 5.1, then the time it takes to analyze the circuit is (5-2)
which is a speedup of order p, the number of partitions. This argument is, of course, an oversimplification. It assumes equal partitions and no cost for the partitioning or the middle block analysis step. For practical problems, the speedup is invariably less than p but greater than 1, and is highly dependent on the algorithm used and the implementation [7]. While the partitioning problem is beyond the scope of this book, it must be noted that, by today's definition, a large circuit has to be built from the bottom up using subcircuits that are put together during the process. These subcircuits for the hierarchical algorithms are excellent partitions, and circuits with such a hierarchical definition do not need to be run through a partitioning algorithm. There are many partitioning algorithms that can be used and are suitable for the symbolic analysis algorithms that make use of circuit level hierarchy (e.g., Refs. [8]-[ 12], to mention a few). The discussion of any particular partitioning algorithm is beyond the scope of this book.
5.1.2. Expression Level Hierarchy (Sequence of Expressions) The main problem with the symbolic analysis of large circuits is the exponential growth of the number of symbolic terms involved in the expression for the transfer function in equation (2-1). The solution to analyzing large circuits lies in a total departure from the traditional procedure of trying to state the transfer function as a single expression and instead using a sequenceofexpressions procedure [13]. The idea is to produce a succession of small expressions with a backward hierarchical dependency on each other. An example of a sequence of expressions is shown via example 5.1 and (5-6) through (5-9). The growth of the number of expressions in this case will be, at worst case, quadratic [7].
106
Chapter 5
Hierarchical Symbolic Analysis of Large Analog Circuits
The advantage of having the transfer function stated in a single expression lies in the ability to gain insight into the relationship between the transfer function and the circuit elements by inspection [14]. For large expressions though, this is not possible, and the single expression loses that advantage. Some algorithms ([ 15]-[ 18]) attempt to handle larger circuits by maintaining the single expression method and using circuit dependent approximation techniques (see chapter 6). The trade-off is accuracy for insight. Therefore, the sequence of expressions approach is more suitable for accurately handling large-scale circuits when obtaining insight by inspection from the expressions is not the primary goal. The following example illustrates the features of the sequence of expressions.
EXAMPLE 5.1 Consider the resistance ladder circuit in Fig. 5.2. The goal is to obtain the input impedance function of the circuit, Zin = V in/ lin. The single expression transfer function Z4 is
Z4
R
I
+R
+R
+R
I
+R
4R3 = -4R- - -4R2 -- -3R - - -3R-2 R +R +R 1
2
(5-3)
3
The number of terms in the numerator and denominator are given by the Fibonacci numbers satisfying the following difference equation:
y(k+2) = y(k+ I) +y(k) An explicit solution to this equation is
y (n) =
~(t +2
k = 0, 1,2, ...
y(O) = O,y(l) = 1 (5-4)
J5y -( J5 y I -2
:::: 0.168 x 1.618
n
(5-5)
for large n
The solution shows that the number of terms in Zn increases exponentially with n. Any single expression transfer function has this inherent limitation. Now, using the sequence of expressions procedure, the input impedance can be obtained from the following expressions: (5-6)
o
o
R2D-2
0-1
••••
•••• Z2n-l Figure 5.2 Resistive ladder circuit.
Sec. 5.1
107
Introduction
(5-7)
(5-8)
(5-9) It is obvious that, for each additional resistance added, the sequence of expressions I) / (R 1. + Z.1- I). The will grow by one expression, either of the form R.1 + Z.1- I or (R.Z. 1 1number of terms in the sequence of expressions can be given by 2.5n - 2
y (n) = ( 2.5n _ 1.5
for n even
(5-10)
for n odd
which exhibits a linear growth with respect to n. So, to find the input impedance of a 20
1DO-resistor ladder circuit, the single expression methods would produce 7.9 x 10 terms, which requires unrealistically huge computer storage capabilities. On the other hand, the sequence of expressions method would produce only 248 terms, which is even within the scope of some desk calculators. Another advantage of the sequence of expressions is the number of mathematical operations needed to evaluate the transfer function. To evaluate Z9' for example, the single expression methods would require 302 multiplications and 87 additions. The sequence of expressions method would only require eight multiplications and eight additions, a large reduction in computer evaluation time. All this makes the concept of symbolic circuit simulation of large circuits very possible.
5.1.3. Parallel Processor Implementation Issues Traditionally, serial algorithms have been independent of the architecture of the machine on which they are run. This is not the case for parallel algorithms. Finding a match between a parallel algorithm and hardware architecture is crucial to the success of parallelization given the numerous parallel architecture and interconnection circuits that exist today. This section merely attempts to identify parallelism in the general hierarchical symbolic analysis skeleton that was presented in the previous two sections. Very few attempts have been made in this direction and discussions of these works can be found in Refs. [19]-[21]. There are tw-o major areas where hierarchical symbolic analysis concepts can be parallelized:
• Outer parallelism. The terminal block analysis can be completely parallelized. This is because terminal blocks can be analyzed independent of each other. This is the outer parallelism, a direct benefit of partitioning.
• Inner parallelism. This parallelism is completely dependent on the type of algorithm that is used for the terminal block analysis, in addition to whether a sequence of expressions method was used or not. Each one of the methods presented in chapter 2 needs to be examined for the parallelism in their algorithms. This has
108
Chapter 5
Hierarchical Symbolic Analysis of Large Analog Circuits
been studied for some MNA-based methods [19], [21], but studies of the parallelism potential of all the methods has yet to be reported.
5.1.4. Existing Hierarchical Methods Two topological analysis methods (flowgraph-based) for symbolic analysis of large circuits have been proposed in Refs. [2] and [4]. The first method utilizes the sequence of expressions idea to obtain the transfer functions. The method operates on the Coates flowgraph [22] representing the circuit. A partitioning is proposed onto the tlowgraph and not the physical circuit. The second method also utilizes the sequence of expressions and a Mason signal tlowgraph [23] representation of the circuit. The method makes use of partitioning on the physical level rather than on the graph level. Therefore, for a hierarchical circuit, the method can operate on the subcircuits in a hierarchical fashion in order to produce a final solution. The fundamentals of both signal flowgraph methods were described in chapter 2. Another hierarchical approach is one that is based on modified nodal analysis [24]. This method ([7], [3]) exhibits a linear growth (for practical circuits) in the number of terms in the symbolic solutions. The analysis methodology introduces the concept of the RMNA (reduced modified nodal analysis) matrix. This allows the characterization of symbolic circuits in terms of only a small subset of the circuit variables (external variables) rather than the complete set of variables. The analysis algorithm is most efficient when circuit partitioning is used. Partitioning results in a reduction in the number of terms in the symbolic solutions. The remainder of this chapter is dedicated to illustrating the three hierarchical methods and a performance comparison between them.
5.2. HIERARCHICAL DIRECT NETWORK METHOD The algorithm described in this section is part of the modified nodal analysis based methods described in section 2.7.3 of this book. This method, as with the other hierarchical methods presented in this chapter, is a noniterative hierarchical approach to symbolic analysis. It was first presented in Refs. [3] and [7] and named "direct network," because it operates directly on the network matrix level rather than the flow graph level that the other two methods proposed for large circuits are based on [2], [4]. The algorithm is implemented in a ~ymbolic £ircuit gnalysis 12rogram with 12artitioning (SCAPP). Another feature that distinguishes this method, but will not be discussed here, is its implementation on a multiprocessor computer system [19]. Following the general skeleton highlighted in section 5.1, the analysis process is divided into the following parts: (1) binary circuit partitioning, (2) subcircuit analysis (terminal block analysis), and (3) upward hierarchical analysis (middle block analysis). The process is modeled using a binary tree, Fig. 5.1b. The circuit is partitioned into subcircuits that are represented by the leaves of the binary tree, and each nonleaf vertex in the tree represents a binary partitioning operation. After circuit partitioning is performed, the binary tree modeling the process is defined and the next step is the terminal block analysis. The implementation of this method, SCAPP, utilizes an automatic circuit partitioning algorithm [12], in addition to accepting pre-partitioned circuits as an input.
Sec. 5.2
109
Hierarchical Direct Network Method
5.2.1. Terminal Block Analysis Terminal block analysis results in a symbolic system of equations extracted from the subcircuit using MNA and RMNA (see section 2.7). The representation is that shown in (2-61). The application of (2-72) and (2-73) on the entries of the matrix results in the generation of a new symbol. This symbol is the only entity carried forward to successive variable suppression steps. This process generates the sequence of expressions, which drastically reduces the number of symbolic terms that are handled and stored. The disadvantage, of course, is that it is not possible to detect cancellation terms. However, because term cancellation is a way of reducing the number of symbolic terms, this sequence of expression provides ample reduction in the number of terms (see section 5.2.3). Exploring the term cancellation in the sequence of expression format without expanding the expression has not been reported in the literature. In order to establish the terminology used in describing a block, terminal or middle, a typical n-terminal block is considered: block Bi . N; is the set of all the nodes of block i. It is defined as follows: (5-11)
N.I = IN.uEN. I I
where IN; is the set of internal nodes to the block and EN; is the set of external nodes. There are n; total nodes in N;. n; is defined as
n I. = in.w en.I I
(5-12)
where in; is the number of elements in IN; and en; is the number of elements in EN;. The complete set of tearing nodes for the entire circuit is TN. The tearing nodes between two or . . k .. ' c TN, is defined as more blocks are always a subset of TN. This subset, TNI,}, follows: (5-13)
TN.I,},i.k .. ' = EN.r.EN.r.ENkr.··· I }
For the simple example of Fig. 5.3a, N.={0,1,2,3} n.=4 en.=3 N 2={0,3,4,5} n2=4 e1l2=3 TN 1,2 ={0, 3 } TN ={0, 1, 3, 5 } Note that IN; r. EN; = 0 is always true.
EN. ={ 0, 1, 3 } EN2 ={ 0, 3, 5 }
IN. = {2}
IN2={4}
The process of performing a symbolic analysis on the circuit in Fig. 5.1 follows these steps (Fig. 5.4): 1. Partitioning the circuit (or using user-defined subcircuits, which is the case for large circuits) into the terminal blocks Bi (1 < i < p) and obtaining the binary tree model shown in Fig. 5.1b. 2. Performing the terminal block analysis on each block B, (on each leaf of the characterizing each one. binary tree) and obtaining an RMNA matrix 3. Successively performing the middle block analysis in a hierarchical binary fashion by traversing the partitioning binary tree upwards starting with the leaves until the root is reached. The final result is one RMNA matrix characterizing the entire circuit in terms of the defined input and output variables
Yk
110
Chapter 5
Hierarchical Symbolic Analysis of Large Analog Circuits
+
(a)
(b) Figure 5.3 Hierarchical analysis example.
Step 1:
Hierarchical partitioning pre-partitioned subcircuits)
of
the
circuit
(or
recognizing
already
Step 2:
Terminal Block Analysis: (Symbolic generation of sequence of expression for each subcircuit) 2.1. Build Symbolic MNA matrix 2.2. Reduce MNA matrix to a RMNA matrix by suppressing all internal variables.
Step 3:
Middle Block Analysis: 3.1. Combine solutions from terminal block analysis of subcircuits in a hierarchical manner. 3.2. Reduce the matrix to a final RMNA matrix by suppressing all internal variables.
Figure 5.4 SCAPP serial algorithm.
Sec. 5.2
111
Hierarchical Direct Network Method
specified by the user. The algorithmis not limited to a hierarchicalbinary process only. The steps illustrated in section 5.2 are intuitively expandable to any number of partitions on a given hierarchical level. Figure 5.4 highlights the algorithm steps.
5.2.2. Middle Block Analysis Middle block analysis is the process of combining the electrical characterization of two n-terminal blocks, one with n 1 terminals and another with n2 terminals, to produce a characterization for a new n-terminal block that physically is the interconnection of the initial two blocks. The number of terminals of the new block, n3' is bound by 3 > n 3 > n 1 + ": - 1, assuming the existence of a reference node that is common to both blocks. Figure 5.3 illustrates the idea of middle block analysis. Blocks B1 and B2 are both and n-terminal blocks that will be characterized by two separate RMNA matrices, respectively. The new n-terminal block B 1,2 that results from the interconnectionof blocks 2. The process of producing B1 and B2 will be characterized by a new RMNA matrix 2 is the middle block analysis. l After partitioning into p terminal blocks and terminal block analysis is performed, the circuit in Fig. 5.1a is characterized by p RMNA matrices in terms of the variables that are the members of the set TN, which includes the extra current variables requested from the analysis. Consider the connection of any two terminal blocks, namely blocks Bj and Bj . The RMNA equations describing each are
yA
Yi,
YA'
yl
r;]
(5-14)
[Y~] .[;;] = r;]
(5-15)
[Yk] . [;f]
=
The two blocks share the tearing nodes in the set TNi,j = TNi () TNj. Also, Ni,i = N i U Nj . The following middle analysis steps are taken in order to produce the RMNA matrix corresponding to a middle block. 1. Combine the vector of external variables for the two blocks by letting
vi.)
= Vie U
li,j = Ii U e
Vie
(5-16)
u
(5-17)
.e
where the vectors Vi,j and li,j are the node voltages and current variables of the middle block BjJo 2. Combine the RMNA matrices to produce a temporary intermediate matrix YR ' such that
t
112
Chapter 5
Hierarchical Symbolic Analysis of Large Analog Circuits
YRi 0] [0 Y~
YR = t
(5-18)
and also to produce the following temporary right-hand-side vector RHSt
Jie RHS = t
0
(5-19)
Jj
e
0 3. Add the columns and rows of YR that correspond to the tearing node voltage t
variables shared between the two blocks, that is, the nodes that are members of the set TNi,j. Mathematically, adding the columns in this step reflects the fact that the voltage at a tearing node is equal in all blocks. The concept of adding the rows is not as simple. Each row corresponding to a tearing node represents the sum of the currents entering the block from that node. The corresponding entry in the RHS vector symbolizes the current entering that node from the rest of the circuit. A tearing node shared between the two blocks falls under one of three categories:
i. The tearing node is only an element of ENi and ENj . So, it is a local tearing
node for block B iJ and therefore it is an internal node to Bi,j and a member of the set INi .
*
*
ii. The tearing node is also an element of ENk , k i and k j . That is, it is shared by more than the blocks B, and Bj . This dictates that it must remain as a tearing node, i.e., its row and column not suppressed. It is therefore an external node to B iJ and a member of the set ENi,j. iii. The tearing node voltage variable is requested by the analysis in which case it becomes a member of ENi . So, when adding the rows of a node corresponding to case 3.i, the entry in RHSt will become zero. This is because the current entering block B j from the rest of the circuit through the tearing node (only Bj in this case) is equal to the negative of the current entering block Bj from the rest of the circuit (only B j in this case). However, when adding the rows of a node corresponding to 3.ii and 3.iii, the entry in 2 becomes simply. a symbol indicating the current entering that node from the rest of the circuit (outside Bi,j).
J:'
4. Suppress all the internal variables to block Bi,j in order to obtain the RMNA matrix characterizing the block in terms of its external variables. After step 3 is completed, the sets INi,j and ENi,j become completely defined and the intermediate RMNA system of equations can be written as
Sec. 5.2
113
Hierarchical Direct Network Method
l] [y',l. ~ . [Vi' I',l R
..
t
= RHS t
(5-20)
The suppression of the tearing nodes shared between the two blocks and corresponding to case 3.i above will reduce .the vi,j vector to the external voltage variable vector v~,j. To understand the entries of r,l, a look at how a current variable reaches a middle block analysis stage is considered. A branch current variable is always an internal variable unless it has been requested by the analysis or has had a pivoting problem and was unable to be reduced earlier, in which case it has been labeled as an external variable. Conceptually, though, it can never be an external variable. Blocks do not share branch currents, they share node voltages, because the partitioning is a node tearing technique [7]. Therefore, an attempt to reduce a current variable that has not been requested by the analysis must be made. The current variables considered here all have a pivot problem. The pivot problem might be resolved by the creation of a fill at that position because of the suppression of the now internal nodes that control the pivot of the current variable. If not, the variable is not suppressed and its row and column are carried along farther up the middle block analysis binary tree. So, Ii,j = Ii,j unless the suppression of one e .. .. or more "healed" variables was successful, in which case I~,l c I',l . The final result of the middle block analysis of blocks B j and Bj is the RMNA matrix characterizing middle block Bj,j in terms of its external variables. The RMNA system of equations is written as e lj = [Ji' e l] . ~ [Vi' [y',l' Ii,j 0 R
(5-21 )
e
The current variables are grouped at the bottom of the variable vector strictly for cosmetic reasons and have no effect on the analysis. An example will serve to illustrate these middle block analysis steps.
EXAMPLE 5.2 The circuit in Fig. 5.3 is partitioned into two terminal blocks: B 1 and B 2 . The binary tree in Fig. 5.3b can be used to model the analysis. The terminal block analysis of each block was performed in example 2.8. Notice that TN,j = {3} and node 3 is local to the middle block B 1,2' Therefore, Nf' 2 = {3} and Ni,2 = {I, 5}. Concatenating and and adding the rows and columns corresponding to the tearing node results in
y1
VI
1 GI
YR
t
=3
0
5 0
V
3
V
yi
s
-G t ll 2
0
-sC3 + G 4 - sC3 1l2 + G s
-G SIl 6
0
sC 7 + G g - sC71l6
(5-22)
The final step of the middle block analysis is to delete the row and column corresponding to the internal variable v3' The result is the following RMNA matrix characterizing the middle block B 1,2:
114
Chapter 5
1, 2 _ 1 G}
YR
-
5 0
Hierarchical Symbolic Analysis of Large Analog Circuits
-SC 3 + G4 -sC 3 Jl2 + GS
(5-23)
sC 7 + G g - sC 7 Jl6
The process of recursively applying middle block analysis up the binary tree of Fig. 5.1b at each nonleaf vertex (middle block) will produce one final RMNA matrix characterizing the circuit in terms of the variables requested by the analysis. The terminal block analysis is performed on the leaves of the tree and p RMNA matrices are produced. At the second level of the binary tree, the middle block analysis is performed on pairs of terminal blocks. The process will produce p/2 RMNA matrices representing the p/2 middle blocks. As illustrated earlier, a middle block is physically a subcircuit. It is the result of interconnecting two closely coupled smaller subcircuits. So, terminating the hierarchical analysis at this point will yield a characterization of the p/2 subcircuits represented by the middle block. Also, at this point, the leaves are no longer of any use to the process. They may be deleted after the middle block analysis at their parent vertex has been performed. The p/2 middle blocks and their RMNA characterizations become the leaves of the new reduced binary tree. They can be treated as terminal blocks and the middle block analysis is repeated at the next level up. The structure of the binary tree is dictated by the partitioning (Fig. 5.1b). Depending on the partitioning, the structure of the binary tree will range between a balanced binary tree and a totally unbalanced binary tree. A balanced binary tree is a highly desirable structure and is essential for the case where the hierarchical analysis is performed on a multiprocessor computer. The algorithm is very parallelizable because each terminal block analysis is a totally independent process and each middle block analysis is only dependent on its children. Examining Fig. 5.1 b will show that block B(3/2)p+l has to wait for blocks Bp+1 and Bp +2 to finish before it can be processed, which in turn requires all four blocks B I , B2, B3 , and B4 to finish. This is the hierarchical dependency of the process. The vertices on the same level are always totally independent processes. They may be analyzed concurrently [19].
5.2.3. Analysis of the Sequence of Expressions The quality of the results of the analysis are measured by statistics based on the resultant sequence of expressions from SCAPP [3]. A good symbolic result for a large circuit is one that has a minimal number of symbolic terms in it and produces a minimal number of mathematical operations required to evaluate the sequence of expressions. The latter is very important, because the main usage of this type of symbolic analysis is the repetitive evaluations of the results in order to characterize a circuit and optimize circuit element values. This section will show that the number of symbolic terms produced by SCAPP grows linearly as a function of the size of the circuit (for practical circuits) and finds an estimate for the number of operations (multiplications, divisions, additions, and subtractions) generated in the sequence of expressions. The basic terminal analysis process is given by Eq. (2-73). The actual implementation is performed on an element-by-element basis of the MNA and RMNA
Sec. 5.2
115
Hierarchical Direct Network Method
matrices as shown in Eq. (2-75). The equation for updating the RMNA matrix element ajk' as a result of reducing the ith variable (ith row and column), is given by for j
~i
and
k~i
The process is performed on the matrix, row by row, only for rows where element Therefore, the term 1 p. = -·a .. I a.. Jl
(5-24) aji ~
o.
(5-25)
II
need only be generated once for each row. The expression in (5-24) can then be written as (5-26) This expression is generated for each element in row j for which a i k ~ O. The goal here is to deal with "real" circuits. What this means is that the number of branches incident on a node are bound by a constant, K, which is on the order of 6 in the worst case (excluding ground and power supply nodes). This results in the number entries in a row of an MNA matrix being bound by the constant K 1 = 2K + L, where L is a constant on the order of 2 in the worst case to account for the entries due to dependent sources in the circuit [24]. By the same analysis, the number of entries in a column is given by a constant K 2. So, for a worst case analysis, assuming no partitioning, the process of reducing an MNA matrix with n variables (n x n matrix) to an RMNA matrix with two variables (2 x 2) matrix will generate a total number of symbols n-2
N sym =Ko·n+ £..J ~ K2 · (3+4·K 1)
(5-27)
i= 1
where the (3 + 4 . K I) is the total number of symbols generated from the processing of one row «5-25) and (5-26» and (K o . n) is the number of symbols needed to represent the initial entries of the MNA matrix.
The expression in (5-27) can be reduced to (K o · n) + (n - 2) . K 2 . (3 + 4· K 1), which is of the order O(n). The Ks in Eq. (5-27) are kept constant because some fills are created in the matrix as the size of the matrix decreases. A good partitioning algorithm (or a reordering algorithm) can guarantee a nonincreasing K 1 and K 2 [7]. The number of operations generated in the sequence of expressions is given by n-2
Nmults",K3+
LK
2"
i
=1
(l +K 1) = K3+ (n-2) " (K 2+K1"K2 )
(5-28)
n-2
Nadds '" K4 +
It K
i
=1
2
= K4 + (n - 2) "K 2
(5-29)
where N mults represents the number of multiplications and divisions, Nadds represents the number of additions and subtractions, K3 and K4 represent the initial figures to represent
116
Chapter 5 Hierarchical Symbolic Analysis of Large Analog Circuits
the initial entries of the MNA matrix (usually only the diagonal will need some addition operations, and K3 represents the frequency variable multiplications). From (5-28) and (5-29), it can be seen that the number of operations that the sequence of expressions will generate for a "real circuit" is linear with respect to the size of the circuit. It must be noted, though, that the constants K} and K 2 in (5-28) can be on the order of 14, which makes the coefficient K} . K 2 on the order of 196, which is significant for large circuits.
5.3. HIERARCHICAL MASON SIGNAL FLOWGRAPH METHOD This method makes use of both partitioning and a sequence of expressions approach to analyze large circuits. The method uses the Mason signal flowgraph (MSFG), described in section 2.4.1, as the engine for the analysis mainly because it is a more general method of representing both electrical and nonelectrical systems versus other methods described in chapter 2 that are more suitable for electrical circuits. Further advantages of using the Mason signal flowgraph are listed in section 5.5. The analysis process consists of the following parts: 1. Partitioning of the circuit. This can be done on one of two levels: on the circuit level, by using circuit partitioning algorithms like the ones described in Ref. [12] or on the signal flow graph level. The second level would require the creation of the signal flowgraph for the entire circuit and then attempting the partitioning. Circuit partitioning is a natural choice for large circuits because they are inherently composed of hierarchically combined subcircuits. These subcircuits are natural partitions on the circuit level but not necessarily on a signal flowgraph level. The discussion of a particular partitioning scheme is beyond the scope of this book. Figure 5.1b shows a recursive hierarchical partitioning model. 2. Signal flowgraph generation. This step is illustrated in section 2.4.1 and may occur in one of two places in the process. It can be performed on each of the subcircuits (terminal blocks) after the circuit partitioning has been performed or on the entire circuit and then performing a graph partitioning. The latter is considered inefficient and is an impractical choice for large circuits. The reason is that the size of a signal flowgraph needed to represent a circuit is much larger than the circuit itself. That is, it has more nodes and branches than the circuit. This is a function of the SFG formulation as illustrated in section 2.4. 3. Analysis of the partitions or terminal block analysis. This consists of using Mason signal flow graph to symbolically analyze the partitions. The goal here is to produce a representation of the partition in terms of its inputs and outputs only. The inputs and outputs of a partition are defined as its tearing nodes, in addition to the input and output variables of the entire circuit. So, for a circuit with two inputs and two outputs, the final reduced signal flowgraph will be as illustrated in Fig. 5.5. All internal nodes of the MSFG have been suppressed using the MSFG reduction rules described a little later in this chapter. 4. Hierarchical recombination of the solutions or middle block analysis. A new partition is created by combining two partitions with at least one common tearing node. Each common tearing node becomes an internal node of the new partition and is reduced using the MSFG reduction rules. The recombination process follows the partitioning model (Fig. 5.1b) hierarchically and recursively up the tree.
117
Sec. 5.3 Hierarchical MasonSignal Flowgraph Method
NETWORK
Figure 5.5 Reduced signal flowgraph model.
The implementation of the flowgraph analysis algorithm is called MASSAP (Mason gnalysis nrogram) [4].
~ymbolic
5.3.1. Analysis of the Partitions (Terminal Block Analysis) This step of the process mainly performs a systematic reduction, also referred to as
node suppression or variable suppression, of all internal nodes of a signal flowgraph representation of a subcircuit (Fig. 5.5). Mathematically speaking, the goal is to find the transfer function of the outputs to the inputs of the subcircuit. A note is in order here: if partitioning is not used and the flowgraph of the entire circuit is submitted for terminal block analysis, the result will be the symbolic transfer functions of the outputs to the inputs of the entire circuit, which is what is desired of the solution.
5.3.1.1. MSFG Reduction Rules The systematic node suppression rules for signal flowgraphs are as follows: I. Series suppression of a node (Fig. 5.6). A series suppression is a specific case of the general suppression with only one branch entering and one branch exiting a node. A new branch is created from node I to node 3 with a reduced weight. 2. Parallel reduction of branches (Fig. 5.7). Any parallel branches are reduced to one remaining branch with a combined weight. A reduction of this type is performed on parallel feedback loops if any exist. 3. General suppression of a node (Fig. 5.8). A general suppression performs a series suppression from every branch entering to every branch leaving that node .
• °3
Figure 5.6 Seriessuppression of node n2'
Figure 5.7 Parallel reduction of branches 1 and 2.
118
Chapter 5
Hierarchical Symbolic Analysis of LargeAnalog Circuits
Figure 5.8 General suppression of node n3'
Once all series suppressions for a given node are complete, the node and its incident branches are removed. 4. Self-loop reduction (Fig. 5.9). A self-loop adjusts the weights of all branches entering the node. The feedback branch is then deleted. 5. Suppression of a node with no outgoing branches. This corresponds to an input-output (I/O) variable not requested by the analysis. The suppression is done by simply deleting the node.
5.3.1.2. Reduction Order The terminal block analysis begins by visiting all the nodes included in the signal flow graph. For all nodes in the flowgraph, any parallel or feedback reductions are performed first, and for all internal nodes, any general reductions are also performed. These operations produce new branch structures. Operations are performed in the order stated previously because parallel and self-loop reductions are computationally less expensive than series reductions. The external nodes are then revisited to reduce any self-loops created by the deletion of internal flowgraph nodes. In addition to the general set of variables defined earlier in section 5.1.1, the following variables are defined:
BR i =set of signal flowgraph branches in partition i. wb = weight associated with branch b. Tn = set of branches entering signal flowgraph node n. F n = set of branches exiting signal flowgraph node n. Being an external node is determined by a direct check in the list of tearing nodes TN. TN is defined as
(5-30)
Figure 5.9 General reduction of a self-loop.
Sec. 5.3
Hierarchical Mason Signal Flowgraph Method
119
If node n does exist in TN, then the node is not to be suppressed. If, however, the node is not in TN, the node is scheduled to be suppressed. The use of the sequence of expressions to perform the suppression is best illustrated via the examples in section 5.3.4.
5.3.2. Middle Block Analysis The algorithm concludes execution by recombining the solutions for the partitions into an overall system solution. The algorithm is recursive, highly parallelizable, and suitable for implementation on multiprocessor machines. Each partition can be analyzed independent of the other partitions and is only visited once (non-iterative). The general algorithm can be illustrated as follows: main {
TN = {set of input and output nodes}; MSFG_analyze (Circuit); suppress (Circuit, TN);
/* Delete any internal nodes left */
/* End of main procedure */ where MSFG_analyze() is the procedure that initiates the process and manages the middle block analysis. The routine suppress() performs the terminal block analysis including the implementation of the MSFG reduction rules. They are both listed here. MSFG_analyze (Circuit) { partition (Circuit);
/* Binary partition into Pleft & Pright and perform the analysis */ /* Partitions P left & Pright and generates their tearing nodes TNleft and TNright*/
if (PIeft is a leaf cell) suppress (P left, TNleft); else MSFG_analyze (Pleft); if (P right is a leaf cell) suppress (Pright, TN right); else MSFG_analyze (Pright) combine (Pleft, Pright); return (Circuit); } /* End of MSFG analysis */
/*Suppress internal nodes for this block*/ /* Recursively call MSFG_analyze */ /*Suppress internal nodes for this block*/ /* Recursively call MSFG_analyze */ /* Produce merged MSFG by concatenating the reduced MSFGs and generate the new Circuit */
120
Chapter 5 Hierarchical Symbolic Analysis of Large Analog Circuits
suppress(P, TN) {
1* Suppress all internal nodes for a partition P *1
foreach (n
E
Ni ) {
1* All nodes*1
1* A parallel suppression (Fig. 5.7)*1 foreach ( b 1 E Tn) {
1* For all incoming branches *1
foreach (b 2 E Tn &&nodel (b1) = node2(b2)){/* All parallel branches *1 Wbl
= Wbl
+ Wb2
I*Wbl
;
= weight of 1st parallel branch *1
delete( b2) ; }
I*reduce all self loops (Fig. 5.9) *1 foreach (b
E
Tn &&nodel (b)
=nodel(b)) {
foreach (b.In E Tn &&b.In ;t b){ Wbin = wbin,!(1 - wb)
foreach (bin
E Tn) {
foreach (b ou t E F n) { create new branch b; W bnew
1* A self-loop found *1 1* For all incoming branches *1
1* A series and general suppression *1 1* (Fig. 5.6 and Fig. 5.8) *1
= w b in· w bo ut ;
delete all branches attached to node n; delete(node n);
} 1* End of variable suppression for this partition *1 } /* End of suppression for this partition *1
5.3.3. Discussion 1. It is better to reduce feedback paths before all the nodes in the forward path of the loop are deleted. This is not a requirement for the success of the algorithm; however, it will have a significant impact on the resultant sequence of expressions. Table 5-1 demonstrates the effect of the reduction order. It is possible to guarantee that all nodes in a feedback path are reduced first by one of two ways:
121
Sec.5.3 Hierarchical Mason Signal Flowgraph Method Table 5·1 Comparison of Bandpass Filter Results *
Partitioning status With partitioning
Without partitioning
Bandpass [2] Analysis method
Mults
Adds
Eqs
Coates (flowgraph) [2]
63
30
25
SCAPP (network) [3]
48
27
56
MASSAP (flowgraph) [4]
70
29
60
Coates (flowgraph)
**
**
**
SCAPP (network)
79
35
88
MASSAP (flowgraph)feedback nodes reduced first
89
38
85
MASSAP (flowgraph)feedback nodes reduced last
94
40
92
* Number of multiplications includes divisions and number of additions includes subtractions. ** Data not available for the unpartitioned case. i. Implementing a check before eliminating each node. A search for any path from that node to itself is sufficient to identify a feedback loop. If such a path is found, the processing of that node is assigned a lowest priority position in the reduction queue. ii. Listing all feedback paths first in the input deck. This will guarantee that all feedback nodes are placed in a higher position in the reduction queue. This is equivalent to labeling the feedback paths or the feedback nodes as such, which is another possible altemativee 2. Because Laplace transforms and signal flowgraphs are only capable of characterizing and analyzing linear systems, operational amplifier circuits can be analyzed only if they are in a linear configuration. Therefore, because there are only a few general forms of such configurations (see Figs. 5.10 and 5.11 and Eqs. (5-33), (5-34), (5-35), and (5-36)), it is best to include them in a macro library. Any occurrence of a linear operational amplifier circuit would be replaced by its appropriate signal flowgraph model.
3. Ideal operational amplifier reduction rules is: Recursively reduce all op-amp feedback loops. The recursiveness is necessary because an op-amp circuit can exist in the feedback path of another op-amp configuration (Fig. 5.12). This would require reducing op-amp circuit A and replacing it by its equivalent op-amp model before continuing with the reduction of op-amp circuit B. Also, all linear operational amplifier configuration signal flowgraphs are derived from a library rather than reanalyzing at every op-amp instance in the circuit. A general form for a linear op-amp circuit is shown in Fig. 5.10. The resulting signal flowgraph is also shown in Fig. 5.10, where
122
Chapter 5
Hierarchical Symbolic Analysis of Large Analog Circuits
4
Figure 5.10 Operational amplifier example. 7 81(5.3)
-.
.....
~----
12
Figure 5.11 Signal flowgraph reduction process on Fig. 5.12.
BLOCKS 1,1,3 and 4
5 1
Part A
PanB
,
Figure 5.12 Building block of the bandpass filter.
s
Sec. 5.3
Hierarchical Mason Signal Flowgraph Method
123 (5-31 )
(5-32) For each additional input Vi - connected to the negative terminal of the op-amp through an admittance Yi-' the expression associated with it is given by
Vo v; H (V , V.) = - = - o 1V. )' 1f
(5-33)
where Yf is the feedback admittance from the op-amp output node to the negative input terminal. Also, for each additional input connected to the positive terminal of the op-amp through an admittance Yi+' the expression associated with it is given by
= Va _ Vi + -
Yi+lLYi- + Yr) YALYi+ + Yg )
(5-34)
where LYi- is the sum of all input admittances connected to the negative terminal of the op-amp and Yg is the admittance between the positive terminal and the low reference voltage. Usually in active filter design, Yg is chosen such that
Yg = LYi- + Yf-LYi+
(5-35)
which makes (5-34) look like (5-36) and reduces the number of operations in the output expressions needed to model the general linear op-amp circuit. However, for the sake of generality, (5-33) and (5-34) are used in solving the examples in this section to produce the figures in Tables 5-1 and 5-2.
5.3.3.1. Performance Measures There are two measures to the performance of the recursive algorithm outlined in the previous section: (1) the program running-time complexity measured by the number of steps the algorithm has to perform and (2) the quality of the results measured in terms of the number of operations it produced in the sequence of expressions (number of additions, subtractions, multiplications, and divisions). First, the algorithm complexity is addressed using a circuit with b branches, n nodes, and p partitions. An average number of nodes per subcircuit is given by
124
Chapter 5
Hierarchical Symbolic Analysis of Large Analog Circuits
Table 5-2 Further Comparisons between Direct Network Method and Mason's Flowgraph Method"
Analysis method
Fig. 5.17: Block 1
Fig. 5.13: Biquad [26]
Mults
Adds
Eqs
Mults
Adds
Eqs
SCAPP
16
7
23
16
6
22
MASSAP
13
5
11
16
5
18
Analysis method
Fig. 5.21: Ladder circuit (10 nodes)
Fig. 5.21: Ladder circuit (20 nodes)
Mults
Adds
Eqs
Mults
Adds
Eqs
SCAPP
48
34
54
102
70
107
MASSAP
98
33
98
218
73
218
* Number of multiplications includes divisions and number of additions include subtractions.
n
p
n p
=-
(5-37)
Because this algorithm seeks to deal with real problems, a perfectly valid assumption is that a real circuit has an upper bound on the number of branches incident and leaving each node (excluding the reference nodes). A general survey of practical (real) circuits showed that an average of six branches are connected to a given circuit node. Therefore, for this discussion, the average number of branches connected to a node is assumed to be a constant. Alternatively, this assumption states that each vertex in the flowgraph has an average of k branches connected to it, kl2 entering and kl2 leaving. Because each branch has two nodes, this gives rise to the following equation:
b
= nk 2
(5-38)
The average asymptotic time complexity of the algorithm is given by
o (nlogn)
(5-39)
Detailed analysis of the individual parts of the algorithm and the derivation of this equation can be found in Ref. [4]. To study the quality of the results, a close inspection of the algorithm yields a direct correspondence between the number of operations that need to be performed in every reduction and the number of operations resulting in the sequence of expressions. In general terms, each series reduction (Fig. 5.6), parallel reduction (Fig. 5.7), general suppression (Fig. 5.8), or self-loop reduction (Fig. 5.9) at a node will produce
Sec. 5.3 Hierarchical Mason Signal Flowgraph Method
2 multiplications and 0 additions for a series 1 reduction
omultiplications and ~
~ ~
additions for a parallel reduction
125 (5-40) (5-41)
multiplications and 0 additions for general suppression
(5-42)
multiplications and I addition for self-loop reduction
(5-43)
Equations (5-40) through (5-43) show that the number of operations that will result in the sequence of expressions will exhibit only a linear growth with respect to the size of the circuit measured by the number of nodes in its signal flowgraph.
5.3.4. Examples EXAMPLE 5.3-BANDPASS FILTER TERMINAL BLOCK
This example (Fig. 5.12) is the analysis of a circuit that is a composed of three subcircuits, labeled Part A, Part B, and Part C. The operational amplifiers have already been reduced to flowgraph form where H (x, y) refers to the weight of the edge between node x and node y. It also corresponds to the transfer function between the input node x and the output node y. Figure 5.11 illustrates the hierarchical combination process and then the process of finding the final result. Because the block has two input nodes (1 and 12) and one output node (5), the resultant signal flowgraph consists of two branches representing the transfer functions H (12,5) and H (1,5). The resulting sequence of expressions is HI (1,3) = (gl (g2 +g4»/(g4(gl +g3» HI (12,3) = - (g2) / (g4) HI (7,3) = - (gg) / (g4) HI (3,5) = - (gs) / (g6 + SC 6) HI (5,7) = - (g7) / (sc g) Reduce node 7
HI (5,3)
Reduce node 3
HI (12, 5)
= HI
= HI
(5,7) . HI (7,3)
(12, 3) . HI (3, 5)
HI (1,5) = HI (1,3) . HI (3,5) HI (5,5) = HI (5,3) . HI (3,5)
Reduce selfloop at node 5
H(I2,5) = HI (I2,5)/(I-HI (5,5» H (1,5) = HI (1, 5) / ( 1 - HI (5,5) )
EXAMPLE 5.4-DUAL-BIQUAD
Consider the dual-biquad amplifier example shown in Fig. 5.13 [25]. The output sequence of expressions is
1
Note that, by definition, a series reduction implies a node with one incoming branch and one outgoing branch. A series reduction for a node that has k/2 incoming branches and k/2 outgoing branches is simply a general suppression (5-42).
126
Chapter 5 Hierarchical Symbolic Analysis of Large Analog Circuits
Gil
G. ~~----Vol
Vin
Figure 5.13 Dual-biquad amplifier for example 5.4 [25].
wl
= -g41 (gl -
sCI)
w2 = -g21sC2 w3
= -gslg6
w4 = -g41g3 w5 = -gglgll w6 = -g7lglO w7
= -g9lglO = w l . w2
HOE1 (1,6) HOE2 (1,8) = w l . w5 HOE3 (1,11)
= wI· w6
HOE4 (10,6) = w4· w2 HOES (10, 8) = w4· w5 HOE6 (10, 11) HOE7 (1, 10) HOE8 (10, 10) HOE9 (1, 10) HOE10(1,8) HOEll (1,11) HOE12 (1, 8)
= w4· w6 = HOE1 (1, 6) . w3 = HOE4 (10, 6) . w3 = HOE7 (1, 10) I (1 - HOE8 (10, 10) ) = HOE9(1, 10) . HOE6(10, 11) = HOE9(1, 10) . HOE6(10, 11) = HOE2 (1, 8) + HOE10 (1, 8)
HOE13 (1, 11) = HOE3(1,11) +HOE11(1,11) +w7
Sec. 5.4
127
Hierarchical Coates Graph Method
5.4. HIERARCHICAL COATES GRAPH METHOD The algorithm illustrated in this section is based on a topological method presented in section 2.4.2. The hierarchical Coates graph method was used for symbolic analysis in Ref. [2]. The Coates graph method itself is not a widely used topological method in electrical engineering applications compared to its counterpart, the Mason signal flowgraph. However, the Coates graph approach was the first hierarchical symbolic analysis method to be developed [2]. The hierarchical Coates graph method consists of the three basic parts of a hierarchical algorithm as presented in section 5.1. They are partitioning, terminal block analysis, and middle block analysis. The partitioning proposed for this method differs from the previous two methods described in that it is performed on the graph level rather than the circuit level. The algorithm requires the building of the Coates graph for the entire (unpartitioned) circuit and then partitioning of the Coates graph. This process, therefore, does not take advantage of prepartitioned circuits. While the methodology looks to be capable of addressing this issue, it has yet to be reported in the literature. The graph partitioning problem is very similar to the circuit partitioning problem mentioned in section 5.1.1. The same basic algorithms (e.g., Refs. [8]-[12], to mention a few) can be used here and the discussion of any particular one is beyond the scope of this book.
5.4.1. Terminal Block Analysis The terminal block analysis consists of the enumeration of all the multiconnections in a block (see section 2.4.2 for the definition of a multiconnection). The reason for that is the interconnection of the subgraphs leads to the connection of their multiconnections to form new ones on higher levels. The multiconnections are generated in groups rather than one at a time and they are connected together in groups, which results in a more efficient algorithm, The only set of multiconnections that are needed are the ones that relate the tearing nodes to each other. The tearing node set for a block, EN, is broken into two parts, set I, which represents the initial nodes, and set 0, which represents the end nodes of multiconnection edges. P(I,O) is defined as the set of multiconnections relating I to O. The rest of the internal nodes have full incidence, that is, they are both initial as well as end nodes for multiconnection edges. We can readily see that tearing nodes included in I n 0 have full incidence. EXAMPLE 5.5 [2]
For the graph in Fig. 5.14, EN = {1,2,3,4}, I = {1,2}, and 0 = {3,4}. The set of multiconnections needed is P(l, 0) =P { { 1, 5, 3},{2, 4, 6}}.From definitions 2.9 and 2.10, these multiconnections are composed of {1,5,3}
E P{
(1,4), (2,3)}
(5-44)
{2,4,6}
E P{
(1,3), (2,4)}
(5-45)
Of course, another choice of I and 0 would produce a different set of multiconnections. I and 0 for a block are defined by its relationship to the rest of the circuit and are assigned during the partitioning phase. The analysis proceeds by finding all the desired multiconnections, as illustrated in section 2.4.2.
128
Chapter 5
Hierarchical Symbolic Analysis of Large Analog Circuits
Figure 5.14 Example of a terminal block.
5.4.2. Middle Block Analysis The middle block analysis for the Coates method consists of the evaluation of multiconnections of a block that is composed of an interconnection of two or more blocks. For clarity purposes, and without loss of generality, the interconnection of two blocks will be considered. The blocks will be referred to as block 1 and block 2 and their external node sets will be EN I and EN2 , respectively. The external node set for the middle block, block 3 (the combination of the blocks 1 and 2), will be denoted EN3 - This is similar for I and 0. The connection of the two blocks may result in nodes that are in both EN I and in EN2 , called common nodes, and nodes that are in one or the other (or both) but not in EN3 , called reducible nodes. The formal definition is common nodes
= COM = EN I
(1
EN 2
(5-46)
reducible nodes
= RED = COM -
EN3
(5-47)
Any set of multiconnections for block 3, P(I3,03), can then be found by the following rule:
(5-48) where "X" is a Cartesian product [26] of the two sets. This summation (union) is performed over all sets of multiconnections of PI (II' 1 ) and P 2 (12, 02)' satisfying the conditions
°
II n I2 = 0
°
1(1° 2
= 0
RED = (IluI2)
(1
(0Iu0 2) (5-49)
where
(5-50) The sign of a multiconnection P3 E P 3 is calculated as follows:
Sec. 5.4
129
Hierarchical Coates Graph Method
(5-51) whereP3 = PI UP2,PI E Pl,andp2E P 2 · The signs of PI and P2 are calculated from (2-27) and the parameters k and ~ are
integers dependent on the number of multiconnections and their permutations [2] and are given by k
= min [card (0 1 nI2nCOM),card(02nll nCOM)]
+ card (COM)
(5-52) (5-53)
where the ord function is defined in (2-27) and the card function gives the number of k-connections in a graph. A great advantage of using (5-48) is the ability to simultaneously evaluate groups of multiconnections.
EXAMPLE 5.6 The two blocks in Fig. 5.15 are to be connected to create a third block with the external nodes 1, 2, and 3 only. The following sets can be readily established from the figure: EN t = { 1, 2, 4 }, EN2 = {2, 3, 4 }, EN 3 = { 1, 2, 3}, COM ={2,4}, and RED = {4}. To calculate all the multiconnections of the type P( { 1, 2},{2, 3}) for block 3, (5-48) and (5-49) are applied and the result becomes P 3 ( { 1, 2}, {2, 3}) = P t ( ( { 1, 2}, {2, 3} ) XP 2 ( { 1, 2}, {2, 3} ) )
u P t ( ( { 1, 2}, {2, 3} ) XP 2 ( { 1, 2}, {2, 3} ) ) u P 1 ( ( { 1, 2}, {2, 3} ) XP 2 ( { 1, 2}, {2, 3} ) )
(5-54)
u P 1 ( ( { 1, 2}, {2, 3} ) XP 2 ( { 1, 2}, {2, 3 } ) )
This middle block analysis shows how to get the multiconnections for the combination of two blocks given the multiconnections for each. The formula for finding the transfer function now can be applied from section 2.4.2. The actual implementation in
Figure 5.15 Middle block analysis.
130
Chapter 5
Hierarchical Symbolic Analysis of Large Analog Circuits
Ref. [2] automates the process a step further and uses the incidence matrix of the Coates graph in order to find the O-connections and l-connections of the combined blocks. Interested readers should refer to Ref. [2] for a comprehensive in-depth analysis of the algorithm.
5.5. COMPARISONS OF HIERARCHICAL METHODS Symbolic analysis has been performed on the bandpass filter of Fig. 5.16 using all three hierarchical methods discussed in this chapter [2], [3], [19]. This particular filter has been chosen because all three hierarchical methods showed detailed results of their analysis of
1.................-
...
.....--I~--.21
36
Figure 5.16 Bandpass filter.
Sec. 5.5
131
Comparisons of Hierarchical Methods
the filter. Figure 5.17 shows the partitionedblocks of the filter and their interconnection. It must be noted that for the Coates graph method, the partitioning is done on the graph level rather than on the circuit level and does not have the same correspondenceas with the other two methods. Figure 5.18 shows the graph and the hierarchicalmodel for the Coates graph method, and the block numbers are postfixed by the letter g to indicate that this is a graph partition rather than a circuit partition. The hierarchical models for the direct network method and the signal flowgraph method are shown in Figs. 5.19 and 5.20, respectively. The sequence of expressions produced by the Coates graph method [2] is shown in Table 5-3, the sequenceof expressionsproducedby the direct networkmethod [3] is shown in Table 5-4, and the sequence of expressions produced by the Mason signal flowgraph method [19] is shown in Table 5-5. The final output functions from each method are indicated at the top of each table. The comparison of the results from all three methods is shown in Table 5-1. Subparts A, B, and C in Fig. 5.20 were analyzed in section 5.4 (subpart A, which is a summer, is slightly different with an extra input terminal). For this example, the data in Table 5-1 show that the direct network approach produces expressions with fewer operations than the other two methods. The data also illustrate that circuit partitioningresults in a reduction in the number of operations produced. The second set of comparisons are between the direct network method and the Mason signal flowgraphmethod and illustratethe differencein performancefor twoclasses of circuit configurations.The circuits analyzedare shown in Figs. 5.13,5.17, and 5.21. The results show the methods to be comparable for circuits where the Mason signal flowgraph of a circuit has a one-to-one branch correspondence with circuit elements, namely, ideal op-amp circuits [4]. Table 5-2 shows that the direct network results are more efficient for cases where the branches in MASSAPdo not exhibit a one-to-onecorrespondence between circuit and flowgraph, which is usually the case. In general, the direct network approach seems to yield the best results, measured in terms of the number of operations produced, for a variety of circuit topologies. The methods are comparable for active filter circuits where ideal operational amplifiers are
BLOCKS
1,2,3aDd4
G.
Gl
BLOCK 5
Figure 5.17 Bandpass filter partitions and interconnection.
132
Chapter 5
Hierarchical Symbolic Analysis of Large Analog Circuits
Figure5.18 Coates graph method hierarchical model and graph representation for bandpass filter.
employed. It must be also noted that the quality of the results are highly dependent on the quality of the partitions used.
5.6. CONCLUSIONS This chapter illustrated the fundamentals of three hierarchical symbolic analysis algorithms for the goal of analyzing large-scale circuits. The idea is the reduction of the computational complexity of some of the basic symbolic analysis algorithms described in chapter 2. The best case speedup is on the order of p, where p is the number of circuits or graph partitions.
Sec. 5.6
Conclusions
133
Figure 5.19 Direct network method hierarchical model for bandpass filter.
Figure 5.20 Mason's signal flowgraph hierarchical model for bandpass filter.
Practically, however, the speedup will be less than p due to the overhead involved in partitioning and setup. The following general observations can be made about the hierarchical methods: 1. All three hierarchical methods use the concept of sequence of expressions to present the results of the analysis. The applications of these methods require postprocessing of the output sequence of expressions, symbolically or numerically, in order to interpret the results of the analysis. The methods do not use any approximation techniques and therefore accurately present the results of the analysis. These methods would not be suitable for designers needing a compact approximate expression for a transfer function for the purpose of interpreting the results of the analysis by direct inspection. Other symbolic
134
Chapter 5
Hierarchical Symbolic Analysis of Large Analog Circuits
Table 5-3 Sequence of Expressions Generated by the Coates Graph Method (VoutlVin= F(24)/F(25))
Block number
EN
EN;
ENo
Function number
9g
26,30
26
30
F(I)
G37(G3S+G40)
30
30
F(2)
G40(G37+G39)
30
26
F(3)
G29G32sC3S(G2S+G30)
26
26
F(4)
(G2S+G30)[G32G34G36+G31 sC3S(G33+sC33)]
19
26
F(5)
G2SG32sC3S(G29+G31 +G36)
26
19
F(6)
G20G23sC26(G19+G21)
19
19
F(7)
(G19+G21)[ G23G2SG27+G22sC26(G24+sC24)]
12
19
F(8)
G19G23sC26( G20+G22+G27)
19
12
F(9)
G11G14sC17(G10+G12)
12
12
F(10)
(G10+G12)[G14G16G1S+G13sC17(G1S+sClS)]
5
12
F(II)
GlOG 14sC 17(G11 +G13+G IS)
12
5
F(12)
G2GSsCS(G1+G3)
5
5
F(13)
(G1+G3)[GSG7G9+G4sCS(G6+sC6)]
1
5
F(14)
G 1GSsC8(G2+G4+G9)
26,30
30,30
F(15)
-F(3)F( 1)+F(4)F(2)
19,26
26,30
F(16)
-F(5)F(I)
19,30
26,30
F(17)
-F(5)F(2)
12,19
19,30
F(18)
F(8)F(16)
19,30
19,30
F(19)
F(7)F(15)-F(6)F( 17)
12,30
19,30
F(20)
-F(8)F(15)
5,12
12,30
F(21)
F(11)F(18)
12,30
12,30
F(22)
F(1O)F( 19)-F(9)F(20)
5,30
12,30
F(23)
-F(11)F(19)
1
30
F(24)
F(14)F(21)
30
30
F(25)
F(13)F(22)-F( 12)F(23)
8g
7g
6g
5g
4g
3g
2g
19
19,26,30
12,19,26
19,26,30
19,26,30
19,26,30
12,19,30
5,12,30
1,30
Weight function
135
Sec. 5.6 Conclusions Table 5·4 Sequence of Expressions Generated by the Direct Network Method (Vout/Vjn =-TO(32, 1)/TO(32, 30)) TERMINAL BLOCKS Block number
Symbolic function
5
P{l)
EN=
{26,30}
{19,26,30}
Pl(32)
(G 38+G40)/P( I )
P8(1)
(-G 1)1P(8)
Tl(32,26)
-PI (32)*(-G 37)
T8(1,1)
(G 1)-P8{l)*(-G 1)
P8(8)
(G 2+G4+G 9)/P(8)
T3(29,19)
1
T8(8,1)
(G29+G31+G36)1P(3) -P3(29)*(-G 28)
EN=
{1,5,12}
P8(4)
-P8(8)*(-G 1) (-G S)/(-G4)
(-G 32)/(-G 31)
T8(4,1)
-P8(4)*T8(8, I)
T3(25,30)
-P3(25)*(-G 29)
T8(4,12)
-P8(4)*(-G 2)
T3(25,19)
-P3(25)*T3(29,19)
T8(4,7)
-P8(4)*(-G9 )
T3(25,28)
-P3(25)*(-G 36)
P8(4)
T8(4,7)/(-sC 8)
P(5)
P5(22) T5(22,12)
EN=
G 28+G30
P3(25)
T3(25,26)
{12,19,26}
Symbolic expression
G)+G 3
P3(25)
3
Symbolic function P(8)
P3(29)
EN=
Block number
G 37+G39
P(3)
4
Symbolic expression
TERMINAL BLOCKS
P5(18) T5(18,12)
T3(25 ,28)/(-sC 3S)
T8(4,5)
MIDDLE BLOCKS
(-G33-sC33)-P3(25)*(-G34) G)9+ G21
(G20+G22+G27)1P(5) -P5(22)*(-G 19)
-G 6-sC6-P8(4)*(-G7)
Block number
Symbolic function
Symbolic expression
P6(11)
T7( II ,5)rr8(4,5)
T6{l1,1)
-P6(11)*T8(4,1)
T6(11,12)
T7( II, 12)-P6( II )*T8(4, 12)
6
EN=
{1,12,19}
(-G 23)/(-G22) -P5( 18)*T5(22, 12)
P4(18)
T5(18,12)rr6(11,12)
7
T5(18,26)
-P5( 18)*(-G 20)
T5(18,2l)
-P5( 18)*(-G 27)
P5(18) T508,19) P(7) P7(15)
T5( 18,21 )/(-SC 26) (-G 24-sC24)-P5( 18)*(-G 25)
EN=
( 1,19,26}
T4(18,l)
-P4(18)*T6(11,1)
T408,19)
T5( 18,19)-P4( 18)*T7( 11,19)
P2(25)
T3(25, 19)rr4( 18,19)
8
EN=
(1,26,30}
G 1O+G)2
T2(25,l)
-P2(25)*T4( 18, I)
T2(25,26)
T3(25,26)-P2(25)*T5( 18,26)
PO(32)
(G II+G 13+G IR)/P(7)
TI (32,26 )rr2(25,26)
9
2
T705,5)
EN=
EN= ( 1,30}
P7{ll) (5,12,19}
-P7(15)*(-G 10) (-G 14)/(-G 13)
T7(11,5)
-P7(1l)*T7(15,5)
T7(11,19)
-P7(1l)*(-G 11)
T7{l1,14)
-P7(1l)*(-G 1R)
P7(1l) T7(11,12)
T7(l 1,14)/(-sC 17) -GIS-sCIS-P7(11)*(-GI6)
TO(32,1)
-PO(32)*T2(25, I)
TO(32,30)
-G4()-PO(32)*T3(25,30)
136
Chapter 5
Hierarchical Symbolic Analysis of Large Analog Circuits
Table 5·5 Sequence of Expression Generated by the Mason Flowgraph Method (VoulVin = H9(1,30)) Block number
New symbol
Value of new symbol
HI(I,3)
(G I(G2+G4»/(G4(GI+G3»
H1(12,3)
-(G 2)/(G4)
Hl'(7,3)
-(G 9)/(G4)
HI(3,5)
-(G S)/(G6+sC6)
HI(5,7)
-(G7)/(sC~)
Reduce node 7
HI(5,3)
HI (5,7)*H1(7,3)
Reduce node 3
HI(l2,5)
HI (12,3)*H I(3,5)
HI(I,5)
Hl(l,3)*HI(3,5)
HI(5,5)
HI (5,3)*H I(3,5)
H1(12,5)
H I( 12,5)/(I-H 1(5,5»
HI(I,5)
HI (1,5)/( I-H I(5,5»
H2(5,IO)
(G Io(Gil +G (3))/(G13(G Io+G(2»
H2(19,IO)
-(G ll)/(G 13)
H2(14,10)
-(GI~)/(G13)
H2(10,12)
-(G I4)/(G IS+sC 1S)
H2(12,14)
-(G (6)/(sC17)
Reduce node 14
HI(l2,10)
HI(12,14)*Hl( 14,10)
Reduce node 10
HI(l9,12)
HI( 19,10)*HI( 10,12)
HI(5,12)
H1(5,1 O)*H 1(10,12)
HI(l2,12)
Hl( 12,IO)*HI( 10,12)
HI(l9,12)
HI( 19,12)/(I-Hl(12,12»
HI(5,12)
HI(5,12)/( I-HI( 12,12»
H3(12,17)
(GI9(G20+G22»/(G22(GI9+G21»
H3(26,17)
-(G 20)/(G22)
H3(21,17)
-(G 27)/(G22)
H3(17,19)
-(G23)/(G24+sC24)
H3(19,21)
-(G 2S)/(sC26)
Reduce node 21
HI(19,17)
HI( 19,21)*HI(21,17)
Reduce node 17
HI(26,19)
HI (26, 17)*HI( 17,19)
H1(12,19)
H1(12,17)*H1(17,19)
Hl(19,19)
H1(19,17)*HI( 17,19)
Terminal Block I
Reduce self-loop at node 5
Terminal Block 2
Reduce self-loop at node 12
Terminal Block 3
Sec. 5.6
137
Conclusions
Table 5·5 Continued Block number
New symbol
Value of new symbol
Reduce self-loop at node 19
HI(26,19)
H1(26,19)/(I-H I( 19,19»
HI(l2,19)
HI(12,19)/( I-HI( 19,19»
H4(l9,24)
(G2X(G29+G31»/(G31(G2X+G30»
H4(30,24)
-(G 29)/(G31)
H4(28,24)
-(G 36)/(G31)
H4(24,26)
-(G32)/ ( G33+sC33)
H4(26,28)
-(G 34)/(sC35)
Reduce node 28
HI(26,24)
HI (26,28)*HI(28,24)
Reduce node 24
HI(30,26)
HI (30,24)*HI(24,26)
HI(l9,26)
HI (19,24)*HI(24,26)
HI(26,26)
HI (26,24)*HI(24,26)
HI(30,26)
HI (30,26)/(I-H I(26,26»
HI(l9,26)
HI( 19,26)/(I-H 1(26,26»
H5(26,30)
(G37(G3X+G40»/(G40(G37+G39»
H6(l,12)
HI (I ,5)*H2(5,12)
H6(l2,12)
HI (12,5)*H2(5,12)
H6(l,12)
H6(I, 12)/(I-H6( 12,12»
H6(l9,12)
H2(19,12)/(I-H6(12,12»
H7(l,19)
H6(I, 12)*H3(12,19)
H7(19,19)
H6(19,12)*H3(12,19)
H7(1,19)
H7(1,19)/(I-H7(19,19»
H7(26,19)
H3(26,19)/(I-H7( 19,19»
H8(1,26)
H7(I, 19)*H4(19,26)
H8(26,26)
H7(30,26)*H4(19,26)
H8(l,26)
H8(I,26)/(l-H8(26,26»
H8(30,26)
H4(30,26)/(I-H8(26,26»
H9(1,30)
H8(1,26)*H5(26,30)
H9(30,30)
H8(30,26)*H5(26,30)
H9(1,30)
H9(I,30)/(l-H9(30,30»
Terminal Block 4
Reduce self-loop at node 26
Terminal Block 5
Middle Block 6
Middle Block 7
Middle Block 8
Middle Block 9 (final)
138
Chapter 5
Hierarchical Symbolic Analysis of Large Analog Circuits
3
1
•
Number of Networknodes =n + I Number of SFG branches = 2n
SCI V
Y
...
RI
sC2
X_X_J·· I CI
:
-sC I
V2
:
Ie
•
I~
-R 1
~Vn+l -SCn
Number of SFG nodes =2n + I Number of SFG branches =2b - I =4n - I Figure 5.21 Ladder circuit and its signal flowgraph model.
algorithms that use approximation techniques are more suitable in these cases and are illustrated in chapter 6. 2. The number of operations and expressions resulting are comparable for all three methods. The use of a sequence of expressions reduces the number of symbolic expressions generated to a polynomial rate rather than the exponential rate that the traditional single expression methods produce (see chapter 2). However, as previously mentioned and to be illustrated in chapter 6, approximation techniques have also managed to drastically reduce the number of symbolic analysis expressions generated. The use of circuit level hierarchy (partitioning), which reduces the overall complexity of the analysis algorithm, further reduces the number of operations produced. 3. All three methods facilitate the building of standard symbolic solution libraries for commonly used cells. This would eliminate the need for the repeated analysis of such cells. Even within one circuit, as soon as a subcircuit that is instantiated more than once is analyzed, no further analysis of the other instances is required. The Coates graph method, however, needs some further work in order to define some interconnection rules between preanalyzed subcircuits. 4. All three methods have the ability to include any current or voltage variable as part of the analysis without any extra or special considerations. However, the Mason signal flowgraph approach has the potential ability to simulate integrated systems; that is, systems with electrical and nonelectrical components. The only requirements on the components of the system is that they be representable in flowgraph format. Mechanical and chemical systems are commonly represented by a Mason flowgraph, and interconnections of such components with electrical circuits can be simulated using the method herein.
139
References
5. The sequence of expressions for the direct network method and the Mason signal flowgraph method feature the existence of division in their expressions, while the Coates graph method does not. The existence of division reduces underflow and overflow problems at expression evaluation time. The Coates graph-generated expressions show a need for normalization during the numerical evaluation process in order to eliminate such problems. 6. The number of terms in the Mason signal flowgraph analysis of active circuits is lower than that for general circuits due to the one-to-one correspondence between the actual circuit nodes and the nodes of its flowgraph model [4]. 7. The use of symbolic solutions facilitates the use of noniterative hierarchical procedures for combining partition solutions into an overall system solution. This application is ideally suited for implementation on parallel processor machines [19].
References [1] P. M. Lin, Symbolic Network Analysis. Amsterdam: Elsevier Science, 1991. [2] J. A. Starzyk and A. Konczykowska, "Flowgraph analysis of large electronic networks," IEEE Trans. Circuits Syst., vol. CAS-33, pp. 302-315, March 1986. [3] M. M. Hassoun and P. M. Lin, "A new network approach to symbolic simulation of large-scale networks," Proc. 1989 IEEE Int. Symp. Circuits Syst., Portland, pp. 806-809, May 1989. [4] M. Hassoun and K. McCarville, "Symbolic analysis of large-scale networks using a hierarchical signal flowgraph approach," Analog Integrated Circuits and Signal Processing, vol. 3, no. 1, pp. 31-42, January 1993. [5] A. Konczykowska and J. A. Starzyk, "Computer justification of upward topological analysis of signal-flow graphs," Proc. European Conf. Circuit Theory Design, pp.464-467, 1981. [6] A. V. Aho et aI., The Design and Analysis of Computer Algorithms. Reading, MA: Addison-Wesley, 1974. [7] M. M. Hassoun and P. M. Lin, *"A hierarchical network approach to symbolic analysis of large-scale networks," IEEE Trans Circuits and Syst. I, March 1995. [8] B. W. Kernighan and S. Lin, "An efficient hueristic procedure for partitioning graphs," Bell Syst. Tech. J., 49, pp. 291-307, 1970. [9] A. S. Vincentelli, L. K. Chen, and L. O. Chua, "An efficient heuristic cluster algorithm for tearing large scale networks," IEEE Trans. Circuits Syst., vol. CAS-24, pp. 709-717, 1977. [10] C. S. Park and S. B. Park, "A network partitioning algorithm using the concept of connection index," Proc.IEEE Int. Symp. Circuits Syst., Rome, pp. 985-987,1982. [11] J. Rutkowski, "Heuristic network partitioning algorithm using the concept of loop index," lEE Proc., vol. 131, pp. 203-208, October 1984. [12] M. M. Hassoun and P. M. Lin, "An efficient partitioning algorithm for large-scale circuits," Proc. IEEE Int. Symp. Circuits Syst., New Orleans, pp. 2405-2408, May 1990. [13] C. E. Endy and P. M. Lin, "A minimization problem in systems characterized by acyclic signal flow graphs," IEEE Transa. Circuits Syst., vol. CAS-28, pp. 768-780, August 1981.
140
Chapter 5
Hierarchical Symbolic Analysis of Large Analog Circuits
[14] P. M. Lin, "A survey of applications of symbolic network functions," IEEE Trans. Circuit Theory, vol. CT-20, pp. 732-737, November 1973. [15] P. Wambacq, G. Gielen, and W. Sansen, "A cancellation free algorithm for the symbolic simulation of large analog circuits," Proc. IEEE Int. Symp. Circuits Syst., San Diego, CA, pp. 1157-1160, May 1992. [16] F. V. Fernandez, J. Martin, A. Rodriguez-Vazquez, and J. L. Huertas, "On simplification techniques for symbolic analysis of analog integrated circuits," Proc. IEEE Int. Symp. Circuits Syst., San Diego, CA, pp. 1149-1152, May 1992. [17] S. Seda, M. Degrauwe, and W. Fichtner, "Lazy-expansion symbolic expression approximation in SYNAP," Proc. 1992 Int. Con! Computer-Aided Design, Santa Clara, CA, pp. 310-317,1992. [18] Q. Yu and C. Sechen, "Efficient approximation of symbolic network function using matroid intersection algorithms," Proc. IEEE Int. Symp. Circuits Syst., Seattle, WA, May 1995. [19] M. Hassoun and P. Atawale, "Hierarchical symbolic circuit analysis of large-scale networks on multi-processor systems," Proc. 1993 IEEE Int. Symp. Circuits Syst., Chicago, pp. 1651-1654, May 1993. [20] T. Matsumoto, T. Sakabe, and K. Tsuji, "On parallel symbolic analysis of large networks and systems," Proc. IEEE Int. Symp. Circuits Syst., Chicago, pp. 1647-1650, May 1993. [21] E. Wehrhahn, "Symbolic analysis on parallel computers," Proc. European Con! Circuit Theory Design, Davos, Switzerland, pp. 1693-1698, 1993. [22] C. L. Coates, "Flow graph solutions of linear algebraic equations," IRE Trans. Circuit Theory, vol. CT-6, pp. 170-187, 1959. [23] S. J. Mason, "Feedback theory-Further properties of signal flow graphs," Proc. IRE, vol. 44, pp. 920-926, July 1956. [24] C. Ho, A. E. Ruehli, and P. A. Brennan, "The modified nodal approach to network analysis," IEEE Trans. Circuits Syst., vol. CAS-25, pp. 504-509, June 1975. [25] W.-K. Chen, Passive and Active Filters Theory and Implementations. New York: John Wiley, 1986. [26] W.-K. Chen, Applied Graph Theory-Graphs and Networks. Amsterdam: North Holland, 1976.
6 Francisco V. Fernandez Angel Rodriguez-Vazquez IMSE-CNM Sevilla, Spain
Symbolic Formula Approximation
6.1. A RATIONALE FOR EXPRESSION APPROXIMATION Experience with symbolic analyzers shows that the expression complexity grows exponentially with the circuit size, especially for circuits described at the device level, obtaining extremely complex formulas even for simple building blocks. This may seriously compromise the practical use of these tools due to the difficulties of handling large symbolic formulas. However, a deeper study of the symbolic expressions resulting for practical circuits shows that only a few terms contain the majority of relevant information, The remainder only hinders getting insight on circuit operation, and makes computational manipulation of the expressions more expensive or even impossible. Hence, one may wonder why to keep those terms whose contribution is insignificant. To illustrate the convenience of formula simplification, consider the two-stage BJT feedback amplifier in Fig. 6.ta, whose small-signal model is shown in Fig. 6.tb. The following exact expression is obtained for the voltage gain, v () v. I
[gml gm2'1tl'1t2 R3 RL Rl +gml'1tl (R 2+RL) (R 3 +'1t2)R 1 +
(6-1)
(R 2+RL) (R 3+'1t2) (R 1 +'1tl) + (R 3+'1t2)'1tl RI]
Although this formula gives precise information about the circuit behavior and is obviously necessary for fine gain adjustment, it is rather cumbersome from a more qualitative point of view, darkening Fig. 6.1 's operation as a feedback amplifier. Assume that symbolic parameters are assigned the typical values indicated along with Fig. 6.1. The
141
142
Chapter 6
Symbolic Formula Approximation
v· I
(a) v·I
+
+
'xl = 'x2 = 10KQ gml = gm2 = O.Olmhos
R2
= R3 = RL = 10KQ
R I = lKQ (b) Figure 6.1 (a) BJT feedback amplifier; (b) amplifier ac model.
first addend in the numerator amounts to 99.82% of the total numerator magnitude and the first addend in the denominator, 95.7%. If these errors are acceptable, the remaining terms may be neglected and (6-1) reduces to (6-2) which displays the feedback effect much more clearly than (6-1) and provides guidelines for coarse voltage adjustment. To ease formula interpretation is one of the motives for simplification. Another motive is the use of symbolic formulas in applications involving repetitive evaluations, such as automated circuit sizing using statistical optimization [1], Monte Carlo simulation, testability analysis, design centering, etc. All these applications require a previous compilation of the formulas describing the circuit behavior, for instance, in the form of executable C code. A large expression size may represent an overload of the compilers. For instance, let us assume a noncomplex CMOS building block, such as the Miller operational transconductance amplifier (OT A) of Fig. 6.2a. Using the transistor model of Fig. 6.2b, the formula representing the voltage gain of this op-amp contains 8616 different terms [2]. A similar number of terms is obtained for other specs that must be taken into account in the design procedure, e.g., CMRR (common mode rejection ratio), PSRR (power supply rejection ratio), noise, input capacitance, etc. A much larger number of terms will result for advanced CMOS or BJT op-amp building blocks, typically containing about 30 transistors. Trying to create models including all the characteristics needed for the ac design of these
Sec. 6.1
143
A Rationale for Expression Approximation
(a)
B S
(b) Figure 6.2 (a) Miller OTA; (b) high-frequency MOS transistor model.
building blocks, and using exact symbolic expressions, will probably be beyond the capabilities of many compilers. In particular, Table 6-1 shows the compilation time versus the formula complexity for different simplified expressions of the voltage gain of the Miller OTA. We can see that the compilation time grows linearly with the number of terms and the compiler crashes when it tries to compile the exact expression. Even if compilation is possible, the formula must be evaluated repeatedly. Obviously, the computation time Table 6-1 Compilation Time for Different Simplified Expressions
Number oftenns
Compilation time
89
1.5 s
140
2.2 s
235
3.1 s
353
4.4 s
835
12.3 s
1568
32.9 s
8616
compiler error
144
Chapter 6
Symbolic Formula Approximation
required for the iterative design procedure grows linearly with the number of arithmetic operations involved in the symbolic expression, or, what is the same, with its size.. These practical problems motivate the introduction of simplifications, intuitively defined as a reduction of expression complexity while maintaining the accuracy as high as possible.
6.2. THE CONCEPT OF SYMBOLIC FORMULA APPROXIMATION Approximating a reference function, defined analytically or as a set of data points, implies calculating an approximating function, typically made up of elementary functions with a predefined structure (piecewise-linear, polynomial, spline, etc.), that fits the target for a given error inside a region of the variable's space [3]. However, this numerical approximation concept is not applicable to a function such as (6-1). First, because the coefficients are symbols, there is no numerical information available to perform the fitting, nor a general mathematical theory to approximate symbolic functions. Second, because the function structure is already known and easily computable, there is no reason to look for an alternative function structure. There usually are large differences among the numerical values of the symbols encountered in electrical circuits, particularly in circuits containing semiconductor devices. For instance, the transconductance gm of a MOS transistor is typically more than 1 order of magnitude larger than the output conductance gds. Similarly, load or compensation capacitors are much larger than parasitic capacitances. This suggests the construction of simplified expressions using those pieces of the original expression that contain the most significant terms. Such approximation of generic symbolic formulas proceeds as previously illustrated for the example of Fig. 6.1. Symbolic expression approximation (or simplification) is hence defined as the reduction of formula complexity by eliminating insignificant terms or subexpressions, determined by numerical estimates of the symbolic parameters. I It aims not to change the function structure, but rather to reduce the number of symbolic terms included in the symbolic expression [2], [4]. This is common practice among expert analog designers, and symbolic tools only try to emulate their working procedures. Based on this approximation concept, we demand the following requirements of potential simplification criteria. 1. Maximum error in simplified formulas should be user-controlled. Ideally, the user should directly control magnitude and phase errors and/or pole/zero errors, that is, the network performance. 2. As shown in the previous example, simplificationdepends on the typical values of the symbolic parameters. Hence, estimates of such values should allow user interaction. 3. Simplificationalso depends on the frequency. It should be possible to perform the simplification procedure over the whole frequency range, a bound range, or a single frequency value. 1 Insignificant terms
are eliminated based on their relative insignificance; hence, the relative, rather than absolute, values of the symbolic parameters are important.
Sec. 6.2
145
The Concept of Symbolic Formula Approximation
There are many reported simplification techniques and different criteria can be used to classify them. Considering the step of the analysis procedure at which the simplification algorithm is applied, they can be classified as follows.
• Approximation-after-generation techniques. The simplification algorithm is applied once the symbolic analysis of the input circuit has been performed and the complete expression has been generated. The simplified symbolic expression is then constructed from pieces of the complete one.
• Approximation-during-generation techniques. The simplification is applied at the same time that the circuit is analyzed, while the symbolic results are being generated. These techniques, of recent appearance, do not generate the complete expression first and, hence, are very adequate when the circuit size renders the generation of such expression impossible.
• Approximation before generation techniques. The simplification is performed at a circuit level or its matrix or graph description, prior to the generation of any symbolic result. Obviously, these can be combined with any of the others. They can also be classified depending on the format of the expression being simplified. These different formats were already presented in chapter 1.
• Expanded format expressions; i.e., H(s,x)
=
-gmI gds2 gdsI gds2
+ sC Ig ds2 + sC Ig m2
+ gm2 gds3 + gmb2 gds3 + gds2 gds3 + sC Igds3
(6-3)
• Nested format expressions; i.e.,
H (s, x)
- (gmi - sCI) gds2
+ gmI gm2
=-----------gds2 + gds3 (gm2 + gmb2 + sCI + gds2)
gdsI
(6-4)
which corresponds to the same expression in (6-3). There, the nesting consists of grouping some common factors. As presented in chapter 1, the nesting can also consist of a sequence of expressions (SOE) format, in which each subexpression is assigned a new variable name. For instance, HII
= ky+ 1
H I 2=k+l H I3
= l+a
H(s,x)
=
s H I 4 = l+GB.E H2I
= H I 2H I 3
H3 I = H2 I +ky
HI 2
which refers to the voltage gain of Fig. 1.11a in chapter 1.
(6-5)
146
Chapter 6
Symbolic Formula Approximation
Assuming that equal subexpressions share the same variable name, they are more compact than nested format expressions, as in (6-4). Therefore, memory consumption is reduced and they are more efficient to evaluate. We must also distinguish, for simplification purposes, between flat and hierarchical analysis. In flat analysis, the circuit is analyzed as a whole. In hierarchical analysis, the circuit is partitioned into subblocks, each part is analyzed separately, and the final result is obtained by somehow joining the results of the constituent parts. This analysis is adequate for large circuit analysis, and inherently provides nested format expressions. Flat analysis techniques may lead to either expanded format or nested format expressions, depending on the particular analysis technique used. Sections 6.3 and 6.4 deal with approximation-after-generation techniques, separately studying algorithms for expanded format expressions and nested format expressions, respectively. Emerging techniques for approximation-during-generation are introduced in section 6.5 and for approximation-before-generation in section 6.6.
6.3. SIMPLIFICATION OF EXPANDED FORMAT EXPRESSIONS As presented in chapter 1, an expanded format expression has the general form N
H(s,x)
=
2
N
')
M
fo(x) +sfl (x) +s!2(x) + ... +s fN(x)
I, /1; (x) =
i =0
M
go (x) +sgl(x) +s-g2(x) + ... +s gM(x)
(6-6)
I,!gj(x) j=o
where the coefficients of s powers are sums of products of the symbolic parameters x
T
=
{XI' x 2' ... , x Q } .
Generically, either t, (x) or
gj (x)
in (6-6) can be written as T
h k (x) = h k1 (x) + "n (x) + ... + hkT(x) ==
I, hk l (x)
(6-7)
I= I
where hkl (x) represents a product of symbols. Simplification criteria typically found in the literature assume that the complex frequency remains a symbol during simplification. This infers that simplification applies to the whole frequency range. The simplification itself is performed through the heuristic pruning of insignificant terms in each coefficient hk (x) 2 in (6-6) so that an approximate polynomial, hkA (x), is found for each coefficient. This approximate polynomial fits the original one for a user-specified maximum error parameter EM and inside a given region R of the symbolic parameter space:
2 h (x) k
comprises either Ii (x) org j
(x) •
Sec. 6.3
Simplification of Expanded Format Expressions
147
(6-8)
Most tools perform this fitting only at a single point of the parameter space x; called the nominal or design point [2], [5]-[7]. The approximation techniques found in the literature do not report large differences in computational efficiency. On the other hand, because approximation time is typically orders of magnitude smaller than analysis time, our primary comparison criterion will be accuracy rather than analysis time. Simplification techniques will be compared with regard to their performance at the nominal point r., as well as at other points of the parameter space located around x o ' This latter situation deserves consideration because the design point in symbolic analysis is not usually known beforehand, and its value is defined as a heuristic guess. Furthermore, even in those applications in which a nominal design point is known a priori, in practice, the actual design point may be largely different due to the influence of unavoidable device mismatches. This has led to the introduction of new approaches, capable of considering wide parameter ranges instead of single numerical. values. Detailed descriptions of these approaches are presented in this section.
6.3.1. Nominal Value Approaches CRITERION 1 The simplest simplification criterion looks for the largest magnitude term for each coefficient hk (x o ) ; multiplying it by a given maximum-allowed error EM (normally userspecified) defines a discrimination threshold. Then, all the terms are taken one by one and those whose magnitude is below the calculated threshold are eliminated. In other words, a term hk l (x) will be eliminated from (6-7) if it fulfills the following:
Ih kl (x o ) 1< EM . max (Ih k I (x o ) I, Ih k2 (x 0) I, ..., Ih k T (x o ) \)
(6-9)
This criterion has been used in SSPICE [7]. Its main drawback is the lack of control of the accumulated error for each coefficient-the accumulated value of the deleted terms can represent either a small or large part of the total magnitude of each coefficient. Consequently, coefficient errors will probably be quite different for different coefficients, and large magnitude and phase errors and large pole/zero displacements can be expected.
CRITERION 2 More involved criteria require previous sorting of terms in hk (x) according to their magnitude at the nominal point x o .3 One possibility is to eliminate the P smallest magnitude terms, P being the largest integer for which the accumulated error is below EM [2], [4]:
must be noted that term-sorting represents an extra CPU time consumption compared to previous criterion.
3 It
148
Chapter 6
Symbolic Formula Approximation
p
L hk/(x) 1= 1 T
L hk/(x)
<EM
(6-10)
1= 1
Efficiency can be somewhat improved by eliminating all those terms h k l (x 0) whose magnitude is below the fraction EM of the coefficient mean value, (6-11) prior to performing the term-sorting [5]. This simple operation deducts a significant number of terms, thus reducing the number of terms to sort. Note that mutually canceling terms do not contribute to (6-10) because they are added with their respective signs. However, such terms may become significant when the simplified formula is evaluated at points other than x o' Hence, although this criterion gives very accurate results at x o' the resulting error at other points may be well beyond EM' This happens, for instance, when mismatches among nominally matched devices are taken into account." Such mismatches have a strong influence on characteristics that rely largely on cancellations, such as CMRR and PSRR. In these cases, large insight is gained if explicit mismatch parameters are introduced. Consider for illustration purposes the calculation of the positive PSRR of the Miller OTA of Fig. 6.3a using the MOST model of Fig. 6.3c. Differences between exact and simplified magnitudes and phases, for different EM' are plotted in Fig. 6.4a and b for a mismatch of 1% among MaS transistors. However, the maximum magnitude and phase deviations for matched transistors are 1.1 dB at 100kHz and -5.1 0 at 2.8 MHz, in both cases for EM = 0.2. As shown, much larger inaccuracies appear when the formula calculated at the nominal point is applied to points located nearby. It is important to note that such problematic examples do not usually occur. However, good reliability of the results requires improved algorithms capable of solving such problems.
CRITERION 3 One solution to avoid elimination of mutually canceling terms is to modify (6-10) as follows: p
L Ihk/(xo)1 I
=I T
L Ihk/(x)!
<EM
(6-12)
1= I
4
Nominally, all the transistors have identical technology-dependent parameters (threshold voltage, oxide thickness, mobility, etc.). However, statistical variations in fabrication processes always introduce deviations or mismatches between nominally identical parameters.
Sec. 6.3
149
Simplification of Expanded Format Expressions
(b)
(a)
B
(c) Figure 6.3 Benchmark circuits of simplification criteria for expanded format expressions: (a) Miller OTA; (b) active CMOS current mirror; (c) highfrequency MOS transistor model.
Neglected terms that are of the same order of magnitude as the last one remaining in the simplified expression should be recovered and kept in this expression [5]. Criteria 2 and 3 yield identical results if all the terms of each coefficient hk (x) have the same sign at x(} and providing that this sign remains the same inside the region considered. However, this can only be assured for passive RLC circuits and, consequently, different results can be expected for each criterion for general active circuits. Criterion 3 is less accurate at the nominal point than the previous; however, the likelihood of additional inaccuracies due to displacements around x(} is smaller. Actually, this criterion is the most commonly used in modern symbolic analyzers [2], [4]. Unfortunately, there are some circuits where its use may yield large errors, as shown in the following. CRITERIA WITH VARIABLE ERROR CONTROL PARAMETER
In all previous criteria, if the same error cM were exactly obtained for all numerator and denominator coefficients in (6-6), the simplified expression would become N
H(s,x)
=
(l-cM)!o(x) +s(l-cM)!1 (x) + ... +s (l-cM)!N(x) (l-cM)go(x) +s(l-cM)gl(x) + ... +s
M
(6-13)
(l-cM)gM(x)
where there is no change in magnitude or phase and neither zero nor pole displacement. However, expression pruning is a discrete process and, hence, the actual errors are different for each coefficient:
150
Chapter 6
,
6.0
,
t M= 0.05
\
co 2. 4.0
Symbolic Formula Approximation
\
\
t M= 0. 10
\
c
\
o
\
tM= 0.20
,,
\
.'§ 2.0 >
<:J
-0
<:J
0.0
--
f---+---+---::::=="--o-------=*=::::::--~
-0
:l
."§ -2.0 OJ) :;l
:::E -4.0 102
104
Frequency (Hz)
106
(a)
0 -;0 -30 <:J
2. c 0
I
-60
/ I
~
I
-0
------
/
~-120 :;l
I
t M= 0.10 tM= 0.20
/
- 150 - 180
t M= 0.05
I
> -90
<:J
..c 0.
11
- - -~-
/.
10°
102
104
Freque ncy (Hz)
106
108
(b) Figure 6.4 Mismatch-induced parametric error profiles for the PSRR of the Miller OTA: (a) deviations in magnitude for different t M; (b) corresponding phase deviations . N
H ( s, x )
=
( I-EO/)!O(x) +s( I- E1n)!j (x) + ... + s ( I- ENn)!N( x) M
(6-14)
( I - EOd)gO(x) + S(I- El d) g l (x ) + .. . + s (I-EMd)gM( x)
Th is may lead to significa nt root displace me nts in circui ts whe re the roots are very sensitive to coefficie nt variations. Such a situation is more likely to happen for criterion 3, particul arly if the expressio ns co ntain coefficie nts with diffe rent signs. Consider, for instance, the current gain of the active current-mirror of Fig. 6.3b [8]. Assume that the MOS transistors are represented by the model of Fig. 6.3c and that the amplifier is represented by a voltage-controlled voltage source (VCVS). Figure 6.5a and b show the loci for the real and imaginary parts of the three poles, as calc ulated by ASAP [2], as a function of EM' As show n, there is a pair of complex co njugate poles in the left half of the
Sec. 6.3
151
Simplification of Expanded Format Expressions
PI Pz
------------ -- ----J r------ -- ----- ------1
0.4
j'
-,
I
0.3 ~
(J
w 0.2 s:
0.1
r -- - - ------ --- - ---~--
I I
- 106
o
Re(s) (a)
0.4 0.3 ~
w 0.2 0.1 0.0
L.....-~""""--.....l.._~__'____L.__'"___'~L_~~....I__'__~__'_:_'-~
o
_ 109
Im (s)
(b) Figure 6.5 Pole loci for the current gain of the active current mirror as a function of EM (a) real parts; (b) imaginary parts of the roots.
s-plane for some values of EM, and in the right half for others. Thus, the circuit may be considered either stable or unstable, depending on the formula used. It is obvious that this type of qualitative error is intolerable for practical use . Different solutions have been proposed to overcome these problems. A trivial strategy adds a numerical fitting factor to each simplified coefficient such that the relative magnitudes of the pruned terms at the nominal point are equalized. This approach has been implemented in different symbolic analyzers and guarantees accuracy at the nominal point, but it does not imply any improvement for points other than nominal. Another possibility is to monitor the magnitude of each term within each hk (x) in (6-6) , to avoid eliminating those whose magnitude is greater than the denominator in (6-12) [4] . Another approach is to use an adaptive EM scheme: term-pruning is performed step by step and the pole/zero displacements are monitored at each step so that simplifications can be stopped when such displacements are beyond a user-specified safety margin [2]. Unfortunately, even though this guarantees a low error at the nominal point, it does not ensure good results for different points of the parameter space. All preceding criteria have assumed that the frequency remains a symbol. If the system function has to be approximated for a single value of the frequency h" then it must be evaluated for s j2rch,. The problem then reduces to approximating the real and imaginary parts of numerator and denominator and, hence, conceptually is no different than
=
152
Chapter 6
Symbolic Formula Approximation
the approximation of individual coefficients of the network function. Expression approximation for a bound frequency range using a nominal value approach is not easy. One possibility is to perform the approximation for different frequency points within the given range and include in the final expression every term that is present at least in the simplified expression at one frequency point. Full accuracy is not guaranteed with this approach. Increasing the number of sample frequency points diminishes the likelihood of errors but also diminishes the speed of the algorithm.
6.3.2. Variation Range Approach The inaccuracies shown in section 6.3.1 have motivated the development of advanced simplification strategies whose accuracy is less sensitive to the evaluation point. This is also based on the fact that, unlike numerical simulators, where sized schematics are analyzed, symbolic analyzers focus on totally or partially unsized circuits. That is, in symbolic analysis the exact numerical value of some or all the parameters is not known beforehand. Hence, approximating symbolic expressions by considering only a single point of the parameter space does not seem consistent with the very nature of symbolic analysis procedure. Even when symbolic analysis is used to study critical parameter variations in sized schematics, simplification using only information about the nominal point may lead to important inaccuracies, as previously shown in Fig. 6.4 for the PSRR of the Miller OTA. Parameter variations in practical circuits are usually restricted to bounded regions of the parameter space. One possibility to extend the validity range of the simplified expressions is the repetitive application of any previous criteria to each point (a sufficiently fine grid should be defined) inside the bounded region. However, because dimensions of the parameter spaces of practical circuits are usually very large, this approach is computationally intractable in practice. The algorithm in Ref. [9] solves this problem by assigning a variation range to each symbolic parameter; simplifications are achieved by performing operations among the parameter ranges. Before describing the simplification procedure, we will briefly describe the range concept and some operators between ranges. This is covered in detail in any basic book on interval analysis [10], [11].
6.3.2.1. Range Concept and Basic Operators This approach assumes that symbolic parameters may take any value within a given variation range: (6-15) where YiL and YiH are real numbers and YiL ~YiH·6 Therefore, products of symbols or sums of products also have an associated variation range. The basic operations between ranges used in the approximation of symbolic expressions are detailed in the following.
5 An analog schematic is said to be
sized when a numerical value has been assigned to each circuit
element and model parameter. 6
These may either correspond to primitive components of the small-signal circuits (transconductances, capacitances, resistances, etc.), to more basic symbols (bias currents, etc.), or to algebraic combinations of symbols.
Sec. 6.3
Simplification of Expanded Format Expressions
153
• Product of ranges. Given the multiplication of two symbolic factors, Yi and Yj' the extrema (y iYj)L and (y iYj)H of the range of the product can be calculated from the extrema of the factors as follows:
(YiYj)L = min (YiLYjL' YiLYjH' YiHYjL' YiHYjH) (YiYj)H
= max (YiLYjL' YjLYjH' YjHYjL' YjHYjH)
(6-16)
This computation can be done more efficiently taking into account the sign of the range extrema:
YiL ~ 0, YjL ~ 0
y,y, I }
[(Y'LY'L)' (Y'HY'H)] I} I}
E
YiL ~ 0, YjH s 0
YjYj E [(YiHYjL) ' (YjLYjH)]
YiH s 0, YjL ~ 0
y,y, I }
YiH s 0, YjH s 0
YjYj E [(YiHYjH) ' (YjLYjL)]
E
[(Y'LY'H)' (Y'HY'L)] I} I}
YiL < 0 < YjH' YjL ~ 0
YiYj E [(YiLYjH) ' (YjHYjH)]
YiL
YjYj E [(YiHYjL) ' (YjLYjL)]
YjL ~ 0, YjL < 0 < YjH
'HY·L) ,(yI 'HY'H) ] Y I,y,} E [(y I } }
YiH s 0, YjL < 0 < YjH
YiYj E [(YiLYjH) ' (YiLYjL)]
YiL < 0 < YiH' YjL < 0 < YjH
v, . Yj E
(6-17)
[min (YjLYjH' YiHYjL) ' max(YiLYjL' YiHYjH) ]
A particular case of this operator is that in which one of the factors is a numerical coefficient, a. In this case, the range of the product is obtained by scaling the range of the symbolic factor:
a~0
~
(aYi)
E
[aYiL' aYiH]
a <0
~
(aYi)
E
[aYjH' aYjL]
(6-18)
• Addition of ranges. For a given sum of two symbols, Yi and )'j, the range of the sum is computed by adding the corresponding extrema of the addends: (6-19)
• Modulus of ranges. For a given symbolic parameter, product of symbols, or sum of products for which a range [YiL' YiH] is defined or calculated, the modulus of ranges operator yields another range, defined from the previous one by taking the modulus of the extrema in an appropriate order: (6-20)
• Upper and lower operator. These two operators return the extrema of the range for a given symbol Yj, respectively, (6-21)
154
Chapter 6
Symbolic Formula Approximation
• Reciprocal of a range. For a given symbol )'i whose range does not include 0: (6-22)
its reciprocal is defined as (6-23)
Subtraction and quotient of ranges operators are easily defined from the addition, product, and reciprocal operators. Frequently, the range of some symbolic polynomial must be evaluated. Direct substitution of the symbolic parameters with their ranges and the real arithmetic operators with their corresponding interval arithmetic operators yield the so-called natural interval extension of the symbolic polynomial. Its main drawback is that the width7 of the range may be considerably larger than the real one, because each range extrema may be calculated with the upper range bound of one symbolic parameter at a polynomial term and the lower bound at another. Sharper bounds of the range of one function are provided by the mean value form [10]: n
FMV(X) = f(m) + LD;F(X)(Xj-m)
(6-24)
i= 1
where capital letters denote interval extension and F MV (X) is the mean value interval extension of the function f(x) [10], a range narrower than the natural interval extension. The set m = {m l' m2, ... , mn } is the vector of mean values of the independent variables x. , while D.F ( .) is the interval extension of the function derivative with respect to the ith I I variable. This interval extension can be computed using the natural interval extension of the derivatives, or recursively calculated using (6-24).
6.3.2.2. Handling ofMismatches The use of ranges provides a natural way to handle mismatches. As presented in chapter 1, modern symbolic analyzers include strategies to explicitly handle mismatches. This involves the so-called delta variables. For instance, to explicitly express mismatch between two nominally matched transistors M1 and M2, each symbolic parameter x i2 of M2 is determined from that corresponding to MIas Xii
= x iQ
(6-25)
x i2 = x iQ+ ~xil2
where
~X iI'
the delta variable, accounts for the dispersions between both device
parameters.f Hence, such variables have some unpredictable value (either positive or negative) between some given extrema.
7 The
II
width of an interval A = [a l' a2l is defined to be w (A) = la 2 - a ~ 0 [II].
Sec. 6.3
Simplification of Expanded Format Expressions
155
When performing numerical estimate calculations to eliminate insignificant terms using a nominal value approach, each mismatch parameter is assigned a numerical value, its extrema, and a sign. However, this is not in good accordance with the physical meaning of mismatch variables. The variation range approach solves the problems of nominal value techniques to handle mismatches. The mismatching philosophy adapts much better to the variation range idea, because each mismatch parameter is assigned a symmetrical interval with 0.0 as a mean value.
6.3.2.3. Simplification Algorithm Like the conventional criteria of section 6.3.1 for approximation over the whole frequency range, the purpose of range simplification criteria is to eliminate the P least significant terms in (6-7) for a given maximum error margin EM. A conservative approach is to apply the following formula: (6-26)
where [5 L' 5 H] represents the range of the sum of all the terms included in the coefficient h k (x) being simplified, and [A cL' A cH ] (henceforth: accumulated sum) denotes the range corresponding to the sum of terms to be pruned, that is, the P least significant terms in this coefficient. Note that the range approach also allows the approximation of symbolic expressions for a limited frequency range, thus avoiding the problems of the nominal value approach. Such a range is assigned to the frequency variable s and is handled like all other symbolic parameters. The simplification algorithm proceeds as follows. First, the range for each term hkl (x) inside the coefficient is calculated using the product of ranges operator. Then, pairs of terms y.,I y.} with opposite signs and similar magnitudes are considered. If their sum, (Yi + Yj)
E
[(YiL + YjL) , (YiH + YjH)]
(6-27)
simultaneously fulfills the following two inequalities,
'U (I [(YiL + YjL) , (y iH + YjH) ll) < L( I[YiL'YiHll)
u(I[(y iL + YjL) , (Y iH + YjH) ]I) < L (I[YjL,yj H]I)
(6-28)
the pair of terms is grouped and a new range defined by (6-27) is associated with it. These groupings allow proper handling of mismatching terms. Pairs of terms corresponding to mismatched parameters may have a large magnitude and would never be eliminated from the exact expression if the terms are neglected one by one, starting with the smallest. The
8 An alternative is to define
= -\0 + ~xil "n = x iO + dX i2 Xi 1
This representation expresses nominal values and deviations around them more clearly, but incorporates more variable names, which means a higher computational cost.
156
Chapter 6
Symbolic Formula Approximation
grouping allows their elimination if the associated range is small enough. Accuracy of the results is enhanced if the range associated to the grouping is as narrow as possible. This is achieved by the factorization of both terms. For instance, two terms of the positive PSRR corresponding to nominally matched transistors of the Miller OTA are (6-29) Applying the product and sum of ranges operator gives a range in which the lower bound is calculated with the minimum values of Gm»s: and Gm 6 for the first term and the maximum values for the second one (and vice versa for the upper range bound). However, it is unlikely that Gm5 and Gm6 have their maximum values for one term while simultaneously taking the minimum in the other. This may be accounted for by factorizing the sum of the terms: Gm6 G m5 (G m 1Gm4 -G m2 Gm3 )
(6-30)
This operation reduces the range width, which may be decisive in the term-grouping. Next, individual and grouped terms are arranged in an ordered array using the modulus and upper operator for the range comparison. A term, )'., is considered less significant than another, •)'.I , if J (6-31) Once all the terms have been sorted, the least significant are eliminated. Beginning with the least significant term, each new term is included in the accumulated sum and pruned one by one until (6-26) is no longer fulfilled. This requires evaluation of the numerator and denominator in (6-26), for which two approaches have been used: • Natural interval extension. The range of the coefficients, [5L' SH]' are calcu-
lated using the addition of ranges operator on the terms. As stated previously, the natural interval extension may yield a pessimistic overestimate. Also, terms added with their maximum value to the accumulated sum (numerator in (6-26)) may be added with the minimum value to the total sum (denominator in (6-26)), yielding very conservative results. This can be palliated by adding with the maximum magnitude in the denominator, those terms which are likewise added in the numerator. • Mean value form. A more accurate range calculation in the numerator and denominator of (6-26) can be made resorting to the use of the mean value form shown in (6-24). However, the computational effort is clearly larger than the natural interval extension. In Ref. [9], the natural interval extension is used to evaluate the derivatives in (6-24).
6.3.2.4. Further Developments Reported techniques use variation ranges for the small-signal parameters appearing at the symbolic expressions, i.e., transistor parameters like gm' gds' etc. Once a range is assigned to each parameter, they are treated as uncorrelated. Further development should formulate variation ranges for independent electrical and technological parameters and small-signal parameters should be correlated according to their relationships. It is
Sec. 6.3
157
Simplification of Expanded Format Expressions
foreseeable that the calculated ranges would be more accurate (narrower) and hence simplification results would be less conservative.
6.3.2.5. Experimental Results As illustrative examples of results from range simplification criteria , we will use the problematic circuits of section 6.3.1, shown in Fig . 6.3. with the same assessment conditions. Figure 6.6 shows the differences in magnitude and phase between the exact expression and different simplifications for the PSRR+ of the Miller OTA using the range criterion for several EM values . The transistor mismatching was assumed the same as for Fig . 6.4. Note that the vertical scales in Fig . 6.4 and Fig . 6.6 differ; maximum deviations
--. 0.2
co 3
::: 0.1 o
~ ~
0.0
-0 <:)
5-0.1 :::
1\ I---+--+--+---+---+--+---+------
--------------
eo ~ -0.2
,,
,, \ \
102
,,
104
Frequency (Hz) (a)
1.5
I
.
CM= 0.05
cM=0.10 cM= 0.20 -1.5
104
Frequency (Hz)
106
(b) Figure 6.6 Illustrating performance of the range criterion for the PSRR of the Miller OTA: (a) parametric magnitude error curves; (b) corresponding phase error curves.
158
Chapter 6
Symbolic Formula Approximation
are 0.4 dB and 2.50 in Fig. 6.6, and 7 dB and 1750 in Fig. 6.4. Consequently, accuracy is much better for the range criterion. In addition, this significant increase in accuracy is obtained without a significant increase in complexity, as presented in Fig. 6.7, where the complexity versus EM figures are shown for the two criteria. This is further illustrated in Fig. 6.8, which shows the locus for the real part of the roots of the active current mirror. Such a locus should be compared to Fig. 6.5a, which shows the same locus for a nominal point simplification criterion. As shown, the range criterion overcomes the qualitative misinterpretation problems emerging from conventional simplification criteria. Furthermore, quantitative root displacements are minimal for values of up to 50% of the error control parameter. On the other hand, complexity of the simplified formula is similar to that of the conventional criteria. For instance, for EM = 0.2, where conventional criteria yield poles on the right half of the complex frequency plane (Fig. 6.5), the number of terms is 25 for range criterion versus 17 2000 _--.....------.,r----__-----.--_--___.
conventional criterion - - - _. range criterion V)
E 1000 B ~
0'-------....10..-----------'------..1""-----0.3 0.2 0.1 0.0 Figure 6.7 Comparative complexity versus EM curves for the PSRR of the Miller OTA using conventional (nominal point) and range simplification criteria.
0.5 r__...--
:t--......-...,..--
--.--
--.---r---...._--,
0.4
0.3 w 0.2 ~
0.1
0·~109
-10 6
-10 3
0 Re(s)
Figure 6.8 Real part of the poles of the current gain of the current mirror of Fig. 6.3b versus the applied error control parameter using the variation range approach.
Sec. 6.4
Simplification of Nested Format Expressions
159
for conventional criterion. These and other examples show that the range criterion allows very flexible accuracy versus complexity trade-offs. For critical circuits, term elimination is limited to the level required to ensure accuracy.
6.4. SIMPLIFICATION OF NESTED FORMAT EXPRESSIONS The efficiency and accuracy of simplification techniques for expanded format expressions constitute a well-developed topic. But the size of such expressions increases exponentially with the circuit size and, hence, they are adequate only for low- and medium-complexity circuits. Due to limited computer resources, larger circuit analysis requires the use of nested format formulas, whose growth rate is approximately linear with the circuit size [12]. Unfortunately, the difficulties encountered in the simplification of nested format expressions increases exceedingly as compared with their expanded counterparts. This section reviews the approaches reported in the literature for the simplification of nested format expressions. Nested format expressions may result using either some flat analysis techniques, i.e., with modified nodal analysis and not completely expanding the determinants, or from hierarchical analysis. However, both cases are equivalent from a simplification point of view, and their joint description follows.
6.4.1. Direct Pruning Approach As shown in (6-4) and (6-5), nested expressions introduce a subexpression hierarchy, which can be conceptualized as an inverted tree. The complete expression is usually called root expression and the expressions at the deepest nested levels are called tree leaves. The direct pruning approach, first introduced in SYNAP [6], eliminates insignificant subexpressions at each nested level. For instance, consider the expression (A + B) (C + D)
(6-32)
where the relative values of the parameters are A = C = 10 and B = D = 1. Then, because B is negligible as compared to A, and D as compared to C, Band D are pruned to obtain ·AC
(6-33)
This pruning is done without assessing how changes in the deleted terms may affect the different s power coefficients of the equivalent expanded network function. However, common practice shows that errors in the root expression may be large if the influence of a pruned subexpression on the coefficients is not homogeneous. These errors may be avoided by separately simplifying each coefficient of the complex frequency s, analogous, in this sense, to all those approximation methods for expanded expressions that consider the different powers of s individually. Unfortunately, techniques currently used for fully symbolic network analysis (compact MNA and sparse Laplace expansion in ISAAC [5]; MNA and determinant calculation in SYNAP [6]; MNA and determinant definition in SAPEC [13]; and hybrid formulation and signal flowgraph in ASAP [2]) do not directly provide nested format expressions for each power of s.9 Consequently, a partial expansion is needed to separate the different coefficients of s. This partially destroys the advantages of the original nested expression, but some problems may even arise using this approach:
160
Chapter 6
Symbolic Formula Approximation
• Significant terms may be pruned while insignificant ones are maintained. For instance, consider the nested expression, (A + B) (C + D) + (E + F) (G + H)
(6-34)
If A = 10, B = 1, C = D = 2, and E = F = G = H = 1,then A »B and the algorithm will prune B, resulting in A ( C + D) + (E + F) (G + H)
(6-35)
where B( C + D) has been eliminated although it is larger than E (G + H), which is kept in (6-35). • Cancellations in the expression tree may cause large errors. Insignificant subexpressions at a given hierarchy level (compared with dominant expressions at the same level) may become significant if the dominant ones are canceled up in the hierarchy. Obviously, such cancellations are not known when the subexpression pruning is performed. For instance, consider A (B + C) - B (A + D)
(6-36)
where B = 10, A = 20, C = 1, and D = 2. B » C and A »D, then C and Dare eliminated and the final result of the expression is 0, which is clearly incorrect. Also, "false" terms may appear. For instance, if in expression (6-36) B » C and A « D, then C and A are eliminated and the final result of the expression is AB-BD
(6-37)
while the expanded form of (6-36) is AC-BD
(6-38)
The term AB has appeared in the approximated expression (6-37), while it does not appear if (6-36) is expanded. Note that although cancellations among consecutive levels can be easily prevented, in a more general case, cancellations need not necessarily occur between consecutive hierarchical levels. A similar approach is used in SSPICE [14], which uses a hierarchical decomposition scheme, calculates the determinant of the admittance matrices of the constituent subblocks, and approximates each determinant before composing the global result, by dropping out unimportant terms. l O In this sense, it is equivalent to pruning subexpressions in the previously cited technique and suffers from the same accumulation of errors problem.
9 An exception should be made for the lumping of expressions available in programs like ISAAC and
ASAP. Although this lumping certainly gives a nested format expression, it is only a circuit transformation, providing only two nesting levels. Moreover,the simplificationis performed in the same way as in expanded format expressions. 10 In this sense, it can also be consid~red an approximation-during-generation technique, described in section 6.5.
Sec. 6.4
Simplification of Nested Format Expressions
161
Reference [14] tries to preserve the numerical accuracy of the symbolic expression by replacing the pruned terms with their numerical value. For instance, applying this to the expression in (6-32) results in (A+I)(C+I)
(6-39)
Another alternative is the use of numerical fitting factors. For the same expression, this approach leads to
~AC 100
(6-40)
Both methods guarantee complete accuracy at the nominal point, but not at other, even close, points. Another more accurate possibility, suggested in Ref. [15], consists of replacing pruned terms for a multivariate Taylor polynomial based on the nominal point. The solution applied in (6-39) corresponds to a zero-order polynomial. Higher-order polynomials increase accuracy at the cost of increasing expression complexity.
6.4.2. Simplification Criterion Requirements The previously cited problems of the direct pruning approach assist in establishing the following requirements that an efficient and accurate simplification criterion for nested format expressions should meet: • Due to the extremely high computation cost of expanding expressions, simplification must be performed directly in nested format. • The error at the top level expression, that is, the error in the global system behavior, must be user-controllable. Hence, the user should not be involved in the simplification of expressions at the lowest or intermediate hierarchical levels. • Simplifications of intermediate expressions should be performed taking into account their influence on the global behavior, rather than their relative importance within their current hierarchical level. • Generally, a given intermediate term or subexpression may affect several coefficients (corresponding to the different powers of the complex frequency s) in the numerator and denominator of the global expression. The simplification algorithm should be conservative in the sense of evaluating the worst case of influence on the different coefficients. • A mechanism should be provided capable of coping with expression cancellations at intermediate hierarchical levels. That is, avoid eliminating expressions of apparently low significance that would become important when cancellations at higher hierarchical levels are performed. • The simplification criterion should have low sensitivity to small parametric variations. In other words, parameter mismatches should be adequately handled.
162
Chapter 6
Symbolic Formula Approximation
6.4.3. The Lazy Expansion Approach A more evolved approach intended to meet previous requirements is the lazy expansion technique in SYNAP [15], [16], which is a determinant-based analyzer. Determinants are expanded enough to isolate the desired coefficients of 5, and then the approximation algorithm is applied for each coefficient. For this approximation, this technique conceptually views the nested expression in its expanded (sum-of-products) form and partitions the terms into two groups: significant and insignificant. This approach uses priority queues to perform partial expansions at each nested level, just enough to extract the significant terms. The nested polynomial is multiplied step by step, collecting as many elements from the significant group as possible, to produce a sequence of sum-ofproduct terms. Terms are ordered in decreasing order by stem magnitude. Term cancellations (including additions) are easily removed because canceling terms have the same numerical magnitude and are hence expanded consecutively. Because the result must contain symbolic terms in strictly decreasing order of magnitude (including numerical coefficients), the terms in stem magnitude order must be reordered and collected appropriately. This requires a user-supplied assumption about the maximum numerical coefficient present in any term. The most significant term groups are generated until (a) the expression has been completely expanded, (b) the magnitude of the expanded terms represents a given fraction of the complete expression, or (c) some user-specified limiting criteria is satisfied, like a maximum number of terms or a maximum term magnitude. As an illustrative example, consider (a + B + c + D) (e + F + g + h)
(6-41 )
Uppercase variables represent large-magnitude circuit parameters and lowercase variables represent small-magnitude parameters. The lazy expansion approach operates by first expanding (6-41) enough to extract the largest-magnitude terms:
BF+DF+B(e+g+h) +D(e+g+h) + (a+c) (e+F+g+h)
(6-42)
This gives the simplified expression:
BF+DF
(6-43)
If additional terms are required, the process is repeated in the remaining nested expression in (6-42).
HANDLING OF MISMATCHES SYNAP [15] treats mismatches as random quantities with zero expected value and a number representing its variability. The lazy expansion approach handles those terms containing mismatch variables and those that do not independently. Terms with no mismatch variables are processed as previously indicated. Terms containing more than one mismatch variable are automatically discarded based on their relative insignificance. Terms containing one mismatch variable are processed by sequentially applying subsets of the partitioning criteria for terms without mismatch variables (cited previously) to: • the terms with one mismatch variable, with its variability as numeric size for comparisons
Sec. 6.4
163
Simplification of Nested Format Expressions
• the coefficients of the mismatch variables of groups of terms, grouped by mismatch variables This approach may yield erroneous results as some parameters' mismatch values are usually larger than nominal values for other parameters. For example, two of the terms appearing at the PSRR,.. calculation of the CMOS Miller OTA of Fig. 6.3 are [2] 2
(6-44)
gds2gm7~gds4~gm2 + gds2gm7~gds4
where gm and gds represent MOS transistor transconductance and output conductance, respectively. According to the lazy expansion technique, the first term in (6-44) contains more than one delta variable and, hence, must be eliminated. However, the transconductance g m is typically several decades larger than the output conductance g ds ' and therefore it is not difficult that ~gm2 > gds2' which means that the eliminated term in (6-44) is more significant than that remaining in the symbolic expression.
EXPERIMENTAL RESULTS The lazy expansion technique has proven capable of handling circuits of up to 24 transistors, like the CMOS OTA of Fig. 6.9. Figure 6.10 illustrates the speed advantage of the lazy expansion technique versus the conventional full expansion approach [15]. The size limit of this tool can be established around 25 transistors. It is difficult to predict the behavior of the lazy expansion approximation technique combined with a hierarchical analysis tool.
6.4.4. The Contribution Factor Approach Another attempt to meet the requirements in section 6.4.2 is based on the contribution factor concept [9]. The contribution factors assess the relative significance of each nested subexpression on each coefficient of the numerator and denominator of the global
~CL
~VcaS2 Figure 6.9 CMOS OTA.
164
Chapter 6
o Full expansion
10
~
•
• Lazy expansion 0 00
...-.-
0 0'\
0
Symbolic Formula Approximation
100
A
......... ~ I
Z
0
.0
~
0
e.t:l
U
0
~
CI:l
'-' ~
E
E= ~
c,
U
0
•
0.1
•
•
AA
t
•
0.01'---------~------------
5
10
15
20
Circuit size (number of transistors)
25
Figure 6.10 Time versus circuit size comparison between the lazy expansion and full expansion approaches [15].
expression. This evaluation is performed without any symbolic expansion and prior to pruning any term or subexpression, to avoid eliminating significant expressions. The system function at either a leaf or intermediate node can be conceptually written as the quotient of two symbolic polynomials,
(6-45) where G Nk (5, x) and G Dk (5, x) are symbolic polynomials in 5 and the circuit parameters x. The contribution factor approach tries to determine how G Nk (5, x) and G Dk (5, x) contribute to the numerator and the denominator of the root expression H (5, x), if this root expression is transformed and given as a ratio of two can be expressed as
5
polynomials. These contributions
(6-46) H N ( 5, X ) GNk(5,X)CNNk(5,X) +GDk(5,X)CNDk(5,X) +R N(5,X) H (s, x) == H ( ) = G Nk (5, x) CDNk (5, x) + G Dk (5, x) CDDk (5, x) + R D (5, x) D 5,X where the polynomials C NNk' C DNk' CNDk' and C DDk represent the contribution factors of G Nk and G Dk to the numerator H N ( .) and denominator H D ( .) of the total transfer function; and RN ( .) and RD ( .) denote the parts of the numerator and denominator polynomials of H ( .) unaffected by g k . Contribution factors for the different subexpressions are calculated to ensure accurate simplification, together with the coefficients of thedifferent 5 powers in H(.), prior to pruning terms in the subexpressions. Thus, it can be predetermined to what degree these simplifications affect the whole. Contribution factors and system function coefficients are
Sec. 6.4
Simplification of Nested Format Expressions
165
computed numerically, taking into account the coefficients' variation ranges appearing in the system functions at the lowest hierarchical levels. It must be emphasized that the use of typical values, instead of ranges, to compute contribution factors is not safe as long as sensitivity to the symbol changes when moving up through the hierarchy levels. The use of variation ranges also avoids the problems of the lazy expansion technique to handle mismatch parameters. Contribution factors allow calculating adequate error control parameters for each nested subexpression. Expressions with little influence on the root expression can be greatly simplified, while small error margins are applied to those for which the root expression is very sensitive. This algorithm provides a natural mechanism to handle possible cancellations at intermediate levels of the hierarchy. If a specific expression is to be canceled at higher levels of the hierarchy, its contribution factor to the root node will be zero and can thus be eliminated. Variation ranges also constitute a major danger of this approach. In some expressions, particularly those with many hierarchical levels, the natural interval extension yields very conservative results. Application of range reduction techniques can be CPUintensive, especially for very large formulas.
HANDLING OF MISMATCHES As previously explained, this technique uses variation ranges for the symbolic parameters. Its use to represent mismatches was already introduced in section 6.3.2. Unlike the lazy expansion approach, the contribution factor approach is insensitive to the number of mismatch variables present.
EXPERIMENTAL RESULTS The low-pass filter network of Fig. 6.11, already used as a test circuit in specialized literature on hierarchical analysis techniques [17], has been used in Ref. [18] to test the feasibility of the hierarchical simplification criterion explained previously. The operational amplifiers were described at the transistor level and high-frequency transistor models (see Fig. 6.2b) were used. Figure 6.12 shows magnitude and phase plots for the exact and simplified expressions. While the complexity of expanded format expressions has traditionally been linked to the number of terms, there is no equivalent definition for nested format expressions.
Vi ........- - - - N U ' - - - - - - '
Figure 6.11 Low-pass filter architecture.
166
Chapter 6
...-.
Symbolic Formula Approximation
-20.0
Exact
~
"'0
"'-"
Simplified
Cl)
.a -40.0
"'0
'2
OJ} ~
~
-60.0
-80.0 .........
--"-I-............--a...............~~..".,.",."""""----"-...."",.,~-.....~.&.M&...
102 103 104 Frequency (Hz)
1
..........~10&&1
(a) 0 -90 -180 ...-. CI) Cl)
-270
Exact
Cl)
-360
Simplified
Cl) .... OJ}
"'0
"'-" Cl) CI)
-450
\
~
..c c,
-540
\'-
-630 -720
....
1
1
10
102
3
4
10 10 Frequency (Hz)
105
106
(b) Figure 6.12 Bode diagrams for exact and simplified expressions of the voltage gain of Fig. 6.11: (a) magnitude; (b) phase.
Because a final expanded expression is rarely obtained, it is more convenient to use the number of multiplications and additions of the nested expression as a complexity measure. As the symbolic expressions will usually experiment posterior computational manipulation, this complexity measure reflects real savings in computational cost. Table 6-2 shows the complexity measures of the exact and simplified network functions plotted in Fig. 6.12. The number of multiplications also includes divisions and the number of additions includes subtractions. A reduction of 3 orders of magnitude can be observed in the complexity of the simplified expression. However, as shown in Fig. 6.12, magnitude and phase errors remain small.
Sec. 6.5
167
Approximation-during-Generation Techniques Table 6-2 Complexity Comparison between Exact and Simplified Expressions
Expression type
Number of additions
Number of multiplications
Exact
626,866
3,033,848
Simplified
294
3,141
6.4.5. Expressions in SOE Format Some small differences, which a simplification criterion should consider, appear when nested format expressions are in SOE format. In this case, the same subexpression can appear at different parts of a higher level expression as a common variable name. Therefore, that subexpression will be approximated equally, independently of its different relative significance in each part where it appears. This can be solved by duplicating common subexpressions, assigning them different names in the distinct places where they appear, and simplifying them individually. Unfortunately, this implies losing memory savings and the efficient computation of SOE expressions.
6.5. APPROXIMATION-DURING-GENERATION TECHNIQUES The simplification techniques presented in previous sections implicitly assume the existence of the exact expressions. They also show that only a small portion of the terms remain after simplification. Consequently, most of the resources employed to generate the pruned terms are wasted. To avoid this and hence enable the analysis of larger circuits, this section describes some emerging approaches in which the simplification is performed at the analysis stage rather than after the full exact analysis. As discussed before, the approximation technique in SSPICE [14] can also be considered as an approximation-during-generation technique in the sense that the analysis results of each decomposed subcircuit are approximated to reduce memory consumption. Another approach, reported in Ref. [19], groups the elements into two or more equivalence classes based on their relative magnitudes. The determinant of the admittance matrix is then approximately calculated by first trying the matrix with only large magnitude conductances. If it is zero, a new combination of equivalence classes is tried by substituting each row with one row of small conductances. The process is recursively applied until a nonzero determinant is found. I I Reported results cover op-amps with up to 12 transistors. The analysis times range from 35.1 s (for an op-amp with seven transistors) to more than 20 min., on a VAX Station 3100. This seems to assert that the technique explodes quickly with the circuit size, particularly when capacitors are also included. Hence, it only slightly increases the maximum capability of conventional approximation-after-generation tools. A more practical idea to approximate symbolic expressions as they are generated was first reported in Ref. [20]. The rationale behind this approach is that terms are 11
The process of progressive expansion of determinants with an increasing number of small conductances has strong similarities with the lazy expansion approach in section 6.4.3.
168
Chapter 6
Symbolic Formula Approximation
generated strictly in decreasing order of magnitude, starting with the largest. When the sum of the generated terms satisfies some error criterion, generation is complete. Two basic advantages arise. First, the analysis time is drastically reduced because no time is wasted in generating terms from the complete expression that will not appear in the simplified expression. Second, the memory requirements are much smaller compared with simplification-after-generation techniques and, hence, the maximum analyzable circuit size increases significantly. Two basic requirements must be met for this approach to be practical: • An analysis technique must be used that is capable of generating symbolic terms in decreasing order of magnitude. • A stopping criterion is needed to determine when a sufficient number of terms has been generated. In what follows, we focus on the description of this technique.
6.5.1. Term Generation The basic idea consists of finding a technique to generate (for numerator and denominator, and each power of the frequency) the valid terms strictly in decreasing order. None of the traditional symbolic analysis techniques is directly applicable to this problem. A direct approach is to enumerate all possible permutations of products of symbolic parameters in decreasing order of magnitude and use some traditional technique (i.e., parameter extraction, tree enumeration, etc.) to check if each corresponds to a valid term of the network function. For all except the simplest circuits, this approach quickly encounters combinatorial explosion problems. The first reliable algorithms capable of efficiently generating terms for circuits of practical size have been reported independently in Refs. [21], [22] and [23], [24]. These algorithms are based on the undirected tree method for generation of symbolic expressions.l ' In this approach, valid terms are given by common spanning trees to the voltage graph G v and the current graph G/-two graphs easily built from the circuit topology. These graphs contain the same nodes as the circuit. The stamp of a passive element for each graph is one branch between its terminal nodes. The voltage graph is constructed with the controlled branch of voltage-controlled current sources (VCCSs) and the current graph with the controlling branch of the VCCS. The stamps in both graphs for the different circuit elements are shown in Fig. 6.13. All other types of controlled sources must be converted to the interconnection of passive elements and VCCSs [25]. Each branch is assigned the admittance (or transadmittance) of the corresponding circuit element. For each common spanning tree in both the voltage and current graphs, a valid symbolic term is given by the product of all the branch admittances included in that spanning tree. The major reported drawback of this technique is the complicated calculation of each term sign [26]. However, once programmed, the computational cost of such calculation is negligible. The computation of the most significant terms for each power of the frequency sk, in the numerator and denominator, reduces to the following graph problem: "Given the voltage and the current graphs of a circuit with n nodes and b branches, enumerate subsets
12 See
chapter 2 of this book for a detailed explanation of the undirected tree enumeration method.
Sec. 6.5
169
Approximation-during-Generation Techniques
Circuit element
Current graph
Voltage graph
v
Figure 6.13 Stamps of basic circuit elements in the tree enumeration technique.
of (n - 1) branches in decreasing order of magnitude that: (a) constitute a spanning tree in G v; (b) constitute a spanning tree in G/; (c) contain k blue branches (corresponding to capacitances) and (n - k - 1) red branches (corresponding to conductances)." The algorithm selects one graph (the voltage graph is chosen for heuristic reasons), generates spanning trees with k blue branches in decreasing order of magnitude in that graph, and for each of them checks if it is also a spanning tree in the current graph. The spanning tree generation algorithm described in Refs. [21], [22] and [23], [24] is basically the same, differing only in some detailed implementation aspects. The generation of spanning trees in decreasing order follows the algorithm in Ref. [27], originally proposed for one-colored graphs but extensible to two-colored graphs. This algorithm starts from a maximum weight spanning tree, called the reference tree, which can be calculated using any traditional technique, such as those reported in Ref. [28]. Then, branch exchanges are performed to obtain spanning trees with smaller weight. Partitioning the solution space after each branch exchange allows efficient generation of spanning trees in decreasing order of magnitude. This algorithm is easily adapted to the enumeration in directed graphs of spanning trees in decreasing order of magnitude. However, for active circuits, the number of term cancellations in the directed tree method is much higher than the number of undirected trees in the voltage or current graphs, which yield no valid terms in the undirected tree method. Reference [29] presents an interesting discussion of the spanning tree enumeration problem in decreasing order of magnitude in terms of matroid intersection problems (see Ref. [30] for an introduction to matroid theory). Each condition (a)-(c) enumerated earlier is mapped into a matroid and the problem of generation of common spanning trees in order is mapped into a weighted matroid intersection problem. The intersection problem for three matroids, in general, is nonpolynomial-hard. However, there are polynomial time algorithms for the intersection of two matroids. The algorithm previously described in this section calculates the intersection of matroids corresponding to conditions (a) and (c). Then, it must be checked if condition (b) is also satisfied. Yu and Sechen [29] explored the calculation of the intersection of the matroids corresponding to conditions (a) and (b).
170
Chapter 6
Symbolic Formula Approximation
Then, because it is not possible to select spanning trees with exactly k blue branches (condition (c)), uncolored common spanning trees at multiple frequency points are generated. Any term generated at some frequency point is kept. Yu and Sechen [29] have shown some promising results. However, the efficiency of this approach strongly depends on the number of sample frequency points. Also, accuracy at frequencies between two sample frequency points is not guaranteed.
6.5.2. Error Criterion The analysis algorithm provides valid symbolic terms in decreasing order of magnitude, but needs some criterion to know when a sufficient number of terms has been generated and the generation engine can stop. Simplification criteria for expanded format expressions, explained in section 6.3, discards the least significant terms for each coefficient in (6-6), beginning with the smallest one, while the magnitude of the pruned terms remains below a given fraction of the exact expression. In Refs. [21] and [31], terms for each coefficient are generated until their accumulated magnitude reaches a given threshold, as shown in the following stopping criterion for the nominal value approach: R
h k (x o ) -
Lh
h k l (x o )
< Eklh k (x o ) I
(6-47)
1=1
R
where
L
kl (x 0)
represents the sum of the R most significant symbolic terms of the
1=1
coefficient hk (x). The numerical evaluation of Ih k (x o ) I in (6-47) is not a major problem, because very efficient techniques exist for the generation of symbolic network functions with only the complex frequency s as symbolic parameter; for instance, the polynomial interpolation method [32]. The simplification technique with variation ranges uses the following stopping criterion for the generation of the dominant terms: L(/[GL,GH]j)
-~--- >
'U(I[SL,SH]j)
(l-E k)
(6-48)
where [G L' G H] represent the range of the sum of the R most dominant terms. The complexity of the calculation of the denominator in (6-48) increases considerably. In this approach, the range of the sum of all symbolic terms must be calculated where such terms are unavailable. The calculated polynomial range must be an overestimate of the real range and its width must be as small as possible to avoid overly conservative simplifications. The traditional numerical interpolation method for real polynomials can be extended to variation ranges by simply changing real variables for interval ones and real arithmetic operations for the corresponding interval arithmetic operations [33]. The resulting rangeis an interval extension of the symbolic polynomial. However, these ranges carr be too wide and, hence, yield excessively conservative results.
Sec.6.5
Approximation-during-Generation Techniques
171
A pessimistic overestimate of an interval extension can be narrowed by applying the algorithm reported in Ref. [34]. In Ref. [24], all terms that are larger than a fraction EM of numerator and denominator EMINI or EMIDI are generated. The comparison is performed for a set of sample frequencies and each term is generated if it is larger for at least one frequency point. The magnitude and phase errors of the resulting symbolic expression are evaluated for the .same set of sample frequencies. The procedureends if the errors are acceptable; otherwise, EM is decreased and the generation procedure continues. This approach suffers from the same risks of sampling at a finite number of frequencies previously discussed.
6.5.3. Handling of Mismatches The inclusion of matching devices introduces possible cancellations in the tree enumeration technique. Symbolic terms that differ when no matching is considered may become equal when matching is introduced. Such terms either cancel one another or result in one symbolic term with an integer coefficient larger than 1. Neither of them pose significant problems to the approximation-during-generation technique explained previously.Those terms have the same numericalmagnitude and, hence, they are generated one immediately after the other. Therefore, cancellations and additions of coefficients are easily performed. As stated previously, much insight can be gained from some small-signal characteristics by explicitly expressing mismatching between devices. For instance, the mismatching between the transconductances of the input matched transistor pair of Fig. 6.14 is expressed as (6-49) As in simplification-after-generation techniques, the mismatching parameter L1gm is assigned a symmetrical interval around 0.0. These mismatches are topologicallyhandled in the tree enumeration approach by splitting the transconductance g m2 into the parallel connection of two transconductances, gm and L1g m, as schematically shown in Fig. 6.14 [21], [31]. Obviously, the controlling voltage for both elements is inherited from the
Figure 6.14 Illustrating the element splitting for explicit expression of mismatches.
172
Chapter 6
Symbolic Formula Approximation
original element. Each element is then operated separately. Terms containing gm will experiment cancellations and additions, as previously explained for the exact matching case. Terms containing the mismatching parameter ~g m are generated only if necessary because they appear in ordered sequence like any other symbolic term.
6.5.4. Experimental Results Comparative results of this approach versus conventional techniques (complete symbolic expression generation + simplification) have been reported in Refs. [21] and [31]. Figure 6.15 shows two academic benchmark circuits: a resistive ladder network and a fully connected circuit, proposed in Ref. [35] as representative examples of extremely sparse and extremely dense circuits. CPU times for both circuits as a function of the number of circuit nodes have been plotted in Fig. 6.16. We can see that the analysis time with the approximation-during-generation approach increases much more slowly than with conventional symbolic analysis tools. Moreover, the analyzed circuits largely exceed the maximum capability of conventional approaches. Experimental results with practical circuits also reveal both a very important efficiency improvement in the analysis of medium-size circuits, which were already analyzable with conventional tools, as well as the ability to increase the maximum analyzable circuit size. For instance, consider the fully differential folded-cascode with linearized input stage of Fig. 6.17. The symbolic analyzer ASAP [2] uses 205 s to obtain the exact expression of the differential voltage gain and to provide a simplified expression with 25% error margin. The tool in [21] needs only 0.1 s to obtain the same simplified expression. It is not easy to compare the techniques presented in Refs. [21] and [31], on the one hand, and in Ref. [24], on the other. This is mainly due to the different error criteria applied and the fact that the tool in Ref. [24] performs a simplification-before-generation procedure (see section 6.6), which significantly reduces the circuit size. On the other hand, these tools are still undergoing development and, hence, the availability of results is still scarce. For illustration's sake, the tool in Ref. [21] provides a simplified expression (error margin Ek = 0.25 in the individual transfer function coefficients) of the voltage gain of the folded-cascode op-amp in Fig. 6.18 in 54.7 s (CPU time measured in a SPARC Station 10). The generation of a symbolic expression for the flA741's transfer function at low frequencies with a magnitude error of 0.1 % (transfer function with 110 symbolic terms) requires 38 s (CPU time on a SPARC Station 10).
• ••
••• •••
n
+
• ••
•••
•••
(a)
•••
···
(b)
Figure 6.15 (a) Ladder resistive network; (b) fully connected resistive network.
••• n
Sec. 6.5
173
Approximation-during-Generation Techniques
I 06--............-....---..,...-poo-...........,....-.--.,............---~-...........,... ...........,......., 105 ,-.
I
104
I I
~ 103 (1)
.§
2 U
ASAP Approximation during generation
I
I I
102
I I
10
I I
I
I I
0.1
(a)
0.0 llo.o.Io-~~"""""'~""""-"""""'_--"'"""'"----""'''''''''''-''''_''''''__-''' 10 15 20 25 30 35 40
Number of ladder stages
I I I I
ASAP Approximation during generation
I I
I ~
0.1 '
(b)
I
0.01 3 4
I
I
~
5
6 7 8 9 10 11 12 13 14 15 16 Number of nodes
Figure 6.16 Time comparison of conventional approach versus approximationduring-generation technique for the benchmark circuits in Fig. 6.15: (a) ladder resistive network; (b) fully connected network.
Figure 6.17 Fully differential folded-cascode op-amp.
174
Chapter 6
Symbolic Formula Approximation
V,B'
Figure 6.18 Folded-cascode op-amp.
An approximated expression (57 terms) for the JlA741 is provided in Ref. [24] in 18.5 s (CPU time on a SPARC Station 2). Another test circuit reported in Ref. [24] is the rail-to-rail op-amp of Fig. 6.19. An approximate expression (36 terms) is provided in 63.4 s (CPU time on a SPARC Station 2).
Figure 6.19 Rail-to-rail op-amp.
6.6. ' APPROXIMATION-BEFORE-GENERATION TECHNIQUES Approximation-before-generation techniques group those techniques in which the approximation is performed before generation: either the determinant is computed in determinant-based methods, or Mason's gain formula is applied in signal flowgraph methods, or tree admittance products are computed in tree enumeration methods, etc.
Sec. 6.6
Approximation-before-Generation Techniques
175
The approximation can take place in the network under analysis, replacing those elements (or subcircuits) whose contribution (appropriately measured) to the network function is negligible with a zero-admittance or zero-impedance element. For instance, the bias circuitry of a given cell, with no effect on the voltage transfer function under calculation, can be substituted with wise-connected zero-impedance elements. Or a small capacitor in parallel with a large one can be replaced with a zero-admittance element. These approximations are usually done when deriving network equations manually. However, except for the most trivial replacements, no automatic procedure has been reported yet. Reported approaches perform approximations directly on the network equations, on either a matrix or a graph, depending on the analysis technique used. In AnalogSifter [36]-[38], symbolic analysis is performed based on the nodal admittance matrix. As a first step, device parameters are eliminated from the cofactors of the nodal admittance matrix if the error induced in the cofactor is below a given error margin. Because each device parameter appears at four positions on the admittance matrix, parameter elimination can be performed at one, two, or all four positions. Concurrently with the device parameter elimination, AnalogSifter tries to reduce determinant dimension by factoring out rows and columns with only one nonzero entry and performs row and column operations to reduce the number of symbols or nonzero entries. These heuristics do not alter the value of the determinant and are not really approximations. However, they are valuable as they partially palliate the cancellation problem of determinant-based approaches. Capacitors must also be included in the admittance matrix for high-frequency analysis. Then, applied approximations are only valid in a limited frequency range. Three scanning frequencies are considered per decade, used to evaluate the influence of elimination of the corresponding capacitor parameter. One element is eliminated at four, two, or one location, only if the induced error in the determinant is smaller than an error bound for all scanning frequencies. This technique has reported CPU times between 21 sand 39 s on a SUN SPARe Station 2 for the analysis of a 741 op-amp for different frequency ranges. The device parameter elimination concept had also been used in Ref. [39]. In this case, the influence of each parameter was evaluated using the Sherman-Morrison formula applied at a single frequency value. Hence, the probability of large errors for different frequency points increased with respect to the previous approach. Neither in this approach nor in Ref. [37] is it described how the complex coefficients of the perturbations errors for ac analysis are compared. As previously discussed, RAINIER [24] uses the undirected tree enumeration method to generate symbolic terms in decreasing order. This tool also incorporates a simplification-before-generation scheme, obviously at a graph level. As the first step, the two graphs (voltage and current) for the numerator of the transfer function under calculation are simplified individually. The contribution of each branch transmittance to the numerator is computed. If the element contribution is weak or strong, the corresponding branch can be deleted or contracted from the current and voltage graphs. Obviously, the significance of the contributions should be checked for the complete frequency range of interest. RAINIER performs the test over a set of sample frequencies selected within such a range. This same operation is then performed for the two graphs corresponding to the denominator of the network function.
176
Chapter 6
Symbolic Formula Approximation
As the second step, branches are deleted or contracted simultaneously in the numerator and denominator two-graphs if the contribution of these transmittances to both the numerator and denominator is similar for all frequencies (in fact, the set of selected sample frequencies). Experimental results of this approach have already been discussed contemplating the simplification-during-generation aspects of this tool in section 6.5.4. Approximation-before-generation techniques can be coupled with approximationduring-generation and approximation-after-generation techniques. Obviously, the global error on the network function will depend on the error of both approximation procedures. Algorithms or heuristics for optimum distribution of errors between approximation-beforegeneration and approximation-during/after-generation techniques are still pending.
6.7. CONCLUSIONS The fundamental issue of simplification of symbolic expressions has been the main topic of this chapter. Techniques for expressions of different formats and complexities have been introduced semichronologically. Most CAD developers have addressed the problem of simplification of expanded format expressions: the least difficult format to deal with. Primitive techniques based their operation on the evaluation of expressions at a single nominal point. The introduction of variation ranges has solved some accuracy problems encountered in those approaches. One possible solution for the limited circuit size amenable to flat symbolic analysis tools producing expanded format expressions is hierarchical circuit analysis. They naturally provide nested format expressions. Several techniques have been reported trying to achieve the accuracy levels of their expanded counterparts. However, the ability of hierarchical techniques to deal with strongly connected circuits is questionable. The absence of reported results for this type of circuit suggests that these techniques are not universally applicable to any kind of circuit above the capabilities of conventional flat analysis tools. On the contrary, circuit partitioning and hierarchical analysis seem to be especially adequate for circuits at the subsystem level. The gap between both kinds of tools might be filled by the recently reported approximation-during and before-generation techniques.
References [1] G. E. Gielen, H. Walscharts, and W. Sansen, "Analog circuit design optimization based on symbolic simulation and simulated annealing," IEEE J. Solid-State Circ., vol. 25, pp. 707-713, June 1990. [2] F. V. Fernandez, A. Rodriguez-Vazquez, and J. L. Huertas, "Interactive ac modeling and characterization of analog circuits via symbolic analysis," Analog Integrated Circuit and Signal Processing, vol. 1, pp. 183-208, November 1991. [3] G. A. Watson, Approximation Theory and Numerical Methods. New York: John Wiley, 1980. [4] G. Gielen and W. Sansen, Symbolic Analysis for Automated Design of Analog Integrated Circuits. Boston: Kluwer Academic, 1991.
References
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[5] G. Gielen, H. Walscharts, and W. Sansen, "ISAAC: A symbolic simulator for analog integrated circuits," IEEE J. Solid-State Circ., vol. 24, pp. 1587-1597, December 1989. [6] S. Seda, M. Degrauwe, and W. Fichtner, "A symbolic analysis tool for analog circuit design automation," Proc. IEEE Int. Conf Computer-Aided Design, Santa Clara, pp. 488-491, 1988. [7] G. Wierzba, Sspice User Manual, Version 1.0. Michigan State University, East Lansing, February 1991. [8] D. Nairn and C. Salama, "High-resolution, current-mode AID convertors using active current mirrors," Electron. Lett., vol. 24, pp. 1331-1332, October 1988. [9] F. V. Fernandez, A. Rodriguez-Vazquez, J. D. Martin, and J. L. Huertas, "Formula approximation for flat and hierarchical symbolic analysis," Analog Integrated Circuits and Signal Processing, vol. 3, no. 1, pp. 43-58, January 1993. [10] R. E. Moore, Methods and Applications of Interval Analysis. Studies in Applied Mathematics, Philadelphia, 1979. [11] G. Alefeld and J. Herzberger, Introduction to Interval Computations. New York: Academic Press, 1983. [12] M. M. Hassoun and P. M. Lin, "A new network approach to symbolic simulation of large-scale networks," Proc. IEEE Int. Symp. Circuits Syst., Portland, pp. 806-809, 1989. [13] S. Manetti, "New approach to automatic symbolic analysis of electric circuits," lEE Proc., P. G, vol. 138, no. 1, pp. 22-28, February 1991. [14] S. Chang, J. F. MacKay, and G. M. Wierzba, "Matrix reduction and numerical approximation during computation techniques for symbolic analog circuit analysis," Proc. IEEE Int. Symp. Circuits Syst., San Diego, CA, pp. 1153-1156, 1992. [15] S. Seda, M. Degrauwe, and W. Fichtner, "Lazy-expansion symbolic expression approximation in SYNAP," Proc. IEEE Int. Conf Computer-Aided Design, Santa Clara, CA, pp. 310-317, 1992. [16] S. J. Seda, Symbolic Analysis for Analog Circuit Design Automation. Konstanz: Hartung-Gorre, 1993. [17] J. A. Starzyk and A. Konczykowska, "Flowgraph analysis of large electronic networks," IEEE Trans. Circuits Syst., vol. CAS-33, no. 3, pp. 302-315, March 1986. [18] F. V. Fernandez, A. Rodriguez-Vazquez, J. D. Martin, and J. L. Huertas, "Approximating nested format symbolic expressions," Alta Frequenza, vol. 5, no. 6, pp. 326-335, November 1993. [19] M. Amadori, R. Guerrieri, and E. Malavasi, "Symbolic analysis of simplified transfer functions," Analog Integrated Circuits and Signal Processing, vol. 3, pp. 9-29, January 1993. [20] P. Wambacq, G. Gielen, and W. Sansen, "A cancellation-free algorithm for the symbolic simulation of large analog circuits," Proc. IEEE Int. Symp. Circuits Syst., San Diego, pp. 1157-1160, 1992. [21] F. V. Fernandez, P. Wambacq, G. Gielen, A. Rodriguez-Vazquez, and W. Sansen, "Symbolic analysis of large analog integrated circuits by approximation during expression generation," Proc. IEEE Int. Symp. Circuits Syst., London, Great Britain, pp.25-28, 1994. [22] P. Wambacq, F. V. Fernandez, G. Gielen, W. Sansen, and A. Rodriguez-Vazquez, "An algorithm for efficient symbolic analysis of large analog circuits," Electron. Lett., vol. 30, no. 14, pp. 1108-1109, July 1994.
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[23] Q. Yu and C. Sechen, "Generation of color-constrained spanning trees with application in symbolic circuit analysis," Proc. Fourth Great Lakes Symp. VLSI, Notre-Dame, IN, pp. 252-255, 1994. [24] Q. Yu and C. Sechen, "Approximate symbolic analysis of large analog integrated circuits," Proc. IEEE Int. Con! Computer-AidedDesign, San Jose, CA, pp. 664-671, 1994. [25] P. M. Lin, Symbolic Network Analysis. Amsterdam: Elsevier, 1991. [26] S. P. Chan, Introductory Topological Analysis of Electrical Networks. New York: Holt, Rinehart and Winston, 1969. [27] H. N. Gabow, "Two algorithms for generating weighted spanning trees in order," SIAM J. Computing, vol. 6, no. 1, pp. 139-150, March 1977. [28] D. Cheriton and R.E. Tarjan, "Finding minimum spanning trees," SIAM J. Computing, vol. 5, no. 4, pp. 724-742, December 1976. [29] Q. Yu and C. Sechen, "Efficient approximation of symbolic network functions using matroid intersection algorithms," Proc. IEEE Int. Symp. Circuits Syst., Seattle, WA, pp.2088-2091, 1995. [30] E. L. Lawler, Combinatorial Optimization: Networks and Matroids. New York: Holt, Rinehart and Winston, 1976. [31] P. Wambacq, F. V. Fernandez, G. Gielen, W. Sansen, and A. Rodriguez-Vazquez, "Efficient symbolic computation of approximated small-signal characteristics of analog integrated circuits," IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 327-330, March 1995. [32] J. Vlach and K. Singhal, Computer Methodsfor CircuitAnalysis and Design, 2nd Ed. New York: Van Nostrand Reinhold, 1994. [33] P. Wambacq, F. V. Fernandez, G. Gielen, and W. Sansen, "Approximation during expression generation in symbolic analysis of analog ICs," Alta Frequenza, vol. 5, no. 6, pp. 336-343, November 1993. [34] S. Skelboe, "Computation of rational interval functions," BIT, vol. 14, pp. 87-95, 1974. [35] G. Gielen, P. Wambacq, and W. Sansen, "Symbolic approximation strategies and the symbolic analysis of large and nonlinear circuits," Proc. IEEE Int. Symp. Circuits Syst., Singapore, pp. 806-809, 1991. [36] Jer-Jaw Hsu and C. Sechen, "Low-frequency symbolic analysis of large analog integrated circuits," Proc.IEEE Custom Integrated Circuits Conf., pp. 14.7.1-14.7.5, 1993. [37] Jer-Jaw Hsu and C. Sechen, "Fully symbolic analysis of large analog integrated circuits," Proc. IEEE Custom Integrated Circuits Conf., San Diego, CA, pp. 21.4.121.4.4, 1994. [38] Jer-Jaw Hsu and C. Sechen, "DC small signal symbolic analysis of large analog integrated circuits," IEEE Trans. Circuits Syst. I, vol. 41, no. 12, pp. 817-828, December 1994. [39] R. Sommer, E. Hennig, G. Droge, and E.-H. Horneber, "Equation-based symbolic approximation by matrix reduction with quantitative error prediction," Alta Frequenza, vol. 5, no. 6, pp. 317-325, November 1993.
7 Piet Wambacq Georges Gielen Willy Sansen Departement Elektrotechniek, ESAT-MICAS
Symbolic Analysis of Weakly Nonlinear Analog Integrated Circuits
Katholieke Universiteit Leuven Hever/ee, Be/gium
7.1. INTRODUCTION In many applications of analog integrated circuits, one is only interested in the circuits' steady-state behavior in response to a sinusoidal excitation or a combination of such excitations. Indeed, many circuit aspects are easier to characterize in the steady state. This is partially due to the fact that an extremely large class of analog integrated circuits can be approximated very well by a linear system. Because sinusoidal functions are eigenfunctions of linear systems, the latter ones can be easily characterized in terms of responses to sinusoidal excitations. Examples of quantities that characterize a circuit in the steady state are transfer characteristics like gain or impedances. These characteristics are also best measured when a circuit is in steady state. Most analog integrated circuits behave weakly nonlinearly. This means that when a sinusoid or a combination of sinusoids is applied, some small unwanted signals occur that distort the wanted output signal, which has the same frequency as the input signal. These unwanted signals occur at multiples of one of the input frequencies, in which case they are termed harmonics, or at frequencies that are linear combinations of the input frequencies, in which case they are denoted as intermodulation products. These unwanted signals are caused by the curvature of the characteristics of the devices of the circuit. This weakly nonlinear behavior contrasts with hard nonlinear behavior, where devices such as transistors switch between an on-state and an off-state. The nonlinear behavior, however, can also be useful in some applications. Oscillators and mixers explicitly rely on nonlinearities for suitable operation. The harmonics or intermodulation products characterize the amount of nonlinearity of a given circuit. Because sinusoidal signals and sums of sinusoids are frequently used as
179
180
Chapter 7
Symbolic Analysis of Weakly Nonlinear Analog Integrated Circuits
inputs, a sinusoidal steady-state analysis of weakly nonlinear circuits is certainly not restrictive. This analysis is carried out in the frequency domain. The familiarity of circuit engineers with linear systems has given rise to many useful insights and design rules for circuits that can be approximated by linear systems. Circuit engineers are able to derive closed-form expressions for characteristics of a linearized circuit, which they can interpret and use afterwards during the synthesis of the circuit. If the circuit or its simplified schematic is too large to analyze with hand calculations, they have to resort to a symbolic analyzer, but they are still able to reason to some extent about the linear circuit's behavior. On the other hand, the analysis and synthesis of circuits in which nonlinearities play a role are difficult. Indeed, for such circuits, just a few design rules exist in the analog design world. There are several reasons for this. First, circuit designers are trained to reason about linear systems, but not about nonlinear ones. Second, it is not easy to analyze nonlinear effects by hand calculations. The most studious designers use Taylor series, but this approach is only feasible in small circuits at low frequencies, with a very small number of non linearities. Usually, nonlinear effects are analyzed with a numerical circuit simulator, often requiring tedious simulations. Moreover, the simulation results give the circuit performance as a list of numbers, but they do not indicate the fundamental circuit parameters that determine the observed performance. As a result, circuit designers often do not know in which way a circuit can be improved in order to meet the specifications related to nonlinear behavior. This problem could be relieved if it were possible to automatically generate interpretable analytic expressions for weakly nonlinear behavior of circuits of practical size with many nonlinearities and with the inclusion of frequency effects. Apart from their usefulness for interpretation, such analytic expressions can also be used in a design automation system for analog circuits. In this chapter, we describe how closed-form expressions can be obtained for the nonlinear behavior of analog integrated circuits. In general, it is not possible to obtain closed-form expressions for a circuit's nonlinear behavior. Many techniques that are used to compute the nonlinear behavior numerically, such as the different variations on the harmonic balance method [I], cannot be used easily to obtain closed-form expressions. The reason is that such techniques use iterations. If iterations were to be performed symbolically, then-in the best case-they would yield large, uninterpretable expressions. However, several techniques exist to obtain approximate closed-form expressions. One of these techniques is the method of the describing function [2]. With this technique, it is possible to obtain closed-form expressions for a feedback system that contains an isolated static nonlinearity in the feedback loop. Because it is not possible in general to map an analog integrated circuit to such a feedback system, the method of the describing function is not used here. Better results can be obtained with the technique of Volterra series [3], [4]. With this technique, closed-form expressions can be obtained for systems that behave weakly nonlinearly. The nonlinearities must be described as polynomials. The output signal is written as a series, which can be broken down after the first few terms. The first term corresponds to the linear behavior of the circuit, the second one to the second-order behavior, and so on. The Volterra approach has proven to be very attractive for hand calculations of small transistor networks. Several studies of effects like intermodulation or harmonic distortion and cross-modulation in such circuits have been reported [3], [5]-[ 10]. Because Volterra kernels retain phase information, they are especially useful for
Sec.7.2
Characteristics of Weakly Nonlinear Analog Integrated Circuits
181
high-frequency analysis and for effects like AM to PM conversion. Volterra series give a general characterization of a nonlinearcircuit in the sense that once the Volterra kernels of a circuit are known, its output can be found for any input. For example, the response of a nonlinear system to noise can be studied with Volterra series [4], [11], [12]. The reported hand calculations of Volterra kernels were limited to small circuits only. In the 1970s an algorithm was developed for the numerical calculation of Volterra kernels in the frequency domain for larger nonlinear networks. The development of the original algorithm by Bussgang, Ehrman, and Graham [13] was granted by the U.S. Air Force for the analysis of their communication receivers. Later, this algorithm was generalized by Chua and Ng [14]. The algorithm allows us to efficiently compute the Volterra kernels of every voltage and current in a circuit by repeatedly solving a linear network. Because sets of linear equations need to be solved, it is possible to obtain closed-form expressions with the approach. From the knowledge of the Volterra kernels, the required harmonics and intermodulation products can be derived. Instead of first computing the Volterra kernels, out of which harmonics and intermodulation products are derived, these figures can be immediately calculated with a perturbation method that does not use Volterra series at all [15]-[ 17].The method leads to exactly the same results and is also limited to weakly nonlinear circuits. In Ref. [18], yet another derivation was developed that again leads to the same results and has the same limitations. The derivation is somewhat more intuitive than the other two mentioned. Moreover, for circuits with more than one input port, such as mixers, the method is simpler than (but equally as accurate as) the Volterra series approach. Indeed, for such circuits, Volterra kernels are tensors, which are not so easy to manipulate. Moreover, it is not necessary to compute all components of those tensors. The method described in this chapter only computes a few of those components, without explicitly using tensors or Volterra series. This calculation method, which is discussed in section 7.4, can be used for the symbolic analysis of circuit characteristics that are determined by weakly nonlinear behavior. These characteristics are discussed in section 7.2. When the calculation method is applied for the symbolic analysis of larger circuits, many precautions need to be taken to manage the complexity of the symbolic expressions. This issue will be discussed in section 7.5. Finally, in section 7.6, some examples are presented that illustrate that new
insights can be obtained from the interpretationof the automaticallygeneratedexpressions. The generated symbolic expressions contain the same small-signal parameters as the ones used in linear analysis, but they also contain parametersthat describe the nonlinear behavior. These parameters are discussed in section 7.3. In that section, nonlinearities are described with power series. This formalism is used by both the Volterra series approach and the calculation method of section 7.4. A complete transistor can be described as being composed of several nonlinearities. These nonlinearities can be described using the transistor model equations.
7.2. CHARACTERISTICS OF WEAKLY NONLINEAR ANALOG INTEGRATED CIRCUITS The definitions in this section are explained by looking at the output of a nonlinear analog circuit. This circuit is excited by one or more sources of the form A,.cos (ro.t) , (i = I, 2, ... ). The circuit can be a continuous-time analog integrated circuit that ideally
182
Chapter 7
Symbolic Analysis of Weakly Nonlinear Analog Integrated Circuits
operates in a linear way, or a circuit, such as a mixer, that is essentially nonlinear. For the latter class of circuits, some extra definitions are necessary.
7.2.1. One-Tone Definitions When a linear circuit is excited with a sinusoidal source with amplitude A 1 and frequency (01' then the output spectrum consists of a signal at (Oland it increases proportionally with A I. However, a real-life circuit is not linear: due to the nonlinear characteristics of the devices in the circuit, the output spectrum also contains signals at 2(O} , 3(O}, .... These signals, called second, third, and higher harmonics, originate from second-order, third-order, and higher-order behavior. When the input amplitude is sufficiently low, then the nth harmonic is caused by nth-order and lower-order. behavior. At high input amplitudes, higher-order behavior can also contribute to lower-order harmonics. These contributions are neglected in the circuits that are addressed in this chapter. Such circuits are denoted as weakly nonlinear circuits. 1 In weakly nonlinear analog circuits, the nth harmonic increases with the nth power of the input amplitude AI. In many analog circuits, the linear response is usually the wanted response, while a harmonic is unwanted. Therefore, it is common to denote the harmonics as distortion. The second and third harmonic distortion, HD 2 and HD 3, are defined as the ratio of the second and third harmonic, Vout (2(01) and Vout (3(01)' respectively, to the fundamental response Vout ((0]): (7-1)
(7-2)
For higher order, of course, the definitions are similar. Harmonic distortion figures are dimensionless. They are often expressed in percent or in decibels for a given input amplitude. The harmonic distortion figures are often used to characterize the general nonlinear behavior of a circuit, even if this circuit is not excited by a single tone in its application. The reason is that, compared with other figures that characterize the nonlinear behavior, harmonics can be computed and measured relatively easily.
7.2.2. Two-Tone Definitions Assume now that a nonlinear analog circuit is excited by two sources, A 1cos (0) 1t) and A 2 cos (0)2t). When A 1 and A 2 are sufficiently low, then the output spectrum contains two signals above the noise floor at the fundamental frequencies (Oland (02 ' due to the circuit's linear behavior. Because for linear behavior the superposition principle is valid, the two excitations do not produce any interfering signals. However, when A 1 and A 2 become larger, then, apart from the harmonics of (01 and (02' interference signals grow 1A
definition of weakly nonlinear behavior that is mathematically better founded can be given in terms of Volterra series. See Ref. [4].
Sec. 7.3
Power Series Description of Basic Weak Nonlinearities
183
above the noise floor. These signals are due to the simultaneous application of the two excitations. They are seen at the frequencies l±moo in which m and n are integers, t±noo21, and they are called intermodulation products. Intermodulation products that occur at all frequencies for which Iml + Inl =k, are called kth-order intermodulation products. For example, second-order intennodulation products occur at 0 Hz and IOOt±OO2', whereas third-order intermodulation products occur at 12oot±oo21 and 12oo2±oot l. When the input amplitudes are sufficiently small, the intermodulation products of order n are caused by nth-order behavior and lower-order behavior. For analog circuits such as amplifiers, the intermodulation products are usually unwanted. Therefore, they are termed intermodulation distortion. When the input amplitudes A t and A2 are taken as equal, then the second-order intermodulation distortion 1M2 and the third-order intermodulation distortion 1M3 are defined as the ratio of a secondor third-order intermodulation product to the fundamental response. For circuits such as mixers, the wanted signal is not the linear response, but the second-order intennodulation product at the sum or difference frequency, while higher-order intermodulation products and all harmonics are unwanted. Indeed, an ideal mixer performs a frequency translation from low frequencies to high frequencies, or vice versa, by combining an input signal with a local oscillator signal. The conversion gain of a mixer is the ratio of the amplitude of the wanted second-order intermodulation product at the output to the amplitude of the sinusoidal input signal. It is important to note that the conversion gain is proportional to the amplitude of the local oscillator, at least if the mixer behaves weakly nonlinearly.
7.3. POWER SERIES DESCRIPTION OF BASIC WEAK NONLINEARITIES 7.3.1. Set of Basic Nonlinearities The devices most commonly used in analog integrated circuits are transistors, resistors, capacitors, and diodes. In circuit analysis, those devices are described using an equivalent circuit. This equivalent circuit can be as simple as one circuit element (e.g., one resistor), or it can be quite complex. Generally, the elements of such equivalent circuits are nonlinear. All nonlinear elements in these equivalent circuits can be represented as voltage-controlled nonlinearities, which means that the current through the nonlinearity is expressed as an algebraic function of one or more controlling voltages. In the case of a nonlinear capacitor, a charge is described as a function of a voltage. For general analog circuits or for macromodels, some current-controlled devices may be required, but they are not considered here. When a circuit that behaves weakly nonlinearly is excited, then this corresponds to small excursions around the quiescent point of the different nonlinearities in the circuit. Such excursions can be described as power series of the algebraic function that describes the nonlinearity. When the excursion is small enough, then this power series can be broken down after the first few terms. For the analysis of weakly nonlinear analog integrated circuits, four voltage-controlled nonlinearities are of interest: a nonlinear conductance, a nonlinear transconductance, a nonlinear capacitance, and a nonlinear current source, depending on several controlling voltages, often indicated as a multidimensional transconductance.r They are depicted in Fig. 7.1. These nonlinearities are referred to as the basic nonlinearities. Their descriptions are given in subsequent sections. In section 7.3.6,
184
Chapter 7
Symbolic Analysis of Weakly Nonlinear Analog Integrated Circuits
I
--o (v+ _ 'rT ~_+l i = f(v)
(v~ ! i = f(v)
--o
j
(a) I
(~~ (:~ ~ (c)
j
(b) i
= f tu, v)
(v
~! = i
f(v)
dl)
j
Figure 7.1 The basic nonlinearities used for the analysis of the weakly nonlinear behavior of analog integrated circuits.
nonlinear equivalent circuits of a MOS and a bipolar transistor are presented. These contain several basic nonlinearities.
7.3.2. Nonlinear Conductance and Transconductance For a nonlinear conductance or a transconductance, the current through the element, i ou7
= II (vCONTR (t» = II (VCONTR + vcontr(t» =
I, (V CONTR)
+
1
ak
L [i-k l l (v (t» 00
k
=I
'av
k
. vcontr(t)
(7-3)
v = VCONTR
The first term in Eq. (7-3) is the quiescent term. The second term in Eq. (7-3) is a power series representing the ac part of the current. When the analysis of a circuit that contains a nonlinear conductance is limited to first-, second-, and third-order nonlinear behavior, then the power series in Eq. (7-3) can be broken down after the third term. Defining the following coefficients, (7-4)
(7-5) v
= VCONTR
2 Although the term transconductance is used, one of the controlling voltages can be the voltage over
the element itself.
Sec. 7.3
185
Power Series Description of Basic Weak Nonlinearities
leads to the expression of the ac current
.
I
() () K out t =gl· v contr t + 2g]
() K 3 () contr t + 3g] ·v contr t
·V 2
+ ...
(7-6)
In this expression, vcon, t (t) denotes the ac value of the controlling voltage. For a conductance this is the voltage over the element, while for a transconductance this is an ac voltage elsewhere in the circuit. The coefficient of the first term in the power series (7-6), g I' is the small-signal (trans)conductance of the linearized element. The coefficients in the
and K 3 ,are, respectively, the second- and third-order second and third term, K 2 g] - g] coefficients that describe the nonlinear element. The subscript for K and K is the symbol 2
3
that represents the linearized element. This convention will be followed for the other basic nonlinearities as well. Note that the units of the coefficients g l' K 2 ,and K 3 are NY, 2 3 . g) g) NY ,and NY-, respectively. -Asan example, consider the simplified model of the collector current iC of a bipolar transistor:
. = Is 'e
exp [V~ ] BE
(7-7)
in which 1.1ij' vBE' and Vt are the transistor saturation current, the base-emitter voltage, and the thermal voltage, respectively. The first derivative of ie with respect to v BE is the transistor's transconductance gm' and one obtains for the first-, second-, and third-order coefficients
gm
Ie
=V
(7-8)
t
Kng
gm
Ie
m
-= - - = - \/,-1 n!V;
For a quiescent current of 1 rnA and with V
K2
gm
=0.751
2
NY ,and K3 gm
=9.70 NY
3 t
n!
(7-9)
t
=0.0258 V, one
obtains g
.
m
=0.0387 NY,
7.3.3. Nonlinear Capacitance The capacitors used in analog integrated circuits can be described with a nonlinear relationship between the charge q OUT on the capacitor and the voltage over the capacitor: qOUT(t) =!2(veoNTR(t)) =!2(VCONTR+vcont,(t))
a
00 1 k =!2(VeONTR) + Lki-k!2 V(t)
k- 1 -
·av
k
·vcont,(t) v
= VCONTR
(7-10)
186
Chapter 7
Symbolic Analysis of Weakly Nonlinear Analog Integrated Circuits
The power series in Eq. (7-10) represents the ac part of the charge on the capacitor. Defining first, second-, and third-order coefficients as
af2 (v) I
(7-11)
C =--
dV
1
K
" C]
=
v = VCONTR
1
a'12 (v)
n!
dV"
(7-12) v = VCONTR
the ac part of the capacitor charge is written as qout = C 1 . vC ontr (t) + K 2
C]
2 . vCOil (t) + K 3 tr
3 . vcon (t) + ... tr
C]
(7-13)
In this equation, C 1 represents the small-signal value of the linearized element. The units for C , K" I
.... c]
2
, and K3
-c]
are, respectively, F, FN, and FN . The ac current io ut (t) through
a capacitor is found by taking the time-derivative of the ac charge on the capacitor:
i
ou
t ( t)
= dd
t
(c
2
v (t) + K".... C . v (t) + K 3C . v 3 (t) + ...)
1.
]
(7-14)
]
As an example, consider the simplified model of the diffusion capacitance between the base and emitter of a bipolar transistor. The nonlinear relationship between the capacitor charge QD and the base-emitter voltage vBE is given by
QD = "tFi e = "tFIsex p(
v~; J
(7-15)
in which r F is the transit time. Noting the first derivative of the charge with respect to the controlling voltage as CD' one obtains the following coefficients: CD
K
"cD
'tFl c
=V
t
= 'tFg m
(7-16)
'tFg m
=
(7-17)
.,n - 1
n! V t
For a collector current of 1 rnA and a forward transit time of 50 pS, the following values are
obtained
at
T
= 300K:
CD
= 1.94pF,
K2
cD
= 37.6 pFN,
and
Sec. 7.3
187
Power Series Description of Basic Weak Nonlinearities
7.3.4. Two-Dimensional Transconductance For a two-dimensional transconductance, the current iOUT (t) through a conductance is a function!] of two voltages UCONTR and vCONTR, which can be expressed in terms of ac values using a two-dimensional power series expansion around the quiescent point (U CONTR' V CONTR,JOUT):
iOUT (t) =!3 (UCONTR (t)
,vCONTR (t»
=!3 (U CONTR + Ucontr (t), =
=
V CONTR + V contr (t»
=
!3 ( UCONT.R' VCONTR) + m
m=l n=O
ar1
(7-18) (u, v)
aunavm - n
= UCONTR v = VCONTR
u
n U contr (t)
In-n V contr (t)
n!
(m-n)!
The ac part of the current corresponds to the second tenn of Eq. (7-18), which is a two-dimensional power series. This series can be split into three series iI' ;2 and ;3' each corresponding to a part of the total ac current. The first two series, ; 1 and ;2' contain powers of one single voltage and so they are similar to the series described in section 7.3.2: 2
3
; 1 = g 1 . ucontr (t) + K 2g . ucontr (t) + K 3g . ucontr (t) + ... 1 1
(7-19)
and (7-20) The third series, ;3' contains nothing but cross-terms, which are terms that contain a nonzero power of both Ucontr and vcontr:
(7-21)
The meaning of the subscripts in the coefficients defined here is as follows. Suppose that the first-order derivative of the total current with respect to U and v are, respectively, g I and Then, a coefficient like K , with m and j positive integers and m > j , mj K1&(m-j)K2 means
g2'
(7-22)
188
Chapter 7
Symbolic Analysis of Weakly Nonlinear Analog Integrated Circuits
. If j or (m - j) are equal to 1, then they are usually omitted as a subscript, as in K 2 The derivatives are evaluated for u = UCONTR and v = VCONTR' g 1&g2
In order to clarify these definitions, consider the simple equation for the collector current of a bipolar transistor including the Early effect:
'c = Is exp[ in which V
AF
v~;
II ~::) +
(7-23)
denotes the Early voltage for the forward active mode of operation.
The first derivatives with respect to the controlling voltages vBE and vCE are, respectively, the transconductance g and the output conductance g . Using these symbols, the ac value of the collector current ~n be written as the sum of a sgries containing powers of vbe only, a series depending only on Vee and a series with nothing but cross-terms:
i = g . Vb + K 2 e
m
+K3
e
3
go
gm
. vee
2 . Vb
e
+ K3
+ .. · +K2
gm
3 . Vb
&
gm go
e
+ ... + g . vee + K2 0
.v be· v ee
+K32g
m
go
.v
2 ee
2 &g · v be· vee
(7-24)
0
in which the time-dependency has been omitted for clarity. The coefficients K 2 and K 3 have already been discussed earlier in the gm
gm
example of the one-dimensional collector current (see section 7.3.2). The coefficients
K2
and K3 are zero because the simple model for the collector current assumes a go linear dependency on the collector-emitter voltage difference. The coefficients of the go
cross-terms in Eq. (7-24) are given by
K
K K For an Early voltage V K 2g &g m
AF 2
0
= 0.00774 A/V
gm
2 g &g m 0
32g &g m 0
3g &2g m 0
= VA F =
gm 2VtVA F
= 0
(7-25)
(7-26) (7-27)
of 50 V and a collector current of 1 rnA, one finds and K 3 2g m&go
= 0.0152 A/V 3 .
Sec. 7.3
189
Power Series Description of Basic Weak Nonlinearities
7.3.5. Three-Dimensional Transconductance A three-dimensional transconductance is a current source whose value is a function
/4 of three voltages u(t), v(t), and w(t).' Using a power series expansion around the quiescent value, lOUT
the
total
current
can
be
split
into
a
quiescent
part
= /4 (U CONTR'VCONTR'WCONTR) and an ac part: (7-28)
iOUT(t) =/4(uCONTR(t),vCONTR(t), wCONTR(t))
= /4 (UCONTR + ucontr (t), V CONTR + vcontr (t), = /4 (U CONTR' k
V CONTR' W CONTR)
a
k-i [ k
L L L
k=l ;=0 j=O
a all'a .
U
I
.
W
k
- I - }./4 (u, v, w) , .
W CONTR
+ wcontr (t))
+
Jcontr (t)
i Ucontr (t) 0'
l.
0
O!
J.
k - ; -(t) j]
W contr
0
(k
-
'
I -
') 1 J .
In this series, the derivatives are evaluated for u = UCONTR' v = V CONTR' and w = W CONTR' The ac current can be split into distinct parts: first, there are three power series that only contain powers of one single voltage, which corresponds to a one-dimensional nonlinear conductance (see section 7.3.2). Next, there are three power series containing only cross-terms in exactly two voltages, similar to the series described in section 7.3.4. Finally, there is a power series that only contains cross-terms in three voltages at the same time. The latter series implies the introduction of the following coefficients:
K m · &k Jgl
(
g2 m-j-
k)
g3
am 1 1 1 = a,javaw . k m - J. - k/(u,v,w). J.-:-, . k-'. . ( m-J· k) , ·
(7-29)
When the positive integersj, k, or (m - j - k) are equal to 1, then they are omitted in • The meaning of the newly defined coefficients is the notation, as in K3 gl&g2&g3 illustrated with the simple model for the drain current of an n-MOS transistor in saturation.
Taking into account bulk effect and Early effect, the drain current is given by (7-30) with
VT = VTO+YlJvSB+2<'PF-J2<'PF)
(7-31)
and ~ is a shorthand notation for Kp x W/ L. The parameters Kp , A, "f, and CIlF are SPICE parameters whose meaning is explained in Refs. [19] and [20]. The first derivatives of the current with respect to the controlling voltages vGS, vSB' and vDS are, respectively, 8m' 8mb' and go' Using these symbols, the ac value of the drain current is given by
190
Chapter 7
Symbolic Analysis of Weakly Nonlinear Analog Integrated Circuits
In this equation, the terms of the powers ofvsb only are negative. The reason is that the bulk transconductance gmb is usually represented as a controlled source flowing from the source to the drain, which is opposite to the direction of the source gm . V s« This yields a positive value for gmb. Hence, gmb is the first-order derivative times -1. For consistency, the and K 3 are adjusted in the same way. Equation (7-32) reveals that coefficients K 2 gmb gmb a description of the second- and third-order nonlinearity of the three-dimensional drain current requires 16 second- and third-order coefficients. However, for the simple MOS model of Eq. (7-30), the coefficients that are computed by deriving twice with respect to VDS are zero because the current is linearly dependent on vDS' Also, coefficients obtained
by deriving three times with respect to vGS are zero because of the quadratic dependency. Table 7-1 lists the expressions for the coefficients from Eq. (7-32) that have been derived using the drain current model ofEq. (7-30). The table also includes numerical values for an n-MOS transistor. The parameters of this transistor are W = 10 urn, L = 3 urn, VGS = 1.46V, VDS = 1.92 V, VSB = 1.54 V, VTO = 0.9 V, Y= 0.3 V 5
In
-1
,2
Kp = 5 x 10- AlV2. Withthese parameters, a draincurrentof 6.80 JlA is found.
7.3.6. Weakly Nonlinear Transistor Models The different basic nonlinearities described in the previous sections can now be tailored together to construct nonlinear equivalent circuits for transistors. These are straightforward extensions of the linear equivalent circuits [20].
7.3.6.1. Bipolar Transistor The nonlinear equivalent circuit for a bipolar transistor is shown in Fig. 7.2. The ohmic resistors rc and rs are often considered as linear elements. With this equivalent
191
Sec.7.3 PowerSeries Description of BasicWeakNonlinearities
Table 7·1 The First-, Second-, and Third-Order Coefficients for the Description of the Nonlinear Drain (AC) Current, Using the Simple Square-Law Model. The Effective Threshold Voltage Vr, Evaluated for Vss =O.5V EqualsO.9aV. gm
K2
gm
K3
gm
gmb
5
~ ( 1 + A. VDS) (V GS - Vr)
3.75 x 10- A/V
~ (1 + AV 2 DS)
5.18 x 10- A/V
0
O.OA/V
5
~ (1 + A. VDS) (V GS - Vr) 'Y
2 (2<1>F+ VSB)
1/2
t
6
3.76 x 10- A/V
K2
gmb
~'Y ( 1 + A. VDS)
VGS- VTO + 'Y ~ ) 3/2 8 (2<1>F+ VSB)
-9.40 x 10- A/V
K3
gmb
~'Y(l+A.VDS)t VGS-VTO+'Y~)
2.10 x 10- A/V
K2
go
K3
go
K2
gm&gmb
7
5/2
16(2<1>F+ VSB)
go
7
~
2A. (V GS - Vr)
2
7
1.24 x 10- A/V
0
O.OA/V
0
O.OA/V
~ (1 + A. VDS) 'Y
-1.04 x 10-5 A/
V
2 J2
F + VSB
K2 K2
gm&go
gmb&go
7
~A.(VGs-Vr)
6.88 x 10- A/V
~A.'Y(VGS- Vr)
-6.89 x 10- A/ V
8
2 J2 F + VSB
K3 K3
2g m&gmb
gm&2gmb
0 ~'Y(1 +A.VDS)
8 (2<1>F + VSB)
K
32g m&go
K3
gm&2go
O.OA/V
3/2
6
1.16 x 10- A/V
0
O.OA/V
0
O.OA/V
192
Chapter 7
Symbolic Analysis of Weakly Nonlinear Analog Integrated Circuits
Table 7·1 Continued
Pi..~ VGS-Vro+yJ2cJ)F)
K3
2g mb&go
8(2<1>F+ VSB)
K3
3/2
0
gmb&2go
K3
A/~
7
-1.90 x 10- A/~
2J2 F + VSB
CJ.L
B'
8
O.OA/~
~A'Y
gm&gmb&go
B
1.72 x 10-
C'
rc
C
ic
s E Figure 7.2 Nonlinear model of a bipolar transistor.
circuit, the dependency of the nonlinearities on their controlling voltage(s) can be described with the model equations. The values of the coefficients K2 and K3 are determined by taking second- and third-order derivatives, respectively, of the model equations. For a first-order model, such as the simple exponential relationship between the collector current and the base-emitter voltage, it was previously illustrated that fairly simple expressions arise for the different coefficients K 2 and K 3 . However, for more advanced models, very complicated expressions arise. Hence, it is more appropriate to keep the coefficients K 2 and K3 as a symbol and to reason with these values, just as designers reason with values of the first-order derivatives such as gm and go. If designers want to reason about nonlinear distortion then, obviously, they must be able to obtain accurate values for the coefficients K 2 and K 3, also for advanced models. Moreover, numerical values for K 2 and K 3 are also required in symbolic analysis, in order to approximate the expressions. Existing circuit simulators provide values for the current and its first-order derivatives, which are the small-signal parameters, but the higher-order derivatives are not computed. Therefore, dedicated routines have been developed to compute those higher-order derivatives. In these routines, the different derivatives are computed as a function of the bias voltages, the transistor dimensions, and the model parameters. In this way, the Gurnrnel-Poon model [21], [20] of a bipolar transistor has been implemented. The approach is also used for MOS transistors, as explained in the next section.
Sec.7.4
193
A Calculation Method for Harmonics and Intermodulation Products
7.3.6.2. MOS Transistor The nonlinear equivalent circuit of a MOS transistor is depicted in Fig. 7.3. Three nonlinear elements occur in this model: the nonlinear drain current, which is a three-dimensional nonlinearity, and two junction capacitors, C sb and Cdb. The oxide capacitors are assumed to be linear.
D'
G
s
rD
D
B
Figure 7.3 Nonlinear model of a MOS transistor.
Just as with the bipolar transistor, the nonlinearities in this equivalent circuit can be described according to different sets of model equations, ranging from the simple square-law model to the more advanced models [19]. With the approach discussed in the previous section, the MOS models of levels 1, 2, and 3 [19] have been implemented.
7.4. A CALCULATION METHOD FOR HARMONICS AND INTERMODULATION PRODUCTS In this section, a method is presented to calculate harmonics and intermodulation products in a weakly nonlinear analog circuit. The method computes the responses in increasing order by repeatedly solving a linear network, namely the linearized equivalent of the weakly nonlinear circuit. First, the linearized circuit is analyzed with the external excitation(s) applied. For higher orders, the same linearized circuit is solved with other inputs. The value of these inputs depends on the lower-order responses. The derivation of the method is given in Ref. [22]. The method is only valid for the analysis of the weakly nonlinear behavior. A calculation method for harmonics and intermodulation products has been reported several times either based on Volterra series [13], [14] or using a perturbation method [15]-[ 17]. For multiple-input systems, however, the use of Volterra series becomes awkward because tensors are required [4]. Although it is possible to get rid of tensor manipulations by the use of the Kronecker product [23], an extension of the calculation method, explained earlier in terms of Volterra series for multiple-input systems, is complex. In this case, the required responses are better computed with the method described here, which circumvents the use of Volterra series.
194
Chapter 7
Symbolic Analysis of Weakly Nonlinear Analog Integrated Circuits
The calculation method will be explained with the network shown in Fig. 7.4, which contains nonlinear circuit elements, including a nonlinear transconductance. The explanation given here will focus only on that transconductance. Other basic voltage-controlled nonlinearities are handled in the same way. The network is excited by two different current sources iin} and iin2 ' applied at two different ports. The network also contains linear elements, including capacitor C. The nonlinear transconductance is controlled by the voltage difference between nodes i and j. The nonlinear relationship between the controlled current i} and the controlling voltage is given by
= g'" (v.-v.) I }
i}
+K2
s.; (v.-v.) I }
2
+K3
gm
(v.-v.) I
3
}
+ ...
(7-33)
in which the time-dependency has been omitted for simplicity. The excitations are given by .
t . } (t) In
1
(joo)!)
= Re
joo)!
= -I. 2 In } e
I.In } e
1 * -joo)! + -I. 2 In } e
(7-34)
and .
t In . 2 (t)
1
joo2!
= 2-I.In 2 e
1 * -joo2! + -I. 2 In 2 e
(7-35)
Under steady-state conditions, the ac-part of every node voltage v (t) can be regarded as x being composed of a sum of harmonics and intermodulation products: +00
vx (t) =
L
I ( Re
V
)(mro\+nro 2
x.m;n e
)1)
m=O n=O
=
+00
m =-00
n =-00
1 2
(7-36)
+00
L L
V
j (moo) + noo ! 2)
x,m,n e
in which Vx,m,n is the phasor of the voltage at node x at the frequency moo} + nOO2 and Vx,m,n = Vx,-m,-n *
k
iinl
s
Ie T
i
--0+
p
m
t, =
!(Vi -
iin2
Vj
--oj
q
Figure 7.4 A general nonlinear network.
n
Sec.7.4
195
A Calculation Method for Harmonics and Intermodulation Products
7.4.1. First-Order Responses The first-order response corresponds to the response of the linearized equivalent of the circuit of Fig. 7.4. The linearized circuit is shown in Fig. 7.5. The computation of the node voltages due to the excitation i;nl yields the complex amplitudes Vx,I,O' whereas the responses due to the excitation i;n2 yields the complex amplitudes Vx,o, I. The complex amplitudes Vx,-I,O and Vx,O,-1 are obtained similarly. One will find, of course, that Vx,-I,O is the complex conjugate of Vx,I,O.
k
;inl
s
1 T
i
---0+
p
c
m
gm(Vi.l. O - Vj.l. O)
---oj
q
n
Figure 7.5 The linearized equivalent of the network of Fig. 7.4 used to find the first-order responses to
iin1'
7.4.2. Second-Order Responses As already explained in section 7.2, the second-order behavior of a weakly nonlinear circuit excited by sinusoidal signals at 001 and ~ yields signals at 0 Hz, 2001' 2~, and at 100 1 ± 00 21. Assume that the response of the circuit at the sum or difference frequency 100 1 ± 00 21 must be known. In the previous section, it was seen that the retrieval of coefficients of exp(±jool t) and exp(±j002t) results in the knowledge of the phasors at the frequencies ±ool and ±~. These phasors are now used for the calculation of second-order harmonics and intermodulation products. In Ref. [22], it is shown that the voltages at 100 1 ± 00 21 can be computed as follows. The unknown node voltages are now Vx,I,±1 instead of Vx,1 ,0' and the frequency is
100 1 ± 00 21. The external excitations are removed. Instead, a new excitation i NL
K2 g
is
applied. This is a fictitious current source, applied in parallel with the transconductancemg m, which is the linearized equivalent of the nonlinear transconductance. The orientation of the source is from the positive node of the nonlinearity to the negative one. The circuit that corresponds to this situation is depicted in Fig. 7.6. The value of the current source is determined by the second-order coefficient of the nonlinearity and by the first-order response at the controlling nodes due to the excitations i;n I and i;n2' respectively. When other nonlinearities are considered, then additional current sources need to be considered, one for every nonlinearity. Their value depends on the kind
196
k
Chapter 7
s
1 Ie
Symbolic Analysis of WeaklyNonlinear Analog Integrated Circuits
i
--0+
p
m
q
n
i NL2gm
--oj
Figure 7.6 Thelinearized equivalent of the networkof Fig. 7.4 excited by i
NL K2
to find the responses at 8m
00 ± 00 , 2 1
Table 7-2 Nonlinear Second-Order Current Sources for the Basic Nonlinearities to Compute Second-Order Intermodulation Products at 00I + 002 and Second Harmonics at 2001' The Controlling Voltages Are vi for the Nonlinear (Trans)Conductance and the Nonlinear Capacitor and vi and Vj for the Two-Dimensional Conductance.
Type of nonlinearity
Nonlinear current source for response at 1001 ± 0021
(Trans)conductance
Nonlinear current source for response at 200 1 K2
K 2g1Vi, 1,0 Vi, 0, I
--..!l (V. 2
Capacitor
Two-dimensional conductance (only cross-terms)
jlOOI
± 0021 K 2 c (Vi, 1,0 Vi, 0, 1) I
K2
+
K2
V
i,I ,O j,O, 1
g\&g2V 2
joo 1K 2C ( Vi I
gl&g2V 2
1,1,0
+
K2
1 0)2
"
gJ&g2V 2
)2
V
i,I,O j,I ,O
V
i,O, 1 j , 1,0
of basic nonlinearity . Table 7-2 lists the value of the current source for the different basic nonlinearities defined in section 7.3. Because these excitations are applied to compute the circuit's second-order nonlinear behavior, they are often called nonlinear current sources
oiorder 2. The complex amplitudes of voltages Vx in the circuit at frequency 1-00 1=f0021, denoted as Vx ,- I ,; I ' are computed from a set of equations that is generated by taking the coefficients of exp U (-00 1=f002) t) in the Kirchhoff equations. When this set is solved, one will find that Vx .- 1,; 1 = Vx ,I,± 1*. Other second-order responses are determined in a similar fashion but with other values for the nonlinear current sources. The values of the sources that have to be applied for the computation of the harmonic at 200I are given in the right-hand column of Table 7-2. The method to compute the second-order responses can be interpreted as follows: every second-order nonlinearity in the circuit combines two first-order responses of its
Sec.7.4
A Calculation Method for Harmonics and Intermodulation Products
197
controlling voltage(s) to produce a second-order signal. This signal, at frequency 1col ± co21, propagates through the rest of the linear circuit to the output and to all other voltages and currents in the circuit, yielding the demanded second-order responses. Interactions of nonlinearities do not have to be considered here because these yield responses of an order higher than 2.
7.4.3. Higher-Order Responses For the computation of responses of order 3, the same procedure leads to the solution of the same linearized network that is excited now with nonlinear current sources of order 3. Their value depends on first- and second-order responses as well as on the coefficients K 2, K 3, ... of the power series expansion for the nonlinearity. The expressions for the nonlinear current sources for the computation of the third harmonic of CO2 are given in Table 7-3. Table 7·3 Nonlinear Third-Order CurrentSources for the Basic Nonlinearities to Compute the Third Harmonic at 3~. The Controlling Voltages Are Vi for the Nonlinear (Trans)Conductance and the Nonlinear Capacitor, Vi and Vj for the Two-Dimensional Conductance, and vit Vj and vk for the Three-Dimensional Conductance.
Type of nonlinearity
Nonlinear current source for response at 3 co2
(Trans)conductance
K2gl V.I" 0 IV.I" 0 2+!K 1 4 3gl ~o I, ,
Capacitor
Two-dimensional conductance (only cross-terms)
Three-dimensional conductance (only cross-terms)
7.4.4. Interpretation of the Results The calculation method explained earlier presents the results in terms of coefficients K 2 and K 3, which are quantities that do not sound familiar yet to circuit engineers. However, if designers want to reason about nonlinear circuits, they have to become acquainted with these parameters. Just as with small-signal parameters, the K2' s and K3' s can be expressed in terms of bias voltages or currents, model parameters, and physical constants. Some simple examples of such expressions have already been presented in section 7.3. More accurate values for the K 2' s and K 3' s must be computed from the model equations.
198
Chapter 7
Symbolic Analysis of Weakly Nonlinear Analog Integrated Circuits
Using the calculation method explained in this section, the harmonics or intermodulation products of order p > 1, at the frequency l±mco1±nco21with Iml +Inl = p, are computed as a sum of contributions: #nonlinearities
L
(7-37)
k=l
The sum is taken over all k nonlinearities. In this equation, iNL is the nonlinear current Pk source of order p for nonlinearity k and TFi
NLPk
~
output denotes the transfer function
from the applied nonlinear current source to the output. The amplitudes of the external excitations have been taken equal to 1 here for simplicity. The formulation of nonlinear responses in the form of expression (7-37) makes reasoning about distortion possible. Indeed, the transfer functions that determine the current sources on one hand, and the transfer functions from the current sources to the circuit's output on the other hand, can be analyzed either numerically or symbolically and interpreted. Moreover, because the current sources are applied in a linear network, the effect of every current source, corresponding to one single nonlinearity, can be studied apart from the other ones, just as with a noise analysis. However, the different contributions of the current sources are complex numbers, whereas in noise analysis the contributions are positive real numbers. This means that distortion sources can cancel, which is not the case for noise sources. Moreover, the nonlinearities can interact, despite the one-to-one correspondence between a nonlinearity and a nonlinear current source. Consider, for example, the third-order nonlinear current sources. Looking at Table 7-3, one can see that their value is determined not only by the coefficients K 2 and K3 of the nonlinearity under consideration, but also by the second-order response at the controlling voltage. This response is in turn determined by the effect of all second-order coefficients K 2 . This interaction prevents the different contributions from being associated with only one nonlinearity. Hence, when this method is used for symbolic analysis, such an interaction can complicate the interpretation of the symbolic expressions. Fortunately, most contributions can be neglected in practical transistor circuits, so that after approximation very few contributions are retained in the result and very often little interaction occurs. This will be illustrated with the examples in section 7.6.
7.4.5. Factorization of Denominators The higher-order responses are determined by repeatedly computing responses in the same linear network. Hence, the system determinant is always the same, apart from the value of the frequency variable. Because the expressions of the nonlinear current sources depend on lower-order responses, it is not difficult to see that the denominator of the value of a nonlinear current source is a combination of products of system determinants, possibly evaluated at a different frequency. In this way, it can be shown that the denominator of a second-order response at 1<0 1 ± <0 21 is det(1<0 1 ± <0 21) det( <0 1) det( CO2) , in which det() is the system determinant. Similarly, it is found that the denominator of any second harmonic at 001 is (det ( 001) ) 2 det (200 1) . This reasoning can be extended to order 3. For example,
Sec. 7.5
Simplified Symbolic Computation of Harmonics and Intermodulation Products
199
for the calculation of third harmonic responses at 300 1, the common denominator is given 3 by det (2 ro1) (det ( ro1)) .
7.5. SIMPLIFIED SYMBOLIC COMPUTATION OF HARMONICS AND INTERMODULATION PRODUCTS From the previous section, it is clear that the numerator of every harmonic or intermodulation product can be computed by combining the numerators of several transfer functions, either from the input to a controlling voltage or from a nonlinear current source to the output or to another controlling voltage. The final result is a nested expression, which can be expanded afterwards. These transfer functions can be calculated with any symbolic analysis technique discussed in chapter 2. However, huge expressions are generated in this way, because a practical circuit contains a lot of basic nonlinearities and each nonlinearity gives rise to a nonlinear current source, whose expression can already be quite complicated. In order to manage this complexity, a two-step simplification procedure is used. In the first step, described in section 7.5.1, numerical computations are used to eliminate the nonlinearities that are unimportant in a frequency .range of interest. The elimination of a nonlinearity corresponds to the linearization of a component. After this first simplification step, a symbolic expression is computed approximately with the nonlinearities that have not been eliminated. This is described in section 7.5.2.
7.5.1. Elimination of Unimportant Nonlinearities The different contributions to the response at the output are first calculated as a function of frequency. This means that every circuit parameter is treated as a number, whereas only the complex frequency is treated as a symbol. For this kind of computation, efficient methods exist, such as the polynomial interpolation method [24], which is explained in chapter 2. The advantage of keeping the frequency as a symbol is that the network functions can be evaluated afterwards for any frequency variable. This is useful for the computation method explained in section 7.4. There it is seen that 'the same numerator or denominator of a network function is used several times, except that the frequency variable is different. For example, the numerator of the transfer function from a nonlinear current source to the output is used for all orders higher than 1, except that the frequency variables are different. Hence, if numerators and denominators of network functions are computed as a function of a frequency variable, then this variable is easily adapted to the order under consideration. In this way, results are reused maximally. The total response is also calculated as a function of a frequency variable by making the sum of the different contributions of the different basic nonlinearities (see Eq. (7-37)). Now that the contribution of every nonlinearity to the total response is computed, it can be checked whether there are any nonlinearities that give a negligible contribution. If nonlinearities can be neglected, then they can be eliminated. The details of the elimination process are described in Ref. [18]. The elimination process is controlled by a user-defined error that should not be exceeded in a frequency range of interest. After the elimination process, the coefficients K2 or K 3 (depending on the response that is computed) of the nonlinearities that give an insignificant contribution are set to zero. Now, a fully symbolic analysis can be performed with the few remaining nonlinearities.
200
Chapter 7
Symbolic Analysis of Weakly Nonlinear Analog Integrated Circuits
In practical analog integrated circuits, the elimination process can reduce the number of nonlinearities. For instance, all nonlinearities from junction capacitors can usually be discarded. This means that the fully symbolic analysis that is carried out afterwards only has to take into account very few nonlinearities. In some cases, however, especially when the distortion is very low, it is impossible to eliminate many nonlinearities, such that the interpretation of the results is difficult. This will be illustrated with the examples in section 7.6. The intermediate results obtained after this elimination step, namely a knowledge of the significant nonlinearities, provide information that is already much more valuable than simulation results obtained from SPICE-like simulators with the .DISTO command, which do not select the significant nonlinearities at all. This knowledge, together with a plot of the different contributions and the total response as a function of frequency, can already yield enough insight such that the user does not need a symbolic analysis anymore. This is also illustrated in the examples.
7.5.2. Generation of the Approximated Symbolic Subexpressions Equation (7-37) reveals that the expressions for the weakly nonlinear behavior of the circuit are nested: the numerators of the different involved network functions can be computed either with flat or hierarchical analysis but they are always combined to a hierarchical expression. In order to simplify the top expression, an approximation algorithm for nested expressions is required, such as the one described in Ref. [25] and discussed in chapter 6.
7.6. EXAMPLES In the following examples, the approach explained previously is used to generate closed-form expressions for the weakly nonlinear behavior of a source follower, a Miller-compensated operational transconductance amplifier (OT A), and a double-balanced mixer.
EXAMPLE 7.1-S0URCE FOLLOWER In this example, the third harmonic at the source of transistor M I in the source follower of Fig. 7.7 is computed. If the square-law model for the transistor is used and bulk effect and parasitic capacitances are neglected, then it is easy to compute that the only contribution to the third harmonic comes from the second-order nonlinearity, corresponding to the coefficient K 2 . This is now checked with a more accurate computation using the method K m
explained in the previous sections. The transistor is represented by the nonlinear equivalent circuit of Fig. 7.3. For third-order nonlinear behavior, this model gives rise to 20 coefficients K 2 and K 3 . For the elimination step explained in section 7.5.1, as well as for the approximation of the symbolic expressions as explained in section 7.5.2, numerical values for the different nonlinear
Sec.7.6
201
Examples
Figure 7.7 A source follower.
coefficients K2 and K3 are needed. These are computed first. In this example, the level 2 model is used for transistor MI. The sizes of the transistor, together with the most important model parameters, are listed in Table 7-4. The meaning of these parameters is explained in Refs. [19] and [20]. The values of second- and third-order coefficients for transistor M 1 are given in Table 7-5. The bias voltages as well as the values for the model parameters that are used both in levelland level 2 are the same as the parameters that are used in Table 7-1 for a transistor modeled with the level 1 equations. In this way, the higher-order derivatives obtained with levelland level 2 model equations can be compared. We see that the Table 7-4 Sizes and Model Parameters for Transistor M1 in the Source Follower of Fig. 7.7
W
20Jlm
Area source
100(Jlm)2
L
10Jlm
Perimeter drain
40Jlm
Area drain
lOO(Jlm)2
Perimeter source
40Jlm
VTO
0.9V
MJSW
0.33
KP
50 X 10-6AIV2
JS
103Alm2
y
0.3Vl/ 2
TOX
42.5 X 10-9m
PHI
0.7V
NFS
1011cm-2 y- l
CGSO
1.76 X 10-lOFlnz
LD
Om
CGDO
1.76 X 10-lOFlm
MJ
0.5
CJ
0.7 X 10-4F1nz2
UCRIT
I04Vlcnz
CJSW
3.9 X IO-lOFlm
A
O.OI9V- 1
202
Chapter 7
Symbolic Analysis of Weakly Nonlinear Analog Integrated Circuits
Table 7·5 Computed Numerical Values for the Transistor M1 in the Source Follower of Fig. 7.7. Level2 Model Equations Are Used. The Bias Voltages' Are VGs =1.46V, VDS =1.92V, and Vas= -1.5.
iD
6.16 x 10-6A
gm
3.42 x 10-5AIV
K2
gm
K3
gm
4.75 x 10-5AIV2 2.41 x 10-7AIV3 3.31 x 10-6AIV
gmb
K2
K3
gmb
gmb
-7.60 x 10-7AIV2 1.46 X 10-7AIV3
K2
& gm gmb
K2g K2 K
&g
m
32g m&gmb
K
3gm&2g mb
K
go
1.22 x 10-7AIV
K
K2
go
2.40 X 10-9AIV2
K
K3
go
4.74 X 10-llAIV3
&g
m
3g &2g m
1.12 x 10- 13F
6.74 x 10-7AIV2
Cgd
3.52 x 10- 15F
-6.52 X 10- 8AIV2
Csb
1.50 x 10- 14F
7.22 X 10-7AIV3
K2 C
-1.21 x 10- 15FIV
7.22 x 10-7AIV3
K3
2.39 x 10- 16FIV2
9.36 X 10-7AIV3
Cdb
1.33 X 10-8AIV3
K2
1.50 x 10- 8AIV3
K3
sb
0
0
32g mb&go 3gmb&2g
K3
<
0
gmb&go
K32g
-8.88 x 10-6AIV2
<,
Cdb Cdb
1.20 x 10- 14F -5.26 x 10- 16FIV 5.71 x 10- 17FIV 2
-1.29 X 10-9AIV3 o
gm&gmb&g(j
-1.75 X 10-7AIV3
deviations between the derivatives obtained with the different model equations increase with increasing order of the derivative. For example, the deviation in the value of the current obtained with levelland level 2 is 10%. For g mb' K 2
gm
'
and K 3
gm
'
the deviations
are 13, 24, and 44%, respectively. This indicates that for accurate distortion computations, less accurate model equations yield deviations that are larger than for computations of the linear behavior. A similar conclusion is valid when there are errors on the model parameters. For example, a deviation on the model parameter PHI of 10% gives a deviation in the value of the drain current of 0.3%, whereas the deviations for the first-, second-, and third-order derivatives are 1, 3, and 6%, respectively. The contributions of the different coefficients K 2 and K 3 to the third harmonic are shown in Fig. 7.8. For reference purposes, the values have been normalized to an input amplitude of 1 V. The total third harmonic is quite low for an amplitude of 1 V. This is
Sec. 7.6
203
Examples
-Iolal G- - O kl.gm&go.m l +---* kl.go.ml kl.gmb&go.ml ~ k2.gm b. m l
~ kl.gm&gmb.m l ~kl.csb.ml
" - $k2.cdb.m l ~k2.gm.m l
_ k 3.gmb.ml - - k3.go.ml ~ k3.2gmb&go.ml tr--Ak3.gm.ml - - - k3.gm&2go.ml G--8 k3.2gm&gmb.ml '--"k3.2gm&go.ml ~ k3.gm&2gmb.ml - - k3.cdb.ml ~ - - ..;.k3.gm&gmb&go.ml T T .csb.ml +--+ k3.gmb&2go.ml
1~
1~
l
1if 1if
1~
1~
freq. (Hz) Figure 7.8 The different contributions to the third harmonic at the source of transistor M1 from Fig. 7.7 normalized to an input amplitude of 1 V.
partially due to the feedback of the source follower . In this operating point, the loop gain, which is given by g
mM\
R E , equals 8.5. We see that the largest contribution comes from
the second-order coefficient K 2 . However, this contribution is not much larger than gm some other contributions. Moreover, the total third harmonic is smaller than the contribution of K 2 . This means that this contribution partially cancels with other gm contributions. With the preliminary elimination step, explained in section 7.5.1, we find that, for an allowed error of 10% on the real and imaginary part of the third harmonic up to I MHz, still nine of the 20 nonlinear coefficients must be taken into account. Consequently, the final symbolic result is quite lengthy: a fully expanded expression valid until I MHz contains 60 terms. This contrasts with the rough simplifications that are often made in reported hand calculations [26]. This example shows that, for very simple circuits, very complicated expressions can arise for the harmonics. We also see that, at low distortion
204
Chapter 7
Symbolic Analysis of Weakly Nonlinear Analog Integrated Circuits
levels, several nonlinearities play a role. In many circuits, however, only very few nonlinearities playa significant role, such that the preliminary elimination step can discard many more nonlinearities than in the case of the source follower. This is illustrated with the next example. EXAMPLE 7.2-MILLER-COMPENSATED OPERATIONAL AMPLIFIER
In this example, the second harmonic at the output of the CMOS two-stage Miller-compensated OTA (Fig. 7.9) in open loop is discussed. In a closed-loop configuration, the second harmonic is divided by « 1 + T Uro) ) 2 ( 1 + T (2jro) » , T being the loop gain [27]. The numerator of the exact expression, which consists of more than 1,000,000 terms, is not generated, because it would require too much memory and CPU time. Instead, the second harmonic is first calculated as a function of the fundamental frequency. The most important contributions to the total second harmonic are shown in Fig. 7.10. Clearly, only one nonlinearity dominates for frequencies below the gain-bandwidth product, namely the second-order nonlinearity K 2
gm
of transistor M 3. This
illustrates that the largest contributions to the nonlinear distortion at the output of an amplifier originate from the circuit elements close to or at the output where signal swings are large. Usually, one is not interested in a symbolic expression for a harmonic up to or beyond the GBW. Instead, a frequency interval from 10Hz to 10kHz is taken for this VDD
~VIN+
VIN-1
VI
cc VOUT
RL
VSS Figure 7.9 A CMOS Miller-compensated operational amplifier.
CL
Sec.7.6
205
Examples
--- - -- --G---£J
-----
o .-.--0 --------
v
+----+
- ----
10
total k2.gm&go.m2 k2.cdb.ml k2.go.m4 k2.gm&go.m3 k2.gm&go.ml k2.gm.m3 k2.gm.m2 k2.go.m2 k2.go.ml k2.go .m3 k2.gm.ml
3
freq. (Hz) Figure 7.10 The most important contributions to the second harmonic of the output voltage of the CMOS two -stage Miller-compensated op-amp of Fig. 7.9 in open loop. as a function of the fundamental frequency . The input amplitude is scaled to 1V. Since there is no feedback from the amplifier's output to the input, the second harmonic is extremely (artificially) high.
example. The GBW of the op-amp is \00 kHz. In this frequency interval, all coefficients
K2 except K2
~m
of transistor M3 are unimportant. This can be seen in Fig. 7.10, and it is
also detected automatically with the procedure described in section 7.5.1. Using this information, a symbolic expression for the second harmonic with a 25% error can now be derived. The result is given by
(7-38)
in which (7-39)
and geql
= GL + g(1M
3
+ g(1M ; A is the input amplitude. 4
206
Chapter 7
Symbolic Analysis of Weakly Nonlinear Analog Integrated Circuits
Expression (7-38) is nothing else but the contribution of the coefficient K2
gm
of M3
to the second harmonic. According to the computation method explained in section 7.4, this contribution consists of the expression of the nonlinear current source that corresponds to
K2
gm
of M3, multiplied by the transfer function from this current source to the output
voltage. The expression of the nonlinear current source contains the square of the first-order (= linear) response of the gate-source voltage of M3, and the coefficient K2 itself.
gm
EXAMPLE 7.3-DOUBLE·BALANCED MIXER A double-balanced mixer (Fig. 7.11) is often used in modulator and demodulator circuits . In this example, the conversion gain of the mixer in Fig. 7.11 is analyzed. This is a second-order response at 100 1 ± For every basic nonlinearity of the circuit, one must first calculate the factors that determine the corresponding nonlinear current source, which are the transfer functions TFI(ool) and TF 2(002) from the inputs vinl and vin2' respectively, to the voltage that determines the nonlinearity . Then the transfer function TF3(100 1 ± (0 21) from the nonlinear current source to the output is calculated . Finally, if the local oscillator voltage via is applied at one of the two input ports and the other input voltage is set to 1 V for reference, then the conversion gain K is found as a sum over all nonlinearities K 2 . :
ool
I
VDD
Figure 7.11 A double balanced mixer.
Sec.7.7
207
Conclusions
K
= VLOLK2tFli (001) TF 2i (002) TF 3 qool ± 002P
(7-40)
i
Applying this formula to the double-balanced mixer of Fig. 7.11, one finds that the conversion gain is primarily determined by the transconductance nonlinearity of the four transistors of the mixer core (enclosed in the shaded area in Fig. 7.11). This means that, in the sum of Eq. (7-40), only four terms are significant. Moreover, these terms are identical, except for their sign. Now, the three transfer functions TF I , TF2 , and TF 3 can be analyzed in detail. In Fig. 7.12, these transfer functions are shown as a function of frequency . Clearly, an overshoot occurs in the transfer functions TF 1 and TF2• This is due to the inductive behavior of the common-base transistors with a base resistance [20].
TF1
-24.--------,
fg-26
-20 r - --
TF2 -
TF3
----,
freq . (Hz)
----,
fg40
!g-25
-28 '---~--' 10 6 8 10 10 10
60 r - - --
-30 '------'------' 10 6 8 10 10 10 freq . (Hz)
20 6 10
10
8
10
10
freq. (Hz)
Figure 7.12 The transferfunctions TF1• TF2• and TF3 as a function of frequency.
When two high-frequency inputs at 00 (= 21t!1) and 00 (= 21tf) are applied to the 1 circuit used as a demodulator, then the transfer function must 5e evaluated at low frequencies because 100 1 - 0021 is small. In this case, the overshoots of TF I and TF2 result in an overshoot in the conversion gain at the difference frequency, which is shown in Fig. 7.I3a. When the mixer is used as a modulator, then the output frequency of interest is the sum frequency 00 + 00 In the conversion gain at the sum frequency, shown in 1 2, Fig. 7.13b, no overshoot occurs because the transfer function TF3 now must be evaluated at high frequencies, where its response is not flat anymore.
TiS
7.7. CONCLUSIONS In this chapter, a method has been discussed to analytically compute harmonics and intermodulation products of weakly nonlinear analog integrated circuits. The use of Volterra kernels can be circumvented here, which is a significant simplification for multiple-input circuits. The method computes harmonics or intermodulation products of voltages and currents in a weakly nonlinear circuit by repeatedly solving a linear circuit.
208
Chapter 7
Symbolic Analysis of Weakly Nonlinear Analog Integrated Circuits
6
7
8
9
log10(12) (a)
OJ
-
10
"0
c 0 en c-10 o
·cu
·w
6
cu-20 > c
o
o-30 :--'~--r_ _-,-_
6
7
8
9
_
-l. 10
log1 0(11)
log10(12) (b) Figure 7.13 Conversion gain at the difference frequency (a) and at the sum frequency (b) of the double-balanced mixer as a function of the two input frequencies. The value is scaled to an amplitude of 1V for both the signal input and the local oscillator input.
Because the method reduces to the repeated solution of linear circuits, it is possible to obtain symbolic expressions that are functions of the linear small-signal parameters and of some coefficients that explicitly express the nonlinear nature of the devices. These newly defined coefficients correspond to the higher-order derivatives of the model equations of the nonlinear elements with respect to the controlling voltage(s). It has been shown that the description of components used in analog integrated circuits in terms of such coefficients can be reduced to the description of four basic voltage-controlled nonlinearities: a
209
References
nonlinear conductance, a nonlinear transconductance, a nonlinear capacitance, and a multidimensional conductance. The calculation method described in this chapter is more general than the procedure that analog designers commonly use for hand calculations. The latter is only valid when an analytic input-output relation can be derived. On the other hand, the method presented here can handle circuits whose input-output relationship cannot be computed explicitly, circuits containing several nonlinearities, and capacitors that may be nonlinear. The required nonlinear response, which can be a harmonic or an intermodulation product up to order 3, is computed as the sum of contributions, one for each nonlinearity. In practical examples, many contributions can be discarded. A procedure has been explained that discards the insignificant contributions with a user-defined error. Finally, a symbolic expression can be computed with the remaining nonlinearities. The experimental results illustrate that this approach allows insight into a circuit's nonlinear behavior.
References [1] E. Van den Eijnde, "Computation of the steady-state response of strong nonlinear circuits," Ph.D. dissertation, Vrije Universiteit Brussel, 1989. [2] D. Atherton, Nonlinear Control Engineering-Describing Function Analysis. New York: Van Nostrand Reinhold, 1975. [3] S. Narayanan, "Transistor distortion analysis using Volterra series representation," Bell Syst. Tech. J., vol. 46, pp. 991-1024, May/June 1967. [4] M. Schetzen, The Volterra and Wiener Theories of Nonlinear Systems. New York: John Wiley, 1980. [5] H. Abraham and R. Meyer, "Transistor design for low distortion at high frequencies," IEEE Trans. Electron Devices, vol. ED-23, no. 12, pp. 1290-1297, December 1976. [6] A. Khadr and R. Johnston, "Distortion in high-frequency PET amplifiers," IEEE J. Solid-State Circuits, vol. SC-9, no. 4, pp. 180-189, August 1974. [7] R. Meyer, M. Shensa, and R. Eschenbach, "Cross modulation and intermodulation in amplifiers at high frequencies," IEEE J. Solid-State Circuits, vol. SC-7, no. 1, pp. 16-23, February 1972. [8] S. Narayanan and H. Poon, "An analysis of distortion in bipolar transistors using integral charge control model and Volterra series," IEEE Trans. Circuit Theory, vol. CT-20, no. 4, pp. 341-351, July 1973. [9] H. Poon, "Modeling of bipolar transistor using integral charge-control model with application to third-order distortion studies," IEEE Trans. Electron Devices, vol. ED-19, no. 6, pp. 719-731, June 1972. [10] W. Sansen, "Optimum design of integrated variable-gain amplifiers," Ph.D. Dissertation, Univ. of California, Berkeley, 1972. [11] E. Bedrosian and S. O. Rice, "The output properties of Volterra systems (nonlinear systems with memory) driven by harmonic and Gaussian inputs," Proc. IEEE, vol. 59, pp. 1688-1707, 1971. [12] M. Rudko and D. Weiner, "Volterra systems with random inputs: A formalized approach," IEEE Trans. Communications, vol. COM-26, no. 2, pp. 217-225, February 1978. [13] J. Bussgang, L. Ehrman, and J. Graham, "Analysis of nonlinear systems with multiple inputs," Proc. IEEE, vol. 62, no. 8, pp. 1088-1118, August 1974.
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Chapter 7
Symbolic Analysis of Weakly Nonlinear Analog Integrated Circuits
[14] L. O. Chua and C.- Y. Ng, "Frequency-domain analysis of nonlinear systems: formulation of transfer functions," lEE J. Electron. Circuits Syst., vol. 3, no. 6, pp. 257-269, November 1979. [15] Y. Kuo, "Distortion analysis of bipolar transistor circuits," IEEE Trans. Circuit Theory, vol. CT-20, no. 6, pp. 709-716, November 1973. [16] S. Chisholm and L. Nagel, "Efficient computer simulation of distortion in electronic circuits," IEEE Trans. Circuits Syst., pp. 742-745, November 1973. [17] L. O. Chua and P.-M. Lin, Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques. Englewood Cliffs, NJ: Prentice-Hall, 1975. [18] P. Wambacq, G. Gielen, and W. Sansen, "Interactive symbolic distortion analysis of analogue integrated circuits," Proc. European Design Automation Conf, pp. 484-488, February 1991. . [19] HSPICE User's Manual H9001. Meta-Software Inc., 1990. [20] K. Laker and W. Sansen, Design of Analog Integrated Circuits and Systems. New York: McGraw-Hill, 1994. [21] I. Getreu, Modeling the Bipolar Transistor. Tektronix, Inc., 1976. [22] P. Wambacq, G. Gielen, J. Vanthienen, and W. Sansen, "A design tool for weakly nonlinear analog integrated circuits with multiple inputs," Proc. IEEE 1991 Custom Integrated Circuits Conf, pp. 5.1.1-5.1.4. [23] A. A. M. Saleh, "Matrix analysis of mildly nonlinear, multiple-input, multiple-output systems with memory," Bell Syst. Tech. J., vol. 61, no. 9, pp. 2221-2243, November 1982. [24] J. Vlach and K. Singhal, Computer Methods for Circuit Analysis and Design. New York: Van Nostrand Reinhold, 1983. [25] F. V. Fernandez, A. Rodriguez-Vazquez, and J. L. Huertas, "Formula approximation for flat and hierarchical symbolic analysis," Analog Integrated Circuits and Signal Processing, vol. 3, no. 1, pp. 43-58, January 1993. [26] Y. Tsividis and D. Fraser, "Harmonic distortion in single-channel MOS integrated circuits," IEEE J. Solid-State Circuits, vol. SC-16, no. 6, pp. 694-702, December 1994. [27] S. Narayanan, "Application of Volterra series to intermodulation distortion analysis of transistor feedback amplifiers," IEEE Trans. Circuit Theory, vol. CT-17, no. 4, pp. 518-527, November 1970.
8 A. Konczykowska M. Bon
FRANCE TELECOM/ CNET-PAB
Structural Synthesis and Optimization of Analog Circuits
Bagneux Cedex, France
8.1. INTRODUCTION The term circuitoptimization is generally used to describe the technique used to determine appropriate circuit parameter values. This process is performed for a given circuit structure in order to obtain the desired circuit performances. Circuit synthesis consists generally of appropriate element values satisfying given specifications. Element values may be obtained either with explicit formulas that are part of the synthesis procedure (e.g., various filter synthesis algorithms) or by some kind of numerical optimization (e.g., real- frequencies method for matching circuits [1]). In the first case, the circuit structure is completely defined by a designer before the optimization process starts and a circuit simulator is used to calculate circuit performances for each set of parameters. Mathematical optimization methods are then used to modify optimization parameters (element values) as functions of calculated variations of performance. In the second case, although the specific structure is not known at the beginning of the synthesis process, it belongs to a specified class of structures defined by the synthesis algorithm. Both techniques play an important role in the design process of circuits and systems, as well as in modeling and tuning, and have numerous implementations in computer-aided design (CAD) programs. Among the disadvantages of these above methods is that, in the optimization process, the designer is in charge of the structure specification and .of possible further modifications, and that synthesis can be applied only to problems for which appropriate algorithms have been developed. In Ref. [2], a structural synthesis concept was presented to enhance the classical optimization/synthesis approach. In this chapter, we present a new method of structural synthesis that is a generalization of classical optimization and synthesis methods. In this
211
212
Chapter 8
Structural Synthesis and Optimization of Analog Circuits
method, the structure is not defined at the beginning of the design process and can evolve (within specified limits) during the synthesis/optimization process. The new formulation of the design goal is presented in order to support the extension of classical approaches. The chapter is organized as follows. In section 8.2, after basic definitions, we present possible formulations of a structural synthesis problem. In section 8.3, general algorithms are introduced, followed by a description of basic modules. The role of symbolic analysis in the methodology is then discussed, and in section 8.5, two practical examples are given.
8.2. BASIC DEFINITIONS AND PROBLEM FORMULATION 8.2.1. Basic Definitions In this section, we recall or define the formalism to be used for the presentation of new methods of structural synthesis and optimization. Definition B.l-Graph: G(N, B, R) is a nonoriented graph in which N is the set of nodes, B is the set of branches, and R is the incidence relation. Definition 8.2-Structure: S(G, F) = S(G(N, B, R), F) stands for a structure, where G is a graph and F is an elementfunction, F: B ~ E, which assigns to each graph branch a circuit element from a given class E of such elements. The composition of class E is defined at the beginning of the design process and depends on the specific application. It can, for example, be a class of reactive elements (L, C), as in the case of passive filter synthesis, or (R,C), as in the case of active filter design, or any other class. Definition8.3-Neighboring Structures: Sl (G1, Fl), S2(G2, F2) are neighboring structures if Gl =G2; Fl =F2 on all except one branch, which means that the structures' graphs are identical, and the assigning of elements is the same in both structures on all but one branch. We ensure that the open circuit belongs to the class of acceptable elements. The specific case of neighboring structures when one of the graph branches is an open circuit can be equivalently defined as follows: B2 = BI + b; N2 =NI or N2 = NI + n; FI(BI) = F2(BI), which means that the structures' graphs are identical except one branch, and the element functions are equivalent on the common part of both graphs. Definition 8.4-Circuit: C(S, P) = C(S(G, F), P) stands for a circuit, where S is a structure and P is a function, P: E ~ 9l, which assigns a numerical value to each circuit element. 9l represents a set of real (most often positive) numbers. A structure is therefore composed of parametrized, symbolically represented electrical elements, while a circuit is composed of elements with assigned numerical values. In. Fig. 8.1, examples of a graph, a structure, and a circuit are presented, and in Fig. 8.2, examples of neighboring structures are given. Definition 8.5-0bjective function or technical performance optimization criterion: the objective function Do determines circuit performances with respect to design specifications. It can be specifiedfor the circuit (numerically defined) and corresponds, in this case, to classical optimization terminology. In our considerations, it is also possible to define an objective function for a structure (symbolically defined). In this latter case, the objective function is expressed in terms of s-polynomials representing characteristic polynomials of the considered structure.
Sec. 8.2
213
Basic Definitions and Problem Formulation
CD r - - - - - - - . , @
1 nH
(a)
(b)
(c) Figure 8.1 (a) A graph; (b) a structure; and (c) a circuit.
• (b)
(a)
•
•
• (c)
Figure 8.2 Neighboring structures (a) and (b), (b) and (c), (a) and (c).
Definition 8.6-Errorfunction: E, is an Lp norm of the differencebetweenthe present structure/circuit performances (D) and design specifications (Do). During the design process, we try to minimize this function.
214
Chapter 8 Structural Synthesis and Optimization of Analog Circuits
Definition 8.7-Element cost: C, is an individual element cost function, Cs : E ~ 9t +, for structure elements. Cc is an individual element cost function, Cc : Ex 9t ~ 9t + , defined for circuit elements (electrical elements with assigned numerical values). Definition 8.8-Cost function or economic performance optimization criterion): the cost function K can be defined for a structure (K s : S ~ 9t + ) or for a circuit (K c : C ~ 9t +). In both cases, it is defined as a sum of the costs of individual components: defined
L
K s (S) =
be B
Kc(C) =
(a)
Cs ( F ( b) )
(8-1)
L Cc(F(b),P(b))
(b)
be B
=
=
where S S(G(N, B, R), F) and C C(S, P). In the simplest case, the costs of individual components are equal, independent of their type and value. The minimization of the cost function is then reduced to the minimization of the total number of elements. In general, individual costs can differ depending on the element type, or even the element type and value. This last situation applies obviously to circuit optimization only. In the case of integrated circuits, the element value is related to the element area. For example, in the case of switched-capacitor ICs, the sum of capacitor values is an indirect measure of the area occupied by the circuit.
8.2.2. Problem Formulation We begin with a class of acceptable electrical elements E and a set of acceptable values of electrical parameters Ve . The cost function of individual elements is defined as Cs (e) or Cc (e, v e), where e E E and vee Ve . The objective function is given. We shall now define three formulations of a structural synthesis/optimization problem.
I. Minimization of cost function with objective function fulfilled In Class I problems, we search for a structure S from the class of structures S (or a circuit C from the class of circuits C), minimizing the cost function while the error function is 0 on S (or C): min K (S)
Se S
s
or
min Kc(C) CeC
(8-2)
where S is a class of acceptable structures and "dS E S: E,(S) = 0; C is a class of acceptable circuits and "dC E C: E,(C) o.
=
II. Optimization of objective function with constraints imposed on cost function
In Class II problems, we search for a structure S from the class of structures S (or a circuit C from the class of circuits C) minimizing the error function while the cost function is limited by a given constant value: min E (S) Se S s
or
min Ec(C) CEC
(8-3)
Sec. 8.2
215
Basic Definitions and Problem Formulation
where S is a class of acceptable structures and \:15
E
S: Ks(5) < Ko;
C is a class of acceptable circuits and \:IC E C: Kc(C) < Ko' III. Global optimization with combined objective/cost goal In Class III problems, we search for a structure 5 from the class of structures S (or a circuit C from the class of circuits C) such that a combined error/cost function is minimized. min (a. x E (5) + ~ Se S r
x K (5)) s
or
min ( a. x E (C) + ~
Ce C
r
x K c ( C) )
(8-4)
where S is a class of acceptable structures; C is a class of acceptable circuits;
n, ~ are numerical weighting factors. In general, we are looking for a structure (or a circuit) composed of symbolic elements from the class E (eventually with associated values from the set Ve ), fulfilling the specifications in the best way while the topology is not completely specified a priori. The topology may be completely free or constrained. We will consider cases where exhaustive structure generation is possible, and also cases where the number of different topologies is so vast that direct verification of all acceptable structures is impossible. In these problem formulations, taking into account the cost function is mandatory for the proposed technique of structural synthesis/optimization. In fact, in classical parametric optimization, the imposed topology limits the total cost. We then have a specific case (one acceptable structure only) of Class II problem. The first two kinds of problem formulation can be transformed into a Class III formulation, although the weighting factors between the error function and cost are not always easy to establish. This situation is similar to multiobjective optimization, where a trade-off is to be found between sometimes contradictory objectives. Let us examine some typical synthesis or optimization problems and their relation to the new problem formulations.
FILTER SYNTHESIS PROBLEM Realize a low-pass LC filter with transfer characteristic function less then 0. 0 in the pass-band and greater then ~o in the stop-band. This kind of problem belongs to Class I, previously defined, because we suppose that the realization should be characterized by some minimal cost (e.g., minimal number of elements).
AMPLIFIER DESIGN For a given circuit structure and a given frequency range, find element values providing maximal amplifier gain. This kind of problem belongs to the Class II, although the class of acceptable structures/circuits is composed of one element only. In general, Class I problems correspond to generalized synthesis problems, while Class II represents generalized optimization problems.
216
Chapter 8
Structural Synthesis and Optimization of Analog Circuits
Class III problems are a generalization of Classes I and II, where both error and cost functions are considered in an equivalent way, and where a trade-off between them must be found during the design process.
8.3. METHODOLOGY OF STRUCTURAL SYNTHESIS AND OPTIMIZATION The problem of choosing proper structures for the realization of specific circuit functions may be stated in two different ways. It often occurs in engineering when, among all known structures, the one best adapted to given specifications must be chosen. It also occurs in research work, when a scientist examines a whole class of new structures solving realization problems, generally in new applications or with the use of new techniques. The two approaches are different. In the first case, most often one structure satisfying the specification is enough. In the second case, the question is, rather, "What are the limits of the considered class of structure?" In this section, we address both aspects of structural synthesis. In the previous section, we presented three formulations of structural synthesis/optimization problems that were oriented toward the "engineer's problem." We now start with three general algorithms to solve these problems (section 8.3.1). In sections 8.3.2 and 8.3.3, we present particular modules of these algorithms in greater detail. In section 8.3.4, we address exhaustive generation of structures.
8.3.1. General Algorithms of Structural Synthesis and Optimization In Fig. 8.3, we present a general organization of the synthesis/optimization algorithm for Class I problems. The main focus of this algorithm is on the minimization of the cost function (most often, the number of elements), while satisfying the objective function (error function equal to 0). The procedure is organized in two parts. First, we search for a structure satisfying the objective function. The FLAG_OBJ is then set to TRUE. Once such a structure has been found, FLAG_OBJ is set to FALSE and structure modifications aim at cost reduction. Two types of structure modifications are present in the diagram, and they are explained in section 8.3.2. In Fig. 8.4, we present an equivalent flowchart of the synthesis/optimization algorithm for Class II problems. Here, again, there are two parts. In the first part, with FLAG_COST set to TRUE, we look for a structure satisfying cost function limits. In the second part, with FLAG_COST set to FALSE, the objective function optimization is performed. The two types of structure modification, similar to those in Class I problems, are present. The flowchart of the synthesis/optimization algorithm for Class III problems is presented in Fig. 8.5. In this class, neither cost nor objective function is privileged. The trade-off between the two functions is expressed by two numerical values, a and ~. During the whole process, structure modifications of both kinds can be performed in an equivalent way. In Figs. 8.3, 8.4, and 8.5, each NEW STRUCTURE generation is followed by the module PARAMETER OPTIMIZATION. This module is necessary only in the case of a circuit synthesis/optimization problem, and is omitted in the case of structure synthesis. In this latter case, the objective (error) and cost functions are calculated from the symbolic results only. The PARAMETER OPTIMIZATION module is presented in section 8.3.3.
Sec. 8.3
217
Methodology of Structural Synthesis and Optimization
T
F
START
Figure 8.3 Synthesis/optimization algorithm for Class I problems.
8.3.2. Structure Optimization The essential part of the structural synthesis algorithm is structure generation. In Figs. 8.3,8.4 and 8.5, this module is entitled STRUCTURE MODIFICATION (type 1 and! or type 2). We present here some heuristic strategies of such structure generation. More details on such strategies can be found in the examples in section 8.5. Knowing that the number of all possible structures increases exponentially with the number of elements, we will consider structural synthesis with constrained acceptable classes of structures. In general, the structural synthesis and optimization are carried out on small cells (especially in the case of the exhaustive generation of structures). Quite often, in the case of a greater structure/circuit design, only a part of it is submitted to modifications (e.g., a feedback part, a matching module, etc.). We also consider cases where the number of elements may be more important, but we limit the number of possible
218
Chapter 8
F
Structural Synthesis and Optimization of Analog Circuits
T
START
Figure 8.4 Synthesis/optimization algorithm for Class II problems.
combinations by imposing constraints on the class of acceptable structures (e.g., only ladder, or leap-frog, structures). This type of constraint is presented in Example 8.2. Let us consider three possible types of structure modifications. Let 51 and 52 be structures from the class of acceptable structures.
• Cost-equivalent structure modification occurs when we move from 5 I to 52 and K s(5 1) = K s(52)·
• Cost-reducing structure modification occurs when we move from 51 to 52 and K s(5 1) > K s(52)·
• Cost-increasing structure modification occurs when we move from 5 I to 52 and K s(5 I) < K s(52) ·
The Type 1 structure modifications are composed of cost-equivalent and cost-increasing modifications. The Type 2 structure modifications are composed of cost-equivalent and cost-reducing modifications.
Sec. 8.3
Methodology of Structural Synthesis and Optimization
219
STRUCTURE MODIFICATION TYPE 1 or 2
GLOBALGOAL FUNCTION CALCULATION
Figure 8.5 Synthesis/optimization algorithm for Class III problems.
In the algorithm for the global optimization class of problems (Class III problems), either type of structure modification is accepted. Although specific rules for graph and structure modifications must be added for a particular application, the general rule for generating new structures is to proceed by elementarysteps of neighboring modifications. In the simplest case, when the structure cost is equal to the number of elements, cost-equivalent structure modifications correspond to changes of element type with no graph change, cost-reducing modifications correspond to element elimination, and cost-increasing modifications correspond to the addition of an element. The proposed structural synthesis algorithms are based on structure modifications between neighboring structures. This kind of algorithm is well adapted to minimize the computational effort necessary for the generation of symbolic results. We can see that modifications, when the graph is the same (basically cost-equivalent modifications) or when elements are eliminated (basically cost-reducing modifications), do not require new symbolic evaluation. The modification of element types changes symbol attributes in the symbolic function, and element elimination (provided that we use an admittance representation, which is the predominant situation) only requires an "eliminated element" symbol to be set to zero. Two different strategies for the choice of a new structure are proposed here. The first one consists of the examination of neighboring structures "one by one," and as soon as better performances (cost, error, or global function) are found, the new structure is taken as reference, and the new search is launched for a next neighboring structure. The order of neighboring structure generation is important in this case, and
220
Chapter 8
Structural Synthesis and Optimization of Analog Circuits
should be adapted (as shown in Example 8.1) to the specific synthesis situation. A data "history" should be kept, to exclude previously examined structures, in order to avoid loops in the procedure. The second strategy consists of generation and examination of all neighboring structures, and the choice of the best among them. In Figs. 8.3, 8.4, and 8.5, the first kind of strategy, "one by one," is presented. In Fig. 8.6, we present the "best neighbor" strategy in the case of the global optimization class of problems. These two strategies are generally used in different ways. In the case of circuit synthesis and optimization, each choice of a new structure is followed by parameter optimization, which can be quite a time-consuming process. In the case of structural synthesis, once symbolic analysis of the structure is completed, both cost and error
START
INITIAL STRUCTURE
GLOBAL GOAL FUNCTION CALCULATION
SET REFERENCE STRUCTURE
GENERATE ALL NEIGHBOURING STRUCTURES and CALCULATE GLOBAL GOAL FUNCTION
DETERMINE "BEST NEIGHBOUR"
N
EXIT
Figure 8.6 Structural synthesis organization with "best neighbor" strategy.
Sec.8.3
Methodology of Structural Synthesis and Optimization
221
functions can be calculated. In general, we recommend using "one by one" strategy in the case of circuit optimization and the "best neighbor" strategy in the case of structural synthesis.
8.3.3. Parameter Optimization Classical circuit design should provide not only the circuit structure, but also circuit element values. The circuit objective function is calculated taking into account these element values. To compare different circuits, the best set of circuit parameters should be determined for each structure, involving classical circuit optimization. Circuit parameter optimization problems, due to the number of parameters and the form of objective functions, are known as difficult mathematical tasks. Different mathematical procedures have been developed to cover various aspects of circuit optimization. The form of parameter optimization module that we recommend, and that was implemented in different application programs we developed, is a multi method module with clearly defined interfaces. This organization is flexible and not only permits use of the same optimization package for various specific application programs, but also enables the choice of the best-suited method for a specific job. Quite often, it is advantageous to use combined methods for one optimization problem, for example, use one method at the beginning of the optimization when we are far from the optimum, and switch to another method in the vicinity of the optimum point. We can enumerate two different families among the most popular optimization methods presently available: gradient methods and nongradient methods (see, e.g., Ref. [3] for general survey and references, and Ref. [4] as an example of a mathematical library with optimization routines). In gradient methods, various approaches such as steepest descent, Newton-Raphson, and Fletcher-Powell (quasi-Newton) methods can be cited. In the nongradient family, we find the nonlinear simplex [5] method and various random-type methods. Alongside the classical random approach, more sophisticated strategies including a random component were developed and applied to analog problems. Methods such as simulated annealing [6], the tabu search approach [7], or genetic optimization methods [8] need, in general, more iteration steps than nonrandom methods, but they are able to approach a global minimum of the function. The success of the optimization process, which can be measured by the error function and the number of iteration steps needed to reach an optimum point, depends on the chosen strategy. This strategy can have different aspects, but two essential points are the choice of the optimization method and the definition of the error function. The form of the error function can greatly influence the convergence of the optimization process and should be carefully chosen respecting specific aspects of each application.
8.3.4. Structural Synthesis: Exhaustive Generation of All Structures The exhaustive generation of structures is a specific case of structural synthesis. One practical application of this type was proposed in Ref. [9]. In this paper, the problem was stated as follows: a family of RC-biquadratic active filters was given in the form of a specified generic network structure. The precise nature of element impedances was not specified, each of them being either resistance, capacitor, or open-circuit. The symbolic
222
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Structural Synthesis and Optimization of Analog Circuits
transfer function for the general network structure under consideration was given. This function was probably calculated manually. A PROLOG [10] program was developed to determine all structures fulfilling the given specifications. The program considered successively different element subsets, assigning specific types to each of them. In each case, the initial transfer function was given with proper types of element impedances. Some evaluation criteria were then applied and satisfactory solutions stored. In Refs. [II] and [12], a different approach was proposed. It combined the exhaustive generation of structures with symbolic simulation technique. Here, we present the principles of this technique. The methodology is based on the assumption that, at each stage of the generation process, the symbolic characteristics of the generated structure can be obtained (in general, with the aid of a symbolic simulator). Our aim is to automate a generation procedure in the cases where general symbolic transfer functions cannot be easily established or simply would be too complex even for storage, to say nothing of any manipulation. In this case, each new structure must be examined individually and its symbolic transfer function generated. The problem of exhaustive generation of circuit structures may be decomposed into four successive stages: Pf): Definition of a class of possible topologies. PI: Exhaustive generation of all possible topologies. For each structure, P2: Generation of a symbolic characteristic function of a circuit. We have introduced two schemes appropriate for automated structure generation: sequential and sequential-parallel. They are presented in Figs. 8.7 and 8.8. The sequential scheme consists of executing the entire evaluation path for each structure. It involves a loop covering the following stages: generate one structure (module PI), calculate its symbolic transfer function (module P2), and perform all evaluation criteria (module P3). A new structure is accepted when all evaluation criteria are satisfied. In the sequential-parallel scheme, the process is decomposed into parts. The first part corresponds to structure generation (module PI). Successive parts cover modules P2 and P3. They consist of generation of the transfer function (module P2-symbolic simulation) and performing one evaluation criterion. These parts may be duplicated as many times as the number of criteria, and arranged in different order. Let us present the advantages and disadvantages of both solutions. Advantages of the sequential-parallel scheme (negation being disadvantages of the sequential scheme): I. The chosen scheme is modular; it is easier to develop, test, and evaluate each part
separately. 2. It is possible to apply several evaluation criteria successively, each time reducing the family of examined structures. It is also possible to apply different sets of tests without repeating the entire generation part.
Sec. 8.3
223
Methodology of Structural Synthesis and Optimization
START Module P1
STRUCTURES GENERATOR
Module P2
Module P3
N
STORE ACCEPTED STRUCTURE 1-------
.'
Figure 8.7 Sequential structure generation schemes.
Disadvantages of the sequential-parallel scheme (negation being advantages of the sequential scheme): 1. When the set of acceptable topologies is very large, the problem of intermediate data (list of structures) arises; it is necessary to decompose the list of possible structures or add new topological criteria to break the problem down into parts. 2. In every part of stages P2 and P3, we calculate the transfer functions of all structures from the examined list. So, for a structure satisfying k criteria, we repeat the calculation of its symbolic transfer function k times. In the applications we developed, we generally used the sequential-parallel scheme, for several reasons. The most important advantage of the sequential-parallel scheme was the possibility of gradual reduction of the set of solutions and the use of different criteria sets on the same initial list of structures. As far as disadvantages are concerned, in our opinion, if all topological solutions without any constraints are considered, we are generally confronted with a combinatorial explosion, and neither the sequential-parallel nor the sequential scheme works. In studies carried out, preliminary elimination of
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N
N
y STORE ACCEPTED STRUCTURE
Figure 8.8 Sequential-parallel structure generation schemes .
obviously trivial cases (easily programmed in languages like PROLOG) resulted in intermediate data of reasonable size . As for the second disadvantage, it should be pointed out that our essential goal was the rapidity and facility of program development rather than CPU time minimization. Because we could obtain symbolic results from symbolic simulators in a quite efficient way, the repetition of some calculation would not cause any major problem. Besides, during different evaluation stages, models of examined structures may sometimes differ . For example, we start with an idealized model and use a more detailed model only after successfully meeting basic criteria.
8.4. SYMBOLIC APPROACH IN STRUCTURE SYNTHESIS AND PARAMETER OPTIMIZATION The methodology presented in section 8.3 can be partly exploited using traditional simulation and optimization tools . Nevertheless, for some parts , the availability of symbolic characteristics is mandatory, and for others, it can greatly enhance an algorithm's efficiency. We now examine different aspects of the proposed structural synthesis and optimization methodology, pointing out where symbolic analysis is necessary and where it can help .
Sec. 8.5
Examples
225
Obviously, for all problems specified in the structure domain, where the objective function is defined for a structure and not for a circuit, we cannot do without symbolic results. Exhaustive structure generation is a specific case of structural synthesis. The aim of this technique is to answer general questions on realizability limits in a class of considered topologies, rather than to solve a specific design problem. In proposed procedures, naturally we are obliged to examine a very large number of structures. The criteria of choice must thus be formulated for structures rather than for circuits, which are only some specific structure instantiations. Symbolic results are then mandatory for exhaustive structures generation. An area in which the symbolic results can improve computational efficiency is parameter optimization. In fact, classical numerical optimization requires a great number of circuit evaluations. With new methods such as simulated annealing [6] or tabu [7], which enable avoidance of local minima, this advantage is offset by an increased number of objective function evaluations. As each circuit optimization is performed for the same structure, the availability of simulation results in symbolic form can greatly accelerate the optimization process. In each iteration step, a new objective function evaluation should be performed. A new set of parameter values is provided by the optimization procedure. This new evaluation can be performed without new analysis, only by updating parameters in previously generated symbolic expressions. Different applications of this principle may be found in this book: automatic sizing of analog cells in chapter 9, design of discrete-time circuits in chapter 10, parameter extraction by optimization in chapter 11, or determination of the statistical parameters of delays in digital circuits in chapter 12.
8.5. EXAMPLES In this section, we present two examples of structural synthesis and optimization. Example 8.1, provided for illustrative purposes only, is a simple synthesis of an LC filter and permits the reader to follow the particular steps of structural synthesis. Example 8.2 presents a case of exhaustive generation of switched-capacitor circuits. New, technically interesting, topologies were obtained in this study.
EXAMPLE 8.1-LC FILTER SYNTHESIS Let us consider the case of LC filter synthesis. In this example, we apply the structural synthesis method to the classical problem of filter synthesis. Comparison with well-known solutions and evaluation of the efficiency of the proposed strategy are provided. Let us consider a low-pass filter specification: with pass-band attenuation AD =0.01 dB, stop-band attenuation As = 41.9 dB, and stop-band edge Os = 1.206 (Fig. 8.9a) (C 07 05/56 in Ref. [13]). This filter can be realized as a seventh-order elliptic filter (Fig. 8.9b). The structure for this realization was defined as a ladder, and the elements under consideration were capacitors and inductances, with given minimal and maximal values. When starting with a two-element LC structure, a final 10-element structure was obtained in 11 steps of structure modification. During this structure optimization process, only three steps of structure modification were rejected after failure of the parameter optimization part.
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LOSS [dB] 80 ~-----------~
60
t--------tt---~r_----____;
40 1 - - - - - - - - - + - - - - - - - - - - - - - - - / 20
1------
--+---------------/
0.01 1 234 NORMALIZED FREQUENCY (a)
I_T_T_I (b) Figure 8.9 The 7th-order elliptic filter: (a) frequency characteristic (different scale for pass-band); (b) structure.
In the parameter optimization module, two alternate initial points are considered: the first point with the new (or changed) element at its maximal or minimal value to start from the situation as close as possible to the previously examined one, and the second point with the changed element having the a priori specified initial value. The cost reduction strategy was also tested in this case. Starting with a 14-element structure, the minimal cost structure was obtained in four steps. The order of elements proposed to be removed was decided according to the parameter values obtained during the optimization. The first elements considered for elimination were those with the maximal or minimal values (representing the closest position to a short or an open circuit, depending on the element type and its location in the circuit).
Sec. 8.5
Examples
227
EXAMPLE 8.2-EXHAUSTIVE GENERATION OF SWITCHED-CAPACITOR STRUCTURES Here, we present a practical study in the area of switched-capacitor integrated circuits (SC ICs) [14]. The methodology used was exhaustive structure generation. The problem was set as follows: we sought new structures for switched-capacitor integrators (integrators are very widely used as basic building blocks in SC circuits). An initial class of such SC integrators was a family of circuits including only one amplifier and three capacitors interconnected by an arbitrary number of switches. We imposed our structure to be parasitic-free (i.e., stray-capacitance insensitive), and we wanted to find a structure least affected by finite amplifier gain. This was done with a view to selecting architecture well suited to high-frequency operation on silicon, as well as on gallium arsenide substrates. The clocking system was decided to be classic two-phase. The symbolic simulator SCYMBAL [15], [16], dedicated to the analysis of switched-capacitor circuits, was used during this research. SCYMBAL allows us to generate the transfer functions of any analyzed network under symbolic form. In the case of switched-capacitor circuits, transfer functions are rational functions of the z-frequency variable, with coefficients being multilinear functions of capacitances and the amplifier's gain. Automated structure generation was organized in a sequential-parallel scheme. A mixed-languages solution was adopted to realize the algorithm. PROLOG language was used to develop modules PI and P3 (as defined in section 8.3.4), and a standard procedural language was chosen for module P2. Let us present the arguments for the proposed mixed-languages organization. PROLOG is a declarative language having internal mechanisms for exhaustive searches of all possible solutions satisfying a set of given constraints. No specific algorithm is then needed for module Pl. A PROLOG program consists of structure definitions and is extremely easy to write and modify. The same reasoning is valid for module P3. It is easy to transform evaluation criteria into PROLOG clauses. Module P2, on the contrary, corresponds to symbolic circuit simulation, which means complicated and sophisticated algorithms. It is very difficult to achieve an efficient simulation program in a declarative language like PROLOG. The generation part was a combinatorial problem with constraints consisting of elimination of symmetrical cases and obviously degenerate cases (e.g., all capacitors short-circuited, etc.). We have five nodes in our network: input, op-amp negative input (positive op-amp input being connected to ground), output (being also op-amp output), free node (a capacitor can be disconnected during one phase), and ground. These nodes are numbered as follows: I-input, 2-op-amp negative input, 3-output, 4-ground, and 5-free node. To determine one structure, we have to define for each capacitor its connection nodes in both phases. As a two-phase clocking scheme was chosen, each capacitor's connections can be defined by a quadruplet, or in other words, 4-uplet (n l' n2' n3' n4), where n i E {I, ... , 5}. The capacitor defined by this 4-uplet is connected between nodes (n l' 1l3) in even-phase, and in odd-phase, between nodes (n2' n4)' As we have three capacitors with two terminals in each phase to be connected, a 12-uplet (Ill, n2' ..., 1l12) determines one possible structure. As each element of a 12-uplet can have one of five possible values, if no preliminary elimination were carried out, 5 12 (about a quarter of a billion!) structures would then have to be examined. In Fig. 8.10, one possible structure [17] is presented. The capacitor C2 is defined by a 4-uplet (5, 3, 2, 2), and a whole structure is characterized by a 12-uplet (4, 1,2,2,5,3,2,2,2, 1,3,3).
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1
2
3
+
e o Figure 8.10 Biquad structure from reference [17].
We organized our structure generator in the following way. First, all possible node pairs were examined. We eliminated combinations leading to "parasitic transitions" as well as constantly open connections. This reduced the number of 2-uplets to 20 (instead of 25). Then all two-element combinations of pairs were examined with the elimination of symmetrical, equivalent, or electrically non valid combinations. This was done with the aid of 12 verification rules (PROLOG clauses). The number of accepted 4-uplets was 30. Then, all three-element combinations of the previously obtained 4-uplets were examined. We eliminated essentially all solutions symmetrical with respect to the two-phase clocking scheme, as well as isomorphous combinations differing only by capacitor positions. The final list contained 1,874 potential structures. The flowchart of this generator is presented in Fig. 8.11. The list of 1,874 structures was then processed by several evaluation modules. Each evaluation module was composed of a symbolic simulation performed by SCYMBAL and an evaluation procedure. The organization diagram of this part is presented in Fig. 8.12. As we wanted to generate integrator structures, the first criterion consisted of checking the correct form of the denominator D(z):
D (z) = 1 - z-2
(8-5)
We obtained 219 structures satisfying this criterion. Then, all these structures were classified according to the form of their numerator. We were checking for BD, FD, LDI, and bilinear integrators [18]. The last criterion consisted of verifying the influence of a finite amplifier gain. This time, the analyzed structures were not considered as ideal, but simulated with parametric amplifier gain. Let fl = I/A, where A is the finite amplifier gain. A gain and a phase error due to a finite amplifier gain were calculated in symbolic form (as a function of u). We searched for structures with error functions depending only on higher orders of fl. We found three, five, and two interesting structures in the BO, FO, and LOI classes, respectively. No bilinear integrator was found. These structures were examined in detail. Among these structure, one published previously [17] was found. Other structures presented equivalent properties, and one was slightly better. This new integrator has a transfer function
Sec. 8.5
229
Examples
GENERATION of 2-UPLETS P=(N1,N2) CRITERION: elimination of parasitic connections
•
I RESULT: 202·UPLETS I
1
GENERATION of 4-UPLETS 0=(P1,P2) CRITERION: 12 elimination rules
I RESULT: 30 4·UPLETS I ~
GENERATION of 12-UPLETS 8=(01,02,03) CRITERION: symmetry elimination
IRESULT: 1874 STRUCTURES I Figure 8.11 Flowchart of structure generator.
(8-6)
and its structure is presented in Fig. 8.13. The symbolic form of errors, expressed as a function of J.l, shows that for the new structure both gain and phase errors have only terms in J.l2 (linear term in J.l is canceled), while previously proposed structures had at least one linear term in u. Figure 8.14 illustrates the phase and the gain errors due to the finite amplifier gain (A = 100). It was assumed that C lfC2 = 0.2 while the clock rate was 100 kHz. The curves presented in these figures are denoted by the symbols: A, B, C, D and correspond to the following data: New structure C I =0.2 C I =0.2
-rcurve A - curve B
Structure from Ref. [17]: C I =0.2 C2 = 1 C 1 = 0.2 C2 = 1
- curve C - curve D
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GENERATION OF THREE CAPACITORS/ ONE OPAMP SC STRUCTURES (in PROLOG) 1847 structures
CHECK IF DOMINATOR PROPORTIONAL TO
1-z-2
(usinQ SCYMBAL)
CHECK FOR LOW INFLUENCE OF OPAMP FINITE GAIN (using SCYMBAL)
!
3 CIRCUITS
!
5 CIRCUITS
!
2 CIRCUITS
Figure 8.12 Flowchart of generation of HF SC integrators.
In Figure 8.14, some numerical results are presented, corresponding to data from Ref. [17]. Figure 8.14a shows that the crucial phase error is lower for the new network, while the gain error is almost the same for both integrators (curves Band C in Fig. 8.14b).
8.6. CONCLUDING REMARKS The progress in available computational capabilities, as well as new software development tools, give rise to new methodologies in computer-aided design. Classical optimization and synthesis techniques form an integral part of CAD systems, and are extremely useful for analog circuit designers. Specific requirements of analog design, among which the most important and most difficult to satisfy are flexibility and high-performance structures, create a need for specific CAD tools and design techniques. In this chapter, we presented a new approach to synthesis and optimization problems. The generalization of the standard approach was presented using a combined objective/cost goal. More specifically, access to the symbolic form of circuit characteristic functions enables the formulation of the structure synthesis problem in the s- (or z-)
Sec. 8.6
231
Concluding Remarks
O e
/
e "9
3
I
A w
II T Figure 8.13
Structure of the new SC integrator.
RELATIVE GAIN ERROR
RELATIVE PHASE ERROR
0
-0.05
-0.05
BC
-0.1
-0.15
-0.2
-0.1
-0.15
AD 0
l 0.01
0.02 0.03 FREQ/Fclock
(a)
0.04
0.05
-0.2
0
0.01
0.02 0.03 FREQ/Fclock
0.04
0.05
(b)
Figure 8.14 (a) Phase errori (b) gain error due to finiteamplifiergain.
domain. The exhaustive structure generation approach was addressed as a special case of structural synthesis. The PROLOG language was used to implement a part of the methods presented. It turned out to be a very satisfying tool, especially for applications using exhaustive structure generation. These new techniques were illustrated by practical examples. The efficiency of the exhaustive generation approach was demonstrated in the case of switched-capacitor structures, yielding a new integrator structure relatively insensitive to finite amplifier gain.
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References [1] H. J. Carlin, "A new approach to gain-bandwith problems," IEEE Trans. Circuits Syst., vol. 24, no. 4, pp. 170-175, April 1977. [2] A. Konczykowska and M. Bon, "Analog design optimization using symbolic approach," Proc. IEEE Int. Symp. Circuits Syst., Singapore, pp. 786-789,1991. [3] L. P. Huelsman, "Optimization-A powerful tool for analysis and design," IEEE Trans. Circuits Syst., vol. 40, no. 7, pp. 431-439, July 1993. [4] NAG FORTRAN Mini Manual, Numerical Algorithms Group, 1981. [5] J. A. NeIder, R. Mead, "A simplex method for function minimization," The Computer Journal, 1965. [6] P. J. M. Van Laarhoven and E. H. L. Aarts, Simulated Annealing: Theory and Applications. Dordrecht, The Netherlands: D. Reidel, 1987. [7] F. Glover, "Tabu search" part I, ORSA J. Computing, vol. 1, no. 3, pp. 190-206, 1989; "Tabu search" part II, ORSA J. Computing, vol. 2, no. 1, pp. 4-32, 1990. [8] D. E. Goldberg, Genetic Algorithms in Search, Optimization and Machine Learning. Reading, MA: Addison-Wesley, 1989. [9] J. C. Mouly and J. Neirynck, "A PROLOG program for the exhaustive search of noninteractive tunable biquads," Proc. IEEE Int. Symp. Circuits Syst., pp. 544-547, 1986. [10] L. Sterling and E. Shapiro, The Art of PROLOG. Cambridge, MA: MIT Press, 1987. [11] A. Konczykowska, J. Mulawka, and M. Bon, "Symbolic simulation: a new approach to automated circuit design," Int. Workshop on Artificial Intelligence for Industrial Applications, Japan, May 1988. [12] A. Konczykowska, J. Mulawka, and M. Bon, "An exhaustive generation of switched-capacitor circuits: a symbolic simulation and artificial intelligence approach," Proc. IEEE Int. Symp. Circuits Syst., Espoo, Finland, pp. 1733-1736, 1988. [13] Von R. Saal, Der Entwurf von Filtern mit Hilfe des Kataloges norrnierter Tiefpasse, Telefunken J., pp. 208-209, 1961. [14] B. J. Hosticka, R. W. Brodersen, and P. R. Gray, "MOS sampled-data recursive filters using switched-capacitor integrators," IEEE J. Solid-State Circuits, vol. SC-12, pp. 600-608, December 1977. [15] A. Konczykowska and M. Bon, "SCYMBAL 2: a portable computer program for efficient all-symbolic hierarchical analysis of large, multi-phase switched-capacitor networks," Proc. European Conf. Circuit Theory and Design, Stuttgart, pp. 375-378, 1983. [16] A. Konczykowska and M. Bon, "Automated design software for switched-capacitor IC's with symbolic simulator SCYMBAL," Proc. 25th ACM/IEEE Design Automation Conf., Anaheim, CA, pp. 363-368, 1988. [17] K. Haug, F. Maloberti, and G. C. Ternes, "Switched-capacitor integrators with low finite-gain sensitivity," Electron. Lett., vol. 21, pp. 1156-1157, 1985. [18] E. P. Fleischer and K. R. Laker, "A family of active switched-capacitor biquad building blocks," Bell Syst. Tech. J., vol. 58, pp. 2235-2268, 1979.
9 Georges Gielen *
Departement E/ektrotechniek, ESAT-M/CAS Katholieke Universiteit Leuven Hever/ee, Be/gium
Automated Analog Design Using Compiled Symbolic Models
9.1. INTRODUCTION The electronics market in the 1990s and, in particular, the market of application-specific integrated circuits (ASICs) are characterized by an increasing tendency to integrate complete systems, which before occupied one or more boards, onto a single chip or multichip module. Although most functions in such integrated systems are implemented with digital circuitry, the analog circuits needed at the interface between the electronic system and the outer world as well as in real high-performance applications (e.g., low noise or very high speed) also have to be integrated on the same die for reasons of cost and performance. The booming market share of mixed-signal ASICs is a direct result of this. Although the analog circuits typically occupy only a small part of the area in these mixed-signal ASICs, they nevertheless require an inversely large part of the design time and cost and are often responsible for design errors and expensive redesign iterations. Indeed, analog design is generally perceived as less systematic and more heuristic in nature than digital design, and most analog designs at present are still carried out manually because of the lack of adequate and mature analog computer-aided design (CAD) tools. The economical pressure for cheap electronic products and short times-to-market have, however, also unveiled the need in the microelectronics industry for analog CAD tools to assist designers with the fast and first -time-correct design of the analog circuitry, without requiring too high a level of analog design expertise, or even automating this design process where possible.
* Research associate of the Belgian National Fund of Scientific Research
233
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The technique of symbolic analysis described in this book has a large application potential in the development of these analog CAD tools, as it is a way to gain insight in the behavior and design trade-offs of analog circuits, and as it can be an important part in the automation of essential design tasks such as circuit sizing and testability analysis. This chapter focuses on the application of compiled symbolic models in automated analog design, where symbolic analysis provides a way to create an open analog synthesis system that is not limited to the built-in circuit schematics but can be extended by the designers themselves. After defining analog specification translation and circuit sizing, section 9.2 will first present the different basic automated analog design techniques and compare them with respect to speed, flexibility, and openness. The technique of analog design optimization based on compiled symbolic models will be shown to offer a good compromise between these criteria. The technique will be explained in detail in section 9.3. Both the analog design optimization formulation and the derivation and use of the symbolic models will be described. Section 9.4 will then present examples of analog synthesis systems based on this approach. This will be illustrated with practical design examples. Conclusions are provided in section 9.5.
9.2. OVERVIEW OF AUTOMATED ANALOG DESIGN TECHNIQUES 9.2.1. Specification Translation and Sizing of Analog Circuits The design of analog integrated circuits starting from the required specifications and .technology process can be divided into three major tasks: the selection of .an appropriate schematic, the sizing of this schematic, and the generation of the layout. Figure 9.1 illustrates these different steps for the design of a simple operational amplifier (op-amp). For a more complex analog circuit such as a phase-locked loop or an analog-to-digital converter, these steps will have to be repeated over different levels of design hierarchy [1].
The schematic is then called an architecture and is defined in terms of subblocks from a lower level in the design hierarchy (e.g., the comparator within the analog-to-digital converter). In general, the performance-driven hierarchical analog design strategy used nowadays [1], [2] consists of the following steps in between any two levels i and i + 1, as schematically shown in Fig. 9.2: top-down path architecture selection specification translation design verification
bottom-up path layout assembly detailed verification (after extraction)
Redesign iterations are needed when the design fails to meet the specifications at some point. The second step in this hierarchical design process, after the selection of an appropriate architecture for the given specifications, is called specification translation. This is the mapping of the specifications for the block to be designed at level i (e.g., analog-to-digital converter) into specifications for each of the subblocks at level i + 1 within the selected block architecture (e.g., comparator within a flash architecture), so that
Sec. 9.2
235
Overview of Automated Analog Design Techniques
SPECIFICA nONS
'\0 = 60 dB GB = 1 MHz SR = 106 Vis ...
topology selection
SIZES 1Ji"1
sizi ng
WI=IO
LI=6
W2=8
L2=6
W3=20
L3=6
layout generation
Figure 9.1 Basic steps in the synthes is of an operational amplifier .
the complete block meets its specifications at level i , while possibly also optimizing some application-specific design objectives (e.g., smallest area or power consumption). The translated specifications can then be verified by means of (behavioral) simulation. At the lowest level in the design hierarchy, the subblocks are single devices and specification translation reduces to circuit sizing (or dimensioning). Sizing is thus the determination of all bias parameters, element values, and device sizes in the circuit so that it satisfies all performance constraints, while possibly also optimizing some design objectives.
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.
specifications atlevel i
layout at level i
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.
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Figure 9.2 Performance-driven hierarchical design methodology for analog integrated circuits.
Specification translation and sizing are critical steps in the overall analog design process. Many high-performance applications and mixed-signal ASICs require an optimal design solution for the analog circuits in terms of area, power, and overall performance. Because of the large diversity of analog specifications and their wide variation from application to application, the use of analog standard cells would require an uneconomically large library of infrequently used cells. Analog circuits are therefore better synthesized and optimized toward each specific application, provided that CAD tools are available to support this. This synthesis is the inverse operation of circuit analysis, where the subblock parameters are given and the resulting block performance has to be derived. During synthesis, the block performance is specified and values for the subblock parameters needed to meet these specifications have to be determined. This inverse process is not straightforward and it is usually an underconstrained problem with many degrees of freedom. In the present analog design systems, these degrees of freedom are eliminated in essentially two different ways: either by exploiting analog design knowledge and heuristics or by optimization. These basic approaches will now be described and compared in more detail in the next section.
Sec. 9.2
237
Overview of Automated Analog Design Techniques
9.2.2. Knowledge-Based Versus Optimization-Based Automated Analog Design For solving the underconstrained problem of specification translation and sizing of analog circuits, two basic approaches are possible: the knowledge-based approach, where specific heuristic knowledge about the circuit architecture is used explicitly to obtain a solution; the optimization-based approach, where the solution is found as the result of a constrained optimization process.
9.2.2.1. The Knowledge-Based Approach There exist different ways to implement the knowledge-based approach. BLADES [3], for instance, uses rules to size the circuits. The most successful approach, implemented in tools such as IDAC [4] and OASYS [5], uses design plans or design scripts to carry out the specification translation or the sizing. The design equations specific to a particular circuit architecture are obtained beforehand, ordered, and rearranged into a fixed design script or design plan. The degrees of freedom in the design are solved explicitly during the development of the design plan using simplifications and design heuristics. During actual synthesis, the design plan is then executed to obtain the design solution for the given specifications. This approach is illustrated schematically in Fig. 9.3a. Because the hardcoded design plan is executed just like a kind of algorithm, this technique is called the algorithmic approach to knowledge-based sizing. The big advantage of using design plans is execution speed. The approach takes advantage of the knowledge of analog designers, and synthesis is fast because it only requires the evaluation of design equations prearranged in the design plan where all degrees of freedom have been eliminated. The big disadvantages of using design plans are the lack of flexibility and the time needed to develop a plan for each architecture and design target. Indeed, analog design heuristics are very difficult to formalize in a general and context-independent way. The heuristics utilized in a design plan are therefore often specific for each architecture and, for a certain architecture, sometimes even specific for a certain design target (e.g., low-power applications). Because the complete design solution specifications
specifications
execute design plan
evaluate performance
design plans
sizes
(a)
optimize sizes
~-----<.
(b)
simulator symbolic models
0 K?
sizes
Figure 9.3 The different approaches towards automated analog design: (a) the knowledge-based approach using design plans; and (b) the optimization-based approach.
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Automated Analog Design Using CompHed Symbolic Models
based on these heuristics is hardcoded in the design plan, such a design plan also becomes target-specific and different design plans will have to be developed for different application domains, even for the same architecture. For example, a design plan oriented toward low power cannot be used for a low-noise application, implying that a separate low-noise plan has to be developed for the same circuit architecture. In addition, it has been reported [6] that the creation of a design script or plan typically takes four times more effort than is needed to actually design the circuit once. Even though the equations used in the design plan could be derived by a symbolic analysis program, the explicit elimination of the degrees of freedom and the ordering of the equations into a predefined solution plan remain the bottleneck. A given architecture must therefore be used in at least four different designs before it is profitable to develop the corresponding design plan. Considering the large number of different analog circuit architectures known today or still to be invented, it is clear that the time needed to introduce a new architecture into an analog synthesis system must be reduced as much as possible for the system to be useful in industrial design practice. Attention must also be paid to make the design plans process-independent.
9.2.2.2. The Optimization-Based Approach The second approach is to apply a general-purpose optimization program to optimize the performance of the circuit, as illustrated schematically in Fig.9.3b. The degrees of freedom are solved implicitly by the optimization program, which simply searches for the design solution that optimizes the objective function. At each iteration of the optimization routine, the performance of the circuit then has to be evaluated. Depending on which method is used to evaluate the circuit performance, two different subcategories of methods can be distinguished. In the equation-based optimization approach, the circuit performance is derived by evaluating a set of symbolic design equations. Examples are the OPTIMAN [7] and OPASYN [8] programs. In the simulation-based optimization approach, the circuit performance is evaluated by means of numerical simulation. An example is the DELIGHT.SPICE program [9]. In the case of equation-based optimization, the design equations will have to be derived in advance, which can be done manually or, to a large extent, also automatically by means of symbolic analysis. As described in this book, symbolic analysis programs nowadays allow us to automatically generate (both exact and simplified) symbolic expressions for the ac characteristics of both continuous-time and discrete-time (e.g., switched-capacitor) analog circuits. The difference with the design-plan approach is that the degrees of freedom do not have to be eliminated explicitly, but will be resolved implicitly by the optimization program. In the case of simulation-based optimization, on the other hand, no specific actions are needed when introducing a new schematic into the synthesis system (except for indicating how the different performances of the circuit have to be simulated). The big advantage of the optimization-based approach is therefore the high flexibility, both in design targets and schematics. Altering the goal function will produce an optimization toward a new design target. For instance, more importance can be assigned to low noise than to low power consumption. In addition, it is much faster to extend the synthesis library with a new architecture, because this requires only the (semi-automated) derivation of the design equations in the equation-based approach and no specific action at all in the simulation-based approach. The technique is also more process-independent. The big disadvantage of the optimization-based approach is, of course, the larger CPU time needed. Because no heuristic knowledge about the architecture under design for
Sec.9.2
239
Overview of Automated Analog Design Techniques
the given design targets is exploited in the system, a kind of blind optimization is done, which can result in many iterations, and therefore long CPU times, compared to the design-plan approach. This blind optimization might even not converge. The use of an equation-based optimization approach is therefore a solution in between because it typically requires less CPU time than the full simulation-based approach at the expense of some loss in accuracy (the latter when using simplified equations). An additional degree of freedom in the development of an optimization-based approach is the selection of the optimization algorithm, where the basic choice is between a global and a local optimization algorithm. Both OPTIMAN [7] and OPASYN [8], for example, use equation-based optimization, but OPTIMAN uses simulated annealing, whereas OPASYN uses a steepest-descent local optimization.
9.2.2.3. Comparison of Knowledge-Based and Optimization-Based Automated Analog Design We can now summarize the comparison among the different approaches: the algorithmic approach (with design plans), the equation-based optimization approach, and the simulation-based optimization approach. The result is shown in Table 9-1, where the following four criteria have been used: •
speed of execution
•
flexibility in design targets
•
effort to include new schematics
•
process independence
The algorithmic approach with dedicated design plans is, in general, faster but less flexible and requires the tedious development of the design plans for each schematic. The optimization approach is, in general, more flexible in design targets and it is easier to include new schematics, but it is also less efficient. The speed penalty can be reduced by using symbolic equations instead of simulations in the optimization loop, while sacrificing some accuracy and introducing the need to derive the equations for each schematic. Process independence, on the other hand, is more difficult to achieve when using hardcoded design plans than when using an optimization approach. In summary, the difference between the knowledge-based and the optimization-based approaches is to a large extent the trade-off between CPU time and flexibility. Table 9-1 Comparison Among the Different Techniques for Analog Specification Translation and Sizing
Algorithmic (design plan)
Equation-based optimization
Simulation-based optimization
+++
+/-
---
flexibility in design targets
--
+++
+++
effort to add new schematics
---
+
+++
-
++
+++
execution speed
process independence
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As a solution toward analog synthesis, one sometimes also uses a combination of these methods. For example, a simple design plan can be used to generate a first-cut solution that is somewhere near the optimum and that is then further optimized toward the user-specified goal function by an optimization routine. Such an approach combines the speed of the algorithmic approach with the flexibility of the optimization approach, but still requires the design plan to be developed for each specific circuit architecture. In the remainder of this chapter, we will describe in detail the optimization-based approach toward analog specification translation and circuit sizing based on compiled symbolic models, because this technique offers a good compromise between speed, flexibility, and openness for analog synthesis and because it is an interesting application of symbolic analysis.
9.3. AUTOMATED ANALOG DESIGN AS AN OPTIMIZATION PROBLEM BASED ON COMPILED SYMBOLIC MODELS In this approach, which is schematically depicted in Fig. 9.4, analog design is formulated as a constrained optimization problem. The performance behavior of the circuit is modeled by means of a set of (simplified) symbolic equations, which are compiled into a symbolic model. The equations can, to a large extent, be derived automatically by means of a symbolic analysis program. The compiled symbolic model is then numerically evaluated at each optimization iteration in order to calculate the circuit's performance for each set of values for the independent design variables suggested by the optimization routine. The resulting performance information is used by the optimization program to check the specifications and to suggest new values for the independent design variables so as to optimize the goal function. symbolic analysis program
~
specifications variable values
_ _.....J
~
designer
~
. symbolic equation equations -7 manipulation I compilation
.. i11 ~
U
evaluate circuit performance
compiled symbolic model
optimize variables
conv.>-----~
optimum values Figure 9.4 Automated analog design as an optimization problem based on compiled symbolic models.
The equation-based analog design optimization approach therefore needs the following information to be included in the symbolic model [10]: • The list of independent design variables, which are the variables that are varied by the optimization routine • Relationships between dependent and independent design variables • Symbolic equations relating the circuit performance to the design variables
Sec. 9.3 Automated Analog Design as an Optimization Problem Based on Compiled Symbolic Models
241
• Possible additional analog expert knowledge about the circuit and other design constraints, expressed as analytic equations This section describes the different aspects of this approach in more detail. First, the symbolic design equations are discussed. Next, the derivation of the independent design variables is presented. Finally, the analog design optimization formulation is described.
9.3.1. Symbolic Design Equations The performance of the circuit under design needs to be evaluated at each iteration of the optimization. In the approach discussed here, this is done by numerically evaluating a compiled symbolic model that describes the circuit's performance behavior by means of (simplified) symbolic equations. The use of (simplified) symbolic equations is motivated by the observation that most circuit characteristics, such as the gain or the phase margin of an operational amplifier, are influenced by a small number of design variables only [10]. All other circuit variables have only a negligibly small influence, even over a broad range of values. Compared to a full numerical simulation, the evaluation of these simplified equations largely speeds up the optimization at the expense of only a small loss in accuracy. At the same time, the derivation of the symbolic equations can largely be automated. In general, symbolic equations are needed to describe the de behavior, small-signal characteristics, large-signal characteristics, and time-domain characteristics. The small-signal characteristics can automatically be derived in symbolic form as a function of the circuit's small-signal elements and the complex frequency by means of a symbolic simulator such as ISAAC [11] or ASAP [12]. These programs can also symbolically simplify the expressions by pruning insignificant terms with respect to more dominant ones, over some range of circuit element values, thereby reducing the complexity of the expressions and speeding up their evaluation. On the other hand, the equations for the large-signal and time-domain characteristics up to now still have to be provided manually by the designer. The small-signal characteristics, however, typically cover the largest part of the symbolic model for building blocks such as operational amplifiers and filters. And most of the other characteristics can, in the future perhaps, also be derived automatically by a program based on topological search and pattern recognition.
EXAMPLE 9.1 The design equations included in a circuit's symbolic model are now illustrated for the example of the CMOS folded-cascode operational transconductance amplifier (OTA) shown in Fig. 9.5: 1. Low-frequency gain: (9-1)
2. Gain-bandwidth: (9-2)
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Vino1
Figure9.5 CMOS folded-cascode OTA.
3. Phase margin: (9-3)
where: (9-4)
(9-5)
(9-6)
(9-7)
4. Power consumption: (9-8)
5. Slew rate:
(9-9)
Sec. 9.3 Automated Analog Design as an Optimization Problem Based on Compiled Symbolic Models
243
6. Systematic offset voltage: (9-10) 7. Common-mode input range: (9-11) (9-12) 8. Output range: (9-13) (9-14) 9. Additional constraints for proper operation of the circuit: (9-15) (9-16) (9-17) 10. Common-mode rejection ratio (at low frequencies): CAIRR =
gmt gds6 gds4 (gm4
2
(9-18)
+ gmS + gmbS)
gm4 (gmS + gmbS)
11. Power-supply rejection ratio (at low frequencies): PSRR+
=
gml gds4 gdsS
----+
gms
+ gmbS
PSRR-
(gdsl
+ gds2) gds3
gm3
+ gmb3
+
gds6 gds4 (gm4
2
+ gms + gmbS)
gm4 (gms
(9-19)
+ gmbS)
=---------------
(9-20)
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12. Equivalent input voltage noise density: 2
2
gm2
2
2
gm4'"
dv n, eq = 2 [ dv n I + dv n2 [ gm I ) 2 + dv n4 [g)m" I ]
(9-21 )
where each transistor equivalent input noise source dv ~i includes a white-noise part and a Ilf-noise part: 2
dv ni
2
K df
F = 4kT3 -.df+ W.L.-f gmt
t
(9-22)
t
13. Integrated output noise in unity feedback:
n
.2
V RrMS = -2 . GB
2
where dv n, eq,
2
2
. dv n, e q, w + In (GB) . dv n, eq., f
(9-23)
2
w
and dv n, eq., f are the white-noise and the llf-noise parts of the 2
equivalent input voltage noise dv n,eq . 14. Settling time for a settling margin E if the phase margin M < 76.35°: (9-24)
15. Settling time for a settling margin E if the phase margin M > 76.35° :
Ts (e) =
sin 2 (M) [-In (e) 4cos ( M)] GB 1- 1 - - - - 2cos (M) . 2 (m )
sin
(9-25)
'I'M
One can also add additional expert knowledge about the circuit to the symbolic model under the form of extra analytic equations. For example, for the folded-cascode OTA of Fig. 9.5, a good heuristic to reduce the offset voltage in the circuit is to choose the current in the input stage equal to the current in the output stage: (9-26) Such symbolic design equations as shown here may not only be derived for operational amplifiers, but for any type of analog functional block, such as voltage and current references, comparators, output buffers, filters, etc., although not always automatically with a symbolic analysis tool and sometimes only with approximate accuracy.
Sec.9.3 Automated AnalogDesign as an Optimization Problem Based on Compiled Symbolic Models
245
9.3.2. The Independent Optimization Variables The generation of the symbolic design equations is only the first step toward analog design optimization. The second step is the identification of the independent variables that are varied by the optimization program in search of the optimum design solution. In general, the program has to determine the optimal values for all the parameters of the subblocks within the circuit architecture under design (e.g., the gain and gain-bandwidth of the op-amp within a filter) so that all specifications for the top circuit are satisfied and the objective function is minimized. At the lowest level in the design hierarchy, this means determining all operating-point voltages and currents, bias sources, element values, and device sizes in the circuit. For a resistor, the value of the resistance needs to be determined. For a capacitor, the value of the capacitance needs to be determined. For a bias source, the value of the bias voltage or bias current needs to be determined. For each bipolar transistor, the current needs to be determined. For each MOS transistor, three variables need to be determined: • two variables out of the following three: the current I D' the saturation voltage (VGS - V r)' or the aspect ratio W/ L; • one variable out of the following two: the width W or the length L. These variables are related by a device equation, depending on the operating region, such as (9-27) An advantage of using currents and saturation voltages as variables for aMOS transistor is that they determine the dc operating point of the device and allow us to explicitly control the operating region (e.g., saturation in strong inversion). Also, it is easy to calculate the small-signal elements of a device, given the de operating point, by using a device model of any desired accuracy (e.g., a simple hand-calculation model or the complete SPICE model). This model can be a completely separate module within the optimization program (e.g., the device routines of SPICE could be linked to the optimization program). For the example of the CMOS folded-cascode OTA of Fig. 9.5, which contains 10 MOS transistors and four bias voltage sources, the following 34 design variables can be identified: I D I A , I D I B , I D 2A , I D 2B, I D 3A, I D 3B , I D4A, I D4 B, IDS' I D 6
(VGS - Vr ) lA' (VGS - Vr ) IB' (VGS - Vr ) 2A ' (VGS - Vr ) 2B ' (VGS - Vr ) 3A (VGS-Vr ) 3B ' (VGS-Vr ) 4A ' (VGS-Vr ) 4 B ' (VGS-Vr ) 5' (VGS-Vr ) 6 L I A, LIB' L 2A, L 2B, L 3A, L 3B, L 4A, L 4B, L 5, L 6,
VB I , VB 2 , VB 3 , VB4
In general, however, these design variables are not totally independent of each other. Instead, they can be reduced to a set of independent design variables by means of
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general constraints, such as Kirchhoffs current and voltage law, e.g.,
(9-28) circuit-specific constraints, such as matching information, e.g.,
(9-29) designer constraints, such as offset-reduction rules, e.g.,
(9-30) These constraints are also expressed as analytic equations and are simply added to the symbolic model of the circuit. The remaining number of independent variables is the number of degrees of freedom in the design of the analog circuit. Sizing the circuit is equivalent to determining values for these remaining independent design variables..Once the independent variables are assigned values, then the circuit is fully characterized and all other variables and the total circuit performance can be calculated by numerically evaluating the design equations in the symbolic model that relate all variables and the performances. Therefore, it is quite obvious to use the set of independent variables as the optimization variables that are varied by the analog design optimization program in order to optimize the goal function. For the example of the CMOS folded-cascode OTA of Fig. 9.5, the 34 variables are, in this way, reduced to 15 degrees of freedom. A set of independent optimization variables for this op-amp is then
These independent variables are optimized by the optimization program, as will be illustrated in section 9.4. Note, however, that the set of independent variables in general is not unique and that other variables (e.g., aspect ratios instead of saturation voltages) could equally well be taken in this set. The identification of the independent design variables, the equations relating dependent and independent design variables, and the symbolic equations relating the circuit performance to the design variables (and possibly additional analog expert knowledge about the circuit) are then all collected into a compiled symbolic model, that is, they are numerically evaluated at each iteration of the optimization program with different values for the independent variables in order to check the corresponding performance of the circuit against the specifications and to optimize the goal function. To allow the numerical evaluation, it must be indicated how and in which order the unknowns (dependent variables and performances) are to be solved from the equations. This might be trivial when the equations are explicit assignments such as in the example of the folded-cascode op-amp in the previous section, but in general it is not. Instead of having the designer define such a computational path, however, the numerical solution plan for a given set of independent variables can automatically be generated and compiled into the symbolic model by an equation manipulation program such as DONALD [13]. Such a tool again adds to the openness of an analog design system based on this approach.
Sec.9.3
Automated Analog Design as an Optimization Problem Based on Compiled Symbolic Models
247
9.3.3. The Analog Design Optimization Formulation The specification translation, or sizing, of an analog circuit in the optimizationbased approach is then, in general, defined as a constrained optimization problem [10]. Mathematically, this is formulated as Find the value of x that minimizes \fJ (x) subjected to the following constraints: gi(X) ~o h.(x) J
'Vi = 1, ... ,m 'Vj = 1, ... , n
=0
(9-31 )
where x is the vector of the independent variables as determined above, \II(x) is the goal function that can combine multiple design objectives, g i(x) are inequality constraints, and
h .(x) are equality constraints. The values of the goal function and of the constraints are all J
obtained by numerically evaluating the compiled symbolic model for each set of values for the independent variables x . The performances of the analog circuit can be specified in two different ways, either as objective or as constraint: • Performance objectives are minimized (or maximized) by the program and are therefore incorporated in the objective function. For op-amp designs, this function can, for instance, be the power consumption, the chip area, the noise, the frequency range (bandwidth), or any weighted combination of these and/or other design targets. • Other performance characteristics are specified as constraints (boundary conditions) that have to be satisfied. These constraints can be of the inequality type (a specified lower or upper limit) or of the equality type (a specified center value). For example, for an operational amplifier, a minimum dc gain of 80 dB can be required, whereas for a wideband amplifier, a gain of exactly 6 dB can be requested. In some cases, these constraints are divided into hard constraints, which have to be met at any price, and soft constraints, which can be relaxed to some extent when needed. In addition, other boundary conditions can be imposed on the independent variables or, in general, on all design variables. A typical example is the requirement for all capacitor or resistor values in the circuit to be larger than or equal to zero in order to allow any physical realization. These conditions are usually fulfilled by construction for the independent variables, but have to be checked for all dependent variables as well. In most cases, the objective function \II(x) in automated analog design consists of a weighted sum of scaled contributions from the different performance characteristics that are specified as design objectives: 'P(x)
=
p ,(X) ]
La.;! [ -'-*i
Pi
(9-32)
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where Ow; is the weighting coefficient that indicates the relative importance of design objective Pj(x), f is some mathematical function, and P; is an acceptable value that scales the contribution of performance Pj(x). The weighting coefficients and the acceptable values have to be provided by the user of the program. The weighting coefficients allow the designer to explore trade-offs between the different design objectives. For example, for an op-amp, a mixed power-area minimization can be performed or the trade-off between noise and area can be investigated. Instead of a weighted summation, a min-max formulation is sometimes used as well for the goal function, but this is not appropriate in combination with certain optimization algorithms. The constraints; on the other hand, can be handled in essentially two different ways. The first possibility is to include them as barrier or penalty functions to the objective function. These barrier functions (e.g., exponentials) then penalize constraint violations and force the solution to lie within the region of independent variable values where all constraints are satisfied. The second possibility that can be used in combination withcertain optimization algorithms (e.g., simulated annealing) is to simply reject each design point suggested by the optimization routine that does not satisfy the constraints and to only consider valid solutions during the optimization. The constraints can also be active directly from the beginning of the optimization, or become more and more active in the course of the optimization so that they are satisfied at the end. The complete flow of analog design optimization based on compiled symbolic models is then as follows: /* preprocessing */ derive the symbolic equations derive a set of independent variables compile the symbolic model while (no convergence) do { /* main optimizationloop */ select values for the independent variables evaluate the symbolic model to obtain the performances check the constraints calculate the goal function update the intermediate design solution (if accepted) } return the final design solution /* output */
Geometrically, one can view the whole analog design optimization process as follows. An analog circuit can be viewed as a multidimensional space spanned by the independent design variables. Each combination of values for the independent variables (i.e., each design point in this multidimensional space) defines a different design instance of the circuit, each with its own performances. The valid design space for a particular application then consists of those points that satisfy the design constraints (both inequalities and equalities). To each point in the design space there also corresponds a value of the objective function. The goal of analog design optimization is then to search in the valid, or feasible, design space for the point that optimizes the objective function. This approach is now illustrated in the following section for some practical analog design systems.
Sec. 9.4
Examples of Analog Design Systems Using Symbolic Models
249
9.4. EXAMPLES OF ANALOG DESIGN SYSTEMS USING SYMBOLIC MODELS 9.4.1. The OPASYN Program The first equation-based analog optimization tool published was OPASYN [8], developed at the University of California, Berkeley (USA). It is a compiler for CMOS op-amps, which accepts specifications and technology data and generates a correct layout of an optimized op-amp. After rule-based selection of an appropriate op-amp architecture, the sizing of this op-amp is performed as a parametric optimization based on a symbolic model of the op-amp. This model consists of a large set of nonlinear analytic equations describing the op-amp's performance, some a priori design decisions, and the list of independent design variables. This list has been strongly reduced during the development of the model by exploiting expert design knowledge. The analytic design equations have also been derived completely manually by an expert designer using first-order circuit analysis techniques and architecture-specific approximations. The equations contain fitting parameters, which allow one to improve the accuracy of the symbolic model by tuning with the results from SPICE simulations. The optimization itself is based on a steepest-descent algorithm. The program always returns a solution, namely the circuit that best matches the specifications (also if it does not meet all specifications). To overcome the problem of getting stuck in a local optimum, the algorithm is started from coarse-grid-sampled multiple starting points. The algorithm also requires a continuous first derivative and has only limited constraint-handling capabilities [8]. The optimization results for the op-amps in the program's database, however, are quite good and are obtained quite quickly (typically 1 min of CPU time on a VAX 8800). The approach was extended to a cyclic analog-to-digital converter architecture later on [14]. The major drawback of the OPASYN tool is that the symbolic model for a new circuit architecture must first be created manually by a good analog designer, which is a tedious and error-prone job. Introducing a new schematic in the program's database therefore requires an enormous effort, which limits the practical usefulness of the system.
9.4.2. The OPTIMAN Program The drawback of the OPASYN tool is, to a large extent, overcome in the OPTIMAN program [7], developed at the Katholieke Universiteit Leuven, Leuven (Belgium). The equations for all small-signal characteristics in the symbolic design model are derived automatically by means of the symbolic analysis program ISAAC [11]. The equations for the other characteristics still have to be provided by the designer. In the initial version of the OPTIMAN program [7], which performs a global optimization of the circuit design starting from specifications and technology data, the designer also had to define the solution plan to numerically evaluate the equations in the symbolic model during the optimization. Although this approach has successfully been applied to the design of op-amps and switched-capacitor filters, it still restricted the extension capabilities of the program. Therefore, in recent years, the program has been included in the open analog design system ARIADNE [15]. In this system, an explicit distinction is made between the derivation of context-independent circuit knowledge (partially by programs and by the designer) and the use of that knowledge within a specific design context (by dedicated
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routines within the system). All knowledge is defined as analytic equations, which in a generalized view are considered as declarative equations that express a relationship between variables, but do not a priori indicate how the equations have to be evaluated. This implies that the equations do not necessarily have to be explicit expressions, such as in example 9.1, and that any variable in the equations in principle can be selected for the set of independent optimization variables, even the performances (although some variables might be better from the point of numerical stability). For any actual design application, the context-independent declarative symbolic design equations, coming both from ISAAC and the designer, are then automatically transformed by the equation manipulation program DONALD [13] into a form that is suitable for the optimization. To this end, DONALD performs the following tasks: it determines the degrees of freedom in the design, selects a set of independent variables, and for this set creates a dedicated computational path that indicates how and in which order the symbolic equations (some subsets possibly simultaneously) have to be solved to evaluate the circuit performance. Based on this compiled solution plan, OPTIMAN then sizes the circuit such that it satisfies all performance specifications and such that a user-defined goal function is optimized. The combination of ISAAC and DONALD (for the creation of the compiled symbolic model) and OPTIMAN (for the global design optimization) make the ARIADNE system a flexible and open analog design environment that is not restricted to a predefined set of circuit schematics [15]. The optimization algorithm used in the OPTIMAN program is simulated annealing [16]. This is a general and robust probabilistic optimization method that explores the design space by making a large number of random moves (i.e., by randomly selecting new values for the independent variables). As it also accepts uphill moves according to a statistical criterion, simulated annealing can find the global optimum of a function, though at the cost of a large number of function evaluations. It is also solely based on function evaluations and does not need any derivatives, which makes it applicable to almost any circuit optimization. Therefore, simulated annealing offers general applicability, flexibility, and good quality of the obtained optimum at the expense of considerable CPU times. In OPTIMAN [7], inequality constraints are handled by simply rejecting a move to a state that does not satisfy all inequalities. For equality constraints, on the other hand, the statistical nature of simulated annealing makes the probability of generating a state that satisfies all equality conditions practically zero. The equality constraints are therefore added to the objective function as additional terms with weighting coefficients that become more and more important toward the end of the optimization. The total goal function is therefore a weighted sum of the design objectives that have to minimized and the equality constraints: \f(x)
-I c.(Pi(X») I~(lhj(x)l) + . * } T -
i
I
Pi
(9-33)
j
where T is the temperature parameter used in the annealing process and ~. is the weighting coefficients for the equality constraints. } The application of an efficient and adaptive annealing schedule allows us to keep the CPU times acceptable, also for large circuits. The general flow of the OPTIMAN program is then as follows:
Sec. 9.4
251
Examples of Analog Design Systems Using Symbolic Models
generate an initial solution and initial temperature while (temperature_stop_criterion not satisfied) do { while (inner_loop_criterion not satisfied) do { generate new values for the independent variables calculate the dependent variables and performances check all inequality constraints calculate the goal function if (move accepted with statistical criterion) then update solution decrease temperature }
read out final solution The capabilities of the OPTIMAN program are now illustrated by means of some practical design examples. EXAMPLE 9.2
The example taken here is the optimization of the CMOS folded-cascode OTA of Fig. 9.5. The symbolic model and the 15 independent variables of this op-amp have been described in sections 9.3.1 and 9.3.2, respectively. The technology process used is MIETEC 3 urn CMOS n-well. In the first experiment, a design has been optimized toward minimum power and area consumption for the specifications given in Table 9-2 and for a capacitive load of 50 pF with +2.5/-2.5 V supply voltages. A gain-bandwidth of 1 MHz requires a biasing current of 64 flA for that load. Table 9-2 shows the specifications and the corresponding performances obtained by OPTIMAN, as well as the results from HSPICE simulations for Table 9-2 Comparison of Specifications, OPTIMAN Data, and HSPICE Simulation Results for a Minimum Power and Area Design of the CMOS Folded-Cascode OTA of Fig. 9.5
Performance
Specification
OPTIMAN
HSPICE
1.014
0.993
gain-bandwidth [MHz]
~
power [mW]
s 1.0
0.64
0.67
gain [dB]
~60
66.7
70.7
phase margin [0 ]
~60
89.1
87.4
1.0
slew rate [V/Jls]
~
0.13
1.27
1.13
output noise [ JlVRM S ]
~200
47.6
15.9
output range [V]
~
1.0
1.05
1.32
input range [V]
~
1.0
1.0
1.09
offset [mY]
~0.5
0.47
1.6
settling time Iusl
~50
4.47
1.16
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Chapter 9
Automated Analog Design Using Compiled Symbolic Models
O.7 .---_--r-----,---r-----r---,---r--...,-----r--r-~
0.6
7ii'
E
>
.s0.5 (J) f/)
'0 c
~O.4 E
,...... I
~
m0.3 ~
§' SO.2 Q) ~
o a.
0.1
oL-_--l.----L--.l.----L-----I--.....l---~:--__=~-~-_:
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.9
0.8
1.1
gain-bandwidth [MHz]
7
Figure 9.6 Power (in mW - straight line), area (in 10- mm
2
- dotted line), and
noise (in m V RM S - starred line) as a function of the gain-bandwidth specification (in MHz) for the CMOS folded-cascode OTA of Fig. 9.5.
the resulting optimum design. Notice the close correspondence between all values, which demonstrates that symbolic models can model the circuit behavior accurately enough to be used in analog synthesis. Typically, most inaccuracies are on characteristics such as the settling time or the output range, the expressions for which cannot yet be generated automatically by a symbolic analysis tool. The optimization required 46 s of CPU time on a SUN Sparcstation IPX. Figure 9.6 shows how the power consumption, the area, and the integrated output noise vary as a function of the gain-bandwidth specification for this op-amp. The larger the gain-bandwidth, the more power and area is required, but also the smaller the integrated output noise. By selecting different weighting coefficients in the goal function, the designer can trade off different design objectives against each other (e.g., power versus noise). Table 9-3 shows the final optimized values for the 15 independent variables in the symbolic model of the CMOS folded-cascode op-amp of Fig. 9.5 for four different designs with the same set of specifications already shown in Table 9-2, but with different optimization objectives: power minimization, area minimization, noise minimization, and gain-bandwidth maximization. (The saturation voltages in this example are bounded to vary between 0.2 V and 0.5 V, the biasing current is limited to IOOJlA, and the minimum transistor length is 3Jlm.) The trade-off between area and integrated output noise in this op-amp is shown in Fig. 9.7, where, for the same value of gain-bandwidth and consumed power, different values of area and noise are obtained depending on the values of the independent variables.
Sec. 9.4
253
Examples of Analog Design Systems Using Symbolic Models
Table 9-3 Optimization Values for the Independent Variables for a Power Minimization, an Area Minimization, a Noise Minimization, and a Gain-Bandwidth (GB) Maximization of the CMOS Folded-Cascode OTA of Fig. 9.5 for the Same Set of Specifications
Variable
Power
Area
Noise
GB
IDI
32.0 flA
32.0 flA
50.0 flA
50.0 flA
(V GS - V T ) I
0.20 V
0.20 V
0.20 V
0.20 V
(V GS- V T) 2
0.34 V
0.50V
0.50 V
0.27 V
(V GS - V T) 3
0.31 V
0.50 V
0.20 V
0.50 V
(V GS-VT ) 4
0.27 V
0.36 V
0.50 V
0.21 V
(V GS - V T) 5
0.30 V
0.28 V
0.20 V
0.50 V
(VGS- V T ) 6
0.32 V
0.40 V
0.38 V
0.36 V
LI
13.0 urn
3.0
urn
18.0 urn
18.0 urn
L2
6.0
urn
3.0
urn
18.0 urn
3.0
urn
L3
8.0
urn
3.0
urn
18.0 urn
3.0
urn
L4
15.5 urn
3.0
urn
17.0 urn
18.0 urn
L5
7.0
urn
3.0
urn
18.0 urn
3.0
L6
14.0 urn
3.0
urn
12.0 urn
14.0 urn
VB I
0.45 V
0.15 V
0.35 V
0.15 V
V B2
-0.30 V
-0.60 V
-0.90 V
-0.40 V
urn
9.4.3. The ASTRXlOBLX Tool The ASTRXlOBLX tool [17], developed at Carnegie Mellon University, Pittsburgh (USA), uses a hybrid approach toward analog circuit sizing, which draws elements from both equation-based and simulation-based optimization. A new formulation of the sizing problem is applied that uses de-free biasing and asymptotic waveform evaluation. De-free biasing means that no de bias equations have to be provided by the designer and that no full de solution is performed at each optimization iteration. Instead, the node voltages are added to the set of independent variables that are varied randomly and the resulting violations of Kirchhoffs current law (KCL) are simply added as additional terms to the cost function and are driven to zero in the course of the optimization. To evaluate the performance of the circuit at each iteration of the optimization, a numerical simulator based on the technique of asymptotic waveform evaluation (AWE) is used for all small-signal characteristics. An expert designer must still provide the symbolic equations for the transient and large-signal characteristics. Compared to OPASYN [8] and
254
Chapter 9
Automated Analog Design Using Compiled Symbolic Models
50r------~----~------r-----.-------...,
45
40
I35
>
2. Q)
(/J
·030 c
25
20
15L.-----....1...---------L--------L-----"'"--------' 0.2 0.25 0.1 0.15 0.05 o area [mmI\2] Figure 9.7 Trade-off between area and noise for a fixed gain-bandwidth and power consumption for the CMOS folded-cascode OTA of Fig. 9.5.
OPTIMAN [7], the use of AWE eliminates the need to derive the symbolic equations for the small-signal characteristics, but also results in larger CPU times for the optimization. Based on this formulation, the performance of the circuit is then optimized by the OBLX program, which uses simulated annealing as the optimization algorithm. The cost function is a weighted sum of design objectives, inequality constraint violations, and KCL violations. Starting from the circuit netlist and the few additional designer-provided symbolic equations, the ASTRX front-end program automatically generates and compiles the code that is needed to evaluate the circuit performance and to calculate all of the goal function's cost terms at each OBLX iteration. A typical CPU time for a fully differential op-amp is 37 min on a 60-MIPS workstation, of which about 92% is consumed by AWE [17]. The same analog sizing formulation has also been solved using a sequential quadratic programming optimization algorithm, as reported in Ref. [18].
9.4.4. ASigma-Delta Modulator Synthesis Tool The University of Sevilla, Sevilla (Spain), has developed a tool that uses equation-based optimization for the specification translation of switched-capacitor sigma-delta analog-to-digital converters [19]. The high-level converter specifications (resolution, bandwidth, and oversampling ratio) are translated into optimum specifications for the subblocks (op-amps, comparator, switches, etc.) in the converter architecture. The performance (resolution) of the converter is evaluated at each iteration using behavioral representations for the different noise sources and nonidealities that limit the converter's
Sec.9.5
Conclusions
255
resolution. These behavioral representations are supported by symbolic equations that are provided by a designer after exhaustive noise analysis of the converter architecture. This equation-based inner optimization loop is supervised by an outer loop, where the resulting converter performance is evaluated by means of a behavioral simulator and which restarts the inner loop if the specified resolution is not obtained. Once the specifications of the subblocks are calculated, they are translated to optimum sizes of the components (transistors, resistors, and capacitors) in the analog building blocks by calling a simulator at each iteration instead of using equations [20]. The specification translation is performed using a statistical optimization algorithm, a variant of simulated annealing, with fast cooling and reheating when necessary. The goal function is a min-max formulation of the design objectives and the violations of soft inequality constraints. The use of several heuristics allows one to increase the efficiency of the algorithm and to obtain a global design independent of the initial starting point. This results in a typical CPU time of 5 s on a SUN Sparcstation for the high-level synthesis (specification translation only) of a second-order sigma-delta converter.
9.4.5. A Switched-Capacitor Filter Synthesis Tool The last example system described here is the synthesis of switched-capacitor filters. Filters in general (passive, active RC, switched-capacitor, switched-current, and continuous-time) lend themselves in a natural way to the approach of optimization based on compiled symbolic models. As described in this book, the transfer functions of these filters can easily be derived in symbolic form as a function of the filter elements and the frequency by existing symbolic analysis programs. Switched-capacitor filters, for example, can symbolically be analyzed in the z-domain by programs such as ISAAC [11] or SCYMBAL [21]. Filter synthesis then consists of several steps. In the first step, the specifications on the amplitude, phase, or group delay behavior in the frequency domain are translated into a mathematical transfer function. In the second step, this transfer function is then synthesized by selecting an appropriate filter structure (often described by means of a signal flow graph) and by determining the proper filter element values and subblock parameters in this structure. The latter step can easily be performed by means of optimization, where the functions describing the filter structure are compiled into a symbolic model. The optimum element values are then determined so that the specified transfer function is realized while some design objectives are minimized. This technique has been applied in OPTIMAN to minimize the switch noise in switched-capacitor filters [7]. But the switched-capacitor filter compiler reported in Ref. [22] also has a symbolic simulator integrated.
9.5. CONCLUSIONS In this chapter, an application of symbolic analysis in the automated design of analog integrated circuits has been presented. How analog specification translation and circuit sizing can be performed by means of optimization based on compiled symbolic models that describe the performance behavior of the circuit has been described. Compared to other approaches, this technique offers a good compromise between required CPU time, flexibility in design objectives, quality of the resulting design, and effort to introduce new
256
Chapter 9
Automated Analog Design Using Compiled Symbolic Models
schematics into the system. The evaluation of a symbolic model, instead of performing a full numerical simulation at each iteration, speeds up the optimization while sacrificing only a little bit of accuracy. In addition, most of the equations in the symbolic model are generated automatically by means of symbolic simulation programs. Symbolic analysis therefore provides a way to create an open analog synthesis system that is not limited to the built-in circuit schematics, but can be extended by the designer alone. The analog design optimization approach based on compiled symbolic models has been discussed in detail in this chapter. Starting from the symbolic equations, a set of independent optimization variables is derived and a computational evaluation plan is constructed. All this is then compiled into the symbolic model that is evaluated at each iteration of the optimization program in search of the optimum design solution that satisfies all specifications while minimizing some design objectives. Several practical analog design systems following this approach have been presented, including programs for op-amp sizing as well as for high-level filter and data converter synthesis. This has been illustrated with some practical design examples, showing the usefulness and efficiency of the approach.
References [1] G. Gielen, K. Swings, and W. Sansen, "Open analog synthesis system based on declarative models," ch. 18 in Analog Circuit Design (J. Huijsing, R. van der Plassche, and W. Sansen, Eds.). Dordrecht: Kluwer Academic, pp. 421-445, 1993. [2] E. Malavasi et aI., "A top-down, constraint-driven design methodology for analog integrated circuits," ch. 13 in Analog Circuit Design (J. Huijsing, R. van der Plassche, and W. Sansen, Eds.). Dordrecht: Kluwer Academic, pp. 285-324, 1993. [3] F. EI-Turky and E. Perry, "BLADES: An artificial intelligence approach to analog circuit design," IEEE Trans. Computer-Aided Design, vol. 8, no. 6, pp. 680-692, June 1989. [4] M. Degrauwe, "IDAC: An interactive design tool for analog CMOS circuits," IEEE J. Solid-State Circuits, vol. 22, no. 6, pp. 1106-1116, December 1987.
[5] R. Harjani, R. Rutenbar, and L. Carley, "OASYS: A framework for analog circuit synthesis," IEEE Trans. Computer-Aided Design, vol. 8, no. 12, pp. 1247-1266, December 1989. [6] G. Beenker, J. Conway, G. Schrooten, and A. Slenter, "Analog CAD for consumer ICs," ch. 15 in Analog Circuit Design (J. Huijsing, R. van der Plassche, and W. Sansen, Eds.). Dordrecht: Kluwer Academic, pp. 347-367, 1993. [7] G. Gielen, H. Walscharts, and W. Sansen, "Analog circuit design optimization based on symbolic simulation and simulated annealing," IEEE J. Solid-State Circuits, vol. 25, no. 3, pp. 707-713, June 1990. [8] H. Koh, C. Sequin, and P. Gray, "OPASYN: A compiler for CMOS operational amplifiers," IEEE Trans. Computer-Aided Design, vol. 9, no. 2, pp. 113-125, February 1990. [9] W. Nye, D. Riley, A. Sangiovanni-Vincentelli, and A. Tits, "DELIGHT.SPICE: An optimization-based system for the design of integrated circuits," IEEE Trans. Computer-Aided Design, vol. 7, no. 4, pp. 501-519, April 1988. [10] G. Gielen and W. Sansen, Symbolic Analysis for Automated Design of Analog Integrated Circuits. Dordrecht: Kluwer Academic Publishers, 1991.
References
257
[11] G. Gielen, H. Walscharts, and W. Sansen, "ISAAC: a symbolic simulator for analog integrated circuits," IEEE J. Solid-State Circuits, vol. 24, no. 6, pp. 1587-1597, December 1989. [12] F. V. Fernandez, A. Rodriguez-Vazquez, and J. L. Huertas, "Interactive AC modeling and characterization of analog circuits via symbolic analysis," Int. J. Analog Integrated Circuits and Signal Processing, vol. 1, pp. 183-208, November 1991. [13] K. Swings and W. Sansen, "DONALD: A workbench for interactive design space exploration and sizing of analog circuits," Proc. European Con! Design Automation, pp. 475-479,1991. [14] G. Jusuf, P. Gray and A. Sangiovanni-Vincentelli, "CADICS - Cyclic analog-to-digital converter synthesis," Proc. Int. Con! Computer-Aided Design, pp. 286-289, 1990. [15] K. Swings and W. Sansen, "ARIADNE: A constraint-based approach to computer-aided synthesis and modeling of analog integrated circuits," Int. J. Analog Integrated Circuits and Signal Processing, vol. 3, pp. 197-215, 1993. [16] S. Kirkpatrick, C. Gelatt Jr., and M. Vecchi, "Optimization by simulated annealing," Science, vol. 220, no. 4598, pp. 671-680, May 1983. [17] L. Carley, P. Maulik, E. Ochotta, and R. Rutenbar, "Analog cell-level synthesis using a novel problem formulation," ch. 14 in Analog Circuit Design (J. Huijsing, R. van der Plassche, and W. Sansen, Eds.). Dordrecht: Kluwer Academic, pp. 325-346, 1993. [18] P. Maulik and L. Carley, "Automating analog circuit design using constrained optimization techniques," Proc. Int. Con! Computer-Aided Design, 1991. [19] F. Medeiro, B. Perez-Verdu, A. Rodriguez-Vazquez, and J.L. Huertas, "A vertically-integrated tool for automated design of L~ modulators," IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 762-772, August 1995. [20] F. Medeiro, R. Rodriguez-Macias, F.V. Fernandez, R. Dominguez-Castro, J. L. Huertas, and A. Rodriguez-Vazquez, "Global design of analog cells using statistical optimization techniques," Analog Integrated Circuits and Signal Processing, vol. 6, no. 3, pp. 179-195, November 1994. [21] A. Konczykowska and M. Bon, "SCYMBAL 2: a portable computer program for efficient all-symbolic hierarchical analysis of large, multi-phase switched-capacitor networks," Proc. European Con! Circuit Theory and Design, Stuttgart, pp. 375-378,
1983. [22] J. Assael, P. Senn, and M. Tawfik, "A switched-capacitor filter silicon compiler," IEEE J. Solid-State Circuits, vol. 23, no. 1, pp. 166-174, February 1988.
10 M. Helena Fino Universidade Nova de Lisboa Lisboa, Portugal Jose E. Franca Instituto Superior Tecnico
Symbolic Signal Flow Graph Methods in Switched-Capacitor Design
Lisboa, Portugal Adolfo Steiger Garyao Universidade Nova de Lisboa Lisboa, Portugal
10.1. INTRODUCTION In previous chapters the use of symbolic methods has been largely dedicated to the lower levels of analog circuit design encompassing circuit elements such as amplifiers and comparators [1]-[3]. In this chapter, we shall describe symbolic signal flowgraph (SPG) computational techniques for the analysis and synthesis of switched-capacitor (SC) circuits. This is based on a hierarchical approach in which signal-processing building blocks are defined in terms of basic elements whose characterization resides in a knowledge base. This knowledge base can be developed both for analog and digital discrete-time building blocks using the common SPG representation of their operation but, for conciseness, we shall consider herein its specific implementation only for discrete-time SC signal-processing building blocks. Besides the Introduction, this chapter comprises six additional sections. Section 10.2 discusses the flow of information for circuit analysis and synthesis of SC building blocks and establishes the hierarchical plans to be considered for the development of an automated design environment. Section 10.3 describes the SPG-based method for generating the symbolic transfer functions of SC networks. After giving a brief description of the SC elementary blocks and the corresponding SFG representation, we shall introduce a simple rule-based approach for automatic identification. Then, section 10.4 describes the symbolic analyzer where a pattern matching technique is used for generating the SFG representation of SC building blocks and for yielding the corresponding symbolic z-domain transfer function. The use of such a symbolic analyzer is discussed in section 10.5 for carrying out highly flexible step-by-step synthesis of SC building blocks and in
258
Sec. 10.2
259
Analysis and Synthesis in Circuit Design
section 10.6 for automatic knowledge capturing of those SC building blocks. Finally, section 10.7 summarizes and concludes the chapter.
10.2. ANALYSIS AND SYNTHESIS IN CIRCUIT DESIGN Circuit design can be broadly characterized by the close interrelation of synthesis and analysis procedures. Here, we define synthesis as the process through which the designer usually assembles simple, fully characterized circuit primitives to create more complex, unknown circuit topologies. These circuit topologies are then characterized and verified using analysis procedures, which throughout this chapter are based on .symbolic computational techniques. This section provides a simple description of the basic flow of information for both analysis and synthesis, as well as the most relevant procedures required for automating both.
10.2.1. Flow of Information for Analysis Figure 10.1 illustrates the flow of information during the analysis of a simple SC building block. Once the description ofa building block is given, an interpretation process identifies the constituting SC elementary blocks and then characterizes each of them in order to determine the behavior of the overall SC building block. Such interpretation is
Building Block Description
- (1 / b)
(1 - z-I ) Itt
Equation Extractor
Numerical Instantiation
H(z)
=
- 1/2
a......z b(1-z-
ae l, b=2 => H(z)
1
......
_
1)
Z
- 1/2
=---num 2(1-z- 1
100
Evaluation
80
60
Figure 10.1 Flow of information during the analysis of an SC building block.
260
Chapter 10
Symbolic Signal Flow Graph Methods in Switched-Capacitor Design
carried out based on a set of primitives usually consubstantiated in a set of rules that define the structure of the elementary blocks and the corresponding characterization. From the interpretation process, the SFG representing the operation of the SC building block is obtained. An equation extractor is then applied to such an SFG, yielding the symbolic z-domain transfer function of the building block under analysis. Later, the transfer function symbols can be instantiated to numerical values so that, in the evaluation phase, the frequency response of the circuit is obtained and relevant performance criteria are evaluated.
10.2.2. Formulation Method for Building Block Interpretation As previously mentioned, the building block interpretation is based on a set of primitives that characterize the SC elementary blocks and is usually accomplished in two phases. In the identification phase, the building block description is browsed so that by applying appropriate pattern-matching techniques, all the constituting elementary blocks are recognized. Then, in the characterization phase, the characterization of each one of the constituting elementary blocks is computed and the overall characterization of the building block is thus obtained. In order to assist the interpretation process for the characterization of the building block, the core of primitives should provide one set of rules concerned with the identification phase of the interpretation process, and another set of rules concerned with the evaluation of the characterization of the elementary blocks. Later, in section 10.3, we shall discuss the relevant rules for the core of primitives for SC analysis and synthesis that are based on discrete-time SFG representation techniques.
10.2.3. Flow of Info.rmation for Synthesis The typical flow of information during the synthesis of an SC building block circuit is represented in Fig. 10.2. The first step consists of obtaining the numerical z-domain transfer function to meet the target specifications. This is accomplished using well-known computer-based routines, e.g., Ref. [4], and therefore will not be considered here. The second step is the building block topology synthesis, where the topological characterization of a building block is obtained and the corresponding symbolic z-domain transfer function is evaluated. This step makes use of the same set of primitives previously mentioned for analysis and that characterizes the relevant SC elementary blocks. In the dimensioning phase, the symbolic expressions of the coefficients of the z-domain transfer function are equated to the previously obtained numerical coefficients. Because the resulting system of equations is usually not solvable by algebraic means, it is necessary to place additional constraints on the symbolic expressions of the coefficients. These constraints are usually based on structural knowledge of the building block topology. Finally, in the evaluation phase, the frequency response of the building block is obtained and relevant performance criteria, e.g., variability of the frequency response against capacitance ratio errors, are evaluated.
Sec. 10.2
261
Analysis and Synthesis in Circuit Design
Numerical Specifications
• 1/2
z 2 (1 - z: I )
H(z) =
1 y
BuildingBlock Topology Synthesis
~~~-IIWC -
~.J::
1
-a.z .. 1/2.. EquationExtraction
,
Dimensioning
~,
Building Block Description
~r
Evaluation
...1/_
~
- (lIb)' (l:r 1 ) .. 1
and~ r:
• 1/2
H(z) = 6
=
z
- 1/2
2 (1 - z: 1
-~~~*~ -
)
~ z: 1
100 80 60
~
-
Figure 10.2 Typical flow of information for synthesis of an SC building block.
10.2.4. Equation Extractor for Dimensioning In the flow of information for analysis, we have introduced an equation extractor responsible for producing the symbolic z-domain transfer function of the SC building block represented by the appropriate SFG. In the synthesis process, however, the equation extractor must also produce additional equations introducing constraints on the symbolic expressions of the coefficients in order to make it possible to automatically dimension all the building block parameters. The equations are based on structural information of the building block and may be automatically evaluated by applying a structural evaluator to the netlist description of the block. The particular case for SC networks will be described in detail in section 10.6.
262
Chapter 10
Symbolic Signal Flow Graph Methods in Switched-Capacitor Design
10.3. SC PRIMITIVES AND IDENTIFICATION TECHNIQUES 10.3.1. SFG Representation of SC Elements SC networks consist of the interconnection of SC elementary blocks, comprising such elements as switches, capacitors, and operational amplifiers, whose discrete-time operation is characterized with respect to the associated timing diagram. By using classical SC circuit analysis techniques [5]-[7], we can derive for various SC elementary blocks the corresponding SFG representation, as summarized in Fig. 10.3. Note that all SC elementary blocks represented here refer to the same timing diagram indicated at the bottom of the figure. Some icons are also indicated in order to simplify schematic representations. All SFGs shown in Fig. 10.3 comprise three different transmission factors, za, zb, and K, that provide physical insight into the operation of the corresponding SC elementary blocks. The transmission factors za and zb represent, respecti vely, the time delay (advance) of the input and output sampling instants of the SC elements with reference to the associated timing diagram. The transmission factor K indicates the relationship between the sampled input and output variables. When the SC element transforms a sampled input voltage signal into a sampled output packet of charge, K represents the equivalent capacitance value, as is the case of all quasi-passive SC elementary blocks, i.e., toggle switched-inverter (TSI), open floating resistor (OFR), toggle switched-capacitor (TSC), parasitic-compensated toggle switched-capacitor (PCTSC), and inverting parasitic-compensated toggle switchedcapacitor (IPCTSC) [8]. In the case of the active SC elementary block also represented in Fig. 10.3, K represents the equivalent transimpedance value (here the inverse of a capacitance) describing the transformation of a sampled input packet of charge into a sampled output voltage signal. The sign associated with the transmission factor K indicates the phase of the input (output) variables with respect to the positive reference phases. Positive voltages are defined from a node to ground, while positive packets of charge are defined for a flow into an output node or for a flow from an input node.
10.3.2. Rule-Based Identification For the identification of the SC elementary blocks comprising a given SC network, a pattern-matching technique is employed based on structural rules residing in the system knowledge base. An example of the Prolog [9] structural rule defining a TSI is shown in Rule 10-1. This TSI comprises four switches and a capacitor. The first switch, operating with phase Phasei, is connected between the input node (Inp) of the element and node X. Connected between this node and ground is another switch operating with phase Phaseo. Between the same node X and node Y is a capacitor with capacitance value C. A third switch, which also operates with the same phase Phasei, is connected between node Yand ground. Finally, a switch operating in the same phase Phaseo as the one connected to the input node is connected between node Yand the output node.
Sec. 10.3
rv-
Memory capacitor
..1 C 1 Yv ~r-~Q ~if1C V
263
SC Primitives and Identification Techniques
Y
X
Y
v
>- . - .--. -... . . . . .
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'7\Q
~
z +b
z' a
K
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, .
--1
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(K = - C)
(K
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z+a
~Q
(K = + C)
Toggle switched-capacitor (TSC)
.-Y---Y- ... -L _
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T
C
~Q
Parasitic-compensated TSC (PCTSC)
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•
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Y T2C
~
~ Y ~ ~Q -.J
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-a
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~
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. (K
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·
2C
.Y;r~~v
y
Y
x
z
JicrQ --1X.2K.X.2KP- V Feedback capacitor
(K
. ... . . . . K
~Q
(K
(d)
1'""'--
i b
=- 11 C) (c) Y
(b)
---1
I -a
I
-b
.
~Q
=-C)
z-a (l-z-I)
(a)
+a
~
LIX I
o
I
Figure 10.3 Elementary blocks for SC networks: (a) structure; (b) icons; (c) SFG; (d) switch-timing.
V
264
Chapter 10
Symbolic Signal Flow Graph Methods in Switched-Capacitor Design
tsit N,lnp,Outp,Phasei, Phaseo,C):s~v( N,lnp,X,Phasei),
/* switch */
Sl-v( N,X,gnd,Phaseo),
capa(N,X,Y,C),
/* capacitor */
sw(N,Y,gnd,Phasei), sw(N,Y, Outp,Phaseo).
Rule 10-1 Structural rule for the identification of a toggle switched-inverter.
10.4. SFG·BASED SYMBOLIC ANALYSIS OF SC NETWORKS 10.4.1. Formulation Method The SFG of an SC network is generated from its circuit description, employing information residing in the knowledge base, as schematically illustrated in Fig. 10.4. Once an SC elementary block has been identified based on the structural rules discussed earlier, the corresponding SFG can be evaluated based on two groups of evaluation rules. One group of evaluation rules is concerned with the calculation of the delay term as a function not only of the switching phases but also of the reference phase, the clock period, Period, and the unit delay, Deluni, to be considered. This is illustrated in Rule 10-2 for the simple example of the TSI SC element previously considered.
Identification ........--4
Inte
Figure 10.4 The SFG of an SC network is derived from its description based on the characterization of SC elementary blocks residing in the knowledge base.
Sec. 10.4
SFG-Based Symbolic Analysis of SC Networks
265
calcdelay(Period,Tframe, Pref,P],P2,Deluni,Delay):member([PJ,TiPJ,ToPJ},Tframe),
/* ToP]-falling edge ofphase P J*/
member([P2,TiP2, ToP2},Tframe),
/* ToP2 - falling edge of phase P2*/
member([Pref,TiPref,ToPref}, Tframe),
/* ToPref - falling edge of the refphase*/
delays(Period,ToP1,ToP2, ToPref,Dels),
/* Delay in input voltage sampling */
delayt(Period,ToP1,ToP2, ToPref,Delt),
/* Delay in charge transfer*/
Deltotal is Dels + Delt, quo(Deltotal,Deluni, Delay).
/* Delay
Rule 10-2 Rule for the evaluation of the delay term of an SC elementary block.
As we can see, the predicate calcdelay starts by obtaining the falling edge instants ToP. and ToP2 of the phases P, and P2 that control the operation of the SC elementary block, as well as the falling edge instant ToPre.fof the phase taken for reference, Pre.f' Then, the predicate delays is invoked so that the delay Dels associated with the input voltage sampling instant is computed. Once the delay Delt related to the charge transfer instant is calculated by the predicate delayt, the total delay factor, Deltotal, is obtained by adding together Dels and Delt. Finally, the Delay term is obtained by normalizing the previously calculated total delay with respect to the unit delay, Deluni. The predicate delays is consubstantiated by Rules 10-3 and 10-4. Rule 10-3 is applied when the input voltage sampling instant, ToP., of the capacitance pertaining to the SC element occurs after the corresponding charge transfer instant, ToP2. In this case, the charge transfer process will only take place in the next clock cycle, i.e., at ToP2 + Period,
delays(Period, ToPJ, ToP2,ToPrefDels):ToP 1
@ > To P2,!,
/* sampling phase is after the charge transfer phase */
To is ToP2 + Period, Dels is ToP] - To.
Rule 10-3 Rule for evaluating the delay associated to the input voltage sampling of an SC elementary block when the sampling instant, ToP1, occurs after the charge transfer instant, ToP2 .
delays(Period, ToP],ToP2,ToPrefDels):Dels is ToP] - ToP2. Rule 10-4 Rule for evaluating the delay associated to the input voltage sampling of an SC elementary block when the sampling instant, To P1, occurs prior to the charge transfer instant, ToP 2 .
266
Chapter 10
Symbolic Signal Flow Graph Methods in Switched-Capacitor Design
and Dels will be given by the difference between ToP] and ToP2+Period. Rule 10-4 is applied when the sampling instant occurs prior to the charge transfer instant, and Dels is given by the difference between ToP} and ToP2. The predicate for the evaluation of the delay associated with the charge transfer process, Delt, is consubstantiated by Rules 10-5 and 10-6. Rule 10-5 is applied when the charge transfer instant, ToP2 , of the capacitance pertaining to the SC element occurs prior to the reference instant, ToPre,f. Here, Delt is given by the difference between ToP2 and
ToPre,f· Rule 10-6 considers the case when the charge transfer instant occurs after the reference phase, so that the reference phase of the next clock cycle, ToPre,f + Period, must be considered. In this case, Delt will be given by the difference between ToP2 and
ToPre,f + Period.
The second group of rules for the SFG evaluation of SC elements concerns the symbolic characterization of the weight factor Y, given the capacitance value C of the capacitor pertaining to the SC element and the previously calculated delay, Delay. The simple case for a TSI element is illustrated in Rule 10-7. As we can see, the transmission factor K is first evaluated (here K = -C) and then the TSI SFG weight Y is obtained by invoking predicated ratFormpf, which returns in the third argument the symbolic representation of the ratio between the first two arguments.
delayt(Period, ToP}, ToP2,ToPrefiDelt):ToP2 @<= ToPrefi!, Delt is ToP2 - ToPref
Rule 10-5 Rule for evaluating the delay associated to the charge transfer process of an SC elementary block when the charge transfer instant, ToP2 , occurs prior to the reference phase, ToPref.
delayt(Period, ToP1,ToP2,ToPrepDelt):Trej2 is ToPref+ Period, Delt is ToP2- Trej2.
Rule 10-6 Rule for evaluating the delay associated to the charge transfer process of an SC elementary block when the charge transfer instant, ToP2 , occurs after the reference phase, ToP ref.
ratpol(tsi, C,Delay,Y):-
1* Y = -c * zNJelay 11
*1
minust[CJ,K), ratFormpf(K*z"Delay,[ 1J, Y).
1* ratFormpf( num, den, num/den)*1
Rule 10-7 Rule for evaluating the SFG weight factor of a TSI.
Sec. 10.5
Step-by-Step SC Synthesis and Knowledge Capture
267
In order to generate the overall symbolic SFG corresponding to a given SC network, the automatic SFG generator first browses the associated netlist so that the operational amplifiers with a feedback capacitor are recognized and, for each of them, both the phase at which the output voltage of the amplifier is sampled (Phaseref) and the unit delay are determined. For determining the unit delay, two distinct cases must be considered. Should the circuit function with a sampled and held input signal, then the unit delay is equal to the period of the clock signal controlling the operation of the circuit. Otherwise, the number of distinct phases, nphases, at which the input signal is sampled is determined and the unit delay is obtained by dividing the period of the clock by nphases. To conclude the overall SFG generation, the remaining SC elementary blocks are identified using the rule-based techniques previously discussed. The SFG of each one of those SC elementary blocks is calculated by applying the rules residing in the knowledge base and taking into account both the reference phase and the unit delay computed for the operational amplifier that is fed by the SC elementary block under consideration. In order to avoid conflicts in the identification phase, the more complex SC elements, e.g., those that are parasitic compensated, are first identified and their constituting capacitors marked as already pertaining to an identified element. After generating the symbolic SFG of a circuit, Mason's rule [10] is applied for determining the overall z-domain transfer function, also in symbolic form. Once the symbols in the z-domain transfer function are instantiated to numerical values, the frequency response of the network can be obtained. Further performance criteria, such as the variability of the frequency response against capacitance ratio errors, can also be easily obtained either by instantiating different capacitance values or by instantiating nominal capacitance values as well as their associated tolerances.
EXAMPLE 10.1 An example considering an SC decimator using an active-delayed block architecture [11] is illustrated in Fig. 10.5. Given the decimator netlist, the operational amplifiers OPt and OP2 are recognized and reference phases 5 and 1, respectively, are associated with each of them. Then, the remaining SC elementary blocks of the circuit are identified: for those belonging to block 1, the delay factor of the corresponding SFG is calculated considering phase 5 as their reference phase; for the elements pertaining to block2, phase 1 is considered as the reference phase. The SFG obtained for the SC decimator in Fig. I 0.5a and with time frame represented in Fig. 10.5b is graphically illustrated in Fig. 10.5c.
10.5. STEP-BY-STEP SC SYNTHESIS AND KNOWLEDGE CAPTURE The first step in the synthesis process consists of obtaining a network topology that may be submitted to the dimensioning process. For this, the designer may opt either for using a previously defined and fully characterized building block topology or for exploring a new topology by assembling simple, fully characterized circuit primitives to create a more complex, unknown network topology. In the process of creating new topologies based on a set of fully characterized circuit primitives, a symbolic calculation is carried out for every step of the construction of the network, so that the designer gains a qualitative insight into the key parameters responsible for the behavior of the circuit.
268
Chapte r 10
inp
~
Symbolic Signal Flow Graph Methods in Switched-Capac itor Design
-
d9 · Z- 9
-l/a
dS'z -S
e 9Z- 9 -C9.i 9
-dl·z-7
<s.r S
-d 6 Z -6
-7 -c7 ' z
-dS.z- S
-clj.z -6
-<4.z 4
-c.s 'z-S
d -3 - 3' z -d2.z-2
-4 -c4 ' z -3 -c3' z
-dl .z - j
-C2 .Z Z
- lib
I au rp
CJ·z - ( co
(c) Figure 10.5 SFG generat ion for an SC decimator with ADS architecture : (a) circuit; (b) time frame; (c) signal flow graph.
Sec. 10.5
Step-by-Step SC Synthesis and Knowledge Capture
269
During such a step-by-step synthesis process, the knowledge created may be kept in the system knowledge base so that it may be reused whenever it is needed to parameterize the same network to meet given target specifications.
10.5.1. Step-by-Step Synthesis For illustration purposes, we consider the step-by-step synthesis of a classical SC biquadratic section [7], [12]. As illustrated in Fig. 10.6, the first step consists of generating a basic structure that implements the quadratic denominator of the transfer function. In Fig. I0.6a.l, this is accomplished by connecting in a loop one negative SC integrator and one positive SC integrator. By using the symbolic analyzer, the designer obtains the SFG and symbolic expression for the denominator D(z), respectively, depicted in Figs. 10.6a.2 and 10.6a.3. Then, as shown in Fig. I0.6b.l, it is necessary to damp the loop with the addition of a damping capacitor E; this yields the SFG and symbolic expression for the denominator D(z) represented, respectively, in Figs. 10.6b.2 and 10.6b.3. Then, in order to realize the quadratic numerator function, feedforward branches must be added from the input terminal to the output of the circuit. In Fig. I0.6c.l, we consider the case of adding two branches to the input of the first operational amplifier, yielding the SFG and transfer function shown, respectively, in Fig. 10.6c.2 and in Fig. 10.6c.3. The same operation is repeated in Fig. 10.6d.1 for the second operational amplifier, thus finally leading to a network topology whose SFG and symbolic transfer function are described, respectively, in Fig. 10.6d.2 and in Fig. 10.6d.3.
10.5.2. Building Block Characterization The complete parameterization of a building block may only be attained if the system is able not only to generate its symbolic z-domain transfer function but also to provide the additional structural knowledge needed to size the final capacitance values [13]. The process of generating the symbolic characterization of an SC filter is depicted in Fig. 10.7. First, it determines such capacitors whose capacitance value may be usually preset to some fixed value so that the extra degrees of freedom for design are eliminated. After obtaining the symbolic z-domain transfer function, a structural evaluation process is also applied to the building block topology to produce the relevant knowledge concerning the capacitance values. This is the case of the integrating capacitors, which can be preset to a unit such that the associated capacitance ratios are replaced by absolute capacitance values, as illustrated in Fig. 10.8a. In Fig. IO.8b, further constraints on the capacitance values may also be applied either by presetting the value of the coupling capacitor A to unit [12] or by presetting the coupling capacitors A and C to the same value A. In Fig. 10.8c, a pair of switched-capacitors connected between the same nodes are preset to the same value, leading also to the elimination of one circuit variable. The SC structural evaluation process also determines the voltage capacitor sets, which can be affected by voltage scaling operations, as well as determining the normalizing capacitor sets upon which we can apply capacitance scaling and sizing the unit capacitance value for capacitance normalization. Voltage scaling operations, illustrated in Fig. 10.9, consist of scaling the output voltage level of each operational amplifier in the circuit to the required value.
~
N
o
E
--
.-
-1 D(l-z-I)
(b.2)
-A-z;l
E-Ez 1
c
-AZ·l
-1 B(I-z- I )
(a.2)
c -1
D (z)
B(I-z· 1)
(a.3)
1 + (ACIBO - 2) i 1+ z- 2 BO( 1- z-I)2
(b.3)
BD( 1- z-l )2
1 + (ACIBO + AF.JBD - 2) i 1+ (1 - AF.JBD) z-2
D (Z)
Figure 10.6 Using the symbolic analyzer for the step-by-step synthesis of an SC biquadratic.
(b.I)
(a.I)
-1 O(I-z 1 )
I\) ~
~
-I
-AZ
-I
Ez-~-E
C
(c.2)
outp
outp
B(l-z-I) _Jz-I
l
Figure 10-6 Continued
(d.2)
-HZ
c E-Ez·
H (z)
H (z)
-1
z + DD
(d.3)
(BO - AE) i 2 + (28D + AC + AE) z·1+ DO
(AU - JD) z-2_ (AG + 10 + JD) z-I- 10
(c3)
AH z-2 - AG z-l -2 (BD - AE) z + (2BO + AC + AE)
272
Chapter 10
Symbolic Signal Flow Graph Methods in Switched-Capacitor Design
Building Block Topology Description I--------------~ Topology Description z-tansfer function generation
Interpretation
Structural Evaluation Equation Extraction
z-transfer function Integrating Capacitors Coupling Capacitors SC Equivalences Voltage Capacitor Sets Normalizing Capacitor Sets
Figure 10.7
Symbolic characterization for SC filter design.
The determination of this value is usually calculated by numerical simulation of the circuit and may be used to trade off the dynamic range of the circuit against capacitance spread and hence the total capacitor area. In order to perform such voltage scaling, the required output voltage level V; of each operational amplifier is calculated and then all the capacitors connected or switched to the associated output terminal are multiplied by a factor k i = Vii V, where V represents the initial output voltage level. For the capacitance scaling operation, illustrated in Fig. 10.10, the SC structural evaluator starts by grouping the circuit capacitors into nonoverlapping capacitor sets such that the capacitors in the capacitor set S; are those that are connected or switched to the input terminal of operational amplifier i. Then, for every capacitor set S;, each capacitor is multiplied by a factor m.1
= CII I C. r
I,
" where CII is the adopted unit capacitance value rmn r
and C;,min is the smallest capacitor in the capacitor set Sj.
10.5.3. Dimensioning The last step in the synthesis process consists of the determination of the capacitance values of the building block by equating its symbolic and numerical transfer functions. As mentioned earlier, further constraints must usually be considered on the capacitance values in order to size the final capacitance values. The constraints criteria are based on structural information generated by the characterization process. In Fig. 10.11, a flow chart representing the unsealed dimensioning, as well as the types of constraints considered, is represented. In order to find a first set of unsealed capacitance values, the system equates the numerical and the symbolic transfer functions of the selected building block topology. For the resulting system of equations, the number of extra degrees of freedom, Nextra, is determined. If the system of equations possesses no extra degrees of freedom, then the capacitance values are immediately calculated and, if a valid solution is found, the numerical netlist of the circuit is produced. If, on the other hand, the values found are not valid, then a new network topology must be selected. Whenever extra degrees of freedom are found, constraints are imposed
Sec. 10.5
273
Step-by-Step SC Synthesis and Knowledge Capture
B
(a.I)
(a.2)
(b.3)
J
c==+
-H-
(c) Figure 10.8 Reducing design variables: (a) by replacing capacitance ratios with nominally equivalent absolute capacitance values; (b) by presetting coupling capacitors; (c) by using established equivalencies between SC branches.
Figure 10.9 Voltage scaling of an operational amplifier output.
274
Chapter 10
Symbolic Signal Flow Graph Methods in Switched-Capacitor Design
Ic IE F2
cd
D
m
xm (m
....
=CJ,.LIE)
G.~ H.~
lem ICit l1·m D.m
Figure 10.10 Capacitance scaling considering E as the minimum capacitance value.
on the network by presetting the integrating capacitors to unit. Again, if no additional degrees of freedom are found, then the capacitance values are immediately calculated, leading to the generation of the numerical netlist of the network. The system keeps track of the capacitors that have been preset to unit. If, on the contrary, extra degrees of freedom still need to be eliminated, then it is necessary to start an interactive process of exploring additional constraints to be applied. Usually, this is based on such criteria as presetting to unit or to a common value, respectively, the capacitance values pertaining to the list of coupling capacitors, ccouple, or to the list of those capacitors, cequal, that, once having set the corresponding capacitance to a common value, yield the application of SC equivalencies. This process usually leads to a set of design equations from which the capacitance values can be univocally determined. If a satisfactory solution is obtained, then the numerical netlist of the building block is automatically generated and a list of the constraints imposed during the unsealed dimensioning process is produced. If no satisfactory solution is found, then sending a message suggesting an alternative network topology should be considered.
10.6. AUTOMATIC SYNTHESIS In this section, we shall present a program for the automatic symbolic synthesis of SC networks, including those that employ multirate techniques. The program, Switcake (Switched capacitor knowledge-based ~nvironment), was implemented in BIM Prolog.
10.6.1. Building Block Knowledge-Base In the previous section, we described the symbolic characterization that must be generated for each network topology so that its dimensioning may be accomplished in a fully automatic way. For representing the knowledge automatically generated for the symbolic characterization of SC networks, we have used a frame-based system [14], [15] to enable keeping the knowledge in a structured way by defining concepts characterized by its attributes. Considering the case of SC networks, we have defined the basic concept, circdesc, represented in Frame 10-1.
Sec. 10.6
275
Automatic Synthesis
building block symbolic characterization
numerical
H(z)
computes Nextra evaluate capacitance values
generate numerical netlist
cintege l
extra=Nextra-Ncinteg evaluate capacitance values
generate numerical netlist constraints=[(1,cinteg)]
Cequal or Ccouple-based constraints
generate numerical netlist constraints=[( 1,cinteg),[cn]] Figure 10.11 Unsealed dimensioning of a circuit for a target numerical transfer function.
Besides enabling the representation of knowledge in a structured way, frame-based systems also account for the implementationof Demons, i.e., procedures that are activated without the explicit influence of the user. In this case, besides those demons used for maintaining the knowledge-base consistency, two additional demons, genstruct and gengraph, are defined. While the former is activated once the netlist of a building block has been introduced,thus immediately generating the correspondingstructural knowledge, the latter is activated once the time frame has been edited, thus generating the corresponding SFG.
276
Chapter 10
Symbolic Signal Flow Graph Methods in Switched-Capacitor Design
Frame: circdesc { netlist:
/* supports netlist */
Demons: emptynet actgraph genstruct timeframe:
/* supports timeframe */
Demons: emptygraph actztransf gengraph graph:
/* supports SFG */
cfeedb:
/*suports list of integrating capacitors */
ccouple:
/* supports list of coupling capacitors */
cequal:
/* supports list of capacitors for SC equivalences */
cinpamp:
/* supports list of capacitors for capacitance scaling */
coutpamp:
/* supports list of capacitors for voltage scaling */
supertype: symbcirc } Frame 10-1 Frame circdesc for supporting knowledge related to the symbolic characterization of SC networks.
By considering the output of the network at different nodes, we obtain distinct z-domain transfer functions. Hence, we have considered an additional concept for supporting the network z-domain transfer function that inherits all the attributes of the corresponding network characterization, as illustrated in Frame 10-2.
Frame: symbcirc ( isa: circdesc
/* inherits the attributes of circdesc */
outnode:
/* supports the definition of the output node*/
Demons: genztransf
ziransf:
/* generates H(z) */
/* supports H(z) */
} Frame 10-2 Frame symbcirc for supporting z-domain transfer function of an SC network.
EXAMPLE 10.2-SECONO-OROER LOW-PASS IIR SC OECIMATOR In this first example, we consider the design of a second-order low-pass SC decimator, with Chebyshev approximation, maximum pass-band ripple of 0.05 dB, and cutoff frequency of 6 kHz. For a decimating factor M = 4, the resulting normalized z-domain transfer function is expressed by
Sec. 10.6
277
Automatic Synthesis
-1.5 Z
H(z) =
7 ~
£..J niz
-i
i_=_O~ _ _
Z-8 _
(10-1)
2.40z -4 + 1.52
where the numerical numerator coefficients are given in Table 10-1. The implementation of the z-domain transfer function is accomplished using the optimum SC decimating architecture [16], represented in Fig. 10.12. In Fig. 10.13, we illustrate the knowledge generated during the several steps in editing the description of the basic topology represented in Fig. 10.12. Once the netlist of this basic structure is given, the corresponding structural characterization is automatically generated yielding the frame iir2nd, represented in the third column. The next step in the characterization process corresponds to the definition of the clocking scheme that controls the circuit as well as its output sampling phase. In this example, the clocking scheme illustrated in Fig. 10.14 with the output voltage at phase e has been considered. Once this information is given, the SFG of the circuit is automatically generated. Then, by either considering the output signal from node 2 or from node 4, the symbolic characterization generated during the characterization process of the basic decimator topology given is illustrated in Fig. 10.15.
=
Table 10·1 Numerator Coefficients for the 2nd-Order Low-Pass SC Decimator, with M 4
i
0
1
2
3
4
5
6
7
ni*103
4.83332
13.9711
22.0784
29.2108
27.8761
18.956
10.8368
3.48675
inp
Figure 10.12 Basic topology for a 2nd-order SC decimator, with M= 4.
278
Chapter 10
Symbolic Signal Flow Graph Methods in Switched-Capacitor Design
Operations
Demons
Frame iir2nd [Itsi.inp.Ll .e.xul.ltsi.inp.Lz.e.x I). [lsi.inp. 1.3.0.x2).[tsi.inp.I ,4.0.x3). [ampop.Lgnd.Zl.lca pacitor.Lz.d]. [tsi.2.3.e.o.al.[tsi.inp .3.4.0.y3). [lsi.inp.3.3.0.y2).[tsi.inp.3.2.e.y I ). [tsi.inp.L l.e .ynl.lampop.Lgnd.a], [capacitor.L a.b).[swirch.c.outp,e], [ofr.d.L e.o.fl.lofr.a.Le.o.cl] ........_."" ccouple: [a.c.f] cequal: nil cfeedb: [b.d] cinpamp.Ijc.d.xo.x l.x2.x3). [a.bJ .yO.y l.y2.y3)) 1 coutpamp.jja.dj.Ib.c.fj ] timeframe: [8.[2.2.3).[ I,4.5).[0. 1,4). [e,S.8).[3.0.1).[4.6.7]) graph: [[I 1.2).[[([0) • 0 • [-I ))).[([-d) • -4 .0 • [d))))). [(3,4),[[([O),O.[-I ))).[([-b) . -4 .0 , [b))))), [(inp. I),[[([-xO) , - 1 .5, [0))).[([0) ,0 . [I))))), [(inp.I),[[([-x l) , -2.5 , [0))).[([0).0 . [ I))))), [(inp, I).[[([-x2) , -3.5 , [0))).[([0) ,0 , [I)))]). [(inp,I),[[([-x3) , -4.5 , [0))).[([0) .0 . [1)))]), [(2,3).[[([-a) , -4 .0 , [0))),[([0) , 0 , [I))))), [(inp.3),[[([-y3) • -4 .5 . [0))),[([0) . 0, [I ))])). [(inp,3),[[([-y2) , -3 .5 . [0))).[([0) . 0 , [I))))), [(inp,3),[[([-y l) . -2 .5 , (0))).[([0) .0 . [I))]]). [(inp.3).[[([-yO) . -1 .5. [0))).[([0) .0 . [I))]]). [(4,3),[[([fJ ,0 .0. [0))).[([0) ,0 . [ I))])). [(4, 1).[[([c) . 0.0. (0))),[([0) . 0 . [ I))]]). [(4,outp),[[([Oj , 0 . [ I))).[([0) . 0. [I)))lll netlist:
genstruct
Figure 10.13 Representation of the knowledge generated during the editing process for the SC decimating topology represented in Fig. 10.12.
By selecting iir2nd4 and equating the symbolic transfer function to the numerical transfer function corresponding to the target specifications, we come to the analy sis equations represented in (10-2): (10-2 ) aX
3 - dY3 = 3.48675e - 3
aX
2-
dyz = 1O.8368e - 3 ax\-dYI = 18.956e- 3
ax o - dyo = 27.8761 e - 3
dY3 = 29.2108e-3
dYl = 13.9711 e - 3
dyo = 4.83332 e - 3
- 2bd+a c-df = -2.4136
dyz = 22.0784 e - 3 bd = 1.0 bd + df = 1.54561
The existing extra degrees of freedom are automati cally eliminated based on the structu ral information of the selected topology. For this purpose, the first step in the elimination of the extra degrees of freedom consists of presetting to unit the integrating capacitors, yielding the system of Eqs. (10-3):
Sec. 10.6
279
Automatic Synthesis
e 2
4
5
....
...,
6
7
Z ·1
Figure 10.14 Representation of the clocking scheme considered for the SC decimating topology represented in Fig. 10.12.
Operations
Frames Frame iir2nd2 incall: iir2nd outnode: 2
no
ztransf: [[([(-x3 ,b) ),-8.5e+00),([(-x2,b)],-7 .5Oe+OO), ([( -x l ,b»),-6.5e+00),([(-xO,b),) ,-5.5e+OO), ([(x3 ,b),(x3,f),(-y3,c) J,-4.5e+OO), ([(x2,b),(x2,f),(-y2,c) ),-3 .5e+OO), ([(xl,b),(xl,f),(-yl,c»), -2 .5e+00), ([(xO,b),(xO,f),(-yO,c») , -1.5e+OO»), [([(b,d)) , -8 .0e+OO), ([(-2,b,d),(c,a),(-f.dj] , -4 .0e+OO), ([(b ,d) ,(f,d») ,0)))
Frame iir2nd4 incall : iir2nd outnode: 4 ztransf: [[([(x3 ,a),( -y3,d)),-8 .5e+OO), ([(x2,a),( -y2,d»),-7.50e+OO), ([(x I ,a),(-y l,d»),-6.5e+00), ([(xO,a),(-yO,d») ,-5.5e+OO), ([(y3,d»),-4.5e+OO), ([(y2,d»),-3.5e+OO), ([(yl,d») , -2 .50e+00), ([(yO,d») ,-1.5e+OO»), [([(b,d») , -8.0e+OO), ([(-2,b ,d) ,(c,a),(-f,d») ,-4.0e+OO), ([(b,d),(f,d)) , 0)))
Figure 10.15 Representation of the knowledge generated for the SC decimating topology represented in Fig. 10.12, during the characterization process.
280
Chapter 10 Symbolic Signal Flow Graph Methods in Switched-Capacitor Design
aX 3 - Y3
= 3.48675e - 3
axo -
= 27.8761 e -
Yo
aX 2- Y2
= 10.8368e-3
aX1-YI
Y3
= 29.2108e-3
)'2
3
= 22.0784e-3 (10-3)
Yo = 4.83332e - 3
YI = 13.9711 e - 3
ac - /
= 18.956e-3
/ = 0.54561
= -0.4136
Because this system of equations still possesses an extra degree of freedom, the coupling capacitor a is also preset to unit, yielding the linear system of Eqs. (10-4) with no extra degrees of freedom:
X
= 3.48675e -
3
X2-Y2
= 10.8368e-3
x1-YI
o - Yo = 27.8761e - 3
Y3
= 29.2108e-3
Y2
X3 - Y3
YI
= 13.9711 e - 3
= 18.956e-3 = 22.0784e-3
Yo = 4.83332e - 3
(10-4)
/ = 0.54561
c -/ = -0.136
Solving the system of Eqs. (10-4) leads to the capacitance values shown in Fig. 10.16a. In order to maximize the dynamic range at the output of the first operational amplifier, a scaling factor of 5.8 dB is applied to the capacitors connected at the output of this first operational amplifier, thus leading to the capacitance values in Fig. 10.17a. Finally, a capacitance scaling process is applied, leading to the values in Fig. 10.17b.
0 S.8dB
a=b=d=l c = 1.320012e-l f = 5.456094e-l xO: 3.270948e-2 xl= 3.292703e-2 x2= 3.29151ge-2 x3= 3.269754e-2 yO: 4.833332e-3 yl= 1.397106e-2 y2= 2.207841e-2 y3= 2.921078e-2 (a)
'"'",
-10
'"\. \,
'"" ~
...
0-
'-
...
-20
1st operational ... ~ ,,~~plifier -'-
'
~
-30
-40
0
8e+04
4e+04
le+05
(b)
Figure 10.16 (a) Unsealed capacitance valuesand (b) frequency response obtained after a first-cut sizing of the circuit in Fig. 10.12.
Sec. 10.6
281
Automatic Synthesis
o a = 1.0734e2 b =2.0688e2 d = 1.587el c = 4.037037 f =1.12885e2 xO= 1.00297 xl= 1.00702 x2= 1.0066 x3= 1.000 yO= 1.000 yl= 2.89058 y2= 4.5679 y3= 6.094 (a)
""
-10
" ...... ,
""
'" . . '" . .
1st operational ..... ".. '" ~amplifier ~"
-...
-20
2ndoperationa amplifier
-30
-40
o
4e+04
le+OS
8e+04
(b)
Figure 10.17 (a) Capacitance values after capacitance scaling; (b) frequency response of the circuit obtained after the final sizing of the circuit of Fig. 10.12.
EXAMPLE 10.3-LOW-PASS NOTCH SC BIQUAD This second example deals with the design of an SC biquad section with a notch frequency atfz = 1800 Hz, a pole Q-factor of Qp = 30 atfp = 1700 Hz, and 0 dB de gain. Here, our first objective is concerned with the characterization process of the basic structure whereby we illustrate that the various SC elements of the circuit can be recognized even though a minimum switch configuration hasbeen used. The second purpose is concerned with the dimensioning process and is related to the removal, based on SC capacitor equivalencies, of extra degrees of freedom in the analysis equations. The given specifications yield the z-domain transfer function
H(z)
= 0.089093 - 1.774911z l-l.99029z
-1
-1
+ 0.089093z -2
-2
(10-5)
+ 0.99723z
which can be implemented using the SC biquad section [12] represented in Fig. 10.18. Once the netlist of this basic structure is given, the corresponding structural characterization is automatically generated, thus yielding the frame biquad represented in Frame 10-3. From this basic structure, the characterization process generates all the symbolic information for the possible structures that may be obtained by selecting either E- or F-damping and, for each of them, considering the output from either the first or the second operational amplifier. Thus, we now proceed to the dimensioning process, considering an E-damping biquad with the output taken from the second operational amplifier. By equating the numerical transfer function in (10-5) to the symbolic transfer function generated automatically [17], we bring to the analysis Eqs. (10-6):
282
Chapter 10
Symbolic Signal Flow Graph Methods in Switched-Capacitor Design
1
°jnH
L----tt----"' IJ
Figure 10.18 SC biquad for realizing a low-pass-notch filtering function.
Frame: biquad (
/* biquad is an instance of circedesc*/
inst :circdesc
netlist: [[switch,inps, l,e],[switch, l,gnd,o],[capacitor, 1,3,G], .. ]; graph: ... cfeedb:
/* list of integrating capacitors */
[B,D]
/* list of coupling capacitors */
ccouple: [A,C,E]
/* list of capacitors for SC equivalences */
cequal: III,J],IG,H]] cinpamp:[[C,D,E,G,H],[A,B,F,I,J]]
/* capacitance scaling */
coutpamp:[[A,D],[B,C,F,E]]
/* voltage scaling */
}
Frame 10-3 Instance of circdesc supporting the characterization of the biquad represented in Fig. 10.18.
(10-6) DI AC+AC+AE-2BD
= 0.89093 = -1.99029
AG-DI- DJ DB
= 1.774911 = 1.0
= 0.89093 DB-AE = 0.99723 DJ -AH
By presetting to unit the integrating capacitors, we obtain Eqs. (10-7):
Sec. 10.6
283
Automatic Synthesis
I = 0.89093
AG-I-J
= 1.774911
J -AH
= 0.89093
(10-7)
AE = 2.77e-3
AC+AE = 9.7Ie-3
Because the system still shows extra degrees of freedom, capacitor J is made equal to I, so that the previously referred SC equivalence is applied, yielding Eqs. (10-8):
I = 0.89093
AG-21 = 1.774911
AC+AE = 9.7Ie-3
/- AH
= 0.89093
(10-8)
AE = 2.77e-3
The final degree of freedom is removed based on the coupling capacitors, i.e., by presetting to unit capacitor A, thus leading to Eqs. (10-9): G - 2/ = 1.774911
/ = 0.89093
C+E
= 9.7Ie-3
/ - H = 0.89093
(10-9)
E = 2.77e - 3
The first set of values obtained from this last system of equations is shown in Fig. 10.19a. From the frequency response obtained at the output of both operational amplifiers, we may conclude that a scaling factor of 11.5 dB should be applied to the capacitors connected at the output of the first operational amplifier. The final capacitance values obtained after capacitance scaling as well as the frequency response of the circuit are represented, respectively, in Figs. 10.20a and b.
EXAMPLE 10.4-THIRD-ORDER LADDER-BASED LOW-PASS SC DECIMATOR In this example, we shall consider the design of a third-order low-pass SC decimator with Chebyshev approximation, nominal cutoff frequency of 3.6 MHz, and 0.25 dB maximum ripple in the pass-band. For a decimating factor M = 2, the specifications given yield the z-domain transfer function
o 4--......:-------
-""- ---
"
A=B=D=I.O
-40 ,
C=0.00694
I J
1st operational amplifier
, , I
E=O.OO277
-80
G=O.00694 1=1=0.89093 (a)
-120
o
8.0e+02
2.0e+03
..
---~ ~
2.4e+03
(b)
Figure 10.19 (a) Unsealed capacitance values and (b) frequency response of the resulting SC biquad.
284
Chapter 10
Symbolic Signal Flow Graph Methods in Switched-Capacitor Design
30 10
A=l.O 0=29.9613
-10
B=12.0365
,.
-30
C=2.5035 -50
E=1.0
I
.,
.~
~
.I'
,"
,"
I
,~
--
-
-~-~
,~~
1st operational amplifier
I I
-70
0=2.5035
I
I=J=10.7238
-90 ~ O.Oe+OO
(a)
1.0e+03
2.0e+03 (b)
Figure 10.20 (a) Capacitance values after capacitance scaling; (b) frequency response of the final biquad.
H(z)
=
0.064237z
-1
+ 0.150366z
-2
+ 0.125776z
-3
+ 0.036921z
-4
4
3.0270359 - 4.732152z -2 + 3.459719z- _ Z-6
(10-10)
which is implemented using the ladder-based SC decimator, with a decimating factor M =2 [18], represented in Fig. 10.21. 6
5
inp
Figure 10.21 The 3rd-order ladder-based SC decimator with a decimating factor of 2.
Sec. 10.6
285
Automatic Synthesis
Once the netlist of this basic structure is given, the corresponding structural characterization is automatically generated, yielding the decladder frame represented in Frame 10-4. For the clockingschemerepresented in Fig. 10.22and considering the outputof the circuit at the output of op3, we arrive at the symbolicz-domain transferfunction 4
I,n;z-; H(z) =
;= 0
(10-11 )
3
I,d 2;z-; ; =0 where the symbolic expressions of the numeratorcoefficients are
_.-...-.-_ _LJ A
B
L
Figure 10.22 Representation of the clocking scheme considered for the SC decimating structure of Fig. 10.21.
Frame: decladder { inst .circdesc
/* decladder is an instance of circdesc*/
netlist:[pctsc,inp,1,Ob.b,xl 0],[ampop,1,gnd,2],[capacitor.I,2,cJ],..] timeframe: ..... graph: ... cfeedb: [c},c3,12I
/* list of integrating capacitors */
ccouple: [cl.col.coi.cos.cs]
/* list of coupling capacitors */
cequal: [I /* list ofcapacitorsfor SC equivalences */ cinpamp:[[cl,col,cs,xlO,xl 1],[c02,l2,x20,x21], [c3,cl,c03,x30]]J
/* capacitance scaling */
coutpamp:[[cl,c02,cs],[co],c03,12],[c3,cl,c02]]/* voltage scaling */
.... } Frame 10-4 Instance of circdescsupporting the characterization of the ladder-based SC decimator represented in Fig. 10.21.
286
Chapter 10 Symbolic Signal FlowGraph Methods in Switched-Capacitor Design
n3
=
-xllco2co3+x2Ico3cl
": = - x IOc o2c o3 + x 20c o3c 1 -
x 30C 1/2 - X 30 C1/2 - X 3o Cs' 2
+ X 3o Co 1Co2
(10-12)
= C3CI/2+C3CI'2+C3CI/2+CsI2C3-CoICo2C3-Co2Co3CI +c 1/ 2c 1 = -C 3C 1'2 - C 3C 1/2 - C 3C 1/2 - C!/ 2 C 3 + Col Co2 C 3 - Cs12 C 3 +
(10-13)
nl
=
no
= - x 20c o3c 1 -
-x2Ico3cl-x2Ico3cs x20co3cs
+ x 30C 1'2 + x 30c s l 2
and the symbolic expressions of the denominator coefficients are
d 6 = -c 3c 1/ 2 d4
d2
+Co2Co3CI-CI/2CI-CI/2CI +csco2co3-cscI/2+colco2cl
do =
c 3c I/2
+ c sl 2c 3 + c I / 2c 1 + c sc l'2
By equating the symbolic transfer function to the numerical H(z) in (10-10), we obtain the system of equations represented in (10-14):
x 30 c 1/2 = 0.036921 -xllco2co3 +x2lco3cI
= 0.125776
-xIOco2co3 +x20co3cl-x30cI'2 -x 30c 1/2 -x 30c!J2 +x30colco2 -x2Ico3cl-x2Ico3cs
= 0.064237
-x20co3cl-x20co3cs +x 30c l/2 +x 30c s12 -C
= 0.150366
= 0
(10-14)
c 1 = -1
3 12
c 3c l ' 2 + c 3c I/2 + c 3c l ' 2 + c s'2 c3
-colco2c3 -co2co3cI
+ c I / 2c 1 = 3.459719
-c 3c 1'2 - c 3 c 1'2 - c 3 c 1'2 - cs 12 c 3 + col c o2 c 3 - cs12 c 3 + c() 2 Co3 c 1 - C 1'2 C 1 -
C 3C 1/2
c 1/2 c 1 + c s c o2Co3 -
CsC 1/2
+ col c o2 c 1 = -4.732152
+ c sl 2c 3 + C 1/ 2c 1 + csc 1/2 = 3.0270359
By presetting to unit the integrating capacitors and the coupling capacitors c0 3 and cs1,we obtain the equations in (10-15):
Sec.10.6
287
Automatic Synthesis
= 0.125776 3x 30 + x 30 co I c o2 = 0.150366 -2x 21c = 0.064237 03 -X
- x IOc o2 + x 20 -
l l c o2 +x 21
- 2x 20 + 2x 30
4 - c o lco2 - c o2 + Col
= 0
(10-15)
= 3.459719
-5+colco2+2co2-3cl +colco2cl = 0.267848
2c I = 1.0270359 Among all the coupling capacitors of the circuit, c0 and cSIwere selected, for these 3 are the ones that, once preset to unit, lead to a system of equations with fewer terms containing products of variables. Solving the design equations (10-15) leads us to the capacitance values shown in Fig. 10.23a. From this first dimensioning, we then apply a scaling factor of 0.4733 dB to the capacitors connected at the output of the second operational amplifier and a scaling factor of 2.7982 dB at the output of the first operational amplifier. The final capacitance values obtained after admittance scaling as well as the frequency response of the circuit obtained are represented, respectively, in Figs. 10.24a and b.
\
-10 2.Xl1=-0.719702 2.XIO=-0.918464 2.X21=-0.642374 X20= 0.0369215 X30= 0.0369215 Col= 1.40100 Co2= 0.43878 Co3= 1.0 C13= 0.513518 Csl= 1.0 CI = 1.0 L2 1.0 C3 1.0
= =
(a)
\
•, \
-20
,
,,
1st operational •• • •.• ~plifier ,,
...... .
-.. ,
-..
2ndoperational , • , " _amplifier -..,-.._-- ....
-30
-
-40
o
9.0e+06 (b)
1.8e+07
Figure 10.23 (a) Unsealed capacitance values and (b) frequency response of the resulting circuit.
288
Chapter 10
Symbolic Signal Flow Graph Methods in Switched-Capacitor Design
.' _ .. \.
1-..: \.. . ~"
-10 2.Xll=-1.0 2.XIO=-1.276172 z.xn =-1.739837 X20= 1.0 X30= 1.0 Co1= 2.055650 Co2=11.884132 C'o2=16.401283 Co3= 28.60122 C13= 13.90837 Csl= 1.917599 C1 =1.9175992 L2= 28.601221 C3= 27.084490
I
, " ..'
\
\
" -20
"
· · _. ··.. \
" ~
1st operational amplifier
. . . . . .. ..... -
2nd operational "' ~ ~ ~ ~ "'--a amplifier _
-30
-40
o
1.8e+07
9.0e+06
(a)
(b)
Figure 10.24 (a) Final capacitance values; (b) frequency response of the final ladder-based SC decimator.
10.7. CONCLUSIONS In this chapter, we addressed the application of symbolic SFG computational techniques for the analysis and synthesis of SC networks. First, we described the rule-based implementation of the pattern-matching technique adopted for generating the SFG representation of an SC network. Then, we discussed the corresponding SFG-based analysis and described the use of symbolic analyzers for carrying out step-by-step synthesis procedures as well as the automatic synthesis of SC networks. In particular, we discussed the knowledge generated during both the analysis and dimensioning processes and presented a frame-based implementation of the system knowledge base for capturing such knowledge. Various working examples were presented to illustrate the techniques and methodologies described throughout this chapter.
References [I] F. Fernandez, A. Rodriguez-Vazquez, and J. L. Huertas, "Interactive ACmodeling and characterization of analog circuits via symbolic analysis," Int. J. Analog Integrated Circuits and Signal Processing, vol. 1, pp. 183-208, November 1991. [2] G. Gielen, "Symbolic analysis methods and applications - an overview," Proc. IEEE Int. Symp. Circuits Syst., San Diego, pp. 1141-1144, May 1992. [3] L. P. Huelsman, "Applications of symbolic analysis to analog system design," Proc. IEEE Int. Symp. Circuits Syst., San Diego, pp. 1165-1168, May 1992. [4] G. Szentinnai, 5/Filsyn Quick Reference Manual. April 1983.
References
289
[5] U. W. Brugger and G. S. Moschytz, "SFG analysis of SC networks comprising integrators," Proc. IEEE Int. Symp. Circuits Syst., Newport Beach, pp. 68-71, May 1983. [6] G. S. Moschytz and U. W. Brugger, "Signal-flow graph analysis of SC networks," lEE Proc., Pt. G, vol. 131, pp. 72-85, April 1984. [7] J. E. Franca, "Switched-capacitor systems for narrow bandpass filtering," Ph.D. dissertation, London, 1985. [8] K. R. Laker, "Equivalent circuits for the analysis and synthesis of switched-capacitor networks," Bell Syst. Tech. J., vol. 58, pp. 729-769, March 1979. [9] L. Sterling and E. Shapiro, in The Art ofProlog: Advanced Programming Techniques (E. Shapiro, Ed.). London: MIT Press Series in Logic Programming, 1986. [10] S. J. Mason, "Feedback theory-some properties of signal flow graphs," Proc. IRE, vol. 41, pp. 1144-1156, September 1953. [11] J. E. Franca and S. Santos, "FIR switched-capacitor decimators with active-delayed block polyphase structures," IEEE Trans. Circuits Syst., vol. CAS-35, pp. 1033-1037, August 1988. [12] P. E. Fleisher and K. R. Laker, "A family of active switched capacitor biquad building blocks," Bell Syst. Tech. J., vol. 58, pp. 2235-2268, December 1979. [13] M. H. Fino-Martins, J. E. Franca, and A. Steiger-Garcao, "A computer-aided tool for the automatic generation of design equations of switched capacitor circuits," Proc. European Conf. Circuit Theory and Design, Davos, Switzerland, pp. 1705-1710, September 1993. [14] M. Minsky, "A framework for representing knowledge," in Psychology of Computer Vision. New York: McGraw-Hill, pp. 211-277,1975. [15] L. Seabra-Lopes, Golog: A Prolog Object Manager (in Portuguese). Electrotechnical Department, F.C.T, New University of Lisbon, April 1993. [16] J. E. Franca and R. P. Martins, "IIR switched-capacitor decimator building blocks with optimum implementation," IEEE Trans. Circuits Syst., vol. 37, pp. 81-90, January 1990. [17] M. H. Fino-Martins, J. E. Franca, and A. Steiger-Garcao, "Towards high-level synthesis of mixed-signal analog-digital ASICs," in Analog-Digital ASICs-Circuit Techniques, Design Tools and Applications (R.S. Soin, F. Maloberti, and J. Franca, Eds.). London: Peter Peregrinus Ltd., 1991. [18] P. Santos, J. E. Franca, and J. Martins, "Synthesis of optimum switched-capacitor state-space decimators," Proc. European Conf. Circuit Theory and Design, Davos, Switzerland, pp. 935-940, September 1993.
11 A. Konczykowska
FRANCE TELECOM/ CNET-PAB Bagneux Cedex, France
Symbolic Methods in Semiconductor Parameter Extraction
W. M. Zuberek
Memorial University ofNewfoundland St. John's, Canada
11.1. INTRODUCTION Due to rapid developments in semiconductor technologies, which have resulted in increased circuit complexity and improved circuit performance, verifying designs through simulation has become an indispensable part of the integrated circuit (K') design process. As complex mixed analog/digital circuits are becoming quite popular, and digital circuits use frequency rates for which analog effects must be taken into account during the design process, there is constant demand for more efficient analysis methods for analog as well as digital circuits. Computer-aided circuit analysis (or circuit simulation) cannot provide reliable results without adequate specification of circuit elements and device models. Existing device models use large sets of parameters, values of which must be determined very carefully to represent device characteristics accurately. Because of highly nonlinear device models, these parameters usually cannot be determined by direct measurements; popular extraction methods use iterative techniques to minimize differences between measurement data and model behavior in the full range of operating conditions. Iterati ve extraction of model parameters can be regarded as an optimization process, which minimizes the differences between a set of measurement data and the corresponding circuit responses by adjusting the values of model parameters (used as optimization variables). These differences are usually expressed by one of a variety of error functions. The result of this optimization determines such a set of model parameters, for which the circuit responses are "as close as possible" to the measurement data (in the sense of the error functions used in optimization).
290
Sec. 11.2 Overview of Parameter Extraction
291
One of the flexible approaches to parameter extraction is to use a circuit simulator rather than a set of model equations (such an approach is called simulation-based parameter extraction [I ]). An important advantage of the simulation-based method is that the extractor can use all capabilities of the circuit simulator, so all packaging and mounting parasitics can easily be taken into account during the extraction process. Moreover, the extraction can use many different types of measurement data (de, ac, noise, distortion, etc.) for the best selection of parameter values. On the other hand, repeated simulations can easily become rather time-consuming, especially when numerous parameters are extracted from large sets of measurement data. For linear, frequency-domain analyses, the dependence of circuit responses on some variables can be derived in a symbolic form. This symbolic form can then be used very efficiently for finding circuit responses of the same circuit for different combinations of parameter values. Many time-consuming computations can be eliminated using such an approach. This chapter briefly describes a simulation-based parameter extraction program and then indicates where symbolic simulation can successfully replace the traditional numerical approach. An interface between symbolic and numerical simulators is outlined and the integration of these two approaches is discussed in the context of parameter extraction. Practical examples of parameter extraction are used as an illustration as well as the basis of some performance comparisons.
11.2. OVERVIEW OF PARAMETER EXTRACTION 11.2.1. Approaches to Parameter Extraction The goal of parameter extraction is to determine such values of device model parameters that minimize the (total) differences between a set of measured characteristics and results obtained by evaluations of the device model. This minimization process is often called fitting of model characteristics to the measurement data. The comparison is performed using some error functions, such as absolute or relative lp-norm, logarithmic norm, etc., that determine the (total) differences between measurement data and evaluated results. Quite often several different error functions are used for different types of data (such as de data, ac data, etc.). Several different approaches to parameter extraction have been proposed. They include general or specialized, and direct or iterative extraction methods. Specialized methods extract some subsets of model parameters, for example, model resistances, or capacitances, or de parameters only [2]-[4], while general methods determine all parameters of the model. Direct extraction methods approximate model equations by linear functions and determine the values of parameters graphically or by solving linearized equations [4], [5], while iterative methods fit the model responses to a set of measured characteristics by minimizing an objective function that quantitatively characterizes the fit [6]-[9]. Sometimes a mixed approach is used in which some parameters are extracted using the direct methods and the remaining ones by an iterative procedure [2], [10], or the direct solution is used as the starting point to an iterative refinement [II], [12]. Iterative methods can be equation-based or simulation-based. Equation-based methods use a set of model equations to evaluate device responses corresponding to measurement data [6], [13]. In the simulation-based approach, a circuit simulator (or its part that evaluates devices and their models) is used to provide circuit responses. The
292
Chapter 11
Symbolic Methods in Semiconductor Parameter Extraction
simulation-based approach eliminates potential inconsistencies between model equations used by the extractor and the equations implemented in simulation tools. It also provides, at the extractor level, many simulation capabilities that are supported by the circuit simulation tool used. Several extraction programs have successfully demonstrated applicability of general optimization methods to parameter extraction [6]-[9]. However, the convergence properties of these methods depend on properties of the error functions; typically, it is required that the error functions have no singularities, be unimodal, and be approximately quadratic in the region of a minimum. These conditions are not always met by popular error functions [14], especially in the absence of good initial estimates of parameters. To achieve convergence, global optimization methods are used [15], [16]. However, global methods are rather inefficient, so an alternative approach replaces the global optimization by a sequence of "partial" extractions [17], each of which is performed using a subset of parameters and a subset of measurement data. Also, less efficient but robust optimization methods are being used [8] in order to avoid convergence problems of gradient techniques. Several programs for parameter extraction are available on a commercial basis. Brief characteristics of some of them are as follows. Hewlett-Packard offers an integrated circuit characterization and analysis program (IC-CAP) [18]. Presented as an open framework for computer-aided engineering (CAE) modeling applications, this tool differs considerably from a previous HP modeling product, TECAP. Standard and user-defined models are supported, as well as different measurement types. Parameter extraction language (PEL) can be used to develop specific extraction tasks. HarPE, from Optimization Systems Associates Inc. (OSA), is an equation-based extractor dedicated to nonlinear device simulation, characterization, and optimization. Frequency-domain large-signal, small-signal, and de measurements are used for extraction. HarPE was developed primarily for microwave applications [19]. SUCCESS is a product of ANACAD-EES [20]. The program provides model parameter extraction for various devices (bipolar, MOSFETs, diodes, etc.), as well as for user-defined models. The program is designed to extract parameters in a user-specified constrained region of operation. The extractor is equation-based and uses a modified Levenberg-Marquardt algorithm for optimization. Universal Transistor MOdelling SofTware (UTMOST) is available from SIL VACO [21]. This program determines model parameters from measurement data via direct parameter extraction and/or optimization methods for various types of measurements and a wide range of devices.
11.2.2. Parameter Extraction as an Optimization Problem Iterative parameter extraction is based on repetitive comparisons of measurements obtained from fabricated devices with the model evaluation results corresponding to different values of (extracted) parameters. The iterative procedure adjusts the values of parameters in a way that minimizes the value of the error function and terminates the extraction when no further improvement can be made. Parameter extraction can be formulated as an optimization problem in which a nonlinear objective function F is minimized with respect to a set of model parameters P, subject to a set of constraints C. The objective function F describes the (total) differences between the measurement data D and the results of model evaluation S(P):
293
Sec. 11.3 Integrated Parameter Extraction
= E(D, S (P))
F(D, P)
(11-1)
where E denotes a (general) error function. The optimization process determines such a vector of parameter values P" that minimizes the objective function F(D, P*) =
min
(F(D, P»
P subject to C
(11-2)
where C determines lower and upper bounds on parameters (e.g., resistances must be positive and not greater than certain physical limits, similarly capacitances, etc.). The set of data D usually contains different types of measurement data (de, ac, noise, etc.). Different error functions can be used for different data types. Moreover, in order to speed up the extraction process and to improve its convergence, quite often an extraction strategy is developed that decomposes the extraction process into a sequence of "partial extractions," i.e., a sequence of extractions performed for (small) subsets of extracted parameters and subsets of corresponding measurement data [1]: F(D,P*) =
mm i = 1,2 ...
(
m in
v, (D i, Pi)) )
Pi subject to C i
(11-3)
c,
where D i c D, Ij ~ P and = C restricted to r, Usually only the last steps of fine tuning involve large sets Pi of parameters and large sets D, of data.
11.3. INTEGRATED PARAMETER EXTRACTION 11.3.1. Simulation-Based Parameter Extractor An iterative, simulation-based and data-driven extraction program, called FIT [1], has been developed using general optimization methods and an "open" circuit simulator SPICE-PAC [22] rather than a set of explicit model equations. The selection of the simulation-based approach rather than the equation-based one was due to FIT's anticipated use in parameter extraction for new, experimental semiconductor devices. The flexibility of the circuit simulation too] is of primary importance for such applications. SPICE-PAC is a SPICE-compatible circuit simulator. It provides the same set of circuit analyses as SPICE [23], but also contains a number of extensions that are not available in SPICE programs. The main difference between SPICE (and other SPICE-like simulators) and SPICE-PAC is in their structure. SPICE is a "closed" program with a fixed set of circuit elements and circuit analyses, while SPICE-PAC is an "open" package that can easily be combined with other computer-aided design (CAD) tools, for example, optimization methods, symbolic and statistical simulators, circuit extractors, and so on. Because FIT is designed in a modular way, many extensions can be implemented in a rather straightforward way. For example, device thermal effects can be taken into account [24] or extraction can be performed with respect to a combination of technological, geometric, and electrical parameters [25]. FIT supports integrated as well as partial extraction performed on arbitrary subsets of measurement data and arbitrary subsets of
294
Chapter 11
Symbolic Methods in Semiconductor Parameter Extraction
parameters. It uses two optimization algorithms; the initial optimization is usually performed by the very robust direct search method of NeIder and Mead [26] (also known as downhill simplex), while a more efficient gradient-based method (from the NAG library [27]) is used in the neighborhood of the solution. The organization of data for a simulation-based extractor is partially implied by its circuit simulation tool. FIT uses three different types of input data: the circuit description, the definitions of variables, and the measurement data. Measurement data normally include de measurements, frequency-domain (ac), and/or time-domain (TR) measurements (used also for large-signal analysis of the periodic steady state); harmonic and noise measurements can also be handled by the extractor. Measurements of the same type (e.g., ac for a given bias point, steady state for a given frequency, etc.) form a data "group." The measurement data are simply organized as a sequence of data groups. These three types of data (the circuit description, the specification of variables, and the measurement data) are processed by different modules of FIT, as shown in Fig. 11.1. The main components of FIT are General driver: coordinates all remaining parts of the program and performs interaction with the user using an interpreter of a simple command language that describes consecutive steps of the extraction process. Variables manager: controls the set of optimization variables. It selects subsets of variables for partial extractions and updates the values of variables (as well as corresponding circuit parameters) after each optimization step. Data manager: maintains a collection of all measurement data and corresponding simulation results. It selects data for partial extraction and stores the results of circuit simulations. Optimizer: selects the optimization method and adjusts optimization parameters accordingly; it also selects the starting point for the optimization. Circuit simulator: performs the analyses required by the evaluation of the objective function, i.e., analyses that correspond to the selected measurement data. A more detailed description of the FIT program is given in Refs. [I] and [28].
DRIVER (INTERACTIVE)
OPTIMI-
CIRCUIT
VARIABLES
MEASUREMENT
DESCR.
DATA
1
1
1
-
DESCR.
VARIABLES MANAGER
DATA MANAGER
CIRCUIT SIMULATOR
1
ZATION METHODS
n
~ OBJECTIVE (OR ERROR) FUNCTION
SIMULATION DRIVER
(SPICE-PAC)
~
Figure 11.1 General organization of the FIT program.
L....-
~
Sec. 11.3
295
Integrated Parameter Extraction
11.3.2. Numerical Methods in Parameter Extraction The popular numerical circuit simulators use a modified form of nodal analysis (modified to take care of voltage sources, floating sources, and inductive elements) and Newton-Raphson iteration to solve the system of simultaneous nonlinear algebraic equations [29] F(X)
=0
(11-4 )
describing the balance of currents at the nodes of the network in terms of node voltages (and some branch currents) X. The solution is typically obtained through a sequence of linear approximations to the nonlinear function F(X) at points XU) (11-5) where G is the Jacobian of F with respect to X (evaluated at XU) and the solution ~ U) is used to determine the next approximation XU + I) = XU) + ~ U). The iteration terminates when ~ U) is sufficiently small. This basic scheme is used in the de operating point, de transfer curve, and even time-domain analysis; in the latter case, the dependence upon time is eliminated by approximating the differential equations by difference equations (using some numerical integration formula) [30], [31]. Only frequency-domain (small-signal) analyses are significantly different, because they require (for each frequency) a solution of a system of simultaneous linear equations in the complex domain; this is often done by separating the real and imaginary parts of the coefficients and variables, and solving a twice-as-Iarge system of linear equations in the real domain. A general data-driven and simulation-based optimization scheme (with emphasis on frequency-domain analyses), as implemented in the FIT program, is shown in Fig. 11.2.
11.3.3. Symbolic Methods in Parameter Extraction For simulation-based parameter extraction in general, but especially in the case of analog (and in particular microwave) applications, a significant part of simulations is performed for the small-signal linear behavior of the circuit. These linear analyses can conveniently be done using symbolic methods rather than numerical ones. The analyzed circuits are typically very small, and the number of symbols can be significantly reduced by eliminating, as soon as possible, all those symbols whose values cannot be modified during analyses. The principle of symbolic simulation is to derive analytic (or symbolic) functions describing the circuit responses, using symbols representing (some) circuit parameters (rather than their numerical values). Evaluation of these symbolic functions for specific values of symbols provides the required responses of the circuit. Circuit functions that are used in parameter extraction are driving-point immittances and various matrices (Y, Z, A, S, etc.) for a two-port circuit representation. All these circuit functions can be obtained easily from characteristic polynomials of the analyzed circuit [32].
296
Chapter 11
Symbolic Methods in Semiconductor Parameter Extraction
continue_optimization := true; while continue_optimization do update_the_values_of_optimization_variables; error_value := 0; for each data_group do if frequency_domain(datagroup) then update_op_point_voltages_and_currents; flndfhenperatingpolntsolution; for each frequency do find_the_solution_of_linear_equations(res); error_value := error_value + difTerences(data,res) endfor else find_circuit_responses(res); error_value := error_value + differences(data,res) endif endfor; if end_of_optimization(error_value) then continue_optimization := false else select_new_values_of_parameters(error_value) endif endwhile;
Figure 11.2 An outline of a simulation-based data-driven optimization scheme.
For linear, lumped,and stationary (LLS)circuits, the transferfunctions of a two-port network are in the form of rational functions of complex frequency s: F.(s)
H(s)
=
~(S)
(11-6)
in which the numerator Fj and the denominator Fk are characteristic polynomials of the two-port. Characteristic polynomials F, can be expressed as n.
Fj(s) = IsIAj/(XI""'Xm ) 1 =0
(11-7)
Sec. 11.3
297
Integrated Parameter Extraction
where coefficients Ail (xI' ... , x m) are (nested or expanded) multilinear functions in symbolic elements X I' ... , X m . In the fully expanded form, the polynomial coefficients are in the sum-of-product form: p
r
A(xl,···,xm ) = ICkIlx kJ k
=I
I
(11-8)
=I
where Ck are real numbers, Xkl are circuit symbols, and p and r depend on the topology of the analyzed circuit. By extracting common factors in (11-7), Fi(s) can be represented as n.
F,'(s)
k.
'.
= s 'T.I "" £..J sJRIJ..
(11-9)
j=o
where each T; is a product of a constant C, and some symbols Xjk' k = 1, ... , m j
Ti =
x ik
(11-10)
k= I
and each Rij , j = 0, 1, ... , n i' is a sum of products lU
R ij =
mUk
L CijkIl xijkJ k= I
(11-11)
I= I
The expanded representation (11-9) is used in a practical implementation of the symbolic analysis. The generated symbolic functions are represented by tables of coefficients C, and Cijk and the products of symbols x I' ... , x n [28], [33]. In the context of parameter extraction, and in particular for a sequence of partial extractions, the symbolic functions can be further refined by eliminating all those symbols that cannot change their values during an optimization. Generally, the symbols can be subdivided into two disjoint classes: fixed symbols, which do not change their values during a single optimization; all such symbols can be eliminated during the generation of symbolic functions by using their numerical values and combining (i.e., multiplying and possibly adding) all such values together, and variable symbols, which include optimization variables as well as all symbols that depend on the operating point solution (used for the calculation of small-signal parameters). For each optimization, only the variable symbols are used in the symbolic representation of characteristic functions. In typical partial extractions, there are only two
298
Chapter 11
Symbolic Methods in Semiconductor Parameter Extraction
or three optimization variables, so the number of variable symbols is rather small, and the symbolic functions are quite simple. The generation of symbolic functions follows the approach used in SYBILIN [34], a symbolic simulator developed for analog and, especially, microwave applications. In general, a different refined form of symbolic functions is needed for each partial extraction. In order to simplify the generation of symbolic functions, the generation is composed of two steps. The first step, performed only once, creates the Coates flowgraph of the circuit with variables corresponding to circuit nodes, as in the modified nodal analysis [35], [36]. This flowgraph is then used to generate all O-connections, and these O-connections are used to generate symbolicfunctions of the circuit. O-connections [37] are subgraphs of the Coates flowgraph composed of such node-disjointdirected loops that are incident with all graph nodes. The second step, performed for each optimization (as it depends on the set of optimization variables), uses O-connections to generate symbolic functions with variable symbols only. For frequency-domain analyses (Fig. 11.2),once the values of variable symbols are determined (by the optimization routine as well as by the solution of the operating point), the symbolic functions can be further reduced by evaluatin¥ all the T; and Rij terms [(11-10), (11-11)]. This results in reduced symbolic functions F;: n·
F; (s)
=
k .« ~ ." s IT; sJRij
s:
(11-12)
j=o where all T; and k;j' j = 0, 1, ... , n;, are constants, provided that no frequency-dependent elements are used; they are obtained by the evaluation of T; and Rij [(11-10), (II-II)]. Only this very simple polynomial form [(11-12)] needs to be evaluated in the innermost (i.e., frequency) loop (Fig. 11.2).
11.3.4. Integration of Numerical and Symbolic Extraction The addition of symbolic simulation to the extractor FIT resulted in the FIT-S version of the program [28], [33]. Any integration of numerical and symbolic simulation must provide some sort of interaction between these two methods. In the integrated numerical/symbolic parameter extractor FIT-S, the interaction is performed through an interface that supports only a few operations (implementedas interface procedures): RESET (NAME) NEXTEL(DESC,TYPE,NODES,LEN) GETVAL(DESC,TYPE,VALUES,LEN) RESETmust always be used as the first operation, before any other operation of the interface, because it initializes extraction of circuit elements for symbolic analysis; its parameter NAME must be a subcircuit expansion name (i.e., an X-name in the SPICE convention), which indicates a subcircuit for symbolic analysis.
Sec. 11.3
Integrated Parameter Extraction
299
NEXTEL returns a descriptor DESC, a type TYPE, and a list of nodes NODES of length LEN of the next circuit element (or indicates that the "next" element does not exist); it is implemented in such a way that consecutive invocations of this operation return descriptions of consecutive subcircuit elements (according to the internal representation of the circuit); zero returned as the value of DESC indicates that there are no more elements. GETVAL uses a vector VALVES to return the numerical values of parameters associated with an element identified by DESC and TYPE; LEN is set to the number of values returned in VALVES. A typical sequence of interface operations is shown in Fig. 11.3. A symbol table, created in this phase, combines all attributes of all symbols used in the simulation and extraction. These attributes include the class of symbols (fixed, variable) and the values of symbols. The last step shown in Fig. 11.3, generate_O-connections, performs the first step of the symbolic analysis. Integration of the second part of symbolic simulation with the general scheme of parameter extraction (shown in Fig. 11.2) is outlined in Fig. 11.4. The step generate_symbolic_terms generates the coefficients T; and Rij [( 11-10), (11-11)] of t~e symbolic function F;(s), while evaluate_coefficients_of_reduced_functions evaluates T; and R;j [( 11-12)] using the retrieved values of variable symbols. The step retrieve_the_values_of_variable_symbols is outlined in Fig. 11.5. At each iteration step, once the values of optimization variables are updated and the solution of the operating point is known, the values of all variable symbols are retrieved from the circuit description and stored in the symbol table. It should be noted that the values of all fixed symbols are retrieved from the circuit before this stage (see Fig. 11.3).
reset(name); graph := empty; nextel (desc,type,nodes,num);
°
while desc > do add_to_flowgraph(symbol,nodes,graph); add_to_symbol_ta ble(desc,type,symbol); if fixed_symbol(desc,type) then getval(desc,type,value,len); store_in_symbol_table(symbol,value,len) endif; nextel(desc,type,nodes,num) endwhile; generate_O-connections(graph); Figure 11.3 Initial part of symbolic analysis.
300
Chapter 11
Symbolic Methods in Semiconductor Parameter Extraction
continue_optimization := true; while continue_optimization do update_the_values_of_optimization_variables; generate_symbolic_terms; error_value := 0; for each data_group do if frequency_domain(datagroup) do update_op_point_voltages_and_currents; find_the_operatingpoint_solution; retrieve_the_values_of_variable_symbols; evaluate_coeflicients_of_reduced_functions; for each frequency do evaluate_reduced_functions(val); convert_to_circuit_responses(val,res); error_value := error_value + differences(data,res) endfor else find_circuit_responses(res); error_value := error_value + differences(data,res) endif endfor; if end_of_optimization(error_value) then continue_optimization := false else select_new_values_of_parameters(error_value) endif endwhile; Figure 11.4 An outline of simulation-based optimization with symbolic frequency-domain analysis.
for each symbol in symbol_table do if variable(symbol) then getval(desc,type,value,len); store_in_symbol_table(symbol,value,len) endif endfor; Figure 11.5 Implementation of retrieve_the_values_of_variables_symbols.
Sec. 11.4
301
Examples
11.4. EXAMPLES EXAMPLE 11.1-MODELING AND CHARACTERIZATION OF PASSIVE ELEMENTS Passive elements are normally characterized by relatively simple frequency-domain small-signal models. However, for higher frequencies, the nonlinear effects and frequency-dependent phenomena must be taken into account. Circuit functions in their symbolic form are useful in the selection of the model's topology. In order to predict the correct behavior of microwave or high-speed circuits, the simulation must take into account models of both passive and parasitic elements. Simulation techniques based on electromagnetic (EM) analysis are not useful in a typical design cycle because of significant memory and computation time requirements. A parametrized library of electrical models was established for the family of passive and parasitic elements such as MIM and interdigitated capacitors, inductors, coplanar capacitors and inductors, bonding wires, TAB (taped automated bonding), bonding pads, vias, etc. [38], [39]. For each element, simplified analytical EM simulation was performed for a wide range of different geometric parameters. Several test designs were fabricated and measured. The topology of small-signal models was investigated using the FIT-S program, and numerical values of model parameters were determined from measurements and compared with those obtained by simulation. Then, for each model parameter, simple analytical formulas in terms of geometric parameters were established. These formulas, obtained using the least square method, can easily be used in circuit simulation in the range of geometries specified for this library. The following example illustrates the extraction part for a coplanar capacitor. Figure 11.6 shows a small-signal model of a coplanar capacitor from Fig. 11.7. The measurement data (for I = 130 urn, W = 14 urn, and g = 10 urn) as well as the results obtained by simulation are presented in Fig. 11.8.
EXAMPLE 11.2-EXTRACTION OF HBT PARAMETERS Heterojunction bipolar transistors (HBT) are recognized as promising candidates for high-performance circuits, which include monolithic microwave integrated circuits and high-speed digital circuits. For all such applications, an accurate HBT CAD model is essential for simulating the behavior of high- frequency circuits [12].
Rr L1
L2
Cs C1
r
Ls
r
C2
Figure 11.6 Electrical model of a coplanar capacitor.
302
Chapter 11
Symbolic Methods in Semiconductor Parameter Extraction
Figure 11.7 A coplanar capacitor layout.
An active device model must accurately represent the static and dynamic behavior of the device. Usually, dc as well as ac measurements are necessary to obtain accurate model parameters. For bipolar transistors, the de measurements are performed for various configurations and the ac measurements are performed for different bias points in the required range of frequencies. Figure 11.9 shows dc Gummel plot forward characteristics of a GaAs HBT. Families of Ie vs,Vee and Vbe vs ,Vee characteristics, with Ib as parameter, are presented in Fig. 11.10 and Fig. 11.11, respectively. Both families show the characteristic self-heating effect (negative slope). This thermal effect is taken into account during parameter extraction by a combined de-thermal analysis [24]. Measured and simulated values of S-parameters, for one bias point, are presented in Fig. 11.12. EXAMPLE 11.3-MODEL TUNING FOR NEW TECHNOLOGIES
The extraction of parameters is one of the possible techniques used in development of models for new technologies. In this case, the number of ac measurements (for different bias points) is usually rather large (50 to 80) because the character of influence of the bias point on the small-signal parameters is not known precisely, and the whole domain of bias conditions (voltages and/or currents) must be covered by measurements . In the case of known models, the nonlinearities are usually characterized by a small number of parameters, so the extraction can be done with a small number (5 to 10) of properly chosen ac data sets. Because of the large number of ac data sets, the efficiency of ac simulation is of primary importance for the extraction process. Moreover, special extraction strategies should be established for each new type of device, in order to get reliable, physically meaningful values of parameters, with as little computational effort as possible. The FIT-5 extractor was used in model development of a submicron (0.25 um) GaAs PET on InP substrate [40]. The topology of the small-signal model is shown in Fig. 11.13. The goal of this extraction was to obtain the characteristics of major small-signal parameters in the function of bias voltages (Vg s and Vds )'
Sec. 11.4
303
Examples
1.5 ~------------------,
0.5 O~.".-------------------t
-0.5 -1
L-....l..--.l-----..._.l...---"---...I-----J._~__i__.__"__I...__~_.I.______.I
o
5
10
15
20
25
30
35
Frequency (GHz)
(a)
0.2 . . . - - - - - - - - - - - - - - - - - - - . . . . . . . ,
0.15 .
0.1
0.05
5
10
15 20 25 Frequency (GHz)
30
35
(b) Figure 11.8 Measured (dots) and fitted (line) 5-parameters of a coplanar capacitor: (a) parameter 5 11 ; (b) parameter 5 12 ,
The characterization process was organized as follows. The values of small-signal parameters were extracted for each bias point, and were used for parameter characteristics in terms of bias voltages. Nonlinear large-signal formulas for model parameters were then determined and verified using the characteristics obtained earlier. Figure 11.14 shows two extracted parameters in function of bias voltages.
11.4.1. Evaluation of Examples The FIT-S extractor was used in all three preceding examples. Integration of numerical and symbolic simulation in the extraction program resulted in significant reduction of the execution time of ac analyses.
304
Chapter 11
Symbolic Methods in Semiconductor Parameter Extraction
I (A) 1E-1
Ie
1E-2 1E-3
Ib
1E-4 1E-5 1E-6
1E-7
0.8
1
1.2
1.4
1.8
1.6
Veb (V) Figure 11.9 Gummel plotdc characteristics of GaAs HBT.
Ie (A)
0.012 0.01 0.008 0.006
0.004 0.002 0 -0.002
0
0.5
1.5 2 Vee (V)
2.5
3
3.5
Figure 11.10 le·Vee characteristics of GaAs HBT.
The reduction of the computation time due to the introduction of symbolic analysis is especially important for model tuning (Example 11.3). In fact, in this case, the majority of extractions are performed for frequency-domain measurements, with a large numberof ac data sets. In the case of extraction of HBT parameters (Example 11.2), the reduction of ac extraction time was also important, but it was the flexibility of the simulation tool that was criticalfor modeling the self-heating effects. In the case of development of a CAD library of passive elements (Example 11.1), FIT.. S was useful on two fronts: the symbolic form was helpful in the development of
305
Sec. 11.4 Examples
Vbe (V) 1.8 r - - - - - - - - - - - - - - - - - - - ,
1.6 1.4
1.2
0.5
1.5 2 Vee (V)
2.5
3
3.5
Figure 11.11 Vbe-Vcecharacteristics of GaAs HBT.
Figure 11.12 S-parameters of GaAs HBT.
model topology, and FIT-S was also used in extraction of parameters from frequency-domain measurements, where, as in previous cases, a significant reduction of the execution time was obtained. In the examples discussed previously, the use of symbolic simulation reduced the execution time of frequency-domain analyses from 13 to 17 times. However, the evaluation of symbolic functions is only a part of all computations performed during parameter extraction. The values of symbolic functions must be converted into S-parameters, they must be stored in a database of results, compared with the corresponding measurement values to update the value of the error function, etc. Therefore, a more realistic performance gain is obtained by comparing the total execution time with and without symbolic analysis for a typical extraction process. The result of such a comparison depends on the number of frequency points, and, for previous examples, varied between three and eight times.
306
Chapter 11
Symbolic Methods in Semiconductor Parameter Extraction
Gate
- - - - - - - - - -. Ad
Drain Ld
Cds,
r
Cpg
r
Cpd
Source Figure 11.13 Small-signal model for GaAs FET.
11.5. CONCLUDING REMARKS Extraction of model parameters through optimization is a practical approach, especially for models for which direct extraction methods are not practical (thermal effects, parameter conversion, etc.). To obtain parameters of large-signal models, both static and dynamic characterization must be performed. An integration of symbolic analysis with traditional numerical simulation can significantly reduce the simulation time for frequency-domain analyses. In the case of parameter extraction, this reduction can be used for more sophisticated extraction strategies or optimization methods, which-in general-are more computationally demanding. The speed-up of the simulation is not the only advantage of the integrated numerical/symbolic extraction. The symbolic form of (some) results can be useful in model development. Availability of symbolic expressions can help in the search for adequate model structure; it can also be useful in the determination of the most sensitive parameters for different data sets; this, in turn, is helpful in developing efficient extraction strategies. Another possible enhancement in the domain of model development is an automated search of optimal topology for the modeled device (e.g., the algorithms presented in chapter 8). The selection of the internal representation of symbolic functions should be guided by an efficient evaluation of these functions. The table representation used in FIT-S is only slightly less efficient than a binary code or a compiled high-level code, while it eliminates disadvantages of these other solutions (nonportability, a need of dynamic compiling and linking) [41l. In parameter extraction, the evaluation of symbolic functions is only a small part of the required computations. Because the analyzed circuits are very simple, the influence of the representation of symbolic functions on the performance of the extractor is difficult to observe. However, for more general applications of symbolic simulation (more complex
307
Sec. 11.5 Concluding Remarks
Gm (5) 0.035 . - - - - - - - - - - - - - - - - - - . r - - - - - - - - . Vgs=0.5 0.03 Vgs=0.25 0.025 -eVgs=O.O 0.02
-.-
0.015
Vgs=-O.25
0.01
Vgs=-0.5
0.005
Vgs=-0.75
-++
... -+-
0.2
0.4
0.6
0.8 1 Vds (V)
1.2
1.4
1.
Vgs=-1.00
(a)
Rds (Ohm) 1,000 r---------------~ ,..-------. Vgs=0.5 500 r - - - - - - - - - . . & = . ; ; ; ;........:=:=:---:~--+--==ooJ.----,I 200
L---------c~~~d~~~~~
100
r------:-~~~~~~-------1
50
~-____;::;~~~~~--------l
20
t:::::;;;;;.....~~."e=-7'-:J~----------1
10
t----=-~~-.r-------------1
-.-
Vgs=0.25 ~
Vgs=O.O Vgs=-0.25
-+-
Vgs=-O.5
+
...
5t-=:;;;~=-----------------t
Vgs=-O.75
2-"'"--....I.------~....I.-.....I.--J.----J.---l-~---J----L..-4..---l.___l.__.J
Vgs=-1.00
o
0.2
0.4
0.6
0.8 1 Vds(V)
1.2
1.4
1.
-+-
(b) Figure 11.14 Extracted transistor parameters in function of bias voltages: (a) dynamic Gm; (b) Rds =1/Gds'
circuits and/or greater numbers of symbols), the symbolic functions become very complex, and then their representation must be carefully selected. The simplification of symbolic functions also should be considered [42], [43]. The implementation of symbolic analysis in the FIT-S program was done with emphasis on efficient ac analysis of linear, lumped, and stationary circuits. For such
308
Chapter 11
Symbolic Methods in Semiconductor Parameter Extraction
circuits, the characteristic functions are polynomials in the complex frequency (s) with real, constant coefficients. Some modifications are needed if distributed elements (e.g., transmission lines modeling accesses to measured devices) or other frequency-dependent elements are to be taken into account. In the present implementation, symbolic analysis is applied to ac analysis only. However, results of ongoing research on extensions of the symbolic approach to other types of analyses (nonlinear, transient) ([42], [44], and chapter 7 of this book) could be of interest. The modular structure of the FIT-S program should be helpful in implementation of such enhancements.
References [I] W. M. Zuberek et aI., "Simulation-based parameter extraction and some applications," lEE Proc.Circuits, Devices Syst., vo1.141, no. 2, pp.129-134, April 1994. [2] A. Ibarra and J. Gracia, "Strategy for DC parameter extraction in bipolar transistors," lEE Proc. Circuits, Devices Syst., vol. 137, no. 1, pp. 5-11, January 1990. [3] F. Lin and G. Kompa, "FET model parameter extraction based on optimization with multiplane data-fitting and bidirectional search-a new concept," IEEE Trans. Microwave Theory Tech., vol. 42, no. 7, pp. 1114-1121, 1994. [4] C. Scharff, J. C. Carter, and A. G. R. Evans, "New and fast MOSFET parameter extraction method," Electron. Letters, vol. 28, no. 21, pp. 2006-2008, 1992. [5] P. R. Karlsson and K.O. Jeppson, "An efficient parameter extraction algorithm for MOS transistor models," IEEE Trans. Electron Devices, vol. 39, no. 9, pp. 2070-2076, 1992. [6] K. Doganis and D. L. Scharfetter, "General optimization and extraction of IC device model parameters," IEEE Trans. Electron Devices, vol. 30, no. 9, pp. 1219-1228, 1983. [7] P. Conway et aI., "Extraction of MOSFET parameters using the simplex direct search optimization method," IEEE Trans. Computer-Aided Design, vol. 4, no. 4, pp. 694-698, 1985. [8] K. Garwacki, "Extraction of BJT model parameters using optimization method," IEEE Trans. Computer-Aided Design, vol. 7, no. 8, pp. 850-854, 1988. [9] J. W. Bandler et al., "Integrated model parameter extraction using large-scale optimization concepts," IEEE Trans. Microwave Theory Tech., vol. 36, no. 12, pp. 1629-1638,1988. [10] A. Davies and A. K. Jastrzebski, "Parameter extraction technique for nonlinear MESFET models," Proc.IEEE Conf. Microwave Theory Tech., pp. 747-750,1990. [11] L. T. Wurtz, "GaAsFET and HEMT small-signal parameter exraction from measured S-parameters," IEEE Trans. Instrumen. Meas., vol. 43, no. 4, pp. 655-658, 1994. [12] S. Lee and S. W. Kang, "A parameter extraction method using cutoff measurement for a large-signal HSPICE model of HBTs," IEEE Trans. Electron Devices, vol. 41, no. 1, pp. 112-114, 1994. [13] M. Eron et aI., "MESFET model extraction and verification techniques for nonlinear CAD applications," Proc. Third Asia-Pacific Microwave Conf., Tokyo, Japan, pp. 321-324,1990.
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[14] G. L. Bilbro et aI., "Extraction of the parameters of equivalent circuits of microwave transistors using tree annealing," IEEE Trans. Microwave Theory Tech., vol. 38, no. 11, pp. 1711-1718, 1990. [15] Y. H. Hu and S-W. Pan, "SaPOSM: An optimization method applied to parameter extraction of MOSFET models," IEEE Trans. Computer-Aided Design, vol. 12. no. 10,pp. 1481-1487, 1993. [16] S. G. Skaggs et aI., "Parameter extraction of microwave transistors using a hybrid gradient descent and tree annealing approach," IEEE Trans. Microwave Theory Tech., vol. 41, no. 4,pp. 726-729, 1993. [17] A. Konczykowska, W.M. Zuberek, and J. Dangla, "Parameter extraction with the FIT-2 program," Proc. 10th European Con! Circuit Theory and Design, vol. 2, Copenhagen, Denmark, pp. 762-771, 1991. [18] HP IC-CAP Modeling and Characterization Software. Hewlett-Packard Information, Santa Rosa, CA, 1993. [19] HarPE, User's Manual. Optimization System Associates, Dundas, Ontario, 1990. [20] SUXES 20, User's Manual. Electrical Engineering Software, Inc., Santa Clara, CA, 1988. [21] UTMOST. SILVACO Information, 1992. [22] W. M. Zuberek, "SPICE-PAC, a package of subroutines for interactive simulation and circuit optimization," Proc. IEEE Int. Con! Computer Design, Port Chester, NY, pp. 492-496, 1984. [23] E. Cohen, Program reference for SPICE 2. Memorandum UCBIERL M592, University of California, Berkeley, 1976. [24] H. Wang et al., "Temperature dependence of DC currents in HBT," Proc. IEEE Int. Microwave Symp., Albuquerque, New Mexico, pp. 731-734,1992. [25] A. Konczykowska, W. M. Zuberek, and J. Dangla, "Characterization of semiconductor devices using technological and geometric parameters," Proc. 35th Midwest Symp. Circuits Syst., Washington, DC, pp. 412-415, 1992. [26] J. A. NeIder and R. Mead, "A simplex method for function minimization," Computer Journal, vol. 7, pp. 308-313, 1965. [27] NAG FORTRAN Library Manual Mark 9, vol. 3. Numerical Algorithms Group, Oxford, UK, 1982. [28] W. M. Zuberek and A. Konczykowska, FIT-5, A Simulation-based Data-driven Parameter Extraction Program. Tech. Rep. #9402, Department of Computer Science, Memorial University of Newfoundland, St. John's, Canada AIC-5S7, 1994. [29] D. O. Pederson, "A historical review of circuit simulation," IEEE Trans. Circuits Syst., vol. 31, no. 1, pp. 103-111, 1984. [30] J. Vlach and K. Singhal, Computer Methods for Circuit Analysis and Design. New-York: Van Nostrand Reinhold, 1983. [31] W. J. McCalla, Fundamentals ofComputer-Aided Circuit Simulation. Boston: Kluwer Academic, 1988. [32] W. K. Chen, Applied Graph Theory - Graph and Electrical Networks. Amsterdam: North-Holland, 1976. [33] W. Zuberek, A. Konczykowska, and D. Martin, "An approach to integrated numerical and symbolic circuit analysis," Proc. IEEE Int. Symp. CircuitsSyst., vol. 1, pp. 33-36, London, UK, 1994. [34] A. Konczykowska et aI., "Symbolic analysis for CAD of microwave circuits," Symp. Computer-Aided Design Microwave Circuits, London, 1985.
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[35] C. W. Ho, A. E. Ruehli,and P. A. Brennan, "The modified nodal approach to network analysis," IEEE Trans. Circuit Syst., vol. 22, no. 6, pp. 504-509, 1975. [36] J. Starzyk and A. Konczykowska, "Flowgraphanalysis of large electronic networks," IEEE Trans. Circuits Syst., vol. 33, no. 3, pp. 302-315, 1986. [37] C. L. Coates,"Flow graph solutionsof linearalgebraicequations," IRE Trans. Circuit Theory, vol. 6, pp. 170-187, 1959. [38] N. Hassaine, "Modelling of passive elements of GaAs integrated circuits." Ph.D. dissertation (in French), INPG, Grenoble, 1994. [39] N. Hassaine et al., "Library of parasiticelement models for MMICs and MHMICs," Proc. 22nd European Microwave Conf., Espoo, Finland, pp. 356-361, 1992. [40] A. Konczykowska et al., "Parameter extraction of semiconductor devices electrical models using symbolic approach," Alta Freq., vol. 5, no. 6, pp. 291-293, 1993. [41] A. Konczykowska and W. Zuberek,"Functionevaluationin symbolicanalysis," Proc. IEEE Int. Symp. Circuits Systems, vol. 3, pp. 2217-2220, Seattle, WA, 1995. [42] G. Gielen and W. Sansen, Symbolic Analysis for Automated Design of Analog Integrated Circuits. Boston: KluwerAcademic, 1991. [43] F. V. Fernandez et aI., "Formula approximation for flat and hierarchical symbolic analysis," Int. J. Analog Integrated Circuits and Signal Processing, vol. 1, pp. 183-208~ November 1991. [44] B. Alspaugh and M. Hassoun, "A mixed symbolic and numeric method for closed-form transient analysis," Proc. 10th European Con! Circuit Theory and Design, Davos, Switzerland, pp. 1687-1692, 1993.
12 Syed A. Aftab Motorola Strategic Systems Tech., Tempe, AZ M. A. Styblinski Dept. ofElectrical Engineering Texas A&M University
Statistical Delay Characterization of CMOS Digital Combinational Circuits
College Station, TX
12.1. INTRODUCTION The previous chapters were devoted to the application of symbolic analysis techniques to analog circuits. This chapter is unique in the sense that it discusses an application of symbolic/iterative techniques to digital circuits. In contrast to analog circuits, fully automated techniques for the generation of symbolic expressions still have to be developed for digital circuits. 1 This is because the time-domain phenomena are described by nonlinear differential equations, which have to be individually simplified, such that a symbolic analytical solution for the output waveforms in terms of transistor parameters and the shape of the input waveform is possible. In some cases, the closed-form symbolic solutions for delays either do not exist or are very difficult to obtain. However, if it were possible to obtain these symbolic solutions for delays of basic building blocks, then it would be natural to apply symbolic model generation to digital circuits. Digital combinational circuits lend themselves well to symbolic model generation, because they are easily decoupled into numerous small-scale subcircuits, or cells, such that each local cell can be individually analyzed with higher efficiency. This decoupled structure can be fully exploited by taking advantage of latency, event-driven operations, and the regular structure of partitioned cells to efficiently generate symbolic formulas for delays in each cell along specified signal paths. The input waveforms for each cell are the output waveforms of the previous cells in the signal path. The total delay would be the sum of delays through each cell in the path.
1 Symbolic
analysis is also used in formal verification of digital circuits using Boolean symbolic
formulas.
311
312
Chapter 12
Statistical Delay Characterization of CMOS Digital Combinational Circuits
In order to take advantage of these arguments, closed-form symbolic solutions for delays of basic building blocks are required. In this chapter, these solutions are obtained using a combination of symbolic and simple iterative methods, because it is practically impossible to always be able to obtain a closed-form delay formula of sufficient statistical accuracy. The resulting models are orders of magnitude faster than the standard iterative numerical time-domain methods (used in such programs as SPICE), and their accuracy in the estimation of signal delays and their statistical properties is very good. This chapter presents a specific application of these new methods to the statistical delay characterization of a class of CMOS combinational circuits. Statistical variations of signal delays are caused by the variations of transistor model parameters, which are a result of the variations of the IC manufacturing process. The vector of the DC characteristic-related CMOS transistor model parameters will be denoted by p in what follows. Similarly, the vector of parameters of the transistor capacitance models will be labeled as pc. Several other parameter vectors will be used: X is the vector of designable transistor parameters, which in this case are transistor widths and lengths, collected into the corresponding vectors Wand L. All random parameters (also called "noise" parameters) are collected into the vector 8. They represent some fundamental random process parameters, and/or some basic CMOS transistor model parameters, such as the oxide thickness, transistor photolithographic width and length reduction, substrate doping, etc. Their specific meaning will be explained later. The objective of statistical delay characterization is to find statistical parameters (such as expectations, variances, correlations, etc.) of delays (represented by the vector y) along specific VLSI circuit signal paths. Moreover, for the purpose of delay optimization and delay variability minimization, the dependencies of these parameters on the designable parameters X have to be identified. The dependencies between different parameters involved in the statistical delay analysis are shown schematically in Fig. 12.1. The X and 8 parameters are combined in Fig. 12.1 through the vector functions p = jJ (X, 8) and Pc = Pc (X, 8), which represent specific statistical models used (in our case, approximating formulas or physical capacitance models), to be described in a later section. The P and Pc parameters are combined into the e vector, which is then passed to the symbolic delay simulator, and constructed automatically for a specific circuit, containing the waveform delay formulas and some iterative algorithms. All the delays are collected in Fig. 12.1 into the vector y. The two major techniques used in practice to statistically characterize circuit performances are the Monte-Carlo (MC) method and sensitivity-based methods. The MC method (represented in Fig. 12.1 as an external loop) involves repetitive circuit analyses for different realizations of the vector of random parameters 8. The MC methods are in general expensive, because the minimum number of analyses required to obtain a reasonable statistical accuracy is about 100-300. The sensitivity-based methods involve repetitive circuit analyses involving perturbations/ of 8; parameters (e.g., along the coordinate axes). Moreover, for circuit optimization, the designable parameters X have to be changed (e.g., to estimate the gradient of a specific objective function). For a large number of 8 and X parameters, the sensitivity-based methods are also expensive (typically, hundreds of analyses are required). Because even a single time-domain SPICE analysis of a large VLSI
2 Direct methods of sensitivity calculations also exist, but are expensive for a large number of X and
e parameters.
Sec. 12.1
313
Introduction P - device model parameters (DC) Random Number Generator
Loop (such as Monte Carlo)
...
a2
al
~
a - fundamental device random parameters
at
StatisticalDevice Models P = (X ,a) P\:= pc(X,a)
P
PI
P2
III R.,
...
- parametersof transistorcapacitance modeI
Y( x ,a)- circuit performances(delays)
XI X" •
DesignableParameters X (transistorlengths and widths)
PJ
Rz
SimulatorParameters e = ( p,P1)
e I
e
...
e
k
SymbolicDelay Simulator y y( e) y(X,a)
=
=
Y1 Statistics of y:
...
Y",
Yj , o j,etc.
Figure 12.1 Dependencies between different parameters involved in statistical delay simulation.
circuit can take several hours of CPU time, statistical analysis and optimization of these circuits are prohibitively expensive, and currently only small VLSI building blocks can be statistically characterized and optimized. To increase efficiency, switch-level simulators using analytical models are used in practice. However, the existing switch-level simulators are primarily configured for nominal analyses only, and are difficult to adapt for statistical analysis. Also, simulators with a relatively good nominal accuracy suffer from poor statistical accuracy. The approach developed in this chapter is a successful attempt to statistically characterize large combinational CMOS digital circuits with high efficiency and accuracy. The statistical modeling methodology described here is characterized by the following features: • Advanced analytical delay models are introduced, based on explicit solutions of appropriate circuit equations. The solutions include the effects of transistor dimensions (the designable parameters X), the basic (independent) process parameters (the noise parameters 8), input waveform shape, and some secondary effects such as back-bias (when the source and bulk are at different potentials). The approximations used reduce the complexity of the circuit solutions, while maintaining high statistical accuracy. The resulting solutions can be also parameterized using additional tuning parameters, as needed to improve the accuracy of the delay estimation. Simple iterative solutions are used where analytical solutions are not possible.
314
Chapter 12
Statistical Delay Characterization of CMOS Digital Combinational Circuits
• The analytical solutions are parameterized by the transistor and capacitor model parameters. The selected transistor model developed in Ref. [I] is empirical, with nonphysical model parameters. Therefore, an advanced interpolation method proposed in Ref. [2] is used to link the designable X and noise parameters to the nonphysical transistor model parameters p, i.e., p :=:: jJ (X, 8) .
e
• Local delays are combined together for fast delay computations of combinational VLSI circuits. The relevant C-code is automatically generated for the selected signal paths to increase efficiency. It relates individual transistor delays to the X and parameters, using symbolic formulas mixed with the calls to iterative algorithms as needed.
e
12.2. OVERVIEW OF SYMBOLIC I ANALYTICAL DELAY MODELING TECHNIQUES The high costs of device-level time-domain analysis of large digital circuits (e.g., as implemented in SPICE) stimulated extensive research on other, more efficient (simplified but accurate) methods. Many techniques, such as those exploiting latency [3], using the waveform relaxation approach [4], etc., have been introduced over the last two decades. A broad class of methods is a descendent of very fast logic circuit simulators (which usually assume fixed delays of basic building blocks of a large digital circuit). This class includes "improved" logic simulators with more accurate delay models and event-driven switch-level timing simulators. Both types are characterized by the use of local analytical delay formulas on the MOS transistor level. Major techniques used here are based on (1) RC (resistor, capacitor) models replacing the highly nonlinear devices and their capacitances, and on (2) models using the direct solution of local nonlinear circuit equations. Such techniques are very different from the "black-box" modeling strategy, which uses approximating (often regression) equations for larger digital blocks [5], [6], especially for statistical circuit design applications. Macromodels have also been used on the gate level [7], [8]. The three basic analytical techniques for delay modeling are briefly discussed in the following sections.
12.2.1. General Assumptions A general model of a digital combinational circuit to be considered in this chapter is shown in Fig. 12.2. In what follows, it is assumed that the basic structure to be considered is a three terminal device charging or discharging a single lumped capacitor through its two terminals, and controlled by the third (input) terminal. Fixed dc voltages VDC 3 are applied to the remaining nodes. Each block 1, 2, ... , N is represented by a model, which can be a switched linear resistor (for RC analysis), a nonlinear current source controlled by V. (1) In
and the fixed de voltages VDC' or a composite model representing several devices. Notice that two or more nodes may be connected to the input terminal, as shown for block 2. It is also assumed that for each block the input-output capacitance (shown as COl for block 1) is small in comparison with other capacitances, so there is no significant direct signal 3 These voltages are
fixed only during the time when the input voltage Vi,,(t) is switching.
Sec. 12.2 Overview of Symbolic / Analy1ical Delay Modeling Techniques
COl
:1 ~ - - Vin(t) 1
Co V
V DC
iD(t)
+ Cl
{
315
oc
L
'O , I( t)
VDC{
Device mode l
(linear, non-linear.
S
co mposi te, etc.)
Figure 12.2 A general model of the combinational digital circuit usedin this
chapter.
transmission through this capacitance. Only one input changes at a time (i.e., there are no race conditions at the inputs") . The composite capacitances CO' C l' ..., CN represent all parasitic/device capacitances lumped together, from both the current block and the loading (fan-out) blocks. The circuit is memory-less (combinational) and no feedback signals exist.
12.2.2. RC-Based Models The simulators using RC element-based modeling techniques [9]-[18] replace a nonlinear time-variant transistor by a linear resistance. Parasitic capacitances are modeled by fixed, time-invariant capacitors. Node voltages are represented by discrete levels and each transistor is replaced by a linear resistive switch controlled by the voltage level at the gate. The circuit is therefore represented as a connection of resistive (R) and capacitive (C) elements, switches, and voltage sources . Each block in Fig. 12.2 is replaced by resistors in series with ideal switches as shown in Fig. 12.3a for an inverter. A lumped RC model (with one or more time constants) is created using the Elmore's time-constant approximation [19]. Node voltages are approximated as single or two time-constant waveforms: V(t) ::::Ae V(t) ::::Ae
4 Event-driven
-ritA
-ritA
(12-1) -rlts
+ Be
simulators normally have the ability to detect race conditions.
(12-2)
316
Chapter 12 Statistical Delay Characterization of CMOS Digital Combinational Circuits
==>
V.
In
V.
In
(a)
(b)
Figure 12.3 (a)CMOS inverter andits RCrepresentation; (b)transistor chainand
its RC representation.
where t A and r B are the time constants. For simplicity, only the single time-constant model of (12-1) is assumed in this overview. For a CMOS inverter with a rising step transition applied to its gate, the output capacitance Cout 5 starts discharging (see Fig. 12.3a).The output voltage is approximated as Vout(t)
= Vdde
-tit n
ifVout(t=O) = Vdd , where t ll = RnCout.Forthecharging
case, the output voltage is approximated as Vout (t) = tp
vdi 1 - e -tl'Cp ).
where
= RpC
OU1 •
Figure 12.3b shows a more complicated case of a chain of N serially connected transistors and its linearized RC representation. This figure will be used to introduce the concept of the basic Elmore's time constant (ETC) [19]-[21]. The node capacitance Ci,
i = 1, ... , N, is the total capacitance seen at the ith node. Similarly, R.I denotes the equivalent resistance of the ith transistor. This RC network is characterized by the following set of equations: 5 This capacitance is a lumped capacitance consistingof the total parasitic capacitance seen at this node.
Sec. 12.2 Overview of Symbolic / Analytical Delay Modeling Techniques
dV
317
V - V -
-cN -dt:N= -N-R-N -1 N
dV k Vk - Vk - I -C- = ---k dt R
k = 1, ..., N-l
(12-3)
k
dV O Vo VI - Vo -C --o dt = RO RI This set of equations is solved, assuming that all capacitors are charged to Vdd at the beginning of the discharge (i.e., when all the (ideal) switches connecting the resistors simultaneously close). If the voltage VN(t) is approximated by the single time constant model VN (t) = Vdde
VN (t)
-tit ", and the delay tD is defined as the time (relative to
t = 0) when
= Vdd / e, then the delay is equivalent to the time constant t n . The total delay is
then approximately [20] N-I
(12-4)
tD"=Ltj i=0
where (12-5)
Note Each term t,I is an RC time constant associated with the ith discharging capacitor C,. I that if only the transistor Mj switches, while all other transistors are already on, then the capacitances Co' ... , Cj _ I are assumed to be zero in (12-4) because they have already been discharged. ETC is related to the one-pole approximation of the circuit step response and is usually used as a first-order approximation of circuit delay. The use ofRC modeling techniques significantly simplifies the calculation of delay. However, the practical implementation of this method requires that several problems be addressed. Because a MOSFET is at best a nonlinear resistance, the value of R can be approximated in an average sense only. The best-case resistance value is obtained if the MOSFET is in saturation. A more realistic value is the resistance averaged over the overall switching interval. Such a value is difficult to obtain without solving the circuit equations. In the example of Fig. 12.3a, the transistor M p is off because of the rising step input. The
M n transistor discharge current is described by Idn = Cout [dV out/ dt] with the initial condition Vout (t = 0) = Vdd . The expression used for I depends on the transistor model dn
selected (SPICE Level 1 model is normally used because of its simplicity), and the transistor region of operation during the switching period. By comparing the actual solution of V ou t (r) with the approximation in (12-1), a value for the effective resistance R n can be
318
Chapter 12 Statistical Delay Characterization of CMOS Digital Combinational Circuits
estimated. In the SPICE Level 1 model, the following equation for the drain current I D is used:
o
(cutoff)
P;( 2 (V
gs - Vth ) Vds -
~s)
~n 2 2 (Vgs-Vth ) (1 + AVds)
(linear region) (12-6) (saturation region)
where Vd, s Vgs,and Vth are the drain to source, the gate to source, and the threshold voltages, respectively, of the NMOS transistor, and ~n == k' (W/ L) , where k' is a parameter dependent on the process, W is the width, and L is the length of the transistor. The time constant t can be calculated as [20], [21] n
(12-7) Consequently, the equivalent resistance is (12-8) Using this expression to calculate Elmore's time constant for the serially connected transistors in (12-4) is complicated by the body-bias effect. When the source and the bulk are at different voltages (Vsb:t: 0) as in a transistor chain, the threshold voltage is usually calculated from (12-9) Because 'Y> 0 and 21<1>1 > 0, Vth increases as Vsb increases. The effective resistance also increases, causing the current to decrease. The body-bias effect is very important, and should be included in delay calculations [21]. However, it significantly increases complexity. Normally, back-bias is neglected in order to simplify the analysis, and tuning parameters are often used to tune the simulator and increase accuracy. An additional difficulty is that (12-8) is only valid for a step response, so it cannot be directly used for any real circuit (with cascaded subcircuits), where a subcircuit input is actually the response of the previous subcircuit. Also, a real circuit may require two or higher time constants to obtain better model accuracy, which complicates the calculation of the effective resistance. Delay tables (built in a presimulation phase) were used in Refs. [14] and [15] to map the transistors to the equivalent resistances that were functions of the slope of the input waveform at the gate node. Alternatively, in the approach proposed in Refs. [10], [11], [17], and [18] a generic delay was determined using a single time constant (12-1) or a two-time-constant approximation (12-2), assuming a step excitation applied to all transistors. This "zero-delay" waveform was then transformed to the actual delay using an empirically determined (during the presimulation phase) piecewise linear transformation dependent on the slope of the input waveform. However, both methods require a significant amount of effort during the presimulation phase [22], and are not sufficiently accurate.
Sec. 12.2 Overview of Symbolic / Analytical Delay Modeling Techniques
319
Until now, RC-based methodologies have proven to be inadequate for statistical analysis, which requires good local accuracy. As mentioned earlier, RC models tend to model the average behavior only, because transistors are not locally well represented by linear and constant resistors. Therefore, even if the effects of the noise parameters are included in the effective resistance calculations, the resistance is still defined in an average sense only. Modifications to the RC network-based simulators are possible for simple structures only, such as inverters [23]. These modifications are by no means trivial and require a great deal of effort. For more complex structures such as NAND/NOR gates, good statistical accuracy is difficult to obtain. This is not surprising, because standard deviation calculation requires accurate function and derivative estimation, which in tum implies a model with high local accuracy. Macromodeling is often used to provide more accurate timing simulation relative to the RC-based modeling methodology.
12.2.3. Macromodels Macromodeling is used to reduce the total amount of information representing a subcircuit being modeled. Generally, accurate results have been reported for nominal analysis for logic gate circuits [7], [8]. Macromodels exploit the repetitive structures in VLSI circuits. In Ref. [24], delays were modeled by linear functions of load capacitance and piecewise linear functions of input waveform slope. The models were stored in a two-dimensional table created in the presimulation phase. SPICE analyses were performed for basic building blocks such as inverters, NAND/NOR gates, etc., for different values of output capacitances and input slope. Macromodeling generally leads to high accuracy, because SPICE simulations are used to characterize the building blocks. The major drawback of this approach is that there is usually no direct dependence on geometric (widths and lengths) or process parameters. If the geometric parameters change (for example, during optimization), then a new model must be created. The memory requirements would increase significantly if the effects of geometric and process parameters were to be included in the macromodels. In Refs. [5] and [6], macromodels of some basic building blocks were created for statistical analysis using approximation ("black-box") techniques, Le., the delays were directly modeled in terms of the geometric and process parameters. The major drawback of both approaches is that the number of SPICE simulations required in the presimulation phase is very large, leading to a significant decrease in efficiency. The second drawback is that the models created are nonphysical and do not enhance the physical understanding of the problem. For statistical analysis, the most promising approach appears to be the direct transient solution of circuit equations, as discussed in the following sections.
12.2.4. Direct Solution of Circuit Equations The direct solution of VLSI circuit equations leads to complex analytical formulas, unless very basic device models are used. Each building block must be individually analyzed and analytical delay formulas determined. The presence of a finite input slope and back-bias effects can significantly complicate the solution. On the other hand, this method offers the potential for obtaining the high accuracy essential for accurate statistical analysis (see section 12.3). For increased efficiency, suitable approximations and simplifications are necessary to decrease the complexity associated with this approach. In what follows, a
320
Chapter12 Statistical Delay Characterization of CMOSDigitalCombinational Circuits
methodology based on a direct solution of appropriate circuit equations will be presented, in order to increase statistical accuracy beyond what is offered by the existing methods. Alternative approaches used by other authors will be referred to, where applicable.
12.3. NOMINAL ACCURACY VERSUS STATISTICAL ACCURACY As mentioned earlier, achieving good nominal accuracy is not sufficient for good statistical accuracy . Statistical analysis requires a higher level of accuracy, because both the function and its derivative must be accurately determined. Therefore, delay formulas with simplified approximations (based on empirical or theoretical considerations) that are accurate for nominal analysis, may not be sufficient for estimating a's of delays . In Ref. [23], the RC delay models from Ref. [10] were modified to include the effects of the noise parameters. The effort was successful for simple cases only (such as inverters). For more complicated structures (such as NAND/NOR) gates, errors in estimating a approached 50%, even if the error in estimating the mean was within 5%. Figure 12.4 is used to illustrate the difficulty in achieving good statistical accuracy relative to nominal analysis. In this case, formulas simpler than those to be discussed later in this chapter were used to obtain solutions to the circuit equations, in order to estimate the delay of four 2-input NAND gates connected in series. Large values of loading
6.0
PLOT LEGEND
-+Vo(t) ---l<-eV2 (t) V2 (sm)(t) '" V2 (pm) (t ) -0-IiV3 (t ) V3 (sm)(t) 'V V3 (pm)(t ) - <>---mV4( t) V4 (sm)(t) .. V4 (pm)(t ) - ~
5.0
4.0 (j)
=§ 3.0 > 2.0
1.0
o.0
~~,.....,..-fi'.r~~PI=''r-fI~l...r'-r-,J=i~r--r-'f'''"t"-r-;--;-l'''l1
0.0
10 .0
20.0
30.0 40 .0 time (ns )
50 .0
60.0
Figure 12.4 Error in delayestimation for four 2-inputNANDgates in series using simplified formulas and proposed formulas.
321
Sec. 12.4 The Statistical Modeling Methodology
capacitances were used, so that any errors from the capacitance model would not affect the solution. The output voltage waveforms (V.( )(t)) from the simplified formulas were Ism
compared with the actual waveforms (V.(t)) from SPICE3 for stages i = 1,..., 4. Here, the I
input waveform to stage i is the output waveform of stage i-I. For such a configuration, the nominal analysis showed an error of - 4% when comparing the time when the output
waveform reaches Vdd/2, i.e., 'i =
tl Vi (t) =V
dd
!2 '
The meanof a lOO-pointMonte-Carlo
sample data set showed similar accuracy. However, crt had an error of - 30%, even though the statistical accuracy of each 2-input NAND gate in isolation was within - 5%. The figure shows how the error propagated from one logic gate to the next for a typical "bad" point in the Monte-Carlo sample. Even though the number of such points was small, they affected the extreme boundaries of the distribution of t (close to the minimum and maximum values), causing a significant error in estimating cr The output waveforms estimated with
r
the proposed strategy at the same data point are represented as Vi(Pm)(t) in Fig. 12.4. Notice that the error is dramatically reduced and, consequently, the estimation of the standard deviation crt is also more accurate (- 5%).
12.4. THE STATISTICAL MODELING METHODOLOGY The statistical modeling approach discussed in this chapter is illustrated in Fig. 12.5 for a CMOS combinational circuit, and consists of two stages. The presimulation stage (Fig. 12.5b) is performed just once and is described here: 1. Select the transistor and capacitor device models. These models should be accurate, but simple enough so that the circuit equations can be analytically solved. Select a statistical model that accurately models the process variations. 2. Statistically characterize each device. This involves determining the relationship between the device model parameters p and the geometric X and noise parameters 8. The selected transistor model (see section 12.5.1) is nonphysical, so no direct dependence of the transistor model parameters P on the geometric and noise parameters is available. Therefore, an efficient approximation strategy (see section 12.5.3) is used to model the relationship p = p (X, 8). In contrast to the device model parameters, the capacitor model parameters Pc are obtained directly from the statistical model (see section 12.5.3 for details), so no approximation is needed. 3. For each building block, obtain vet) by solving the generic equation Cdv (t) = iD (t) dt. Several cases may arise, with different expressions for the current iD(t) in each case. The analytical models developed here are hybrid analytical/iterative and are characterized by the transistor and capacitor model parameters (see section 12.5) and the shape of the input waveform. Wherever
322
Chapter 12 Statistical Delay Characterization of CMOS Digital Combinational Circuits
Select device models Select statistical model
Reduce circuit into cells along critical paths
Decompose cells into basic building blocks Statistically characterize devices p =p(X,a)andp =p (X,a)
Building block ...
Generate C-code for selected paths
Solve circuit equation C dv(t) = iD(t) dt
(b)
(a)
Delay Executable
x. "in (t)
I
I I
Hybrid analytical/iterative models
: for basic building blocks
delay W,L
a
p = p =
c
p (X, a) pc (X, a) (c)
Figure 12.5 Methodology for statistically characterizing delay of CMOS digital circuits: (a) presimulation; (b) code generation for specific signal paths; (c) simulation stage.
possible , more complex building blocks are reduced to simpler blocks , whose equations are easier to manage. The generic local analytical delay models are created once and stored in a delay library. In contrast , the approximation models relating the transistor model parameters p to the geometric X and noise parameters must be recreated if the process data change . Because the approximation models are used to characterize a single transistor type only, this process is computationally inexpensive.
e
323
Sec. 12.5 Device Models
The second stage of the proposed methodology is used to generate delay models based on a specific circuit topology. This process is described here: 1. Select critical paths (input node to an output node) for which delays should be calculated. 2. Decompose each critical path into cells (see section 12.6.1). 3. Further decompose each cell into basic building blocks (such as inverters, NAND/NOR gates, etc.). The output waveform of one building block in a cell is the input waveform to the next building block in the same cell or in the next cell. 4. Combine the local delay expressions of each building block in a selected path. Generate symbolic formulas describing this delay model as C-code corresponding to the delays for each selected path. 5. Link the generated code to form the delay executable. As demonstrated in Ref. [23], this can result in a speed increase of up to 3 orders of magnitude relative to a numerical simulator performing exactly the same operations. Once the C-code representing the delay for a specific path has been generated, compiled and linked, it can be directly used for statistical analysis as shown in Fig. 12.5c. The delay executable has specific calls to the analytical functions that were created in the presimulation stage. 1. Calculate the device model parameters p for the given X and 9 from the approximating equations p = p (X, 9) and Pc = Pc (X, 9). 2. Estimate the total lumped capacitance at the output node of each building block, based on the p values just calculated. c 3. Use the analytical models for each building block from the delay library (see section 12.6). 4. Postprocess the final output waveform V (t) to calculate the delays. o
This methodology is successfully used in the following sections for the statistical characterization of combinational CMOS digital circuits. The first step in the presimulation stage is the selection of the device models (transistor, parasitic capacitances) as well as a statistical model.
12.5. DEVICE MODELS In the statistical modeling methodology just presented, only the transistor and capacitor model parameters exhibit direct dependence on the statistical noise parameters 9 and on the designable parameters X. Therefore, the selection of the transistor and capacitor models is of paramount importance. The device and statistical models must be analytically simple, but sufficiently accurate.
12.5.1. MOS Transistor Model The simple (Levell) SPICE transistor model is of questionable accuracy, especially for short-channel devices, while SPICE Level 2 models are too complex for direct
324
Chapter 12 Statistical Delay Characterization of CMOS Digital Combinational Circuits
analytical solution. A simple empirical MOSFET transistor model was proposed in Ref. [1]. The transistor model accuracy was tested on 0.25 urn NMOS and PMOS transistors. The measured I-V characteristics of both devices were accurately reproduced by the models, while the SPICE Levell model (of a similar level of complexity) was entirely inadequate. Model accuracy was somewhat low in the near and subthreshold regions, but these regions are less important for delay calculation for CMOS combinational circuits. Moreover, the nonphysical nature of the model parameters (which must be extracted from transistor I-V curves) allows for accurate representation of composite MOS structures (e.g., transistors in series or parallel (for NANDINOR gates)). A MOS structure can then be replaced by an equivalent'' composite transistor. For actual experimental data and results demonstrating the transistor model accuracy (for MOSFETs, GaAs FET, and composite MOS transistor structures), refer to Ref. [1]. The basic transistor model used is described here. When a MOS transistor operates in the saturation region, the drain current I D is expressed as a function of the gate-to-source voltage V ,the drain-to-source voltage V and the threshold voltage V as follows:
ds
~
'
th
ID
= ldsat = B (Vgs - Vth ) 11 (1 + AVds ) ;
(12-10)
where B, 11, and Aare transistor model parameters and Vdsat is the drain-to-source saturation voltage. Note that in the standard SPICE Level 1 formula, 11 = 2, so the commonly used Vd s = Vgs - Vth does not apply here. Vdsa t = K (Vg s - V th )
m
(12-11)
(12-12) where the zero-bias threshold voltage Vto' the body-bias parameter 'Y, and the surface inversion potential 2<1> are additional parameters of the transistor model. As usual, the threshold voltage is dependent on the source-to-bulk voltage V back-bias. If the transistor operates in the linear region, then
sb
. This
effect is often called
(12-13) In general, the parameters B, 11, K, m, A, Vto' 'Y, and 2<1> of the transistor model (represented in Fig. 12.5 as the vector p) are sufficient to reproduce the simulated or measured characteristics of MOS devices. For digital circuits, A is generally ignored without a significant loss of accuracy. 7 Here, A is also ignored unless it is required (see section 12.6.5). Two additional parameters are defined for Vgs = V = Vdd and Vbs = 0, i.e., ds
6 Identical I-V curves (de) but with different parasitic capacitances. 7 This
may not be true for submicron processes.
325
Sec. 12.5 Device Models
(12-14) (12-15) I
DO
is defined as the current when V = V = V gs
ds
dd
and VDO is the saturation voltage when
Vgs = Vdd·
All the model parameters are extracted based on SPICE simulations. As an alternative, actual measurement data can also be used, if available. The extraction procedure consists of selecting the values of the gate, drain, source, and bulk voltages and measuring the associated current. By manipulating the transistor model equations (12-10)-(12-15), the transistor model parameters can be calculated. The extraction procedure is outlined next.
EXTRACTION OF TRANSISTOR MODEL PARAMETERS The parameters of the transistor model (12-10)-(12-15) [1] are extracted by applying appropriate V ' V ,and Vb voltages to the transistor and measuring (or calculating) the ds
gs
s
current for each combination. The voltages V , V ,and Vb are user-selected, and the ds
gs
corresponding currents are measured (or calculated).
s
Here, the extraction procedure is described for an NMOS transistor only.8 Figure 12.6 shows the I-V curves for a MOS transistor. The numbers 1-8 on the plots indicate the current measurement points. To extract A, the transistor should be in saturation, so V = 0 and V = V are selected. Then, from (12-10), bs
gs
dd
6
7 8
2
V
v
gs
3
V
ds
(a)
v
gs
(b)
Figure 12.6 Current measurements used to extract the transistor model parameters.
8 PMOS transistors are treated similarly, except for the signs of the voltages.
bs
326
Chapter 12 Statistical DelayCharacterization of CMOS Digital Combinational Circuits
1~1) _ 1 + AVJ])
1(6) - 1+AV(6) D ds
A=
(12-16)
/(6) _/(1) D D
l~l)VJ~) -/~6)VJ])
Next, Vto must be determined. If the transistor is in saturation and V
bs
then from (12-10),
ID( 1)
_ [
_
-
Vto )11
V(2)-V
/(2) D
1(2) D
Vgs ( 1)
=0 and Vds =Vdd,
gs
to
(12-17)
[V(2) gs - Vto )11
1(3) -
V(3) - V gs
D
to
Eliminating 11 from these equations results in the following nonlinear equation: 1(1)
In
D
( 2) /D
I
n
V(2) - V
gs to (3) _ Vgs VtO
I
/(2)
D
I
V(l) - V gs
to - 0
(12-18)
n(3) n (2) _ ID Vgs VtO
This equation is iteratively solved, using the bisection search, to determine Vto' To extract 11 and B, the transistor must operate in saturation. If V V
bs
ds
= 0, then from (12-17),
= Vdd
and
1(1) D In (2) /D
11 = - - - V(l) - V
In gs
V(2) -
gs
(12-19)
to V to
while B can be calculated once 11 is known from (12-10): B
=
/ (1) D
(ViP -Vto)Tl(l + AVds )
(12-20)
To extract m and K, the transistor must operate in the linear region. If \II == 2 - (Vds / Vd sa t)' then the linear region current defined in (12-13) at Vgs = Vgs(i) for fixed V and V =0 is ds
bs
/ (i)
/(i)
D
= \{I(i) ~ V V (i) ds dsat
(12-21)
Sec. 12.5
327
Device Models
Define E (i) == ID(i) /1dsat (i) . Then
I
(i)
E (i) == --!2- = /u)
dsat
\U
(i)
_T_
V
VU) ds dsat
V (2 - --!!.!-.. V) --!!.!-..
=
VU) dsat
VU) dsat
(12-22)
Solvingfor VJ:~t gives
vdsat to Jii)
J
= Vd~ ( 1 + 1 - E (i) E (I)
(12-23)
)
is thus calculatedbased on the measuredvalue of the current I ~i). Then, I J:~t can be
calculated, because A, Vto' 11, and B have already been determined earlier. From the saturation voltageexpression (12-11), one obtains V(4) dsat V(5) dsat
=
(V(4) gs - V th V(5) - V gs th
)m
(12-24)
which leads to the following expression for m:
InVJ;Jt V(5) dsat V(4)-V gs th In (5) Vgs - Vth
m= - - - -
K can be calculatedonce m is known from (12-11), as follows: V(4) dsat
K =
(4 ) ( V gs
(12-26)
)m th
V
To determine 2<1> and 'Y, the voltages V ds and V gs are typically fixed to V and the current dd plotted against Vbs ' From the saturation region current defined in (12-10),
r 1
Vt~) = V
gs
+ [B (l
~~VdS)
(12-27)
Once Vt~7) and Vt~8) are computed, 2<1> is extractedfrom the threshold voltageexpression (12-12):
Vt~7) - VtO --- = Vt~8) - VtO
( J2cl> - Vi]) - ~ )( Vt~8) -
VtO) =
J21cl>1- Vfl) - J21cl>1 J21cl>1- Vi:) - J21cl>1
--,:::===---== (J2cl> - VJ:) - ~ )( Vt~7) -
(12-28) VtO)
328
Chapter 12 Statistical Delay Characterization of CMOS Digital Combinational Circuits
Again, the bisection search is used to extract 2<1>. Finally, 'Y can be extracted once 2<1> is known from (12-12), (12-29)
These equations are sufficient for extracting the MOS transistor model parameters. The next step is to accurately model all the existing capacitances (which will be combined into the lumped capacitances CO' Cl' ... , CN in Fig. 12.2).
12.5.2. Capacitor Model Some of the MOS transistor parasitic capacitances can be safely neglected, while others must be modeled. Here, the nonlinear parasitic capacitances are modeled by linear time-invariant capacitances. This assumption significantly simplifies the solution of the circuit equations. However, it also introduces errors into the delay calculations. These errors can be minimized by appropriate tuning parameters, which are adjusted for the nominal point only. Initially, simple capacitance models, similar to those introduced in Ref. [23], were used. This proved to be insufficient and had to be modified to obtain better accuracy of the resulting statistical model. For more details on these improved models, refer to Refs. [21], [20], and [25]. In Fig. 12.7, the parasitic capacitances of an inverter are shown. They are lumped into a constant input capacitance Cin and an output capacitance Couto The parasitic capacitances are modeled as
Cg = kgLett (wC ox + CGBO) Cd = Cgd + Cdb
(12-30)
Cs -- Cgs +Csb' where C is the total gate capacitance, Cd is the total drain capacitance, C is the total source g
s
capacitance, Leffis the effective channel length, CGBO is the gate-bulk overlap capacitance
c .-.:....g,p~ I
MP
MP
I
-,---
: Cgd,p
..------.....--..------4
:Cgd n
---l.-
--r-
>:
I I
I
I
I I
I
'
I
MN
=r= C :
: (from next stage)
I
-,:C.=C :
in
g,n
+C
g,p
MN
TCout I
I I
I
I
C out =C +Cdb,n +Cdb,p + Cgd,p +Cgd,n Figure 12.7 Capacitance modelfor an inverter.
329
Sec. 12.5 Device Models
per unit length, and kg is a tuning parameter. Cox = £s·1 t ox ,where tox is the oxide I thickness and £Si is the permittivity of silicon. w is an empirical coefficient. Note that for an inverter, the capacitance C = 0, because the source and bulk are S
connected together. The gate-to-drain (C d) and the gate-to-source (C ) capacitances are g
calculated as [21], [20], [25]
where k
gd
~
Cgd =
kgdw(~COX + CGDO)
Cgs =
kgdw(~COX + CGSO)
(12-31)
is another tuning parameter, and CGDO and CGSO are, respectively, the
gate-drain and gate-source overlap capacitance per unit length. The constants 112 and 2/3 represent the worst case values of C d or C ,if k d = 1 g
gs
g
[21]. In such a case, these formulas tend to produce conservative performance estimation. The drain-to-bulk (Cdb) and the source-to-bulk (C ) capacitances are of the sb
depletion type, and are a sum of the junction capacitance (C.) and the sidewall capacitance J
(C. ). If Cd is used to represent a generic depletion capacitance for source and drain, then ep
JSW
Cd ep = C.(V) J
+ C.JSW (V)
(12-32)
where
(12-33)
Here, C' and C. JO
JSW
are the zero-bias junction and sidewall capacitances, V is the bias
voltage applied, and m. and m. J
respectively.' Ad and P ep
d ep
JSW
R
are the junction and sidewall grading coefficients,
are the area and perimeter of the depletion region.
Notice that all these parameters are also required for SPICE analysis. These capacitances are voltage (time) variant, and are modeled as average capacitances over the as follows [21]: entire voltage range V . to V min
max
CjOA dep Vbi [( 1 + ....!!!:!!:!. V = (1 - m.) .) Vb'I J (Vmax - Vmin
9 These
parameters are user-specified, as in SPICE.
)l-m. (1 + Vmin )l-m.] J_
J
Vb'I
(12-34)
330
Chapter 12
Statistical Delay Characterization of CMOS Digital Combinational Circuits
Similarly, the average sidewall capacitance is Cjsw,av = V
=
Here, V
max
max
1 - V.
min
C.
JSW
JVVmax Cjsw(VR)dVR min
OPd Vb· ep
l
(l-m jsw) (Vmax- Vmin)
[(
V )l-mj SW ( V. )1_mj sw j 12-35) 1+ ~ _ 1 + mln V bi V bi
and V . , with the assumed nominal values of 5 V and 0 V, respectively, are min
actually used as additional tuning parameters. As noted before, tuning can be performed (for the nominal point), although until now, no tuning has had to be done. For accurate statistical analysis, transistors and capacitors must be modeled statistically. Notice that both the transistor and the capacitor model parameters are directly dependent on the process parameters. Therefore, a statistical model of the process-related parameters is required.
12.5.3. Statistical Model Statistical variations of the empirical MOS transistor model parameters p = [A, V 0' B, 11, K, m, 21<1>1, y] «12-10)-(12-15)) and parameters p t
c
characterizing the
MaS capacitances (12-30)-(12-35) result from the statistical variations of the manufacturing process. Moreover, the parameters p are, in general, functions of the vectors of transistor widths Wand lengths L. In contrast, in the capacitance models, the dependencies on Wand L (or Let? are explicit (see e.g., (12-30) and (12-31)), and the statistical process parameters (such as Cox) are directly used (see e.g., (12-30) and (12-31)). This is not the case for the parameters p, because they are empirical in nature and do not relate to any actual physical model. Therefore, the dependence of Pi on W, L, along with its statistical distribution are found using the following two major approaches, dependent on the data availability: (a) using direct Mas transistor characterization for different W/s, and
L/ s for a large number of chips; in this way, the approximation models p :=::p (W, L) can be constructed and statistical distributions of p obtainedl'' and (b) using computer simulation, utilizing other more complicated MOS transistor deterministic and statistical models. The second technique has been used in our investigations, so it is described in more detail in the following. Most of the computer programs use more complicated and more "physical" models than the model used in this chapter, such as Levels 2 and 3, BSIM, and other (e.g., proprietary) models used in SPICE. In this case, it has been shown [26] that the device model parameters (as an example, the SPICE MaS model Level 2 was used in Ref. [26]) can be very accurately related through regressional dependencies to a small set of basic, 10 Several
variants of the direct (measurement-based) model construction can be used, using standard statistical techniques, depending on the required accuracy.
331
Sec. 12.5 Device Models
uncorrelated (independent) statistical parameters 9 (often called the basic "noise" parameters). To identify the set 9, the techniques of principal component analysis and factor analysis were used in Ref. [26], followed by the application of linear and quadratic regressional models relating the Level 2 model parameters to 9. The following basic 9., I i = 1, ... , 8, parameters were identified:
8 = TOX (Oxide thickness; same for NMOS and PMOS transistors) 1 e2 = ~ t.; (Length reduction for NMOS) 8
3
=~ Lp (Length reduction for PMOS)
8 = ~ Wn (Width reduction for NMOS) 4
8 = ~ Wp (Width reduction for PMOS) 5 86 = XJ,p (Junction depth for PMOS) 87 =Nsub,n (Substrate doping for NMOS) 88 = Nsub,p (Substrate doping for PMOS) The resulting regression models (in terms of 8) were able to accurately reproduce the statistics of the other Level 2 model parameters and the nonlinear correlational dependencies between some of them. Models of the transistor model parameters p = p (W, L, 8) were created as follows: several sets of values, (w
p (W, L, 9).
Although other
models could be used here, we selected a new, but well-proven, technique developed in Ref. [2] called the maximally flat quadratic interpolation (MFQI). This technique automatically selects an optimal set and number of "base" points, giving the most accurate quadratic interpolation [2], [6]. It has been shown to be more accurate than the traditional interpolation technique using N
= (n; 2) = [(n+ 1) (n + 2) ] 12
data points (''full''
unique quadratic interpolation). The MFQI uses a smaller number of base points than
(n; 2). Figure 12.8 illustrates the procedure for characterizing the transistor.
The nominal values of p parameters for both the NMOS and PMOS transistors with the width of 12 um and the length of 8 urn, for a typical CMOS process, were extracted. They are listed in Table 12-1. In order to test the accuracy of the MFQI models, an independent test data set of 500 samples
was
generated. The error of each MFQI model was defined as E U) = P U) - P (W U), L U), 8 U»), j = 1, ... , 500, where p(j) is the vector of the actual
transistor parameter values for the jth sample, and p(wU), L (j), e(j») is the vector of
332
Chapter12 Statistical DelayCharacterization of CMOS Digital Combinational Circuits
statistical model
-,
Latin Hypercubdj Design (X, S)
~~
p . (W,L,S.) spIce
I
p (X.,S.)
MFQI
generate model
Figure 12.8 Characterization of transistorusing MFQI. Table 12-1 Extracted Nominal Values of NMOSand PMOSTransistor Parameters
A
B
2<1> (V)
y
0.70
0.14
1.01
0.0005
VtO (V)
11
(mAN")
K (V 1-m)
m
(IN)
NMOS
0.04
0.60
1.64
0.194
0.92
PMOS
0.14
0.95
1.92
-0.036
0.53
Pi
(rnA)
VDO (V)
0.32
2.64
2.59
-1.04
0.89
2.18
[DO
transistor parameter values calculated from the MFQI model, at the same sample. The mean ( € ) and standard deviation (cre) of this error (E) is shown in Table 12-2. Even though more
sophisticated types of approximation were available [6], Table 12-2 shows that the MFQI
models are sufficiently accurate for our application. Once the models Pi = Pi (W, L, e) are available (C-code is generated and linked to the rest of the system), a random number generator of a suitable distribution (usually Gaussian) generates eU) points used during statistical circuit analysis, which are then transformed into the Pi parameters, necessary for delay evaluation. Table 12-2 Meanand Sigmaof Error of MFQI Modelsfor Transistor Model Parameters
€
(Je
Pi
A
VtO
11
B
K
m
2<1>
y
NMOS
2.00%
1.87%
1.63%
1.80%
3.27%
2.44%
4.26%
5.77%
PMOS
1.45%
2.01%
3.13%
1.51%
4.58%
6.02%
6.08%
2.88%
NMOS
1.64%
1.89%
1.39%
1.63%
3.17%
2.79%
4.16%
6.12%
PMOS
1.22%
2.33%
2.81%
1.24%
4.38%
5.17%
6.81%
4.89%
333
Sec. 12.6 Analytical DelayModels
Selecting the device models and creating the formulas relating the device model parameters to W, L, and e completes the prerequisites required to generate the symbolic delay formulas.
12.6. ANALYTICAL DELAY MODELS The first step in creating analytical delay models is the decomposition of the circuit into a set of unidirectional cells, allowing each cell to be dealt with independently, thus reducing complexity and increasing efficiency. Therefore, the issues of circuit decomposition and waveform representation must be addressed before the analytical models of the basic building blocks are developed.
12.6.1. Circuit Decomposition Large-scale CMOS circuits must be decoupled into several small-scale subcircuits. Each subcircuit can be more efficiently analyzed individually. Circuit decomposition is normally based on graph representation of each MOS transistor [9], [11], [22]. The approach used in Ref. [27], where each transistor is represented by its switch-level graph representation, namely, a branch between its drain and source plus an isolated node at the gate, is followed here (see Fig. 12.9a). The circuit is partioned into many isolated cells, such that each cell consists of the connected nodes and/or branches. Partitioning is illustrated for a combinational circuit in Fig. 12.9b. Cell 2 is controlled by cellI, while cell D
D
! D
G-1~
>
s
G.
s
(a)
CD
_____;-/>
(@\
®
~ce1l4
Celli Cell 2
(b)
Cell 3
Figure 12.9 Partitioning large-scale circuits: (a) switchgraphrepresentation of an NMOS/PMOS; (b) partitioning of an example combinational circuit.
334
Chapter 12
Statistical Delay Characterization of CMOS Digital Combinational Circuits
3 is controlled by cells 2 and 4. In addition, each cell is further partitioned into smaller building blocks, by deleting the nonconducting branches from the cell. Note that transitive devices (conductive for a short period) are included in the cell. It was shown in Ref. [27] that the parasitic couplings between cells are practically negligible in combinational circuits. The procedure takes advantage of the latency and event-driven nature of combinational digital circuits based on the unidirectional coupling property between partitioned cells. The algorithm dynamically creates a delay model for each cell in the selected signal path-from the input node to the output node. The delay for the selected paths is the sum of the delays of each cell along that path, as shown in Fig. 12.10. The program implementing the algorithm in Ref. [27] is used to generate all the information regarding the list of events as they are triggered. Following the approach in Ref. [23], this information is used to generate the C-code representing the delay for the user-defined specific paths. The details on software implementation can be found in Ref. [28]. Once the circuit is partitioned into simpler building blocks, the analytical delay models for these blocks are generated. These models are strongly dependent on the shape of the input waveform. Therefore, accurate representation of the voltage waveform is essential to accurate delay modeling. Combinational Digital Circuit Delay =1:DelaYCell
[ cell) [Cell ] Output
Input
Figure 12.10 Decomposing a digital circuit into simpler cells.
12.6.2. Waveform
Represe~tation
Accurate representation of the voltage waveforms is critical, because the output waveform of one cell is the input to the next cell in a selected signal path. Generally, a detailed time-domain voltage waveform is not necessary for digital applications. Most simulators approximate the input waveform by a straight line, because of its simplicity. Usually, the slope of the line is determined from the two points at 10% and 90% of Vdd [1], [20]. Another approach based on the two-time-constant approximation of the voltage waveform specifies a ramp that corresponds to the critical regions on the loading gate's DC transfer curve [24] (specifically, the -1 slope points of the dc transfer curve, because such points are the boundaries of the high gain regions of the gate where the output is most sensitive to the input). A multisegment piecewise linear representation of the voltage waveforms is proposed here. This gives added flexibility in cases where errors in waveform representation may be propagated from one cell to the next in the signal path. The accuracy
335
Sec. 12.6 Analytical DelayModels
can be traded off with speed (because more time points have to be computed) by increasing the number of segments selected. For efficiency reasons, a two-segment piecewise linear representation is normally used. Figure 12.11 shows a nonlinear waveform and its different representations already discussed. Note that a typical waveform with an initial fast transition, followed by a slow "tail," is quite well approximated by a two-segment piecewise linear representation . In such a case, the waveform is characterized by three levels: 110 == tl v = 0.1 V
d/
t50 == tl v = Vd/2' and 190 == tl v = 0.9Vdd· In general, the number
of segments is user-defined in the practical system implementation. This increases
programming complexity, because the correct waveform segment must be identified before applying the symbolic formulas to calculate the output voltage (see later in this chapter) at a specific time t, but offers greater flexibility. The proposed representation of the voltage waveforms simplifies the delay calculations for such building blocks as inverters, NAND/NOR gates, etc. The case of a capacitor discharging through an NMOS transistor is considered first. Volts
non-linear function 10%-90% model Slope model - - Piece-wi se linear model
Figure 12.11 Two-segment piecewise linearrepresentation of a nonlinear
waveform.
12.6.3. Charging and Discharging a Capacitor through an NMOS Transistor Several methods to explicitly solve the circuit equations for the case of a capacitor charging (or discharging) have been proposed . In Ref. [22], the currents were modeled as a quadratic function in time and the output voltage was estimated as a linear function of time. The time steps were kept sufficiently small, so that the previous assumptions were valid. This required the estimation of the output voltage at a number of time points, such that the entire output waveform was determined . As mentioned earlier, this level of description is most often not necessary for typical digital circuits. Moreover, the formulas
336
Chapter 12 Statistical Delay Characterization of CMOS Digital Combinational Circuits
used in Ref. [22] were based on the SPICE Level 1 model, which is simple, but introduces substantial inaccuracies into the analytical formulas. In Ref. [1], the circuit equations were solved for the fast input case and for the slow input case. The delays from the fast and the slow cases were connected at a "critical input transition time." The output waveform slope was approximated by 70% of its derivative at Vd d/2. This approximation, although sufficient for nominal responses, appears to be
inadequate for estimating standard deviations (0), especially when logic gates are connected in series (see later in this chapter). Even a small number of "problem" points in the Monte-Carlo data set can cause large errors in estimating o. For example, the error of o can approach 50% even though the average error of the data set may be less than 10%. Following Refs. [22], [1], [20], [21], and [25], the switching period is classified into time intervals (or phases) based on the transistor region of operation and whether the input waveform is changing or if it is fixed. The switching of the NMOS transistor is illustrated for the very fast and very slow input cases in Fig. 12.12. For the very fast input case, three phases (I, II , and III) are defined in Fig. 12.12. For the very slow input case, three phases f are again identified (I, II , and III). Each phase is characterized by a unique differential s
equation(and its solution). The time interval during which the transistor is in saturation and V (t) is switching is called phase I. In phase III, the transistor is in the linear region and g
V (t) is constant. Phase lItiS only applicable to the fast input case, while phase II is only s
g
applicable to the slow input case. In phase II , the transistor is in saturation and Vg(t)=V , dd f while the transistor is in the linear region and V (t) is not constant for phase II . Note that s
g
the number of segments used to represent the input waveform is independent of the phase. In Fig. 12.12, a two-segment piecewise linear representation of the input waveform is shown. t
dsat
is defined as the time when the transistor switches from saturation to the linear
region, i.e., t
dsat
=t(V =Vdsat'l. 0
In contrast to Ref. [1], the circuit equations for all the
phases are solved here, in order to increase the local accuracy. To increase efficiency and reduce complexity, the effects of the parameter A are neglected in the analytical formulas in this section. Such a simplification does not seem to affect statistical accuracy significantly (however, it may be important for submicron processes). Here, v tO
all voltages
= VtOIVdd,
and time by
't
v dsat
are normalized by V
= VdsatlVdd'
= CVddl I DO'
= VDoIVdd),
dd
(v g
= VgIVdd,
V
o
= VolVdd, = IDIIDO)'
all currents by I DO (i D If the gate input voltage is described by a two-segment v DO
piece-wise linear approximation, i.e., v (t) = at + ~ with different values of a and ~ for g
each waveform segment, then the output waveform will also be characterized by a two-segment piecewise linear approximation, i.e., t'90 == tlv
t' 10 == tl v
=0.1
=0.9' t'50 == tlv =0.5'
and
must be identified. To calculate the times defined earlier.ithe correct
segment of the input waveform representation must be determined (because it is used in the differential equation solutions for phases I and II ). Figure 12.13 shows a flowchart to s
*
calculate the time when the output reaches a specific target value v (e.g., 10%, 50%, or
Sec. 12.6
337
Analytical Delay Models
Voltage (Normalized)
1.0 0.9
Fast Input Case
v*
0.5
Vo
0.1
1\
t
to ttO
tso
~ ttOO tdsar t no
IE
~IE
~I
~IE
Phase II
Phase I
f
Phase III vg
1.0 0.9
Slow Input Case
0.5 v dsat
0.1
Phase I
Phase II s
Phase III
Time (Normalized) Figure 12.12 Phases of switching for the fast (top) and slow (bottom) input cases.
90% of V ) using a multi segment representation of the input waveform, i.e., dd
t == t (v o = v*). A waveform segment is only valid in a region defined as t E [ta, tb] , where ta and tb are different for each waveform segment. Because the differential equation and its solution for each phase is different, the correct phase must be identified to calculate v . o
Note that the flowchart shown in Fig. 12.13 is somewhat simplified. The actual implementation requires additional checks to ensure that the correct waveform segment equation is used in the appropriate analytical formulas. For the slow input case, t
dsat
(time when the transistor switches from saturation to
the linear region) is determined using a bisection search procedure, Le., the time when
338
Chapter 12
Statistical Delay Characterization of CMOS Digital Combinational Circuits
A
Want to calculate t (v0= v*> No
Yes
No
Phase lIs
No
Phase III
1
Phase 1
Figure 12.13 Algorithm for calculating (t ) o d'sat'
V
t == t ( v
0
= v*).
=vdsat is identified. For the fast input case, tdsat =tDO is calculated directly from
the phase II! equation.
The fundamental differential equation describing the discharge process after normalization is (12-36) Depending on the complexity of the function iD(t), this equation may not be analytically solvable. In such cases, simplification of the iD(t) expression may be necessary. Moreover, iterative procedures may be required in some instances. However, once (12-36) is solved, v (t) can be plotted as a function of time. The o
delay td is often defined as td = tl = V vo ddl2 - tl Vin = Vddl2' Referring to Fig. 12.12, the delay is td = t- t 50 . Other delays, such as rise/fall times, can also be calculated.
Sec. 12.6
339
Analytical Delay Models
PHASE I For phase I, the transistor operates in the saturation region and v (t) < 1. Normalizing the g
saturation current expression defined in (12-10) (A is neglected) and applying it to (12-36) gives
dv (t) _ 0 _ = -i (t) dt D
( vg (t) - v to)" 1- v tO
(12-37)
Using the initial conditions t = to and vo(t = 1.0, the solution is o) v (t) = 1.0 o
(v g (t) -v to) " + 1 - (v g (to) -v to) " + 1
--.;;;~------.;;;-----
a (11 + 1)
(1 - v to) "
(12-38)
If the time 1 is to be calculated for a specific v0 (1), then (12-39) 1
vg (t) = ( ex ( 1.0 - v0 (t)) (l - v to),ll
tn + 1) + (vg (to) -vto) 11 + 1)11 + 1 + vto
Once vg (1) is known, v (1) - ~
1 = ....;;g~-
(12-40)
a
where a and ~ are the coefficients of the linear equation describing the waveform segment actually used.
PHASE II, In phase II vg(t) = 1.0, and transistor is in saturation. The current I D(t) = I DO' because Ais
f
being neglected. The differential equation for this phase is obtained in the same manner as for phase I: dv (t) _0_
dt
= -i (t) = -1
(12-41)
D
The solution, for the initial conditions t = t 100' is
vo(t) = vo(t 1oo ) +t1oo-t
(12-42)
If the time 1 is to be calculated for a specific vo (1), then 1 = v0 (t 100) - v0 (1)
PHASE II
+ t 100
(12-43)
s
In phase II , the transistor operates in the linear region and v (t) < 1. After normalization, s
g
the linear region current defined in (12-13) is applied to (12-36) to obtain
340
Chapter 12 Statistical Delay Characterization of CMOS Digital Combinational Circuits
dv ( t ) . - = -I 0
dt
D
=-idsat -( 2 -
(t)
Vdsa t
-
V0
)
V
Vds at
0
(12-44)
The solution for the initial condition t.
in
V0
(t) =
=tdsat is
exp( -~ (v _1_ exp (_! {V(t
V
dsat
Z
g
g (t) -v tO) a )
)-v )a)_J...z-m'afJ.l(t) ds at to 2K J.l (t d )
r,-m/ae-~dr,
(12-45)
sat
where
a=11- m + 1
(12-46)
ti.Ka ( 1 - Vto) 11 z=-----
(12-47)
( V (t) - Vto) a )let) =~g--
(12-48)
2
z
The integral in the denominator of (12-45) has an analytical solution if m/a is an integer. Generally, this will not be true. Therefore, the integral must be evaluated using numerical techniques. The Gauss method [29] is used here because high accuracy can be obtained by using a fifth-order Legendre polynomial approximation, which is defined as
f/ u) 1
dt » 0.2778/(0.1127) + 0.4444/(0.5) + 0.2778/(0.8873)
(12-49)
On most occasions, it is possible to use only a third-order approximation (requiring two f(t) evaluations). As (12-45) indicates, the time 1 for a specific
be calculated analytically. The waveform
V
o
V0
(1) cannot, in general,
(t) in phase II is therefore modeled by a s
quadratic function (using three points), because it is monotonic and well behaved: (12-50) and then, the time 1 is estimated from
J
'i = - b ± b 2 - 4a( c - v0 (1) ) 2a
(12-51)
Sec. 12.6
341
Analytical Delay Models
PHASE III In phase III, the transistor is in the linear region, v (t) = 1, I g
Vdsat
= I DO (neglecting A), and
dsat
= VDO· The linear region current defined in (12-13) is normalized and applied to
(12-36), (12-52) This equation is solved with the initial condition t = t. . For the fast input case, In
(tin == t DO) = vDO' where tDO is determined from (12-43). For the slow input case, ) is determined from (12-51). The solution is V (t. = t V0
100
o In
V
o
(t) =
1
-
[2v DO
--+e
2
vDO
(t-t. )
1
in
Co (tin)
If the time t is to be calculated for a specific
V0
1
2v D
)-1
J
-----
(12-53)
(t), then
- 1- - -1-
'i = vDoln v0 ('i)
2v DO + t In. 211 -----vo(t in) 2v DO
(12-54)
The set of equations introduced here is sufficient for the calculation of delay caused by discharging a capacitor through an NMOS transistor. As previously mentioned, the numerical techniques used inevitably slow down the computation of delay. However, the bisection method and the quadratic modeling of v (t) in phase II are very efficient, so the o
s
penalty in computational speed is relatively small. In addition, the evaluation of the integral is optimized for speed, as shown earlier. The overall speed of delay computation is very high (2-4 orders of magnitude faster than SPICE, depending on the size of the circuit). Although excluding the Amodel parameter introduces some errors, the total statistical error in calculating the delay for a capacitor discharging through an NMOS transistor is usually around 2-3%, which is sufficient for our applications. This methodology for calculating delays of a capacitor discharging through an NMOS transistor will be expanded in the following section to include CMOS inverters.
12.6.4. Inverter The inverter case is different from the discharging capacitor case, because of the charging action of the PMOS transistor during the initial period. The circuit equations were solved in Ref. [22] by modeling the currents by means of a quadratic and the output function v (t) as a local linear function of time. However, it is much simpler to find the o
342
Chapter 12
Statistical Delay Characterization of CMOS Digital Combinational Circuits
switching threshold voltage of the inverter Vg (tth) == V gth [1], [20], [21]. Once the gate voltage (input waveform) V (t) ~ V h' the inverter behaves like a single transistor g
gt
discharging (or charging). Therefore, the equations described in the previous section can be reused for an inverter, with the gate voltage modified as V (t) = 0 for t < t h. The penalty g
t
for this simplification is minor because the current through the PMOS transistor is typically an order of magnitude smaller than the current through the NMOS transistor (discharging case) by the time the output voltage reaches Vddl2. Almost all the current is initially supplied by the PMOS transistor. Eventually, at time tth the currents from both transistors are equal and the output voltage is still V
t»
As dd. tth' the process is dominated more and more by the NMOS transistor. We want to find
the value of the gate voltage V h when the currents are identical, Le., I N(t) = I p(t). dsm dsm ~ Therefore,
I
(Vgth - VtON)'llN = I (Vdd - V gth - VtOp)"P DON V - V DOP V - V dd tON dd tOP
(12-55)
As before, an exact analytical solution of this equation is not possible. An analytical solution was obtained in Ref. [1], by approximating both ll
N
and II p with (l1 N + l1 p ) 12.
This introduces an error of the order of 20-30% in the determination of the switching threshold voltage. For statistical analysis, greater accuracy is necessary and the bisection method is used here to determine V h. As before, (12-40) is used to determine t given gt th Vgth.
A more difficult building block to analyze is a chain of serially connected transistors. These are typically used in CMOS gates, so accurate delay estimation is essential for such cases.
12.6.5. Serially Connected Transistors (NAND/NOR Structure) This section presents a methodology to calculate the delay through a chain of serially connected transistors. This is a difficult case, not well handled by any of the existing methods for statistical analysis [23]. The primary cause for this is the presence of back-bias ( Vsb *- 0 ). The source voltage of each transistor in the chain is no longer the same as the bulk voltage. Consequently, the threshold voltage of each transistor increases and the current decreases. Most simulators sacrifice accuracy by ignoring back-bias in order to reduce complexity. However, statistical accuracy is difficult to attain if back-bias is ignored. In Ref. [22], the circuit equations were solved ignoring the effects of back-bias. In addition, the use of the SPICE Levell model further decreased accuracy. In Ref. [1], a chain was treated as a single composite transistor (see description later). A number of approximations and empirical formulas were used for chains with identical transistors only. However, such approximations are unlikely to be effective in estimating a's (see the next section). Also, the use of empirical formulas is undesirable, because the effectiveness of the
Sec.12.6
343
Analytical Delay Models
formulas is dependent on the process data. Moreover, the procedure in Ref. [1] is not effective if several transistor gates are tied to the same node. In what follows, it is assumed that the race conditions are not present, i.e., only one input node is switching, which means that all transistors connected to this particular node have a voltage V (t), while the remaining transistors have a voltage of V g
dd
applied to their
respective gates (for NMOS). As before, only the NMOS case is illustrated, because the PMOS case is symmetric. Following the approach in Refs. [1] and [20], we replace the chain with an equivalent composite transistor, which exhibits the same I-V curves as the chain being replaced.l! Therefore, if the model parameters of this equivalent composite transistor are known, then a NANDINOR structure can be treated in the same fashion as an inverter. Consider the chain of N serially connected transistors in Fig. 12.14a. Each transistor
Mk has Vgk applied to its gate, Vk to its drain, V + i to its source, and Vb to its bulk. Note that k only the gate voltage of the switching transistor (or several transistors if their gates are connected together) can be manipulated. The gate voltages of the remaining transistors are fixed to V
dd
for an NMOS chain. For the equivalent transistor Me (Fig. 12.14b), the drain
1~,o
Vgo--j
V =V d o
VI
1~,k
~
Me
1~,c
V(N-I)
1~,(N-l)
Vg(N~ M(N_l)
V N (b)
(a)
Figure 12.14 (a) An NMOS chain of length N; (b) the equivalent composite transistor.
11 The
only parasitic capacitances associated with the composite transistor are the C d and Cdb capacitances of the transistor connected to the output node. g
344
Chapter 12
Statistical Delay Characterization of CMOS Digital Combinational Circuits
and source voltages are defined as Vd == Vo and Vs == VN' respectively. The gate of the
composite transistor must have exactly the same waveform V applied as the gate of the g
switching transistor( s) in the chain. The bulk of the composite transistor is at the same potential as the bulk of all the transistors in the chain. The calculation of the delay through a chain of serially connected transistors consists of the following steps: 1. Extract the composite transistor model parameters. Eight sets of the voltages V , g
V ' V , and Vb are selected according to the procedure outlined in section 12.5.1 s
d
and the currents I d 1 - I d8 from Fig. 12.6 are determined. 2. Calculate the composite (12-16)-(12-29).
transistor
model parameters
using formulas
3. Calculate the delays using the procedures described in section 12.6.4 and section 12.6.3. The composite transistor model parameters determined in step 2 are used in all the formulas from these sections. As previously indicated, the only difficulty is the estimation of the currents corresponding to the selected voltages V , V , V , and of the composite transistor. These currents can be g
s
d
calculated from SPICE (or measured). However, this is not very efficient and will significantly affect the speed of analysis. A better method is to approximate the solution to the dc circuit equations (based on the transistor model developed in Ref. [1]) and then estimate the currents based on this approximation. Note that the estimation of the composite transistor model parameters is performed dynamically during the delay calculation, instead of during the presimulation stage. In
what
follows,
a procedure
is
described
to
calculate
the
current
I D, C == I D, 0 = ... = I D, (N _ 1) through a chain of length N. An analytical solution is difficult to obtain for such a case, so a numerical technique (bisection search) is used. To
calculate the current, the node voltages Vl' ...' V(N-l) have to be determined. Fortunately, these voltages are not independent of each other. If the node voltage V(N_l) is known, then the remaining node voltages can be directly calculated, as shown in the following. Algorithm 1: Determination of the current ID,C in a MOS transistor chain of length N. 1. Initialize. In reference to Fig. 12.14a, select the voltages V 0' VN' Vb' and V g according to the extraction procedure defined in section 12.5.1. The voltages VgO' .•. , Vg (N -1) are also known (either fixed to Vdd or set to Vg ). The node
voltages VI' ... , V (N -1) are unknown along with the current I D, C·
Sec. 12.6
345
Analytical Delay Models
2. Use bisection search to provide an estimate of the drain current 1D, C == 1D, k · a. Loop: for k = N - 1 to k = 0: i. If
l
Mk
transistor Vds , k
is
in
~ Vd sa t, k == K (Vg s, k -
1-[
Vds, k -- A k
"
saturation,
Vth , k) m ), calculate
Id, k"
11k
- 1
i.e.,
1D, k ~ Idsat, k
Vds, k : From (12-10),
J
(12-56)
Bk(Vgs,k- Vth,k)
If transistor Mk is in the linear region, (12-13) can be rewritten as
where I'dsat, k == Bk (Vg S, k -
Vds, k : Vds, k» calculate Vk
Vth, k) Tlk.
Eq. (12-57) is then analytically
solved to estimate ii. From
(see Fig. 12.14a): (12-58)
where Vk+1 is the source voltage of transistor Mk, which was calculated previously as the drain voltage of the transistor M k+1. b. The last node voltage estimated in step 2.a.ii is
Vo . The actual value of Vois
known, as it was selected by the user. Calculate the objective function "
"
12
!(V(N-1)) = Vo- Vo·
Stop if !(V(N-1)) ~o. Return the estimated value of the current
3.
ID,c
calculated in step 2.a. Else go to 2. In this algorithm, the parameter
Ais included in the transistor equations. Otherwise there
would be no dependence of the current on the drain-to-source voltage for a transistor in saturation, so Vdsk would be undetermined. For the transistors in the linear region, ignoring
A changes the cubic equation in (12-57) to a quadratic equation. Because this does not 12
Observe
that
the
bisection
procedure
of
step
2
actually
solves
f(V (N-l)) = Vo- Vo(V(N-l)) = 0 relative to V(N-l) , where Vo is known.
the
equation
346
Chapter 12 Statistical DelayCharacterization of CMOS Digital Combinational Circuits
increase efficiency significantly, the cubic equation is retained. This algorithm is able to estimate the node voltages (and current) very accurately, with errors usually less than I %, relative to SPICE. The bisection search algorithm is used for high efficiency, and is able to obtain the node voltages within a few iterations. Every iteration requires N evaluations of the transistor model equations (12-10)-( 12-15), which is relatively fast. It should be pointed out that in order to calculate the currents it is possible to use other numerical approaches than the one described earlier. Several of them were actually investigated; they showed similar accuracies, but were not as efficient as the method we used. This methodology allows the determination of currents for specific Vg , Vd, Vs' and Vb of the equivalent composite transistor. Once the nodal voltages are known for specific combinations of gate, source, drain, and bulk voltages, the current can be estimated for each combination. Consequently, the composite transistor model parameters are estimated using formulas (12-16)-(12-29) from section 12.5.1. Finally, C-code is generated for delays along the user-defined paths. The methodology presented earlier to estimate the output waveforms is tested on four examples in the following section.
12.7. EXAMPLES This section shows how various basic building blocks can be statistically characterized using the methodology previously presented.
EXAMPLE 12.1-STATISTICAL DELAY MODEL OF A CMOS INVERTER The methodology was initially tested for a CMOS inverter (Fig. 12.15), with the widths and lengths of both NMOS and PMOS transistors set arbitrarily to 8 Jl and 3 Jl, respectively, and an output capacitance set to I pF. The input waveform (ramp) had a slope of 0.5 V/ns for 0 < t < 10 ns, otherwise the slope was zero. As suggested in Ref. [26], the independent (basic) noise parameters were used to generate the remaining SPICE level 2 model parameters based on the regression models created in Ref. [26]. Table 12"3 shows the set
e
Vdd
D Mean
v.: 0
Actual
Model
...ErroL.
"t
11.13 ns 11.32 ns
1.7 %
cr"t
0.57 ns 0.60 ns
5.3 %
v.
C=lpF t
Figure 12.15 Example 12.1: Inverter model accuracy.
(ns)
347
Sec. 12.7 Examples
Table 12-3 Noise Parameters TOX
Mn
LlWn
Nsub,n
Mn
LlWn
~,p
Nsub,p
Vdd
(A)
(urn)
(um)
(m ')
(urn)
(pm)
(urn)
(rn-3)
(V)
e
318
0.348
0.4
1.44e16
0.285
0.4
0.678
6.02e16
5.0
as
15%
15%
20%
15%
15%
20%
15%
15%
15%
of the e parameters. One hundred random Monte-Carlo samples were generated using the data from Table 12-3. The output waveform from the model was compared with the actual waveform. Figure 12.15 shows the estimated time t when Vo (t) = Vdd/2 using the proposed model and SPICE3. The mean and standard deviation errors of 1.7% and 5.3%, respectively, are very reasonable. For other sets of widths, lengths, capacitances, and input waveforms, the model showed similar accuracy. Because the circuit size is small, about 100 times reduction in analysis time relative to SPICE was obtained. 13 EXAMPLE 12.2-STATISTICAL DELAY MODEL OF A NAND GATE An experiment was performed for a two-input NAND gate (Fig. 12.16a) and a five-input NAND gate (Fig. 12.16b). In both cases, the gate voltage was applied to the NMOS transistor closest to the output node, while V was applied to the remaining NMOS dd transistors. One hundred random Monte-Carlo samples were generated using the noise parameters specified in Table 12-3. All the lengths were again set to 3 Jl, while the widths of the NMOS and PMOS transistors were set to 12 Jl and 8 u, respectively. The output capacitance and the input waveform were defined as in the inverter example. The means and standard deviations estimated from the model are again compared to the actual means and standard deviation calculated from SPICE3 in Fig. 12.16a and Fig. 12.16b. The statistical accuracy of the model is again very high (about 5% error in estimating standard deviations). The model shows similar accuracy for different sets of widths, lengths, and input waveforms. For this example, the reduction in analysis times was approximately 400 times, relative to SPICE. Next, a more complex example is shown containing loading inverters instead of large loading capacitances. EXAMPLE 12.3-STATISTICAL DELAY MODEL OF A 2-81T ADDER Our statistical model was applied to a 2-bit adder circuit (Fig. 12.17), consisting of 18 two-input NAND gates (therefore, NFETs are connected in short chains), with each output node loaded with an inverter, so the accuracy of the parasitic capacitance models is critical. The sizes of all transistors were identical: W i / L i = 8Jl/3Jl. The selected critical path starts from the input carry node and ends at the output carry node of the adder. One operand of the adder was set to 0 and the other to 3. As before, 100 random Monte-Carlo samples were generated. The output waveform from SPICE and from the model were compared in 13 The time required for generating and compiling the C-code (a few seconds) is not included in this
comparison.
348
Chapter 12
V
dd
Statistical Delay Characterization of CMOS Digital Combinational Circuits
o
Actual
r
0"
t
Model
~
0.480s 0.510s
6.8 %
v.
C=lpF
v. t---___. I
I I
"t
Vout t (ns)
(b) Figure 12.16 Example 12.2: Delay models for NAND gates: (a) two-input NAND gate; (b) five-input NAND gate.
the same fashion as was done for the inverter and the NAND gates. In Ref. [23], RC models (modified for statistical analysis) were used to characterize this circuit. Although these RC models showed good accuracy in estimating the means of the delay , the error in estimating a d I approached 30-40%, even with an exten sive nominal point tuning. Figure 12.17 e ay
shows the means and standard deviations from the proposed models and from SPICE3
based on the same 100 Monte-Carlo samples. The results show very close agreement with
Sec. 12.7
349
Examples
Error
lIi...... .
t
l
t_ _~ :;:~
0.56 ns 0.60 ns
Actual
III
Mean 13.35 ns ~ : ; ; . _1fJ!t:lt,tYI 14.02 ns 5.02 % 0"" t
o
Model
A-I B·1
I I I I I I I
Ci_1 -,-- - - - - - - - - - ...J
7.14 %
C I.
~ S. I I I
I
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --_...!
Figure 12.17 Example 12.3: Delay mode for a 2-bit adder.
SPICE, with an error of about 7% in estimating the standard deviation. The analysis was more than 600 times faster than using SPICE. Note that the nominal point tuning was not performed, even though the capacitance model is based on an average capacitance . Initially, simpler models were tried using approximations instead of some of the iterative schemes proposed, but even with nominal point tuning, the statistical accuracy was low. EXAMPLE 12.4-STATISTICAL DELAY MODEL OF A 5 x 5 BAUGH-WOOLEY MULTIPLIER
In order to test the accuracy of the models for a large circuit, a 5 x 5 Baugh-Wooley multiplier (Fig. 12.18) was selected as an example . The circuit contains approximately 1,200 transistors . It has a very regular structure with l-bit full adders arranged in the form of rows and columns. The size of the circuit prevented the determination of the standard deviation from SPICE, because of the long simulation times involved. In fact, SPICE3 ran into convergence problems and could not simulate this circuit. Therefore , HSPICE was used to determine the delay from node a b0 to the output node P9' Using a modified version 3
of the program rc_ko [23], the worst-case path was generated between these nodes. Because it was not possible to determine o from the simulator, the accuracy of the model was tested on three points only. The nominal point showed very good accuracy (6.5%) when estimating the time 'i when the output waveform reaches Vd/2 . The two data points from the Monte Carlo test set from the previous example (adder) that showed the smallest and the largest values of 'i were assumed to be critical for this example as well, because both use a very similar structure. The errors at these "estimated" worst cases also showed
350
Chapter 12 Statistical DelayCharacterization of CMOS Digital Combinational Circuits
F=XOR(X,Y) 3
(a)
C.
1-"""""""""-----------4l--~~
Ai
4
s·
1 ~---------=--
Bi
(b) LEGEND
Error for Path from a b0 to Pg 3
Nominal - 6.5% Max. 1(est) - 9.9% Min. ~ (est) - 11.1 %
~o
Figure 12.18 Example 12.4:The 5 x 5 Baugh-Wooley multiplier: (a) the XOR gate; (b) the full adder (~).
good modeling accuracy (9.9% and 11.1%), especially considering that no nominal point tuning had been performed. In this example, the systematic errors from the capacitance model caused a systematic increase in the estimated worst-case model errors (from about 6% at the output of the first full adder B to a maximum of 11% at the node P9) from one
Sec. 12.8 Conclusions
351
node to the next in the signal path selected. Because the errors are still acceptable, no tuning was performed. For much larger circuits, local tuning may have to be performed for some subcircuits (for example, for the full adder), to increase statistical accuracy. For this example, the speed of analysis was> 6,000 times relative to SPICE. Note that the proposed scheme can model significantly larger circuits than this, but there is really no way to check statistical model accuracy for such circuits (SPICE is too slow and runs into convergence problems). In Fig. 12.18b, the internal structure of the full adder used in this example is illustrated. The RC modeling strategy [10] assumed the worst-case path starting from node 1, going through node 6, and ending at node 5. However, for some combinations of the widths and lengths and the input waveforms, a race condition was created when the transition at node 8 started before the transition at node 7 was complete. This phenomenon was entirely missed by the RC modeling strategy, but was correctly detected by the proposed methodology. The approach described in this chapter presents unique, new statistical delay models with such a high level of accuracy. Previously, that level of accuracy has been achieved for the nominal analysis only.
12.8. CONCLUSIONS In this chapter, an efficient methodology was presented to statistically characterize signal delays of CMOS VLSI circuits. The effects of process-related noise parameters, geometric parameters, and input waveform shape are modeled using advanced analytical delay formulas obtained by explicitly solving appropriate circuit equations. Suitable approximations were made in order to reduce complexity. In such cases, the resulting equations were parameterized with additional tuning parameters. Simple iterative techniques were used where analytical solutions were not possible. An accurate, but simple, semi-empirical MOS transistor model was combined with an efficient "black-box" interpolation scheme to link the nonphysical transistor model parameters with the noise and geometric parameters. The resulting hybrid analytical/iterative models were dependent on the geometrical (widths and lengths) and noise parameters indirectly through the transistor and capacitor model parameters. The analytical models of the delay of basic building blocks are combined together for analysis of complex combinational circuits. To increase the speed of analysis, the C-code was generated for specific critical signal paths. As can be seen from the examples, the influence of the "noise" parameters was modeled very well. Even though the Level 2 model SPICE3 was used as a reference in the examples, the methodology is not affected if a more accurate reference simulator is substituted (e.g., using the BSIM models). The resulting models increase the speed of analysis by 2-4 orders of magnitude relative to SPICE. Due to this high efficiency, statistical delay characterization of large combinational VLSI circuits is possible. It can be used for manufacturing yield optimization, delay variability reduction, and in other statistical circuit design tools.
352
Chapter 12 Statistical DelayCharacterization of CMOS Digital Combinational Circuits
References [1]
[2]
[3] [4] [5]
[6]
[7]
[8] [9] [10] [11]
[12] [13]
[14] [15] [16] [17]
[18]
T. Sakurai and A. R. Newton, "A simple MOSFET model for circuit analysis and its application to CMOS gate delay analysis and series-connected MOSFET structure," Memo UCBIERL M90/19, University of California, Berkeley, March 1990. R. M. Biernacki and M. A. Styblinski, "Efficient performance function interpolation scheme and its application to statistical circuit design," Int. J. Circuit Theory Appl., vol. 19, pp. 403-422, 1991. A. R. Newton, "The simulation of large scale integrated circuits," Ph.D. thesis, University of California, Berkeley, July 1978. J. K. White and A. Sangiovanni-Vincentelli, Relaxation Techniques for the Simulation ofVLSI Circuits. Boston: Kluwer Academic, 1987. J. Benkowski and A. Strojwas, "A new approach to hierarchical and statistical timing simulations," IEEE Trans. Computer-Aided Design, vol. CAD-6, no. 6, pp. 1040-1052, November 1987. M. A. Styblinski and S. A. Aftab, "Combination of interpolation and self organizing approximation technique-A new approach to circuit performance modeling," IEEE Trans. Computer-Aided Design, vol. 12, no. 11, pp. 1775-1785, November 1993. A. Patel, W. Bridgewater, and R. Pokala, "NEWTON: Logic simulation with circuit simulation accuracy for ASIC design," Proc. IEEE Custom Integrated Circuits Conf., Portland, OR, 1986. S. Nassif and S. W. Director, "WASIM: A waveform based simulator for VLSI's," Proc. IEEEInt. Conf. Computer-Aided Design, Santa Clara, CA, 1985. R. E. Bryant, "MOSSIM: A switch-level simulator for MOS LSI," Proc. 18thDesign Automation Conf., Nashville, TN, pp. 786-790, 1981. A. C. Deng, "Piecewise-linear timing delay modeling for CMOS Circuits," IEEE Trans. Circuits Syst., vol. CAS-35, pp. 1330-1334, October 1988. A. C. Deng and Y. C. Shiau, "Generic linear RC delay modeling for digital CMOS circuits," IEEETrans. Computer-Aided Design, vol. 9, no. 4, pp. 367-376, November 1990. C. J. Terman, "RSIM-A logic-level timing simulator," Proc. IEEE Conf. Computer Design, New York, NY, 1983. B. Hoppe, G. Neuendorf, D. Schmitt-Landsield, and W. Specks, "Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation," IEEE Trans. Computer-Aided Design, vol. 9, no. 3, pp. 236-247, March 1990. M. A. Horowitz, "Timing models for MOS circuits," Ph.D. thesis, Stanford University, December 1983. J. Rubinstein, P. Penfield, and M. Horowitz, "Signal delays in RC tree networks," IEEE Trans. Computer-Aided Design, vol. CAD-2, no. 3, pp. 202-211, July 1983. T.-M. Lin and C.A. Mead, "Signal delay in general RC networks," IEEE Trans. Computer-Aided Design, vol. CAD-3, no. 4, pp. 331-349, October 1984. M. A. Styblinski, X. Sun, K. M. Opalska, and L. J. Opalski, "An efficient symbolic approach to time delay optimization of CMOS circuits," Proc. IEEE Int. Symp. Circuits Syst., Singapore, May 1991. J. F. Tuan, "Mixed-mode analog/digital simulator of MOS circuits," Ph.D. thesis, Texas A&M University, December 1990.
References
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[19] W. Elmore, "The transient response of damped linear network with particular regard to wideband amplifiers," J. Appl. Phys., vol. 19, pp. 55-63, October 1948. [20] M. Shoji, CMOS Digital Circuit Technology. Englewood Cliffs, NJ: Prentice Hall, 1988. [21] J. P. Uyemura, Circuit Design for CMOS VLSI. Boston: Kluwer Academic, 1992. [22] V. B. Rao, D. V. Overhauser, T. N. Trick, and I. N. Haji, Switch-Level Timing Simulation ofMOS VLSI Circuits. Boston: Kluwer Academic, 1989. [23] K. Opalski, L. J. Opalski, and M. A. Styblinski, "Symbolic modeling of VLSI CMOS circuits for statistical optimization," Tech. Rep. LIDS #92-7, Texas A&M University, September 1992. [24] L. Brocco, S. McCormick, and J. Allen, "Macromodeling CMOS circuits for timing simulation," IEEE Trans. Computer-Aided Design, vol. 7, no. 12, pp. 1237-1249, December 1988. [25] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective. Reading, MA: Addison-Wesley, 1985. [26] J. Chen and M. A. Styblinski, "A systematic approach to statistical modeling and its applications to CMOS circuits," Proc. IEEE Int. Symp. Circuits Syst., Chicago, IL, May 1993. [27] A. C. Deng, "On network partitioning algorithms for large-scale CMOS circuits," IEEE Trans. Circuits Syst., pp. 294-299, February 1989. [28] S. A. Aftab, "The DELAY modeling system-A user's guide," Technical Report LIDS #93-11, Texas A&M University, December 1993. [29] W. E. Milne, Numerical Calculus. Princeton, NJ: Princeton University Press, 1949.
13 Stefano Manetti D.I.F.A. Universita della Basilicata Potenza, Italy
Analog Testability and Fault Diagnosis Using Symbolic Analysis
Antonino Liberatore D.I.E. Universita diFirenze Firenze, Italy
13.1. INTRODUCTION Testing and fault diagnosis fulfill a vital need for the electronics industry. Testing an integrated circuit (IC) is an essential part of its overall design and fabrication process, which is going to be more critical with technology improvements and with the coexistence on a chip of analog and digital components. The faults in analog circuits can show themselves as a change of some parameters in a continuous range of values. This makes the testing and fault diagnosis of analog and mixed analog-digital systems very difficult compared to digital-only systems. While testing and fault diagnosis of digital ICs has been successfully developed to the point that it can be automated, for analog (or mixed digital-analog) ICs, these tasks are far from being automated and the engineer's intuition is still the most powerful tool used in the industry. In general, while digital tests are normally generated automatically even for very large systems, analog tests are hand-crafted and take a longer time to develop than those for digital. In this class of problems, the symbolic approach can be very useful to develop efficient testing methodologies and design for testability tools. As several methods and techniques have been proposed in the past to face the problem of analog fault diagnosis, let us start this chapter with a brief discussion of these topics, so that it will be clear what our theoretical approach is to these problems. Problems concerning analog fault diagnosis do not fall into the two main topics of circuit theory, namely analysis and synthesis. The aim of network analysis is the determination of the desired input/output (110) relations, starting from a given circuit structure and component values, while the network synthesis is the inverse problem of analysis.
354
Sec. 13.1
355
Introduction
The fault diagnosis can be viewed as a third problem, that is, given a circuit structure and some I/O relations, we want to obtain the related component values (Fig. 13.1). Then, from a theoretical point of view, the fault diagnosis can be considered as a parameter identification problem. In practice, however, in a fault diagnosis problem, it is not necessary to obtain precise values of all components. Usually it is sufficient to determine what components are out of a predefined tolerance band, that is, what components give rise to a fault condition. In this kind of problem, the symbolic approach is a natural choice, because an I/O relation that is independent of component values, or in which the component values are the unknowns, is properly represented by a symbolic I/O relation . In fault diagnosis, an essential point is the concept of testability , which gives information about the solvability of the problem. In other words, given a circuit structure, given some I/O relations to be measured, given some unknown component values, testability allows us to establish , a priori, if the problem is uniquely solvable or not. If not, we must add other I/O relation measurements, that is, other test points in the circuit, or we must accept a reduced number of unknown parameters. Testability information is essential either to designers who must know which test points to make accessible for testing or to test engineers who must plan tests and know how many and what parameters can be uniquely isolated by these tests. Section 13.2 of this chapter is dedicated to testability. In particular, after a discussion on the testability concept and definition, the algorithms, both numerical and
Circuit Structu re
1/0 Relations
Component Values
R j = 10 Kohm Cj = 5 pF Rk = 15 Kohm Lm= 3.3 mH gn= 3 ohm
Figure 13.1 The fault diagnosis problem.
356
Chapter 13
Analog Testability and Fault Diagnosis Using Symbolic Analysis
symbolic, used for testability computation are presented. The other two sections of the chapter introduce the use of symbolic methods for the fault diagnosis of analog circuits. Section 13.3 discusses the fault diagnosis of linear circuits using frequency- or time-domain measurements, while section 13.4 introduces an approach to the fault diagnosis of nonlinear circuits based on the generation of dedicated simulators.
13.2. THE TESTABILITY CONCEPT Selecting an optimum set of measurements, and then of test points, to detect or locate faults is an essential problem in fault diagnosis applications. To perform this task, it is necessary to have a quantitative index to compare different solutions. For analog circuits, the testability measure concept meets this requirement. Testability is strictly tied to the concept of network-element-value-solvability, which was first introduced by Berkowitz [1]. Successively, a very useful testability measure was introduced by Saeks et al. [2]-[5]. Although other testability definitions were introduced (see, e.g., Refs. [6]-[8]), the Saeks method is still the most widely used [9]-[12] because it provides a well-defined quantitative measure of testability. In fact, this definition is a measure of solvability of the nonlinear fault diagnosis equations and indicates the ambiguity that will result from an attempt to solve. such equations in a neighborhood of almost any failure. Algorithms for evaluating this kind of testability measure have been developed by the authors in the past years, using a numerical approach [13], [14]. These algorithms were utilized for the implementation of programs for analog network testability calculation. However, these methods were suitable only for networks of moderate size, because of the inevitable round-off errors introduced by numerical algorithms, which render the obtained testability only an estimate. To this end, we have proposed the use of the symbolic approach to overcome this difficulty through an efficient manipulation of algebraic expressions [15].
13.2.1. Testability Based on the Multifrequency Approach The analog circuit under test can be considered as a multiple-input multiple-output linear time-invariant system. Using the modified nodal analysis (MNA), the circuit can be described using the following equation:
A (p, s) .
~ (p, S)]
le (P, s)
=
rx (S)]
l0
(13-1)
where
P = ~l e» ...,Pmr
is the vector of the parameters that are potentially faulty,
assuming that all faults are expressed as parameter variations, without influencing the circuit topology; x (s) =
[Xl (s) Xz (s)
...
Xn/S)]' is the input vector;
Atp,s) is the characteristic matrix, conformable to the vectors;
Sec. 13.2
357
The Testability Concept
... Y (P, ny
S)r is the vectorof the outputtest points
e (P, s) = [e 1 (P, s) e2 (P, s) .. , e (P, ne
S)r is the vector of the inaccessible
1Yl (P, s) Y2 (P, s) (voltages an~or currents); and y (P, s) =
voltage nodes and/orcurrents of voltage sourcesand of elementsthat do not have an admittancerepresentation. From the superposition principle, the following transfer functions may be thus defined:
U)
hi
. . det A ij (P, s)
(p, s) = ( 1)1+1
det A (P, s)
i = 1, ... , ny
j
= 1, ... , nx
(13-2)
where A ij is the minor of the matrix A (p, s). We can find the following network functions, which are the fault diagnosis equationsof the circuit under test:
u)
h. I
where
U)
=
v,
(P, s)
i = 1, ... , ny
x (s) j
j = 1, ... , nx
Y?) (P, s) is the ith output due to the contributionof input
Xj
(13-3)
only.
Let (s) = ( rk (s)) be the Jacobian matrix associated with the algebraic diagnosis Eqs. (13-2), evaluated at a generic frequency s and at a nominal value Po of the parameters. From (13-2), we obtain for rk (s): i+j
rk(s) = (-1)
a
(det Aij(P,s)) apk det A (P,s)
(13-4) p =Po
where r = (i - j) nx +j . The matrix (s) is rational in s and, from (13-4), we get that the functions (det A (P, s) 21p = p rk (s) are polynomialfunctions in s. o
As shownin Refs. [2]-[5], the testabilitymeasure T of the analogsystem,evaluated in a suitable neighborhood of the nominal value Po' is given by the maximum number of linearly independentcolumns of (s): T = rankcol( (s) )
(13-5)
13.2.2. Algorithms for Testability Evaluation A numerical algorithm for the evaluation of the previously defined testability measure, that is, for the evaluation of the maximum number of linearly independent columns of the matrix <1>, can be based on the following considerations [13], [14].
358
Chapter 13 Analog Testability and Fault Diagnosis Using Symbolic Analysis
13.2.2.1. Numerical Algorithm The matrix can be expressed in the form 1 (p s) = P(s) , (det A (p, s) ) 2
(13..6)
where P(s) is a polynomial matrix in which the (r, k)th element is a polynomial in s of degree drk . An upper estimate d for the degree of such a polynomial can easily be carried out on the basis of the type of components present in the circuit under test. Indeed, such degrees cannot be larger than twice the number of components dependent on the frequency that appears in the network under consideration [14]. The testability measure T, i.e., the number of linearly independent columns of the Jacobian matrix, coincides with the number of linearly independent columns of the polynomial matrix P(s). The proposed algorithm was based on the representation of the polynomials of P(s) as a linear combination of suitable orthogonal polynomials; in fact, it was proved [14] that
T = rank (C)
(13..7)
where C is the matrix composed of the coefficients obtained by expanding the polynomials of P(s) into a series of orthogonal polynomials. This method provides a valid means for the numerical computation of testability. However, the numerical programs obtained in this way are of a very high computational complexity. First, the calculation of the coefficients of the polynomials Prk requires the knowledge of the values assumed by the polynomials in at least d + 1 points, where d is the degree of the polynomial; this degree must be a priori estimated, on the basis of the type of the components present in the circuit under test. Therefore, for large circuits, the numerical calculation of a considerable number of circuit sensitivities is required. Furthermore, the program must take into account the inevitable round..off errors introduced by the algorithm used for sensitivity computation. This problem was partially overcome by using two different polynomial expansions (for example, Stirling and Chebycheff [14]). Nevertheless, for large circuits these errors could have a magnitude so large that the obtained testability values must be considered only as an estimate of the true testability.
13.2.2.2. Symbolic Algorithm These drawbacks are completely overcome if we are able to determine the polynomial matrix directly in a completely symbolic form. This new approach is based on the following theorem:
THEOREM 13.1 Let P(s) be the following polynomial matrix: Pll (s) P12 (s) ... Plm (s)
P(s) =
(13..8)
Sec. 13.2
359
The Testability Concept
where (13-9) and d
= max{ de gp l l ' degp12' ... , degpZm}.
Let PI' .. .Pm be the m column-vectors of the matrix P(s). Then the maximum number of linearly independent columns of the matrix P(s) is equal to the rank of the matrix B (which has (d + 1) 1rows and m columns):
B=
Le., rankcol (P) = rank (B)
(13-10)
(13-11)
We note that the numerical matrix B is composed of (d + 1) submatrices, of order
1x m , whose elements are the coefficients of the polynomials Prk (s).
The proof of this theorem can be found in Ref. [15]. It is worth pointing out that this approach holds in a suitable neighborhood of the nominal value Po of the parameters, and so it is valid for faults relative to parameters' variations. Faults such as "open" and "short," which influence the circuit topology, are not considered. In other words, this approach is suitable for parametric faults and not for catastrophic faults. Thus in order to determine the testability measure T of the circuit under consideration, it is sufficient to evaluate the rank of the numerical matrix B, composed of the polynomial coefficients b rk' Nevertheless, in numerical testability computation, the previous result is not easily applicable because the computation of coefficients b rk by means of classical numerical analysis algorithms is very difficult and may cause considerable drawbacks, particularly for large networks. The result is very useful if we generate b rk coefficients in completely symbolic form. In this case, they are functions of circuit parameters, to which we can assign arbitrary values [3]. It is worth pointing out that the matrix B is, essentially, a sensitivity matrix of the circuit under test, and that, starting from a fully symbolic generation of the network
360
Chapter13 AnalogTestability and Fault Diagnosis Using Symbolic Analysis
functions corresponding to the selected fault diagnosis equations, it is very easy to obtain symbolic sensitivity functions [16]-[18]. This new symbolic approach for the testability evaluation has been utilized for the development of the program SAPTES [15], which is based on the previous theorem and is devoted to circuit testability computation. SAPTES operations start with a symbolic analysis of the circuit under test. The network functions obtained are used to compute first the network sensitivity functions, and then the polynomials required in order to determine the testability. These polynomials are obtained in symbolic form with respect only to the complex frequency s, by assigning to circuit components arbitrary values. In fact, it was shown [2]-[5] that the circuit testability is independent of component values. The computation of the number of linearly independent columns of the polynomial matrix P(s) is then performed by the method previously presented. That is, this number is computed as the numerical rank of the matrix of the polynomial coefficients. In this case, these coefficients are those of the canonical forms. It is worth pointing out that such coefficients are not affected by any computational errors; moreover, the coefficient matrix could be composed only of integer numerical values by a suitable choice of arbitrary component values. The numerical rank of this matrix is obtained by classical triangularization methods. The fundamental steps followed by SAPTES are shown in the block diagram of Fig. 13.2. The program runs on MS-DOS personal computers and requires an ASCII file describing the circuit under test. The form of this file is similar to that required by the SPICE program: each device of the circuit is represented in the input file by one line. A
Generation of fau~ diagnosis equations in completely symbolic form Generation of sensitiY~y functions in symbolic form with respect tothe complex frequency Generation ofpolynomial matrix P(s), and numerical coefficients matrix B
Figure 13.2 Fundamental steps of the program SAPTES.
Sec. 13.2 The Testability Concept
361
particular command, included in the input file, must be used to communicate to the program the list of test points (voltages or currents). The program yields an output file that contains, essentially, the following information: • • • •
initial list of test points; testability value obtained; list of test points effectively used; list of not testable components.
It must be noted that the information given by SAPTES is not limited only to the obtained testability value. In fact, if a maximum of testability is not attainable, the program gives a possible set of not testable components.' Furthermore, if some test points of the initial list are not necessary for the obtained testability value, they are not present in the list of test points used. This important additional information is obtained by the program during the application of the triangularization method used to find the numerical rank. In fact, in this procedure a subset of rows of the matrix B is selected and a group of rows of B corresponds to each test point. Then the test points that correspond to rows not utilized during the triangularization procedure are redundant; in fact, their elimination does not change the obtained testability value. Furthermore, each column of B corresponds to a circuit component; then the columns not used during the triangularization procedure correspond to a subset of not testable components.
EXAMPLE 13.1 Let us consider an example of SAPTES application. The circuit is shown in Fig. 13.3. In Fig. 13.4, two examples of output files are reported. In the first case, the initial list of test points is not sufficient to attain a maximum of testability, and a list of not testable components is given. This information means that, for the given circuit with the given set of test points, the testable components can be identified, if we suppose to know the values of the not testable components. In the second case, the obtained testability value is maximum and the test point I_OA3, corresponding to the output current of the op-amp OA3, has been eliminated by the test points list; that is, such output is redundant. The program SAPTES has been utilized to realize the expert system ESTEPS (Expert System for Test Point Selection), devoted to the automatic selection of test points in analog linear circuits [19], [20].
13.2.2.3. Further Developments Recently, the methodology for circuit testability computation has been further developed, leading to a new and simpler procedure [21], [22]. In order to present the new methodology, for the sake of simplicity, let us consider a circuit with only one test point. In this case, we have only one fault diagnosis equation, which can be written in the form
1 It must be noted that the partition between testable and not testable components is, in general, not
unique. Then, several sets of not testable components may exist.
362
Chapter 13
Analog Testability and Fault Diagnosis Using Symbolic Analysis
G3 Gl 2
Cl
G8 6
5
OA3
+
Figure 13.3 Vogel filter. VOGEL FILTER (A) Components: (Cl C2 Gl G2 G3 G4 G5 G6 G7 G8) Test points: (3 5 7) Testability value: 6/10 Test points utilized: (3 5 7) Not testable components: (G4 G5 G6 G8) VOGEL FILTER (8) Components: (C1 C2 G1 G2 G3 G4 G5 G6 G7 G8) Test points: (3 5 7 I OA1 I OA2 I OA3) Testability value: 10710 Test points utilized: (3 5 7 I_OA1 I_OA2)
Figure 13.4 Two examples of SAPTES output file. n
=N(P,s) D (P, s)
h (s,p) = m-l
L bj(P) s.i+
(13-12)
Sm
j=o
wherep = [PI' Pl' ... , P ql t is the vectorof potentially faulty parameters, and nand mare the degrees of, respectively, the numerator and the denominator. The Jacobian matrix ep can be written as
Sec. 13.2
The Testability Concept
363
cI>(p,s)
(13-13)
and the polynomial matrix P as
(13-14)
(13-15)
As shown in the previous section, the testability coincides with the rank of the matrix B of the coefficients of the polynomials of P. In the present case, such a matrix is made up of m + n + 1 rows (that is, the number of coefficients in h) and q columns (the number of unknown parameters). Let us consider, now, a new matrix, B c' of order (m + n + 1) x d, made up of the derivatives of the coefficients of h with respect to the unknown parameters
aa n apl
aa n _ l apl
Bc
=
aa o apl
ab m _ l apl
abo apl
aa n ap2 aa n _ l ap2
aa n ap q aa n _ l ap q
aao ap2 ab m _ l ap2
aao ap q
<: ap
abo ap2
abo ap q
(13-16)
q
It is easy to show that the new matrix Bc has the same rank of the previous matrix B. In fact, from (13-15) and (13-16), it is evident that the rows of Bc are a linear combination of the rows of B. Then the testability measure can be computed as the rank of
s;
If the circuit under test is a multiple-input multiple-output system, that is, if we have more than one test point, we can easily obtain the same result.
364
Chapter 13 Analog Testability and Fault Diagnosis Using Symbolic Analysis
This is a noteworthy simplification from a computational point of view,becausethe derivatives of the coefficients of h are simplerto compute withrespectto the derivatives of
h.
Furthermore, from this new procedure, it is possible to derive some necessary conditions for a testable circuit (i.e., a circuit with maximum of testability) that are very simpleto apply. Thesenecessary conditions are simplybasedon the consideration that,for a maximum of testability, the matrix Be must have a rank equal to the numberof unknown parameters, that is, equal to the numberofcolumns. Then, for a given circuit with a set of given test points, we have the following first necessary condition: Necessary condition for maximum of testability: the number of coefficients that are present in the fault diagnosis equations must be equal to or greater than the number of unknown parameters.
Another interesting necessary condition follows from the consideration that the numberof coefficients depends on the orderof the network. In fact, the maximum number of coefficients of a network function is 2N + 1, if the network is of order N. From this consideration, and from the previous necessary condition, it is possible to determine the minimum number of fault diagnosis equations, and then of test points, necessary for maximum of testability. Or, given the numberof test points,it is possibleto determine the maximum numberof unknown parameters for a maximum of testability. For the singletest point case, we have Mp
= 2N+ 1
(13-17)
where Mp is the maximum numberof unknown parameters, that is, the maximum number of parameters that it is possible to determine with the given fault diagnosis equation. For the multiple test point case, because all the fault diagnosis equations are characterized by the same denominator, we have (13-18)
Mp=N+n(N+l)
where n is the numberof fault diagnosis equations. In summary, we have the following secondnecessary condition: For a circuit of order N, with n test points, a necessary condition for maximum of testability is that the number of potentially faulty parameters is equal to or lower than N + n (N + 1).
EXAMPLE 13.2 Let us considera simpleexample to showthe application of previous results. The circuit in Fig. 13.5 is a bandpass active circuit. Consider as the test point the output voltage Vo' The symbolic analysis of the circuit gives the following fault diagnosis equation: Vo
H(s) = V
in
= s2+ (G
-G tB 2s
2B 1
+G
2B2
)s +G
(13-19) 1B1G2B2
Sec. 13.2
365
The Testability Concept
C2 R2
Rl Cl
Vo
+
Vin
Figure 13.5 Bandpass filter.
where G.I = l/R.,I B.J = l/CJ.. In the fault diagnosis equation, there are three coefficients; then, if we consider as potentially faulty aJl four components, the testability cannot be maximum. The matrix Be is the following:
Bc
-B 2
0
o
0
B 1 +B 2
G2
-G I G2
G2B I B 2
G1B I B 2
G IG 2B 2
G 1G 2B I
=
( 13-20)
and its rank is three (we recall that, because the testability value is independent on the component values, the rank can be easily computed by assigning dummy values to the components). Then the network has a testability equal to three. However, a different choice for the test point can lead to a maximum of testability. In fact, the second necessary condition is satisfied: the circuit is of the second order and then, from (13-17), the maximum number of testable components is five. If we consider as the test point the output current of the ideal op-amp, we have the following fault diagnosis equation: lOA
H(s) = V.
=
In
G 1S2 + (G 1G2B 1 +G IG 2B 2)s s2+ (G 2B 1 +G2B2)s+GIBIG2B2
(13-21 )
In this case, we have four coefficientsand the testability can be maximum.Matrix Be is now 0
Bc
=
G 2B I
+ G 2B2
GIB I
+ G IB2
0
0
GIG2
GIG2
0
B 1 +B 2
G2
G2
G2B 1B 2
G IB 1B 2
G 1G2B 2
G I G 2B I
The rank of the matrix is four, and we have maximum of testability.
(13-22)
366
Chapter 13
Analog Testability and Fault Diagnosis Using Symbolic Analysis
Obviously, in a real application, several other practical considerations must be taken into account in the choice of test points. For example, in the circuit just presented, depending on the technology used for the realization, the current test point could be very difficult to use. Voltage test points are usually preferred. On the other hand, it is easy to prove that, using only voltage test points, that is, using only fault diagnosis equations represented as voltage transfer functions, the testability can never be maximum if all circuit components are considered potentially faulty. In fact, such network functions are invariant with respect to a component value's amplitude scaling. In these cases, the maximum value of testability attainable is the number of circuit components minus one.
13.2.3. Testability of Nonlinear Circuits The definitions and the methods presented in previous sections are based on the study of given network functions in the transformed domain. Then the approach is rigorously applicable only for linear circuits. However, by means of some practical considerations, the presented technique can give useful information also for the fault diagnosis of nonlinear circuits. To discuss such considerations, it is useful to take into account two different kind of nonlinear circuits: those in which the nonlinear behavior is structural, that is, the presence of nonlinear components is essential to the desired behavior (rectifiers, mixers, modulators, and so on), and those in which the nonlinear behavior can be considered as a parasitic bearing. For these latter, the techniques presented can be applied to a linearized model of the circuit under test and can be used directly to optimize the selection of test points in the circuit. Obviously, the nonlinear behavior, which could be prevalent in fault conditions, will render much more difficult the fault diagnosis phase, requiring the use of proper and particular techniques. For the former case, the use of the proposed techniques can be useful if it is possible to represent the nonlinear circuit by means of suitable piecewise linear (PWL) models. In this case, the testability value can be computed on the corresponding PWL circuit. This aspect will be further discussed in section 13.4.
13.3. FAULT DIAGNOSIS OF LINEAR ANALOG CIRCUITS In the past few years, a noteworthy number of techniques have been proposed for the fault diagnosis of analog linear and nonlinear networks (excellent presentations of the state of the art in this field can be found in Refs. [23]-[25]). All these techniques can be classified into two basic classes: simulation-before-test (SBT) techniques and simulation-after-test (SAT) techniques. These two classes share a combination of simulation and measurements, the difference depending on the time sequence in which they are applied. In the former case (SBT), the circuit under test is simulated under different faults, and after a set of measurements, a comparison between the actual circuit response to a set of stimuli and the presimulation gives an estimation of how probable a given fault is. These techniques are especially suited to the location of hard or catastrophic faults because they are generally based on the assumption that any fault influences the large-signal behavior of the network. There exist many different procedures, but they often rely on constructing a fault dictionary, i.e., a prestored data set corresponding to the value of some network variables when a given fault exists in the circuit.
Sec. 13.3
Fault Diagnosis of Linear Analog Circuits
367
The SAT approaches are mostly tailored to cases where the faults perturb the small-signal behavior; that is, they are especially suited to diagnose and locate parametric faults (i.e., deviations of parameter values from a given tolerance). These methods use measurements from a selected subset of circuit nodes (test points); then, from the measurements, network parameters are reconstructed and compared to those of the fault-free network to identify the fault. The use of symbolic methods is particularly suited for SAT techniques and, in particular, for those based on parameter identification methods. These last methods can be further split into two main categories: those based on frequency-domain measurements and those based on time-domain measurements.
13.3.1. Symbolic Methods Based on Multifrequency Measurements Fault diagnosis methods based on repeated ac measurements, p.erformed at different frequencies, have been extensively studied in the past. From a theoretical point of view, these procedures are based on the formulation of a system of fault diagnosis equations, and on the solution of this system with respect to the unknown parameters. The system obtained is nonlinear, even for a linear circuit, and the solution requires nonlinear techniques. The use of repeated measures allows us to obtain a determined system starting from a number of fault diagnosis equations inferior to the number of unknown parameters. From a practical point of view, the application of this procedure is not straightforward and several tricks could be used to obtain practical results. References and suggestions on these methods can be found in papers already cited [23]-[25]. In any case, for these techniques, the use of a symbolic approach is very useful as it makes it possible to obtain the fault diagnosis equations in symbolic form with respect to the unknown parameters. Let us briefly show this aspect using the very simple example already used for testability (circuit of Fig. 13.5). We assume to use one test point corresponding to the output voltage (as already shown, the testability, in this case, is equal to three). The corresponding fault diagnosis equation, in symbolic form, is
H (s)
V
= --.!!.. = V.
(13-23)
In
Because the testability is three, the parameter identification problem is solvable only for three unknown parameters. We can assume one of the components is not subject to fault, or, equivalently, that one of the components is directly measurable. We assume that such a component is G} and that its value is 20 11- 1• The three unknown parameters are then G2, B}, and B2. To solve the problem, we need a system of three equations. This can be obtained, starting from the unique fault diagnosis equation, by means of three measurements. For example, we can measure the amplitude of the fault diagnosis equations for three different values of the frequency. The corresponding system will be
368
Chapter 13
Analog Testability and Fault Diagnosis Using Symbolic Analysis
= F.1
i
= 1,2,3
(13-24)
where F; are the measurements. Assume that the measurement frequencies are <01 = 1 rad/s, <02 = 2 rad/s, and <03 = 4 rad/s, and that the corresponding measurements give F I =200, F 2 = 13.304, and F 3 = 5.331. Then, the unknown parameter (G 2, B I , B2 ) values can be obtained solving the following nonlinear system: 20B 2
J (G 2B 1 + G 2B 2) 2 + (20G 2B 1B 2 - I) 2 40B 2
(13-25)
J4(G 2B 1 +G 2B 2)2+ (20G 2B 1B 2-4)2 80B 2
= 5.331
The solution of the system, with the constraint G2 , B I' B2 > 0, gives the result G2 = 0.05, B I=I,andB2=1. From a theoretical point of view, the outlined procedure is always applicable. However, even this very simple example shows that, from a practical point of view, there are several problems to overcome. The nonlinear system is very complex, even for a very simple circuit. Another noteworthy problem is the choice of the test frequencies. The practical solvability of the system depends, in fact, on the chosen frequencies. To reduce the complexity of the problem, some assumptions can be made. Often the problem is simplified assuming the number of expected faulty components bounded. This is the so-called k- fault diagnosis problem, where k is the bound on the number of possible faults. Nevertheless, in this case, component value tolerances must be taken into account. That is, the problem has to be modified because it must be solved considering a tolerance band for every component, instead of just a nominal value.
13.3.2. Symbolic Methods Based on Time-Domain Measurements The use of fault diagnosis methods based on time-domain measurements, that is, on I/O sampled waveforms, is very attractive because it greatly simplifies the test phase. In order to make this, it is necessary to discretize the fault diagnosis equations. To this end, it is possible to use one of the well-known discretization techniques such as backward
differences. In this way, by replacing s with
II -z )/T in the fault diagnosis equations -I
s
(13-3), we obtain, for the linear network, the following difference model, constituted by ", . n.v equations: (J) ) 1•
= a I)' .(J) (k - 1) + ... + a
v.(J)
l i n · 1
(k - n) + box (j) (k) + ... + bn x (J) (k - n) ( 13-26)
Sec. 13.3
369
Fault Diagnosis of Linear Analog Circuits
These equations describe an infinite impulse response (IIR) system, which represents an approximate model of the analog circuit under test. The coefficients of each difference equation (the coefficient number is at most 2n + 1 , if n is the order of the circuit) depend on the circuit parameters in a nonlinear way. Therefore, from the network function discretization, we obtain a new fault diagnosis system for the parameter identification, constituted by (2n + 1) (n x . n y ) nonlinear equations. In fact, if we are able to numerically evaluate the difference equation coefficients, this system becomes a nonlinear system with respect to unknown vector p components. It is evident that this procedure requires a symbolic approach. In fact, if the test point network functions are known in completely symbolic form with respect to both component values and complex frequency s, the discretization yields the knowledge of the coefficients of the difference equations in completely symbolic form with respect to component values.
EXAMPLE 13.3 As an example, let us consider again the circuit of Fig. 13.5. By replacing s with
II -z )/T -I
s in the fault diagnosis equation, we obtain the discretized transfer function:
( 13-27)
that is, the following difference equation: ( 13-28)
where the symbolic expression of the coefficients are
no = -TsG}B 2 d} = -2-TsG2B2-TsG2B}
do = 1 + TsG2B2 + TsG2B} + T.;G}G
(13-29)
2B}B2
These equations represent a new system of fault diagnosis equations. Obviously, this system represents a usable fault diagnosis system only if we are able to numerically evaluate the difference equation coefficients. This operation can be made by exploiting time-domain measurements of test-point outputs and inputs, so that, in Eq. (13-28), the coefficients n; and d, are unknown, while the samplesof the input x(t) and test-point outputs y(t) are known. This kind of problem falls within the general problem of discrete-time dynamical system identification [26], [27] and several methods have been proposed for its solution. The fundamental steps of the procedure are summarized in the block diagram of Fig. 13.6. The hard point of the outlined procedure is the IIR system identification.That is, the determination of the numerical values of the coefficients of the discrete-time network functions, starting from 1/0 sampled waveforms. This is a classical problem and there is a lot of work on this subject, performed in the fields of adaptive filtering, adaptive control,
370
Chapter 13
Analog Testability and Fault Diagnosis Using Symbolic Analysis
I
IAnalOg Circuit I
test points symbolic network functions s - z approximation discrete-time symbolic network functions discrete-time model of the circuit under test
sampled 110 waveforms
~
IIR system
determ ination of the num erical values of the coefficients of the discrete-time symbolic n.f,
IIR system identification procedure
fault diagnosis equations system: symbolic expressions of the coefficients of the discrete-time symbolic n.f. I
Figure 13.6 Time-domain fault diagnosis procedure.
and system identification. Several algorithms have been proposed (see, for example, Refs. [26] and [27]), but the problem is not yet completely resolved. However, in our particular case of fault diagnosis, the requests are less stringent than in other application fields: usually we are not interested in determining precise values of components, but it is sufficient to evaluate what components are changed with respect to their nominal values. Furthermore, usually we are not interested in a real-time identification, as, for example, is requested in the field of adaptive systems. The k- fault diagnosis hypothesis can be used also in this case to reduce the complexity of the problem.
13.4. FAULT DIAGNOSIS OF NONLINEAR CIRCUITS The fault diagnosis methodologies outlined in previous sections are applicable only to linear circuits or to linearized models of the circuit under test. They are not applicable to circuits in which the nonlinear behavior is structural, that is, it is essential to the requested electrical behavior. However, the symbolic approach can be usefully applied also in these cases. The aim of this section is to present an example of this kind of application [28].
Sec. 13.4
Fault Diagnosis of Nonlinear Circuits
371
As is known, a field in which the symbolic approach can give noteworthy advantages with respect to the numerical techniques is constituted by those applications that require the repetition of a high number of simulations performed on the same circuit topology with the variation of component values and/or input signal values. In this kind of application, the symbolic approach can be used to generate the requested network functions of the analyzed circuit in parametric form. In this way, circuit analysis is performed only once and, during the simulation phase, only a parameter substitution and an expression evaluation are required to obtain numerical results. The outlined approach can be used to generate autonomous programs devoted to the topological circuit analysis. Furthermore, for a complex circuit, these simulators can be dedicated to parts of the circuit in order to obtain a simulator library. In this section, a program package is presented following the outlined approach. The program, named SAPDEC (Symbolic Analysis Program for Diagnosis of Electronic Circuits), is able to produce dedicated simulators for nonlinear analog circuits and is aimed at fault diagnosis applications. The technique proposed in this section presents several novel aspects with respect to existing symbolic approaches. First of all, the output of the realized program package, SAPDEC, is an autonomous executable program, a simulator dedicated to a given circuit structure, instead of a network function in symbolic form. The generated simulators work with inputs and outputs in numerical form; nevertheless, they are very efficient because they strongly exploit the symbolic approach; in fact: • they use, for numerical simulation, the closed symbolic form of the requested network functions; • they are dedicated to a given circuit structure; and • they are independent from both the component values and input values, which must be indicated only at run-time, before numerical simulation. Another novel aspect of the presented approach is that the generated symbolic simulators produce time-domain simulations and are able to work on nonlinear circuits. To this end, the following methods have been used: • nonlinear components are replaced by suitable PWL models; • reactive elements are simulated by their backward-difference models; and • a Katzenelson-type algorithm is used for time-domain response calculation. These three points are examined in detail in the following sections.
13.4.1. PWL Models With the PWL technique [29], the voltage-current characteristic of any nonlinear electronic device is replaced by piecewise linear segments obtained by means of the individuation of one or more corner points on the characteristic. The piecewise linear characteristic thus obtained describes approximately the element behavior in the different operating regions in which it can work. It is evident that the increase of the number of corner points and, consequently, of the number of linearity regions allows us to obtain a
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higher precision in the simulation of the real component; obviously, in this way, the corresponding model becomes more complex. It is worth pointing out that the symbolic analysis is completely independent from the number of corner points of the PWL characteristics; in fact, from a symbolic analysis point of view, each nonlinear component of a PWL model is represented by a single symbol. However, the increase of the number of corner points influences computational time in the numerical simulation phase, so a trade-off between a small number of corner points and requested accuracy must be realized for each model. In order to determine the circuit network functions, the MNA (modified nodal analysis) is used during symbolic analysis. This method yields a solution system whose dimension increases with the number of components that have impedance representation. For this reason, if possible, a characteristic I = G( V) has to be considered. for nonlinear components. In this way, an equivalent circuit constituted by a conductance G, in parallel with a current source Ii can be associated with each nonlinear component: for every linearity region, Gi corresponds to the slope of the segment and Ii to the zero-voltage current of the segment, as shown in Fig. 13.7 for a diode.
2 G..............
G.
• ••• 1
I
....
>:. v
I·I
a)
b)
Figure 13.7 (a) Diode PWL model; (b) diode PWL characteristic.
13.4.2. Transient Analysis Models for Reactive Components The reactive components are made time-independent by using the backward-difference algorithm, and the corresponding circuit models are constituted by a conductance in parallel with a current source [28]. In Fig. 13.8, the model of a capacitor is shown as an example: the conductance value is a function of the sampling time T and of the capacitance value, while the current value depends on the sampling time T, the capacitance value, and the voltage value at the previous time step. In this way, neither the Laplace variable nor integrodifferential operations are used, and the circuit becomes, from the symbolic analysis point of view, without memory, and, from the numerical simulation point of view, time discrete.
Sec. 13.4
373
Fault Diagnosis of Nonlinear Circuits
V k+1
G
1= (Crf)V
k
=
Ik+1 (CIT)I\/ - Vk ) \ v k+1 Figure 13.8 Backward-difference model of a capacitor.
13.4.3. The Katzenelson-Type Algorithm The Katzenelson algorithm is an iterative process, which allows one to determine the de solution of a PWL circuit. In its standard form, this algorithm is summarized in Refs. [29] and [30] and in the following. The starting system is of the kind ( 13-30) where T1 is the characteristic matrix of the circuit and the subscript I denotes the region in which the network operates. The right-hand-side vectors denote the equivalent sources due to linearization (wI) and the independent sources (w), and they are written separately for clarity. Because at the beginning the regions are unknown, the node voltages and the currents of current-controlled elements are arbitrarily selected in order to determine all the operating regions of PWL elements. Then, all G I and II are known and the vector x is so determined. This vector does not satisfy Eq. (13-30) due to the arbitrary choice of node voltages and the currents of the current-controlled elements. Thus, an iterative process of correction starts, for which the estimated vector x represents the initial value. By defining an error vector as (13-31) where k indicates the kth iteration, the solution is reached when fk is equal to zero. Once fk has been evaluated, a correction vector 8x k is determined by solving the following system: ( 13-32) The new solution is ( 13-33) IfEq. (13-33) implies that none of the PWL elements changes its own operating region with respect to the kth iteration, x k + 1 is the desired final solution, otherwise the procedure starts again, replacing x k by a new x k + 1 , which is obtained from Eq. (13-33) by multiplying
374
Chapter 13
Analog Testability and Fault Diagnosis Using Symbolic Analysis
I1xk by a suitable corrective factor Ok [29]. It must be noted that, using a symbolic approach, the time-domain simulation can be obtained with an algorithm derived from that just described, but simpler. By means of the symbolic MNA applied to the circuit structure, all the necessary network functions are available for the algorithm in a symbolic form. Starting from an arbitrary value for the MNA unknown vector, the corresponding PWL element values are determined and introduced in the network functions, together with the actual values of both inputs and linear components. The correction vector is then evaluated and the iterative process starts until the final solution is achieved. The difference with respect to the standard Katzenelson algorithm consists, to a large extent, in the fact that, with the symbolic approach, the program works on the closed-form expressions of the network functions and then, for each step of the algorithm, there is not a linear system solution, but only an expressions evaluation. This allows us to obtain a noteworthy gain in terms of computational times in the numerical simulation phase. In particular, i1xk can be computed simply as the difference between the x k vector and the corresponding vector obtained from the symbolic network functions, in which the PWL component values have been replaced by the values corresponding to the x k vector.
13.4.4. The Circuit Fault Diagnosis Application Following the approach outlined in the previous section, a program package named SAPDEC (Symbolic Analysis Program for Diagnosis of Electronic Circuits) has been developed. It is able to generate simulators dedicated to any part of a suitably partitioned circuit. The program can be used to realize a library of dedicated simulators. Each simulator in the library is dedicated to a part of the circuit and can be directly used by an expert system for circuit fault diagnosis. The input signals for these simulators can be constituted by the actual signals on the circuit under test, suitably measured, and stored on a file. The circuit responses, produced by the simulators and stored in another file, can be compared by means of qualitative and/or quantitative methods with the actual responses measured on the circuit under test. From this comparison, the expert system will be able to test the correctness of the behavior of the part under study. When a faulty part has been located, the expert system can try to locate the fault at a component level. This last phase will require repeated simulations with suitable variations of component values. The realization of the simulator library for a given equipment requires a preliminary phase constituted by the decomposition of the circuit under test in small parts by means of suitable partitioning techniques. Then, for each part, the following operations have to be carried out: 1. Representation of nonlinear components by means of appropriate piecewise linear (PWL) models; 2. Symbolic analysis of each part with the generation of the required network functions as C language statements; 3. Generation of the dedicated simulator by means of the compilation of the produced functions and linking with a standard module, in C language, which implements a PWL simulation technique by means of a Katzenelson-type algorithm.
Sec. 13.4
Fault Diagnosis of Nonlinear Circuits
375
These operations are performed, in an automatic and autonomous way, by the program SAPDEC. An important characteristic of the proposed approach is the fact that the input signals for the simulators are made up of the actual signals on the circuit under test, measured in fault conditions. In fact, for fault diagnosis, test signals are usually used instead of actual input signals; this can be very difficult to do and may not reflect the real behavior in many cases, as, for example, in equipment with strong feedback and with internally generated signals, such as de-de converters. Regarding the decomposition of the circuit under test, some considerations can be done. At present, this partition is not performed automatically and has to be performed by the user, who must try to obtain trade-offs among several objectives. An important point is the choice of the size of the blocks; they must be small, not only to obtain faster simulators, but to have blocks characterized by a high testability, in which it is possible to determine the faulty components starting from the measurements performed on input/output nodes. On the other hand, very small blocks increase the cost of the test because they complicate the phase of location of the faulty block (or blocks) and they generally involve a high number of input/output nodes (which, obviously, must be accessible). A possible route to follow is the iterative use of existing partitioning techniques [31]-[33] and applying the algorithms for testability computation to the obtained parts, until a good trade-off is obtained.
13.4.5. The SAPDEC Program In Fig. 13.9, the block diagram of SAPDEC is shown. The program runs on MS-DOS personal computers and requires an ASCII file describing the circuit under test. The form of this file is, for many aspects, similar to that required by the SPICE program. Each device of the circuit is represented in the input file by one line. The allowed linear components are: conductor, inductor, capacitor, independent voltage and current sources, the four controlled sources, mutual inductance, and ideal transformer. The nonlinear components are nonlinear conductor, diode, voltage-controlled switch, operational amplifier, and bipolar and MOS transistor. Suitable commands, included in the input file, must be used to communicate the output node list and the names of the files containing the input signal samples and component values to the program. Once the program has started, all the component numerical values (both linear and nonlinear) are stored, and both nonlinear and reactive components are automatically replaced by the corresponding equivalent circuits. Then, the symbolic evaluation of the requested network functions is carried out by means of a program written in c++ language. These network functions are generated in the form of C language statements and are automatically assembled with the standard module, in C language, which implements the Katzenelson-type simulation algorithm. Finally, the compilation and linking of the obtained source program is automatically performed, thus realizing the dedicated simulator, which is independent of the component values, input sample values, and sampling time. The obtained simulator is able to produce a file containing the output signal samples, the result of the simulation, starting from the input sample file (also containing the used sampling time) and from the component value file. The nonlinear component values are in the form of a list of parameters for semiconductor components and for the operational amplifier (for example, ~t"e' V beo' Vcesat' etc., for bipolar transistor), while, for nonlinear conductors and diodes, the slope (in the form of conductance) and the corner voltage of
376
Chapter 13
Analog Testability and Fault Diagnosis Using Symbolic Analysis
SPICE-like circuit description
generation of symbolic network functions
SAPDEC
symbolic network functions compiler simulation algorithm
dedicated simulator
Figure 13.9 Block diagram of SAPDEC operations.
each PWL characteristic linearity region are given. For these last elements, all the corner current numerical values are automatically calculated by supposing the corresponding characteristic crossing the point (0, 0); this assumption makes univocal the corner point determination without loss of generality, because all the considered components have an 1- V characteristic crossing the point (0, 0) (for example, photovoltaic components have not been considered). In Fig. 13.10, the dedicated simulator flow diagram is shown. Once the simulator is realized, by changing only the files containing the component values and the input samples, respectively, repeated simulations can be obtained in a very fast way. Suitable PWL models have been chosen by the authors for transistors and operational amplifiers in such a way to realize a trade-off between a low number of components and simulation accuracy, taking into account the specific application requirements [28]. The models presented in Ref. [28] are very simple, so the obtainable simulation accuracy is not very high, but it is acceptable for fault diagnosis as well as for other application fields. Obviously, the use of more complex models permits us to obtain more accurate results. Summarizing, the simulators produced by SAPDEC have the following characteristics:
Sec. 13.4
377
Fault Diagnosis of Nonlinear Circuits
component
input file
values file
DEDICATEDSIMULATOR
output file
Figure 13.10 Dedicated simulator operations flow diagram.
1. They are very compact (a few tens of kilobytes);
2. They are very fast (a few seconds to obtain 100 output samples on a medium-speedPC); 3. The input signal samples are read from a file; 4. The output signal samples (the simulation result) are stored in a file; 5. The component values are read from a file.
It is worth pointing out that the files for input signals and for output signals have the same structure. Then, it is also possible to use the simulated output signals of a given block as input signals for another block. EXAMPLE 13.4
As a simple example to show how SAPDEC is used, let us consider the circuit in Fig. 13.11, in which a fault condition has been simulated by changing the value of the conductance G, from 1/220
rr' to 1/82 n- I .
2
1
C1
G2
10uF
1/4.7K
0-----1
4
G6 1/47K
3
5
Figure 13.11 Nonlinear circuit example.
378
Chapter 13
Analog Testability and Fault Diagnosis Using Symbolic Analysis
First of all, SAPDEC is used to generate the dedicated simulator, starting from the input file describing the circuit. In this file, no value is assigned either to the components or to the inputs. In the file there are appropriate commands to indicate which files will contain component values and input signal values, and which will be read during simulation. The circuit constitutes a part of a greater network that is connected to it by means of nodes 2, 3, and 4. The actual measured input signals, that is, the voltages at nodes 2, 3, and 4 are stored in a file in sampled form, in a format that the dedicated simulator generated by SAPDEC is able to read. This file also contains the sampling time used. The nominal component values are stored in another file. In Fig. 13.12, the measured output signal at node 5 is shown. In Fig. 13.13, the output signal at node 5 obtained by the dedicated simulator, for component nominal values, is reported. The comparison between these two signals reveals that the circuit is faulty. The location of the faulty components requires the repeated use of the dedicated simulator of the circuit, by suitably changing component values until the measured output waveform and the simulated one agree within a suitable tolerance. This search procedure can be performed using appropriate algorithms (as, for example, a sort of optimization algorithm), and/or using heuristic methods. In Fig. 13.14, the simulated output signal obtained for Gs = 1/820-1 is shown. A comparison of the waveforms in Figs. 13.12 and 13.14 reveals that the component Gs is faulty. The fact that the two waveforms do not fit perfectly is due 0.04
0.03
0.02 I - - - - - + - - - - + - - - - - + - - - I - - - - + - - - - - + - - - - - - - l
0.01 1 - - - - - + - - - - - - + - - - - - + - - - 1 - - - - + - - - - - + - - - - - - - 1
56
112
168
224
280
336
392
Figure 13.12 Measured output voltage at node 5.
0.054
0.027
0.0135 1 - - - - - + - - - - - + - - - - + - - - 1 - - - - - + - - - - - + - - - - - 1
56
112
168
224
280
336
Figure 13.13 Node 5 voltage, simulated for the G5 nominal value.
392
379
References
0.04
0.03
0.02 I - - - - - + - - - - - + - - - - - t - - - - - + - - - - - - + - - - - - - + - - - - - - - - I
0.01 I - - - - - + - - - - - + - - - - - t - - - - - + - - - - - - + - - - - - - + - - - - - - - - I
56
112
168
224
280
336
392
Figure 13.14 Node 5 voltage,simulated for the Gs fault value.
to the very simple model adopted for the transistor, but, for this kind of application, the obtained accuracy is usually sufficient.
13.5. CONCLUSIONS An overview on the application of symbolic methodologies in the field of testability and fault diagnosis of analog circuits has been presented. It is our opinion that the advantages of the symbolic approach in this particular, and difficult, field have not yet been fully exploited. We think that symbolic techniques can give a noteworthy contribution to overcoming the difficulties that form the basis of the gap between the analog and digital fields.
References [1] R. S. Berkowitz, "Conditions for network-element-value solvability," IEEE Trans. Circuit Theory, vol. CT-9, pp. 24-29, 1962. [2] R. Saeks, "A measure of testability and its application to test point selection theory," 20th Midwest Symp. Circuit Syst., Texas Tech. Univ., Lubbock, August 1977. [3] N. Sen and R. Saeks, "Fault diagnosis for linear systems via multifrequency measurement," IEEE Trans. Circuits Syst., vol. CAS-26, pp. 457-465, July 1979. [4] H. M. S. Chen and R. Saeks, "A search algorithm for the solution of multifrequency fault diagnosis equations," IEEE Trans. Circuits Syst., vol. CAS-26, pp. 589-594, July 1979. [5] R. Saeks, N. Sen, H. M. S. Chen, K. S. Lu, S. Sangani, and R. A. De Carlo, "Fault analysis in electronic circuits and systems," Tech. Rep., Inst. for Electron. Sci., Texas Tech. Univ., Lubbock, January 1978. [6] G. Ternes, "Efficient method of fault simulation," 20th Midwest Symp. Circuits Syst., Texas Tech. Univ., Lubbock, August 1977. [7] W. J. Dejka, "A review of measures of testability for analog systems," Proc. AUTOTESTCON, 1977. [8] R. W. Priester and J. B. Clary, "New measures of testability and test complexity for linear analog failure analysis," IEEE Trans. Circuits Syst., vol. CAS-28, pp. 1088-1092, November 1981.
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[9] J. W. Bandler and A. E. Salama, "Fault diagnosis of analog circuits," Proc. IEEE, vol. 73, pp. 1279-1325, August 1985. [10] J. A. Starzyk and H. Dai, "Multifrequency measurements of testability in analog circuits," Proc. 1987 IEEE Int. Symp. Circuits Syst., Philadelphia, PA, 1987. [11] G. N. Stenbakken and T. M. Souders, "Test point selection and testability measures via QR factorization of linear models," IEEE Trans. Instrumen. Meas., vol. IM-36, pp. 406-410, June 1987. [12] G. N. Stebbakken, T. M. Souders, and G. W. Stewart, "Ambiguity groups and testability," IEEE Trans. Instrumen. Meas., vol. 38, pp. 941-947, October 1989. [13] G. Iuculano, A. Liberatore, S. Manetti, and M. Marini, "Multifrequency measurement of testability with application to large linear analog systems," IEEE Trans. Circuits Syst., vol. CAS-23, pp. 644-648, June 1986. [14] M. Catelani, G. Iuculano, A. Liberatore, S. Manetti, and M. Marini, "Improvements to numerical testability evaluation," IEEE Trans. lnstrumen. Meas., vol. IM-36, pp. 902-907, December 1987. [15] R. Carmassi, M. Catelani, G. Iuculano, A. Liberatore, S. Manetti, and M. Marini, "Analog network testability measurement: a symbolic formulation approach," IEEE Trans. lnstrumen. Meas., vol. 40, no. 6, pp. 930-935, December 1991. [16] A. Liberatore and S. Manetti, "SAPEC-A personal computer program for the symbolic analysis of electric circuits," Proc. 1988 IEEE Int. Symp. Circuits Syst., Helsinki, Finland, pp. 897-900, June 1988. [17] A. Liberatore and S. Manetti, "Network sensitivity analysis via symbolic formulation," Proc. 1989 IEEE Int. Symp. Circuits Syst., Portland, OR, pp. 705-708, May 1989. [18] S. Manetti, "A new approach to automatic symbolic analysis of electric circuits," lEE Proc. P. G: Electron. Circuits Syst., vol. 138, no. 1, pp. 22-28, February 1991. [19] S. Manetti, M. C. Piccirilli, and A. Liberatore, "Automatic test point selection for linear analog network fault diagnosis," Proc. 1990 IEEE Int. Symp. Circuits Syst., New Orleans, pp. 25-28, May 1990. [20] A. Liberatore, S. Manetti, and M. C. Piccirilli, "Tecniche di intelligenza artificiale applicate alia detenninazione della testabilita ed alia scelta dei punti di prova in circuiti lineari analogici," Alta Frequenza, vol. III, no. 2, pp. 137-145, 1991. [21] S. Manetti and M. C. Piccirilli, "Symbolic method for circuit testability and fault diagnosis in time domain," Proc. 11th European Conf. Circuit Theory Design, Davos, Switzerland, pp. 1681-1686, August 1993. [22] A. Liberatore, S. Manetti, and M. C. Piccirilli, "A new efficient method for analog circuit testability measurement," 1994 Instrumen. and Meas. Conf., Hamamatsu, Japan, pp. 193-196, May 1994. [23] J. W. Bandler and A. E. Salama, "Fault diagnosis of analog circuits," Proc. IEEE, vol. 73, no. 8,pp. 1279-1325, 1985. [24] R. Liu, Testing and Diagnosis of Analog Circuits and Systems. New York: Van Nostrand Reinhold, 1991. [25] J. L. Huertas, "Test and design for testability of analog and mixed-signal integrated circuits: theoretical basis and pragmatical approaches," Proc. 11th European Con! Circuit Theory Design, Davos, Switzerland, August 1993. [26] J. P. Norton, An Introduction to Identification. London: Academic Press, 1986. [27] C. F. N. Cowan and P. M. Grant, Adaptive Filters. Englewood Cliffs, NJ: Prentice-Hall, 1985.
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[28] S. Manetti and M. C. Piccirilli, "Symbolic simulators for the fault diagnosis of nonlinear analog circuits," Analog Integrated Circuits and Signal Process., pp. 59-72, 1993. [29] J. Vlach and K. Singhal, Computer Methodsfor CircuitAnalysis and Design, 2nd ed. New York: Van Nostrand Reinhold, 1994. [30] J. Katzenelson, "An algorithm for solving nonlinear resistor networks," Bell Syst. Tech. J., vol. 44, pp. 1605-1620,1965. [31] A. Konczykowska and J. Starzyk, "Computer analysis of large signal flowgraphs by hierarchical decomposition methods," Proc. European Conf Circuit Theory Design, pp. 408-413, 1980. [32] J. Starzyk, "Signal-flow-graph analysis by decomposition method," lEE Proc., P. G, vol. 127,no.2,pp. 81-86,1980. [33] A. Konkzykowska and 1. Starzyk, "Flowgraph analysis of large electronic networks," IEEE Trans. Circuits Syst., vol. CAS-33, no. 3, pp. 302-315,1986.
Index
A Analog design knowledge-based, 237-240 optimization-based, 238-240 overview of automated techniques, 234-240, tools: see ARIADNE, ASTRXI OBLX, BLADES, DELIGHT.SPICE, DONALD, IDAC, OASYS, OPASYN, OPTIMAN using symbolic models, 11, 240-256
see testability Analysis numerical, 2 qualitative, 2 see symbolic analysis see symbolic analyzers Approximation after generation of expanded format expressions, 146-159 before generation, 174-176 concept, 144-146 during generation, 167-174 of nested format expressions, 159-167 of weakly-nonlinear expressions, 199-207 rationale for, 141-144 see error (criterion for approximation) see range of variation
Analog synthesis building block knowledge-base for, 274-288 flow of information for, 260 parameter optimization, 221 step-by-step SC synthesis, 267-274 structure optimization, 216-224 using symbolic approach, 224-230 see analog design
ARIADNE, 249, 250
Analog test see fault diagnosis,
ASAP, 6, 12-13,20-21,150,159,172, 173,241
383
384
Index
criterion for approximation, 147-151,
ASTRX/OBLX, 253-254
155,157-159,170-171
B BLADES, 237
c Cancellation-free algorithm,.29 expression, 29,32, 36; 55 Connection
O-connecuon, 42 l-connection, 42 k-connection, 42 Contribution factors, 163.. 165
D
Expanded format expressions see approximation see format of symbolicexpressions
F Fault diagnosis of linear analog circuits, 366-370 of nonlinearcircuits, 370-379 see SAPDEC see testability
FIT, 293-295,298, 309 FIT-S, 298,301-309 Flowgraph analysis of SC networks based on, 264-267
Delay models analytical, 333.. 346 CMOS. inverterdelay, 341-342 composite transistordelay, 342-346 Re.. based, 31 ~-319 statistical, 321..323
Arnautovic-Lin approach based on, 73-79
Coates graph, 42-43, 97-99, 127-130 Mason signal flowgraph, 36-42, 97-99,116-127
representation of SC elements, 262 Sedlar..Bekey method based on,
DELIGHT.SPICE, 238 Delta variable, 13, 154, 163 Design see analog design Device models capacitor, 328.. 330 MOS.,transistor, 323-328 PWLmodels, 371..372 statistical, 330·333
weakly-nonlineartransistor models, 190-193
Distortion see harmonics see intermodulation see weakly-nonlinear circuits
DONALD, 250
E Elmore's time constant, 315..318
ESTEPS, 361 Error
66-73 FLOWUP, 102
Format of symbolic expressions expanded, 14-16,145.. 159 nested, 14-16, 145,159-167 sequence-of-expressions, 14-16, 28, 114-116, 145
G Graph colored, 169 current,33, 168..169 directed, 29-32,97, 169, see flowgrap, two-graph, 33, 44, 176 undirected, 33-35, 97 voltage, 33, 168.. 169,175
H Harmonics
385
Index
calculation methods for, 193-199 see Volterra simplified symbolic computation of, 199-207 HarPE, 292 Hierarchical analysis Coates graph method, 127-130 direct network method, 108-116 Mason signal flowgraph method, 116-127 parallel processor implementation, 107-108 see approximation (of nested format expressions) Hierarchy circuit-level hierarchy, 102-105 expression-level hierarchy, 105-107 identification techniques for SC primitives, 262-264 see format of symbolic expressions
I IC-CAP, 292 IDAC, 237 Indefinite admitance matrix, 44, 99 Intermodulation calculation methods for, 193-199 simplified symbolic computation of, 199-207 see Volterra Interval extension meanvalue form, 156 natural, 154, 156, 160-161 ISAAC, 21, 55, 92, 94-95, 241, 249, 250, 255
L Lazy expansion, 162-165, 167 Loop transmittance, 69-71, 78 Loop weight, 37,40-41
M MASSAP, 102,117,121,124,131
Matroids, 169, 178 Middle block analysis, 111-114, 119-120, 128-130 see hierarchical analysis Mismatch 13,16,20-21,147-150, 154-155, 161-165, 171-1 72 Multiconnection see connection (k-connection)
N NAPPE, 18 NASAP, 18, 24, 36, 62 Nested format expressions see approximation see format of symbolic expressions Nodal analysis Modified Nodal Analysis (MNA), 19-21, 48-49, 51-53, 55-56, 59-60, 91-94, 108-110, 114-116, 159, 295, 298, 356, 372,374 MNA compacted (CMNA), 20, 48, 92-94, 159 MNA reduced (RMNA) 19-20, 48, 56, 59-60, 108-115 Node suppression see variable suppression
o OASYS, 237,256 OPASYN, 238-239, 249, 253, 256 OPTIMAN, 238-239, 249-251, 254, 255 Optimization for parameter extraction, 292-293 see analog design see analog synthesis
p Parameter extraction numerical methods, 295, 298-306 overview of methods, 291-293 simulation-based methods, 293-295 symbolic methods, 295-306
386
Index
Parameter extraction tCont'di tools: see FIT, FIT-S, HarPE, IC-CAP, SUCCESS, UTMOST Path transmittance, 69-70, 76, 79-83 Path weight, 37
Sequence of expressions analysis of, 114-116 see approximation (of nested format expressions) see format of symbolic expressions see hierarchical analysis SIFTER, 20-21, 175
Poles and Zeros see symbolic analysis (symbolic poles and zeros)
Signal flowgraph, see flowgraph
Power series descriptions see weakly nonlinear circuits
Simpli fication see approximation SNAP, 18, 24, 36, 62
R RAINIER, 20-22, 175 Range of variation (variation range) addition of, 153-154, 156 approximation using, 152-159 concept, 152 lower operator, 153 modulus of, 153, 156 product of, 153-156 quotient of, 154 reciprocal of, 154 subtraction of, 154 upper operator, 153, 156
SSCNAP, 22,92, 100, 101 SSPICE, 20-21, 25,147,160,167,177 Stamps, 30-31, 43, 50-53, 59, 93, 168-169 SUCCESS, 292 Switch -level simulator, 313-314, 333, 352, 353 models, 89-90, 93, 95, 98, 262, 315 states, 88-90,92, 97-98, 179, 262, 317 Switched-capacitor (SC) circuits, 86-92, 94-96,98,99,227,258-289
s Sampled-data circuits, 4, 19,22,87,88 Sampled-data systems Arnautovic-Lin approach, 73-79 matrix approach, 65-66 signal flowgraph, 64, 66-73 Sedley- Bekey method, 66-73 topological analysis, 64-65 SAPDEC, 371, 375-379 SAP~C,
Spanning tree see tree (spanning)
19-20,24,159,380
SAPTES, 360-362 SCAPP, 19-20,56,102,108,110,114, 121, 124 SCYMBAL, 19,22-23,62,97,98, 101, 227,228,232,255,257 Sensitivity, 17-18,21,23-25,84,161,165, 232,312,358-360,380
Switched-current (SI) circuits, 87-88, 100, 255 SYBILIN, 19-20,298 SYNAP, 20-21, 25, 63,140,159,162,177 Symbolic analysis concept and types, 1-3, 91 flowgraph methods, 36-43, 64-79, 97-99,116-132,264-267 hierarchical symbolic analysis, 102-139 interpolation methods, 47-48 matrix-based methods, 48-60, 65-66, 91-95,108-116 of sampled-data circuits, 64-84, 86-100, 258-288 of weakly nonlinear circuits, 179-207 parameter extraction, 43-47, 99-100 symbolic poles and zeros, 16-17
387
Index
tree-enumeration, 29-36 see analog design see analog synthesis see approximation see delay models see parameter extraction see testability Symbolic analyzers historical notes, 18-22 inputs of, 12-14 outputs of, 14-18 see ASAP, ESTEPS, FLOWUP, ISAAC, MASSAP, NAPPE, NASAP, RAINIER, SAPEC, SCAPP, SCYMBAL, SIFTER, SNAP, SSCNAP, SSPICE, SYBILIN, SYNAP see format of symbolic expressions Symbolic/analytical models of SC circuits, 88-91 of weakly nonlinear circuits, 179-209 see analog design see delay models
of nonlinear circuits, 366 see fault diagnosis, see SAPTES Time complexity, 61 Time-varying circuits, 88, 97 Tree binary tree, 102 directed, 29-30, 32, 169 partitioning tree, 103-104 two-tree, 33-36, 61 spanning, 22, 34, 61, 168-170, 178 undirected, 168, 169 Tree-enumeration directed, 29, 61 und~ecwd,29,33,61,
168,175
U UTMOST, 292
v
Synthesis see analog synthesis
Volterra kernels, 180, 181, 207 series, 180-182, 193, 209, 210
T
w
Tableau analysis, 48 approach, 63 equations, 44 formulation, 91 method, 43 Tearing nodes, 104, 109, 111-113, 116, 118, 119,127 variables, 104 Term cancellations, 28, 29, 36, 94, 109, 162, 169 Terminal block analysis, 109-111, 117-119,127-128 see hierarchical analysis Testability algorithms for evaluation, 357-366 multifrequency approach, 356-357
Weakly nonlinear circuits characteristics of, 181-183 power series description of, 183-193 see approximation see device models (weakly nonlinear transistor models) see harmonics see intermodulation products see Volterra
About the Editors
Francisco V. Fernandez received the physics degree in Electronics in 1988 and the Ph.D. degree in 1992, both from the University of Sevilla, Spain. In 1988, he joined the Department of Electronics and Electromagnetism at the University of Sevilla and in 1991, he was appointed assistant professor. During 1993, he worked at the ESAT laboratory of the Katholieke Universiteit Leuven, Belgium, as a senior researcher. Since 1995 he has been an associate professor at the University of Sevilla. He also works at the Institute of Microelectronics of Sevilla, which is part of the National Microelectronics Center, where he is coordinating, or participating in, several research projects on analog CAD. Dr. Fernandez has coauthored about 50 papers in books, journals, and conference proceedings. His research interests include design and modeling of analog integrated circuits and analog design automation. He is a member of the IEEE. Angel Rodriguez-Vazquez is a professor of electronics at the Department of Electronics and Electromagnetism at the University of Sevilla, as well as a member of the research staff of the Institute of Microelectronics of ~evilla - National Microelectronics £enter (IMSE-CNM), where he is heading a research group on Analog and Mixed-Signal VLSI. His team has participated in a number of ESPRIT Projects; namely, ADCIS, AD2000, AMFIS and AMADEUS, in the course of which a number of state-of-the-art mixed-signal chips have been designed. Dr. Rodriguez-Vazquez has research interests in the design of analog interfaces for mixed-signal VLSI circuits, CMOS imagers and vision chips, neuro- fuzzy controllers, symbolic analysis of analog integrated circuits and optimization of analog integrated circuits. He has authored or coauthored one book, 12 book chapters, more than 60 journal 389
390
About the Editors
papers and about 120 international conference papers. He was corecipient of the 1995 Guillemin-Cauer award of the IEEE Circuits and Systems Society. He also received the best paper award of the 1995 European Conference on Circuit Theory and Design. In 1992 he also received the Young Scientist award of the Sevillian Academy of Science. In 1996 he was elected to the degree of Fellow of the IEEE for "contributions to the design and applications of analog/digital nonlinear ICs". Dr. Rodriguez-Vazquez has been a member of different Technical Program Committees and served as associate editor for the IEEE Transactions on Circuits and Systems - I (1993-1997) and for the IEEE Press. He has been guest coeditor for a number of special issues of the Kluwer journal, Analog Integrated Circuits and Signal Processing, and of the IEEE Transactions on Circuits and Systems.
Jose L. Huertas received his Ph.D. from the University of Sevilla in 1973, where he became a full professor in 1981. From 1970 to 1971, he was with the Philips International Institute, Eindhoven, Holland, working on secure data storage and retrieval. Between 1981 and 1986, he worked at various times in the Electronics Research Laboratory, EE & CS Department, University of California, Berkeley, where he was a senior researcher. Dr. Huertas is presently the Director of the Institute of Microelectronics of Sevilla, which is part of the National Microelectronics Center. He is a Fellow of the IEEE, a member of the (Spanish) national board for evaluating research activities, and a member of the scientific advisory committee of the National Council for Research (CSIC). He has coauthored almost 300 papers and has been corecipient of two best paper awards from the IEEE and one from the lEE. His current research interests include design and test of analog and mixed-signal integrated circuits, nonlinear circuit theory, and CAD tools. Georges G. E. Gielen received the M.Sc. and Ph.D. degrees in electrical engineering from the Katholieke Universiteit Leuven, Belgium, in 1986 and 1990, respectively. From 1986 to 1990, he was appointed as a research assistant by the Belgian National Fund of Scientific Research (BNFSR). In 1990, he was appointed as a postdoctoral research assistant and visiting lecturer at the Department of Electrical Engineering and Computer Science of the University of California, Berkeley. From 1991 to 1993, he was a postdoctoral research assistant of the BNFSR at the ESAT laboratory of the Katholieke Universiteit Leuven. In 1993, he was appointed as a tenure research associate of the BNFSR and, at the same time, as an assistant professor at the Katholieke Universiteit Leuven where, in 1995, he was promoted to associate professor. Dr. Gielen' s research interests are in the design of analog and mixed-signal integrated circuits, and especially in analog and mixed-signal CAD tools and design automation (modeling; simulation and symbolic analysis; analog synthesis; analog layout generation; analog and mixed-signal testing). He is coordinator or partner of several (industrial) research projects in this area. Dr. Gielen has authored or coauthored one book and more than 70 papers in edited books, international journals, and conference proceedings. He is a regular member of the program committees of international conferences (ICCAD, ED&TC, etc.); he has been an associate editor of the IEEE Transactions on Circuits and Systems, part I; and he is a member of the Editorial Board of the Kluwer international journal, Analog Integrated Circuits and Signal Processing. He is a member of the IEEE.
