Solid-State Microwave High-Power Amplifiers (Artech House Microwave Library)

Solid-State Microwave High-Power Amplifiers

For a list of recent related titles in the Artech House Microwave Library, please turn to the back of this book.

Solid-State Microwave High-Power Amplifiers Franco Sechi Marina Bujatti

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Library of Congress Cataloging-in-Publication Data A catalog record for this book is available from the U.S. Library of Congress. British Library Cataloguing in Publication Data A catalog record for this book is available from the British Library.

ISBN-13:  978-1-59693-319-4 Cover design by Igor Valdman © 2009 ARTECH HOUSE INC. 685 Canton Street Norwood, MA 02062 All rights reserved. Printed and bound in the United States of America. No part of this book may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording, or by any information storage and retrieval system, without permission in writing from the publisher. All terms mentioned in this book that are known to be trademarks or service marks have been appropriately capitalized. Artech House cannot attest to the accuracy of this information. Use of a term in this book should not be regarded as affecting the validity of any trademark or service mark. 10 9 8 7 6 5 4 3 2 1

For Enzo, Gino, Sebastiano, Tabo, and Taip

Contents Preface

xi

  Chapter 1  Introduction

1

1.1  Scope of This Book 1.1.1  Future Developments References

1 3 3

  Chapter 2   High-Power Amplifiers

5

2.1  Applications and Specifications 2.2  Active Devices References

5 11 14

  chapter 3   Physics of Active Devices

17

3.1  3.2  3.3  3.4  3.5  3.6 

Introduction Basic Concepts of Solid-State Physics Charge Transport in Semiconductors Junctions and Barriers FETs and MESFETs Heterojunction Transistors References

17 17 25 27 37 45 53

  chapter 4   Device Characterization and Modeling

57

4.1  Introduction 4.2  Small-Signal Characterization and Models 4.2.1  MESFET and HEMT Small-Signal Model 4.2.2  HBT Small-Signal Model 4.3  Large-Signal Characterization 4.3.1  Load Pull 4.3.2  Large-Signal Parameters: AM/AM and AM/PM 4.3.3  S-Parameters Versus Bias 4.4  Large-Signal Models 4.4.1  MESFET and HEMT Large-Signal Model 4.4.2  HBT Large-Signal Model References

57 57 58 59 60 60 66 67 69 69 71 74 vii

viii

Contents

  chapter 5   Phase Noise 5.1  5.2  5.3  5.4  5.5 

Introduction Noise in Semiconductors Noise in Active Devices Phase Noise Phase Noise in Amplifiers References

  chapter 6   Technologies for Microwave Power Amplifiers

77 77 78 81 87 89 96

99

6.1  Introduction 6.2  Waveguide Components 6.3  Microwave Integrated Circuits (MICs) 6.3.1  Microwave Printed Circuits 6.3.2  Hybrid Circuits 6.3.3  Miniature Hybrid or Semimonolithic Ceramic Circuits 6.3.4  Monolithic Circuits References

99 99 100 101 102 105 108 112

  chapter 7   Power Combiners and Dividers

115

7.1  Introduction 7.2  Balanced Stages and Quadrature Couplers 7.2.1  Interdigitated Couplers 7.2.2  Branch-Line Couplers 7.2.3  Wilkinson Couplers, In-Phase and Quadrature 7.2.4  Comparison of Three Types of Microstrip Quadrature Couplers 7.3  180° Couplers 7.4  Lumped-Element l /4 Transformers 7.5  Radial Combiners 7.5.1  Microstrip Lines 7.5.2  Radial Waveguides 7.5.3  Conical Waveguides 7.6  Coupler Arrays References

115 116 117 122 125 129 130 131 132 132 134 140 142 144

  chapter 8   General Power-Amplifier Design

149

8.1  8.2  8.3  8.4  8.5  8.6 

149 149 150 155 158 163

Introduction Load-Pull Design Broadband Matching Networks Bode and Fano—Theoretical Limitations on Matching Bandwidth vs. Power Load-Line Design

Contents

ix

8.7  Large-Signal Simulation Design: Harmonic Balance 8.8  Potential Instabilities 8.8.1  Low-Level Oscillations: Rollet’s k Factor 8.8.2  Internal Oscillations 8.8.3  Parametric Oscillations 8.8.4  Bias Oscillations References

171 173 173 175 176 178 179

  chapter 9   High-Efficiency Amplifiers

181

9.1  9.2  9.3  9.4 

Introduction Class A: Output Power and Efficiency Versus Load Line Class AB: Peak Voltage Versus Conduction Angle and Load Line Overdriven Amplifiers 9.4.1  Class B: Optimal Efficiency and Class F 9.4.2  Class B: Optimal Power 9.4.3  Class A: Optimal Loading 9.4.4  Class A: Optimal Power and Efficiency 9.5  Class E 9.6  Real Devices and Circuits References

181 181 184 192 192 197 200 203 205 213 214

  chapter 10   Linear Power Amplifiers

217

10.1  Introduction 10.2  Linearity 10.2.1  Amplitude Distortion: Two-Tone IMD 10.2.2  Real IMD Curves 10.2.3  Phase Distortion: Two-Tone IMD 10.2.4  Composite Amplitude and Phase Distortion 10.2.5  Spectrum Asymmetry and Memory Effects 10.3  Design Technique: Intermodulation and Power Contours 10.4  Test Set 10.5  A Simple Quadrature Model 10.6  Behavioral Models 10.6.1  Power and Taylor Series 10.6.2  Volterra Series 10.6.3  Other Miscellaneous Models 10.7  Linearization Techniques 10.7.1  Predistortion 10.7.2  Feedforward Technique 10.7.3  Envelope Feedback 10.8  Channel Interference: ACPR, NPR, M-IMR References

217 217 218 222 226 229 230 232 236 237 240 241 242 243 243 243 250 252 253 255



Contents

  chapter 11   Special Power Amplifiers

259

11.1  Doherty Amplifier 11.2  Chireix Amplifier 11.3  Kahn EER Amplifier References

259 263 268 270

  chapter 12   Bias Circuits

273

12.1  12.2  12.3  12.4 

Introduction Passive Circuit Broadband Voltage Followers Bias Supply 12.4.1  Gain Stabilization Versus Temperature 12.5  Distributed Pulsing References

273 273 276 278 279 282 285

  chapter 13   Thermal Design

287

13.1  Introduction 13.2  Device Life Versus Temperature 13.3  Junction Temperature Measurements 13.3.1  IR Microscopy 13.3.2  Liquid Crystals 13.3.3  Electrical Parameters 13.4  Mode of Operation 13.4.1  CW 13.4.2  Pulse 13.5  Heat Sinks References

287 287 289 289 291 294 295 296 298 301 303

About the Authors Index

305 307

Preface To a large extent, this book originates from our shared experience at Microwave Power Inc. (MPI), a company dedicated to the design, development, and manufacturing of high power solid-state microwave amplifiers. We cofounded the company in 1986 and have managed it jointly for over twenty years. Working in a small company environment is certainly a good antidote against specialization—we developed a perception that many topics relevant to microwave amplifiers are of interdisciplinary nature and we have tried to convey this broad point of view in this book. While we cover all traditional power amplifier design topics, from large signal device characterization to power combining and all main design procedures, we have also given more space than usual to device physics, phase noise, bias circuits, and thermal design. Throughout the book we have tried to emphasize fundamental concepts. We think it is the only way to avoid quick obsolescence when writing on a topic that is in continuous evolution. When we show the logic and principles behind the various design techniques, we mean to encourage the reader to apply the same ideas to future designs; or when we point to the fundamental laws behind present day devices, we offer a key to understand newer ones. We hope that our emphasis on fundamental concepts and our wide range of subjects may appeal to a broad audience. For instance, while we are not specifically addressing the field of wireless communications, many of the topics covered in this book are of interest to designers of power amplifiers for base stations: in particular we are thinking of large signal device characterization, phase noise, design techniques, special amplifiers, and thermal design. We also hope that the book will be of interest as a reference or textbook in advanced microwave courses. Since we started off mentioning Microwave Power, let us take this opportunity to thank all MPI employees who have worked with us through the years and have contributed in so many different ways. We also wish to thank Tim Heyboer, the present manager of MPI, and Dr. Tibby Mazilu, Ed McAvoy, Jacob Inbar, and Glenn Nakao of AML Communications for their encouragement during the writing of this book, especially in connection with the phase noise measurements and several of the figures. Finally, we wish to acknowledge the constructive criticism and suggestions of the Artech House reviewers.

xi

Chapter 1

Introduction

1.1  Scope of This Book Amplifiers are key components of most microwave systems, and their characteristics often determine a system’s architecture. In the early days of microwave engineering, all amplifiers were based on vacuum tubes, such as klystrons, magnetrons, or traveling-wave tubes (TWT) but the tremendous progress of solid-state technology has been progressively eroding this dominant position. The advantages of solidstate devices in terms of reliability, ruggedness, characteristics of operation, size, and cost are such that, whenever a solid-state alternative becomes available, it is quickly adopted by the system designer. In a plot of power versus frequency, as shown in Figure 1.1 for narrow-band amplifiers, the progress of solid-state technology through the years can be visualized as a moving boundary that encloses an increasingly wide region, while the vacuum tubes’ domain is progressively pushed toward higher and higher frequencies and powers. The gray areas marked 1989 and 2009 represent our uncertainty in the position of this moving boundary in these two years. Also shown in the figure is the region of powers and frequencies characteristic of handheld cell phones. Any plot of this type can be only approximate and general, at best. There are always going to be special cases related to cost, specifications, or legacy that will move a tube into solid-state space and vice-versa. This book covers only solid-state power amplifiers (SSPA) and focuses on the highest powers reachable with solid-state technology. This may mean a few watts for multioctave bandwidths or hundreds of watts for narrow bands. As shown by the area marked in Figure 1.1, we might define our focus as “whatever power levels were beyond reach 20 years ago.” Naturally, this is not to say that design principles and techniques discussed in this book would not apply to lower powers, but rather that topics such as power combining and heat management will receive more than the usual share of attention. The choice of examples will also reflect our area of interest. The applications we have in mind are mostly in radars, electronic warfare, telecommunication equipment, and special test systems. A large body of literature is already available on amplifiers for cell phones and similar wireless applications [1–6], so we will not dwell on them; however, this book certainly applies to the high-power amplifiers used in base stations. We have also made the choice of concentrating on compound semiconductor devices. We feel some excellent books, reviews, and product literature [7–9] already cover the relatively low-frequency, high-power Si MOS transistors that have made such impressive progress in recent 



Introduction

Figure 1.1  This book’s area of interest is marked by a heavy line on top of a graph representing the progress of solid-state power amplifiers vs. vacuum tubes over 20 years. Also shown are typical frequencies and powers used in cell phones.

years, while there is not much new to add on Si bipolars [10–12]. They were the first transistors to reach microwave frequencies back in the 1960s. They are still quite popular because of their low cost and good phase-noise characteristics, but their use in amplifiers, especially at high-power levels, does not extend much beyond 4–5 GHz. The ability of a semiconductor to respond to higher frequencies is mostly related to electron velocity, and several semiconductor materials are known to have both higher mobility and higher peak velocities for electrons than Si. Among them, GaAs has been the most successful so far. This is due to a combination of factors. Certainly its well-developed technology, driven by the large market in the optical field (as an LED and laser material) was a major element in its early success. Another favorable factor is its relatively large bandgap leading to a fairly high intrinsic resistivity. This makes it suitable (though not optimum) as a substrate for microwave propagation, and it was therefore a key to the success of monolithic microwave integrated circuits (MMICs). However, new materials are now gaining ground, and we will review some of the most promising results. Considering its title, this book covers an unusual amount of solid-state and device physics, possibly too much for some readers. To make life easier for them, we have concentrated most of this subject in Chapter 3, so that whoever is either not interested or already knowledgeable can easily skip it. Our emphasis reflects our experience that understanding solid-state physics is a major asset in the effective utilization of a power microwave device. A solid-state device used in a power amplifier often exploits to the limit all the characteristics of a given material and technology. Knowing these boundaries, and the physical reasons behind them, is essential for a sound and reliable design. Finally, we feel a microwave designer is faced with a continuous stream of new devices, technologies, and materials, but, actually, the basic principles behind them are not that numerous. A grasp of these fundamental ideas will help in finding logic and continuity behind the variety.

1.1  Scope of This Book



In terms of frequencies, we will address the whole range from 1 to 50 GHz, but will concentrate mostly on broadband applications and higher frequencies (as long as significant power is available). These seem to us the most challenging areas for future development. Although we have tried to justify some of our choices on a rational basis, there is no denying that they also reflect our professional interests. We feel that these are the topics where we can offer more original insight. 1.1.1  Future Developments

The demand for higher solid-state power is very strong in all fields of application, and the general trend is always toward higher powers at higher frequencies. For solid-state amplifiers, there are two main possibilities: improved combining techniques and higher power devices. Most SSPAs, and certainly all the highest-power ones, use some kind of power combination. We believe new low-loss combining techniques are very promising. The main advantage of increasing power output this way is the ability to distribute power dissipation more effectively. As an example, we will see in Chapter 7 that power amplifiers based on planar radial combiners are built with power devices evenly distributed around the periphery of the combiners, and heat is very effectively distributed. Today, many low-loss, high-power combiners introduce limitations in the bandwidth, but we expect new and improved techniques will progressively lead to efficient broadband combining, while maintaining the important thermal advantage. In terms of device power, the greatest hopes come from the new wide-gap semiconductors, especially GaN. When the active layers of GaN are grown on SiC, the device takes advantage of the excellent heat conductivity of the substrate, and power outputs five times as high as those of present-day GaAs devices may be within reach. The area is developing so fast that any reported result is quickly obsolete. We have tried to overcome this problem by stressing basic principles in the hope that the reader will be able to apply them also to devices and materials not yet available today.

References   [1] Cripps, S. C., RF Power Amplifiers for Wireless Communications, Norwood, MA: Artech House, 1999.   [2] Cripps, S. C., Advanced Techniques in RF Power Amplifier Design, Norwood, MA: Artech House, 2002.   [3] Sowlati, T., et al., “1.8-GHz Class E Power Amplifier for Wireless Communications,” Electronics Letters, Vol. 32, September 1996, pp. 1846–1848.   [4] 9th European Conf. on Wireless Technology, Manchester, England, September 10–12, 2006.   [5] Weitzel, C. E., “RF Power Amplifiers for Wireless Communications,” Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 24th Annual Technical Digest, October 20–23, 2002, pp. 127–130.   [6] 2008 IEEE Radio and Wireless Symposium, January 22–24, 2008.   [7] Baliga, B. J., Silicon RF Power Mosfets, Singapore: World Scientific Publishing Company, 2005.



Introduction   [8] Dye, N., H. Granberg, and L. Leighton, Radio Frequency Transistors: Principles and Practical Applications, Woburn, MA: Butterworth-Heinemann, 2001.   [9] Freescale, RF LDMOS Power Transistors, http://www.freescale.com, last accessed April 20, 2009. [10] M/A-COM, http://www.macom.com, last accessed April 20, 2009. [11] Allison, R., “Silicon Bipolar Microwave Power Transistors,” IEEE Trans. on Microwave Theory and Techniques, Vol. MTT-27, 1979. [12] Rudiakova, A., and V. Krizhanovski, Advanced Design Techniques for RF Power Amplifiers, The Netherlands: Springer, 2006.

Chapter 2

High-Power Amplifiers 2.1  Applications and Specifications In designing a microwave system, the specification of the power amplifier is generally one of the most critical steps: the power amplifier is often the most expensive component, and its characteristics leave a clear footprint on the whole system. This is especially true when choosing between a traveling wave tube (TWT) and a solidstate power amplifier (SSPA), since the properties of the two types of amplifiers are extremely different. Even if we consider only the solid-state option, however, there is much more to a power amplifier than its output power and frequency of operation. Depending on the application and the type of system, many different properties can become important or desirable. Some of them may weigh substantially on the cost of the system and therefore represent a clear economic trade-off, but others may be available at very low cost by making the correct choices. Power output, gain, frequency of operation, bandwidth, and cost are almost always included even in the shortest specification list. Other characteristics are more significant in specific cases: for a high power amplifier (several watts and above), thermal management is typically a major issue; efficiency, weight, and size are most critical in an airborne application; and reliability (which is always important) becomes foremost in a space application. As we will see later in more detail, many modern communications systems require high linearity and low phase noise. Finally, the time required to develop an amplifier with specific characteristics is always an important cost component, but sometimes it may become a dominant parameter, for example, when the amplifier is timed in conjunction with a particular system. This chapter will briefly touch upon the complex issue of the relationship between the power amplifier and the overall system. Occasionally, the relationship is so tight that the only practical possibility is designing them both at the same time, but more often a two-way relationship develops. Sometimes it is the amplifier manufacturer who responds to specific system requests by modifying some characteristics or adding new features, and other times it is a new amplifier development which makes a different or improved system feasible. By considering the effects of some of the amplifier properties on the system, we intend to stress the importance of an optimum match between specifications and application. At the same time, we hope to clarify our choice of topics for the following chapters and their relative emphases. Let us then look at a few specific issues. One of the most important aspects of a system design drastically affected by the power amplifier is heat management. This is especially true when using solid-state devices. First, transistors are much less efficient than tubes. In addition, in an SSPA, the high power output is achieved by





High-Power Amplifiers

combining several solid-state devices in parallel, and each level of combination contributes additional losses. On the other hand, both reliability and power output decrease substantially if the temperature of operation is increased. Consider the case of a typical 100W amplifier for a transmitter station in the popular 14–14.5-GHz radio link [1]. All but 100W of its DC power consumption, which may be close to 2 kW, has to be removed from the active devices, where most of the heat is generated. At the same time, the devices need to remain as cool as possible. Indeed, for every increase of only 10°C in device temperature, the RF power output typically decreases by as much as 5%, and the life expectancy by almost a factor of 2. Heat removal is generally accomplished by bulky forced-air heat sinks: this approach may be acceptable in a commercial ground station, but may be difficult to accommodate in other cases, such as in an airborne application. A careful thermal evaluation, as early as possible in the design cycle, is clearly a very important part of both the amplifier specification and the system design (as will be discussed in more detail in Chapter 13). But even using fairly sophisticated heat sinks, these may contribute well over one-half of both weight and volume to the overall amplifier. The problem of heat transfer is magnified by the need to maintain the temperature drop between heat source and heat sink as low as possible; introducing new devices capable of efficient operation at higher temperatures would considerably ease the problem. This is one of the main factors behind the development of semiconductors with larger energy gaps, such as GaN and SiC, which are already showing excellent results and will be reviewed in Chapter 3. Finally, this example also illustrates the significant role of losses, not only in the active devices, but also in all other elements, which are often treated as “ideal” in low power applications, but cannot be considered so at high power levels. Not only do losses in the various stages of combination contribute, of course, directly to the heat to be dissipated, but also, the higher the loss, the larger the number of devices required to achieve the desired power. In the particular amplifier mentioned above, an additional loss of only 0.8 dB in the output combiner is enough to require an increase in the required number of active devices from ten to twelve. All the other stages have to be scaled accordingly, and, in practice, the 20% increase in the devices directly translates into a similar increase in DC power consumption. As we will see in Sections 6.2 and 7.5, the remarkably low loss of waveguides (especially when compared to microstrips) has made them the favorite structure for high-power combiners. One drawback is their limited bandwidth, and this is indeed a major drawback for a number of very important applications, such as instrumentation and electronic warfare, where there seems to be no limit to the desired bandwidth. Not all applications require a broad band but, for those that do, the trade-off between power and bandwidth often becomes the dominant issue. This is exemplified in Figure 2.1 by a selection of commercial products [2]. The figure is divided by shaded gaps in three regions, each corresponding to a different architecture. As sketched in Figure 2.2, a typical layout for an SSPA comprises a gain stage, which is essentially a low-power amplifier providing most of the gain, followed by the driver and output stages. Both of these are generally structured as combinations of simple amplifying modules, which may be either microwave monolithic integrated circuits (MMICs) or equivalent ceramic circuits. We will see in Section 8.6, when discussing design issues, that the product of power and bandwidth can be viewed

2.1  Applications and Specifications



Figure 2.1  A selection of commercial power amplifiers. For each model, the first two numbers of the label define the frequency range in GHz, followed by the saturated output power in dBm.

Figure 2.2  An example of a block diagram for a high-power amplifier.



High-Power Amplifiers

as characteristic of a given technology. In many ways, it could be seen as a measure of its performance. In other words, once this choice has been made, the higher the power, the more difficult it is to achieve a large bandwidth. Therefore the gain stage, which is at low power, is generally designed with an ample frequency response, so as not to limit the overall band, which is then determined by the combiners and the output circuits (with the driver stage or stages contributing sometimes to a lower degree). Generally speaking, simpler combinations and lower power outputs will yield larger bandwidths. The two examples shown in the lowest region of Figure 2.1 are the result of a single combination in microstrip of broadband GaAs MMICs. In the central band, we see several higher-power devices with smaller, but still considerably broad, bandwidths. These are the result of more complex, multiple combinations using coaxial, stripline, and microstrip combiners. For the active modules, some use MMICs, and some use semimonolithic ceramic circuits. The first technology is favored at higher frequencies, while the latter is favored at lower frequencies. Both are capable of good power/bandwidth products, but each has its own features, as we will see in more detail in Chapter 6. The highest power levels, represented in the upper band of the chart, are achieved mostly by using radial waveguide combiners. Their low loss allows the efficient combination of a large number of power modules. For the standard communication bands, these are mostly internally matched GaAs devices; otherwise they are microwave integrated circuits. The band is generally limited here by the combiner. We will see in Chapter 7 how some recently proposed coaxial approaches may be able to relieve this limitation. Meanwhile, in terms of specifications, a glance at this figure will suffice to indicate that bandwidth at high power levels is a very valuable commodity. In a limit case, in an application with two distinct frequency bands of interest, unless they were really close (say within 10%), it would be probably cheaper to purchase two amplifiers than a single one covering the two bands. Let us now consider the issue of linearity: this is especially important in many communications systems where a linear response is often required in order to maintain low intermodulation or to minimize the bit-error rate. The specific way the amplifier distorts the input signal, in both amplitude and phase, then becomes a key parameter in the design of the amplifier, as well as a critical part of its specification. The linearity of an amplifier has been often described in terms of the compression or saturation curve, that is, the plot of output versus input power. When the amplitude of the input signal is low, there is a linear relationship between the input and output signals, and the gain is constant. As the input signal is increased, the gain most often decreases (though intermediate regions of gain expansion are possible). The output power saturates and eventually does not change anymore: the amplifier has reached full saturation. Often, the value of the output power where the gain has dropped by 1 dB with respect to the small-signal gain (P1dB) is taken as an indication of the amplifier’s distortion. However, the compression curve and P1dB are only related to amplitude, and not to phase distortion. In Chapter 10, we will discuss how both amplitude and phase distortion contribute to the intermodulation distortion (IMD) effect, which introduces spurious signals in the amplifier response. We will then argue that the actual measurement of the IMD (or an equivalent test) should be used to specify the linearity performance.

2.1  Applications and Specifications



From the design point of view, the linearity of any amplifier, but particularly a power one, is critically dependent both on the characteristics of the active device and on the circuit impedance. A designer will need a complete characterization of the device and a good understanding of its physical properties to draw the optimum performance from any selected device. We have suggested that one of the factors affecting the linearity of an amplifier is the type of active device on which it is based. This is certainly true for the noise characteristics as well. If the phase noise of an amplifier is plotted as a function of the frequency offset from the carrier, one can distinguish two regions: at low frequency, the noise is quite high and decreases approximately as 1/f, while at higher frequencies it is basically white, or independent of frequency. The crossover between the two regions (called corner frequency), takes place anywhere between a few Hz and several MHz depending on the devices used, as well as the amplifier structure. The example shown in Figure 2.3 is sketched from an actual measurement taken on a 16W, 1–4-GHz amplifier based on GaAs FET technology. This data will be discussed in more detail in Chapter 5. The portion of the spectrum near

Figure 2.3  Phase noise vs. frequency offset from the carrier for a power amplifier based on GaAs technology.

10

High-Power Amplifiers

the carrier almost always originates from the upconversion of 1/f noise present in the active devices, while the flat region away from the carrier may have different origins, depending on the amplifier characteristics. It may result from upconversion of the devices’ white noise, or it may originate from thermal noise generated in the resistors. For a power amplifier, the white noise is seldom critical. The gain of the amplifier is typically adjusted so that the operating input power is quite high, relative to the noise floor, so that the reduction in signal-to-noise ratio of the system due to the power amplifier is generally negligible. Should this not be the case, adding a broadband, low-noise stage (typically based on HEMTs) would be a simple and inexpensive solution. Therefore, we will not dwell on this type of noise and refer to the ample literature [3–5]. On the other hand, a high phase noise near the carrier is not easily corrected. Not all systems are affected by phase noise, but its significance is increasing in many important applications, wherever the phase carries information; to give a few examples, it may limit the spacing of closely adjacent channels in a communication system, affect the sensitivity of modern radars, which detect both phase and amplitude, or introduce errors in digitally modulated signals. Given the growing interest and still open debate on phase noise, the whole of Chapter 5 is devoted to it. Finally, we will mention an example of the flexible boundary between system and amplifier design. Pulsing the RF signal is a required feature in pulse radars, and it is used in many measuring systems to improve their sensitivity. In fact, whenever a measurement is performed by transmitting and receiving a signal, the ability to turn off the transmitter during reception greatly improves the signal-to-noise ratio. Traditionally, pulsing was part of the system design, and it was most often performed by turning off and on the RF signal. However, if the power amplifier is based on FETs or HEMTs, it operates well only in class A or AB, and the device is not fully turned off when the RF is brought to zero. For optimum performance, its DC bias needs to be switched, which is not a trivial task when the current amounts to several tens or even hundreds of amperes. Also, since modern systems require faster and faster switching, the pulsers need to be kept as close as possible to the devices. As discussed in Chapter 12, a much improved overall performance is then obtained by including the pulsing feature within the power amplifier. The pulsing characteristics then become a part of the amplifier specifications. Not only the shape of the RF pulse, but also the stability of the amplifier from pulse to pulse may considerably affect the system performance, and it needs to be carefully specified. In reviewing some of the main characteristics of a power amplifier, we have not discussed gain, which is certainly one of the main specifications but seldom involves any complex trade-offs. Like white noise, gain can be adjusted inexpensively and easily by adding, replacing, or removing a stage from the preamplifier section. Adding 3 dB of gain might increase the cost of a unit by a few percent, as compared to almost doubling it when 3 dB are added to the saturated power. The use of MMICs, which are often fairly high gain blocks, may sometimes pose a challenge in adjusting the gain to a specific value, but these are issues which belong more in a general low-power amplifier discussion. The purpose of this survey, by no means exhaustive, is to highlight topics which are more relevant at high power, and exemplify the strong interaction between the power amplifier specifications and the system’s application.

2.2  Active Devices

11

2.2  Active Devices In this brief review of the most important active microwave devices, we will confine ourselves to transistors, in particular to those capable of good performance at high frequency. Diodes, especially Gunn, are still used in many low-power and low-cost applications, even at very high frequency, but transistors generally offer much better performance, and the choice is now so ample as to accommodate the widest range of requirements. Boundaries are always difficult to draw. Our emphasis on higher frequencies and compound semiconductors has led us to neglect LDMOS, a device that is playing a dominant role in power amplifiers for base stations [6]. It is still a member of the large FET family, however, and much of the general discussion of FETs in Chapter 3 applies to LDMOS as well. One of the main technological advances behind the proliferation of compound semiconductor devices in recent years is the advent of molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD), sometime in the late 1970s or early 1980s. These technologies enable the deposition of high-quality crystalline films of different materials on top of each other, with excellent composition and structure control. A reasonable matching of the crystalline structure is generally required, but a fair amount of mismatch may be tolerated, and even mismatches are sometimes used to advantage in the so-called strained layers. This allows an enormous amount of experimentation with new materials and structures, and dramatically reduces the development time for a new device, especially when a new material is involved. Three-terminal active devices can be classified in two broad groups: bipolar transistors (BTs) and field-effect transistors (FETs). The first is basically a current amplifier, and the controlling element is the pn (or np) junction. Both holes and electrons participate in the charge transport, and the flow of current is vertical, that is, perpendicular to the junction itself, the substrate, and any interface created by epitaxial growth. For this reason, bipolars generally do not require extremely fine photolithography. Their high-frequency performance is affected more by the ability to control the junctions’ thicknesses and positions than by the pattern of the electrodes. They can typically provide high currents. Also, they are almost immune to some of the sources of 1/f noise (those taking place at the substrate interface or at the surface). As a result, they offer a reduced frequency corner and low phase noise. On the other hand, FETs are termed horizontal, because the current flows parallel to the substrate and the controlling element. This is either a junction or a metalsemiconductor barrier (including metal-oxide-semiconductor) and is crossed by currents only during breakdown. FETs are voltage-controlled, rather than currentcontrolled, and only majority carriers (generally electrons) are involved in the current transport. Some time ago, one would have said that a material with low-hole mobility (including most III-V compounds) could be used only for FET-type devices. The advent of MBE and MOCVD, with the ability to pick and choose materials for emitter, base, and collector, and the development of heterojunction bipolar transistors (HBTs) have certainly changed the situation. Still, for a low hole mobility material, an FET structure is likely to be the first choice. Because all the current flow is exposed to fluctuations due to injection of charges from the substrate and the surface region, all FET structures are prone to 1/f noise, albeit to different degrees.

12

High-Power Amplifiers

Silicon bipolar junction transistors (BJT) were the first solid-state three-terminal devices to reach microwave frequencies back in the early 1960s. Since silicon was already a well-developed material, the devices reached quickly their full potential, which was limited by the fundamental characteristics of the material itself. The main properties affecting electron device performance for a number of semiconductors are compared in Table 2.1 [7, 8]. Some of the parameters listed in the table have a fairly wide range of values. We have tried to select numbers corresponding to operational device conditions, namely room temperature and a typical donor density of 1017/ cm³. For SiC, we have used parameters corresponding to the 4H crystal structure, which is presently the preferred form, due to its somewhat higher electron mobility. For GaAs and GaN, we have included the typical mobilities for a two-dimensional electron gas (2DEG), which apply to HEMT-type devices and will be discussed in Chapter 3. Desirable properties include: ·

· · ·

A large energy gap, which generally implies an ability to withstand higher internal electric fields and a lower sensitivity of the material’s parameters to temperature variations, as well as improved radiation resistance; A low dielectric constant, leading to lower capacitances per unit area and therefore higher frequencies and larger RF currents; High thermal conductivity, especially important for high-power devices, since it characterizes the ability to extract heat from the active area; High electric field breakdown, typically related to the energy gap.

As far as the electron velocities and both mobilities are concerned, their importance depends on the type of device. For FETs only the electron parameters are important, and which of the three ends up determining the frequency performance of the device depends on the magnitude of the electric field in the most critical transit region. In general, devices fabricated with wider gap materials would use higher voltages and higher electric fields, so that the saturation velocity would tend to be the dominant parameter. By comparing silicon to the other semiconductors in the table, we can see that its weakest point is the low electric field for breakdown, combined with the relatively low mobilities. In fact, since the electric fields are limited by breakdown, the mobility (rather than the saturation velocity) determines the frequency performance. These issues will be discussed in more detail in Chapter 3. At the time when Si appeared to be reaching its limits as a microwave device material, some of the III-V compounds, notably GaAs and InP, were already well Table 2.1  Semiconductor Properties Parameter Energy Gap Relative Dielectric Constant Thermal Conductivity Breakdown Electric Field Peak Electron Velocity Saturated Electron Velocity Electron Mobility

Units eV — W/K cm MV/cm 107 cm/s 107 cm/s cm2/Vs

Si 1.12 11.9 1.5 0.3 1 1 1,500

Hole Mobility

cm2/Vs

450

GaAs 1.43 12.5 0.54 0.4 1.5 0.6 5,000

InP 1.34 12.4 0.67 0.45 2.5 2 4,000

SiC 3.2 10 4 3.5 2 2 500

GaN 3.4 9.5 1.3 3.3 2 2 400

150

Low

Low

(8,000 2-DEG)

400

(1,500 2-DEG)

2.2  Active Devices

13

developed as optical materials, due to their direct bandgap, which made them suitable for lasers. Both of them were also known in the microwave community because of the Gunn effect, and both had remarkably higher mobilities than silicon. Because of the rather low hole mobility an FET-like structure would be the natural device to try. There are probably two main reasons why GaAs was more successful than InP, despite its lower electron saturation velocity. Its technology was far more advanced and its mechanical properties less forbidding (as compared to silicon). Process lines designed for silicon could barely handle GaAs (albeit with some breakage). InP was far too fragile and delicate. GaAs FETs dominated the microwave scene for many years. The development of the high electron mobility transistor (HEMT) and all the subsequent varie­ ties, most notably the highly successful pseudomorphic type (PHEMT), blended in smoothly and extended the GaAs dominance further, both in frequency and power, at least in terms of substrate material. In fact, these devices are all based on heterostructures containing other III-V compounds as well [9, 10], but, from the user’s point of view, they are all FET-like devices that operate in a basically similar way, except with much more brilliant performance in terms of noise, power, and frequency. The use of heterostructures can avert most of the weaknesses of the GaAs material. As an example, the channel material in a PHEMT is actually GaInAs, where the introduction of indium brings the peak electron velocity very close to InP. But since all these structures share a GaAs substrate, the main common weak point is the low thermal conductivity. A high-power microwave device, especially of the FET variety, produces a large amount of very concentrated heat that needs to be spread out and dissipated through the substrate. Despite the introduction of integrated heat sinks and through vias [11], at some time in the 1990s it became apparent that the power density of the GaAs device family was thermally limited. Even when the devices are optimized for high temperature performance, their most important parameters, such as gain, saturated power, and maximum frequency of oscillation are thermally sensitive [12, 13], and therefore the maximum operating channel temperature is severely limited by both reliability and performance considerations. Thus, poor thermal conductivity is especially damaging. The search for improved heat transport and high temperature performance has called attention to wide bandgap semiconductors [14, 15], represented in Table 2.1 by SiC and GaN. In addition to an excellent saturation velocity, both materials show a high electric field for breakdown and relatively low dielectric constant, as expected from the large energy gap. Mobilities are relatively low, but in power devices operating with high internal fields, the frequency response is dominated by the peak and saturation velocity. Besides, the GaN/AlGaN heterojunction enjoys an especially favorable combination of relatively good electron mobility (reported in Table 2.1 as 2-DEG) and unusually high carrier density [16, 17]. This is one of the main factors responsible for the superior frequency performance of GaN HEMTs and the impressive progress of GaN technology [18]. Unfortunately, the characteristics of this two-dimensional electron gas are not as stable with temperature as the GaN material itself, but there is still a significant improvement over GaAs PHEMTs [19]. SiC can also offer an unusually good thermal conductivity, which is shared by GaN devices when they are grown on SiC substrates [20, 21]. In fact, there is presently no developed technology to grow GaN crystals, but good quality films can be

14

High-Power Amplifiers Table 2.2  Device Summary Acronym

Type of Device

Si BJT GaAs HBT GaAs FET GaAs PHEMT GaN HEMT SiC FET

Bipolar Bipolar Field effect Field effect Field effect Field effect

Max Freq. for Power Amps GHz 10 20 15 50 >50 10

Fmax GHz 50 200 100 200 200 60

NF (at GHz) dB 2 (2) 3 (10) 1 (10) 1 (30) 1 (30) 3 (2)

Noise Corner Hz 5–50k 1–50k 1–10M 1–10M 1–10M 100k–1M

Power Density (at GHz) W/mm 1.5 (5) 4 (10) 1 (10) 1.5 (30) >7 (30) 5 (10)

grown on sapphire, SiC, or even plain Si (albeit with the introduction of a transition layer to decrease the stress). Some of the best results so far have been obtained on SiC, but, certainly, Si offers considerable economic advantages: There might a place for both technologies. Summarized in Table 2.2 are the main properties of some of the leading microwave transistors for high-power and high-frequency applications. Even though we have not included transistors used mostly at frequencies lower than about 4–5 GHz, we have made an exception for the GaAs HBT because it also represents a viable alternative at higher frequencies [22], especially in applications requiring low 1/f noise. We have tried to select realistic numbers that could be obtained by using one of the several available foundries. Much higher values have been reported, for instance, for the highest frequencies of oscillation, but we have selected numbers compatible with a power technology. In the same vein, we have not included InP devices. Their high-frequency performance has no competition, but the power is still relatively low [23, 24]. For heterojunction devices, we have used GaAs and GaN as labels, even though several III-V compounds are involved in each device. The noise parameters for the wide-gap devices are still tentative. In this respect, GaN seems to behave very much like GaAs, while there is some interesting indication that SiC may have an anomalous, and rather favorable, 1/f noise behavior [25–27]. But clearly the most striking feature reported in the table is the power and frequency performance of the GaN device. After the Si and GaAs seasons, there is no question that the time for GaN has come.

References   [1] Specific numbers are taken from the commercial amplifier C140145-50 manufactured by Microwave Power Inc.   [2] Sechi, F. N., and M. Bujatti, “Broadband High Power Amplifiers for Instrumentation,” 67th ARFTG Conf. Proc., June 16, 2006, pp. 61–67.   [3] Fukui, H., Low Noise Microwave Transistors and Amplifiers, New York: Wiley, 1999.   [4] Virdee, B. S., B. Y. Benyamin, and A. S. Virdee, Design of Broadband Amplifiers, Norwood, MA: Artech House, 2004.   [5] Howard, R. M., Principles of Random Signal Analysis and Low Noise Design, Wiley, 2002.   [6] van Rijs, F., “Status and Trends of Silicon LDMOS Base Station PA Technologies to Go Beyond 2.5-GHz Applications”, Radio and Wireless Symposium Digest, pp. 69–72.

2.2  Active Devices

15

  [7] Levinstein, M., S. Rumyantsev, and M. Shur, (eds.), Handbook Series on Semiconductor Parameters, Vol. 1/2, London: World Scientific, 1996, 1999. Also see: http://www.ioffe. ru/SVA/NSM/Semicond, last accessed on April 22, 2009.   [8] Trew, R. J., “SiC and GaN Transistors—Is There One Winner for Microwave Power Applications?”, IEEE Proc., Vol. 90, No. 6, 2002, pp. 1032–1047.   [9] S. Tiwari (ed.), “Compound Semiconductor Transistors: Physics and Technology,” New York: IEEE Press, 1993. [10] Schwierz, F. “Microwave Transistors—The Last 20 Years,” 3rd IEEE Intl. Caracas Conference on Devices, Circuits, and Systems, Cancun, Mexico, March 15–17, 2000, pp. D28/1–D28/7. [11] Ishikawa, T., et al., “A High Power GaAs FET Having Buried Plated Heat Sink for High Performance MMICs,” IEEE Trans. on Electronic Devices, Vol. 41, 1994, pp. 3–9. [12] Wurfl, J., “Recent Advances in GaAs Devices for Use at High Temperatures,” IEEE High Temperature Electronic Materials, Devices and Sensors Conf., San Diego, CA, Feb. 22–27, 1998, pp. 106–116. [13] Chiu, H., et al., “AlGaAs/InGaAs Heterostructure Doped Channel FETs Exhibiting Good Electrical Performance at High Temperatures,” IEEE Trans. on Electronic Devices, Vol. 48, 2001, pp. 2210–2215. [14] Yoder, M. N., “Wide Bandgap Semiconductor Materials and Devices,” IEEE Trans. on Electronic Devices, Vol.43, 1996, pp. 1633–1636. [15] Zolper, J. C., and K. Shanabrook, (eds.), “Special Issue on Wide Bandgap Semiconductor Devices”, IEEE Proc., Vol. 90, No. 6, June 2002, pp. 939–1085. [16] Zhang, Y., et al., “Charge Control and Mobility in AlGaN/GaN Transistors: Experimental and Theoretical Studies,” J. Appl. Phys., Vol. 87, 2000, pp. 7981–7987. [17] Ambacher, O., et al., “Two-Dimensional Electron Gases Induced by Spontaneous and Piezoelectrical Polarization in Undoped and Doped AlGaN/GaN Heterostructures,” J. Appl. Phys., Vol. 87, 2000, pp. 334–344. [18] Kao, M.Y., et al., “High-Efficiency and Low-Noise AlGaN/GaN HEMTs for k- and KaBand Applications,” CSMANTECH Conference Digest, May14–17, 2007, paper # 04a. [19] Nuttinck, S., et al., “Thermal Analysis of AlGaN-GaN Power HFETs,” IEEE Trans. on Microwave Theory and Techniques,Vol. 51, 2003, pp. 2445–2452. [20] Milligan, J. W., et al., “SiC and GaN Wide Bandgap Device Technology Overview,” 2007 IEEE Radar Conference, Boston, April 17–20, 2007, pp. 960–964. [21] Cappelluti, F., et al., “On the Substrate Thermal Optimization in SiC-Based BacksideMounted High-Power GaN FETs,” IEEE Trans. Electronic Devices, Vol. 54, 2007, pp. 1744–1752. [22] Couturier, A. M., et al., “A Robust 11W High Efficiency X-Band GaInP HBT Amplifier,” 2007 IEEE MTT-S Intl. Symp., Honolulu, HI, June 3–8, 2007, pp. 813–816. [23] Sano, E., and K. Inafune, “Recent Progress in Devices and Circuit Technologies for mmWave Applications”, 19th IEEE Intl. Conf. on Indium Phosphide and Related Materials (IPRM), Matsue, Japan, May 14–18, 2007, pp. 523–526. [24] Deal, W. R., et al., “270-Ghz MMIC Amplifier Using 35-nm InP HEMT Technology,” IEEE Microwave and Wireless Comp. Lett., Vol. 17, 2007, pp. 391–393. [25] Rumyantsev, S. L., et al., “Generation and Recombination Noise in GaN/AlGaN Heterostructure Field Effect Transistors,” IEEE Trans on Electronic Devices, Vol. 43, 2001, pp. 530–534. [26] Levinshtein, M. E., et al., “Low Frequency and 1/f Noise in Wide-Gap Semiconductors: Silicon Carbide and Gallium Nitride,” IEE Proc. on Circuits, Devices and Systems, Vol. 149, Feb. 2002, pp. 32–39. [27] Levinshtein, M. E., et al., “Low Frequency Noise in 4H SiC,” J. Appl. Phys., Vol. 81, Feb. 1997, pp. 1758–1762.

Chapter 3

Physics of Active Devices 3.1  Introduction As we discussed in the previous chapter, most characteristics of a power amplifier are affected by the active devices used. Today, especially at the highest frequencies and powers, these are almost always transistors, and the most likely choice is a member of the large family of field effect transistors (FETs). In this chapter, we will review their operation and will dwell in particular on some of the most successful members of the family. There are, however, particular applications where the properties of a bipolar device—most significantly, the low phase noise—are a definite advantage. Therefore, we will also include a brief introduction to the newest member of this group, the heterojunction bipolar transistor (HBT). Even in a very brief and qualitative review as the one we are attempting here, there are a number of basic concepts of solid-state physics that cannot be avoided. While we could not possibly cover them here, we hope a short summary will point the reader in the right direction. There are plenty of good books available at all different levels [1–5]. It goes without saying that readers familiar with the subject are encouraged to skip Section 3.2.

3.2  Basic Concepts of Solid-State Physics One of the fundamentally new concepts introduced by quantum mechanics is the dual aspect particle/wave of both electrons and photons. Which of the two aspects is dominant depends on whether the position or the momentum (which is associated with the wavelength) is better defined. The two variables are related to each other by the uncertainty principle, whereby the uncertainty in the position of a particle is inversely proportional to the uncertainty in its momentum. In general, we can think of a particle as a wave packet: A well-defined position in space (a sharp pulse, in the limit of a single point, or, in another word, a particle) implies a very broad range of wavelengths, and conversely a single wavelength, or a wave, implies a completely undefined position. In a similar way, a short RF pulse corresponds to a very broad frequency range. The mathematical formalism is very similar, although the physical meaning of the wave is different: the particle is represented by a state function that determines the probability of every property related to the particle. In particular, the square of its modulus determines the probability of a particle to be in a given position in space. Newton’s laws (or, more directly, the Hamiltonian formulation of classical mechanics) are replaced by Schrödinger’s equation:

∇2 Ψ + (2m/¯h2 )(E − V)Ψ = 0

(3.1) 17

18

Physics of Active Devices

where Y is the state function, m is the mass of the particle, − h is a constant (the reduced Planck constant), E is the particle’s energy, and V is its potential energy. We will generally find that solutions are possible only for specific, discrete values of a set of so-called quantum numbers, which define the possible states of the particle. A basic principle of quantum mechanics, known as the Pauli exclusion principle, states that no two electrons can occupy the same quantum state at the same time. In other words, we can have only one electron for each allowed combination of quantum numbers. The significant quantum numbers depend on the physical situation. In the particularly important example of a spherically symmetric Coulomb potential (the hydrogen atom problem), the quantum numbers, traditionally labeled as n, l, m, and s, specify, respectively, the energy, angular momentum, magnetic moment, and spin of the electron. There are only two possible spin orientations (up and down), so we can have two electrons for each set of values of n, m, and l. These three numbers are related to each other by two simple rules: (1) For a given n, the number l can only take the values 0, 1, 2…up to n–1; and (2) for every value of l, m can only take 2l+1 values: 0, ±1, ±2…up to ±l. Pauli’s principle forms the basis for the periodic table of the elements. Electrons revolve around the nucleus in discrete shells characterized by a value of the quantum number n, and each shell can accommodate only a limited number of electrons, as specified by the above rules. It should be mentioned that, while in the hydrogen atom the energy is fully defined by n, when we have more than one electron, their interaction will lead to a splitting of the energy into sublevels, so that the quantum number n will not completely identify the energy anymore. As the number of electrons increases, we progressively fill the shells. A full shell acquires a particularly uniform and stable configuration [6]. When atoms are brought together to form a solid body, the outer shells start interacting with each other, and there is a tendency for electrons of one atom to occupy states available in the other atom. To a large extent, the interaction is limited to the outer shell, so that we can generally think of a positive ion core, including all shells but the last one, and a negative electronic distribution surrounding it. Two opposite forces operate: attraction between the positive ions and the negative electrons on one side and repulsion between similar charges on the other one. The final arrangement at equilibrium depends on the strength of the charges and on the electron distribution. Atoms arrange themselves so that the electrons can reach as close as possible towards the positive ion cores. In the case of a single electron on the outer shell, we typically arrive at a situation where a regular array of closely packed positive ions is surrounded by an almost uniform distribution of electrons (each donated by one of the original atoms), which moves around almost freely. This is the case with a metal such as copper, silver, or gold. A similar result is generally reached when we have two electrons on the outer shell. In fact, metals generally originate from these two situations. The sea of electrons is free to move around under the influence of an electric field and is responsible for the high electrical conductivity characteristic of metals. When we speak instead of a semiconductor, we refer to a crystal where only relatively few electrons are available to conduct current. Silicon and germanium are the only single-element semiconductors. Both belong to the IV column of the periodic system; hence they have four electrons in the outer shell or, conversely,

3.2  Basic Concepts of Solid-State Physics

19

need four more electrons to reach a full shell. In this case, a very stable condition is achieved when each electron in the outer shell of one atom pairs up with an electron of opposite spin in a neighboring atom, forming a so-called covalent bond. In the resulting structure (often referred to as the diamond structure), each atom is surrounded by four equally distant neighbors arranged as the corners of a tetrahedron. This tetrahedral bond is sketched in Figure 3.1, for the general case of a compound with two different atoms. For diamond, silicon, or germanium, both A and B are the same atom. The covalent bond has been drawn with a spindle shape rather than a simple line to suggest the region of high probability for the electrons forming the covalent bond. In the following, we will use t to indicate the length of the bond, or the distance between the ion A and any of the ions B. Most III-V compounds (including GaAs) crystallize in the zincblende structure, which is similar to diamond, except that the atomic sites are occupied alternatively by two different elements. A few other semiconductors (including GaN) have a wurtzite lattice, with hexagonal, instead of cubical, symmetry. In both structures, however, the local arrangement is still the same cluster shown in Figure 3.1. If we take GaAs as an example, each gallium ion is surrounded by four arsenic ions, and conversely, each As ion by four Ga ions. Out of the eight electrons forming the tetrahedral bond, three originate from a gallium atom, and five from an arsenic one, so there is a charge unbalance between the two ions and some amount of ionic bonding. Still, the covalent bond definitely prevails [7], and the properties of the III-V compounds are remarkably similar to those of the IV-column elements. When the distance between atoms is decreased, and they start to interact, their energy levels begin to broaden, in the same way as the frequencies of resonant circuits do when the circuits interact. The simplified sketch of Figure 3.2, based on a classic calculation [8], shows qualitatively what happens when a large number (N) of carbon atoms are brought together by varying the distance between them while maintaining a diamond lattice. Even though the calculation is for carbon atoms, it can be used qualitatively for any atom belonging to the IV column with four electrons in the outer shell, since most of the interaction takes place only at this highest

Figure 3.1  Tetrahedral bond characteristic of the diamond or zincblende structures. In diamond, A and B are the same ion, but in zincblende they are different.

20

Physics of Active Devices

Figure 3.2  Energy bands for hypothetic materials formed by atoms of the IV column when brought progressively closer while maintaining the diamond structure, as a function of the distance t between atoms. The labels 4N and 2N refer to the number of states available in each energy band.

level. In the case of carbon, this is characterized by the quantum number n = 2. As mentioned above, there is a small difference between the energy of the two electron pairs, l = 0 and l = 1, due to the different way each pair interacts with the other electrons, so that the n = 2 level is actually split into two sublevels. As the separation between the carbon atoms is decreased and the energy levels progressively broaden to accommodate all the N atoms interacting with each other, there is a range of t, roughly between 3.2 and 2.8Å, where the two subshells merge with each other. All energy levels become available, and electrons can gain and lose energy in a continuous way. This situation is similar to the one of conduction electrons in a metal. In fact, Gray Tin, which crystallizes in the diamond structure right at the border of this range, behaves somewhat as a metal, though with poor characteristics. (As noticed above, “real” metals would not crystallize in this structure, but in a more packed one, favoring electronic conduction.) A further decrease in the length of the tetragonal bond brings about the most characteristic feature of a semiconductor, a forbidden range of energies or energy gap (also bandgap). Electron wave functions with energies within this gap are exponentially attenuated and are not stable solutions. Electrons with energy near the lower edge of the gap cannot continuously increase their energy, but require an amount at least equal to the energy gap in order to reach the upper band. Notice that, after the mixing of the two energy bands, taking place around t = 3Å, there are four quantum states per atom available in the lower band, which can thus accommodate all four electrons originating from the n = 2 carbon shell. This is indicated by the circled 4N in the drawing. Therefore, at very low temperatures, the lower energy band (called the valence band) will be fully occupied, and the upper band (the conduction band), will be empty. At higher temperatures, there is some chance that a few electrons will acquire enough energy

3.2  Basic Concepts of Solid-State Physics

21

to cross the gap and contribute to the conductivity of the semiconductor. We speak of an insulator when the gap becomes so large that this chance is negligible at all operating temperatures. Such is the case for diamond. Once we accept the concept of the wavelike nature of electrons, the energy gap is a result of the periodic nature of the crystal lattice. In reality, while most semiconductor devices are single crystals, most other solids are polycrystalline; still, the size of the microcrystals is normally large enough for the theory to apply. The problem of waves in periodic structures has been studied in many different contexts. As discussed in the classic book by Leon Brillouin [9], it is essentially the same as that of an electrical filter, with frequency corresponding to energy and the energy gap being equivalent to a stop band. As we mentioned above for the hydrogen atom, the distribution of electrons in a solid is described by a state function that is a solution of Schrödinger’s equation, except that now the potential is not spherically symmetric, but rather a periodic function simulating the array of ions. Only periodic wave functions with the same periodicity as the lattice will satisfy the boundary conditions, and they will correspond to definite ranges of energy, leaving energy gaps, which do not correspond to viable solutions. In terms of the covalent bond picture shown in Figure 3.1, we may view the energy gap as the amount of energy required to break the bond and allow each electron to move freely from ion to ion. If the atoms are far away and the bond is very weak, little energy is required to break it. As the structure becomes tighter, this energy progressively increases. This picture is especially useful in understanding the role of doping in a semiconductor. Let us consider the case of a silicon crystal where one of the Si atoms is replaced by an element from the V column of the periodic system, that is, with five electrons on the outer shell, for example, arsenic. There will be a tendency for it to lose (or donate) one of the electrons, and use the remaining four to complete the tetragonal bond. Very little energy will be required to break away this fifth electron from the neighborhood of the original As, so it will be easily available for conduction. The material will be called n-type, because the charges conducting electricity are negative (electrons), and the arsenic atom will be called a donor. Conversely, if we introduce in a silicon crystal an impurity from the III column, such as boron, with three electrons on the outer shell, it will have a tendency to capture (or accept) an electron in order to complete the bond. Not much energy will be required for an electron to hop from another bond into this, so that this broken bond will move across the crystal, behaving as a positive charge called a hole. This situation is sketched in Figure 3.3, where Ed and Ea represent the amounts of energy required, respectively, to break away an electron from its donor and to attract an electron from another covalent bond into an acceptor site. The finely dashed areas of the conduction and valence band represent, respectively, electrons and holes which are available for conduction. In a typical situation, most of the conduction electrons in an n-type material come from the donor level and few from the valence band. Similarly, most of the holes in a p-type material are created by electrons that have been captured by acceptors. Implicit in our description of Figures 3.2 and 3.3 is the very powerful assumption that Pauli’s principle is forcing the electrons to distribute themselves over a broad energy range, rather than pile up at the lowest possible energy, as they would do based on classical physics. According to this principle, as we mentioned above

22

Physics of Active Devices

Figure 3.3  Energy bands for n-type and p-type semiconductors. Ed is the energy required to excite an electron from the donor level to the conduction band (free an electron from a donor site); Ea has a similar meaning for holes, relative to the valence band and the acceptor site.

for the case of the quantum states in an atom, only two electrons (with opposite spin) can correspond to each solution of Schrödinger’s equation, that is, each quantum state. Therefore electrons will fill up the energy levels based on how many states are available at each level. Let us look at the example of a free electron gas, or the case of electrons immersed in a field of constant potential. This is the most elementary approximation to the problem of electrons in a metal, when we consider them subject to an average positive potential created by the closely packed positive ions. This hypothetical flat potential is compared in Figure 3.4 to the real potential distribution in a line going through the ions (a) or in between (b). Of course, as the metal ends, there will be a sharp discontinuity, which corresponds to the binding or cohesive energy of the particular crystal. In other words, the energy for electrons interacting with each other and the regular array of ions is lower than for electrons in isolated atoms: this is why the solid keeps together. An example is seen in Figure 3.2. The average energy of the four electrons in the n = 2 shell of the carbon atoms is higher than in the valence band for any of the crystals formed by the merging. As shown in Figure 3.4, the free electron model is not accurate for any real metal, but it does give a first-order insight into many physical properties. Inside the metal, where the potential is constant, we can always choose it as the zero of the

3.2  Basic Concepts of Solid-State Physics

23

Figure 3.4  Potential near the surface of a metal: (a) along a line passing through the ions, (b) along a line halfway between the ions, and (c) approximation of free electrons.

energy scale, so that, in each direction, Schrödinger’s equation, (3.1), becomes a very familiar wave equation:

-2 Ψ + (2m/h )EΨ = 0

(3.2)

with solutions of the type exp(± jkx) (running waves). To simplify things even further, let us assume that the barrier at the surface of the metal is infinite, so that the probability of an electron being outside the metal is negligible. Then the boundary conditions Y = 0 at the two surfaces would lead to a solution of the type sin [(pn/L)x], where L is the macroscopic dimension of the solid, and n is an integer number, which represents in this case the only quantum number (apart from the spin). In other words, the values of k are quantized, and each value corresponds to a different state. The corresponding energy levels are:

En = An2 , where A = (p /L)2 (¯h2 /2m)

(3.3)

Apart from the spin, in this one-dimensional case there is only one quantum number (n), and we have one state for each n. Therefore, if we have N electrons, or N/2

24

Physics of Active Devices

pairs, at very low temperatures all the energy levels up to a maximum energy Ê = A (N/2)² will be occupied by electrons, while higher energy levels will be empty. If we follow the same kind of argument in three dimensions, as detailed in [10], we now have three quantum numbers, say n1, n2, and n3, and we find that the energy levels are given by A(n1² + n2² + n3²). Each set of positive integers corresponds to two quantum states (one for each spin), so that the number of quantum states n(E) with energy up to any energy E is equal to twice the number of cubes of side one contained in one eighth (for positive integers) of a sphere of radius (E/A)1/2; namely, n(E) = 2(p/6) (E/A)3/2. The density of states (variation of the number of states with energy) is then:

dv/dE = (p /2)A(−3/2) E1/2

(3.4)

At zero absolute temperature, all states are occupied by the N available electrons up to a maximum energy Ê, such that

3/2 ˆ N = 2(p /6)(E/A)

(3.5)

The energy level Ê is called Fermi energy and is one of the most important parameters in solid-state physics. In general, Ê is defined as the highest filled energy level at zero absolute temperature, and, as we saw from the two preceding examples, is determined by setting the condition that the number of available electrons should equal the number of quantum states for all energies up to the Fermi energy itself. Notice that A-3/2 is proportional to the volume of our sample (L³), so that Ê is only a function of the number of electrons per unit volume. When the constants are plugged in, the highest energy of the electrons at absolute zero is found to be as high as several electron volts, a remarkable result of Pauli’s exclusion principle and quite in contrast with classical views. As an example, the value of Ê, computed for copper assuming one free electron per atom, is found to be as high as 7 eV. At higher temperatures, some of the electrons close to the Fermi energy will move to higher energy states and leave some of the states below the level empty. At any given absolute temperature T, the probability that a quantum state of energy E is occupied by an electron is given by the Fermi-Dirac distribution function [11]

f(E) = 1/[exp{(E − EF )/KT} + 1]

(3.6)

where K is the Boltzmann constant and EF is the chemical potential of the electrons. In the literature on semiconductor devices, this is generally referred to as the Fermi level. At absolute zero, the Fermi level coincides with the Fermi energy, Ê. At any temperature, it could be defined as the energy level where f(E) = 1/2, namely there is an equal probability of the level being empty or occupied. In general, it is defined and can be calculated using the condition that the total number of electrons N should always be equal to the integral, over all possible energy levels, of the density of states times the distribution function. Namely:

N=

�

v(E)f(E)dE



(3.7)

3.3  Charge Transport in Semiconductors

25

Figure 3.5  Fermi-Dirac distribution at two different temperatures, as compared to absolute zero. For a constant density of states, shaded areas above EF are proportional to the number of electrons excited when the temperature is raised, respectively, from 0 to 300K and 300 to 600K. The shaded areas below EF have the same meaning with respect to emptied available states.

One can easily see that, if the density of states is constant (or the variation is gentle), and EF is much larger than KT (a condition often satisfied, since KT = 25.9 meV at room temperature), the chemical potential remains quite close to the Fermi energy. Sketched in Figure 3.5 are Fermi-Dirac distribution functions at two different temperatures, as compared to the abrupt distribution at zero, all of them computed for the same value of EF. Assuming a constant density of states, the conservation of the electrons requires that equally shaded areas above and below the Fermi level should be equal, which here is clearly the case. On the other hand, we can infer that, if the density of states is not constant, the position of the Fermi level will have to move in order to maintain the same number of excited electrons above the level as the number of available empty states below. In the following, we will often discuss situations where E-EF >> KT, and therefore the Fermi-Dirac distribution can be approximated by exp{-(E-EF)/KT} (namely by Boltzmann’s distribution). When different materials are brought in contact, and electrons are allowed to transfer from one to the other, they will flow toward the lowest Fermi level, thereby raising it until the level in the whole system is equalized, somewhat like a liquid in communicating vessels.

3.3  Charge Transport in Semiconductors Despite all we have said above about the wavelike nature of electrons, we find it convenient (and more intuitive) to adopt a particle-like terminology when discussing the transport of carriers through a semiconductor. This is fictitious: the relationship between energy E and momentum k of the electron wave (as obtained from the solution of Schrödinger’s equation) is quite complex. Near the bottom of the conduction band (as well as the top of the valence band), however, it can be

26

Physics of Active Devices

approximated with a quadratic relationship of the type E µ k². In other words, in the vicinity of the energy gap, the momentum is related to the energy in the same way as for a free particle, provided we assume for the particle a suitable effective mass m* to fit the proportionality constant. We will write, therefore:

h k = m*v, for the electron’s momentum, and

(3.8)



E = 1/2m*v 2, for its energy above the bottom of the conduction band,

(3.9)

where -h is the reduced Plank constant we have met earlier. The value of the effective mass, obtained by fitting the momentum-energy relationship, may be quite different from the free electron mass. As an example, the ratio of the two is equal to 0.067 for electrons in GaAs. In absence of an electric field electrons and holes will move at random within the lattice, interacting with the lattice vibrations (phonons) and the impurities. When an electric field is applied, they will develop, in average, a velocity vd in the direction of the field, which is termed drift velocity. For relatively low field strengths, this is found to be proportional to the electric field E, namely:

vd = m E

(3.10)

where m is, by definition, the electron (or hole) mobility. It is a function of the material and the temperature as well as the doping density, especially when this is high, since then the scattering of carriers (electrons or holes) by the impurities becomes a dominant factor limiting the mobility. At higher fields, the velocity progressively saturates, sometimes reaching a maximum and then decreasing. The saturation is due to a stronger interaction of the carriers, energized by the field, with both lattice and impurities, and it is present in all semiconductors. The decrease, instead, is peculiar to some materials, mostly III-V compounds, and is related to the specific structure of the conduction band. In these materials, the band presents two minima, relatively close to each other, the lower one characterized by much higher electron mobility than the upper one, so that, when energized electrons are excited in a significant number to the upper minimum, the overall mobility is effectively decreased. This phenomenon is the basis of the transferred electron (or Gunn) effect [12]. The electron drift velocity versus electric field is shown in Figure 3.6 for a few typical semiconductors at room temperature and relatively low doping densities (less than 1017 cm-3) [13]. Silicon provides an example of a smooth saturation, while GaAs and InP clearly show the decrease in velocity, corresponding to a negative differential resistivity, that can lead to oscillations. A similar feature, although somewhat less pronounced, is present in GaN, but at much higher electric fields, as shown on the righthand side, using a different horizontal scale. In terms of device operation, the velocity that mostly affects microwave performance depends on the type of device and the operating electric fields. As we will see later in this chapter, in a field-effect transistor (FET), the low-field velocity (or the initial slope of the curves in Figure 3.6) mostly relates to the parasitic elements

3.4  Junctions and Barriers

27

Figure 3.6  Drift velocity versus electric field for a few typical semiconductors. The initial slope of the curves represents, by definition, the electron mobility.

of the device, while the frequency response is determined, to a large extent, by the peak value. This assumes, of course, that the operating electric field is properly adjusted. At even higher electric fields, carriers will reach enough energy to produce electron-hole pairs by impact ionization. This is one of the main mechanisms responsible for the breakdown of junctions as well as transistors. In this connection, it is generally referred to as avalanche breakdown.

3.4  Junctions and Barriers A three-terminal active device can be viewed as a piece of semiconductor, where a large flow of charges, moving from a source (or emitter) to a drain (or collector), is regulated by some kind of controlling element. A small signal, applied to this element, modulates the whole flow, which thus reproduces the signal in an amplified way. In this section, we deal with the nature of this element: it should enable an effective control on the main flow of charges, without allowing too much charge flow through itself, so as to maximize the amplifying effect. We will review here the three main alternatives: a metal-semiconductor junction (including metal-oxidesemiconductor); a p-n junction; and a heterojunction. Metal contacts are also required to provide a connection to both source and drain, but, in this case, the contact should allow the current to go through with as little resistance as possible, and facilitate the transfer of charges both in and out of the semiconductor. These are called ohmic contacts. In Figure 3.4 of Section 3.2, we have sketched an idealized model for the region near the surface of a metal and have indicated that the potential step at the surface represents the amount of energy either required to extract an electron from the metal or gained when an isolated electron is brought into the metal. We now know that electrons, confined within a potential well, as depicted in the figure, will fill it up to the Fermi level (plus or minus excited electrons). The difference in energy between this level and an electron outside the metal is termed the work function of the metal, and it is indicated with Fm in Figure 3.7. Since in a metal the Fermi level

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Physics of Active Devices

is a weak function of temperature, in most practical situations the work function can be considered almost a constant, which is a characteristic of the metal. The situation is different in a semiconductors, where the variation of the Fermi level with temperature is generally quite strong. Let us take as an example an n-type semiconductor: at low temperatures, when the first electrons reaching the conduction band originate exclusively from the donors, the Fermi level must be located somewhere between the donor level and the lower edge of the conduction band (the specific position depends on the donors’ density and the density of states in the band), but eventually all donors lose their extra electrons and become ionized, while some electrons from the valence band become excited. The Fermi level then crosses the donor level and moves progressively towards the center of the gap. We are assuming, of course, that the donors’ density is much lower than the density of states in both conduction and valence band; otherwise, one would not talk of a doped semiconductor, but rather of a new compound. In this situation, it is not practical to use the concept of work function, as would be used for a metal. The analogous quantity characteristic of a semiconductor is instead the electron affinity, indicated as c in the figure and defined as the energy difference between an electron at the bottom of the conduction band and one outside the semiconductor. We will now consider what happens when a metal is brought into direct contact with a semiconductor, say, by vacuum deposition. Let us first assume that the region next to the surface of the semiconductor be unchanged with respect to the bulk. This is actually a strong assumption, and rather unlikely: after all, we have justified the presence of an energy gap by asserting that it is due to the periodicity of the crystal lattice, which is clearly broken by the surface. So we expect that, at the surface, the gap will be at least modified. In fact, so-called intrinsic surface states, that is, available energy levels which fall within the energy gap due to the broken crystal symmetry, are typically present. In addition, a semiconductor surface exposed to air, or even to the limited vacuum of most deposition systems, is generally covered by a very thin layer of oxygen, hydrogen, or water molecules that become attached to the broken bonds exposed when the surface is formed. In some cases, one can think of a very thin oxide layer; in others, it is more like an amorphous distribution. In any case, these impurities are also responsible for the formation of energy states within the forbidden gap, which are referred to as extrinsic surface states. This is not to say that similar states, whether due to impurities or broken symmetry, do not take place also at the surface of a metal, or, on a semiconductor, within valence and conduction bands. But then, they barely alter the already high density of available states and, therefore, have a much lower impact. When the surface states fall within the gap, they create a qualitatively new situation. Let us now, for a moment, go back to the ideal situation of an absence of surface states. We will take this as a limit case, never quite reached in real life, but sometimes approached. In this case, the energy levels of the metal and the semiconductor, before the two are brought into contact, will look as in Figure 3.7(a), where we have chosen to represent an n-type semiconductor. When the two materials are brought together, as shown in Figure 3.7(b), electrons will transfer from the semiconductor to the metal until the Fermi level is equalized, thereby leaving the region next to the surface of the semiconductor positively charged, mostly by ionized donors, and almost fully depleted of mobile charges. This charge is compensated

3.4  Junctions and Barriers

29

Figure 3.7  Metal-semiconductor junction in absence of surface states: (a) before and (b) after making contact.

by an electron sheet concentrated at the surface of the metal. The voltage barrier created in the process is given by the difference between the metal work function and the semiconductor affinity. A similar situation is observed in several wide gap semiconductors, especially of the ionic type, such as CdS [14]. This does not necessarily mean that there are no surface states. They may be located close to the edges of the bandgap, and, therefore, are not swept by the Fermi level during the barrier formation. Surface states bring much variety and complexity to the situation. If there is a fairly high density of such states within the region of the gap occupied by the Fermi level, the region near the surface of the semiconductor can be depleted, to some extent, even before the metal is brought into contact, as shown in Figure 3.8(a). Electrons originating from the donors will fill the surface states available within the gap, rather than populate the conduction band, thereby leaving a layer of positively ionized donors and creating a depletion region without any contribution of the metal. The layer might, or might not, be further increased when the metal is brought into contact, depending on the density of the states. As shown in Figure 3.8(b), it is possible that the transfer of charge required to equalize the Fermi level on the two sides may be fully absorbed by the surface states, without requiring additional ionization of donors. In any case, the resulting barrier is not related in a

Figure 3.8  Metal-semiconductor junction with high density of surface states: (a) before and (b) after making contact.

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Physics of Active Devices

direct way to the work function, and, if the density of surface states is high, the barrier might become completely independent on the metal. A very mild dependence is in fact observed in GaAs, while Si is an intermediate case [15]. If we assume that all donors in the depleted region are ionized, and therefore positively charged, while all donors outside the depletion region are neutral (the abrupt junction approximation), and we neglect the contribution of the tail of conduction electrons present at the edge of the depletion region, the application of Poisson’s equation to the charge distribution shown in Figure 3.9 gives:

d2 V/dx2 = −eN D /e

(3.11)

where V is the potential of the electrostatic field, e is the electronic charge, ND is the donor density, and e is the dielectric constant of the semiconductor. Integrating

Figure 3.9  Charge density (r), electric field (E ), and potential (V ) in the depletion region of a metal semiconductor barrier under the abrupt approximation, as a function of distance into the semiconductor (x).

3.4  Junctions and Barriers

31

over a depleted region of depth W under boundary conditions of zero electric field and zero potential at the boundary (dV/dx = 0 and V = 0 for x = W), we find the linear field and parabolic potential distributions shown in Figure 3.9. Notice that the maximum electric field at the surface is equal to the charge per unit surface, as required by Gauss’s law. The depth of the depletion region varies as the square root of the potential barrier:

W = (2e Vb /eND )1/2

(3.12)

and, since the total charge per unit surface is Q = eNDW, the capacitance per unit surface associated with the depletion region is found to be:

C = dQ/dVb = eND (dW/dVb ) = e /W

(3.13)

It is interesting to notice that, while the square root relationship (3.12) and the linear or parabolic shapes shown in Figure 3.9 are only valid for a constant density of donors, the inverse proportionality between capacitance and depth of the depletion region described by (3.13) is valid for any shape of the donor distribution. When an external positive bias V is applied to the metal side, namely the junction is forward biased, the barrier height on the semiconductor side is decreased by a corresponding amount, and the opposite effect is produced by a reverse bias. This is shown schematically in Figure 3.10, where, for the sake of simplicity, we have

Figure 3.10  Metal semiconductor barrier under an applied voltage V, with a schematic indication of the main transport processes across the barrier.

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Physics of Active Devices

neglected the barrier lowering induced by the image force (Schottky effect), which would have smoothed the sharp and unrealistic spike at the metal’s surface [16]. The depletion region is correspondingly reduced under forward bias and extended under reverse bias. Three main mechanisms have been proposed for the current transport across the barrier. With reference to the numbers shown in the figure, they are: 1. tunneling (a quantum-mechanical phenomenon whereby electron waves have a finite probability of penetrating through a potential barrier); 2. thermionic emission (excited electrons acquiring sufficient energy to reach over the top of the barrier); and 3. electron/hole recombination (either in the depleted region or within the semiconductor body). In the context of microwave devices, the first two are the most important. Tunneling prevails in highly doped, very thin barriers and is often a major contributor to the behavior of ohmic contacts, while thermionic emission is generally the main mechanism in the gate structure, especially in high-mobility semiconductors. Both types of current are due to majority carriers; in our case generally electrons, since most microwave FETs are made with n-type material (the electrons’ mobility being generally higher than the holes’). Without going into too much detail on the specific expression for the thermionic current, which can be found in [17], we can derive its general form by elementary and intuitive considerations. The number of electrons coming from the metal side that will be able to cross the barrier is proportional to the tail of the Fermi distribution function for energies above FB, namely, for FB»KT, to exp(-FB/KT). Conversely, the barrier viewed from the semiconductor side is now decreased by an amount equal to the applied voltage V, so that the flow of electrons in this direction will be proportional to exp[- (FB-V)/KT ]. The net electron flow from the semiconductor to the metal will be then:

J = JS [exp(V/KT) − 1]

(3.14)

where JS is a function of temperature and of the parameters characterizing the metal/ semiconductor pair. Equation (3.14) clearly shows that the usefulness of a metalsemiconductor junction as a gate in a three-terminal device is limited to the reverse bias. At forward biases, the current through the junction grows exponentially, effectively short-circuiting the signal applied to the gate. In any case, in the forward direction, the barrier collapses as soon as the voltage reaches FB. In the reverse direction, on the other hand, the useful range is limited by the junction breakdown. This is due most often to a combination of avalanche breakdown and tunneling, with the latter prevailing at higher doping densities [18]. Since the gate breakdown is one of the major mechanisms limiting the power output of microwave devices, we will meet this subject again, in Section 3.5 and Chapter 8. We will not discuss here a very important variation of the metal-semiconductor junction that is obtained when an insulator, most often an oxide, is interposed between the metal and the semiconductor. This type of diode structure is the basis of the MOSFET transistor. Since this is the most important player in the field of verylarge-scale integrated circuits, a wealth of literature is available on this subject. (See, for instance, Tsividis, Y., Operation and Modeling of the MOS Transistor, 2d. ed., New York: McGraw Hill, 1999; Bhattacharyya, A.B., Compact MOSFET Models for VLSI Design, Hoboken, NJ: Wiley, 2009; and Nicollian, E.H. and Brew, J.R., MOS/Metal Oxide Semiconductors Physics and Technology, Hoboken, NJ: Wiley

3.4  Junctions and Barriers

33

Paperbacks, 2002.) We will close, instead, by spending a few words on ohmic contacts, which are a key element in any electronic device. A good ohmic contact should provide the required current flow, without affecting the device performance and introducing negligible contact resistance. In other words, the junction barrier should be as low and narrow as possible, thus virtually disappearing from the picture. To decrease the barrier depth, and favor the tunneling of carriers through it, a highly doped layer is generally formed in the semiconductor right before the metal junction. In absence of surface states, the height of the barrier can be minimized by using a metal with a low work function, such as Al. This is used, in fact, in combination with semiconductors where surface states are not active and even, to some extent, with Si, despite some surface states activity. In III-V compounds, particularly GaAs, where the Fermi level is virtually pinned by the surface states and the work function of the metal is not significant, the recipe for ohmic contacts generally involves an alloyed layer, where the metal-semiconductor interface is melted and regrown, thereby creating a graded junction which smooths out the barrier. For GaAs, one of the most popular approaches involves the Au/Ge eutectic. The drawback of this approach is often some roughness of the contact layer, due to the process of recrystallization after melting. Different strategies have been proposed to reduce this problem, most often of them involving a thin film Ni, which has the main function of improving the adherence and the uniformity of the layer. This type of contact has been used successfully for a long time and has been reviewed relatively recently and reoptimized [19]. Let us then move on to p-n junctions. These generally provide the most smooth and defect-free interfaces, a characteristic which is partly responsible for the lower phase noise of bipolar devices. In fact, as opposed to a metal-semiconductor junction or a heterojunction, which are formed by growing or depositing a different material on top of a basic semiconductor, a p-n junction is generally obtained by diffusing or ion implanting a dopant into the single crystal semiconductor itself. The barrier is strictly determined by the levels of doping. Since electrons have generally higher mobility than holes, in a high-speed application one would typically favor them as the major carriers of current. Therefore, in microwave devices, it is more common to see junctions obtained by diffusing or ion-implanting donors into a ptype material than vice versa, thus forming what is sometimes described as an n+-p junction. Such a case is portrayed in Figure 3.11, where in the first sketch we show two separate p and n pieces for purely conceptual reasons. Once the two regions are in contact, electrons will diffuse from the n-type to the p-type material, where they will recombine with holes. Similarly, holes will diffuse in the opposite direction. In this process, electrons will leave behind positively ionized donors, and holes will leave negatively charged acceptors. This double layer of charges produces an electric field E that opposes the diffusion process. As usual, equilibrium will be reached when the Fermi level is equalized throughout the semiconductor. For simplicity, we have again adopted an abrupt junction approximation, assuming that all donors ND and acceptors NA are ionized up to the end of the two-sided depletion region and that both sides of the semiconductor are, otherwise, neutral. Solving Poisson’s equation on the two sides of the depletion region and imposing the continuity of field and potential leads to the following expression for the built-in potential Vbi:

Vbi = (e/2e )[NA ND /(NA + ND )]W2 , with W = WA + WD

(3.15)

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Physics of Active Devices

Figure 3.11  A p-n junction. (a) The two sides of the junction; (b) electron (e) and hole (h) concentrations in the proximity of the junction; (c) charge density, formed by ionized donors (ND+)and acceptors (NA-), producing an electric field E in the direction shown; and (d) energy-band diagram showing the built-in potential barrier Vbi.

This is the equivalent of (3.12) for the metal-semiconductor barrier, and it relates the built-in potential to the depth of the depletion region. In this case, however, since there are no surface states involved, we can also directly connect the barrier height to the doping of the semiconductor on both sides of the junction. Notice

3.4  Junctions and Barriers

35

first that in any semiconductor the product of the electron and hole densities is a constant that depends only on the semiconductor itself and the temperature, not on the doping. In fact, using Boltzmann’s distribution, we have

n = Nc exp[−(Ec − EF )/KT ], and p = Nv exp[(Ev − EF )/KT ]

(3.16)

so that

np = Nv Nc exp(EG /KT )

(3.17)

where Nc , Nv (density of states at the edge of the conduction and valence bands) and EG (energy gap) are characteristic of the semiconductor and do not depend on the doping. In particular, the np product is the same as for an intrinsic semiconductor, and therefore, it is generally indicated with ni2. Using the subscripts n and p to indicate, respectively, the n and p sides of the junction, we have

Vbi = EG − (Ec − EF )n − (Ev − EF )p

(3.18)

which, using relationships of the type in (3.16) for the two sides of the junction, translates into

Vbi = KT ln(nn pp /n2i ) ∼ = KT(NA ND /n2i )

(3.19)

where the last step assumes most electrons on the n side come from the donors and most holes on the p side from the acceptors. When an external bias is applied to the junction, with the positive on the p side, it has the effect of decreasing the built-in voltage, shrinking the depletion region, and enhancing the diffusion of charges in both directions. Electrons diffuse across the lowered barrier and recombine on the p side of the junction. Holes diffuse towards the n side where, again, they recombine. The probability for both carriers to cross toward the opposite side of the barrier increases in proportion to exp(eV/KT), where V is the applied voltage. Conversely, a reverse voltage quickly cuts off all diffusion of electron or holes uphill across the barrier, leaving only a small residual current, Jsg. This is due to thermally generated pairs on both sides of the junction flowing downhill (electrons towards the n side, holes towards the p side). Such reverse current is basically unaffected by the applied bias. Therefore, despite the fact that the main transport mechanism is not the same (this is rather akin to the one indicated with 3 in Figure 3.10), the general expression for the current in a p-n junction is quite similar to (3.14), namely

J = Jsg [exp(eV/KT) − 1]

(3.20)

where, however, Jsg is different from JS, including a different temperature dependence. The simple expression for the current (3.20), originally derived by Shockley [20], is valid only in first approximation and neglects some important aspects [21], but is still qualitatively sufficient for our scope. Basically, it portrays the rectifying characteristic of the junction, which is the basis for the operation of a bipolar transistor.

36

Physics of Active Devices

As early as the 1950s, it was proposed from different sources [22] that improved characteristics for a p-n junction could be obtained if the two sides of the junction were made from different materials; however, it was not until the 1970s that crystalline interfaces of sufficient quality could be actually produced. With the advent of molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD), it became possible to deposit layers of different compounds maintaining an almost perfect lattice quality across the junction, provided the two materials had reasonably close crystal structures. Clearly, the freedom introduced by the use of heterostructures opens up all kinds of possibilities, not only in diodes and transistors but also in optical devices. At the moment, we will concern ourselves only with p-n junctions [23], but later we will have another opportunity to meet heterostructures when discussing the high electron mobility transistor (HEMT). As an example of a typical application, and one of the first to be proposed [24], we show in Figure 3.12 the use of a large bandgap material for the n side and a smaller band-gap material for the p side. In the upper part of the picture, the energy bands of the two materials are sketched with reference to the vacuum level, that is the energy of an electron outside the semiconductor. As discussed in connection with metal-semiconductor junctions, assuming a conduction band discontinuity equal to

Figure 3.12  Formation of a heterojunction: (a) energy diagrams for the n- and p-type semiconductors prior to the formation of the junction; and (b) energy diagram for the heterojunction.

3.5  FETs and MESFETs

37

the difference of the electron affinities implies the absence of interface states and may not be realistic. In practice, the discontinuity may be taken as an empirical characteristic of the semiconductor pair. As usual, under equilibrium conditions, the Fermi level will be even across the junction. This condition, together with the given band discontinuity, will determine the total voltage buildup at the interface. The extent of the depletion regions on the two sides and the junction capacitance can be then obtained by solving Poisson’s equation on the two sides of the barrier, in the same way as discussed earlier for a metal-semiconductor junction. The major portion of the voltage will develop on the side with lower doping. In the particular case exemplified in the figure, the positions of the Fermi level in the two semiconductors, as shown in Figure 3.12(a), clearly indicate that the p-type semiconductor on the right is more heavily doped than the n-type on the left. Accordingly, the depletion region and the band bending extend on the left side of the interface more than on the right. When used as the emitter-base junction of an n-p-n transistor, the band discontinuity created by the heterojunction has the desirable effect of reducing the barrier from the n side to the p side for electrons, thereby increasing the electron flow from emitter to base, while at the same time raising the barrier for holes and, therefore, decreasing the hole flow in the opposite direction. We will come back to this point in Section 3.6, when we will discuss heterojunction transistors.

3.5  FETs and MESFETs Field effect transistors are majority carrier devices where a flow of electric current is controlled transversally by an applied voltage. They are divided into three major groups, depending on the type of electrode, or gate, used to apply the controlling voltage. In MOSFETs, the gate is formed by a metal-oxide-semiconductor contact, while JFETs are controlled by a p-n junction, and MESFETs by a metal-semiconductor barrier. The three branches of the large FET family have found distinct fields of application. While the first is by far dominant in large-scale integrated circuits and the second finds application in many niches thanks to its versatility, the third is the preferred choice as a microwave device. The main difference is not so much in the characteristics of each type of junction (although this is a factor) as in the right combination between junction and semiconductor. In contrast with silicon, which has a remarkably good natural oxide and very well developed p-n junctions, most III-V compounds, and specifically GaAs, have neither (at least to the same extent as silicon). In addition, compound semiconductors cannot withstand severe processing in the same way as silicon does. In particular, Ga and As have substantially different vapor pressures, so that treatments at elevated temperatures or in high-energy plasma easily produce As vacancies and other kinds of stoichiometric unbalances. Such crystal defects play a role similar to foreign impurities and affect both mobility and doping. Therefore, relatively low temperature processes are generally preferable. A metal deposition is certainly one of the most gentle process steps and is not likely to create appreciable damage. It is, therefore, not surprising that most compound-semiconductor devices are of the MESFET variety. This said, it is also true that the metal-semiconductor junction is typically faster, and that the low resistance

38

Physics of Active Devices

presented by the metal gate offers considerable advantages at high frequency, especially in terms of a lower phase shift along the gate. These are additional reasons favoring this type of junction at high frequency, independent of the semiconductor. Because of our focus on microwave devices, we will concentrate on MESFETs from now on, though a lot of what we say applies to any type of FET. We will start with the most basic structure, as sketched in Figure 3.13, and concentrate on GaAs, which has been for many years the most successful semiconducting material for microwave FETs. In the sketch, a flow of electrons, moving from source to drain within the n-type GaAs channel, is restricted under the gate by a depleted region, free of electrons, which is controlled by the negative voltage applied to the gate. The depleted region is extended toward the drain because of its positive bias, which makes the drain-to-gate voltage drop higher than the source-to-gate voltage. This basic device could be fabricated by depositing an n-doped epitaxial layer, either by liquid or vapor-phase growth, onto a high-resistivity semi-insulating substrate. Alternatively, the doped layer could be formed by ion implantation into the substrate and subsequent annealing. Next, ohmic contacts are first evaporated and then alloyed-in. The most usual recipe uses Au and Ge in the ratio of 88:12, corresponding to a eutectic composition, often with the addition of Ni, which improves wetting and helps in preventing ball formations during alloying. Finally, the gate metal is deposited and defined. Gold alone cannot be used because it diffuses easily in GaAs so that the barrier would quickly deteriorate. The earlier devices used mostly Al, which gives a junction with good characteristics, but is incompatible with Au: they form an intermetallic compound of very poor characteristics, colloquially known as “purple plague.” Since the ohmic contacts are gold-based, the problem became especially severe with the development of monolithic microwave integrated circuits, because of the obvious need to interconnect the two metal systems. Currently, all devices have gold-compatible gates (typically a sequence of a good adherence layer, such as Ti, followed by a barrier metal, such as Pt, and finally Au). In the elementary device pictured in Figure 3.13, the substrate is considered as a rigid and inert boundary, which does not participate in the process. In reality, there

Figure 3.13  Basic structure of a GaAs FET. The flow of electrons moving from source to drain is controlled by the depletion region under the gate.

3.5  FETs and MESFETs

39

is a voltage barrier between the channel and the substrate, which can be crossed by charges as well as modulated, and it is involved in a number of important effects including back-gating [25] and low-frequency noise [26, 27]. In fact, the n-type channel has a doping on the order of 1017 cm-3, and therefore its Fermi level is quite close to the conduction band, while in the substrate the Fermi level is approximately in the middle of the gap. So, the barrier is about one-half of the energy gap. In the same way, for the sake of simplicity, we are neglecting at the moment the depleted regions under the GaAs surfaces between source and gate or gate and drain (ungated surfaces). When we discussed metal-semiconductor junctions in Section 3.4, we mentioned that most III-V compounds have a fairly high density of surface states in the middle of the energy gap, so that the surface barrier is virtually pinned by them and depends very little on the metal. In other words, in absence of any voltage applied to the gate, there is an almost uniform depletion region all the way from source to drain. Only after the gate is biased does a more marked depletion develop under it. Although the effect of the ungated surface regions is somewhat attenuated by the use of recessed gates, they can still play an important role in noise and breakdown phenomena [28]. We will come back later to both substrate and surface effects. At the moment, let us go back to the elementary device depicted in the figure and discuss its basic operation. Due to the complex velocity-field relationship shown in Figure 3.6, even this simplified structure is far from trivial. Let’s assume a negative gate bias on the gate, which will produce a depletion region of depth W. Initially, as we apply an increasingly positive drain voltage, the current, for a device of width Z with a channel of thickness a, will be

I0 = eND Zv(a − W) = eND Z m E(a − W)

(3.21)

where we have assumed that all donors are ionized, so that the density of charges equals the donors’ density. This is the initial, linear region of the I-V characteristic shown in Figure 3.14. A deeper depletion (corresponding to a more negative gate bias) results in a lower slope. Because of current conservation along the x axis, the electric field must be inversely proportional to the thickness of the undepleted channel (a - W), and therefore it will concentrate under the gate, particularly at the drain side. This is the region where the velocity will be highest and will first reach its peak value. As shown in Figure 3.6, this will happen when the electric field will reach a value of approximately 3 kV/cm. As the drain bias is further increased, the velocity will continue to increase in the low-field regions, but will actually decrease at the drain edge of the gate, giving rise to a charge accumulation. Further out toward the drain, the velocity will increase again, and a charge depletion region will develop. This results in a dipole formation at the drain end of the gate, which further contributes to a concentration of the electric field in this region [29]. The decrease in electron velocity after the peak would also lead to a dip in the I-V characteristics [30, 31], although this is seldom observed experimentally because of various secondary effects, including the contact resistance and the flexibility of the channel-tosubstrate barrier. In practice, after a sharp corner, the experimental curves are well approximated by a saturated-velocity model [32], which simply assumes a constant

40

Physics of Active Devices

Figure 3.14  I-V Characteristics of a GaAs MESFET for two values of the applied gate voltage, with Vg1 less negative than Vg2.

velocity vs in the most restricted portion of the channel under the gate. Thus, for a channel with uniform doping, ND, the saturated current becomes

Is = eZvs ND (a − W)

(3.22)

Or, for any doping profile N(y): �

(3.23) with the integral extending from W to a. The value of vs that best fits the experimental data is 1.2 ´ 107 cm/s, substantially higher than reported in the equilibrium velocity-field curve of Figure 3.6. This has been attributed to a velocity overshoot of the electrons as they enter the high electric field region under the gate [33]: in a short-channel device (such as all present microwave transistors), the electric field in this region varies so rapidly that electrons may not have the time to reach equilibrium conditions. For the case of uniform doping, the device’s transconductance, gm, can be obtained by differentiating (3.22) with respect to the applied gate voltage, Vg:

Is = eZvs N(y)dy



gm = dIs /dVg = (dIs /dW)(dW/dVg ) = (Zvs eND )(e /WeND ) = Zvs e /W (3.24) where we have used (3.12) for W and the fact that the barrier, Vb, varies linearly with Vg. Although, to simplify the formulas, we have derived the last equality in (3.24) assuming a constant donors’ distribution, it can be easily shown [34] that it is actually valid for any doping profile, in the same way as the (3.13) is for the Schottky barrier capacitance per unit area. The depleted area under the gate is more complex than the metal-semiconductor barrier we considered in Section 3.4, mostly because the voltage at the end of the depletion region varies from the source to the drain side, so that the second electrode of the capacitor is not well defined. In a first approximation, we can split it in two, one at the source bias (typically ground) and

3.5  FETs and MESFETs

41

Figure 3.15  Physical origin of the equivalent circuit of a GaAs MESFET. The current generator, i, is the product of the transconductance times the voltage across the capacitor Cgs.

the other at the drain bias. This concept is represented schematically by the two capacitors Cgs and Cgd of Figure 3.15. We will come back to this figure later to discuss the other electrical elements. At the moment, we will identify the first of these two capacitors with the depletion region capacitance of (3.13). If we use L for its effective length and assume its depth W to be uniform (as was implied throughout in these derivations), the ratio of transconductance to gate capacitance (an important parameter in determining the frequency response of the device) becomes remarkably simple and independent on the doping profile:

gm /Cgs = vs /L



(3.25)

It is therefore possible to optimize the doping profile with other criteria in mind, in particular to improve the device linearity [35, 36] by minimizing the variation of gm as a function of the applied voltage. From (3.24) and (3.12) it is apparent that, for a constant doping, the transconductance varies inversely with the square root of the barrier voltage, namely as (Vb0 + Vg)-½, where we have used Vb0 to indicate the height of the barrier, in the absence of an applied voltage. An extremely sharp doping profile (a delta function), located at some depth W0, has instead the effect of freezing the end of the depletion region, so that the transconductance is kept constant and equal to Zvse/W0. In fact, a structure with a spike profile grown by MOCVD [37] has demonstrated remarkable linearity. Let us now come back to other electrical elements sketched in Figure 3.15. This figure forms the physical basis for the small-signal equivalent circuit shown in Figure 4.1. After reaching saturation, the horizontal I-V characteristics of a MESFET can be clearly simulated by a current source, which is a function of the gate voltage. This is physically localized in the narrowest portion of the channel. Its characteristic impedance is represented by the resistance of that channel region and by a capacitance, which is mostly related to the depletion region at the substrate interface. The

42

Physics of Active Devices

rest of the channel on the source side is split into two resistors: one (Rgs) is part of the circuit charging the gate-to-source capacitor, while the other (Rs1) is part of Rs, the source-to-ground connection. Similarly, Rd1 is part of the drain resistor, Rd. The remaining parts of Rs and Rd (namely, Rs2 and Rd2) are mostly in the connecting wires, while in the gate resistance and inductance (Rg and Lg) the contribution of the thin gate structure itself is not negligible. From the definition of transconductance and the identification of Cgs as the depletion capacitance, we can write the current source as the product gmVgs, where Vgs is the small-signal voltage across the capacitor Cgs. A parameter often used in characterizing the frequency response of a device is the frequency fT where the gain is equal to 1. Here, the small-signal current gain of the intrinsic FET is equal to 1 when the current through the capacitor equals the generator current, namely when

2p fT Cgs Vgs = gm Vgs

(3.26)

fT = vs /2p L = 1/2pt

(3.27)

or, using (3.25):

The time t, defined by the above equation as the ratio of the gate length to the saturated velocity, represents a transit time for the carriers to cover the gate length from the source to the drain end, and it is therefore an intrinsic delay in the gate operation. Accordingly, a phase shift, w t, is often introduced in the current generator; however, this effect is generally rather small (t is on the order of 10 ps), and it is not the dominant factor limiting the frequency response of the device. This is typically determined by the RC time constant of the input circuit. Through the years, the structure of Figure 3.13 has been modified in a number of ways to enhance noise, speed, or power performance. Noise figure and frequency response are improved mostly by decreasing the effective gate length L and the parasitic source and gate resistances. Power optimization is less straightforward. The output power of a device is determined by the maximum current it can carry and the maximum voltage swing it can withstand. The most obvious way to increase the current is by widening the device: this is generally accomplished by combining a large number of fingers with various interconnecting approaches [38]. As far as the design of the channel is concerned, all the important parameters, such as doping, channel thickness, and channel shape, need to be optimized together, taking into account both voltage and current. We have reproduced in Figure 3.16 a set of actual I-V characteristics measured on a medium-power device. Although devices from different manufacturers share, qualitatively, similar characteristics, the details can vary significantly, and they depend mostly on the specific design of the device channel. The hyperbola limiting the plot in the upper-right corner represents a particular value of power dissipation (in this case 6W) beyond which the measurement could not be carried out because of overheating. A similar boundary limits the safe use of the device from the thermal burnout point of view. As compared to the idealized curves shown in Figure 3.14, here the flat portion is not quite as horizontal. In fact, both the depletion region under the gate and the back barrier are not functions of the gate voltage alone; they depend, albeit slightly, also on the drain bias. The effect is especially noticeable if the gate is very short

3.5  FETs and MESFETs

43

Figure 3.16  Typical I-V characteristics of a power GaAs FET.

with respect to the channel thickness. For similar reasons, also the pinchoff varies with the drain bias. In the example shown, it is approximately 3V at low drain voltages, but close to 3.5V toward the end of the plot. The sharp increase in current at the very end of the curve is due, however, to an altogether different phenomenon, namely the gate-to-drain breakdown. The additional current does not run sourceto-drain, but rather gate-to-drain. This typically represents the main limitation to the available voltage swing. With reference to the load line shown in the figure, it is generally recognized that most often the power output is limited on the left side by the gate drawing forward current and on the right side by gate-to-drain avalanche breakdown [39]. Much effort has been devoted to the understanding and modeling of this phenomenon, which is clearly indicated by gate current, gate waveform clipping [40], and light emission [41]. Some of the most important improvements introduced in the basic FET structure to optimize power performance are summarized in Figure 3.17. A highly doped n+ layer under the ohmic contacts (using either an additional epitaxial layer or a double implantation [42, 43]) reduces source and drain resistances, improves the alloying process, smooths out the border of the contacts, and redistributes the electric field, thereby decreasing the probability of breakdown at the drain edge. As a result, the gate-to-drain voltage can be increased, and now breakdown is observed mostly at the gate edge. The gate recess was also introduced first to increase the breakdown voltage by reducing the concentration of the electric field near the drain [44]. But its benefits are more widespread: as we mentioned earlier, it reduces the effect of the surface depletion regions located in the ungated source-gate and gate-drain

44

Physics of Active Devices

Figure 3.17  Some characteristic features of a MESFET optimized for power.

regions. The channel in these regions is now more open, and parasitic resistances are minimized. Also, the gate-controlled depletion is now better defined, reducing gate capacitance fringing and decreasing the effective gate length. Finally, when properly optimized, the recess allows a redistribution of the potential between gate and drain and a control of the overall gate-drain avalanche breakdown [45, 46]. In the picture, we also show gold-plated source and drain contacts. They reduce resistances and inductances and enable the processing of via holes, which reach the sources from the back, as discussed below. The gate is shown shorter and thicker than in earlier sketches to symbolize the progress towards higher frequencies and the desire to minimize gate inductances. In fact, various T-shaped structures have been successfully implemented, especially at the highest frequencies. We have also included a buffer between the channel and the substrate. We mentioned earlier that the GaAs substrate is not just a simple support, as both Figures 3.13 and 3.15 would suggest. Perfect and intrinsic GaAs material, with an energy gap of 1.43 eV, would have a sufficiently high resistivity (on the order of 108 W-cm) to amply qualify as semiinsulating; but various native imperfections (such as As vacancies, Ga on an As site and similar) act mostly as deep donors, so that compensating impurities (typically Cr or C) have to be introduced to bring the Fermi level back to the center of the band. In addition, crystal dislocations and other structural defects also play a role. The substrate is, therefore, a complicated system, loaded with active centers that affect, in many ways, the performance of the device [47, 48]. The most common approach to reducing substrate effects is the introduction of a thick buffer layer, although such highly resistive layers are not easy to control and often suffer from problems similar to those of the substrate itself [49]. The last two characteristic features of a power device are shown in Figure 3.17(b), since they require a different scale (where the details of the channel cannot be distinguished). They deal with the

3.6  Heterojunction Transistors

45

removal of heat from the active region, one of the main challenges in the design of power devices. Since GaAs is a fairly poor heat conductor, the approach used most often is to thin down the GaAs wafer as much as possible and replace the removed material with a plated heat sink of gold, which conducts heat well, bonds easily, and provides the required mechanical strength. In addition, via holes, also plated with gold, provide a direct connection between the device sources and the bonded back side. Besides helping with heat removal, these vias drastically reduce the source-toground inductance, which is a very important element in determining the gain of the device. For the same reason, different portions of the source are typically connected with plated air bridges. The features we have described stretch as far as possible the power capabilities of a GaAs MESFET. The main limitations one struggles against are avalanche breakdown, poor heat conduction, and degraded performance at high temperatures. Even though bulk properties do not necessarily always apply (in particular concerning breakdown), and different geometries can help, the basic limitations come from the material itself. As we mentioned in Chapter 2, materials with wider energy gaps generally show better thermal characteristics and higher electrical strength. In particular, GaN and SiC have received considerable attention. GaN is used mostly in HEMT-like structures, in combination with AlGaN, and it will be discussed in the next section. There is no such favorable heterojunction for SiC; however, with its unusually good thermal characteristics (in particular, a thermal conductivity as good as the best metals), and an electric field for breakdown four or five times as large as that of Si or GaAs, this material is an ideal choice for high temperatures and high voltage operation. Thus, SiC MESFETs may find their application niche as power devices in thermally challenging environments at relatively limited frequencies.

3.6  Heterojunction Transistors In a semiconductor, both mobility and saturated velocity depend strongly on the presence of impurities and defects. Why these imperfections would scatter electrons and slow down their motion, while the much more numerous ions forming the perfect crystal do not, is an interesting question addressed by Feynman in his lectures [50]. The answer is fundamentally related to the wavelike nature of electrons. The stable solutions of the Schrödinger equation in a periodic potential of ions already take into account the presence of the ions themselves. In a similar way, the electromagnetic field in a resonator is not disturbed by metallic pegs inserted in positions of zero field, but a similar obstacle placed somewhere else gives rise to strong ripples. As the technology of a material matures, crystals become more and more perfect and clean, so that the density of undesired imperfections progressively decreases. Intentional doping (of either donors or acceptors) will still be present, however, because otherwise we would not have any carriers. Or could we? This is the issue behind the development of the high electron mobility transistor (HEMT). Consider a regular MESFET, as described in Section 3.5. The doping used in the active layer is on the order of 1017 cm-3. From the GaAs mobility plot shown in Figure 3.18 (adapted from the Ioffe Institute website [51], assuming a low amount of compensation, namely assuming donors are the main scattering centers), we can

46

Physics of Active Devices

Figure 3.18  Electron drift mobility in GaAs as a function of the doping density.

expect a mobility of approximately 5,000 cm2/Vs, but we see that it could be increased to above 8,000 if the donor density would go down to 1015 or 1014. Given the amount of native defects in GaAs, this is approximately as low as we can hope to bring the total density of scattering centers in undoped material. So, if we can place the donors somewhere else and transfer the generated electrons into an undoped active channel, both mobility and saturated velocity are not limited anymore by the doping, and the frequency response of the device is substantially increased. This is, in fact, accomplished by growing a highly doped layer of AlGaAs on top of undoped GaAs, thereby forming a heterojunction between the two materials. A simplified energy diagram for this structure is shown in Figure 3.19, while a precise calculation can be found in Yoshida’s paper [52]. As we have seen toward the end of Section 3.4, a sharp well is formed at the edge of the smaller bandgap material (GaAs), which collects electrons generated across the interface, in the highly doped AlGaAs. This pocket is so deep and narrow that it is often referred to as a twodimensional electron gas (or 2-DEG) and behaves as the delta function doping we mentioned in Section 3.5, when discussing MESFETs, except that here there is no doping, just electrons. A HEMT (sometimes also called HFET or MODFET) is very similar to a MESFET, except that the active layer is replaced by a heterostructure, which includes a highmobility 2-DEG. A typical example is shown in Figure 3.20. The spacer is introduced to keep the electrons away from the ionized donors (thereby reducing both interdiffusion and scattering), but it is kept very thin (a few 10s Å) to maximize the transfer of electrons to the conducting channel. A lightly-doped layer is also used on the gate side to improve gate breakdown, so that the heavy doping is typically confined to the central region of the AlGaAs layer. To avoid any conduction in this

3.6  Heterojunction Transistors

47

Figure 3.19  Formation of an electron well at the interface between highly doped n-type AlGaAs and undoped GaAs.

layer (which has poor electron drift velocity), the device is designed so that the gate depletion region extends as far as the interface, and only the deep well next to it is swept during the operation. In the figure, we suggest an n+ doping produced by ion implantation (typically Si) in an undoped or lightly-doped AlGaAs layer. A similar structure could be obtained by the epitaxial growth of a sequence of layers, including a thin undoped spacer, a highly-doped donor layer, and a low-doped Schottky contact. Because HEMTs are typically designed for high-frequency operation and gates are extremely short, the use of a T gate has become almost universal, even in power devices. Various processes lead to slightly different shapes, but there is a clear need to decrease the resistance and inductance of the thin gate structure. We have generically indicated a buffer layer. Sometimes this is simply a thick layer of undoped or p-doped GaAs; however, since these epitaxial structures are fabricated mostly by MBE or MOCVD, building a GaAs/AlGaAs super-lattice does not add too much to the original task, and produces a very effective buffer. Initially the HEMT was viewed mostly as a high-frequency, low-noise device, rather than a power one. The power capability is strongly related to the total charge available in the 2-DEG, which does increase with the doping, but is basically limited by the particular semiconductor pair. In the AlGaAs/GaAs case, the maximum sheet

48

Physics of Active Devices

Figure 3.20  Typical HEMT structure. The channel is formed by a heterojunction, including a highmobility 2-DEG. The energy diagram of such a junction is shown in Figure 3.19.

density is in the range of 1.2–1.5 1012 cm-2, but higher densities can be obtained by increasing the difference in the energy gap of the pair forming the junction. In particular, when some In is added to the GaAs, thus forming a compound of the type InxGa1-xAs, the energy gap decreases, while the drift velocity increases, a very desirable combination for the conduction layer. While all the crystals with compositions in the range of GaAs-AlAs (namely all compounds of the type AlxGa1–xAs) have a virtually identical structure, making them ideal candidates for hetero­ junctions. On the contrary, InGaAs compounds have larger lattice constants than GaAs. It was felt, therefore, that they could not be grown free of defects on this substrate. This assumption did not turn out to be true. If the mismatched layer is thin enough, it will adapt to the substrate lattice while still maintaining devicequality crystalline structure. The acceptable thickness decreases with increasing mismatch (or In content). A typical channel with composition In.22Ga.78As may be as thick as 150Å and still conform to the substrate. Such strained layers are called pseudomorphic, and a device based on them is known as a pseudomorphic HEMT (PHEMT). Due to the increased difference in the energy gap, the AlGaAs/InGaAs heterojunction has a much higher carrier concentration than the AlGaAs/GaAs one, reaching sheet densities around 3.5 1012 cm-2. To further increase the currentcarrying capacity, a double heterojunction is often used, at both sides of the pseudomorphic layer. A typical structure of a power device is shown in Figure 3.21. The highly doped layer within the AlGaAs can be either a Si pulse produced by ion implantation or a separate epitaxial layer. There is no special significance in the different shape of the two T gates sketched in Figures 3.20 and 3.21, just an indication that there is a variety of proprietary approaches aimed at increasing the gate cross-section, while minimizing its footprint. Similarly, various slightly different recipes have been used both for the In content in the channel layer and for the Al content in the donor layer. In particular, one tries to minimize the effect of the poorly behaved trap centers DX, which are present in AlGaAs at high percentages of Al, while, on the other hand, the energy gap (and therefore the carrier concentration of the heterojunction) progressively increases as we go from GaAs to AlAs. This leads to an optimal Al content somewhere around .25–.30. In the figure, the source and drain contacts have been

3.6  Heterojunction Transistors

49

Figure 3.21  Typical structure of a power PHEMT. The active layer is formed by InxGa1-xAs and includes two electron wells.

shown sitting on top of the epitaxial structure. In reality, due to the alloying process, they intermingle with the underlying layers, so as to effectively convey charges to and from the conducting channels. Electrically, the operation of a HEMT (including PHEMTs) is quite similar to a MESFET. The I-V characteristics and the equivalent circuits are similar. The main process limiting the power performance is also similar: again, it is mostly the gate-to-drain breakdown. The main differences are related to the much different distribution of carriers. In a uniformly doped MESFET channel, as we have seen in Sections 3.4 and 3.5, the transconductance, gm, (inversely proportional, in the saturated velocity model, to the depth, W, of the depletion region) decreases smoothly with increasing negative gate voltage, leading to a classical compression curve, characterized by progressively decreasing gain. Ion-implanted layers and other graded profiles lead to a more constant transconductance and, thus, more linear transfer characteristics Id(Vg) and sharper compression curves. A significant increase in gain with increasing input power (the so-called gain expansion) is observed only occasionally and mostly in spike-doped devices designed for high linearity, where the depletion region is pinned to the d doping [53]. In HEMTs, on the other hand, carriers are always concentrated in the 2-DEG spike, leading, as a norm, to a peaked transconductance [54] and, frequently, to gain expansion. In addition, the maximum current in a MESFET is sharply limited at positive gate voltages by forward gate conduction, so that, when the input power increases, the current is clipped almost symmetrically by gate conduction on one side and gate-to-drain breakdown on the other. In HEMTs, instead, due to the strong asymmetry of the transconductance, as well as the ability to tolerate positive gate biases with further current increases, the saturation is less smooth and predictable, giving rise to both gain expansions and cancellation effects in the intermodulation [55]. In fact, by varying the relative strength of the two doping peaks in a double heterojunction device, these effects can be maximized, and extremely linear devices have been reported [56]. Other devices of the HEMT family are referred to as metamorphic, to indicate that their epitaxial structure includes changes in the crystal lattice. As an example, a graded buffer of InGaAs may be grown on GaAs with a thickness much above the maximum pseudomorphic limit, so that the layer, initially stretched, relapses progressively to its normal crystal structure. Dislocations originating from this change of lattice are very pronounced near the interface, but their density decreases

50

Physics of Active Devices

toward the top, so that the upper surface is good enough to grow device-quality layers. This approach allows one to build active channels with higher In contents, which generally have higher mobility, but still use GaAs substrates, which are much more readily available and cheaper than InP. The variations and combinations of compositions and structures are endless. Some materials have specific advantages. In particular, InP-based HEMTs have consistently shown the most brilliant performance at very high frequencies [57]. Until very recently, however, we would have said that GaAs PHEMTs (that is, based on GaAs substrates, even though the channel is InGaAs), with a structure close to the one depicted in Figure 3.21, are the dominant solution for power devices at relatively high frequencies, which is the area of interest for this book. What is now changing the picture is the advent of GaN, with its remarkably favorable combination of a high electric field for breakdown (as expected from the large energy gap) and heterojunctions with excellent properties. The best studied is the one with AlGaN, but combinations including InGaN [58] and AlInN [59] have also been explored. These heterojunctions owe their unusual characteristics to the different crystal structure of this new group of semiconductors. As opposed to most of the traditional materials, such as Si, Ge, and GaAs, which crystallize in a cubic lattice, GaN has a hexagonal structure, called Wurtzite. The local bond is still the tetrahedral cluster shown in Figure 3.1, but the tetrahedrons are stacked differently, and the resultant structure has a 6-fold symmetry. Such materials show a strong tendency to spontaneous electrical polarization along the c-axis (the longitudinal axis perpendicular to the hexagonal pattern). If the crystal is strained, it develops additional strong polarization of piezoelectric origin, still along the same axis. As a result, a crystalline layer of GaN, with c-axis perpendicular to the layer itself, will develop sheet charges of opposite signs and equal magnitudes on the two faces, which will be further enhanced if the crystal is strained by growing a pseudomorphic layer of AlGaN on top. This material also shows spontaneous and piezoelectric polarization, but the magnitude is different than in GaN. Therefore, a net charge, equal to the difference in polarization between the two components of the heterojunction, will accumulate at the interface, forming a 2-DEG with densities as high as 1013 cm-2, much higher than one can obtain in GaAs HEMTs, even with the heaviest possible doping [60]. This high carrier density, combined with the ability to work at high voltages (thanks to the high electric breakdown), translates into an excep­ tionally high power density, potentially 40 or 50 times as high as in GaAs PHEMTs. Hopefully, high voltages also lead to higher efficiencies, but, still, the challenge of removing the heat from such a powerful and concentrated source is staggering. Fortunately, the performance of a larger bandgap material is less temperaturedependent, and the devices can therefore operate well at higher temperatures. Also, GaN can be successfully grown on substrates of SiC, one of the best heat-conducting materials in nature. This is so effective in spreading the heat that there is generally no need for via holes, and, therefore, the source contacts are typically from the top. But crystalline SiC, especially the semi-insulating variety, is quite expensive. More economical approaches use a buffer in combination with low-resistivity SiC, which is less expensive, or a thick transition layer on Si substrates. Both solutions represent a cost-effective compromise, at least at lower power densities. The main difficulty with large bandgap materials is the control of the many interface traps

3.6  Heterojunction Transistors

51

and surface states that fall within the large gap. A number of geometrical structures and passivation schemes have been proposed to address this problem, with various degrees of success. The progress of these structure and schemes was recently reviewed by Mishra et al. [61]. A basic device is sketched in Figure 3.22. The thin AlN interlayer has been found to increase band discontinuity and improve both mobility and sheet density. In this sketch, the approach adopted to reduce the effect of surface states is a socalled deep-recessed structure, filled up by a thick AlGaN cap layer. To stress the dominant role of polarization in building the 2-DEG, we have shown no intentional doping, although some Si doping is often used to improve the charge balance and reduce hole accumulation, especially in deep-recessed structures, such as the one shown. The ohmic contacts are typically based on Ti/Al. More complex structures, including double heterojunctions, have also been proposed [62]. Thanks to the similarity of process flow and physical operation between GaAs and GaN HEMTs, the development of these new devices has made a rapid progress, and several production lines are already in place only ten to fifteen years after the first performance demonstrations [63–66]. We conclude this brief review of heterojunction devices with a few words on heterojunction bipolar transistors (HBT). Their main field of application is in wireless communications, especially the handset market, where they hold a dominant position [67]. This is outside the scope of this book; however, these devices offer a unique combination of low phase noise and high linearity that is attractive also for some applications at higher frequencies. A recently opened foundry line dedicated to high power GaInP/GaAs HBT amplifiers [68] may encourage the use of this device in a wider range of applications. In general terms, heterojunctions make it possible to engineer the forces acting on electrons and holes independently of each other. In a semiconductor barrier with uniform gap, electrons and holes are subject to the same electric field (which is essentially the slope of the band edge). This is not true in a heterojunction, where the slope of the two edges can be quite different. This can give a lot of freedom and flexibility. In particular, we have seen, at the end of Section 3.4, how using a wider bandgap semiconductor as the emitter in a bipolar transistor has the effect

Figure 3.22  A GaN HEMT with a deep-recessed structure, filled up by a thick AlGaN cap layer. This is one of the possible approaches used to minimize the effect of surface states.

52

Physics of Active Devices

of increasing the ratio between the electron current injected into the base and the opposite hole current, or in other words, increasing the emitter efficiency. In addition, electrons overcoming the barrier will be injected in the base with additional energy (above the conduction band edge), thus with additional velocity, an effect that will reduce the transit time in the base. On the other hand, the sharp notch in the conduction band, which traps electrons and therefore slows them down (increasing the probability of recombination), can be eased and virtually eliminated by grading the junction and increasing the p-type doping in the base. In traditional n-p-n bipolars fabricated from a single semiconductor, the emitter generally has a higher doping density than the base, in order to favor the electrons’ current over the holes’ current. Since here a high ratio of electron-to-hole flow is already guaranteed by the band discontinuity, one is free to use a high doping in the base. The thickness of the base can then be reduced (thereby reducing transit time) without increasing its resistance, and the modulation of the base region under high electric fields can be minimized. At the same time, the use of a higher bandgap semiconductor and the ability to decrease the emitter doping help to improve voltage breakdown. A sketch of a GaInP/GaAs HBT is shown in Figure 3.23. This picture refers to a particular combination of materials, but several others (including the classical pair, AlGaAs/GaAs, which was dominant in all the initial development) have been used successfully. We chose this example because it represents at the moment the state of the art in the field of applications that is the focus of this book. But we should mention that Si/SiGe HBTs have been very successful in broadband wireless amplifiers [69], while InP-based devices hold, as usual, the high-frequency record [70]. In Figure 3.23, the arrows indicate the electron flow, which is transversal to the heterojunctions. We recall that, in the FET family, the main current runs instead along the substrate, within a conducting layer of limited thickness. In a HEMT, it is virtually two-dimensional (the familiar 2-DEG we have discussed so many times). In fact, the power capability of a FET is generally quoted in a watts per unit gate width. As a result of this, a high-power FET requires a relatively extensive surface, which translates almost directly into a high price, since the cost of a device or a

Figure 3.23  Structure of a GaInP/GaAs HBT designed for high power at X-band. The arrows indicate the electron flow. E, B and C denote, respectively, the emitter, the base, and the collector contacts.

3.6  Heterojunction Transistors

53

monolithic integrated circuit is determined to a large extent by the substrate area. Also, the main current is channeled on both sides by interfaces, where deep traps are generally present. The capturing and releasing of charges is thus a major physical origin of the low-frequency (1/f) noise. Finally, the asymmetrical control of the current flow from the upper side typically results in a decrease of the transconductance with increasing gate voltage, which is a main source of nonlinearity. Conversely, in bipolar transistors, the flow is perpendicular to the substrate and has similar dimensions in both directions. Currents and powers are measured per unit surface, and considerable powers can be concentrated in much reduced substrate areas. The ensuing advantage in both size and price is a major factor in the dominant position of HBTs in the wireless handset market. As we will discuss in more detail in Chapter 5, we also view the vertical flow, with carriers crossing the barriers rather than grazing them, as the root cause of the lower 1/f noise of bipolar devices, while the uniform control over the whole cross-section of the current is arguably responsible for a superior linearity. On the other side of the coin, the compact size poses a severe challenge from the thermal management point of view, both in CW and in pulsed operation [71]. Special features, such as ballasts, are required to prevent thermal runaway [72, 73], and accurate thermal modeling is a must [74].

References   [1] Sze, S. M., Physics of Semiconductor Devices, 2nd ed., Wiley, 1981.   [2] Kittel, C., Introduction to Solid State Physics, 8th ed., Wiley, 2005.   [3] Ashcroft, N.W., and N. D. Mermin, Solid State Physics, Pacific Grove, CA: Brooks Cole, 1976.   [4] Harrison, W. A., Solid State Theory, Dover Publications, 1980.   [5] ece-http://www.colorado.edu/~bart/book, last accessed April 30, 2009.   [6] Feynman, R. P., R. B. Leighton, and M. Sands, The Feynman Lectures on Physics, Vol. 3, Addison Wesley Longman, 1970.   [7] Phillips, J. C., “Ionicity of the Chemical Bond in Crystals,” Rev. Mod. Phys., Vol. 42, 1970, pp. 317–356.   [8] Kimball, G. E., “The Electronic Structure of Diamond,” J. Chem. Phys., Vol. 3, 1935, pp. 560–564.   [9] Brillouin, L., Wave Propagation in Periodic Structures, Dover Publications, 1953. [10] Mott, N. F., and H. Jones, The Theory of the Properties of Metals and Alloys, Dover Publications, 1958, pp. 51–56. [11] Fowler, R. H., Statistical Mechanics: The Theory of the Properties of Matter in Equilibrium, U.K.: Cambridge University Press, 2nd ed., 1980. [12] Houston, P. A., and A. G. R. Evans, “Saturation Velocity of Electrons in GaAs,” IEEE Trans. on Electronic Devices, Vol. ED-23, 1976, pp. 584–586. [13] http://www.ioffe.ru/SVA/NSM/Semicond/, last accessed April 30, 2009. [14] Bujatti, M., “CdS-Metal Barriers from Photovoltage Measurements,” J. Phys. D, Vol. 1, 1968, pp. 581–584. [15] Cowley, A. M., and S. M. Sze, “Surface States and Barrier Height of Metal-Semiconductor Systems,” J. Appl. Phys., Vol. 36, 1965, pp. 3212–3220. [16] Sze, S. M., Physics of Semiconductor Devices, 2nd ed., Wiley, 1981, pp. 250–254. [17] Sze, S. M., Physics of Semiconductor Devices, 2nd ed., Wiley, 1981, pp. 254–270.

54

Physics of Active Devices [18] Sze, S. M., Physics of Semiconductor Devices, 2nd ed., Wiley, 1981, pp. 93–104. [19] Lin, H. C., et al., “Optimization of AuGe-Ni-Au Ohmic Contacts for GaAs Mosfets,” IEEE Trans. on Electronic Devicest, Vol. 50, 2003, pp. 880–885. [20] Shockley, W., “The Theory of p-n Junctions in Semiconductors and p-n Junction Transistors,” Bell Syst. Tech. J., Vol. 28, 1949, pp. 435–489. [21] Moll, J. L., “The Evolution of the Theory of the Current-Voltage Characteristics in p-n Junctions,” IRE Proc., Vol. 46, 1958, pp. 1076–1082. [22] For a historical review, see [1], pp. 122–123, and Alferov, Z. I., “Nobel Lecture: The Double Heterostructure Concept and Its Applications in Physics, Electronics and Technology,” Rev. Mod. Phys., Vol. 73, 2001, pp. 767–782. [23] Kroemer, H., “Heterostructure Bipolar Transistors and Integrated Circuits,” Proc. IEEE, Vol.70, 1982, pp.13–25. Also in Tiwari, S., (ed.), Compound Semiconductor Transistors: Physics and Technology, IEEE Press, 1993. [24] Kroemer, H., “Theory of a Wide-Gap Emitter for Transistrors,” IRE Proc., Vol. 45, 1957, pp. 1535–1537. [25] Kocot, C., and Stolte, C. A., “Back-Gating in GaAs MESFETs,” Trans. on Electronic Devices, Vol. 29, 1982, pp. 1059–1064. Also in Tiwari, S., (ed.), Compound Semiconductor Transistors: Physics and Technology, IEEE Press, 1993, pp. 107–112. [26] Miller, D. J., and M. Bujatti, “Mechanisms for Low-Frequency Oscillations in GaAs FETs,” IEEE Trans. on Electronic Devices, Vol. 34, 1987, pp. 1239–1244. Also in Tiwari, S., (ed), Compound Semiconductor Transistors: Physics and Technology, IEEE Press, 1993, pp. 91–96. [27] Forbes, L., “On the Theory of 1/f Noise of Semi-Insulating Materials,” IEEE Trans. on Electronic Devices, Vol. 42, 1995, pp. 1866–1868. [28] Ohno, Y., “Surface-State Effects on GaAs FET Electrical Performance,” IEEE Trans. on Electronic Devices, Vol. 46, 1999, pp. 214–219. [29] Liechti, C. A., “Microwave Field-Effect Transistors-1976,” IEEE Trans. on Microwave Theory and Techniques, Vol. 24, 1976, pp. 279–300. [30] Wada, T., and Frey, J., “Physical Basis of Short-Channel MESFET Operation,” IEEE Trans. on Electronic Devices, Vol. 26, 1979, pp. 476–490. [31] Shur, M. S., and L. F. Eastman, “Current-Voltage Characteristics, Small-Signal Parameters and Switching Times of GaAs FETs,” IEEE Trans. on Electronic Devices, Vol. 25, 1978, pp. 606–611. [32] Williams, R. E., and D. W. Shaw, “Graded Channel FET’s Improved Linearity and Noise Figure,” IEEE Trans. on Electronic Devices, Vol. 25, 1978, pp. 600–605. [33] Ruch, J. “Electron Dynamics in Short Channel Field-Effect Transistors,” IEEE Trans. on Electronic Devices, Vol. 19, 1972, pp. 652–654. [34] See [8] above or [1], pp. 333–334. [35] Williams, R. E., and D. W. Shaw, “GaAs FETs with Graded Channel Doping Profile,” Electron. Lett., Vol. 13, 1978, pp. 408–409. [36] Pucel, R. A., “Profile Design for Distortion Reduction in Microwave Field-Effect Transistors,” Electron. Lett., Vol. 14, 1979, pp. 204–206. [37] Chu, S. L. G., et al., “A Highly Linear MESFET,” 1991 IEEE MTT-S Int. Microwave Symp. Digest, 1991, pp. 725–728. [38] Di Lorenzo, J. V., and W. R. Wisseman, “GaAs Power MESFETs: Design, Fabrication, and Performance,” IEEE Trans. on Microwave Theory and Techniques, Vol. 27, 1979, pp. 367–378. [39] Frensley, W. R., “Power Limiting Breakdown Effects in GaAs MESFETs,” IEEE Trans. on Electronic Devices, Vol. 28, 1981, pp. 962–970. [40] Sechi, F., H. Huang, and B. Perlman, “Waveforms and Saturation in Power MESFETs,” Proc. of 8th European Microwave Conference, Paris, 1978, pp. 473–477. [41] Yamamoto, R., et al., “Light Emission and Burnout Characteristics of GaAs Power MESFETs,” IEEE Trans. on Electronic Devices, Vol.25, 1978, pp. 567–573.

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[42] Fukuta, M., et al., “Power GaAs MESFET with High Drain-Source Breakdown Voltage,” IEEE Trans. on Microwave Theory and Techniques, Vol. 24, 1976, pp. 312–317. [43] Stoneham, E., T. S. Tan, and J. Gladstone, “Fully Ion Implanted GaAs Power FETs,” Int. Electron Device Meeting Technical Digest, 1977, pp. 330–333. [44] Hasegawa, F., et al., “GaAs Power MESFETs with a Simplified Recess Structure,” ISSCC Technical Digest, February 1978, pp. 118–119. [45] Wemple, S. H., et al., “Control of Gate-Drain Avalanche in GaAs MESFETs,” IEEE Trans. on Electronic Devices, Vol. 27, 1980, pp. 1013–1018. Also in Tiwari, S., (ed.), Compound Semiconductor Transistors: Physics and Technology, IEEE Press, 1993, pp. 78– 83. [46] Mizuta, H., K. Yamaguchi, and S. Takahashi, “Surface Potential Effect on Gate-Drain Avalanche Breakdown in GaAs MESFETs,” IEEE Trans. on Electronic Devices, Vol. 34, 1987, pp. 2027–2033. [47] Wang, F. C., and M. Bujatti, “Experimental Correlation Between Substrate Properties and GaAs MESFET Transconductance,” IEEE Electronic Development Letters, Vol. 5, 1984, pp. 188–190. [48] Miyazawa, S., and F. Hyuga, “Proximity Effect of Dislocations on GaAs MESFET Threshold Voltage,” IEEE Trans. on Electronic Devices, Vol. 33, 1986, pp. 227–233. Also in Tiwari, S., (ed.), Compound Semiconductor Transistors: Physics and Technology, IEEE Press, 1993, pp. 84–90. [49] Itoh, T., and H. Yanai, “Stability of Performance and Interfacial Problems in GaAs MESFETs,” IEEE Trans. on Electronic Devices, Vol. 27, 1980, pp. 1037–1045. [50] Feynman, R. P., R. B. Leighton, and M. Sands, The Feynman Lectures on Physics, Vol. 3, Addison Wesley Longman, 1970, pp. 13.1–13.3. [51] http://www.ioffe.ru/SVA/NSM/Semicond/GaAs/Figs/433b.gif, last accessed April 30, 2009. [52] Yoshida, J., “Classical Versus Quantum Mechanical Calculation for the Electron Distribution at the n-AlGaAs/GaAs Heterointerface,” IEEE Trans. on Electronic Devices, Vol. 33, 1986, pp. 154–156. Also in Tiwari, S., (ed.), Compound Semiconductor Transistors: Physics and Technology, IEEE Press, 1993, pp. 156–158. [53] Chu, S. L.G., “A Highly Linear FET,” 1991 IEEE MTT-S Int. Microwave Symp. Digest, 1991, pp. 725–728. [54] Hughes, W. A., and C. M. Snowden, “Nonlinear Charge Control in AlGaAs/GaAs Modulation-Doped FETs,” IEEE Trans. on Electronic Devices, Vol. 34, 1987, pp. 1617–1625. Also in Tiwari, S., (ed.), Compound Semiconductor Transistors: Physics and Technology, IEEE Press, 1993, pp. 159–167. [55] Bailey, M. J., “Intermodulation Distortion in Pseudomorphic HEMTs and an Extension of the Classical Theory,” IEEE Trans. on Microwave Theory and Techniques, Vol. 48, 2000, pp. 104–110. [56] Chiu, H. C., et al., “Microwave Performance of Double Delta-Doped High Electron Mobility Transistor with Various Lower/Upper Planar-Doped Ratio Designs,” IEEE Trans. on Electronic Devices, Vol. 55, 2008, pp. 256–260. [57] Pukala, D., et al., “Submillimeter-Wave InP MMIC Amplifiers from 300–345 GHz,” IEEE Microwave Wireless Comp. Letters, Vol. 18, 2008, pp. 61–63. [58] Liu, J., et al., “DC and RF Characteristics of AlGaN/GaN/InGaN/GaN DoubleHeterojunction HEMTs,” IEEE Trans. on Electronic Devices, Vol. 54, 2007, pp. 2– 10. [59] Gaquiere, C., et al., “AlInN/GaN a Suitable HEMT Device for Extremely High Power High Frequency Applications,” 2007 MTT-S Int. Microwave Symp. Digest, 2007, pp. 2145– 2148. [60] Eastman, L. F., et al., “Power Limits of Polarization-Induced AlGaN/GaN HEMTs,” Proc. 2000 IEEE/Cornell Conf. on High Perf. Dev., 2000, pp. 242–246.

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Physics of Active Devices [61] Mishra, U. K., et al., “GaN-Based RF Power Devices and Amplifiers,” IEEE Proc., Vol. 96, 2008, pp. 287–305. [62] Palacios, T., et al., “Use of Double-Channel Heterostructures to Improve the Access Resistance and Linearity in GaN-based HEMTs,” IEEE Trans. on Electronic Devices, Vol. 53, 2006, pp. 562–565. [63] Therrien, R., et al., “AlGaN/GaN HFETs on Si Substrates for WiMAX Applications,” 2006 MTT-S Int. Microwave Symp. Digest, 2006, pp. 710–713. [64] Gassmann, J., et al., “Wideband, High-Efficiency GaN Power Amplifiers Utilizing a NonUniform Distributed Topology,” 2007 MTT-S Int. Microwave Symp. Digest, 2007, pp. 615–618. [65] Kao, M. Y., “High-Efficiency and Low-Noise AlGaN/GaN HEMTs for K and Ka-Band Applications,” 2007 CS MANTECH Conf. Proc., 2007, pp. 61–64. [66] Milligan, J. W., et al., “SiC and GaN Wide Bandgap Device Technology Overview,” 2007 IEEE Radar Conf. Proc., 2007, pp. 960–964. [67] Zampardi, P. J., “GaAs Technology Status and Perspectives for Multi-Band and MultiStandard Challenges in Upcoming RF-Frontends,” 2008 IEEE Radio and Wireless Symp. Digest, 2008, pp. 187–190. [68] Couturier, A. M., et al., “A Robust 11W High Efficiency X-Band GaInP HBT Amplifier,” 2007 MTT-S Int. Microwave Symp. Digest, 2007, pp. 813–816. [69] Rieh, J-S. “A Brief Overview of Modern High Speed SiGe HBTs,” 2006 ICSICT Int. Conf. Digest, 2006, pp. 170–173. [70] Radisic,V., et al., “Demonstration of 184 and 255-GHz Amplifiers Using InP HBT Technology,” IEEE Microwave and Wireless Comp. Lett., Vol. 18, 2008, pp. 281–283. [71] Floriot, D., et al., “Thermal Management of Power HBT in Pulsed Operating Mode,” 2005 European Microwave Conf., Vol. 3, 2005, 4 pp. [72] UMS, “X-Band GaInP HBT 10W High Power Amplifier Including On-Chip Bias Control Circuit,” 2003 MTT-S Int. Microwave Symp. Digest, 2003, pp. 855–858. [73] Dong-Yue, J. et al., “Ballasting Resistor Optimum for the Self-Heating Effect Compensation in RF Power HBTs,” 2006 ICSICT 8th Int. Conf. Digest, 2006, pp. 224–226. [74] Burton, R., and Vijayakumar, B., “Compact Thermal Model for HBT Devices,” 2006 ITHERM Conf. Proc., 2006, pp. 653–659.

Chapter 4

Device Characterization and Modeling 4.1  Introduction The linear response of an active device in the vicinity of a specific bias point and at a specific temperature is completely defined by its small-signal S-parameters, measured as a function of frequency. While for packaged devices the measured Sparameters are often used directly for the circuit design, for devices in chip form it may be more convenient to use the measured S-parameters to define a small-signal model that, in turn, is used to design the circuit. There are several advantages to this approach: specifically, it (1) allows an intuitive comparison of different devices for diagnostic or replacement purposes; (2) offers a useful guide for the design of the tuning circuits; (3) allows extrapolation to frequency ranges where S-parameters may not be directly available; and (4) results in a characterization that is broadband, while using only a few circuit parameters. The large-signal characterization is far more complex, and there is no largesignal S-parameters test that fully defines the device in all its facets. In practice, a combination of different measurements is generally used. Then it might be possible to synthesize the results into a large-signal model derived from the device’s physics, but the fit is seldom as good as in the small-signal case. Alternatively, mathematical models, often in the form of expansion series, might be derived from the large-signal measurements. These black box behavioral models do not make any assumptions about the active device. Instead, they translate the black box transfer function, usually in the form of AM/AM and AM/PM data, into a mathematical algorithm that computes operational characteristics, such as intermodulation performance. In this chapter, we will deal mostly with the S-parameters and the equivalent-circuit approach. Since behavioral models are used most often for predicting intermodulation or similar linearity-related effects, we will cover them as part of the linear amplifier design in Chapter 10. Behavioral models may be the only practical approach for the analysis of complex nonlinear systems.

4.2  Small-Signal Characterization and Models The small-signal characterization of active devices is carried out by measuring the small-signal S-parameters using a vector network analyzer (VNA). This type of measurement is common, well documented, and, with proper equipment, very accurate, even above millimeter-wave frequencies. The device, in our case a transistor, is typically biased for operation in class A, and the peak of the RF signal is kept small with respect to the bias voltage and current. Thus, the S-parameters are a measure of the incremental linear response of the device around the bias point. 57

58

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Eight numbers are needed to define the S-parameters at each frequency; thus, a full set of S-parameters over a wide frequency range can be a rather large file. A more compact way of characterizing the device is to derive an equivalent circuit model. The model is composed by constant elements, such as capacitors, inductors, resistors, and controlled generators, which can be associated to physical parameters of the device, as we have seen in Chapter 3 for the MESFET. The frequency response of the model is a result of the topology of the circuit. Thus, relatively few parameters can describe a device over a very wide range of frequencies and biases. 4.2.1  MESFET and HEMT Small-Signal Model

Since both MESFETs and HEMTs have an FET structure, we’ll assume that their models are sufficiently similar to be treated together. Figure 4.1 is a typical model for these devices in chip form. The physical origin of the circuit elements was discussed in Chapter 3 and displayed in Figure 3.15. The components Rg, Lg, Rd, Ld, Rs, and Ls are associated with resistances and inductances of the gate, drain, and source connections, including bond wires. The components Cgs and Rgs represent the gate-to-channel impedance, while the capacitor Cgd denotes the capacitive coupling between drain and gate. The output current generator is controlled by Vgs through the transconductance gm. Also associated with the generator is a delay, t, which stands for the transit time associated with the carrier transport through the channel. Finally, the output impedance is represented by Rds and Cds. The simplest and fastest way to derive a small-signal equivalent circuit model is to automatically adjust the values of the circuit elements (the model parameters) to reproduce the measured S-parameters, using the optimization routine that is part of most computer programs for microwave circuits. If the convergence routine shows signs of instability (in other words, if more then one set of model parameters can fit the measured S-parameters), it might be useful to add a separate set of measured data. For instance, one could measure the S-parameters of the same device at zero

Figure 4.1  FET small-signal model.

4.2  Small-Signal Characterization and Models

59

bias. This is often referred to as a cold test. In this case, the operation of the intrinsic device is much simpler, and it can be modeled, for instance, by a distributed network of capacitors and resistors, as shown in Figure 4.2. The intrinsic device is now characterized by only two variables, R and C, and the modeling of the components associated with the gate, drain, and source connections can be carried out with a higher degree of confidence [1]. This method, based on fitting S-parameters, is simple and convenient to carry out, but still may not give consistent results. A better technique, which gives more precise and consistent results, is based on the direct extraction of the values of the circuit elements from the Z- and Y-parameters, which, in turn, are derived from the S-parameters of the device [2–4]. In particular, achieving consistent results is important when deriving a large-signal model from S-parameters measured at different biases, as described in Section 4.3.3, or when the equivalent circuit is used for device diagnostics [1]. Typically, the fitting of the equivalent circuit in Figure 4.1 to the measured Sparameters of a device in chip form is excellent over a very wide band. However, if the device is in a package, the fitting might not be equally good, because the model of the package is often not well known, and the additional circuit variables associated with the package add uncertainty and affect the precision of the computed model parameters. Thus, when working with packaged devices, it is often more convenient to work directly with measured S-parameters. 4.2.2  HBT Small-Signal Model

A typical model for a heterojunction bipolar transistor (HBT) is shown in Figure 4.3. The components Rb, Lb, Rc, Lc, and Le are associated with resistances and inductances of the base, collector, and emitter connections between the intrinsic device and the surrounding circuit. As for the FET model, the simplest and fastest way to derive a small-signal model from the measured S-parameters is to use an optimizing modeling routine that is part of most computer programs for microwave

Figure 4.2  FET model for a cold test.

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Figure 4.3  HBT small-signal model.

circuits. Also, cold tests, for instance by shorting the collector to the emitter and reverse-biasing the base, might be useful for a more precise derivation of some of the model elements. As with FETs, the direct extraction of the circuit parameters [2, 3], although more complex, gives more consistent results. A number of papers have dealt with parameter extraction techniques that give accurate results up to millimeterwave frequencies [5–10]. As for FETs, typically the model is accurate only for devices in chip form.

4.3  Large-Signal Characterization While for small-signal operation a device is fully characterized by a set of S-parameters, no equivalent measurement of large-signal S-parameters is sufficient to fully characterize a nonlinear device. Often the large-signal characterization requires additional measurements, such as S-parameters versus bias and load pull. 4.3.1  Load Pull

The idea behind the load-pull testing of power devices is that some of the most important operating characteristics (output power, efficiency, and intermodulation) are strongly dependent on the load impedance and are only weakly dependent on the source impedance. Thus, the power device may be characterized by varying its load impedance and monitoring the resulting performance. The results are often in the form of impedance contours plotted on a Smith chart. A typical system setup for output power load-pull measurements is shown in Figure 4.4 [11]. The signal from the RF source is usually amplified to reach a level adequate to saturate the device, and it is cleaned from harmonics by a low-pass filter (LP). Also, the reflections are suppressed by an isolator (Isol). An input prematching tuning circuit (Inp Tng) allows the efficient transfer of power from the 50W impedance of the isolator to the input impedance of the device under test

4.3  Large-Signal Characterization

61

Figure 4.4  Load-pull test set.

(DUT). Similarly, the output prematching tuning circuit (Out Tng) facilitates an efficient transfer of power from the output of the DUT to the tuner. The mechanical tuner can be precisely adjusted over a wide range of impedances, while the power, filtered from harmonics and sampled at the output of a power attenuator (Att), is measured and recorded. A computer controller sets the frequency and the power of the RF source, monitors the RF input power and the DC power of the power supplies biasing the DUT, operates the tuner through an algorithm, and records the output power. The results are then displayed, often on a Smith chart. The input and output prematching circuits—Inp Tng and Out Tng—can be designed to match the input and output ports of the device simply on the basis of the small-signal S-parameters of the device. Although small-signal matching is not correct for operation under large signals, this prematching is adequate to reduce mismatches to an acceptable level and to allow the tuner to operate with low loss. The set of S-parameters of the Out Tng prematching circuit, when entered in the computer program, allows the system software to compute the impedance through the prematching circuit and to display, with high accuracy, the impedance as seen at the output of the DUT. Similarly, the input prematching circuit provides sufficiently low reflections for an efficient delivery of the RF power at the input of the device. Although useful for measurement accuracy, these prematching circuits limit the bandwidth; thus, the basic test set of Figure 4.4 is sometimes modified by removing the pretuning circuits and adding a second computer-controlled tuner at the input. For this configuration, the tuners must be designed to operate with low loss, even under very high reflections. The key component is the mechanical tuner. An example of a coaxial doubleslug tuner is shown in Figure 4.5. A slotted 50W coaxial line has two low-impedance

Figure 4.5  Double-slug tuner.

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Device Characterization and Modeling

lines (slugs) riding on the center conductor. One end of the line is terminated on 50W; the other side is the test port. The slugs are positioned along the line by highprecision driving mechanisms powered by two precision stepper motors. The slugs have a metal core that is capacitively coupled to the line through a dielectric layer. Their electrical length is short, relative to the wavelength, and when their separation is approximately 1/4 wavelength, the two reflections cancel at the test port and the corresponding impedance is 50W. When the spacing between the slugs is approximately 1/2 wavelength, the reflections of the slugs add at the test port and the reflection coefficient reaches its maximum value. If the slugs are shifted along the line while keeping their relative distance constant, the phase of the reflection coefficient at the test port varies linearly with their position along the line, while the amplitude remains constant. Thus, by varying the position of the slugs, the tuner can be set for any reflection coefficient of amplitude ranging from zero to a maximum value that is determined by the physical parameters of the slugs and the frequency. A different type of tuner used in load-pull systems is the one based on an adjustable probe coupled to a 50W line. Figure 4.6 shows a typical construction using a slab 50W line, which consists of a center conductor centered within two ground planes. The center conductor is close to the ground plains. Thus, the electromagnetic field is concentrated in the narrow gap, and practically no energy is radiated through the open sides. The probe is capacitively coupled to the center conductor, and its position can be adjusted, both in the x and y directions, by a high-precision mechanism powered by stepper motors. Thus, the reflection coefficient at the test port can be adjusted for any phase and any magnitude between zero and a maximum value that is determined by the physical parameters of the probe and by the frequency. When comparing the two types of tuners, we find that the probe tuner is very broadband, while the practical operating range of a double-slug tuner is limited to about one octave. The double-slug tuner is easy to build in a very stable form, however, while the probe tuner requires a much more elaborate construction to achieve the required mechanical stability.

Figure 4.6  Probe tuner.

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63

After the tuner is fabricated, it requires a calibration. Two approaches are available. The first approach is to measure the S-parameters of the tuner at different settings and over a wide frequency range and derive from these measurements an equivalent circuit of the tuner, or model, that describes electrically the line and the tuning elements as a function of position. The resulting model is defined by a small set of parameters, specifically, characteristic impedances and distances, that fully describe the tuner at any frequency and any impedance within the prescribed ranges. Therefore, the calibration results in a compact set of data [11]. The second approach is to simply measure the tuner at different positions and frequencies and to store all the data. The various positions and frequencies might be chosen with a criterion that maintains a continuity of the reflection coefficient versus position and frequency, so as to allow interpolation. Still, since each set of four S-parameters comprises eight numbers, a calibration set that covers a large number of frequencies and a large number of tuner settings can be very large indeed. With the present availability of large memory storage, however, this approach is viable, and, in fact, it’s commonly used in commercial systems. A computer-controlled load-pull system requires a search algorithm, and again there are two distinct approaches. The first approach is based on a gradient technique [11], and it is shown schematically in Figure 4.7, where W(G) is the surface representing the parameter being searched (output power or efficiency, for instance) subtended by the plane of the reflection coefficient G, which is, in fact, the Smith chart. Depicted in this figure is the search for the maximum of the function W. The search starts by sampling the function at the starting point, 1, and computing the gradient at that point as:



∇W = ar

¶W 1 ¶W + aq ¶r r ¶q

(4.1)

where ar and aq are unit vectors in the radial and tangential directions, respectively.

Figure 4.7  Gradient-guided search algorithm.

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Device Characterization and Modeling

The angle of the gradient defines the direction of the maximum change of W. Two steps are taken in that direction (points 2 and 3), and the function is sampled at those points. A second-order polynomial (a parabola) is fitted through the three points, the position of the vertex is computed, the gradient is recomputed at that point, and the process is restarted and then repeated, until point M (the maximum) is reached. After finding the maximum of the function, it is of particular interest to find the loci of the points for which the function assumes a constant value. This is represented by a horizontal cross section of the surface W. The search starts at a point where W assumes the required value. The search for the next point, for which W has the same value, is performed by computing the gradient, taking a step in the direction orthogonal to the gradient, and then running a narrow sweep centered on that direction until the point is found [11]. The process is repeated until the line, for a specified value of W, is defined on the G plane. This line is often described as a contour. The second search approach is based on measuring the parameter of interest (for instance, output power) at some preset impedance points evenly distributed on the Smith chart. A mathematical function fitted through the points approximates the surface W. The function maximum and the locus of the constant value of W are then derived mathematically. The mathematical surface can be in the form of a polynomial or of a three-dimensional spline [12], which is a function of the reflection coefficient. Points of interest, such as the reflection coefficient (in other words, impedance on the Smith chart) corresponding to the maximum of the function, or to any given constant value of the function, can be derived using a mathematical engine. When comparing the two search approaches, we find that the first approach is more efficient from the computational point of view, because the computations are simple. The measurement and search process is efficient, however, only if the function W is analytical, or, in other words, if the derivatives of the function are independent of the direction of approach. For power devices, this cannot be taken for granted, because heating, for instance, can create hysteresis effects that cause irregularities in the derivatives. Although the search algorithm might recover, this comes at the expense of efficiency. The second approach is more robust, since the testing process is empirical and doesn’t require any degree of regularity for the function; the smoothing of the function is achieved mathematically. The computation is more complex, but it can be performed efficiently, and, in fact, this approach is often adopted in commercial systems. An example of the load-pull results for a 500-mW GaAs MESFET is shown in Figure 4.8. Point A represents the load impedance for maximum output power at 4.4 GHz, while the inner and outer contours centered around point A are the loci of the load impedance for output powers of 1 dB and 2 dB below the maximum, respectively. Similar results are shown for the upper end of the band, at 5.0 GHz. Similar tests were performed at the intermediate frequencies in the band, and ZL opt is the load impedance for maximum output power over the 4.4–5.0-GHz frequency range. Also shown on the Smith chart is the complex conjugate of the small-signal output impedance of the device (S22*), which is the load impedance that would result in minimum output reflection and, thereby, maximum gain. In this example, the impedances are referred to the terminals of the packaged device, and

4.3  Large-Signal Characterization

65

Figure 4.8  Example of load-pull.

there is no obvious connection between ZLopt and S22*. As described in Section 8.6, however, an interesting connection does develop if the reference is moved to the intrinsic device. A somewhat different approach is adopted in the active load-pull technique [13–15], which is based on injecting an RF signal at the output of the DUT. By varying the amplitude and phase of the signal, it is possible to synthesize the load impedance presented to the active device. The system does not require a mechanical tuner and can be built with standard off-the-shelf components. It does require, however, a vector network analyzer (VNA) permanently connected to the test set that computes the synthesized load impedance from samplings of the incident and reflected wave. Its main limitation is that the RF signal must be a single carrier; thus, the system cannot be used for intermodulation measurements (see Chapter 10), nor can it be used with modulated RF signals, as required for adjacent channel power ratio (ACPR) measurements. It might be used with pulsed signals if the VNA can operate in that mode, but even in this case, the load-pull system might be severely limited by the pulsing range capability of the VNA. Another practical limitation is that it is often very difficult to maintain the stability of the DUT through a broad range of output load impedances. Finally, another modification of the basic setup is used for harmonic tuning [16, 17]. In a system with a mechanical tuner, this is typically done by adding harmonic probes. As we will see in Chapter 9, the control of the harmonics is important to achieving high RF efficiency.

66

Device Characterization and Modeling

4.3.2  Large-Signal Parameters: AM/AM and AM/PM

A simple and basic setup to measure large-signal parameters is shown in Figure 4.9. The signal from the RF source is fed into a power amplifier, which in turn feeds the device under test (DUT). The output of the DUT is terminated into a load (T), and there is a provision for measuring the level of the input power. The incident and reflected waves at the input and output of the DUT, sampled through couplers, are fed into a vector network analyzer (VNA). With the possible exception of the high-power source, it is clearly identical to an S-parameter setup. Thus, for simplicity, we’ll retain the standard S-parameter nomenclature. We must point out to the reader, however, that, although we can define each parameter as a function of power, it is not possible to link the input and output parameters to specific power levels; thus, we cannot assemble a consistent four-parameter set, and there is no technical validity in a large-signal S-parameter set. The simple test set of Figure 4.9 measures the large-signal S11 and S21, while the additional parameters, S22 and S12, must be derived by reversing the DUT. Since the measurement of these large-signal parameters (just as for the standard S-parameters) is based on wave-amplitude ratios, within the dynamic range of the VNA the response of the VNA is independent from the level of the RF signal. Thus, any change in the parameters as a function of the RF level is attributed to a change of the DUT. While the large-signal S11 can be used directly to design the input-tuning circuit, the large-signal S22 cannot be used in a similar way for the design of the output circuit. Rather, as described in Chapter 8, the design of the output circuit must be based on different techniques such as load-pull, load-line estimation or large-signal modeling. As described in Section 8.6, however, there is a link between the impedance that the output circuit must present to the device to achieve the maximum output power and the complex conjugate of S22. Specifically, both impedances have substantially the same value of reactance. This applies, however, only when both impedances are referred to the intrinsic device. This feature, in fact, is used in the design technique described in Section 8.6. Of particular importance is the measurement of S21, because it defines the transfer function of the DUT as a function of power. Specifically, the change of the gain as a function of power defines the amplitude-to-amplitude (AM/AM) conversion, while the change of the phase as a function of power defines the amplitude-to-phase (AM/PM) conversion. Both the AM/AM and the AM/PM conversions contribute

Figure 4.9  Basic large-signal S-parameters test set.

4.3  Large-Signal Characterization

67

to intermodulation and spectrum spreading (see Chapter 10); thus, they are often important parameters in the specification of a microwave system. As an example of amplitude and phase distortion, Figure 4.10 shows the test results at 8 GHz for a high-gain 6–18-GHz, 3W power amplifier. For an input power below -21 dBm, both gain and phase are almost constant. As the power increases, the gain decreases steadily. At 10 dBm, it is about 1.8 dB below the small-signal value. This change of gain versus input power is a measure of the amplitude distortion. Similarly, the phase of the output signal, referenced to the phase at a low level, changes with input drive and varies rapidly above -16 dBm. This change of phase between the input and output signal, as a function of power, is a measure of phase distortion. The absolute value of the phase shift between the input and output signals is not significant in itself. What is significant is how the phase changes with a change of input power. Thus, phase distortion (in other words, the AM to PM or AM/PM conversion) is defined as the derivative of the phase versus input power and is measured in degrees/dB. The AM/PM conversion, computed for that same amplifier, is shown in Figure 4.11. It is very small at low drive, increases gradually with increasing RF power, and peaks right around the point where the gain has dropped by 1 dB (1-dB compression). A further increase in drive results in a decrease of the AM/PM conversion, because the progressive saturation reduces the sensitivity to the input drive. This behavior is fairly common in power amplifiers, although other phenomena, such as a shift of bias due to rectification of the RF voltage or to voltage breakdown, substantially affect the phase response at high drive. The system in Figure 4.9 is simple, easy to implement, and gives important information that is also intuitively significant. Much more complex VNA systems have also been developed, however, that allow, for instance, measuring the amplitude and phase of the spectral components of the output signals. From these measurements, the system can reconstruct the waveforms at the terminals of an active device under test [18–21] and extract the parameters that define its nonlinear model [22]. 4.3.3  S-Parameters Versus Bias

Useful information on the large-signal behavior of an active device can be derived from measurements of S-parameters over a wide range of bias conditions. An

Figure 4.10  Example of amplitude and phase distortion in a high-gain 3W amplifier.

68

Device Characterization and Modeling

Figure 4.11  Example of AM/PM conversion in a high-gain amplifier.

array of bias points for an FET is shown schematically in Figure 4.12. When each set of S-parameters, measured over a wide frequency range, is applied to an equivalent circuit model (as described in Section 4.2), the change of the model parameters as a function of bias provides a measure of how the model elements vary as functions of an electrical variable, such as current or voltage. In effect, by varying the bias, this technique simulates the swing of a large RF signal. It allows, for instance, measuring in an FET the change of the RF transconductance as a function of drain current or the change of the associated capacitors as a function of voltage. The information can then be compiled into a large-signal model. Since most characteristics of an active device vary with temperature, and different bias points will generally correspond to different values of power dissipation, it is important that the S-parameters be measured in a pulsed mode in order to minimize the temperature rise caused by the DC bias [23]. The duty cycle should be low to allow cooling between measurements, and the pulse length should be short, with respect to the time constant of the device under test. Notice that the thermal constant in question is the fast one of the device die, as low as a few microseconds, and not the slower one of the die embedded into the surrounding package.

Figure 4.12  Bias points for S-parameters versus bias.

4.4  Large-Signal Models

69

4.4  Large-Signal Models 4.4.1  MESFET and HEMT Large-Signal Model

The most complete electrical characterization of the large-signal operation of an active device can be achieved by a large-signal model. This is an equivalent circuit quite similar in topology to its correspondent small-signal model, as described in Section 4.2. The only, but very important, difference is that some of the circuit elements are nonlinear; thus their values change as a function of some operating parameters. The challenge is, of course, to develop a model that, while including a minimum number of nonlinear elements, can be still successfully validated by comparison with measured data, such as tests of AM/AM, AM/PM, load pull or intermodulation. The validation tests are usually dictated by the specific application of the model. Many large-signal models for GaAs FETs, both MESFETs and HEMTs, have been developed through the years. They all share a similar topology that is prescribed by the physics of the device, but differ in the way the model parameters are extracted or in their dependence on various electrical variables. An early model, proposed by Willing, et al. [24], includes 6 nonlinear elements and was developed from measurements of S-parameters over a wide range of bias points, as described in Section 4.3.3. A simple model that has stood the test of time and is still used with many variations, is the Curtice-Ettenberg model [25]. The schematic of the intrinsic device, stripped of the external parasitic elements, is shown in Figure 4.13. It includes three nonlinear elements, with the intrinsic input and output voltages as independent variables. The drain-to-source current is defined by the following:

Ids = (A0 + A1 V1 + A2 V12 + A3 V13 )tanh[g Vout (t)]

(4.2)

where the A coefficients are computed from measured data in the saturation region and V1 is the following function of the input and output voltages:



(4.3) V1 = Vin (t − t )[1 + b (V0out − Vout(t))] where b represents the change of the pinch-off voltage vs. the drain-sourc

V0out is the output voltage at which the A coefficients were evaluate t is the internal transit-time delay and is related to the output volta t = A5 Vout (t)

Figure 4.13  FET large-signal model.

70

Device Characterization and Modeling

V1 = Vin (t − t )[1 + b (V0out − Vout(t))] where where b represents the change of the pinch-off voltagethe vs.change the drain-source voltage,voltage vs. the b represents of the pinch-off V 0out is the output voltage at which 0the A coefficients were evaluated, Vout is the output voltage at which the A coefficients we t is the internal transit-time delay and is related to the output voltage by: t is the internal transit-time delay and is related to the o t = A5 Vout (t) gVout(t) is the argument of the hyperbolic tangent function tanh; and g is the slope of the drain-current characteristic in the linear region. The hyperbolic function gives the drain current its characteristic familiar shape of a linear, and then saturated, region. This function was originally proposed by Taki [26] to describe the Ids characteristic of junction FETs. Much effort has been dedicated through the years to an accurate simulation of the drain-current Ids, not only because it is a major parameter in any large-signal model, but also because, in the early days of GaAs FETs, current saturation was considered as the main factor limiting the output power of the device. Indeed, in the first large-signal models, power saturation is modeled through the Ids response [24, 25, 27]. Surprisingly, subsequent measurements of voltage and current waveforms at microwave frequencies presented by Sechi, et al. [28], clearly showed that in GaAs MESFETs the voltage breakdown of the gate Shottky barrier, not the limitation on the drain current, is the main factor inducing power saturation. Thus, as discussed in Section 3.5, in connection with Figure 3.16, optimizing the gateto-drain breakdown is one of the main priorities in designing a power MESFET [29]. We must point out that the breakdown of the gate under large RF signals has implications, not only in the modeling of the output power performance, but also in a number of operating characteristics, such as AM and FM noise performance and pulse-mode operation. Indeed, since this effect was pointed out, it has been included in all subsequent nonlinear models. In particular, in the model we are describing, the second nonlinear element is in fact the Idg current generator that represents this voltage breakdown and is defined as

Idg =

Vdg (t) − VB R1

for Vdg > VB

(4.4)



Idg = 0 for Vdg < VB

(4.5)

where VB = VB0 + R2Ids R1 is the approximate breakdown resistance; R2 is the resistance relating breakdown to channel current; Finally, the third nonlinear element is the gate forward conduction, represented by a gate-to-source current:

Vin (t) − Vbi RF



Igs = 0 for Vin (t) < Vbi

Igs =

for Vin (t) > Vbi



(4.6) (4.7)

4.4  Large-Signal Models

71

where Vbi is the built-in potential, and RF is the forward-bias resistance. All the other elements of the circuit are derived from small-signal S-parameter measurements and are constant. Most of the later models, such as those in [30–34], more realistically feature nonlinear capacitors, which is clearly a requirement if the model has to predict intermodulation performance or in a large-signal analysis at frequencies where their reactance is non-negligible. Many different models have been proposed and are described in the literature. Some have very similar or even identical topologies to the one described earlier, and some differ on how the nonlinear elements are formulated and the parameters extracted. Specific details can be found in [35–38]. Although most of the models have been developed for implementation on more powerful, nonlinear analysis programs based on the harmonic balance technique, which is described in Section 8.7, some models for simpler microwave circuits have been developed for implementation on SPICE [39, 40]. Finally, we should caution that not all models are optimal for every mode of operation; some guidance for specific applications may be deduced from [4, 41]. 4.4.2  HBT Large-Signal Model

The classic Ebers-Moll and Gummel-Poon [42] large-signal models, which were developed for Si bipolar transistors, can still be used, with some modifications, for GaAs HBTs. Figure 4.14 shows a modified Gummel-Poon model, where the diode Dbe represents the forward-biased base-to-emitter junction, and the diode Dbc represents the reverse-biased collector-to-base junction. Capacitors Cp, Cci, and Cco are the capacitances associated with the junctions, and Rbb, Rbi, and Rci are the resistors associated with the base and the collector. In the Gummel-Poon model,

Figure 4.14  HBT large-signal model.

72



Device Characterization and Modeling

the output current generator Icc is controlled by the voltage across the base-emitter junction, Vp. The connections between the intrinsic device and the outer base, emitter and collector contacts (usually bond wires) are modeled by R-L circuits. The simplest and most direct way to derive nonlinear model parameters is to measure the S-parameters of the device over a wide range of frequencies and bias points, as described in Section 4.3.3. These measurements must be then supplemented by DC measurements and, possibly, by S-parameters cold-tests (see Section 4.2.2). The nonlinear model parameters may be described by polynomials or by functions derived from physical considerations, in which the independent variable is an electrical quantity, such as a voltage or a current. For instance, the depletion capacitance of a reverse-biased junction usually can be fitted with the classic equation: Cj (0) � Cj (Vj ) = � (4.8) Vj m 1− j

where Vj is the voltage applied to the junction; Cj(0) is the capacitance at 0 voltage; j is the built-in potential; and m is a factor reflecting the doping profile. Also, the Icc current can be described by an exponential function in the form:





� � bV Icc = Ico e A − 1

(4.9)

where V is the control voltage and b, A, and Ico are derived from the fitting of the test data. Alternatively, in accordance with the Gummel-Poon model, Icc may be expressed as � � Vbc Iss Vp eD −e F Icc = (4.10) C where Iss, C, D, and F are derived from the fitting of the test data; Vp is the voltage across the base-emitter junction; and Vbc is the voltage between base and collector. To model accurately an HBT, the standard Gummel-Poon model must be modified to include the transit time associated with the transport of carriers across the base and collector regions and the effect of self-heating. While the inclusion of a time delay in the collector current generator can be implemented through a delay option usually available in commercial circuit simulators, self-heating generally cannot be simply dialed in, and needs to be carefully modeled. The effect is present in Si bipolars as well, but it is less pronounced due to the relatively high thermal conductivity of silicon. In GaAs HBTs, self-heating affects the collector current in a major way. The effect is seen in the collector-emitter I-V characteristics, where the current shows a

4.4  Large-Signal Models

73

negative slope becoming progressively larger as the dissipated power increases. In fact, the current gain, after gradually decreasing with increased dissipated power, may suddenly collapse due to a strong nonuniform current distribution among the emitter fingers caused by thermal instability. Thus any reliable large-scale HBT model must include self-heating effects [43–47]. If the circuit simulator has no provision for temperature-dependent circuit parameters, the thermal effect can still be modeled by introducing an electrical equivalent model of the thermal structure. The first step is to develop a nonlinear model with temperature as an additional variable. Thus, for instance, a nonlinear element may be a function of two independent variables: an electrical parameter and the temperature. Then we introduce the electrical equivalent circuit of the thermal structure, as shown in Figure 4.15, for the simplest case of a single, thermal, time constant. The current generator, the capacitor, and the resistor simulate, respectively, the dissipated power, the thermal capacity, and the thermal resistance of the thermal system. The power dissipated in the device is the DC power minus the RF output power, and it is computed, at any instant of time, from the electrical model.

Pd = Vce Ice − Pout



(4.11)

In the thermal model of Figure 4.15, the current of the generator is set to be numerically equal to Pd. Also, the resistor, Rth, is set to be numerically equal to the thermal resistance between the device junction and the device mounting base. The capacitor, Cth, represents the thermal capacitance of the structure and is computed by

Cth =

a Rth

(4.12)

where a is the thermal time constant. Techniques for deriving the thermal resistance and the time constant are described in Chapter 13. Thus, when Pd varies with time, the voltage, DT, across the resistor, Rth, is numerically equal to the rise of the junction temperature over the mounting base. The junction temperature is then

T = To + DT

(4.13) where To is the temperature of the mounting base, and it is set as a constant.

Figure 4.15  Thermal equivalent circuit.

74

Device Characterization and Modeling

When the thermal equivalent circuit of Figure 4.15 is integrated with the nonlinear model of Figure 4.14, the circuit simulator computes Pd from the electrical model, derives the temperature T from the thermal model, and accordingly adjusts the nonlinear circuit elements, thereby accurately simulating the dynamic heating of the device. This same technique for thermal modeling can be applied to FETs as well. Although thermal modeling is less critical for FETs than it is for HBTs, it can still be of importance in high-power applications.

References   [1] Curtice, W. R., and R. L. Camisa, “Self Consistent GaAs FET Models for Amplifier Design and Device Diagnostics,” IEEE Trans. on Microwave Theory and Techniques, Vol. MTT32, No. 12, December 1984, pp. 1573–1578.   [2] Dambrine, G.; et al., “A New Method for Determining the FET Small-Signal Equivalent Circuit,” IEEE Trans. on Microwave Theory and Techniques, Vol. 36, No. 7, July 1988, pp. 1151–1159.   [3] Golio, J. M., Microwave MESFETs and HEMTs, Norwood, MA: Artech House, 1991.   [4] Grebennikov, A., RF and Microwave Power Amplifier Design, New York: McGraw Hill, 2005, pp. 77–108.   [5] Costa, D., W. U. Liu, and J. S. Harris, “Direct Extraction of the AIGaAs/GaAs Heterojunction Bipolar Transistor Small-Signal Equivalent Circuit,” IEEE Trans. on Electronic Devices, Vol. ED-38, September 1991, pp. 2018–2024.   [6] Schaper, U., and B. Holzapfl, “Analytical Parameter Extraction of the HBT Equivalent Circuit with T-Like Topology from Measured S-Parameters,” IEEE Trans. on Microwave Theory and Techniques, Vol. MPT-43, March 1995, pp. 493–498.   [7] Samelis, A., and D. Pavlidis, “DC to High-Frequency HBT-Model Parameter Evaluation Using Impedance Block Conditioned Optimization,” IEEE Trans. on Microwave Theory and Techniques, Vol. MTT-45, June 1997, pp. 886–897.   [8] Ghaddab, H., F. M. Ghannouchi, and F. Bouallegue, “Small-Signal Modeling of HBTs Using a Hybrid Optimization/Statistical Technique,” IEEE Trans. on Microwave Theory and Techniques, Vol. MTT-46, March 1998, pp. 292–298.   [9] Li, B., F. S. Prasad, L.-W. Yang, and S.C. Wang, “A Semianalytical Parameter- Extraction Procedure for HBT Equivalent Circuit,” IEEE Trans. on Microwave Theory and Techniques, Vol. MTT-46, October 1998, pp. 1427–1435. [10] Yang, T. R., et al., “SiGe HBT’s Small-Signal Pi Modeling,” IEEE Trans. on Microwave Theory and Techniques, Vol. 55, July 2007, pp. 1417–1424. [11] Sechi, F. N., et al., “A Computer-Controlled Microwave Tuner for Automated Load Pull,” RCA Review, Vol. 44, December 1983, pp. 566–583. [12] Hart, P., et al., “Improving Loadpull Measurement Time by Intelligent Measurement Interpolation and Surface Modelling Techniques,” 67th ARFTG, San Francisco, June 16, 2006, pp. 69–72. [13] Bava, G. P., U. Pisani, and V. Pozzolo, “Active Load Technique for Load-Pull Characterization at Microwave Frequencies,” Electronic Letters, Vol. 18, No. 4, February 18, 1982, pp. 178–180. [14] Williams, T., J. Benedikt, and P. J. Tasker, “Experimental Evaluation of an Active Envelope Load Pull Architecture for High Speed Device Characterization,” IEEE MTT-S Int. Microwave Symp. Digest, Long Beach, CA, June 2005, p. TH1G. [15] D. Barataud, et al., “Measurement and Control of Current/Voltage Waveforms of Microwave Transistors Using a Harmonic Load-Pull System for the Optimum Design of High

4.4  Large-Signal Models

[16] [17]

[18]

[19]

[20]

[21] [22]

[23]

[24]

[25]

[26] [27] [28] [29] [30]

[31] [32]

[33]

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Efficiency Power Amplifiers,” IEEE Transactions on Instrumentation and Measurement, Vol. 48, No. 4, August 1999, pp. 835–842. Stancliff, R. B., and D. P. Poulin, “Harmonic Load-Pull,” MTT-S Int. Microwave Symp. Digest, 1979, pp. 185–187. Blanchet, F., et al., “The Locus of Points of Constant Output VSWR Around the Optimal Impedance Evaluation of Power Transistors’ Robustness,” 67th ARFTG, San Francisco, June 16, 2006, pp. 129–132. Verspecht, J., et al., “Accurate on Wafer Measurement of Phase and Amplitude of the Spectral Components of Incident and Scattered Voltage Waves at the Signal Ports of a Nonlinear Microwave Device,” IEEE Microwave Theory and Techniques Symp., Orlando, Florida, May, 1995, pp. 1029–1032. Barataud, D., et al., “Measurements of Time-DomainVoltage/Current Waveforms at RF and Microwave Frequencies Based on the Use of a Vector Network Analyzer for the Characterization of Nonlinear Devices’ Application to High-Efficiency Power Amplifiers and Frequency-Multipliers Optimization,” IEEE Trans. on Instrumentation and Measurement, Vol. 47, No. 5, October 1998. pp. 1259–1264. Verspecht, J., and D. Schreurs, “Measuring Transistor Dynamic Loadlines and Breakdown Currents Under Large-Signal High-Frequency Operating Conditions,” 1998 IEEE MTT-S Int. Microwave Symp. Digest, Vol. 3, June 1998, pp. 1495–1498. Rytting, D., “Network Analyzers from Small Signal to Large Signal Measurements,” 67th ARFTG Conf. Digest, San Francisco, June 16, 2006, pp. 11–49. Citronali, A., C. Accillaro, and G. Manes, “Mildly Nonquasi-Static Two-Port Device Model Extraction by Integrating Linearized Large-Signal Vector Measurements,” IEEE Trans. on Microwave Theory and Techniques, Vol. 55, November 2007, pp. 2277–2289. Teyssier, J. P., et al., “A Pulsed S-Parameters Measurement Setup for the Nonlinear Characterization of FETs and Bipolar Power Transistor,” 23rd EuMC 93 Proc., Madrid, September, 1993, pp. 489–493. Willing, H., et al., “A Technique for Predicting Large-Signal Performance of a GaAs MESFET,” IEEE Trans. on Microwave Theory and Techniques, Vol. MTT-26, 1978, pp. 1017–1023. Curtice, W. R., and M. Ettenberg, “A Nonlinear GaAs FET Model for Use in the Design of Output Circuits for Power Amplifiers,” IEEE Trans. on Microwave Theory and Techniques, Vol. MTT-33, 1985, pp. 1383–1394. Taki, T., “Approximation of Junction Field-Effect Transistor Characteristics by a Hyperbolic Function,” IEEE J. of Solid-State Circuits, Vol. SC-13, October 1978, pp. 724–726. Kacprzak, T., and A. Materka, “Compact dc Model of GaAs FET’s for Large-Signal Computer Calculation,” IEEE J. of Solid-State Circuits, Vol SC-18, April 1983, pp. 211–213. Sechi, F., H. Huang, and B. Perlman, “Waveforms and Saturation in Power MESFETs,” Proc. of 8th European Microwave Conf., Paris, 1978, pp. 473–477. Wemple, S. H., et al., “Control of Gate-Drain Avalanche in GaAs MESFETs,” IEEE Trans. on Electronic Devices, Vol. 27, No. 6, June 1980, pp. 1013–1018. Materka, A., and T. Kacprzak, “Computer Calculation of Large-Signal GaAs FET Amplifier Characteristics,” IEEE Trans. on Microwave Theory and Techniques, Vol. MTT-33, February 1985, pp. 129–135. Statz, H., et al., “GaAs FET Device and Circuit Simulation in SPICE,” IEEE Trans. on Electronic Devices, Vol. ED-34, February 1987, pp. 160–168. Angelov, I., H. Zirath, and N. Rorsman, “A New Empirical Nonlinear Model for HEMT and MESFET Devices,” IEEE Trans. on Microwave Theory and Techniques, Vol. MTT-40, December 1992, pp. 2258–2266. Staudinger, J., et al., “Considerations for Improving the Accuracy of Large-Signal GaAs MESFET Models to Predict Power Amplifier Circuit Performance,” IEEE J. of Solid-State Circuits, Vol. 29, No. 3, March 1994, pp. 366–373.

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Device Characterization and Modeling [34] Collantes, J. M., “A New Large-Signal Model Based on Pulse Measurement Techniques for RF Power MOSFET,” 1995 IEEE TTTS-S Digest, 1995, pp. 1653–1556. [35] Dortu, J. M., et al., “Accurate Large-Signal GaAs MESFET and HEMT Modeling for Power MMIC Amplifier Design,” Int. J. of Microwave and Millimeter-Wave ComputerAided Eng., Vol. 5, September 1995, pp. 195–208. [36] Schreurs, D., et al., “Straightforward and Accurate Nonlinear Device Model ParameterEstimation Method Based on Vectorial Large-Signal Measurements,” IEEE Trans. on Microwave Theory and Techniques, Vol. 50, No. 10, 2002, pp. 2315–2319. [37] Schwierz, F., and J. J. Liou, Modern Microwave Transistors: Theory, Design, and Performance, John Wiley & Sons, 2003. [38] Raffo, A., et al., “Electron Device Model Parameter Identification Through Large-SignalPredictive Small-Signal-Based Error Function,” IEEE Trans. on Microwave Theory and Techniques, Vol. 55, October 2007, pp. 1997–2005. [39] Golio, J. M., et al., “A Large-Dignal GaAs MESFET Model Implemented on SPICE,” IEEE Circuits and Devices Mag., September 1985, pp. 21–30. [40] McCamant, A. J., G. D, McCormack, and D. H. Smith, “An Improved GaAs MESFET Model for SPICE,” IEEE Trans. on Microwave Theory and Techniques, Vol. MTT-38, June 1990, pp. 822–824. [41] Miller,M., et al., “Choosing an Optimum Large Signal Model for GaAs MESFETs and HEMTs,” 1990 IEEE MTT-S Int. Microwave. Symp. Digest, Vol. 3, 1990, pp. 1275– 1282. [42] Gummel, H. K., and H. C. Poon, “An Integral Charge Control Model of Bipolar Transistors,” Bell Systems Technical Journal, No. 49, 1970. [43] Grossman, P., J. Choma, Jr., “Large Signal Modeling of HBTs Including Self-Heating and Transit Time Effects,” IEEE Trans. on Microwave Theory and Techniques, March 1992, pp. 449–464. [44] Baureis, P., and D. Seitzer, “Parameter Extraction for HBTs Temperature Dependent LargeSignal-Equivalent Circuit Model,” 1993 IEEE GaAs IC Symp. Tech. Digest, 1993, pp. 263–266. [45] Lu, K., P. A. Perry, and T. J. Brazil, “A Large-Signal AlGaAs/GaAs HBT Model Including Self-Heating Effects with Corresponding Parameter-Extraction Procedure,” IEEE Trans. on Microwave Theory and Techniques, Vol. 43, July 1995, pp. 1433–1445. [46] Camnitz, L. H., et al., “An Accurate Large-Signal High Frequency Model for GaAs HBTs,” 1996 IEEE GaAs Symp., 1996, pp. 303–306. [47] Teeter, D. A., and W. R. Curtice, “Comparison of Pi and Tee HBT Circuit Topologies and Their Relationship to Large-Signal Modeling,” 1997 IEEE MTT-S Digest, pp. 375–378.

Chapter 5

Phase Noise

5.1  Introduction Traditionally, microwave amplifiers were classified into two broad groups: low noise and high power. An amplifier of the first type was typically operated in the linear region, and its noise properties were summed up by the noise figure (NF), a measure of the degradation in signal-to-noise ratio contributed by the amplifier. For the second group, any information on noise was considered nonessential, because of the negligible degradation in signal-to-noise ratio generally contributed by a power amplifier, due to its high signal level, even at the input. While this argument is fairly clear when we talk about the amplification of input noise within the amplifier’s bandwidth, it becomes questionable when the output noise is produced by an interaction of the signal with strong out-of-band noise (such as 1/f), generated either inside or outside the amplifier. The result of such mixing, which is due to the amplifier’s nonlinear behavior, may be quite significant. It modulates both phase and amplitude, but the phase variation is especially bothersome in many important applications, and it is more difficult to overcome, so most of the attention has been focused on this. Of course, phase noise was always of interest in oscillators, and considerable work on noise in nonlinear amplifiers came from modeling oscillators as amplifiers with a feedback path, but it was only in the late 1990s that the topic of noise (and especially phase noise) in power amplifiers developed a life of its own. As we mentioned in Chapter 2, this is a typical situation where system designers are demanding attention on an issue that is increasingly important in a number of major applications, ranging from Doppler radars to data-communication links, multichannel receivers, and test sets: in other words, any application in which the phase of the signal carries information. In line with the subject of this book, we will not discuss noise in general, nor low-noise amplifiers. Many good books are already available on these topics [1–5]. We will limit ourselves to the discussion of phase noise in power amplifiers, a subject that is presently receiving considerable attention, but, to our knowledge, has not yet been reviewed in technical books. The noise at the output of a nonlinear amplifier is the result of three mechanisms: amplification of the input noise, mixing of the input noise with the signal due to nonlinear elements in the amplifier, and generation of the noise inside the amplifier itself [6]. This last contribution is the most difficult to evaluate, not only because there is limited information on the phase noise of the single devices, but also because the overall result depends on the particular position a device will take 77

78

Phase Noise

in the amplifier’s architecture, and, therefore, will vary significantly from one case to another. In this chapter, we will first discuss the noise characteristics of the solid-state devices most likely to be used in power amplifiers, and we will then try to develop an understanding of their contribution to the amplifiers’ noise. Given the applications’ emphasis on phase noise, we will concentrate on this topic, but most of what we say refers to amplitude noise as well.

5.2  Noise in Semiconductors Every electronic component contributes noise. Power supplies and conditioners, especially the switching type, are certainly a significant source, and any resistor generates thermal noise. The active devices, however, are likely to be the main contributor to the noise of a power amplifier. Beside the usual thermal noise, which is present whenever there is an electrical conduction, the most important types of noise in active devices are shot, diffusion, avalanche, generation-recombination (G-R), and 1/f (also called flicker). Less frequent, at least in high-quality microwave power devices, is the burst noise, which is typical of a single trap activity when the density of free carriers is especially low. In bipolar transistors, it is often associated with damaged or defective devices [7]. We will start this brief review with thermal noise, the most common and wellknown noise variety. Consider a resistor, R, at an absolute temperature, T. The free electrons [8] in the resistor are in random motion, and, if they are in thermal equilibrium, their kinetic energy is proportional to KT, where K is the Boltzmann constant. Their displacements are equivalent to microscopic currents and generate a fluctuating voltage at the resistor’s terminals, with zero average value, but nonzero power. If we transform the time variation of such fluctuation in a frequency spectrum, we find that, within practical limits (namely excluding extremely low temperatures or high frequencies), such a spectrum is flat or, as we say, white. Within a given frequency band B, the noisy resistor can be modeled with a noise source made up of a noiseless resistor, R, and a voltage generator, Vn, given by

V2n = 4KTRB



(5.1)

If such a source is connected to a matched load, the power P delivered to the load over the frequency band B is given by:

P = KTB

(5.2)

Systems with narrower bandwidths collect less thermal noise, and cooler resistors produce less noise, but we should be careful not to extrapolate the meaning of the expression beyond its limits of validity. An infinite bandwidth does not lead to infinite noise power (the so-called ultraviolet catastrophe), because this formula for the power is not valid at very high frequencies. But within usual conditions, these expressions apply to any physical conductor, provided the free electron gas is in thermal equilibrium. If the electrons (for any reason, but most typically under

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79

the effect of a high electric field) gain more energy than they are able to dissipate through collisions with the lattice, then they are not in thermal equilibrium any more, and they are called hot. They still produce noise, but their energy is not related to the temperature T of the environment, and the above expressions are not valid. In other words, the noise is not thermal anymore; it becomes one of the other varieties we listed above. The shot noise is generally associated with electrons either ejected at random from a hot cathode (in other words, “shot” from the cathode) or randomly gaining enough energy to cross a potential barrier and become available for conduction. That’s where the name originally comes from, but in fact, in any electric current, whether or not a barrier is involved, there is implicit a random process due to the quantized nature of the electric charge. If, in an ideal experiment, we could count charges crossing a given position during equal intervals of time, we would see the numbers fluctuate at random, while, of course, the macroscopic current is defined as an average. In other words, the quantized nature of carriers produces a fluctuation around such average current, I, and again, if we transform the time variation into a frequency spectrum, we obtain a constant spectral distribution. In this case, the noise source is more often represented as a current generator In, and its value within a frequency band, B, is given by

In2 = 2qBI

(5.3)

where q is the electron charge. This result is based on Boltzmann statistics, and it is not affected by the details of the process producing the current. Under thermal equilibrium, we can use Einstein’s relation linking the mobility, m, to the diffusion coefficient, D:

D/m = KT/q



(5.4)

and, if we express the current as diffusion of charges, we can transform (5.3) into the expression:

I2n = 4KTB/R



(5.5)

which we can easily recognize as equivalent to the thermal-noise source (5.1). In other words, as was relatively recently recognized [9], under conditions of thermal equilibrium, shot and thermal noise are just two different expressions of the same physical phenomenon. While (5.1) is valid only in thermal equilibrium, however, the validity of (5.3) extends to more energetic electrons as well. Shot noise is independent of frequency (in other words, white) only in the low and intermediate ranges; at very high frequency it shows a tendency to increase. It is generally the dominant factor in the noise figure of bipolar devices. In a similar way, diffusion noise can be also viewed as an extrapolation of the thermal noise to nonequilibrium situations, such as the velocity saturation regime that characterizes the channel of an FET. Under low electric fields, in a steady-state condition, electrons acquire as much energy from the field as they dissipate through collisions with the lattice. The kinetic energy of the charges is proportional to the

80

Phase Noise

absolute temperature, T, of both the electrons and the environment, leading to (5.4). Under the effect of a stronger electric field, however, the electrons acquire more energy than they are able to transfer to the lattice through collisions. This is often described by assigning to them an effective temperature higher than the lattice’s (the electrons are then called hot). Their energy increases until it reaches the threshold for new dissipation mechanisms, such as collisions with optical phonons [10] or transfer to other conduction-band minima, as we discussed in Section 3.3 for the III-V compounds. These new processes lead to the drift velocity saturating or even decreasing, as we have seen in Figure 3.6. Under these conditions, the noise corresponding to the random fluctuations of the electric current is not proportional to the absolute temperature anymore, or at least not to the lattice temperature, as in (5.5). But it was proposed by van der Ziel [11] that the correspondent expression in terms of diffusion constant should still remain valid, even at high electric fields. In other words, if we consider a small slice, d x, of a conducting channel with cross-section A, and express the square of the noise current (5.5), using Einstein’s relationship, as

I2n = 4q2 DnA/δ x



(5.6)

this diffusion noise is found to describe in a satisfactory way even the noise in a saturated velocity regime, in particular in the channel of an FET [12]. Thermal, shot, and diffusion noise can be thus seen as fundamentally related, or as different representations of the statistical randomness in the motion of the electric charges. Apart from extreme situations (in terms of temperature and frequency), all three types have a constant frequency spectrum; they are, namely, white noise. When the electric field is increased still further, beyond saturation, some electrons may acquire enough energy to free an additional electron from an atom. In a semiconductor, this creates an electron-hole pair. We have already met this phenomenon at the end of Section 3.3 as avalanche breakdown. It is normally present in the gate junction of FETs under large-signal conditions. It does not lead to failure if the current is limited, but, if it is not controlled, the phenomenon is catastrophic. In the presence of avalanche multiplication, and much before an actual burnout takes place, the noise will start to increase, signaling local and sporadic pair formation. Avalanche noise is generally avoided by using devices with a higher breakdown or by limiting the operating voltages; however, because of its broadband white spectrum, this process is typically used to advantage in standardized noise sources. So far, we have seen basically white sources of noise. The first three are related to randomness in the motion of the charges and the last one to random charge generation, but with a broad spectrum of energy. We come now to a type of noise that is also caused by a random variation of the number of available charges, but with relatively well-defined energy spectra. This is the generation-recombination (G-R) noise, due to the trapping and releasing of charges between the conduction band and specific energy levels created by impurities or other defects. The fluctuations in the number of free electrons cause the conductance, and therefore the current, to fluctuate in turn. In the simple case of a single or, at least, a dominant trap, if we indicate with t a relaxation time characteristic of the trap (usually in the range of 10-6–10-3 s) the spectral distribution of the G-R noise is found to be proportional

5.3  Noise in Active Devices

81

to t/{1+(2pf )2t 2} [13], showing a low-frequency plateau and a corner frequency, 1/t, beyond which the noise falls off as 1/f 2. This is called a Lorentzian spectrum. When many traps are involved, the physical analysis becomes increasingly complex. If the traps do not interact with each other (neither directly nor via the conduction band), however, the resulting spectrum approaches 1/f in the whole frequency region from 1/t1 (t1 being the characteristic time of the slowest trap) to 1/tn (corresponding to the fastest trap) [14]. Three or four traps may be all that is needed to cover a frequency range from 10 to 105 Hz. It was also pointed out [15] that, since the time constant of a trap is a function of temperature, in a measurement on an actual transistor a single trap may contribute a whole range of values for t, due to the temperature variation within the active device. Therefore, the trapping and releasing of charges can be responsible, under different conditions, for both Lorentzian and 1/f types of spectra. Generally speaking, the 1/f (also called flicker) noise can have a variety of physical origins. Any conductivity fluctuation with a noise spectrum inversely proportional to the frequency, f, goes under this name. This type of noise, upconverted by any nonlinearity present in the system, is the main contributor to phase noise near the carrier of either power amplifiers or oscillators, and, therefore, is of especially high interest to us. This noise is found in any electronic device, including a simple homogeneous piece of semiconductor or metal. When a constant voltage, V, is applied to a resistor of resistance, R, that fluctuates as 1/f, the current, I, will fluctuate in a similar way. If we are dealing with a piece of bulk material with N independent electric carriers, we might expect the noise spectrum, SI(f ), of the electric current to be proportional to N. Since the current is also proportional to N, Hooge [16] proposed the following empirical formula:

SI (f )/I2 = SR (f )/R = aH /Nf

(5.7)

where aH is a constant called the Hooge parameter, typically in the range of 10-3– 10-5. This formula does not say anything about the physical origins of the noise, which may be related either to mobility fluctuations (due to scattering of electrons by all types of lattice imperfections and vibrations) or to carrier fluctuations (mostly due to trapping and releasing of charges) [17].

5.3  Noise in Active Devices Bulk material is very seldom the main source of flicker noise in microwave devices. Most often, such noise is dominated by the effect of either surfaces or interfaces between different regions. Within a depletion region, the Fermi level is further away from the conduction band, thereby uncovering traps that, in the bulk material, are normally filled. Therefore, these regions are especially prone to G-R processes. As carriers are released or captured by the traps, their population fluctuates, and so does the depth of the depletion region. This process will often dominate over all other different mechanisms taking place in the bulk of the device. In a modern Si or SiGe bipolar transistor, most of the 1/f noise originates in the two junctions separating the emitter from the base and the base from the collector.

82

Phase Noise

Because of the geometrical configuration of the device, surface depletion regions are much less significant. When the junction is modulated by noise, the current crossing the barrier is modulated as well. Both emitter-to-base and base-to-collector junctions generate low-frequency noise. In most cases, however, the noise on the base current, IB, dominates and is transferred directly onto the collector current, IC, so that, if we indicate with SIB and SIC the respective noise spectra, in the lowfrequency region we will typically have [18]

SIB ∼ = SIC

(5.8)



Even though the application of (5.7) to a thin depletion region, rather than a homogenous sample, is not straightforward, we can still use the same general physical argument and observe that we may expect both the population of noise-generating centers and the electric current to be proportional to the surface of the junction. The ratio of the noise current spectrum to the square of the current may be then reasonably expected to be inversely proportional to such a surface. In particular, for the emitter-to-base interface, indicating with A the surface of the emitter and with IB the base dc current, we may expect, for the 1/f base current noise spectrum, an expression of the type:

SIB (f ) = KI2B /Af

(5.9)

where K is an empirical proportionality coefficient, with the dimensions of a surface. If we wish to express SIC in terms of the IC current, we can use the relationship IC  @ bIB and use (5.8) to write

SIC ∼ = KI2C /b 2 Af



(5.10)

These expressions for the noise current spectra adequately fit the experimental results for many Si and SiGe bipolars [19, 20], confirming that the emitter junction is the main source of 1/f noise and indicating a uniform distribution of trapping centers in the junction. In some III-V heterojunction bipolars, where, depending on the specific geometry, the effect of surface regions may not be completely negligible, there is often a need for a more general expression:

SIB (f ) = KF IAF B /f

(5.11)

where both KF and AF are empirical constants. This is the expression used for the 1/f noise in the SPICE model. In addition, in the III-V compounds the presence of specific and dominant trapping centers is more common than in Si or SiGe, so that it is more common to observe G-R bumps superimposed on 1/f spectra. As an example, Figure 5.1 shows two typical base current noise spectra of bipolar devices. The upper curve (adapted from [21] and [22]) was measured on an AlGaAs/GaAs HBT with an emitter area of 40m2, a collector current of 1 mA and a base current of 48 mA. Superimposed on a general 1/f trend, we find a characteristic bump (labeled G-R) in the vicinity of 105 Hz. This indicates the presence of a trap with a

5.3  Noise in Active Devices

83

Figure 5.1  Low-frequency base current noise spectra of two heterojunction bipolar transistors with similar base currents and collector current densities: (a) AlGaAs/GaAs and (b) SiGe.

time constant on the order of 10–5 seconds. The lower curve is for a SiGe Bipolar, with an emitter area of 20m2 and a similar current density of 2 kA/cm2. This curve gives no indication of any specific trap. This measurement is taken from the work by Bary, et al. [20], which includes data for otherwise identical devices, in a range of SiGe compositions. It is interesting to note that, currently, SiGe bipolars have a noise performance remarkably similar to pure Si, a testimony to the maturity of this technology. Out of the group, we have chosen the device with 10% Ge because its base current is the closest to the GaAs example. In the upper plot, tree regions are clearly displayed: the characteristic lowfrequency 1/f noise, which is always present, a Lorentzian-shaped bulge typical of a G-R noise source, and a flat white-noise plateau. In this particular case, the trap responsible for the G-R noise has been identified as the DX center, which is characteristic of AlGaAs, especially at relatively high Al concentrations. In fact, by decreasing the Al content, the strength of the bump was found to decrease. Thermal noise in the resistive portions of the device, and shot noise in the junctions, both contribute, in principle, to the high-frequency plateau. But the second is the dominant effect; in practice, high-frequency noise in the base current is often very close to 2qIB and, in the collector current, to 2qIC. This is typical of high-quality bipolars, with negligible recombination currents and surface effects. The lower plot is very similar, except there is no evidence of any specific trap. Again, the high-frequency portion of the curve is virtually identical with 2qIB. Both plots, apart from the G-R feature, can be described as

SIB (f ) = KI2B /Af + 2qIB



(5.12)

84

Phase Noise

where K and A have the same meaning as in (5.9). Since the base current is very similar and the emitter areas differ only by a factor of two, it is clear that most of the difference in the 1/f portion of the spectrum is due to a different value of K, which has an order of magnitude of 10-7m2 for the GaAs HBT, but only of 10-9m2 for the SiGe device. This parameter is an indicator of trap density in the emitter junction, and it is not surprising that it is found to be much lower in a more mature technology. The different K values translate into similarly different corner frequencies, fc, defined as the frequencies where the white noise equals the 1/f noise. This is often used as a figure of merit for a given technology, but one should keep in mind that it represents only an order-of-magnitude indication, since it varies with device geometry and bias. Even for the same transistor, we can clearly see from (5.12) that it changes with the base current. Values of fc in the range of 1–10 kHz are fairly typical for Si or SiGe bipolars, however, and so are values between 100 kHz and 1 MHz for GaAs HBTs. In agreement with the physical picture of two dominant noise sources identified with the source-to-base and base-to-collector junctions, the simple noise model sketched within the dashed box of Figure 5.2 is often sufficient to describe the noise behavior of a bipolar at low frequency [23]. At higher frequencies, the voltage sources associated with thermal noise in the resistors have to be taken into account. A similar noise model is included in most CAD tools, such as SPICE and Microwave Office [24]. We have seen that the low-frequency noise of a bipolar transistor is dominated by the emitter-to-base junction, which in turn modulates the collector current. Therefore, it is not surprising that the phase noise of a common emitter bipolar amplifier can be reduced by a stabilizing feedback inserted in the emitter-collector path. This can be implemented by a simple, unbypassed resistor in the emitter leg or by a more sophisticated servo-system [25]. We will see later that a similar approach applied to FETs meets with only limited success. We have had the opportunity to mention several times that bipolar transistors enjoy a considerable advantage over FETs in terms of 1/f noise. In fact, corner frequencies in excess of 10 MHz are fairly typical for both MESFETs and HEMTs (including PHEMTs). This is understandable, due to the different geometry of the two types of devices. In both bipolars and FETs, the low-frequency noise is mostly

Figure 5.2  Noise model for a bipolar transistor. The core elements included in the dashed box are often sufficient to simulate the 1/f noise. The two noise sources can be derived, respectively, from inb2(f ) = KIB2 /Af + 2qIB and inc2(f ) = KIC2 /b 2Af + 2qIC.

5.3  Noise in Active Devices

85

generated in the depletion regions associated with either barriers or surfaces. In bipolars, however, the main current runs across the barriers, while surfaces are often negligible. Thus, we expect the current noise fluctuation to be proportional to the surface of the junction being crossed by the main current. On the other hand, in an FET, the current runs along the surfaces that are the main sources of noise. Thus, the modulation of the current extends to the whole channel surface, WLt (W and Lt representing, respectively, the channel’s width and its total length, including ungated surfaces). In fact, it possibly extends to twice as much, since the backside barrier and upper surface are both noise sources, though not necessarily equally effective. This is a much wider area than the device cross section, typically 30–100 times wider in a MESFET and even more in a HEMT. Thus, we may expect a similarly stronger noise. Based on these geometrical considerations, we do not expect the low-frequency noise in FETs to be inversely proportional to the current cross-section, as in (5.9) for bipolars. Applying the same physical reasoning to the FET situation, however, since both the device current and the population of noise-generating centers is expected to be proportional to the width, W, of the device, we still expect the 1/f noise to vary as 1/W. This is, in fact, confirmed by experimental data [26]. There is also general agreement that the noise decreases with the gate length and increases with the drain current [27], but there is no general agreement on a specific formula. The actual dependence on frequency often deviates from a clean 1/f plot, due to the presence of one or more bulges characteristic of a G-R noise source, as exemplified in Figure 5.3 by typical noise measurements for MESFET and PHEMPT devices. These

Figure 5.3  Low frequency equivalent input noise voltage spectra for a MESFET and a PHEMT.

86

Phase Noise

were adapted from [15, 28]. Very similar data were reported in [29]. The MESFET curve extends far enough to show a corner frequency of approximately 40 MHz, which is within the range of 10–100 MHz typical of FET devices. These results can be summarized by a general expression that combines 1/f and G-R noise:

SV (f ) = C + AIαd /Wf + Bτ /{1 + (2π f )2 τ 2 }

(5.13)

where A, B, C, and a are empirical parameters; Id is the drain dc current; and t is the time constant characteristic of the trap involved in the G-R center. In other cases, where more than one bump is present, the last term would be replaced by a sum of similar expressions, each referring to a different trap [30], namely,

SV (f ) = C + AIαd /Wf + ∑i Bi τi /{1 + (2π f )2 τi2 } where Bi and ti are characteristic of each trap, and the summation runs over the whole set of traps. In connection with Figure 5.3, we may notice that, while in bipolars the lowfrequency noise is generally presented in terms of the base or collector current spectra, for FETs it is customary to present the data in terms of an equivalent input noise voltage. In fact, for a long time, the modulation of the gate depletion by trapping and releasing of charges was considered as the only source of 1/f noise, and was seen as a noise voltage applied on the gate. Of course, this modulation is transferred on the drain current and generally measured as a variation of such current, but the results were still traditionally expressed as input voltages. At low frequency, the drain current noise is simply proportional to the voltage fluctuation, namely SI(f) = gm2 SV(f ), where gm is the device transconductance. Through the years, however, the view of a single voltage noise source, located on the gate and modulating the current via the gate-to-source capacitance, has been found inadequate to explain experimental data. In particular, the microwave phase noise of both MESFETs and HEMTs was found to be poorly correlated to the lowfrequency baseband noise of their drain currents [31, 32]. Therefore, it is not surprising that, by applying a stabilizing feedback to the drain current, only a limited reduction could be obtained in the amplifier noise [33]. Other major inconsistencies were observed when analyzing the noise upconversion in FET oscillators [34]. Also, Llopis, et al., [28] have shown that the one-source model was unable to explain the experimental variation of the 1/f noise with input power. These and other similar effects clearly suggest the need for a more complex model. On the other hand, a model which concentrates all the noise on the gate depletion also contradicts our physical understanding that both surfaces and backside barrier also play an important role in the 1/f noise of FETs. This was clearly established by many experiments showing the decrease of 1/f noise when a buffer layer was introduced in the back or surfaces were controlled by different means, such as passivation. A modulation of either the back barrier or the surface depletion clearly affects many of the FET circuit parameters, notably the input and output resistances [35].

5.4  Phase Noise

87

While there is a general agreement that at least two independent noise sources are needed to explain the experimental data, the specific location of such sources is still debated. The popular Chalmers large-signal model [36] extends to low frequencies the same equivalent circuit structure used for high-frequency noise, with the noise sources modified to include additional 1/f and G-R components. This approach does not fit some experimental results [26, 28], however, and a different circuit, reproduced in Figure 5.4, was proposed by Llopis, et al., [28]. In addition to the traditional gate voltage generator, SV, which modulates the drain current, a 1/f current source, SI, modulates the input resistor. This noise source does not affect significantly the drain current, but it introduces a fluctuation in the input reactance and the phase of the device. The two sources are not correlated. A similar fluctuation of the input resistance has been proposed by Margraf and Boeck [26] to explain the low-frequency noise characteristics of resistive FET mixers. As compared to low-frequency noise, which is still the subject of considerable debate, the high-frequency noise of FETs has been fairly well understood for some time. Within practical limits, the high-frequency noise is white, or independent of frequency, and is generally characterized by the noise figure. One of the most popular small-signal models was proposed by Pospieszalski [37]. This was extended to large signals by the Chalmers University group [36]; however, the field of large-signal modeling, for both bipolars and FETs, is still the subject of much research and debate [38]. Another very important (and, to some extent, related) subject that has only recently received attention is the effect of temperature and thermal nonuniformities on noise [39, 40]. This is especially important at high powers and in compound semiconductors, which typically have much poorer thermal conductivity than silicon. Indeed, the junction’s temperature may be vastly different from the room’s or even the carrier’s temperatures, and the effects of the thermal variation within the device are not easy to separate from other large-signal and high-bias effects.

5.4  Phase Noise A carrier signal with low amplitude (AM) and phase (PM) modulations can be represented by a sinusoid, with amplitude and phase varying slowly and randomly with time:

Figure 5.4  Low-frequency noise model for FETs, including a modulation of the input resistance.

88



Phase Noise

V(t) = {V0 + ε (t)}cos{2π f0 t + ϕ (t)}

(5.14)

where e and j represent, respectively, the amplitude and phase fluctuations. This representation in the time domain provides an intuitive feeling for the two types of noise. Both amplitude and phase noise, however, are most often expressed and measured in the frequency domain rather than the time one. In general terms, the relationship between the two representations is still a subject of research [41], and we will not enter into this subject here. We will provide first an elementary example, and then we will try to extrapolate to more general situations. Let us then assume that we can neglect the amplitude variation, and let us consider a small sinusoidal phase variation with frequency f:

j (t) = Φ sin(2p ft)

(5.15)

If we introduce (5.15) in (5.14) and expand the expression using trigonometrical formulas, assuming the phase variation to be small (F ‹‹ 1), so that the sine can be replaced by the angle and the cosine by 1, we obtain

V(t) » V0 {cos(2p f0 t) - Φsin(2πf0 t)sin(2p ft) } = = V0 {cos(2p f0 t) - Φ/ 2[cos2p (f0 - f )t - cos 2p (f0 - f )t]}



(5.16)

From (5.16), we can see that a small sinusoidal phase variation adds two symmetrical sidebands to the basic signal. If we indicate with dj(f ) the rms of the phase variation (dj2 = F2/2), we can write for the power contained in each of these sidebands: Pj = V02 dj2 /4 R, where R is the load resistance, while the carrier power is V02/2R. The phase-noise spectrum Sj (f ) is defined as the ratio of the phase-noise power per unit bandwidth to the power of the carrier, and it includes both sidebands. Thus, in our example, we would simply have Sj (f ) = dj (f )2 /B. The amplitude noise spectrum is defined in a similar way as the ratio of the amplitude noise power per unit bandwidth to the power of the carrier. Following a similar approach, we would find Sa(f ) = de (f )2 / V02B, where, in the simple case of a small sinusoidal variation of the amplitude, de (f ) is the rms of the amplitude fluctuation. These two expressions for the noise spectra, which we have derived here using an elementary example, have very general validity, provided dj and de are defined in a more general way. Again, we will not attempt to discuss this complex issue here and will defer to the references already quoted in Section 5.1, in particular, Maas’s book [4]. Under simplifying assumptions (which are discussed in the quoted references), if we can take the Fourier transform, over a period of time T, of a large number of phase fluctuations j (t), we can define |Dj (f )|2 as the limit, for T ® ¥ of the mean square value of such transforms, where f is the Fourier frequency offset from the carrier frequency f0. The phase-noise spectrum is then expressed as

Sϕ (f ) = |Δϕ (f )|2 /B In a similar way, for the AM noise we can write

(5.17)

5.5  Phase Noise in Amplifiers



89

Sa (f ) = |Δε (f )|2/V20 B

(5.18)

As clearly shown by these two expressions, as well as the basic definitions, both amplitude and phase-noise spectra are defined only relative to a carrier signal, and they are always measured as a function of the frequency offset from the carrier. Instead of including both sidebands, single sideband phase-noise spectra are often presented. The usual symbol is L (f ) and we have: Sj(f) = 2 L (f ). Phase noise is generally expressed in decibels relative to the carrier power, per unit bandwidth.

5.5  Phase Noise in Amplifiers In recent years, the phase noise of an amplifier has been increasingly recognized as a critical performance parameter for many important applications. It is generally understood that the noise in the active devices is the main source of the amplifier’s PM noise, but the specific mechanisms connecting the two are still a subject of much research and debate, especially when the amplifier does not operate linearly. We can say, in general, that two are the leading mechanisms: a conversion to high frequency of the transistor low-frequency (LF) noise, and a direct superposition, amplified, of the transistor high-frequency (HF) noise. The second effect often dominates away from the carrier (in other words, at high offset frequencies), while the first always prevails near the carrier. The two mechanisms can be clearly distinguished by their dependence on the power of the input signal. A direct superposition is an additive process; in other words, the noise is added onto the carrier, and therefore, its level relative to the carrier decreases with increasing input power. On the other hand, in a frequency conversion, the resultant phase noise is proportional to the signal, and therefore the signal-to-noise ratio is not expected to change when the signal power increases, at least as long as the noise sources and the nonlinearities responsible for the upconversion remain unchanged. In the case of a random noise, such as the thermal noise in a resistor, the noise power is distributed equally between amplitude and phase modulation. However, when an upconversion process is involved, different circuit parameters operate differently on the two types of noise, and the PM noise may end up higher or lower than the AM noise, depending on the circuit configuration [42]. We can see these two mechanisms at work even in the simple case of a single device. Shown in Figure 5.5 is a phase measurement on a SiGe HBT, which we have adapted from [43]. The device is measured at 2 GHz in an open-loop configuration, with 50W terminations. The bias network has been optimized for minimum lowfrequency noise. The input power is varied between -5 and +7 dBm; for this device, the level of -3 Bm corresponds to the 1-dB compression. The noise figure, as usually measured (namely in absence of an external input signal), is approximately 2 dB. Each of the curves shown in Figure 5.5 appears very similar to Figure 5.1(b), except that, since the high-frequency floor varies with input power, while the 1/f portion does not, the concept of corner frequency loses its significance. In any case, there is no clear relationship to the corner frequency derived from the current or voltage noise spectrum. The variation of phase noise with power at higher frequencies suggests we are dealing with amplified input noise. As we have seen in (5.2)

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Phase Noise

Figure 5.5  Phase noise of a SiGe HBT as a function of the offset frequency, measured at 2 GHz with input power ranging from -5 to +7 dBm.

in Section 5.2, the thermal-noise power per unit bandwidth in the input resistor is simply given by KT. If we assume it is split equally between phase and amplitude, the phase noise at the input of the device (or any amplifying unit) is KT/2 in each of the two sidebands. Using the definition of phase noise spectrum as the ratio of phase noise power (in both sidebands) to carrier power, we obtain, for the power spectrum Sjin at the input of the device:

Sϕ in(f ) = KT/Pin

(5.19)

where Pin is the input power. The power spectrum at the output can be then expressed in terms of the noise figure F of the device (or the amplifier), defined as the degradation in signal-to-noise ratio, or, in the customary notations:

F = (Si /Ni )/(So /No )



(5.20)

where the input noise is defined as the thermal noise of a resistor at a standard temperature To = 290K. If we apply this definition to the phase noise, we notice that the phase power spectra at input and output can be identified, respectively, with the inverses of the numerator and the denominator. Thus, the output spectrum is given by

5.5  Phase Noise in Amplifiers



91

Sϕ out(f ) = F Sϕ in(f ) = FKTo /Pin

(5.21)

In dBm terms, this expression becomes

Sϕ out(f ) = −174 + F − Pin

(5.22)

Or, for a single sideband,

Lϕ (f ) = −177 + F − Pin

(5.23)

In fact, if we look at the upper curve of Figure 5.5, which corresponds to Pin = -5 dBm, we find a good agreement with the value of -167 computed from (5.22), using the noise figure of 2 dB. As the power increases, however, in order to maintain agreement we need to allow the noise figure to increase progressively. In particular, for the maximum power of 7 dBm, the noise figure is approximately 3.5 dB. Values of the noise figure obtained in this way are in good agreement with direct measurements of the noise figure, provided these are carried out in the presence of an input signal of a strength similar to the one used in the phase measurement. Results similar to the ones shown in Figure 5.5 for a single device were reported also for complete amplifiers; in fact, similar results were reported for amplifiers based on a number of different devices, including GaAs FETs and HEMTs, as well as bipolars [44, 45]. We should mention that, while the situation portrayed in Figure 5.5 is quite common, in some cases the upconverted noise of the active devices may dominate the phase noise both near and away from the carrier. The highfrequency plateau is then determined by the active device’s phase noise, and it does not vary with input power (at least as long as the amplifier behaves linearly). In this case, the corner frequency of the amplifier agrees with the one of the device. Clearly, this situation is more likely to take place when the high-frequency noise of the devices is high, the linearity of the amplifier is poor (or the upconversion mechanism is strong), and the input power is high. In the case of Figure 5.5, the phase spectrum near the carrier does not vary appreciably with power. This is found to be approximately true for many amplifiers of different types, based on both bipolar and FET technologies [44 – 46], at least up to compression. However, there are also many examples of single devices, as well as amplifiers, where the phase noise near the carrier is found to change substantially with input power. For instance, Llopis, et al., [28] report strong variations of phase noise in PHEMTs. It has also been demonstrated several times [43, 45, 47] that the upconversion process is stronger when a device (either a single transistor or an amplifier) is less linear. The portion of the spectrum due to upconversion can be described by an expression of the type

Sj (f ) = k21 S1 + k22 S2 + k23 S3 + . . .

(5.24)

where the S’s are the various device noise sources (both voltage and current), and the k’s are voltage or current conversion factors for each source. Such factors depend on the linearity of the device, which in turn depends on the operating conditions,

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including biases and input power. The low-frequency noise sources do not provide any information on the conversion factors. There is clearly some connection to the device’s intermodulation and distortion characteristics (which will be discussed in Chapter 10), but this whole topic is still quite open for research. At the moment, the k’s are generally used as empirical fitting factors. There is no relationship between the noise figure and the whole portion of the noise spectrum due to upconversion. In addition, as we have seen, the noise figure is not constant for a given amplifier, but depends on the input power. For these reasons Hati, et al., [47] are proposing to replace the noise figure with direct phasenoise spectra as the main noise characterization tool of an amplifier. Most of the issues we have discussed in this section are exemplified by some previously unpublished data for a 16W, 1–4-GHz amplifier based on GaAs FET technology and manufactured by Microwave Power, Inc. (model L104-43) [48]. This unit is built with a modular approach, incorporating GaAs monolithics in the preamplifier section and ceramic circuits, with GaAs FETs, in the driver and output sections. In particular, the high-gain monolithic used at the input (TGA 8061) has a typical noise figure of 2.5 dB in the 1–4 GHz frequency range. The residual phasenoise measurements are taken with a commercial phase-measuring system based on dual channel cross correlation. The system noise floor is always at least 20 dB below the measured data. The setup is very similar to the one described by Hati, et al., [44, 47]. Some of the main issues pertaining to residual phase noise measurements are also reviewed in these references. An overview of the measuring technique can be found in [49]. The term residual refers to the fact that the measuring system automatically subtracts the source noise, leaving the device noise as a residue. Additive has been proposed as an alternative term, but other authors use it to mean the noise generated inside the amplifier (as opposed to the one amplified or upconverted by it), so the meaning of this term is somewhat ambiguous. At the moment we will still use residual. A typical unretouched measurement is shown in Figure 5.6. This is a singlesideband residual phase noise spectrum taken at 2 GHz, with an input power of -21 dBm and an output power of 38.2 dBm. At this point, the amplifier still operates almost within its linear range: the gain compression is less than .5 dB. Apart from the peak near 1 kHz, which we will address shortly, the noise close to the carrier follows a 1/f slope up to 5 or 10 kHz; after that, white noise takes over. If this could be interpreted as a corner frequency for GaAs FETs, it would be quite a remarkable result. In fact, this early onset of white noise clearly suggests that the high-frequency plateau is not due to the upconversion of the transistors’ lowfrequency noise; rather, it represents the additive amplification of the input thermal noise. Applying (5.23) to the plateau on the right side, we obtain a noise figure of 3 dB, in good agreement with the noise figure of the input MMIC. Only the portion of the curve below about 10 kHz represents an upconversion of the transistors’ phase noise. Thus, with reference to Figure 5.3, only the 1/f noise of the FETs contributes to the phase noise of the amplifier. The upconverted white noise (represented by the noise figure of the devices) is buried under the additive amplified thermal noise. The variation of the phase noise with power for the same amplifier is displayed in Figure 5.7. Here the original spectra were replaced by smooth line fits to enable a clear view of the crossing between the two curves. On the right-hand side, the noise

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Figure 5.6  Residual phase noise of a 16W, 1–4 GHz amplifier, measured at 2 GHz.

Figure 5.7  Residual phase noise for the same amplifier, as in Figure 5.6. The two spectra are taken at 3 GHz, with two different power levels.

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decreases with increasing power, as expected for the additive process related to the amplification of the input thermal noise. As for Figure 5.6, there is good agreement with (5.23), provided the noise figure is allowed to increase from about 3 dB at the low-power level to about 9 dB at the high one. This effect has been well established [43– 47]. Typically, the noise figure starts to change in the neighborhood of 1-dB compression; the less linear the amplifier, the stronger the variation. The portion of the spectrum near the carrier shows the familiar 1/f general trend, with the addition of two bumps, one around 1 kHz and the other around 100 kHz. The latter one is hidden at the lowest power (as well as in Figure 5.6) by the high level of white noise. This bump, with its characteristic Lorentzian shape, is typical of a G-R noise source present in many GaAs-based devices. For instance, it is clearly visible in the HBT of Figure 5.1 and the MESFET of Figure 5.3. In fact, when the phase noise of the power devices used in this unit (FLK307X, manufactured by Eudyna) was separately measured, a similar profile was clearly present. The peak around 1 kHz is more intriguing because of its sharp features. A G-R bump in this frequency range is not unusual for GaAs devices (see, for example, the PHEMT example of Figure 5.3), but it is often at least partially buried in the high 1/f noise background. A mild enhancement was observed also in the phase noise of the power FETs used in this unit. The development of a well-defined peak, as observed in Figures 5.6 and 5.7, is probably due to the high electric fields present in the output power devices, combined with the interconnection of eight devices in parallel. It is well known that under the influence of strong electric fields, the capture of electrons by a deep trap can be enhanced to the point of generating oscillations in the GaAs semi-insulating substrate [50, 51]. An oscillation of this type can be transferred to the FET current either by backgating or (more likely) through the gate pad. In the process, the oscillation is typically dampened enough to become harmless, but it can still be detected as a peak in noise. The most interesting result displayed in Figure 5.7 is the strong shift upward of the phase noise near the carrier when the power increases. The residual phase noise is found to rise by over 10 dB when the output power varies from 28.8 dBm (about 10-dB below the onset of compression) to 43.9 dBm (full saturation). As a result, the whole curve pivots around a point (in the neighborhood of 100 kHz), which separates the additive portion of the spectrum on the right from the upconverted portion closer to the carrier. The upconversion process includes both 1/f noise and trap-related peaks. With reference to (5.24), we have mentioned earlier that we do not expect a change in phase noise near the carrier as long as the noise sources in the devices, as well as the conversion factors, remain constant. However, neither of these conditions is generally true. In particular, for the case of FETs, both the low-frequency noise and the upconversion mechanism have been shown to vary substantially with power [28]. Also, as the input power is progressively increased, we expect different sections of the amplifier to operate progressively in a less linear fashion. All the devices that are included in the unit participate in the upconversion process. Even when the amplifier operates linearly, there are nonlinear elements in the devices, which upconvert the low-frequency noise and are responsible for its transformation into phase noise near the carrier. Such an element is, for instance, the gate of an FET. However, as the strength of the RF signal is progressively in-

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95

creased, the contribution of different devices will change differently with power. In the case of this particular amplifier, the whole preamplifier section is designed to operate linearly, even when the amplifier is well into compression. Therefore in this section, both noise sources and upconversion factors are not expected to vary substantially. This is not true for the GaAs FETs in the output and driver sections. These are expected to be the main contributors to the change in phase noise with power. Also, as the power is progressively increased, we expect the output FETs to be involved first, followed by the drivers. All we have said so far refers to phase noise caused by upconversion of the active devices’ low-frequency noise. At higher signal levels, other sources of phase noise are also expected to play a role. In particular, AM-to-PM conversion has been proposed as a major source of phase noise increase in amplifiers at high compression levels [52]. In the case of Figure 5.5, however, most of the change appears to be related to a variation of the low-frequency noise sources in the devices and their upconversion factors, since the noise increase is concentrated in the 1/f region near the carrier. The variation of phase noise with power is further explored in Figure 5.8, where the residual phase noise of the same amplifier at 100 Hz is plotted against the output power. The straight line is just a best fit that is compatible with experimental errors, and does not imply an exactly linear dependence. Since the 1-dB compression point is 39 dBm, we find that the amplitude of the RF signal affects the phase noise near the carrier already at levels well below the 1-dB compression. The

Figure 5.8  Phase noise at 100 Hz as a function of the output power for the same amplifier as in Figures 5.6 and 5.7. The measurements were taken at 2 GHz.

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specific dependence on output power shown in this figure is undoubtedly tied to the architecture of this amplifier: indeed, the particular way phase noise varies with compression is known to depend on the position of the main noise sources within the amplifier (closer to the input or the output) [53]. However, this design approach (where the output devices are under strongest compression) is certainly not unusual in power amplifiers. The results shown in Figure 5.8 suggest that, to achieve a very low phase noise performance, one might have to operate the amplifier well below the onset of compression.

References   [1] Fukui, H., Low Noise Microwave Transistors and Amplifiers, IEEE Press, 1981.   [2] Motchenbacher, C. D., and J. A. Connelly, Low Noise Electronic System Design, WileyInterscience, 1993.   [3] Fish, P. J., Electronic Noise and Low Noise Design, McGraw Hill, 1993.   [4] Maas, S. A., Noise in Linear and Nonlinear Circuits, Norwood, MA: Artech House, 2005.   [5] Bonani, F., and G. Ghione, Noise in Semiconductor Devices: Modeling and Simulation, Springer-Verlag, 2001.   [6] Escotte, L., et al., “Noise Behavior of Microwave Amplifiers Operating under Nonlinear Conditions,” IEEE Trans. on Microwave Theory and Techniques, Vol. 53, 2005, pp. 3704–3711.   [7] Vandamme, L. K. J., “Noise as a Diagnostic Tool for Quality and Reliability of Electronic Devices,” IEEE Trans. on Electronic Devices, Vol. 41, 1994, pp. 2176–2187.   [8] We have seen in Section 2 of Chapter 3 that electrons follow the Fermi distribution function. Only a fraction of them, within an energy range of the order of KT from the Fermi energy, can be thermally excited. These are the electrons we are referring to as free electrons.   [9] Sarpeshkar, R., T. Delbruck, and C. A. Mead, “White Noise in MOS Transistors and Resistors,” Circuits & Devices, November 1993, pp. 23–29. [10] These are lattice vibrations that require a minimum of energy to be excited. [11] Van der Ziel, A., “Thermal Noise in the Hot Electron Regime in FETs,” IEEE Trans. on Electronic Devices, Vol. 18, 1971, p. 977. [12] Statz, H., et al., “Noise Characteristics of Gallium Arsenide Field-Effect Transistors,” IEEE Trans. on Electronic Devices, Vol. 21, 1974, pp. 549–562. [13] Van der Ziel, A., “Noise in Solid-State Devices and Lasers,” IEEE Proc., Vol. 58, 1970, pp. 1178–1206. [14] Hooge, F. N., “1/f Noise Sources,” Trans. on Electronic Devices, Vol. 41, 1994, pp. 1926– 1935. [15] Hughes, B., et al., “GaAs FETs with a Flicker-Noise Corner Below 1MHz,” IEEE Trans. on Electronic Devices, Vol. 34, 1987, pp. 733–741. [16] Hooge, F. N., “1/f Noise Is No Surface Effect,” Phys. Lett., Vol. A29, 1969, p. 139–140. [17] Van der Ziel, A., “Unified Presentation of 1/f Noise in Electronic Devices: Fundamental 1/f Noise Sources,” IEEE Proc., Vol. 76, 1988, pp. 233–258 (1988). See also [10]. [18] Pawlikiewicz, A. H., and A. van der Ziel, “Location of 1/f Noise Sources in BJT’s—II. Experiment,” Trans. on Electronic Devices, Vol. 34, 1987, pp. 2009–2012. [19] Niu, G., “Noise in SiGe HBT RF Technology: Physics, Modeling and Circuit Implications,” IEEE Proc., Vol. 93, 2005, pp. 1583–1597. [20] Bary, L., et al., “Low Frequency Noise and Phase Noise Behavior of Advanced SiGe HBTs,” IEEE MTT-S Int. Symp. Digest, 2001, pp. 1705–1708.

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[21] Vandamme, L. K. J., and G. Trefan, “Review of Low-Frequency Noise in Bipolar Transistors over the Last Decade,” Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2001, pp. 68–73. [22] Costa, D., and J. S. Harris, “Low-Frequency Noise Properties of N-p-n AlGaAs/GaAs Heterojunction Bipolar Transistors,” IEEE Trans. on Electronic Devices, Vol. 39, 1992, pp. 2383–2394. [23] Kuleshov, V. N., “1/f Models of Bipolar Junction Transistor and Their Application to PM and AM Noise Calculation,” 1998 IEEE Int. Freq. Cont. Symp., pp. 164–170. See also [20]. [24] Applied Wave Research, El Segundo, California, http://www.awrcorp.com, last accessed April 29, 2009. [25] Ferre-Pikal, E. S., “Reduction of Phase Noise in Linear HBT Amplifiers Using Low-Frequency Active Feed-Back,” IEEE Trans. on Circuits Systems I, Vol. 51, 2004, pp. 1417–1421. [26] Margraf, M., and Boeck, G., “Analysis and Modeling of Low-Frequency Noise in Resistive FET Mixers,” IEEE Trans. on Microwave Theory and Techniques, Vol. 52, 2004, pp. 1709–1718. [27] Liu, S.-M. J., “A Comparison of Low- and High-Frequency Noise Spectra of 0.1 Micron Gate-Length Conventional, Pseudomorphic, and Planar-Doped Mosfet Structures,” 1987 IEDM Digest, 1987, pp. 414–417. See also [15]. [28] Llopis, O., et al., “Nonlinear Noise Modeling of a PHEMT Device Through Residual Phase Noise and Low-Frequency Noise Measurements,” 2001 MTT-S Int. Symp. Digest, 2001, pp. 831–834. [29] Felgentreff, T., and Olbrich, G. R., “Modeling of Low-Frequency Noise Sources in HEMTs,” 1996 MTT-S Int. Symp .Digest, 1996, pp. 1743–1745. [30] Graffeuil, J., and Plana, R., “Low-Frequency Noise Properties of Microwave Transistors and Their Applications,” 1994 European Microwave Conf., 1994, pp. 62–75. [31] Dallas, P. A., and Everard, K. A., “Measurement of Cross Correlation Between Baseband and Transposed Flicker Noises in a GaAs MESFET,” 1990 MTT-S Int. Symp. Digest, 1990, pp. 1261–1264. [32] Martinez, R. D., et al., “Measurement and Model for Correlating Phase and Baseband 1/f Noise in an FET,” IEEE Trans. on Microwave Theory and Techniques, Vol. 42, 1994, pp. 2051–2055. [33] Peacock, S. C., et al., “Study of Flicker Phase Modulation and Amplitude Modulation Noise in Field Effect Transistor Amplifiers,” Proc. of 2001 IEEE Int. Freq. Contr. Symp., 2001, pp. 200–204. [34] Verdier, J., et al., “Analysis of Noise Up-Conversion in Microwave Field-Effect Transistor Oscillators,” IEEE Trans. on Microwave Theory and Techniques, Vol. 44, 1996, pp. 1478–1482. [35] Reynoso-Hernandez, J. A., and Graffeuil, J., “Output Conductance Frequency Dispersion and Low-Frequency Noise in HEMTs and MeESFETs,” IEEE Trans. on Microwave Theory and Techniques, Vol. 37, pp. 1478–1481. For the input resistance, see [28] and [26]. [36] Angelov, I., et al., “A Simple Bias Dependent LF FET Noise Model for CAD,” IEEE MTT-S Int. Symp. Digest, 2001, pp. 407–410. [37] Pospieszalski, M. W., “Modeling of Noise Parameters of MESFETs and MODFETs and Their Frequency and Temperature Dependence,” IEEE Trans. on Microwave Theory and Techniques, Vol. 37, 1989, pp. 1340–1350. [38] Traverso, P. A., et al., “An Empirical Bipolar Device Non Linear Noise Modeling Approach for Large Signal Microwave Circuit Analysis,” IEEE Trans. on Microwave Theory and Techniques, Vol. 54, 2006, pp. 5341–4352, and references therein. [39] Jahan, M. M., et al., “Bias Dependence of High-Frequency Noise in Heterojunction Bipolar Transistors,” IEEE Trans. on Microwave Theory and Techniques, Vol. 51, 2003, pp. 677–683.

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Phase Noise [40] Thorsell, M., et al., “Thermal Characterization of Intrinsic Noise Parameters for AlGaN/ GaN HEMTs,” 2008 MTT-S Int. Symp. Digest, 2008, pp. 463–466. [41] Demir, A., “Computing Timing Jitter from Phase Noise Spectra for Oscillators and PhaseLocked Loops with White and 1/f Noise,” IEEE Trans. on Circuits Systems I, Vol. 53, pp. 1869–1884, and references therein. [42] Walls, F. L., et al., “Origin of 1/f PM and AM Noise in Bipolar Junction Transistor Amplifiers,” IEEE Trans. on Ultras. Ferroel. Freq. Cont., Vol. 44, 1997, pp. 326–334. [43] Cibiel, G., et al., “A Study of the Correlation Between High-Frequency Noise and Phase Noise in Low-Noise Silicon-Based Transistors,” IEEE Trans. on Microwave Theory and Techniques, Vol. 52, 2004, pp. 183–190. [44] Hati, A., et al., “Noise Figure vs. PM Noise Measurements: A Study at Microwave Frequencies,” Proc. of 2003 IEEE Int. Freq. Contr. Symp., 2003, pp. 516–530. [45] Chambon, C., et al., “C-Band Noise-Parameter Measurement of Microwave Amplifiers Under Nonlinear Conditions,” IEEE Trans. on Microwave Theory and Techniques, Vol. 55, 2007, pp. 795–800. [46] Silva, M. J. M., et al., “Phase Analysis of a Variable Gain Amplifier Controlled Through Matching Networks,” 4th ICEEE Proc., Mexico City, 5–7 September 2007, pp. 221– 224. [47] Hati, A., et al., “Merits of PM Noise Measurement over Noise Figure: A Study at Microwave Frequencies,” IEEE Trans. on Ultras. Ferroel. Freq. Cont., Vol. 53, 2006, pp. 1889–1893. [48] Courtesy of Dr. T. Mazilu and G. Nakao of AML Communications. [49] Breitbarth, J., and J. Koebel, “Additive (Residual) Phase Noise Measurement of Amplifiers, Frequency Dividers, and Frequency Multipliers,” Microwave Journal, June 2008, pp. 66–82. [50] Miller, D. J., and M. Bujatti, “Mechanisms for Low-Frequency Oscillations in GaAs FETs,” IEEE Trans. on Electronic Devices, Vol. 34, 1987, pp. 1239–1244. Also in Tiwari, S., (ed.), Compound Semiconductor Transistors: Physics and Technology, IEEE Press, 1993, pp. 91–96. [51] Kiyama, M., et al., “Quantitative Analysis of Low Frequency Current Oscillations in SemiInsulating GaAs,” European Phys. J. Appl. Phys., Vol. 27, 2004, pp. 185–188. [52] Breitbarth, J., et al., “Additive Phase Noise in Linear and High-Efficiency X-Band Power Amplifiers,” 2006 IEEE MTT-S Int. Symp. Digest, 2006, pp. 1871–1874. [53] Escotte, L., et al., “Noise Behavior of Amplifiers Operating Under Nonlinear Conditions,” IEEE Trans. on Microwave Theory and Techniques, Vol. 53, 2005, pp. 3704–3711.

Chapter 6

Technologies for Microwave Power Amplifiers

6.1  Introduction In this chapter, we will briefly review the main technologies used in microwave power amplifiers. As in the rest of this book, we will deal only with solid-state devices and concentrate chiefly on high power levels and high frequencies. The applications we will address are in the traditional fields of radar, electronic warfare, telecommunication equipment, and dedicated test and measuring systems. From the production point of view, these are mostly high-cost, relatively low-volume products; they require specialized assembly and time-consuming, sophisticated testing. Often, a significant amount of dedicated development will have to be absorbed by a limited production run. The cost of labor (including development) is so prevailing, that seldom does the price of components or materials become a significant issue. For instance, gold has always been the preferred choice as a conductor, independent of its price fluctuations on the market. In the last 10–20 years, with the advent of cell phones and other similar wireless applications, a large microwave consumers’ market has also developed. It is concentrated in a relatively narrow frequency range (mostly below 3 GHz), at low or moderate powers. The large volumes and tight profit margins characteristic of this type of market dictate different logics and specific technological choices. Silicon devices and integrated circuits are used much more than in the rest of the microwave industry [1, 2]. Low-temperature cofired ceramics (LTCC) [3] and other similar multilayer approaches are favored. In fact, in this market, microwave and computer technologies appear to be progressively merging. This is a very remarkable development, but it is outside the scope of this book and has been covered by other authors [4, 5]. Still, some of the technologies we will discuss, notably ceramic circuits, are also a basis for many of the developments in the wireless industry. Also, within the wireless industry, power amplifiers for base stations, with their relatively high powers and moderate volumes, share many of the characteristics that are the focus of this book.

6.2  Waveguide Components Until the 1950s, waveguides and coaxial cables were the main microwave transmission media; microwave signals were processed mostly by waveguide components. 99

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With the development of microwave integrated circuits (MICs), in their various forms, these have progressively become the dominant technology and planar lines (especially microstrip) the preferred transmission media. As a result, systems have become smaller and lighter, less expensive and, at the same time, more sophisticated. Waveguide components, however, are far from obsolete. In fact, they still maintain a significant advantage in terms of losses and power handling capability. For this reason, they are still often the preferred choice for output couplers and radial combiners in high-power amplifiers. The advantage of waveguides is especially significant at higher frequencies, where their physical size is more manageable, and, on the other hand, the loss of planar transmission lines is higher. Several examples of combiners based on waveguides will be given in Chapter 7. In particular, Figure 7.31 displays a photograph of a radially combined power amplifier operating at 20 GHz.

6.3  Microwave Integrated Circuits (MICs) Several excellent historical reviews of microwave integrated circuits (MICs) are available in the literature [6–8]. A large variety of technologies goes under this general name. We will review here only the ones most common in power amplifiers, especially broadband amplifiers at higher frequencies. Circuits fabricated using soft substrates are often separately classified as microwave printed circuits (MPCs). These circuits generally use copper as a conductor and are fabricated by a process of photolithography and wet chemical etching quite similar to the one used for low-frequency printed circuit (PC) boards. They do not incorporate resistors or dielectrics, just the conductive elements. They are typically used to fabricate passive components. At high frequencies and for broadband applications, a rigid and dimensionally stable substrate, such as alumina, is generally preferred, and microstrip is the most common transmission medium. Since most of the electromagnetic field is contained in the substrate, the choice of material is critical. Many characteristics are important. Dielectric constant, thermal transfer, mechanical strength, and manufacturing compatibility are some of them, but the first requirements are low electrical conductivity and low loss. In fact, despite many valiant attempts and the attractive characteristics of silicon, its relatively low intrinsic resistivity has always proven an insurmountable obstacle to its widespread use in MICs. Depending on the choice of material, we can divide MICs into two very broad groups: hybrid circuits, where the substrate is not a semiconductor and active devices need to be separately attached once the circuit is completed, and monolithic microwave integrated circuits (MMICs), where the substrate is a semiconductor, and active devices are fabricated within the substrate itself. Among hybrid circuits, we might make an additional distinction between circuits where even passive elements are separately attached, and only the conductive pattern is defined on the substrate (sometimes called chipand-wire circuits) and the more sophisticated variety where all passive elements are integrated, and only active devices need to be added. These are sometimes called semimonolithic ceramic circuits, and they also generally include effective provisions to incorporate and heat-sink the active devices.

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6.3.1  Microwave Printed Circuits

A soft substrate for microwave applications is composed of a dielectric sheet of polytetrafluoroethylene (PTFE, best known as Teflon) sandwiched between two metal foils. The dielectric is loaded with either glass fiber or ceramic powder. Glass fiber is used to increase the mechanical stability of the sheet, while ceramic powder is used to adjust the dielectric constant of the substrate. The metal foils, typically copper, are attached with an adhesive. Commercial products, often known under the trade name of Duroid [9], are available with relative dielectric constants ranging from 2.2 to 10.2 and metal thicknesses from 8 to 70 mm. In power amplifiers, soft substrates are used mostly in combination with packaged devices. In a typical configuration, the substrate of the printed circuit is soldered on a ground plate, and the RF circuit, etched on the top surface, includes matching circuits, bias networks, and couplers of either the branch or ring type. Note that the patterning resolution achievable on this medium is not high, and certainly not good enough for Lange-type couplers. The power devices are typically dropped in holes punched through the substrate and fastened to the supporting ground plate for heat sinking. The RF terminals of the package are then soldered to the metal traces of the matching circuits. The complete circuit may include many additional discrete components, such as various capacitors, bias or termination resistors, and lumped inductors. The resultant overall structure is usually large, compared to an alumina-based amplifier, but the heat dissipation is good, and the assembly is sturdy, since all the delicate components are packaged, and all the circuit connections are soldered. In this type of application, printed circuits are almost exclusively in the form of microstrip lines. Soft substrates, however, are widely used in a stripline configuration to build passive components; in fact, the stripline technology dominates the production of microwave couplers. Couplers of this type may be used in power amplifiers for signal dividing, broadband power combining, and signal sampling. Finally, soft substrates are also used in some special applications, such as finlines, to couple into waveguides, coplanar waveguides, and some types of radial combiners. A soft substrate, when compared with a hard one, has a number of desirable characteristics. It can be cut and punched easily with simple tools. The material is inexpensive and can be acquired in sheets as large as 18 ´ 48 inches. It can be processed in the same way as the standard epoxy-fiberglass used for PC boards, including photolithographic techniques, double-side patterning, and metal-coated vias. Hence, large production facilities are readily and cheaply available. The metal foil can be sufficiently thick to carry large currents, and, since it is made of copper, it can be soldered with simple tools using regular PbSn solder alloys. The main problem with a soft substrate is the dimensional stability, particularly if the circuit must operate at high temperature. The thermal expansion coefficient of the dielectric is high, and because of the plastic characteristic of PTFE, the circuit may not recover its original size after a complete temperature cycle. Also, if PTFE is mechanically stressed, it deforms permanently, even at room temperature (in other words, it cold flows). Finally, the substrate is not suitable for the definition of small details, because, on one side, the surface is not sufficiently flat to allow fine photolithography, and on the other, the metal foil is too thick for high-precision etching.

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Technologies for Microwave Power Amplifiers

6.3.2  Hybrid Circuits

For hybrid circuits, alumina is by far the most popular substrate. It is a ceramic-like microcrystalline material, almost totally composed of Al2O3 (with small amounts of glassy filling) and produced by a high-temperature process called firing. It is available in many degrees of purity and grain size (the higher the purity, the finer the grain structure), as well as various thicknesses, typically ranging from 0.005 to 0.05 inches. A larger grain size is associated with rougher surfaces and increased scattering, and therefore is avoided, especially at higher frequencies. A 996 grade (99.6% of Al2O3) is generally used in microwave applications. Alumina substrates are available both polished and as fired. Polishing improves both surface smoothness and flatness. Typically, the surface finish may go from four to one m-inch and the bowing of the substrate (its camber) from 2 ´ 10-3 to about 5 ´ 10-4. This is a significant issue in connection with the ability to reproduce fine details by photolithography and achieve a uniform dimensional control in critical features, such as high-frequency Lange couplers and other similar structures. As compared to silicon or GaAs wafers, alumina substrates are more rigid and less flat, so they do not adhere well to the glass masks used in the photolithographic process. Especially on large substrates of several inches, as used in many modern batch fabrication processes, the ability to produce a good contact and a sharp image is limited mostly by the substrate’s flatness. The best strategy is to maintain a slight separation between the substrate and the mask and use an optical system designed to project the image across the small gap, rather than form a sharp focus at the mask level. This approach also saves the mask from the damage produced by a tight contact with a hard substrate. Because of its hardness (9 on the Mohs scale), alumina is drilled mostly by laser, and a fine row of laser-drilled holes is used, in lieu of scribing, to cut substrates to size, but the resulting edge is somewhat rough. When a clean cut is required, in particular when separating finished circuits, a diamond saw is generally preferred. In terms of process compatibility, alumina is extremely sturdy: it can withstand almost any chemical etching and most common plasma processing. At thicknesses of 10 mils or higher, there is seldom any issue of breakage during process, even for large and drilled substrates. The most likely failure is cracking due to thermal stress, when there is a strong thermal excursion and alumina is attached to a metal with a rigid bond, either during processing or during final assembly. But this is true for most rigid substrates. As shown in Table 6.1, all have much lower thermal-expansion coefficients than most common metals: in the same units, aluminum has 2.4 ´ 10-5, and copper 1.7 ´ 10-5. Alumina is an excellent dielectric, with a low loss tangent and a decent thermal conductivity. By far, it is not enough to dissipate the heat produced by an active device of any significant power, but it is typically sufficient, for instance, to heat-sink safely the termination resistors of a coupler, even in a power application. The dielectric constant is fairly high, in the range of 9.5–10 (with higher values corresponding to higher percentages of Al2O3). This is an advantage at relatively low frequencies, since it leads to smaller dimensions for the circuit elements; however, at higher frequencies, when the substrate thickness needs to be reduced to prevent excessive radiation loss, the dimensions of the microstrip lines may become too small to be practical. A material with a lower dielectric constant, such as fused silica, is often

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Table 6.1  Characteristics of MIC Substrates Parameter

Units

Alumina

Fused Silica

Aluminum Nitride

Beryllia

GaAs

GaN

SiC

Relative Dielectric Constant Loss Tangent Thermal Conductivity Linear Thermal Expansion

—

9.5–10

3.8

8.5–9

6.5

12.5

9.5

10

—

3 ´ 10-4

1 ´ 10-5

1 ´ 10-3

5 ´ 10-4

6 ´ 10-3 2 ´ 10-2

3 ´ 10-3

0.01

2

3

0.54

1.3

3–4

0.6

4–5

8–9

5.7

3–4

3–4

W 0.27 °C-1cm-1 10-6 °C-1 8

preferred in this case. The term quartz (sometimes fused quartz) is often used, even though we are dealing with a noncrystalline, glassy form of SiO2. It has a relatively low dielectric constant of 3.8 and an excellent loss tangent, as low as 1 ´ 10-5; however, it is more fragile and expensive than alumina and not as widely available, especially in large sizes. Also, its thermal properties make it unsuitable for any application where a significant amount of heat transfer is involved. Beryllia (BeO) and aluminum nitride (AlN) are used when good heat conduction is required. The first has superior thermal characteristics, but its machining is problematic, since the dust is a severe health hazard. Partly for this reason and partly because Be is a fairly rare element, beryllia is one of the most expensive of all ceramic materials, and its use is limited to extreme situations, where the advantage in heat conduction is the only determining factor. For most applications, aluminum nitride, with thermal properties only slightly less favorable, is generally preferred. The characteristics of the most important MIC substrates are compared in Table 6.1, which includes both insulators used in hybrids and semiconductors used in MMICs. These data should be used only as an indication, since values reported in the literature vary quite a bit, especially for newer materials, where there is ongoing progress. The values in the table were taken from the major manufacturers’ Web sites in early 2009. In terms of metallization, two different approaches are available. In thin-film technology, the metal layer is formed by vacuum deposition (most often sputtering) and electroplating. Patterns are defined by photolithography and etching. For semimonolithic ceramic circuits, resistive and dielectric films are also formed in a similar way. A thick-film circuit is fabricated instead by silk-screening special inks, which can be conductive, resistive, or insulating, depending on the desired electrical function [10]. A thick-film ink is a mixture of an organic vehicle and an inorganic powder (in particular, a metallic powder) dispersed in a small amount of glass, which provides adhesion [11]. During a high temperature process called “firing,” the organic vehicle burns off, and the glass flows, forming a composite with the inorganic powder. This is a simple and flexible technology, whereby multilayers of conductive, resistive, and dielectric structures can be formed on both sides of a substrate. Both solderable and bondable surfaces can be obtained, so that all types of electronic components may be assembled on the finished circuit; however the quality of the thick-film deposits, in terms of loss, noise, and microdefects, is not as

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high as for thin films. Also, the ability to accurately define and reproduce detailed patterns is limited, and minimum features typically do not exceed 100 mm. For these reasons, the thin-film approach is generally preferred in microwave high-frequency applications. The process flow for a thin-film chip-and-wire circuit typically starts with the vacuum deposition of a thin adhesive layer (such as TiW), followed by a thicker Au layer, on the front and back of the substrate. This is done preferably by sputtering, which provides superior adherence and unstressed, dense layers. An additional advantage is the good coverage of edges, corners, and even the internal surfaces of via holes. The thickness of the conductor depends on the operating frequency. To minimize losses, a thickness of about three times the skin depth is generally specified. At 10 GHz, this amounts to about 2.5 mm. Predeposited substrates are available on the market, with typical Au thicknesses of 3–5 mm, which are adequate for frequencies above approximately 2.5 GHz. The metalized substrate is coated with photoresist and exposed to a light source through a mask that contains the circuit pattern. Many specialized computer-aided design (CAD) tools are available for the design and fabrication of suitable masks. The circuit is then etched, either by wet etches or by sputtering. The second approach is by far preferable, since it produces straight walls and excellent definitions, just as good as the masking process allows. Conversely, a wet chemical etch always undercuts the pattern to some extent, at least by the same amount as the thickness of the layer, but typically more, especially if the adherence of the photoresist to the layer, or the layer to the substrate is not perfect. An additional consideration is the environmental issue of disposal: chemicals suitable to etch Au are not the friendliest substances. The only concern with sputteretching, especially for thicker Au layers, is the ability of the photoresist pattern to withstand the long and harsh process. The etching system should be designed to keep the substrate cool and the photoresist should be hardened using a combination of a high-temperature bake and a UV exposure. For very thick layers (as required for frequencies below 2 GHz), these precautions may not be sufficient. An alternative approach uses a thin Au layer that is selectively electroplated in correspondence to the circuit pattern. Thicknesses above 10 mm are easily obtained this way. If the seed layer is thin, the whole substrate can be chemically etched without a mask, since the plated features would be hardly affected. This approach, however, produces poorer definitions especially if the plating is thicker than the defining photoresist, since the well known “mushroom” shape of plated structures rounds off all corners and sharp features. Also, metal layers obtained by plating are always porous to some extent, and the effective conductivity is not as high as for sputtered layers. Once the conductive pattern is defined, the substrate is cut, typically with a diamond saw, and the discrete components are attached and bonded. Die attaching is typically performed using silver epoxy, and ball bonding with gold wire is generally used on most patterns, except for some particularly small areas (such as the gate of FETs), where wedge bonding must be used. In chip-and-wire circuits, assembly is the most time consuming and expensive operation. It is generally done by highly skilled and specialized labor. Sophisticated computer-controlled machines for die attaching and bonding are now available on the market, but, in the type of applications we are addressing, automatic machines often are not flexible enough: the

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variety of patterns and specifications, combined with relatively low volumes, gives manual labor a definite edge. The main advantage of chip-and-wire technology is the low investment cost, both in terms of equipment and initial cost per run. Masks are inexpensive, and relatively simple CAD tools are required. On the negative side, beside the high labor cost for assembly and testing, chip-and-wire circuits are less reproducible and reliable than more integrated ones. At high frequency, the shape, length, and position of bonds, as well as the exact location of components, are all critical tuning parameters. Manual assembly leads to higher variation and results in longer tuning times. Also, the large number of bonds has a negative effect on circuit reliability. Finally, a drawback that is particularly significant for high-frequency broadband amplifiers is the constrained position of the active devices. These are typically die-attached on a metal ridge, with two hybrid circuits placed against the ridge at both sides, as shown in Figure 6.1. This photograph displays a detail from a low power amplifier stage built with hybrid technology. In this particular case, the sources of the GaAs FET are bonded on capacitors. More often, especially for higher power devices, they would be directly grounded to the metal ridge through via holes. In any case, all the input and output tuning is confined to the two circuits, while all the effective grounding is confined to the ridge. Visible in the picture are several capacitor chips. The dark, irregularly shaped region around the FET and the capacitors is the silver epoxy used for die attachment. Portions of wire-bonded Lange couplers are also visible on both sides. Various conductive patches, some of them connected with wire bonds, are used as tuning elements. 6.3.3  Miniature Hybrid or Semimonolithic Ceramic Circuits

Through the years, a number of highly integrated, ceramic-based technologies have been proposed, with the aim of preserving the flexibility and low investment cost of hybrids, while correcting some of their weaknesses [12–15]. As an example,

Figure 6.1  Detail of an amplifier stage built with hybrid technology (courtesy of AML Communications).

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Figure 6.2 shows a low-power balanced amplifier fabricated with a semimonolithic ceramic technology [16], where only the active devices are still missing. The central strip, grounded by multiple solid via holes, is ready for their die attachment. Other via holes, used as grounds for the capacitors, are visible at the four corners. All resistors and capacitors are fully integrated, and the two Lange couplers are interconnected with air bridges. Except for the higher degree of integration, this circuit is very similar to the one pictured in Figure 6.1 (where only one of the two coupled stages is shown in more detail). When comparing the two pictures, the savings in assembly are immediately visible, but probably the main advantage of the increased integration is the improvement in reproducibility and reliability. The high reproducibility also translates into much shorter tuning times. The use of solid via holes is especially beneficial in high-power amplifiers. Shown in Figure 6.3 is a two-stage amplifier in K-band, where the GaAs FETs are directly attached with Au-Sn eutectic onto solid gold-filled vias that extend through the 10-mil substrate [17]. These conductive pillars provide both grounding and heat sinking. The one for the output device is approximately 40 mils wide and 10 mils long. The smaller, round vias of 10-mil diameter that are visible in the picture are used as electric grounds. All resistors and capacitors are also integrated. Clearly recognizable at the bottom is the resistive bias network. The large, rectangularshaped capacitors are used for blocking and biasing, and the comb-like structures

Figure 6.2  A balanced amplifier stage built with a semimonolithic ceramic technology (courtesy of AML Communications).

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Figure 6.3  1W, K-band amplifier fabricated with a semimonolithic ceramic technology. The size of the chip is about 7.5 × 5.5 mm2.

at the input, interstage, and output for tuning. With respect to a hybrid approach (as exemplified in Figure 6.1), where the position of the device is constrained to a metallic ridge, here it is possible to surround the devices with bias and tuning elements. This generally represents a significant advantage in broadband applications, as discussed in Section 8.3. A typical process flow for a semimonolithic ceramic technology with filled vias comprises the following steps: 1. Drilling the alumina substrate by laser; 2. Filling the holes by plating. 3. Front and back sputter deposition of the first metal, formed by an adhesive layer (such as TiW), followed by gold. Notice that while this is the only metallization for the back, most conductive elements in the front will consist of two metal layers (the top and bottom surfaces of the capacitors). Therefore each layer only needs to be about 1.5 times as thick as the skin depth. 4. Definition of the first metal by sputter etching; 5. Deposition of the resistive layer, typically tantalum nitride; 6. Definition of the resistive layer; 7. Deposition of the dielectric, typically silicon nitride, either by plasma or by reactive sputtering; 8. Definition of the dielectric, typically by plasma; 9. Definition of the polyimide (or other dielectric) used as support for the air bridges; 10. Deposition of the second metal (similar to the first); 11. Definition of the second metal; 12. Removal of the air bridges’ support. This step is not always required, since seldom is the capacitance contributed by such supports significant, and, on the other hand, the support lends mechanical stability.

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Technologies for Microwave Power Amplifiers

Clearly, the process complexity is much greater than in simple chip-and-wire circuits. Equipment costs and processing times, however, are still much more modest than for a monolithic process. Turnaround times may vary between one and two weeks. Masks are relatively cheap, and typical yields are as high as 80%. The size of a two-stage amplifier module, as shown in Figure 6.3, generally does not exceed 0.2 ´ 0.3 inches (.51 ´ .76 cm). Given the high yield, a 3 ´ 3 inch substrate may provide over 100 modules. The final assembly is limited to the die attaching and wire bonding of the devices. Most power devices have source vias connecting the front side to the back side of the die, so that only gates and drains need to be wire-bonded. Similar highly integrated processes on ceramics also find applications in advanced high-frequency packaging and multichip integration of monolithic cir­ cuits [17]. 6.3.4  Monolithic Circuits

While the initial concept of microwave monolithic integrated circuits (MMICs) dates back to the 1950s or 1960s, the real progress came only with the arrival of GaAs MESFETs. This planar device is ideal for incorporation into integrated circuits, and GaAs has intrinsic resistivity sufficiently high to operate well as a microwave substrate. For many years, the low quality of the semi-insulating material available was the main obstacle. The uniformity was insufficient and the yields low, especially for high-power amplifiers, which required relatively large areas of good material. Sometime in the 1990s, however, sufficient progress was made in the basic material to allow the full realization of the GaAs MMIC technology’s potential. Today, not only is a very large variety of circuits readily available at reasonable prices, but there is a choice of good foundry facilities where specially designed circuits can be fabricated without facing a major investment hurdle. Designing an MMIC still requires a considerable investment in CAD software and time. Special attention must be paid to tolerances and variations of components’ characteristics, as well as parasitic effects, such as couplings or resonances. A process for GaAs monolithics typically begins with the formation of the active layer: this can be done by ion implantation or epitaxial techniques. Currently, especially for HEMT devices, molecular beam epitaxy (MBE) is often the preferred approach. Active areas, where the devices will be located, are then isolated, either by additional ion implantation or etching. Next, the devices’ ohmic contacts (typically a gold-germanium alloy) are deposited and defined, followed by the gate structure, which includes an adhesive layer (e.g., Ti), a barrier (e.g., Pt), and Au. This completes the essence of the active devices, and test structures are generally available, so that the wafer can be evaluated at this point. If it meets specifications, resistive and dielectric structures are deposited and defined. Nickel-chrome and tantalum nitride are the most common resistive materials, but doped GaAs is also used. Most often, silicon oxides or nitrides are used for the capacitors. Next, a second layer of metallization is deposited and defined. Often, some areas (in particular, the sources of the power devices) are selectively plated. This is especially important to provide a solid landing to the via holes, which connect the sources to the back of the device. After the front process is completed, the wafer is thinned by lapping, via holes are etched, and the backside is metallized. Most often, especially for high-

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power circuits, the metallization of the backside and vias is reinforced by plating to improve the heat-sinking capability. Once the wafer is tested and cut and the individual chips are selected, we are left with the final step of incorporating the MMIC in the amplifier assembly. Low-power and small-dimension chips are generally handled as single devices. They are dieattached with silver epoxy or Au/Sn eutectic, mostly using manual tools. However, for high-power monolithics with relatively large dimensions, where the issues of heat transfer and thermal stress are critical, the MMIC is generally attached first to an optimal carrier, which is in turn assembled in the amplifier unit. There are three major challenges: (1) eliminating any voids in the die-attaching layer (generally Au/Sn eutectic); (2) matching the coefficient of thermal expansion between GaAs and the carrier; and (3) ensuring optimum heat transfer through the carrier. To minimize voids, the die attaching is generally done under vacuum, after repeatedly flushing with a reducing gas to avoid oxidation of the Au/Sn. The thermal cycle for the die-attaching process needs to be carefully optimized to obtain a complete reflow of the solder and still avoid damage to the MMIC. Concerning the other two requirements, there is a limited choice of suitable materials that offer an acceptable match to the GaAs expansion and provide good heat conduction. Copper-molybdenum and copper-tungsten alloys are the most common choices. Their characteristics vary with the copper content. As expected, an increase in copper leads to higher thermal conduction but also higher expansion. A Cu/W with 10% copper has a thermal expansion of 6.5 ´ 10-6 °C-1 (a pretty good match to GaAs), but the thermal conductivity is only about 1.5 W °C-1cm-1. An increased copper content leads to thermal conductivities as high as 2.5 W °C-1cm-1, but the match in thermal expansion deteriorates. The two alloys have similar thermal characteristics. An advantage of the molybdenum alloy is the lower density (about 10g cm-3, versus 15g cm-3 for Cu/W), but Cu/Mo is also more expensive, so it is preferred only when weight is critical. Both alloys can be machined relatively easily, even in complex shapes, by specialized workshops, but the cost is not negligible. An alternative material, which was originally developed at Texas Instruments specifically as a carrier for GaAs, is Silvar [18]. It is a much softer alloy, easy to stamp, machine, and plate. It contains various percentages of Fe, Ni, Co, and Ag, and is often manufactured starting from Kovar and silver powders. With expansion of around 7 ´ 10-6 °C-1 and conductivity around 1.2 ´ W °C-1cm-1, Silvar’s thermal characteristics are slightly less good than Cu/W or Cu/Mo, but the material is lighter (about 8.8g cm-3) and it is so much easier to machine and plate that it can be handled even in a laboratory environment. At the other extreme are the recently developed aluminum-silicon carbide composites [19]. Their thermal and mechanical characteristics are excellent: as light as Al, but much stronger, they have thermal conductivity as high as 2 W °C-1cm-1 and tailor-made expansion coefficients in the range of 6.5–9.5 ´ 10-6 °C-1. The extreme difficulty of machining, however, is a major drawback. An example of a very high power GaAs MMIC is shown in Figure 6.4. This is a 16W two-stage amplifier operating from 1.3 to 2.5 GHz, with a small signal gain of 25 dB [20, 21]. It is produced with a planar ion-implanted process and incorporates a polyimide scratch protection. The basic active device is a power FET capable of delivering about 1.5W. Two pairs of such devices are visible just above the lower

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Technologies for Microwave Power Amplifiers

Figure 6.4  A high-power GaAs MMIC die, manufactured by M/A-COM (MAAPGM0076).

edge of the picture, while the 16 output devices form an almost continuous stripe just below the center. The upper half of the chip is taken up by the bias network (including the characteristic spiral inductors) and the output combiner. Most of the conducting structures are heavily plated. This is required by the relatively low frequency of operation. The unusually large dimensions of this chip (about 5 ´ 8 mm2) pose significant challenges in terms of die attaching. A vacuum reflow process and a carrier with good thermal matching are definitely required. Another example of a high power amplifier, at a much higher frequency but lower power, is given in Figure 6.5. The TGA4906, manufactured by TriQuint [22] with its “0.15m power PHEMT” process, delivers 4W in the frequency range of 28 to 31 GHz. Its main application is for VSAT. It is a 3-stage amplifier, with 4 devices at the input, 8 at the interstage, and 16 at the output. The device geometry is differrent at each different stage. Despite the high complexity, the size of the die is not too large (about 3 ´ 3 mm2), and the output combiner is fairly compact, due to the high frequency of operation. This chip also exists in a double version, capable of delivering 7W in a slightly reduced frequency range. As a final example, we have chosen for Figure 6.6 a lower power MMIC die manufactured again by TriQuint. This is a broadband (2–22 GHz), 1W amplifier using the standard TriQuint “0.25m PHEMT” process. It is designed as a distributed amplifier [23], with the signal meandering through the die, from the input in the lower right corner to the output in the upper right one. Most conductive structures are Au plated. As is typical of TriQuint processes, extensive use is made of air bridges, and care must be exercised in picking up and handling the die, so as not to damage the fragile structures. Many bridges can be identified easily in the picture, including a large one at the output and another, with a double span, in the bias network on the right. All these examples use GaAs, which is, by far, the preferred material. Some specialized high-frequency circuits are fabricated on InP, while Si is sometimes used at the lower frequencies. In the future, GaN is expected to have an increasing role.

6.3  Microwave Integrated Circuits (MICs)

Figure 6.5  A power amplifier manufactured by TriQuint (TGA4906).

Figure 6.6  A distributed amplifier manufactured by TriQuint (TGA2509).

111

112

Technologies for Microwave Power Amplifiers

The development of a new material is never completely painless, but, in this case, the introductive phase may be shortened by the good compatibility between GaN and the existing GaAs facilities. Today, there is a very large variety of MMICs ready for use, and most high-volume applications are well covered, sometimes with a range of choices. If a monolithic circuit with the right characteristics is available, this is most often the best solution, and almost always the most economical one. But in many high performance amplifiers, there is still a need for custom-designed circuits. In this case, the designer has a choice between using one of several MMIC foundries and adopting a hybrid approach. Designing a monolithic circuit requires considerable experience and extensive use of CAD software. The design procedure must take into account components’ tolerances, proximity effects, and realistic discontinuity models. Parasitic effects are not always easy to control; tolerances are tight, and the number of processing steps is high. All this translates generally into low yields and a high cost of entry. In practice, a customized MMIC is typically justified only for relatively high volumes (on the order of several hundred, at least). For lower quantities, a semimonolithic hybrid approach represents a viable alternative.

References   [1] Rijs, F., “Status and Trends of Silicon LDMOS Base Station P. A. Technologies to Go Beyond 2.5-GHz Applications,” 2008 IEEE Radio and Wireless Symp., 2008, pp. 69–72.   [2] Nobbe, D. W., “Silicon Technology Status and Perspectives for Multiband and MultiStandard Challenges in Upcoming Frontends,” 2008 IEEE Radio and Wireless Symp., 2008, pp. 191–194.   [3] Imanaka, Y., Multilayered Low Temperature Co-Fired Ceramic (LTCC) Technology, Springer, 2005.   [4] Chang, K., et al., RF and Microwave Circuit Design for Wireless Applications, Wiley, 2001.   [5] Cripps, S. C., RF Power Amplifiers for Wireless Communications, Norwood, MA: Artech House, 1999.   [6] Niehenke, E. C., et al., “Microwave and Millimeter-Wave Integrated Circuits,” IEEE Trans. on Microwave Theory and Techniques, Vol. 50, 2002, pp. 846–856.   [7] Howe, H., Jr., “Microwave Integrated Circuits—An Historical Perspective,” IEEE Trans. on Microwave Theory and Techniques, Vol. 32, 1984, pp. 991–995.   [8] Oliner, A. A., “Historical Perspectives of Microwave Field Theory,” IEEE Trans. on Microwave Theory and Techniques, Vol. 32, 1984, pp. 1022–1045.   [9] Rogers Corporation, http://www.rogers.com, last accessed April 29, 2009. [10] Haskard, M. R., and K. Pitt, Thick Film Technology and Applications, Electrochemical Publications, IOM, 2005. [11] Rose, A., “Considerations in Formulation and Manufacturing of Thick Film Inks,” Electrocomponent Science and Tech., Vol. 9, 1981, pp. 43–49. [12] Sechi, F., et al., “Miniature Beryllia Circuits—A New Technology for Microwave Power Circuits,” RCA Rev., Vol. 43, 1982, pp. 363–372. [13] Sechi, F. N., and Bujatti, M., “Broadband Power Amplifiers Based on a New Monolithic Ceramic Technology,” 1989 IEEE MTT-S Int. Symp. Digest, 1989, pp. 937–940. [14] Bujatti, M., and F. N. Sechi, “Wideband Power Amplifiers for Test Instrumentation,” Microwave Engineering Europe, October 1995, pp. 43–47.

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[15] Stoneham, E. B., “High-Precision Flip-Chip Process Yields E-Band Harmonic Mixers with Potential Sub-10-dB Conversion Loss,” 2006 European Microwave Conf. Digest, 2006, pp. 506–509. [16] http://www.microwavepower.com, last accessed April 29, 2009. [17] Sechi, F. N., and M. Bujatti, “Gold Vias Aid Multichip Integration,” Microwave and RF, Oct. 1994, pp. 76–82. [18] Tagore, E. R., et al., “Processing of Silvar for MIC Packaging Applications,” IEEE Trans. Electron. Packag. Manuf., Vol. 31, 2008, pp. 260–265. [19] Bugeau, J. L., et al., “Aluminum Silicon Carbide for High Performance Microwave Packages,” 1995 IEEE MTT-S Int. Symp. Digest, pp. 1575–1578. [20] Conway, D., et al., “A New Process Enables Wideband High-Power GHz Amplifiers to Deliver up to 20 W,” RF Design, February 2006, pp. 8–11. [21] http://www.macom.com, last accessed April 29, 2009. [22] http://www.triquint.com, last accessed April 29, 2009. [23] Pozar, D. M., Microwave Engineering, 3rd ed., John Wiley & Sons, 2005, pp. 565–570.

Chapter 7

Power Combiners and Dividers

7.1  Introduction We have seen earlier, in Sections 2.1 and 3.5, that microwave power devices operate at extremely high power densities, often reaching kilowatts per square millimeter in the active region, with electric fields and temperatures approaching the absolute maxima for the specific material used. The maximum usable size for a single die is limited, on one hand, by the difficulty in extracting large amounts of heat from a concentrated source and, on the other hand, by the effects of the die’s dimensions on bandwidth. In fact, as we will see in Chapter 8, the available bandwidth is often controlled by parasitic elements, such as the inductance of bond wires, which generally do not scale with the size of the die. Briefly stated, the power available from a single microwave transistor is indeed limited and especially so at higher frequencies; thus, the ability to combine with low loss the output power of several single devices is clearly a key requirement to achieve high power levels. An additional issue that favors the choice of a combined architecture is the so-called graceful degradation [1], meaning that, should some devices fail, the power degrades gradually in proportion to the number of devices that are not operating. This is achieved by ensuring isolation between the individual devices, while still combining their output power. A graceful degradation behavior can be an important factor in choosing the amplifier architecture, because, by allowing system operation after a failure, albeit at reduced performance, it effectively increases system reliability. Couplers, used either as combiners or dividers, are often of the hybrid type. That is, when properly terminated, they maintain isolation between the two signals to be combined (or generated by the division). In the simplest case of a two-way divider, the hybrid coupler is a four-port device [2]: a signal applied to the input port is divided equally between the two output ports, and is not coupled to the fourth, which is generally terminated. Conversely, the same coupler can be used as a combiner by reversing the role of the input and output ports. We speak of quadrature couplers when the two divided (or combined) signals are out of phase by 90º. As described in Section 7.2, this type of coupler, when used to combine in parallel a pair of devices, has the very desirable feature of inducing a cancellation of the devices’ input and output reflections. While quadrature hybrid couplers are the most common in microwave amplifiers, in-phase and 180º couplers are also used in several important, though maybe less common, applications. For instance, in-phase combiners are often used in radial configurations that combine a large number of devices, while 180º couplers are 115

116

Power Combiners and Dividers

used to build push-pull stages, which have the desirable characteristic of suppressing the second harmonic. The number of power-combining schemes that have been proposed through the years is larger than we can possibly hope to cover in this book: we will describe here those that are most common and those that we consider most potentially useful. We do not mean to rule out the possibility that some configurations, not featured in this chapter, might be optimal for specific applications. For instance, there may be cases in which serial power combiners offer the best solution [3, 4], and others in which space combiners, both in free space [5 – 7] or confined within a microstrip pattern [8–10], may have advantages. Short-slot Riblet waveguide couplers [11–13] are sometimes preferred for high-power, very low-loss combining. For all these special situations, we have to refer the reader to the quoted literature, since a complete treatment of all microwave couplers is outside the scope of this book. We think it may be instructive, however, to compare three types of couplers— interdigitated, branch-line, and Wilkinson—that can all be implemented in a microstrip configuration and are widely used in microwave amplifiers. They are, to some degree, interchangeable, but they differ in some important characteristics, such as bandwidth and phase performance. Thus, their comparison is of practical interest. In order to highlight the main operating differences, we have analyzed examples of these three types of couplers, all designed for the same center frequency. To maintain a common ground, all the couplers are simulated for the same substrate, and the simulation does not include the effect of discontinuities, which are inevitable in a practical implementation, but also too dependent on the details of the microstrip pattern.

7.2  Balanced Stages and Quadrature Couplers The balanced stage, introduced by Eisele, et al., [14], is the most common configuration in microwave amplifiers. As shown in Figure 7.1, it consists of two identical stages of amplification combined in parallel by two quadrature (90º) hybrid

Figure 7.1  Balanced stage. Two identical amplifier stages are combined by two quadrature couplers.

7.2  Balanced Stages and Quadrature Couplers

117

couplers. When a signal is applied to the input, the first coupler splits it into two signals of equal amplitude, offset in phase by 90°. After amplification, these are recombined in phase by the second coupler at the output. In principle, any type of 3-dB coupler could be used, provided the two couplers are identical, but what makes the paralleling by quadrature couplers special is how the reflected power is routed. Specifically, because of the 90º phase shifting in the coupler, signals reflected at the input of the amplifier stages (see dashed arrows in the figure) subtract at the input, while adding at the terminated port. Thus, if the two stages are identical, the input reflections are fully absorbed by the termination and cancel at the input port. Similarly, if a signal is injected at the output port, the output reflections of the two stages are absorbed by the termination, and no reflection is seen at the output port. In a simple and elegant way, this balanced stage configuration allows easy cascading of amplifier stages while maintaining low interstage reflections. This is particularly useful in the design of wideband or power amplifiers in which the tuning circuits are generally optimized with criteria other than minimum reflections. Beside, should one of the two stages fail, a balanced configuration would still allow the system to operate, though with reduced performance. The hybrid couplers allow the two amplifiers to operate in parallel, while remaining isolated, which is desirable to avoid oscillations. Even with perfect couplers, however, good isolation between the two stages is not to be taken for granted: it is achieved only if the input and output ports are well terminated. For instance, a strong input mismatch caused by a mismatched driver preceding the balanced pair, might degrade the isolation enough to cause circuit instability. 7.2.1  Interdigitated Couplers

The coupler most frequently used in microwave amplifiers was introduced in 1969 by Lange [15]. It is formed by two coupled, interdigitated microstrip lines that are printed on a hard substrate, typically of ceramic or fused silica. Figure 7.2 is a drawing of a typical printed pattern. The lines are folded, so to speak, with the two coupled ports located adjacent to each other. In order to suppress higher-order modes, while maintaining the propagation of the main mode, the open ends of the fingers are bridged to the same lines they are already connected to at the opposite side. These four bridges are normally implemented either by wire bonds or

Figure 7.2  Lange coupler. Layout of the microstrip pattern.

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Power Combiners and Dividers

Figure 7.3  Lange coupler. Electrical schematic.

by printed air bridges. The design of this coupler, based on interdigitated, coupled lines, is well described in the literature [16–19] and will not be covered here. Also, the electrical modeling of a Lange coupler is included in all the computer-aided design (CAD) programs developed for microstrip circuits, and this greatly facilitates its design. Electrically, the coupler is a 90º hybrid, and its schematic representation is shown in Figure 7.3. When a signal enters port 1, it is equally divided between ports 2 and 3, while the reflections are collected at port 4, which is normally terminated. Because of its microstrip construction, its small size, and the layout with adjacent output ports, the Lange coupler is particularly well suited for solid-state amplifiers, and it is the most used coupler for balanced stages. One variation of the Lange coupler is the unfolded configuration [20], as shown in Figure 7.4. When unfolded, interdigitated couplers require only two bridges instead of four. Also, because all the fingers have full length, the electromagnetic field is more uniform than in the Lange coupler, facilitating operation at higher frequencies. Often the arms of the output ports of this coupler are extended by an equal length in order to bring

Figure 7.4  Unfolded, interdigitated coupler.

7.2  Balanced Stages and Quadrature Couplers

119

Figure 7.5  Unfolded coupler with extended output ports.

the output ports in an adjacent configuration, while still maintaining the 90º phase relationship between the two output signals (see Figure 7.5). For the purpose of comparing couplers of different types, we have computed the response of a Lange coupler, which is configured as a divider and designed for the frequency range of 6–18 GHz. We have used an alumina substrate with a relative dielectric constant of 10 and a thickness of 15 mils, and a 4-finger configuration with a finger width of 1.3 mils, a gap of 1.0 mils, and a finger length of 105 mils. The coupling was adjusted to have a maximum difference of .5 dB between the output signals at the coupled and direct ports. The amplitude and phase responses are shown in Figures 7.6 and 7.7, respectively. If we assume a maximum spread of .5 dB between the two outputs, the resultant bandwidth is 6.7 GHz. We should point out that, while the unbalance in amplitude is not a very significant issue in small-signal amplifiers, as the two couplers of a balanced stage compensate for each

Figure 7.6  Lange coupler. Computed amplitude response. S21 and S31 are the magnitudes of the transmission coefficients between the input port and the coupled and direct ports, respectively.

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Power Combiners and Dividers

Figure 7.7  Lange coupler. Computed phase response. ANG [S21] and ANG [S31] are the phases of the transmission coefficients between the input port and the coupled and direct ports, respectively.

other and provide a uniform gain response for the pair, the effect is far from negligible in power amplifiers. Since a power amplifier is defined to a large extent by its saturation characteristic, having one of the two stages overdriven while the other is underdriven causes a degradation of the saturation behavior, and thus of the linear performance, for the overall amplifier. One of the most striking features of the Lange coupler, and, in general, of all coupled-line couplers, is their almost perfect quadrature response over a very broad band. This is exemplified in Figure 7.7, in which a virtually perfect 90° phase offset between the two output signals is maintained over the whole 6–18-GHz band. Thus, in this type of coupler, the operating bandwidth is determined only by its amplitude response. A much wider bandwidth can be achieved by cascading multiple couplers [21–23]. For instance, Tserng and Nelson [22] combine three single couplers, as shown in Figure 7.8. The two outer couplers are identical and rather loosely coupled (14 dB), while the center one is tightly coupled (1.5 dB). The result is a bandwidth of 2.5 octaves, with a fairly tight tolerance of the coupling over the band. The main difficulty with such a multisection approach is the very tight coupling required for the central coupler. This can be achieved, as reported in [22], by increasing the number

Figure 7.8  Broadband interdigitated coupler.

7.2  Balanced Stages and Quadrature Couplers

121

Figure 7.9  Microstrip coupled lines. Even mode.

of interdigitated fingers from four (typical for a Lange coupler) to six. This results in very narrow fingers and gaps, however, posing a challenge to the photolithographic process. Alternatively, depending on the frequency and the bandwidth, an acceptable solution might be found by increasing the thickness of the substrate and, thereby, increasing both the width and the gap of the lines. A different approach to a tight coupling is the use of vertical parallel plates [24–26], forming a distributed capacitor mounted on one edge over the substrate. The disadvantage of this approach is that the coupler becomes nonplanar and cannot be completely fabricated with photolithography techniques, with obvious consequences for cost and reproducibility. The operation of an interdigitated coupler relies on the combined propagation of even and odd modes; Figures 7.9 and 7.10 represent the electromagnetic fields of these two modes. Because of the asymmetrical configuration of the microstrip, while the even mode is mostly retained within the high-permittivity substrate, a substantial fraction of the odd-mode field propagates above the substrate (in air or vacuum), and therefore propagates at a higher velocity. The difference in the velocities of the even and odd modes affects the isolation between ports. Some improvement can be achieved by using dielectric overlays.

Figure 7.10  Microstrip coupled lines. Odd mode.

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Interdigitated microstrip couplers have many desirable features: they are small and can be fabricated cheaply and very accurately in batches using standard photolithography techniques. Their main downside, however, is their loss. In addition to the standard dielectric and conductor loss, a substantial contribution to the overall loss is caused by crowding of the RF current at the edges of the strips. This loss is very sensitive to the smoothness of the edges of the lines and, in turn, becomes very sensitive to the details of the processing. Another significant contributor to the loss is radiation. As we noted above, a substantial fraction of the odd-mode field propagates above the substrate and, therefore, is particularly prone to loss by radiation. Experience has shown, for instance, that loss of an interdigitated coupler on a 15mil alumina substrate increases rapidly above 15 GHz, and we attribute that rapid increase to radiation loss. A reduction of the radiation loss at high frequencies can be achieved by reducing the thickness of the substrate. This, of course, results in thinner lines, which in turn causes conductor losses to increase. For high-frequency operation, however, the reduction of the radiating area and the corresponding decrease in radiation loss may overcome the increase in conductor loss. This approach is followed, for instance, in commercial MMICs operating at up to 40 GHz and featuring interdigitated couplers built on 2–3-mil thick, semi-insulating GaAs substrates. 7.2.2  Branch-Line Couplers

A branch-line coupler is composed of four l /4 lines, interconnected as shown in Figure 7.11. In a 50W system, the characteristic impedances of the lines are Z1 =

Figure 7.11  Branch-line coupler. Electrical schematic.

7.2  Balanced Stages and Quadrature Couplers

123

Figure 7.12  Branch-line coupler. Typical microstrip layout.

50W and Z2 = 35.3W [27], and a typical pattern for a coupler implemented on a microstrip circuit is shown in Figure 7.12. The coupler is a quadrature hybrid. As a divider, an input signal applied to port 1 is divided equally among ports 2 and 3, and the two signals are in quadrature, while port 4 is terminated and absorbs the reflections. As a combiner, two equal-amplitude quadrature signals entering ports 2 and 3 will combine either at port 1 or at port 4, depending on their relative phase. As mentioned in Section 7.1, we find it useful to analyze the performance of a microstrip branch-line coupler designed for the same center frequency and the same microstrip substrate as the Lange coupler described in Section 7.2.1. The electrical schematic is shown in Figure 7.13. The two horizontal lines are 29-mil wide and

Figure 7.13  Example of branch-line coupler.

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Power Combiners and Dividers

Figure 7.14  Branch-line coupler. Computed amplitude response. S21 and S31 are the magnitudes of the transmission coefficients between the input port 1 and ports 2 and 3, respectively.

97-mil long, while the two vertical lines are 15-mil wide and 112-mil long. The computed amplitude and phase responses are plotted in Figures 7.14 and 7.15, respectively. The amplitude response changes by .5 dB over a frequency range of 1.8 GHz, while, over that same frequency range, the phase response remains close to the ideal 90º. Thus, using the same convention as for the Lange coupler of Figure 7.6, the bandwidth of the branch-line coupler is 1.8 GHz. To get a clean compari-

Figure 7.15  Branch-line coupler. Computed phase response. ANG[S21] and ANG[S31] are the phases of the transmission coefficients between the input port 1 and ports 2 and 3, respectively.

7.2  Balanced Stages and Quadrature Couplers

125

son between different couplers, we did not include in the electrical design the effect of the discontinuities at the four corners of the coupler. In its microstrip configuration, this type of coupler has found extensive use in narrowband power amplifiers. It has the advantage of not requiring precise photolithography, and it can be fabricated easily, even on a soft substrate. Also, since one side of the termination is grounded, it can be made to easily dissipate a large power. Its loss is rather low, even in microstrip, because the field is well contained within the substrate, and there is no strong current crowding to increase the conductor loss. Also, unlike the interdigitated coupler, which is always fabricated in microstrip, the branch-line coupler can be realized in any transmission-line medium, including waveguide. If a larger bandwidth is needed, this can be achieved by cascading a number of couplers [28]. Clearly, the larger bandwidth comes at the expense of increased loss and size; however, the size can be greatly reduced by replacing the l /4 lines with their T or p lumped-element equivalent networks, as described in Section 7.4 and in [29, 30]. So far, we have considered only a division by two (N = 2). Clearly, by cascading couplers in a treelike structure, we easily obtain a division by N = 4, 8, 16, and so forth. This type of structure, where N = 2n (n = 1, 2, 3,…), is known as a binary divider (or combiner). It is used quite often, but it does not allow enough choice on the number of ports; for instance, it rules out 12. There is then an interest in nonbinary dividers, for instance, dividers by N = 3; and in fact, branch-line couplers can be designed for a nonbinary number of ports, while still maintaining a planar structure [31, 32]. 7.2.3  Wilkinson Couplers, In-Phase and Quadrature

This coupler was proposed by Wilkinson in 1960 [33], and in various forms, it has been amply described in the literature [34– 40]. It consists of l/4 impedance transformers interconnected by isolation resistors, and it can be built with any number of output ports, including an odd number. Like the branch-line coupler, it can be realized in many transmission-line media, although practical considerations have limited its use to microstrip, stripline, and coaxial media. Its fabrication in microstrip

Figure 7.16  Wilkinson coupler. Electrical schematic.

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Power Combiners and Dividers

does not require high-precision photolithography, and even a soft substrate can be used. Also, the electromagnetic field is well contained within the substrate, so that radiation losses are low, and the coupler operates well, even at millimeter frequencies, for example, up to 40 GHz. The only substantial drawback is the relatively large size and the lack of a ground connection for the isolation resistor, which makes it difficult to achieve a high power dissipation capability. In its simplest and most used form, the number of ports is two. In this case, as shown in Figure 7.16, the coupler consists of two l /4 impedance transformers and an isolation resistor connected between the ports. In a 50W system, the 70.7W, l /4long lines transform the 50W impedance of ports 2 and 3 into two 100W impedances connected in parallel at the input port. A 100W resistor connected between the two ports provides isolation between them. Figure 7.17 is an example of microstrip layout. As a power divider, a signal entering the coupler at port 1 is equally divided between ports 2 and 3, and the two signals are equal in amplitude and phase. Also, a signal entering port 2 is divided between port 1 and the isolation resistor, and it is strongly attenuated at port 3. Thus, ports 2 and 3 are isolated. In other words, the coupler is an in-phase (0º) hybrid. Conversely, the coupler can be used as an in-phase combiner. While in this form the Wilkinson coupler doesn’t have the quadrature characteristic that is required for a balanced stage (Section 7.2), it can be converted into a quadrature hybrid by introducing a 90° phase shift. This is achieved either by extending one arm by l /4 or by adding high-pass and low-pass networks [41]. This Wilkinson coupler with a quadrature response can be then compared with the other two quadrature couplers we have already seen (Lange and branch-line couplers). The electrical schematic of the coupler we consider for this example is shown in Figure 7.18. The substrate is, again, 15-mil alumina, the two transformers are 6-mil wide and 96-mil long, and the extended arm is 15-mil wide and 96-mil long. The computed amplitude and phase performances are plotted in Figures 7.19 and 7.20, respectively. Clearly, while the amplitude response is excellent, even over the full band from 6 to 18 GHz, the phase difference between the two output signals deviates over the band from the ideal 90°. This, of course, affects the cancellation of the reflection at the input port. In the limit case of full reflections at the two output ports (either short or open circuits), the input return loss is

�

1 RL0 = 20 log sinq

Figure 7.17  Wilkinson coupler. Microstrip layout.

�



(7.1)

7.2  Balanced Stages and Quadrature Couplers

Figure 7.18  Wilkinson coupler. Electrical schematic of the quadrature configuration.

Figure 7.19  Quadrature Wilkinson coupler. Amplitude response.

127

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where q is the phase deviation from 90°. With reference to the balanced configuration of Section 7.2, if RL1 is the return loss at the input of each of the two amplifiers, the total return loss at the input of the balanced stage is

RL = RL0 + RL1

(7.2)

The same reasoning applies to the output return loss. In order to derive a value for the bandwidth, to be used in our comparison with the other couplers, we make the assumption that an acceptable phase deviation may be q £ 20° . According to (7.1), this corresponds to a return loss of



RL0 = 9.3 dB



(7.3)

which seems acceptable in practical situations. By reviewing the data in Figure 7.20, we see that the difference in phase between S21 and S31 remains within 90° ± 20° from 9.5 to 15 GHz. Thus, based on the practical though somewhat arbitrary criterion of (7.3), the bandwidth of the quadrature Wilkinson coupler is 5.5 GHz. As we have seen already for other couplers, larger bandwidths can be achieved by cascading multiple stages, as shown in the example of Figure 7.21; however, these larger bandwidth Wilkinson couplers can be implemented only for the in-phase (not the quadrature) configuration. Finally, we should mention that Wilkinson couplers can be designed also for an odd or nonbinary number of outputs [42, 43].

Figure 7.20  Quadrature Wilkinson coupler. Phase response.

7.2  Balanced Stages and Quadrature Couplers

129

Figure 7.21  Broadband Wilkinson coupler. Electrical schematic.

7.2.4  Comparison of Three Types of Microstrip Quadrature Couplers

Table 7.1 summarizes the characteristics of the three examples of quadrature couplers we have analyzed in Sections 7.2.1–7.2.3. The couplers were all designed for the same substrate (15-mil thick alumina) and for the same center frequency (11.5 GHz). If we accept a spread of .5 dB between the amplitudes of the two output signals, the bandwidth is 6.7 GHz for the Lange coupler and 1.8 GHz for the branch-line coupler. Within their bandwidth, the phase response for both couplers is very close to a perfect 90º. (Note that in Figures 7.15 and 7.20, +180 and -180 are, in fact, the same angle.) The quadrature Wilkinson has quite a different performance: the amplitude response is very uniform over a broad band and is practically identical for both output signals. What limits the bandwidth, however, is the phase and, within the practical criterion of (7.3), the usable bandwidth is 5.5 GHz. With reference to the Lange coupler, the branch-line bandwidth is 27%, and the Wilkinson is 82%. Within the validity limits of the simulations, relative bandwidths are independent of frequency; therefore, these data can be applied to different center frequencies. With regard to losses, we have seen in Section 7.2.1 that the Lange coupler is prone to radiation because the energy associated with the odd mode of propagation is not well contained within the substrate. An acceptable loss, for instance, at 40 GHz, is achieved only with a very thin substrate. In comparison, the branch-line and Wilkinson couplers are less prone to radiation, because the propagating field is well contained within the substrate, and experience shows, for instance, that on a 10-mil substrate they operate well up to 40 GHz. There are also important differences in terms of technology. The Lange coupler requires high-definition photolithography, which, in practice, is achieved only on hard substrates, such as alumina or fused silica. The pattern-definition requirements for the branch-line and the Wilkinson couplers are far less stringent. In fact, particularly for lower frequency applications, these couplers can be printed easily even on soft substrates. Table 7.1  Comparison of Quadrature Microstrip Couplers Coupler

BW

Relative BW

Pattern

Substrate

Type

GHz

 

Resolution

Type

Lange Branch-Line Quadrature Wilkinson

6.7 1.8 5.5

100% 27% 82%

High Low Low

Hard Hard or Soft Hard or Soft

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7.3  180° Couplers Hybrid couplers of 180° are used in power amplifiers when a push-pull operation is required. The advantage of the push-pull configuration, as compared with the more standard configuration of paralleling amplifier stages using quadrature or inphase couplers, is the reduced level of the second harmonic, due to a cancellation effect within the hybrid. This is particularly useful for multioctave amplifiers, where the harmonics cannot be suppressed by filtering, and by suppressing the second harmonics, the push-pull configuration may give some advantage in terms of intermodulation performance [44]. Also, its differential operation reduces the common lead current to the ground of the push-pull pair, thus reducing unwanted feedback and increasing the RF gain [45]. The 180° hybrid most frequently used in microwave amplifiers is the ring hybrid, also called the rat-race hybrid, which is depicted schematically in Figure 7.22 and is usually built on microstrip [19]. It consists of four lines arranged in a ring structure with four ports spaced at l/4 intervals. A signal entering port 1 is divided between ports 2 and 3 into two signals of equal amplitude, offset in phase by 180°. Similarly, if two signals offset by 180° are fed into ports 2 and 3, they combine at port 1, and they subtract at port 4. This port, also called the difference port, is usually terminated to provide isolation between the ports. The pattern of a ring hybrid, when printed on a microstrip substrate, covers a rather large area. As described in Section 7.4, however, the size can be greatly reduced by implementing the circuit in lumped-element form [46, 47]. Also, the operating bandwidth can be improved substantially by additional circuit-compensation techniques [48].

Figure 7.22  Ring coupler.

7.4  Lumped-Element l/4 Transformers

131

Figure 7.23  Magic T.

The ring coupler can be built in any transmission-line medium, including waveguide. In fact, in the waveguide configuration, it has found use for low-loss power combining at high frequencies up to 60 GHz [49]. Another 180° hybrid, of a completely different type, is the waveguide magic T [2, 50], which is depicted in Figure 7.23. A signal entering port 1 is equally divided into two 180° signals at ports 2 and 3. Port 4 is terminated to provide isolation. Conversely, two signals offset by 180° entering ports 2 and 3 add in power at port 1, and subtract at port 4. It is a combiner well suited for very high power signals because of the very low loss of the waveguide circuit and the possibility of using a waveguide high-power termination at the isolated port. Often it is used to combine complete high-power amplifiers, which are already equipped with input and output waveguide ports, and where the low-loss combination and the high-power handling capability are of particular importance.

7.4  Lumped-Element l/4 Transformers The operation of any transmission line can by reproduced, to any required degree of accuracy, by a cascade of series inductors and parallel capacitors, whose values are related to the characteristic impedance Z0 by



Z0 =

�

L C



(7.4)

where L and C are, respectively, the inductance and capacitance of each element. Of particular importance in the design of couplers is the lumped-element equivalent network of a l /4 transformer. Figure 7.24 shows four different configurations of lumped elements, which are all electrically equivalent to a l /4 line. Figures 7.24 (a, b) are p and T configurations, respectively. Figures 7.24 (c, d) are also p and T configurations that are derived from Figures 7.24 (a, b) by replacing each

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Power Combiners and Dividers

Figure 7.24  Four lumped-element configurations that are equivalents of a l\4 transformer.

capacitor with an inductor, and vice versa. In all cases, the reactance of the lumped element is



X = Z0

(7.5)

In practice, some or all the l/4 transformers that form the couplers described in Sections 7.2 and 7.3 can be implemented in lumped-element form. This can result in a great reduction in the physical dimensions, particularly for low-frequency applications.

7.5  Radial Combiners Radial combiners are often used when the number of ports is large, say, eight or more [51–59]. When compared to a tree of binary combiners, radial combiners typically feature a lower loss because of their compact architecture and fewer steps for impedance transformation. Also, by distributing the amplifier stages over the periphery of the combiner, the overall structure usually has better heat-dissipation characteristics than that of a binary-tree-combining structure. However, the mechanical design of a radial combiner is often more complex than that of a standard microstrip circuit. Also, the electrical design generally cannot be completely defined in terms of uniform transmission lines, and, at least for some elements of the circuit, it might require either an electromagnetic field simulator or some experiments. All radial combiners have one circuit element which distributes the electromagnetic energy in the radial direction, and this element characterizes the type of combiner. Accordingly, in Sections 7.5.1, 7.5.2, and 7.5.3, we describe combiners based on microstrip lines, radial waveguides, and conical waveguides, respectively. 7.5.1  Microstrip Lines

One of the first radially combined amplifiers was developed by Schellenberg for an X-band application [60], and it is shown in the schematic drawing of Figure 7.25. The amplifier has a combiner and a divider of identical construction. Each is composed of a coaxial transformer and a microstrip divider. As an example of an implementation, Figure 7.26 shows a 12-way microstrip divider. The 12 ports are distributed around the periphery, and isolation resistors are connected between

7.5  Radial Combiners

133

Figure 7.25  Microstrip radial combiner.

adjacent ports. Electrically, the microstrip circuit is a Wilkinson divider in which the star of isolation resistors has been replaced by a polygon of resistors. Although this polygonal configuration, compared with the star configuration, results in a nonoptimal isolation performance, it still maintains an adequate isolation between ports, and it is, comparatively, much easier to implement. The amplifier modules are distributed on the outer surface of the drum-shaped structure, and they must be cooled by circulating water, since there is no surface available for an efficient conduction cooling. An important detail in this design is how the coaxial line is connected to the radial microstrip circuit. If we want to position the coaxial line on the same side

Figure 7.26  Substrate of microstrip radial combiner.

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Power Combiners and Dividers

as the etched microstrip circuit, we have to solve the problem of connecting the ground of the coaxial line (the outer conductor) with the ground of the microstrip circuit, which is, of course, on the other side of the substrate. The connection can be implemented using via holes, but this leads often to unwanted parasitic elements that dampen the RF performance of the circuit. Here the problem is solved elegantly by reversing the ground of the coaxial line. As shown in Figure 7.25, the outer conductor of the coaxial line forms a secondary line that is set to a length of l/4, and its end is connected to the center of the microstrip divider. This balun-type structure allows the end of the outer conductor of the coaxial line to float and to develop an RF voltage, which launches the wave into the microstrip. The center conductor, instead, is connected to the ground of the microstrip circuit through one single hole in the substrate. The reversed-ground configuration greatly simplifies the mechanical as well as the electrical design of the coaxial-to-microstrip connection. 7.5.2  Radial Waveguides

A very different approach was followed by Belohoubek, et al. [61, 62]. The amplifier, shown in the schematic drawing of Figure 7.27, consists of a bottom power divider, a top power combiner, and a number of amplifier modules mounted at the periphery of a circular plate. The combiner and the divider are identical, and they are composed of a radial waveguide and a coaxial transformer. The center of the waveguide is interfaced with the transformer [63], while the edge transitions into an array of microstrip lines that, in turn, connect to the amplifier modules. It should be noted that the substrate is continuous or, in other words, the substrate of the peripheral microstrip lines also fills the central radial waveguide. In this particular application, the substrate is made of a Teflon-based Duroid material that is 10-mil thick, and thus, the height of the radial line is only 10 mil. Short coaxial lines connect the divider to the input of the amplifier modules. The top view of the combiner (Figure 7.28) shows the coaxial output, microstrip lines, and modules distributed around the circumference of the combiner. An interesting feature of this design is the transition between the microstrip line and the radial waveguide. The transition is realized by etching l /4-long radial slots at the periphery of the top wall of the radial waveguide. The slots are shorted at the far end by the metal wall of a choke. This arrangement allows the peripheral sections of the metal pattern to develop

Figure 7.27  Thin radial waveguide combiner.

7.5  Radial Combiners

135

Figure 7.28  Top view of thin radial waveguide.

an RF voltage, matching the wave into the microstrip line connected to the amplifier. Finally, isolation resistors, connected across the l /4 slots, absorb high modes of propagation and, thereby, improve port-to port isolation. As compared to the microstrip radial combiner approach of Figure 7.25, the advantage of this approach is to allow cooling by conduction, since the amplifier modules are set on a flat, though ring-shaped, surface. Also, the loss might be lower, because the field in the radial waveguide is well confined and there is no radiation, which is present instead in a microstrip circuit. There might be a substantial bandwidth limitation in this approach, however, due to the difficulty of efficiently launching a wave from the coaxial line into the very thin radial waveguide. A large improvement in heat dissipation is achieved with the configuration of Figure 7.29 [64, 65]. Here, the power modules are equipped with integral output waveguides of standard size, which radiate into a radial waveguide of the same height. The modules are fastened directly on the flat surface of the heat sink, and they are uniformly distributed around the periphery of the combiner, as shown in Figure 7.30(a). The power-divider at the input is separated from the rest of the structure and is connected to the power modules by a set of coaxial cables of identical length. It is indeed by separating the divider from the combiner that it becomes

Figure 7.29  Full-size radial waveguide combiner.

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Power Combiners and Dividers

Figure 7.30  Radial amplifier layout.

possible to construct a structure which has optimal heat-dissipation characteristics. The divider is often built with microstrip or strip-line technology, and it is typically rather small and inexpensive. Its loss is quite high when compared with the output combiner, but the impact on the overall amplifier performance is negligible if the gain of the amplifying modules is sufficiently high. On the other hand, this configuration, with modules spread over a wide area and mounted on a single wide surface, results in an excellent heat sinking for the active devices, with clear advantages in performance and reliability. In terms of electrical performance, this approach has demonstrated RF bandwidths of 15–25%. Figure 7.31 is a photograph of an amplifier of this type operating at 20 GHz. The driver feeds the power divider, which, in turn, feeds the 12 power modules located around the output combiner. The RF power, collected at the center of the combiner, is fed into the waveguide output section, which includes, at the end, a sealing window. Although not implemented in this case, the output section may include waveguide couplers to monitor forward and reflected output power. The design of these radial waveguide combiners hinges upon the ability to model a radial transmission line. The wave equation for the radial line has been solved in terms of Bessel and modified Bessel (Neumann) functions [50]. Specifically, the normalized admittance at the radius, r, for the dominant mode is expressed as follows:

Y� (r) =

j + Y� (r0 )ζ (x, y)ct(x, y) Ct(x, y) + jY� (r0 )ζ (x, y)

(7.6)

7.5  Radial Combiners

137

Figure 7.31  Photograph of a radial amplifier. Courtesy of Microwave Power Inc.

where ct and Ct are the small and large radial cotangent functions, respectively. In terms of Bessel and Neumann functions, we have

ct(x, y) =

J1 (x)N0 (y) − N1 (x)J0 (y) J0 (x)N0 (y) − N0 (x)J0 (y)



Ct(x, y) =

J1 (y)N0 (x) − N1 (y)J0 (x) J1 (x)N1 (y) − N1 (x)J1 (y)

ζ (x, y) =

J0 (x)N0 (y) − N0 (x)J0 (y) J1 (x)N1 (y) − N1 (x)J1 (y)

Also, where

(7.7)

(7.8)

(7.9)

x = kr  y = kr0  k = 2p /l J1,2 are Bessel functions and N1,2 are Neumann functions. Although the formulation of (7.6–7.9) is elegant, it is complex and cannot be easily integrated in a standard CAD program for microwave circuits. Therefore, we describe here an approach that leads to a simple simulation using available CAD programs. The radial waveguide in these radial combiners operates in the dominant mode. This mode is remarkably simple. As shown in Figure 7.32, the E field has components only in the Z direction, while the H field-lines are circles concentric with the waveguide. Both the H and E fields vary only in the direction of propagation, r, and are constant in the Z and angular directions. Also, both are orthogonal to r, and

138

Power Combiners and Dividers

Figure 7.32  Radial transmission line.

thus, the dominant mode is actually a TEM mode. Incidentally, this is why a radial waveguide operating in the dominant mode is often referred to as a radial line. In fact, as shown in Figure 7.33, this field configuration is identical to that of an ideal line, with a characteristic impedance of

377 h Z0 = √ e w



(7.10)

where 377 is the free-space impedance, e is the relative dielectric constant of the medium, and h and w are the height and width of the line, respectively.

Figure 7.33  Ideal transmission line.

7.5  Radial Combiners

139

If we apply this formula to the radial line, we then have:

377 h Z0 = √ e 2p R





(7.11)

which defines the characteristic impedance of the radial line at any radius, R. Going back to Figure 7.32, we can now envision dividing the radial line into many narrow concentric and adjacent strips, each strip being a transmission line in the radial direction, for which we assume constant characteristic impedance. Then, when all the strips are cascaded, they form the complete radial line. Since the curvature of the strip is what limits the accuracy of this approach, it is useful to define a metric. If we consider a single strip, shown as the hatched area in Figure 7.32, we define as curvature the difference between the outer and inner perimeters, relative to the inner perimeter. Namely:

Cr =

2p (R + L) − 2p R L = 2p R R



(7.12)

Thus, if we wish to section the radial line in strips of constant curvature, Cr, we have to vary L, the width of the strip, in proportion to the radius. Under the condition of constant curvature, the widths of the strips and the radii follow a geometric progression with a ratio:

(7.13)

a = 1 + Cr Then the length of the first strip is



L1 = Ra Cr

(7.14)

and the progression of the strip widths is



L1, L1 a ,L1 a 2,L1 a 3, . . .

(7.15)

Also, the progression of the strip radii is as follows:



Ra ,Ra a ,Ra a 2 ,Ra a 3, . . .

(7.16)

The average radius of the first strip is

R1 avg = Ra +

� � C L = Ra 1 + 2 2

(7.17)

and the progression of the average radii is

R1 avg,R1 avga ,R1 avga 2,R1 avga 3, . . .



(7.18)

The characteristic impedance of the first strip is

h 377 Z01 = √ e 2p R1 avg



(7.19)

140

Power Combiners and Dividers

The progression of the characteristic impedances has a ratio of 1/a, and thus, the progression is as follows:

Z01 ,

Z01 Z01 Z01 , , ,... a a2 a3



(7.20)

Finally, the equation:

an =

Rb Ra

(7.21)

links the resolution of the step-modeling, a, the number of steps, n, and the radii. In summary, the radial waveguide is modeled by a cascade of transmission lines with characteristic impedances and physical lengths described by the progressions (7.15) and (7.20), respectively, in a medium having a relative dielectric constant of e. Since the radial line is a reciprocal circuit element, in the design process the combiner is often simulated as a divider, because it is usually more convenient to simulate a circuit having a single source and multiple loads. Also, in some cases, it might be convenient to partition the radial waveguide in sectors, as shown in Figure 7.34. This can be done without introducing any additional approximation since the E and H fields have no variation in the angular direction. For a single sector, the characteristic impedances of (7.7) must then be multiplied by the factor m, or the number of peripheral ports. Partitioning the radial waveguide is convenient when, for instance, tuning circuits are associated with the loads (or the sources) and must be optimized as part of the radial line. 7.5.3  Conical Waveguides

Since radial waveguide combiners are inherently limited in bandwidth, different combiners based on coaxial TEM waveguides have been developed specifically for

Figure 7.34  Sector of radial line.

7.5  Radial Combiners

141

Figure 7.35  Conical waveguide combiner.

operation over wide bands. One approach, described in [66, 67], and shown schematically in Figure 7.35, is composed of two conical coaxial TEM waveguides terminated by an array of amplifiers that interface with the coaxial waveguide via fin-line, tapered transformers. The amplifiers, mounted on trays, are fitted on the outer surface of a drumlike body, and they are cooled by conduction. The heat is then removed by conduction through the outer shell. This combiner has demonstrated operation over a remarkably broad band, 2–20 GHz. However, because of the drum shape of the main body, good heat dissipation at high power might be difficult to achieve. Another wideband TEM-mode combiner [68] is shown schematically in Figure 7.36. The main body of the combiner is a conical line that is fed by a coaxial transformer. Multiple coaxial ports coupled to the conical line are located around the periphery of the cone. The conical line propagates the wave at a constant characteristic impedance that is defined by the angles q1 and q2, as follows [50]:



q2 2 Z0 = 60 ln q1 tan 2 tan

Figure 7.36  Conical-line combiner.

(7.22)

142

Power Combiners and Dividers

Figure 7.37  Top view of conical-line combiner.

A set of coaxial probes, distributed at the periphery of the conical waveguide, couple the energy from the conical line into the coaxial ports. A top view of the combiner, in this case with 10 coaxial ports, is shown in Figure 7.37. Regarding the electrical design of such a device, we should point out that the design parameters of the coaxial probes are not accurately defined in closed-form solutions and must be determined by analysis, using an electromagnetic field solver. However, since the characteristic impedance of the conical line is known from (7.9) and it is constant, once we have determined the impedance of the coaxial probes, the rest of the design, including the design of the coaxial transformer, can then be carried out using standard transmission-line models. The coaxial ports are spaced far apart and are easily accessible. Thus, when power modules are connected to the coaxial ports, the overall structure can be designed to operate with good heat-dissipation characteristics.

7.6  Coupler Arrays When laying out an array of couplers to combine in parallel in a number of stages, we must ensure that the divider and the combiner are complementary to each other. In other words, the phase shifts of the signals going through the branches of the combiner and the divider must be all identical, so that the signals combine in phase at the output. The simplest case is the one of a divider and a combiner with identical coupler layouts. An example is shown in Figure 7.38 for an eight-way combiner implemented with Lange couplers. If we follow the signals through the eight branches, from the input to the output, we find that all the signals go through the same phase shift and, therefore, combine properly at the output port. This verifies that the two

7.6  Coupler Arrays

143

Figure 7.38  Uniform topology power stage. The combiner and the divider arrays have the same topology.

networks (the divider and the combiner) are complementary. We should point out that the insertion of the two drivers does not affect the phase balance. While having the same coupler topology for the divider and the combiner might be convenient for practical reasons, and it does ensure complementarity, it may still not be an optimal topology for considerations of length of the RF connections or mechanical layout. For instance, Figure 7.39 shows a layout that minimizes the

Figure 7.39  Nonuniform topology power stage. The topology of the combiner is optimized for short connections.

144

Power Combiners and Dividers

length of the connections in the output combiner, which is clearly desirable for RF-loss considerations. We see that two types of couplers are used, one a mirror image of the other. Now that the combining couplers have been laid out, with the rule of minimizing the length of the interconnections, we are left with the task of devising a topology for the divider that assures complementarity. This rule, for devising complementary topologies, can be derived from the two-way combiner described in Section 7.2. From this simple case, we see that two corresponding couplers must be of the same type in order to ensure complementarity. They don’t have to be identical (in fact, they can even be built in different media), but they must have the same phase relationship between corresponding ports. This rule, that corresponding couplers must be of the same type (have the same phase relationship between corresponding ports) can be extended to a higher level. For instance, in Figure 7.39, coupler 3 must be of the same type as the corresponding coupler 5, and coupler 4 must be of the same type as 6. Also, coupler 2 must be of the same type as the corresponding coupler 7. Similarly, coupler 1 must be of the same type as coupler 8. The same rule applies to the couplers in the remaining half of the structure. Having chosen first the topology of the combiner, with this simple rule we can easily determine the topology of the divider, with the assurance that the divider and combiner are complementary. Finally, we may note that the shortening of the connection in the combiner has been achieved at the expense of a corresponding lengthening of the connections in the divider, which is still, however, a good bargain, because gain is always cheaper then power.

References   [1] Ernst, R. L., et al., “Graceful Degradation Properties of Matched N-Port Power Amplifier Combiners,” IEEE MTT-S Int. Microwave Symp. Digest, June 1977, pp. 174–177.   [2] Collin, R. E., Foundation for Microwave Engineering, McGraw-Hill, 1966, pp. 282–286.   [3] Bert, A., and D. Kaminsky, “The Travelling Wave Divider/Combiner,” IEEE Trans. on Microwave Theory and Techniques, Vol. MTT-28, No. 12, 1980, pp. 1468–1473.   [4] Cappucci, J. “Combining Amplifiers? Try Serial-Feed Array,” Microwaves, October 1976, pp. 36–41.   [5] Ender, J. H, et al., “Progress in Phased Array Radar Applications,” IEEE MTT-S Int. Microwave Symp. Digest, 2005, p. TH1E.   [6] Mallet, A., et al., “Multi-Port Amplifier Operation for Ka-Band Space Telecommunication Applications,” IEEE MTT-S Int. Microwave Symp. Digest, 2006, pp. 1518–1521.   [7] Mink, J. “Quasi-Optical Power Combining of Solid-State Millimiter-Wave Sources,” IEEE Trans. on Microwave Theory and Techniques, February 1986, Vol. 34, pp. 273–279.   [8] Abouzahra, M. D., K. C. Gupta, and A. Dumanian, “Use of Circular Sector Shaped Planar Circuits for Multiport Power Divider-Combiner Circuits,” 1988 IEEE MTT-S Int. Microwave Symp. Digest, May 1988, pp. 661–664.   [9] Kobeissi, H., and K. Wu, “Design Technique and Performance Assessment of New Multi­ port Multihole Power Divider Suitable for M(H)MICs,” IEEE Trans. on Microwave Theory and Techniques, April 1999, Vol. 47, No. 4, pp. 499–505. [10] Li, L., and K. Wu, “Integrated Planar Spatial Power Combiner,” IEEE Trans. on Microwave Theory and Techniques, April 2006, Vol. 54, pp. 1470–1476. [11] Hendrick, L. W., and R. Levy, “Design of Waveguide Narrow-Wall Short-Slot Couplers,” IEEE Trans. on Microwave Theory and Techniques, October 2000, Vol. 48, pp. 1717–1773.

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[12] Alessandri, F., et al., “A New Multiple-Tuned Six-Port Riblet-Type Directional Coupler in Rectangular Waveguide,” IEEE Trans. on Microwave Theory and Techniques, May 2003, Vol. 51, No. 5, pp. 1441–1448. [13] Lapidus, A. D., “Dual Mode Broadband Hybryds: Theory and Experiments,” Microwave Journal, November 2001, pp. 118–128. [14] Eisele, K. M., R. S. Engelbrecht, and K. Kurokawa, “Balanced Transistor Amplifiers for Precise Wideband Microwave Applications,” IEEE Int. Solid-State Circuits Conf., February, 1965, pp. 18–19. [15] Lange, J., “Interdigitated Stripline Quadrature Hybrid,” IEEE Trans. on Microwave Theory and Techniques, Vol. MIT-17, No. l2, 1969, pp. 1150–1151. [16] Bryant, T. G., and J. W. Weiss, “Parameters of Microstrip Transmission Lines and of Coupled Pairs of Microstrip Lines,” IEEE Trans. on Microwave Theory and Techniques, December 1968, Vol. 16, pp. 1021–1027. [17] Ou, W. P., “Design Equations for Interdigitated Directional Coupler,” IEEE Trans.on Microwave Theory and Techniques, February 1975, Vol. 23, pp. 253–255. [18] Paolino, D. D., “Design More Accurate Interdigitated Couplers,” Microwaves, May 1976, pp. 34–37. [19] Pozar, D. M., Microwave Engineering, New York: John Wiley & Sons, 1998. [20] Waugh, R., and D. LaCombe, “Unfolding the Lange Coupler,” IEEE Trans. on Microwave Theory and Techniques,” Vol. MTT-20, November 1972, pp. 777—779. [21] Shelton,T. P., T. F. Wolfe, and R. C. Van Wagoner, “Tandem Couplers and Phase Shifters for Multioctave Bandwidth,” Microwaves, Vol. 4, April 1965, pp. 14–19. [22] Tserng, H. Q., and S. R. Nelson, “5–18 GHz 3-dB Hybrid Coupler,” Electronics Letters, April 2, 1981, Vol. 17, No. 7, pp. 258–259. [23] Walker, J. L. B., “Analysis and Design of Kemp-Type 3-dB Quadrature Couplers,” IEEE Trans. on Microwave Theory and Techniques, March 1990, Vol. 38, pp. 88–90. [24] Konishi, Y., et al., “A Directional Coupler of a Vertically Installed Planar Circuit Structure,” IEEE Trans. on Microwave Theory and Techniques, June 1988, Vol. 36, pp. 1057– 1067. [25] Dongtien, L., “New Types of 3-dB Directional Couplers of Microstrip Transmission Lines,” 1988 IEEE MTT-S Int. Microwave Symp. Digest, pp. 265–268. [26] Chen, H. C., and C. Y. Chang, “Modified Vertically Installed Planar Couplers for Ultrabroadband Multisection Quadrature Hybrid,” IEEE Microwave and Wireless Components Letters, Vol. 16, No. 8, August 2006, pp. 446–448. [27] Grebennikov, A., RF and Microwave Power Amplifier Design, McGraw Hill, 2005. [28] Kumar, S., C. Tannous, and T. Danshin, “A Multisection Broadband Impedance Transforming Branch-Line Hybrid,” IEEE Trans. on Microwave Theory and Techniques, Vol. MTT–43, November 1995, pp. 2517–2523. [29] Chun, Y.-H., and J.-S. Hong, “Compact Wide-Band Branch-Line Hybrids,” IEEE Trans. on Microwave Theory and Techniques, February 2006, Vol. 54, No. 2, pp. 704–709. [30] Wang, J., et al., “A Compact Slow-Wave Microstrip Branch-Line Coupler with High Performance,” IEEE Microwave and Wireless Components Letters, Vol. 17, No. 7, July 2007, pp. 501–503. [31] Chao, C. L., “A New Odd Number N-Way Power Combiner/Divider,” IEEE MTT-S Int. Microwave Symp. Digest, 1977, pp. 506–508. [32] Chao, C. L., “N-Way Branch Line Directional Couplers,” IEEE MTT-S Int. Microwave Symp. Digest, 1974, pp. 93–95. [33] Wilkinson, E., “An N-Way Hybrid Power Divider,” IRE Trans. on Microwave Theory and Techniques,Vol. MTT-8, No. 1, January 1960, pp. 116–118. [34] Cohn, S. B., “A Class of Broadband Three-Port TEM-Mode Hybrids,” IEEE Trans. on Microwave Theory and Techniques, Vol. MTT-16, No. 2, pp. 110–116.

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147

[57] Swiff, G. W., and D. I. Stones, “A Comprehensive Design Technique for the Radial Wave Power Combiner,” 1988 IEEE MTT-S Int. Microwave Symp. Digest, pp. 279–281. [58] Tokumitsu, Y., “6 GHz 80W GaAs FET Amplifier with TM Mode Cavity Power Combiner,” IEEE Trans. on Microwave Theory and Techniques, Vol. MTT-32, No. 3, 1984, pp. 301–307. [59] Holme, S. C., V. E. Dunn, and V. Jamnejad, “A Compact Seven-Way Power Divider for Satellite Beam-Forming Network,” 1988 IEEE MTT-S Int. Microwave Symp. Digest, pp. 665–668. [60] Schellenberg, J. M., and M. Cohn, “A Wideband Radial Power Combiner for FET Power Amplifiers,” 1978 ISSCC Digest of Technical Papers, February 1978, pp. 164–164. [61] Belohoubek, E., “30-Way Radial Combiner for Miniature GaAsFET Power Amplifiers,” IEEE MTT-S Int. Microwave. Symp. Digest, 1986, pp. 515–518. [62] Fathy, A. E., S.-W. Lee, and D. Kalokitis, “A Simplified Design Approach for Radial Power Combiners,” IEEE Trans. on Microwave Theory and Techniques, Vol. 54, January 2007, pp. 247–255. [63] Williamson, A. G., “Radial Line/Coaxial Line Stepped Junction,” IEEE Trans. on Microwave Theory and Techniques, Vol. 55, January 1985, pp. 56–59. [64] Sechi, F. N., et al., “Radially Combined 30-W 14–16 GHz Amplifier,” 1994 IEEE MTT-S Int. Microwave Symp. Digest, May 23–27, 1994, San Diego, pp. 1737–1738. [65] Sechi, F. N., and M. Bujatti, “Broadband High Power Amplifiers for Instrumentation,” 67th AFTG Conf. Digest, San Francisco, June 16, 2006, pp. 61–67. [66] Jia, P., et al., “Multioctave Spatial Power Combining in Oversized Coaxial Waveguide,” IEEE Trans. on Microwave Theory and Techniques, May 2002, Vol. 50. pp. 1355–1360. [67] Jia, P., “A 2–20-GHz High Power Amplifier Using Spatial Power Combining Techniques,” Microwave Journal, April 2005, pp. 108–118. [68] Villiers, D., P. W. Van der Walt, and P. Meyer, “Design of a Ten-Way Conical Transmission Line Power Combiner,” IEEE Trans. on Microwave Theory and Techniques, Vol. 55, February 2007, pp. 302–308.

Chapter 8

General Power-Amplifier Design 8.1  Introduction There are many types of power amplifiers—saturated, linear, or high-efficiency, for instance—but despite their differences, they all share some common features. All high-power amplifiers operate under large signal conditions, involve thermal management issues, and require matching of very low device impedances to much higher system impedances. In this chapter, we will design an amplifier optimized for maximum output power, assuming it operates in saturation. Then, in Chapters 9, 10, and 11, we will further develop the design toward more specific applications. The design of the output matching circuit is the most critical step to obtain good power performance. Here we follow three different approaches, namely, load-pull, load-line, and nonlinear model, each starting from a different set of device data. The design of the input matching circuit, instead, is often the most critical step to obtain uniform gain over the bandwidth. Both present similar challenges, but they also differ in important ways. In Section 8.2.1, we offer guidelines for the design of broadband matching circuits. For didactical purposes, we will use GaAs FETs in chip form, rather than in packages. This is because the best broadband performance can be reached only with chip devices and also because the basic chip has a well-established equivalent circuit that can be used as a basis for some general examples of matching circuits. However, the design techniques and criteria we describe for GaAs FETs apply to bipolar transistors, MOSFETs, and LDMOS as well, both in chip and package form, without any change or any loss of accuracy. A critical aspect of the design is the stability of the overall amplifier, specifically when stages are combined in series and in parallel to achieve high gain and high power, respectively. This is particularly important, since a standard stability criterion (the K factor) often used for amplifiers is not a sufficient condition to ensure the stability of a nonlinear system such as a power amplifier.

8.2  Load-Pull Design We have already described the load-pull technique in Section 4.3.1 as part of the large-signal characterization of power devices, where the technique is often applied to verify the validity of large-signal models (see Section 4.4.1). As described in the present section, the load-pull technique is also an important tool for the design of a power amplifier, especially the output-matching network. The design starts with the characterization of the active device, where the device under test (DUT) is fitted with an input-tuning circuit and with a variable output149

150

General Power-Amplifier Design

Figure 8.1  Principle of load-pull-based design.

load circuit. The input circuit is tuned and the RF input power increased until the device is fully saturated, so that the output power does not change any more with the RF input. The output circuit is then varied to maximize the output power, while the corresponding load impedance is recorded. By repeating this process at different frequencies, we can define Zopt —the locus of output impedances resulting in optimal output power versus frequency. We then proceed to design an output-matching circuit which, connected at the output test port, closely tracks the optimal impedance, Zopt. Finally, the design is completed by simulating the overall amplifier stage, as depicted in Figure 8.1. The device, represented by its S-parameters, is loaded by the output-matching circuit previously defined, and the input-matching circuit is now optimized for uniform gain over the required bandwidth. This modular design process, which separates the input from the output network design, is simple and quite effective. We should mention that the design of the broadband matching networks, as described in Section 8.3, is independent of the load-pull technique and is fully applicable to the load-line and nonlinear modeling designs as well.

8.3  Broadband Matching Networks As we mentioned in Section 8.2, the first step in the design is the definition of the output-matching circuit. For didactical purposes, we’ll consider the very simple case shown in Figure 8.2(a), where the output port of the active device is represented by a current source with its output capacitance, and the device is partially tuned by a shunt inductor Lp. If we were to run a load-pull at that port, we would find an optimal load impedance, Zopt, of the type shown in the Smith chart of Figure 8.2(b), where F1 and F2 are the low and high ends of the band, respectively, and Fc is the center frequency. Our task now is to design a network whose impedance, ZL, closely tracks Zopt. If it’s our objective to match the curvature of Zopt, we can consider the network of Figure 8.3(a) with an inductor and a capacitor in parallel. As seen on the Smith chart of Figure 8.3(b), indeed the impedance, ZL, appears to tracks Zopt very closely. There is a major problem, though: it tracks at the wrong frequencies! This is because, for increasing frequency, ZL rotates clockwise, while Zopt rotates counterclockwise. Thus, the load is correctly matched only at the center frequency, and it’s badly mismatched everywhere else. If we were to plot the output power versus frequency, we would obtain the result exemplified in Figure 8.3(c), in which the output

8.3  Broadband Matching Networks

151

Figure 8.2  (a, b) Zopt with output inductor tuning.

power reaches the optimal value only at the center frequency and drops very low at the two extremes of the band. We must design a better network, but we quickly come to realize that the impedance versus frequency of any physically realizable network always rotates clockwise on the Smith chart. As a consequence, we cannot track curvature and frequency at the same time. With this in mind, the next step is clear: a series resonator, as seen in the schematic of Figure 8.4(a).

Figure 8.3  (a–c) Output circuit with parallel resonator.

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General Power-Amplifier Design

Figure 8.4  (a–c) Output circuit with series resonator.



The impedance plots of Figure 8.4(b) show that ZL matches Zopt at two frequencies, thus the power response, as shown in Figure 8.4(c), develops the shape typical of a double-tuned circuit. In fact, if we re-examine the circuit in Figure 8.4(a), we can clearly see the parallel and series resonators connected in a familiar way: it is a filter! Although it seems counterintuitive at first, because we are used to thinking of filters as band-limiting devices, in fact broadband matching networks must take the form of filters. We will return to this topic in a more formal way when we discuss the Bode-Fano equations in Section 8.4. For now, we will just point out that simply building filterlike structures does not ensure broadband operation: it is essential to include the device and the parasitic elements in the filter structure. As a general rule, this involves compensating capacitors with closely placed inductors (or vice versa) and making the resulting resonator a part of the filterlike matching network. As we will discuss in Section 8.4, the maximum achievable bandwidth is set by the ability to compensate the reactances near the active device, and once the bandwidth is lost, nothing can be done to retrieve it. Finally, if at all possible, the RF network should be configured so that the device can be biased without introducing unwanted parasitic effects. For instance, in the example of Figure 8.4 the shunt inductor is clearly a convenient element to bias the drain of the active device. Before we approach the design of the input circuit, let us bring to mind the very simple series-to-parallel impedance transformation, which we find often useful in setting up an initial matching network. With reference to Figure 8.5, the impedance formed by the reactance, Xs, in series with the resistance, Rs, is equivalent to the impedance formed by the reactance, Xp, in parallel with a resistance, Rp, if � � �2 � Rs (8.1) and Xp = Xs 1 + Xs

8.3  Broadband Matching Networks

153

Figure 8.5  Series-to-parallel conversion.

�

Rp = Rs 1 +

�

Xs Rs

�2 �

(8.2)

In the common case where Xs >> Rs, (8.1) and (8.2) simplify as



Xp = Xs

and Rp =

Xs2 Rs

(8.3)

We should remember, however, that the equivalency is valid only at the frequency F0 where Xs and Xp are computed, and that the impedances of the two networks will diverge as the frequency moves away from F0. Still, this transformation is often useful for an intuitive layout of the matching circuit. Let’s now assume we have designed an output circuit whose impedance, ZL, tracks Zopt within acceptable limits. The circuit will generally contain a tuning element for the output capacitance, as well as some impedance-transforming network, which will include resonators if broadband operation is required. The device can now be loaded by the output circuit, and the present task is to design the input matching. As shown in Figure 8.6(a), the input circuit of a typical FET device can be described by an inductor simulating the bond wires, connected in series with a capacitor and a resistor, which represent the gate junction. This circuit has high- and low-frequency approximations, shown in Figures 8.6(b) and 8.6(c), respectively. The dominant tuning is the one at high frequency (Figure 8.6(b)), implemented by the capacitor, C1, tuning the inductor, Lg. Using (8.3), the low-resistance Rgs is conveniently transformed into a higher resistance R1, which favors matching to the preceding circuit. Occasionally, the device might require tuning also at the low end of the band. This is shown in Figure 8.6(c), where the inductor, L2, tunes the capacitor, Cgs. Again, Rgs is transformed into a relatively high-value R2. The design now proceeds by simulating the complete stage as drawn in Figure 8.7, where the device is represented by its S-parameters or its equivalent smallsignal circuit, and the output is loaded by the output matching network (with equivalent impedance, ZL) and is now kept fixed. The task is to design an input network that provides adequate matching and uniform gain over the required bandwidth. As described above, C2 compensates the inductance, Lg, and, by and large, sets the high end of the frequency band. The resonator formed by C1 and L1 provides

154

General Power-Amplifier Design

Figure 8.6  (a–c) Input tuning.

broadband performance, and the resulting filter structure may be completed by a shunt resonator, which can be part of the driver stage. Sometimes there is need for additional tuning at the low end of the band; this is provided here by inductor L2 tuning the capacitor Cgs. This produces a peak of gain at low frequency, which might have to be dampened by introducing the resistor R2. Though, for simplicity, the circuit is described here in lumped-element form, the practical realization is often carried out using distributed elements. For instance, inductors are implemented with thin lines and series resonators with l /2 lines. The design procedure was described here for devices in chip form, which are very close to the intrinsic device and, therefore, have much more predictable impedances. Thus, we could carry out meaningful examples of matching circuits. If the device includes a package, however, which is most convenient and often adequate for narrow or medium bandwidths, the basic design process is unchanged. The only significant difference is that the load-pull and S-parameters data must be defined at

Figure 8.7  Amplifier stage.

8.4  Bode and Fano—Theoretical Limitations on Matching

155

the input and output ports of the package. With this in mind, the design procedure is quite flexible and applicable to any active device. Finally, a word of caution applies: a broadband circuit typically includes resonators, which can be completely mistuned by some of the circuit-optimization programs, if the starting point is too far off mark. Thus, it is advisable to set up the initial circuit with elements having values that have been estimated, even by very simple computations. After that, the circuit can be easily computer optimized. Otherwise, the optimization program may become locked in a local feature and miss the overall correct solution.

8.4  Bode and Fano—Theoretical Limitations on Matching The matching problem can be stated as follows: given an impedance, including at least one resistive and one reactive element, what is the limitation in matching such an impedance into a resistive load, with the only restriction that the matching network be physically realizable? Or, more specifically, how low a reflection coefficient can a matching network achieve, within a specified band, if we do not set any limit on the number of elements? The problem was first analyzed theoretically by Bode [1] for the simple but important case of a resistor shunted by a capacitor. The theoretical analysis was later expanded by Fano [2], who derived closed-form expressions for a number of special cases, including a resistor in series with an inductor. The case of a series capacitor and inductor and that of a parallel inductor and resistor can be found in [3]. Specific cases with three and four elements can also be found in [4]. The first two cases we mentioned, pictured in Figure 8.8, are most significant for our discussion, because they can be used to model the input and output impedances of an FET. As we have seen in Section 8.2.1, the series inductor and resistor of Figure 8.8(a) approximate the input impedance of a device at high frequencies, while the parallel capacitor and resistor of Figure 8.8(b) can simulate its output impedance, or more precisely, the complex conjugate of the optimum load impedance. The lossless networks shown in the two pictures are designed to match such loads into generators having purely resistive output impedances and r is the magnitude of the corresponding reflection coefficient.

Figure 8.8  (a, b) Bode-Fano networks.

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General Power-Amplifier Design

Bode and Fano’s analysis showed that, to be physically realizable (this is the only condition), the network of Figure 8.8(a) must satisfy the following equation: �∞

ln



0

pR 1 dw ≤ r (w ) L

(8.4)

and, for the case of Figure 8.8(b), �∞

ln



0

p 1 dw ≤ r (w ) RC

(8.5)

Let us now introduce a time constant t for each of the two networks: t = RC for Figure 8.8(a) and L for Figure 8.8(b). t= R Then both matching networks must satisfy the following condition: �∞

ln



0

p 1 dw ≤ r (w ) t

(8.6)

The fact that (8.6) applies to both networks is not surprising because of the duality between the two. The positive reactance (inductive) in series with a resistance transforms into a positive susceptance (capacitive) in parallel with a conductance. Since we are interested in achieving the lowest value of r within a specified bandwidth (w2 - w1), (8.6) suggests that, ideally, the contribution of the integral outside the bandwidth (w2 - w1) should be 0. Thus, just by inspection, we see that the ideal response of a matching network, as shown in Figure 8.9, is indistinguishable from that of an ideal filter. Specifically, the reflection coefficient of an ideal

Figure 8.9  Ideal matching network.

8.4  Bode and Fano—Theoretical Limitations on Matching

157

matching network (as well as that of an ideal filter) must be 1 outside the band and must remain below a maximum value, rmax, within the band. If we then make the further assumption that r is constant within the band, we have:

ln

1

rmax

≤

p (w 2 − w1 ) t

(8.7)

which tells us right away that, for a given t and rmax, the maximum bandwidth (w2 - w1) cannot exceed the value indicated by (8.7), no matter how many elements we use in the matching network. Other considerations might not be as obvious. For instance, a low reflection coefficient within the band is achieved at the expense of a large one outside the band. This is not necessarily intuitive, but we had a hint in Section 8.2.1, when we found that a broadband network requires the use of resonators, which are bound to produce large reflections outside the band. A second consideration is that t should be kept as low as possible, because, fundamentally, it is the reactive component of the load that determines the bandwidth. In practice, we can say that the bandwidth is defined by such a reactive component and the first matching elements. After that, there is no clever network design that can recover more bandwidth. By properly designing the filter, no matter how many elements we use, all we can hope to achieve is a smoother response. Let’s take, as a simple example, the input impedance of an FET as represented by the circuit of Figure 8.6(b). If we now tune the inductor with a shunt capacitor, as described in Section 8.2.1, we might be tempted to increase the inductance externally to transform, in accordance with (8.3), the series resistor into a parallel resistor of convenient value, for instance 50W. This, however, increases t and thereby decreases the available bandwidth. A better strategy is to keep the inductor as small as possible, tune it with a capacitor, and include the impedance transformation within the filter network. Another important consideration is that the bandwidth limitation is independent of the ratio between the load and the generator impedance. In fact the BodeFano problem is stated in terms of “matching an impedance into a resistive load” with no condition on the impedance ratio [2]. This seems to be in contrast with common experience. For instance, it is a common and well documented experience that high-power transistors, which, for physical reasons, operate at low-impedance levels, are more difficult to match than low-power ones, and operate over narrower bands. In other words, for solid-state devices, power and bandwidth are very closely (and inversely) linked. But this relationship, which is very real, does not derive from impedance ratios, as we might think intuitively. Its fundamental reason is a different one, and we will discuss it in Section 8.5. Finally, we should mention the important implications of (8.6) for circuit technology: when we build a circuit, the parasitic elements have a large effect on the maximum available bandwidth. This is clear, for instance, in the input tuning of an active device, where the input inductance is the key in defining the bandwidth. Once t is defined, the maximum bandwidth is defined, and (as we have already stressed a few times) no circuit design, however sophisticated, can overcome that limit. It is now clear why monolithic (MMIC) or semimonolithic (MMCC) technologies can

158

General Power-Amplifier Design

achieve very wide bandwidths, even when, as in the case of the MMIC technology, the circuit design is severely constrained in the number of tuning elements by the high value of the substrate real estate. Concerning the applicability of the Bode-Fano criteria, we should point out that, although the theory of broadband matching has been derived for lumpedelement networks, its general results apply also, without exceptions, to distributed elements. This is evident when we consider that any distributed element can be simulated, to any desired degree of precision, by a cascade of lumped elements. Finally, we should mention that the criteria we have described for band-pass networks apply to low-pass and high-pass networks as well, simply by substituting the bandwidth with the cut-off frequency, as is customary in filter theory.

8.5  Bandwidth vs. Power We mentioned in Section 8.4 that the Bode-Fano equation does not explain why, when the power of a solid-state device is increased by connecting cells in parallel, the available bandwidth is invariably decreased. The impedance ratio does not appear in (8.6) and (8.7), and, thus, it’s not a factor, and when paralleling cells, the time constant of the paralleled impedances remains unchanged. Why, then, the decrease in bandwidth? The answer comes by noting that the parasitic elements, which become part of the impedances we are trying to match, do not scale exactly with the number of cells. This will become clear in the following example. Let us consider a one-cell FET chip bonded to matching circuits, as shown in Figure 8.10(a). In this example, the device is a commercial PHEMT which is available in a one-, two-, four- and eight-cell configurations [5]. It is equipped with source vias. Thus, wire bonds are required only for the gate and the drain contacts. The bond wires are typically 25 mm (1 mil) in diameter, 0.2-mm long, and slightly looped to relieve the stress at the two ends. We’ll assume here that the average

Figure 8.10  (a, b) One- and two-cell FETs bonded into matching circuits.

8.5  Bandwidth vs. Power

159

height over the ground plane is 0.25 mm (10 mils). Clearly, the bond wires are part of the impedances we are trying to match. For simplicity and clarity of explanation, we’ll analyze here the input tuning of the FET where, as we have seen in Section 8.3, the inductance of the gate bond determines, by and large, the time constant of the load impedance. In order to compute the inductance of the gate bond, we’ll consider here the bond wire as a transmission line shorted at one end. Under this condition, the input impedance of the line is

Zsc = jZ0 tanq





where

q = 2p

x 300 , l = (mm) l f(GHz)

and x is the length of the bond. For x << l, tan q » q. Thus, the inductance per unit length of the wire is simply





L=

Z0 (nH/mm) 300

(8.8)

Now we must compute the characteristic impedance of the wire. A closed form is available for the configuration of Figure 8.11(a), and the characteristic impedance is given by [6] 4h 138 (8.9) Z0 = √ log10 d e With e = 1, h = 0.25 mm, and d = 0.025 mm, Z0 = 221W, and, from (8.8), the inductance per unit length of the wire is 0.74 nH/mm. Now comes an interesting result: let’s consider a 2-cell FET, bonded as shown in Figure 8.10(b). The two bond wires form the transmission line shown in Figure 8.11(b), and the characteristic impedance of the two wires in parallel can be approximated as [6]: ⎡ � ⎤ � �2 69 2h ⎦ 4h Z0 = √ log10 ⎣ 1+ (8.10) e d D

Figure 8.11  (a, b) One- and two-wire transmission lines.

160

General Power-Amplifier Design

In the device chosen for this example, the separation between cells is 0.192 mm. Thus D = 0.192 mm and (8.10) results in Z0 = 143W. From (8.8), the inductance of the two wires in parallel is 0.477 nH/mm; thus, the effective inductance of each wire is 0.954 nH/mm. This is almost 30% higher than the inductance of the bond wire for a single cell! Thus, everything else being the same, the time constant t is 30% higher, and according to (8.6), we lost 30% of the bandwidth just by connecting a second cell in parallel. The problem originates from the mutual inductance between the two wires, which increases the effective inductance of each wire. Clearly, if the wires were decoupled, by going from a 1- to a 2-cell configuration, both the inductance and the resistance would scale by a factor of ½. Thus the time constant—and therefore the bandwidth—would remain unchanged. It is of interest to compute the effect of a further increase in the number of paralleled cells, up to eight, for instance, since the device chosen for this example is available in an eight-cell configuration, as shown in Figure 8.12. We now have to compute the characteristic impedance of an array of wires. A simple approach is to approximate the array with a strip, as indicated in Figure 8.13. Thus the impedance can be computed from the microstrip line equations [7]



� � 8h 0.25w 60 Z0 = √ ln + w h e

for

Figure 8.12  Eight-cell FET bonded to a matching circuit.

w ≤1 h

(8.11)

8.5  Bandwidth vs. Power

161

Figure 8.13  (a, b) Wire array.

and

120p √ e



w �w � for Z0 = w ≥1 h + 1.393 + 0.667 ln + 1.444 h h

(8.12)

In our case, w = (n -1)D, where n is the number of wires, and e = 1. The results for up to eight wires (n = 8) are summarized in Table 8.1, where BWr is the bandwidth relative to a single cell, computed as

BWr =



Z0 (1) nZ0 (n)

(8.13)

and Le, the effective inductance of each wire in the wire array, is computed as

Le =



nZ0 (nH/mm) 300

(8.14)

The parameters are w = width of the array of wires, h = distance from ground, Z0 = characteristic impedance of the array, BWr = bandwidth relative to a one-cell configuration, and Le = equivalent inductance per unit length of each wire. The relative bandwidth, BWr , and the effective wire inductance, Le, are plotted in Figure 8.14 as a function of n. These data show that the inductance of a bond wire increases by a factor of 1.7 from a one-cell to an eight-cell array, while the maximum theoretical bandwidth, relative to a single cell, drops from 1.0 to 0.58.

Table 8.1  Bandwidth as a Function of the Number of Cells n 1 2 3 4 5 6 7 8

w (mm) —   0.384 0.576 0.768 0.960 1.152 1.344

w/h —   1.51 2.27 3.02 3.78 4.53 5.29

Z0 (W) 221 143 104   83   70   60   53   47

BWr 1.00 0.77 0.70 0.66 0.63 0.61 0.59 0.58

Le (nH/mm) 0.74 0.95 1.04 1.11 1.16 1.20 1.23 1.26

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General Power-Amplifier Design

Figure 8.14  Relative bandwidth and bond wire inductance versus number of wires.

This calculation was based on a particular family of devices, but the cell spacing, the wire diameter, and the position of the wire above ground are very common for most power FETs, and therefore, the results are fairly typical for most power FET configurations. Notice that Le has been computed as an average inductance, while in fact, because of the mutual coupling, the inductance is highest for the wires at the center and lowest for the wires at the edges. The resultant shift in tuning among the cells, although generally not critical in most FET applications, may be compensated for by grading the length of the bond wires, a technique that has been indeed used in power bipolar transistors. We ran this example for the input tuning of an FET because it is a clear case in which the time constant of the load is directly proportional to the inductance of the bond wire. The same effect of mutual coupling appears also at the output of the device, however, and, in more general terms, the detrimental effect of parasitics that don’t scale with the size of the device can be detected in other areas. For instance, in the above example, the sources of the FET are connected to ground by means of conductive vias that provide a connection with a very low inductance. This is clearly very beneficial, but a large part of the source inductance derives from the crowding of ground currents in the small cross section of such vias. If we consider a one- and two-cell configuration, we can intuitively see that, because of additional inductance due to the interaction between the currents spreading into the ground in the region where the two cells border, the effective source inductance for two cells is greater than ½ of the corresponding inductance for one cell. In other words, the source inductance also doesn’t scale with the number of cells, and this has a detrimental effect, if not on the bandwidth, then certainly on the gain of the device. A similar crowding effect is present also for heat dissipation, which we’ll discuss in Chapter 13. Thus, an increase in power of the device, which is generally achieved by increasing the number of paralleled cells, is obtained at the expense of bandwidth (and

8.6  Load-Line Design

163

gain). This can be avoided, in part, by using combiners. For example, if a four-cell device cannot meet the bandwidth requirement, experience has shown that it may be possible to meet the same requirement by paralleling four one-cell devices in a combiner array, as described in Chapter 7. Note that the overall impedance transformation is identical in both configurations, which clearly indicates that the impedance transformation is not at issue. Rather, as stated correctly in (8.6), it is the nature of the load impedance that sets the maximum achievable bandwidth.

8.6  Load-Line Design Let’s consider an amplifier stage operating in a class A tuned mode. A set of drain I-V characteristics for a typical FET are drawn in Figure 8.15, with a load line superimposed. The line is straight, which indicates that the voltage and current waveforms reach the peak at the same time. Thus they are in phase, and the load is seen by the device as a pure resistor. The difference between this amplifier stage and one loaded by a resistor is that this one (or, in fact, any stage we would consider for microwave amplification) has been tuned. This means that the load includes a resonant circuit formed by a capacitor and an inductor or by an equivalent set of circuit elements. Thus the operating point will ride on the straight line depicted in Figure 8.15 only if the circuit is operating at its resonant frequency. Let’s now consider the quiescent point: by definition, in a class A amplifier, the quiescent point, defined

Figure 8.15  I-V characteristics and load-line.

164

General Power-Amplifier Design

by the current Io and the voltage Vo is located at the middle point of the load line. In a tuned amplifier, where the bias is applied to the device through the inductor of the resonant circuit or through a choke (or an inductor presenting a high impedance for the RF signal and a low impedance for dc), Vo is equal to the power supply voltage. This is different from a resistor-loaded class A amplifier, in which the power supply voltage is set by the intersection of the load line with the Vd axis. The tuned configuration has an important implication on the maximum voltage seen by the device. Specifically, while in a resistor-loaded amplifier the voltage presented to the device never exceeds the power-supply voltage; in a tuned amplifier it can reach values twice as large or even greater. This can be seen by following the operating point on the load line. At point B the device is fully on, the voltage across the device is at its minimum value Vk (knee voltage), and the corresponding voltage across the load is maximum. At this point, the capacitor of the load circuit is charged at a voltage equal to Vo - Vk, or, in other words, since Vk is small, a voltage almost equal to the power-supply voltage. At point A, one-half of a period later, the device is off, the voltage across the capacitor is reversed because of the energy exchange with the inductor, the capacitor voltage adds to the power supply, and the total (now approximately twice the voltage of the power supply) appears across the device. As we mentioned above, the voltage across the output load complements the voltage across the device. When the first one is minimum, the second one is maximum, and vice versa. Thus, if we maximize the voltage and current swings of the device, in effect we maximize them also at the output load and, thereby, we maximize the output power. This clearly provides the criterion for optimizing the load line. Point A, the intersection of the load line with the Vd axis, is defined by the voltage, Vmax, which in turn is defined by the voltage breakdown of the device. Thus, point A is fixed. Now we can pivot the load line around point A and monitor point B—the intersection with the highest current device line. With a few trials, we can define the point B of the optimal load line, or the one that maximizes the product of the peak voltage by the peak current. Having defined the optimal load line, both the bias point and the resistive part of the output load are fully defined:





V0 =

Vmax + Vk 2

I0 =

Imax 2

(8.15) (8.16)



and the optimal load resistance is

RL =

V0 − Vk I0

(8.17)

Having defined the resistive part of the optimal load impedance, the next step is to find the equivalent output capacitance of the device and any other reactive element (such as the inductance of the bond wires) that must be included in the

8.6  Load-Line Design

165

design of the output matching network. We shouldn’t forget the effect of internal feedback, which causes a mutual interaction between the input and output impedances. Experience has shown that, although a power-amplifier design deals with large RF signals, the reactive parameters of the device can still be evaluated with adequate precision by using small-signal S-parameters. This approach is shown in Figure 8.16, where the device is matched at the input, and the overall circuit is analyzed as a one-port network. The active device is represented by its S-parameters or its small-signal model, which is completely equivalent. Here we choose the latter approach simply for didactical reasons, because it shows clearly the gate-to-drain capacitance, Cgd, as the internal feedback element. We mentioned that the input must be matched, and this can be done by providing an initial tentative matching. Then, by computing over a broad frequency range the impedance at the drain port, we can derive the equivalent output circuit formed by the capacitor, Co, the resistor, Ro, and the wire bond inductor, Ld. Since we are designing the circuit for optimum power, rather than the lowest output reflection, Ro is not of interest in this design, and it is replaced by RL. Now the task is to design a matching network that converts the load, typically 50W, to the optimal load resistance, RL, computed from (8.17), while compensating for Co and Ld over the operating frequency range. In practice, it is convenient to turn the issue around by making use of the reciprocity of a lossless network. We can set up the problem as the design of a network which matches to 50W the circuit composed by RL, Co, and Ld, as shown schematically in Figure 8.17. If we achieve a match to 50W at port 2, then, when port 2 is terminated on 50W, the impedance to the right of port 1 is indeed the complex conjugate of the one to the left. This load-line design procedure, although approximate, gives results that compare favorably with those obtained from large-signal simulations, as will be shown in Section 8.7. It can also be adapted to compute some approximate power contours [8]. It is important to recognize that the load-line technique can be applied only to the intrinsic device. If the device is in a package, and no information is available on the internal construction or the equivalent circuit of the package, the package parameters must be derived by modeling. Starting from a best estimate of the package and the intrinsic device, their electrical parameters can be derived by fitting the response of the network (device + package) to the measured S-parameters of the packaged device. A word of caution applies: the load-line technique can be applied only to the intrinsic device and not to the package, bond wires, or output circuit. For instance, applying the load-line technique at the terminals of a packaged device, without transferring the load impedance to the intrinsic device, produces useless results, even at a relatively low frequency, such as 2 GHz, because of the

Figure 8.16  Device output capacitance.

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General Power-Amplifier Design

Figure 8.17  Reciprocal configuration for output-matching design.

great disparity between the waveforms at the package terminals and those at the intrinsic device. The above discussion sheds some light on the relationship between the load impedance for maximum power and the complex conjugate of S22 (S22*), which, through the years, has prompted much work on the so called large-signal Sparameters. As we discussed in Section 4.3.2, there is no technical validity in a set of large-signal S-parameters, and there is no justification for the use of the largesignal S22* as the load impedance for maximum power. However, as we have seen in the load-line technique described above, when the impedances are referred to the intrinsic device, the reactance of S22* virtually coincides with the reactance of the optimal load. In other words, under this condition, the two impedances share approximately the same reactance. However, there is no connection between the real part of S22* and the real part of the optimal load impedance. It might be instructive, at this point, to apply the load-line technique to a specific problem. Let’s consider, for instance, the device TGF2022-48 (from Triquint), and let’s use it here for a stage operating from 0.8 to 4.2 GHz. This is an eight-cell PHEMT, available in chip form, which we have already encountered in Section 8.5. The linear model of a single cell is shown in Figure 8.18, and eight of these

Figure 8.18  Linear model for one of the eight cells of TGF2022-48.

8.6  Load-Line Design

167

cells are connected in parallel, as shown in Figure 8.12. We will assume a bias voltage of +10V, as suggested by the manufacturer. The manufacturer indicates that the bias current will increase with the RF drive and may reach a maximum value of 1.2A at full RF drive. For safety reasons, we will allow the current to reach 90% of the maximum value. Finally, we will assume a knee voltage (Vk in Figure 8.15) of 1V. Then, from (8.17):

RL =



10 − 1.0 = 8.3W 0.9 × 1.2

(8.18)

With reference to the procedure sketched in Figure 8.16, the device is simulated by eight of the circuits shown in Figure 8.18, connected in parallel. The initial input matching is an L-C circuit, as described in Section 8.3, tuned at the high end of the band. The bond inductance, Ld is computed, assuming a bond length of 0.4 mm. From Table 8.1, the inductance of each wire is 1.26 nH/mm; thus, the equivalent inductance of the array of bonds is

Ld =



1.26 × 0.4 = 0.06 nH 8

(8.19)

A simulation set up with the above parameters shows that the equivalent output capacitance of the device, Co, is 1.36 pF, and the equivalent output resistance, Ro, is 13W. We may note that Co is about 1.5 times the output capacitance of the equivalent circuit of Figure 8.18 (0.115 ´ 8 = 0.92 pF), which gives a measure of the substantial effect caused by the device’s internal feedback, even at relatively low frequencies. The present task is to design a network that matches to 50W the impedance formed by 8.3W in parallel with 1.36 pF, with 0.06 nH in series. To set our bearings, let’s compute the theoretical bandwidth for this load. The time constant of the load is

t = RC = 8.3 × 1.36 × 10−12 = 11.29 × 10−12 s

(8.20)

and from (8.7):

ln

1

ρmax

= 13.0, i.e.

1

ρmax

= e13

(8.21)

Thus rmax is very low, which indicates that the reflection coefficient within the bandwidth is not limited by the time constant of the load. Rather, it will be determined by the impedance transformer and, specifically, by the number of elements composing such a transformer. We first investigate a five-section l /4 transformer, of the type drawn in Figure 8.19. For simplicity, we first tune at the center frequency the 1.36-pF load capacitance with a 5.9-nH shunt inductor, so that the task is now to design a transformer matching 8.3W to 50W. Although we are going to computer-optimize the network,

168

General Power-Amplifier Design

Figure 8.19  Five-section microstrip transformer.



it is useful to start with a realistic set of parameters. Thus, we’ll divide the overall impedance ratio into five equal parts with a ratio of � 5 50 (8.22) a= = 1.43 8.3 As shown in Figure 8.19 the first l /4 section transforms 8.3W into 11.9W (8.3 ´ 1.43), the second 11.9W into 17W (11.9 ´ 1.43), and so forth. The characteristic impedance of the first section is

Z0 =



√

(8.23)

8.3 × 11.9 = 9.94W

and so forth. We’ll set the length of each section to be l /4 at the center frequency:

F0 =



√

0.8 × 4.2 = 1.83 GHz

(8.24)

We’ll assume we are building the transformer in microstrip, on a 0.25-mm (10mil) alumina substrate. Then, by using a simulation program or (8.11) and (8.12), we can derive the width and length of each section of the transformer. These results are compiled in Table 8.2, in the Flat Response column. We then computer-optimize the transformer, with the goal of limiting the reflection coefficient to a maximum value within the band. The response, shown in Figure 8.20, has approximately equal ripples and thereby approximates a Chebyshev response. The corresponding widths and lengths are compiled in Table 8.2 in the Equal Ripple Response column. Interestingly, this approach results in a substantially shorter transformer. As in any practical design, it is useful to examine different approaches. Clearly, the above microstrip transformer gives good performance: it’s easy to fabricate, and, most important, the width of the first element fits well the width of the FET

Table 8.2  Microstrip Transformer R W

Z0 W

Flat Response W L mm mm

Equal Ripple Response W L mm mm

8.30 11.90 17.00 24.00 35.00 50.00

9.94 14.20 20.20 29.00 41.80 —

2.56 1.67 1.06 0.64 0.35 —

2.36 1.57 0.96 0.61 0.35 —

Lp

6.00 (nH)

14.10 14.40 14.80 15.20 15.70 —

5.30 (nH)

9.10 10.10 11.20 11.20 10.40 —

8.6  Load-Line Design

169

Figure 8.20  Response of five-section microstrip transformer.



chip (2.42 mm). However, the total length is rather large. The obvious approach is then to investigate a similar design implemented with lumped elements. This is outlined in Figure 8.21, where each l /4 section of the transformer is replaced by an L-C circuit. As in the transmission-line case, each section of the lumped-element transformer is designed for a constant impedance ratio. The impedance transformation is controlled by the series inductance, L, while the parallel capacitance, C, compensates the equivalent parallel inductive reactance. From (8.2), we have � Rp Xs = Rs −1 (8.25) Rs If we define the impedance transformation for each section as

Rp a= = Rs



� 5

50 = 1.43 8.3

(8.26)

then

√ Xs = Rs a − 1 = Rs × 0.65

Figure 8.21  Five-section lumped-element transformer.

(8.27)

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General Power-Amplifier Design

And, from (8.27):

�

Then, from (8.26): � Xp = Xs 1 +



Xs Rs

�2

1 a −1

�

= a − 1

= Xs

(8.28)

a = Xs × 3.31 a−1

(8.29)

Thus, the series inductance and the parallel capacitance for each cell are, respectively,

Xs w0

(8.30)

1 w0 Xp

(8.31)

L=

and

C=



where w0 = 2p F0 . These data are compiled in Table 8.3 in the Flat Response columns. The computations can be simplified by noticing that, after calculating the L and C values for the first section, all the other values follow geometric progressions with ratios of a and 1/a, respectively. As in the previous case, the values of the computer-optimized network are compiled in Table 8.3 in the Equal Ripple Response column. The input reflection of this network is very similar to that of the microstrip transformer, as shown in Figure 8.20. We have already mentioned that the first element of the microstrip transformer matches the size of the FET chip well; thus, a practical solution might be to implement the initial sections with microstrip lines and then switch to lumped elements to maintain a small overall size. In fact, the lumped inductors can also be formed with thin microstrip lines, so that the complete transformer can be printed on a single substrate.

Table 8.3  Lumped-Element Transformer Rs

Xs

Flat Response Xp L

C

Equal Ripple Response L C

W

W

W

nH

pF

nH

pF

8.30 11.90 17.00 24.00 35.00 50.00

5.45 7.82 11.17 16.00 22.90 —

18.00 25.90 37.10 53.10 76.00 —

0.47 0.67 0.96 1.38 1.97

4.82 3.37 2.35 1.64 1.15 —

0.37 0.86 1.23 1.65 2.00 —

6.08 4.99 3.71 2.71 1.37 —

Lp (nH)

6.00

3.70

8.7  Large-Signal Simulation Design: Harmonic Balance

171

After the output-matching network, the design of the amplifier stage proceeds with the input side, as we have already described in Section 8.3 and represented schematically in Figure 8.7. We have already remarked that, because of the device’s internal feedback, the output impedance is affected by the input one, and vice versa. Thus, after designing the input-matching circuit, it is advisable to recompute the output equivalent capacitance and, if necessary, readjust the output-tuning circuit. Similarly, we might then need to readjust the input circuit. Typically, one or two iterations with small adjustments are sufficient to achieve a self-consistent solution.

8.7  Large-Signal Simulation Design: Harmonic Balance In Chapter 4, we described the development of nonlinear models for active devices. When these nonlinear devices are combined in a circuit, their behavior is described by a set of nonlinear integro-differential equations relating voltages and currents at the terminals of the devices. The solution is then obtained by, first, locally linearizing the nonlinear characteristics using the derivative of the function, and, second, stepping the time in small increments and solving the equations by numerical integration. As voltages and currents develop in amplitude, the nonlinear elements are linearized at different points, and the process is restarted. In order to achieve an adequate precision, often the time steps must be small. Thus, the process has to go through a large number of time steps to first exhaust the initial transient and then reach a stable solution. Even in the simplest case of a lumped-element network, if the elements—linear or nonlinear—are many, the process can be quite time consuming. But when applied to distributed elements, such as transmission lines, a full time-domain analysis of a complete microwave circuit can be so slow that it is hardly practical. The solution came from the realization that, in a typical microwave circuit, most of the elements are actually linear, and only a few clearly defined elements are nonlinear. Then, the network can be conveniently separated into three subnetworks: the first contains the relatively few nonlinear elements, the second contains all the linear elements, and a third contains the RF source and the load. Under excitation from the RF source, the first subnetwork is analyzed in the time domain. The time-varying voltages and currents at the interface with the second subnetwork are decomposed as frequency spectra by an FFT algorithm, which is in turn applied to the linear subnetwork. This subnetwork is analyzed at all the spectral frequencies, and the result is fed back into an iterative loop that runs until the system reaches a self-consistent solution. This technique, known as harmonic balance (HB), originally proposed in a practical form by Nakhla and Vlach [9], was applied by Filicori, et al., [10] to a nonlinear amplifier and developed into a circuit-analysis computer program by Rizzoli, et al., [11]. The HB is now the basis of all commercial microwave, nonlinear network-analysis programs, and it is presently the most common technique for the analysis of nonlinear microwave circuits that include distributed elements, such as transmission lines. If the nonlinear elements are few, the HB technique is very efficient, because most of the circuit is analyzed in the frequency domain, where the analysis is very efficient, even in the presence of distributed elements. An important feature of the HB technique is that the third subnetwork can be set up to include a number of

172

General Power-Amplifier Design

Figure 8.22  Simulated load-pull at (a) 0.8 GHz, (b) 2.0 GHz, and (c) 4.2 GHz.

8.8  Potential Instabilities

173

excitation sources, and thus, the system can analyze mixing effects, such as the intermodulation performance of amplifiers. Of course, the number of frequencies, including excitation, computation harmonics, and mixing products, determines the speed of the analysis process. Provided that a nonlinear model of the active device is available, a nonlinear analysis program can be used to compute the load-pull contours that, in turn, define the optimal impedance for output power. The analysis is carried out by distributing an array of load impedances over the Smith chart and computing the output power for each impedance. A surface fitted through the points describes, in a continuous form, the power as a function of the load. This surface can be intersected at different levels to determine the impedance contours for constant output power. In fact, this process mimics the actual measurement of load-pull contours. Examples of load-pull contours are shown in Figures 8.22(a), 8.22(b), and 8.22(c) [12]. They were computed for the same device and frequency range we considered earlier for the load-line technique, as described in Section 8.6. In these graphs, the optimal load impedance at each frequency is defined by the center of the set of contours, and the output power levels corresponding to each contour are listed in the right-hand column. For comparison, the complex conjugate of the output impedance we derived in Section 8.6 on the basis of load-line considerations is 8.3W, in parallel with 1.36 pF; at 2 GHz, this translates into a value of 0.62 + j0.02 relative to 50W, varying only by a very small amount over the 0.8–4.2-GHz range. Clearly, there is close agreement between the results, which lends support to both approaches. The lower agreement at 0.8 GHz is due to a convergence instability (unfortunately, a common problem) that prevented the simulation of the device at full saturation.

8.8  Potential Instabilities There are many indications of instabilities in power amplifiers, the most obvious being, of course, a stable oscillation. Sometimes the instability shows as noise or as a hysteresis effect. Sometimes it appears only within a limited range of RF input power, or as a sudden switch in the operation of the system, especially when many devices are connected in parallel. At times, an oscillation is harmless, and at other times it can be catastrophic. There are as many causes of oscillations and instabilities as there are varieties. In this section, we’ll attempt to describe the main causes and suggest possible ways to avoid the problem. 8.8.1  Low-Level Oscillations: Rollet’s k Factor



Defining the stability of a two-port network is a topic of utmost importance in electrical engineering. The most common criterion used in the design of microwave amplifiers is the k factor introduced by Rollett [13]. If a two-port network is described by its Y parameters, namely: � I1 = Y11 V1 + Y12 V2 (8.32) I2 = Y21 V1 + Y22 V2

174

General Power-Amplifier Design

the k factor is defined as



k=

2Re(Y11 + YS )Re(Y22 + YL ) − Re(Y12 Y21 ) |Y12 Y21 |

(8.33)

where Re(Y) is the real part of the admittance Y, and YS and YL are, respectively, the admittances of the source and the load. Based on the k-factor, the Rollett criterion for stability can be stated as follows:

If k > 1 the network is unconditionally stable

If k < 1 the network is potentially unstable

(8.34)

The k factor has found widespread application in the design of microwave amplifiers, and most of the computer-aided design programs have provisions for computing and displaying k together with the other network parameters, such as gain and reflections. The question is then: What if the simulation shows that k is uncomfortably close to 1, or, in fact, is less than 1? Choosing a different device is almost never a viable option in high-performance microwave-amplifier design, because the device has been already selected on the basis of key operational parameters, such as power and frequency performance. The possibility of reducing internal feedback could be explored, but in practice, taking power FETs as an example, the common source inductance is already minimized to achieve good RF performance, and the neutralization of the gate to drain capacitance often is not helpful, because it introduces additional instabilities. Thus, in practice, we might have to learn how to design a stable circuit even when k < 1. The key is to recognize that the condition k < 1 does not indicate that the network will necessarily oscillate, rather it indicates that it is potentially unstable and that there is at least one set of source and load impedances that will cause oscillations. Clearly, the solution is then to design matching circuits that present impedances safely different from those. A classic example is that of a bipolar transistor operating in common base. In this configuration, the collector-to-base capacitance introduces a positive feedback that, at high frequencies, causes the real part of the input impedance to become negative, making the stage potentially unstable. Yet, even though the circuit simulation indicates a k < 1, if the input is properly terminated, the stage is completely stable, and, in fact, this is a configuration which has found wide use. If, during a simulation, the value of k is found to be less than 1, the stage cannot be matched with the conjugate impedance, because that would result in infinite gain. The problem of designing the matching circuits can be then translated into maximizing the gain of the stage, which is defined, however, as the difference between input and output powers, rather then their ratio [14]. Alternatively, we can design for conjugate match after making the two-port network unilateral, for instance, by removing temporarily the S12 parameter. Or we may simply optimize the matching circuits for a constant and moderate gain over the operating bandwidth, while analyzing them over a wide band to detect points of high gain that might indicate potential instabilities. Whichever technique is used, experience has shown that,

8.8  Potential Instabilities

175

with proper care, completely stable circuits can be designed, even under conditions of potential instability. The above considerations pertain to the design. If the amplifier is already built, oscillations that can be traced to simple k < 1 effects are usually easy to detect, because they persist even when the RF input power is removed. The quenching of such oscillations generally requires only minor circuit modifications, perhaps as simple as the addition of absorbing elements in selected points of the circuit. These are relatively weak oscillations, which start at a low level and grow in amplitude until the onset of saturation reduces the gain and brings them to a steady-state condition. Although they clearly prevent the proper operation of the amplifier, they are seldom a cause of catastrophic failure. 8.8.2  Internal Oscillations

Let’s assume we are running a test on a multistage amplifier. The output of the amplifier is connected to a spectrum analyzer, and the RF input is swept in frequency over the operating range. The level of the RF input is low, and the sweep rate is slow, so that we can clearly see the spectral line moving across the screen. No other line is visible. We slowly increase the input power, and, in a narrow range of frequencies, we see somewhere on the screen a spurious line, which moves at a different rate and in the opposite direction relative to the main line. As the frequency sweep continues, the spurious line suddenly disappears, to appear again in a different region of the spectrum, moving now towards the main line. The operation is stable and repeats for each sweep. If we raise the input level, the spurious line gains in strength and appears over a wider frequency range. As the power is further increased, however, it suddenly switches off, and the amplifier operates correctly up to saturation. If we reduce the input power, the spur reappears. This behavior is not uncommon in amplifiers that include monolithic circuits. Using this technology, several high-gain stages can be compacted into remarkably small areas. Besides, the active devices (mostly PHEMTs) are often capable of substantial gain, even at very high frequencies, such as 40 GHz and beyond. The conditions are then ripe for high-frequency oscillations. Let’s consider, for instance, a few monolithic stages embedded into a multistage amplifier as depicted schematically in Figure 8.23. We can see that the bias line feeding the drains of the devices may provide a feedback path between cascaded stages. This can happen either because the RF signal on the bias line is not adequately bypassed or because the capacitors and the interconnecting lines form l/2 resonators that effectively couple the cascaded stages. Similar effects can appear also on the gate-bias lines, although some additional filtering is provided by the resistors that are always part of the gate-bias network. Whatever the specific reason, a particular stage may develop an oscillation, often at a low level and at a frequency that is well above the operating frequency of the circuit. For example, a 6–18-GHz circuit might, in fact, oscillate at 30 GHz. This high-frequency oscillation may not be detected at the output because of the frequency cutoff of the subsequent stages. However, when the input signal reaches a level that induces nonlinearity in some of the stages, either the carrier frequency or one of its harmonics may beat with the oscillation frequency. If any of the mixing products falls within the band, it is amplified and appears at the output. As the

176

General Power-Amplifier Design

Figure 8.23  Path for internal oscillation.

carrier frequency is swept, the spurious signal may appear to move either toward or away from it, depending on the relative position of the mixing frequencies. This process clearly requires a nonlinearity, and it will not occur at a low level. Thus, spurious signals will appear only at a sufficiently high input power. If we further increase the level, however, the gain drops due to saturation. As a result, the internal oscillation is quenched, and the spurious signals suddenly vanish. Even though they appear at a relatively high level of power, these are still lowlevel oscillations in the sense that they initiate, like those related to the k-factor, down at the noise level and grow in amplitude until they induce self-saturation. Like the k-factor oscillations, they seldom cause a device failure. 8.8.3  Parametric Oscillations

Let’s run another test. We have an amplifier driven by an RF source, and we monitor the output power and the spectrum. We start from a low RF level and see a normal swept response. As we increase the input power, while sweeping the frequency, and as the amplifier starts to saturate, we notice a number of characteristic features. We might have a sudden drop in output power, typically by 1–3 dB, within a narrow range of frequency. Outside that frequency range, the power response and spectrum are normal, but within that band of instability, the spectrum is broken into a carrier with many sidebands. Alternatively, we might see a lump of noise in some band that coalesces into a single spectral line when the input power is increased. Or we might see a power step with a hysteresis effect, but no breaking-up of the spectrum. If we increase the input power, the instability changes, but often persists even when the amplifier has reached full saturation. All these various instabilities result from parametric effects due to a nonlinear circuit element, such as the gate-to-source capacitance in an FET or the base-toemitter capacitance in a bipolar transistor, driven by a large RF signal. To gain insight into how these parametric instabilities develop, it is useful to review the basic principle of a parametric amplifier [15]: the essential elements are a nonlinear

8.8  Potential Instabilities

177

device (typically a nonlinear capacitance) and an RF circuit, including a high-Q idler resonator. The circuit is fed by a low-level signal of frequency ws, and a large RF signal (the pump) of frequency wp. If a current is allowed to flow in the idler circuit at frequency wp - ws, further frequency mixing takes place, producing power at the frequency ws. If such power exceeds that supplied by the generator at frequency ws, the nonlinear element appears to have a negative resistance at frequency ws. If we now replace the generator with a resonant circuit at frequency ws, and the equivalent resistance of the circuit is lower than the negative resistance generated by the nonlinear element, any initial thermal noise is amplified, grows in amplitude, and develops into a stable oscillation. Hence, what’s required in a circuit to develop parametric oscillations, or, more generally, instabilities of this type, are an idler high-Q circuit and a resonant circuit at frequency ws. If the input signal, which plays the role of the pump, satisfies the condition that

ωp = ωs ± ωi

(8.35)

where wi is the idler frequency, then the circuit can sustain an oscillation at frequency ws. Since the parametric process can support a very broad frequency range, including dc, there are opportunities for a circuit to have at least one high-Q resonance, often far from the operating frequency. For instance, in the balanced stage represented schematically in Figure 8.24, the gate-bias circuit, formed by the inductor, Lg, and the bypass capacitor, Cg, can, in fact, form a high-Q, relatively low-frequency resonator that can function very efficiently as an idler. All that’s needed now is

Figure 8.24  Example of a circuit prone to parametric oscillations.

178

General Power-Amplifier Design

another resonance, not necessarily of high-Q, but probably within the bandwidth, since the idler frequency is relatively low. In the configuration of Figure 8.24 this can happen, for instance, if the coupler ports do not offer 50W terminations to the matching circuits. In fact, it’s a common experience that poor isolation between the two output ports of a coupler often results in a strong tendency towards parametric oscillations: indeed, the defective isolation prevents the coupler from showing 50W impedance at its ports. In practice, this may be caused either by a high-output reflection of the driver or simply by a failure of the coupler termination resistor. The possible configurations that may lead to parametric oscillations are many, but they all share some common features. The circuit must include a highly nonlinear element, at least one high-Q resonance to circulate the idler current and one additional resonance to support the oscillation; in addition, the frequencies must satisfy (8.35), where wp is the input frequency. Thus the basic strategy to prevent parametric oscillations is to avoid high-Q resonances, even at very low or out-of-band frequencies, and to maintain the in-band matching circuits as well terminated. As opposed to the low-level oscillations we discussed earlier, which are relatively harmless, parametric oscillations are often quite dangerous for the active devices, especially the power ones, because they generally affect their bias. In FETs, for instance, the oscillation often involves the gate-bias circuit, and the resultant large voltage swing may lead to breakdown. Parametric oscillations are difficult to simulate, even when using a large-signal simulator. As we mentioned in Section 8.7, the HB algorithm is built around the concept of analyzing the circuit at the input frequencies, the harmonics, and the beat frequencies. No other frequency, and, specifically, no random oscillation frequency, is included in the simulation. Thus, the standard algorithm will find a stable solution without any indication of parametric effects, even when a parametric oscillation is in fact present. A solution to this problem was proposed by Mons [16], and it is based on an extension of the Nyquist open-loop stability criterion. The network to be analyzed is excited by an auxiliary generator, which permits the generation of Nyquist stability diagrams, while the active devices are driven by a separate, large RF signal. The Nyquist stability criterion then yields the conditions for oscillation and the oscillation frequency. Another solution includes an auxiliary generator at frequency wa [17]. The generator can be connected at different points in the circuit, and by analyzing the impedance seen at the connection point at frequency wa, it is possible to detect conditions of instability. However, as we mentioned above when reviewing the basic operation of a parametric amplifier, many interrelated parameters are at play. In this simulation, the only known parameter is the pump frequency, and even that must be swept over the band. Thus, the auxiliary frequency wa, as well as the location of the connection node, must be determined by trial. 8.8.4  Bias Oscillations

Transistors that are designed to operate at microwave frequencies will exhibit a very high gain at low frequencies. Thus, special care must be taken to isolate the inputand output-bias circuits to prevent even the smallest amount of feedback, which could still result in dangerous oscillations. In Chapter 12, we will discuss the design of bias networks. Here, we will just mention that bias oscillations can be quite

8.8  Potential Instabilities

179

dangerous. Thus, the bias circuit must provide very strong filtering over the widest possible frequency range. This normally includes a parallel combination of various capacitors. The inductances associated with the connection of the capacitors to the circuit must be kept to a minimum to prevent dangerous parallel resonances. Additional aspects of the bias circuit design are discussed in Chapter 12.

References   [1] Bode, H. W., Network Analysis and Feedback Amplifier Design, New York: Van Nostrand, 1945.   [2] Fano, R. M., “Theoretical Limitations on the Broadband Matching of Arbitrary Impedances,” J.l of the Franklin Institute, Vol. 249, No. 1, January 1950, pp. 57–83, and No. 2, February 1950, pp. 139–154.   [3] Grebennikov, A., RF and Microwave Power Amplifier Design, New York: McGraw Hill, 2005.   [4] Kerr, A. R., “Some Fundamental and Practical Limits on Broadband Matching to Capacitive Devices and the Implications for SIS Mixers Design,” IEEE Trans. on Microwave Theory and Techniques, Vol. 43, January 1995, pp. 2–13.   [5] Triquint Device Models TGF2022-6,-12,-24,-48, http://www.triquint.com, last accessed April 21, 2009.   [6] ITT, “Reference Data for Radio Engineers,” 5th ed., Howard W. Sams & Co. Inc, 1968, pp. 22.   [7] Bahl, I. J., and D. K. Trivedi, “A Designer’s Guide to Microstrip Line,” Microwaves, May 1977, pp. 174–182.   [8] Cripps, S. C., RF Power Amplifiers for Wireless Communications, Norwood, MA: Artech House, 1999.   [9] Nakhla, M. S., and J. Vlach, “A Piecewise Harmonic-Balance Technique for Determination of Periodic Response of Nonlinear Systems,” IEEE Trans. Circuits Systems, Vol. CAS-23, February 1976, pp. 85–91. [10] Filicori, F., et al., “Simulation and Design of a Microwave Class-C Amplifier Through Harmonic Analysis,” IEEE Trans. on Microwave Theory and Techniques, December 1979, Vol. 27, pp. 1043–1051. [11] Rizzoli,V., et al., “General-Purpose Harmonic Balance Analysis of Nonlinear Microwave Circuits Under Multitone Excitation,” IEEE Trans. Microwave Theory and Techniques, Vol. 36, December 1988, pp. 1650–1660. [12] Courtesy of Microwave Power Inc and Bob DeBoo. [13] Rollett, J. M., “Stability and Power Gain Invariants of Linear Two-Ports,” IRE Trans. Circuit Theory, Vol. CT-9, March 1962, pp. 29–32. [14] Kotzebue, K. L., “Microwave Amplifier Design with Potentially Unstable FETs,” IEEE Trans. on Microwave Theory and Techniques, Vol. 27, January 1979, pp. 1–3. [15] Collin, R. E., Foundation for Microwave Engineering, New York: McGraw-Hill, 1966, p. 557. [16] Mons, S., et al., “A Unified Approach for the Linear and Nonlinear Stability Analysis of Microwave Circuits Using Commercially Available Tools,” IEEE Trans. on Microwave Theory and Techniques, Vol. 47, No. 12, December 1999, pp. 2403–2409. [17] Suarez, A., et al., “Stability Analysis and Stabilization of Power Amplifiers,” IEEE Microwave Magazine, October 2006, pp. 51–65.

Chapter 9

High-Efficiency Amplifiers 9.1  Introduction In this chapter, we will analyze the parameters that affect the operating efficiency of an amplifier. Classifying amplifiers on the basis of power, efficiency, or linearity is a didactical device that allows us to isolate those parameters that are most important to achieve a specific performance, such as high power, efficiency, or linearity. It is a rather artificial classification, since most often the design objective is to achieve an optimal combination of operating characteristics, for example, power and efficiency or efficiency and linearity. In this context, we find that the standard class C mode of operation is of limited interest, because its theoretical efficiency of 100% is achieved only at zero output power, while, for instance, the overdriven class B mode described in Section 9.5 is a much more attractive alternative, because a similarly high efficiency is achieved at high output power. However, for the latter approach, the price is an increased complexity of the RF circuitry. We also find it useful to analyze in this chapter the efficiency and power performance of class A and AB amplifiers. Though they don’t reach the theoretical efficiency of 100%, they are unsurpassed for linear performance over a wide dynamic range.

9.2  Class A: Output Power and Efficiency Versus Load Line In this section, we’ll consider a tuned amplifier, such as the one sketched in Figure 9.1. The active device, shown here as an FET, is loaded at the output by a parallel resonator comprising a capacitor, C, an inductor, L, and a resistor, Rrf, which represents the resistive loading. Vd and Id are, respectively, the voltage and current at the terminals of the active device. We now consider, for the FET, the set of I-V characteristics shown in Figure 9.2. On the maximum current characteristic (Vg > 0) we have marked eleven A points, each defined by a voltage, Vn, and a current, In. Also, we assume here an RF breakdown voltage of 18V, which is 30% higher then the dc breakdown voltage shown on the I-V characteristics and is typical for this type of device. We can now draw a load line from point A to point B, with the quiescent point set on the load line at a position equidistant between A and B, as required for class A operation. Our objective now is to analyze how the output power and the efficiency vary as a function of the load line. Since the voltage breakdown is a boundary that cannot be overstepped, we will vary point A, while pivoting the load line around point B. The computations were run as a spreadsheet, and they are shown in Table 9.1.

181

182

High-Efficiency Amplifiers

Figure 9.1  Tuned amplifier with a parallel resonator as the output circuit.

The quiescent point is defined by

Vo =

Vdd + Vn 2

and

Io =

In 2



(9.1)

The corresponding dc power is

Pdc =

Vo × Io 1000



(9.2)

and the slope of the load line is

RL =

Vdd − Vn × 1000 In



(9.3)

Figure 9.2  I-V characteristics of an FET. Defined on the high-current characteristic are eleven A points, with coordinates Vn and In.

9.2  Class A: Output Power and Efficiency Versus Load Line

183

Table 9.1  Class A: Pout and Efficiency Versus Load Line Vdd(V)

In(mA)

Vn(V)

Vo(V)

Io(mA)

Pdc(W)

RL(ohm)

Vpp(V)

Pout(W)

Eff(%)

18.00 18.00 18.00 18.00 18.00 18.00 18.00 18.00 18.00 18.00 18.00

200.00 300.00 400.00 500.00 600.00 700.00 780.00 830.00 860.00 880.00 890.00

0.30 0.40 0.50 0.60 0.70 0.80 1.30 2.00 3.00 4.00 6.00

  9.15   9.20   9.25   9.30   9.35   9.40   9.65 10.00 10.50 11.00 12.00

100.00 150.00 200.00 250.00 300.00 350.00 390.00 415.00 430.00 440.00 445.00

0.92 1.38 1.85 2.33 2.81 3.29 3.76 4.15 4.52 4.84 5.34

88.50 58.70 43.80 34.80 28.80 24.60 21.40 19.30 17.40 15.90 13.50

17.70 17.60 17.50 17.40 17.30 17.20 16.70 16.00 15.00 14.00 12.00

0.44 0.66 0.88 1.09 1.30 1.51 1.63 1.66 1.61 1.54 1.34

48.40 47.80 47.30 46.80 46.30 45.70 43.30 40.00 35.70 31.80 25.00

We should mention that only in the standard class A operation, with sinusoidal waveforms, is the slope RL equal to the load resistance Rrf shown in Figure 9.1. In a more general case, the two resistances are related by the frequency components of the waveforms, as we will see in an example in Section 9.2. The peak-to-peak output voltage is

Vpp = Vdd − Vn



(9.4)

Thus, the RF output power is

and the drain efficiency is

Vpp × In 8 × 1000

(9.5)

Pout × 100 Pdc

(9.6)

Pout =



Eff =

It is interesting to examine the plots of power and efficiency versus load-line resistance that are drawn in Figure 9.3. The most striking feature is the very strong asymmetry of the efficiency, with respect to the value of load resistance corresponding

Figure 9.3  Standard class A. Output power and efficiency versus load line resistance.

184

High-Efficiency Amplifiers

to the maximum power. It is apparent from these plots that a designer will always choose a value of load resistance equal to or higher than the one corresponding to the maximum power, and the final choice will depend on the specific design objectives. For instance, in the common case in which power and efficiency are equally important, an RL of 21.4W, such that the decrease in power is proportionally the same as the increase in efficiency, might be the best choice. If efficiency is the most important parameter, an even higher RL value might be preferable. These are only qualitative considerations. Although this analysis is based on realistic I-V characteristics, it is still simplified; it neglects, for instance, circuit losses.

9.3  Class AB: Peak Voltage Versus Conduction Angle and Load Line After analyzing the operation of the device in class A, we may wonder about the implications of operating that same device in class B. To carry out this analysis, we will adopt the same I-V characteristics and RF circuit we used for class A, as shown in Figures 9.1 and 9.2, respectively. Our approach is to shift the operation from class A toward class B, by varying the conduction angle, and to analyze the response at different values of the loadline resistance. Figure 9.4 shows the device characteristics, the load line, and the quiescent point set for operation in class AB. Before we analyze the voltages and currents versus time, however, we must note that the voltage, vd, must be sinusoidal, because this is the only stable solution for the voltage across a parallel resonator. In other words, the parallel resonator presents a short circuit to all the harmonics of the current, and no voltage can develop across the resonator at any of the harmonic

Figure 9.4  Class AB operating diagram.

9.3  Class AB: Peak Voltage Versus Conduction Angle and Load Line



185

frequencies. This is a good approximation, even if the resonator is not ideal. Starting from the quiescent point at wt = 0, with increasing time, the operating point moves along the load line, and the voltage keeps the current sinusoidal. The current peaks when the operating point reaches A (wt = p /2), then decreases monotonically to zero when the operating point reaches B. Up to this point, the voltage vd has forced the current id to maintain a sinusoidal shape. Now the process must change, however, because the device cannot support a negative current. Thus, we assume that the current remains zero, while the operating point rides on the Vd axis. The voltage, vd, will then reach a peak value Vpk, and, when the voltage decreases below Vdd, the device starts conducting again, and the cycle is repeated. We should verify that the assumption on the current waveform is correct and that the clipped waveform we have postulated for the current, id, is indeed supported by the RF circuit. We can do this by considering the voltage and current spectral components: we note that the spectrum of the current includes both odd and even harmonics, while the spectrum of the voltage has no harmonics. This happens if the RF circuit is seen as a short for all the harmonics, which is indeed the case for a parallel high-Q resonator, in which the capacitor is effectively a short circuit for all of the frequencies above resonance. Thus, the current waveform is consistent with the RF circuit as long as the resonator is sufficiently selective. Since we are operating at the resonant frequency, voltage and current are in phase, and thus, the instantaneous operating point always rides on the resistive load line or on the x-axis. Incidentally, if we consider for the output circuit the dual configuration with a series resonator, then it is the current that must be sinusoidal, while the voltage may have a nonsinusoidal shape. This is, in fact, the basic configuration of a class E amplifier, as described in Section 9.5. We must note that the shapes of the waveforms—in this case, full sinusoidal for the voltage and clipped sinusoidal for the current—derive essentially from the frequency (or time) response of the RF circuit. This is contrary to an intuitive thinking that would associate the sharp clipping of the current waveforms to the pinchoff of the channel in the device. In other words, the pinchoff of the channel does, indeed, limit the current swing, but it is the frequency response of the circuit that allows the current waveform to assume its clipped shape. In fact, if the output circuit was a series resonator, the current would be sinusoidal and the voltage would be clipped. Before analyzing the circuit of Figure 9.4, it is useful to carry out a Fourier analysis of the single-clip sinusoid that describes the current, id. In order to make use of symmetry in the computation, we model the current as a cosine function, as shown in Figure 9.5. The clipping is defined between the angles a and 2p–a, and it is symmetrical with respect to the angle p. Thus the function is defined as � � cos(q ) for 0 < q < a (9.7) F(q ) = cos(a ) for a < q < 2p − a The amplitude of the fundamental is



A1 =

1 p

�2p 0

F(q )cos(q )dq =

1 ×B p



(9.8)

186

High-Efficiency Amplifiers

Figure 9.5  Single-clip cosinusoid.

Where B is the sum of the three integrals:

B=

�a

2

cos (q )dq +

2� p −a

cos(a )cos(q )dq +

a

0

�2p

cos2 (q )dq = C + D + E (9.9)

2 p −a

The first term is

C= the second term is

�

�a

1 1 q + sin(2q ) 2 4

=

0

a 1 + sin(2a ) 2 4

D = cos(a ) [sin(q )]2ap −a = −2sin(a ) cos(a ) = −sin(2a )



(9.10)

(9.11)

and the third term is equal to the first because the cosine function is symmetrical with respect to the angle p. Thus,





E=C

(9.12)

Finally, the amplitude of the fundamental is expressed by � � 1 1 A1 = a − sin(2a ) p 2

(9.13)

Similarly, the average value of the function F(q) is computed as ⎛ ⎞ �p �a �p 1 1⎝ 1 Aavg = F(q )dq = cos(q )dq + cos(a )dq ⎠ = (A + B) p p p

(9.14)

A = [sin(q )]a0 = sin(a ) and B = (p − a )cos(a )

(9.15)

0

0

a

where

9.3  Class AB: Peak Voltage Versus Conduction Angle and Load Line

187

Thus, the average value is given by



Aavg =

1 [sin(a ) + (p − a )cos(a )] p



(9.16)

Now, we can proceed to analyze the circuit as we vary both the load line and the mode of operation from class A to class B. We vary the mode of operation by varying a from p /2 to p. Note that, with this notation, a is ½ of the conduction angle. Thus, ⎧ ⎫ ⎨ p class A operation ⎬ (9.17) a= p Conduction angle = 2a ⎩ class B operation⎭ 2

We vary the load line by rotating it around a point A. The point A we choose as a pivot, defined by the coordinates Vn = 1.3V and In = 780 mA, is the same point that provided the best compromise between power and efficiency in class A. With reference to Figure 9.4, the peak-to-peak value of the current is equal to In, thus,

In = Ip (1 − cos(a ))



(9.18)

Therefore, the peak value of the current is

Ip =



by

In 1 − cos(a )



(9.19)

The current and voltage at the quiescent point, Io and Vo, respectively, are given

Io = In − Ip and Vo = Vn + RL(In − Io)



(9.20)

The intersection of the loadline with the Vd axis is defined by

Vdd = Vo + Io × RL





(9.21)

And the peak of the vd voltage, which should be monitored and compared against the breakdown voltage of the device, is given by



Vpk = 2Vo − Vn

(9.22)

The amplitude of the current fundamental is � � 1 Ip I1 = a − sin(2a ) p 2

(9.23)

and the average is

Iavg =

Ip (sin(a ) + (p − a )cos(a )) p



(9.24)

188

High-Efficiency Amplifiers

Thus the dc current is



Idc = Io + Iavg

(9.25)

while the amplitude of the voltage fundamental is

V1 = Vo − Vn



(9.26)

Pdc = Idc × Vo



(9.27)



(9.28)

The dc power is and the RF power is

Prf =

V1 × I1 2

Finally, the efficiency is

Eff =



Prf × 100 Pdc



(9.29)

Table 9.2 shows the circuit parameters computed for a, varying from p /2 to p and an RL value of 21.4W. If we assume that the maximum voltage across the device, Vpk, cannot exceed 18V, then we find, in agreement with the results of Section 9.2, that the value of a must be p. In other words, under these conditions the device must be operated in class A in order to maintain its peak voltage at 18V. The corresponding power is 1.63W, and the efficiency is 43.3%. Let’s now reduce RL so that the device can be operated in class AB. Table 9.3 lists the results for an RL of 17.5W. The peak voltage of 17.9V is reached at a value of a of 2.27 rad, which is clearly in class AB. Interestingly, the corresponding power and efficiency, 1.73W and 53.7%, are higher than those of class A, even though the peak voltage is virtually the same. Table 9.2  Class AB: Pout and Efficiency Versus a, with RL = 21.4W

RL

In

Vn

(mA) (V) (W) 21.40 780.00 1.300 a (deg)

a Ip (rad) (mA)

(mA)

Io

Vo (V)

Vdd (V)

Vpk (V)

I1 (mA)

Pdc (W)

Prf (W)

Eff. (%)

90.00 100.00 110.00 120.00 130.00 140.00 150.00 160.00 170.00 180.00

1.57 1.75 1.92 2.09 2.27 2.44 2.62 2.79 2.97 3.14

0.00 115.00 199.00 260.00 305.00 338.00 362.00 378.00 387.00 390.00

17.99 15.52 13.74 12.43 11.46 10.75 10.25 9.91 9.71 9.65

18.00 18.00 18.00 18.00 18.00 18.00 18.00 18.00 18.00 18.00

34.70 29.70 26.20 23.60 21.60 20.20 19.20 18.50 18.10 18.00

390.00 248.30 248.00 16.69 4.47 405.00 157.00 272.00 14.22 4.23 415.00 96.50 295.00 12.44 4.06 418.00 56.70 317.00 11.13 3.94 417.00 31.00 336.00 10.16 3.85 413.00 15.20 354.00 9.45 3.80 406.00 6.20 368.00 8.95 3.77 399.00 1.80 380.00 8.61 3.76 393.00 0.20 387.00 8.41 3.76 390.00 0.00 390.00 8.35 3.76

3.25 2.88 2.58 2.33 2.12 1.95 1.82 1.72 1.65 1.63

72.90 68.20 63.60 59.10 55.00 51.30 48.10 45.60 43.90 43.30

780.00 665.00 581.00 520.00 475.00 442.00 418.00 402.00 393.00 390.00

Iavg (mA)

Idc (mA)

V1 (V)

9.3  Class AB: Peak Voltage Versus Conduction Angle and Load Line

189

Table 9.3  Class AB: Pout and Efficiency Versus a, with RL=17.5W RL

a

(W) 17.5

In (mA) 780.0

Vn (V) 1.3

(deg)

(rad) (mA)

a

Ip

(mA)

(V)

(V)

(V)

Vpk

I1 (mA)

90.00 100.00 110.00 120.00 130.00 140.00 150.00 160.00 170.00 180.00

1.57 1.75 1.92 2.09 2.27 2.44 2.62 2.79 2.97 3.14

780.00 665.00 581.0 520.00 475.00 442.00 418.00 402.00 393.00 390.00

0.00 115.00 199.00 260.00 305.00 338.00 362.00 378.00 387.00 390.00

14.95 12.93 11.47 10.40 9.61 9.03 8.62 8.34 8.18 8.13

15.00 15.00 15.00 15.00 15.00 15.00 15.00 15.00 15.00 15.00

28.60 24.60 21.60 19.50 17.90 16.80 15.90 15.40 15.10 15.00

390.00 248.30 248.00 13.65 3.71 2.66 405.00 157.00 272.00 11.63 3.52 2.36 415.00 96.50 295.00 10.17 3.39 2.11 418.00 56.70 317.00 9.10 3.29 1.90 417.00 31.00 336.00 8.31 3.23 1.73 413.00 15.20 354.00 7.73 3.19 1.60 406.00 6.20 368.00 7.32 3.17 1.48 399.00 1.80 380.00 7.04 3.17 1.40 393.00 0.20 387.00 6.88 3.17 1.35 390.00 0.00 390.00 6.83 3.17 1.33

Io

Vo

Vdd

Iavg (mA)

Idc (mA)

V1 (V)

Pdc (W)

Prf (W)

Eff. (%) 71.70 66.90 62.20 57.80 53.70 50.00 46.80 44.30 42.60 42.00

To allow operation in class B, we need to decrease RL even further. Table 9.4 shows the results for an RL of 10.7W. Now a Vpk of 18V is reached for a value of a of 1.57 (p/2) rad, which defines class B operation. Note that, with respect to class AB operation, the power has decreased from 1.73W to 1.63W, while the efficiency has increased from 53.7% to 68%. So far, we have seen how the circuit responds when the conduction angle a is varied, while keeping RL constant. Let’s now see what happens when we change RL and a, so that the peak voltage remains fixed, say, at 18V. Under the condition of a constant Vpk, the voltage and current of the quiescent point can be defined as

Vo =

Vpk − Vn 2

and Io = In −

Vo − Vn RL



(9.30)

while the peak of the current is determined by

Ip = In − Io



(9.31)

Table 9.4  Class AB: Pout and Efficiency Versus a, with RL=10.7W

a

RL (W) 10.7

In (mA) 780.0

Vn (V) 1.3

(deg)

(rad) (mA)

a

Ip

(mA)

(V)

(V)

(V)

(mA)

90.00 100.00 110.00 120.00 130.00 140.00 150.00 160.00 170.00 180.00

1.57 1.75 1.92 2.09 2.27 2.44 2.62 2.79 2.97 3.14

780.00 665.00 581.00 520.00 475.00 442.00 418.00 402.00 393.00 390.00

0.00 115.00 199.00 260.00 305.00 338.00 362.00 378.00 387.00 390.00

9.65 8.41 7.52 6.86 6.38 6.03 5.77 5.60 5.50 5.47

9.60 9.60 9.60 9.60 9.60 9.60 9.60 9.60 9.60 9.60

18.00 15.50 13.70 12.40 11.50 10.80 10.20 9.90 9.70 9.60

390.00 248.30 248.00 405.00 157.00 272.00 415.00 96.50 295.00 418.00 56.70 317.00 417.00 31.00 336.00 413.00 15.20 354.00 406.00 6.20 368.00 399.00 1.80 380.00 393.00 0.20 387.00 390.00 0.00 390.00

Io

Vo

Vdd

Vpk

I1

Iavg

(mA)

Idc

(mA)

V1 (V)

Pdc (W)

Prf (W)

Eff. (%)

8.35 7.11 6.22 5.56 5.08 4.73 4.47 4.30 4.20 4.17

2.39 2.29 2.22 2.17 2.15 2.13 2.13 2.13 2.13 2.13

1.63 1.44 1.29 1.16 1.06 0.98 0.91 0.86 0.83 0.81

68.00 62.90 58.10 53.50 49.40 45.80 42.70 40.30 38.70 38.10

190

High-Efficiency Amplifiers

Since the peak of the current and the value of In are related by

Ip (1 − cos(a )) = In





(9.32)



(9.33)

we can derive the angle a as

a = cos



−1

� � In 1− Ip

The RF voltage is sinusoidal with amplitude equal to



V1 = Vo − Vn

(9.34)

while the amplitude of the current fundamental is given by � � 1 Ip I1 = a − sin(2a ) p 2

(9.35)

and the average current is



Iavg =

Ip (sin(a ) + (p − a )cos(a )) p



(9.36)

Thus the dc current is given by

Idc = Io + Iavg



(9.37)

and the corresponding dc power is

Pdc = Vo × Idc

(9.38)

The RF output power of the fundamental (no harmonics) is

Pout =

V1 × I1 2

(9.39)

and the corresponding efficiency is

Eff =

Prf Pdc

(9.40)

Finally, the RF load resistance for the fundamental is given by

Rrf =

V1 I1

(9.41)

In Table 9.5, we have selected for RL a set of values from 11 to 21.4W, which we have already found to be consistent with operations ranging from class B to class A. The output power and the efficiency for the fundamental frequency are plotted in Figure 9.6 as a function of a. We find that, under the single constraint of a maximum peak voltage, the output power in a class AB mode reaches a maximum for a = 120º, corresponding to a conduction angle of 240º (9.17). With respect to

9.3  Class AB: Peak Voltage Versus Conduction Angle and Load Line

191

Table 9.5  Class AB: Pout and Efficiency Versus RL Vpk (V) 18.0

In (mA) 780.0

Vn (V) 1.3

RL (W)

Vo (V)

Io (mA)

Ip (mA)

V1 a a (rad) (degree) (V)

I1 (mA)

Iavg (mA)

11.00 12.00 13.00 14.00 15.00 16.00 17.00 18.00 19.00 20.00 20.50 21.00 21.20 21.40

9.65 9.65 9.65 9.65 9.65 9.65 9.65 9.65 9.65 9.65 9.65 9.65 9.65 9.65

20.91 84.17 137.69 183.57 223.33 258.13 288.82 316.11 340.53 362.50 372.68 382.38 386.13 389.81

759.09 695.83 642.31 596.43 556.67 521.88 491.18 463.89 439.47 417.50 407.32 397.62 393.87 390.19

1.60 1.69 1.79 1.88 1.98 2.09 2.20 2.32 2.46 2.62 2.73 2.86 2.94 3.10

392.85 401.37 408.14 413.21 416.60 418.29 418.23 416.29 412.27 405.76 401.33 395.84 393.22 390.18

231.26 252.17 181.03 265.20 140.32 278.02 107.13 290.70 79.99 303.32 57.82 315.95 39.84 328.66 25.45 341.56 14.25 354.78 6.03 368.53 3.04 375.73 0.90 383.28 0.33 386.46 0.00 389.82

91.58 96.95 102.38 107.93 113.65 119.64 126.02 132.96 140.79 150.26 156.20 164.09 168.63 177.49

8.35 8.35 8.35 8.35 8.35 8.35 8.35 8.35 8.35 8.35 8.35 8.35 8.35 8.35

Idc (mA)

Pdc (W)

Pout (W)

Eff (%)

Rrf (W)

2.43 2.56 2.68 2.81 2.93 3.05 3.17 3.30 3.42 3.56 3.63 3.70 3.73 3.76

1.64 1.68 1.70 1.73 1.74 1.75 1.75 1.74 1.72 1.69 1.68 1.65 1.64 1.63

67.40 65.48 63.51 61.50 59.42 57.28 55.05 52.73 50.27 47.63 46.21 44.68 44.02 43.30

21.25 20.80 20.46 20.21 20.04 19.96 19.97 20.06 20.25 20.58 20.81 21.09 21.23 21.40

class A, the additional power is not large—only about 0.3 dB—but it is significant, because in shifting the operation to class AB, we also achieve a substantial improvement in efficiency. This results in a lower junction temperature for the active device and, therefore, a further increase in output power. Thus, in practice, the advantage may be substantially higher then the 0.3 dB shown in the plot. Another interesting result is that, while the load-line resistance, RL, varies by almost a factor of 2 when going from class A to class B, the load RF resistance, Rrf, remains virtually constant. We can understand this intuitively by noticing that the conduction angle effectively varies the average resistance seen by the RF circuit over a full cycle. Thus, in class A (conduction angle = 360º) Rrf is equal to RL. As the operation is shifted towards class B, and RL is decreased to maintain the peak voltage constant, RL is integrated through a decreasing conduction angle and is seen by the RF circuit as an increased resistance. The net result is that Rrf (the resistance seen by the RF circuit) remains practically constant. This has an important

Figure 9.6  Class AB. Output power and efficiency at constant peak voltage.

192

High-Efficiency Amplifiers

implication: the amplifier stage can be designed as a class A amplifier, even if the final mode of operation is class AB or class B. This ensures that the peak voltage remains at a constant value, which is a main requirement for proper operation of GaAs FETs. It is reassuring to find that the operation detailed in Table 9.5 conforms to the practical experience of working with GaAs FETs and MMICs. When experimentally tuning a device for maximum output power, often the initial mode of operation is class A. Then, while keeping the drain-bias voltage constant, the gate bias is usually readjusted (as predicted by the analysis above) to optimize the output power, which typically shifts the operation to a class AB mode in accordance with the data of Figure 9.6. However, despite this mode change and the implicit change in load line, usually no improvement is obtained by retuning the RF circuit. Although surprising at first, the above analysis shows that it is, in fact, a direct consequence of the peakvoltage limitation of the device.

9.4  Overdriven Amplifiers We have seen in Section 9.3 that the characteristics of the RF circuit determine the voltage and current waveforms. The parallel resonator output circuit allows the clipped current waveforms that define the operation of classes B and AB. Clearly, if we were to employ different circuits, the waveforms would be different. The question is then: What if we design circuits that support square waves? Intuitively, we expect this approach to lead to a class of circuits that operate with high efficiency. This is, in fact, the approach taken by Snider in his 1967 paper [1] in which he analyzes the response of devices that are overdriven—therefore approaching the behavior of a switch—and loaded with circuits having prescribed responses at the fundamental as well as the harmonic frequencies. In Sections 9.41 to 9.44, we’ll analyze overdriven class A and class B amplifiers. The main assumptions we make in this analysis is that (1) the device is an ideal switch; (2) the current is limited only by the load line (not by the saturation of the device); and (3) the switching time is zero. Of course, this is not quite realistic (we’ll come back to this topic in Section 9.6), but at this point, by assuming that the device is ideal, we can better define the characteristics of the RF circuitry. 9.4.l  Class B: Optimal Efficiency and Class F

We’ll assume now that the current and voltage waveforms are as shown in Figure 9.7. For consistency with the rest of this chapter, we’ll use the nomenclature of an FET, but the nature of the active device is not relevant. The operation is in class B— defined by a conduction angle of p —and the current waveform is half-sinusoidal, as expected for class B operation. Differing from the classic class B, however, the voltage is a symmetrically clipped sinusoid where the degree of clipping is defined by the angle q1. If q1 is equal to p, the voltage is unclipped, and if it is zero, it becomes a square waveform. The mode of operation with a square waveform is often named class F [2]. We now define an overdrive factor, K, as the amplitude ratio between the unclipped and the clipped sinusoids. Thus K is related to q1 by

9.4  Overdriven Amplifiers

193

Figure 9.7  Voltage and current waveforms. Optimal efficiency case.



K=

1 sin q1

(9.42)

Now, we analyze the waveforms in terms of a Fourier expansion, where the subscript A denotes cosine terms, while the subscript B denotes sine terms, and n denotes the harmonic number. Then, the cosine components of the current are as follows ⎫ ⎧ � � 1 Is 1 ⎪ ⎪ ⎨ for n even⎬ + Is (9.43) DC component: IA0 = and IAn = p 1 + n 1 − n ⎪ ⎪ p ⎭ ⎩ 0 for n odd while the sine components of the current are

IB1 =



Is 2

and

IBn = 0



(9.44)

In other words, the current waveform has a dc component and only even harmonics, and the amplitude of the fundamental is ½ of the peak value. The har­ monics are all cosine terms, while the fundamental is a sine term. Similarly, the cosine terms of the voltage waveform are

DC component: VA0 = Vdd

and VAn = 0 for n �= 0



(9.45)

while the sine terms are

VB1 =

Vdd [2Kq1 − K sin 2q1 + 4 cos q1 ] p



(9.46)

where VB1 is the amplitude of the fundamental, and the amplitudes of the harmonics are

Vdd [2Knq1 − 2K sin(q1 + nq1) + 4 cos nq1 ] for n odd p = 0 for n even

VBn = VBn

Thus, the voltage waveform has a dc component and only odd harmonics.

(9.47)

194

High-Efficiency Amplifiers

The obvious question is: What type of circuit would produce these waveforms? The answer comes from analyzing the response of the circuit in the frequency domain. Clearly, the impedance of the circuit is defined by the ratio of the voltage and the current. Thus, the impedance for the fundamental is

Z1 =



VB1 8 Vdd = IB1 p Is

(9.48)

and the impedance for the harmonics is

Zn =



0 IAn

= 0 for n even

and Zn =

VBn = ∞ for n odd 0

(9.49)

Therefore, in order to produce the waveforms we have stipulated, the output circuit should present to the fundamental the resistive loading defined by (9.48), while acting as a short circuit for the even harmonics and an open circuit for the odd harmonics. It’s interesting to analyze the response of this circuit when we vary the overdrive. The data is shown in Table 9.6. The angle q1, given in the table in both degrees and radians, defines the overdrive, as shown in Figure 9.7. (In the table, q1 = 0 is actually set to q1 = 0.001º to avoid the divide-by-zero computational error.) K is related to q1 by (9.42) and K(dB)= 20 logK



D defines the amplitude of the fundamental component as a function of q1:

D = 2Kq1 − 2 sin 2q1 + 4 cos q1



(9.50)

Table 9.6  Overdriven Class B: Optimal Efficiency Case q1 degree

q1 rad

K dB

K

D

P1/Pa

Eff. %

P1/Pa (dB)

Z1r

AM/AM Compr

0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 50.00 55.00 60.00 65.00 70.00 75.00 80.00 85.00 90.00

0.00 0.09 0.17 0.26 0.35 0.44 0.52 0.61 0.70 0.79 0.87 0.96 1.05 1.13 1.22 1.31 1.40 1.48 1.57

95.16 21.19 15.21 11.74 9.32 7.48 6.02 4.83 3.84 3.01 2.31 1.73 1.25 0.85 0.54 0.30 0.13 0.03 0.00

57295.78 11.47 5.76 3.86 2.92 2.37 2.00 1.74 1.56 1.41 1.31 1.22 1.15 1.10 1.06 1.04 1.02 1.00 1.00

4.00 3.99 3.98 3.95 3.92 3.88 3.83 3.77 3.70 3.64 3.56 3.49 3.42 3.35 3.28 3.23 3.18 3.15 3.14

2.55 2.54 2.53 2.52 2.50 2.47 2.44 2.40 2.36 2.31 2.27 2.22 2.18 2.13 2.09 2.05 2.03 2.01 2.00

100.00 99.87 99.50 98.87 98.01 96.94 95.66 94.21 92.61 90.89 89.10 87.27 85.46 83.72 82.11 80.70 79.57 78.82 78.54

4.06 4.05 4.04 4.01 3.97 3.92 3.87 3.80 3.73 3.64 3.56 3.47 3.38 3.29 3.20 3.13 3.07 3.03 3.01

2.55 2.54 2.53 2.52 2.50 2.47 2.44 2.40 2.36 2.31 2.27 2.22 2.18 2.13 2.09 2.05 2.03 2.01 2.00

0.00 0.00 0.01 0.02 0.03 0.04 0.06 0.08 0.10 0.12 0.15 0.19 0.23 0.27 0.31 0.36 0.41 0.46 0.50

94.11 20.15 14.18 10.74 8.36 6.57 5.16 4.04 3.12 2.38 1.77 1.27 0.88 0.58 0.35 0.18 0.08 0.02 0.00

9.4  Overdriven Amplifiers

195

The power, P1, (the output power at the fundamental frequency) is computed as

P1 =

Vdd Is ×D 4p

(9.51)

In order to remove from this equation the bias parameters, we will express P1 in terms of the output power in a class A mode, which is defined as

Vdd Is 8

(9.52)

2 P1 = × D PA p

(9.53)

PA =

Thus:

From Equation 9.42 we derive the dc power as

Pdc =

Vdd Is p

(9.54)

Thus, the output efficiency is computed as

Eff =

P1 D = Pdc 4



(9.55)

The RF impedance at the fundamental is computed as the ratio of the amplitudes of the voltage and current components:

Z1 =

VB1 Vdd 2D = IB1 Is p

(9.56)

and again, in order to eliminate from the equation the bias parameters, we define Z1 as

Z1 = ZA × Z1r

(9.57)

Vdd where ZA = is the RF impedance in the class A mode of operation. Thus Is 2D r Z1 = is the RF load impedance relative to the class A mode. p The AM-to-AM conversion, which we have already discussed in Section 4.3.2, is defined as the ratio between the increment in output power and the corresponding increment in the unsaturated power, both expressed in decibels (dB). In our case, K is the amplitude ratio between the unsaturated (sinusoidal) and the saturated (clipped) waveforms. Since the level of the clipping is constant, K becomes a measure of the unsaturated waveform. For instance, if we look in Table 9.6 at the K(dB) column, starting from the bottom (K = 0 dB), when K increases to 1.25 dB, the output power increases from 3.01 to 3.38 dB. Which we can rephrase as the following: when we increase the drive by 1.25 dB, the output power increases by 0.37 dB. Thus, we can express the AM/AM conversion as P1 (dB) PA AM/AM = DK(dB) D



(9.58)

196



High-Efficiency Amplifiers

Another parameter that is often of interest in power amplifiers is the 1-dB compression, also discussed in Section 4.3.2. In general terms, a compression parameter measures the cumulative change between the unsaturated and the saturated output power (clipped waveform), starting from zero saturation (K = 0 dB). Thus, we compute the compression parameter, expressed in decibels, as: � � � � P1 P1 (dB) Compr = K(dB) − − (9.59) PA PA K = 0 dB Note that the compression is a cumulative measure, which starts from K = 0 dB, while the AM/AM is an incremental measure around a specific point. It is useful to plot some of these parameters. Figure 9.8 shows the efficiency and the output power (relative to the class A power) as functions of the overdrive. At 90º, there is no overdrive, the voltage waveform is sinusoidal, the efficiency is 78.5%, and the power is twice that of a class A amplifier, all of which coincides with the standard class B operation. As the operation is shifted toward overdrive and clipped waveform, both efficiency and power increase, reaching a maximum of 100% and 2.55, respectively, at q1 = 0 (square waveform). This result is remarkable because the high efficiency is obtained together with high output power, which makes this mode of operation much preferable to the standard class C mode, where the limit of 100% efficiency is obtained at zero output power. What is required, however, is a control of the harmonics, and specifically, the output load must present a short to the even harmonics and an open to the odd harmonics. We should also mention that the output power increases with decreasing q1, not because of an increase in the harmonics’ power, which in fact is not collected, but rather because the amplitude of the fundamental increases as the waveform approaches a square wave. This is shown schematically in Figure 9.9, where the fundamental is plotted for q1 = p (Figure 9.9(a)), q1 =  45 (Figure 9.9(b)) and q1 =  0 (Figure 9.9(c)). Figure 9.10 is a plot of the compression characteristic. For instance, at 1-dB compression, the output power is 3.4-dB higher than the class A power. Notice that, within the assumptions of this analysis, and specifically the assumption of an ideal device, the compression derives from the clipping of the waveforms, not the saturation of the device.

Figure 9.8  Efficiency and output power. Optimal efficiency case.

9.4  Overdriven Amplifiers

197

Figure 9.9  (a–c) Amplitude of the fundamental as a function of the overdrive angle.

The AM/AM conversion is shown in Figure 9.11. Even at the onset of the over­ drive (K = 0 dB) an increase in overdrive by a small amount, say, 0.1 dB, corresponds to an increase in output power of only half that much, and this fraction decreases rapidly as the overdrive (K) increases. We’ll see, in Section 9.4.2, that different modes of operation may have a more desirable AM/AM characteristic. Finally, we may note that the RF load resistance varies with overdrive from a value of 2 times the class A load resistance (consistent with sinusoidal class B operation) to a value of 2.55 for square-wave operation (class F). 9.4.2  Class B: Optimal Power

Let’s now assume the set of waveforms depicted in Figure 9.12. As compared to those of Figure 9.7, the voltage waveform is unchanged, but the current is a sinusoid of amplitude KIs clipped at a value Is. Many of the operating parameters are the same as in the optimal efficiency case, while others are derived in a similar fashion. Specifically, the Fourier components of the current are as follows:

Is ×E p

(9.60)

p − 2q1 + K − K cos q1 2

(9.61)

Idc =

where E is defined as:

E=

Figure 9.10  Output power compression. Optimal efficiency case.

198

High-Efficiency Amplifiers

Figure 9.11  AM/AM conversion. Optimal efficiency case.



The A components of the current are � � 0 for n odd IAn = f (K, q1 ) for n even

(9.62)

The function f(K, q1 ) could be evaluated, but it’s not required because the voltage waveform does not contain A components. The B components are

IBn =

Is [2Knq1 − 2K sin(q1 + nq1 ) + 4 cos nq1 ] for n odd 2p

(9.63)

and, therefore, the amplitude of the fundamental component is

IB1 =

Is × D 2p

(9.64)

where D is defined in (9.50). The voltage waveform is the same as that of the optimal efficiency case, and thus its components are defined in (9.45), (9.46), and (9.47). The output power is then

P1 =

Vdd Is × D2 4p 2

Figure 9.12  Voltage and current waveforms. Optimal power case.

(9.65)

9.4  Overdriven Amplifiers

199

and the relative output power is

P1 =2 PA

The dc power is

�

D p

Pdc = Vdd × Idc =

�2



(9.66)

Vdd Is × E p

(9.67)

where E is defined in (9.61), and the efficiency can be expressed as

Eff =

1 D2 4p E

(9.68)

In Table 9.7, we have summarized the operating parameters as a function of the overdrive. A plot of the relative output power and efficiency is shown in Figure 9.13. Under this mode of operation the efficiency peaks at q1 = 33º, while the power increases monotonically with increasing overdrive and reaches a value of 3.2 at q1 = 0. This value is substantially higher then the value of 2.55 reached under the optimal efficiency condition, and thus the definition of this mode as optimal power. The compression characteristic and the AM/AM conversion are plotted in Figures 9.14 and 9.15, respectively. The 1-dB compression is reached at an output power of 4 dB (over class A), appreciably higher then the 3.4 dB obtained under the optimal efficiency condition. Interestingly, at the onset of the overdrive, the AM/AM conversion is equal to 1, indicating that the clipping of the waveforms is fully compensated for by the increase in amplitude of the current and voltage fundamental components, as shown graphically in Figure 9.9. The net result is that the Table 9.7  Overdriven Class B: Optimal Power Case q1 degree

q1 rad

K dB

K

D

E

P1/Pa

Eff. %

P1/Pa (dB)

AM/AM

Compr. dB

0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 50.00 55.00 60.00 65.00 70.00 75.00 80.00 85.00 90.00

0.00 0.09 0.17 0.26 0.35 0.44 0.52 0.61 0.70 0.79 0.87 0.96 1.05 1.13 1.22 1.31 1.40 1.48 1.57

95.16 21.19 15.21 11.74 9.32 7.48 6.02 4.83 3.84 3.01 2.31 1.73 1.25 0.85 0.54 0.30 0.13 0.03 0.00

57295.78 11.47 5.76 3.86 2.92 2.37 2.00 1.74 1.56 1.41 1.31 1.22 1.15 1.10 1.06 1.04 1.02 1.00 1.00

4.00 3.99 3.98 3.95 3.92 3.88 3.83 3.77 3.70 3.64 3.56 3.49 3.42 3.35 3.28 3.23 3.18 3.15 3.14

1.57 1.53 1.48 1.44 1.40 1.36 1.32 1.28 1.24 1.20 1.16 1.13 1.10 1.07 1.05 1.03 1.01 1.00 1.00

3.24 3.23 3.21 3.17 3.11 3.05 2.97 2.88 2.78 2.68 2.57 2.47 2.37 2.27 2.19 2.11 2.05 2.01 2.00

81.06 83.16 84.95 86.40 87.49 88.22 88.59 88.61 88.30 87.68 86.80 85.71 84.46 83.14 81.81 80.57 79.53 78.81 78.54

5.11 5.10 5.06 5.01 4.93 4.84 4.72 4.59 4.44 4.28 4.11 3.93 3.74 3.56 3.40 3.25 3.12 3.04 3.01

0.00 0.01 0.02 0.03 0.05 0.08 0.11 0.15 0.20 0.25 0.31 0.38 0.45 0.54 0.63 0.73 0.83 0.93 1.00

93.06 19.10 13.15 9.74 7.39 5.65 4.31 3.25 2.41 1.74 1.22 0.82 0.52 0.30 0.15 0.07 0.02 0.00 0.00

200

High-Efficiency Amplifiers

Figure 9.13  Efficiency and output power. Optimal power case.



output power remains constant, despite the initial clipping. This behavior, together with the higher power at 1-dB compression (as compared to the optimal efficiency case), would result in an improved linearity. Finally, we have to define the output load that is required to operate under these conditions. Since the voltage has only B components, the RF load impedance is ⎧ ⎫ 2Vdd ⎨ ⎬ for n odd VBn Is Zn = = (9.69) ⎩ ⎭ IBn 0 for n even

Thus, the output circuit must present to the device a resistive termination for the fundamental and all the odd harmonics, while acting as a short circuit for all the even harmonics. 9.4.3  Class A: Optimal Loading

Since the class A operation is well known for good linear performance, it may be of interest to apply the efficiency-enhancing overdrive technique to a class A amplifier. In this context, we define class A as the mode where the dc parameters are

Figure 9.14  Output power compression. Optimal power case.

9.4  Overdriven Amplifiers

201

Figure 9.15  AM/AM conversion. Optimal power case.

invariant with the amplitude of the signal, but we set no conditions on the shape of the waveforms. Now we consider the waveforms of Figure 9.16. The current is sinusoidal with a peak value Is, while the voltage is clipped at the amplitude Vdd. For lack of a better name, we will call this mode of operation optimum loading, in accordance with the nomenclature of [1]. Because of class A operation, Vdd and Is /2 are the dc bias parameters. By setting the same peak current and voltage as those in the class B mode, we can make performance comparisons between the different modes of operation. From (9.46), the voltage amplitude at the fundamental frequency is

VB1 =

Vdd × D p

(9.70)

and the amplitude of the corresponding current is

IB1 =

Is 2

Figure 9.16  Voltage and current waveforms. Optimal loading case.

(9.71)

202

High-Efficiency Amplifiers

Thus, the output power at the fundamental is

P1 =

VB1 IB1 Vdd Is ×D = 2 4p

(9.72)

while the output power of a classic class A amplifier is

PA =

Vdd Is 4

(9.73)

Thus the output power referenced to the Class A power is

D P1 = PA p

Since the dc power is

Pdc =

(9.74)

Vdd Is 2

(9.75)

D 2p

(9.76)

the efficiency is

Eff =



The load impedance for the fundamental is

Z1 =

VB1 2Vdd = × Z1r IB1 Is

(9.77)

D p

(9.78)

where



Z1r =

Since there are no harmonics in the current waveform, � � ∞ for n odd and �= 1 Zn = any value for n even

(9.79)

In Table 9.8 we have compiled the operating parameters versus the overdrive angle. A plot of the output power and the corresponding efficiency is shown in Figure 9.17. Since the dc power is constant, the efficiency is proportional to the output power. Thus, with proper scaling, a single graph can represent both quantities. When the voltage waveform reaches a square wave, the efficiency is 63.5%, and the output power, at the fundamental frequency, is 1.27 times (1 dB) higher than for a standard class A amplifier operating under the same bias conditions. The plot of the compression characteristic, shown in Figure 9.18, indicates that the 1-dB compression power is 0.4-dB higher than the output power of a standard class A amplifier. The plot of the AM/AM conversion is shown in Figure 9.19. This characteristic is similar in shape to that of the Class B optimal efficiency case, which is not surprising, given the similarity of the waveforms. Finally, what load circuit generates these waveforms? As we can see from the Z1r column, the load resistance for the fundamental changes with overdrive and

9.4  Overdriven Amplifiers

203

Table 9.8  Overdriven Class A: Optimal Loading q1 degrees

q1 rad

K dB

K

D

P1/Pa

Eff. %

P1/Pa dB

Z1r

AM/AM

Compr. dB

0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 50.00 55.00 60.00 65.00 70.00 75.00 80.00 85.00 90.00

0.00 0.09 0.17 0.26 0.35 0.44 0.52 0.61 0.70 0.79 0.87 0.96 1.05 1.13 1.22 1.31 1.40 1.48 1.57

95.16 21.19 15.21 11.74 9.32 7.48 6.02 4.83 3.84 3.01 2.31 1.73 1.25 0.85 0.54 0.30 0.13 0.03 0.00

57295.78 11.47 5.76 3.86 2.92 2.37 2.00 1.74 1.56 1.41 1.31 1.22 1.15 1.10 1.06 1.04 1.02 1.00 1.00

4.00 3.99 3.98 3.95 3.92 3.88 3.83 3.77 3.70 3.64 3.56 3.49 3.42 3.35 3.28 3.23 3.18 3.15 3.14

1.27 1.27 1.27 1.26 1.25 1.23 1.22 1.20 1.18 1.16 1.13 1.11 1.09 1.07 1.05 1.03 1.01 1.00 1.00

63.70 63.60 63.30 62.90 62.40 61.70 60.90 60.00 59.00 57.90 56.70 55.60 54.40 53.30 52.30 51.40 50.70 50.20 50.00

1.05 1.04 1.03 1.00 0.96 0.91 0.86 0.79 0.72 0.63 0.55 0.46 0.37 0.28 0.19 0.12 0.06 0.02 0.00

1.27 1.27 1.27 1.26 1.25 1.23 1.22 1.20 1.18 1.16 1.13 1.11 1.09 1.07 1.05 1.03 1.01 1.00 1.00

0.00 0.00 0.01 0.02 0.03 0.04 0.06 0.08 0.10 0.12 0.15 0.19 0.23 0.27 0.31 0.36 0.41 0.46 0.50

94.11 20.15 14.18 10.74 8.36 6.57 5.16 4.04 3.12 2.38 1.77 1.27 0.88 0.58 0.35 0.18 0.08 0.02 0.00

2Vdd at full overdrive (q1 = 0). Also, as described by Is (9.79), the load must present an open circuit for the odd harmonics, while the im-

reaches a value of 1.27 ×

pedance for the even harmonics is not relevant. 9.4.4  Class A: Optimal Power and Efficiency

We will now consider the waveforms of Figure 9.20, where both the current and voltage waveforms are clipped sinusoids. The output power at the fundamental is

P1 =

Vdd Is × D2 4p 2

Figure 9.17  Efficiency and output power. Optimal loading case.

(9.80)

204

High-Efficiency Amplifiers

Figure 9.18  Output power compression. Optimal loading case.

and the relative power is

P1 = PA

The efficiency is



�

1 Eff = 2

D p

�

�2

D p



�2

(9.81)



while the load impedance is ⎧ ⎫ ⎨ 2Vdd for n odd including the fundamental⎬ Is Zn = ⎩ ⎭ any value for n even

(9.82)

(9.83)

The operating parameters, as a function of the overdrive, are listed in Table 9.9. The output power and efficiency at the fundamental frequency are plotted in Figure 9.21. At full overdrive, the efficiency reaches 81% with a corresponding power 1.62 times (2.1 dB) that of a standard class A amplifier. These are quite re-

Figure 9.19  AM/AM conversion. Optimal loading case.

9.5  Class E

205

Figure 9.20  Voltage and current waveforms. Optimal power and efficiency case.

markable results, when we consider that they are obtained from a class A amplifier, albeit overdriven (but all high-efficiency amplifiers are overdriven). Figure 9.22 shows the compression characteristic: the 1-dB compression is 1 dB above the standard class A power. The AM/AM conversion, shown in Figure 9.23, is clearly very similar to that of the class B optimal efficiency mode, which is consistent with the similarity in waveforms.

9.5  Class E Of the high-efficiency modes of operation, class E is the mode that is best known for RF applications. It was proposed by Sokal and Sokal in 1975 [3], was patented [4], and has been heavily promoted by the authors. In their original paper, they outlined some optimal idealized waveforms and listed seven rules that defined the class E mode of operation. A detailed mathematical analysis, yielding more realistic Table 9.9  Overdriven Class A: Optimal Power and Efficiency q1 degrees

q1 rad

K dB

K

D

D2

P1/Pa

Eff. %

P1/Pa dB

AM/AM

Comp.r dB

0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 50.00 55.00 60.00 65.00 70.00 75.00 80.00 85.00 90.00

0.00 0.09 0.17 0.26 0.35 0.44 0.52 0.61 0.70 0.79 0.87 0.96 1.05 1.13 1.22 1.31 1.40 1.48 1.57

95.16 21.19 15.21 11.74 9.32 7.48 6.02 4.83 3.84 3.01 2.31 1.73 1.25 0.85 0.54 0.30 0.13 0.03 0.00

57295.78 11.47 5.76 3.86 2.92 2.37 2.00 1.74 1.56 1.41 1.31 1.22 1.15 1.10 1.06 1.04 1.02 1.00 1.00

4.00 3.99 3.98 3.95 3.92 3.88 3.83 3.77 3.70 3.64 3.56 3.49 3.42 3.35 3.28 3.23 3.18 3.15 3.14

16.00 15.96 15.84 15.64 15.37 15.04 14.64 14.20 13.72 13.22 12.70 12.19 11.69 11.21 10.79 10.42 10.13 9.94 9.87

1.62 1.62 1.60 1.58 1.56 1.52 1.48 1.44 1.39 1.34 1.29 1.23 1.18 1.14 1.09 1.06 1.03 1.01 1.00

81.10 80.90 80.20 79.20 77.90 76.20 74.20 71.90 69.50 67.00 64.30 61.70 59.20 56.80 54.60 52.80 51.30 50.40 50.00

2.10 2.09 2.05 2.00 1.92 1.83 1.71 1.58 1.43 1.27 1.10 0.92 0.73 0.55 0.39 0.24 0.11 0.03 0.00

0.00 0.01 0.02 0.03 0.05 0.08 0.11 0.15 0.20 0.25 0.31 0.38 0.45 0.54 0.63 0.73 0.83 0.93 1.00

93.06 19.11 13.15 9.74 7.39 5.65 4.31 3.25 2.41 1.74 1.22 0.82 0.52 0.30 0.15 0.07 0.02 0.00 0.00

206

High-Efficiency Amplifiers

Figure 9.21  Efficiency and output power. Optimal power and efficiency case.

waveforms, was later published by Raab [5], where the class E mode of operation was analyzed as a function of various operating parameters, such as the nature of the output resonator (series or parallel), the value of the duty cycle, and the rate of the turn-on slope. The analysis is based on ideal conditions, such as an ideal switching element and an ideal RF circuit. Still, by necessity, the mathematical derivations are lengthy, rather tedious, and, in our view, not conducive to an intuitive under­standing of the operation of the circuit, which is, in fact, quite interesting. Therefore, for didactical purposes, we favor some simplified analyses, for instance Grebennikov [6] or Cripps [7], which clearly show the main operating characteristics of the circuit, lead to the derivation of waveform equations, and yield a simple, but adequate, design procedure. If needed, a more complete analysis, including nonideal switching devices and circuits, can then be carried out by numerical techniques, using computer programs such as SPICE or a harmonic-balance circuit simulator (see Section 8.7). The simplest and most typical class E circuit is shown in Figure 9.24(a). The active device is switched on and off by an RF generator, and the output circuit in-

Figure 9.22  Output power compression. Optimal power and efficiency case.

9.5  Class E

207

Figure 9.23  AM/AM conversion. Optimal power and efficiency case.

cludes an output capacitor C, whose value includes the device output capacitance, an RF choke for biasing the drain at a voltage Vdd, a series resonator, and the output load R. We’ll assume that the active device (shown here as an FET, but in fact a transistor of any type) is ideal and that it can be represented by the switch shown in Figure 9.24(b). Since the functioning of the circuit, as we’ll see later, depends on

Figure 9.24  (a, b) Class E electrical circuit.

208

High-Efficiency Amplifiers

a phase shift between the voltage across the switch and the current in the load, the output resonator must be detuned. This is represented in the electrical circuit by an additional inductor, L, in series with the resonator formed by Co and Lo, which is tuned at the operating frequency. Using the nomenclature of [6], Io is the power supply current, i(wt) is the current flowing in the switch, v(wt) is the voltage across the switch and the capacitor C, iC(wt) is the current in the capacitor, and iR(wt) is the current in the load resistor. We also make the following assumptions: 1. the switch is ideal, in other words, the on resistance is zero, the off resistance is infinite, and the on-off time is zero; 2. the capacitance C, including the output capacitance of the device, is constant; 3. all the reactive circuit elements are lossless; 4. the resonator is ideal; 5. the duty cycle is 50%. Also, for lossless operation we have to ensure that the voltage across the switch and its derivative are zero just before the closing of the contact:

[v(w t)]w t=2p = 0, and

�

dv(w t) dw t

�

w t=2 p

= 0

(9.84)

Since the currents and voltages in this circuit are all interrelated, we break the loop by making an assumption and then setting the conditions to satisfy such an assumption. The assumption we make is that the voltage and the current in the resonator are out of phase; this, as we mentioned before, is represented in the circuit by the additional inductance L. We don’t know, at this point, the value of the phase shift. We do know, however, that the current iR(wt) is sinusoidal, because that is the stable solution for an ideal series resonator. Thus,

iR (w t) = IR sin(w t + j ),

where j is the current to voltage phase shift (9.85)

Since at the time zero (closing of the switch) the voltage, and its derivatives, are zero, and therefore the currents in the capacitor and in the switch are zero then

i(0) = Io + IR sin j = 0 Io = −IR sin j

(9.86)

We can now write the current in the load, relative to the bias current as

iR 1 sin(w t + j ) =− Io sin j

(9.87)

We have plotted this in Figure 9.25(a) with an angle of j = -32.5º. The reason we chose this angle will be made clear shortly. Similarly, we can express the current in the switch, relative to the bias current as

i(w t) 1 sin(w t + j ) = 1− Io sin j

for 0 < w t < p

(9.88)

9.5  Class E

209

Figure 9.25  (a−e) Waveforms of class E mode of operation.

This is plotted in Figure 9.25(c). Now something interesting happens: at the time wt = p, the switch opens, and the current, iR(wt), is redirected into the capacitor, as shown in Figure 9.25(d), charging it and building up the voltage v(wt). Note that, meanwhile, the current, iR(wt), remains sinusoidal. We consider this switching of the current from the active device to the capacitor, while maintaining continuity

210

High-Efficiency Amplifiers

for the current in the output load, to be the defining characteristic of the class E mode of operation [7]. The current in the capacitor is

iC (w t) 1 sin(w t + j ) = 1− Io sin j



for p < w t < 2p

(9.89)

and the voltage building up across the capacitor is



1 v(w t) = wC

�w t p

Io iC (w t)dw t = wC

for p < w t < 2p

�w t� p

1−

� 1 sin(w t + j ) dw t sin j

(9.90)

The result of the integration is

Io [cos(w t + j ) + cos(j ) + (w t − p )sin j ] sinj × w C IR =− [cos(w t + j ) + cos(j ) + (w t − p )sin j ] wC

v(w t) =

(9.91)



If we now impose the first condition of (9.84), the term within the parenthesis must be 0 for wt = 2p, thus

2 cos j + p sinj = 0 tan−1 j = −

2 p

j = −32.5◦

(9.92)

This, not surprisingly, is the phase shift we had chosen from the beginning. We could have chosen initially any value of j for Figure 9.25, but, in this way, the figure already displays the correct waveforms. As shown in Figure 9.25(e), by choosing j = -32.5º, the voltage reaches zero exactly at wt = 2p. Also, we can see by inspection that the function under the integral in (9.90) is equal to zero for wt = 2p, irrespective of the value of j; thus the derivative of v(wt) is also zero at wt = 2p, irrespective of the value of j. Thus, the conditions we have set initially in (9.84) are both satisfied. What is left, in order to generate the plot of Figure 9.25(e), is to tie the voltage v(wt) to the bias voltage Vdd. We note that the value of Vdd is equal to the average of v(wt) over the period 2p:



1 Vdd = 2p

�2p p

IR v(w t)dw t = − 2pw C

+ (w t − p ) sin j ) dw t = −

�2p

(cos(w t + j ) + cos(j )

p

� � IR 1 2 sin j + p cos j + p 2 sin j 2pw C 2

(9.93)

Then the voltage across the capacitor and the switch, referenced to the bias voltage, is

v(w t) 2p {cos(w t + j ) + cos(j ) + (w t − p ) sin j } = Vdd 2 sin j + p cos j + 12 p 2 sinj

(9.94)

9.5  Class E

211

We can now write the design equations that allow us to define the values of the circuit elements. We can also make at least an initial choice for the active device on the basis of the peak current and voltage requirements. From Figures 9.25(c) and 9.25(e), the peak values are

Ipeak = 2.86 Io and Vpeak = 3.54 Vdd



(9.95)

Having defined acceptable peak values for the device, we can then derive the bias Io and Vdd. We also note that, within the initial assumptions, the circuit efficiency is 100% because (1) all the elements are lossless; (2) the product of the voltage and current at the switch terminals is always zero; and (3) there is no power dissipated at harmonic frequencies, because the output resonator is an ideal filter. Thus we can compute the RF output power as

Pout = Vdd × Io



(9.96)

However, the output power is also expressed as

Pout = and, from (9.86):

IR =



I2R R 2

(9.97)

Io 0.54

(9.98)

Thus, the output load resistance is

R = 0.58



Pout Io2



(9.99)

From (9.91), the in-phase and quadrature components of the voltage v(wt) are

1 VR = p



�2p

v(w t) sinw t dw t =

p

� IR � p sin 2j + 2 cos 2j pw C 2

IR = (−0.58) pw C 1 VL = p

�2p p

v(w t) cos w t dw t = −

IR =− (0.67) pw C

(9.100)



� IR � p + p sin2 j + 2 sin 2j pw C 2



(9.101)

where VR and VL are, respectively, the voltages across the resistor, R, and the inductor, L. Note that there is no voltage across the resonator at the resonant frequency. Therefore,

VL wL 1.15R = = 1.15 thus L = VR R w

(9.102)

212

High-Efficiency Amplifiers

and, from (9.100):

R=

VR 0.58 0.18 = thus C = IR pw C wR



(9.103)

For the resonator, the only requirement is an adequate selectivity to maintain a sinusoidal current waveform. If we choose, for instance, a quality factor of 10, then

Lo =

10R w

and Co =

1 w 2L

(9.104)

At this point we have computed the value of all the elements in the circuit, with the assumption that the duty cycle is 50% and the current offset angle, j, is -32.5º. We must note that, only for this optimal value of j, the voltage across the switch is zero just before closing. Any different value of j will leave a residual voltage V across the contacts, which will result in dissipating the energy ½CV2 at the time of closing. Computations based on (9.94) show that this residual voltage increases rapidly when j is offset from its optimal value. For instance, Figure 9.26 shows the residual voltage for two values of j, both 1.5º off the optimum value. In both cases, the residual voltage is very close or exceeds 0.5 times the bias voltage Vdd, a substantial value for such a small angular offset. Since j changes with frequency, for broadband performance the output circuit must include a reactance compensation, which may be implemented by a combination of series and parallel resonators [6, 8].

Figure 9.26  Voltage across capacitor C for two different values of the current offset angle.

9.6  Real Devices and Circuits

213

9.6  Real Devices and Circuits In Sections 9.4 and 9.5, we assumed perfect active devices and circuits; this leads, not surprisingly, to configurations achieving theoretical efficiencies of 100%. The mathematical analysis of these simplified circuits resulted in simple design equations and procedures. At this point, however, some consideration of real devices and circuits is in order. Although, as we have stressed before, it is the response of the RF circuit that shapes the waveforms, still these waveforms must be compatible with the physical limits of the device. At the same time, the circuit sets its own limits. For instance, as we have described in Sections 9.2 and 9.3, if the resistance of the load line is too high, it limits the current to a lower value than is actually available from the device. Thus, the usable current is determined by the load line, not by the device. The opposite happens if the load-line resistance is too low. Similar considerations can be made for the peak voltage, which is controlled by the circuit, and the voltage breakdown, which is a limit of the device. Thus, the initial design, based on idealized conditions, must be modified, possibly using numerical techniques, to best utilize the actual device. Different modes of operation result in different voltage and current requirements. For instance, in the overdriven class B mode (class F) the peak voltage is 2 times the bias, and the peak current is 3.14 times the bias (9.43), while in the class E mode of operation, the peak voltage and current are, respectively, 3.54 and 2.86 the corresponding bias values (see Figure 9.25). The high peak voltage in class E can be a problem with GaAs-based technology, although it might not be a problem with other technologies. After settling the issue of voltage and current limits in the device, we need to consider the effect of the device’s switching time. Again, we find it useful to compare the class E and F modes of operation. In the class F mode, the switching occurs at a time when the current is about 0, and the voltage across the device is, on the average, equal to Vdd. Thus, the power dissipated in each cycle (two switchings) is

Psw =

2Vdd 2 t Rsw T



(9.105)

where Rsw is the average equivalent resistance of the switch, t is the switching time, and T is the period. In class E operation, the opening of the switch occurs when the current is twice the bias current Io, and thus, the power dissipated is

Posw =

(2Io)2 t Rsw T



(9.106)

At the closing of the switch, if the phase angle, j, is offset even slightly from its optimal value of -32.5º (see Figure 9.26), there is a residual voltage, Vres, across the capacitor, and the power dissipated at closing is

Pcsw =

1 t CV2res 2 T

(9.107)

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High-Efficiency Amplifiers

Note that, assuming a constant switching time, t, all these switching losses are proportional to the frequency, so that, in practice, an approach that works well, say, at 100 MHz might be too lossy when applied in the GHz range. Finally, there is the issue of implementation of the RF circuitry. For class F operation, we have to present to the intrinsic device a certain load resistance for the fundamental, (see (9.48)), a short for the even harmonics, and an open for the odd harmonics, (see (9.49)). Satisfying this condition for an infinite number of harmonics may appear to be an impossible task, but in practice it can be shown that most of the waveform shaping is achieved by the first few harmonics, say, the second and the third. In fact, it is pointless to be concerned about the fourth harmonic, for instance, if the device does not respond at a frequency 4 times the fundamental. In other words, given a certain device, there is simply no substantial harmonic content above a certain frequency, and this cannot be overcome by any circuit or mode of operation. In fact, it was shown long ago that excellent performance can be obtained just by providing a short for the second harmonic and an open for the third harmonic [9]. In this case, the harmonic tuning was implemented by l /4 stubs located at the proper electrical distance from the intrinsic device, and the amplifier used a standard packaged device designed for operation up to 8 GHz. For operation in class E, the circuit is simpler, at least for narrow band, except for the need to connect at the output of the intrinsic device (in practice, the device chip) a capacitor whose value is equal to the C0 of (9.104) minus the output capacitance of the device. There is no other place where that capacitor can be connected. Thus, in practice, a true class E operation cannot be implemented at microwave frequencies, above 2 GHz, for instance, without having access to the device chip. Both the overdriven class B (class F) and class E amplifiers reach a theoretical efficiency of 100%. Their modes of operation are quite different, however, and, as a result, they differ in many of the operating parameters, such as peak voltages and currents, as well as harmonic response of the load network. Neither of the two approaches has an overwhelming advantage, a result we consider beneficial, since it provides welcome diversity and a real choice between two very different alternatives.

References [1]

[2] [3]

[4] [5] [6]

Snider, D. M., “A Theoretical Analysis and Experimental Confirmation of the Optimally Loaded and Overdriven RF Power Amplifier,” IEEE Trans. on Electronic Devices, Vol. ED14, No. 12, December 1967, pp. 851–857. Raab, F. H. “Class-F Power Amplifiers with Maximally Flat Waveforms,” IEEE Trans. on Microwave Theory and Techniques, Vol. 45, November 1997, pp. 2007–2012. Sokal, N. O., and Sokal A. D. “Class E—A New Class of High-Efficiency Tuned SingleEnded Switching Power Amplifiers,” IEEE J. Solid-State Circuits, Vol. SC-10, June 1975, pp. 168–176. Sokal, N. O., and Sokal A. D., “ High-Efficiency Tuned Switching Power Amplifier,” U. S. Patent 3 919 656, Nov. 11, 1975. Raab, F. H., “Idealized Operation of the Class E Tuned Power Amplifier,” IEEE Trans. on Circuits and Systems, Vol. CAS-24, No. 12, December 1977. Grebennikov, A., RF and Microwave Power Amplifier Design, New York: McGraw Hill, 2005.

9.6  Real Devices and Circuits [7] [8]

[9]

215

Cripps, S. C., Advanced Techniques in RF Power Amplifier Design, Norwood, MA: Artech House, 2002. Kumar, N., et al., “High-Efficiency Broadband Parallel-Circuit Class E RF Power Amplifier with Reactance-Compensation Technique,” IEEE Trans. on Microwave Theory and Techniques, Vol. 56, March 2008, pp. 604–612. Sechi, F. N. “High Efficiency Microwave FET Power Amplifiers,” Microwave Journal, November 1981, pp. 59–66.

Chap te r 10

Linear Power Amplifiers 10.1  Introduction Many phenomena contribute to the distortion of a signal as it goes through an amplifier. Even in the simplest case of an RF signal with constant envelope, some distortion is still caused by the variation of the group delay within the band. The problem becomes much more complex if the envelope is not constant, either because it consists of multiple RF carriers, or because it is, in fact, amplitude modulated. This is inevitably the case in modern communication systems: as the channel information efficiency is increased, the modulation becomes progressively more sophisticated. In fact, an efficient coding generally includes both amplitude and phase modulation, and the most efficient codings result in signals that closely resemble band-limited white noise. Such signals typically exhibit high peak-to-average power ratios. The problem is further aggravated when multiple signals are amplified within a single RF channel, because, as described in Section 10.2.1, the beat between carriers generates amplitude modulation. This is, in fact, the mode of operation that is typical of base stations. In order to maintain signal integrity, even at the high peaks, the amplifier is operated at reduced output power, in what is called a backoff mode. This inevitably reduces the operating efficiency, which becomes the most critical parameter. Thus optimizing the efficiency at a specified value of linearity is typically the main objective in the design of a linear power amplifier. The amplifier must reproduce with low distortion both the amplitude and the phase of the signal. Yet, for the sake of simplicity, phase linearity is often neglected, and the entire industry of microwave solid-state amplifiers has been built around the concept of P1dB, which, as we describe in Section 10.2, is only a measure of amplitude distortion, at best. Unfortunately, as we will describe in Section 10.2.2, relying on the P1dB measurement and overlooking phase distortion results in a large discrepancy between the estimated and actual performance of an amplifier.

10.2  Linearity The linearity of an amplifier can be characterized by measuring the AM/AM and AM/PM conversions, as we have already discussed in Section 4.3.2. These data are of interest, because they quantify separately the amplitude and the phase distortions. However, often it is convenient to derive data that describe directly the combined effects of these distortions, such as the generation of spurious signals: how we can acquire this data is discussed in Section 10.2.1.

217

218

Linear Power Amplifiers

10.2.1  Amplitude Distortion: Two-Tone IMD

The two-tone test is the technique most commonly used to determine the effect of nonlinearities on amplitude-modulated signals. It is designed to measure the most damaging effect, which is the intermodulation distortion (IMD). The intermodulation process transfers modulation between carriers and generates products at frequencies adjacent to the original carriers. The effect of amplitude distortion on a two-tone signal can be computed in terms of its spectral components, by assuming a polynomial relationship between the instantaneous input and output voltages of the amplifier. In the following, we’ll consider the simple case of a third-degree polynomial [1]:

eout = k1 ein + k2 e2in + k3 e3in



(10.1)

where ein and eout are, respectively, the input and output instantaneous voltages. If we assume, for simplicity, that the input signal is composed by two sinusoids of equal amplitude A and frequencies w1 and w2:

ein = A(cos w1 t + cos w 2 t)



(10.2)

then the output signal is expressed by the following three terms:

eout = k1 A(cos w1 t + cos w2 t) + k2 A2 (cos w1 t + cos w2 t)2

+ k3 A3 (cos w1 t + cos w2 t)3

(10.3)

The first term represents the linear amplification. The second term includes a dc shift: (10.4)

a dc shift: + k2 A2



the sum and difference of the frequencies:

+k2 A2 cos(w1 t ± w 2 t)



(10.5)

and the second harmonics:



+

k2 A2 cos 2w1 t 2

and

+

k2 A2 cos 2w2 t 2

(10.6)

The third term includes the third harmonics:

1 k3 A3 cos 3w1 t 4

and

1 k3 A3 cos 3w2 t 4

(10.7)

the sum and difference frequency products:

3 k3 A3 cos(2w1 t ± w2 t) 4

and

3 k3 A3 cos(2w2 t ± w1 t) 4

(10.8)

10.2  Linearity

219

and two products at the same frequency as the input signals:



3 + k3 A3 cosw1 t 4

and

+

3 k3 A3 cosw2 t 4

(10.9)

Under normal conditions the gain decreases (compresses) as the amplifier approaches saturation; thus gain compression is modeled by a negative k3. Occasionally, the amplifier exhibits a gain expansion, and in that case, k3 is positive. The products generated by the nonlinear process are categorized by their order, where the order number is defined by the number of frequencies involved in the mixing, with the understanding that the same frequency may be involved more than once. Thus the second harmonic is a second-order distortion product and 2w1t - w2t is a third-order product. In our simple case of a polynomial representation, the second- and third-degree terms of the power series do generate second- and third-order distortion products, respectively. However, this simple relationship doesn’t apply in every case, and specifically, it doesn’t apply where there is a feedback path [2]. If we assume now that w1 and w2 are close together, for instance, a few MHz apart at microwave frequencies, we find that all the second-order distortion products fall at frequencies that are far away from the input signal and often can be filtered out. More troublesome are the third-order intermodulation products deriving from the mixing of the two carriers. Some products, defined by (10.9), cause transfer of modulation between the carriers [1] (whereby, the name intermodulation), and some, deriving from the same phenomenon, are of the type:

2w 1 t − w 2 t

and 2w 2 t − w 1 t

(10.10)

and fall near the carriers. In fact, it is the level of the (10.10) products that is taken as a measure of the third-order intermodulation distortion of the amplifier. We must note, however, that filtering out the (10.10) products would not overcome the inher­ ent damage of intermodulation, which is in fact the transfer of modulation from one carrier to another, as defined by (10.9). Additional intermodulation products that are present in amplifiers can be modeled by extending the degree of the polynomial (10.1). For instance, a fifth-degree term generates products of the following type:

3w1 t − 2w2 t

and 3w2 t − 2w1 t

(10.11)

which fall adjacent to the (10.10) products. In general, the even-degree terms of the polynomial generate dc products, harmonics, and other products that are far from the carriers, while the odd-degree terms, in addition to harmonics and distant products, generate the more damaging intermodulation products that fall near the carriers. We should mention, however, that the generation of dc products, while seemingly harmless, is in fact the key to the detrimental spectrum asymmetry discussed in Section 10.2.5. Also, the secondorder distortion in nonlinear elements, such as the capacitors in the nonlinear equivalent circuit of an active device, causes phase distortion and intermodulation, a topic discussed in Section 10.2.3.

220

Linear Power Amplifiers

Figure 10.1  Two-tone signal: (a) spectrum; and (b) amplitude-modulated signal in the time domain.

It is useful to view the two-tone signal of (10.2) in a graphical form. Figure 10.1(a) is the corresponding spectrum, which is composed by two lines of amplitude A at frequencies f1 and f2. Figure 10.1(b) is the corresponding time-domain representation. We note that, even though the two tones are CW, the composite signal is amplitude modulated: the beat between the tones establishes an amplitude modulation of the RF envelope, at a frequency equal to the difference between the two carriers:

fm = f2 − f1

(10.12)

Although this signal in the time domain appears simply as an amplitudemodulated carrier, there is a significant difference: the phase of the signal reverses after each beat cycle, which, of course, doesn’t happen with a simple amplitude modulation. From the polynomial analysis, we have found that if we feed the signal of Figure 10.1 into an amplifier, whose response is modeled by (10.1), the output signal includes third-order intermodulation products at frequencies 2f1 - f2 and 2f2 - f1, and possibly fifth-order distortion products at frequencies 3f1 - 2f2 and 3f2 - 2f1. Thus, the spectrum appears as in Figure 10.2. Note that the spectrum is symmetrical and consists of equally spaced lines, where the spacing is equal to the modulation frequency fm. In the figure, I3 and I5 are the third- and fifth-order intermodulation products, respectively. If we now plot the results of the polynomial analysis in terms of output power and third-order intermodulation as a function of input power, all expressed in decibels, we obtain the result shown schematically in Figure 10.3. At small signals— when the amplitude A of each tone is small, the term (10.9) is negligible, the output is defined by the linear term kA, the gain is constant, and C, the single-tone Pout versus Pin characteristic, is a straight line with a 1:1 slope. As the power increases, a larger term, (10.9), is subtracted from the linear term, the gain decreases, the

10.2  Linearity

221

Figure 10.2  Two-tone signal, including intermodulation products.

power saturates, and the characteristic C deviates markedly from a straight line. In a similar way, we can plot the power of the third-order intermodulation product, I3, as a function of Pin. Since the level of the intermodulation product is proportional to A3, the I3 characteristic initially has a 3:1 slope and then shows saturation at larger signals in accordance with the saturation of the carrier. The distortion is then measured by the C/I ratio. If we now extend the linear portions of the C and I3 curves, their intersection defines the IP3 point also known as the third-order intercept point. We can also apply the polynomial model, (10.1), to a single CW carrier and compute the saturation from (10.9). We can then compute P1dB as the output

Figure 10.3  Output power and third-order intermodulation versus input power.

222

Linear Power Amplifiers

power level, corresponding to a gain that is 1-dB below the small-signal gain. It can be proven that IP3 is 9.6-dB higher then P1dB [1]. Now, by keeping in mind that a 1-dB change in output power corresponds to a 2-dB change in C/I, we have a very simple rule for computing intermodulation in the region where the C and the I3 characteristics are substantially linear:

IP3 = P1dB + 9.6 (dB) and

C/I = 2(IP3 − P1out ) (dB)

(10.13)

These relationships let us compute the C/I for any value of output power P1out or vice versa. Note that P1out is the output power of each single tone in a two-tone signal, while P1dB is measured with a single tone. The simple modeling defined by (10.1) can be extended to higher-degree polynomials to evaluate higher-order intermodulation products and their mathematical expression is available in the literature [3]. What is hidden in this rather simple polynomial modeling is a serious mathematical instability in the computation of coefficients for a polynomial degree greater than 3. We will discuss this point again in Section 10.6.1. Finally, we can extend the modeling by adding additional tones to the input signal, and a three-tone analysis is carried out in [1]. It is also useful to derive the value of the peak power in the case of a multitone signal. If we consider n tones, each of a constant amplitude A, and a load resistance of 1W, then the average power per tone is

P=



A2 A2 and the average power for the n tones is Pavg = n 2 2

(10.14)

The peak power is reached when the n phasors are all lined-up. Thus, the peak power is (nA)2 (10.15) Ppk = = nPavg 2 which indicates that an increase in the number of tones, even at a constant average power, proportionally increases the peak power. Thus, different signals, even those having the same average power, may generate very different intermodulation products. 10.2.2  Real IMD Curves

It is instructive to examine the intermodulation performance of a power amplifier measured over a broad frequency range. In Figure 10.4, curves (a) through (d) show the intermodulation at selected frequencies in the 8–18-GHz range. In these graphs, the output power is plotted as a function of the carrier-to-intermodulation ratio (C/I). These are the two most important (and closely linked) parameters defining the IMD performance of an amplifier. From this measured data, we can make the following observations: 1. Even within the same amplifier and under constant bias, the shape of the IMD curves can be very different at different frequencies, which is quite evi-

10.2  Linearity

Figure 10.4  (a–d) Example of measured 8–18-GHz IMD performance.

223

224

Linear Power Amplifiers

dent when comparing plot (a) (8 GHz) with (b) (12 GHz). One characteristic that they have in common is that both curves are rather flat in the saturation region, where the C/I is low. Thus, a small change of output power results in a large change of C/I. For instance, in (b) a change of 2 dB in output power results in a change of 15 dB in C/I. 2. In many cases, the slope of the IMD characteristic deviates greatly from the classic third-order distortion 2:1 slope. The obvious question is: How do these IMD data compare with the theory of Section 10.2.1? The simple answer is: not very well, and we’ll show some examples in the following. To apply (10.13), we have to determine the value of P1dB. Let’s consider, for instance, the performance at 8 GHz. The measured Pin−Pout and gain of the amplifier, as plotted in Figure 10.5(a), show that the gain drops 1 dB at an output power of 42.5 dBm. This is the P1dB value we need to compute the power versus C/I. From (10.13), we then have

P1out =



2 × IP3 − 2

C I

(10.16)



Note that P1out is the power of each tone, while Figure 10.4 refers to the total power of the both tones. Thus the computed total power is



Pout =

2 × IP3 − 2

C C 2 × (P1dB + 9.6) − I +3= I +3 2

(dBm)



(10.17)

This is plotted in Figure 10.5(b), and it shows as a straight line. On the same figure we replotted the measured IMD. The discrepancy with the IMD computed from the P1dB varies with the power, but typically is 3–4 dB. This is a large discrepancy, because, for instance, if we base an initial design on the P1dB rule of (10.13) and then we have to modify it to meet IMD performance requirements, we have to redesign the amplifier for a power, and therefore a cost, that is more than double. Clearly, a faulty estimation of the nominal power of the amplifier has very serious implications. For completeness, we also show in Figure 10.5(c) the IMD computed with the simple quadrature model described later in Section 10.5, which includes phase distortion. Clearly, the agreement with the measured IMD is much improved, despite the simplicity of the model. It’s also interesting to apply the same analysis to data at a different frequency, and specifically at 12 GHz, where the IMD response is quite irregular. The plot of output power and gain of Figure 10.6(a) clearly shows an irregular response: the gain has a region of gain expansion before entering the region of regular gain compression. If we consider the compression as starting at the peak of the gain, we derive a P1dB of 41.2 dBm and, therefore, an IP3 of 50.8 dBm. Thus, the computed IMD is the straight line shown in Figure 10.6(b). Again, the agreement with the measured data is poor, caused in part by the irregularity of the gain response. The

10.2  Linearity

225

Figure 10.5  (a–c) 8GHz computed IMD.

IMD computed from the quadrature model, as shown in Figure 10.6(c) is still not accurate, but it is a better approximation. These results show that the simple and classic model of IMD caused by amplitude distortion alone does not describe adequately the IMD performance of real amplifiers. Specifically, the estimation of the IMD on the basis of the P1dB is, in most cases, way off. The main problem with this approach is that the simple polynomial representation of (10.1), although seemingly very general and complete, is in fact only a dc model that does not apply very well to time-varying signals, and specifically, cannot model phase nor phase distortions.

226

Linear Power Amplifiers

Figure 10.6  (a–c) 12-GHz computed IMD.

10.2.3  Phase Distortion: Two-Tone IMD

The origin of amplitude distortion is quite intuitive: the device saturates, the voltage and current waveforms become compressed, and the effect is easily simulated by the k3 coefficient of the power series described in Section 10.2.1. On the other hand, the origin of phase distortion is still simple, but not as intuitive. If we simulate the amplifier with a network that includes the nonlinear elements associated with the

10.2  Linearity

227

active device, we can again describe each nonlinear element with a power series. For instance, a nonlinear capacitor can be described as a function of voltage by a third-degree polynomial:

C(v) = C0 + h1 v + h2 v2 + h3 v3



(10.18)

where v is the instantaneous voltage of the RF signal, C0 is the capacitance in absence of RF excitation, and the h coefficients are constants. We consider again a two-tone RF signal, as we have done in Section 10.2.1, so that the voltage is

v = A(cos w1 t + cos w2 t)



(10.19)

Following the same process as in Section 10.2.1, we find that the products associated with the h2v2 term include a dc component, +h2A2. This is a capacitance added to C0, whose value is a function of the amplitude of the RF signal. In other words, the second-order distortion introduces a shift in the average-value capacitance, and this shift varies with the level of the input power. This effect appears, of course, on any element of the network that has a second-order distortion. The variation of the average value of capacitors and resistors in the network describing the amplifier results in an additional phase shift between the input and output RF signals; such a shift is a function of the amplitude of the RF input power. This is the phase-distortion effect we encountered in Section 4.3.2 and it is clearly the result of the second-order distortion in the amplifier. Many mathematical models have been developed to account for the combined effect of amplitude and phase distortions on the intermodulation. Early models, developed for TWTs [4−7], were derived from measured AM/AM and AM/PM data. Through the years, many additional models have been proposed, and a very simplified description of them is contained in Section 10.6. What all these models have in common is the very high complexity of the mathematical treatment. While the effects of amplitude distortion can be understood and computed easily from simple trigonometric derivations, the effects of phase distortion cannot be computed in a similarly simple way. Still, there is a need for a simple model, even though approximate, to gain an intuitive understanding of the phase distortion process and to derive the most important features of the IMD induced by phase distortion. To this end, the approach we follow here is the one proposed by Sechi to explain the operation of a linearized class B amplifier [8]. Our objective is to define how the AM/PM conversion process produces intermodulation products that are coherent with those produced by AM/AM conversion. Thus we rewrite the two-tone signal of (10.2) as



� � w1 − w2 w1 + w2 a = A(cos w1 t + cos w2 t) = 2A cos t × cos t 2 2

(10.20)

We saw in Section 10.2.1 that this signal is similar to a carrier:



2A cos

w1 + w2 t 2

(10.21)

228

Linear Power Amplifiers

amplitude modulated by the term:

cos



w1 − w2 t 2

(10.22)

and the modulation frequency is

wm = w1 − w2



(10.23)

rather than ½ this value, as might be suggested by (10.22). In fact, the envelope of the wave peaks when

cos



w1 − w2 t is either + 1 or − 1 2

(10.24)

thus, the modulation frequency is indeed as described in (10.23). We now consider the case of an amplifier having a linear phase distortion defined as

F = KA



(10.25)



where F is the phase difference between input and output, K is a constant, and A is the amplitude of a single input carrier. If we now apply the signal (10.20) to the input of the amplifier, the amplitude modulation caused by the beat will result in phase modulation having a peak value of qp = K A

Thus, the output signal is





w1 − w2 b = 2AGcos t × cos 2

�

� w1 + w2 t + qp cos wm t 2

(10.26)

Expanding (10.26) in a series of Bessel functions and considering the first three terms, � w1 − w2 w1 + w2 b = 2AGcos t J0 (qp ) cos t 2 2 � � � �� � � (10.27) w1 + w2 w1 + w2 − J1 (qp ) −sin − wm t + wm t + sin 2 2 The first term is



2AGJ0 (qp )cos

w1 − w2 w1 + w2 t cos t = AGJ0 (qp ) (cos w1 t + cosw2 t) (10.28) 2 2

10.2  Linearity

229

Noting that, for qp small, J0(qp) » 1, this term describes the two amplified carriers at the output port. The second term is

� � w1 − w2 w1 + w2 2AG cos t J1 (qp ) sin + wm = 2 2



= AGJ1 (qp ) [sinw2 t + sin(w2 + wm )t ]

(10.29)

whose components are

AGJ1 (qp ) sinw2 t , 2nd carrier, and

(10.30)



(10.31)

AGJ1 (qp ) sin(w2 + wm )t, higher sideband. Similarly, the third term gives



−AGJ1 (qp ) sinw1 t , 1st carrier, and

(10.32)



−AGJ1 (qp )sin(w1 − wm )t, lower sideband.

(10.33)

Clearly (10.31) and (10.33) are coherent with intermodulation products generated by amplitude distortion. Also, we must note that, even though the terms (10.31) and (10.33) add to the carrier with different signs, they are sine terms, while the carriers are cosine terms. Thus they are in quadrature, and therefore the carriers maintain identical amplitude:



� AG J02 (qp ) + J12 (qp )

(10.34)



The carrier-to-intermodulation ratio, caused by phase distortion, is



C = I

�

J20 (qp ) + J12 (qp ) J1 (qp )

(10.35)

10.2.4  Composite Amplitude and Phase Distortion

So far, we have analyzed the effects of the amplitude and phase distortions as two independent phenomena. In practice, of course, the two effects are simultaneous and the intermodulation distortion that we measure is the result of the combined contribution of the two distortions. We have seen that, with a two-tone input signal A(cos w1t + cos w2t), as defined by (10.2) and (10.20), the amplitude-distortion intermodulation products are



3 k3 A3 cos(w1 − wm ), lower sideband, and 4

(10.36)

230



Linear Power Amplifiers

3 k3 A3 cos(w2 + wm ), higher sideband, 4

(10.37)

while the corresponding phase-distortion products are

−AGJ1 (qp ) sin (w1 − wm )t, lower sideband, and

(10.38)



AGJ1 (qp ) sin (w2 + wm )t, higher sideband.

(10.39)



Comparing these sidebands, we see that products generated by phase distortion are coherent, but in quadrature with those generated by amplitude distortion. Thus, despite the opposite sign between the lower and higher phase-distortion sidebands, the composite spectrum of amplitude and phase distortion is symmetrical. Although this same result can be obtained from a more complete mathematical analysis [4], it is surprising at first because large spectrum asymmetries are often observed experimentally. An explanation for this phenomenon is given in Section 10.2.5. 10.2.5  Spectrum Asymmetry and Memory Effects



We mentioned in Section 10.2.4 that large asymmetries in the output spectrum (often 10 dB or more) are observed experimentally, even in situations where the RF bandwidth is large compared to the output spectrum. It can be shown that this phenomenon is related to the bandwidth of the bias circuit [8]. Indeed, in a real amplifier, the RF signal always affects, to some degree, the bias current. In particular, an amplitude-modulated signal will induce a modulation of the bias current. In the case of a two-tone signal, we saw earlier (see (10.20)) that the modulation frequency is equal to the frequency separation between the two tones. If we then assume that the bias circuit is partially reactive at the modulation frequency, the modulated current will generate a voltage across the device that has a quadrature component with respect to the modulation of the input signal. This effect is often referred to as nonlinear long-term memory: nonlinear because the effect only appears with large signals, long-term because of the relatively slow modulation frequency, and memory because it is a reactive effect. The quadrature voltage component generates a phase modulation that is also in quadrature. Thus, in place of (10.22), we can now write � � w1 − w2 w1 + w2 (10.40) b = 2AGcos t × cos t + qp sinwm t 2 2 where the sin wmt has replaced the cos wmt modulation, and qP is the peak modulation angle. By the same procedure followed above, we obtain



� w1 − w2 w1 + w2 b = 2AGcos t J0 (qp ) cos t 2 2 � � � �� � � w1 + w2 w1 + w2 − J1 (qp ) −cos − wm t + wm t + cos 2 2

(10.41)

10.2  Linearity

231

and the amplitudes of the two sidebands derived from the second and third terms are

−AGJ1 (qp )cos(w1 − wm )t, lower sideband, and AGJ1 (qp ) cos (w2 + wm )t, higher sideband.





(10.42) (10.43)

This result is interesting in that it shows sidebands as cosine terms, similar to the AM-generated sidebands (also cosine terms), but opposite in sign. Since all the sidebands (see (10.36), (10.37), (10.38), (10.39), (10.42), and (10.43)) appear at the same time, the result is an asymmetrical spectrum. In summary, the asymmetry derives from the bandwidth limitation of the bias circuit, and specifically from the bias circuit becoming reactive at certain modulation frequencies. This is consistent with the experimental observation that the output spectrum is symmetrical for small-carrier separations and degrades, becoming asymmetrical, when the carrier separation approaches the cutoff frequency of the bias circuit. The general degradation is attributed to the bias voltage that drops at the peak of the RF envelope. We must note that the above explanation for spectrum asymmetry, which is simple and intuitive for class B operation, is in fact quite general: it applies correctly even in low-level cases where the modulation of the current in the bias circuit is so small that it seems to have vanished, and the amplifier is considered to be operating in class A. In fact, let us assume (10.1) as a model for an active device, with eout representing the device current. In the presence of a second-order distortion, a two-tone input signal produces in the bias network a signal with frequency wm and amplitude k2A2(see (10.5)). It is important to note that the current modulation at frequency wm is proportional to A2, while the IMD is proportional to A3 (see (10.8)), so that their ratio is inversely proportional to A:



4k2 3k3 A

(10.44)

This expression shows that when the level of the input signal (A) decreases, the current modulation, relative to the level of intermodulation, becomes progressively stronger, rather than vanishing. In general, we can safely assume that, if there is a third-order distortion, there is also a commensurate level of second-order distortion, no matter how low the input signal. Thus, if we can detect an IMD signal, we can be assured that there is also a current modulation in the bias circuit and, therefore, the potential for IMD asymmetry. In other words, class A operation is only an approximation, which is never fully realized in practice. In summary, we have shown that (10.42) and (10.43), which were originally reported in [8], explain the IMD spectrum asymmetry well, both for large signals (class B operation) and low-level signals (class A operation). In comparison, the explanation for low-level asymmetry given in [9] requires a substantial reactance at the second harmonic. This cannot be a general explanation, because most amplifiers showing spectrum asymmetry are of a tuned type and are narrowband amplifiers. Thus, the second harmonic is inevitably shorted out by the output capacitance of the device.

232

Linear Power Amplifiers

The limitation of the modulation bandwidth sets a limit on the usable instantaneous RF bandwidth of the channel. For instance, if RF carriers are widely spaced in the RF channel, the wide spacing results in high modulation frequencies that may exceed the bandwidth of the bias circuit. The result is not only an asymmetrical spectrum, but also an increase of the intermodulation. The relationship between maximum amplitude-modulation frequency and RF bandwidth is specific of the signal in question. In a simple case of three equally-spaced carriers, the instantaneous RF bandwidth cannot be higher then twice the maximum modulation frequency. The concept of a memory effect is useful to explain spectrum asymmetries due to nonelectrical phenomena, such as heating. Specifically, if the bias current modulation is rather large, and the thermal time constant associated with the active region of the RF device is similar to the modulation period, the periodic heating and cooling at the rate of the modulation frequency but delayed by the thermal time constant can result in spectrum asymmetries [10, 11]. Similarly, the storing and releasing of electrons by traps located at the interface between the active channel of an FET and the substrate can also result in memory effects and, therefore, in spectrum asymmetries. Of course, the time constants of the different memory effects can be vastly different. For instance, memory effects due to thermal phenomena might appear at modulation frequencies in the kHz range [10], while memory effects in the bias circuit might appear at modulation frequencies in the 10–100-MHz range [13]. The task of building broadband (low-memory) bias circuits, with very low output impedance, is often not trivial. The main difficulty is that the paralleling of different capacitors, used to bypass different ranges of frequency, often results in parallel resonances that raise the output impedance at certain frequencies. The performance can be improved by connecting series resonators tuned at the high end of the modulation band [12]. A novel approach, described in Section 12.3, is based on an active bias circuit implemented with a high-frequency transistor.

10.3  Design Technique: Intermodulation and Power Contours The design of GaAs FET linear amplifiers offers a unique challenge because of the following issues: 1. The intermodulation distortion (IMD) depends critically on the circuit impedance; 2. The slope of the IMD characteristics versus RF drive differs from the normal 3:1 slope—typical of a predominant third-order distortion—and can reach values as high as 8:1. Therefore, FET amplifiers are often very sensitive to overdrive, and only an accurate and systematic characterization of the active device, coupled to a precise design method, can draw from the selected device its optimum performance. For a well-behaved amplifier, which typically operates in class A or AB, there is a clear tradeoff between the degree of linearity and the level of output power. Specifically, the required level of linearity may be achieved by reducing the level

10.3  Design Technique: Intermodulation and Power Contours

233

of output power. However, this backoff mode of operation reduces the efficiency, which is often a critical parameter. The objective of the design technique we will describe is to determine the set of operating parameters that result in the device delivering maximum output power at predetermined values of intermodulation distortion and frequency. For simplicity, but without loss of generality, we’ll assume that the amplifier operates in class A, so that the maximum output power is equivalent to the maximum efficiency. Alternatively, output power can be replaced by power-added efficiency or, in fact, by any other quantity of interest. The frequency is considered constant, and the most important independent variables are load impedance, RF input power, and bias. Once these are fixed, the set of operating parameters—RF output power, intermodulation, load impedance, RF input power, and bias—is unique. A corollary is that no tradeoff can be made between gain and power at a predetermined intermodulation level. For instance, we cannot achieve a higher level of output power, at a preset value of intermodulation, by increasing the input drive (thereby decreasing the gain) and retuning the output circuit. In other words, we cannot trade a reduction in gain with an increase in output power. A design technique that is both effective and instructive is the one based on intermodulation and output-power contours. These contours can be either measured by using a load-pull system (see Section 4.3.1 and [13]) or simulated from a nonlinear model by using a large-signals circuit simulator. For ease of explanation, we’ll use simulated contours. Figure 10.7 is an example of intermodulation contours obtained from the AWR Microwave Office large-signal simulator by running a harmonic balance algorithm [14]. The device model is a Curtice cubic nonlinear FET model biased at Vg = -0.3V and Vd = +3V. The RF input is a closely-spaced

Figure 10.7  Example of third-order intermodulation (IM3) contours computed for a two-tone signal. The level of the intermodulation product is referenced to the level of the carrier.

234

Linear Power Amplifiers

two-tone signal set at 2.2 GHz. Each contour on the Smith chart is the locus of load impedances that result in a constant value of third-order intermodulation distortion (IM3). The center of the contours (p11) is a contour collapsed to a single point, and it corresponds to the lowest level of intermodulation (-33.8 dB below the carrier). Each of the other contours (p1 through p10) is the locus of load impedances that correspond to a constant value of IM3. The contours are plotted at IM3 levels spaced 2-dB apart. Figure 10.8 shows the corresponding contours of the two-tone output power. The center point corresponds to the highest output power (+19.36 dBm), while the remaining contours (p1 through p8) are the loci of constant levels of output power, spaced 1-dB apart. If we now superimpose the IM3 and the Pout contours, as shown in Figure 10.9, we can determine the output power and the corresponding intermodulation for any load impedance within the intersect area of IM3 and power contours. One easily sees, by inspection, that along a line of constant intermodulation, the best load impedance corresponds to the point closest to the center of the power contours, since that load provides the highest output power for the specified value of IM3. This condition is expressed more precisely by stating that the optimum load is defined by the tangent point between the IM3 contour and the corresponding power contour. Notice that for a well-behaved device only one power contour is tangent to one IM3 contour, thus the tangent point is unique. The optimum path is now defined as the locus of the tangent points between the power and the IM3 contours and, being a gradient of both power and IM3 contours, it is perpendicular to both. This is shown schematically in Figure 10.10, where I1 is one IM3 contour and P1 is the corresponding tangent power contour. The common gradient line connects the point for minimum IM3 (A) with the point for maximum output power (B). This line is an optimal path, as any impedance on that line provides an optimal performance for power versus IM3.

Figure 10.8  Example of two-tone output-power contours.

10.3  Design Technique: Intermodulation and Power Contours

Figure 10.9  Superimposed IM3 and power contours.

Figure 10.10  Load-impedance optimal path.

235

236

Linear Power Amplifiers

There are still two independent variables to be optimized: these are the RF input power and the bias point. If we iterate the process for a few values of input power, we find that typically the optimal path remains virtually unchanged. Thus, we can define a coordinate along the optimal path, and, using either a graphical technique [13] or an analytical one, we can interpolate the data and determine the exact impedance for maximum output power. The same process can then be used to optimize the bias point. The final result is an optimal set of operating parameters—load impedance, RF input power, and bias point—that maximizes the output power delivered at a specified value of intermodulation distortion.

10.4  Test Set We should add some practical notes about the IMD measurement system. A typical setup for a two-tone measurement is shown in Figure 10.11. The signals of two separate RF sources—at frequencies f1 and f2, typically set a few megahertz apart—are fed into a 3-dB hybrid through two attenuators, A1 and A2. The function of the attenuators is to improve a critical parameter in the test set, the isolation between the two sources. If needed, two auxiliary amplifiers, AM1 and AM2, might be used to boost the level of the input signal. Note that, within this configuration, the nonlinearity of the auxiliary amplifier does not affect the background system IMD. Harmonics, which might affect the IMD readings by mixing with the fundamental frequencies and generating additional IMD products, are removed by a low-pass filter (LP). A variable attenuator (VA) adjusts the level of the input power applied to the device under test (DUT) through an isolator (IS). The RF input power (Pin) is measured through a coupler. Although the Pin measurement must be adjusted for the loss of the isolator, this configuration eliminates errors due to reflection at the input of the DUT and the finite isolation of the coupler. The input signal, composed of two clean spectral lines at frequencies f1 and f2, is processed by the DUT. The resulting output signal spectrum contains the two amplified signals, at frequencies f1 and f2, plus the intermodulation products. The carrier-to-intermodulation ratio (C/I) is measured by a spectrum analyzer (SA), while the output power is measured by a power meter through an attenuator (A3).

Figure 10.11  Test set for IMD measurements.

10.5  A Simple Quadrature Model

237

By replacing the DUT with a through connection, we can verify that the background system IMD is sufficiently low (typically at least 10 dB below the minimum IMD product to be measured). One major source of the system IMD is an insufficient isolation between the two sources. This can be improved by increasing the attenuation of A1 and A2, as long as the available level of the input power is sufficient. Alternatively, isolators might be needed. The other source of system IMD is the spectrum analyzer. Note that the level of the signal at the input of the analyzer should be adjusted at least as high as for the final measurement. To reach a sufficiently high level, one might have to bypass the output coupler. If the objective is to measure a large C/I, for instance, 60 dB or higher, the spectrum analyzer must be checked carefully. If there is an excess of system IMD, it can be determined whether it derives from the sources or from the spectrum analyzer by varying the power by a small amount, for instance, 2 dB. If the IMD level varies by the same amount, the IMD derives from the sources, and the isolation between the sources must be improved. If it varies by more than 2 dB, it derives from intermodulation within the spectrum analyzer, and in this case, the level of the measured signal must be lowered. Of course, this might reduce the maximum measurable C/I. Finally, an insufficient isolation between the sources may cause a spectrum asymmetry due to a phase-pulling effect. If, when running a test, there is a doubt that the asymmetry might derive from the measurement system, it is useful to switch the frequencies of the two generators. If the spectrum asymmetry also switches, the asymmetry derives from the measurement system. If it doesn’t, it derives from the DUT by the mechanism described in Section 10.2.5.

10.5  A Simple Quadrature Model The simple quadrature model described in this section is based on a separate computation of the IMD products generated by the amplitude distortion (as described in Section 10.2.1) and by the phase distortion (as described in Section 10.2.3). These products are then combined in quadrature to compute the total IMD. Even though the superposition of effects is not valid in nonlinear systems, the quadrature combining is still correct, because the products are mutually independent. One key assumption we make for this model is that we can transfer parameters from the CW measurement of amplitude and phase distortion to the two-tone computation of IMD by matching the peak values of the wave envelope. For ease of computation, the model is developed here in the form of a spreadsheet (Microsoft Excel) from measurements taken on an amplifier at a specific frequency. We will use the data presented in Section 10.2.2 and run this example with data taken at 8 GHz. The first four columns of Table 10.1 are the measured data of input and output power, in decibels and watts: they effectively define the amplitude distortion of the amplifier. The ein and eout columns are the computed input and output voltages across 50W loads. We fit the data of these last two columns into the third-degree polynomial:

eout = k1 ein + k2 e2in + k3 e3in



(10.45)

31.5300 30.5300 29.5300 28.5300

32.5300

dBm 43.400 43.2900 43.0300 42.5000 41.8400 41.0800 40.1900 39.2900 38.3400 37.4300 36.4200 35.4000 34.4800 33.5400

Pout

-21.7000 -22.7000 -23.7000 -24.7000

0.0070 0.0050 0.0040 0.0030

1.4200 1.1300 0.9000 0.7100

2.2600 1.7900

0.0110 0.0090

-19.6800 -20.7000

W 21.8800 21.3300 20.0900 17.7800 15.2800 12.8200 10.4500 8.4900 6.8200 5.5300 4.3900 3.4700 2.8100

mW 0.2070 0.1640 0.1310 0.1040 0.0840 0.0670 0.0530 0.0430 0.0340 0.0270 0.0210 0.0170 0.0130

dBm -6.8400 -7.8500 -8.8200 -9.830 -10.7600 -11.7200 -12.740 -13.7000 -14.710 -15.6800 -16.7400 -17.7900 -18.7000

Pout

Pin

Pin

Table 10.1  Quadrature Model Computation

0.0260 0.0230 0.0210 0.0180

0.0330 0.0290

V 0.1440 0.1280 0.1150 0.1020 0.0920 0.0820 0.0730 0.0650 0.0580 0.0520 0.0460 0.0410 0.0370

ein

0.0119 0.0106 0.0095 0.0084

0.0150 0.0134

kV 0.0468 0.0462 0.0448 0.0422 0.0391 0.0358 0.0323 0.0291 0.0261 0.0235 0.0209 0.0186 0.0167

eout

0.0150 0.0130 0.0120 0.0100 0.0090

0.0160

V 0.0720 0.0640 0.0570 0.0510 0.0460 0.0410 0.0360 0.0330 0.0290 0.0260 0.0230 0.0200 0.0180

A

45.7900 47.7900 49.7900 51.7900 53.7900

43.7500

dB 18.0700 20.0900 22.0300 24.0500 25.9100 27.8300 29.8700 31.7900 33.8100 35.7500 37.8700 39.9700 41.7900

C/IA

0.0300 0.0200 0.0200 0.0100 0.0100

0.0400

V 3.7000 2.6100 1.8600 1.3200 0.9500 0.6800 0.4800 0.3500 0.2400 0.1700 0.1200 0.0800 0.0600

IA

0.4000 0.2000 0.1000 0.0000 0.0000

0.6000

dgrees 4.8000 4.5000 5.5000 4.4000 4.0000 3.8000 3.2000 2.9000 2.3000 2.0000 1.6000 1.2000 1.0000

PH msr

0.6700 0.5400 0.4200 0.3300 0.2500

0.8400

degrees 4.6200 5.0300 4.9600 4.6200 4.1900 3.6900 3.1700 2.7100 2.2700 1.9000 1.5500 1.2500 1.0400

PH cmt

IP

0.0400 0.0200 0.020000 0.0100 0.0100

0.0500

V 1.1900 1.1500 1.0200 0.8400 0.6900 0.5400 0.4200 0.3200 0.2400 0.1800 0.1300 0.0900 0.0700

I

0.0500 0.0300 0.0200 0.0200 0.0100

0.0700

V 3.8800 2.8500 2.1200 1.5600 1.1800 0.8700 0.6400 0.4700 0.3400 0.2500 0.1800 0.1200 0.0900

C/I

42.2000 44.1000 46.2000 48.3000 50.4000

40.2000

dB 17.6000 19.3000 20.9000 22.5000 24.1000 25.7000 27.4000 29.1000 30.9000 32.7000 34.6000 36.6000 38.3000

P02

29.5300 28.5300 27.5300 26.5300 25.5300

30.5400

dBm 40.4000 40.2900 40.0300 39.5000 38.8400 38.0800 37.1900 36.2900 35.3400 34.4300 33.4200 32.4800 31.4800

238 Linear Power Amplifiers

10.5  A Simple Quadrature Model

239

With eout expressed in kilovolts and ein expressed in volts, the fitting by a leastsquares algorithm results in the following coefficients:



k1 = +0.411

k2 = +1.27

(10.46)

k3 = −13.23

Now we make an important assumption: we postulate that the distortion data of the first six columns—obtained with a single tone—can be matched with the data of a two-tone signal by setting equal peak values. Thus, the distortion corresponding to a single tone of voltage ein is applied to a two-tone signal, where each tone has an amplitude of ein A= (10.47) 2 so that, when the envelope is at its peak, the voltage is indeed ein. Thus, from (10.8),



C Ak1 4k1 (AM) = 20log = 20log 3 IA 3k3 A2 k3 A3 4

(10.48)

(dB)

The corresponding IMD voltage for AM distortion is



3 IA = 1000 k3 A3 4

(10.49)

Thus, we have defined the voltage, as well as the C/I of the IMD product generated by the amplitude distortion. Regarding the phase distortion, the data PHmsr are phase shifts in degrees versus input power measured with a single tone. Since the measurement is imprecise at low-input voltages, and we know that the phase is zero at zero input voltage, better data at low input can be derived from the polynomial:



PHcmt 2 + u3 e3in = u1 ein + u2 ein 10

(the denominator 10 is a scaling factor) (10.50)

The coefficients are computed by a least-squares fit of the ein and PHmsr measured data:

u1 = +0.1932

u2 = +96.56

u3 = −522.8

(10.51)

From (10.31), the amplitude of the first sideband due to phase modulation is

Ip = 1000k1 AJ1 (PHcmt )

(10.52)

where J1 is the Bessel function of the first order and its argument usually is expressed in radians.

240



Linear Power Amplifiers

The total intermodulation product, I, is obtained by combining IA and IP in quadrature: � (10.53) I = IA2 + IP2 Thus the total carrier-to-intermodulation ratio is



C 1000k1 A = 20log10 I I

(dB)



(10.54)

and, on the basis of (10.15) and (10.47), the corresponding output power of the two-tone signal is

P02 = Pout (dBm ) − 3 (dBm)

(10.55)

On the basis of measured amplitude and phase distortions, this simple model computes the IMD performance for a two-tone signal. The model accuracy can be evaluated by comparing Figure 10.5(c) (model) with Figure 10.5(b) (measured data) and Figure 10.6(c) with Figure 10.6(b). In regions where the IMD characteristics don’t show strong irregularity, the agreement is within an acceptable value of about 1 dB. By comparing the values in the C/IA and C/I columns, we see that they differ by about 3 dB: thus, in this case, the amplitude and the phase distortions give approximately equal contributions. In fact, we see the usefulness of this model in quantifying the contribution to the IMD of the phase distortion, which is difficult to evaluate by other means.

10.6  Behavioral Models Nonlinear modeling is a field that has been developing very rapidly in recent years, thanks to the availability of powerful personal computers and, most importantly, of powerful commercial programs designed to run efficiently on such computers. Generally speaking, nonlinear models can be classified in two categories: physical and empirical. In Chapter 4 we described physical models. Although the parameters of these models are usually derived from experiments, the configuration of the model is based on the physics of the device. Behavioral models, instead, are blackbox models: they are empirical and make no assumption about the internal functioning of the device. In practice, they rely exclusively on the measured response at the available ports. Why the interest in behavioral models? Basically for the following reasons: 1. They provide an efficient way to analyze complex systems that would be practically impossible to analyze by detailing all the nonlinear elements; 2. They can be used to analyze the response of a system operating with a variety of input signals; 3. A behavioral model, used in reverse, can be used for a digital linearization technique of power amplifiers, as proposed, for instance, in [15].

10.6  Behavioral Models

241

With the exception of the simplest behavioral model, the Taylor series, all the other models involve very complex mathematical tools, and their treatment is beyond the scope of this book. Thus, here we make only some very simple comments on these models, and we direct the reader to the published literature that is referenced in Sections 10.6.1 through 10.6.2. 10.6.1  Power and Taylor Series

Let’s assume that we know the nonlinear relationship between the input and output RF voltages for a two-port black box:

eout = f(ein )



(10.56)



where ein and eout are the instantaneous input and output voltages, respectively. Then, with a Taylor series, we can describe the function in the vicinity of a quiescent point. If we assume, without any loss of generality, that the quiescent point is at ein= 0 and f(ein) = 0, the original function can be described, for example, by the first three terms of the Taylor series:

eout = k1 ein + k2 e2in + k3 e3in



(10.57)

where

� � d(f ) �� 1 d2 (f ) �� k1 = k2 = � dein �ein =0 2 de2in � ein =0



and the nth term is



� 1 dn (f ) �� kn = n! denin �ein =0

� 1 d 3 (f) �� k3 = � 6 de3in � e

(10.58)

in =0

(10.59)

All the derivatives are computed at ein = 0. We can now apply any kind of input signal and derive the output signal from (10.57), as long as the signal is small. In fact, (10.57) is the simplest behavioral model, and we already used this model in Section 10.2.1 when we analyzed the response for a two-tone signal. This model, although very elementary, has given us a simple and intuitive understanding of mixing effects and, specifically, of intermodulation and signal compression. Unfortunately, however, this type of modeling is very limited. The most obvious limitation is in the level of the signal: the Taylor series describes the function only in the vicinity of the quiescent point, and a substantial deviation from it may result in large errors. We could increase the number of terms in the series, but that might increase the precision, not the useful range. Also, the computational precision of the higher-order derivatives decreases rapidly because of the inevitable uncertainty in the empirical data. The obvious reaction is the following: Why don’t we approximate the function with a high-degree polynomial, and compute the coefficients of the power series by least-squares curve fitting? In this way we wouldn’t have the problems of computing high-order derivatives. The main problem is that

242

Linear Power Amplifiers

the coefficients of the polynomial become ill-defined. For instance, we saw in Section 10.2.1 that the k2 and k3 coefficients determine the level of the second harmonic and the intermodulation, respectively. As we fit the function with a polynomial of increasing degree, the values of k2 and k3 change dramatically, and, in fact, become more and more unstable as we increase the order of the polynomial. Results derived from such coefficients become, in turn, increasingly implausible. Another serious limitation of the power-series model is that it is memoryless. In other words, it cannot describe a reactive circuit that includes capacitors and inductors, and therefore, it cannot model a phase shift or an AM/PM conversion. Clearly, this has serious implications for the computation of the intermodulation distortion. Other limitations are less obvious: as pointed out in [16], a power series cannot model circuits that include cascaded nonlinear elements or any feedback path. 10.6.2  Volterra Series

Most of the limitations of the power series are overcome by the Volterra series model. It can model nonlinear phase responses and can include multiple nonlinear elements and feedback. The only limitation is that the nonlinear elements are described by the Taylor series, and therefore, the model typically is accurate only for weak nonlinearities: it may fail catastrophically if applied near device saturation. However, if applied properly, this model can generally give very accurate results. As implied by the name, the Volterra model is based on a mathematical method devised by the mathematician Vito Volterra (1860–1940), which describes the inputoutput relationship in a nonlinear system. The most common implementation uses nonlinear current sources. For instance, a voltage-controlled nonlinear element is simulated by a linear element connected in parallel with voltage-controlled nonlinear current sources. An introductory explanation of the method can be found in [16, 17] and a more complete description in [2]. The actual implementation of the Volterra series analysis is mathematically quite complex, and a full description of the technique is beyond the scope of this book. However, the recent availability of the Volterra-series analysis as an easy-to-use tool in a commercial nonlinear circuitanalysis program [14] justifies some additional comments for the potential user. The Volterra method is very efficient and can accurately predict the mixing effects due to weak distortion, effects that cannot be accurately simulated by other methods. However, the Volterra method should be used to analyze only circuits that are weakly nonlinear, while the analysis of strongly nonlinear circuits should be carried out using more suitable techniques, such as harmonic balance or time domain. Also, to achieve accurate results, the models used in the Volterra analysis must have a correct description for the derivatives of the nonlinearities. This is not always easy to achieve, and in the experimental phase of the model extraction, it might require substituting some of the standard dc measurements with ac measurements carried out, for instance, at VHF frequency. This allows (1) to minimize errors due to thermal hysteresis or trapping (especially in FETs); and (2) to evaluate the nonlinearity more precisely by measuring its effect, for instance the harmonic output, rather than directly measuring the nonlinear characteristic [18]. In short, the user must be

10.7  Linearization Techniques

243

aware that models that are adequate for harmonic-balance or time-domain analysis might not be precise enough for Volterra analysis. A word of caution: as we already saw in Section 10.6.1, the description of a nonlinearity by means of a high-order polynomial, which has been sometimes applied in Volterra analyses reported in the literature, leads to very serious computational instabilities, which make the results unreliable. 10.6.3  Other Miscellaneous Models

Since the 1970s, many different models have been developed to analyze the performance of power amplifiers under different signal conditions and to optimize the tradeoff between efficiency and linearity. Early models were developed for TWTs, and measured data of AM/AM and AM/PM were the primary inputs for the model development [4−7]. They are quadrature models, where the nonlinear AM/AM and AM/PM characteristics are combined in quadrature. As we mentioned in Section 10.5, the superposition of the quadrature effects is still valid, even in a nonlinear system. The extraction of the parameters is a key step in model development. The excitation of the device might include random-phase multisinusoidal signals [19]. Also, a heuristic algorithm [20] or a hybrid-learning algorithm [21] may be used to identify the model parameters. Models could also be applied in reverse to implement a digital predistortion [22, 23]. Finally, we must refer the reader to the extensive overview of the field of behavioral modeling and the categorization of the various approaches that can be found in [24], while a comparative analysis of four models as applied to two different power amplifiers can be found in [25].

10.7  Linearization Techniques The linearity of an amplifier can be generally improved by any of several linearization techniques that have been proposed. Sometimes, significant improvements can be obtained at a fairly low increase in cost and complexity: this is particularly true for predistortion techniques. Other more complex approaches, such as feedforward approaches, offer performances which cannot be easily achieved by standard means (e.g., by increasing the power of the amplifier). The feedback technique, which is used so often to linearize and stabilize amplifiers at low frequency, is seldom used for microwaves, because it leads to instability. It has been used, however, in a special form: as applied to the RF signal envelope. We will discuss these three techniques in Sections 10.7.1 through 10.7.3. But we should warn the reader that the combinations and variations are innumerable, and, in fact, this field has been exceptionally fertile for patent disclosures. 10.7.1  Predistortion

The underlying idea of predistortion is very simple: the input signal of the nonlinear device—the power amplifier—is predistorted in a fashion which is a mirror image of the distortion induced by the device itself, so that, in principle, the output signal

244

Linear Power Amplifiers

Figure 10.12  (a–c) Principle of predistorton.



comes out undistorted. This is depicted schematically in Figure 10.12. As shown in Figure 10.12(b), the gain of the PA is approximately constant at low input drive, and it drops when the output power approaches saturation. The function of the predistorter (PD) is to introduce a gain that is approximately constant at low drive and increases, for increasing input power, at a rate matching the corresponding drop in the PA. Of course, this is applicable only below saturation: when the PA is near its limit of output power capability and a hard saturation sets in, the predistortion cannot overcome the power limit of the device. In other words, predistortion can improve the P1dB, but cannot change the level of the saturated power. In Section 10.2.3, we have seen that improving the linear power is not enough to improve the IMD performance and that we have to pay close attention to the phase distortion. Thus, for optimal IMD performance, the linearizer must include a provision to correct the phase distortion, as shown in Figure 10.12(c). The linearization process can be carried out also by predistorting a digital signal prior to its upconversion to microwave frequencies. This approach is very powerful, and a great deal of literature is available on this topic. An introductory treatment can be found in [26]. However, this is a topic of digital signal processing and is out of the scope of this book. An element used often for RF predistortion is the Shottky diode, whose I-V characteristic, shown in Figure 10.13, can be expressed as [2]: � � qV h KT (10.60) I(V ) = I0 e −1 where q is the electron charge, K is the Boltzmann constant, T is the absolute temperature, h is an ideality factor ranging from 1.0 (ideal) to, typically, no more then 1.2, and I0 is the reverse-bias current.

10.7  Linearization Techniques

245

Figure 10.13  Diode I-V characteristic.

In the forward-conduction region, the current can be expressed as

I(V ) ≈ I0 e

40V h



(10.61)

Thus, the differential conductance is



40V dI 40 40 I0 e h = I = dV h h

(10.62)

and the differential resistance—see Figure 10.13—is



r=

dV 25h = (W) dI I

(10.63)

where I is expressed in mA. For instance, at small signals, an ideal diode biased at 0.5 mA is seen as a 50W resistor and appears as a decreasing-value resistor at increasing current.

Figure 10.14  Series diode linearizer.

246

Linear Power Amplifiers

Figure 10.15  Circuit schematic for diode large-signal simulation.

The most simple gain linearizer is a diode connected in series on the RF line, as shown in Figure 10.14. As the level of the RF input increases, the voltage across the diode increases, and therefore, so does the current. Thus, the series resistance and the corresponding loss decrease. The simplicity comes at a price: limited gain compensation and no separate phase adjustment. A more interesting configuration can be derived by using the diode in a reflection mode. To understand its operation and to acquire design data, it is useful to start with the analysis of a single diode. This is done here with a large-signal circuit simulator [14]. The circuit schematic is shown in Figure 10.15. The port PS1 is the

Figure 10.16  Diode current versus RF power.

10.7  Linearization Techniques

247

Figure 10.17  (a–e) Diode reflection versus RF power at different values of series resistance and bias voltage.

input port, and the input power is swept from 0 to 20 dBm. The diode I-V characteristic is defined in (10.60) and the capacitance is set to zero, to make the computation results frequency independent. The capacitor C1 is a dc block and the inductor L1 is a choke; both are assumed to be frequency independent. The current-limiting resistor R1 and the bias voltage V1 are set initially at 500W and + 0.8V, respectively. As shown in Figure 10.16, when the RF input power is swept from 0 to 20 dBm, the diode current varies monotonically from 1.5 to 9.0 mA. Figure 10.17(a) shows the corresponding reflection at the input port: the reflection at 20 dBm is 1.7-dB higher than at 0 dBm. We can vary the rate of change for the current, and thereby for the reflection, by changing the resistor: the reflections for a lower value (250W) and a higher value (1000W), are plotted in Figures 10.17(b) and 10.17(c). Similarly,

248

Linear Power Amplifiers

Figure 10.18  (a, b) Single-path reflection linearizer.

we can go back to 500W and vary the bias voltage. Figures 10.17(d) and 10.17(e) show the reflections for a bias voltage of 0.7V and 0.9V, respectively. Thus, by varying the bias voltage and the current-limiting resistor, it is possible to achieve a wide range of slopes and curvatures for the reflection of the diode as a function of the incident power. A convenient configuration for a reflection-type linearizer is shown in Figure 10.18(a). The coupler CPL is a 3-dB quadrature hybrid, such as a Lange coupler. A signal entering port 1 is split into two signals of equal amplitude, feeding two identical diode networks. Each network is like the one shown in Figure 10.15, except for the addition of a bypass capacitor, Cb and an inductor that is adjusted to tune the diode capacitance at the operating frequency. The two equal reflections combine at port 2 (the output port). Because of the nonlinear reflection of the diodes, the magnitude of the transmission coefficient increases with increasing power, as shown schematically in Figure 10.18(b). If the reflections from the two diode networks are identical, both the input and output ports are matched. However, at the expense of some mismatch, a small phase predistortion can be obtained by unbalancing the dc bias and the current in the two diodes. A better control of the phase predistortion is achieved by the configuration of Figure 10.19. The input signal is spilt by a 3-dB quadrature hybrid (for instance, a Lange coupler) forming two channels, I and Q. The I and Q signals are predistorted and recombined by an in-phase coupler, for instance a Wilkinson coupler. As shown in Figure 10.20, it is possible to compensate independently for both

10.7  Linearization Techniques

249

Figure 10.19  Dual path reflection linearizer.

amplitude and phase distortions by adjusting the rate of change of the transmission coefficients in the I and Q channels. Since the intermodulation products in an amplifier are caused by odd-order distortion, it may be useful to eliminate the even-order distortion in the predistorter, so as to avoid unwanted mixing with the fundamental. This can be achieved by replacing each diode with the antiparallel configuration shown in Figure 10.21. Other devices can be used as nonlinear elements for predistortion. For instance, an FET connected in a shunt, as shown in Figure 10.22(a), has been proposed for simple gain predistortion [27]. The alternative configuration of Figure 10.22(b) is another possibility [28], and so is a dual-gate FET in a cascade configuration, due to the gain expansion characteristic of a class B operation [29]. Finally, an HBT in a shunt configuration can also perform as a simple linearizer [30]. When using predistortion linearizers, one of the main challenges is achieving an adequate intermodulation improvement over a sufficiently broad range of output power. For instance, it is relatively easy, even with a very simple linearizer, to achieve a sharp null of the intermodulation at a specific value of power, but this operating condition is rarely acceptable. The key to achieving an optimal dynamic range is to position the linearizer where it can mirror the amplifier characteristic over a wide dynamic range. Thus, for optimal performance, the linearizer must be

Figure 10.20  Phasors in dual path linearizer.

250

Linear Power Amplifiers

Figure 10.21  Antiparallel diode configuration.

often integrated into the amplifier chain, and the very simple configuration of Figure 10.12 is seldom an optimal choice. Another challenge is stability: predistortion is an open-loop process that is not self-adjusting and is very sensitive to any deviation from the optimal conditions. Deviations may come from temperature, RF input power, frequency, or simply aging. Thus, temperature compensation and a very uniform frequency response are usually important requirements in this design. All things considered, even though the predistortion process can produce a very deep null of the intermodulation products, typically the improvement that can be realistically maintained is about 10 dB. For higher improvements, it is advisable to use the feedforward technique described in the following section. 10.7.2  Feedforward Technique

The feedforward linearization technique was invented by H. S. Black [31], who later also invented the feedback technique [32]. The feedback technique found widespread application in the development of all kinds of amplifiers, but the feed-

Figure 10.22  (a, b) FET predistortion elements.

10.7  Linearization Techniques

251

forward technique was initially applied only sporadically, and only much later was rediscovered by Seidel and applied to the development of high-linearity RF amplifiers [33, 34]. Although not as elegant as the feedback technique, the feedforward technique is of interest for microwave amplifiers because it does not induce RF instability. In fact, because of the combined characteristic of very high linearity and wide dynamic range, the feedforward technique has found wide use in linear amplifiers for base stations. The principle of operation is shown in Figure 10.23, as applied here for didactical reasons to the amplification of a two-tone signal. The RF input is divided by a power splitter (Sp). One signal is fed into the main amplifier (MA) and the other is fed into a subtracter (Sb). The output from the main amplifier includes the amplified carriers plus the unwanted intermodulation products. Such products are separated from the carriers by feeding a fraction of the MA output signal, coupled through CPL1, into Sb, where it is compared with the undistorted input signal. The output from Sb is the error signal, which contains the intermodulation products and some residual carriers. This signal is fed into the error amplifier (ER), and the output is reinjected, 180º out of phase, into the signal from the main amplifier through the coupler CPL2. Thus, the combined output signal includes only residual intermodulation products. For this process to work properly, some conditions must be satisfied: 1. To obtain full cancellation in the subtracter and at the output coupler, CPL2, the phase relationship must be maintained over the whole operating bandwidth; thus, the group delays in the two loops must be equalized by the delay lines D1 and D2. 2. The error signal must be amplified without introducing additional distortion; therefore, the EA amplifier must operate in a highly linear mode. Thus, even though the error signal is very low compared with the output signal, the power capability of the error amplifier is often very similar to that of the main amplifier. In practice, the two amplifiers might actually be identical. This, of course, has substantial implications for the overall efficiency and cost of the system.

Figure 10.23  Feedforward linearization.

252

Linear Power Amplifiers

A summary of the design equations and variations of the basic system can be found in [26]. Within the variations, an important category is the one based on multiple nesting. For instance, a single feedforward system can be considered as the main amplifier and can be nested within a second feedforward system. In principle, the process can be repeated as many times as needed to achieve the required performance. Clearly, the practical limitations of this scheme are determined by considerations of system complexity, cost, and efficiency, as well as parameter stability. Alternatively, if the overall system performance is limited by the distortion in the error amplifier, then this amplifier may be replaced by a feedforward system, and, if needed, the nesting can also be repeated. Finally, a simpler variation of the basic system can be implemented by including predistortion in the main amplifier. The improvement in intermodulation performance that can be obtained by applying a feedforward technique depends on many factors specific to a particular application. It is widely recognized, however, that this approach can achieve reliably an IMD cancellation far deeper than what can be practically maintained with predistortion. For instance, while predistortion can be relied on for about 10 dB of cancellation, a single feedforward process can achieve typically 20 dB or more [26]. With multiple loops, the IMD cancellation can be even much higher. Of course, this is obtained at a substantial increase of the system complexity and cost. However, because of limitations in device power capability, the feedforward technique often proved to be the only practical way to achieve very high linearity performance at high power. 10.7.3  Envelope Feedback

As we mentioned in Section 10.6, the RF feedback technique is seldom applied at microwave frequencies, because the rapid rate of change in the phase through the amplifier stages makes it very difficult to maintain the proper phase relationship. The stability in the pass band, and even more out of band, is therefore jeopardized. One solution to the stability problem is to apply feedback only to the envelope of the RF signal. In a very simple configuration, this can be achieved by detecting a sample of the output signal and applying the resultant envelope signal to a modulator located at the input of the amplifier. The decrease in gain due to a gradual saturation of the amplifier can be thus overcome, and the amplitude response is effectively linearized. A similar technique can be applied also to linearize the phase response. We should note that, since the system operates in an open loop, it is very sensitive to the response of the loop. For instance, the gain linearization process is very sensitive to the response of the detector, which can cause substantial problems in the production of amplifiers of this type [26]. An obvious extension of this approach is to compare the input signal with the output signal, derive amplitude and phase errors, and apply a correction at the input of the amplifier. This scheme, in a simplified form, is drawn in Figure 10.24. The elements A and P are, respectively, the amplitude and phase comparators whose output signals control amplitude and phase modulators located at the input of the amplifier. By making direct comparison of the input and output signals, this configuration achieves higher stability from variations of the system parameters than what can be achieved with the open-loop system mentioned above. In

10.8  Channel Interference: APR, NPR, M-IMR

253

Figure 10.24  Envelope feedback.

addition, it corrects for both amplitude and phase distortions; thus, in principle, it has very desirable characteristics. However, in this type of system, a significant difficulty resides in achieving a sufficiently wide modulation bandwidth. We should keep in mind that an inadequate modulation bandwidth gives rise to the memory effects and spectrum asymmetry we discussed in Section 10.2.5. So far, modulation frequencies of 20 kHz and 1 MHz have been reported in different system configurations [35, 36].

10.8  Channel Interference: ACPR, NPR, M-IMR The measurement of intermodulation by using a two-tone signal is simple and widely used in the characterization of amplifiers; however, such a simple signal does not model the actual operation of typical systems accurately. In fact, an actual signal is much more akin to white noise. Also, the most detrimental effect of intermodulation is interference between adjacent channels. This effect is often quantified by the adjacent channel power ratio (ACPR), and its measurement is outlined in Figure 10.25. The ACPR is defined as the ratio of the power in a certain bandwidth

Figure 10.25  ACPR measurement.

254

Linear Power Amplifiers

Figure 10.26  NPR measurement.

away from the channel to the power in a bandwidth within the channel. The measurement bandwidths and the frequency offset from the center of the channel are usually defined by the measurement standard and are often specific to a particular application. The noise power ratio (NPR) is another measurement of intermodulation. The channel is loaded at its nominal power with a signal (typically white noise) that is deeply notched at the center of the channel by a filter. When the signal is run through the amplifier, the intermodulation causes power to spill into the notched area. As shown in Figure 10.26, NPR is the ratio of the power in the notch to the power of the signal in the channel. In some cases, the channel may be loaded with multiple tones. This is the case, for instance, of a base-station transmitter or a repeater for multiple TV signals. As

Figure 10.27  M-IMR measurement.

10.8  Channel Interference: APR, NPR, M-IMR

255

shown in Figure 10.27, the multitone intermodulation ratio (M-IMR) is the ratio of the power of the highest intermodulation product to the power of a tone in the channel. On the basis of some simplified amplifier characteristics, it is possible to derive equivalency ratios between the two-tone intermodulation measurement and the more complex measurements, such as ACPR, NPR, and M-IMR [37, 38]. The equivalency is only approximate, because different signals—the two-tone versus other more complex signals which have different peak-to-average ratios and different power probabilities—differ in the way they are affected by nonlinearities. Because of these different signal characteristics, an amplifier whose performance has been optimized with a two-tone signal most often will have to be reoptimized when used with a different signal, but generally the readjustment is only minor.

References   [1] Simons, K. A., “The Decibel Relationship Between Amplifier Distortion Products,” IEEE Proc., Vol. 58, No. 7, July 1970.   [2] Maas, S. A., Non-Linear Microwave and RF Circuits, Norwood, MA: Artech House, 2003.   [3] Cripps, S. C., RF Power Amplifiers for Wireless Communications, Norwood, MA: Artech House, 1999.   [4] Shimbo, O., “Effects of Intermodulation, AM–PM Conversion, and Additive Noise in Multicarrier TWT Systems,” IEEE Proc., Vol. 59, No. 2, February 1971, pp. 230–238.   [5] Hetrakul, P., and D. P. Taylor, “Nonlinear Quadrature Model for a Travelling-Wave-TubeType Amplifier,” Electronics Letters, 1975, Vol. 11, No. 2, January 23, p. 50.   [6] Abuelma’atti, M. T., “Frequency-Dependent Non-Linear Quadrature Model for TWT Amplifiers,” IEEE Trans. on Communications, Vol. Com-32, No. 8, August 1984, pp. 982–986.   [7] Saleh, A., “Frequency-Independent and Frequency-Dependent Nonlinear Models of TWT Amplifiers,” IEEE Trans. Communication, Vol. COM-29, No. 11, November 1981, pp. 1715–1720.   [8] Sechi, F. N., “Linearized Class-B Transistor Amplifiers,” IEEE J. of Solid-State Circuits, Vol. SC-11, No. 2, April 1976, pp. 264–270.   [9] Carvalho, N. B., and J. C. Pedro, “A Comprehensive Explanation of Distortion Sideband Asymmetries,” IEEE Trans. on Microwave Theory and Techniques, Vol. 50, No. 9, September 2002, pp. 2090–2101. [10] McIntosh, P. M., and C. M. Snowden, “The Effect of a Variation in Tone Spacing on the Intermodulation Performance of Class A & Class AB HBT Power Amplifiers,” IEEE MTT-S Int. Symp. Digest, 1997, pp. 371–374. [11] Vuolevi, H. K., et al., “Measurement Technique for Characterizing Memory Effects in RF Power Amplifiers,” IEEE Trans. on Microwave Theory and Techniques, Vol. 49, August 2001, pp. 1383–1389. [12] Takenaka, I., et al., “Improvement of Intermodulation Distortion Asymmetry Characteristics with Wideband Microwave Signals in High Power Amplifiers,” IEEE Trans. on Microwave Theory and Techniques, Vol. 56, No. 6, June 2008, pp. 1355–1365. [13] Sechi, F. N., “Design Procedure for High-Efficiency Linear Microwave Power Amplifiers,” IEEE Trans. on Microwave Theory and Techniques, Vol. 28, No. 11, November 1980, pp. 1157–1163. [14] AWR Microwave Office, Applied Wave Research, El Segundo, California, http://www. awrcorp.com, last accessed April 28, 2009.

256

Linear Power Amplifiers [15] Roblin, P., et al., “Frequency-Selective Predistortion Linearization of RF Power Amplifiers,” IEEE Trans. on Microwave Theory and Techniques, Vol. 56, No. 6, January 2008, pp. 65–75. [16] Maas, S. A., “Analysis and Optimization of Nonlinear Microwave Circuits by VolterraSeries Analysis,” Microwave Journal, April 1990, pp. 245–251. [17] Maas, S. A., “Applying Volterra-Series Analysis,” Microwaves & RF, May 1999, pp. 55– 66. [18] Maas, S. A., and A. Crosmun, “Modeling the Gate I-V Characteristic of a GaAs MESFET for Volterra-Series Analysis,” IEEE Trans. on Microwave Theory and Techniques, Vol. 37, No. 7, July 1989, pp. 1134–1136. [19] Rolain, Y., et al., “Experimental Characterization of the Nonlinear Behavior of RF Amplifiers,” IEEE Trans. on Microwave Theory and Techniques, Vol. 54, August 2006, pp. 3209–3218. [20] Gilabert, P. L., et al., “Heuristic Algorithms for Power Amplifier Behavioral Modeling,” IEEE Microwave and Wireless Components Letters, Vol. 17, No. 10, October 2007, pp. 715–717. [21] Zhai, J., et al., “Dynamic Behavioral Modeling of Power Amplifiers Using ANFIS-Based Hammerstein,” IEEE Microwave and Wireless Components Letters, Vol. 18, No. 10, October 2008, pp. 704–706. [22] Safari, N., et al., “An Approximation of Volterra Series Using Delay Envelopes, Applied to Digital Predistortion of RF Power Amplifiers With Memory Effects,” IEEE Microwave Wireless Components Letters, Vol. 18, No. 2, February 2008, pp. 115–117. [23] Zhu, A., et al., “Digital Predistortion for Envelope-Tracking Power Amplifiers Using Decomposed Piecewise Volterra Series,” IEEE Trans. on Microwave Theory and Techniques, Vol. 56, No. 10, October 2008, pp. 2237–2247. [24] Pedro, J. C., and S. A. Maas, “A Comparative Overview of Microwave and Wireless Power-Amplifier Behavioral Modeling Approaches,” IEEE Trans. on Microwave Theory and Techniques, Vol. 53, No. 4, April 2005, pp. 1150–1163. [25] Isaksson, M., D. Wisell, and D. Rönnow, “A Comparative Analysis of Behavioral Models for RF Power Amplifiers,” IEEE Trans. on Microwave Theory and Techniques, Vol. 54, January 2006, pp. 348–359. [26] Kenington, P. B., High Linearity RF Amplifier Design, Norwood, MA: Artech House, 2000. [27] Tsai, J.-H., et al., “Design and Analysis of a 44-GHz MMIC Low-Loss Built-In Linearizer for High-Linearity Medium Power Amplifiers,” IEEE Trans. on Microwave Theory and Techniques, Vol. 54, No. 6, June 2006, pp. 2487–2496. [28] Katz, A., S. Moochalla, and J. Klatskin, “Passive FET MMIC Linearizers for C,X an Ku Band Satellite Applications,” IEEE MTT-S Int. Microwave Symp. Digest, 1993, pp. 353– 356. [29] Kim, J., et al., “A New ‘Active’ Predistorter With High Gain and Programmable Gain and Phase Characteristics Using Cascode-FET Structures,” IEEE Trans. on Microwave Theory and Techniques, Vol. 50, No. 11, November 2002, pp. 2459–2466. [30] Yamanouchi, S., et al., “Analysis and Design of a Dynamic Predistorter for WCDMA Handset Power Amplifiers,” IEEE Trans. on Microwave Theory and Techniques, Vol. 55, No. 3, March 2007, pp. 493–503. [31] Black, H. S., “Translating System,” U. S. Patent 1,686,792, Issued October 9, 1928. [32] Black, H. S., U. S. Patent 2,102,671, Issued December 1937. [33] Seidel, H., H. R. Beurrier, and A. N. Friedman, “Error Controlled High Power Linear Amplifiers at VHF,” The Bell System Technical Journal, Vol. 47, May/June 1968, pp. 651– 722. [34] Seidel, H., “A Feedforward Experiment Applied to an L-4 Carrier System Amplifier,” IEEE Trans. on Communication Technology, Vol. COM-19, No. 3, June 1971, pp. 320–325.

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[35] Cardinal, J.-S., and F. M. Ghannouchi, “A New Adaptive Double Envelope Feedback (ADEF) Linearizer for Solid State Power Amplifiers,” IEEE Trans. on Microwave Theory and Techniques, Vol. 43, No. 7, July 1995, pp. 1508–1515. [36] Park, H.-M., et al., “A Predistortion Linearizer Using Envelope-Feedback Technique with Simplified Carrier Cancellation Scheme for Class-A and Class-AB Power Amplifiers,” IEEE Trans. on Microwave Theory and Techniques, Vol. 58, No. 6, June 2000, pp. 898–904. [37] Pedro, J. C., and N. B. De Carvalho, “On the Use of Multitone Techniques for Assessing RF Components’ Intermodulation Distortion,” IEEE Trans. on Microwave Theory and Techniques, Vol. 47, No. 12, December 1999, pp. 2393–2402. [38] Carvalho, N. B., and J. C. Pedro, “Compact Formulas to Relate ACPR and NPR to TwoTone IMR and 1P3,” Microwave Journal, December 1999, pp. 70–84.

C h a p t e r 11

Special Power Amplifiers

11.1  Doherty Amplifier In 1936, W. H. Doherty proposed a scheme for linear power amplifiers that was based on electrically modulating the load impedance of a power amplifier to achieve a linear operation with high efficiency over a wide range of output powers [1]. The scheme is well conceived and remarkably elegant in its simplicity. The principle of operation is described here with the aid of a diagram shown in Figure 11.1. The two generators represent two separate amplifiers. The main amplifier is connected to the output load, R/2, through an impedance-inverting network. An auxiliary amplifier is directly connected to the load resistor, and its function is to electrically modulate the output load as it is seen by the main amplifier. We now make some assumptions regarding the amplifiers: 1. Both amplifiers have identical peak-power capability and deliver the maximum output power when loaded with impedance equal to R. 2. The peak output voltage from the main amplifier is constant and is directly related to the bias voltage, while the bias current is inversely proportional to the load resistance. Thus, when the load resistance is varied from R to 2R, both the bias current and the output power are reduced by a factor of 2, so that the efficiency remains unchanged. 3. When the RF level is below a certain threshold and the auxiliary amplifier is not excited, its output impedance is an open circuit. 4. Both amplifiers are fed from a single source, but the auxiliary amplifier is inactive until the amplitude of the RF signal is high enough to begin saturating the main amplifier. At this point, the auxiliary amplifier is gradually turned on until it reaches its full output power. We turn now our attention to Figure 11.1. At low input power, the auxiliary amplifier is off, and its output looks like an open circuit. The load resistor, R/2, is transformed by the impedance inverter into a 2R load; thus, as noted in the second point in the preceding list, the main amplifier still can operate efficiently at a reduced level of output power. When the RF level reaches the threshold, the auxiliary amplifier is turned on and delivers power to the load. The change is viewed by the main amplifier as a change in load impedance. This can easily be seen by noting that a generator is equivalent to a negative resistor, as represented schematically in Figure 11.2. The standard convention for a generator calls for the current to be 259

260

Special Power Amplifiers

Figure 11.1  Principle of operation of the Doherty amplifier.

positive when exiting the positive-voltage terminal. On the other hand, for a passive component, the current is positive when entering the positive terminal. Thus, if we adopt the convention used for a passive component, we see a generator as a negative resistor of value V/I. When this small negative conductance is added in parallel to R/2, the overall resistance increases and, through the impedance inverter, the load impedance presented to the main amplifier decreases. This has a double effect: the bias current (and therefore the output power) of the main amplifier increases, and the power generated by the auxiliary amplifier is added into the output load. The process is complete when the RF level is such as to fully turn on the auxiliary amplifier. At this point, the amplifier delivers its full output power at voltage V and current I, such that V/I=R. The voltage and current are seen as a negative resistance in parallel with the output load. By simply adding the respective conductances, as shown in Figure 11.3, it is easy to see that the overall resistance is indeed R. When this resistance is seen through the impedance inverter, it still remains equal to R. Thus, at full drive, both amplifiers operate into their optimal load impedance R and deliver their full output power. Also, when the contribution of the auxiliary amplifier is properly phased in, the operation is linear and remains efficient over a wide range of power levels. The improvement in efficiency resulting from this configuration is outlined schematically in Figure 11.4 [2]. The standard-configuration line indicates the theoretical

Figure 11.2  Negative resistance equivalency of a generator.

11.1  Doherty Amplifier

261

Figure 11.3  Output load modulation.

efficiency of the two class B amplifiers combined in a standard configuration, for instance, with quadrature couplers. The efficiency reaches a maximum of 78% at full power and decreases with increased backoff. In contrast, the Doherty configuration is twice as efficient at low output power (high backoff), because it provides the power with just one amplifier. The efficiency reaches 78% when the main amplifier operates at full output, namely at 6 dB backoff (3 dB because only the main amplifier is active and an additional 3 dB because both current and power are cut in half, while the load is 2R). At lower backoff (between 6 and 0 dB) the efficiency initially decreases, as the auxiliary amplifier first turns on, but then recovers and again reaches the 78% mark when both amplifiers work at full power. A key component for the Doherty operation is the somewhat mysterious impedance-inverting network. In fact, it is a common device, in most cases a l /4 transformer. The classic equation for a l /4 transformer is

R1 R2 = Z20



Figure 11.4  Efficiency improvement.

(11.1)

262

Special Power Amplifiers

where R1 and R2 are the input and output impedances and Z0 is the characteristic impedance of the line. If the load impedance is

R2 = nR and Z0 = R, then the input impedance is R1 =

1 R n

(11.2)

An important observation is that the phase shift through the impedance-inverting network is invariant with the impedance loading, thus the active-load modulation does not induce a phase modulation, which otherwise would seriously damage the linearity response. The impedance-inverting network can be made more compact by replacing the l /4 transformer with any of the equivalent lumped-element configurations described in Section 7.4. A schematic of the amplifier configuration, as derived from the principle of operation of Figure 11.1, is shown in Figure 11.5. The impedance, R, is set to the familiar value of 50W, and a 35W, l /4 transformer provides the load resistance R/2 = R1 = 25W. The impedance-inverting network is a 50W, l /4 line, thus,

R ≤ R2 ≤ 2R

(11.3)

A l /4 line at the input of the auxiliary amplifier compensates the phase shift of the inverting network, and an input signal divider feeds the two separate amplifying channels. We should warn that the simplicity of the configuration in Figure 11.5 is deceptive. Specifically, connecting two generic class B amplifiers does not necessarily provide a Doherty mode of operation. For that to take effect, a number of conditions must be satisfied: 1. The main amplifier, when loaded with an impedance of 2R (e.g., 100W) must operate at ½ of the nominal current, while delivering ½ of its nominal power at the maximum efficiency. 2. The auxiliary amplifier, when not active, must be seen at the output as an open circuit. 3. The auxiliary amplifier must be inactive when the RF input level is below a certain threshold.

Figure 11.5  Schematic of Doherty configuration.

11.2  Chireix Amplifier

263

The original configuration was conceived for vacuum tubes, which, compared with solid-state devices, have rather ideal characteristics; none of these conditions are easily satisfied with solid-state devices. This is in fact the challenge in designing a Doherty amplifier. However, despite (or because of) the challenge, the Doherty configuration has been the subject of a very large number of publications, too many to list here, and applied often to wireless communication: see, for instance, [3–14]. In these amplifiers, the active devices are often GaAs FETs or PHEMTs. A device that is probably better suited for the Doherty configuration, however, is the GaN HEMT, because its high-voltage breakdown allows easier operation in class B [15–17]. The Doherty configuration has been applied to the demanding requirements of base-station amplifiers, as reported in [16, 17]. The Doherty configuration has also been applied in conjunction with other linearization techniques, such as feedforward [18], analog predistorter [19], or envelope tracking [20]. Finally, a nested architecture can also be used, where, for instance, the main amplifier is, by itself, in a Doherty configuration.

11.2  Chireix Amplifier Let’s consider the configuration of Figure 11.6. Two identical amplifiers are driven by two RF signals of identical amplitude, but different phase. More specifically, the output of the first amplifier is delayed by the angle j, while the output of the second amplifier is advanced by the same angle. If we now subtract the two signals (for instance, by means of a transformer) the resultant RF signal has constant phase, but its amplitude is modulated by j. This can be proven easily, either by trigonometrical derivations or by a simple vector addition, as shown in Figure 11.7. In the figure, vectors V1 and V2 have equal amplitude, but opposite phases with respect to the jaxis. By adding V1 to -V2, thereby subtracting the two signals, we obtain the vector VL, whose phase is invariant, but whose amplitude varies as sin j:

VL = 2V1 sinj

(11.4)

The amplitude of the envelope is controlled by the angle j, and it can vary from zero at j = 0 to the maximum value

VLP = 2V1 at j = 90

Figure 11.6  Principle of outphasing amplitude modulation.

264

Special Power Amplifiers

Figure 11.7  Outphasing vector diagram.

The angle j can be expressed as

j = sin−1

VL VLP

(11.5)

Note that, although the output signal is amplitude modulated, there is no requirement on the linearity of the amplifiers, which, in fact, can be operated in a highly efficient, saturated mode. As a result, this approach to amplitude modulation by signal outphasing can lead to a highly linear, yet highly efficient operation. The outphasing technique was first described by H. Chireix in a 1935 paper [21], as it was applied to the high-power transmitter of the Paris AM broadcasting station. Later, the same technique was reproposed by Cox as linear amplification with nonlinear components, under the acronym LINC [22]. The schematic for an example of implementation of this technique is shown in Figure 11.8 [23, 24]. The input signal is decomposed by the signal component separator (SCS) into two constant envelope signals having identical amplitude and opposite phase shift. The two output signals from the amplifiers are fed into the output load through two l /4 transformers. The signals are then combined at the output load RL. Because they arrive at the load with different phases, the signals, in fact, modulate the load impedance.

Figure 11.8  Outphasing amplifier.

11.2  Chireix Amplifier

265

The load seen though the transformer can be expressed by the admittances

Y3 =

2RL VL 2RL (sin j + j cos j ) = 2 sin j (sin j + j cos j ) 2 V Z0 LP Z0

(11.6)



Y4 =

2RL VL 2RL (sin j − j cos j ) = 2 sin j (sin j − j cos j ) 2 V Z0 LP Z0

(11.7)

Thus the resistive and the reactive components are

G3 =



2RL Z20

sin2 j

G4 = G3

and B3 =

2RL 1 sin 2j Z20 2

and B4 = −B3

(11.8)

(11.9)

If we now normalize the admittances by the factor

2RL



Z20



we obtain



G�3 = sin2 j G�4 = G�3

and

B�3 =

1 sin 2j 2

and B�4 = −B�3

(11.10)

(11.11)

These components are plotted in Figure 11.9. The resistive component varies monotonically, as a function of the outphase angle, while the reactive component peaks at j = 45º. Clearly, outphasing results in a modulation of the load impedances. Specifically, the impedances vary while maintaining mirror symmetry: the resistive components are always identical, while the reactive components are identical in magnitude, but always opposite in sign. The obvious next step is then to compensate the reactive part of the load impedances by connecting susceptances in shunt at the output of the amplifiers, as shown in Figure 11.8. From (11.8), the value of the susceptance is computed as



RL

(11.12) sin 2j0 Z20 where j0 is the angle at which the total susceptance is zero. This tuning susceptance must be negative (inductive) for PA1 and positive (capacitive) for PA2. Thus, the normalized load admittances at ports 1 and 2 are defined by

BS =

G�1 = sin2 j G�2 = sin2 j

1 (sin 2j − sin 2j0 ) 2 1 and B�2 = (−sin 2j + sin 2j0 ) 2 and B�1 =

266

Special Power Amplifiers

Figure 11.9  Amplifier output-load admittance.

One important parameter still to be determined is the overall efficiency of the amplifier. For this, generally we’ll follow the Chireix approach. Not surprisingly, Chireix analyzes the system with the tools of power engineering, computing the parameters of the system on the basis of apparent power (A), active (real) power (Wr) and reactive (imaginary) power (Wi); the electrical machine (the vacuum tube) is defined in terms of its apparent power, and all the loads are defined in terms of active power and reactive power. Thus, for instance, a 100-kVA vacuum tube is characterized by its capability to generate 10 kV (defined by the electrodes’ spacing) with 10A (defined by the cathode), irrespective of the relative phase between the voltage and the current. How efficiently the machine is used is determined by the load. Thus, the power factor is defined as:

h=

Wr |A|

where

A = Wr + jWi

(11.13)

Then Chireix makes the assumption that the dc power is equal to A, which is a rather rough approximation. Now, however, (11.3) defines the efficiency of the system, which is our objective. Rather than dealing with powers, it is more convenient for us to use the identical definition of h in terms of load-impedance parameters:

h=

G G =� |Y| G2 + B2

(11.14)

11.2  Chireix Amplifier

267

Figure 11.10  Amplifier efficiency versus outphasing angle and tuning.

The efficiency, as defined by (11.14), is plotted in Figure 11.10, with the normalized parameters:

G = G�1

and B = B�1

(11.15)

The tuning, shown here for the 15° and 30° angles, greatly improves the efficiency, particularly at high-power levels (high values of j) where efficiency is most important. We should keep in mind that the efficiency, as defined in (11.14), relates only to the level of utilization of the available power by the load. An overall efficiency computation must include the efficiency characteristic of the amplifier; for instance, a class B amplifier has an efficiency no higher then 0.78. The total efficiency is then computed as

hT = h × hA

(11.16)

where hA is the efficiency of the power amplifiers. One important component that we still have to discuss is the SCS, which separates the input signal into two constant-envelope, phase-modulated components. The first step for its implementation is to recover the modulation and the carrier. The modulation signal may be recovered by a diode detector [25], and the carrier may be recovered by a limiter, preferably followed by a phase-locked oscillator. Then, the two phase-modulated components are derived from a subsequent

268

Special Power Amplifiers

modulation process. A number of SCS schemes have been devised specifically for application in LINC systems [26–28] and a number of implementations of the Chireix amplifier have been reported in the literature for low-power cell phones, as well as for high-power base stations [29–31]. In summary, the main advantage of the Chireix configuration derives from operating the amplifiers with constant envelope signals, where the signals are amplified efficiently in a saturated mode of operation. Also, unlike the Doherty scheme, there is no strict requirement on the output impedance of the amplifiers or their mode of operation; thus, the Chireix scheme can be implemented with rather generic amplifiers. A substantial difficulty resides in the implementation of the SCS. Beside the obvious additional complexity of the system, there is a problem in maintaining good linearity in the demodulation and subsequent modulation processes. As a result, the configuration of Figure 11.8, which we have used for didactical purposes, may not be an optimal solution. A more advantageous architecture is that of an amplifier integrated with the modulation system, where the baseband signal (either in analog or digital format) and the local oscillator are available in their original form and can be directly applied to generate the phase-modulated components [25].

11.3  Kahn EER Amplifier Another scheme for efficiently amplifying an amplitude-modulated RF signal is the one based on the envelope elimination and restoration (EER) technique that was proposed in 1952 by Kahn [32]. The principle of operation is shown in Figure 11.11. The RF input signal is divided by the power splitter (S) and fed into two branches. The signal in the upper branch is detected and the baseband (BB) modulation signal is fed into a pulse-width modulator (PWM). The output of the modula-

Figure 11.11  EER principle of operation.

11.3  Kahn EER Amplifier

269

tor is a series of pulses, whose period is short with respect to the modulation period, and whose length is proportional to the amplitude of the modulation signal. After removing the high-frequency components with a low-pass filter (LP), the signal is a high-efficiency amplified replica of the BB signal, which, in turn, modulates the bias voltage of the RF power amplifier (PA). In the lower branch, the RF signal goes through a hard limiter, which removes the amplitude modulation. The output signal from the limiter, now containing only the phase information, is delayed and then amplified by the PA, which also restores the modulation on the RF signal. The PA, although modulated, is designed to operate in a highly efficient, saturated mode. The network DLY is adjusted to ensure that the group-delay of the BB branch is identical to that of the RF branch, so that the signal is reconstructed properly both in amplitude and phase. The equalization of the time delay between the BB channel and the RF channel is important to be able to amplify signals that contain phase information. We must note that this is the case for single sideband signals, even if they are only AM modulated. And even the simple two-tone signal we have considered in Section 10.2.1 and displayed in Figure 10.1 carries phase information, because the phase reverses at the beginning of every modulation cycle. Thus, without phase equalization, only the simplest signals can be amplified with low distortion using this scheme. An important factor in this scheme is that the group-delay in the BB branch can be exceedingly large when compared to the delay in the RF channel [25]. Typically, the group-delay in the BB branch is on the order of 10–20 ms, most of it due to the LP filter which recovers the modulation signal, while the group delay in the RF branch is on the order of a few nanoseconds. If we should attempt equalization by inserting a Teflon-loaded coaxial cable in the RF channel, even a delay of just 10 ms would require a length of more than 2 km. Thus, the simple scheme of Figure 11.11 is not useful and, in fact, practical implementations are of the type shown in Figure 11.12 [32, 33]. The main difference is that the input signal enters at the IF frequency, where the delay can be implemented in economical and practical ways, for instance, by cascading op-amps in an all-pass network configuration [33]. The

Figure 11.12  EER amplifier.

270

Special Power Amplifiers

system now must include a local oscillator (LO) and an up-converter (UP), followed by a bandpass filter (BP), which selects the desired mixing product. Otherwise, the operation of the system is the same as described above. Another factor to consider in the design of an EER system is the bandwidth of the BB branch. Since the modulator may have to supply rather large currents if the PA is of high power, the practical bandwidth might be limited to only a few MHz. This inevitably limits the instantaneous RF bandwidth as described in Section 10.2.5. In fact, even if the bandwidth of the RF branch is much larger than the one of the modulation branch, the extra band cannot be utilized in an instantaneous mode. This is because any additional signal in the RF band introduces modulation frequencies higher than what the BB circuitry can support, which in turn results in strong intermodulation and spectrum asymmetry. As described in Section 10.2.5, this limitation of the RF instantaneous bandwidth applies to any amplifier with limited-modulation bandwidth, although it is particularly severe in the EER scheme.

References   [1] Doherty, W. H., “A New High Efficiency Power Amplifier for Modulated Waves,” IRE Proc., Vol. 24, September 1936, pp. 1163–1182.   [2] Grebennikov, A., RF and Microwave Power Amplifier Design, New York: McGraw Hill, 2005.   [3] Cripps, S. C., RF Power Amplifiers for Wireless Communications, Norwood, MA: Artech House, 1999.   [4] Srirattana, N., et al., “Analysis and Design of a High-Efficiency Multistage Doherty Power Amplifier for Wireless Communications,” IEEE Trans. on Microwave Theory and Techniques, Vol. 53, No. 3, Part 1, March 2005, pp. 852–860.   [5] Kim, J., et al., “Analysis of Fully Matched Saturated Doherty Amplifier with Excellent Efficiency,” IEEE Trans. on Microwave Theory and Techniques, Vol. 56, February 2008, pp. 328–338.   [6] Park, H., et al., “A New Compact Load Network for Doherty Amplifiers Using an Imperfect Quarter-Wave Line,” IEEE Trans. on Microwave Theory and Techniques, November 2007, Vol. 55, pp. 2313–2319.   [7] Messaoudi, N, et al., “A Comparative Study of Power Amplifiers’ Sensitivity to Load Mismatch: Single Branch vs. Doherty Architectures,” Electrical and Computer Engineering. 2007. CCECE 2007. April 22–26, 2007, pp. 1543–1546.   [8] Ahn, G., et al., “Design of a High-Efficiency and High-Power Inverted Doherty Amplifier,” IEEE Trans. on Microwave Theory and Techniques, Vol. 55, No. 6, Part 1, June 2007, pp. 1105–1111.   [9] Kim, W.-J., et al., “Piecewise Pre-Equalized Linearization of the Wireless Transmitter with a Doherty Amplifier,” IEEE Trans. on Microwave Theory and Techniques, September 2006, Vol. 54, pp. 3469–3478. [10] Jeong, H. T., I. S. Chang, and C. D. Kim, “Compensation Method for a Nonlinear Amplifier Using the Gain Expansion Phenomenon in a Doherty Amplifier,” IEEE Trans. on Microwave Theory and Techniques, Vol. 54, April 2006, pp. 1425–1430. [11] Hammi, O., et al., “Design and Performance Analysis of Mismatched Doherty Amplifiers Using an Accurate Load—Pull-Based Model,” IEEE Trans. on Microwave Theory and Techniques, Vol. 54, August 2006, pp. 3246–3254. [12] Crescenzi, E. J., et al., “60-Watt Doherty Amplifiers Using High Gain 2-Stage Hybrid Amplifier Modules,” IEEE MTT-S Int. Symp. Digest, 2005, p. TH1B.

11.3  Kahn EER Amplifier

271

[13] Iwamoto, M., et al., “An Extended Doherty Amplifier with High Efficiency Over a Wide Power Range,” IEEE Trans. Microwave Theory Tech., Vol. MTT-49, Dec. 2001, pp. 2472–2479. [14] Cho, K.-J., et al., “40W Gallium-Nitride Microwave Doherty Power Amplifier,” IEEE MTT-S Int. Symp. Digest, June 2006, pp. 1895–1898. [15] Lees, J., et al., “Experimental Gallium Nitride Microwave Doherty Amplifier,” Electronics Letters, Vol. 41, No. 23, November 10, 2005, pp. 1284–1285. [16] Takenaka, I., et al., “A Distortion-Cancelled Doherty High-Power Amplifier Using 28V GaAs Heterojunction FETs for W-CDMA Base Stations,” IEEE Trans. on Microwave Theory and Techniques, Vol. 54, December 2006, pp. 4513–4521. [17] Li, N., H. Sano, and S. Sano, “An 80W 2-Stage GaN HEMT Doherty Amplifier with 5O-dBc ACIR, 42% Efficiency 32-dB Gain with DPD for W-CDMA Base Station,” IEEE MTT-S Int. Microwave Symp. Digest, June 3–8, 2007, pp. 1259–1262. [18] Cho, K.-J., et al., “A Highly Efficient Doherty Feedforward Linear Power Amplifier for W-CDMA Base-Station Applications,” IEEE Trans. on Microwave Theory and Techniques, Vol. 53, No. 1, January 2005, pp. 292–300. [19] Lee, Y.-S., S.-Y. Lee, and Y.-H. Jeong, “Linearity Improvement of Doherty Amplifier with Analog Predistorter for WCDMA Applications,” 36th European Microwave Conf., 2006. September 10–15, 2006, pp. 1205–1208. [20] Moon, J., et al., “Analysis and Design of a High-Efficiency Multistage Doherty Power Amplifier for Wireless Communications. A Wideband Envelope Tracking Doherty Amplifier for WiMAX Systems,” IEEE Microwave and Wireless Components Letters, Vol. 18, No. 1, January 2008. pp. 49–51. [21] Chireix, H., “High Power Outphasing Modulation,” IRE Proc., Vol. 23, November 1935, pp. 1370–1392. [22] Cox, D.C., and R. P. Leck, “Component Signal Separation and Recombination for Linear Amplification Using Nonlinear Components,” IEEE Trans. on Communication, Vol. COM-23, November 1975, pp. 1281–1287. [23] Raab, F. H., “Average Efficiency of Outphasing Power-Amplifier Systems,” IEEE Trans. on Communication, Vol. COM-33, October 1985, pp. 1094–1099. [24] Grebennikov, A., RF and Microwave Power Amplifier Design, New York: McGraw Hill, 2005, pp. 77–108. [25] Kenington, P. B., High Linearity RF Amplifier Design, Norwood, MA: Artech House, 2000. [26] Cox, D. C., and R. P. Leck, “Component Signal Separation and Recombination for Linear Amplification Using Nonlinear Components,” IEEE Trans. on Communication, Vol. COM-23, November 1975, pp. 1281–1287. [27] Cox, D.C., and R. P. Leck, “A VHF Implementation of a LINC Amplifier,” IEEE Trans. on Communication, Vol. COM-24, Sept. 1976, pp. 1018–1022. [28] Rustako, A. J., and Y. S. Yeh, “A Wide-Band Phase-Feedback Inverse-Sine Phase Modulator with Application Toward a LINC Amplifier,” IEEE Trans. on Communication, Vol. COM-24, Oct.1976, pp. 1139–1143. [29] Birafane, A., and A. B. Kouki, “Phase-Only Predistortion for LINC Amplifiers with Chireix-Outphasing Combiners,” IEEE Trans. on Microwave Theory and Techniques, Vol. 53, June 2005, pp. 2240–2250. [30] Hakala, I., et al., “A 2.14-GHz Chireix Outphasing Transmitter,” IEEE Trans. on Microwave Theory and Techniques, June 2005, Vol. 53, pp. 2129–2138. [31] Huttunen, A., and R. Kaunisto, “A 20-W Chireix Outphasing Transmitter for WCDMA Base Stations,” IEEE Trans. on Microwave Theory and Techniques, Vol. 55, December 2007, pp. 2709–2718. [32] Kahn, L. R., “Single-Sideband Transmission by Envelope Elimination and Restoration,” IRE Proc., Vol. 40, July 1952, pp. 803–806. [33] Raab, F. H., “Intermodulation Distortion in Kahn-Technique Transmitters,” IEEE Trans. on Microwave Theory and Techniques, Vol. 44, No. 12, December 1996, pp. 2273–2278.

C h a p t e r 12

Bias Circuits

12.1  Introduction Besides delivering bias to the active devices, the bias circuit provides other important functions. A most important one is stability. While the power supply is common to many devices, the bias circuit must ensure that the coupling between the input and output of each device and between devices of the amplifier chain is minimal and is well below the level that might induce either RF or low-frequency bias oscillations. We should keep in mind that an oscillation of the bias circuit is very dangerous. In fact, while an RF oscillation disrupts the functioning of the system but seldom causes permanent damage, a bias oscillation, producing large swings of the bias voltage, may easily induce a catastrophic failure of the active devices. While most often the filtering effect in the bias circuit is achieved mainly by capacitors, an active bias circuit (as described in Section 12.3) offers an outstanding broadband performance that cannot be achieved with a passive circuit. Finally, the bias circuit often includes a system for gain stabilization. In Section 12.4, we describe the computer optimization of a gain-control network.

12.2  Passive Circuit There are two basic requirements of a bias circuit: (1) filtering, at both low and high frequencies, must be adequate to avoid oscillations; and (2) the bias circuit impedance must be low and uniform from dc to the maximum modulation frequency (see Section 10.2.5). The first requirement determines the network stability. Although in Section 8.8 we have already discussed a number of potential instabilities, here we are specifically concerned with instabilities deriving from a coupling of the various active devices through the bias circuit. Such coupling can lead to both RF and low-frequency oscillations. An RF oscillation occurs at a frequency within the bandwidth of the amplifier (or at most, near its edge), and its amplitude is determined by the RF gain of the stages and the level of coupling through the bias network. Such oscillation certainly disrupts the normal operation of the amplifier, but seldom causes a catastrophic failure of any active device, because its amplitude is limited by the saturation of the device itself, which, in a power amplifier, does not lead to failure. On the contrary, a low-frequency oscillation, which is sustained by a low-frequency coupling between devices through the bias network, is far more dangerous: indeed the bias circuitry becomes part of the resonator and the peak voltage can reach a 273

274

Bias Circuits

value as high as twice the voltage of the power supply. In addition, the voltage regulator of the power supply, subject to a rapidly variable load, might lose regulation, leading to a further increase of the peak voltage. Another important parameter of the bias network is its bandwidth. We discussed in Section 10.2.5 how the bandwidth of the bias circuit affects the spectrum of an amplitude-modulated RF signal, and, in fact, may limit the available instantaneous RF bandwidth. In the same section, we discussed how the modulation frequency appears in the bias circuit, even for an amplifier operating nominally in class A, because of the inevitable presence of second-order distortion. In other words, class A operation is only an approximation; thus, the bandwidth of the bias network affects any amplifier operating with amplitude-modulated signals. Finally, the bias network for FETs must have a provision for limiting the gate current, because, under a large-signal RF drive, the gate of the FET is driven into reverse-voltage breakdown and (or) forward conduction. Unless the gate current is limited, the device might become damaged. Often device manufacturers specify either the maximum gate current or the resistance of the bias circuit. We should mention, however, that there is a tradeoff between maximum gate current and amplifier performance: a high gate-circuit resistance, which limits the gate current to a very low and safe value, results in a lower saturated output power and poorer linearity. The electrical schematic of a typical bias circuit for an FET is shown in Figure 12.1. Resistors R1 and R2 form a filter for the low frequencies, as well as a voltage divider and a limiter for the gate current. The gate and drain biases are fed to the device through inductors L1 and L2, respectively, while capacitors C1 and C4 block the propagation of the RF signal into the bias network. Additional capacitors C2, C3, C5, and C6 provide low-frequency filtering and a low-impedance path for the modulation frequency. Table 12.1 lists typical characteristics for the capacitors, including the frequency at which the reactance is 1W. As an example, for operation from C to Ku band, the capacitors C1 and C4 typically have a value on the order of 100 pF and feature a parallel plate structure; the most common dielectrics are either a low-loss ceramic or a thin film of silicon dioxide or nitride. For operation at different frequencies, only these two capacitors need to be changed. They

Figure 12.1  Electrical schematic of a typical FET bias circuit.

12.2  Passive Circuit

275 Table 12.1  Characteristics of Capacitors Used in a Typical Bias Circuit Capacitor

Value

Frequency at Xc=1W

Technology

C1,C4 C2,C5 C3,C6

100.00 pF 0.01 mF 10.00 mF

1.60 GHz 16.00 MHz 16.00 kHz

Parallel plate Multilayer ceramic Solid tantalum

can be scaled in approximately inverse proportion to the frequency: for instance, 200-pF capacitors may be used below C band and 50-pF above Ku band. Although these values are not critical, we must be aware that, at high frequencies, capacitors act as transmission lines and might exhibit resonances that are detrimental to the operation of the amplifier. Capacitors C2 and C5 are typically built with a low-inductance, multilayer structure. Ceramic capacitors suitable for this application are available in remarkably small sizes, thanks to the use of materials with a very high dielectric constant. A good choice for C3 and C6 are tantalum electrolytic capacitors. They have a small size and their solid-electrode structure ensures a low value of parasitic inductance. Connecting different capacitors in parallel (as required to provide filtering and low circuit impedance over a very broad band) is not a trivial issue, since their parasitic inductances generate parallel resonances. For instance, capacitor C6 (which provides low impedance at low frequencies) behaves as an inductor at higher frequencies, for example 16 MHz, where, in conjunction with C5, it forms a parallel resonant circuit, resulting in increased circuit impedance at the resonant frequency. The effect is twofold: (1) it increases the chance of an oscillation; and (2) it increases the impedance of the bias circuit at the resonant frequency. If this frequency falls within the modulation bandwidth, it results in an asymmetry of the RF spectrum (see Section 10.2.5). In our experience, an effective approach is to select capacitors with low parasitic inductance, keep their number to a minimum, and connect them in the bias circuit with as few additional parasitics as possible. This way, one can take advantage of the damping effect induced by the loss of a lower frequency capacitor when operated at higher frequencies. For instance, capacitor C4 might resonate with capacitor C5 at a frequency in the GHz range, but, at that frequency, the dielectric material of C5 is very lossy. In fact, in formulating the ceramic material, its high dielectric constant is typically obtained at the price of elevated highfrequency losses. Thus, the parallel resonance between C4 and C5 is strongly damped by the losses in C5, and the effect of the resonance on the impedance of the bias circuit is only minor. Alternatively, parallel resonances can be dampened by inserting resistors in series with the parallel capacitors. The problem with this approach is that the series resistor inevitably increases the inductance of the connection; thus the approach quickly becomes counterproductive. Clearly, the use of multiple parallel capacitors to provide broadband performance has significant limitations. An interesting approach to providing a resonance-free ultrabroadband performance is based on the active circuit described in Section 12.3.

276

Bias Circuits

12.3  Broadband Voltage Followers Voltage followers, either in the form of emitter followers or of source followers, can be frequency compensated to provide low output impedance over a remarkably broad band. Let’s consider the emitter follower in Figure 12.2, where Y1 is the total admittance seen from the base terminal of the BJT. Under the assumption of unity voltage-gain, the output admittance is

Y2 = b Y1

(12.1)

where b is the transistor current gain. The current gain can be expressed as a function of the frequency as

b =

b0 1+j

w wC

(12.2)

Where b0 is the dc current gain and wC is the 3-dB cutoff frequency. If we assume now that Y1 is composed by a resistor R in parallel with a capacitor C, then

Y2 =

b0 1 + jw RC R 1+j w wC



(12.3)

And if we now adjust the input network so that its time constant is

RC =

1 wC

(12.4)

we achieve the remarkable result that the output admittance as a function of frequency is constant and equal to its dc value:

Y2 =

b0 = constant R



Figure 12.2  Schematic of the broadband emitter follower.

(12.5)

12.3  Broadband Voltage Followers

277

Figure 12.3  Performance of a 110-mA BJT voltage follower.

In other words, when (12.4) is satisfied, capacitor C provides a perfect frequency compensation. Another interesting feature of this circuit is that the output voltage can be modulated by applying to the base terminal a modulation voltage, Vm, from a relatively high-impedance source [1]. In this case, the circuit elements R and C represent the entire external circuit connected to the base terminal, or, in other words, the bias circuit and the voltage source. In order to achieve a resonance-free, low-impedance bias source over a wide modulation bandwidth it may be necessary to implement the circuit of Figure 12.2 using a microwave transistor [2]. As an example, Figure 12.3 shows the computed performance of a broadband voltage follower, based on a 4-GHz 110-mA silicon BJT [3]. The output impedance is plotted versus frequency for two cases: with frequency compensation (C = 20 pF), and without compensation (C = 0). In both cases, R =1000W. The difference between the two cases is striking: with compensation, the output impedance remains low—below 5W—and resonance-free up to a modulation frequency of 2 GHz. Although we derived (12.4) for a bipolar transistor, the same approach can be applied to an FET. In fact, Figure 12.4 shows the computed performance of a voltage follower based on a 500-MHz 1.5-A N-channel MOSFET [4]. Again, with frequency compensation (C = 60 pF) the performance is remarkable: it is resonancefree and exhibits low output impedance—below 3W—up to a modulation frequency of 900 MHz.

278

Bias Circuits

Figure 12.4  Performance of a 1.5 A MOSFET voltage follower.

12.4  Bias Supply A bias supply diagram of a typical GaAs FET power amplifier is shown in Figure 12.5. In this example, the RF amplifier consists of two stages of preamplification, followed by driver and power stages. To bias the drains, the input bias supply (+Vin) feeds a drain-supply circuit, which includes voltage regulators and voltage-drop power resistors. To bias the gates, we note that power FETs and MMICs have the sources directly connected to ground. This leads to efficient heat-sinking and optimal RF performance. It implies, however, the need for a negative voltage supply

Figure 12.5  Bias supply diagram of a typical GaAs FET power amplifier.

12.4  Bias Supply

279

to bias the gates of the active devices. If a negative voltage supply—in addition to the high-current positive one for the drains—is available from outside, a regulator inside the amplifier is all that is needed to provide the bias to the gates. This dual power supply configuration is the simplest and most spurious-free, although not the most common and most convenient for the user. More common is a single power-supply configuration, which implies, however, that a negative voltage must be generated inside the amplifier. This is accomplished either by a small dc-to-dc converter or by an inductorless charge-pump voltage inverter. Both of these devices are commercially available in small sizes. In Figure 12.5, the negative supply voltage is generated by an inverting circuit (INV), most often a charge-pump device, fed by the input supply (+Vin). If the amplifier uses GaAs FETs and MMICs, the value of +Vin is typically within the range of +10V to +15V. If the voltage of the available dc power is outside this range, an alternative configuration includes a power dc-to-dc converter, which provides both the high-current positive voltage to bias the drains and the low-current negative voltage to bias the gates. We should caution that when a switching oscillator is included in the amplifier, as part of either a voltage inverter or a dc-to-dc converter, the switching signal inevitably finds a path to modulate the RF signal. In practice, any line connected to the switching device requires careful filtering to ensure that the level of the spurious sidebands is adequately low. The small-signal gain of FETs and MMICs can be adjusted, within a limited range, by varying the gate bias. This can be used to compensate the amplifier smallsignal gain over temperature. We should keep in mind, however, that the gate voltage of the driver and power stages is not available for gain compensation, because its value must be optimized for output power and linearity. Thus, the diagram of Figure 12.5 shows two gate-voltage regulators: VR1 provides a fixed bias to the driver and power stages, while VR2, which incorporates a temperature-sensitive element (T), provides to the low-power stages a bias that varies with temperature as required to compensate the gain variation. A technique we found useful for temperature compensation is described in the Section 12.4.1. 12.4.1  Gain Stabilization Versus Temperature

When a GaAs FET is biased at the center of its operating characteristics—at a drain current approximately ½ of Idss—the small-signal gain can be adjusted by varying the gate-bias voltage. Specifically, the gain increases by increasing the drain current (gate voltage less negative) and vice versa. Since the gain of the amplifier decreases with increasing temperature, a simple temperature-compensation network can be built using a voltage divider with the configuration shown in Figure 12.6. The component RT is a thermistor, which has a resistance that decreases rapidly with temperature. Thermistors with different resistance values and different temperature characteristics are readily available. A typical rate of change is a decrease in resistance by a factor of 10 for an increase in temperature of 8–9ºC. The resistors, Rp and Rs, adjust the slope of Vg versus temperature at the low and high ends of the temperature range, respectively, while the series resistor, Rg, sets the voltage dividing ratio. The circuit is very simple and easy to implement. However, there is a practical inconvenience: since Rg is constrained by the gate-current limitation, as described in Section 12.2, one needs to keep a large stock of thermistors of different

280

Bias Circuits

Figure 12.6  Simple thermistor network for gain compensation.

resitance values to cover the large variety of temperature compensations that is often required in practical applications. This problem is overcome by using a thermistor in conjunction with a voltage regulator. Figure 12.7(a) shows a schematic of a temperature-compensation circuit, including a three-terminal voltage regulator—for instance, the readily available LM137. The regulator maintains a constant voltage (Vref) between the out and the adj terminals. Assuming that the current in the adj terminal is negligible, then

Vadj R2 = Vref R1



(12.6)

Thus, the output voltage is

�

R2 Vout = Vref + Vadj = Vref 1 + R1

and

Vadj = Vref

R2 R1

�



(12.7)

(12.8)

Figure 12.7  (a, b) Temperature compensation circuit using a thermistor and a voltage regulator.

12.4  Bias Supply

281

All we have to do now is replace R2 with the thermistor network of Figure 12.7(b) to obtain a Vout that is variable, at an adjustable rate, with temperature. The temperature-compensation circuit can be optimized by using a networkanalysis program equipped with an optimization routine. As a first step, we store the thermistor characteristic (i.e., its resistance versus temperature) in a file where we replace temperature with frequency. If the temperature range includes negative values, we can either add a constant or use the absolute temperature (in K). We then connect a separate power supply to the adj terminal and run a temperature test of the amplifier while adjusting the voltage to maintain a constant gain. This generates a table of optimal values of Vadj (Vadjopt) versus temperature. From (12.8), we then derive the ratio:

R2 opt Vadjopt = R1 Vref



(12.9)

where Vref is a constant for the specific regulator; as an example, it is 1.25V for the LM137. We now enter in the circuit simulator a table of the values from (12.9), where, again, temperature is replaced by frequency (Figure 12.8(a)). Also, we enter in the simulator the circuit of Figure 12.8(b), which includes the thermistor, RT, in a table form, Rs and Rp to be optimized, and an ideal 1:N transformer, with a ratio, N, that is also to be optimized. The optimization target is the table derived from (12.9). The optimization yields the values of Rs, Rp, and N. The value of R1 is then computed as

R1 = N 2

(12.10)

At this point, the temperature-compensation network is completely defined. The advantage of this approach, as compared to the one sketched in Figure 12.6, is that it covers a very wide range of temperature compensations, while requiring only one thermistor of a single value. Also, once the equivalent circuit of the temperature compensation (Figure 12.8(b)) is set up in the circuit-simulation program, the optimization process is very fast and accurate.

Figure 12.8  (a, b) Equivalent circuit of the temperature-compensation algorithm.

282

Bias Circuits

12.5  Distributed Pulsing It is not uncommon for microwave systems, such as radars, to require operation in a pulse mode. Traditionally, and specifically with bipolar transistors, pulse operation was achieved by operating the RF devices in class B or C mode. In this mode, the pulsed RF signal drives the device into an amplifying condition, without the need of additional circuitry. The operation is fast, and the system is simple. However, GaAsbased FETs don’t operate well in class B or C because, when biased at pinchoff, the voltage breakdown greatly limits the available drain voltage and, consequently, the available output power. Thus, GaAs FET amplifiers either must be operated in CW mode, even with pulsed RF signals, or the drain bias needs to be pulsed. The first approach results in two major difficulties. The first difficulty is that the amplifier emits noise, even when the RF pulse is off. This seriously complicates the system design and degrades the performance. The second difficulty is the increase, often by a large amount, of the dc-power requirement and of the heat dissipation. The second approach, based on switching the drain-bias current, clearly solves these problems; however, even turning off and on a few amperes would not be an easy task at the high speed typical of most of the applications. A direct and simple switching of the high currents required in high-power amplifiers is just not feasible. Thus, to solve the problem of fast pulsing in high-power amplifiers, we developed a distributed pulsing architecture that we first applied to a 30W Ku-band amplifier [5]. A pulsing module (pulser) of a configuration that is simple and convenient is shown in Figure 12.9. A power MOSFET switches the drain-bias current. It is of p type, thus, the device is turned on when the gate is negative with respect to the source and, in this circuit configuration, the MOSFET is fully turned on when the gate is grounded. This results in a particularly simple driver circuit that is easily implemented with a commercial TTL-controlled driver. For energy storage, the circuit includes a fast, large-value capacitor, C1, connected at the input of the MOSFET. When the MOSFET is turned on by a TTL signal applied to the driver, the capacitor discharges rapidly into the RF device and turns on the RF stage. A number of factors must be considered in order to achieve a clean pulse. Most important is the connection between the pulser and the RF device. Specifically, in

Figure 12.9  MOSFET pulser for GaAs FET.

12.5  Distributed Pulsing

283

order to maintain high switching speeds, the capacitance on the connecting line must be low, typically no more then a few hundred pF’s. Thus, the drain-bias circuit cannot be loaded with the large capacitors normally used to prevent bias oscillations. Rather, the low-frequency filtering must be delegated to the energy-storage capacitor. Also, the connecting line must be short, since any series inductance, in conjunction with the circuit capacitance, forms a resonant circuit. When excited by the current pulse, this generates voltage ripples that degrade the RF pulse. Furthermore, as the current is turned off, the decreasing magnetic field associated with the series inductance produces a negative voltage spike that, if unchecked, might damage the RF device. For this purpose, a Shottky diode, D1, provides additional protection. The capacitor C1 must be capable of a fast discharge and should include a minimum of series inductance. Experience has shown that the type most suitable for fast pulsing is solid tantalum, while the common electrolytic type with wound electrodes does not provide acceptable high-speed performance. As energy-storage capacitor, C1 must keep the voltage drop, over a specified length of time, within an acceptable limit. Thus, its value can be computed as

C=

I × Dt DV



(12.11)

where I is the load current, Dt is the length of the pulse, and DV is the voltage drop from the beginning to the end of the pulse. If the pulse length is very long, up to CW, the voltage regulator feeding the pulser takes over the task of keeping the voltage constant. Under this condition, Dt is then the response time of the voltage regulator. Since the connection between the pulser and the RF devices is critical in obtaining fast and clean pulses, it is clear that in a high-power amplifier, which is built by paralleling many RF stages, the simple approach of collecting all the drain-bias lines into a single high-current pulser does not lead to an acceptable high-speed performance. Much more successful is an architecture in which the pulsers are distributed and in close proximity to the separate RF stages. A diagram of a 100W, X-band amplifier composed of 16 power modules paralleled by a radial combiner, is shown, as an example, in Figure 12.10. Each RF power module, as well as the RF driver,

Figure 12.10  Example of distributed pulsing.

284

Bias Circuits

Figure 12.11  (a, b) Rise and fall time of 100W, X-band amplifier.

includes pulsers and energy-storage capacitors, which are integrated with the RF circuitry. Each pulser is controlled by a TTL signal, and all the TTL lines, of high impedance and equal length, are combined into a single input. This distributed pulsing architecture can achieve truly notable performances. Shown in Figure 12.11 are rise and fall times of 15 and 18 ns, respectively, measured on a power amplifier of the type sketched in the Figure 12.10. This is quite remarkable, if we consider that the total switched current is over 100A. The longpulse operation of the same unit, shown in Figure 12.12 for a 160-ms pulse, is also very uniform and well behaved. In fact, the pulse can be extended all the way to CW. When designing a distributed pulsing network, we must take into consideration the connection between the power supply and the individual pulsers. In this application, the power supply, or the voltage regulator, operates in a difficult environment because it is required to provide a constant voltage, even while the load is pulsed. Although most of the current transient is absorbed by the energy-storage capacitor, under some combinations of pulse length and duty cycle, the voltage regulator may partially lose its regulation. Then the output voltage fluctuates, typically only slightly, at a rate determined by the response-time of the regulator. The result is that

Figure 12.12  Long-pulse operation of 100-W X-band amplifier.

12.5  Distributed Pulsing

285

a train of equal-amplitude RF input pulses is translated by the amplifier into pulses of slightly different amplitudes, causing very puzzling effects in the operation of a system. However, once the problem is detected, it can be solved in a rather simple way by substantially increasing the energy storage capacitance at the output of the power supply (or of the voltage regulator).

References   [1] In fact, the circuit was originally developed by one of the authors (Sechi) to modulate Gunn diode oscillators, which are notorious for developing bias oscillations when the bias source doesn’t have sufficiently low impedance over a broad band.   [2] Sechi, F. N. “Linearized Class-B Transistor Amplifiers,” IEEE J. of Solid-State Circuits, Vol. SC-11, No. 2, April 1976, pp. 264–270.   [3] AT-64000 by Avago Technologies, http://www.avagotech.com, last accessed April 29, 2009.   [4] MFT1511NT1 by Freescale Semiconductor, http://www.freescale.com, last accessed April 29, 2009.   [5] Sechi, F. N., et al., “Radially Combined 30-W 14–16 GHz Amplifier,” 1994 IEEE MTT-S Int. Microwave Symp. Digest, San Diego, May 23–27, 1994, pp. 1737–1738.

C h a p t e r 13

Thermal Design

13.1  Introduction The thermal design of a power amplifier is an important part of the overall amplifier design. We’ll see in Section 13.2 that a difference in junction temperature of a few degrees C can make a large difference in the life of the active device. Thus, verifying the actual operating junction temperature is important, and we’ll describe three techniques that have been proven most useful for measuring temperature in microwave devices. A major factor affecting the operating junction temperature is how power is applied and dissipated by the device. When the power is applied in a pulsed mode, the junction temperature fluctuates, and its peak value is a function of both the pulse parameters and the thermal time constant of the device. Finally, an important issue is the choice of the heat sink, and we’ll describe three types of air-cooled heat sinks that differ in technology, efficiency, and cost.

13.2  Device Life Versus Temperature The life of an amplifier is largely determined by the life of its active devices, which in turn is determined by physical phenomena such as metal migration, dopant diffusion, or other modifications of the device characteristics. These phenomena are critically dependent on temperature. One of the most useful models relating temperature to the speed of a physical or chemical reaction is the Arrhenius model, which expresses the rate of change, r, as

E

A r = Ae− KT

(13.1)

where A is constant, EA is an activation-energy characteristic of the specific process, K is the Bolztmann constant [8.617 ´ 10-5(eV/ K)] and T is the absolute temperature in K. Experience has shown that (13.1) models well many of the phenomena which lead to failure in an electronic component. Accordingly, we expect the life, l, of the component (or, in other words, the time before its failure), to be inversely proportional to r. Its relation to temperature is given by

EA

l = Be KT

(13.2)

where B is a constant. It is also useful to define a relative life time, by making reference to the component’s life, l0, at a normalized temperature, T0. Based on (13.2), this is equal to 287

288

Thermal Design EA

l0 = Be KT0



(13.3)

thus the relative life time is

EA l l = =eK l0

�

1 1 T − T0

�



(13.4)

As an example of a typical situation, the relative life time, l, of a power MMIC based on GaAs PHEMTs is plotted in Figure 13.1 for a reference temperature of 100ºC (373 K). For this device, the activation energy, equal to 1.1 eV, is determined by the primary failure mechanism of gate metal interdiffusion [1]. This is one of the leading causes of failure in power FETs. We should note that 100ºC is a typical junction temperature for a power FET operating at a case temperature of 25ºC. The most striking result from the data in Figure 13.1 is the high slope of the curve: the life time decreases, for instance, by a factor of 10 for a junction temperature increase of only 30ºC, and by a factor of 2 for an increase of about 8ºC. Conversely, similar increases of life time are obtained for similar decreases in junction temperature. Clearly, even a few degrees’ improvement can make a very substantial change in the life of the device. Moreover, although an amplifier may operate correctly at elevated ambient temperatures, such as +85ºC, continuous operation at that temperature for extended periods of time may shorten the life by a factor of 100, as compared to operation at an ambient temperature of 25ºC. Maintaining a low junction temperature is the key to achieving adequate operating life times and, in turn, effective heat sinking is the key to keeping the temperature under control.

Figure 13.1  Relative life time versus junction temperature for an activation energy of 1.1 eV.

13.3  Junction Temperature Measurements

289

13.3  Junction Temperature Measurements The measurement of the operating junction temperature, or at least the device’s thermal resistance, is a required step in the thermal design of an amplifier. The technology for measuring the operating temperature of semiconductor devices is rather mature. Through the years, many techniques have been devised and implemented, and a review of these techniques has been compiled by Blackburn [2]. Here we’ll consider those that are more common for microwave devices, and specifically, the techniques based on IR microscopy, liquid crystal, and an electrical temperaturesensitive parameter. 13.3.1  IR Microscopy

Any object at a temperature above 0 K radiates energy with a spectrum that is related to temperature by Planck’s law [3]. Specifically, the radiation of a black body is described by

U(l, T ) =

1 8p hc ( J/m4 ) hc 5 l e l KT − 1



(13.5)

where U is the spectral intensity of the blackbody radiation, h is the Plank’s constant (6.626 ´ 10-34 J-s), c is the speed of light (3 ´ 108 m/s), K is the Boltzmann constant (1.38 ´ 10-23 J/K), l is the wavelength, and T is the absolute temperature (K). Equation (13.5) can be used to describe the emission spectrum at any constant temperature and it is plotted in Figure 13.2 for the temperatures of 50, 100, and 150 ºC. Notice that the junction temperature of microwave power devices, and specifically of power FETs, often falls within this range.

Figure 13.2  Spectral intensity of blackbody radiation at three different temperatures.

290

Thermal Design

At any given wavelength, the emission is a function of temperature and can be used to monitor temperature distributions on the emitting surface. However, when this approach is applied to microwave devices, the issue is complicated by the different characteristics of different areas on the surface. Equation (13.5) refers to a black body; for any real surface, the energy radiated is proportional to the surface emissivity e, where

0 < e < 1, e = 0 for a perfect mirror and e = 1 for an ideal blackbody

(13.6)

At the surface of a transistor, e is high (approaching 1) on the exposed area of the semiconductor, and is low (approaching 0.1) on the metallization pattern. Because of the very large variation of emissivity at the surface of the device, the pattern of IR radiation strongly reflects the pattern of the surface emissivity and only weakly reflects the pattern due to the temperature profile. A careful correction for the surface emissivity is essential to determine the actual operating temperature of the device. An accurate model of the detector’s output as a function of temperature is also required. The output from the IR detector can be described by

E(T ) = e

�l2

D(l )U(l, T )dl



(13.7)

l1

Where D is the response of the detector as a function of wavelength, l1, l2 are the low and high limits of the detector range, and e is the emissivity of the target, which, here, is assumed constant over the range of interest of l. For an ideal detector—with a uniform response versus l—the output would be proportional to T4 (Stefan-Boltzmann equation) [3]. In practice, detectors have a limited range of wavelength response and therefore their output is a more complex function of temperature. The detectors typically used for IR microscopy are made of indium antimonide (InSb), and their response, after filtering, is in the 3 to 5-mm range. Thus, as we can see from Figure 13.2, an InSb detector collects energy only at the tail of the spectrum, and its output will not simply be proportional to T4. A simple model for the detector is of the type:

E(T ) ≡ e T a

(13.8)

A more accurate model can be derived from (13.7) by applying a realistic response for the InSb detector [4]. The calibration of the system is carried out by mapping the radiation while the device is uniformly heated at known calibration temperatures. A minimum of one calibration temperature is required, but higher precision is achieved by using two or more temperatures. The microscope objective for IR radiation is either of a refractive or reflective type. A refractive objective uses lenses of a material, such as silicon, which is transparent to IR radiation. The reflective objective, instead, focuses the image using a parabolic mirror. The image is focused on a detector that is typically an InSb CCD, cooled at liquid-nitrogen temperature (-200ºC). Its spatial resolution depends on the objective, but it typically falls between 10 and 20 mm.

13.3  Junction Temperature Measurements

291

An example of the thermal map of a GaAs FET obtained by IR microscopy is shown in Figure 13.3 [5]. Clearly visible are the outline of the chip and the gate and drain fingered patterns. In the actual instrument display, the temperatures are indicated by a color code ranging from blue to red, violet, and white as the temperature increases. The IR microscopy technique is particularly useful when measuring the temperature of a device operating in a realistic environment, including an RF signal. The accurate temperature map reveals defects in the die attaching, the formation of potentially harmful hot spots and, in some cases, the distribution of RF power among multiple cells of a single device. The measurement of the actual operating junction temperature leads to a reliable estimate for the life expectancy of the device. IR microscopy can also be used in a pulsed mode to determine the peak device junction temperature [6]. Furthermore, it can be used in conjunction with numerical modeling techniques to estimate the operating temperature of devices with a geometry too small for direct thermal mapping [7, 8]. The downside of IR thermal mapping is that the die must be visible, and thus it cannot be applied to packaged devices. The equipment cost is also a consideration. 13.3.2  Liquid Crystals

The liquid-crystal phase is a state of the matter that is intermediate between the crystalline state, which is characterized by an orderly distribution of the molecules,

Figure 13.3  Example of IR thermal mapping of a GaAs FET.

292

Thermal Design

and the liquid state, in which the molecules are randomly distributed. We are interested here in nematic liquid crystals (NLC), where the molecules have no positional order, but, as long as the temperature is below a transition temperature (Tt), they point mainly in one particular direction. Thus an NLC film is strongly anisotropic. More specifically, it strongly reflects polarized light whose axis is in the direction of the molecules. If the temperature is raised above Tt, the film becomes isotropic, and the disorderly molecules scatter the polarized light. What is important for our application is that this transition is very sharp, typically within 1ºC. Also, the transition temperature is a function of the chemical formulation, and there is a wide choice of NLCs available, with Tt ranging from 25 to 300ºC. Figure 13.4 is a schematic illustration of the measurement setup. The main instrument is a standard high-power microscope equipped with coaxial illumination. A polarizer, typically located in the filter drawer of the microscope, produces a beam of polarized light from the illuminator. The light reflected from the device under test (DUT) goes through a second polarizer, which is typically part of the eyepiece. To prepare the DUT for measurement, the NCL, supplied normally in the form of powder, is dissolved in a solvent (typically acetone), and a drop of the solution is deposited on the surface of the DUT. The solvent quickly evaporates, leaving behind a thin film of NLC. For the temperature test, the DUT, connected to a power supply, is placed under the microscope. With the power supply off, the polarizers are adjusted for maxi-

Figure 13.4  Microscope setup for liquid-crystal thermal measurements.

13.3  Junction Temperature Measurements

293

mum reflection from the surface of the DUT. This ensures that the polarized illuminator light is aligned in the direction of the NLC molecules and that the reflected light is collected efficiently by the eyepiece. The power supply is then turned on, and the DUT is biased with an increasing amount of dc power. When the temperature in an area on the surface of the device reaches or exceeds the transition temperature, the NLC film in that area depolarizes the incident light and the area—typically at the center of the device—appears dark, as shown in Figure 13.5. Note that the area decreases by decreasing the power dissipation. If we now adjust the dc power for a small, dark spot, the thermal resistance, referred to the hottest area of the device, is computed as

q=

Tt − Th PDC

(◦ C/W)



(13.9)

where Tt is the transition temperature of the NLC, Th is the heat-sink temperature, and PDC is the dissipated power. The heat-sink is defined by the location where the temperature is measured (typically with a thermocouple). It can be a small chipcarrier, a device package, or a larger assembly. The junction temperature under RF operating conditions can be then calculated, based on the actual power dissipation. Note that this procedure determines only the thermal resistance between the device junction and the device heat-sink. We should mention that the thermal resistance of a semiconductor device is not constant with temperature, and, for a GaAs FET, it may vary by ±10% for a junction temperature change of ±50ºC [9]. Thus, the thermal resistance should be measured at a temperature close enough to the expected operating junction temperature of the device.

Figure 13.5  Example of liquid-crystal thermal display.

294

Thermal Design

In summary, the measurement technique based on liquid crystals is easy and usually inexpensive to implement, because the main equipment—the high-power microscope—is often already available in a laboratory. The spatial resolution is excellent—typically 1 mm, that is about 10 times as high as that of an IR technique. In fact, it is so good that it can be used to validate high-resolution 3D thermal modeling [10]. The downside is that it measures only the thermal resistance, rather than the actual operating junction temperature of a device, because the coating prevents the operation under RF conditions. As described above, it requires different liquid crystals for different temperatures. The use of multicolor, multitemperature liquid crystals has also been reported [11]. In this form, however, the technique has a more limited temperature range, and it requires a rather expensive setup and a complex calibration routine. 13.3.3  Electrical Parameters

Many parameters of a semiconductor device vary substantially with temperature: with appropriate calibration, any of these parameters can be used as a thermometer [2]. One of the parameters most often used is the junction forward voltage (Vj), measured at a constant junction current (Ij). In a bipolar transistor it is the base-toemitter voltage, while in a MESFET it is the voltage of the forward-biased gate-tosource junction. Other usable temperature-sensitive parameters are the current gain for bipolar transistors [12], the transconductance for FETs, the channel resistance for FETs, and the threshold voltage for MOSFETs. Calibration requires the measurement of the chosen electrical parameter as a function of temperature. This is done by heating the device with an external heater at a uniform and controlled temperature. In the process, one should make sure that any localized self-heating introduced by the process of sampling the temperaturesensitive parameter can be neglected. For instance, if Vj is the thermometer parameter, the current Ij must be set to a value sufficiently low to avoid any significant heating. The result of the calibration is a table relating the voltage, Vj, to the junction temperature, Tj. A point in favor of choosing Vj as a thermometer is that, for a constant Ij, Vj varies almost linearly with temperature [2, 13]. For different devices and junction currents, typical rates are in the range:

DVj ≈ −1.4 to −2.0 DTj

(mV/◦ C)

(13.10)

After calibration, the temperature measurement can be carried out either in a CW or in a pulse mode, each mode having its own characteristics. The simplest measurement is, of course, CW. In this case, dc power is delivered to the device by applying a bias voltage to the third terminal of the device, either the collector for a BJT or the drain for a MESFET. We may note that, in the case of a MESFET, since the gate is forward biased and the device draws its maximum current, the drain voltage we can apply, without exceeding the power dissipation of the device, is typically no more than ½ of the nominal operating voltage. By measuring Vj and obtaining the temperature, Tj, from the calibration data, the thermal resistance is computed as

13.4  Mode of Operation



295

q (Tj ) =

Tj − Th PD

(◦ C/W)



(13.11)

where Th is the heat-sink temperature, and PD (in watts) is the power dissipated in the device. The thermal resistance can then be measured as a function of temperature by varying either Th or PD. The main limitation of any measurement derived through an electrical parameter is that the resultant temperature reading is an average value over the junction area, and no information can be obtained on its peak value. This is a most serious limitation, because any damage caused by high temperature, even in a limited area, results in a failure of the full device. Another limitation, this one limited to the CW technique, derives from the underlying assumption that the electrical parameter used as a thermometer, for instance Vj, is not affected by other electrical parameters, such as the collector voltage. This clearly may not be correct. This limitation is overcome by operating the device in a pulsed mode. In this mode, for most of the time (say 99.9%), the device is biased and dissipates heat, while for a short time (say 0.1%), Vj is measured with the bias tuned off. The pulse technique overcomes the problem mentioned above, but introduces other variables that can affect the final temperature reading, such as the pulse response of the electrical circuit, the effect of the thermal time constant of the active area of the device, and the dispersion effect of the device’s electrical parameters [14]. Another electrical parameter that has been used for bipolar transistors is the set of output I-V characteristics of the device. A desirable feature of this approach is that the measurement can be carried out using a standard device analyzer. Also, calibration is required at only two [15] or even just one [16] known temperature. In summary, any measurement technique based on a temperature-sensitive electrical parameter is inevitably limited, because it does not provide information on the peak temperature nor does it provides a temperature map that might indicate potential faults. Thus, striving to achieve high precision may not be very productive. The strong advantage of this approach, however, with respect to the ones based on IR and liquid crystals, is the ability to provide temperature information without a view of the device’s surface, so it can be applied also to packaged devices. Rather then giving detailed information on a device temperature, it provides a simple, but sensitive technique to compare empirically thermal characteristics of devices of the same type. Specifically, it can be used to screen devices that are already fully assembled. This feature can be of quite great value in a production environment.

13.4  Mode of Operation If an amplifier is operated in a CW mode, the heat dissipation is constant, and after an initial transient at turn on, the system reaches a thermal equilibrium that is characterized by constant temperatures. If the amplifier is turned on in a pulse mode with a constant repetition rate, after an initial transient, the system also reaches a thermal equilibrium. The temperatures, however, do not settle to a constant value: they cycle with a period set by the pulsing.

296

Thermal Design

Figure 13.6  Device heat-sinking structure.

13.4.1  CW

Outlined in Figure 13.6 is a typical heat-sinking structure, where we are showing a single device for the sake of simplicity. We saw in Section 13.3 that the active device is typically attached on a heat sink, which is either a small chip-carrier or a package. This is then fastened to the floor of the amplifier housing, which is mounted, in turn, onto the main heat sink. This heat sink interfaces with the ambient, which, because of its large heat capacity, is expected to absorb heat without a change in temperature. The ambient can be air, a cooling fluid, a large heat-conducting body, or even a vacuum, if the heat sink is designed as a radiator. Some of the materials typically used in the structure are listed in Table 13.1, where K is the thermal conductivity and E is a measure of the thermal expansion per degree Celsius. Included in the table are the specific heat and the density coefficients, to be used later, in Section 13.4.2, to compute thermal time constants. As discussed in Chapter 6, the device heat sink is made of a material with a thermalexpansion coefficient closely matching the one of the semiconductor. A common choice is a sintered copper-tungsten composite. The housing and the heat sink are usually made of aluminum. Note that the Kovar alloy, which is often used for carriers and housings in low-power applications, is not suitable at high power because

Table 13.1  Thermal Properties of Some Common Materials (Typical Values)

Material Aluminum Copper Copper-Tungsten (85W, 15 Cu) Kovar Stainless Steel, 18–8 Silicon GaAs

K

E

S

D

Thermal Conductivity W/cm ºC 2.03 3.88 1.90 0.19 0.16 1.51 0.54

Thermal Expansion ´ 10-6/ºC 28.7 16.1 7.2 6.2 19.1 3.8 5.7

Specific Heat J/g ºC 0.89 0.38 0.17 0.63 0.48 0.70 0.33

Density g/cm3 2.7 8.9 16.4 8.2 7.9 2.3 5.3

13.4  Mode of Operation

297

of its poor thermal conductivity. The device heat sink is connected to the housing either by soldering or by mechanical fasteners. Soldering provides an excellent thermal connection, but if the thermal expansions of the bonded materials are very different, which is the case for copper-tungsten and aluminum, the joint might crack or delaminate under thermal cycling. The alternative is mechanical fastening, for instance by screws, but unless the facing surfaces are flattened by lapping, a good thermal conduction of the joint can be achieved only by filling the gaps with a thermal interface material (TIM). The most common is a heat-conducting grease compound, which is inexpensive and easy to apply. However, its thermal conductivity degrades with time and temperature because of the evaporation of the oily part of the compound. More stable materials for this application are epoxies or gel-based compounds. A review of available TIMs can be found in [17, 18]. Similar considerations about the use of TIMs apply also to the joint between the amplifier housing and the main heat sink. We must note that the use of a TIM is of particular importance when the amplifier operates in a vacuum environment, because the removal of the thin film of air filling the gap between the facing surfaces substantially increases the thermal resistance of the joint, even for a very small gap. When a concentrated heat source spreads heat into a large (at the limit infinite) medium, the three-dimensional heat flow is constricted by the small cross section of the source. As compared to a parallel flow, this constriction gives rise to a spreading resistance. This is the case, for instance, when a small active-device chip is mounted on a relatively large device heat sink, and when, as outlined in Figure 13.6, the device heat sink is mounted in turn on an even larger housing floor. Evaluating the effect of the spreading of heat is of considerable practical importance, because most often the spreading resistance is a dominant factor in the overall thermal resistance of the system. Some close-form expressions for the thermal resistance associated with a device mounted on an infinite plate are available [19, 20], but these expressions are quite complex, and, in addition, they are developed only for very specific configurations. A much more flexible and accurate approach is based on the numerical solution of the heat-flow equations by using a finite-element algorithm. Computer programs based on this technique, which can accurately compute the heat flow even in anisotropic media, are commercially available, but because of their complexity, they are rather expensive. A very simple, though approximate, approach is based on the assumption that heat spreads at a 45º angle. In this model, the heat flow is fully contained within the spreading cone, thus the material outside the cone does not contribute to the heat conduction. The material within the cone can then be subdivided into N thin plates, each plate having a thermal resistance:

Rn =

1 ln K An

(◦ C/W)



(13.12)

where K is the thermal conductivity listed in Table 13.1, ln is the plate thickness (in cm), and An is the average cross section (in cm2) of the cone. The thermal resistance of the material within the spreading cone is then

N

RS = å Rn 1

(13.13)

298

Thermal Design

We must also include the resistance of the interfaces: M

RI = å Ri



(13.14)

1

where Ri is the thermal resistance of each interface (which must be evaluated for the specific TIM used at the interface), and M is the number of interfaces. The total thermal resistance between the device’s active area and the ambient is then

RT = RD + RS + RI + RH

(13.15)

Where RD is the thermal resistance of the device between the active area and its heat sink (either specified by the device manufacturer or measured, as we have described in Section 13.3), and RH is the thermal resistance of the heat sink, which we’ll examine in more detail in Section 13.5. Thus, the operating temperature of the device is

TD = TA + RT PD

(13.16)

where TA is the ambient temperature, and PD is the dissipated power. So far, we have considered the heat-sink structure of a single heat source, although typically, in a power amplifier many heat sources contribute to the total power dissipation. Often, for functional reasons, these sources are not spaced far enough apart to avoid thermal coupling, and, in the simple cone heat-spreading model, the cones overlap. In this case, the computation must be carried out by merging the heat sources and computing the total thermal resistance of the array. 13.4.2  Pulse

What we have described in Section 13.4.1 for CW operation, and specifically the effect of the thermal resistance on the heat flow, also applies to pulse operation. However, when heat generation varies with time, there are additional phenomena to be considered. The storage and release of energy during the thermal cycle will drastically affect the system’s thermal performance. In this connection, it is particularly important to determine how the junction temperature varies with time. In order to compute the response of the system, it is useful to note that the same set of equations that connects, in the time domain, temperature, power, thermal resistance, and thermal time constant, also connects electrical parameters, such as voltage, current, resistance, and time constant. This permits a description of the thermal system in terms of an equivalent electrical circuit that simulates the thermal performance. According to the equivalency convention, a voltage corresponds to temperature and a current to thermal power. Thus resistance is equivalent to thermal resistance and capacitance to thermal capacity, which is defined as the specific heat times the mass (see Table 13.1). For instance, the thermal structure of Figure 13.6 can be represented by the electrical circuit of Figure 13.7, where the thermal input power is represented by the current source, the thermal capacity by capacitors, and the resistance to the heat flow by resistors. The time-domain response

13.4  Mode of Operation

299

Figure 13.7  Electrical equivalent circuit of a thermal system.

of the system, under an arbitrary excitation, can be computed using either a timedomain analysis technique (SPICE, for instance) or a frequency-domain technique in conjunction with a Fourier-series expansion. The equivalent circuit of Figure 13.7 clearly identifies the time constants associated with the various elements of the thermal structure. These time constants have an important effect in pulse operation. Just by inspection, we may note that the device chip, with its small size and low thermal resistance, has the lowest time constant and, therefore, the fastest pulse response. It is instructive, at this point, to compute the thermal time constant of an FET chip, in order to acquire a feel for the thermal response of this type of device. For instance, the typical size of a 1W, Ku-band, GaAs FET chip [21] is 0.086 ´ 0.048 ´ 0.006 (cm), and the corresponding volume is 2.47 ´ 10-5 cm3. From Table 13.1, the density of GaAs is 5.3 g/cm3, and the weight of the chip is 1.31 ´ 10-4g. Thus, the thermal capacity of the chip is

C = 0.33 × 1.31 10−4 = 0.43 10−4



( J/◦ C)

(13.17)

The thermal resistance is

R=

1 0.006 = 2.64 0.55 0.086 × 0.048

(◦ C/W)



(13.18)

300

Thermal Design

and the thermal time constant is

t = RC = 1.14 × 10−4 s = 114 m s

(13.19)

Notice that devices of the same type, but different power capability, have similar time constants, because a change in the number of interconnected cells results in a change in volume inversely proportional to the change in thermal resistance, so that the RC product remains constant. Once the time constants of the other elements in the circuit are computed in a similar way, the response of the system can be determined for any type of excitation. It is useful to consider two limit cases that lead to simple but interesting results. Under the condition of repetitive pulsing, we define the duty cycle as

DC =

ton tpd

(13.20)

where ton is the on time of the pulse, and tpd is the period of the repeating pulses. The average dissipated power is then

Aavg = PD × DC,



(13.21)

where PD is the peak power. Now we consider two operating conditions characterized by the same duty cycle (DC) and Aavg values, but having very different pulse lengths: (1) ton >> t (long pulse); and (2) ton << t (short pulse). Under the long-pulse condition, after turn on, the junction temperature rises and approaches the asymptotic value defined by the CW operation. In fact, after a time equal to twice the time constant, the temperature is already quite close to the CW value (86%). Thus the junction temperature is

TJ ≈

PD RT

(13.22)

with RT defined by (13.15). Under short-pulse operation, instead, the thermal inertia maintains the junction temperature at an approximately constant value:

Tj ≈

DC × PD RT

(13.23)

As an example, for DC = 10%, the rise in temperature of the junction over the ambient is 10 times larger for a long pulse than for a short one, even though the average power and the average heat dissipated by the heat sink are identical. In other words, everything else being the same, a long-pulse operation leads to a higher thermal stress for the active device.

13.5  Heat Sinks

301

Figure 13.8  Example of profile of an extruded heat sink.

13.5  Heat Sinks Here we’ll consider three types of heat sinks, suitable for air cooling either by forced air or by natural convection. Typically, they are made of either aluminum or copper, with aluminum being by far the most common because of its light weight and low cost. We should point out that the heat sink of a power amplifier can be quite large, particularly if it is using natural convection. Thus, its weight is often a significant factor, and its cost is not always negligible. The most common type of heat sink is derived from an extrusion, and Figure 13.8 is an example of a common profile. Because of physical constraints in the extrusion process, the fins cannot be made very thin and cannot be spaced very close.

Figure 13.9  Example of bonded-fin heat sink.

302

Thermal Design

This sets a rather low limit to the maximum surface area that can be developed within a given volume. The result is that extruded heat sinks, though simple to make, are not the most efficient. Better efficiency is obtained by bonding fins onto a plate: an example is shown in Figure 13.9. The fins are press-fitted into grooves and bonded in place, often by epoxy. Since the fins are thin and closely spaced, bonded-fin heat sinks are substantially more efficient than those made from extrusions. However, the most efficient heat sinks are built by pressing long pins into holes in a plate, as in the example shown in Figure 13.10. Their high efficiency derives not only from the large surface area created by the pin array, but also from the vortex flow of air around the pins. One additional advantage of this configuration is that it allows impingement cooling, with the direction of the air flow perpendicular to the base plate. Thus, the heat sink can be integrated with its fan in a compact assembly. Heat sinks are produced by a number of manufacturers, [e.g., 22–24] who also provide the information required for the design of the cooling system. Specifications are in the form of thermal resistance or temperature rise over ambient as a function of power. For forced air, the data varies, depending on the air speed. Finally, there is a small, practical point: in the United States, the heat-sink manufacturer generally specifies the required air speed in linear feet per minute (LFM), while the fan is generally specified in terms of cubic feet per minute (CFM). The relationship between the two quantities is clearly (CFM) = (LFM) ´ A, where A is the heat sink’s cross-section.

Figure 13.10  Example of a pin-fin heat sink.

13.5  Heat Sinks

303

References   [1] Anderson, W. T., J. A. Roussos, and J. A. Mittereder, “Life Testing and Failure Analysis of PHEMT MMICs,” Proc. of GaAs Reliability Workshop, 2000, November 5, 2000, pp. 45–52.   [2] Blackburn, D. L., “Temperature Measurements of Semiconductor Devices—A Review,” 20th Annual IEEE Semiconductor Thermal Measurement and Management Symp., 2004, March 9–11, 2004, pp. 70–80.   [3] Landau, L. D., and E. M. Lifshitz, Statistical Physics, 3rd ed., Part 1, Oxford: ButterworthHeinemann, 1996.   [4] Sechi, F. N., B. S. Perlman, and J. M. Cusack, “Computer Controlled Infrared Microscope for Thermal Analysis of Microwave Transistors,” IEEE MTT-S Int. Microwave Symp. Digest, 1977, pp. 143–146.   [5] Courtesy of Glenn Nakao of AML Communications. The instrument model is Infrascope II, made by Quantum Focus, http://www.quantumfocus.com, last accessed April 30, 2009.   [6] Hefner, A., et al., “A High-Speed Thermal Imaging System for Semiconductor Device Analysis,” 17th Annual IEEE Symp. Semiconductor Thermal Measurement and Management, 2001, 2001, pp. 43–49.   [7] Li, L., et al., “Multi-Scale Thermal Analysis of GaAs RF Device,” 21st Annual IEEE Semiconductor Thermal Measurement and Management Symposium, 2005, March 15–17, 2005, pp. 259–263.   [8] Kuball, M., et al., “Thermal Properties and Reliability of GaN Microelectronics,” Compound Semiconductor Integrated Circuit Symp., October 14–17, 2007.   [9] Minot, M. M., “Thermal Characterization of Microwave Power FETs Using Nematic Liquid Crystals,” IEEE MTT-S Int.Microwave Symp. Digest, 1986, pp. 495–498. [10] Park, J., M. W. Shin, and C. C. Lee, “Thermal Modeling and Measurement of GaN-Based HFET Devices,” IEEE Electronic Device Letters, Vol. 24, No. 7, July 2003, pp. 424– 426. [11] Azar, K., J. R. Benson, and V. P. Manno, “Liquid Crystal Imaging for Temperature Measurement of Electronic Devices,” 7th Annual IEEE Semiconductor Thermal Measurement and Management Symp. Proc., 1991, February 12–14, 1991, pp. 23–33. [12] Dawson, D. E., A. K. Gupta, and M. L. Salib, “CW Measurement of HBT Thermal Resistance,” IEEE Trans. on Electronic Devices, Vol. 39, No. 10, October 1992, pp. 2235– 2239. [13] Gorecki, K., et al., “Thermal Resistance Measurements of Microwave Devices,” 14th Int. Conf. on Microwaves, Radar, and Wireless Communications, 2002, 2002, Vol. 2, pp. 383– 386. [14] Rodriguez-Tellez, J., et al., “Characterization of Thermal and Frequency-Dispersion Effects in GaAs MESFET Devices,” IEEE Trans. on Microwave Theory and Techniques, Vol. 49, No. 7, July 2001, pp. 1352–1355. [15] Bovolon, N., et al., “A Simple Method for the Thermal Resistance Measurement of AlGaAs/GaAs Heterojunction Bipolar Transistors,” IEEE Trans. on Electronic Devices, Vol. 45, No. 8, August 1998, pp. 1846–1848. [16] Chen, B., B. L. Ooi, and P. S. Kooi, “A Fast and Practical Approach to the Determination of Junction Temperature and Thermal Resistance for BJT/HBT Devices,” 9th Int. Conf. on Communications Systems, 2004, Sept. 7–7, 2004, pp. 588–591. [17] Prasher, R., “Thermal Interface Materials: Historical Perspective, Status, and Future Directions,” IEEE Proc., Vol. 94, No. 8, August 2006, pp. 1571–1586. [18] Prasher, R. S., and J. C. Matayabas, Jr., “Thermal Contact Resistance of Cured Gel Polymeric Thermal Interface Material,” IEEE Trans. on Components and Packaging Technologies, Vol. 27, No. 4, December 2004, pp. 702–709.

304

Thermal Design [19] Karmalkar, S., P. V. Mohan, and B. P. Kumar, “A Unified Compact Model of Electrical and Thermal 3-D Spreading Resistance Between Eccentric Rectangular and Circular Contacts,” IEEE Electronic Device Letters, Vol. 26, No. 12, December 2005, pp. 909–912. [20] Bhatt, A., and J. Rhee, “Thermal Spreading Resistance for Square and Rectangular Entities,” 11th Int. Symp. on Advanced Packaging Materials: Processes, Properties, and Interface, 2006, pp. 175–178. [21] Eudyna, FLK107XV. [22] Aavid Thermalloy, http://www.aavidthermalloy.com, last accessed April 30, 2009. [23] Wakefield Thermal Solutions, http://www.wakefield.com, last accessed April 30, 2009. [24] Cool Innovations, http://www.coolinnovations.com, last accessed April 30, 2009.

About the Authors Franco Sechi received his doctorate degree in electrical engineering from Polytechnic of Milano, Italy. He worked for 15 years at the RCA Laboratories in Princeton on R&D programs for solid-state power amplifiers. During this time he developed the first modern load-pull system, the first system to directly map the temperature in high power transistors using computer controlled infrared microscopy, and the first system for measuring current and voltage microwave waveform in power transistors. He also developed the first semimonolithic circuits on beryllia substrates. In 1986 he cofounded Microwave Power Inc. (MPI), a manufacturer of high performance solid-state power amplifiers, where he served as president and vice president. In 2004 MPI merged with AML Communications, a manufacturer of low-noise amplifiers. Dr. Sechi is presently retired and works as a consultant for MPI. He is the author of many papers and patents, a member of the editorial board of the IEEE Transactions on Microwave Theory and Techniques, a member emeritus of the MTT Technical Coordinating Committee on high power amplifier components, a member of the MTT-S Symposium Technical Program Committee, and a lifemember of the IEEE. Marina Bujatti received her doctorate degree in electronics engineering, cum laude, from the University of Rome (Italy), her M.S. in electrical engineering from the University of California, Berkeley, and her Ph.D. in solid-state physics from the University of Zagreb (Yugoslavia). She held teaching positions at the University of Roma (Italy) and the University of Nevada in both physics and engineering. In 1973 she joined Hewlett-Packard’s Microwave Technology Center where she developed the production process for the first GaAs FET made in the United States and available on the market, the HP300. After a few years in Italy, where she worked both on hybrid and GaAs monolithic microwave circuits in the research department of the Selenia (now Alenia) Company, she returned to HP’s Microwave Technology Division, where she was project manager for GaAs material research. In 1986 she cofounded Microwave Power Inc. (MPI), where she was responsible for technology development and was vice president and then president until her retirement in 2006.

305

Index 1/f noise, 9, 52, 78, 81 1-dB compression, 8, 67, 196–205 See also P1dB 2-DEG, 12, 46, 50 A ACPR, 253 measurement, 65 Activation energy, 287 gate metal inter-diffusion, 288 Adjacent Channel Power Ratio. See ACPR AlGaAs, 46 AlGaN, 13, 45, 50 AlInN, 50 Al-Si carbide composites 109 Alumina, 102 Aluminum Nitride, 103 AM/AM conversion, 66–67, 217, 227, 243 AM/PM conversion, 66–67, 217, 227, 242, 243 Amplifier device selection, 11–14, 149, 174 architecture, 6, 78, 96, 115 assembly, 109, 296 layout, See architecture noise, 77, 81, 89–96 specifications, 5–10 Arrhenius model, 287–88 Au/Ge eutectic, 33, 108 Avalanche breakdown, 27 Avalanche noise, 78, 80 B Back gating, 38, 94 Backoff mode, 217, 233 Backside effects, See Substrate effects

Balanced stage, 116–17 Band-gap, 20, See Energy gap Bandwidth, 6 vs. number of cells, 158, 161 See also Broadband matching Base station, 1, 11, 99, 251, 268 multiple carrier operation, 217 Behavioral model, 57, 240–43 Beryllia, 103 Bias circuit, active, 276–78 bandwidth, 230–32, 274, 275, 277 filtering, 273 gate current limiting, 274 impedance, 273–74, 276 pulsing, 282–84 stability, 273 transmission line resonances, 275 typical schematic, 274 Bias supply diagram, 278 Binary divider, 125 Bipolar transistor, 11, 17, 35, 149 low frequency noise model, 84 noise, 81–84, 89–90 vs. FET, 53 BJT, See Bipolar transistor Black box. See Behavioral model Blackbody radiation, 289 Bode and Fano equations, 156–57 theoretical analysis of matching, 155–58 Boltzmann distribution, 25 Breakdown, electric field for, 12 avalanche, 27, 43 Broadband amplifiers, 6–8, 110 Broadband matching, 150–58 filter network, 152, 156 first matching elements, 157 307

308

Broadband matching (continued) impedance ratio, 157, 158 in-band and out-of-band reflections, 156–57 input circuit, 154 parasitic elements inclusion, 152 reflection-coefficient theoretical limit, 156 rule, 152 technology implications, 105, 107, 157, 158 theoretical limit, 155–58 See also Bode and Fano Burst noise, 78 C C/I ratio, 221, 222, 224 Capacitor, energy storage, 282–83 Carrier to intermodulation ratio, See: C/I Carriers, chip or device, 109, 293, 296 Charge-pump device, 279 Chip and wire circuits, 100, 104 Chireix amplifier amplitude modulation, 263 efficiency, 266–67 load admittances, 265 load impedance modulation, 264 principle of outphasing, 264 reactive load impedances compensation, 265 signal component separator (SCS), 264, 267 Class A approximation, 231 asymmetry of efficiency vs. load resistance, 183–84 load-line slope vs. RF load-resistance, 181–83 Pout and efficiency vs. load line, 183 Class A optimal loading AM/AM conversion, 202–03 class A context definition, 200–01 compression, 203 Fourier components, 201 harmonic load impedance, 202 operating parameters vs. overdrive, 203

Index

relative load impedance, 202 relative output power, 202 waveforms, 201 Class A optimal power AM/AM conversion, 207 compression, 206 harmonic load impedance, 204 operating parameters vs. overdrive, 205 relative output power, 204 waveforms, 205 Class A tuned amplifier optimal load resistance, 164 output voltage, 164 Class AB clipped sinusoid id, 185 conduction angle, 187 experimental verification, 192 operating point locus, 185 Pout and efficiency @ constant RL vs. conduction angle, 187–90 Pout and efficiency @ constant Vpk vs. conduction angle, 191 Pout and efficiency @ constant Vpk vs. RL, 189–91 Rrf for constant Vpk, 191–92 series resonator output load, 185 single-clip sinusoid Fourier components, 185–87 nd peak value, 185 waveforms consistency, 185 Class B overdriven, optimal efficiency. See Class F Class B optimal power AM/AM conversion, 199 compression, 199 current Fourier components, 197–98 efficiency, 199 load impedance, 200 operating parameters vs. overdrive, 199 relative output power, 199 waveforms, 197–98 Class E, 205–12 capacitor charging, 209 current-voltage phase shift, 208, 210 design equations, 211–12 detuning inductor, 208 residual voltage vs. phase shift, 212

Index

simplifying assumptions, 208 switching loss, 212, 213 typical circuit, 207 waveforms, 209 Class F, 192–97 AM/AM conversion, 195 compression, 196 Fourier components, 193–94 load impedance, 194 operating parameters vs. overdrive, 194–95 overdrive factor, 193 Pout and efficiency vs. overdrive, 196 practical harmonic tuning, 214 relative load impedance, 195 waveforms, 192–93 Cold test, 59 Combiner, See Coupler Compound semiconductors, 12, 19, 37, 39 noise, 82 Compression, 8, 49, 196–205, 219, 224 Conduction band, 20, 25–26, 80–81 discontinuity in heterojunctions, 36–37, 51–52 Conical line characteristic impedance, 141 Conical waveguide combiner, 140–42 amplifier trays, 141 cooling, 141 Corner frequency, 9, 81, 84, 86, 89, 91 Coupler array, 142–44 “same type” couplers, 144 complementary, 142 Coupler, (180º), 115, 130–31 push-pull configuration, 130 ring hybrid schematic, 130 Coupler, branch-line, 122–25 broadband, 125 electrical schematic, 122, 123 layout, 123 response, 124 Coupler, hybrid, 116 Coupler, in-phase (0º), 115, 125–26 Coupler, interdigitated, 117–122 broadband, 120 even and odd modes, 121 multi-section, 120

309

radiation loss, 122 unfolded, 118–19 Coupler, Lange, 117–18 response, 119–20 Coupler, quadrature (90º), 116–29 Coupler, Wilkinson, 116, 125–29, 133 broadband, 128–29 electrical schematic, 125, 127 layout, 126 odd ports, 128 quadrature configuration, 126–28 response, 127–28 Couplers bandwidth comparison, 129 losses, 129 pattern resolution, 129 Crystal structures 19–21, 50 Cu/Mo, 109 Cu/W, 109, 296 Current modulation, from 2nd order distortion, 231 D Device life, 287–88 Diffusion noise, 78, 80 Digital predistortion, 243 Distortion amplitude, 66–67, 217, 218–226, 237–240 phase, 66–67, 217, 226–230, 237–240 Distributed pulsing, 282–284 Divider. See Coupler Doherty amplifier assumptions, 259 efficiency improvement, 260–61 GaN HEMT, 263 generator as a negative resistor, 259–60 impedance-inverting network, 261–62 phase shift, 262 principle of operation, 259–61 requirements, 262 schematic, 262 Drift velocity, 26 Driver, TTL-controlled, 282

310

Dual power supply configuration, 279 Duroid, 101

E EER, See: Kahn amplifier Effective mass, 26 Electrical parameter, used as thermometer CW measurement, 294–95 pulse measurement, 295 temperature calibration, 294 thermal resistance measurement, 295 thermal screening, 295 Electron affinity, 28 Electron velocity, 12, 39 Envelope Elimination and Restoration (EER) technique. See Kahn amplifier Emissivity, surface, 290 Emitter follower, compensated, 276–77 Energy gap, 12, 20 Envelope feedback amplitude response, 252 detector linearity, 252 modulation bandwidth, 253 phase response, 252

Index

G GaAs, 19, 38 electron velocity, 27 properties, 12–13, 103, 296 Gain compensation over temperature, 279–81 voltage regulator, 280–81 optimization routine, 281 simple thermistor network, 280 Gain compression, 219 Gain expansion, 8, 49, 219, 224, 249 GaInAs, 13 GaInP, 52 GaN, 6, 12, 19, 45, 50 electron velocity, 27 use in Doherty amplifier, 263 GaN/AlGaN heterojunction, 13, 45 Gate, 37–38 breakdown, 43, 70 T-shaped, 44 Generation-recombination noise, See G-R noise G-R noise, 78, 81 Graceful degradation, 115 Gunn diode, 11 Gunn effect, 13, 26

F Feedforward base stations, 251 design equations, 252 multiple nesting, 252 principle of operation, 251 typical IMD cancellation, 252 Fermi energy, 24 Fermi Level, 24 Fermi-Dirac distribution, 24–25 FET, 11, 17, 37 I-V characteristics, 39–43, 182 large-signal model, 69–71 low frequency noise model, 87 noise, 9, 84–86 RF voltage breakdown, 181 small-signal model, 58–59 Field Effect Transistors See FET Flicker noise. See 1/f noise Free electrons, 22, 78

H Harmonic balance comparison with load-line technique, 173 load-pull contours, 172–73 non-linear network analysis, 171–73 Harmonic termination, 185, 194, 196, 200, 202, 204, 214 HBT, 11–17, 51, 53 large-signal model, 71–74 noise, 82–83 small-signal model, 59–60 thermal effects, 53, 73–74 Heat 45º spreading, 297 dissipation, 5–6, 103, 109, 162, 295 spreading resistance, 297–98 Heat-sink, 5-6, 100, 101, 106, 287, 293, 296–297, 301–302

Index

bonded fins, 301 extrusion, 301 pin-fin, 302 Heat-sinking structure, 296 materials, 296 HEMT, 13, 45–46 I-V characteristics, 49 large-signal model, 69–71 metamorphic, 49 small-signal model, 58–59 Heterojunction Bipolar Transistor. See HBT Heterojunction, 27, 36–37, 45–53 High Electron Mobility Transistor. See HEMT Hole, 21 Hooge parameter, 81 Hot electrons, 80 Hybrid circuits, 102 I IMD, 8, 218, 224, 225, 227, 231 computed from P1dB, 222, 224 from amplitude and phase distortions, 227–29 in saturation region, 224 irregular response, 224 measured, 222–226 quadrature model, 225–26, 237–40 IMD measurement system, 236–37 IMD model behavioral, 240–43 combined amplitude and phase distortions, 237–40 TWT, 227, 240 Infrared. See IR InGaAs, 48 InGaN, 50 InP, 26, 50, 52, 110 electron velocity, 27 properties, 12–13 Input matching circuit, 153–54 Insulator, 21 Intermodulation distortion. See IMD Inverting circuit, 279 IP3, 222

311

IR microscope calibration, 290 thermal scan example, 291 InSn detector response, 290 objective, 290 pulsed mode, 291 Isolation between stages, 117, 126, 130, 131, 178 resistor, 125, 126, 132, 133, 135

J JFET, 37 Junction temperature CW mode, 298 pulse mode, 298–300 Junction forward-biased, 31 reverse-biased, 32

K K factor <1 design, 174 Rollet’s, 173–75 stability criterion, 174 Kahn amplifier, 268–70 IF-frequency implementation, 269 modulation bandwidth, 270 RF instantaneous bandwidth, 270 time delay equalization, 269

L Large-signal model Curtice-Ettenberg, 69–71 Gummel-Poon, 71 HBT, 71–74 HEMT, 69–71 MESFET, 69–71 thermal, 73–74 validation, 69 Large-signal characterization, 60–69 parameters, 66–67 parameters test set, 66

312

Large-signal (continued) S-parameters, validity of, 66 VNA, 66 LDMOS, 11, 149 Life time, 287 LINC. See Linear amplification with nonlinear components Linear amplification with nonlinear components, 268 Linear amplifier main operating parameters, 233 optimum path, 234–35 power and IM3 contours, 233–35 unique set of operating parameters, 233 Linearity, 8, 91, 217–232 Linearizer dual path reflection-type, 249 dual-gate FET, 249 dynamic range, 249 series diode, 245 shunt FET, 249 shunt HBT, 249 single path reflection-type, 248 stability, 250 Liquid crystal temperature measurement, 292–93 set-up, 292 transition temperature, 292 Load time-constant, 156 Load-line design, 166–71 5-section lumped-element transformer, 169–71 5-section l/4 transformer, 167–69 validity, 165–66 Load-pull, 60–65 active, 65 calibration, 63 double-slug tuner, 61–62 harmonic tuning, 65 optimal load impedance, 150 output circuit design, 149–50 power contours, 64–65 pre-matching circuits, 60–61 probe tuner, 62 search algorithm, 63–64 set up, 60–61

Index

Lorentzian spectrum, 81, 83, 94 Low frequency noise, 82 FET vs. bipolar, 85–87 See also: 1/f noise Low Temperature Co-fired Ceramics, 99 Lumped-element transmission line, 131–32 l/4 transformer, 131–32 M Magic T, 131 MBE, 11, 36, 108 Memory effects bias-circuit bandwidth, 230, 232 electron traps, 232 thermal, 232 MESFET, 37 equivalent circuit, 41 gate, 38 I-V characteristics, 39 large-signal model, 69–71 ohmic contacts, 38 power, 43 small-signal model, 58–59 transconductance, 40 Metal-Organic Chemical Vapor Deposition, See MOCVD Metal-semiconductor junction, 27 MIC, 100 substrates, properties, 103 Microstrip 100, 101, 102, 125, 168–170 Microwave Integrated Circuit. See MIC Microwave Monolithic Integrated Circuits. See MMIC Microwave Printed Circuits, 100 M-IMR, 254 Miniature hybrid. See Semimonolithic circuits MMCC, 106–107, 157 See also Semimonolithic circuits MMIC, 6, 8, 100, 108, 110, 112 carrier, 109 processs flow, 108 Mobility, 12, 26, 45

Index

MOCVD, 11, 36 Modulation bandwidth, 232, 253, 270, 275, 277 Molecular Beam Epitaxy. See MBE MOSFET, 32, 37 Multitone Intermodulation Ratio. See M-IMR

N Nematic liquid crystals, 292 Noise 1/f, See 1/f noise backside effects on, 86 compound semiconductors, 82 figure, 77 bipolars, 81–84 FETs, 84–86 HBT, 82–83 phase. See Phase noise power Ratio. See NPR sources, 81 NPR, 254

O Ohmic contacts, 27, 33, 38, 108 Optimal load impedance vs. S22*, 166 Oscillations bias, 178–79, 273 internal mixing, 175–76 internal path, 175–76 low level, 175 Oscillations, parametric, 176–78 broken spectrum, 176 hysteresis, 176 idler high-Q circuit, 178 origin, 176–78 power drop, 176 simulation, 178 voltage breakdown, 178 Output capacitance, equivalent, 165 Output impedance vs. optimal load, 64–65 Output matching design, reciprocal configuration, 165–66, 167

313

P P1dB, 217, 221, 224, 225 amplitude distortion only, 217 See also 1–dB compression Parameter extraction direct, 59, 60 from S-parameters, 58–59 Parasitic source inductance, 162 Pauli Exclusion Principle, 18 Peak power of multi-tone signal, 222 Phase distortion, origin, 226–27 Phase noise, 9, 88 amplifiers, 89 GaAs FET power amplifier, 92 PHEMT, 13, 48–49 Planck’s law, 289 p-n junction, 27, 33, 35 Polynomial mathematical instability, 222, 243 Power at 1dB compression. See P1dB Power contours. See Load-pull Power series ill-defined coefficients, 241–42 limitations, 241–42 Predistortion, 243–44 See also Linearizer Pseudomorphic High Electron Mobility Transistor. See PHEMT Pulsing, 10, 282–285 module, 282 Q Quantum mechanics, 17 R Radial full-size waveguide combiner, 135–36 20 GHz amplifier, 137 bandwidth, 136 conduction cooling, 135–36 power modules, 135 Radial line, 136–40 characteristic impedance, 138–39 curvature, 139

314

Radial line (continued) dominant mode, 137 normalized admittance, 136 cascade model, 139–40 strip impedance, 139 Radial microstrip combiner, 132–34 ground reversal, 133–34 isolation resistors, 133 secondary line, 134 Wilkinson divider, 133 Radial thin-waveguide combiner, 134–35 conduction cooling, 135 isolation resistor, 135 microstrip transition, 135 substrate, 135 l/4 radial slot, 135 Reflection cancellation, 116–17 Relative life time, 288 Rollet’s k factor. See K factor

S Saturation. See Compression Schrödinger’s equation, 17 Self-heating effects. See Large-signal model, thermal Semiconductor, 12, 18, 21 Semi-monolithic ceramic circuits, 100 process flow, 107 Series to parallel impedance transformation, 153 Shot noise, 78, 79 Shottky barrier voltage breakdown, power limitation from, 70 Shottky diode anti-parallel configuration, 250 circuit schematic, 246 current vs. RF input power, 246 differential resistance, 245 I-V characteristic, 244–45 reflection coefficient vs. RF input power, 247 Si, 18, 21, 35, 37, 100, 110 electron velocity, 27 properties, 12–13 SiC, 6, 12–13, 45

Index

Silicon nitride, 107 Silvar, 109 Single power supply configuration, 279 Single-tone, Pout vs. Pin characteristic, 221 Small-signal model, 57–60 HBT, 59–60 FET, 58–59 HEMT, 58–59 MESFET, 58–59 characterization, 57–60 S-parameters vs. bias, 67–68 Solid-State Power Amplifier. See SSPA Source follower, compensated, 277–78 S-parameters, pulsed, 68 Spectrum asymmetry bias circuit bandwidth, 230, 232 low-level signal, 231 memory effects, 230–32 two-tone test, 230–32 Spectrum symmetry, two-tone test, 220, 230 SSPA, 1, 3, 5 Stefan-Boltzmann equation, 290 Stripline 8, 101, 125 Substrate effects, 44, 85, 86 See also back gating Surface states, 28–29, 38–39

T Taylor series uncertainty of high-order derivatives, 241 nonlinear model, 241–42 Temperature measurement electrical parameter, 294 IR microscopy, 289 liquid crystal, 291 Thermal Interface Materials, 297 Thermal noise, 78 Thermal properties, 12, 103, 296 Thermal resistance spreading, 297 GaAs FET, 293 total, 298

Index

Thermal structure electrical equivalent circuit, 299 time constants, 299 Thermal time constant, FET chip, 299 Thermionic emission, 32 Third-order intercept point. See IP3 Traveling Wave Tube. See TWT Tuned amplifier, 163–64, 181 Tunneling, 32 Two dimensional electron gas. See 2-DEG Two-tone intermodulation measurement, equivalency with ACPR, NPR and M-IMR, 255 Two-tone, 3rd order intermodulation vs. Pin, 221 distortion, 219 Two-tone test dc products, 219 harmonics, 218–219 intermodulation, 219 nonlinearities effect, 218 output signal, three terms, 218–219 output spectrum, 221 products order-number, 219 third-degree polynomial, 218 Two-tone amplitude modulation frequency, 220 phase reversal, 220

315

spectrum, 221 time domain representation, 220 TWT, 1, 5, 227, 243 V Valence band, 20 Via holes, 45, 109 solid, 106 VNA, Vector Network Analyzer, 57, 65–67 Voltage followers, compensated, 276–78 Volterra series computational instability, 243 model parameters extraction, 242 nonlinear model, 242 Taylor-series nonlinear elements, 242 weak nonlinearities, 242 W Waveguide, 6, 99–100, 101 conical, 140–142 couplers, 116, 125, 131 radial, 134–140 White noise, 78, 80 Wide bandgap semiconductors, 6, 13, 45 Wire-bond inductance, 159–162 Work function, 27

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