Omnidirectional Inductive Powering for Biomedical Implants

Biopotential Readout Circuits for Portable Acquisition Systems

ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES Consulting Editor: Mohammed Ismail. Ohio State University Titles in Series: OMNIDIRECTIONAL INDUCTIVE POWERING FOR BIOMEDICAL IMPLANTS Lenaerts, Bert, Puers, Robert ISBN: 978-1-4020-9074-5 BIOPOTENTIAL READOUT CIRCUITS FOR PORTABLE ACQUISITION SYSTEMS Yazicioglu, Refet Firat, Van Hoof, Chris, Puers, Robert ISBN: 978-1-4020-9092-9 STRUCTURED ANALOG CMOS DESIGN Stefanovic, Danica, Kayal, Maher ISBN: 978-1-4020-8572-7 LOW POWER UWB CMOS RADAR SENSORS Paulino, Nuno, Goes, João, Steiger Garção, Adolfo ISBN: 978-1-4020-8409-6 ANALYSIS AND DESIGN OF QUADRATURE OSCILLATORS Oliveira, L.B., Fernandes, J.R., Filanovsky, I.M., Verhoeven, C.J.M., Silva, M.M. ISBN: 978-1-4020-8515-4 THE GM/ID DESIGN METHODOLOGY FOR CMOS ANALOG LOW POWER INTEGRATED CIRCUITS Jespers, Paul G.A. ISBN-10: 0-387-47100-6 LOW-POWER HIGH-SPEED ADCS FOR NANOMETER CMOS INTEGRATION Cao, Zhiheng, Yan, Shouli ISBN: 978-1-4020-8449-2 SUBSTRATE NOISE COUPLING IN RFICS Helmy, Ahmed, Ismail, Mohammed ISBN: 978-1-4020-8165-1 CIRCUIT AND INTERCONNECT DESIGN FOR HIGH BIT-RATE APPLICATIONS Veenstra, Hugo, Long, John R. ISBN: 978-1-4020-6882-9 HIGH-RESOLUTION IF-TO-BASEBAND SIGMADELTA ADC FOR CAR RADIOS Silva, Paulo G.R., Huijsing, Johan H. ISBN: 978-1-4020-8163-7 MULTI-BAND RF FRONT-ENDS WITH ADAPTIVE IMAGE REJECTION A DECT/BLUETOOTH CASE STUDY Vidojkovic, V., van der Tang, J., Leeuwenburgh, A., van Roermund, A.H.M. ISBN: 978-1-4020-6533-0 SILICON-BASED RF FRONT-ENDS FOR ULTRA WIDEBAND RADIOS Safarian, Aminghasem, Heydari, Payam ISBN: 978-1-4020-6721-1 DESIGN OF HIGH VOLTAGE XDSL LINE DRIVERS IN STANDARD CMOS Serneels, Bert, Steyaert, Michiel ISBN: 978-1-4020-6789-1 HIGH-LEVEL MODELING AND SYNTHESIS OF ANALOG INTEGRATED SYSTEMS Martens, Ewout S.J., Gielen, Georges ISBN: 978-1-4020-6801-0 BASEBAND ANALOG CIRCUITS FOR SOFTWARE DEFINED RADIO Giannini, Vito, Craninckx, Jan, Baschirotto, Andrea ISBN: 978-1-4020-6537-8 CMOS MULTI-CHANNEL SINGLE-CHIP RECEIVERS FOR MULTI-GIGABIT OPT... Muller, P., Leblebici, Y. ISBN 978-1-4020-5911-7 ANALOG-BASEBAND ARCHITECTURES AND CIRCUITS FOR MULTISTANDARD AND LOW-VOLTAGE WIRELESS TRANSCEIVERS Mak, Pui In, U, Seng-Pan, Martins, Rui Paulo ISBN: 978-1-4020-6432-6 FULL-CHIP NANOMETER ROUTING TECHNIQUES Ho, Tsung-Yi, Chang, Yao-Wen, Chen, Sao-Jie ISBN: 978-1-4020-6194-3

Refet Fırat Yazıcıo˘glu Chris Van Hoof Robert Puers •

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Biopotential Readout Circuits for Portable Acquisition Systems

Dr. Refet Fırat Yazıcıo˘glu Katholieke Universiteit Leuven Interuniversity Microelectronics Center (IMEC) Kapeldreef 75 3001 Leuven Heverlee Belgium Email: [email protected]

Prof. Dr. Robert Puers Katholieke Universiteit Leuven Dept. Electrical Engineering (ESAT) Kasteelpark Arenberg 10 3001 Leuven Belgium Email: [email protected]

Prof. Dr. Chris Van Hoof Katholieke Universiteit Leuven Interuniversity Microelectronics Center (IMEC) Kapeldreef 75 3001 Leuven Heverlee Belgium Email: [email protected]

ISBN 978-1-4020-9092-9 e-ISBN 978-1-4020-9093-6 Library of Congress Control Number: 2008934402 All Rights Reserved © 2009 Springer Science + Business Media B.V. No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Printed on acid-free paper 9 8 7 6 5 4 3 2 1 springer.com

To my parents and sister, Hüseyin, Betil, and Gözde Yazıcıo˘glu; and to my wife, Begüm Yazıcıo˘glu

Acknowledgements

Before the start of this text I would like to express my sincere gratitude to friends, colleagues, and family. First of all, I would like to express my appreciation and thanks to my supervisors Prof. Chris Van Hoof and Prof. Robert Puers for their valuable guidance, support and comments. I would like to thank my M.S. thesis supervisor Prof. Tayfun Akin and METUMEMS group members. Prof. Akin is actually the person, who has introduced me to microelectronics and circuit design. I would like to thank the members of ULPEXEL team of IMEC vzw, Belgium. To start with, many thanks goes to Prof. Patrick Merken for the valuable discussions and guidance and also for turning the office environment into a fun place. I would like to thank Tom Torfs for his helps during the testing of the ASICs and discussions we had about the system implementations. He has written lots of test softwares for me. I would like to thank Jan Putzeys for helping me during the usage of the instruments in his lab. Many thanks also go to Munir Abdalla, Ybe Creten, Inge Doms, Burak Okcan, Junaid Aslam, and Tim Souverijns for the enjoyable office and research environment that they have created at IMEC. I also would like to thank many past and present colleagues. Just a few to name: Mehmet Akif Erismis, Deniz Sabuncuoglu, Didem Ernur, Mustafa Badaroglu, Kris Verheyen, Koen De Munck, Caroline Geuens, Hercules Pereira Neves, Christophe Winters, Xavier Rottenberg, Kuba Raczkowski, Tom Sterken, Fre Vanaverbeke, and Vladimir Leonov. I am grateful to IMEC and the Katholieke Universiteit Leuven (K.U. Leuven). Both IMEC and K.U. Leuven provide me the necessary means to conduct my Ph.D. research in an excellent environment. I am also grateful to the employees of INVOMEC department, Steve Mattheus, Greta Milzanowski, Marc Van Eylen, and Kurt Van Genechten, for their patience to my endless questions and for their help with all my software and tape-out related problems. I would like to thank my dear friends, Arda, Sencer, and Emrah for the fun we had for all those years. Other friends to mention are Rana, Ozlem, and Onur. I also would like to express my sincere greetings to my cousin and her husband, Tugba and Fatih Vardareli. I would like to open a special paragraph for my parents and my sister. Without their unlimited love and support, it would not be possible to overcome the tough challenges of Ph.D. research and living abroad. I am grateful to them and my love for them is endless. I also would like to thank my aunt, Yildiz Sakin, and my grandfather, Hilmi Gozen, who are as close as a mother and a father to me. When it comes to thank my wife, Begum Yuksel, words are just not enough. I am grateful for her patience and support for me. Leuven, Belgium

Refet Fırat Yazıcıo˘glu July 2008 vii

Contents

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Introduction . . . . . . . . . . . . . . 1.1 Ambulatory Health Care Systems 1.2 Body Area Networks . . . . . . . 1.3 Scope of the Book . . . . . . . .

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Introduction to Biopotential Acquisition . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Introduction to Biopotential Signals . . . . . . . . . . . . . . . . 2.3 Introduction to Biopotential Electrodes . . . . . . . . . . . . . . 2.3.1 Equivalent Circuit Model . . . . . . . . . . . . . . . . . 2.3.2 Types of Biopotential Electrodes . . . . . . . . . . . . . 2.4 Introduction to Biopotential Amplifiers . . . . . . . . . . . . . . 2.4.1 Interference Theory . . . . . . . . . . . . . . . . . . . . 2.4.2 Noise-Efficiency Factor (NEF) of Biopotential Amplifiers 2.4.3 State-of-the-Art in Instrumentation Amplifier Design . . 2.5 Introduction to Chopper Modulation Technique . . . . . . . . . . 2.5.1 Noise Analysis of Chopper Modulation Technique . . . . 2.5.2 Charge Injection and Residual Offset of Chopper Modulated Amplifiers . . . . . . . . . . . . . . . . . . . 2.5.3 Signal Distortion in Chopper Modulated Amplifiers . . . 2.5.4 CMRR of the Chopper Modulated Amplifiers . . . . . . 2.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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24-Channel EEG Readout Front-End ASIC . . . . . . . . . . . 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 ASIC Architecture . . . . . . . . . . . . . . . . . . . . . . . 3.3 Current Balancing IA . . . . . . . . . . . . . . . . . . . . . 3.3.1 Implementation . . . . . . . . . . . . . . . . . . . . 3.3.2 Measurement of Performance . . . . . . . . . . . . . 3.4 CMRR Model for Biopotential Instrumentation Amplifiers . . 3.4.1 Systematic CMRR . . . . . . . . . . . . . . . . . . . 3.4.2 CMRR Limit Due to Differential DC Electrode Offset 3.4.3 Verification of the CMRR Model . . . . . . . . . . . 3.5 Programmable Gain Stage . . . . . . . . . . . . . . . . . . . 3.5.1 Finite-Gain Compensated SC Amplifier . . . . . . . . 3.5.2 Programmable Gain Stage Implementation . . . . . . 3.6 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . .

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Biopotential Readout Front-End ASICs . . . . . . 4.1 Introduction . . . . . . . . . . . . . . . . . . . 4.2 AC Coupled Chopper Modulated IA (ACCIA) . 4.2.1 Architecture of the ACCIA . . . . . . . 4.2.2 Architecture of the CBIA . . . . . . . . 4.2.3 Power-Noise Performance of the ACCIA 4.3 Chopping Spike Filter (CSF) . . . . . . . . . . 4.4 Low-Power Programmable Gain Stage . . . . . 4.5 Single-Channel ExG Readout Front-End . . . . 4.5.1 Implementation . . . . . . . . . . . . . 4.5.2 Measurement of Performance . . . . . . 4.5.3 Biological Test Results . . . . . . . . . 4.6 Eight-Channel EEG Readout Front-End . . . . . 4.6.1 Implementation . . . . . . . . . . . . . 4.6.2 Measurement of Performance . . . . . . 4.6.3 Biological Test Results . . . . . . . . . 4.7 Comparison with the State-of-the-Art . . . . . . 4.8 Conclusions . . . . . . . . . . . . . . . . . . .

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A Complete Biopotential Acquisition ASIC . . . . . 5.1 Introduction . . . . . . . . . . . . . . . . . . . . 5.2 ASIC Architecture . . . . . . . . . . . . . . . . . 5.3 Bias Generator Circuit . . . . . . . . . . . . . . . 5.4 Class-AB Buffer Architecture . . . . . . . . . . . 5.5 ACCIA with Coarse-Fine Servo-Loop . . . . . . . 5.5.1 Structure of the ACCIA . . . . . . . . . . 5.5.2 Coarse Transconductance (CGM) Stage . . 5.5.3 Fine Transconductance (FGM) Stage . . . 5.5.4 Integrator Stage . . . . . . . . . . . . . . 5.5.5 Current Balancing IA (CBIA) Architecture 5.5.6 Gain Stage . . . . . . . . . . . . . . . . . 5.5.7 Implementation of the ACCIA . . . . . . 5.5.8 Fast Start-Up of the ACCIA . . . . . . . . 5.5.9 Power-Noise Performance of the ACCIA . 5.5.10 Measurement of Performance . . . . . . . 5.5.11 Comparison with State-of-the-Art . . . . . 5.6 Chopping Spike Filter . . . . . . . . . . . . . . . 5.7 Low-Power Programmable Gain Stage . . . . . . 5.8 Readout Front-End Channel Test Results . . . . . 5.9 Square Wave Relaxation Oscillator . . . . . . . . 5.10 Analog-to-Digital Converter . . . . . . . . . . . . 5.10.1 Basic Operation Principle . . . . . . . . . 5.10.2 Architecture . . . . . . . . . . . . . . . . 5.10.3 Capacitive DAC Implementation . . . . . 5.10.4 Low-Offset Comparator Implementation .

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Wireless Biopotential Acquisition Systems . . . . . . . . . . . 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 A Wireless VEMP Acquisition System . . . . . . . . . . . 6.3 A Wireless Two-Channel ExG Acquisition System . . . . . 6.4 A 1 cm3 Wireless Eight-Channel EEG Acquisition System . 6.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . .

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Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 7.1 Achievements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 7.2 Suggestions for Future Work . . . . . . . . . . . . . . . . . . . . 149

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5.10.5 Test Results . . . . . . . . . . . . . . . Impedance Measurement and Calibration Modes Biological Test Results . . . . . . . . . . . . . Summary of the Biopotential Acquisition ASIC Conclusions . . . . . . . . . . . . . . . . . . .

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Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Symbols and Abbreviations

Symbols ACM Av BW Cbg Cbp Ciso Cin Cox Eg fc fc,1/f fchop fCSF fLP,IA gds gm go ID Ids Itot k KF F μp n q Rds Rel Rs S0 T VCM Velec-off ,max Vgs Vin,rms Vsg Vsd Vt

Common-mode gain of an amplifier Open-loop gain of an amplifier −3 dB bandwidth of an amplifier (Hz) Coupling capacitor between body and earth ground Coupling capacitor between body and mains Isolation capacitance between earth ground and battery Input capacitance Gate-oxide capacitance per unit area (F/cm2 ) Bandgap energy of silicon (≈1.12 eV) Low-pass cut-off frequency of an amplifier Corner frequency of the 1/f noise Chopping clock frequency Operating frequency of the CSF stage Low-pass cut-off frequency of the IA Output transconductance of a MOS transistor Transconductance of a MOS transistor Output transconductance of a current source Displacement current through human body Drain current of a MOS transistor Total supply current Boltzmann constant = 1.3806 × 10–23 m2 kg/s2 1/f noise constant of a MOS transistor (C2 /cm2 ) Mobility of pMOS transistors Weak inversion slope factor (= 1.45 in AMIS 0.5 µm technology) Unit charge = 1.6 × 10–19 C Drain-to-source resistance of a MOS transistor Electrode impedance Source resistance Thermal noise level of an amplifier Absolute temperature in Kelvin Common-mode voltage on the human body Maximum differential DC electrode offset voltage that can be filtered by ACCIA Gate-to-source voltage of a nMOS transistor Input-referred total RMS voltage noise Source-to-gate voltage of a pMOS transistor Source-to-drain voltage of a pMOS transistor Thermal voltage kT /q xiii

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Symbols and Abbreviations

Abbreviations ACM ACCIA ADC ADM CMFB CBIA CMRR CMRReq CMRRgds CMRRgo CMRRsys CMOS CGM CSF DAC DSP ECG EEG EMG EOG FGM HPF IA LPF NEF nMOS OTA pMOS PSG PSD RGC RMS S&H SAR SC SFDR SNDR SPI SPL STFT T&H TC THD

Common-mode gain of an amplifier AC Coupled Chopper Modulated Instrumentation Amplifier Analog-to-Digital Converter Differential-mode gain of an amplifier Common Mode Feedback Current Balancing (or Feedback) IA Common Mode Rejection Ratio Equivalent CMRR including all the limiting mechanisms CMRR limit due to gds mismatch of the input pair transistors CMRR limit due to go mismatch of current sources Systematic CMRR Complementary Metal Oxide Semiconductor Coarse Transconductance Chopping Spike Filter Digital-to-Analog Converter Digital Signal Processing Electrocardiogram Electroencephalogram Electromyogram Electrooculogram Fine Transconductance High-Pass Filter Instrumentation Amplifier Low-Pass Filter Noise-Efficiency Factor n-Channel Metal Oxide Semiconductor Operational Transconductance Amplifier p-Channel Metal Oxide Semiconductor Polysomnography Power Spectral Density Regulated Cascode Current Mirror Root-Mean-Square Sample-and-Hold Successive Approximation Switched-Capacitor Spurious Dynamic Range Signal-to-Noise Dynamic Range Serial Peripheral Interface Sound Pressure Level Short-Time Fourier Transform Track-and-Hold Temperature Coefficient Total Harmonic Distortion

Symbols and Abbreviations

VEMP VGA WHO WLAN

Vestibular Evoked Myogenic Potential Variable Gain Amplifier World Health Organization Wireless Local Area Network

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Chapter 1

Introduction

1.1 Ambulatory Health Care Systems Experts indicate that as many as 98,000 people die only in US each year at hospitals as a result of medical errors, such as diagnostics and treatment that could have been prevented. This is more than die from motor vehicle accidents, breast cancer, or AIDS. Therefore, the cost of faulty medical errors is actually higher than some causes that receive far more public attention. Interestingly, these medical errors are more commonly caused by faulty systems and conditions that lead people to make mistakes other than the people themselves [1]. A typical example for a faulty diagnostics can be the diagnosis of the epilepsy seizures that requires continuous monitoring of the patient at the hospital, which is a costly endeavor. Since it removes the patient from his or her routine, the diagnostics can be affected. A possible solution to this problem is the ambulatory monitoring of the patients. This can not only enable the patient to live his or her routine and improve the diagnostics, but also can reduce the medical cost [2]. However, the ambulatory monitoring of the patients’ requires an adequate technology platform for the support of the patient. The e-Health project, “The use, in the health sector, of digital data—transmitted, stored and retrieved electronically—in support of health care, both at the local site and at a distance.” as defined by WHO, can be the platform for the support and the diagnostics of the patients. E-health is claimed to offer the potential to reduce the medical cost, enable personalized health care, deliver remote health services, and increase the delivery efficiency in real-time. Therefore, the gathering of fast and reliable medical information from the patient lies in the center of the e-Health project, which can be achieved through implementation of biomedical sensors in Body Area Networks (BAN).

1.2 Body Area Networks Body Area Network [3] is a composition of miniaturized sensors and actuators that are attached to the human body, and capable of communicating with each other and/or with a central node worn on the body, Fig. 1.1 [4]. Each sensor node carries its own power source, and implements enough intelligence for standalone operation. The central node communicates with the outside world using a standard telecommunication infrastructure, such as WLAN or a cellular phone network, so that a medical personal can diagnose the results. Further improvement of the BAN system can add more intelligence to the nodes for the treatment of diseases and drug delivery. However, the realization of the BAN requires innovative solutions for the following technological problems: R.F. Yazıcıo˘glu et al., Biopotential Readout Circuits for Portable Acquisition Systems, © Springer Science + Business Media B.V. 2009

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Introduction

Fig. 1.1 The technology vision for the year 2010

• The power dissipation of the nodes must be improved for a better power autonomy. • The size and the weight of the sensor nodes must be reduced for invisibility and comfort. • New integration and packaging techniques must be developed to decrease the form factor and reconcile the sensor nodes with the human body. • Intelligence of the sensor nodes must be improved in order to shift from the treatment of the diseases towards the prevention of the diseases. • The sensor nodes should include its own energy source, which consists of energy generation and storage. • The cost of the system must be minimized. On the other hand, the nodes must be able to deal with the following implementation issues [5]: • • • •

Reliability, robustness, and durability. Look/unobtrusiveness. User identification. Zero maintenance and fault recovery.

So that the sensor nodes can be integrated in the every-day life of the human beings.

1.3 Scope of the Book A crucial and important part of a medical diagnostics system is the monitoring of the biopotential signals. These signals are recorded routinely in the modern clinical

1.3 Scope of the Book

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Fig. 1.2 A biopotential sensor node architecture indicating the scope of this Book

practice. Commonly, patients are connected to a bulky and mains-powered instrument, which reduces their mobility and creates discomfort. This limits the acquisition time, prevents the continuous monitoring of patients, and affects the diagnostics of the illness. Therefore, there is a growing demand for low-power, small-size, and ambulatory biopotential acquisition systems [2, 4, 6–9]. The ultimate goal is to implement a biopotential acquisition system that is comfortable and invisible to eye with long-term power autonomy, high signal quality, and configurability for different biopotential signals. The aim is not only to increase the patients’ quality of life, but also to extend device applications to sports, entertainment, comfort monitoring, etc. Therefore, intelligent and miniaturized biopotential acquisition sensor nodes can improve the functionality of a BAN system. The most critical demands for these sensor nodes are the ultra low power dissipation and minimal size for the improved autonomy. However, it should be noted that the signal quality must not be sacrificed for extending the power autonomy of the sensor nodes. Figure 1.2 shows the architecture of a typical biopotential acquisition sensor node. A crucial and power consuming building block of this sensor node is the readout front-end, which defines the quality of the extracted signals. However, long-term power autonomy dictates the need for low-power circuitry, putting strict design constraints on the readout front-end circuit. The challenges for designing a biopotential readout front-end circuit can be summarized as follows: Due to the low frequency behavior of the signals, in-band noise of the readout is dominated by 1/f noise. Moreover, the common-mode interference from the mains to the human body disturbs the biopotential signals [10], and there is the problem of electrode offset generated at the skin-electrode interface [11]. Therefore, in order to achieve signal extraction under these circumstances a readout front-end is needed with high CMRR, low-noise, and band-pass filter characteristics. Moreover, amplitude and bandwidth characteristics of biopotential signals vary

4

Introduction

for different biopotential signals, and different applications of these signals. Therefore, the front-end should have configurable gain and filter characteristics. As a consequence, this thesis describes the design and the implementation of lownoise and low-power ASICs convenient for the acquisition of different biopotential signals. This enables the implementation of miniaturized biopotential acquisition sensor nodes with long-term power autonomy. It should be noted that the circuits described in this thesis do not want to sacrifice performance for reducing power dissipation. Instead, the goal is to increase the performance of the readout circuits and decrease their power dissipation simultaneously.

Chapter 2

Introduction to Biopotential Acquisition

2.1 Introduction The biopotential readout circuits have to cope with various problems, while extracting the biopotential signals from the human body. These problems are not only due to the extremely weak characteristics of the biopotential signals but also due to the environment and the apparatus that are being used during the signal acquisition. Therefore, the design of a readout circuit for the biopotential acquisition systems requires a solid understanding of not only the analog circuit design techniques but also the origin and the characteristics of the biopotential signals. This Chapter gives a brief introduction to the challenges of extracting biopotential signals. Section 2.2 introduces the genesis of the biopotential signals, and presents the frequency and the amplitude characteristics of the EEG, ECG, and EMG signals. Section 2.3 explains the chemistry of the biopotential electrodes, which acts as a transducer between the human body and the readout circuit, and describes the non-ideal characteristics of the biopotential electrodes. Section 2.4 introduces the interference theory, i.e. the theory of the common-mode interference from the mains. This Section also presents the state-of-the-art in IA design, the building block that defines the quality of the extracted signals from the biopotential electrodes. Section 2.5 describes the chopper modulation technique, which is used in the literature to achieve low-noise and high-CMRR IAs. Finally, Sect. 2.6 states the conclusions of this Chapter.

2.2 Introduction to Biopotential Signals Biopotential signals are generated due to the electrochemical activity of certain class of cells that are components of the nervous, muscular or glandular tissue. Electrically, these cells exhibit a resting potential, and when they are stimulated they generate an action potential. The electrical activity of each cell is described by the ion exchange through the cell membrane. The membrane potential of an inactive cell is called the resting potential. At the rest state, the membrane of the cell is more permeable to K+ than Na+ , and K+ concentration of the interior of the cell is much higher than the exterior. Therefore, a diffusion gradient of K+ occurs towards the exterior of the cell making the interior more negative relative to the exterior, which results in an electrical field build up towards the interior of the cell. At steady state, the diffusion gradient of the K+ ions are balanced by the electrical field and the equilibrium is reached with a polarization voltage of nearly −70 mV. When the cell is electrically stimulated (through the central nervous system), the permeability of R.F. Yazıcıo˘glu et al., Biopotential Readout Circuits for Portable Acquisition Systems, © Springer Science + Business Media B.V. 2009

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Introduction to Biopotential Acquisition

Fig. 2.1 Frequency and amplitude characteristics of the biopotential signals, EEG, ECG, and EMG, and the correlating signals of the biopotential signals

the membrane to Na+ ions increases. Thus, Na+ ions diffuse toward the inside of the cell, resulting in a potential increase of the interior of the cell. As the potential reaches to +40 mV, the permeability of the membrane to Na+ ions decreases and to K+ increases, resulting in a sharp decrease in the membrane potential towards its rest state. This cycle of the cellular potential is called the action potential, and the biopotential signals, such as EEG, ECG, EMG, are the result of several action potentials produced by a combination of different cells [11]. EEG is the measure of the electrical activity of the brain created by a group of neurons. Electrodes are placed on the predefined locations of the scalp [12], and the voltage of the electrodes versus a reference is measured. Similarly, ECG is the measure of the electrical activity of the heart. It is extracted from the electrodes on the chest, and it is characterized by its three main features, the P-wave, the QRScomplex, and the T-wave [11]. Finally, EMG is the electrical potential of the skeletal muscle cells, which is generated during the contraction of the muscle. Figure 2.1 shows the frequency and amplitude characteristics of EEG, ECG, and EMG waves, when recorded by surface electrodes [11]. In order to extract the biopotential signals, the correlating signals, such as the 1/f noise of the CMOS transistors, the interference from the mains, and the DC differential electrode offset voltage between the biopotential electrodes, must be rejected or filtered by the readout circuit.

2.3 Introduction to Biopotential Electrodes Although readout circuits implemented in CMOS technology usually have very large input impedance, a non-zero current should flow from the body to the input

2.3 Introduction to Biopotential Electrodes

7

of the readout circuit. However, this current is carried by ions in the body, whereas it is carried by electrons on the wires connecting the electrodes to the readout circuit. Therefore, a transducer interface is necessary between the body and the readout circuit that converts the ionic current into electronic current, or vice versa. This interface is called a biopotential electrode. The operation principle of a biopotential electrode can be described by an electrode–electrolyte interface. In order to allow the current flow between the electrolyte, which has no free electrons, and the electrode, which has no free cations or anions, a chemical reaction has to occur at the interface that can be represented by the following general equations: C ↔ C+ + e− A− ↔ A + e −

(2.1)

In this equation, C and A stands for the cations and anions in the electrolyte, respectively, and it has been assumed that the electrode is made up of the cations of the electrolyte. Therefore, the cations in the electrode can oxidize at the interface, and the anions coming to the interface can be oxidized to a neutral atom, both resulting in a free electron in the electrode. Thus, current can pass from the electrode to the electrolyte. Similarly, the reduction reactions create current in the reverse direction. Therefore, if a metal is inserted in a solution, which has the ions of the same metal and some anions to preserve the neutrality of the solution, the reactions given in (2.1) starts to occur depending on the concentration of the cations in the solution. This disturbs the neutrality of the solution, and a charge gradient builds up at the electrode–electrolyte interface, resulting in a potential difference that is called the half-cell potential. The mismatch of the half-cell potential between the reference electrode and the recording electrode is responsible for the differential DC electrode offset voltage.

2.3.1 Equivalent Circuit Model Biopotential electrodes can be grouped as, polarizable and non-polarizable electrodes. The perfectly polarizable electrodes have no actual charge transfer between the electrode–electrolyte interface. Thus, such electrodes behave as capacitors and the current is due to the displacement current. On the other hand, the current passes freely across the electrode–electrolyte interface of the non-polarizable electrodes, thus these electrodes behave as a resistor. However, neither of the two types can be fabricated. Thus, practical electrodes are somewhere in between these two types. The equivalent circuit of an electrode can be described as shown in Fig. 2.2. CA and RA represents the impedance associated with the electrode–electrolyte interface, and RS is the resistance of the electrolyte solution. The half-cell potential of the interface is represented with a voltage source, Vhc .

8

Introduction to Biopotential Acquisition

Fig. 2.2 Equivalent circuit model of a biopotential electrode

In conventional electrodes, the electrolyte represents the gel that is used in between the tissue and the electrode. Since the biopotential signals are generally extracted differentially from two electrodes, there is always a mismatch between the half-cell potentials due to the difference in the gel–tissue interface (sweat glands and different epidermis effect the half-cell potentials of the electrodes [11]). Therefore, there appears a DC potential between the two electrodes, which is much larger than the µV level biopotential signals. This DC potential will be referred as differential DC electrode offset voltage in the rest of the text. Hence, the biopotential readout circuit should exhibit high-pass filter (HPF) characteristics to prevent the saturation of the readout circuit.

2.3.2 Types of Biopotential Electrodes Biopotential electrodes can also be classified as: wet, dry, and non-contact electrodes. Wet electrodes use a gel type electrolyte between the electrode and the surface of the skin. The most common type of a wet electrode is the Ag/AgCl electrode. Its characteristic approaches that of a perfectly non-polarizable electrode. The electrode metal is made up of Ag, which is coated with an AgCl layer. An electrolyte gel is used to establish the electrical contact between the electrode and the surface of the skin. The most important advantages of the Ag/AgCl electrodes are their low impedance and low artifact due to the motion of artifact. On the other hand, the use of the gel creates discomfort and increases the preparation time of the acquisition system. Dry electrodes, as their name imply, do not use any kind of gel to make contact between the electrode and the body. Thus, they are more comfortable and easy to prepare compared to the wet electrodes. However, due to the lack of the electrolyte, their characteristics are closer to a polarizable electrode, which can be characterized as a leaky capacitor. Therefore, the readout circuit for a dry electrode must have very high input impedance (1 G). Moreover, due to the very high impedance, the readout circuit must be placed very close to the electrode in order to prevent the electromagnetic interference. This can be achieved by using active electrodes [13]. However, the main disadvantage of the active electrodes is the necessity for matched components to achieve high CMRR, which is not straight forward in CMOS process. Alternatively, the characteristics of the dry electrodes can be improved by utilizing the advantages of MEMS processing technology to prevent the active electrode usage. Reference [14] proposes a dry electrode with micromachined spikes, where

2.4 Introduction to Biopotential Amplifiers

9

these spikes can penetrate through the stratum corneum of the skin, and bring the electrode directly in contact with the electrically conductive living epidermis. Test results shows that this dry electrode achieves 87 k at 0.6 Hz, and the arithmetic mean of the offset voltage between two electrodes is 11.8 mV, which is comparable to the performance of wet electrodes. Non-contact electrodes can be considered as a pure capacitor between the human body and the readout electronics, so they allow remote sensing of the biopotential signals [15]. They are intrinsically safe (no DC current drawn from the body) and biocompatible. However, the input impedance of the readout circuit must be extremely high for extracting the biopotential signals from non-contact electrodes. In addition, any motion of the electrode with respect to the body will create an artifact due to the change of capacitance. References [16] and [17] demonstrate ECG and EEG signals using non-contact electrodes.

2.4 Introduction to Biopotential Amplifiers The essential purpose of a biopotential amplifier is to amplify and filter the extremely weak biopotential signals. However, the design of this amplifier is not straight forward. Biopotential amplifiers must cope with various challenges in order to extract the biopotential signals. Meanwhile, the power dissipation of the amplifier must be minimized for long-term power autonomy. The challenges of designing a biopotential amplifier for portable biopotential acquisition systems can be summarized as follows: • • • • •

High CMRR to reject interference from mains. HPF characteristics for filtering differential DC electrode offset. Low-noise for high signal quality. Ultra-low power dissipation for long-term power autonomy. Configurable gain and filter characteristics that suit the needs of different biopotential signals and different applications.

Figure 2.1 shows the frequency characteristics of the correlating signals for the biopotential signals. The interference from the mains to the human body appears at the 50/60 Hz and at its harmonics. Thus, amplifier must have high CMRR in order to reject this common-mode signal. The differential DC electrode offset voltage, which is orders of magnitude larger than the biopotential signals, must be rejected to prevent the saturation of the amplifier. Therefore, the biopotential amplifier must have HPF characteristics. Meanwhile, the biopotential amplifier should minimize its power dissipation to improve the power autonomy. Subsection 2.4.1 will describe the theory of interference from the mains, and Sect. 2.4.2 will describe a parameter called NEF that can be used to compare the power-noise performance of the different amplifiers.

10

Introduction to Biopotential Acquisition

Fig. 2.3 Electrostatic interference to the human body

2.4.1 Interference Theory Biopotential acquisition systems are often disturbed by the interference from the mains. Two main types of interference are called the electromagnetic interference and the electrostatic interference. In the case of the electromagnetic interference, the magnetic field created by the alternating mains current cuts the loop enclosed by the human body, the leads of the circuit, and the biopotential amplifier. This induces an electromotive force (EMF), which creates an AC potential at the input of the circuit. The electromagnetic interference can be reduced by decreasing the area of the loop by twisting the cables [18]. Further reduction is possible by using miniaturized portable biomedical acquisition systems that can be placed much closer to the electrodes, which in turn reduces the cable length. Figure 2.3 shows the equivalent circuit for describing the electrostatic interference [10]. The human body is capacitively coupled to the mains via Cbp and also to the ground via Cbg . In addition to these two capacitances, there exists an isolation

2.4 Introduction to Biopotential Amplifiers

11

capacitance between the earth and the ground of the amplifier battery. As a result, the path through the coupling capacitors creates a displacement current, ID , passing through the human body and splitting equally between the Cbg and Ciso [19] (Cbg and Ciso have similar capacitance values and Rgnd is much smaller than the impedance of Ciso and Cbg at 50 Hz/60 Hz). Therefore, an AC voltage with magnitude:   ID Rgnd VCM = (2.2) 2 is created on the human body. Unless there is a mismatch between Rel1 and Rel2 , this voltage appears as a common-mode input to the amplifier, and can be rejected by the amplifiers high CMRR. However, there is always a mismatch between the electrode impedances, due to this mismatch, a differential error signal is created with amplitude:   |Rel1 − Rel2 | VIN = VCM (2.3) Zin where Zin stands for the input impedance of the amplifier [18]. As a conclusion, a high CMRR alone is not sufficient for an IA to completely reject the electrostatic interference. In addition, it should implement very high input impedance.

2.4.2 Noise-Efficiency Factor (NEF) of Biopotential Amplifiers Due to the small frequency bandwidth of the biopotential signals, it is the target noise level that defines the power dissipation of the biopotential amplifiers. As the type and the number of noise sources increase, the total noise of the amplifier also increases. Therefore, the amplifier requires more power to achieve the target noise level. The term called noise-efficiency factor (NEF) is first introduced by [20] in order to compare the power–noise performance of different amplifiers and can be expressed as:  2Itot NEF = Vin,rms (2.4) πVt 4kT BW where BW is the −3 dB bandwidth of the amplifier and Vin,rms is the total input referred voltage noise of the amplifier. The NEF of a single bipolar transistor having only thermal noise is 1, which is the theoretical limit for any practical circuit. NEF can be used to compare the power–noise performance of different amplifiers. The amplifier with lower NEF can achieve lower power dissipation for a given noise level.

12

Introduction to Biopotential Acquisition

Fig. 2.4 Simplified schematic of a current balancing IA

2.4.3 State-of-the-Art in Instrumentation Amplifier Design The IA is the most critical building block of the analog readout front-end in terms of the signal quality and clarity. It defines the noise level and the CMRR of the readout front-end, and filters the differential DC electrode offset. Hence, it is generally the most power consuming building block of an analog readout front-end. Therefore, the design effort focuses on implementing a low-power and low-noise IA. The most common and well-known IA architecture is called the three-opamp architecture [21–25]. However, it is very-well known that the CMRR of the threeopamp IA is highly dependent on the matching of the resistors [26]. This matching requires laser trimming in standard CMOS technology that increases the cost. In addition to that, the necessity for low output impedance opamps for driving the feedback resistors, results in excessive power dissipation. A second technique for implementing IAs uses switched-capacitor (SC) architectures [27, 28]. Although SC amplifiers are capable of eliminating the 1/f noise of the CMOS transistors, they suffer from the noise fold-over above Nyquist frequency (half of the sampling frequency) [29]. In order to compensate this increase in noise, the power dissipation of the SC amplifiers has to be increased. Therefore, SC architectures are not efficient for low-power and low-noise IAs. Another IA topology is called Current Balancing (Current Feedback) IA (CBIA) [20, 30–33]. Figure 2.4 shows the simplified block diagram of a CBIA. The input stage acts as a transconductance amplifier. The current passing through Rin is copied to the transresistance stage, and the voltage created on Rout is buffered to the output. Therefore, the voltage gain of the CBIA can be written as: (Vout+ − Vout− ) =

Rout (Vin+ − Vin− ) Rin

(2.5)

where the ratio of the two resistors defines the voltage gain of the CBIAs. Thus, the CBIA topology eliminates not only the need for matched resistors for achieving high CMRR but also the need for low output impedance amplifiers. Therefore, the CBIA topology is convenient for implementing low-power and low-noise IAs. Table 2.1 summarizes the properties of three-opamp, switched-capacitor, and CBIA architectures for biopotential readout applications. On the other hand, 1/f noise of the CMOS transistors limits the power reduction and process induced transistor mismatches degrades the CMRR of the CBIA.

2.5 Introduction to Chopper Modulation Technique

13

Table 2.1 Comparison of the three-opamp, switched-capacitor, and CBIA architectures for biopotential readout applications

Low Power Dissipation Free of Noise Fold-Over High Input Impedance

Three-Opamp IA

SC IA

x √

x

√

x x

CBIA √ √ √ √

CMRR Independent from Matching of Passives

x

x

CMRR Independent from Matching of Transistors

x

x

x

Negligible 1/f Noise in the Signal Bandwidth

x

x

x

The chopper modulation technique [29] can be used both for increasing the CMRR of the amplifiers and for eliminating the 1/f noise of the CMOS transistors (See Sect. 2.5 for further description of the chopper modulation technique). However, the main disadvantage of the chopper modulated amplifiers is the inherent DC coupling. Thus, they also amplify the differential DC electrode offset voltage between the biopotential electrodes. References [34–36] addresses the AC coupling issue in IAs using the chopper modulation technique. Reference [34] uses off-chip HPFs for filtering the electrode offset voltage. However, this technique not only results in large number of off-chip components for multi-channel biopotential readout frontends, but also implements a very low input-impedance amplifier and degrades the signal-to-noise ratio of the IA. Reference [35] uses a differential difference amplifier for introducing HPF characteristics to a chopper modulated IA. However, this technique consumes excessive power due to the resistive feedback topology. Finally, Ref. [36] implements a low-power chopper stabilized IA with monolithic HPF. Although, the circuit achieves 105 dB CMRR and eliminates majority of the 1/f noise, the input impedance of the amplifier is very low (7.5 M) especially for EEG acquisition systems, where a minimum of 100 M is required [37].

2.5 Introduction to Chopper Modulation Technique The operation principle of the chopper modulation technique is described in Fig. 2.5 [38]. The low frequency input signal (the bandwidth of the signal must be smaller than fchop /2 to prevent aliasing) is modulated with the square wave modulation signal, m(t). This shifts the frequency spectrum of the input signal, X(s), to the odd harmonics of fchop . Then, the modulated input signal is amplified by the amplifier with transfer function A(f ), and demodulated with m(t). This shifts the modulated spectrum back to its original location, leaving replicas at the odd harmonics of fchop . These replicas can be filtered by a LPF.

14

Introduction to Biopotential Acquisition

Fig. 2.5 Operation principle of chopper modulation technique. Input signal is modulated by m(t), amplified by A(f ), and demodulated by m(t)

Subsections 2.5.1 and 2.5.2 will present the necessary formulas for understanding the operation of the chopper modulation technique. More detailed analysis of the chopper modulated amplifiers can be found in [29, 39–41].

2.5.1 Noise Analysis of Chopper Modulation Technique Figure 2.5 describes the principle of how the chopper modulation technique eliminates the 1/f noise of the MOS transistors. The output noise and the offset of the core amplifier are indicated by vn and voff , which are only modulated by the output modulator. Therefore, the input referred noise of a chopper modulated amplifier is equivalent to vn , multiplied with a square wave with frequency fchop , when referred to the input of the chopper modulated amplifier. Hence, the double-sided inputreferred voltage noise power spectral density (PSD), Sin (f ), of the amplifier can be written as:  2  ∞ 1 2 Svn (f − nfchop ) (2.6) Sin (f ) = π n2 n=−∞,odd

2.5 Introduction to Chopper Modulation Technique

15

This equation should be handled separately for the thermal noise and the 1/f noise. Considering first the thermal noise component, (2.6) can be approximated as (2.7), if the fc of the amplifier is much larger than fchop [29]. This equation is only valid for the region where |f | < 0.5fchop . Further approximation reduces (2.7) to (2.8) considering that fc  fchop : fc   tanh( π2 fchop ) 1 − S (f = 0) = S Sin,thermal (f ) ∼ = in,thermal 0 f π 2

Sin,thermal ∼ = S0

c fchop

   ≤ 0.5 and fc  1  fchop chop

  f for  f

(2.7)

(2.8)

As a result, the thermal noise of the chopper modulated amplifiers is not affected from the chopping operation as long as fc of the amplifier is much larger than fchop , which is due to the fact that the chopping operation only periodically changes the sign of the thermal noise. On the other hand, considering that the 1/f noise of an amplifier is in the form of (2.9), the PSD of the input referred 1/f noise can be approximated by inserting (2.9) to (2.6), which can be expressed as (2.10) and indicates that the input referred 1/f noise of chopper modulated amplifiers can be approximated by a white noise component in the baseband [29]. S1/f (f ) = S0

fc,1/f |f |

fc,1/f Sin,1/f (f ) ∼ = 0.8525S0 fchop

(2.9)

(2.10)

As a result, the total input referred noise of the amplifier in the baseband can be calculated by combining (2.8) and (2.10) as:      f  fc,1/f ∼   ≤ 0.5 and fc  1 (2.11) for  Sin,total (f ) = S0 1 + 0.8525 fchop fchop  fchop As a conclusion, the chopper modulation technique can effectively eliminate the 1/f noise of the MOS transistors without affecting the thermal noise, if fchop can be selected to be much higher than fc,1/f .

2.5.2 Charge Injection and Residual Offset of Chopper Modulated Amplifiers Theoretically chopping amplifiers can achieve zero input referred offset voltage, since the offset of the core amplifier is modulated by the output chopper and can

16

Introduction to Biopotential Acquisition

Fig. 2.6 Input modulator schematic of a chopper amplifier describing the charge injection from the nMOS switches to the input of the amplifier

be filtered. However, due to the non-ideality of the chopper switches, a residual offset remains. Figure 2.6 shows the schematic of a chopper modulator implemented with nMOS switches. Switches M1 , M2 and M3 , M4 are periodically toggled by the modulator signals m(t) and m(t), respectively. During the switching of the nMOS transistors a certain amount of charge is injected to the source and drain of the MOS switch [42]. Although, in an ideal situation the charge injection of the transistors M1 and M2 are equal and appears as common-mode at the input of the amplifier, there is always a small mismatch, q1 , which is injected to the input capacitance of the amplifier, Cin . Similarly, the mismatch between M3 and M4 results in an equivalent charge injection of q2 . As a result, the total equivalent charge that is injected to the input of the amplifier can be written as: q = |q1 − q2 |

(2.12)

which results in an equivalent differential input voltage of: Vinj =

q Cin

(2.13)

at the input of the amplifier with time constant: τinj = Rs Cin

(2.14)

as illustrated in Fig. 2.6. The input voltage, Vinj is amplified by the amplifier and then demodulated by the output chopper demodulator, creating an error output voltage, which has an average DC level of Voff . Assuming an amplifier with infinitely large bandwidth. The total input referred offset of the amplifier can be written as [40]: Voff = 2τ · fchop · Vinj

(2.15)

2.5 Introduction to Chopper Modulation Technique

17

As a conclusion, the offset of the chopper modulated amplifiers depend on the source resistance and the amount of the charge injection to the input. On the other hand, it is independent of the input capacitance of the amplifier. Assuming that the source resistance is defined by the sensor, where the readout is connected to, the offset of the chopped amplifiers can be decreased by reducing the sizes of the chopper switches or decreasing the chopping frequency. More detailed analysis about the offset in chopper amplifiers can be found in [39–41]. Several techniques have been proposed in the literature for reducing the inherent DC offset problem of the chopper modulated amplifiers. Reference [38] uses a bandpass filter between the input and the output choppers. However, matching of the bandpass filter center frequency with the chopping frequency limits the efficiency of this technique. Reference [43] uses nested choppers, where in addition to the input and output modulators, another pair of slow chopping modulators are used to modulate the output spikes of the fast modulator. Although, this technique can be very efficient for slow signals, biopotential signals have too large bandwidth for this solution (1 kHz bandwidth is necessary for EMG signals). Another technique is proposed by [44]. It uses a SC notch filter with synchronous integration after the output modulator to filter both the chopping ripple and the modulated amplifier offset, however results in excess quiescent current and complexity in the signal path.

2.5.3 Signal Distortion in Chopper Modulated Amplifiers Signal distortion problem appears in chopper amplifiers due to the finite bandwidth of the core amplifier. Figure 2.7 describes the signal distortion in chopper modulated amplifiers. The differential input signal is modulated with the square wave modulation signal. However, due to the finite bandwidth of the core amplifier, high frequency components of the square wave is filtered by the core amplifier. When

Fig. 2.7 Signal distortion problem in a chopper modulated amplifier due to the finite bandwidth of the core amplifier

18

Introduction to Biopotential Acquisition

this signal is demodulated by the output chopper, signal distortion in the shape of spikes appears at the output with the time constant: τ=

1 2πfc

(2.16)

The main consequence of these spikes is the reduction in the gain of the chopper modulated amplifier, which can be derived by considering a DC input voltage and calculating the average value of the output voltage for half the period of the chopping signal:   4τ Achopped (f ) = A(f ) 1 − (2.17) T It should be noted that the techniques presented in the Sect. 2.5.2 are also effective for reducing the signal distortion in chopper modulated amplifiers.

2.5.4 CMRR of the Chopper Modulated Amplifiers Basically, there are two different mechanisms that define the CMRR of the conventional amplifiers: Systemic common-mode gain, which is due to the topology of the IA and mismatch induced common-mode gain, which is due to the process induced mismatches. Both of these CMRR reduction mechanisms can be eliminated by the chopper modulation technique. The chopper structure shown in Fig. 2.6 is transparent to common-mode signals. Therefore, the input common-mode signal passes through the input chopper without being modulated and appears as a common-mode input to the core amplifier. The common-mode gain of the core amplifier converts the common-mode input into differential output. However, this differential output voltage, which is due to the non-zero common-mode gain of the amplifier, is modulated by the output modulator. Thus, it can be eliminated in a similar way the 1/f noise and the offset of the IA are filtered.

2.6 Conclusions Biopotential readout circuits suffer from various problems for extracting biopotential signals. The extremely weak amplitudes of the biopotential signals make them susceptible to various correlating signals. Table 2.2 summarizes the requirements of a configurable readout front-end for biopotential acquisition systems. The first problem is the 1/f noise of the CMOS transistors that dominates the noise of the readout circuit in the frequency band of the biopotential signals. Moreover, there is the interference from the mains, thus the readout circuit must achieve high CMRR to reject the large common-mode signals, while amplifying the biopotential signals. Both the interference and the 1/f noise problem can be solved by

2.6 Conclusions

19

Table 2.2 Requirements of a configurable readout front-end for biopotential acquisition systems Problem Solution Technique 1/f Noise

1/f noise Filtering

Chopper Modulation

Common-Mode Interference

High CMRR

Chopper Modulation

Differential DC Electrode Offset

HPF Characteristics

?

Configurability for Different Biopotential Signals

Variable Gain

SC Resistive ?

Long Term Power Autonomy

Variable Bandwidth

?

Low-Power Design

?

using the chopper modulation technique. However, there is the problem of the differential DC offset between the electrodes. This DC voltage is orders of magnitude larger than the biopotential signals and can saturate the IA. Thus, the IA must have HPF characteristics for filtering the differential DC electrode offset voltage. Unfortunately, the chopper amplifiers are inherently DC coupled. Therefore, there is a need for a chopper modulated IA with HPF characteristics, so that the 1/f noise, the interference, and the differential DC offset problems can be solved and high quality biopotential signals can be extracted. In addition, configurable characteristics for different biopotential signals and ultra low power dissipation for long term power autonomy is a must for portable biopotential acquisition systems.

Chapter 3

24-Channel EEG Readout Front-End ASIC

3.1 Introduction The existing multi-channel EEG acquisition systems make use of off-the-shelf components for the implementation of the analog readout front-end. This not only consumes an excessive amount of power but also increases the size of the system that limits the autonomy of the patient. Therefore, there is a need for a multi-channel ASIC that is tailored towards the low-power and the small size needs of the biopotential acquisition systems. This Chapter describes a 24-channel EEG readout front-end ASIC that can circumvent the above mentioned problems of size and power for the EEG acquisition systems with large number of channels. It is capable of extracting biopotential signals from conventional Ag/AgCl biopotential electrodes. Section 3.2 describes the architecture of the 24-channel EEG readout front-end ASIC. Each channel of the ASIC uses a CBIA architecture that is described in Sect. 3.3 to filter the out of band signals and to reject the common-mode interference. Furthermore, Sect. 3.4 introduces a new CMRR reduction mechanism called electrode offset induced commonmode gain and demonstrates that this reduction mechanism is dominant for the IAs that are being used under large differential DC offset voltage between the biopotential electrodes. Later, Sect. 3.5 describes the gain stage of the channels that is for the further amplification of the output of the CBIA. Section 3.6 presents the test results of the ASIC, and Sect. 3.7 states the conclusions of this Chapter.

3.2 ASIC Architecture Figure 3.1 shows the simplified schematic of the 24-channel EEG readout front-end ASIC. It consists of 24 EEG readout channels and a single ECG readout channel that are multiplexed at the back-end and buffered to the output. The 24 EEG channels share a common reference input that is compatible with the applications using 10– 20 electrode placement systems [12]. On the other hand, the single ECG channel has a separate reference input so that ECG signals can be extracted independently from the EEG signals. Each channel consists of an IA and two cascaded gain stages. The front-end IA amplifies the biopotential signals and performs the differential-to-single ended conversion, while rejecting the common-mode signals. Then, two SC amplifiers further amplify the signal. The gain of the IA is 10 and the gain of the SC gain stage can be selected between 20 and 1000. This results in a programmable channel gain between 200 and 10000 that can be digitally configured by digitally selecting the gain R.F. Yazıcıo˘glu et al., Biopotential Readout Circuits for Portable Acquisition Systems, © Springer Science + Business Media B.V. 2009

21

22

24-Channel EEG Readout Front-End ASIC

Fig. 3.1 Architecture of the 24-channel EEG readout front-end ASIC

capacitors in the SC gain stage. On the other hand, the gain of the IA and the first amplification stage are 5 and 4 for the ECG channel, respectively, which translates into configurable gain between 20 and 1000. The IA of each channel uses off-chip passive components indicated by gray color in Fig. 3.1. These external components are used for setting the gain and the cut-off frequencies of the IA.

3.3 Current Balancing IA 3.3.1 Implementation Each channel of the 24-channel EEG readout front-end circuit uses the CBIA architecture as a preamplifier. Figure 3.2 shows the schematic of the CBIA architecture that consists of a transconductance stage and a transresistance stage [33]. The first stage is a transconductance amplifier, where the input voltage is converted into a current. Under steady state, this current equals the differential input voltage divided by R1 , which is mirrored to the transresistance stage and converted into voltage on the resistor R2 . Therefore, the gain of the IA can be defined as: Gain =

R2 R1

(3.1)

3.3 Current Balancing IA

23

Fig. 3.2 Schematic of the CBIA of each channel of the 24-channel EEG readout front-end ASIC. Off-chip components are indicated with gray color Table 3.1 Operating points of the transistors in Fig. 3.2 Transistors

W/L (µm/µm)

Ids (µA)

gm /Ids (1/V)

M1 , M2

800/20

12

12

M3 , M4

100/10

6

9.2

M5 , M6

300/200

12

5.1

M7 , M8

100/200

6

4.2

M9

14/20

2

8.5

M10

84/20

12

8.5

M11 , M12

300/3

6

21

Passives R1

10 k

Cc

50 pF

The bandwidth characteristics of the IA is set by R2 -CLPF and OTA1 -CHPF . The R2 -CLPF pair sets the LPF cut-off frequency of the IA as described in (3.2), and the HPF cut-off frequency is set by the OTA1 -CHPF according to (3.3). Therefore, the gain, the LPF cut-off frequency, and the HPF cut-off frequency can be precisely defined with three external passives. Table 3.1 shows the dimensions and the operating points of the implemented IA. fIA,LPF =

1 2πR2 CLPF

(3.2)

gm,OTA1 2πCHPF

(3.3)

fIA,HPF =

24

24-Channel EEG Readout Front-End ASIC

Fig. 3.3 Schematic of the OTA1 of Fig. 3.2

The resistor R1 is selected as 10 k and implemented using hipo resistors. If R2 is selected as 200 k the gain is set to 10. The LPF cut-off frequency of the IA can be set to 80 Hz by selecting CLPF as 10 nF. The size of the CHPF is defined by the transconductance of OTA1 . In order to reduce the size of the external capacitor, the transconductance of OTA1 must be as small as possible, which can be reduced using the series-parallel division of current as proposed in [45, 46]. Figure 3.3 shows the schematic of the OTA1 implementation. The equivalent transconductance of the architecture is 3.2 µS. Therefore, selecting CHPF as 1 µF sets the HPF cut-off frequency of the IA to 0.5 Hz. Different from the architecture of [33], the current mirrors I1 and I2 are implemented using the active current mirror architecture, shown in Fig. 3.4 [47], which increases their output resistance compared to a conventional cascode current mirror. This is necessary for the CMRR of the IA to be resistant to the increasing DC differential offset of the biopotential electrodes (This will be further described in Sect. 3.4). The output resistance of the active current mirror can be expressed as: Rout,Mirror = Av gm,MB1 Rds,MB1 Rds,MA1

(3.4)

which indicates that the active current mirror multiplies the output impedance of a conventional cascode current mirror by the open-loop gain of the opamp, Av .

3.3.2 Measurement of Performance The presented CBIA, see Fig. 3.2, is implemented in a 0.5 µm 3-metal double-poly CMOS process through AMIS and consumes 110 µA from a single 3 V supply. The implemented CBIA is capable of filtering ±50 mV differential DC electrode offset before the input transconductance stage saturates. Figure 3.5 shows the gain-

3.4 CMRR Model for Biopotential Instrumentation Amplifiers

25

Fig. 3.4 Current mirror architecture of I1 and I2 of Fig. 3.2

Fig. 3.5 Gain-bandwidth measurement of the CBIA

bandwidth plot of the IA without using the CLPF capacitor that sets the LPF cut-off frequency. The in-band gain of the IA is 10.5, and the HPF cut-off frequency appears at 0.5 Hz. Figure 3.6 shows the input referred voltage noise PSD of the IA. The total input referred voltage noise of the IA can be calculated as 0.64 µVrms between 0.5 Hz and 100 Hz.

3.4 CMRR Model for Biopotential Instrumentation Amplifiers The interference from the mains to the human body appears a common-mode signal at the input of the IA (see Sect. 2.4.1). Hence, the biopotential signals are correlated by the common-mode interference. The CMRR of the IA defines how good the IA rejects this common-mode interference and amplifies the biopotential signals. Basically, two different mechanisms define the CMRR of the conventional amplifiers: Systematic common-mode gain, which is due to the topology of the IA and

26

24-Channel EEG Readout Front-End ASIC

Fig. 3.6 Measured input referred voltage noise PSD of the CBIA

mismatch induced common-mode gain, which is due to the process induced mismatches. Unlike the conventional IAs, the IAs that are connected to the biopotential electrodes suffer from another type of common-mode gain mechanism called electrode offset induced common-mode gain. The differential electrode offset voltage at the input of the IA introduces operating point mismatches to the transistors of the IA. Unlike the other two mechanisms, the chopper modulation technique can not eliminate the electrode offset induced common-mode gain. This is due to the fact that the differential DC offset between the biopotential electrodes is also modulated by the input chopper. Therefore, any error signal at the output of the core amplifier appears to be modulated. Hence, it is demodulated to the baseband by the output chopper. Therefore, an IA for biopotential applications must preserve its CMRR under high differential DC offset voltages. The following subsection will describe a model for calculating the amount of CMRR reduction with changing electrode offset voltage. Although the model will be derived for a specific type of IA (a CBIA), its conclusions can be generalized for all types of IAs.

3.4.1 Systematic CMRR The systematic CMRR, CMRRsys , of an IA depends on the architecture. Unless the IA architecture is fully-differential, CMRRsys is finite. Figure 3.7(a) shows the simplified schematic of the CBIA of [33] and Fig. 3.7(b) shows the low-frequency small signal model of the same IA1 . Assuming that the symmetric transistors are 1 The small signal model is given for the flipped version of the circuit of Fig. 3.7(a), i.e., nMOS and pMOS transistors are interchanged.

3.4 CMRR Model for Biopotential Instrumentation Amplifiers

27

(a)

(b) Fig. 3.7 (a) Simplified schematic of the CBIA, (b) low-frequency small-signal circuit of the CBIA

perfectly matched, the common-mode gain of the transconductance stage can be written as:

ACM =

I1 I2 gds,M5 go (2g1 + gm,M1 ) =− = vin vin 2gm,M1 gm,M5

(3.5)

where g1 = 1/R1 . Similarly, the differential gain of the transresistance stage can be written as: 1 vout = (I2 − I1 ) 2g2

(3.6)

28

24-Channel EEG Readout Front-End ASIC

where g2 = 1/R2 . Thus, CMRRsys of the CBIA of Fig. 3.7(a) can be expressed as: CMRRsys =

ADM 2g1 gm,M1 gm,M5 = ACM gds,M5 go (2g1 + gm,M1 )

(3.7)

Equation (3.7) indicates that CMRRsys of the IA can be increased by maximizing g1 and gm,M1 . Therefore, the input pair transistors should be operated in weak inversion for maximizing their transconductance [48]. Additionally, the output resistances of the current sources I1 and I2 can be increased in order to boost the CMRR, which is demonstrated by [49].

3.4.2 CMRR Limit due to Differential DC Electrode Offset Even though the transistors of a circuit are perfectly matching, the differential DC electrode offset voltage introduces operating point mismatches to the IA, which reduces its CMRR. These operating point mismatches can be divided into two. The first one is due to the mismatch of the drain-to-source voltages of the input pair transistors and the second one is due to the mismatch of the output transconductances of the current sources I1 and I2 . The effect of the drain-to-source voltage mismatch of the input pair transistors on the CMRR of the IA can be described as follows: The differential input voltage to the IA is copied to the terminals of R1 . If we assume that the gmi has infinite transconductance, the drain to source voltage of the input pair transistors will differ by the amount of the differential input voltage. Hence, there will be a gds mismatch between the input pair transistors. Figure 3.7(b) shows the introduced mismatch gds to the input pair transistors. Therefore, CMRR limit of the circuit due to the output transconductance mismatch of the input pair transistors can be written as: CMRRgds (vin ) =

gm gds (vin )

(3.8)

On the other hand, the effect of the output transconductance mismatch of the current sources can be described as follows: The differential DC input will create a DC current through R1 . This disturbs the matching of the quiescent current of the input pair transistors. However, the gmi stage compensates this mismatch by adjusting its output currents. Therefore, the differential DC input voltage does not disturb the DC quiescent current of the input pair transistors, but it affects the DC operating points of the transistors of I1 and I2 by changing the quiescent current. Figure 3.7(b) shows the added parameter, go , in order to represent the output transconductance mismatch of the current source I1 and I2 . Calculation of the CMRR considering this parameter results in: CMRRgo (vin ) =

2g1 go (vin )

(3.9)

3.4 CMRR Model for Biopotential Instrumentation Amplifiers

29

After separately describing the three limitations for maximum achievable CMRR, the equivalent CMRR, CMRReq can be written as the superposition of the CMRRsys , CMRRgds , and CMRRgo as: 1 1 1 1 = + + CMRReq CMRRsys CMRRgds CMRRgo

(3.10)

assuming that the CMRR limiting factors are uncorrelated.

3.4.3 Verification of the CMRR Model In order to verify the presented CMRR model, the CBIA implementation of Sect. 3.3 is used. The main difference between the implemented IA and the IA of Fig. 3.7(a) is the structure of the current mirrors I1 and I2 . Instead of using the conventional current mirrors, the active current mirror structure shown in Fig. 3.4 is used. This structure boosts up the output impedance of the current mirrors, as shown in (3.11), compared to a normal current mirror. Thus, the CMRRgo limit is increased by a factor of (Av gm,Mc1 /gds,Mc1 ). go,active =

gds,M1 gds,Mc1 1 gm,Mc1 Av

(3.11)

Figure 3.8 shows the comparison of the simulated, the calculated, and the measured CMRR of the implemented IA at 50 Hz with changing differential DC input voltage, which represents the differential DC offset voltage of the biopotential electrodes. CMRRgds and CMRRgo of (3.10) are also shown in the same figure to

Fig. 3.8 Comparison of the calculated, the simulated, and the measured CMRR of the implemented CBIA

30

24-Channel EEG Readout Front-End ASIC

demonstrate their contribution to CMRReq . Under low differential DC input voltage, CMRReq is defined by the process related mismatches of the circuit. However, as the differential DC input increases, which is the operating region of a biopotential IA, CMRReq is reduced due to the reduction in CMRRgds . The simulated, calculated, and measured CMRR fits well in the large differential DC input voltage regions. Use of the active current mirrors increases CMRRgo , leaving CMRRgds as the dominant mechanism defining the CMRReq of the IA. The simulations and calculations show that if the active current mirror structure is replaced with a conventional current mirror, the CMRReq of the IA will be reduced down to 75 dB at 50 mV differential DC input voltage, which is purely due to CMRRgo .

3.5 Programmable Gain Stage 3.5.1 Finite-Gain Compensated SC Amplifier The programmable gain stage of each channel of the 24-channel EEG ASIC uses a SC amplifier architecture. Conventional SC amplifiers rely on high open-loop gain OTAs. These amplifiers can be implemented using cascaded or cascode architectures. However, the cascode implementations reduce the amplifier output voltage swing and the cascade architectures increase power dissipation. These two problems can be circumvented by using finite-gain compensated SC amplifiers as shown in Fig. 3.9 and described in [29]. The operation of the amplifier can be divided into two phases. φa is the amplification phase. During φa , C1 discharges into C2 and the output is created, which

Fig. 3.9 Schematic of the finite-gain compensated SC amplifier

3.5 Programmable Gain Stage

31

Fig. 3.10 Equivalent circuits of the SC amplifier in amplification (phase A) and sampling (phase B) phases

is stored by C3 . φb is the sampling phase. The voltage difference between the input and the negative input of the OTA is stored by C1 . Also, in this mode, C3 acts as a feedback capacitor and keeps the output voltage of the amplifier close to the value stored during the amplification phase. Therefore, due to the fact that the output of the amplifier is not reset, the slew-rate considerations of the OTA is relaxed. 3.5.1.1 Precision and Offset of the SC Amplifier The main drawback of the SC amplifiers is their dependency on the open-loop gain of the OTA. The transfer function of the finite-gain compensated SC amplifier can be extracted by dividing the operation of the circuit into two phases, phase A and phase B. Using the equivalent circuit models shown in Fig. 3.10, and assuming that the sampling frequency is high enough so that the input voltage can be assumed to be constant between two samples [50], the following equations can be written:    3  vB C1 3 out (n − 2 ) − vB n − + C1 + C2 in 2 Av,OTA  3  vB vA (n − 1) C2 out (n − 2 ) A vout (n − 1)− = − out (3.12) + C1 + C2 Av,OTA Av,OTA   1 vB 1 vA out (n − 2 ) out (n − 1) A n − = v vB (n − 1) − = out out 1 2 Av,OTA (1 + Av,OTA )

(3.13)

    1 3 B n − n − ≈ v vB out out 2 2

(3.14)

32

24-Channel EEG Readout Front-End ASIC

Fig. 3.11 Small signal equivalent circuit of the amplification and the sampling phases of the SC amplifier

Using (3.12), (3.13), and (3.14), the transfer function of the SC amplifier can be given as in (3.15), which shows that the gain error of the finite-gain compensated SC amplifier is scaled by A2v,OTA instead of Av,OTA as in a conventional amplifier. As a result, the necessity for high open-loop gain is eliminated by the using the finite-gain compensated SC amplifier architecture. Similar to the gain analysis the output offset voltage of the SC amplifier can be calculated as in (3.16).   3 C1 /C2 a b vout (n − 1) = (3.15) v n− 1 C2 ) in 2 1 + (1+C 2 Av,OTA

vout,offset =

(1 + C1 C2 ) vOTA,offset Av,OTA

(3.16)

3.5.1.2 Speed of the SC Amplifier Figure 3.11 shows the small signal equivalent circuits of the finite-gain compensated SC amplifier for the amplification and the sampling phases. The time constant of the output voltage of each phase can be calculated from the small signal equivalent circuits and can be expressed as given in (3.17) and (3.18), where Ceq,amp = C1 + Cin , Ceq,samp = C1 + C2 + Cin , and CL,eq = C3 + CL .   CL,eq Ceq,amp 1 τamp = (3.17) + CL,eq + Ceq gm,OTA C2 τsamp =

1 gm,OTA



CL Ceq,samp + CL + Ceq C3

 (3.18)

3.5.2 Programmable Gain Stage Implementation Figure 3.12 shows the architecture of the programmable gain stage. It consists of two finite-gain compensated SC amplifiers operating in complementary clock phases.

3.5 Programmable Gain Stage

33

Fig. 3.12 Programmable gain stage architecture of the 24-channel EEG readout front-end Fig. 3.13 OTA structure of the finite-gain compensated SC amplifier stages

The first stage is implemented with a fixed gain of 20 for the EEG channels. The C2 capacitor of the second gain stage is digitally selectable that allows gain selection between 1 and 50 with 8 different settings. Therefore, the total gain of the channel can be selected between 200 and 10000. The OTA of the SC amplifier are implemented using the current mirror architecture shown in Fig. 3.13. The input pair transistors operate in weak inversion in order to maximize their transconductance and reduce the time constant of the amplification and sampling phases. The transconductance of the OTA is 21.5 µS, hence, the worst case time constant of the SC amplifier appears as 20 µs for the second SC am-

34

24-Channel EEG Readout Front-End ASIC

plifier stage with the gain setting of 50. The amplification time of the SC amplifier stages is selected as 140 µs, equivalent to 7τamp . Therefore, the operating frequency of the amplifiers is 3.125 kHz.

3.6 Test Results The presented 24-channel EEG readout front-end ASIC is implemented in 0.5 µm double-poly triple-metal CMOS process. Figure 3.14 shows the photo of the ASICs on 6-inch wafer. The total area of the ASIC measures 7.5 mm by 8.2 mm. In order to verify the operation of the 24-channel EEG readout front-end ASIC, a test setup has been prepared. Two Ag/AgCl cup electrodes are placed on the skull of a subject at the locations O1 and O2 (occipital cortex) in accordance with [12], Fig. 3.15. These electrode are connected to the inputs of the two channels of the 24-

Fig. 3.14 Photo of several 24-channel EEG readout front-end ASICs on 6-inch wafer. ASIC is implemented in 0.5 µm three-metal double-poly CMOS process through AMIS

Fig. 3.15 Extracted EEG signals and their STFT from the two electrodes connected to the occipital cortex of a subject (locations of the electrodes are indicated on the left)

3.6 Test Results 35

36

24-Channel EEG Readout Front-End ASIC

Table 3.2 Performance summary of the 24-channel EEG readout front-end ASIC Performance Summary Voltage Supply

3V

Current Consumption (24 EEG + ECG Channels)

3.42 mA

Number of Channels (EEG/ECG)

24/1

Input Clock Frequency

32 kHz

Input Common-Mode Range

0.5 V–1.8 V

Output Voltage Swing

0.3 V–2.0 V

Programmable Channel Gain Range (EEG)

200–10000

Programmable Channel Gain Range (ECG)

20–1000

CMRR (with 0 mV Differential Electrode Offset)

107 dB

CMRR (with 50 mV Differential Electrode Offset)

90 dB

Input Ref. Voltage Noise of IA (0.5 Hz–100 Hz)

0.64 µVrms

Input Ref. Voltage Noise of EEG Chn. (0.5 Hz–100 Hz)

<1.3 µVrms

HPF Cut-Off Frequency (CHPF = 1 µF)

0.5 Hz

LPF Cut-Off Frequency (CLPF = 10 nF, R = 200 k)

78.8 Hz

Maximum Capacitive Output Load

50 pF

channel EEG readout front-end ASIC. The common reference input of the ASIC is connected to the electrode REF, located on the top of the subject’s skull and aligned with the longitudinal fissure of the brain. A separate electrode is used to set the DC level of the patient in the common-mode input range of the ASIC. Output of the ASIC is digitized by a 12-bit off-chip ADC converter. Figure 3.15 shows the extracted signals and their short-time Fourier transform (STFT). After the patient closes his eyes the dominant frequency appears in the alpha range (8–13 Hz) [11] demonstrating the proper operation of the ASIC. Table 3.2 summarizes the specifications of the ASIC.

3.7 Conclusions This Chapter demonstrates the first multi-channel EEG readout front-end circuit that is capable of extraction EEG signals from conventional Ag/AgCl biopotential electrodes. The CMRR model derived for the biopotential IAs describes a new CMRR reduction mechanism. This reduction mechanism is due to the operating point mismatches of the IA transistors created by the differential DC offset voltage between the biopotential electrodes. Based on this model the CMRR of an IA has been improved such that it is more resistant to the increasing electrode offset voltage. This IA is used as a preamplifier in each channel of the 24-channel EEG readout front-end ASIC for extracting high-quality biopotential signals. The test results prove that the implemented ASIC is indeed convenient for multi-channel biopotential acquisition systems.

3.7 Conclusions

37

Although the large number of external passive circuits and the comparatively large current consumption of the ASIC is a disadvantage in terms of system size and power autonomy, the presented ASIC is still an important improvement compared to the systems implemented with off-the-shelf components.

Chapter 4

Biopotential Readout Front-End ASICs

4.1 Introduction The readout front-end ASIC of Chap. 3 requires a large number of off-chip components and has a relatively large current consumption. Although, its usage can considerably improve the size of the existing biopotential acquisition systems, the relatively large current consumption still limits the power autonomy of the system. Therefore, further improvement is possible if the number of external components and the power dissipation can be reduced. This Chapter presents a single-channel ExG ASIC and an eight-channel EEG readout front-end ASIC. The main focus is to minimize the power dissipation of the building blocks of the ASICs, while maximizing the performance such as higher CMRR and reduced 1/f noise. Except for the number of channels the building blocks of the two ASICs of this Chapter are similar, where each channel consists of an AC coupled chopped IA (ACCIA), a chopping spike filter (CSF), and a programmable gain stage (PGS). The single-channel ExG ASIC can be used for EEG, ECG, and EMG acquisition applications and the eight-channel EEG ASIC is dedicated to EEG acquisition applications. The first three Sections of this Chapter describe the building blocks of the readout channels of the ASICs. Section 4.2 proposes an IA architecture called the ACCIA that implements HPF characteristics to a chopper modulated IA. Thus, it is capable of filtering the differential DC electrode offset between the biopotential electrodes, and achieving low-noise and high-CMRR. Section 4.3 introduces the CSF stage that can filter the spikes appearing at the output of the ACCIA due not only to the charge injection from the input chopper switches but also to the finite bandwidth of the core IA of the ACCIA. Section 4.4 presents a low-power programmable gain stage implementation that follows the CSF stage and allows electronic selection of the channel gain and bandwidth. After introducing the building blocks of the channels of the ExG ASIC and the EEG ASIC, Sect. 4.5 describes the architecture of the single-channel ExG readout front-end ASIC. In addition, the same Section also demonstrates the performance test results and presents the biological signals that are extracted using the single channel ExG readout front-end ASIC. Similarly, Sect. 4.6 describes the architecture of the eight-channel EEG readout front-end ASIC and presents both the performance test results and the biological test results of the ASIC. Section 4.7 compares the performance of the presented ACCIA architecture with the literature. Finally, Sect. 4.8 presents the conclusions of this Chapter. R.F. Yazıcıo˘glu et al., Biopotential Readout Circuits for Portable Acquisition Systems, © Springer Science + Business Media B.V. 2009

39

40

Biopotential Readout Front-End ASICs

4.2 AC Coupled Chopper Modulated IA (ACCIA) 4.2.1 Architecture of the ACCIA In order to benefit from the advantages of the chopper modulation technique for biomedical applications, AC coupling must be introduced to prevent the readout channel saturation. Figure 4.1 shows the concept of the proposed ACCIA. The input voltage is modulated by the input chopper and amplified by the core amplifier. The servo-loop implemented by a LPF stage filters the output, and subtracts it from the input of the core amplifier. Thus, the HPF characteristics can be implemented. The proposed ACCIA implementation uses a CBIA architecture as the core amplifier (refer to Fig. 2.4 for the operation principle of a CBIA). The operation of the ACCIA can be described as follows: The DC input voltage, which is the differential DC electrode offset voltage for biopotential applications, is modulated by the input chopper and copied to the terminals of R1 . This voltage creates a current through R1 , which is copied to R2 and converted into voltage, which defines the output voltage of the ACCIA after demodulation by the output chopper. A transconductance stage, GM, with the transfer function: GM(s) =

gm s 1 + 2πf c

(4.1)

passes only the components with frequencies lower than fc of the GM stage. Later, a chopper modulates the output current of the GM stage. At steady-state, the current supplied by the GM stage equals to VDC /R1 . Therefore, all the current passing through R1 due to the input DC voltage is supplied by the GM stage. Since, no current is supplied by the CBIA for the signals with frequencies below the fc , the current through R2 is zero. Therefore, the ACCIA can filter the differential DC electrode offset of the biopotential electrodes.

4.2.1.1 Gain-Bandwidth of the ACCIA The transfer function of the ACCIA of Fig. 4.1 can be calculated as (4.2), assuming that the low-pass cut-off frequency of the CBIA, fLP,IA , is much larger than fchop . If the gm R2 of (4.2) can be made much larger than unity, then the transfer function of the ACCIA reduces to (4.3). Av,ACCIA (s) =

s + 2πfc Vout R2 (s) = Vin R1 s + (2πfc )(1 + gm R2 )

(4.2)

s + 2πfc Vout R2 (s) = Vin R1 s + (2πfc )gm R2

(4.3)

Av,ACCIA (s) =

4.2 AC Coupled Chopper Modulated IA (ACCIA)

41

Fig. 4.1 Concept of the AC-coupled chopped instrumentation amplifier

As a consequence, it can be concluded that the ACCIA structure of Fig. 4.1 implements a HPF with cut-off frequency, fHP,ACCIA , equals to: fHP,ACCIA = gm × R2 × fc

(4.4)

thus it is capable of filtering the differential DC electrode offset between the biopotential electrodes.

4.2.1.2 Noise Calculation of the ACCIA The noise PSD of the ACCIA can be calculated from (2.11). If fLP,CBIA  fchop and fc,1/f  fchop , then the input referred noise PSD of the ACCIA, SACCIA , can

42

Biopotential Readout Front-End ASICs

be expressed in terms of the input referred noise PSD of the CBIA, SCBIA , as:   fc,1/f SACCIA (f ) = SCBIA,thermal 1 + 0.8525 fchop ∼ (4.5) = SCBIA,thermal This indicates that SACCIA equals to the thermal noise component of the SCBIA , SCBIA,thermal . In addition to the noise of the ACCIA, the GM stage also contributes to the total noise of the ACCIA. However, this contribution is not important in the pass-band of the ACCIA since the input referred noise of the GM stage is filtered by its transfer function. As a result, the total noise of the ACCIA can be expressed as the summation of the input referred noise PSD of the GM stage, SGM and SCBIA,thermal : SACCIA,total = SCBIA,thermal + SGM × GM(s) × R1 ∼ = SCBIA,thermal

(4.6)

It should be noted that the LPF cut-off frequency for the input referred noise of the GM stage is gm R2 times lower than the cut-off frequency of the ACCIA in (4.4). Therefore, it is significantly filtered at the frequencies of interest for the biopotential signals. Hence, the noise of the GM stage can be designed to have negligible contribution to the total noise of the ACCIA. As a result, the presented ACCIA architecture is capable of filtering not only the differential DC electrode offset but also the 1/f noise of the CBIA. As it will be demonstrated in the following Sections, the noise contribution of the GM stage to the total noise is negligible.

4.2.1.3 Structure of the ACCIA Figure 4.2 shows the implementation of the concept presented in Fig. 4.1. The simplified schematic of the CBIA is used for the clarity of the schematic. The GM stage of Fig. 4.1 is implemented by the combination of the OTA2 -Cext2 LPF and the transconductance stage, gm2 . This results in an equivalent transconductance of Av,OTA2 × gm2 , where Av,OTA2 is the open-loop voltage gain of OTA2 . This ensures the condition gm R2  1 for the implementation of the characteristics presented in (4.3). Therefore, by replacing the gm of (4.3) with Av,OTA2 × gm2 , and fc with gm,OTA2 /(Av,OTA2 Cext2 ), fHP,ACCIA can be written as:   gm,OTA2 (4.7) fHP,ACCIA = gm2 R2 2πCext2 The OTA2 is implemented as a current mirror OTA, Fig. 4.3(a), where gm,OTA2 is reduced using series-parallel division of current [45, 46]. The gm2 stage is implemented as a basic differential stage, Fig. 4.3(b), which acts as a voltage-to-current

4.2 AC Coupled Chopper Modulated IA (ACCIA)

43

Fig. 4.2 ACCIA implementation that can eliminate the 1/f noise, the differential DC electrode offset, and the IA offset

Fig. 4.3 (a) Schematic of the current mirror OTA that is used to implement the OTA1 -Cext1 and OTA2 -Cext2 low-pass filters of Fig. 4.2, (b) schematic of gm1 and gm2 of Fig. 4.2

44

Biopotential Readout Front-End ASICs

converter. The output current of gm2 is mirrored to the terminals of R1 through current mirrors, CM1 and CM2 . Therefore, as it is described in the beginning of this Section, the current through R1 due to the differential DC input voltage can be supplied by the difference of the current through the branches of gm2 stage. Thus, no current is copied to R2 and the output is nulled. The maximum differential DC electrode offset that can be filtered by the ACCIA is defined by the maximum current that can be supplied through the servo-loops. Therefore, the limit of the servo-loop is achieved, when the difference between the currents through CM1 and CM2 equals the tail current of gm2 stage, Ibias2 , of Fig. 4.3(b). Hence, the maximum allowed differential DC electrode offset voltage that can be filtered by the ACCIA can be expressed by: Velec-off ,max = R1 ×

Ibias2 2

(4.8)

Similar to the OTA2 -Cext2 and gm2 servo-loop, another servo-loop consisting of OTA1 -Cext1 and gm1 is implemented in order to filter the offset voltage of the CBIA. Unlike the OTA2 -Cext2 filter, the input of OTA1 is connected to the output of the CBIA, before the output chopper. At this node the input voltage to the ACCIA is modulated to fc . Therefore, the OTA1 -Cext1 filter only passes the amplified offset voltage of the CBIA. The gm1 stage converts the voltage output of the OTA1 -Cext1 filter to current, which is mirrored to the terminals of R1 through the current mirrors CM1 and CM2 . At steady-state the current difference between the branches of the gm1 stage equals to the input referred offset voltage of the CBIA divided by R1 , Voffset,CBIA /R1 . Hence, the offset of the CBIA can be filtered. The maximum CBIA offset that can be filtered by the servo-loop can be expressed as: Ibias1 (4.9) VCBIA-off ,max = R1 × 2 As a result, the combination of the two servo-loops implemented by the OTA1 Cext1 and gm1 , and OTA2 -Cext2 and gm2 can filter both the differential DC electrode offset voltage between the biopotential electrodes and the offset voltage of the CBIA.

4.2.2 Architecture of the CBIA The main power consuming block of the ACCIA is the CBIA. Therefore, the number of parallel branches of the CBIA must be minimized in order to minimize the power dissipation. Figure 4.2 includes the simplified schematic of the implemented CBIA structure. It consists of 4 parallel branches and the need for opamps as in the case of [20, 30–33] is eliminated. Hence, the power dissipation can be lowered. The presented CBIA consists of two transconductance stages operating in negative feedback. The operating principle can be described as follows: The differential

4.2 AC Coupled Chopper Modulated IA (ACCIA)

45

input voltage creates a current through R1 that decreases the current through the input transistor with the higher gate voltage. This disturbs the equality of the voltages at the gates of the transistors M2 and M3 . This voltage difference creates a current through R2 . This current disturbs the equality of the currents passing through M2 and M3 . At steady state, the current difference between M1 and M2 reaches to the same value as the current passing through R1 . As a result, the current passing through the input transistors M2 and M3 are held constant. Therefore, the transconductance stage implemented by M2 , M3 and R2 not only serves the purpose of the gmi stage of the CBIA architecture in Fig. 3.2, but also performs the operation of the transresistance stage, which allows to save considerable power compared to the CBIA architecture of Fig. 3.2.

4.2.2.1 Gain-Bandwidth of the CBIA The voltage gain of the CBIA architecture can be calculated from the low-frequency small-signal half-circuit [51], Fig. 4.4, of the simplified CBIA structure. Assuming that Rds,1 and Rds,2 are much larger than R1 /2 and R2 /2, the voltage gain of the CBIA structure can be derived as: Av,CBIA (s) =  α= 1+

Vout,half 1 R2 =− Vin,half R1 1 + ( αR2 ) Rout,eq 1

gm,M1 R1

 1+

1 gm,M2 R2

(4.10)

 (4.11)

where Rout,eq equals to Rds,1 //Rout,2 . If αR2  Rout,eq , then the differential voltage gain of the CBIA can be written as (4.12), and the LPF cut-off frequency of the CBIA can be found by replacing Rout,eq with Rout,eq //(1/sCc ), which gives (4.13)

Fig. 4.4 Low-frequency small-signal circuit of the half-circuit of the CBIA of Fig. 4.2

46

Biopotential Readout Front-End ASICs

as the LPF cut-off frequency of the CBIA. Av,CBIA =

Vin,p − Vin,n R2 = Vout,p − Vout,n R1

1 fLP,CBIA = 2π



1 αR2 Cc

(4.12)

 (4.13)

Hence, both the voltage gain and the LPF cut-off frequency of the CBIA can be set by selecting R1 , R2 , and the transconductances of M1 and M2 . 4.2.2.2 Noise Calculation of the CBIA Keeping in mind that the power limit of the ACCIA is defined by the thermal noise level of the CBIA, the noise of the CBIA has to be minimized. Therefore, the noise contribution of each transistor to the total noise of the ACCIA has to be calculated. The input referred voltage noise PSD of the CBIA architecture, v2in,CBIA , can be found by using the simplified schematic of the CBIA shown in Fig. 4.2 as: v2in,CBIA = 2v2M1 + v2R1 + +2

2 gm,I  2  1 2 2 + 2 v + 2v v M2 A2v,CBIA R2 g12 I1

1

g2 2 + 2 m,I3 v2 v I (g1 //gm,M1 )2 2 g12 I3 2 gm,I 2

(4.14)

where gm,I1 , gm,I2 , and gm,I3 are the transconductances of the MOS transistors that implements the current sources I1 , I2 , and I3 , respectively. Assuming that Av,CBIA  1, then (4.14) reduces to: v2in,CBIA = 2v2M1 + v2R1 + 2

2 gm,I 1

g12

v2I1 + 2

g2 2 + 2 m,I3 v2 v (g1 //gm,M1 )2 I2 g12 I3 2 gm,I 2

(4.15)

expressing the input referred voltage noise PSD of the CBIA.

4.2.2.3 Structure of the CBIA Figure 4.5 shows the complete schematic of the implemented CBIA. The current mirrors I1,1 and I1,2 of the simplified CBIA schematic in Fig. 4.2 are implemented by the regulated cascode current mirrors (RGC) [52]. Compared to the current mirror structure of Fig. 3.4, this structure achieves similar output impedance with lower power dissipation due to the elimination of the opamp. The output impedance of the RGC mirrors can be given by: go,RGC =

gds,ML7 gds,ML8 (gds,ML9 + go,IRGC ) gm,ML8 gm,ML9

(4.16)

4.2 AC Coupled Chopper Modulated IA (ACCIA)

47

Fig. 4.5 Complete schematic of the current balancing IA that is used in the ACCIA implementation

Therefore, it boosts up the CMRRgo of (3.10) by decreasing go in (3.9). The implemented CBIA has a fully-differential architecture so the CMRRsys component of (3.10) is infinite. As a consequence, CMRRgds defines the CMRR of the CBIA under large differential DC input voltages. The transistors ML3 , ML4 and MR3 , MR4 serve as a level shifter in order to maximize the input-output voltage swing of the CBIA. The second gain resistor, R2 , is implemented by a long-channel nMOS transistor, so that the gain of the circuit can be continuously adjusted. Finally, due to the fully differential nature of the CBIA, a CMFB circuit is implemented. The CMFB circuit of the CBIA consists of two differential pairs as in [53], which sense the common-mode level of the output, and adjusts it by controlling the current through transistors ML5 , ML6 and MR5 , MR6 . Although CMRRgds defines the CMRR limit of the CBIA. It should be noted that this limit can not be increased by employing the chopper modulation technique since the differential DC input voltage is also modulated by the input chopper of the amplifier. Therefore, a dedicated input stage is implemented for increasing the CMRRgds limit of the CMRReq . Figure 4.6 shows the schematic of the implemented input stage for the CBIA architecture of Fig. 4.5. The purpose of the circuit is to assure that the Vsd,M1 of the transistor M1 is independent of the input DC level. This is achieved by utilizing the transistors Mc1 and Mc2 . The current source, Ibias , forces a constant current through Mc2 , which defines Vsg,c2 . On the other hand, Vsg,c1 of the transistor Mc1 is defined by the current passing through M1 and Mc1 , which is always kept constant by the feedback loop of the CBIA architecture (refer to Sect. 4.2.2 for the detailed description). Therefore, the Vsd,M1 of the transistor M1 can be defined

48

Biopotential Readout Front-End ASICs

Fig. 4.6 Schematic of the input transistors of the current balancing IA (CBIA) of Fig. 4.5

by: Vsd,M1 = Vsg,c2 − Vsg,c1

(4.17)

Equation (4.17) states that the Vsd,M1 of the input transistor M1 is independent of the DC level at the gate of M1 due to the fact that Vsg,c2 and Vsg,c1 are constant and defined by the constant quiescent current of the transistors. Consequently, the CMRRgds is infinite, since gds term in (3.8) is eliminated by the making Vsd,M1 independent of the input DC level. It is important to note that, any Vsd,M1 mismatch between the two symmetric input transistors of the CBIA will be eliminated by the chopper modulation technique. As a result, the CMRR of the presented CBIA is resistant to the increasing differential DC electrode offset voltage.

4.2.3 Power-Noise Performance of the ACCIA The total noise of the implemented ACCIA can be found by combining the results of (4.6) and (4.15). In addition, the noise contributions of the gm stages gm1 and gm2 , and the transistors CM1 and CM2 of Fig. 4.2 has to be included for calculating the total noise of the ACCIA. The input referred PSD of a MOS transistor operating in saturation region consists of the thermal noise and the 1/f noise, and can be expressed as [54]:   KFF f α + (4.18) v2in = 4kT 2 f gm W LCox where α is a constant, ranging from 2/3 (strong inversion) to n/2 (weak inversion) [48]. The dominant noise source for the ACCIA is the thermal noise of the MOS transistors, since the 1/f noise will be eliminated by the chopper modulation technique. Assuming that the sizes of the transistors CM1 and CM2 of Fig. 4.2 are same

4.2 AC Coupled Chopper Modulated IA (ACCIA)

49

with the transistors ML7 and MR7 of the RGC current mirror in Fig. 4.5 (so their transconductance is same and indicated with gm,I1 ), then the total input referred noise PSD of the ACCIA can be written using (4.15) as:  v2in,ACCIA,min = 8kT +α

α gm,M1

+

1 (gm1 + gm2 ) +α 2g1 g12

(2gm,I1 + gm,I3 ) gm,I2 +α (g1 //gm,M1 )2 g12

 (4.19)

which includes the noise contributions from the transistors CM1 and CM2 (factor 2 in front of gm,I1 ), and from the transconductance stages gm1 and gm2 . Above equation indicates that the noise of the ACCIA can be decreased by operating the input pair transistors in weak inversion, which maximizes their transconductance for a given current consumption [48]. Additionally, g1 must be maximized. However, the larger the value of g1 , the smaller the maximum differential DC electrode offset that can be filtered by the ACCIA, which is defined by (4.8). Therefore, constantly increasing g1 necessitates higher current consumption for a constant Velec-off ,max . For this reason, selecting g1 close to gm,M1 will give a good compro2 . In addition, designing all the current mise between the Velec-off ,max and vin,ACCIA sources in strong inversion and input pair transistors in weak inversion will assure that g1 and gm,M1 are much larger than gm,I1 , gm,I2 , and gm,I3 . Therefore, (4.19) can be simplified to (4.20), which gives the theoretical noise floor for the presented ACCIA architecture.

v2in,ACCIA,min

8kT = gm,M1



n 1 + 2 2

 (4.20)

Hence, using (2.4) the NEF of the ACCIA can be written as:  2Itot gm,M1 Vt

NEF =



n 1 + 2 2

 (4.21)

which reduces to (4.22), knowing that M1 is operating in weak inversion and its transconductance can be expressed as Ids /(nVt ) [48]. It has been also assumed that the current passing through an input pair transistor is 1/6 of the total current consumption of the ACCIA (4/6 of the total current is consumed by the CBIA and 2/6 is consumed by the gm1 and gm2 ). As a result, the NEF limit of the presented ACCIA can be calculated as 4.6 (n is 1.45 in AMIS 0.5 µm CMOS technology [55]).  NEF =



n 1 + 12n 2 2

 = 4.6

(4.22)

50

Biopotential Readout Front-End ASICs

Fig. 4.7 Schematic and operation principle of the Chopping Spike Filter (CSF) stage

4.3 Chopping Spike Filter (CSF) Two common problems of the chopped amplifiers are the chopping spikes due to the charge injection from the input chopper switches and the signal distortion due to the finite bandwidth of the core amplifier (refer to Sects. 2.5.2 and 2.5.3). Figure 4.7 shows the CSF stage that can be used for filtering the chopping spikes and the distortion spikes. The operation principle of the CSF stage is based on T&H operation. The start time of the spike at the output of the ACCIA is precisely known from the chopping clock. Therefore, the switch S can be opened just before the switching moment of the chopping clock and kept open. Therefore, the spike free signal is held on the capacitor CH . Since, S is kept open during the presence of the chopping spikes, the output of the CSF stage will be cleaned from the chopping spikes. The most important concern about the CSF stage is the noise fold-over due to the sampling nature of the proposed CSF stage. The effect of CSF stage on the output noise of the ACCIA can be found from the noise transfer function of a T&H stage [56]. Therefore, the output noise of the CSF stage is simply the input noise of the CSF stage, which includes the output noise of the ACCIA, multiplied by the noise transfer function of the T&H stage:   2BWn m2 2 πmf 2 2 vout,CSF = vout,ACCIA × sinc fCSF fCSF

 BW n /fCSF 

 2 2 (4.23) + 1−m 1+2 sinc πn(1 − m) n=1

where m is the duty cycle of the hold time (TOFF /TCSF ), BWn is the noise bandwidth of the input signal (πfLP,ACCIA /2). The first and second terms in the brackets represents the noise contributions of the hold and the track operations, respectively. Figure 4.8 shows the plot of the transfer function presented in (4.23) with changing duty cycle, m, and changing κ = fLP,ACCIA /fCSF . As m decreases, the noise gain of the ACCIA stage approaches 1, independent of κ. As a conclusion, if m of

4.4 Low-Power Programmable Gain Stage

51

Fig. 4.8 Magnitude of the noise transfer function of the CSF stage for input signal frequency smaller than fCSF and with changing duty cycle, m. κ represents the ratio of fLP,ACCIA /fCSF

the CSF stage is kept below 10%, then the effect of the CSF stage on the output noise of the ACCIA is negligible. However, this limits the minimum fLP,ACCIA due to the fact that most of the spike energy must be concentrated in the 10% of the CSF stage operating period, TCSF . The time constant of the distortion spikes at output of the ACCIA can be given as (refer to Sect. 2.5.3): τACCIA =

1

(4.24)

2πfLP,ACCIA

where fLP,ACCIA is defined by (4.13). Hence, TOFF must be larger than 3 × τACCIA so that the ACCIA output can settle after the chopper switches change their state. Therefore, the following condition should hold between fchop , which is always fCSF /2, and fLP,ACCIA . 3τACCIA <

1 TCSF 10

⇒

fLP,ACCIA >

30 fchop π

(4.25)

4.4 Low-Power Programmable Gain Stage Configurable gain and bandwidth is vital for the biopotential readout circuits due to the fact that not only different biopotential signals have different amplitude and frequency behavior but also various applications of the biopotential signals focus on the different characteristics. Figure 4.9 shows the architecture of the proposed gain stage that has electronically settable gain and bandwidth. It consists of a fixed gain stage and a VGA. The fixed gain stage of the architecture is implemented as proposed in [57], which also acts as a differential to single-end converter. The low-power characteristics of

52

Biopotential Readout Front-End ASICs

Fig. 4.9 Low-power configurable gain stage architecture for the biopotential readout circuits

this amplifier makes it ideal to be used in the gain stage. It should be noted that, the very low CMRR of this amplifier is not important, since it will be used as a back-end stage in the channel architecture of the readout front-end, and the CMRR will be set by the ACCIA. The gain of this architecture is defined by the ratio of the two capacitors as C1,1 /C1,2 . The core OTA is implemented as a current mirror amplifier as shown in Fig. 4.3(a). Hence, the bandwidth of the fixed gain stage can be adjusted by selecting the load capacitance of the OTA. The load capacitances are implemented as nMOS transistors, and the value of the load capacitance can be changed by the SBW switches. The fixed gain stage is followed by a VGA. Conventional VGAs use either SC or resistive feedback topologies, where former has the aliasing problem and latter consumes excessive power. The proposed VGA stage of the programmable gain stage operates in continuous-time and gain is defined by the ratio of capacitors. Thus, while achieving low-power dissipation, it can also perform the operation of an anti-aliasing filter. The pseudo-resistors of [57] set the DC level at the inverting node of the OTA of the VGA. Similar to the fixed gain stage, a current mirror OTA has been used. The transfer function of the VGA can be written as:     1 1 CT AV ,VGA (s) = 1 + s+ s+ C1 CT Rpar C1 Req     CT CL +1 (4.26) ×1 s C1 gm,OTA where CT is the total equivalent capacitance of the variable capacitor bank, Req is the equivalent resistance of the pseudo resistors, CL is the total load capacitance,

4.5 Single-Channel ExG Readout Front-End

53

and Rpar is the any parasitic resistance between node A and ground. The variable capacitor bank architecture of the presented VGA stage prevents any parasitic resistance at node A, thus the DC gain of the VGA can be set to unity, and the transfer function can be expressed as:   s CT 1 AV ,VGA (s) = 1 + × (4.27) CT CL C1 (s + C 1R ) [s( ) + 1] C1 gm,OTA 1 eq indicating that the in-band gain is defined by the ratio of CT and C1 . CT can be set through the switches of the capacitor bank. If a capacitor is connected to the ground, it increases CT , else it does not contribute to the total capacitance, since source follower stage equalizes the voltages on the terminals of the capacitor. Additionally, the LPF cut-off frequency of the VGA can be set through the variable load capacitance.

4.5 Single-Channel ExG Readout Front-End 4.5.1 Implementation An analog readout front-end that has configurable characteristics for extracting EEG, ECG, and EMG signals has been designed. Figure 4.10 shows the architecture of the ExG readout front-end ASIC. It uses the ACCIA architecture as the preamplifier, which defines the noise and the CMRR of the channel, and filters the differential DC electrode offset. The ACCIA is followed by the CSF stage that eliminates both the chopping spikes due to the charge injection from the input chopper switches and the distortion spikes due to the finite bandwidth of the ACCIA. The programmable gain stage is used after the CSF stage to further amplify the signal, and to set the gain and the bandwidth for different biopotential signals. It also serves the purpose of a second order anti-aliasing filter. Finally, a buffer that is capable of driving a 50 pF load at 5 kHz serves as an interface between any external circuit and the ExG readout front-end. The presented readout front-end is implemented in AMIS 0.5 µm three-metal double-poly CMOS process through AMIS. Figure 4.11 shows the die micrograph. Core area measures less than 2 mm2 . Table 4.1 lists the operating points of the transistors in the ACCIA implementation for the ExG readout front-end ASIC. Transistors of the current sources, I1 , I2 , and I3 are operated at the edge of the stronginversion and the moderate-inversion for a good compromise between noise and input-output voltage swing. Transistor sizes are large to decrease the corner frequency of the 1/f noise below fchop /2. The corner frequency of the 1/f noise is simulated to be 400 Hz, thus the chopping frequency is selected to be 10 times the 1/f noise corner frequency as 4 kHz to minimize the contribution of the 1/f noise to the total noise as described in (2.10). The bandwidth of the ACCIA is 40 kHz, which satisfies both the condition fLP,ACCIA /fchop  1 in (2.8) and the condition for filtering the distortion signal in (4.25).

Fig. 4.10 Architecture of the ExG biopotential readout front-end that is designed for the acquisition of EEG, ECG, and EMG signals

54 Biopotential Readout Front-End ASICs

4.5 Single-Channel ExG Readout Front-End

55

Fig. 4.11 Die micrograph of the ExG biopotential readout front-end ASIC implemented in AMIS 0.5 µm three-metal double-poly CMOS process through AMIS Table 4.1 Operating points of the transistors in Fig. 4.5, Fig. 4.6, and Fig. 4.3(b) for the ExG readout front-end ASIC Transistors

W/L (µm/µm)

Ids (µA)

gm /Ids (1/V)

Current Balancing IA (CBIA) MR2 , ML2

40/5

1.0

19.5

MR3 , ML3 , MR4 , ML4

50/4

0.1

22.6

MR5 , ML5

8/75

0.4

7.5

MR6 , ML6

8/2

0.4

20.2

MR7 , ML7 , CM1 , CM2

24/20

1.2

7.5

MR8 , ML8

100/2

1.2

21

MR9 , ML9

80/2

0.2

23.4

MI 1 , McI 1

12 × [2/20, 5/2]

1.2

7.4, 19.9

MI 2 , McI 2

4 × [4/75, 4/2]

0.8

7.5, 20.1

MI 3 , McI 3

10 × [2/20, 5/2]

1.0

7.4, 19.9

MR2

2/120 CBIA Input Stage Transistors

MR1 , ML1

1120/7

1.2

22.6

MRC1 , MLC1

112/4

1.2

19.3

MRC2 , MLC2

16/128

0.2

5.9

GM Stages in the Offset Filter Loop of the ACCIA Mgm1

2.5/80

0.3

4.85

Mgm2

7.5/80

0.9

4.78

R1 of the ACCIA is selected to be 50 k, which is implemented using a hipo resistor, so that g1 of (4.19) is close to gm,M1 in order to minimize noise. R2 is implemented by a nMOS transistor of size 2/120. If the output common-mode level is set to 1.15 V by the CMFB circuit and the gate bias is tied to 3 V, the equivalent

56

Biopotential Readout Front-End ASICs

Fig. 4.12 Differential DC electrode offset voltage measurements from Ag/AgCl electrode pairs. Two different subjects and two different electrode types are used. Five electrodes from each type are placed on the chest of the two subjects. The dotted lines show the maximum measured differential DC offset voltage from all possible combinations and the straight line shows the average

resistance of this nMOS transistor is 500 k, setting the voltage gain of the ACCIA to 10. Another consequence of selecting R1 as 50 k is that the ACCIA can filter a maximum differential DC electrode offset voltage of 50 mV (see 4.8). Although the ANSI-AAMI EC13 standards [58] states that Cardiac Monitors have to be able withstand differential DC electrode offset voltages of ±300 mV, this value is stated considering the usage of different kinds of electrodes (e.g. Stainless Steel, Ag/AgCl) and considering the DC input current limit of 100 nA, which can polarize the electrodes and create considerable offset voltage. It should be noted that this design is specifically intended for Ag/AgCl electrodes, which are known for their low-offset voltages and stability due to their non-polarizable characteristics [11]. Figure 4.12 shows our differential DC electrode offset measurements from several electrode pairs on two different subjects. The maximum measured differential electrode offset voltage is smaller than 20 mV, which is less than half of the maximum allowed limit of the ACCIA. The operating frequency of the CSF stage, fCSF , is 8 kHz, and the duty cycle is selectable between 6.25% and 12.5%. The programmable gain stage is implemented with a fixed first stage gain of 20. The VGA stage has selectable gain values of 2, 4, 8, and 13. Therefore, the total channel gain can be set to 400, 800, 1600, and 2600. Table 4.2 summarizes the building blocks of the ExG readout front-end ASIC.

4.5.2 Measurement of Performance Figure 4.13 shows the measured gain-bandwidth of the ExG readout front-end ASIC with changing VGA settings, when the ACCIA voltage gain is 10. The voltage gain

4.5 Single-Channel ExG Readout Front-End

57

Table 4.2 Summary of the building blocks of the ExG readout front-end ASIC AC Coupled Chopped IA (ACCIA) BWACCIA fchop Av,ACCIA Current Consumption Input Ref. Noise Density NEF

40 kHz 4 kHz 10 11.1 µA√ 57 nV/ Hz 9.2

3 V gate bias

Chopping Spike Filter (CSF) fCSF Duty Cycle (m) Current Consumption

8 kHz 6.25%, 12.5% 0.8 µA

1-bit digital input

Programmable Gain Stage Programmable Gain Current Consumption

40, 80, 160, 260 1.4 µA and 0.75 µA

2-bit digital input Fixed Gain Stage and VGA

Buffers and Bias Circuit Output Buffer Current Bias Buffers Bias Circuit

2.4 µA 2 × 0.6 µA 2.4 µA Complete ASIC

Total Current Consumption Operating Voltage Total Power Dissipation

20 µA 3V 60 µW

of the ASIC can be set to 400, 800, 1550 and 2500. Moreover, the HPF cut-off frequency can be adjusted via external capacitor Cext2 of Fig. 4.2. The HPF cutoff frequency appears at 0.3 Hz for Cext2 of 1 µF, convenient for EEG and ECG applications, and can be set to 14 Hz for EMG applications by changing Cext1 to 22 nF. Additionally, the LPF cut-off frequency can be set by changing the capacitive load of the gain stages through SBW switches of Fig. 4.9. Figure 4.14 shows the CMRR measurement of the ExG front-end and the change of the CMRR with increasing differential DC input voltage to simulate the increasing electrode offset voltage. The CMRR of the front-end is better than 120 dB up to 1 kHz and better than 110 dB, measured at 100 Hz, with 50 mV differential DC input voltage. This demonstrates the effectiveness of the presented input stage in Fig. 4.6. The importance of the presented input stage can be realized more, if we compare the CMRR change of the presented ACCIA with the CMRR change of the IA in Fig. 3.8. The presented ACCIA achieves 20 dB higher CMRR than the CMRR of the IA in Sect. 3.4 under 50 mV differential DC input voltage. It is important to

58

Biopotential Readout Front-End ASICs

Fig. 4.13 Gain and bandwidth measurements of the ExG readout front-end. Gain is selectable through the VGA. The HPF cut-off frequency is defined by the external capacitor, Cext2 . The LPF cut-off frequency is set by digitally selecting the load capacitors of the programmable gain stage

Fig. 4.14 CMRR measurement of the ExG readout front-end and the change of the CMRR with increasing differential DC input voltage to simulate the electrode offset

4.5 Single-Channel ExG Readout Front-End

59

(a)

(b) Fig. 4.15 CSF stage test (a) for the chopping spikes generated due to the charge injection from the input chopper switches, (b) for the signal distortion spikes due to finite bandwidth of the CBIA. The spectrums are shifted to increase the clarity. Amplitudes are referred to the output of the channel

remember that the chopper modulation technique has no effect on this CMRR improvement. Therefore, this improvement is completely due to the presented input stage. Figure 4.15(a) demonstrates the operation of the CSF stage both for the chopping spikes and for the distortion spikes. Measurement is recorded at the output of the ExG readout front-end ASIC. The gain of the readout is 800, the bandwidth is set to minimum, and the CSF duty cycle is 6.25%. The inputs of the ASIC are connected to a fixed voltage through two 10 k resistors to simulate the electrode impedance. The chopping spikes generated due to the charge injection from the input chopper switches can be completely filtered by the CSF stage.

60

Biopotential Readout Front-End ASICs

Fig. 4.16 Measured input-referred voltage noise PSD of the ExG readout front-end demonstrating the reduction of 1/f noise. Chopping reduces the 1/f noise corner frequency from 350 Hz to 3 Hz. The residual 1/f noise is due to the OTA2 stage and the back-end stages

Similar to this test, another test is also performed for measuring the efficiency of the CSF stage on filtering the distortion spikes, which occur due to the finite bandwidth of the CBIA. Figure 4.15(b) shows the measurement result. The gain of the readout is 400, the bandwidth is set to maximum, and the CSF duty cycle is 6.25%. The amplitude of the distortion spike at 8 kHz is reduced more than 8 times. Figure 4.16 shows the measured input referred voltage noise PSD of the ExG readout√front-end. The thermal noise level of the front-end is measured to be √ 57 nV/ Hz, which is consistent with the simulated value of 60 nV/ Hz. Chopping effectively eliminates the 1/f noise of the CBIA. The corner frequency of the 1/f noise is reduced from 350 Hz to 3 Hz. Residual 1/f noise is due to the OTA2 stage of Fig. 4.2 and the stages following the ACCIA, and has negligible effect on the total noise of the ACCIA. As Fig. 4.16 shows, 1/f noise is decreased, if the gain of the ACCIA is set to 20 via changing the gate bias of R2 proving that the most of the residual 1/f noise is due to the back-end stages. Table 4.3 presents the improvement of the noise performance with chopping for different applications of the ExG ASIC. Especially the improvement for the EEG applications is more than 50%. Table 4.4 summarizes the measured performance of the ASIC.

4.5 Single-Channel ExG Readout Front-End Table 4.3 Improvement of total noise with chopping

61

Application Integration BW (Hz)

Unchopped Noise (µVrms )

Chopped Noise (µVrms )

EEG

0.5–40

0.95

0.41

ECG

0.5–125

1.21

0.67

EMG

14–350

1.32

1.05

Table 4.4 Performance summary of the ExG readout front-end ASIC measured from 4 chips Performance Summary (4 Chips) Voltage Supply

3V

Current Consumption

20 µA

Input Common Mode Range

1.05 V–1.7 V

Electronics Gain Selection (IA Gain = 10)

390, 800, 1550, 2500

Continuous Gain Adjustment

via R2

Input Referred Voltage Noise Density

56.6–57.4 nV/sqrt (Hz)

THD (5 m Vpp input and with minimum gain)

0.45–0.52%

CMRR (0 mV Differential DC Input Voltage)

>120 dB

CMRR (50 mV Differential DC Input Voltage)

>110 dB

PSRR+, PSRR− (@ 50 Hz)

>80 dB, >78 dB

HPF Cut-Off Frequency (Cext2 = 1 µF, Cext2 = 22 nF)

0.30–0.34 Hz, 14.0–15.8 Hz

LPF Cut-Off Frequency Gain = 390

0.65, 0.88, 1.35, 1.85 kHz

Gain = 800

0.4, 0.65, 0.8, 1.2 kHz

Gain = 1550

0.25, 0.34, 0.5, 1 kHz

Gain = 2500 Input Impedance

0.15, 0.23, 0.33, 0.6 kHz >100 M

4.5.3 Biological Test Results Figure 4.17 shows the extracted biopotential signals from the ExG readout frontend ASIC using disposable Ag/AgCl electrodes for the ECG and the EMG signals, and using Ag/AgCl cup electrodes with conductive paste for EEG measurements. It is important to note that no digital signal processing is performed on the extracted biopotential signals. The EEG measurement has been performed on a subject with two electrodes connected to the backside of the head (occipital cortex) and when his eyes are closed. The gain of the front-end is set to 2500 with minimum bandwidth configuration (150 Hz), and the HPF cut-off frequency is set to 0.3 Hz by selecting Cext2 of 1 µF. Figure 4.18 demonstrates that the dominant rhythm of the EEG signal is in the alpha range (8–13 Hz) [10], and there is no sign of 50 Hz. Similarly, the ECG signal is extracted by connecting two electrodes to the chest of the subject and setting the gain of the front-end to 800 and the bandwidth to

Fig. 4.17 Extracted ExG signals from the ExG readout front-end using Ag/AgCl electrodes without digital signal processing. Signals amplitudes are referred to the circuit input

62 Biopotential Readout Front-End ASICs

4.6 Eight-Channel EEG Readout Front-End

63

Fig. 4.18 Spectrum of the extracted EEG signal of Fig. 4.17 from occipital cortex. Patients’ eyes are closed, thus dominant rhythm is in alpha range

400 Hz, and keeping the HPF cut-off frequency at 0.3 Hz. All the characteristics of an ECG signal, the P wave, the QRS complex, and the T wave, are clearly visible without any sign of 50 Hz. Finally, for the extraction of EMG waves, two electrodes are connected to the biceps muscles of the right arm, and gain is set to 400 with LPF cut-off frequency of 650 Hz, and Cext2 is changed by a 22 nF capacitor in order to set the HPF cut-off frequency to 14 Hz. The EMG signal appearing due to the contraction of the biceps muscle is clearly visible at the output.

4.6 Eight-Channel EEG Readout Front-End 4.6.1 Implementation A biopotential readout front-end circuit dedicated to EEG signal extraction is implemented. Figure 4.19 shows the architecture of the eight-channel EEG readout front-end ASIC. The channel architecture of the EEG readout front-end is similar to the architecture of the ExG readout front-end ASIC. Each channel consists of an ACCIA as the preamplifier, a CSF stage to filter the chopping spikes and distortion spikes, and a programmable gain stage to set the gain and the bandwidth of the channel for different applications of the EEG signal analysis. Each channel uses a channel buffer to prevent the kick-back effect of the output analog multiplexer. The analog multiplexer circuit time multiplexes the channels and an output buffer drives the multiplexed signal to the output, so that a single ADC can sample all the channels of the ASIC. The bias circuit of the ASIC not only generates the necessary bias currents for the building blocks of the ASIC, but also generates two reference current sources, from

Fig. 4.19 Architecture of the eight-channel EEG readout front-end ASIC

64 Biopotential Readout Front-End ASICs

4.6 Eight-Channel EEG Readout Front-End

65

Fig. 4.20 Die micrograph of the eight-channel EEG readout front-end ASIC implemented in 0.5 µm three-metal double-poly CMOS process through AMIS

which the patient bias (patient ground) and other DC bias voltages of the ASIC can be generated. The on-chip buffers with LPF characteristics are used to buffer and filter the excess noise on these DC voltage levels. All the digital signals of the chip are generated by the on-chip digital control circuit. This circuit accepts a 64 kHz external clock as an input and generates all the necessary timing signals from this single clock input. The presented ASIC has been implemented in 0.5 µm three-metal double-poly CMOS process. Figure 4.20 shows the die micrograph of the eight-channel EEG readout front-end ASIC. The noise and the CMRR performance of the readout channel is defined by the ACCIA, which has been implemented as shown in Fig. 4.2. A more detailed explanation of the design of ACCIA is given in Sect. 4.5.1 for the ACCIA of the ExG readout front-end ASIC, therefore in this section only a brief description will be presented. The voltage gain of the ACCIA is set to 10 by the CBIA architecture shown in Fig. 4.5 by selecting R1 as 100 k and implementing R2 with a nMOS transistor of size 2/255. If the common-mode output voltage level is set to 1.15 V, this transistor implements a 1 M resistor. Table 4.5 shows the dimensions and the operating points of the transistors of the CBIA implementation for the eight-channel EEG readout front-end ASIC. The simulated 1/f noise corner frequency is 60 Hz, thus the chopping frequency of the ACCIA is set to 1 kHz. The simulated bandwidth of the

66

Biopotential Readout Front-End ASICs

Table 4.5 Operating points of the transistors in Fig. 4.5, Fig. 4.6, and Fig. 4.3(b) for the eightchannel EEG readout ASIC Transistors

W/L (µm/µm)

Ids (nA)

gm /Ids (1/V)

Current Balancing IA (CBIA) MR2 , ML2

40/10

500

19.8

MR3 , ML3 , MR4 , ML4

50/4

50

23.7

MR5 , ML5

8/100

400

6.5

MR6 , ML6

12/2

400

21

MR7 , ML7 , CM1 , CM2

24/40

600

7.4

MR8 , ML8

100/2

600

22.3

MR9 , ML9

80/2

100

24.5

MI 1 , McI 1

24/40, 60/4

600

7.4, 19.7

MI 2 , McI 2

4/75, 4/2

200

7.5, 20.1

MI 3 , McI 3

10/75, 10/2

500

7.5, 20.1

MR2

2/255 CBIA Input Stage Transistors

MR1 , ML1

1120/7

600

23.8

MRC1 , MLC1

112/4

600

20.9

MRC2 , MLC2

16/128

100

8.2

GM Stages in the Offset Filter Loop of the ACCIA Mgm1

2.5/160

150

4.85

Mgm2

7.5/160

450

4.71

CBIA is 20 kHz. Similar to the ExG ASIC, the EEG ASIC can also filter ±50 mV differential DC electrode offset voltage. The CSF stage of the each channel operates at 2 kHz with selectable duty cycle of 3.125% or 6.25%. The programmable gain stage has 8 different gain settings between 2000 and 9000. The readout channels of the ASIC needs various bias voltages and bias currents. In battery powered systems, the supply voltage changes as the battery discharges. Therefore, the eight-channel EEG readout front-end ASIC includes a supply independent bias generator circuit, Fig. 4.21. The core of the bias circuit is the reference current generator circuit. The transistors M1 –M4 of the reference current generator operates in weak inversion, therefore the reference current can be expressed as: Iref = n × Vt ×

ln(a) R

(4.28)

where n is the weak inversion slope factor (1.45 for AMIS 0.5 µm CMOS technology [55]) and a is the ratio between the current mirrors. If a 63.4 k resistor is used and the mirroring ratio is 8, the generated reference current is set to 1.2 µA. The negative feedback nature of the reference current generator circuit is also stable while no current passes through its branches. Therefore, a start-up circuit

4.6 Eight-Channel EEG Readout Front-End

67

Fig. 4.21 Bias generator circuit of the eight-channel EEG readout front-end ASIC. The supply independent bias circuit generates the bias currents for the channels. The bias buffers filters and buffers the bias voltages

is included, which forces an initial current through the branches of the reference current generator during the start-up. The bias circuit generates eight bias currents for each readout channel of the ASIC. In addition to that, two reference current sources (1 µA source current and 1.2 µA sink current) are generated so that all the bias voltages of the ASIC can be generated from the two sets of external resistors. The voltages that needs to be constant with changing power supply voltage are generated from the source current, where as the voltages that need to be changing together with power supply voltage (e.g. the gate bias of the cascode transistor of the pMOS current sources) are generated from the current sink. Additionally, the bias circuit includes three low power buffer circuits (one of them is a dummy buffer circuit). One of the buffers is used for buffering the patient bias voltage, where as the other is used for filtering the excess noise on the ACCIA_ref voltage (this reference voltage is used in the servo-loop of the ACCIA as shown in Fig. 4.2). Finally, the last building block of the eight-channel EEG readout front-end ASIC is the digital control circuit that generates the necessary digital signals for the readout channels and the analog multiplexer. Figure 4.22 shows the architecture of the digital control circuit of the EEG ASIC. The main function of the digital control circuit can be summarized as follows; the non-overlapping clock generator circuit generates the complementary clock signals at 1 kHz for the chopper switches of the ACCIA. Based on the select chn sampling rate, the sampling frequency of each channel can be selected to be 1 kHz/chn or 2 kHz/chn. The sample signal of the first channel is also an output signal, so that an ADC that is connected to the output of the ASIC can use it to synchronize its sampling instant with the internal sampling of the ASIC. The combinational logic circuit generates the CSF stage clock from the output of the frequency divider. The frequency of the CSF clock is 2 kHz with externally selectable duty cycle of 3.125% or 6.25%. Finally, the digital control circuit controls the gain and the bandwidth switches of the readout channels depending upon 2-bit

68

Biopotential Readout Front-End ASICs

Fig. 4.22 The architecture of the digital control circuit of the eight-channel EEG readout front-end ASIC

Select BW and 3-bit Select Gain digital input signals. Table 4.6 gives the current consumptions and the operating conditions of the each block of the eight-channel EEG readout front-end ASIC.

4.6.2 Measurement of Performance Figure 4.23 shows the gain and the bandwidth plot of the ACCIA. Measurement has been taken after the CSF stage. If neither the chopping nor the CSF stage is active, the gain of the ACCIA is 10 and the LPF cut-off frequency is 16 kHz. If only chopping is activated, the gain of the ACCIA is reduced due to the distortion spikes at the output of the ACCIA. This gain reduction can be calculated from (2.17) as 4% (τ = 1/(2π16 kHz) and fchop = 1 kHz), which matches perfectly with the measured reduction in the gain. After CSF stage is activated, this gain reduction is fully restored since the CSF stage filters the distortion spikes. If Cext2 is 1 µF, the HPF cut-off frequency appears at 0.2 Hz. Figure 4.24 shows the time-domain comparison of the output of the ACCIA, while the CSF stage is active with 3.125% duty-cycle, and while it is disabled. The distortion spikes are successfully filtered by the CSF stage. Similar to the distortion spikes, another test is performed to demonstrate the operation of the CSF stage on the chopping spikes by shorting the inputs of the ACCIA. Figure 4.25 demonstrates that CSF stage can also filter the chopping spikes generated due to the charge injection from the input chopper switches. Figure 4.25 also demonstrates the operation of the servo-loop implemented with OTA1 -Cext1 in Fig. 4.2, whose purpose is to filter the offset of the CBIA. The loop successfully filters the offset of the CBIA, the modulated output offset of the CBIA is only 300 µV, which states that the input referred

4.6 Eight-Channel EEG Readout Front-End

69

Table 4.6 Summary of the building blocks of the eight-channel EEG readout front-end ASIC Readout Channel BWACCIA fchop Av,ACCIA Current Consumption Input Ref. Noise Density NEF

AC Coupled Chopped IA (ACCIA) 20 kHz 1 kHz 10 6.25 µA√ 75 nV/ Hz 9.3

fCSF Duty Cycle (m) Current Consumption

Chopping Spike Filter (CSF) 2 kHz 3.125%, 6.25% 0.4 µA

Programmable Gain Current Consumption

Programmable Gain Stage 200, 300, . . . , 800, 900 0.7 µA and 0.38 µA

3 V gate bias

1-bit digital input

3-bit digital input Fixed Gain Stage and VGA

Channel Buffer Current Consumption

0.8 µA Buffers and Bias Circuit

Output Buffer Current Bias Buffers Bias Circuit

3.6 µA 3 × 0.6 µA 10.7 µA Digital Control Circuit

Clock Frequency

64 kHz Complete ASIC

Total Current Consumption Operating Voltage

92.6 µA 2.7–3.3 V

offset voltage of the CBIA is only 30 µV, thanks to the servo-loop implemented by the OTA1 -Cext1 . Figure 4.26 shows the input referred voltage noise PSD measurement of the ACCIA with and without chopping. The 1/f noise corner frequency of the ACCIA is reduced to 2 Hz, when chopping is activated, otherwise 1/f noise corner frequency is 60 Hz. √ The input referred voltage noise level of the ACCIA is measured to be 75 nV/ Hz. The residual 1/f noise is due to the OTA2 -Cext2 filter in Fig. 4.2, and has negligible effect to the total noise of the ACCIA. The total integrated input referred voltage noise is 0.78 µVrms between 0.5 Hz and 100 Hz, when chopping is

70

Biopotential Readout Front-End ASICs

Fig. 4.23 Gain and bandwidth of the ACCIA of the eight-channel EEG ASIC. The gain of the ACCIA is reduced according to the (2.17) while chopping is active and CSF stage is disabled. After CSF stage is activated (3.125% duty cycle) the gain of the ACCIA is restored

Fig. 4.24 Comparison of the output of the ACCIA for a 20 mVpp sine wave input while CSF stage is active with 3.125% duty-cycle and while it is disabled

active, and 1.23 µVrms , when chopping is disabled. Therefore, the improvement of noise with chopping is more than 35%. All the bias voltages are generated from the reference source current and sink current outputs by using off-chip resistors. Figure 4.27 shows the test of the supply independent bias generator circuit. The supply voltage is changed from 2.7 V to 3.3 V. The voltages generated from the source current output are constant in the whole range of the supply voltage, where as the voltages generated from the sink current output follow the change in the supply voltage. The total supply current of

4.6 Eight-Channel EEG Readout Front-End

71

Fig. 4.25 Comparison of the output of the ACCIA while the inputs are shorted. The CSF stage can completely filter the chopping spikes due to the charge injection from the input chopper switches

Fig. 4.26 Comparison of the measured noise of the ACCIA with and without chopping. Chopping reduces the 1/f noise corner frequency from 60 Hz to 2 Hz

the ASIC is measured to be 95 µA, which only changes less than 2% in the specified supply voltage range. Figure 4.28 shows the output of the ASIC for a common-mode sine wave input of 750 mVpp at 50 Hz, where the channel gain is set to 9000. The CMRR of the readout channels of the ASIC is better than 130 dB at 50 Hz. Finally, Fig. 4.29 shows the variation of the output offset voltage for the each channel of the ASIC. The maximum deviation is less than 10 µV, when referred to the input of the channels. Table 4.7 summarizes the measured performance of the ASIC.

4.6.3 Biological Test Results In order to verify the operation of the EEG ASIC with real EEG signals, a test setup has been prepared. Eight Ag/AgCl cup electrodes are placed on the skull of a subject

72

Biopotential Readout Front-End ASICs

Fig. 4.27 Total supply current of the ASIC, and change of supply current and bias voltages with changing supply voltage

Fig. 4.28 Output of the ASIC for a common-mode input sine wave of 750 mVpp at 50 Hz. Channel gain is 9000 during the measurement

at the locations O1, O2: occipital cortex, P3, P4: parietal cortex, C3, C4: central, F3, F4: frontal cortex in accordance with [12]. These electrodes are connected to the eight channel inputs of the ASIC. The patient bias voltage, which is generated from the on-chip source current and buffered by the on-chip buffer (see Fig. 4.21), is connected to the Gnd electrode located on the top of the subject’s skull aligned with the longitudinal fissure of the brain. The reference electrode is connected to

4.6 Eight-Channel EEG Readout Front-End

73

Fig. 4.29 Deviation of the output offset voltage of the channels of the eight-channel EEG readout front-end ASIC. Maximum deviation is less than 10 µV, when referred to the input of the channels Table 4.7 Performance summary of the eight-channel EEG readout front-end ASIC Performance Summary Voltage Supply

2.7 V–3.3 V

Current Consumption

95 µA

Input Common Mode Range

1.05 V–1.7 V

Electronics Gain Selection (ACCIA Gain = 10)

2000, 3000, . . . , 9000

Continuous Gain Adjustment

via R2

Input Referred Voltage Noise Density

75 nV/sqrt (Hz)

CMRR

>130 dB

HPF Cut-Off Frequency (Cext2 = 1 µF)

0.2 Hz

Input Impedance (signal input)

>500 M

Offset Deviation of the Channels (Input Referred)

<10 µV

Isupply /Vsupply

−110 dB

Maximum Output Load (@ 2 kHz/chn sampling)

50 pF

the common reference input of the ASIC. A microcontroller [59] is employed for controlling the data acquisition and for sampling the multiplexed output of the EEG ASIC. The built-in 12-bit ADC of the MSP430 microcontroller converts the sampled output of the ASIC into digital domain. The gain of the channels are set to 9000, the bandwidth is set to minimum (60 Hz), and the internal channel sampling rate is set to 1 kHz/chn. The sampling time of the ADC is synchronized with the sampling time of the ASIC using the ADC SYNC output of the digital control circuit. Figure 4.30 shows the extracted signals from the electrodes and their STFT, when the subjects eyes are closed. The amplitudes are referred to the input of the

74

Biopotential Readout Front-End ASICs

Fig. 4.30 Extracted EEG signals and their STFT from the electrodes connected to the skull of the subject. The dominant rhythm at locations O1–O2–P3–P4 are in the alpha range

4.7 Comparison with the State-of-the-Art

75

Fig. 4.31 Power–noise performance comparison of the ACCIA with the commercially available micropower IAs () (AD627: [60], INA126: [61], LT1101: [62], INA122: [63], INA321: [64]) and IAs from the literature (♦) (Eatock: [31], Ng: [35], Yen: [25], Martins: [33], Steyaert: [20], Burke: [21], Denison: [36], Harrison: [57]). Constant NEF contours are indicated by dashed lines. The NEF of the commercial IAs are calculated for a −3 dB cut-off frequency of 100 Hz and including the 1/f noise of the IAs

ASIC. The dominant frequency of the signals that are extracted from the electrodes close to the occipital cortex (O1, O2, P3, P4) of the brain are in the alpha range (8–13 Hz) [11].

4.7 Comparison with the State-of-the-Art The NEF factor that is introduced in Sect. 2.4.2 is used for comparing the powernoise performance of the proposed ACCIA architecture with the different IAs from the literature. Figure 4.31 shows the NEF graph, which includes the IAs from , and some commercially available micropower IAs. The ACCIA design of the ExG read√ out front-end ASIC achieves a NEF of 9.2, which is calculated from the 57 nV/ Hz noise level and 11.1 µA current consumption. Similarly, the ACCIA design of the eight-channel EEG readout front-end ASIC achieves a NEF of 9.3, calculated from √ 75 nV/ Hz noise level and 6.25 µA current consumption. The discrepancy with the theoretical NEF value of 4.6 and the measured NEF values is due to the fact that the

76

Biopotential Readout Front-End ASICs

Table 4.8 Comparison of the presented ACCIA architecture with the IFCN standards for digital recording of clinical EEG (Harrison: [57], Denison: [36]) IFCN Standards

Harrison

Denison

ACCIA (ExG)

ACCIA (EEG)

Voltage

–

5V

1.8 V

3V

3V

Current

–

180 nA

1.2 µA

11.1 µA

6.25 µA

Input Ref. Noise (0.5–100 Hz)

0.5 µVrms

1.6 µVrms

0.94 µVrms

0.6 µVrms

0.75 µVrms

CMRR

110 dB

>86 dB

105 dB

>120 dB

>130 dB

Input Impedance

100 M

Larger

>7.5 M

>100 M

>500 M

HPF −3 dB Cut-Off

<0.16 Hz

0.016 Hz

0.5 Hz

0.5 Hz (ext. cap)

0.5 Hz (ext. cap)

Area

–

0.16 mm2

1.4 mm2

0.61 mm2

0.61 mm2

Elec. Offset

–

Rail-to-rail

50 mV

50 mV

50 mV

NEF

–

4.8

4.9

9.2

9.3

current source transistors and the transistors of the gm1 and the gm2 are operating barely in strong inversion. The measured NEF value can be decreased by designing the current source transistors to operate in deep strong inversion at the cost of lower input-output voltage swing. The IA of [34] is not included in the NEF curve, since the noise measurements are given for a DC coupled amplifier and the AC-coupled implementation by using an external capacitor and a resistor will attenuate the input signal that would result in a much lower signal-to-noise ratio than the presented value in [34]. Moreover, on the contrary to the proposal of [34], it is not possible to replace the external capacitor and the resistor with an on-chip capacitor and a transistor operating in the subthreshold region. This will implement a very high source impedance for input chopper switches, which will prevent the settling of the amplifier input node due to the extremely large time constant. There exist two IAs that achieve lower NEF than the proposed ACCIA implementation [36, 57]. Table 4.8 compares the characteristics of the presented ACCIA and the IAs of [36, 57] with the IFCN standards for digital recording of clinical EEG [37], which has the most strict specifications for the biopotential signals. It is clear that the CMRR of the IA of [57] is too low for extracting clean biopotential signals. Additionally, it should be noted that the noise level is also too high for extracting EEG signals. This is due to the fact that the thermal noise level of the amplifier is high, which makes the 1/f noise negligible in the total noise of the amplifier. However, in an attempt to design an amplifier for EEG applications, the thermal noise of the amplifier should be lowered, which, in turn, increases the contribution of the 1/f noise. As a result, the NEF of the amplifier will increase. Hence, the IA of [57] has an increasing NEF for low noise applications, such as EEG acquisition systems. As a consequence, the amplifier of [57] will achieve worse NEF

4.8 Conclusions

77

than the presented ACCIA architecture for applications requiring low-noise and low-bandwidth IAs. On the other hand, the handicap of the IA of [36] is the very low input impedance (7.5 M) due to the usage of large capacitors in the chopped signal path. Although, this input impedance level is still allowed for ECG applications (5 M [58]), it is an order of magnitude less than what is required for the EEG applications (100 M) [37]. The main consequence of the small input impedance will be the lowered CMRR under electrode impedance mismatches. For instance, an impedance mismatch of 1 k will reduce the CMRR of the IA of [36] to 77 dB, where as in the case of 5 k mismatch, the CMRR will be 63 dB. As a result, it can be concluded that the presented ACCIA architecture outperforms the IAs in the literature for biopotential signal acquisition applications.

4.8 Conclusions An IA architecture called AC Coupled Chopped IA, which implements HPF characteristics to the chopper modulation technique is proposed. It achieves high CMRR and low-noise, and dissipates low-power, while filtering the differential DC electrode offset voltage from the biopotential electrodes. This ACCIA is used as a preamplifier in the channels of two different readout front-end ASICS, namely, the single-channel ExG readout front-end ASIC and the eight-channel EEG readout front-end ASIC. The ACCIA implementation for the ExG ASIC achieves more than √ 120 dB CMRR, 57 nV/ Hz input referred voltage noise density, and it is capable of filtering 50 mV differential DC electrode offset between two biomedical electrodes, while consuming 11.1 µA from a single 3 V supply. The ACCIA √ implementation for the EEG ASIC achieves more than 130 dB CMRR, 75 nV/ Hz input referred voltage noise density and it is also capable of filtering 50 mV differential DC electrode offset, while consuming 6.25 µA from a single 3 V supply. The power-noise performance of the ACCIA implementation are compared with the literature. The ACCIA implementation for the ExG ASIC and for the EEG ASIC achieve NEF of 9.2 and 9.3, respectively. Only two IA architectures in the literature achieve lower NEF than the presented ACCIA architecture. Reference [57] achieves NEF of 4.8. However, it has been shown that the low CMRR of this IA, prevents its use for the EEG applications. Moreover, actual NEF of the design would be much worse for an attempt to reduce the noise level of the IA for EEG applications. On the other hand, [36] achieves NEF of 4.9, but the very low input impedance of 7.5 M limits the use of this amplifier. As a consequence, the noise-power performance of the presented ACCIA architecture outperforms the IAs in the literature that are capable of extracting high-quality biopotential signals. In addition to the ACCIA, this Chapter proposes a CSF stage and a programmable gain stage that operates in continuous-time. It has been demonstrated that the CSF stage that follows the ACCIA is capable of filtering both the chopping spikes and distortion spikes of the chopper modulation technique. On the other hand, the programmable gain stage dissipates low-power and implements variable gain and

78

Biopotential Readout Front-End ASICs

Table 4.9 Proposed implementation techniques for the requirements of the biopotential acquisition systems Problem

Solution

Technique

1/f Noise

1/f noise filtering

Common-Mode Interference

High CMRR

ACCIA Architecture (Sect. 4.2)

Differential DC Electrode Offset

AC Coupled Chopped Amplifier

Reduction of CMRR with Electrode Offset

CMRR resistant to differential DC input

Input Stage of Fig. 4.6

Configurability for Different Biopotential Signals

Variable Gain

Programmable Gain Stage (Sect. 4.4)

Long Term Power Autonomy

Low-Power Design

Variable Bandwidth

Combination of the ACCIA, CSF and Programmable Gain Stages

variable bandwidth characteristics. If the ACCIA gain is set to 10, the channel gain of the single-channel ExG readout front-end ASIC can be set to 400, 800, 1550, and 2500 through the VGA. Similarly, the gain of the eight-channel EEG readout frontend ASIC can be selected between 2000 and 9000 with 8 different gain settings. In addition to the low power dissipation, the most important advantage of the programmable gain stage is the continuous time operation, which enables its use both as a programmable gain stage and as an anti-aliasing filter. As a result, this Chapter proposes solutions to the questions raised in Table 2.2 as shown in Table 4.9. Both of the single channel ExG ASIC and the eight-channel EEG ASIC are implemented in 0.5 µm double-poly triple-metal CMOS process. The single channel ExG ASIC has a total current consumption of 20 µA from a 3 V supply, where as the eight-channel EEG readout front-end ASIC consumes 95 µA. In addition to the 8 readout channels, the EEG ASIC also includes a multiplexer that enables a single ADC to sample all the channels of the ASIC. Both of the ASICs include output buffers that enable a sampling rate of 2 kHz/chn for the eight-channel EEG ASIC and 5 kHz for the single-channel ExG ASIC, if the load capacitance is smaller than 50 pF. Therefore, an ADC can sample the outputs of the ASICs. As a conclusion, the combination of the presented readout front-end ASICs with a low-power ADC and a low-power radio will enable the implementation of the portable/wearable fully autonomous biopotential acquisition systems.

Chapter 5

A Complete Biopotential Acquisition ASIC

5.1 Introduction Another power consuming block of an EEG acquisition systems is the ADC. Therefore, the power autonomy of the biopotential acquisition systems can be further improved, if an on-chip low-power ADC is included together with the analog readout front-end. This Chapter describes a complete EEG Acquisition ASIC, where the outputs of the analog readout front-ends can be digitized using the on-chip lowpower ADC. This eliminates the use of an external ADC that not only improves the power dissipation of the EEG acquisition system but also can shrink the system size. Moreover, a new ACCIA architecture is introduced that improves the NEF of the presented ACCIA in Chap. 4 and eliminates the need for external passives for implementing HPF characteristics. Thus, both the power autonomy and the size of the EEG acquisition system can be further improved. In addition to the acquisition mode, the ASIC has impedance measurement and calibration modes. During the impedance measurement mode, the ASIC is configured such that is can measure the impedance of the biopotential electrodes, where as, during the calibration mode the gain mismatch of the readout front-end channels can be calculated. The organization of the Chapter is as follows; Sect. 5.2 presents the architecture and the functional block diagram of the EEG acquisition ASIC. Section 5.3 describes how the bias currents and the voltages for the building blocks of the ASIC are generated. Section 5.4 describes the Class-AB buffer architecture of the ASIC that is used to buffer the output voltage of the front-end channels and the reference voltage of the ADC. Section 5.5 presents the proposed ACCIA architecture that improves the NEF of the ACCIA of Sect. 4.2, and eliminates the need for external passives. Section 5.6 and Sect. 5.7 describes the CSF stage, and the programmable gain stage, respectively, and Sect. 5.8 presents the measured performance of the readout front-end channels. Section 5.9 describes the design of the relaxation oscillator that generates the operating clock of the ADC. Section 5.10 describes the design of the 11-bit SAR-ADC of the ASIC. Section 5.11 describes the impedance measurement and calibration modes of the ASIC. Finally, Sect. 5.14 states the conclusions of this Chapter.

5.2 ASIC Architecture Figure 5.1 shows the architecture of the proposed EEG acquisition ASIC. The main building blocks of the ASIC are: eight readout front-end channels, an 11-bit SAR R.F. Yazıcıo˘glu et al., Biopotential Readout Circuits for Portable Acquisition Systems, © Springer Science + Business Media B.V. 2009

79

Fig. 5.1 Functional block diagram of the EEG Acquisition ASIC

80 A Complete Biopotential Acquisition ASIC

5.3 Bias Generator Circuit

81

ADC, a bias circuit, a 1 MHz relaxation oscillator, an electrode impedance measurement circuit, and a calibration signal generator. The readout front-end channels are responsible for extracting and conditioning the EEG signals from the biopotential electrodes. The preamplifier of a readout channel is an ACCIA, which has a modified servo-loop compared to the ACCIA implementation of Sect. 4.2 for improving the noise-power performance of the ACCIA. The ACCIA is followed by a CSF stage, which includes a HPF with adjustable cut-off frequency. After the CSF stage a programmable gain stage further amplifies the extracted biopotential signals. The output of each channel is buffered and time-multiplexed. Finally, a class-AB buffers the outputs of the channels and drives the input capacitance of the ADC. The ADC of the ASIC is implemented using the SAR-ADC architecture due to its low-power dissipation characteristics. The operating clock of the ADC is generated by the on-chip 1 MHz relaxation oscillator. The operation of the relaxation oscillator is duty cycled such that it generates the 1 MHz clock only when the ADC is asked to convert an analog input signal. The reference voltage of the ADC is generated by the bias circuit, and it is buffered by a class-AB buffer to drive the capacitive DAC of the SAR-ADC. The ASIC is designed for battery powered systems, where the supply voltage changes as the battery discharges. Therefore, the bias generator circuit of the ASIC uses a PTAT voltage generator to generate a temperature and supply independent reference voltage. This reference voltage is used to generate all the bias voltages and currents of the ASIC, as well as the reference voltage of the ADC. Additionally, It should be noted that the patient bias voltage that is used for the grounding of the patient is also generated by the bias generator circuit. The digital control circuit of the ASIC uses a 32 kHz clock input from which the sample signals of the analog multiplexer is generated, and to which the operation of the ADC is synchronized. The sample time of the first channel of the ASIC can be used as a synchronization signal with an external microcontroller. Additionally, the digital control circuit accepts a clock signal with 1 ms pulse duration and 300 s period. This clock is necessary for the operation of the coarse transconductance stage (CGM) of the ACCIA. During this 1 ms pulse time the coarse transconductance stage checks whether the fine transconductance stage (FGM) has reached its limits. If so, the CGM adjusts its output accordingly. However, this slow operation of the CGM can make the start-up of the ACCIA circuit extremely slow. Therefore, the ASIC has a start-up mode, details of which will be described in Sect. 5.5. Finally, the ASIC includes an electrode impedance measurement and calibration modes, which enable the user to measure the impedances of the biopotential electrodes and to calibrate the matching of the readout front-end channels, respectively.

5.3 Bias Generator Circuit The bias generator circuit generates the necessary bias voltages and currents for the building blocks of the EEG acquisition ASIC. The core of the bias generator circuit is a bandgap voltage reference generator. Figure 5.2 shows the schematic of the

82

A Complete Biopotential Acquisition ASIC

Fig. 5.2 Schematic of the bandgap voltage reference generator circuit

bandgap voltage reference generator. The operation of the circuit can be described as follows. The emitter-base voltage of a PNP bipolar transistor (VEB ) can be written as:   IC VEB = Vt × ln (5.1) IS where the saturation current, IS can be expressed as:   Eg IS = D T η exp − kT

(5.2)

The constant D is independent of temperature and η is defined by the doping level [65]. The temperature dependency of the VEB of a PNP bipolar transistor can be found from (5.1) as [51]: ∂VEB VEB − ηVt − Eg /q = ∂T T

(5.3)

In order to compensate the TC of the VEB voltage, a voltage source with opposite TC is necessary so that the summation of this voltage source with VEB cancels the TC. The transistors M1 –M4 of Fig. 5.2 ensure that same emitter current flows through Q1 and Q2 . Therefore, the voltages at the sources of M6 and M7 are same. Then, the emitter current passing through the bipolar transistors can be written as:   VEB1 − VEB2 1 Q2 (5.4) IE,Q1 = IE,Q2 = = Vt ln R1 R1 Q1

5.3 Bias Generator Circuit

83

This emitter current is copied to another branch, where the series combination of a resistor and a PNP bipolar transistor creates the bandgap voltage. The resulting output voltage can be given as:   Q2 R2 VBG = VEB3 + Vt ln R1 Q1

(5.5)

The TC of the output voltage (VBG ) can be written as:   ∂VBG ∂VEB3 R2 k Q2 = + ln ∂T ∂T R1 q Q1

(5.6)

In order to set the TC of the VBG to zero, the TC of the first term, given in (5.3), must cancel the TC of the second term. Setting R1 as 125 k and the ratio between Q1 and Q2 to 10 equates IE,Q1 and IE,Q2 to 475 nA. R2 is set to 1 M for canceling the negative TC of VEB3 . Therefore, the VBG voltage is set to 1.125 V with zero TC at room temperature and 0.15% variation from −40 °C to 80 °C (simulated). The start-up circuit ensures that the circuit does not settle to zero current operating point. On the other hand, the cascode PMOS transistors, makes IE,Q1 and IE,Q2 resistance to the supply voltage changes. Therefore, the generated output voltage is temperature and supply voltage independent. Having the temperature and supply independent voltage reference in hand, all the currents and bias voltages of the ASIC can be generated from this voltage. Figure 5.3 shows the complete schematic of the bias circuit. The bandgap voltage is buffered to a 2.5 M resistor creating 500 nA current through the transistors M1 and M2 . Offchip SMD thick film resistors are preferred instead of on-chip hipo resistors due to their superior TC (100 ppm/°C vs. −1250 ppm/°C). The current through M1 and M2 is used as a temperature independent reference current and all the bias currents are generated from this reference current. Additionally, the bias circuit has a 1 µA current source output such that the necessary DC voltage levels can be generated using off-chip resistors. The reference voltage of the ADC is generated by copying the current through M1 and M2 to another external 4 M SMD resistor. Since both of the external SMD resistors have the same TC, the TC of the ADC reference voltage equals to the TC of the VBG voltage. A capacitor is used in parallel with the 4 M resistor to filter the excessive noise on the reference voltage. The ADC reference is buffered by a class-AB buffer for driving the SAR capacitors of the ADC. The patient bias voltage for the grounding of the patient is also generated by the bias generator circuit. Since the value of this voltage is not critical, it is simply generated by a diode connected nMOS transistor. The total current consumption of the complete bias circuit is 11.05 µA.

Fig. 5.3 Schematic of the bias generator circuit of the EEG Acquisition ASIC

84 A Complete Biopotential Acquisition ASIC

5.4 Class-AB Buffer Architecture

85

Fig. 5.4 Schematic of the class-AB buffer circuit

5.4 Class-AB Buffer Architecture Class-A buffers have poor transient response characteristics due to their limited output current. Therefore, one has to increase the power dissipation of a class-A amplifier beyond what is necessary, in order to meet the requirements of the large signal transient response. On the contrary, the quiescent current of the class-AB buffers are designed considering their small signal response, and the current is boosted-up for the large signal response. The general principle of the class-AB amplifier topologies boosts up either the tail current of the amplifier [66, 67] or the output stage current [68–71]. The class-AB buffers of the EEG acquisition ASIC is implemented using the architecture of [71]. However, the feedback network is modified such that it increases the tail current. Figure 5.4 shows the architecture. The circuit consists of a buffer and a tail current boost circuitry. The buffer circuit is implemented with a classical current mirror OTA, where the quiescent tail current is defined by the pMOS transistor with the size 6 × M1 . On the other hand, the tail current boost circuit is simply implemented as an open-loop differential amplifier. The inputs of the amplifier are connected to the input and the output of the buffer circuit. The transistor sizes of the nMOS load and the pMOS current source is adjusted such that I2 > I1

(5.7)

Thus, the output of the differential amplifier is zero, as long as the output of the buffer is close to the input. Therefore, transistors M3 and M4 are OFF and no current is mirrored to increase tail current of the buffer. In this state, the circuit acts as a simple buffer with constant tail current source. If the difference between the input and the output exceeds the limit given by:   I2 V = n × Vt × ln (5.8) I2 − I1

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A Complete Biopotential Acquisition ASIC

where n is the weak inversion slope factor, then the gate voltage of either M3 or M4 increases, creating a large current that increases the tail current of the input transistors. Therefore, both the bandwidth and the output current drive capability of the buffer circuit increase. An important factor for the design of the tail current boost circuit is the ratio I2 /I1 . This ratio must be large enough so that the offset voltage of the buffer can not falsely activate the tail current boost circuit. On the other hand, increasing the ratio further makes the tail current boost circuit being turned off, while the buffer circuit is still slewing. Hence, the standard deviation of the input referred offset voltage of the buffer, σin,offset , is calculated as 4.3 mV. Therefore, the ratio I2 /I1 is set to 1.5, which sets the turn on voltage of the tail current boost circuit to 40 mV according to (5.8). The designed buffer circuit has a −3 dB cut-off frequency of 2.6 MHz and 230 kHz under no load and with 25.6 pF capacitive load (in addition to the 4 pF compensation capacitor), respectively. The positive and the negative slew rates of the class-AB buffer are 2.5 V/µs and 2.25 V/µs with 25.6 pF load, respectively. The input-output voltage swing of the buffer is between 0.3 V and 2.1 V. The class-AB buffer can settle from 0.3 V to 2.1 V in 2.2 µs with 0.1% precision and from 2.1 V to 0.3 V in 5.1 µs, with 25.6 pF load. The quiescent current consumption of the class-AB buffer circuit is 10 µA and 95% of this current consumption can be duty cycled by using the power switches. Under no load condition, the power-on time of the class-AB buffer is less than 1 µs. This class-AB buffer is used to buffer the ADC reference voltage and the multiplexed readout front-end output.

5.5 ACCIA with Coarse-Fine Servo-Loop 5.5.1 Structure of the ACCIA Defining the noise and the CMRR performance of the channel, and filtering the differential DC electrode offset, the ACCIA is the most important and power consuming building block of a readout front-end channel. The noise-power efficiency calculation of the ACCIA architecture of the previous Chapter is presented in Sect. 4.2.3. The calculation is based on the assumption that an input stage transistor of the CBIA is using only the 1/6 of the total current consumption of the ACCIA. Considering that the NEF of the ACCIA is proportional with the current passing through the input transistors, increasing the ratio of the current passing through the input transistors can improve the NEF of the ACCIA (due to the improved thermal noise). On the other hand, the maximum differential DC electrode offset filtering capability of the ACCIA, which is defined by (4.8), states that higher the current consumption of the transconductance stage, the higher the electrode offset filtering limit of the ACCIA. Therefore, there is a contradiction between the maximum allowed differential DC electrode offset voltage and the noise-power efficiency of the ACCIA architecture of Sect. 4.2.

5.5 ACCIA with Coarse-Fine Servo-Loop

87

Possible solutions for improving the NEF of the ACCIA can be: • Decreasing the current consumption of the gm1 and the gm2 stages of Fig. 4.2. • Increasing the current mirroring ratio of the current mirrors CM1 and CM2 . • Implementing the gm1 and the gm2 stages of Fig. 4.2 with pMOS transistors that replaces the current sources I1,1 and I1,2 in Fig. 4.2. The consequences of these solutions are: • The maximum allowed differential DC electrode offset voltage that can be filtered by the ACCIA decreases. • The contribution of the input pair transistors of the gm1 and the gm2 stages to the total noise of the amplifier increases, which increases NEF. • Input voltage swing of the ACCIA decreases considerably, and the sensitivity of the CMRR to the differential DC electrode offset voltage increases, due to the fact that under DC differential electrode offset, the transistors of the gm stages will be operating with different quiescent operating point. Hence, the CMRRgo term of (3.10) is reduced considerably. As a result, in an attempt to decrease the NEF of the ACCIA, the servo-loop that implements the HPF characteristics to the ACCIA is modified as shown in Fig. 5.5. The gm2 stage of Fig. 4.2 is decomposed into two parts, namely, the coarse transconductance (CGM) and the fine transconductance (FGM) stages. These two transconductance stages simulates the operation of the gm2 stage of Fig. 4.2. The operation of the FGM is same as the gm2 stage of Fig. 4.2, however, FGM stage consumes much less current. Therefore, the FGM can supply enough current difference between its output branches to filter only ±Vfilter,fine differential DC electrode offset voltage, which is defined by: Vfilter,fine =

|Ifine,L − Ifine,R | Ifine × M × R1 = R1 2 2

(5.9)

where M is the ratio of the current mirrors in the FGM. Meanwhile, the CGM checks whether the FGM has reached its limit by using two comparators. If the input of the FGM reaches to the top limit, VH , the thermometer code counter counts up. Else if the input of the FGM stage reaches to the bottom limit, VL , the thermometer code counter counts down. Therefore, in the former case, a current DAC bit is steered to increase IL by IDAC , and decrease IR by IDAC , whereas, in the latter case the opposite steering of the current DAC occurs. The steering of the single-bit current DAC from left to right or from right to left can create 2 × IDAC current difference between its output branches, which can filter ±Vfilter,DACbit differential DC electrode offset voltage that is defined by: Vfilter,DACbit = IDAC × R1

(5.10)

Therefore, the complete CGM can filter ±Vfilter,coarse that is defined by: Vfilter,coarse = mDAC × Vfilter,DACbit where mDAC is the number of bits of the current DAC.

(5.11)

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A Complete Biopotential Acquisition ASIC

Fig. 5.5 The operational principle of the ACCIA with coarse-fine servo-loops that implements HPF characteristics to the CBIA

As a result the maximum differential DC electrode offset that can be filtered by the ACCIA structure can be found by adding (5.9) with (5.11) assuming that the thermometer code counter has reached to its limit:

5.5 ACCIA with Coarse-Fine Servo-Loop

Velec-off ,max = Vfilter,fine + Vfilter,coarse    Ifine × M + mDAC × IDAC × R1 = 2

89

(5.12)

An example behavior of the fine-coarse servo-loop under changing differential DC electrode offset voltage of the biopotential electrodes is described in Fig. 5.6. The main purpose of the servo-loop is to supply the current through R1 due to the differential DC electrode offset voltage, so that no current is supplied by the core CBIA and output is nulled. In the beginning, the CGM stage steers its current output such that the remaining necessary current difference can be adjusted by the FGM stage. As soon as, the remaining necessary current difference falls into this range, the VINT,OUT decreases from VH limit. Therefore, from this moment on the CGM stage sustains its output current difference. Meanwhile, the FGM stage adjusts its output such that (IL − IR ) equals to Velec-off /R1 . Therefore, at this instance, all the necessary current through R1 is supplied by the servo-loop, and the differential DC electrode offset is rejected by the ACCIA. As the electrode offset voltage of the biopotential electrodes drifts, the FGM stage adjusts its output till the point, where VINT,OUT reaches either VH or VL . At this instant, the CGM stage senses this and adjusts its output. Later, the FGM stage adjusts itself to the change in the CGM stage. As a result, all the necessary current through R1 due to the input differential DC electrode offset voltage can be supplied by the fine-coarse servo-loop. An important consideration of the fine-coarse servo-loop design is to prevent the saturation of the FGM stage. Therefore, VH and VL voltages must be selected such that the CGM stage should update its output before the FGM stage saturates. In such a situation, the HPF cut-off frequency of the ACCIA, fHP,ACCIA , is defined by the

Fig. 5.6 Illustration of the fine-coarse servo-loop operation with changing input differential DC electrode offset voltage of the biopotential electrodes

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A Complete Biopotential Acquisition ASIC

FGM stage. Therefore, fHP,ACCIA can be written using (4.4) as: fHP,ACCIA = [gm,fine · M · Av,INT ] × [R2 · A] × fLP,INT

(5.13)

where gm in (4.4) is replaced by Av,INT × gm,fine × M, and R2 is replaced by R2 × A. Av,INT and fLP,INT are the open-loop DC gain and the LPF cut-off frequency of the integrator stage. M and gm,fine are the current mirror ratio of the FGM stage and the transconductance of the input pair transistors, respectively. A is the gain of the second gain stage of the ACCIA.

5.5.2 Coarse Transconductance (CGM) Stage 5.5.2.1 Functional Block Diagram Figure 5.7 shows the implementation of the CGM stage. The counter of the CGM stage is reset after the power-on of the ASIC. This sets the output of the 4-bit binary counter to (1000)2 , which is the mid-level for the counter, and sets half of the current DAC bits to state 1 and other half to state 0. Therefore, IDAC,L equals to IDAC,R just after the reset. The operation of the CGM stage is controlled by three clock signals, compRST, compPOWER, and checkCLK. The comparators of the CGM stage are powered on

Fig. 5.7 Schematic and operation principle of the Coarse Transconductance (CGM) stage

5.5 ACCIA with Coarse-Fine Servo-Loop

91

with the compPOWER. A delay time is introduced between the compPOWER and compRST so that the transistors of the comparators settle to their quiescent operating points before the comparator decision. Together with the compRST, the two comparators check whether the output of the source follower is between VH and VL . If it is below VL or above VH then the output of the bottom or the top comparator goes high, respectively, which makes the counter to count. Meanwhile, a NAND gate and an OR gate check whether the counter has reached its limit, and prevent the transition of the counter from (0000)2 to (1111)2 or from (1111)2 to (0000)2 . The binary-to-thermometer code converter converts the output of the counter to thermometer code for the control of the current DAC bits. A 1-bit increase/decrease in the counter results in 2 × IDAC change for IDAC,L − IDAC,R . Therefore, each bit of the counter can steer enough current to cancel IDAC × R1 of the differential DC electrode offset of the biopotential electrodes. 5.5.2.2 Current DAC Architecture Figure 5.6 gives an example behavior of the fine-coarse servo-loop assuming that the current DAC is implemented using a conventional DAC architecture, where the steering of the DAC is instantaneous. Therefore, after the DAC steers its output, the total current (IL − IR ) is not equal to what is necessary to filter the input differential DC electrode offset voltage, since integrator output is at its limit prior to the steering. Hence, the integrator has to adjust its output so that (IL − IR ) will be set to what is necessary to filter the input differential DC electrode offset voltage. However, due to the large time constant of the integrator stage, an artifact will occur at the output of the ACCIA, when the integrator stage is adjusting its output. Therefore, a conventional DAC architecture is not convenient for the CGM stage. Figure 5.8 shows the proposed architecture of a single bit of the current DAC. The main difference between a conventional DAC and the implemented DAC is the change of the output current. On the contrary to a conventional DAC, the output current of this implementation steers slowly. This is due to the fact that the gates of the transistors, M1 and M2 , are connected to the output of a LPF that is implemented with pMOS transistors operating in OFF state and a load capacitor. Therefore, any fast voltage change at the input of this LPF will be filtered by the time constant of the LPF stage. The OFF state pMOS transistors can be modeled with two PNP bipolar transistors. When the input of the LPF filter switches from the supply voltage to Vcas the load capacitor is discharged by the base-emitter reverse bias leakage current of Q1 and the base-to-body leakage current. On the other hand, when the input switches from Vcas to VDD, the load capacitance is charged only by the base-emitter reverse bias leakage current of Q2 , and the base-to-body leakage is compensated by the base-emitter forward bias current of Q1 . Therefore, the rate of voltage change at the gates of the transistors M1 and M2 can be given as:  Icharge /CnMOS ⇔ input(Vcasp to VDD) ∂Vg1,g2 (5.14) = ∂t (Idischarge + Ibase-to-body )/CnMOS ⇔ input(VDD to Vcasp )

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A Complete Biopotential Acquisition ASIC

Fig. 5.8 Architecture and operating principle of the current DAC that has slowly varying current output

where Icharge and Idischarge are defined by the BE reverse bias leakage of the bipolar transistors. Hence, the discharge of the load capacitance will be faster than the charging due to the fact that the total discharging current of the load capacitance is larger than the charging current by Ibase-to-body . The operation of this current DAC implementation can be described as follows: When Qn changes from 1 to 0, the input of the left LPF switches from Vcasp to supply voltage, and the input of the right LPF switches from supply voltage to Vcasp . Therefore, the gate voltage of the transistors M1 and M2 increases and decreases with slope given in (5.14), respectively. As a result, the current is steered slowly from left to right. The target is to make the time constant of the output current change much smaller than 1/(2πfHP,ACCIA ) so that the artifact of the current DAC is suppressed. Then, the operation of the fine-coarse servo-loop can be illustrated as in Fig. 5.9, which describes that fine-coarse servo-loop can continuously supply the necessary current to filter the DC differential electrode offset voltage of the biopotential electrodes.

5.5.2.3 Latched Comparator The CGM stage uses a static latched comparator as shown in Fig. 5.10 [72]. It consists of a differential input stage, a current mirror, and a regenerative active load.

5.5 ACCIA with Coarse-Fine Servo-Loop

93

Fig. 5.9 Illustration of the fine-coarse servo-loop operation, which uses a current DAC in the CGM stage having a large time-constant while steering its outputs

Fig. 5.10 Comparator schematic of the Coarse Transconductance stage

The signal compPOWER enables or disables the tail current of the input differential stage. Therefore, when compPOWER is low the comparator consumes no current. When compPOWER goes high the differential input voltage creates a current difference between the drain currents of the input pair transistors. This current difference is mirrored to the regenerative active load. During compRST is high, the comparator is in reset mode, and output is set to zero. When the compRST goes low, the active load creates virtually infinite gain, due to the regenerative process. This yields rapid amplification of the signals to the logic levels [72]. The main advantage of this comparator is its low kick-back noise. Since the input differential stage and the regenerative active load is isolated from each other with

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A Complete Biopotential Acquisition ASIC

Fig. 5.11 Schematic of the Fine Transconductance (FGM) stage

the current mirrors, the regeneration process has minimal effect on the inputs of the comparator [73]. The static power consumption of this architecture is not important since the tail current of the input differential stage is duty-cycled, and the power-on time is negligible (1 ms/300 s). Therefore, the average current consumption of this comparator is nearly zero, when it is used in the CGM stage. The implemented comparator consumes 500 nA when it is ON. The start-up time of the comparator is 2.5 µs, and it can resolve 1 mV differential input in less than 1 µs. Therefore, the delay of 62.5 µs between the clock signals of the CGM stage (see Fig. 5.7 for the clock signals of the comparator) is a very relaxed number that assures the proper operation.

5.5.3 Fine Transconductance (FGM) Stage The architecture of the FGM stage is very similar to the architecture of the gm2 stage of Fig. 4.2. Figure 5.11 shows the schematic of the FGM stage. The source follower of the FGM stage has the same size with the source follower of the CGM stage. Therefore, the output of the two source follower stages match. The nMOS differential pair transistors compare the output of the source follower with a reference voltage. Based on the source follower voltage, a current difference, (Ifine,L − Ifine,R ) is created and mirrored to the terminals of R1 of the CBIA. The tail current of the differential pair transistors is 100 nA and the current mirroring ratio between the current mirrors is 2. The differential pair transistors of the FGM stage is designed in deep strong inversion to minimize their noise contribution. The transconductance of the input differential pair transistors is 210 nS.

5.5.4 Integrator Stage The purpose of the integrator stage is to filter the output of the ACCIA such that only the signals below the cut-off frequency of the integrator, fLP,INT , are amplified.

5.5 ACCIA with Coarse-Fine Servo-Loop

95

Fig. 5.12 Schematic of the integrator stage

Therefore, both the CGM and the FGM stages can use the output of the integrator to set their outputs for filtering the differential DC electrode offset of the biopotential electrodes. Figure 5.12 shows the schematic of the integrator stage. The integrator characteristics are implemented using a differential amplifier, two resistors that are implemented with diode connected pMOS transistors operating in subthreshold region as in [74], and two capacitors. The transfer function of the integrator can be written as: Av,INT (s) =

Aopen-loop sRpMOS CLPF Aopen-loop + 1

(5.15)

where Aopen-loop is the open-loop DC gain of the differential amplifier. Hence, the integrator cut-off frequency can be given as: fLP,INT =

1 2πRpMOS CLPF Aopen-loop

(5.16)

The large time constant of the circuit can be reduced for the fast start-up of the circuit, which will be described in the later Sections. The implemented integrator stage has an open-loop DC gain of 77 dB and the total input referred noise is 50 µVrms . The total current consumption of the integrator stage is 50 nA.

5.5.5 Current Balancing IA (CBIA) Architecture The CBIA of the ACCIA is implemented as in Fig. 4.5 with some minor changes for decreasing the power dissipation and further improving the NEF of the ACCIA. Figure 5.13 shows the schematic of the CBIA. One of the main difference of this

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A Complete Biopotential Acquisition ASIC

Fig. 5.13 Schematic of the Current Balancing Instrumentation Amplifier (CBIA) of the ACCIA with fine-coarse servo-loop

CBIA implementation with the CBIA implementation of Fig. 4.5 is the elimination of the CMFB circuit for saving power. Instead, the second gain resistor is used for sensing the common-mode level of the output and this voltage is used to control the current through the transistors ML5 and MR5 . Similar to the previous implementation, the input stage of the CBIA uses the structure shown in Fig. 4.6 so that the CMRR of the ACCIA circuit will be resistant to increasing input DC differential electrode offset voltage of the biopotential electrodes. Table 5.1 shows the dimensions and the operating points of the transistors of the implemented CBIA circuit. The total current consumption of the CBIA circuit is 1.95 µA, and 1.8 µA of it is supplied by the FGM and CGM stages. Therefore, nearly all of the tail current of the CBIA stage can be used to filter the differential DC electrode offset voltage. Another important change of this CBIA implementation is the minimized current consumption of the transistors ML2 and MR2 , so that most of the current is utilized by the input pair transistors for decreasing the noise of the CBIA. The input transistors of the CBIA circuit consumes 1.5 µA of the total supply current. R1 of the CBIA is selected as 50 k so that 1/R1 is smaller than gm,M1 . Therefore, the noise of the CBIA can be minimized as explained in Sect. 4.2.3. R2 is implemented by four pMOS transistors of size 1.2/45. If the gate of the nMOS transistors are connected to 200 mV, the equivalent resistance is set to 2 M, setting the gain of the CBIA to 40. The compensation capacitance of the architecture is 0.7 pF, which sets fLP,CBIA to 40 kHz according to (4.13).

5.5 ACCIA with Coarse-Fine Servo-Loop

97

Table 5.1 Operating points of the transistors in CBIA implementation of Fig. 5.13 Transistors

W/L (µm/µm)

Ids (nA)

gm /Ids (1/V)

Current Balancing IA (CBIA) MR2 , ML2

10/2.5

MR3 , ML3 , MR4 , ML4 MR5 , ML5

150

22.1

8/4

25

21.9

6/200

750

2.8

MI 1 , Mcasp

2/100, 4/4

50

4.6, 18.9

MI 2

4.5/100

150

8.0

MILVL

2/200

25

4.6

MR2

1.2/45 CBIA Input Stage Transistors

MR1 , ML1

1120/7

750

23.4

MRC1 , MLC1

112/4

750

21.8

MRC2 , MLC2

16/128

50

11.1

5.5.6 Gain Stage A separate gain stage is implemented after the CBIA in order to increase the gain of the ACCIA architecture. The main reason behind dividing the gain of the ACCIA into two stages is to eliminate the servo-loop OTA1 -Cext1 and gm1 of Fig. 4.2 that filters the offset voltage of the CBIA. If the second gain stage can be AC coupled to the CBIA, then the offset voltage of the CBIA can be rejected. Since the differential input voltage is modulated by the input chopper, it will not be affected by this AC coupling. Figure 5.14 shows the schematic of the AC coupled gain stage. The voltage gain is defined by the transconductance of the input pair transistors multiplied by the drain-to-source resistance of the diode connected load transistors. Thanks to the minimum number of parallel branches, this architecture consumes minimum current and achieves the maximum bandwidth compared to the other differential gain architectures. The implemented gain stage has a differential gain of 5 and achieves 50 kHz cut-off frequency, while consuming 150 nA. The AC coupling of the gain stage is achieved by a RC filter, where the resistors are implemented with diode connected pMOS transistors operating in subthreshold region as in [74]. The start-up switches are also used in this stage in order to decrease the start-up time.

5.5.7 Implementation of the ACCIA The presented ACCIA architecture is implemented as the preamplifier of the analog readout channels of the EEG acquisition ASIC as shown in Fig. 5.1. fHP,ACCIA of

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A Complete Biopotential Acquisition ASIC

Fig. 5.14 Schematic of the gain stage of the ACCIA implementation

the ACCIA can be calculated by combining (5.13), (5.15) and (5.16) as: fHP,ACCIA =

Mgm,fine R2 A 4.2 = 2πRpMOS CLPF 2πRpMOS CLPF

(5.17)

Since it is not possible to reliably set the value of the RpMOS , on-chip digital trimming of the RpMOS is implemented via changing the number of series and/or parallel transistors. The aim is to set fHP,ACCIA lower than 0.5 Hz so that the back-end stages can effectively set it to the generally desired frequency 0.5 Hz for EEG applications. The chopping frequency of the ACCIA is selected considering the bandwidth of the CBIA and the differential gain stage. The bandwidth of the CBIA and the gain stage combination is simulated as 28 kHz, and the 1/f noise corner appears at 280 Hz. Therefore, the chopping frequency is selected as 2 kHz, so that Sin,total of the ACCIA will be only 1.1 × S0 according to (2.11), where S0 is the input referred thermal noise PSD of the ACCIA. This translates into only 6% increase of the input referred voltage noise from the thermal noise level of the ACCIA. Another important consideration is setting the VH and VL limits of the CGM stage, so that the FGM stage operates in its linear transconductance range, which is designed as ±4 mV. At 4 mV differential input, the current difference between the input pair transistors of the FGM stage is 80 nA. Since, the current mirror ratio is 2, 80 nA current difference in the differential pair, results in (Ifine,L − Ifine,R ) of 160 nA. Therefore, the output current difference of the FGM stage is sufficient to filter ±4 mV of the input DC differential electrode offset voltage of the biopotential electrodes (Refer to (5.9)). The reference voltage of the FGM stage is selected as 1.8 V, and VH and VL are set to 2.2 V and 1.4 V, respectively. This means that as soon as the FGM is set to filter ±4 mV differential electrode offset voltage, the CGM stage updates its output, which supplies enough current difference to filter ±5 mV differential electrode offset voltage (Refer to (5.10)). Therefore, as the CGM stage changes its output, the FGM stage is set to filter the remaining ∓1 mV of the differential DC electrode offset voltage.

5.5 ACCIA with Coarse-Fine Servo-Loop

99

Fig. 5.15 Circuit configuration for the fast start-up of the ACCIA

As a result, considering the fine-coarse operation of the servo-loop, the maximum allowed differential DC electrode offset voltage is set to ±45 mV, where ±40 mV can be filtered by the CGM and ±5 mV can be filtered by the FGM.

5.5.8 Fast Start-Up of the ACCIA An important concern for the ACCIA is the start-up. After the power-on of the ASIC, the counter of the CGM stage is set to the mid-range so that (IDAC,L − IDAC,R ) of the current DAC in Fig. 5.5 is zero. For a worst case scenario, the input DC differential offset voltage of the electrodes can be ±45 mV, which means the counter of the CGM stage has to count up/down to 1111/0000. Considering the timing of the CGM stage as shown in Fig. 5.7, this will take more than 40 minutes for the ACCIA to start extracting the EEG signals. In order to reduce the waiting time before starting to extract the biopotential signals, the ACCIA can be set to fast START UP mode after the power-on of the ASIC. Figure 5.15 describes the circuit configuration for the fast START UP of the ACCIA. In this mode, following changes occur in the architecture of the ACCIA: • The transition of the current DAC of the CGM stage is fast, since the pMOS OFF transistors in Fig. 5.8 are turned ON. • The subthreshold transistors of the integrator stage in Fig. 5.12 are bypassed by the switches, and the input of the integrator stage is disconnected from the output of the ACCIA and connected to the Voutp,START and Voutn,START outputs of the

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A Complete Biopotential Acquisition ASIC

CBIA. The CINT of the integrator stage and the output resistance of the nodes Voutp,START and Voutn,START set the dominant pole and ensures stability. • The subthreshold transistors of the gain stage in Fig. 5.14 are shorted by switches. Therefore, all the high impedance nodes of the ACCIA architecture are shorted to the low-impedance nodes by switches. As a consequence, the steering of the DAC can be fast, since the FGM stage can immediately adjust its output to the change of the CGM stage. Therefore, the TCGM of the CGM stage in Fig. 5.7 can be decreased down to 10 ms, which improves the worst case start-up time of the ACCIA from 40 minutes to less than 100 ms.

5.5.9 Power-Noise Performance of the ACCIA The main reason for splitting the servo-loop of the ACCIA as fine and coarse servoloops is to improve the power-noise performance. Figure 5.16 shows the equivalent circuit for the input referred noise calculation of the ACCIA with the coarse-fine servo-loop. Using this circuit the total input referred voltage noise PSD can be written as: v2in,ACCIA = v2in,CBIA + + v2in,FGM

v2in,GS A2v,CBIA

  2 gm,I DAC + mDAC v2in,DACbit g12

(M × gm,fine )2 g12

+ v2in,LPF

A2v,CBIA

1 × A2v,GS

(5.18)

where mDAC is the number of bits of the current DAC of the CGM stage, gm,IDAC is the transconductance of the current source of the each bit of the current DAC, and gm,fine is the transconductance of the differential pair of the FGM stage. The values of Av,CBIA , Av,GS , M, mDAC , g1 , gm,IDAC , and gm,fine are 40, 5, 2, 16, 20 µS, 460 nS,

Fig. 5.16 Equivalent circuit for calculating the noise of the ACCIA with fine-coarse servo-loop

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101

and 210 nS, respectively. Therefore, the total input referred voltage noise PSD of the ACCIA can be approximated as: v2in,ACCIA ∼ = v2in,CBIA,thermal

(5.19)

where v2in,CBIA,thermal is the thermal noise component of v2in,CBIA . It is important to note that although the FGM and the CGM stages are outside the choppers, i.e. their 1/f noise will not be eliminated by the chopper modulation technique, the noise components v2in,DACbit and v2in,FGM will be negligible, when they are referred to the input of the ACCIA. This is due to the fact that gm,fine and gm,DACbit are much smaller than g1 . In addition, the size of the current source transistors of the current DAC are maximized. The v2in,CBIA,thermal of the CBIA can be calculated from (4.15), which results a NEF of (4.21). Therefore, the NEF formula of the ACCIA with the coarse-fine servo-loop is same with the NEF formula of the ACCIA of Sect. 4.2 and can be expressed as:    n 1 2Itot NEF = + (5.20) gm,M1 Vt 2 2 Up to this point everything looks similar to the ACCIA of Sect. 4.2. Knowing that M1 operates in weak inversion, the transconductance, gm,M1 , can be written as Ids /(nVt ) and Itot can be calculated by adding the current consumption of the building blocks. The current consumption of the FGM, CGM, gain stage, integrator, and CBIA are 137.5 nA, 37.5 nA, 150 nA, 50 nA and 1.95 µA, respectively. (The current consumption of the current DAC is included in the CBIA stage current consumption.) Considering that current passing through an input transistor of the CBIA is 750 nA, then Ids of the CBIA can be defined as 1/3 of the total ACCIA current. This yields:    n 1 + = 3.25 (5.21) NEF = 6n 2 2 Hence the minimum achievable NEF of the ACCIA with coarse-fine servo-loop is improved compared to the ACCIA of Sect. 4.2, where the improvement is approximately equivalent to 2 times reduction in the current consumption at the same noise level. As a summary, the main advantage of the coarse-fine servo-loop of the ACCIA is that the tail current of the CBIA can be more efficiently used for filtering the electrode offset voltage. Therefore, less current is necessary for the building blocks that implements HPF characteristics to the CBIA. Hence, the NEF can be considerably improved compared to the NEF of the ACCIA of Sect. 4.2.

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Fig. 5.17 Input referred voltage noise density measurement of the ACCIA with coarse-fine servo-loop

5.5.10 Measurement of Performance Figure 5.17 shows the measured input referred voltage noise density √ of the ACCIA with coarse-fine servo-loop. The thermal noise level is 55 nVrms / Hz and 1/f noise corner frequency appears at 4 Hz. The chopper modulation technique improves the corner frequency of the 1/f noise from 80 Hz down to 4 Hz. The residual 1/f noise is due to the unchopped FGM and CGM stages. Figure 5.18 shows the measured transfer function of the ACCIA. The gain of the IA is slightly higher than the design value of 200. This can be expected since the gain of the IA is defined by the ratio of a hipo resistor and the resistance implemented by pMOS transistors operating in linear region. The in-band gain of the ACCIA is 240 and the HPF cut-off frequency appears at 0.1 Hz which is set by the FGM stage. Figure 5.19 shows the CMRR measurement of the ACCIA. The CMRR is higher than 120 dB up to 1 kHz. Therefore, the chopping successfully increases the CMRR of the circuit. Figure 5.20 demonstrates the operation of the coarse-fine transconductance during the START UP mode as described in Sect. 5.5.8. A 20 mVpp triangular wave at 30 mHz is given as a differential input to the circuit, and the VINT,OUT node in Fig. 5.15 is monitored. As soon as the VINT,OUT reaches the upper or the lower limit, the current DAC updates its output setting VINT,OUT between VH and VL . Hence, the CGM stage can successfully adjust its output and prevent the saturation of the FGM stage. Although the DAC transition is FAST during the START UP mode of the ACCIA, it should be SLOW during the normal operation of the ACCIA so that the steering of the DAC does not create any artifact at the output. Figure 5.21 shows the measured

5.5 ACCIA with Coarse-Fine Servo-Loop

103

Fig. 5.18 The voltage gain measurement of the ACCIA with coarse-fine servo-loop

Fig. 5.19 CMRR measurement of the ACCIA with coarse-fine servo-loop

output current of a single current DAC bit, when it is steering from left to right. The steering of the output current is realized in two phases, phase1 and phase2 , as described in Sect. 5.5.2.2. Phase1 is due to the discharge of the gate M1 from VDD to Vcasp and phase2 is the due to the charging of the gate of M2 from Vcasp to VDD (refer to Fig. 5.8). Although, phase1 is faster than phase2 , it is still much lower than 1/(2πfHP,ACCIA ). Therefore, the artifacts of at the output of the ACCIA due to the steering of the DAC is minimized as it will be demonstrated in Sect. 5.8. An important consideration for the biopotential instrumentation amplifiers is the input impedance since the mismatch between the electrode impedances can reduce

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Fig. 5.20 The operation of the fine-coarse transconductance stage during the START UP mode of the ACCIA. The differential input to the circuit is a 20 mVpp differential triangular wave at 30 mHz

Fig. 5.21 Steering of a single-bit of the current DAC

5.5 ACCIA with Coarse-Fine Servo-Loop

105

Fig. 5.22 Input impedance of the ACCIA with coarse-fine servo-loop and the input impedance of the reference input of the EEG acquisition ASIC

the CMRR (refer to (2.3) for detailed description). Figure 5.22 shows the input impedance measurement of the presented ACCIA with coarse-fine servo-loop. The measured input impedance is larger than 1 G indicating that even if there is a 10 k mismatch between the electrode impedances, the CMRR of the readout will be still larger than 100 dB. The same figure also shows the measurement of the input impedance, when eight ACCIA shares an input terminal as a reference input implementation for the eight channel acquisition system (refer to Fig. 5.1). The measured impedance of this input is close to 200 M, which is nearly eight times less than the impedance of a single input. The summary of the measured performance of the ACCIA with coarse-fine servo-loop is given in Table 5.2.

5.5.11 Comparison with State-of-the-Art Table 5.3 compares the performance of the proposed ACCIA with fine-coarse servo-loop with the state-of-the-art for EEG acquisition and with the IFCN standards. The proposed ACCIA is the only IA meeting the requirements of the IFCN standards, except for a slightly elevated total input referred noise. On the other hand, the total integrated input referred noise of the ACCIA is 0.57 µVrms between the frequencies 0.5 Hz and 100 Hz, while consuming 2.3 µA, which translates into the lowest NEF in the literature. It is important to note that the ACCIA with the modified

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Table 5.2 Performance Summary of the ACCIA with coarse-fine servo-loop Performance Summary Voltage Supply Current Consumption CMRR Voltage Gain Input Referred Voltage Noise (0.5 Hz–100 Hz) HPF Cut-Off Frequency Input Impedance Input CM Range Maximum Allowed Electrode Offset Area Noise-Efficiency Factor (NEF)

2.7 V–3.3 V 2.3 µA >120 dB 240 0.57 µVrms 0.1 Hz 1 G  17 pF 0.85 V–1.8 V ±45 mV 0.45 mm2 4.1

Table 5.3 Comparison of the proposed ACCIA with fine-coarse servo-loop to the state-of-the-art for EEG acquisition. The equivalent −3 dB bandwidth for NEF calculation is 64 Hz (Denison: [36], Harrison: [57], IFCN Standards: [37]) IFCN Standard

Harrison

Denison

ACCIA (ExG)

ACCIA with CoarseFine Servo-Loop

Voltage

–

5V

1.8 V

3V

3V

Current

–

180 nA

1.2 µA

11.1 µA

2.3 µA

Input Ref. Noise (0.5–100 Hz)

<0.5 µVrms

1.6 µVrms

0.94 µVrms

0.6 µVrms

0.57 µVrms

CMRR

>110 dB

>86 dB

105 dB

>120 dB

>120 dB

Input Impedance

>100 M

Large

>7.5 M

>100 M

>1 G

HPF −3 dB Cut-Off

<0.16 Hz

0.016 Hz

0.5 Hz

0.5 Hz (ext. cap)

0.1 Hz

Area

–

0.16 mm2

1.4 mm2

0.61 mm2

0.45 mm2

Elec. Offset

–

Rail-to-rail

50 mV

50 mV

45 mV

NEF

–

4.8

4.9

9.2

4.1

HPF achieves nearly two orders of magnitude higher input impedance compared to a recently proposed IA using chopper modulation [36].

5.6 Chopping Spike Filter A CSF stage for the each of the two outputs of the ACCIA is used in order to filter both the chopping and the distortion spikes at the output of the ACCIA (refer to Sects. 2.5.2 and 2.5.3). Figure 5.23 shows the schematic of a CSF stage. In addition to the T&H, a HPF is used before the CSF stage. Although the slow DAC implementation minimizes the artifact at the output of the ACCIA, which occurs due to

5.7 Low-Power Programmable Gain Stage

107

Fig. 5.23 Schematic of the CSF stage of the EEG Acquisition ASIC. A CSF stage is connected to the each output of the ACCIA

the steering of the current DAC, this HPF filters the residual artifact at the output of the ACCIA. If the difference between vdc,lvl and vhpf is set to 300 mV, the HPF cut-off frequency appears at 0.5 Hz. The CSF stage operates at 4 kHz, which is twice the chopping frequency of the ACCIA, and the total current consumption of the two CSF stages is 200 nA. Just before the chopping switches change their state, the switches of the CSF stages are opened, and the spike free signal is held on the capacitor CH . After the spikes settle, the switch is closed, and the output of the CSF stage follows its input. The duty cycle of the hold time is 6.25% (15.625 µs), which minimizes the effect of the T&H operation on the output noise of the ACCIA (refer to Fig. 4.8). The efficiency of the CSF stage on filtering the distortion spikes can be calculated from the step response of a two pole system, where the first pole is the pole of the CBIA at 40 kHz, and the second pole is the pole of the gain stage at 50 kHz. In order to simply the calculations, the step response of a two pole system is used, where both poles are assumed to be at 40 kHz. Therefore, the step response of the CBIA plus the gain stage chain can be given as:     t −t/τ (5.22) e VOUT,ACCIA (t) = VOUT 1 − 1 + τ where τ = 1/(2π40 kHz) and VOUT is the final value. From the above formula, it can be calculated that after the switch of the CSF stage is closed, the output of the ACCIA would already reach the 99% of the final value in 15.625 µs. Therefore, the distortion spikes can be efficiently filtered.

5.7 Low-Power Programmable Gain Stage 5.7.0.1 Implementation The programmable gain stage of each channel of the EEG acquisition ASIC consists of a variable gain amplifier and a LPF with digitally selectable cut-off frequency. The VGA serves as the final gain stage of the channel, and also sets the first pole

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Fig. 5.24 Schematic of the programmable gain stage of the EEG acquisition ASIC. The gain and the bandwidth of the stage can be set through switches SBW and SG

of the low-pass filter characteristics of the channel, where as, the LPF stage sets the second pole of the low-pass filter characteristics. Figure 5.24 shows the implementation of the low-power programmable gain stage. The VGA is implemented using an architecture similar to [57]. The variable gain characteristics is introduced to the architecture using switches SG0 and SG1 , and the source follower stages. When the capacitors C3 and C4 are connected to the output of the source followers their effective value is canceled and the gain of the VGA increases. Else they are connected in parallel with the capacitor C2 , and the gain of the VGA stage decreases. The purpose of the source follower stages are similar to the source follower stages of Sect. 4.4. In addition to the gain adjustment, the VGA sets the first pole of the LPF characteristics of the channel and the pole frequency can be selected by changing the load capacitance of the OTAVGA using the SBW switches. The architecture of the OTAVGA is presented in the Appendix. The gain can be set to 50, 25, and 16.7 using the SG switches that sets the gain of the channel to 12000, 6000, and 4000, respectively. (The gain of the ACCIA is measured as 240.) On the other hand, the LPF cut-off frequency can be calculated by using the formula: fLP,VGA =

gm,VGA Av,VGA × CL,VGA

(5.23)

The transconductance of the OTAVGA is 290 nS. Therefore, the LPF cut-off frequency of the VGA can be set to, (70 Hz, 105 Hz, 210 Hz), (130 Hz, 193 Hz, 377 Hz), and (206 Hz, 302 Hz, 575 Hz) for gain settings of 50, 25, and 16.7, respectively. The GM stage is implemented using a buffer connected current mirror OTA, where the input stage has a voltage controlled source degeneration resistance for improving the linear transconductance range of the OTA as proposed in [75] (re-

5.8 Readout Front-End Channel Test Results

109

Fig. 5.25 Gain and bandwidth measurements of a readout front-end channel of the EEG ASIC. The gain of the stage can be selected through the SG of the VGA and the LPF cut-off frequency can be selected through the SBW switches

fer to Appendix for the schematic of the buffer connected transconductance stage). Therefore, this stage acts as a LPF with unity gain, and the LPF cut-off frequency is defined as gm,GM /CL,GM , where CL,GM is the load capacitance of the GM stage. The transconductance of the GM stage is 9.7 nS, therefore the cut-off frequency can be set to 316 Hz, 180 Hz, 126 Hz, and 100 Hz by changing the load capacitance through SBW switches. As a result, the gain of the low-power programmable gain stage can be set by the VGA, and the second order LPF characteristics can be configured by selecting the load capacitances.

5.8 Readout Front-End Channel Test Results Figure 5.25 shows the gain-bandwidth measurements of a readout front-end channel of the EEG Acquisition ASIC. The gain of the channel can be selected by changing the configuration of the SG switches, and the bandwidth of the channel can be selected through the SBW switches of programmable gain stage of the channel. The total gain of the channel can be selected as 4000, 6000, or 12000. The adjustable HPF of the CSF stage sets the HPF cut-off frequency to 0.5 Hz. Figure 5.26 shows the residual artifact at the output of a channel generated by the steering of a single current DAC bit of the ACCIA with coarse-fine servo-loop.

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Fig. 5.26 Residual artifact at the output of a channel for a single bit change in the current DAC of the ACCIA with coarse-fine servo-loop

The artifact is visible only during the phase1 of the current DAC steering. The input referred amplitude of the residual artifact is less than 5 µV, and it is clear from the measurement that the frequency components of the artifact is much less than the minimum frequency of the EEG signals (0.5 Hz).

5.9 Square Wave Relaxation Oscillator 5.9.0.1 Implementation The EEG acquisition ASIC includes a square-wave relaxation oscillator, [76], that generates the 1 MHz clock of the ADC, Fig. 5.27. The operation of the oscillator can be described as follows: When the RST signal is high, outputs of the comparators are set to 0, which set both inputs of the RS Latch to 0. The RST input of the RS latch initializes Q1 and Q2 to 1 and 0, respectively. The operation of the relaxation oscillator starts, when the RST signal goes low. Initially, Ic starts to charge COSC1 , and when V1 reaches Vthreshold , the output of the top comparator switches to 1, setting the R input of the RS latch to 1. Therefore, Q1 and Q2 are set to 0 and 1, respectively. Synchronously, COSC1 is connected to ground and Ic starts to charge COSC2 . When V2 reaches Vthreshold , this time S input of the RS latch is exerted, toggling the states of Q1 and Q2 . As a result, the CLK output of the circuit oscillates with frequency: fOSC =

Ic 2COSC Vthreshold

(5.24)

5.9 Square Wave Relaxation Oscillator

111

Fig. 5.27 Schematic of the square wave relaxation oscillator

The square-wave relaxation oscillator uses two continuous-time comparators with regenerative active loads, Fig. 5.28. A comparator consists of a core part and a level converter. The regenerative load of the core part consists of four equal sized transistors in order to minimize the hysteresis of the comparator [77]. The level converter part amplifies the differential output of the core comparator to supply rails. It should be noted that the level converter does not consume any current, when the output of the comparator is low. Therefore, the total current consumption is 3 µA, when output is low, and increases to 7.25 µA, when output is high. The comparators of the square-wave relaxation oscillator only goes high, when V1 or V2 exceeds Vthreshold . Since the time that the output stays above Vthreshold equals to the delay time of the comparator, which is 40 ns, the increased current consumption of the comparator is negligible. The main consideration during the design of the relaxation oscillator is the jitter of the output clock signal. Due to this jitter the sampling instant of the input signal can be “wrong”, which is equivalent to a decrease in the ADC’s resolution. If we suppose that a full-scale sine wave input to a N -bit ADC is 2(N −1) sin(2πfsignal t), the signal will be most sensitive to jitter, when its is crossing the zero level. The

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Fig. 5.28 Schematic of a comparator of the square-wave relaxation oscillator

maximum allowed peak-to-peak jitter so that the sampled signal is still in ±1 LSB range is the inverse of the slope of the full-scale sine wave at zero crossing. Therefore, the value of the RMS jitter can be calculated by dividing the maximum allowed peak-to-peak jitter with 6 (assuming peak-to-peak jitter equals to 6σ ) Tjitter,RMS =

1 1 × 6 2(N −1) × 2πfsignal

(5.25)

Limiting the accuracy of the sampling instant to ±0.2 LSB necessitates that the total RMS jitter of the ADC clock must be 1/5 of (5.25). Therefore, an 11-bit ADC with a maximum sine wave input frequency of 500 Hz (assuming 1 kHz/chn sampling rate) requires 1 MHz clock with Tjitter,RMS smaller than 10 ns. The jitter of the square-wave relaxation oscillator can be calculated from [78]: 

σjitter,RMS TOSC

 =α·

√

 1.5 ·

Svn,thres (1/td,tot ) Vthreshold

(5.26)

where α is a constant, Svn,thres is the total voltage noise PSD of the threshold voltage, and td,tot is the total delay time of the oscillator (refer to [78] for detailed descriptions). However, a more precise way of estimating the jitter of the oscillator is to use the Virtuoso Spectre Circuit Simulator XL (formerly Virtuoso Spectre RF Simulation) [79]. The RMS jitter of the square-wave relaxation oscillator is estimated to be 6 ns from 1 kHz to 1 MHz bandwidth, which is smaller than 10 ns for ±0.2 LSB accuracy of the sampling instant. When the square-wave relaxation oscillator is constantly ON, it consumes 8.5 µA static and 6.75 µA dynamic current, where the dynamic current consumption is mostly dominated by the non-overlapping clock generator. However, even in the worst case the operation of the oscillator will be duty-cycled with 50% ON time, reducing the equivalent current consumption of the oscillator block to 7.625 µA.

5.10 Analog-to-Digital Converter

113

Fig. 5.29 Output of the square-wave relaxation oscillator

5.9.0.2 Test Results Figure 5.29 shows the measurement of the square wave relaxation oscillator circuit. The oscillator is turned ON with the CONVERT signal. The start-up time of the oscillator is nearly 2 µs and the oscillation frequency is 1.05 MHz.

5.10 Analog-to-Digital Converter An acquisition ASIC requires an analog-to-digital converter for digitizing the multiplexed analog outputs of the readout front-end channels. A successive approximation ADC (SAR-ADC) architecture is selected due to its superior power dissipation characteristics compared to other architectures [80]. Therefore, the EEG ASIC includes an 11-bit SAR-ADC that can be operated at a maximum sampling rate of 25 kHz and 19 kHz, when using the parallel and the serial outputs of the ADC, respectively.

5.10.1 Basic Operation Principle Figure 5.30 illustrates the operation principle of a N -bit SAR-ADC [81, 82]. Before the beginning of the successive approximation algorithm, the input voltage is sampled by a S&H circuit. All the capacitive DAC switches are connected to ground, and the RSTDAC switch is closed. Therefore, the total charge of the capacitive DAC is initialized to zero. Later the reset switches are opened and the successive approximation algorithm starts. The switch SN −1 is connected to VH by the SAR register as the first iteration

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Fig. 5.30 Operation principle of a N -bit SAR-ADC

to the input voltage, which sets the voltage at node Vcomp to VH /2. The sign of the voltage difference between VIN and Vcomp is detected by the comparator, and based on the result either the switch SN −1 is left unchanged or it is connected to ground. Next, the switch SN −2 is left unchanged or it is connected to ground. Next, the switch SN −2 is connected to VH , and this iteration continues down to the last bit. Hence, based on the configuration of the switches, the voltage at node Vcomp can be written as: Vcomp = VH

SN −1 2N −1 + · · · + S1 21 + S0 20 2N

(5.27)

After the decision of the last bit, the conversion of the N -bit ADC is completed. As a result, an N -bit SAR ADC needs N iterations to finish its conversion.

5.10.2 Architecture Figure 5.31 shows the architecture of the 11-bit SAR-ADC of the EEG acquisition ASIC. The structure of the ADC is symmetric in order to reduce the effects of charge injection from the switches and the mismatch of the parasitic capacitances. The digital input signals to the ADC are the Convert, CLK (1 MHz OSC) , and RST. The RST signal sets the ADC to its initial state (capacitive DAC is discharged, SAR and digital logic are set to their initial states), the CLK (1 MHz OSC) is the output of the square wave relaxation oscillator of Sect. 5.9, and the Convert signal is generated by the digital control circuit of the EEG ASIC. The Convert signal is also used to generate the Sample signal of the analog output multiplexer. Therefore, the convert signal and the switching of the analog multiplexer of the channels are synchronized. The square wave relaxation oscillator of the system is turned ON as the Convert signal goes high and supplies the necessary clock signal for the operation of the

5.10 Analog-to-Digital Converter

115

Fig. 5.31 Architecture and timing diagram of the 11-bit SAR-ADC of the EEG Acquisition ASIC

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A Complete Biopotential Acquisition ASIC

SAR-ADC. The first phase of the ADC conversion includes the auto-zero phase of the preamplifier and the sampling of the input voltage. The auto-zero phase of the preamplifier samples the offset of each stage of the preamplifier, and subtracts it from the output during the amplification phase (further details will be presented in the following Sections). It should be noted that the preamplifiers are powered ON before the auto-zero phase starts (PW goes high), so that they can settle to their quiescent operating points. Meanwhile, the sampling of the input signal is performed with the signals BTM and SMP using the bottom plate sampling technique [83], in order to minimize the voltage dependent charge injection from the input switch to the sampling capacitor CH . After the Convert signal goes high, the output buffer of the analog readout front-end of the EEG ASIC is turned ON, and it charges the capacitor CH with the output voltage of a readout channel. The sampling of the input voltage occurs with the opening of the BTM switch. The time reserved for the settling of the class-AB buffer of the readout front-end is approximately 13 µs. Later, the SMP switches are opened. Since the bottom plate of the sampling capacitor CH is not connected to the ground at this instant, there will not be any charge injection from the SMP switch to the hold capacitor CH . Therefore, the size of the SMP switch of the input signal can be increased to decrease its resistance, where as the sizes of the BTM switch, and the SMP switch of the capacitive DAC can be minimized to decrease the charge injection. After the auto-zero of the preamplifier, the class-AB buffer of the readout frontend is turned OFF and the class-AB buffer of the ADC reference voltage is turned ON, and settles to 2 V, before the bit-cycle of the ADC starts. During the bit-cycling phase, the MSB bit of the ADC is decided first by connecting the MSB capacitor of the capacitive DAC to the reference voltage and comparing the DAC voltage with the input voltage. Initially, the first 6-bits of the ADC are decided by iterating the mainDAC switches and comparing the DAC output voltage with the input voltage. During the decision of the 6 MSB bits, the sub-DAC is connected to ground (RST subDAC is high) to prevent the loading of the main-DAC. After the bits of the main-DAC are decided, RST subDAC goes low and the final 5-bits of the ADC are decided. The bit-cycling scheme of this implementation uses the self-timed bit-cycling scheme introduced in [84], and later used by [85, 86]. Figure 5.32 demonstrates the advantage of the self-timed bit cycling over the conventional bit-cycling. The DAC bits of the conventional bit-cycling scheme are always updated with fixed intervals. On the other had, the self-timed bit-cycling scheme checks whether the output latch of the ADC is resolved. If so, the next DAC bit is immediately switched to the reference voltage to decide the next bit. This means that the residual time from the previous bit is borrowed for an extra settling time of the preamplifier stage. Therefore, a critical decision (for instance when the input voltage is close to the MSB bit levels) can utilize more settling time. Knowing that no successive critical decisions occur for the MSB bits of the SAR-ADC, the settling time can be nearly doubled for the critical decisions.

5.10 Analog-to-Digital Converter

117

Fig. 5.32 Comparison of the conventional and self-timed bit-cycling schemes

Fig. 5.33 Architecture of the 11-bit capacitive DAC that consists of a 6-bit main-DAC and a 5-bit sub-DAC

5.10.3 Capacitive DAC Implementation A common technique that is used to reduce the size of the capacitive DAC is to divide the DAC into two parts as a main-DAC and a sub-DAC [87]. Figure 5.33 shows the architecture of the 11-bit capacitive DAC, which consists of a 6-bit mainDAC and a 5-bit sub-DAC. The voltage generated on the sub-DAC will be divided by the capacitor divider implemented by the coupling capacitor, Cc , and the main-DAC. Hence, the equivalent effect of having an 11-bit DAC is created at the output [88]. The capacitive DAC is implemented using the poly–poly capacitors due to their superior matching characteristics. The sizing of the capacitors are determined by the matching. The mismatch between the capacitors of the DAC affects the transition voltages of the ADC bits. The DNL of the ADC is the difference between the actual width of a code and a LSB voltage. Figure 5.34 describes the worst case scenario for the DNL error of the ADC. In an ideal DAC, the output voltage of the DAC

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A Complete Biopotential Acquisition ASIC

Fig. 5.34 The capacitance mismatch scenario for the largest DNL

should change by a single LSB voltage, when the DAC configuration changes from Fig. 5.34(a) to Fig. 5.34(b). However, due to the mismatch of the MSB capacitance with respect to the rest of the DAC capacitance, a DNL error will be generated. It can be found that, in order to limit the DNL error to 0.1 LSB, the following equation must hold for the MSB capacitor:   C 0.1 3×σ = N −1 (5.28) C MSB 2 which can be written for the unit capacitance, C0 , as:   0.1 C = 3×σ C C0 2 N−1 2

(5.29)

Therefore, it can be calculated that 150 fF is sufficient for an 11-bit SAR-ADC to achieve 0.1 LSB DNL error. The unit capacitance of the main-DAC, CM0 , is selected to be 400 fF in order to decrease the influence of the parasitic capacitances to the mismatch of the capacitors. On the other hand, the sub-DAC unit capacitance has lower specifications in terms of matching. However, the parasitic capacitance at the top plate of the subDAC results in linearity error. This is illustrated in Fig. 5.35. The parasitic capacitance of the main-DAC scales all the code lengths with the same amount, thus it does not affect the linearity of the ADC but only results in gain error. On the contrary, the parasitic capacitance at the top plate of the sub-DAC further scales the sub-DAC voltage and results in linearity error. A solution to this problem is over-sizing the value of the capacitor Cc , which increases the weight of the sub-DAC and circumvents the sub-DAC voltage scaling problem [80]. The value of the Cc can be found from:   Cp,Sub (5.30) Cc = CM0 1 + N 2 sub-DAC CS0

5.10 Analog-to-Digital Converter

119

Fig. 5.35 The main-DAC and sub-DAC parasitic capacitances. The main-DAC parasitic capacitances result in gain error, where as the sub-DAC parasitic capacitances result in linearity error

where Nsub-DAC is the number of bits of the sub-DAC. The CS0 is selected as 800 fF in order to further decrease the effect of parasitic capacitance. The total parasitic capacitance at the top plate of the sub-DAC is extracted as 254 fF from the layout, therefore using (5.30), the Cc is set to 404 fF, instead of the ideal value of 400 fF. The layout of both the main-DAC and the sub-DAC use the common-centroid architecture as proposed in [89], in order to minimize the mismatch of the capacitances. All the routing is done using the top metal layer and there are no routing metals crossing the poly-poly capacitors. The capacitor CH of the SAR-ADC is set equivalent to the total capacitance of the main-DAC, 25.6 pF, so that the input nodes of the ADC are symmetric. This indicates that the kT/C noise of the CH capacitance is 12 µVrms or 72 µVpp , which is smaller than the 0.1 LSB voltage (considering the reference voltage of the ADC, VH , is 2 V).

5.10.4 Low-Offset Comparator Implementation The comparator of the SAR-ADC is responsible for deciding the polarity between its inputs. The most power efficient architecture for the comparator stage is the regenerative latch architecture due to its superior power-delay product [80]. However, regenerative latches suffer from offset voltages as large as 50 mV. Therefore, a lowoffset preamplifier with a total gain larger than 100 is necessary for reducing the input referred offset voltage to smaller than half a LSB voltage. The optimum number of preamplifier stages is important for minimizing the power-delay product of the preamplifier. The total delay of a N -stage preamplifier can be expressed as [90]: td,total =

CL × (Atotal N!)1/N gm

(5.31)

where Atotal is the total gain of the cascaded preamplifiers, gm is the transconductance of the input pair transistors of each gain stage, and CL is the load capacitance.

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A Complete Biopotential Acquisition ASIC

Fig. 5.36 Change of power-delay product of the preamplifier with number of stages

Multiplying the total delay of the preamplifier with N × gm will give the powerdelay product of the preamplifier normalized with the load capacitance of each stage of the preamplifier. Figure 5.36 shows the change of the normalized power-delay product with increasing number of stages for Atotal equals to 100. The curve has its minimum at three, therefore three preamplifier gain stages is most efficient in terms of power-delay product. The bandwidth of each gain stage can be determined from the step response of cascaded N gain stages. Considering that the input stage of the latch has the same bandwidth with the preamplifier stages, the necessary amplification time can be found using:  N −1

(t/τ )k −t/τ = 0.99 (5.32) 1−e k! k=0

so that the output reaches the 99% of the final value. The constant τ is the time constant of the each gain stage and the input stage of the regenerative latch [91], and N equals to four (three gain stages plus the input stage of the regenerative latch). Hence, it can be found that 10 × τ is necessary for the preamplifier and the input stage of the latch to settle. The self-timed bit cycling (Fig. 5.32) can increase the settling time of the critical decisions up to 2 µs. Considering an average settling time of 1.5 µs, the bandwidth of each stage has to be larger than 1 MHz. Figure 5.37 shows the architecture of the low-offset comparator. It consists of three preamplifier stages and a regenerative latch. The preamplifiers utilize the autozeroing technique in order to eliminate the offset voltage and low-frequency errors of the preamplifiers [29], and amplify the input signal. Later, the regenerative latch amplifies the output of the preamplifier stage to supply rails. The auto-zeroing of the preamplifiers consists of a PURGE and an AUTO-ZERO phases. During the PURGE phase, all the preamplifiers are reset and PRG switches

5.10 Analog-to-Digital Converter

121

Fig. 5.37 Architecture of the low-offset comparator of the SAR-ADC

are closed. Therefore, the capacitor voltage is discharged. Later, PRG switches are opened and the preamplifiers are set to amplification mode by setting the RSTpre signal to high. In this mode, the offset of the preamplifiers are amplified and stored on the auto-zero capacitors. Next, the AZ switches are opened consecutively. First, the AZ1 switch is opened, therefore any charge injection from the AZ1 switch is considered as offset voltage by the following stage, hence the charge injection from the switches AZ1 and AZ2 can be eliminated. Figure 5.38 shows the building blocks of the implemented low-offset comparator architecture. The first preamplifier (PA1 ) is implemented with pMOS input pair transistors and nMOS loads, so that the input range of the first stage is consistent with the output voltage swing of the analog readout front-end circuit (0.3 V–2.1 V). On the other hand, the current consumption of the input pair transistors are adjusted such that the total input referred peak-to-peak voltage noise is smaller than 0.2 LSB (∼200 µV). Assuming that the noise of the load transistors are negligible and the input pair transistors are operating in weak inversion, the following condition should hold in order to meet the noise specification:  200 µVpp 4kT n π (5.33) × × fp,PA1 < gm 2 6 where fp,PA1 is the −3 dB bandwidth of the PA1 . From this equation, it can be extracted that the transconductance of the input pair transistors must be larger than 50 µS, when the bandwidth of the preamplifier is 1.5 MHz. The size of the input

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Fig. 5.38 Building blocks of the low-offset comparator of the SAR-ADC, (a) PA1 , (b) PA2 , (c) PA2 , (d) Regenerative Latch

transistors are limited to 180/1.5 and the quiescent current of the input pair transistors are set to 3 µA. Therefore, the transconductance of the input stage is 60 µS. Since the current consumption of the first preamplifier stage is defined by the noise specifications, the gain of the stage is maximized by using long channel nMOS transistors as the load. Hence, the gain of the PA1 is 6.6, and the two load capacitances of size 0.6 pF set the −3 dB bandwidth of PA1 to 1.3 MHz. Then, the total input referred peak-to-peak noise voltage of the preamplifier is 210 µVpp . During the AUTO-ZERO phase, the preamplifier also sees the hold capacitance as a load, and the −3 dB bandwidth is reduced to 600 kHz. Since 2 µs is allocated for the PURGE phase, the offset of the PA1 can be precisely sampled. Since the noise and the input voltage swing of the preamplifier channel is defined by the PA1 , the second and the third preamplifier stages (PA2 and PA3 ) use nMOS input pair transistors due to their superior mobility compared to pMOS transistors. Both PA2 and PA3 have the same current consumption and gain, where as the PA2 includes a level shifter. Since the PA1 has a gain of 6.6, the necessary gain for each of these two preamplifiers are 3.9 for the total gain of 100. The tail current is set to

5.10 Analog-to-Digital Converter

123

Fig. 5.39 Measurement of the timing and the SPI output of the 11-bit SAR ADC

1.5 µA for each gain stage and the pMOS load transistors are adjusted such that the gain is 4.2. Therefore, the −3 dB cut-off frequency appears at 2 MHz. Finally, the regenerative latched comparator uses the same architecture shown in Fig. 5.10 due to its low kick-back noise [73]. The critical design parameter of the latched comparator is the settling time of the input stage of the comparator, so that the gate voltages of the current mirrors settle to their final values before the Comp signal goes high. Since previously it has been shown that the bandwidth of the input stage of the comparator must be larger than 1 MHz, the tail current of the latched comparator is set to 2 µA, which sets the bandwidth of the input stage to 1.5 MHz.

5.10.5 Test Results Figure 5.39 shows a sample output of the ADC. The digital input signal CONVERT starts the conversion process. The PW signal is monitored to measure the conversion time of the ADC. At the instant that PW goes high, the input is sampled by the ADC. The rising edge of the PW also indicates the start of the bit-cycling process, where as, the falling edge shows the moment when the ADC has accomplished the conversion process. At this instant, the parallel outputs of the ADC are ready and can be sampled. Later, the serial output of the ADC is generated. The serial output of the ASIC is updated at the each falling edge of the CLK_SPI. The first 5-bits of the 16 clock cycles are zero and the MSB starts from the 6th falling edge of the CLK_SPI. The power ON time of the ADC is 28 µs during which the ADC performs the conversion process.

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A Complete Biopotential Acquisition ASIC

(a)

(b) Fig. 5.40 (a) DNL and (b) INL measurement of the 11-bit SAR ADC. The maximum DNL ad INL are −0.27 and 1.45, respectively

Figure 5.40 shows the DNL and INL measurements of the 11-bit SAR-ADC. The maximum DNL of the ASIC is 0.21/−0.27 LSB indicating that there are no missing codes and the maximum INL is 1.45/−0.67 LSB. Finally, AC characteristics of the ADC is characterized for a full-scale input sine wave of 105 Hz. In order to simulate the operation of the ADC is the EEG acquisition ASIC, the ADC is operated at its maximum sampling rate (25 kHz), and the output of the ADC is demultiplexed that represent the outputs of the eight acquisition channels. This corresponds to a channel sampling rate of 3.125 kHz per channel (25 kHz for 8 channels). Figure 5.41 shows the 12500 point FFT of the ADC output for a single channel. SNDR, SFDR, and

5.11 Impedance Measurement and Calibration Modes

125

Fig. 5.41 12500 point FFT of the demultiplexed ADC output for a full-scale sine wave input at 105 Hz. ADC is operating at 25 kHz sampling rate. The output of the ADC is demultiplexed into eight channels representing the outputs of the eight acquisition channels that corresponds to 3.125 kHz/chn sampling rate

THD of the ADC are calculated as 64.9 dB, 66.8 dB, and −66.4 dB, respectively. Therefore, the ADC has 10.5 ENOB.

5.11 Electrode Impedance Measurement and Calibration Modes of the ASIC 5.11.0.1 Implementation The EEG acquisition ASIC can be configured as an impedance measurement circuit that enables the user to measure the impedance of the biopotential electrodes. Figure 5.42(a) shows the architecture of the impedance measurement mode of the EEG acquisition ASIC. When the ASIC is set to the Electrode Impedance Measurement mode, the positive input of each channel is connected to an on-chip square wave current source with 10 nApp amplitude. Since the current flows through the smallest impedance path, it flows through the biopotential electrodes and the patients’ ground electrode to the output of the patient bias buffer. Since the input of the each readout channel is a high impedance node compared to the patient bias voltage, no current passes through the reference electrode. As a result, the differential voltage at the input of

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A Complete Biopotential Acquisition ASIC

(a)

(b) Fig. 5.42 (a) Architecture of the built-in electrode impedance measurement mode. (b) Architecture of the built-in calibration mode

5.11 Impedance Measurement and Calibration Modes

127

each channel can be expressed as: Vin,peak–peak = Ipeak–peak × Zelec

(5.34)

where Zelec is the equivalent electrode impedance. Therefore, the differential input voltage is directly proportional to the electrode impedance to which the channel is connected. This input voltage is amplified by the readout channel and digitized by the ADC. As a result, the electrode impedance of each channel can be extracted. In addition to the Electrode Impedance Measurement mode, the EEG acquisition ASIC includes a Calibration mode to test the functionality of the ASIC and the gain matching of the readout front-end channels. The configuration of the ASIC during the Calibration mode is explained in Fig. 5.42(b). When the ASIC is set to the Calibration mode, a square wave current source of the impedance measurement circuit is used for generating a 10 µVpp square wave voltage over a 10 k hipo resistor. This voltage is connected to the positive inputs of each channel and amplified by the readout front-end channels. The output of each channel is digitized by the ADC and the result can be used to extract the gain matching of the readout front-end channels.

5.11.0.2 Test Results Figure 5.43 shows the output of the ASIC in Calibration mode. The voltage generated on the on-chip hipo resistor is amplified by all the channels and digitized by the ADC. The output indicates the gain and the bandwidth matching of the channels. Since the value of the on-chip resistor and the current source can not be known precisely, it is not convenient to measure the gain of the individual channels using this method. Instead, the matching of the readout channels can be extracted using this

Fig. 5.43 Output of the ASIC in calibration mode

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A Complete Biopotential Acquisition ASIC

Fig. 5.44 Impedance measurement of dummy resistors that are connected to the inputs of the EEG acquisition ASIC during Electrode Impedance Measurement mode in order to simulate the biopotential electrode impedances Table 5.4 Measured resistance values of the dummy resistors during Electrode Impedance Measurement mode for two different resistors used as a reference electrode resistance Channel

Resistance (k)

Measurement (Ref. Electrode = 10 k)

Measurement (Ref. Electrode =∼ 0 k)

1

4.67

4.58

4.59

2

8.2

8.06

8.04

3

2.7

2.69

2.70

4

1.8

1.83

1.81

5

10

9.84

9.87

6

10

9.80

9.77

7

1.2

1.22

1.21

8

6.8

6.68

6.68

test. After the output waveform is filtered with a bandpass filter, the gain matching of the channels is measured as 1%. The test of the Electrode Impedance Measurement mode is performed by connecting dummy resistors to the inputs of the channels that simulates the biopotential electrode impedances. The ASIC is configured to impedance measurement mode, and the output of the channels are digitized by the ADC. Figure 5.44 shows the bandpass filtered outputs of the ASIC, and Table 5.4 shows the measured resistance

5.12 Biological Test Results

129

values for the each ASIC channel for two different resistance values used as a reference electrode resistance. The results show that the circuit can extract the impedance of the electrodes with high precision and proves that the reference electrode resistance has no effect on the measurements. It should be noted that the resistance values are extracted by incorporating the measured output voltage amplitude of each channel during the Calibration mode. Since it is known that the on-chip resistor of the Calibration mode is 10 k, the electrode impedance of each channel is calculated from the ratio of the output voltage during the Calibration mode and during the Electrode Impedance Measurement mode. Therefore, the gain mismatch of the channels has no effect on the electrode impedance measurement.

5.12 Biological Test Results In order to verify the operation of the EEG ASIC with real EEG signals, a test setup has been prepared. Two Ag/AgCl cup electrodes are placed on the skull of a subject at the locations O1 and O2 (occipital cortex) in accordance with [12]. These two electrodes are connected to the two inputs of the ASIC. The patient bias voltage, which is generated on-chip, is connected to the electrode located at T3. Finally, the reference input of the ASIC is connected to another Ag/AgCl electrode at the location Oz. A microcontroller [59] is employed for generating the 32 kHz clock signal of the ASIC. The readout front-end channels are configured for maximum gain and minimum bandwidth. The channel sampling rate of the ADC is selected as 1 kHz/chn. The EEG signals are amplified and filtered by the two front-end channels. The outputs of the channels are sampled by the on-chip ADC and extracted by the computer. Figure 5.45 shows the extracted EEG signals (amplitudes are referred to the channel inputs), and their STFT. The dominant rhythm, when the patient closes his eyes, is in the alpha range (8–13 Hz). It should be noted that the electrode at the location O2 has 7 mV offset with respect to the reference electrode, which proves the operation of the fine-coarse servo-loop of the ACCIA.

5.13 Summary of the Biopotential Acquisition ASIC Figure 5.46 shows the die micrograph of the biopotential acquisition ASIC implemented in 0.5 µm three-metal double-poly CMOS process through AMIS. It measures 3.9 mm by 4.5 mm. Table 5.5 summarizes the measured performance of the EEG acquisition ASIC. The total current consumption of the ASIC is 66 µA, when all of its eight channels are sampled with 8 kHz sampling rate (1 kHz/channel). This measurement is taken when the SPI output of the ADC is not loaded, i.e. no connection is made to the SPI data and SPI clock outputs of the ASIC. If the SPI output of the ASIC will be used the current consumption of the ASIC will be increased due to the increased power consumption of the bondpad output buffers of the SPI outputs.

Fig. 5.45 Extracted EEG signals and their STFT from the electrodes connected to the skull of the subject at location O1 and O2. The dominant rhythm is in the alpha range (8–13 Hz), when the patient closes his eyes

130 A Complete Biopotential Acquisition ASIC

5.14 Conclusions

131

Fig. 5.46 Die micrograph of the biopotential acquisition ASIC implemented in 0.5 µm three-metal double-poly CMOS process through AMIS

5.14 Conclusions This chapter introduces the design and implementation of a low-power (66 µA) EEG acquisition ASIC, that includes eight acquisition channels, an 11-bit ADC, a 1 MHz square-wave relaxation oscillator, a temperature-voltage independent bias circuit. In addition to the Acquisition mode, the ASIC has Electrode Impedance Measurement and Calibration modes. Therefore, the EEG acquisition ASIC presents a single-chip solution for signal extraction, conditioning, and digitization for the EEG signals, as

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well as for the quality monitoring of the biopotential electrodes and the calibration of the readout front-end channels. The most important building block of the ASIC in terms of signal quality and power dissipation is the IA. The proposed IA architecture of this Chapter, called the ACCIA with coarse-fine servo-loop, not only improves the performance of the ACCIA architecture of Chap. 4 and eliminates the external passives for setting the HPF frequency, but also achieves the best power-noise performance (NEF) in the literature for EEG signal extraction. The new architecture has key benefits compared to the state-of-the-art. The input impedance of the ACCIA with coarse-fine servo-loop is more than two orders of Table 5.5 Summary of the Biopotential Acquisition ASIC Specification

Value

Total Cur. Cons. of Bias Circuit

11 µA

Description

Readout Channel Building Blocks AC Coupled Chopped IA (ACCIA) with Coarse-Fine Servo-Loop BWACCIA

28 kHz

fchop

2 kHz

Voltage Gain

240

Input Ref. Noise Density

√ 55 nVrms / Hz

Input Impedance

>1 G

CMRR

>120 dB

HPF cut-off frequency

∼0.1 Hz

Current Consumption

2.3 µA

NEF

200 mV gate bias

4.1 Chopping Spike Filter (CSF)

fCSF

4 kHz

Duty Cycle (m)

6.25%

HPF Cut-Off Frequency

∼0.5 Hz

Current Consumption

0.2 µA

Total current of two CSF stages

Programmable Gain Stage Programmable Gain

16.7, 25, 50

SG1 SG0 = 00, 01(10), 11

Programmable BW (First Pole)

200, 300, 575

SG1 SG0 = 00, SBW1 SBW0 = 11, 01(10), 00

130, 190, 375

SG1 SG0 = 01(10), SBW1 SBW0 = 11, 01(10), 00

70, 105, 210

SG1 SG0 = 11, SBW1 SBW0 = 11, 01(10), 00

Programmable BW (Second Pole)

100, 125, 180, 320

Set by LPF (SBW1 SBW0 = 11, 10, 01, 00)

Current Consumption

0.5 µA

Total of the VGA and the LPF

5.14 Conclusions

133

Table 5.5 (continued) Specification

Value

BW

450 kHz

Current Consumption

0.6 µA

Description

Channel Buffer

Analog Readout Front-End Number of Channels

8

Cur. Consumption of a Readout Chn

3.6 µA

ACCIA + CSF + VGA + LPF + Chn. Buffer

Programmable Gain

4000, 6000, 12000

SG1 SG0 = 00, 01(10), 11

Programmable BW

see Programmable Gain Stage

THD

<1%

PSRR +/−

89 dB/90 dB

Current Cons. of the Output Buffer

1.35 µA

Total Current Consumption

31 µA

1.65 Vpp output voltage swing 8 kHz ADC samp. rate (1 kHz/chn) (sim)

Square Wave Relaxation Oscillator Static/Dynamic Cur. Cons.

8.5 µA/6.75 µA

Continuous operation (sim)

Duty Cycled Current Cons.

7.65 µA

50% duty cycled current cons. (sim)

11-bit SAR Analog-to-Digital Converter DNL/INL

0.27/1.45

ADC Total Current Cons.

7.6 µA

FOM

2 pJ/conversion

SNDR

64.9 dB

ENOB

10.5

8 kHz ADC sampling rate (1 kHz/chn)

3.125 kHz/chn samp. rate (equals 25 kHz for the 8 channels)

Impedance Measurement and Calibration Signal Generator Impedance Measurement Frequency

15.625 Hz

Max. Measurable Electrode Imp.

33 k

Minimum gain configuration

Complete ASIC Total Current Consumption

∼66 µA

Using the parallel outputs of the ADC

Total Current Consumption

∼80 µA

SPI outputs are loaded with a long line + uC

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A Complete Biopotential Acquisition ASIC

magnitude larger than a recently proposed IA architecture using chopper modulation technique [36]. Moreover, the proposed ACCIA achieves much larger CMRR and lower 1/f noise than the IA of [57]. It should be noted that while achieving key benefits, the ACCIA with coarse-fine servo-loop outperforms the NEF of both [36] and [57]. The implemented ADC uses the state-of-the-art techniques for decreasing its power dissipation. The ADC can sample all the channels of the ASIC through a multiplexer, therefore it eliminates the need for an external ADC and reduces the power dissipation and size of the EEG acquisition systems. The proposed electrode impedance measurement architecture lets the user to extract a square wave voltage, amplitude of which is proportional to the impedance of the biopotential electrodes that are connected to the inputs of the readout front-end channels. Therefore, not only the electrode preparation time can be reduced but also the quality of the electrode, which directly affects the EEG signal quality, can be checked during the EEG measurement.

Chapter 6

Wireless Biopotential Acquisition Systems

6.1 Introduction The low-noise and low-power analog readout front-end ASICs of this book may open the doors towards the miniaturization of low-cost and high-performance wireless biopotential acquisition systems that can improve the patients’ autonomy and quality of life. This Chapter presents the wireless biopotential acquisition systems that make use of the analog readout front-end circuits presented in Chap. 4. All of the wireless biopotential acquisition systems include a state-of-the-art low-power microcontroller, a state-of-the-art low-power radio, and a custom designed antenna. The low-power microcontroller is the MSP430 from Texas Instruments [59]. It consumes 0.6 nJ/instruction active power. Its low stand-by power (2 µW) and fast wake-up time enables the duty-cycled operation of the microcontroller. Furthermore, the built-in ADC can be used to digitize the analog output of the biopotential readout front-end ASICs. The low-power radio is the nRF2401 2.4 GHz transceiver from Nordic [92]. It is capable of transmitting at a maximum data rate of 1 Mbit/s. Thus, the low data-rate applications can be operated in burst mode, transmitting the data at high data-rates and turning off the transceiver during the rest of the time, in order to decreases the power dissipation. The supply current of the transceiver is 8 mA, when transmitting at −5 dBm, and 15 mA in receive mode. The antenna of each system is a custom designed integrated dipole antenna, which takes into account the close proximity of the human body [93]. Different wireless biopotential systems utilizing the biopotential front-end ASICs and the above mentioned components are realized. Each of these acquisition systems can be tailored towards the different needs of the biopotential signals demonstrating the configurable characteristics of the biopotential readout front-end ASICs. This Chapter is organized as follows: Sect. 6.2 and Sect. 6.3 present two wireless biopotential acquisition systems employing the single-channel ExG readout frontend ASIC. The first system is called the wireless Vestibular Evoked Myogenic Potential Acquisition system [94] that uses two of the ExG ASICs to measure the response of the SCM muscles to the voice stimulation through ear. The second system is a wireless two-channel ExG system [95] that utilizes the configurable characteristics of the ExG ASIC such that it is capable of extracting EEG, ECG, EMG, and EOG signals. Section 6.4 demonstrates a 1 cm3 wireless eight-channel EEG acquisition system, which makes use of the eight-channel EEG readout front-end ASIC and achieves the smallest form factor for a multi-channel EEG acquisition system. Finally, Sect. 6.5 states the conclusion of this Chapter. R.F. Yazıcıo˘glu et al., Biopotential Readout Circuits for Portable Acquisition Systems, © Springer Science + Business Media B.V. 2009

135

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Wireless Biopotential Acquisition Systems

6.2 A Wireless VEMP Acquisition System The measurement of Vestibular Evoked Myogenic Potential (VEMP) is a relatively new clinical non-invasive diagnostics for the patients with specific vestibular (balance) disorders [96, 97]. The first reliable measurement procedure is presented by Colebatch et al. by putting surface EMG electrodes on the sternocleidomastoid (SCM) muscles [96]. The vestibular organ is stimulated by loud clicks or tone bursts through ear and the response of the SCM muscles is measured. The VEMP response of a healthy subject is characterized by the positive and the negative peaks of the averaged EMG response of the SCM muscles. These peaks are called p13 and n23, where they are the first positive and negative peaks appearing after the stimulation of the vestibular organ, respectively. The numbers represent the latency of the peaks to the click or to the tone bursts in milliseconds. In order to extract these signals, an electrode is placed on the upper two-third of the SCM muscles. Click or tone bursts are applied as a stimulation signal to the patient via earphones. The repetition rate of this stimulation is generally around 5–7 seconds. The response of the muscles to the stimulation is measured and averaged for fewer than 500 sweeps. Currently available VEMP measurement systems are cabled systems that obstruct the experiments that involve the motion and the rotation of the patients. Therefore, a compact and wireless VEMP acquisition system is implemented for the first time [94], which employs two of the single-channel ExG readout front-end ASICs. Figure 6.1 shows the photo of the wireless VEMP acquisition system. The wireless VEMP acquisition system consists of a MSP430 microcontroller, a single-chip short-range 2.4 GHz transceiver, a dipole antenna, and two audio amplifiers, in addition to two single-channel ExG readout front-end ASICs. The two ExG ASICs are responsible for extracting the response of the SCM muscles on the two sides of the neck to the voice stimulation. Thanks to its configurable gain and bandwidth, the ExG readout front-end ASICs can be configured for the needs of the VEMP acquisition systems. The voice signals are generated by the internal DAC of the MSP430 microcontroller. The audio amplifiers drive the two earphones of the patient, through which the voice stimulation of the vestibular organ can be performed. The microcontroller also generates the 128 kHz clock signal for the ExG ASICs and digitizes the outputs of the ASICs by its internal 12-bit ADC. The radio transmits the digitized VEMP signals to the computer through the wireless link over an USB transceiver. A wireless VEMP test has been performed on a voluntary test person to demonstrate the operation of the system. The voltage gain and the bandwidth of the ExG ASICs are configured to 400 and 1.85 kHz, respectively. The recording electrodes that are connected to the positive and negative inputs of the ExG ASIC are placed to the upper two-third of the SCM muscle and to the SCM muscle tendon just above the sternum. The patient bias (ground) electrode is placed to the forehead of the subject. The vestibular organ of the subject is stimulated through his ear with 5 cycle tone burst at 500 Hz with 5.1 Hz repetition rate at 124 dB RMS SPL. During the measurement, the subject is asked to turn his head to the reverse direction of his ear that is being stimulated.

6.3 A Wireless Two-Channel ExG Acquisition System

137

Fig. 6.1 Photo of the wireless VEMP acquisition system

The output of an ExG ASIC is sampled by the ADC inside the microcontroller. After each sweep of the voice stimulation, microcontroller averages the acquired EMG signal with the previous results in synchronization with the stimulation instant, so that the EMG responses of the muscles are averaged out and the VEMP signal can be extracted. After each sweep, the averaged result is sent to the computer through the wireless link so that the build-up of the VEMP signal is visible. Figure 6.2 shows the result of the wireless VEMP measurement on a healthy subject after the averaging of the 100 stimulations. The amplitude of the VEMP signal is referred to the input of the ExG ASIC. The p13 and n23 peaks are clearly visible demonstrating the operation of the wireless VEMP acquisition system and the successful integration of the ExG ASICs to the wireless VEMP acquisition system. As a conclusion, the new wireless VEMP system gives the patient freedom to move during the VEMP measurement, which enables new experiments that involve motion and rotation of the patient. The system operates from two AA alkaline batteries and it is capable of making more than 1000 acquisitions without the need for battery replacement.

6.3 A Wireless Two-Channel ExG Acquisition System A wireless two-channel ExG acquisition system is implemented that fully utilizes the configurable characteristics of the single-channel ExG ASIC [95]. In addition

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Wireless Biopotential Acquisition Systems

Fig. 6.2 Recorded VEMP signal from a voluntary subject using the wireless VEMP acquisition system. Voice stimulation is 5-cycle tone burst at 500 Hz with 5.1 Hz repetition rate and 124 dBrms SPL

Fig. 6.3 Photo of the wireless ExG acquisition system

to using two single channel ExG ASICs, a MSP430 microcontroller, a nRF2401 2.4 GHz transceiver, and a dipole antenna are integrated in the system. Figure 6.3 shows the implemented wireless ExG acquisition system. The system is capable of extracting EEG, ECG, EMG, and EOG signals, thanks to the configurable gain and bandwidth of the ExG ASIC. The analog outputs of the ExG ASICs are sampled and digitized by the internal 12-bit ADC of the microcontroller. The 128 kHz main clock of the ASIC is also

6.3 A Wireless Two-Channel ExG Acquisition System

139

Fig. 6.4 (a) Three ExG acquisition systems integrated in a flexible band that is worn by the subject. It simultaneously acquires single channel EEG, two channel EOG, and single channel EMG. Electrode locations for each system are indicated on the figure, (b) implemented PSG recording system and a commercial PSG recording system worn by a subject. The commercial system has long cables and also it must be attached to the computer beside the bed through a cable that limits the autonomy of the patient

generated by the microcontroller. The configuration settings of the ASIC can be received from the computer through the wireless link before the start of the acquisition process. The microcontroller receives the configuration settings and adjusts the gain and the bandwidth of the ExG ASICs by setting the Select Gain and Select BW digital inputs of the ASIC. Therefore, the ExG board can be wirelessly configured towards different biopotential signals. The system is operating from a prismatic Li-Ion battery with a capacity of 150 mAh, which also includes a battery protection circuit. The 8 mA average total current consumption of the system, which is dominated by the radio, results in more than 15 hours of power autonomy. The implemented wireless ExG system is compared with a commercial Polysomnography (PSG) recording system in terms of patient autonomy and in terms of signal quality. Figure 6.4(a) shows the implementation of the three wireless ExG systems as a PSG recording system [95]. The three wireless ExG acquisition systems are integrated in a flexible band that is worn by the subject. It simultaneously acquires single channel EEG, two channel EOG, and single channel EMG. The reference electrode of the EEG acquisition system is attached to the back of subject’s ear, where as the other electrode is on the forehead. The EOG acquisition channels have a common reference for its two channels on the forehead at the top of the nose of the subject, and the two other electrodes are connected to the sides of the eyes for EOG extraction. Finally, the EMG acquisition system is connected to

140

Wireless Biopotential Acquisition Systems

Fig. 6.5 (a) Hypnogram of the commercial PSG system [98]. (b) Hypnogram of the PSG system using the wireless two-channel ExG acquisition systems [99]

the electrodes on the chin to measure the tension level. All the three systems share a single patient bias electrode on the forehead. Figure 6.4(b), [95], shows the implemented PSG recording system and the commercial PSG recording system (DREAM system from MEDATEC [98]) worn by a subject. The commercial system has long wires connecting the electrodes to the central node with the chest strap, which can create discomfort and result in cable movement artifacts. In addition, this acquisition box is connected to the computer positioned beside the bed through a cable, which considerably limits the patient autonomy. On the contrary, the implemented PSG recording system is worn by the patient on her head, and the wireless link to the computer enables the free movement of the patient inside the room. Therefore, the implemented system has superior autonomy compared to the commercial PSG recording system. Figure 6.5 shows the comparison of hypnograms extracted from the commercial PSG system, [98], and the PSG system implemented with the wireless two-channel ExG acquisition system [99]. The very similar behavior of the two hypnograms should be noted. Figure 6.6 shows the quantitative comparison of the signals extracted from the two PSG systems. As the values clearly demonstrate the hypnograms of the two systems are very close to each other demonstrating the quality of the extracted signals from the wireless two-channel ExG acquisition system, which in turn proves the performance of the implemented single-channel ExG readout front-end ASIC.

6.4 A 1 cm3 Wireless Eight-Channel EEG Acquisition System

141

Fig. 6.6 (a) Quantitative analysis of the sleep staging extracted with the commercial PSG system [98]. (b) Quantitative analysis of the sleep staging extracted with the PSG system using the wireless two-channel ExG acquisition systems [99]

6.4 A 1 cm3 Wireless Eight-Channel EEG Acquisition System Although EEG diagnostic is a time consuming test, conventional EEG acquisition systems prevent the patients’ mobility due to their bulky size and high power consumption. Thus, such EEG acquisition systems can make use of a low-power multichannel readout front-end for EEG acquisitions. This EEG ASIC can considerably decrease the size and the power consumption of the analog readout front-end. There-

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fore, it increases the power autonomy of the system. On the other hand, the wireless communication channel can eliminate the cables that connect the patient to the EEG monitoring device. The goal is to achieve a small-size, low-power, and ambulatory EEG acquisition device that can not only improve the patients’ quality of life but also extend the device application to sports, entertainment, human-computer interfaces, and so on. A low-power eight-channel EEG readout front-end is implemented as presented in Sect. 4.6. Therefore, this ASIC can be integrated in IMEC’s 3D System-in-aPackage approach in order to achieve high integration density and small footprint that can result in a small form factor for the EEG acquisition system. Figure 6.7(a) shows the photo of the IMEC’s 3D SIP wireless eight-channel EEG acquisition system. It consists of 4 layers, where each has dedicated purposes. The top layer is the radio layer. Similar to the previous wireless acquisition systems, it uses the nRF2401 2.4 GHz transceiver to communicate with the computer. A dipole antenna is integrated that is folded around the transceiver to maximize the total perimeter of the antenna while minimizing the consumed area [93]. The layer below the radio layer is the microcontroller layer that integrates the MSP430 microcontroller. The layer beneath the microcontroller layer is the sensor layer, which uses the eight-channel EEG readout front-end ASIC of Sect. 4.6. The EEG ASIC is wire bonded to the PCB substrate as shown in Fig. 6.7(b), and covered with glob top for protection. The passives of the ASIC are placed at the bottom side of the PCB. Each layer is attached to each other through ball-to-ball stacking concept, which provides electrical and mechanical interconnection between the two adjoining layers [100]. Finally, a prismatic Li-Ion battery with 150 mAh capacity and a 3 V voltage regulator is used as the power layer. The operation of the system is as follows; the 64 kHz main clock of the ASIC is generated by the microcontroller and routed to the ASIC through the ball-to-ball solder interconnects between the microcontroller layer and the EEG layer. Similarly, the multiplexed analog output of the ASIC is routed through the solder-ball interconnects to the ADC input of the microcontroller. The sampling instant of the ADC is synchronized with the multiplexed output of the ASIC by using the ADC SYNC output of the digital control circuit of the ASIC (Fig. 4.22), which indicates the sampling instant of the first channel of the ASIC. Thus, the microcontroller can digitize each channel of the ASIC from the multiplexed output and sort the data points of the each channel. The digitized data is sent to the computer through the wireless link. All the bias voltages, including the patient bias voltage, are generated by the source and sink current outputs of the ASIC. The patient bias voltage is buffered by the on-chip buffer of the ASIC before it is connected to the patient. Figure 6.8 shows the power dissipation of the building blocks of the eightchannel wireless EEG acquisition system for 2048 Hz (256 Hz/chn) and 4096 Hz (512 Hz/chn) sampling rate. In both cases, the dominant power dissipating block is the radio. The EEG ASIC has only 10% contribution to the total power dissipation even if the 256 Hz/chn sampling rate is used, where the power dissipation of the radio and the microcontroller is minimized. It should be noted that the power dis-

6.4 A 1 cm3 Wireless Eight-Channel EEG Acquisition System

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Fig. 6.7 (a) Photo of the eight-channel wireless EEG acquisition system using a 150 mAh prismatic Li-Ion battery, (b) photo of the sensor layer showing the implementation of the eight-channel EEG analog readout front-end ASIC implementation

sipation of the microcontroller includes the power dissipation of the ADC. Based on these figures, the wireless eight-channel EEG acquisition system has a power autonomy of 60 hours even at 512 Hz/chn sampling rate from a 150 mAh prismatic Li-Ion battery. In order to verify the operation of the system, an EEG acquisition test is performed. The two channel inputs of the EEG ASIC are connected to the electrodes attached to the skull on the occipital cortex at locations O1 and O2 . The common

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Wireless Biopotential Acquisition Systems

Fig. 6.8 Power dissipation comparison of the each layer of the wireless eight-channel EEG acquisition system

Fig. 6.9 Two channel EEG signals extracted from O1 and O2 locations of the occipital cortex using the wireless eight-channel EEG acquisition system. Signal amplitudes are referred to the EEG ASIC inputs

reference input of the EEG ASIC is connected to an electrode at the Oz location. The gain of the channels is set to 9000 through wireless link. Figure 6.9 shows the extracted signals, when the subjects eyes are closed. The alpha activity [10] in 8–13 Hz band is clearly visible.

6.5 Conclusions

145

6.5 Conclusions The introduction of the biopotential readout front-end ASICs in Chap. 4 not only opens the doors towards miniaturization of the biopotential acquisition systems, but also enables the integration of the battery powered biopotential acquisition systems with long-term power autonomy. Therefore, this Chapter demonstrates the implementation of various wireless, battery-powered, and miniaturized biopotential acquisition systems that make use of the biopotential ASICs introduced in Chap. 4. Three different biopotential acquisition systems have been described in this Chapter. The first system is a wireless VEMP acquisition system [94]. It employs two of the single-channel ExG ASICs for extracting the SCM muscle response to a voice stimulation through ear. The outputs of the ASICs are digitized by the microcontroller and sent to the computer through wireless link. Due to the fact that the wireless VEMP system is capable of making ambulatory measurements, it enables the measurement of new VEMP tests that include the movement and the rotation of the patients. The second system is a wireless ExG acquisition system that employs two of the single-channel ExG ASIC. Thanks to the configurable gain and bandwidth of the ExG ASIC, this wireless system is configurable for extracting EEG, ECG, EMG, and EOG signals. A PSG recording system is implemented using three of the wireless ExG acquisition system and the acquired signals are compared with a commercial PSG recording device for the clinical validation of the ExG systems [95]. The results prove the performance of the system and the quality of the signals extracted from the single-channel ExG readout front-end ASIC. When it is considered that the commercial PSG system is mains powered, the importance of the results can be further appreciated. At last but not the least, a miniaturized 1 cm3 wireless EEG acquisition system is implemented employing the eight-channel EEG analog readout front-end ASIC. The EEG ASIC is implemented as a separate layer to the IMEC’s 3D SIP approach, resulting in the smallest multi-channel EEG acquisition system ever demonstrated. It has been also shown that the power dissipation of the EEG ASIC is negligible compared to the power dissipation of the microcontroller and the transceiver. As a conclusion, this Chapter demonstrates that the low-power and the highperformance biopotential readout front-end ASICs of Chap. 4 can indeed enable the integration of ambulatory biopotential acquisition systems with long-term power autonomy.

Chapter 7

Conclusions

7.1 Achievements A crucial and important part of a medical diagnostics system is the monitoring of the biopotential signals. These signals are recorded routinely in the modern clinical practice. Commonly, patients are connected to a bulky and mains-powered instrument, which reduces their mobility and creates discomfort. This limits the acquisition time, prevents the continuous monitoring of patients, and affects the diagnosis of the illness. Biopotential readout circuits suffer from various problems for extracting biopotential signals. The extremely weak amplitudes of the biopotential signals makes them susceptible to various correlating signals. The circuits described in this book propose improved architectures and techniques for extracting high quality biopotential signals under low-power dissipation. Three different ASIC are implemented, each of which includes an improved IA and more functionality compared to its successor and compared to state-of-the-art. Chapter 2 gives an introduction to the biopotential acquisition. The characteristics of the biopotential signals, the chemistry of the biopotential electrodes, and the mechanisms behind the generation of the differential DC electrode offset voltages between the biopotential electrodes are introduced. In addition, the interference theory is presented, describing the coupling of the common-mode signals from mains to the human-body that needs to be rejected by the IA. Finally, the advantages of the chopper modulation technique is introduced, which clearly indicates that the chopper modulation technique is effective for achieving high-CMRR and low-noise amplifiers. Unfortunately, the chopper modulation technique is inherently DC coupled, leading to saturation under differential DC electrode offset voltages that are orders of magnitude larger than the biopotential signals. Chapter 3 describes the first biopotential readout front-end architecture of this book, which is an integrated 24-channel EEG readout front-end ASIC. It is capable of extracting EEG signals from conventional Ag/AgCl electrodes. The main criteria during the design of this ASIC is to improve the CMRR of the circuit under large differential DC offset voltages between the biopotential electrodes. For this purpose, a model is derived that describes the CMRR reduction of the IAs with increasing DC electrode offset voltage. Using this model, an IA is implemented with improved CMRR under large differential DC electrode offset voltages. The 24-channel EEG readout front-end ASIC uses this IA architecture in each of its channels. The ASIC is implemented in 0.5 µm CMOS process through AMIS. The proposed IA consumes 110 µA from a single 3 V supply and achieves 0.64 µVrms in 0.5–100 Hz bandwidth (equivalent −3 dB bandwidth of 64 Hz), while rejecting common-mode signals with more than 90 dB CMRR even under 50 mV R.F. Yazıcıo˘glu et al., Biopotential Readout Circuits for Portable Acquisition Systems, © Springer Science + Business Media B.V. 2009

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differential DC electrode offset voltage. The IA is followed by two SC amplifier stages where the first gain stage has a fixed gain of 20 and the second gain stage has electronically selectable gain between 1 and 50 with eight different settings. Therefore, the channel of the 24-channel EEG readout front-end ASIC has variable gain between 200 and 10000. The ASIC also includes an ECG readout channel with selectable gain between 20 and 1000. The 24-channel EEG readout front-end ASIC consumes 3.42 mA from a single 3 V supply, and presents the first single-chip analog readout front-end solution for multichannel EEG monitoring systems. Chapter 4 describes two ASICs implementations, namely, a single-channel ExG readout front-end ASIC and an eight-channel EEG readout front-end ASIC. Both of the ASICs use the same readout channel architecture that makes use of the proposed AC Coupled Chopped Amplifier (ACCIA) architecture. The ACCIA architecture possesses all the advantages of the chopper modulation technique, such as reduced 1/f noise and increased CMRR, and beyond that exhibits HPF characteristics, so that, it can filter the differential DC electrode offset voltage between the biopotential electrodes. Moreover, the ACCIA uses the results of the CMRR model derived in the Chap. 3 and incorporates an input stage architecture that makes the CMRR of the ACCIA resistant to increasing differential DC electrode offset voltage. Therefore, the proposed architecture not only enables the use of the chopper modulation technique for the biopotential applications but also improves their CMRR under large DC input voltages. Two implementations of the √ ACCIA consumes 11.1 µA √ and 6.25 µA, while achieving 57 nV/ Hz and 75 nV/ Hz for the single channel ExG and eight-channel EEG ASICs, respectively. Therefore, the ACCIA of the ExG ASIC achieves 9.2 NEF and the ACCIA of the eight-channel EEG ASIC achieves 9.3 NEF. Both of the ACCIAs achieve higher than 120 dB CMRR at 50/60 Hz, and they are capable of filtering ±50 mV differential DC electrode offset voltage between the biopotential electrodes. In addition to the ACCIA, the channel(s) of the single (eight) channel ExG (EEG) ASIC include(s) a variable gain stage that has configurable gain and bandwidth. The variable gain stage implementations of both ASICs use continuous-time variable gain stages, where the gain is defined by the ratio of the two capacitors. Therefore, these gain stages not only achieve low-power dissipation and amplify the output of the ACCIA but they also act as anti-aliasing filters before the sampling ADC stage that digitize the channels of the ASICs. Both of the ASICs are implemented in 0.5 µm CMOS process through AMIS. The total current consumption of the single channel ExG and the eight-channel EEG ASICs are 20 µA and 93 µA, respectively. Chapter 5 implements a complete eight-channel EEG acquisition ASIC. The building blocks and the architecture of this ASIC is improved compared to the previous ASICs in several aspects. First of all, the ACCIA architecture is improved by proposing a coarse-fine LPF architecture in the servo-loop of the ACCIA, which also eliminates the need for external passives for setting HPF cut-off frequency of the ACCIA. This architecture achieves 0.57 µVrms total input referred voltage noise from 0.5 Hz to 100 Hz, while consuming 2.3 µA from a single 3 V supply. This improves the NEF of the ACCIA to 4.1, which is equivalent to more than four-times power reduction compared to the ACCIA of Chap. 4, resulting in the lowest NEF

7.2 Suggestions for Future Work

149

for the IAs in the literature for EEG extraction. Moreover, the input impedance and the CMRR of the proposed ACCIA is superior to IAs in the literature. In addition to the improved ACCIA, the ASIC includes an on-chip 11-bit ADC that can sample all the channels of the eight-channel EEG acquisition ASIC. This can further improve the power dissipation and size of an EEG acquisition system implementation. The clock of the ADC is generated from an on-chip 1 MHz relaxation oscillator. Another important improvement for eight-channel EEG acquisition ASIC is the Calibration and Electrode Impedance Measurement modes. The Calibration mode of the ASIC lets the user to calibrate the matching of the channels of the ASIC. Therefore, signal amplitudes from the different channels of the ASIC can be compared with the each other. On the other hand, the impedance measurement mode of the ASIC decreases the electrode preparation time by enabling the user to measure all the electrode impedances using the ASIC. In addition, the quality of the electrodes can be checked remotely by interrupting the acquisition process and setting the ASIC into Electrode Impedance Measurement mode. The eight-channel EEG ASIC is implemented in 0.5 µm CMOS process through AMIS. The total current consumption is 66 µA at 8 kHz sampling rate and when the SPI outputs are not loaded (using the parallel outputs of the ADC), and can reach up to 80 µA when the SPI outputs are preferred. At last but not the least, Chap. 6 presents different wireless biopotential acquisition systems that incorporate the ASICs presented in Chap. 4. The comparison of the wireless ExG system with a commercial mains-powered PSG system proves the performance of the single-channel ExG ASIC and the quality of the extracted signals.

7.2 Suggestions for Future Work Based on the presented achievements and developments in this work, the suggestions for future research can be summarized as follows: • The presented ASICs have been successfully implemented in different systems. The ExG system that is using the two of the single-channel ExG readout front-end ASIC is compared with a commercial PSG device that demonstrates the performance of the ASICs. However, further medical validation is necessary especially on patients with disorders. • Another power consuming block of a wireless biopotential acquisition system is the radio. Since the radio is mainly a digital building block, its power dissipation can be reduced by decreasing supply voltage. The minimum supply voltage of the proposed ASICs is 2.7 V. Therefore, further reduction in the radio voltage requires two separate supply voltages. This can be done either by using a low-voltage battery and up-converting the supply voltage for the biopotential ASICs or using a 3 V battery for the ASICs and down-converting the supply voltage for the radio. However, both of these solutions require efficient DC-DC converters for reducing

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•

•

Conclusions

the power dissipation. Alternatively, the ASIC architecture can be modified for low supply voltages. The main building blocks that limit the operation of the proposed ASICs under low-supply voltages are the CBIA architectures of Chap. 4 and Chap. 5. Therefore, these architectures can be modified for operation under lower-supply voltages. The presented ASICs performs the sole purpose of monitoring of the biopotential signals. Therefore, they are useful for the diagnostics of the diseases after they appear. However, an important consideration for the medical world is the prevention of the diseases. This can only be done by integrating intelligent signal analysis, as well as, stimulation/drug delivery blocks to the monitoring systems. The implants are the most suitable form for the prevention of the disorders. The circuit architectures presented in this book (especially the ACCIA of Chap. 5) achieves much better performance than the circuits presented in the literature for the implants. However, the higher voltage of the presented ASICs is a disadvantage. Therefore, further research must be conducted for making the proposed architectures suitable for the biopotential implants. An important consideration for the biopotential signal acquisition is the electrodes. Ag/AgCl wet electrodes are preferred during conventional hospital use due their non-polarizable characteristics. However, the wet electrodes are not convenient for long-term recordings. The reasons for this can be summarized as: – Frequent replacement of the electrodes is necessary due to the dry-out of the conductive gel. – Skin irritation and allergic contact reactions are possible. – Trained personnel is necessary to apply the wet electrodes to the patient. – Cost increases due to the replacement of the electrodes. Therefore, dry electrodes should be considered for the systems dedicated to the long-term monitoring of the patients. However, although there are some dry electrode implementations that have low-impedance and good signal quality [14], the contact problem of these electrodes is a challenge with the hairy parts of the body. Therefore, further research is necessary on the dry electrode architectures for implementing a complete autonomous biopotential acquisition system. Although the characteristics of the spiked dry electrode architecture in [14] are suitable for the usage with the presented ASICs. Improved ASIC architectures must be investigated considering the increased impedance and offset voltage of the dry electrodes. The possibility of using capacitively coupled electrodes should be investigated. Considering the extremely high impedance of these electrodes, the readout circuit should be able to achieve T range input impedance, in order to extract high quality signals from capacitively coupled electrodes.

Chapter 8

Appendix

Current Mirror OTA of Fig. 4.3(a) Schematic

Dimensions for the ExG ASIC (W/L, µm/µm) M1 = M2 = 50/5, M3 = M4 = M5 = 2×2/250, M6 = M7 = 2/250, M8 = 2×7/250, M9 = M10 = 7/250, Ibias = 400 nA. Dimensions for the 8-channel EEG ASIC (W/L, µm/µm) M1 = M2 = 50/10, M3 = M4 = M5 = 2 × 2/250, M6 = M7 = 2/250, M8 = 2 × 7/250, M9 = M10 = 7/250, Ibias = 200 nA.

R.F. Yazıcıo˘glu et al., Biopotential Readout Circuits for Portable Acquisition Systems, © Springer Science + Business Media B.V. 2009

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GM Stages of Fig. 4.3(b) Schematic

Dimensions for the ExG ASIC (W/L, µm/µm) Mgm1 = 2.5/80, Ibias1 = 600 nA, Mgm2 = 7.5/80, Ibias2 = 1.8 µA. Dimensions for the 8-channel EEG ASIC (W/L, µm/µm) Mgm1 = 2.5/160, Ibias1 = 300 nA, Mgm2 = 7.5/160, Ibias2 = 900 nA.

Appendix

Appendix

153

OTAs of the Programmable Gain Stage of Fig. 4.9 Schematic

OTA1 dimensions for the ExG ASIC (W/L, µm/µm) M1 = M2 = 200/10, M3 = M4 = M5 = 2 × 2/200, M6 = M7 = 2/200, M8 = 2 × 4/100, M9 = M10 = 4/100, M11 = 140/40, Ibias = 800 nA. OTA1 Dimensions for the 8-channel EEG ASIC (W/L, µm/µm) M1 = M2 = 200/20, M3 = M4 = M5 = 2 × 2/200, M6 = M7 = 2/200, M8 = 2 × 4/100, M9 = M10 = 4/100, M11 = 140/40, Ibias = 400 nA. OTA2 dimensions for the ExG ASIC (W/L, µm/µm) M1 = M2 = 100/10, M3 = M4 = M5 = M6 = M7 = 2/200, M8 = M9 = M10 = 4/100, M11 = 140/40, Ibias = 200 nA. OTA2 Dimensions for the 8-channel EEG ASIC (W/L, µm/µm) M1 = M2 = 100/20, M3 = M4 = M5 = M6 = M7 = 2/200, M8 = M9 = M10 = 4/100, M11 = 140/50, Ibias = 100 nA.

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Appendix

Bias Buffers of Fig. 4.21 Schematic

Dimensions for the ExG ASIC (W/L, µm/µm) M1 = M2 = 200/10, M3 = M4 = 7.5/100, Ibias = 600 nA, Cc = 1 pF.

OTAVGA of Fig. 5.24 Schematic

Dimensions for the ExG ASIC (W/L, µm/µm) M1 = M2 = 50/5, M3 = M4 = 4/200, M5 = M6 = M7 = M8 = 2/200, M9 = M10 = 2/200, Ibias = 100 nA.

Appendix

155

GM stage of Fig. 5.24 Schematic

Dimensions (W/L, µm/µm) M1 = M2 = 8/40, M3 = M4 = 8/200, M5 = M6 = M7 = M8 = M9 = M10 = M11 = M12 = 2/200, M13 = M14 = 2/200, Mgm = 2/240, Ibias = 100 nA.

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Index

3D, 142 AC Coupled Chopper Modulated IA (ACCIA), 40 architecture, 40 concept, 40 GBW, 40 NEF, 48 noise, 41 structure, 42 ACCIA with coarse-fine servo-loop architecture, 86 CMRR, 102 GBW, 102 NEF, 101 noise, 102 start-up, 99 ADC, 113 ASIC architecture 24-channel EEG readout front-end, 21 complete biopotential acquisition, 79 Eight-channel EEG readout front-end, 63 ExG readout front-end, 53 auto-zero, 120 auto-zero phase, 116 BAN, 1 bandgap voltage reference, 82 biopotential acquisition systems, 18 electrodes, 7 signals, 5 bottom-plate sampling, 116 calibration, 127 capacitive DAC main-DAC, 117 sub-DAC, 117 chopper modulation, 13 1/f noise, 14 CMRR, 18 residual offset, 15 signal distortion, 17 thermal noise, 15

Chopping Spike Filter (CSF), 50, 106 class-AB buffer, 85 ADC reference, 116 readout front-end, 116 CMRR chopper modulation, 18 differential DC electrode offset, 28 electrode offset induced common-mode gain, 26 mismatch induced common-mode gain, 18, 26 systematic, 26 systematic common-mode gain, 18, 26 comparator, 92, 111 complete biopotential acquisition ASIC architecture, 79 biological test results, 129 comparison, 105 DAC artifact, 109 GBW, 109 input referred noise PSD, 102 conversion, 123 current balancing IA 24-channel EEG readout front-end ASIC, 22 biopotential readout front-end ASICs, 44 current balancing IA complete biopotential acquisition ASIC, 95 current DAC, 91 current mirror active, 24 cascode, 24 current mirror OTA, 42 differential DC electrode offset voltage, 8 dipole antenna, 135 DNL, 117, 124 dummy resistor, 128 ECG, 6 EEG, 6 eight-channel EEG readout front-end, 63 architecture, 63 biological test results, 71

R.F. Yazıcıo˘glu et al., Biopotential Readout Circuits for Portable Acquisition Systems, © Springer Science + Business Media B.V. 2009

163

164

CMRR, 71 comparison, 76 GBW, 68 input-referred noise PSD, 69 electrode Ag/AgCl, 8 dry, 8 non-contact, 9 non-polarizable, 7 polarizable, 7 wet, 8 electrode impedance measurement, 125 electrode–electrolyte interface, 7 EMG, 6 ENOB, 125 ExG readout front-end, 53 architecture, 53 biological test results, 61 CMRR measurement, 57 comparison, 76 GBW, 56 input referred noise PSD, 60 half-cell potential, 7 hypnogram, 140 IA architectures current balancing IA (CBIA), 12 current balancing IA (CBIA), 22 SC, 12 three-opamp, 12 INL, 124 integrator, 94 interference, 10 common-mode, 25 electromagnetic, 10 electrostatic, 10 jitter, 112 kick-back noise, 93, 123 low-offset comparator, 119 maximum CBIA offset limit, 44 maximum differential DC electrode offset limit, 44 maximum differential DC electrode offset limit, 88

Index

microcontroller, 135 MSP430, 135 Noise-Efficiency Factor (NEF), 11 occipital cortex, 34, 61, 129, 143 OFF state PMOS transistors, 91 oscillator, 110 polysomnography, 139 power-delay product, 119 preamplifier, 119 PSG, 139 purge, 120 radio, 135 resting potential, 5 SAR-ADC, 113 saturation current, 82 SCM, 136 self-timed bit-cycling, 116 servo-loop, 40 servo-loop coarse-fine, 87 Short-Time Fourier Transform (STFT), 36 step-response, 120 sternocleidomastoid, 136 switched-capacitor amplifier finite-gain compensated, 30 precision and offset, 31 speed, 32 temperature coefficient, 82 temperature independent reference current, 83 tranconductance coarse (CGM), 87 fine (FGM), 87 transceiver, 135 transconductance coarse (CGM), 90 fine (FGM), 94 VEMP, 136 vestibular organ, 136 WHO, 1