Multi-GHz Frequency Synthesis & Division

MULTI-GHz FREQUENCY SYNTHESIS & DIVISION

This page intentionally left blank

MULTI-GHz FREQUENCY SYNTHESIS & DIVISION Frequency Synthesizer Design for 5 GHz Wireless LAN Systems

Hamid R. Rategh Tavanza, Inc.

Thomas H. Lee Stanford University

KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

eBook ISBN: Print ISBN:

0-306-48106-5 0-7923-7533-5

©2003 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print ©2001 Kluwer Academic Publishers Dordrecht All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: and Kluwer's eBookstore at:

http://kluweronline.com http://ebooks.kluweronline.com

Contents

List of Figures List of Tables Preface Acknowledgments 1. INTRODUCTION 1.1 Organization

vii xi xiii xvii 1 2

2. WIRELESS LOCAL AREA NETWORKS 2.1 Wireless LAN standards 2.2 Wireless LAN transceivers 2.3 Summary

5 6 9 10

3. FREQUENCY SYNTHESIZERS 3.1 Phase–locked loops 3.2 Linearized PLL models 3.2.1 First order PLL 3.2.2 Second order PLL 3.2.3 Third order PLL 3.2.4 Fourth order PLL 3.3 Noise in phase–locked loops 3.4 Conclusion

13 13 18 19 20 23 30 37 39

4. FREQUENCY DIVIDERS 41 41 4.1 Digital frequency dividers 48 4.2 Analog frequency dividers 51 4.3 Injection–locked frequency dividers 52 4.3.1 Model for injection–locked frequency dividers 4.3.1.1 Divide–by–two ILFDs with third and fourth order nonlinear 55 functions 4.3.2 Tracking injection–locked frequency dividers 58

vi

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

4.4

4.3.3 Noise in injection–locked frequency dividers Summary

5. EXPERIMENTAL INJECTION–LOCKED FREQUENCY DIVIDERS 5.1 Circuit topologies 5.2 Measurement Results 5.2.1 Single–ended ILFD 5.2.2 Differential tracking ILFD 5.2.3 Noise transfer function 5.3 Summary

58 62 65 65 69 69 73 79 81

6. AN EXPERIMENTAL 5GHZ FREQUENCY SYNTHESIZER 6.1 Proposed synthesizer architecture 6.2 Synthesizer building blocks 6.2.1 Voltage–controlled oscillator 6.2.2 Injection–locked frequency divider 6.2.3 Programmable frequency divider 6.2.4 Phase/frequency detector 6.2.5 Charge pump and Loop filter 6.3 Measurement Results 6.4 Conclusion

83 85 86 86 90 91 95 97 99 103

7. CONCLUSION 7.1 Future work

109 110

Appendices 2D Fourier series expansion of an ILFD nonlinear function Input–output phase difference in an ILFD Polynomial approximation of an oscillator nonlinearity On–chip spiral inductors

113 113 115 119 123

References

127

Index

135

List of Figures

2.1

Network topologies. (a) Access point. (b) Ad hoc. (c) Multihop ad hoc.

8

2.2

U–NII and HIPERLAN frequency bands.

8

2.3

Simplified picture of a wireless transceiver.

10

3.1

Block diagram of a typical heterodyne receiver.

14

3.2

Block diagram of a typical phase–locked loop. Signal–to–interference degradation due to LO spurious sidebands.

14 15

3.4

Signal–to–interference degradation due to LO phase noise.

17

3.5

Linearized PLL model.

18

3.6

Circuit realizations of the loop filter in a second order PLL.

21

3.7

Circuit realization of the loop filter in a third order PLL.

24

3.8

Maximum phase margin as a function of in a third order PLL.

26

3.3

3.9

ratio

Normalized settling time to 10 ppm accuracy as a function of maximum phase margin in a third order PLL.

27

3.10 Normalized settling time to 10 ppm accuracy as a function of crossover frequency in a third order PLL.

28

3.11 The magnitude of the input–output phase transfer function at the reference frequency as a function of the crossover frequency when the phase margin is 50°.

29

3.12 Circuit realization of the loop filter in a fourth order PLL.

30

3.13 Loop transmission Bode plot of a typical fourth order PLL.

31

viii

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

3.14 Maximum phase margin as a function of ratio in a fourth order PLL.

33

3.15 Normalized settling time to 10 ppm accuracy as a function of crossover frequency in a fourth order PLL.

34

3.16 Normalized settling time to 10 ppm accuracy as a function of maximum phase margin in a fourth order PLL.

35

3.17 Normalized magnitude of the input–output phase transfer function of a fourth order PLL at the reference frequency as a function of the crossover frequency (PM=50°).

36

3.18 The linearized PLL model with noise added at the input and output.

37

Block diagram of a flipflop–based divide–by–two frequency divider.

42

(a) Block diagram of a flipflop–based dual modulus divide–by–2/3 frequency divider. (b) Block diagram of a master–slave D–flipflop.

43

4.1 4.2

4.3

State transitions in the dual modulus divide–by–2/3 when

44 45

4.4

Schematic of the SCL D–latch.

4.5

Input (Clk) and steady state output voltage of the SCL D–latch in a very high frequency divide–by–two frequency divider. Normalized maximum operational frequency of the SCL latch in a divide–by–two frequency divider as a function of product.

49

(a) Regenerative frequency divider. (b) Parametric frequency divider.

50

4.8

Model for a free–running oscillator.

52

4.9 4.10 4.11 4.12 4.13

Model for an injection–locked frequency divider. Tracking ILFD. ILO model used for noise analysis. Phasor representation of signals in Fig. 4.11. Noise transfer function of an ILO.

52 58 59 59

5.1

Schematic of the single–ended ILFD.

4.6

4.7

46

62 66

ix

List of Figures

5.2

Schematic of the differential tracking ILFD.

68

5.3

(a) Top view of a square planar spiral inductor. (b) A circuit model for spiral inductors.

69

Die micrograph of the SILFD in a CMOS technology (0.7 mm × 1 mm, including pads).

70

Measured input referred locking range of the SILFD as a function of incident amplitude.

71

Measured maximum input referred locking range of the SILFD as a function of bias current.

72

5.4 5.5 5.6 5.7 5.8 5.9

SILFD phase noise measurements. Chip micrograph of the DILFD in a technology

73

CMOS

Tuning range of the free–running DILFD.

74 74

5.10 Operational frequency range of the DILFD for different incident amplitudes and two different control voltages.

75

5.11 Measured DILFD locking range and power consumption as a function of incident amplitude.

76

5.12 DILFD phase noise measurement setup.

77

5.13 DILFD phase noise measurements. 5.14 Sideband generation due to noise injection at an offset

78

from the incident frequency.

5.15 Measured noise transfer function in the SILFD 5.16 Measured noise transfer function in the SILFD

80 81 82

Simplified block diagram of the front end of the U–NII band WLAN receiver.

84

6.2

Block diagram of the proposed frequency synthesizer.

87

6.3

(a) Schematic of the quadrature VCO. (b) Representation of the quadrature VCO as a ring oscillator.

88

Schematic of the differential tracking ILFD, with dummy transistor M4 to provide a symmetric load for the differential VCO. Block diagram of the pulse swallow frequency divider. Block diagram of the program and pulse swallow counters.

90 91 92

6.1

6.4

6.5 6.6

x

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

Block diagram of the prescaler. Timing diagram of the prescaler over one output cycle when it divides by nine. 6.9 Circuit implementation of the NOR/flipflop of the dual modulus divider in the prescaler. 6.10 The block diagram of the phase/frequency detector. 6.11 The phase/frequency detector with reduced skew between the complementary outputs. 6.7 6.8

6.12 Schematic of the charge pump and loop filter. 6.13 Schematic of the rail to rail unity gain buffer used in the charge pump. 6.14 Percentage of the systematic error between up and down currents as a function of the output voltage. 6.15 Simulated VCO phase noise due to the thermal noise of the loop filter resistors. 6.16 Die micrograph of the 5 GHz frequency synthesizer in a CMOS technology (1 mm × 1.45 mm, including pads). 6.17 VCO tuning range. 6.18 Phase noise of the synthesizer output signal. 6.19 Spectrum of the synthesized signal. 6.20 Synthesizer settling time. B.1 ILFD model used for noise analysis. B.2 Phasor representation of signals in Fig. B.1. D.1 Cross–section of a 2–turn spiral inductor.

93 94 94 96 96 97 98 99 101

102 103 104 105 106 115 116 125

List of Tables

2.1 2.2 4.1

First generation WLAN standards. Summary of HIPERLAN/1 standard. State transitions for the dual modulus divide–by–2/3 when 5.1 DILFD performance summary. 6.1 Power consumption of fully integrated wireless receivers 6.2 PLL parameters. 6.3 Measured synthesizer performance. 6.4 Performance comparison of CMOS PLLs. C.1 Polynomial coefficients of a BJT Colpitts oscillator nonlinearity. D.1 Definition of parameters for on–chip spiral inductor modeling.

7 9 43 79 84 100 107 108 121 126

This page intentionally left blank

Preface

In the past 10 years extensive effort has been dedicated to commercial wireless local area network (WLAN) systems. Despite all these efforts, however, none of the existing systems has been successful, mainly due to their low data rates. The increasing demand for WLAN systems that can support data rates in excess of 20 Mb/s enticed the FCC to create an unlicensed national information infrastructure (U–NII) band at 5 GHz. This frequency band provides 300 MHz of spectrum in two segments: a 200 MHz(5.15–5.35 GHz) and a 100 MHz (5.725–5.825 GHz) frequency band. This newly released spectrum, and the fast trend of CMOS scaling, provide an opportunity to design WLAN systems with high data rate and low cost. One of the existing standards at 5 GHz is the European high performance radio LAN (HIPERLAN) standard that supports data rates as high as 20 Mb/s. One of the main building blocks of each wireless system is the frequency synthesizer. Phase–locked loops (PLLs) are universally used to design radio frequency synthesizers. Reducing the power consumption of the frequency dividers of a PLL has always been a challenge. In this book, we introduce an alternative solution for conventional flipflop based

xiv

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

frequency dividers. An injection–locked frequency divider (ILFD) takes advantage of the narrowband nature of the wireless systems and employs resonators to trade off bandwidth for power. We have designed a fully integrated CMOS PLL–based frequency synthesizer for a 5 GHz WLAN receiver which is compatible with the HIPERLAN standard. In this design we have used an ILFD as the first divider in the feedback path of the PLL to reduce the overall power consumption. The on–chip spiral inductors of the voltage controlled oscillator (VCO) are optimized to reduce the power consumption and to improve the phase noise performance at the same time. The on–chip inductors of the ILFD are also optimized for wide locking range and low power consumption. The synthesizer consumes 21.6 mW, of which less than 1 mW is consumed by the ILFD. The phase noise of the synthesizer is less than -134 dBc/Hz at 22 MHz offset frequency, and all spurious tones are at least 70 dB below the carrier.

Dedicated to Leili

This page intentionally left blank

Acknowledgments

We would like to acknowledge the contribution of many people and organizations who helped us throughout this study at Stanford University. We would like to express our gratitude to Professors Wooley, Cox, Horowitz, and Wong, and also to the students in their research groups whom we enjoyed our long technical discussions. We also would like to acknowledge the members of Stanford Microwave IntegRated Circuit (SMIrC) lab, for being a continuous source of support. Ann Guerra deserves special thanks. Although she always says that she is “just doing her job,” but she always goes far out of her way to help. We are grateful to her for having helped us any time we asked. We would like to thank the Stanford Graduate Fellowship (SGF) organizers and sponsors for their financial support. We would also like to acknowledge National Semiconductor, and specifically Tom Redfern, for providing Stanford with a leading edge CMOS technology. We would also like to acknowledge Tektronix, and specifically Jack Hurt, for supporting us with their simulation tool, ADS.

xviii

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

We find ourselves in great debt to our parents, brothers and sisters, and to our in–laws for their unconditional love and support. Finally, we thank our wives for their patience and encouragements.

Chapter 1 INTRODUCTION

In the past decade the wireless industry has attracted the attention of many researchers, industrialists, and even investors. The current exponential growth of the wireless market requires wireless transceivers with ever increasing bandwidth, better quality, lower cost, and longer battery life. Cellular phones by far constitute the biggest market for wireless systems, but wireless local area network systems are also growing at a very fast pace. Until very recently two limitations of wireless local area network (WLAN) systems have been low data rate and high cost. The former is being overcome by allocating new frequency bands for WLAN service. Among these are the ISM band at 2.4 GHz and the U–NII band at 5 GHz. New standards have been developed, with still others under development, to take advantage of these frequency bands. High integration in low cost technologies is the main step toward reducing the cost of WLAN systems. The fast trend of CMOS scaling makes it an attractive technology for low cost systems. However, to get the required RF performance out of standard digital CMOS technologies, new system architectures and circuit topologies need to be developed.

2

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

Careful studies of wireless architectures identify fundamental limitations and allow modifications to improve performance while maintaining or even increasing battery lifetime. The increasing demand for wideband WLAN systems is the motivation for studying here the design of a fully integrated CMOS receiver at 5 GHz. In this book we focus only on the frequency synthesizer and describe how new architectures and circuit topologies enable us to reduce the cost and power consumption while achieving high performance.

1.1.

Organization

The main objective of this book is to study high frequency and low power frequency synthesis and division in a low cost CMOS technology. The techniques developed in this study apply to any technology and are not limited to CMOS. To prove the effectiveness of these techniques we demonstrate them in the context of a 5 GHz WLAN receiver. The following chapter introduces WLAN concepts and discusses different WLAN standards. In this chapter we present the existing and future markets for WLAN systems and explain the requirements necessary for a successful WLAN system. Chapter 3 deals with phase–locked loop–based frequency synthesizers, which are an essential part of any modern wireless system. In this chapter we specifically examine PLL filter design strategies. The effect of loop bandwidth and phase margin on loop settling time, spur levels, and output phase noise are studied and quantified. Finally we introduce a very simple loop filter design recipe for third and fourth order PLLs. Chapters 4 and 5 focus on high frequency and low power frequency division techniques. In chapter 4 we review existing frequency dividers and present the advantages as well as the disadvantages of each technique. Injection–locked frequency dividers (ILFDs) that trade off bandwidth for

Introduction

3

power consumption are introduced and studied in detail. In this chapter we present a general theory of ILFDs which explains the frequency division mechanism of ILFDs and predicts their operational frequency range (locking range). We also introduce design techniques to reduce the power consumption of an ILFD while increasing its locking range. In chapter 5 we demonstrate the design of two experimental ILFDs and compare their performance with that of conventional frequency dividers. In chapter 6 we put the theoretical and experimental developments of the previous chapters into practice and present the implementation of a fully integrated CMOS frequency synthesizer at 5 GHz. The experimental results show the lowest power consumption reported in any technology while comfortably meeting all specifications for a HIPERLAN receiver. We also demonstrate the operation of analog CMOS circuits with a sub–2V supply. Finally chapter 7 concludes with a summary and a list of suggestions for future work. The four appendices at the end of the book provide supplemental information. Appendices A and B present the extended mathematical analysis of the ILFD model and noise dynamics. Appendix C explores a polynomial approximation of oscillator nonlinearities. Finally, appendix D describes the inductor model used in the optimization of the on–chip spiral inductors.

This page intentionally left blank

Chapter 2 WIRELESS LOCAL AREA NETWORKS

The idea of a modern wireless local area network (WLAN) goes back at least to the late 1970s when IBM laboratories in Ruschlikon, Switzerland reported their infrared (IR) technology for indoor wireless networking [1]. Unfortunately the diffuse IR technology never provided a reliable link for desired data rates [2] and suffered from requiring a non–obstructed medium. In 1985 WLANs entered a new era when the industrial, scientific, and medical (ISM) band was released by the FCC. The advent of new technologies, new architectures, and the allocation of compatible frequency spectrum stimulated the industry, resulting in the appearance of first generation commercial WLAN products around 1990. The demand for WLAN systems has increased steadily since. In health care industries, WLANs not only facilitate wireless connection of laptops, notebooks, and hand–held instruments but also provide a wireless connection to health monitoring systems. They also allow fast and mobile connections to pharmaceutical and personal health care databases. In factory floors, WLANs speed up database access, and allow instant network access for delivery trucks. Educational environments also take advantage of WLANs by providing distant learning through wireless

6

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

classrooms. Students have access to computational databases and online classes with notebook computers no matter where the students are. By far the biggest market for WLANs is in homes and small offices. Multiple computers, printers, and other peripherals are connected without the need for cumbersome wiring. Additional nodes can be introduced easily without retrofitting the building to provide wired connections. Mobility is of course another big advantage. In conference rooms information can be transferred between laptops in real time. To maximize utility, WLANs should interoperate. In turn, interoperability requires a universally accepted standard. Because of the consequent importance of standards, we review some existing WLAN standards in the next section.

2.1.

Wireless LAN standards

First generation standards for spread spectrum WLAN systems in the 2.4 GHz ISM band include IEEE 802.11, Bluetooth, and HomeRF. Table 2.1 summarizes key specifications for these three standards. They all support data rates of 1 Mb/s over a distance of 50 m. One main difference among these three standards is that Bluetooth adopts an ad hoc topology (Fig 2.1(b)) and creates piconets. Each piconet consists of up to eight nodes, any of which can be a slave or a master. Although HomeRF and IEEE 802.11 are capable of supporting ad hoc networks, they employ access points (Fig. 2.1(a)) to control LAN operation in their primary configurations. Wireless LANs generally need to provide data rates in excess of 10 Mb/s to compete with existing wired LANs. The IEEE 802.11b standard provides data rates of up to 11 Mb/s in the 2.4 GHz ISM band. In the US new spectrum, called the unlicensed national information infrastructure (U–NII) band, has been allocated for high data rate wireless

Wireless Local Area Networks

7

communication. As shown in Fig. 2.2 the 300 MHz U-NII band consists of a 200 MHz span from 5.15 GHz to 5.35 GHz, and a 100 MHz band from 5.725 GHz to 5.825 GHz. One of the developing WLAN standards in the U-NII band is IEEE 802.11a standard. Wireless LANs compatible with IEEE 802.11a use orthogonal frequency division multiplexing (OFDM) to provide data rates of 6, 9, 12, 18, 24, 36, 48, and 54 Mb/s [3]. The European WLAN standard for data rates in excess of 20 Mb/s in the 5 GHz frequency range is the high-performance radio LAN (HIPERLAN). The first draft of the HIPERLAN specification was released in October, 1996, and was finalized by the European Telecommunication Standards Institute (ETSI) with two amendments in June, 1998. The HIPERLAN/1 standard employs a multihop ad hoc topology (Fig. 2.1(c)), which allows wireless connectivity beyond the radio range of a single node [4]. Each HIPERLAN node is either a forwarder or a nonforwarder. A nonforwarder node simply accepts the packet intended for it. A forwarder node transmits the received packet to other terminals in its neighborhood. The 150 MHz of the HIPERLAN spectrum (Fig. 2.2), which overlaps the lower 200 MHz of the U–NII spectrum, is divided into 5 channels,

8

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

Wireless Local Area Networks

9

each of which is almost 23.5 MHz wide, leaving a guardband of about 25 MHz at each end of the spectrum. As shown in Table 2.2 modulation in a HIPERLAN/1 system is Gaussian minimum shift keying (GMSK) with a 3 dB–bandwidth–bit duration product (BT) of 0.3 which allows a data rate of 20 Mb/s in a 23.5 MHz wide channel [5]. As yet none of the existing standards has received universal acceptance. New standards are still under development to improve the quality of service, to reduce system costs, and to provide higher data rates in the existing frequency spectrum, while operating in a hostile environment in the presence of strong interferers.

2.2.

Wireless LAN transceivers

In this section we do not intend to study all existing wireless transceiver architectures; instead we provide an overview of a representative wireless system. Fig. 2.3 shows a simplified picture of a typical wireless transceiver. In the transmitter the input data is modulated on a carrier signal and transmitted over a wireless medium. In a typical heterodyne receiver the incoming signal is first amplified with a low noise amplifier (LNA), then mixed with a local oscillator

to

10

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

downconvert to a lower intermediate frequency. Finally the demodulator detects the received information to produce output data. As can be seen in Fig. 2.3 both the transmitter and receiver require accurate local oscillators for proper frequency conversion. It is the generation of these local frequencies which is the focus of this book. In the following chapters we will first develop the required bases for the synthesis of radio frequency signals and then demonstrate the experimental results of such systems.

2.3.

Summary

In this chapter we have discussed the history of wireless LANs and some of their applications. A list of existing WLAN standards with a summary of their specifications was also provided for both low and high data rate systems. Existing standards are modified continuously and new standards are being developed. However, the question of which standard will survive and gain worldwide acceptance is not yet answered. It is most probable that a few existing and future standards will coexist and multi–standard wireless systems will be built. Important factors in determining the success of these systems are performance, reliability, cost, and the ability to operate in the presence of interference generated by both compatible and incompatible systems.

Wireless Local Area Networks

11

In the following chapters we focus on the design and implementation of a phase–locked loop– (PLL–) based frequency synthesizer as a local oscillator (LO) for a low power and low cost U–NII band WLAN receiver. Both system and circuit level issues will be discussed in detail.

This page intentionally left blank

Chapter 3 FREQUENCY SYNTHESIZERS

Frequency synthesizers are an essential part of nearly all multi frequency wireless transceivers. Phase–locked loop– (PLL–) based frequency synthesizers are used as local oscillators (LOs) in wireless receivers (Fig. 3.1) to downconvert the carrier frequency to a lower intermediate frequency Phase–locked loops are also used to perform frequency modulation [6],[7] and demodulation [8]. Clock recovery systems also benefit from phase–locked loops [9]. In this chapter we focus only on the frequency synthesis aspect of phase–locked loops and study different classes of PLLs.

3.1. Phase–locked loops Fig. 3.2 shows the block diagram of a typical PLL. The frequency divider in the feedback path divides the VCO output frequency and compares it with a reference frequency with a phase/frequency detector (PFD). The output of the PFD is filtered with a lowpass filter, whose output in turn is the VCO control voltage. In this configuration the output frequency is M times the reference frequency. In an integer–N frequency synthesizer M is an integer and thus the frequency separation between adjacent LO frequencies is the same as the

14

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

reference frequency. In case of a fractional–N frequency synthesizer the division ratio is a rational number and thus the LO spacing is a fraction of the reference frequency. Wireless systems require very accurate synthesized frequencies (1– 10 ppm accuracy). Therefore, temperature compensated crystal oscillators are generally used in generating the reference frequency. Unfortunately, fundamental modes of inexpensive quartz crystals are limited to

Frequency Synthesizers

15

approximately 30 MHz [10] and operation at large–order overtone modes is impractical. Therefore, it is not cost effective and practical to design fractional–N frequency synthesizers for systems with tens of MHz channel spacing, as they require crystal oscillators in the hundreds of MHz frequency range. Integer–N frequency synthesizers are thus more practical and less costly, compared to fractional–N frequency synthesizers, for such systems. Low spurious sideband amplitudes are an important requirement for frequency synthesizers. Fig. 3.3 pictures the problem of spurious sidebands. Suppose the synthesized LO is a pure sinusoid plus unwanted spurs at offset frequencies equal to the channel spacing. In the receiver the unwanted spurs act as parasitic LO signals that can downconvert the adjacent channel, into the same intermediate frequency (IF) as the de-

16

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

sired channel and thus degrade the signal to interference ratio. In the transmitter the spurious emissions generate interference for the adjacent channels. Generally the in–band blocking requirements define the maximum tolerable spurious tone levels. In most wireless systems spurious sidebands have to be less than –50 dBc (dB below carrier). In an integer–N frequency synthesizer spurious tones appear at offset frequencies equal to the harmonics of the reference frequency and thus fall in the middle of the adjacent channels. In a fractional–N synthesizer, spurs at the harmonics of the reference frequency are not as important. However, spurs at fractions of the reference frequency can fall in the center of the adjacent channel and these are problematic. The source of the fractional spurs is the fractional divider. Generally a fractional divider is designed as a dual or perhaps multi modulus divider that toggles between two or more integer division ratios. The overall division ratio is thus the time average of the integer division ratios which is a fractional number. The periodic toggle between integer division ratios generates strong spurious tones at fractions of the reference frequency. In some synthesizers modulators are used to push this quantization noise to higher frequencies and reduce close–in fractional spurs [11]. Reciprocal mixing of the adjacent channels with LO phase noise also reduces the signal to interference ratio (Fig. 3.4). To understand this mechanism, suppose the RF signal is a pure sinusoid with a strong adjacent tone. When this composite signal is mixed with the noisy LO signal the tail of the downconverted adjacent channel falls in the same IF frequency as that of the desired channel. The signal to interference ratio is approximated by:

Frequency Synthesizers

17

where L is the phase noise in (dBc/Hz) at a given offset frequency, is the ratio of the unwanted tone to the desired signal in (dB) at the same offset frequency, and is the signal bandwidth in (Hz). This equation assumes that the signal is a random process with a uniform power spectral density across the channel bandwidth. It also assumes that the LO phase noise is independent of the signal and is constant over the channel bandwidth. Clearly the phase noise must be reduced to tolerate larger blockers. The close–in or in–channel LO phase noise also degrades the signal to interference ratio. This time the interferer is the desired signal itself. The close–in PLL phase noise is usually dominated by the noise of the

18

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

reference signal 1 and is typically almost constant over the PLL bandwidth The phase noise beyond the PLL bandwidth is mostly due to VCO noise and generally reduces in a

fashion (ignoring the flicker noise).

With the assumption that the signal is a random process with a uniform power spectral density across the channel bandwidth and is independent of the LO phase noise, the signal to interference ratio is approximated

by:

where

is the close–in phase noise in (dBc/Hz). As the loop bandwidth

increases it is important to reduce the close–in phase noise to prevent signal to interference degradation.

3.2.

Linearized PLL models

A typical phase–locked loop of the type shown in Fig. 3.2 can be modeled as a linear system, as shown in Fig. 3.5. As long as the loop bandwidth of the PLL is much less than the reference frequency the same linear model can be used for a charge pump PLL as well [12]. 1

Refer to section 3.3 for a detailed PLL noise analysis.

19

Frequency Synthesizers

The sample and hold nature of the charge pump PLL also demands a small loop bandwidth relative to the reference frequency to guarantee loop stability [8]. In this model the input and output are phases and not voltages. Therefore, the VCO is modeled as an integrator with a gain of and the phase detector has a gain of In a charge pump PLL where is modeled with

is the charge pump current. The loop filter The number of poles of the loop filter, plus the

fundamental pole of the VCO, define the order of the PLL.

3.2.1.

First order PLL

In a first order PLL

is a simple scalar. The PLL is a type–one PLL

with one integrator in the loop. In this case the closed–loop input–output phase transfer function is:

Although the first order loop can provide a very fast loop response [13], it suffers from a non–zero steady state phase error

If the reference signal is a pure sinusoid, the input phase is a ramp function

and the steady state phase error is

where is the reference frequency and is the crossover frequency (open loop unity gain frequency), which is very often referred to as the loop bandwidth. A continuous–time first order PLL is stable for any crossover frequency. However, in a practical PLL the crossover frequency is always much smaller than the reference frequency to suppress

20

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

spurious tones at the harmonics of the reference frequency. Therefore, the steady state phase error can be very large. First order PLLs using finite–range phase detectors can thus go unstable unless an extended– range phase detector like the one in [13] is used.

3.2.2.

Second order PLL

The steady state phase error is forced to zero in a second order PLL by introducing an additional integrator in the loop (type–two PLL). Fig. 3.6 shows two ways of implementing this additional integrator in a charge pump PLL. Capacitor provides the additional integrator by integrating the charge pump current. Furthermore, the combination of and generates a zero at which improves the phase margin. In this case the input–output phase transfer function is:

where

and

Compared to a first order PLL, the additional pole of a second order PLL can potentially increase the loop settling time. Settling time is especially an issue for fast frequency hopped systems, where the frequency synthesizer rapidly switches among different frequencies. Typically the PLL frequency is changed by adjusting the frequency multiplication factor M. Suppose at time zero M changes by a small amount

21

Frequency Synthesizers

The output frequency is then equal to:

The multiplicative term in the reference frequency at

can be viewed as a step change With this simplification the output

22

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

frequency is

The initial output frequency is

and the final value is

The transient time for the output frequency to reach within

of its final

value equals

where

is the settling time of a second order PLL. One would expect

that a larger crossover frequency would result in a faster loop and thus a shorter settling time. To place this relationship on a quantitative basis, first note that the crossover frequency of a second order PLL is:

where

Therefore, we can rewrite (3.14) as:

Frequency Synthesizers

23

which demonstrates the inverse dependency of the settling time on crossover frequency. If we repeat the preceding analysis for a first order PLL we get:

and

where and are the settling time and crossover frequency of a first order PLL, respectively. Equations (3.17) and (3.19) show that, for a given crossover frequency, the settling time of a second order PLL is more than twice as much as that of a first order PLL. With our linearized model a second order PLL is always stable. However, if a charge pump is used then our linear model is valid only as long as the crossover frequency is much less than the reference frequency. In practice the sample and hold nature of a charge pump PLL requires the crossover frequency to be less than about 1/10 of the reference frequency to guarantee stability. Furthermore, any mismatch in the charge pump of a second order PLL causes sudden jumps on the VCO control voltage at every phase measurement cycle. Large spurious tones can thus appear at the output. Therefore, an additional capacitor is usually added to the loop filter (Fig. 3.7) to prevent sudden jumps on the VCO control voltage and thus reduce the spurious sideband levels. Unfortunately, this added capacitance increases the PLL order to three.

3.2.3.

Third order PLL

The additional pole of a third order PLL provides more spurious suppression. However, the extra phase lag associated with this pole introduces a stability issue. Thus the loop filter must be designed carefully to

24

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

provide the required filtering while maintaining the loop stability. The impedance of the loop filter shown in Fig. 3.7 is:

where third order PLL is

and

The loop transmission (LT) of the

25

Frequency Synthesizers

The phase margin of the loop is

where

is the crossover frequency. By differentiating (3.22) with

respect to when

it can be shown that the maximum phase margin is achieved

with a corresponding maximum phase margin

The maximum phase margin is thus only a function of (the ratio of to

). For less than one the phase margin is less than 20° (Fig. 3.8),

which makes the loop stability unsatisfactory. To complete our loop analysis we force

and get:

For a third order loop it is analytically complicated to find the settling time. In general the settling time is a function of the percentage change in the feedback division ratio

and is larger for a larger

Eq. (3.25) is satisfied. For most wireless systems Fig. 3.9 shows the simulated settling time to 10 ppm accuracy as a function of phase margin when crossover frequencies

The simulation is repeated for several The settling time in Fig. 3.9 is normalized

to the period of the reference frequency,

For all crossover

26

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

frequencies there is a minimum for the settling time when and the settling time increases by only 30% when the phase margin is between 46° and 52°

For each phase margin

the settling time is inversely proportional to the crossover frequency (Fig. 3.10), as expected. The following empirical formula can be used to estimate the settling time to 10 ppm accuracy when

and

20° < PM < 70°:

where PM is in degrees and is calculated from (3.24). Notice that according to Eq. 3.26, the settling time changes by more than a factor of

Frequency Synthesizers

27

three for phase margin variations from 30° to 70°:

To minimize the loop settling time of a fast frequency hopped PLL, it is therefore important to design the loop filter with a 50° phase margin. As mentioned before, the main reason for adding the third pole to the loop is to reduce spurious tones. Fig. 3.11 shows the magnitude of the input–output phase transfer function at the reference frequency as a function of the crossover frequency when the phase margin is 50°. The vertical axis is normalized to the PLL frequency multiplication factor (M). For a crossover frequency of 1/10 of the reference frequency the normalized attenuation at the reference frequency is almost 30 dB. The attenuation is larger for smaller crossover frequencies and is proportional

28

to

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

(-40 dB/dec). The attenuation of the nth harmonic of the ref-

erence frequency

is

more than that of the reference

frequency. From the forgoing developments, we can finally define a loop filter design recipe as follows:

1 Find

for the VCO.

2 Choose a desired phase margin and find

3 Choose the crossover frequency for 4 Select

and

from (3.24). [IF PM=50°,

and find from (3.23).

such that they satisfy (3.25).

Frequency Synthesizers

29

5 Calculate the noise contribution of 2. If the calculated noise is negligible the design is complete; otherwise go back to step 4 and increase In a third order PLL the combination of the phase margin and crossover frequency defines the characteristics of the loop. To further reduce the spurs without decreasing the crossover frequency and hence increasing the settling time, an additional pole needs to be added to the loop. This additional pole increases the PLL order to four.

2

Refer to section 3.3 for noise calculation.

30

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

3.2.4.

Fourth order PLL

Fig. 3.12 shows the circuit implementation of the loop filter in a fourth order PLL. In this case the impedance of the loop filter is:

where

The phase margin is

where

is the crossover frequency of the loop transmission. As for

a third order loop the maximum phase margin is achieved when the

31

Frequency Synthesizers

derivative of (3.29) with respect to

is zero. The crossover frequency

for the maximum phase margin in a fourth order PLL is

Finally for ing equation.

to be the crossover frequency it should satisfy the follow-

32

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

As in a third order loop the maximum phase margin is not a function of the absolute values of the R’s and C’s; it is only a function of their ratios. Equations (3.29), (3.30), and (3.32), although accurate, are too complex and must be simplified in practical cases. Fig. 3.13 shows the loop transmission Bode plot of a typical fourth order PLL. Because of the two integrators in the loop the phase starts at –180°. The zero then adds positive phase and increases the phase margin. Finally the third and fourth poles come into play and the phase at high frequencies is –270°. A positive phase margin is the result of the zero at a lower frequency than the two high frequency poles and therefore Also for the fourth pole not to decrease the phase margin drastically it has to be more than a decade away from the zero and thus With these conditions and we can approximate A,

and (3.32) as:

The maximum phase margin also simplifies to

With these approximations the maximum phase margin is only a function of

Fig. 3.14 shows the exact maximum phase margin as

a function of for different

ratios. The phase margin for the case of

33

Frequency Synthesizers

is shown as well. When and Eq. (3.36) is exact. For

the loop order reduces to three and the phase margin

estimated by Eq. (3.36) is less than 2° higher than the exact value. The error is bigger for larger values of and Simulation is used to estimate the settling time to 10 ppm accuracy when

As for any loop the settling time is inversely propor-

tional to the crossover frequency (Fig. 3.15). Also, as shown in Fig. 3.16 the settling time at a given phase margin is independent of

and is the

same as that of a third order loop with the same phase margin. Therefore, equation (3.26) can be used for a fourth order loop as well to estimate the settling time. As in a third order loop the loop filter should be designed for a 50° phase margin to minimize the PLL settling time.

34

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

So far we have shown that for with the same

third and fourth order loops

and crossover frequency have nearly identical phase

margins and settling times. The additional pole of a fourth order PLL provides higher spurious filtering without reducing the crossover frequency. The spurs appear at the harmonics of the reference frequency and are usually largest at the first harmonic. Fig. 3.17 shows the magnitude of the input–output phase transfer function at the reference frequency. The solid line is for a third order loop. The non–solid lines are for a fourth order loop with different

ratios. As the crossover

frequency decreases, the additional filtering of the fourth pole becomes more prominent. For example when the crossover frequency is 1/100 of the reference frequency the attenuation at the reference frequency is

35

Frequency Synthesizers

14 dB larger in a fourth order loop with

and increases by

To improve the spurious filtering of a third order loop by the same amount, we would have to reduce the crossover frequency by more than 2.2 times, which would increase the settling time by the same factor. The filtering of the higher harmonics is improved by an even larger factor in a fourth order loop. The attenuation of the nth harmonic of the reference frequency is This is

more than that of the reference frequency. more than what is achieved in a third order PLL.

Now we can define the loop filter design recipe of a fourth order loop: 1 Find

for the VCO.

2 Choose a desired phase margin and find from (3.36). [If PM=50°,

36

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

3 Choose the crossover frequency for

and find

4 Choose the desired spur attenuation and find 5 Select

and

from (3.34).

from Fig. 3.17.

such that they satisfy (3.35).

6 Calculate the noise contribution of

and

If their noise con-

tribution is negligible the design is complete, otherwise go back to step 5 and increase 3

to reduce the noise of both

Refer to section 3.3 for noise calculation.

and

or just

37

Frequency Synthesizers

increase

(for a fixed ) and repeat step 6 to reduce only the noise

of

3.3.

Noise in phase–locked loops

There are several noise sources in a PLL. The two main noise sources are that of the VCO, modeled by and the noise from the reference signal, Fig. 3.18 shows the linearized PLL model with the VCO and reference noise added. The noise of the frequency dividers, phase detector, charge pump, and loop filter can all be represented by The noise transfer function from

to

is the same as the input–output

phase transfer function and is a low pass function:

where

and

are the numerator and denominator of the loop

filter transfer function respectively. At low frequencies:

38

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

and

This low frequency noise amplification is expected from the frequency multiplication of the PLL. However, at high frequencies and the attenuation increases by where

of the frequency,

is the order of the loop and

The VCO noise, unlike

is attenuated

is the order of

is high pass filtered:

At low frequencies

and the VCO noise attenu-

ation is proportional to

where

is the number of integrators in the

loop. Except for the first order loop all other loops discussed in the previous sections have two integrators. At frequencies beyond the crossover frequency

and

Typically at low fre-

quencies the PLL noise is dominated by reference noise and at higher frequencies by VCO noise. The noise of the frequency dividers, phase detector, and charge pump are simply added to the reference noise and are usually negligible in a careful design. However, loop filter noise can be considerable especially when the VCO gain constant,

is large.

The only source of noise in a loop filter of a second and a third order PLL is resistor

The transfer function from

noise of

the equivalent voltage

to the output is calculated as:

The fourth order loop has an additional source of noise, noise transfer function from

the equivalent voltage noise of

to the output is calculated as:

The

39

Frequency Synthesizers

Because of the additional zeros in (3.39) and (3.40) compared to (3.37) the output noise due to the thermal noise of

and

initially increases

with frequency and then decreases. Therefore, it is important to make sure that the thermal noise of these resistors does not cause too much noise peaking at low frequencies while maintaining low noise at high frequencies.

3.4.

Conclusion

In this chapter we discussed phase–locked loops at a system level. Loop stability, phase noise (both in–channel and out of channel), spurious tones, and loop settling time are the main issues to consider in a PLL design. Assuming that all of these issues are equally important, the fourth order PLL provides a good compromise, although a third order loop may suffice for many applications. In this chapter we focused on the design of single loop frequency synthesizers and introduced very simple design recipes for third and fourth order PLLs. In some applications we may need to use multiple loops to improve the overall performance, mainly the settling time and noise. Despite the increased complexity of such systems the design of each loop uses the same principles discussed in this chapter.

This page intentionally left blank

Chapter 4 FREQUENCY DIVIDERS

In the previous chapter we saw one of the main applications of frequency dividers. Frequency dividers are placed in the feedback path of phase–locked loops to synthesize a high frequency local oscillator (LO) from a precise low frequency crystal oscillator. Another important application for frequency dividers is to generate quadrature signals from a higher frequency signal [14]. Conventionally digital techniques are used for both purposes. However, as the frequency of operation approaches the limits of the technology, digital techniques become less attractive as they consume extensive power or even fail to operate. Therefore, at high frequencies purely analog techniques become more appropriate. In this chapter we survey some of the most popular digital and analog frequency division techniques and study injection–locked frequency division as a solution for very high frequency and low power applications.

4.1.

Digital frequency dividers

A digital frequency divider is in principle a counter. The main advantage of digital dividers over their analog counterparts is that they can be readily designed for variable division ratios and are easily cascaded to generate very large division ratios. General characteristics of these di-

42

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

viders are that they are wideband and their power consumption increases with the frequency of operation. Figure 4.1 shows a specific example of a divide–by–two frequency divider. It comprises two ring–connected D–latches. Details of latch design differ, depending upon the frequency of operation. At low frequencies CMOS logic is desirable. However, at high frequencies source– coupled logic (SCL) is preferred for two reasons. First, operation at higher frequencies is feasible with SCL latches. Secondly, power consumption in both CMOS and SCL latches, when designed properly, is proportional to age,

where

is voltage swing,

is supply volt-

is frequency, and C is total capacitance. Therefor, due to the

smaller voltage swing of SCL latches the power consumption can be reduced considerably at high frequencies. As mentioned earlier an important characteristic of digital dividers is the feasibility of implementing a variable division ratio. Fig. 4.2(a) shows the block diagram of a dual modulus divide–by–2/3 made of two D–flipflops, an AND gate, and an OR gate. The implementation of each flipflop is shown in Fig. 4.2(b). When the first flipflop (FF1) is isolated from the output. Therefore, the divider has only one state

Frequency Dividers

variable and divides by two. However, when two state variables and In steady state

43

there are

44

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

where the indices represent the cycle numbers. All the possible states and transitions are tabulated in Table 4.1 and shown in Fig. 4.3. Each circle in Fig. 4.3 represents one state, marked with the state variables In steady state there are only three feasible states and thus the divider divides by three. Flipflop FF2 in the dual modulus divide–by–2/3 frequency divider has a fanout of three (Fig. 4.2(a)), while the fanout of the divide–by–two divider (Fig 4.1) is two. Therefore, the maximum operational frequency of the dual modulus divide–by–2/3, made of the same latches as in the divide–by–two frequency divider, is lower by almost a factor of 1.5. Also, the dual modulus divide–by–2/3 divider has twice as many latches plus two additional gates, so its power consumption is more than twice the power of the divide–by–two divider. The maximum operational frequency of these dividers is determined by the speed of the latches. As mentioned earlier SCL latches can potentially operate at higher frequencies than their CMOS counterparts, with lower power consumption. An example of an SCL latch is shown in Fig. 4.4. The operation is as follows. When input, Clk, is high the signal on the D port is passed to the output over a bandwidth set by the output RC time constant, where R is the output resistance and C

45

Frequency Dividers

is the total output capacitance. As Clk transitions from high to low the cross–connected transistors M5 and M6 generate a negative conductance which provides regenerative feedback and latches the output. To find the maximum theoretical operational frequency of this latch assume that Clk is a square wave signal. Fig. 4.5 shows the SCL latch input (Clk) and output voltage

in a divide–by–

2 configuration at a very high operation frequency. Without loss of generality we assume that at where

Clk transitions from low to high and

is the output amplitude. For

where T is the period of Clk, the output increases exponentially

46

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

and

where

At

Clk transitions from high

to low and the output is

In the next half cycle

M5 and M6 provide a dif-

ferential negative conductance G at the output. For simplicity we ignore short channel effects and assume transistors are square law devices In this case the negative conductance as a function of the output voltage is

When

either M5 or M6 is turned off and G = 0. When

the output conductance is at its most negative value

47

Frequency Dividers

where

is the small signal transconductance of M5 and M6 biased with

a drain current of I/2. For simplicity we assume G is constant over the whole half cycle

With this assumption the output voltage

increase exponentially with time

where

At the end of the cycle

the output voltage

is

Eq. (4.4) and (4.7) result in

where

Now if we replace

where

is the overdrive voltage

by IR and recall that we can

rewrite Eq. (4.8) as:

To steer the current substantially from one branch of a differential structure to the other branch, the output amplitude should be greater than or equal to about

For every value for e.g., replace

Therefore,

(4.10) defines a minimum value for

or a maximum

at which the divider still functions. Assume that at a given ) the maximum value for by RC to get

is i.e.,

). Now

48

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

If we assume that the divider in Fig. 4.1 drives an identical divider, then

where

is the gate–source capacitance of M5 or M6

(Fig. 4.4). Thus

or

The normalized maximum operation frequency of this divider is plotted in Fig. 4.6 as a function of than

product, and is seen always to be less

In practice the maximum frequency of operation will

be even less than predicted by (4.13), because practical circuits do not satisfy the assumption of a perfect square law device and Clk will not be a perfect square wave. At higher frequencies analog techniques are the only solution. For this reason several relevant analog frequency division techniques are discussed in the following sections.

4.2.

Analog frequency dividers

An important characteristic that distinguishes analog frequency dividers from digital dividers is their narrower frequency range of operation. Digital dividers can be viewed as inherently lowpass systems while analog dividers can be bandpass in nature, and potentially operate at higher frequencies. With the right architecture and careful design, analog dividers can trade off bandwidth with power and maximum operational frequency. This trade–off is the key to design very high frequency and low power frequency dividers. Regenerative dividers, Fig. 4.7(a), are the most widely used analog frequency dividers [15],[16],[17], and operate by combining frequency multiplication in the feedback path with mixing at the input. Regenera-

49

Frequency Dividers

tive dividers can operate at frequencies close to

[14]. As mentioned

earlier, analog dividers may be bandpass systems. In the special case of a divide–by–two regenerative frequency divider, the theoretical maximum ratio of the highest frequency of operation to the lowest frequency of operation is less than three. In practice regenerative dividers require many functional blocks to guarantee proper operation [17]. Therefore, regenerative frequency dividers, although capable of operation at very high frequencies, are not the best solution for low power systems. Parametric frequency dividers, Fig. 4.7(b), are a group of analog frequency dividers often used in microwave systems [15], [18], [19]. The frequency division principle of a parametric frequency divider relies on exciting a varactor at frequency

and realizing a negative resistance

50

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

that sustains a loop gain of unity at

High

varactors and inductors

are key elements in parametric frequency dividers [19]. Therefore, a successful and fully integrated implementation of this kind of divider in contemporary silicon technologies is hard, if not impossible. A third group of analog frequency dividers uses injection locking. Conventionally injection locking is used to lock an oscillator to the fundamental or a higher harmonic of an incident signal [20],[21],[22],[23]. However, injection–locked oscillators can also serve as frequency dividers [24]. In the following sections we look at the history of injection– locked oscillators (ILOs) and develop a general theory for the operation and noise of injection–locked frequency dividers.

51

Frequency Dividers

4.3.

Injection–locked frequency dividers

An injection–locked frequency divider is an oscillator in which a harmonic of the oscillation frequency is locked to the fundamental frequency of the incident signal. The theory of injection locking or forced oscillation in nonlinear circuits was first studied by van der Pol in the early 1920s [25]. Adler [26] used a phasor diagram technique to model the behavior of an ILO locked to the fundamental frequency of an incident signal and defined a locking range figure of merit. The study of ILOs was later extended to an ILO with a subharmonic of the oscillation frequency locked to the incident frequency [20],[21],[22],[23]. Uzunoglu et al. [27] prefer the term synchronous oscillator (SO) for an injection–locked oscillator. They report frequency division with SOs without providing a physical model to explain the frequency division mechanism. Historically ILOs are named based on the ratio of the incident frequency

to the oscillation frequency

When the oscillation fre-

quency is the same as the incident frequency

the ILO is called

a first–harmonic ILO. When the incident frequency is a fraction of the oscillation frequency

the ILO is a subharmonic ILO. Finally,

when ILOs behave as frequency dividers, where the incident frequency is a harmonic of the oscillation frequency

they are called su-

perharmonic ILOs. We w i l l refer to this latter group as injection–locked frequency dividers. Regardless of the names and terms used for different classes of ILOs, all of the previously published work focused on small signal analysis and application of ILOs. In the following sections we eliminate restrictions on signal amplitude and develop a general theory for injection–locked frequency dividers (ILFDs). We also introduce an ILFD whose center frequency tracks the incident frequency, to extend the locking range. A noise analysis of the ILFD completes this chapter.

52

4.3.1.

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

Model for injection–locked frequency dividers

An ILFD is an oscillator with a forced oscillation. An oscillator can be modeled as a nonlinear block, followed by a frequency selective block (e.g., an RLC tank), in a positive feedback loop as shown in Fig. 4.8. The nonlinear block models all the nonlinearities in the oscillator, including any amplitude–limiting mechanism. In order to have a steady–state oscillation, a loop gain of unity should be maintained. As with conventional unforced oscillators, we may express the oscillation condition in terms of amplitude and phase criteria. The amplitude condition is satisfied if the output amplitude is the same as the input amplitude in an open loop excitation of the system at the oscillation frequency

53

Frequency Dividers

The phase condition requires that the excess phase introduced in the loop at be zero. With an additional external signal (i.e., the incident signal) this same model can be applied to an ILFD (Fig. 4.9). The nonlinear block is now a function of two variables

To investigate the injection locking

phenomenon in an ILFD, we define:

where

is the incident signal,

is the output signal,

difference between those two signals, and

and

is the phase

are the resonant

frequency and loaded quality factor of the RLC tank, respectively. The output of the nonlinear block,

generally contains various harmonic

and intermodulation terms of

and

As shown in appendix A,

we can write

as:

where each

is an intermodulation coefficient of

We assume that all frequency components of far from the resonant frequency of the tank are filtered out, so the frequency of the output signal can be written as

Thus, we need only consider

intermodulation terms with frequency

that is,

an N-th order ILFD (i.e.,

For

the intermodulation terms with

possess a frequency equal to

of the incident frequency.

54

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

The signal

which is the component of

with frequency

can be written as:

Using a complex exponential to replace sines and cosines, and applying the oscillation condition, the output signal can be written as:

or

The imaginary and real parts of (4.21) can be equated separately to yield:

Equations (4.22) and (4.23) are the fundamental equations for an N-th order ILFD. The simultaneous solution of these two equations specifies and

for any incident amplitude

equivalently, for any offset frequency can be rearranged as:

and any incident frequency

or,

Equation (4.22)

55

Frequency Dividers

where

is Adler’s locking range figure of merit [26]. The

fundamental equations, (4.22) and (4.23), are very general, but provide limited intuition. However, as shown in the next section, (4.22) and (4.23) can be solved analytically for special cases which allow the development of design insight. 4.3.1.1

Divide–by–two ILFDs with third and fourth order nonlinear functions

In many cases the ILFD nonlinearity can be approximated with a polynomial function of the sum of the two variables . In this case if we limit the order of the nonlinearity to three (i.e., the only unknown in (4.22) for a divide–by–two ILFD (N = 2) is the input-output phase difference, The phase condition thus can be satisfied independently of the amplitude condition:

and

On the other hand, solving (4.23) results in an expression for the oscillation amplitude:

As (4.25) suggests, a larger incident amplitude as well as a larger result in a larger achievable locking range,

In an LC oscillator

so the largest practical inductance should be used if maximizing the locking range is the objective. Increasing the incident amplitude

56

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

increases the locking range as long as there exists a solution for (4.26),

The term

represents the oscillator small signal loop gain and has to

be larger than unity for an oscillator to start oscillating. The coefficient of the third order nonlinearity,

has to be less than zero to reduce the

loop gain as the oscillation amplitude grows and thus limit the oscillation amplitude (Appendix C). Therefore, (4.27) simplifies to:

In practice the locking range can be phase limited (limited by the failure of (4.25)), or amplitude limited (limited by (4.28) failure). An amplitude limited locking range is only observed at large incident amplitudes, with an oscillation amplitude at the edge of the locking range even smaller than the free running oscillation amplitude. Therefore, a phase limited locking range can be distinguished from an amplitude limited locking range by its relatively large output amplitude at the edge of the locking range. A strong quadratic nonlinearity

also increases the lock-

ing range of a divide–by–two ILFD. Therefore, circuit topologies with a dominant second order nonlinearity (e.g., the differential ILFD in section 5.1) are favorable for wide locking range divide–by–two ILFDs. A counterintuitive result of (4.25) is that the locking range does not depend on the tank quality factor, . . One would expect that a lower results in a larger locking range as the total 180° phase variation of the tank circuit spans a larger frequency range. That is, we would think that a circuit with a lower

, being less frequency selective, should

provide a larger locking range. The

–independence of locking range

57

Frequency Dividers

is indeed unusual, and holds only for a third order nonlinear system. If we repeat the preceding analysis with a fourth order nonlinear function we observe the expected Q dependence of the locking range. In this case Eq. (4.22) and (4.23) simplify to:

and

The right hand side of (4.29) is the same as that of (4.25) with an additional term from the fourth order nonlinearity. In this case the locking range not only depends on and the incident amplitude, but also on the oscillation amplitude,

A larger tank Q results in a

larger oscillation amplitude and thus reduces the locking range if In Appendix C the nonlinearity of a single–ended bipolar oscillator is approximated with a fourth order polynomial function. The identified nonlinear coefficients satisfy the above assumption. Another important observation is that, unlike an ILFD with a third order nonlinearity, the locking range is not a linear function of the incident amplitude. Because of the

term in (4.29), the locking range is sub–linear and is less

than what is predicted by (4.25). The difference, of course, is more obvious at large incident amplitudes. Finally the locking range in an ILFD is a function of the incident amplitude. So, by injecting the incident signal into a high–impedance node, the required incident power can be reduced significantly. Due to the high impedance of the gate of MOS transistors, MOS transistors are a good candidate for injection–locked oscillators.

58

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

4.3.2.

Tracking injection–locked frequency dividers

The previous section discusses different design techniques to increase the locking range of an ILFD. All those methods follow from the fundamental equations (4.22) and (4.23). The underlying assumption in the derivation of (4.22) and (4.23) is that the resonant frequency of the LC tank is constant. In a tracking ILFD we intentionally violate this assumption to achieve a wider locking range [28]. Fig. 4.10 illustrates the idea of a tracking ILFD. The free–running oscillation frequency of the tracking ILFD is tuned with a varactor and its control voltage is tied to that of the voltage– controlled oscillator (VCO) that supplies the incident signal. Thus the center frequency of the ILFD tracks the incident frequency (VCO frequency).

This additional frequency tuning capability of the tracking

ILFD increases its locking range beyond what is achieved with a fixed tank frequency.

4.3.3.

Noise in injection–locked frequency dividers

In order to investigate the phase noise performance of an ILFD, we first consider the response of a first–harmonic ILO to a deterministic sinusoidal noise input. For simplicity we assume proximated by noise,

can be ap-

Fig. 4.11 shows the simplified model with the

added to the summing junction. The noise can either come

Frequency Dividers

59

from the incident signal, or from the ILO itself. The incident signal, output signal, and sinusoidal noise are represented by their equivalent phasors in Fig. 4.12, and mathematically defined as:

60

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

In the absence of noise, the input–output phase difference is constant when the output signal is injection–locked to the incident signal. However, when sinusoidal noise at an offset frequency added to the system, frequency,

is

is no longer constant and the instantaneous output

is defined as:

It is the variation of which generates phase noise in the output signal. As shown in Appendix B, can be approximated as:

where

is the difference between the incident frequency and the free– and °

running frequency,

The input–output phase

difference can be written as:

where

is the input–output phase difference in the absence of noise

and is a constant variant portion of

from (B.10)), and When

and

the input–output phase difference are very small can be simplified to:

is the time–

the fluctuations of and (4.35)

61

Frequency Dividers

where

If

implying that the incident frequency is not at the

edge of a phase limited locking range, K can be approximated as:

which allows simplification of (4.37) to a first–order differential equation:

The noise transfer function from

to the output phase is shown in

Fig. 4.13. From Eq. (4.40) and Fig. 4.13 it is clear that an ILO has the same noise transfer function as a first–order PLL. The noise from the incident signal is shaped by the lowpass characteristic of the noise transfer function and the output signal tracks the phase variations of the incident signal within the loop bandwidth

However,

unlike a first–order PLL, the loop bandwidth of an ILO is a function of the incident amplitude and is larger for a larger incident amplitude. The interpretation of the noise transfer function is a little different if the noise comes from the ILO itself. Within the loop bandwidth the noise from the ILO is suppressed by the ratio of the noise power to the incident power. Outside the loop bandwidth the noise suppression increases by 20 dB per decade of offset frequency and a

phase noise region is

observed. The noise behavior in an N-th order ILFD is the same as that of a first–harmonic ILO, except that the frequency division operation causes

62

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

to be

of that in a first–harmonic ILO. So (4.40) for an N–th order

ILFD can be modified as:

where

is no longer a simple function of

but is determined by solv-

ing the fundamental ILFD equations (4.22) and (4.23). As the division ratio N increases the noise rejection increases proportionally. So in a divide–by–two ILFD the output close–in phase noise is lower than that of the incident signal. The fact that the ILFD close–in phase noise is determined by the phase noise of the incident signal has important implications for very low power frequency dividers, just as it does for any other frequency divider.

4.4.

Summary

In this chapter we have discussed different frequency division techniques and explained the tradeoffs and application of each method. We explained that at high frequencies (e.g., higher than

analog tech-

Frequency Dividers

63

niques become more attractive than digital methods. Among all analog frequency dividers, injection–locked frequency dividers can potentially operate at a higher frequency and with a lower power consumption. The reason is hidden in the nature of the injection–locked frequency dividers: An ILFD is an oscillator capable of operation at frequencies approaching of the technology. We also developed a general theory for injection–locked frequency dividers which elucidates the frequency division mechanism of an ILFD based on intermodulation of the input and output signals. This model predicts for the first time the possibility of injection locking failure at large incident amplitudes. It also provides direct design insight on how to maximize the locking range of an ILFD. Finally we derived a first order differential equation which describes the noise performance of an ILFD.

This page intentionally left blank

Chapter 5 EXPERIMENTAL INJECTION–LOCKED FREQUENCY DIVIDERS

In this chapter we introduce two circuit topologies (single–ended and differential) for divide–by–two injection locked frequency dividers. Both topologies are fully integrated in standard CMOS processes. The single–ended topology was initially designed and fabricated as a proof of concept and was not targeted for any specific application nor optimized for power consumption. However, the differential architecture was designed to be used as a tracking ILFD in a 5 GHz frequency synthesizer as will be discussed in chapter 6. The organization of this chapter is as follows. We first describe the two circuit topologies and explain their operation. Since on–chip inductors are a critical part of the design we discuss their optimization next. Finally, measurement results followed by a summary conclude this chapter.

5.1.

Circuit topologies

Fig. 5.1 shows the schematic of a single–ended injection–locked frequency divider (SILFD). For simplicity the biasing circuitry is not shown in this figure. A Colpitts oscillator forms the core of the SILFD. The incident signal is injected into the gate of M1. Transistors M1 and M2 are used in cascode, mainly to provide more isolation between the input and

66

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

output (drain of M2). Transistor M2 is sized to be smaller than Ml by almost a factor of three to reduce the parasitic capacitance at the output node. As a result a larger inductor can be used to resonate this reduced capacitance. As discussed in section 4.3.1.1, using a larger inductor increases the locking range. The power consumption is also reduced due to the increased effective parallel impedance of the LC tank, assuming that tank losses are mainly from the inductor. Lastly,

and

in the

gate of M1 are used to model the LC tank of the preceding LC oscillator. The isomorphism of this circuit with the model in Fig. 4.9 can be understood by observing that transistor M1 functions as the nonlinear block. The incident and output signals are summed across the gate and source of M1 before they excite the oscillator nonlinearity. Therefore, in this circuit The schematic of a differential tracking ILFD (DILFD) is shown in Fig. 5.2. The incident signal is injected into the gate of M3 and de-

Experimental injection–locked frequency dividers

67

livered with a sub–unity voltage gain to node Vx, the common source connection of M1 and M2. The output signal is fed back to the gates of M1 and M2 and summed with the incident signal across the gates and sources of M1 and M2. In this circuit, node Vx moves at twice the frequency of the output signal even in the absence of the incident signal. Therefore, this circuit has a dominant second order nonlinearity. As mentioned in section 4.3.1.1 a large quadratic nonlinearity increases the locking range of a divide–by–two ILFD. Thus the DILFD is a good candidate for a divide–by–two ILFD when the incident signal is effectively injected into node Vx. To further improve the locking range of the DILFD accumulation mode MOS varactors [29], [30] are used to realize a tracking ILFD (section 4.3.2).

Inductors in both circuits are on–chip planar spiral inductors with patterned ground shields [31]. The inductors are designed to maximize the locking range of the ILFD and also reduce the power consumption. As mentioned in section 4.3.1.1 the largest practical inductance L maximizes the locking range. However, reduction of power consumption demands maximization of the effective parallel impedance of the RLC tank. Assuming inductors are the main source of loss, the effective parallel impedance of the tank equals

and is thus the largest when the

LQ product is maximized. On the other hand the inductor has its largest value when the total capacitance that resonates with it is minimized. Assuming the external capacitances are already minimized, the only remaining parameter is the inductor parasitic bottom plate capacitance. To reduce this latter capacitance, the inductor should be laid out with narrow lines using the topmost metal. However, the large series resistance of narrow metal strips degrades the inductor quality factor and reduces the LQ product significantly. Therefore, both L and the LQ product may not

68

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

be maximized simultaneously for an on–chip spiral inductor resonating with a fixed capacitance. To design the spiral inductors, we use a

model for an inductor as

reported in [32]. Fig. 5.3 shows the top view of a square planar spiral inductor as well as the

model used in our design. Design parameters

are the inductor metal width (W), metal spacing

number of turns (n),

and outer dimension (OD). Resistor Rs represents the resistive loss in the inductor metal strips (including skin effect) as well as the substrate magnetic loss (Appendix D, Eq. D.9). Capacitors Cp1 and Cp2 model the parasitic capacitance between the inductor layer and the effective substrate (here, the ground shield). The parallel combination of Rsi and Csi model the substrate. If a ground shield is used Rsi and Csi need not

69

Experimental injection–locked frequency dividers

be modeled and Cp1 and Cp2 are grounded. Capacitance Cs models both the inter–winding capacitance and the capacitance between the inductor top metal layer and the under–pass metal used to gain access to the inner terminal of the inductor (Appendix D, Eq. D.3) . The inductance L is first approximated with a monomial expression (Appendix D, Eq. D.6) [33], then optimization used to find the maximum inductance such that the LQ product is large enough to satisfy the specified power budget. Notice that maximizing L with a fixed LQ product also minimizes Q. This minimized Q further increases the locking range as discussed in section 4.3.1.1.

5.2. Measurement Results 5.2.1. Single–ended ILFD The SILFD shown in Fig. 5.1 is designed in a

CMOS technol-

ogy and operates on 2.5 V at a bias current of 1.2 mA. The free–running frequency of oscillation is 920 MHz and the incident frequency is around 1840 MHz. The die micrograph of the SILFD is shown in Fig. 5.4. The total die area, including pads, is

(0.7 mm × 1 mm).

70

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

The measured locking range as a function of incident amplitude is shown in Fig. 5.5. A maximum locking range of more than 190 MHz (11% of the center frequency) is achieved when consuming 3 mW of power. Notice that increasing the incident amplitude initially increases the locking range, as predicted by (4.25). However, as the incident signal goes beyond 250 mV, amplitude condition (4.28) fails prior to the phase condition and the locking range decreases. The measured maximum achievable locking range at different bias currents is shown in Fig. 5.6. Although this circuit was designed to prove the concept of injection–locked frequency division and was not optimized for the minimum power consumption, a locking range of more than 135 MHz is achieved with less than 600

bias current.

Experimental injection–locked frequency dividers

71

The phase noise of the SILFD is measured both in free–running and injection–locked modes (Fig. 5.7). The thin solid line in this figure shows the phase noise of the free–running SILFD. The thick solid line is the phase noise of the HP8664A signal generator used as the incident signal. The non–solid lines are the phase noise measurement of the SILFD when locked to three different incident frequencies, referred to as middle frequency, phase limited, and amplitude limited curves. The middle frequency curve is the output phase noise measured at an incident frequency in the middle of the locking range. The phase limited and amplitude limited curves are measured when the incident frequency is at the edge of a phase limited and amplitude limited locking range, respectively.

72

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

At low offset frequencies the divider output phase noise is almost 6 dB lower than the incident phase noise, as is expected from the divide– by–two operation and predictions of (4.41). However, at higher offset frequencies the excess noise from the divider itself and the following buffers increases the output phase noise. The far out phase noise at the edge of the amplitude limited locking range is even worse than the phase noise of the free–running oscillator because of the small oscillation amplitude at this edge. Despite the large phase noise of the free–running ILFD, the divider close–in phase noise tracks the phase noise of the incident signal. As a result an ILFD can be designed for very low power operation, without sacrificing the noise performance of the system. Also very low Q on–

Experimental injection–locked frequency dividers

73

chip spiral inductors, with small physical dimensions, can be used in an ILFD.

5.2.2.

Differential tracking ILFD

A differential tracking ILFD of the type shown in Fig. 5.2 is designed in a CMOS technology. The chip shown in Fig. 5.8 has an area of excluding the pads. In the free–running mode, the oscillator is biased with and The free–running oscillation frequency as a function of the control voltage is shown in Fig. 5.9. The tuning range is about 110 MHz of the center frequency) for a 1.5 V control voltage variation. For divide–by–two operation the supply voltage is set to 1.5 V and the tail current is reduced to However, because of the partial recti-

74

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

Experimental injection–locked frequency dividers

75

fication of the incident signal the average tail current increases beyond Fig. 5.10 shows the operational frequency range of the divider as a function of the incident amplitude for two different control voltages. For a given incident amplitude the operation region lies between the two ends of each curve in Fig. 5.10. By increasing the control voltage the resonant frequency of the LC tank increases and moves the operation region up in frequency. tude for two different control voltages. The locking range increases with the incident amplitude but it is not a linear function of the incident amplitude, just as predicted by (4.29). For a given control voltage, a greater

76

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

than 1150 MHz ( range is achieved when

of the center frequency) input–referred locking Addition of tank tuning increases

the total achievable locking range to greater than 1260 MHz (

of

the center frequency) at this incident amplitude. Higher incident amplitudes are not tested due to instrument limitations. As expected, changing the control voltage changes only the operational frequencies and not the locking range. Unlike the single–ended ILFD reported in the previous section, the locking range in a DILFD is phase limited and monotonically increases with incident amplitudes even as large as 1.5 V. This difference can be attributed to the fact that the voltage gain of M3 in Fig. 5.2 is less than unity and the amplitude of the incident signal at the summing node (the common source connection of M1 and M2) is less than that

Experimental injection–locked frequency dividers

77

on the gate of M3. The amplitude limited region of the locking range, which is observed only at large incident amplitudes, therefore appears at larger input levels. Compounding this effect is that the increased average tail current (in a DILFD) in the presence of a large incident signal changes the DILFD nonlinearity and effectively moves the amplitude limited region of the locking range to larger incident amplitudes. The average power in the DILFD as a function of the incident amplitude is shown in Fig. 5.11. The average power at 400 mV incident amplitude is less than 0.55 mW while the input referred locking range exceeds 600 MHz (> 12%).

Fig. 5.12 shows the test setup for the DILFD phase noise measurement. The phase noise measurement results are shown in Fig. 5.13. The solid line shows the phase noise of the HP83732B signal generator used as the incident signal. The dashed line is the phase noise of the free– running DILFD. The other two curves are the phase noise of the DILFD when locked to two different incident frequencies. The curve marked as middle frequency is measured when the incident frequency is in the middle of the locking range and the edge frequency curve is measured at the lower edge of the locking range. Like the SILFD, at low offset

78

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

frequencies the output of the frequency divider follows the phase noise of the incident signal and is 6 dB lower due to the divide–by–two operation. At larger offset frequencies the added noise from the output buffer, the external amplifier (Fig. 5.12), and from the divider itself reduces the 6 dB difference between the incident and output phase noise. Phase noise measurements for offset frequencies higher than 300 kHz are not accurate due to the dominance of noise from the output buffer and the external amplifier. As discussed earlier the locking range of the DILFD is always limited by the failure of the phase condition. Therefore, the phase noise degradation observed at the edge of the amplitude limited locking range of the SILFD is not an issue for the DILFD.

Experimental injection–locked frequency dividers

79

Table 5.1 summarizes the performance of the DILFD. The power consumption of two flipflop–based frequency dividers at 5 GHz is also listed for comparison purposes. In a

CMOS technology a simulated

SCL flipflop–based frequency divider loaded with the same capacitance as in the DILFD, consumes almost an order of magnitude more power than the DILFD with a 600 MHz locking range. The measurement results for a fast flipflop–based divider in an advanced

CMOS

technology show a power consumption of 2.6 mW at 5 GHz [34] which is still more than four times the power of the

DILFD with a

600 MHz locking range.

5.2.3.

Noise transfer function

In order to verify the noise dynamics derived in section 4.3.3, the SILFD is injection locked to an incident frequency while a second signal is injected at an offset frequency from the incident frequency. As demonstrated in Fig. 5.14, two sidebands are generated in the output signal spectrum. The sideband power relative to the carrier is measured at different offset frequencies and is shown in Fig. 5.15 and 5.16. In

80

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

Fig. 5.15 the incident power,

is constant and the noise transfer func-

tion is measured for three noise power levels,

As predicted by (4.41),

reducing the noise power by 3 dB shifts the noise transfer function curve down by the same amount. The measurements are repeated for different incident powers, while keeping the noise power constant. The results are shown in Fig. 5.16. When the incident power increases by 3 dB both the loop bandwidth and the close–in noise rejection increase by 3 dB, while the far out noise does not change. The noise transfer function measurement results of Fig. 5.15 and 5.16 are in very good agreement with (4.41).

Experimental injection–locked frequency dividers

5.3.

81

Summary

In this chapter we presented two circuit topologies for divide–by-two injection–locked frequency dividers. The single–ended ILFD clearly demonstrates the two failure mechanisms of injection locking. At small incident amplitudes the locking range is limited by the failure of the phase condition, while failure of the amplitude condition is the reason for the loss of injection locking at large incident amplitudes. On the other hand, the locking range of the differential ILFD is always phase limited even for incident amplitude as large as 1.5 V. Therefore, the DILFD has superior phase noise performance over the SILFD at the edge of the locking range for all incident amplitudes. Furthermore, the strong second order nonlinearity of the DILFD extends its locking range in a divide–by–two operation.

82

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

The design of the on–chip inductors was optimized to increase the locking range while reducing the power consumption. Under this objective, inductors were designed with a maximum inductance, L, and minimum quality factor, Q, for a given LQ product at the frequency of operation. To extend the locking range of the DILFD even further, the resonant frequency of the output circuit was tuned in a tracking ILFD configuration. The combination of the frequency tuning capability and optimized inductors resulted in a locking range of more than 26% for less than 1 mW of power consumption. The power consumption of the DILFD is reduced to about 0.5 mW for a 15% locking range (including the frequency tuning of the tracking ILFD).

Chapter 6 AN EXPERIMENTAL 5GHZ FREQUENCY SYNTHESIZER

In the previous chapters we discussed system level design issues of a frequency synthesizer. We also studied the design of very low power frequency dividers. In this chapter we use the knowledge of the previous chapters to implement a low power frequency synthesizer for a U–NII band WLAN receiver (chapter 2). Frequency synthesizers usually consume a large percentage (20–30%) of the total receiver power (Table 6.1). As mentioned in chapter 3 a typical PLL–based frequency synthesizer comprises both high and low frequency blocks. The high frequency blocks, mainly the VCO and first stage of the frequency dividers, are the main power consuming blocks, especially in a CMOS implementation. Therefore, BiCMOS technologies have often been chosen over CMOS, where the VCO and the prescaler are designed with bipolar transistors and the low frequency blocks are CMOS [35]. Off–chip VCO’s and dividers have also been used as an alternative [7]. However, because of the increased cost neither of these two solutions is suitable for many applications, and a fully integrated CMOS solution is favorable. A dividerless frequency synthesizer [36] that eliminates power hungry frequency dividers is one solution for such

84

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

low power and fully integrated systems. In this technique an aperture phase detector is used to compare the phase of the reference signal and the VCO output at every rising edge of the reference signal only for a limited time window that is a small fraction of the reference period. Thus, no frequency divider is required in this PLL. The idea of a dividerless frequency synthesizer, although suitable for systems such as a GPS receiver where only one LO signal is required, is not readily applied to wireless systems which require multiple LO frequencies with a small frequency separation.

An experimental 5GHz frequency synthesizer

85

In chapter 2 we mentioned the increasing demands for WLAN systems that can support data rates in excess of 20 Mb/s with very low cost and low power consumption. We also discussed the existing standards for such high data rate systems at 5 GHz. In this chapter we describe the design of an integer–N frequency synthesizer as a local oscillator (LO) for a U–NII band WLAN receiver. To stay compatible with HIPERLAN, we divide the lower 200 MHz of the U–NII spectrum into 8 channels that are 23.5 MHz wide, leaving 12 MHz for guard bands. The minimum signal level in a class C receiver is –70 dBm while the maximum strength of the received signal is –25 dBm (Table 2.2). The large dynamic range and wide channel bandwidth of this system set very stringent requirements for synthesizer phase noise and spurious sideband levels. The synthesizer is fully integrated in a standard CMOS process. The front–end of the receiver is described in detail in [40] and its simplified version is shown in Fig. 6.1. This double conversion architecture is known as a Weaver architecture. This architecture rejects the image signal without any external image reject filter. However, it requires fairly accurate quadrature LOs to perform the image rejection. To reject the image by more than 41 dB the phase error between the quadrature LOs should be less than 1° [8], assuming zero gain mismatch.

6.1.

Proposed synthesizer architecture

Our proposed architecture (Fig. 6.2) is an integer–N frequency synthesizer with an initial low power divide–by–two in the PLL feedback path. The prescaler follows the fixed frequency divider and operates at half the output frequency and thus its power consumption is reduced significantly. Furthermore, the first divider is an injection–locked frequency divider (chapter 4) which takes advantage of the narrowband nature of the system and trades off bandwidth with power via the use of resonators.

86

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

To further reduce the power consumption, optimization techniques are used to design the on–chip spiral inductors of the VCO and ILFD. Because of the fixed initial divide–by–two in the loop, the reference frequency in our system is half of the LO spacing and is 11 MHz. Consequently, the loop bandwidth is reduced to maintain the loop stability. This bandwidth reduction helps to filter harmonics of the reference signal (mainly the second harmonic) which generate spurs in the middle of the adjacent channels. The drawbacks of a reduced loop bandwidth are an increased settling time and a higher in–band VCO phase noise. The higher in–band VCO phase noise is not a limiting factor here as the in–band noise is dominated by the upconverted noise of the reference signal (section 3.3). The slower settling time is only a problem in very fast frequency hopped systems. The synthesized LO frequency in our system is of the received carrier frequency. This choice of LO frequency not only eases the issue of image rejection in the receiver [40], but also facilitates the generation of the second LO, which is of the first LO, with the same synthesizer.

6.2. 6.2.1.

Synthesizer building blocks Voltage–controlled oscillator

To generate the accurate quadrature LO signals required for the Weaver architecture we have used the quadrature VCO of Fig. 6.3(a) [41]. This VCO consists oftwo mutually coupleddifferential VCO’s, markedinside the dashed squares. Each VCO is made of two cross-coupled transistors, (M1, M2) and (M3, M4), to generate the negative conductance required to cancel the losses of the RLC tanks. Transistors M5–M8 couple the two VCO’s. These two VCO’s oscillate at the same frequency but in quadrature phases. The two VCO’s, with their coupling transistors, can be pictured as two differential buffers in a ring structure as shown in

An experimental 5GHz frequency synthesizer

87

Fig. 6.3(b). A sustained oscillation of the ring requires a zero phase shift across the ring. The inverting structure of the loop introduces 180° of phase shift. Therefore, each buffer should introduce an additional 90° phase shift to provide the overall zero phase shift in the ring. The two VCO’s thus oscillate in quadrature. As mentioned before, the symmetry of the VCO structure defines the quadrature accuracy of VCO outputs and thus the total receiver image rejection. Therefore, it is important to sustain the VCO symmetry in a perfectly symmetric layout. On–chip spiral inductors with patterned ground shields [31] are used in this design. The two main requirements for the VCO are low phase

88

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

noise and low power consumption. If the inductors were the main source of noise, maximizing their quality factor would improve the phase noise significantly. However, in multi–GHz VCO’s with short channel transistors, inductors are generally not the main source of noise although

An experimental 5GHz frequency synthesizer

89

they are still the main source of loss in the RLC tank. Therefore, a better design strategy is to maximize the effective parallel impedance of the RLC tank at resonance. With a maximized tank impedance the oscillation amplitude is maximized for a given power consumption and thus the phase noise due to the noise of active devices is reduced. Since inductors are the main source of loss in the tank, the LQ product should be maximized to maximize the effective parallel impedance of the tank at resonance, where L is the inductance and Q is the quality factor of the spiral inductors. It is important to realize that maximizing Q alone does not necessarily maximize the LQ product, and it is the latter that matters here. To design the spiral inductors, we use the same inductor optimization technique explained in chapter 5 with the objective to find inductors with the maximum LQ product. The inductors in this design are 2.3 nH each with a quality factor of 5.6 at 5 GHz. It is worth mentioning that at 5 GHz, the magnetic loss in the highly doped substrate of the epi process reduces the inductor quality factor significantly. Approximate calculations [42] show that substrate inductive loss is proportional to the cube of the inductor’s average diameter (Eq. D.9). Therefore, a multi– layer stacked inductor which has a smaller area compared to a single layer inductor with the same inductance may achieve a larger quality factor. We should mention that in this design, inductors are laid out using only the top–most metal layer. The varactors in Fig. 6.3 are accumulation mode MOS capacitors [29], [30]. The quality factor of these varactors can be substantially degraded by the gate resistance of the structure, if the varactors are not laid out properly. In this design each varactor is laid out with 21 fingers each of which is wide and long. The quality factor of this varactor

90

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

at 5 GHz is estimated to exceed 60. The losses of the RLC tank are thus dominated by the inductors, as expected.

6.2.2.

Injection–locked frequency divider

The same differential tracking ILFD discussed in chapter 5 is used in this design and is shown in Fig. 6.4. The only modification is the dummy transistor M4 to provide a symmetric load for the differential VCO which drives the ILFD. The inductors of the ILFD are 10.5 nH with a quality factor of 3.6 at 2.5 GHz.

An experimental 5GHz frequency synthesizer

6.2.3.

91

Programmable frequency divider

Fig. 6.5 shows the block diagram of the programmable frequency divider known as a pulse swallow frequency divider. The pulse swallow frequency divider

consists of a

prescaler followed by

a program and swallow counter. Only one CMOS logic ripple counter is used for both the program and pulse swallow counters (Fig. 6.6). The program counter generates one output pulse for every P input pulses to the counter. The output of the swallow counter (MC) switches the division ratio of the prescaler and is controlled by five binary coded channel–select bits (Ch1–Ch5). At the beginning of the cycle MC = 1 and the prescaler divides by N + 1. After S + 1 cycles, with S determined by the channel select bits, MC is set to zero and the prescaler divides by N for the rest of the cycle. Therefore, the overall division ratio is M = NP + S + 1. Flipflops FF1 and FF2 in Fig. 6.6 are used to set and reset MC at the falling edges of the C1k. Therefore, the set and reset of MC are independent of the delays of the ripple counter and the logic gates. Also, because of FF2 the system can tolerate a total delay of as large as one C1k cycle before its operation fails.

92

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

The first step in the design of a pulse swallow frequency divider is to select the values of N, P and S. One constraint in this process is The second constraint is set by the required minimum power consumption. Conventionally a prescaler is designed by cascading dual modulus frequency dividers and fixed frequency dividers to get the desired division ratio (Fig. 6.7). Each dual modulus (e.g., a divide– by–2/3) generally burns more than twice the power of a divide–by–2 (section 4.1). Therefore, to minimize the power consumption of the prescaler, it should consist of no more than one dual modulus divider, which means N is an integer power of two. Finally the last constraint is the overall division ratio. In this design the overall division ratio of the pulse swallow frequency divider is an integer number between 220 and 227. The selected values of N, P, and S based on the preceding

An experimental 5GHz frequency synthesizer

93

discussions are N = 8, P = 26, and S is an integer between 11 and 18 to select any of the eight channels. The prescaler consists of one dual modulus divide–by–2/3 and two divide–by–2 frequency dividers made of SCL flipflops and gates (Fig. 6.7). The modulus control (MC) input selects between divide–by–8 and divide– by–9. To divide by eight, MC is set to zero and the dual modulus divider divides by two. When MC=1 the dual modulus divider divides by three only once per output cycle and therefore the overall division ratio is nine. Fig. 6.8 shows the prescaler input as well as outputs of each divider over one output cycle when the prescaler divides by nine. The shaded area in this figure marks the time when the dual modulus divider divides by three and swallows one input cycle.

94

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

The block diagram of the dual modulus divide–by–2/3 is shown inside the dashed square in Fig. 6.7. The advantage of this structure over the conventional implementation of the divide–by–2/3 shown in Fig. 4.2 is its simpler and more symmetric layout, rather than speed as mentioned

An experimental 5GHz frequency synthesizer

95

in [43]. To reduce the prescaler power consumption, the current of each NOR gate is shared with the following flipflop. Fig. 6.9 shows the circuit implementation of the NOR/flipflop of the dual modulus divider. Unlike the implementation of the NOR/flipflop in [43] this implementation is fully differential and symmetric with respect to both NOR inputs. In addition, no extra reference voltage is required for the NOR gate in our implementation. All of the flipflops, including those used in the CMOS counters, are triggered by the falling edges of their input clocks, allowing a delay of as much as half the period of the input of each divider. With this arrangement we guarantee overlap between Out, and MC (Fig. 6.7) at the right time and prevent a race condition.

6.2.4.

Phase/frequency detector

Fig. 6.10 shows the block diagram of the phase/frequency detector. Flipflops FF1 and FF2 are falling edge–triggered D–flipflops with their D input connected to Vdd. The clock of FF1 is connected to the reference signal, R, and FF2 is clocked with the output of the program counter, V. If the falling edge of R arrives before the falling edge of V, output U is set to speed up the VCO. In a different scenario if the falling edge of V arrives prior to the falling edge of R the VCO is faster than the reference signal and D is set to slow down the VCO. In either condition the falling edge of the late signal resets both U and D. The next cycle starts with the next falling edge of V or R. The two inverters in the reset path generate enough delay to eliminate the dead zone of the charge pump [44]. The implementation of the phase/frequency detector at the gate level is shown in Fig. 6.11. In order to reduce the skew between the complementary output signals, and

complementary pass gates are used to match the delay

96

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

of a single inverter in the output stage of the phase/frequency detector (Fig. 6.11).

An experimental 5GHz frequency synthesizer

6.2.5.

97

Charge pump and Loop filter

Fig. 6.12 shows the circuit diagram of the charge pump and loop filter. In this charge pump the up and down current sources are always on and transistors M1–M4 are used as switches to steer the current from one branch of the charge pump to the other. The charge pump has a differential architecture, but only a single output node, drives the loop filter. To prevent node

from drifting to the rails when neither

of the up and down signals (U and D) is active, a rail to rail unity gain buffer of the kind shown in Fig. 6.13 is placed between the two output nodes. This buffer keeps the two output nodes at the same potential and thus reduces the systematic charge pump offset. Transistors M5–M8 are used to reduce the charge injection into the VCO control line by the up and down signals. The power of the synthesizer spurious sidebands is thereby reduced. To compensate the finite output impedance of the up and down current sources and match their currents more precisely over all output voltages,

98

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

the up and down currents are monitored in a replica circuit. A feedback network measures the output voltage, voltage of the replica circuit,

and compares it with the

and thereby equates the up and down

currents at every output voltage. Fig. 6.14 shows the simulated systematic percentage mismatch between the up and down currents as a function of the output voltage. The percentage error for is less than 0.05% and increases to less than

for

With the loop filter shown in Fig. 6.12 we have a fourth order PLL. Table 6.2 summarizes the values of the loop parameters. The loop has a phase margin of 49°. As shown in chapter 3 a phase margin of about 50° minimizes the loop settling time for a given loop bandwidth. With

An experimental 5GHz frequency synthesizer

99

this phase margin and a crossover frequency of 60 kHz the settling time to a 10 ppm accuracy is less than Fig. 6.15 shows the calculated VCO phase noise due to the thermal noise of resistors and using Eq. 3.39 and 3.40. The calculated contribution to VCO phase noise at 22 MHz offset frequency is –149 dBc/Hz, which is negligible compared to the intrinsic noise of the VCO.

6.3.

Measurement Results

The frequency synthesizer is designed in a CMOStechnology. Fig. 6.16 shows the die micrograph of the synthesizer with an area of 1 mm × 1.45 mm, including pads. The VCO layout is symmetrical

100

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

(Fig. 6.16) to minimize the phase error between the VCO quadrature outputs. The synthesizer can operate with a single 2 V supply. However, to demonstrate the feasibility of sub 2 V analog design in a conventional CMOS process, the analog blocks (VCO, ILFD, and prescaler) are supplied by 1.5 V while the digital portions of the synthesizer are supplied by 2 V.

The quadrature VCO consumes 12 mW of power and has more than 550 MHz (11% of center frequency) of frequency tuning range (Fig. 6.17). The phase noise of the synthesized signal is shown in Fig. 6.18. The phase noise at small offset frequencies is due mainly to the phase noise of the reference signal multiplied by the synthesizer frequency multiplication factor. The phase noise measured at offset frequencies beyond the PLL bandwidth is the inherent VCO phase noise. The phase noise at 22 MHz offset frequency, which is the center of the adjacent channel,

An experimental 5GHz frequency synthesizer

101

is less than –134 dBc/Hz. The noise of the VCO, integrated over the bandwidth of the received signal (23.5 MHz) centered at 22 MHz offset frequency, is –58 dBc. Therefore the adjacent signal can be 48 dB stronger than the desired signal for a 10 dB signal to interference ratio. This is 3 dB better than the 45 dB dynamic range requirement of a HIPERLAN/1 class C receiver. Fig. 6.19 shows the spectrum of the synthesized signal. All the spurs are more than 70 dB below the carrier. This spurious free signal is achieved by the careful design of the semi–differential charge pump and also the very good matching between the up and down current sources. Also the reasonably small loop bandwidth (60 kHz) of the fourth order PLL provides enough filtering to suppress the spurs.

102

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

An experimental 5GHz frequency synthesizer

103

Fig. 6.20 shows the VCO control voltage as the synthesizer switches between channel one and four. As expected from Eq. (3.26) the settling time is less than which meets the HIPERLAN requirement by a large margin.

6.4.

Conclusion

In this work we demonstrated the design of a fully integrated, 5GHz CMOS frequency synthesizer designed for a U–NII band WLAN receiver. We not only qualified CMOS at 5 GHz but also showed that with a correct choice of architecture it is feasible to design analog circuits with a sub 2 V supply. The tracking injection–locked frequency divider used as the first divider in the PLL feedback loop reduces the power consumption considerably, without limiting the PLL performance. Ta-

104

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

ble 6.3 summarizes the performance of the synthesizer. Although the ILFD operates at twice the frequency of the prescaler, it consumes less than 1/7 of the power. This low power consumption is achieved by trading off bandwidth for power and also by optimizing the spiral inductors of the ILFD. Finally Table 6.4 compares the power consumption of this work with a few of the most recently published fully integrated CMOS synthesizers. Despite the higher operational frequency of this work, its power consumption is the lowest. For a fairer comparison we define a figure of merit:

An experimental 5GHz frequency synthesizer

105

where f is the frequency of operation and L is the minimum feature size of the process technology. Notice that the figure of merit for this work is at least 30% larger than that of all previously published work thanks to the low power tracking ILFD.

106

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

An experimental 5GHz frequency synthesizer

107

108

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

Chapter 7 CONCLUSION

In this book we discussed several frequency division techniques and explained the limitations as well as advantages of each method. We demonstrated the design of very high frequency and low power frequency dividers using injection locking. We developed a general theory for injection–locked frequency dividers which resulted in very important design techniques for wide locking range dividers. The idea of a tracking ILFD was introduced to extend the locking range of an ILFD even further. The noise characteristic of the ILFD’s was also studied. It was shown that an ILFD has the same noise dynamics as a first order PLL, with the exception that the bandwidth of the noise transfer function increases with the amplitude of the incident signal. A fully integrated CMOS frequency synthesizer was designed that takes advantage of a tracking ILFD to reduce the overall power consumption. In this design we not only proved the functionality of CMOS circuits at 5 GHz but also demonstrated the operation of analog CMOS circuits with a sub 2 V supply. The semi–differential charge pump with its well matched up and down current sources, along with the filtering of the fourth order loop provided a spurious free output. Despite the reason-

110

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

ably small loop bandwidth of 60 kHz the loop settling time is less than 35

due to the careful choice of 49° phase margin, which minimizes

the settling time. The frequency synthesizer consumes less than 22 mW, of which more than half is consumed by the VCO. The Quadrature VCO in this synthesizer resulted in a relatively large

noise corner and

thus the VCO current was increased to reduce the VCO close–in phase noise. Therefore, the VCO power consumption can be reduced significantly if it is designed as a complementary oscillator [46]. The better single–ended symmetry of the complementary oscillator as well as its higher oscillation amplitude compared to an all–NMOS oscillator with the same bias current, improves the phase noise and reduces the corner significantly [47],[48]. We also studied phase–locked loops in detail and introduced a very simple design recipe for third and fourth order PLLs. The design trade– offs are clearly described. The effects of loop bandwidth and phase margin on the loop settling time as well as the noise characteristic of the loop are examined in detail.

7.1.

Future work

The injection–locked frequency division technique is an important contribution of our research. However, in this book we focused on divide–by–2 ILFD’s. Further studies need to be done on frequency division by larger numbers. New circuit topologies should be investigated to achieve a reasonably wide locking range for larger division ratios. More theoretical analysis of the fundamental limitations on the absolute minimum power consumption of an ILFD is necessary. It w i l l prove useful to quantify further the trade–offs with power consumption such as noise floor, locking range, division ratio, and oscillation frequency. Such

Conclusion

111

analyses would provide designers with valuable information necessary to customize their design for a desired objective. Another related research area is to study the possibility of designing a programmable ILFD, perhaps a dual– or multi–modulus ILFD, that would allow one to incorporate the ILFD directly into a prescaler. This would not only reduce PLL power consumption but would also allow the elimination of the fixed frequency divider before the prescaler. Finally, we can further study the idea of injection locking as it historically proceeded. The primary goal of a PLL is frequency multiplication. A subharmonic ILO, as discussed in section 4.3, provides the same functionality. A subharmonic ILO has its own challenges and limitations, including the difficulty of multiple frequency synthesis as required in most wireless systems. One alternative architecture is to follow the idea of combining a PLL and an ILO, like the one shown in Fig. 6.2, but instead of placing the ILO in the feedback path, cascade the PLL and subharmonic ILO. Dual and multi modulus injection-locked frequency multipliers are also other alternatives that are possible areas for research.

This page intentionally left blank

Appendix A 2D Fourier series expansion of an ILFD nonlinear function

In the derivation of the ILFD mathematical model, we expand the output of the nonlinear block in terms of the intermodulation of the input and output signals. To simplify the proof of (4.18), we redefine and

as:

where

and

both with respect to function

The nonlinear function

and

For every

is periodic

we can define a periodic

as:

Since by its Fourier series as:

and

can be represented

114

where each

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

is a Fourier series coefficient of

and is calculated

as:

Since each is even and periodic in of its Fourier series as

it can be represented in terms

where

Now to complete the proof, insert (A.7) into (A.4) and replace

by

Appendix B Input–output phase difference in an ILFD

In order to derive (4.40), we start by evaluating the excess phase introduced in the loop, excluding the phase added by the frequency selective block in a first–harmonic ILO. For convenience we have repeated the ILFD noise model in Fig. B.1. Phasor representation of the signals in Fig. B.1 is also repeated in Fig. B.2. The phasor representation of as the vector sum of

and

E, (Fig. B.1 and B.2) is calculated As E excites the nonlinearities of

new harmonics are generated, but the same instantaneous frequency as

the component of

with

stays in phase with

So

116

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

the phasor representation of

and E have the same direction as

shown in Fig. 4.12. The phase difference introduced between

and

is equal to:

where is the phase difference between ) and is the phase difference between we can approximate

and

and and as:

(vector sum of

and

(Fig. 4.12). When

117

APPENDIX B: Input–output phase difference in an ILFD

where

To satisfy the phase condition, introduced by the RLC tank

should be canceled out by the phase Thus

where

and

where

is replaced by its equivalent from (4.34). To calculate

we

insert (B.8) and (B.1) into (B.6) and rearrange terms:

Equation (B.9) can be further expanded by replacing and (B.4):

and from (B.2)

118

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

Now if we replace by

from (B.5), and expand

can be written as:

Since

we can approximate

which ends our derivation.

as:

(B.10)

Appendix C Polynomial approximation of an oscillator nonlinearity

In a single–ended bipolar oscillator, such as a Colpitts, the transistor output current is an exponential function of the base–emitter voltage. As shown in [49] for a sinusoidal base–emitter voltage the collector current is:

where

is a modified Bessel function of order

is the DC bias current,

and argument

is the electron charge,

is the Boltzmann’s constant, T is temperature in kelvin, and V is the base–emitter voltage amplitude. Now suppose we want to approximate the current with a fourth order polynomial function:

120

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

From trigonometry we know that

therefore, we can rewrite (C.3) as:

where

Parameters

can be estimated by forcing the first and second har-

monics of in (C.8) to be the same as those in (C.1),

and

Notice that in the foregoing derivation we assumed and ignored the DC value of therefore, the parameter cannot be estimated from this analysis. Table C.1 summarizes the normalized values of

APPENDIX C: Polynomial approximation of an oscillator nonlinearity

121

This page intentionally left blank

Appendix D On–chip spiral inductors

Figure D.1 shows the cross section of a 2–turn spiral inductor, with corresponding parameters defined in Table D.1. The parasitic bottom plate capacitances,

and

(Fig. 5.3), are estimated as the parallel

plate capacitance between the inductor metal and substrate (or the ground shield).

The shunt capacitance comprises two parts, the parasitic parallel plate capacitance between the inductor top layer and the underpass layer which contacts the inner terminal

and the interwinding capacitances

To estimate the interwinding capacitance we assume the voltage is linearly distributed along the inductor trace.

124

where

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

is an empirical compensation factor to take fringing

crudely into account and

is the coupling capacitance per unit length

of two metal strips with a separation of The inductance is approximated with a monomial expression [33]:

where L is in nH and all lengths are in

The exponents in (D.6) are:

The series resistance models the inductor resistive loss as substrate magnetic losses [42].

where

as well

APPENDIX D: On–chip spiral inductors

125

and

= average inductor diameter (Table D.1). In the calculation of inductor resistive loss (D.8) we take into account the metal skin depth. At high frequencies, where the skin depth is less than the metal thickness, the inductor resistive loss increases with the square root of frequency. On the other hand substrate magnetic loss (D.9) is proportional to the square of frequency. Therefore, depending upon the inductor geometry, at a certain frequency the substrate magnetic loss will dominate the inductor losses. The substrate magnetic loss is also proportional to the cube of inductor average diameter

So,

126

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

it is important to reduce the inductors’ physical dimensions at higher frequencies to reduce the substrate magnetic losses.

References

[1] F. R. Gfeller and U. Bapst, “Wireless in-house data communication via diffuse infrared radiation,” Proceedings of the IEEE, pp. 1474– 1486, Nov. 1979. [2] Kaveh Pahlavan, Thomas H. Probert, and Mitchell E. Chase, “Trends in Local Wireless Networks,” IEEE Communication Magazine, pp. 88–95, Mar. 1995. [3] Rishi Mohindra and Benno Ritter, “RF directly converts on 802.11 line,” Electronic Engineering Times, p. 98, Nov. 1999. [4] Kaveh Pahlavan, Ali Zahedi, and Prashant Krishnamurthy, “Wideband Local Access: Wireless LAN and Wireless ATM,” IEEE Communication Magazine, pp. 34–40, Mar. 1997. [5] “Broadband Radio Access Networks (BRAN); High PErformance Radio Local Area Network (HIPERLAN) Type 1; Functional specification,” European Standard (Telecommunications Series), July 1998. [6] Tom A. D. Riley and Miles A. Copeland, “A Simplified Continuous Phase Modulation Technique,” IEEE Journal of Solid-State Circuits, vol. 41, no. 5, pp. 321–328, May 1994.

128

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

[7] Michael H. Perrott, T. L. Tewksbury, and C. G. Sodini, “A 27mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2.5-Mb/s GFSK Modulation,” IEEE Journal of Solid-State Circuits, vol. 32, no. 12, pp. 2048–2059, Dec. 1997. [8] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 1998. [9] B. Razavi, Monolithic Phase–Locked Loops and Clock Recovery Circuits, IEEE Press, 1996.

[10] M-tron Engineering Notes, Dec. 1997. [11] Tom A. D. Riley, Miles A. Copeland, and Tad A. Kwasniewski, “Delta-Sigma Modulation in Fractional-N Frequency Synthesis,” IEEE Journal of Solid-State Circuits, vol. 28, no. 5, pp. 553–559, May 1993. [12] Floyd M. Gardner, “Charge–Pump Phase–Lock Loops,” IEEE Transactions on Communications, vol. 28, pp. 1849–1858, Nov. 1980. [13] Scott Willingham, Michael Perrott, Brian Setterberg, Andrew Grzegorek, and Bill McFarland, “An Integrated 2.5GHz Frequency Synthesizer with Settling and 2Mb/s Closed Loop Modulation,” ISSCC Digest, pp. 200–201, Feb. 2000. [14] Behzad Razavi, RF Microelectronics, Prentice Hall, NJ, 1998. [15] Michael M. Driscoll, “Phase Noise Performance of Analog Frequency Dividers,” IEEE Transactions on Ultrasonics, Ferroelectronics, and Frequency Control, vol. 37, no. 4, pp. 295–301, July 1990.

REFERENCES

129

[16] Robert G. Harrison, “Theory of Regenerative Frequency Dividers Using Double-Balanced Mixers,” IEEE MTT-S Digest, pp. 459– 462, 1989. [17] Vadim Manassewitch, Frequency Synthesizers: Theory and Design, Wiley, New York, 1987. [18] Inder Bahl and Prakash Bhartia, Microwave Solid State Circuit Design, Wiley, New York, 1988. [19] George R. Sloan, “The Modeling, Analysis, and Design of FilterBased Parametric Frequency Dividers,” IEEE Transactions on Microwave Theory and Techniques, vol. 41, no. 2, pp. 224–228, Feb. 1993. [20] A. S. Daryoush, T. Berceli, R. Saedi, P.R. Herczfeld, and A. Rosen, “Theory of Subharmonic Synchronization of Nonlinear Oscillators,” IEEE MTT-S Digest, pp. 735–738, 1989. [21] G. R. Poole, “Subharmonic Injection Locking Phenomenon in Synchronous Oscillators,” Electronics Letters, vol. 26, no. 21, pp. 1748–1750, Oct. 1990. [22] Ivan Schmideg, “Harmonic Synchronization of Nonlinear Oscillators,” Proceedings of the IEEE, pp. 1250–1251, Aug. 1971. [23] X. Zhang, X. Zhou, B. Aliener, and A. S. Daryoush, “A Study of Subharmonic Injection Locking for Local Oscillators,” IEEE Microwave and Guided Wave Letters, vol. 2, no. 3, pp. 97–99, Mar. 1992. [24] Hamid R Rategh, Hirad Samavati, and T. H. Lee, “A CMOS Frequency Synthesizer with an Injection–Locked Frequency Divider for a 5GHz Wireless LAN Receiver,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 780–787, May 2000.

130

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

[25] Balth van der Pol, “Forced Oscillations in a Circuit with Nonlinear Resistance. (Reception with Reactive Triod.),” Philosophical Magazine, vol. 3, pp. 361–376, Jan. 1927.

[26] R. Adler, “A Study of Locking Phenomena in Oscillators,” Proceedings of the I.R.E, vol. 34, pp. 351–357, June 1946. [27] Vasil Uzunoglu and Marvin H. White, “The Synchronous Oscillator: A Synchronization and Tracking Network,” IEEE Journal of Solid-State Circuits, vol. 20, no. 6, pp. 1214–1226, Dec. 1985.

[28] Hamid R Rategh, Hirad Samavati, and T. H. Lee, “A 5GHz, 1mW CMOS Voltage Controlled Differential Injection Locked Frequency Divider,” Custom Integrated Circuits Conference Digest, pp. 517–520, May 1999.

[29] A. S. Porret, T. Melly, and C. C. Enz, “Design of High-Q Varactors for Low-Power Wireless Applications using a Standard CMOS Process,” Custom Integrated Circuits Conference Digest, pp. 641– 644, May 1999.

[30] Theerachet Soorapanth, C. Patrick Yue, Derek K. Shaeffer, Thomas H. Lee, and S. Simon Wong, “Analysis and Optimization of Accumulation–Mode Varactor for RF ICs,” Symposium on VLSI Circuits Digest, pp. 32–33, 1998. [31] C. Patrick Yue and S. Simon Wong, “On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC’s,” Symposium on VLSI Circuits Digest, pp. 85–86, 1997.

[32] C. Patrick Yue, Changsup Ryu, Jack Lau, Thomas H. Lee, and S. Simon Wong, “A Physical Model for Planar Spiral Inductors on Silicon,” International Electron Devices Meeting Digest, pp. 6.5.1–6.5.4, 1996.

REFERENCES

131

[33] M. Hershenson, S. S. Mohan, S. P. Boyd, and T. H. Lee, “Optimization of Inductor Circuits via Geometric Programming,” Design Automation Conference Digest, pp. 994–998, June 1999.

[34] Behzad Razavi, Kwing F. Lee, and Ran H. Yan, “Design of HighSpeed, Low-Power Frequency Dividers and Phase-Locked Loops in Deep Submicron CMOS,” IEEE Journal of Solid-State Circuits, vol. 30, no. 2, pp. 101–109, Feb. 1995.

[35] Turgut S. Aytur and Behzad Razavi, “A 2-GHz, 6 mW BiCMOS Frequency Synthesizer,” IEEE Journal of Solid-State Circuits, vol. 30, no. 12, pp. 1457–1462, Dec. 1995.

[36] A. Shahani, D. Shaeffer, S. Mohan, H. Samavati, H. Rategh, M. Hershenson, M. Xu, C. Yue, D. Eddleman, and T. Lee, “Low–Power Dividerless Frequency Synthesis Using Aperture Phase Detector,” IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 2232– 2239, Dec. 1998. [37] D. Shaeffer, A. Shahani, S. Mohan, H. Samavati, H. Rategh, M. Hershenson, M. Xu, C. Yue, D. Eddleman, and T. Lee, “A 115-mW, CMOS GPS Receiver with Wide Dynamic-Range Active Filters,” IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 2219–2231, Dec. 1998.

[38] M. Steyaert, M. Borremans, J. Janssens, B. D. Muer, N. Itoh, J. Craninckx, J. Crols, E. Morifuji, H. S. Momose, and W. Sansen, “A Single-Chip CMOS Transceiver for DCS-1800 Wireless Communications,” ISSCC Digest, pp. 48–49, 1998.

[39] J. Craninckx and M. Steyaert, “A Fully Integrated CMOS DCS– 1800 Frequency Synthesizer,” ISSCC Digest, pp. 372–373, 1998.

132

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

[40] Hirad Samavati, Hamid R. Rategh, and T. H. Lee, “A 5GHz CMOS Wireless–LAN Receiver Front–End,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 765–772, May 2000. [41] A. Rofougaran, J. Rael, M. Rofougaran, and A. A. Abidi, “A 900 MHz CMOS LC oscillator with quadrature outputs,” ISSCC Digest, pp. 316–317, Feb. 1996. [42] S. S. Mohan, The Design, Modeling and Optimization of On– chip Inductor and Transformer Circuits, Ph.D. thesis, Stanford University, Aug. 1999. [43] Christopher Lam and Behzad Razavi, “A 2.6-GHz/5.2-GHz Frequency Synthesizer in CMOS Technology,” Symposium on VLSI Circuits Digest, pp. 117–120, June 1999. [44] John George Maneatis, Precise Delay Generation Using Coupled Oscillators, Ph.D. thesis, Stanford University, June 1994. [45] James F. Parker and Daniel Ray, “A 1.6GHz CMOS PLL with On–Chip Loop Filter,” IEEE Journal of Solid-State Circuits, vol. 33, no. 3, pp. 337–343, Mar. 1998. [46] Ali Hajimiri and T. H. Lee, “Design Issues in CMOS Differential LC Oscillators,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 717–724, May 1999. [47] H. Wang, “Comments on Design Issues in CMOS Differential LC Oscillators,” IEEE Journal of Solid-State Circuits, vol. 35, no. 2, pp. 286, Feb. 2000. [48] A. Hajimiri and T. H. Lee, “Authors’ Reply to Comments on Design Issues in CMOS Differential LC Oscillators,” IEEE Journal of Solid-State Circuits, vol. 35, no. 2, pp. 287, Feb. 2000.

REFERENCES

133

[49] Kenneth K. Clarke and Donald T. Hess, Communication Circuits: Analysis and Design, Addison–Wesley, 1971.

This page intentionally left blank

Index

acceptance, 9, 10

appendices, 3

Access point, 8 access, 5, 6, 69 point, 7 accumulation, 67 mode MOS capacitors, 89 accuracy, 25–28, 33–35

applications, 10, 39, 41, 83

active, 89, 97 adjacent, 13 channel, 15, 16 channels, 16 tone, 16 adjacent channel, 100 Adler, 51, 55 ADS, xvii advantages, 109 amendments, 7 amplifier, 9, 78, 79

Approximate, 89 approximate, 32, 116, 118, 119 approximations, 32 architecture, 48, 65, 85, 86, 97, 103, 1 1 1 architectures, 1, 2, 5, 9 attenuation, 27, 28, 34–36, 38 average, 16, 75, 77, 89 diameter, 125 dimension, 126 power, 77 axis, 27

band, xiii, 5–7, 11 bandpass, 48 systems, 49 bands, 1, 85

amplitude, 45, 47, 51, 52, 54–57, 61, 62, 69–72, 75–78, 81, 109, 110, 119

bandwidth, xiv, 1, 2, 17–19, 44, 48, 61, 80, 85, 86, 98, 100, 101, 104, 107, 109, 110

amplitudes, 56, 57, 63, 75–77, 81 analog, 41, 48, 62, 100, 107 blocks, 100

battery, 1

circuits, 103 CMOS circuits, 3, 109 dividers, 48, 49 frequency dividers, 48–50, 63 frequency division, 41, 48 analysis, 3, 23, 25, 51, 57, 110, 120 aperture phase detector, 84

lifetime, 2 Bessel, 119 bias, 72, 110 current, 69, 71, 119 currents, 70 BiCMOS, 83 binary coded, 91 bipolar, 83 oscillator, 57, 119

136

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

bits, 91 BJT, 121

topologies, 56, 65, 81, 110 circuit implementation, 95

block, 113, 115 blockers, 17

circuit topologies, 1, 2

blocks, xiii, 83, 100 Bluetooth, 6, 7

circuits, 3, 48, 51, 67, 103, 107, 109

Bode, 31, 32 Boltzmann

classrooms, 6

constant, 119 book, xiii

circuitry, 65 classes, 6, 51 Clk, 44–46, 48, 91 Clock recovery systems, 13

branch, 47, 97

clock, 95

buffer, 78 buffers, 72, 86

CMOS, xiv, 1, 2, 42, 44, 65, 69, 70, 73, 74, 79, 83, 99, 102, 103, 107, 108 circuits, 3, 109

calculation, 125 calculations, 89 candidate, 57, 67 Capacitance, 69 capacitance, 23, 42, 45, 48, 66–69, 79, 123, 124 capacitances, 67 Capacitor, 20 capacitor, 23 Capacitors, 68 capacitors, 89 Carrier, 9 carrier, 9, 79, 101 frequency, 13, 86 cascade, 111 cascode, 65

counters, 95 frequency synthesizer, 3, 103, 109 implementation, 83 logic, 42 logic ripple counter, 91 process, 85, 100 receiver, 2 scaling, xiii, 1 synthesizers, 104 coefficient, 53, 56, 114 coefficients, 57, 121 Colpitts, 119 oscillator, 65, 121 Comment, 108

Cellular

commercial, xiii

phones, 1 channel, 15, 16, 46 bandwidth, 17, 18

communication, 6 compatible, xiv, 5, 7, 10, 85

spacing, 15 channel bandwidth, 85 channels, 7, 16 characteristic, 42, 48, 61, 109, 110 charge pump, 109 charge pump, 23, 37, 38, 97, 101 charge pump current, 19, 20 charge pump offset, 97

WLAN products, 5

compensate, 97 complementary, 95, 96 oscillator, 110 output, 95 complex, 32 exponential, 54 component, 54, 115 composite signal, 16

charge pump PLL, 18–20, 23

computational

chip, 73 circuit, 11, 56, 66, 67, 69, 70, 82

databases, 6 computers, 6

implementation, 30

conductance, 45, 46, 86

137

INDEX conference rooms, 6

cycle, 23, 44, 46, 47

configuration, 13, 45, 82

cycles, 91

configurations, 7 connections, 5, 6

Data, 7, 9

connectivity, 7 consequent, 6 constant, 17, 18, 38, 44, 47, 58, 60, 80, 119 constraint, 92 consumption, xiii, xiv, 65–67, 70, 76, 79, 82 contacts, 123 contemporary, 50 control, 6, 75, 93, 97, 101 voltage, 13, 23, 58, 73, 75, 76 voltage variation, 73 voltages, 75 convenience, 115 conventional, 52 CMOS process, 100 flipflop, xiii frequency dividers, 3 implementation, 94 conversion, 10, 85 corner, 110 cosines, 54 counter, 41, 91, 95 counterintuitive, 56 counters, 91, 95 coupling capacitance, 124 Cox, xvii critical, 65 cross-coupled

data, xiii, 1, 5–7, 9, 10 database, 5 databases, 5, 6 dead zone, 95 decade, 32, 61 degradation, 15, 17, 18, 78 degrees, 26 delay, 91, 95 delays, 91 demodulation, 13 demodulator, 10 density, 17, 18 derivation, 58, 113, 120 detector, 13, 19, 20, 37, 38 detectors, 20 deterministic sinusoidal noise, 58 develop, 10 device, 48 diameter, 89, 125 differential, 47, 61, 63, 65, 68, 90, 95, 97 architecture, 65 buffers, 86 ILFD, 56, 81 negative conductance, 46 tracking ILFD, 66, 73, 90

transistors, 86 crossover frequencies, 25, 27

VCO, 86, 90 diffuse, 5

crossover frequency, 19, 22, 23, 25–31, 33–36, 38, 99

Digital

crystal

digital, 41, 100, 107

oscillator, 41 oscillators, 14, 15 crystals, 14 cube, 125 cumbersome, 6 current, 1, 47, 69, 71, 73, 75, 77, 110, 119 sources, 109 currents, 70

dividers, 48 CMOS, 1 dividers, 41, 42, 48 frequency divider, 41 methods, 63 DILFD, 66, 67, 74–79, 81, 82 locking range, 76 nonlinearity, 77

curve, 71, 75, 77, 80

phase noise measurement, 77 dimension, 126

customize, 111

dimensions, 73, 126

138

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

direct, 63

WLAN, 7

disadvantages, 2 distance, 6

exception, 109 excitation, 52

distant, 5

expansion, 113

distinguished, 56

experimental, 83

distributed, 123

results, 10

divider, xiv, 13, 16, 41–14, 47–51, 62, 65, 72,

experimental ILFDs, 3

75, 78, 79, 84, 85, 91–95, 103, 111 output phase noise, 71 dividerless

experimental results, 3

frequency synthesizer, 83, 84 dividers, xiii, xiv, 2, 3, 37, 38, 41, 42, 44, 48–51, 62, 63, 65, 79, 81, 83, 92, 93, 109 division, 2, 7, 41, 48, 49, 51, 61, 62, 70, 109, 110 mechanism, 3, 51, 63 ratio, 14, 16, 25, 42, 62, 110 ratios, 16, 41, 110

dominance, 78

exponential, 1, 54, 119 exponentially, 45, 47 exponents, 124 expression, 55 extensive, xiii, 41 factor, 66, 67, 82 factory, 5 fail, 41 fanout, 44

dominant, 56

fast, xiii, 5, 79

second order nonlinearity, 67 double conversion architecture, 85 down, 80, 109 downconvert, 9, 13, 15 draft, 7 drawbacks, 86

fast frequency hopped PLL, 27 fast frequency hopped systems, 20, 86 fast loop response, 19 FCC, xiii, 5 feasibility, 42 feasible, 42, 44, 103

DSSS, 7 duration, 9

feedback, xiv, 13, 41, 45, 48, 52, 85, 103 division ratio, 25

dynamic range, 85, 101 dynamics, 3, 79, 109

network, 98 path, 111 FHSS, 7

early, 51

figure of merit, 104, 105

Educational, 5 effects, 110 effort, xiii eight, 6 electron, 119 emissions, 16

filter, 2, 13, 19, 21, 23, 24, 27, 28, 30, 33, 35, 37, 38 noise, 38 filtering, 109 finalized, 7 fingers, 89

empirical, 124 formula, 26 epi, 126

flicker, 18

process, 89

Flipflop, 44 flipflop, xiii, 42, 95 Flipflops, 91, 95

era, 5 error, 19, 20, 33, 85, 98–100

fluctuations, 60

ETSI, 7 European, xiii

force, 25 formula, 26

Telecommunication Standards Institute, 7

flipflops, 93, 95

forwarder, 7

139

INDEX node, 7 four, 29, 79 Fourier series, 113, 114

multiplication, 38, 48, 111 multiplication factor, 20, 27, 100 multipliers, 111 range, 3, 7, 15, 48, 56, 75

series coefficient, 114

synthesis, 2, 13, 111 synthesizer, xiii, xiv, 2, 3, 11, 13, 14, 16, 20, 65, 83–85, 99, 102, 103, 109,

series expansion, 113 fourth, 30–35, 55, 57 order, 119

110

order loop, 33–35, 38, 109

synthesizers, xiii, 2, 13, 15, 39

order nonlinearity, 57

tuning, 58, 79, 82

order PLL, 30–32, 34, 36, 39 order PLLs, 39, 110 fourth order PLL, 98, 101 fraction, 14, 51, 84 fractional, 16 divider, 16 spurs, 16 fractions, 16 free, 56 free space, 126 frequencies, 10, 13–16, 20, 25, 27, 32, 37–39, 41–44, 48, 49, 62, 63, 71, 72, 76– 79, 84, 100, 107 Frequency band, 7 dividers, 41 synthesizers, 13, 83 frequency, xiv, 2, 5, 8–10, 13–23, 25–36, 38, 39,

tuning range, 100 fringing, 124 functional blocks, 49 functionality, 109, 1 1 1 functions, 47, 66 future standards, 10 future markets, 2 gain, 10, 19, 38, 50, 52, 56, 66, 69, 76 gain mismatch, 85 gate, 42, 57, 65, 66, 77 gate resistance, 89 gates, 44, 67 Gaussian, 9 generator, 71, 77 geometry, 125

41, 42, 44–46, 48–54, 56, 58, 60, 61, 63, 67, 69–71, 73, 75–77, 79,

GPS

82–87, 90, 91, 99–101, 104, 105, 107, 109, 110, 115, 125

receiver, 84 ground, 68, 87, 123

band, xiii bands, 1 conversion, 10 curve, 71 divider, xiv, 13, 41–44, 49–51, 62, 65, 78, 79, 84, 85, 91, 92, 103, 111 dividers, xiii, 2, 3, 37, 38, 41, 48–51, 62, 63, 65, 79, 81, 83, 92, 93, 109 division, 2, 7, 41, 48, 51, 61, 62, 70

GMSK, 9

shield, 68, 126 shields, 67 growth, 1 guard, 85 guardband, 9 Guerra, xvii half, 110

division mechanism, 3, 51, 63 division principle, 49 hopped PLL, 27

hard, 50 harmonic, 50, 51, 53 harmonics, 16, 19, 34, 35, 86, 115, 120 health care databases, 5

hopped systems, 20, 86 modulation, 13

heterodyne, 14

health monitoring systems, 5

140

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION receiver, 9

incompatible, 10

hidden, 63

incorporate, 111

higher, 110 Higher incident amplitudes, 76

indoor

HIPERLAN, xiii, xiv, 7, 85, 103

inductance, 55, 67, 69, 82, 89, 124

frequency, 8 node, 7 receiver, 3 spectrum, 7 HomeRF, 6, 7 Horowitz, xvii

inductive

wireless networking, 5

loss, 89 inductor, 66–69, 89, 123, 126 average diameter, 89, 125 diameter, 125 geometry, 125

hostile, 9 Hurt, xvii

length, 126 losses, 125 model, 3

IBM, 5 IEEE, 6, 7 ILFD, xiv, 3, 51–58, 61–63, 65–68, 72, 73, 76, 81, 86, 90, 100, 104, 107–111, 113 configuration, 82 mathematical model, 113 model, 3 noise model, 115 nonlinearity, 55 ILFDs, 2, 3, 55, 56

ILO, 51, 58, 59, 61, 62, 111, 115 ILOs, 50, 51 image, 85 reject filter, 85 rejection, 85–87 signal, 85 imaginary, 54 impedance, 24, 30, 57, 66, 67 implementation, 3, 11, 30, 42, 50, 83, 94, 95 impossible, 50 incident, 66, 71, 72, 76, 78, 80, 109 amplitude, 69, 70, 75–77, 81 amplitudes, 75–77, 81 frequencies, 71, 77 frequency, 69, 71, 77, 79 power, 80

optimization, 89 parasitic, 67 resistive loss, 124, 125 trace, 123 Inductors, 67 inductors, xiv, 50, 65, 67, 68, 73, 81, 82, 86–90, 104 industrial, 5 industrialists, 1 industries, 5 industry, 1, 5 inexpensive quartz crystals, 14 infrared, 5 infrastructure, xiii, 6 initial, 22 injection, 80, 97 locked, 79 locked frequency dividers, 65 locking, 81, 109, 111 injection locking, 50, 51, 63 injection locking phenomenon, 53 injection-locked frequency multipliers, 111 inner, 123 dimension, 126

signal, 65–67, 70–73, 76–78 incident amplitude, 54, 55, 57, 61, 62 incident amplitudes, 56, 57, 63

Input

incident frequency, 51, 53, 54, 58, 60, 61 incident power, 57, 61

input, 19, 37, 65, 71, 72, 77, 113 input-output, 55 instantaneous

incident signal, 51, 53, 57–62

locking range, 79

141

INDEX frequency, 115 output frequency, 60

laptops, 5, 6 latch, 42, 44, 45, 49

Institute, 7 instrument, 76 instruments, 5

latches, 42, 44, 45 layout, 87, 94, 100 level, 9, 11

integer, 13

lifetime, 2 limit, 55, 56

division ratios, 16 integrated, xiv, 3, 50, 65, 83–85, 101, 103, 104

linear, 18, 23, 57, 75

CMOS frequency synthesizer, 109 CMOS receiver, 2 integration, 1 integrator, 19, 20

system, 18 linearized, 23 PLL model, 37 link, 5

integrators, 32, 38 intentionally, 58

list, 3, 10 Local, 5

interference, 10, 16–18, 101 interferer, 17

local, xiii, 1, 5, 10 oscillator, 9, 11

interferers, 9 intermediate

oscillators, 10 local oscillator, 41, 85

frequency, 10, 13, 15 intermodulation, 53, 63, 113

local oscillators, 13 lock, 50

coefficient, 53 interoperability, 6 interoperate, 6 interpretation, 61

locked, 65, 71, 77, 79 locking, 81, 109, 111 range, xiv, 66, 67, 69–72, 75–79, 81, 82, 109, 110

interwinding

locking phenomenon, 53 locking range, 3, 51, 55–58, 61, 63 logic, 42, 91

capacitance, 123 capacitances, 123 intrinsic noise, 99 intuition, 55 inverse, 23 inverter, 95 inverters, 95

ISM, 7 band, 1, 5, 6 isolated, 42 isolation, 65 isomorphism, 66 junction, 58 kelvin, 119 laboratories, 5 LAN, xiii, 6, 7, 9 LANs, 6, 7, 10

Loop, 31 stability, 39 loop, 52, 53, 86, 87, 97, 98, 101, 103, 109, 110 bandwidth, 61, 80, 110 filter, 97, 98, 101 gain, 50, 52, 56 parameters, 98 stability, 86 Loop bandwidth, 107 loop bandwidth, 2, 18, 19 loop filter, 2, 19, 21, 23, 24, 27, 28, 30, 33, 35, 37, 38 loop filter noise, 38 loop stability, 19, 24, 25 loop transmission, 24, 30, 32 LOs, 13 loss, 45, 67, 68, 81, 89, 124, 125 losses, 66, 86, 90 lowpass, 48, 61

142

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION filter, 13

modulation, 9, 13 modulators, 16

magnetic, 68 loss, 89, 125 losses, 124, 126 magnitude, 79 margin, 2 market, 1, 6 markets, 2 master, 6 matched, 109 matching, 101 mathematical analysis, 3

modulus, 42–44, 111 modulus control, 93 modulus divider, 92–95 monitoring, 5 monomial, 69 expression, 124 monotonically, 76

MOS, 67 capacitors, 89 transistors, 57 motivation, 2 multi

model, 113 maximization, 67 maximized, 67, 68 maximized tank impedance, 89 measurement, 23, 71, 77 results, 65, 77, 79, 80 measurements, 78, 80

modulus, 1 1 1 multi modulus divider, 16 Multihop, 8 multihop, 7 Multiple, 6 multiple, 39, 84 frequency synthesis, 111

mechanism, 3, 16, 51, 52, 63 medical, 5

multiplexing, 7 multiplication, 20, 27, 38, 48, 100, 1 1 1

medium, 5, 9 merit, 51, 55, 104, 105 metal, 67–69, 89

multiplicative, 21 multipliers, 1 1 1

metal skin depth, 125, 126 metal strips, 124 metal thickness, 125

narrowband, xiv, 85 national, xiii, 6 National Semiconductor, xvii

methods, 58, 63

negative, 47 conductance, 45, 46, 86 resistance, 50

micrograph, 69, 70, 74, 99, 102 microwave systems, 49 mismatch, 23, 85, 98 mobile connections, 5 Mobility, 6 mode, 67, 73 model, 3, 18, 19, 23, 37, 51, 53, 58, 59, 63, 66, 68, 69, 113, 115 models, 69 modern, 5 wireless system, 2 modes, 71

neighborhood, 7 network, xiii, 5, 98 networking, 5 networks, 6 node, 57, 66, 67, 76 noise, xiv, 2, 9, 16–18, 28, 29, 36–39, 50, 58–63, 70–73, 77, 78, 80–82, 85–89, 99– 101, 104, 107, 109, 110, 115 amplification, 38 analysis, 51 attenuation, 38

modifications, 2

characteristic, 109, 110 corner, 110

Modulation, 7, 9

degradation, 78

143

INDEX dynamics, 3, 79, 109 floor, 110 injection, 80 measurement, 7 1 , 77 measurement results, 77 measurements, 78 model, 115

oscillation, 51, 52, 54, 69 amplitude, 55–57, 72, 110 frequency, 51, 52, 58, 73, 110 oscillator, xiv, 9, 11, 41, 50–52, 55–58, 63, 65, 66, 72, 73, 85, 110, 119, 121 nonlinearities, 3

nonlinearity, 66 oscillators, 10, 13–15, 50, 52, 57

power, 80 rejection, 62, 80

Output

sources, 37 suppression, 61

frequency, 79 output, 10, 66, 78, 82, 109, 113, 119

noisy, 16 nonforwarder, 7 node, 7 nonlinear, 55, 57, 113 block, 52, 53, 66, 113

buffer, 78 node, 66 phase noise, 71, 72, 78 signal, 67, 79 output amplitude, 45, 47, 52, 56

circuits, 51

output impedance, 97

coefficients, 57

output noise, 39 output phase noise, 2 output resistance, 44

system, 57 nonlinearities, 3, 52, 115 nonlinearity, 55–57, 66, 67, 77, 81 normalized, 25, 27, 48, 120 notebook computers, 6 notebooks, 5 objective, 2, 55, 82, 89, 1 1 1 observing, 66 OFDM, 7 offices, 6 offset, xiv, 54, 60, 61, 71, 72, 77–80, 97, 99–101 frequencies, 15, 16 frequency, 17, 79 online, 6 operating, 9 operational frequencies, 76 frequency, 44, 45, 48, 49, 104 frequency range, 3, 75 optimization, 3, 65, 69, 86, 89 optimized, xiv, 65, 70, 81, 82 order, 52–58, 61–63, 67, 79, 81, 109, 110, 115, 119 organization, 65 orthogonal frequency division multiplexing, 7

outputs, 87, 93, 100 Outside, 61 overdrive voltage, 47 overlap, 95 overtone modes, 15 oxide, 126 thickness, 126 pace, 1 packet, 7 pads, 69, 73, 99 parallel, 67, 68 impedance, 66, 67 plate capacitance, 123 Parameters, 120 parameters, 68, 98, 123, 126 Parametric, 50 frequency dividers, 49 parametric frequency divider, 49 frequency dividers, 50 parasitic, 15, 67, 123 capacitance, 66, 68 parallel plate capacitance, 123

144

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

partial rectification, 73 path, xiv, 13, 111 patterned ground shields, 67, 87 percentage, 83, 98 period, 25, 45 periodic, 16, 113, 114 peripherals, 6

spiral inductor, 68, 69 spiral inductors, 67 plate, 67 PLL, xiii, xiv, 2, 13, 18–20, 22–25, 27, 29–34, 36–39, 61, 84, 85, 98, 101, 103, 109, 111 bandwidth, 18, 100 feedback loop, 103

permeability, 126 permittivity, 126

model, 37

personal

order, 23, 29

health care databases, 5 PFD, 13 pharmaceutical, 5

power consumption, 111

Phase noise measurements, 78 phase, 70, 71, 76, 78, 81, 115–117 margin, 110 noise, xiv, 70–73, 77, 78, 81, 110 noise degradation, 78 noise measurement, 71, 77 noise measurement results, 77 phase detector, 19, 20, 37, 38, 84 phase detectors, 20 phase error, 19, 20, 85, 100 phase lag, 23 Phase margin, 26, 27, 33, 35, 107 phase margin, 2, 20, 25–33, 35, 98 phase margins, 34 Phase noise, 107 phase noise, 2, 16–18, 39, 58, 60–62, 85–89, 99– 101 phase variation, 56 Phasor, 115 phasor, 51, 115, 116 phasors, 59 phenomenon, 53 phones, 1 physical, 126 dimensions, 73 model, 51 piconet, 6 piconets, 6 picture, 9, 10 pictures, 15 planar

noise, 18, 38 phase noise, 17 PLLs, xiii, 2, 14, 20, 39, 110

Pol, 51 pole, 19, 20, 23, 27, 29, 32, 34 poles, 19, 32 popular, 41 port, 44 positive, 32 feedback loop, 52 phase margin, 32 potential, 97 Power, 7, 108 power, xiv, 9, 11, 41, 44, 48, 50, 57, 61, 62, 69, 70, 72, 77, 79, 80, 83–87, 89, 92, 95, 97, 100, 103–105, 109 consumption, xiii, xiv, 42, 44, 63, 65–67, 70, 76, 79, 82, 109–111 spectral density, 17, 18 precise, 41 Prescaler, 107 prescaler, 83, 85, 91–94, 100, 104, 1 1 1 power consumption, 95 principle, 41, 49 printers, 6 probable, 10 process, 17, 18 product, 9, 48 products, 5 program counter, 91, 95 programmable frequency divider, 91 ILFD, 111 proof, 65, 113, 114

145

INDEX proportionally, 62

Reference, 84, 108

pulse swallow counters, 91

frequency, 107 reference, 18, 28, 84, 86, 95, 100

pulse swallow frequency divider, 91, 92

frequency, 13, 14, 16, 18–21, 23, 25, 27, quadratic nonlinearity, 56, 67 Quadrature VCO, 110 quadrature, 41, 86, 88 accuracy, 87 LOs, 85 outputs, 100

29, 34–36, 86 noise, 37, 38 signal, 19, 37 voltage, 95 Regenerative dividers, 48 frequency divider, 50

quantified, 2

regenerative, 45 dividers, 49 frequency divider, 49 frequency dividers, 49 region, 61, 75, 77

quantitative, 22 quantization

reliability, 10

phases, 86 VCO, 86, 88, 100 qualified, 103

noise, 16 quartz, 14 race, 95 radio, 7 frequency, 10 frequency synthesizers, xiii LAN, xiii range, 7 ramp, 19 random process, 17, 18

rejection, 62, 80 reliable, 5 replica, 98 research, 110, 111 reset, 91 path, 95 resistance, 44, 50, 67, 89, 124 resistive loss, 68, 124, 125 Resistor, 68 resistor, 38 resistors, 39, 99 resonance, 89

Range, 7 range, xiv, 7, 15, 66, 67, 69–79, 81, 82, 109, 110 ratio, 42, 49, 51, 61, 62, 110

resonant

rational, 14 ratios, 16, 32, 34, 41, 110

resonators, xiv, 85 response, 58 restrictions, 51

real, 6, 54 Receiver sensitivity, 9 receiver, xiv, 2, 3, 9–11, 15

frequency, 53, 58, 75, 82 resonate, 66

ripple counter, 91 Ruschlikon, 5

receiver power, 83 receivers, 13 recipe, 2, 28, 35, 110

scalar, 19 scaling, xiii, 1

recipes, 39 Reciprocal, 16 rectification, 73

schematic, 65, 66

Redfern, xvii

Schematic, 88 scientific, 5 SCL, 42, 45, 46, 79 flipflops, 93

146

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION latch, 44, 45, 49

latches, 42, 44 second, 21, 38, 79 harmonics, 120 order nonlinearity, 56, 67, 81 order PLL, 20, 22, 23 sensitivity, 9 series, 113, 114 resistance, 67, 124 Settling, 107 settling, 2, 110 setup, 77

spectrum, xiii, 5–7, 9, 79, 85, 101 speed, 5, 44 spiral, 69, 123, 125 inductor, 68, 69, 123, 126 inductors, xiv, 67, 68, 72, 86, 87, 89, 104 spread spectrum WLAN systems, 6 spur, 2 attenuation, 36 spurious, 15, 16, 34, 35, 85 emissions, 16 free output, 109 free signal, 101

SGF, xvii

sideband, 15, 23

shield, 68, 126 shields, 67, 87 short channel effects, 46 short channel transistors, 88 shunt capacitance, 123

sidebands, 15, 16, 97

sideband, 15, 23, 79, 85 sidebands, 15, 16, 79, 97 signal, 9, 44, 45, 47, 51, 53, 54, 56–62, 65–67, 70–72, 75–79, 109 amplitude, 51 generator, 71, 77 signal bandwidth, 17 SILFD, 65, 69–72, 77–79, 81, 82 silicon, 50 Simulation, 25, 33 simulation, 25 simultaneous, 54 sines, 54

suppression, 23 tones, xiv, 16, 19, 23, 27, 39 Spurs, 107 spurs, 15–17, 29, 34, 86, 101, 105 square, 125 planar spiral inductor, 68, 69 square law device, 48 stability, 19, 23, 24, 26, 39, 86 stable, 19, 23 Standards, 7 standards, xiii, 1, 2, 6, 7, 9, 10, 85 state, 19, 20, 42–44, 46 variables, 43, 44 states, 44 steady state, 43, 44 steady slate output, 46 steady state phase error, 19, 20

single, 7 loop frequency synthesizers, 39

step, 91

sinusoid, 15, 16, 19 sinusoidal, 119 noise, 58–60

strategy, 89 strips, 67, 68, 124

skew, 95, 96 skin, 68 depth, 125, 126 slave, 6 SMIrC, xvii SOs, 51 source, 16, 38, 66, 67, 76 sources, 67, 97, 101, 109 spacing, 14, 15, 86, 107

strategies, 2

strong, 9, 16, 56 second order nonlinearity, 81

sub, 100, 109 subharmonic, 51 ILO, 51, 111 substrate, 68, 89, 123, 126 inductive loss, 89 magnetic loss, 125 magnetic losses, 124, 126 superharmonic

147

INDEX ILOs, 51

theory, 3, 50, 51, 63, 109

supplemental, 3 Supply

thermal

voltage, 107 supply, 3, 109

thick, 71

voltage, 42, 73 suppression, 23, 61 swallow, 91, 92 counter, 91

noise, 39, 99, 101 thickness, 125, 126 thin, 71 third, 24, 26–28, 32, 34, 39, 110 order loop, 25, 30, 31, 33–35, 39 order PLL, 23–25, 29, 35, 38

counters, 91 switches, 91, 97, 103

third order nonlinearity, 56, 57

switching, 9

three, 23, 26, 33, 66,71,80

Switzerland, 5 symmetric, 95

toggle, 16

layout, 87, 94 load, 90 symmetrical, 100 symmetry, 87, 110 synchronous oscillator, 51 synthesis, 2, 10, 13, 111 synthesize, 41 synthesized frequencies, 14 synthesizer, xiii, xiv, 2, 3, 11, 13, 14, 16, 20, 65, 83–85, 87, 99, 100, 102–104, 107, 109, 110 phase noise, 85 spurious sidebands, 97 synthesizers, xiii, 2, 13, 15, 16, 39, 83, 104 system, xiii, 2, 9, 11, 18, 39, 52, 57, 60, 72 architectures, 1

third order nonlinear system, 57

tolerable, 16 tone, 16, 17 tones, xiv, 16, 19, 23, 27, 39

Top, 69 top, 68, 69 topologies, 1, 2, 8, 56, 65, 81, 110 Topology, 7, 9 topology, 6, 7, 65 trace, 123 tracking, 68, 73, 103 ILFD, 58, 65–67, 73, 90, 108, 109 ILFD configuration, 82 trade, 2 transceiver, 9 architectures, 9 transceivers, 1, 13 transconductance, 47 transfer, 61, 62, 109

systematic charge pump offset, 97 systems, xiii, xiv, 1, 2, 5, 6, 10, 13–16, 20, 25, 39, 48–50, 111

Transistor, 66

tail, 73, 75, 77 tank, 53, 56–58, 66, 67, 75, 76, 117

Transistors, 65, 86, 97 transistors, 45, 46, 57

transient, 22 transistor, 66, 90, 119

circuit, 56 losses, 66 targeted, 65 Tektronix, xvii Telecommunication, 7 temperature, 14, 119 terminals, 7

transitions, 43–46 Transmitter power, 9 transmitter, 9, 10, 16 trend, xiii, 1 trigonometry, 120 trucks, 5 tuned, 82

test setup, 77

tuning, 58, 103

148

MULTI–GHZ FREQUENCY SYNTHESIS & DIVISION

tuning range, 73 turned, 46

architecture, 85, 86 wideband, 41 WLAN systems, 2

U–NII

wired

range, 100

window, 84 band, 7 underpass, 123, 126 unforced, 52 unity, 19, 50, 52, 56, 76 universal, 9 universally, xiii University, xvii unlicensed, xiii, 6 unstable, 20 upconverted noise, 86 utility, 6 Uzunoglu, 51 valuable, 1 1 1 varactor, 49, 58, 89 varactors, 50, 89 variables, 43, 44, 53, 55 variation, 56, 60, 74 VCO, xiv, 13, 18, 19, 28, 35, 37, 38, 58, 83, 84, 86–88, 90, 95, 97, 99–101, 107, 110 control voltage, 13, 23, 101 gain constant, 38 layout, 99 outputs, 87 phase noise, 86, 99–101 power consumption, 110

connections, 6 LANs, 6 Wireless LANs, 6 LANs compatible, 7 systems, 14 wireless, xiii, 1, 5, 10, 84 architectures, 2 classrooms, 6 communication, 6 connectivity, 7 LANs, 10 market, 1 medium, 9 networking, 5 receivers, 13 system, xiii, 2, 9 systems, xiv, 1, 10, 16, 25, 84, 1 1 1 transceiver, 9 transceiver architectures, 9 transceivers, 1, 13 wiring, 6 WLAN, 1, 2, 5, 7, 84 products, 5 receiver, xiv, 2, 11, 83, 85, 103 standards, 2, 6, 7, 10 system, 2 systems, xiii, 1, 2, 5, 6, 85

vector, 115, 116 vertical, 27 voltage, 13, 23, 73, 75, 76, 119, 123

WLANs, 5, 6 Wong, xvii

controlled oscillator, xiv

Wooley, xvii

gain, 66, 76

worldwide, 10

noise, 38 variation, 74 voltages, 19

yield, 54

wave, 45, 48 Weaver

zeros, 39 zone, 95

zero, 20, 31, 32, 53, 56, 85, 87, 91, 93